patent_id
stringlengths 7
8
| description
stringlengths 125
2.47M
| length
int64 125
2.47M
|
|---|---|---|
11942868 | DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, such that those skilled in the art can easily implement the present invention. The present disclosure may be implemented in various forms, and is not limited to the embodiments to be described herein below. Reference should be made to the drawings, in which similar reference numerals are used throughout the different drawings to designate similar components. Therefore, the aforementioned reference numerals may be used in other drawings. The drawings are intended to be drawn to scale with angles and relative proportions representing at least one embodiment, but changes in angles and scale are considered part of the inventive concept. Furthermore, the expression “being the same” may mean “being substantially the same”. In other words, the expression “being the same” may include a range that can be tolerated by those skilled in the art. The other expressions may also be expressions from which “substantially” has been omitted. FIG.1is a diagram for describing a display device1in accordance with an embodiment of the present disclosure. Referring toFIG.1, the display device1may include a processor9, a timing controller11(e.g., a control circuit), a data driver12(e.g., a driver circuit), a scan driver13(e.g., driver circuit), a pixel component14, an emission driver15, and a power provider16(e.g., a power supplying circuit). The configuration of the foregoing functional components pertaining to, for example, whether to integrate the foregoing functional components on one IC or a plurality of ICs, may be changed in various ways depending on the specifications of the display device1. The timing controller11may receive grayscale signals and timing signals for each frame period from the processor9. The processor9may correspond to at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application processor (AP), and the like. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like. Each cycle of the vertical synchronization signal may correspond to a corresponding frame period. Each cycle of the horizontal synchronization signal may correspond to a corresponding horizontal period. The grayscale signals may be supplied on a horizontal-line basis in response to a pulse of an enable level of a data enable signal during each horizontal period. The horizontal line may refer to pixels (e.g., a pixel line) connected to the same scan line and the same emission line. The timing controller11may render the gray scale signals in consideration of the specifications of the display device1. For example, the processor9may provide a red grayscale signal, a green grayscale signal, and a blue grayscale signal for each unit dot. For example, in the case in which a pixel component14has an RGB stripe structure, pixels may correspond one to one to respective grayscale signals. In this case, rendering of the grayscale signals may not be necessary. However, for example, in the case where the pixel circuit14has a PENTILE™ structure, because adjacent unit dots may share a pixel, the pixels may not correspond one to one to the respective grayscale signals. In this case, the rendering of the grayscale signals may be necessary. Grayscale signals that have been rendered or have not been rendered may be provided to the data driver12. Furthermore, the timing controller11may provide a data control signal to the data driver12. In addition, the timing controller11may provide a scan control signal to the scan driver13, and may provide an emission control signal to the emission driver15. The pixel component14may be a display panel including the pixels. The data driver12may generate, using the grayscale signals and the data control signal that are received from the timing controller11, data voltages (i.e., data signals) to be provided to data lines DL1, DL2, DL3, . . . , DLn. Here, n is an integer greater than 0. The scan driver13may generate, using scan control signals (e.g., a clock signal, a scan start signal, and the like) received from the timing controller11, scan signals to be provided to the scan lines SL0, SL1, SL2, . . . , SLm. The scan driver13may sequentially supply scan signals each having a turn-on level pulse to the scan lines SL0 to SLm. The scan driver13may include scan stages configured in the form of a shift register. The scan driver13may generate scan signals in such a way as to sequentially transmit a scan start signal having a turn-on level pulse to a subsequent scan stage under the control of a clock signal. Here, m is an integer greater than 0. The emission driver15may generate, using emission control signals (e.g., a clock signal, an emission stop signal, and the like) received from the timing controller11, emission signals to be provided to the emission lines EL1, EL2, EL3, . . . , ELo. The emission driver15may sequentially supply emission signals each having a turn-on level pulse to the emission lines EL1 to ELo. The emission driver15may include emission stages, each of which is configured in the form of a shift register. The emission driver15may generate emission signals in such a way as to sequentially transmit an emission stop signal having a turn-off level pulse to a subsequent emission stage under the control of a clock signal. Here, o is an integer greater than 0. The pixel component14includes pixels. Each pixel PXij may be connected to a corresponding data line (e.g., DL1), a corresponding scan line (e.g., SL0), and an emission line (e.g., EL1). The pixels may include pixels configured to emit a first color of light, pixels configured to emit a second color of light, and pixels configured to emit a third color of light. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue. The second color may be one of red, green, and blue, other than the first color. The third color may be the remaining color among the red, green, and blue, other than the first color and the second color. Furthermore, in lieu of red, green, and blue, magenta, cyan, and yellow may be used as the first to third colors. The power provider16may include a first power supply161and a second power supply162. The first power supply161and the second power supply162may be configured as different integrated chips (IC), or may be integrated into one IC. Each of the first power supply161and the second power supply162may be formed of a voltage converter. For example, each of the first power supply161and the second power supply162may be implemented as a buck converter, a boost converter, a buck-boost converter, or the like. The first power supply161may provide a first power voltage to the pixel component14through a first power line ELVDDL. The pixels of the pixel component14may be connected in common to the first power line ELVDDL, and may be supplied with the same first power voltage. The second power supply162may provide a second power voltage to the pixel component14through a second power line ELVSSL. The pixels of the pixel component14may be connected in common to the second power line ELVSSL, and may be supplied with the same second power voltage. During a display period of the pixel component14, the first power voltage may be greater than the second power voltage. Power current flowing out of the first power supply161through the first power line ELVDDL may flow into the second power supply162through the second power line ELVSSL. FIG.2is a diagram for describing a pixel PXij in accordance with an embodiment of the present disclosure. Referring toFIG.2, the pixel PXij includes transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting element LD. Hereinafter, a circuit (e.g., a PMOS circuit) of the pixel PXij configured of P-type transistors will be described by way of example. However, the circuit may be configured of N-type transistors by changing the polarity of the voltage to be applied to the gate terminal of each transistor to form an NMOS circuit. In another embodiment, the circuit may be configured of a combination of a P-type transistor and an N-type transistor. The term “P-type transistor” is a general name for transistors in which the amount of current increases when a voltage difference between a gate electrode and a source electrode increases in a negative direction. The term “N-type transistor” is a general name for transistors in which the amount of current increases when a voltage difference between a gate electrode and a source electrode increases in a positive direction. Each transistor may be configured in various forms such as a thin film transistor (TFT), a field effect transistor (FET), and a bipolar junction transistor (BJT). The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be referred to as a driving transistor. The transistor T2 may include a gate electrode connected to a scan line SLi1, a first electrode connected to a data line DLj, and a second electrode connected to the node N2. The transistor T2 may be referred to as a scan transistor. The third transistor T3 may include a gate electrode connected to a scan line SLi2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The transistor M3 may be referred to as a compensation transistor. The transistor T4 may include a gate electrode connected to a scan line SLi3, a first electrode connected to the first node N1, and a second electrode connected to an initialization line INTL. The transistor T4 may be referred to as a gate initialization transistor. The transistor T5 may include a gate electrode connected to an i-th emission line ELi, a first electrode connected to the first power line ELVDDL, and a second electrode connected to the node N2. The transistor T5 may be referred to as an emission transistor. In an embodiment, the gate electrode of the transistor T5 is connected to an emission line different from the emission line to which a gate electrode of the transistor T6 is connected. The transistor T6 may include the gate electrode connected to the i-th emission line ELi, a first electrode connected to the third node N3, and a second electrode connected to an anode of the light emitting element LD. The transistor T6 may be referred to as an emission transistor. In an embodiment, the gate electrode of the transistor T6 is connected to an emission line different from the emission line that is connected to the gate electrode of the transistor T5. The transistor T7 may include a gate electrode connected to a scan line SLi4, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light emitting element LD. The transistor T7 may be referred to as a light-emitting-element initialization transistor. The storage capacitor Cst may include a first electrode connected to the first power line ELVDDL, and a second electrode connected to the first node N1. The light emitting element LD may include an anode connected to the second electrode of the transistor T6, and a cathode connected to the second power line ELVSSL. The light emitting element LD may be a light emitting diode. The light emitting element LD may be formed of an organic light emitting diode, an inorganic light emitting diode, a quantum dot/well light emitting diode, or the like. The light emitting element LD may emit light having any one of a first color, a second color, and a third color. Although in the present embodiment only one light emitting element LD is provided in each pixel, a plurality of light emitting elements may be provided in each pixel in another embodiment. Here, the plurality of light emitting elements may be connected in series, parallel, or series-parallel to each other. A first power voltage may be applied to the first power line ELVDDL. A second power voltage may be applied to the second power line ELVSSL. An initialization voltage may be applied to the initialization line INTL. For example, the first power voltage may be greater than the second power voltage. For example, the initialization voltage may be the same as or greater than the second power voltage. For example, the initialization voltage may correspond to the lowest data voltage among data voltages that can be provided. In an embodiment, the magnitude of the initialization voltage is less than the magnitudes of the data voltages that can be provided. FIG.3is a diagram for describing a method of driving the pixel ofFIG.2. Hereinafter, for the convenience of explanation, it is assumed that each of the scan lines SLi1, SLi2, and SLi4 is an i-th scan line SLi, and that the scan line SLi3 is an i−1-th scan line SL(i−1). Here, connection relationships between the scan lines SLi1, SLi2, SLi3, and SLi4 may be changed in various ways depending on the embodiments. For example, the scan line SLi4 may be an i−1-th scan line or an i+1-th scan line. First, an emission signal having a turn-off level (a logic high level) may be applied to the i-th emission line Eli. A data voltage DATA(i−1)j for an i−1-th pixel may be applied to the data line DLj. A scan signal having a turn-on level (a logic low level) may be applied to the scan line SLi3. Whether the logic level is high or low may be changed depending on whether the transistor is a P-type or an N-type. Here, since a scan signal having a turn-off level is applied to the scan lines SLi1 and SLi2, the transistor T2 is turned off, so that the data voltage DATA(i−1)j for the i−1-th pixel may be prevented from being drawn into or applied to the pixel PXij. Here, since the fourth transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and the voltage of the first node N1 is initialized. Since an emission signal having a turn-off level is applied to the emission line Eli, the transistors T5 and T6 are turned off, and the light emitting element LD may be prevented from being unnecessarily operated during an initialization voltage application process. Next, a data voltage DATAij for the i-th pixel PXij is applied to the data line DLj, and a scan signal having a turn-on level is applied to the scan lines SLi1 and SLi2. Hence, the transistors T2, T1, and T3 enter a state capable of conducting electricity, and the data line DLj and the first node N1 become electrically connected to each other. Therefore, a compensation voltage obtained by subtracting a threshold voltage of the transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node N1) of the storage capacitor Cst. The storage capacitor Cst may maintain a voltage corresponding to the difference between the first power voltage and the compensation voltage. This period may be referred to as a threshold voltage compensation period or a data write period. Furthermore, in the case in which the scan line SLi4 is an i-th scan line, the transistor T7 is turned on, so that the anode of the light emitting element LD and the initialization line INTL become connected, and the light emitting element LD may be initialized with the amount of charges corresponding to the difference between the initialization voltage and the second power voltage. Thereafter, as an emission signal having a turn-on level is applied to the i-th emission line Eli, the transistors T5 and T6 may conduct electricity. Therefore, a driving current path that connects the first power line ELVDDL, the transistor T5, the transistor T1, the transistor T6, the light emitting element LD, and the second power line ELVSSL may be formed. The amount of driving current that flows through the first electrode and the second electrode of the first transistor T1 may be adjusted in response to the voltage maintained in the storage capacitor Cst. The light emitting element LD may emit light at a luminance corresponding to the amount of driving current. The light emitting element LD may emit light until an emission signal having a turn-off level is applied to the emission line ELi. The sum of magnitudes of driving currents that flow through the pixels of the pixel component14may be the same as the magnitude of power current. When the emission signal is at a turn-on level, pixels that receive the corresponding emission signal may be in a display state. Therefore, a period during which the emission signal is at a turn-on level may be referred to as an emission period EP (or an emission enable period). Furthermore, when the emission signal is at a turn-off level, pixels that receive the corresponding emission signal may be in a non-display state. Therefore, the period during which the emission signal is at a turn-off level may be referred to as a non-emission period NEP (or an emission inhibit period). The non-emission period NEP described with reference toFIG.3may be for preventing the pixel PXij from emitting light at an undesired luminance during the initialization period and the data write period. While data written in the pixel PXij is maintained (e.g., during one frame period), one or more non-emission periods NEP may be added. The reason for this is because of the fact that, as the emission period EP is reduced, low gray scales may be effectively expressed, or motion in an image may be smoothly blur-processed. FIG.4is a diagram for describing the power provider16in accordance with an embodiment of the present disclosure. Referring toFIG.4, the power provider16in accordance with an embodiment of the present disclosure includes a first inductor L1, a second inductor L2, a third inductor L3, a first transistor M1, a second transistor M2, and a second power supply162. Here, the second power supply162may be formed of an integrated chip (IC). Referring toFIG.1, the power provider16may further include a first power supply161. The first power supply161may have a different structure from that of the second power supply162. The first inductor L1 may include a first electrode connected to an input terminal of the second power supply162, and a second electrode connected to the ground. The second inductor L2 may include a first electrode connected to an input terminal of the second power supply162, and a second electrode connected to the ground. The third inductor L3 may include a first electrode connected to an input terminal of the second power supply162, and a second electrode connected to the ground. In an embodiment, the inductors L1, L2, and L3 are disposed outside the second power supply162rather than being integrated into the second power supply162, due to relatively large volumes of the inductors L1, L2, and L3. The first transistor M1 may include a first electrode configured to receive an input voltage VBAT, and a second electrode connected to the first electrode of the second inductor L2. The gate electrode of the first transistor M1 may receive a control signal PWM2, which is outputted from the second power supply162. The second transistor M2 may include a first electrode configured to receive the input voltage VBAT, and a second electrode connected to the first electrode of the third inductor L3. The gate electrode of the second transistor M1 may receive a control signal PWM3, which is outputted from the second power supply162. The second power supply162may include the input terminals that are respectively connected to the first electrode of the first inductor L1, the first electrode of the second inductor L2, and the first electrode of the third inductor L3, and an output terminal connected to the second power line ELVSSL. The second power supply162in accordance with an embodiment of the present disclosure may include a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a current sensor1621, a converter selector1622, a control voltage generator1624, feedback resistors FBR1 and FBR2, a first gate driver16231, a second gate driver16232, and a third gate driver16233. The third transistor M3 may include a first electrode connected to the first electrode of the second inductor L2, and a second electrode connected to the output terminal of the second power162. A gate electrode of the third transistor M3 may receive a control signal PWM2B. The control signal PWM2B may be generated by inverting the control signal PWM2. The fourth transistor M4 may include a first electrode connected to the third inductor L3, and a second electrode connected to the output terminal of the second power162. A gate electrode of the fourth transistor M4 may receive a control signal PWM3B. In an embodiment, the control signal PWM3B is generated by inverting the control signal PWM3. The fifth transistor M5 may include a first electrode configured to receive the input voltage VBAT, and a second electrode connected to the first electrode of the first inductor L1. A gate electrode of the fifth transistor M5 may receive a control signal PWM1. The sixth transistor M6 may include a first electrode connected to the first electrode of the first inductor L1, and a second electrode connected to the output terminal of the second power162. A gate electrode of the sixth transistor M6 may receive a control signal PWM1B. In an embodiment, the control signal PWM1B is generated by inverting the control signal PWM1. The current sensor1621may sense power current through the second electrode of the third transistor M3, the second electrode of the fourth transistor M4, and the second electrode of the sixth transistor M6, and provide sensing information ISNS based on the sensed currents. For example, the current sensor1621may determine that the sum of the amount of current flowing from the output terminal of the second power supply162to the second electrode of the third transistor M3, the amount of current flowing from the output terminal of the second power supply162to the second electrode of the fourth transistor M4, and the amount of current flowing from the output terminal of the second power supply162to the second electrode of the sixth transistor M6 is a value of the power current. The sensing information ISNS may be a voltage having a magnitude corresponding to the magnitude of the power current. For example, as the magnitude of the power current is increased, the voltage value of the sensing information ISNS may be increased. The converter selector1622may generate a first select signal SEL1, a second select signal SEL2, and a third select signal SEL3 based on the sensing information ISNS. The converter selector1622may be implemented by signal, voltage, or clock generator. For example, each of the first select signal SEL1, the second select signal SEL2, and the third select signal SEL3 may be an enable signal or a clock signal (e.g., a signal that toggles periodically between two different logic values). Here, in the case where a first select signal SEL1 is received, the first gate driver16231may generate pulse-width modulated control signals PWM1 and PWM1B. For example, the first gate driver16231may be implemented by a signal, voltage, or clock generator. In the case where a second select signal SEL2 is received, the second gate driver16232may generate pulse-width modulated control signals PWM2 and PWM2B. For example, the second gate driver16232may be implemented by a signal, voltage, or clock generator. In the case where a third select signal SEL3 is received, the third gate driver16233may generate pulse-width modulated control signals PWM3 and PWM3B. For example, the third gate driver16233may be implemented by a signal, voltage, or clock generator. A process of operating the converter selector1622based on the sensing information ISNS will be described with reference toFIGS.7to10. The feedback resistors FBR1 and FBR2 may be connected in series between the output terminal of the second power supply162and a reference voltage BGR or a node providing the reference voltage BGR. The control voltage generator1624may generate a control voltage CTRL based on a feedback voltage FBV received from a node between the feedback resistors FBR1 and FBR2. For example, the node is electrically connected to the feedback resistors FBR1 and FBR2. A process of generating, by the control voltage generator1624, the control voltage CTRL may be described below with reference toFIGS.5and6. The first gate driver16231may control turning on or off of the fifth transistor M5 and the sixth transistor M6, based on the first select signal SEL1, the sensing information ISNS, and the control voltage CTRL. The first inductor L1, the fifth transistor M5, and the sixth transistor M6 may form a first converter CVT1. The first converter CVT1 may be an inverting buck-boost converter. For example, the first gate driver16231may supply control signals PWM1 and PWM1B with a difference in phase by 180° to the fifth transistor M5 and the sixth transistor M6, respectively, thus enabling the first converter CVT1 to generate a second power voltage. The second gate driver16232may control turning on or off of the first transistor M1 and the third transistor M3, based on the second select signal SEL2, the sensing information ISNS, and the control voltage CTRL. The second inductor L2, the first transistor M1, and the third transistor M3 may form a second converter CVT2. The second converter CVT2 may be an inverting buck-boost converter. For example, the second gate driver16232may supply control signals PWM2 and PWM2B with a difference in phase by 180° to the first transistor M1 and the third transistor M3, respectively, thus enabling the second converter CVT2 to generate a second power voltage. The third gate driver16233may control turning on or off of the second transistor M2 and the fourth transistor M4, based on the third select signal SEL3, the sensing information ISNS, and the control voltage CTRL. The third inductor L3, the second transistor M2, and the fourth transistor M4 may form a third converter CVT3. The third converter CVT3 may be an inverting buck-boost converter. For example, the third gate driver16233may supply control signals PWM3 and PWM3B with a difference in phase by 180° to the second transistor M2 and the fourth transistor M4, respectively, thus enabling the third converter CVT3 to generate a second power voltage. In an embodiment of the present disclosure, the surface area of each of the first transistor M1 and the second transistor M2 is greater than that of each of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. In other words, the surface area of each of the transistors M1 and M2 provided outside an IC may be greater than that of each of the transistors M3, M4, M5, and M6 provided inside the IC. In an embodiment, the surface of each of the transistors M3 and M4 is greater than that of each of the transistors M5 and M6. The first converter CVT1 may be used in the case where relatively low power is needed. The second converter CVT2 and the third converter CVT3 may be used in the case where relatively high power is needed. Therefore, the surface of each of the transistors M1, M2, M3, and M4 that form the second converter CVT2 and the third converter CVT3 may be greater than that of each of the transistors M5 and M6 that form the first converter CVT1. In an embodiment, a switching frequency of the first transistor M1 or the second transistor M2 is greater than that of the fifth transistor M5. In other words, the frequency of each of the control signals PWM3 and PWM2 may be greater than that of the control signal PWM1. In an embodiment, the inductance of the first inductor L1 is greater than that of the second inductor L2 or the third inductor L3. Hence, the slope and the peak of current that flows through the first inductor L1 when the first converter CVT1 is operated may be reduced. In other words, ripples of a power voltage and power current that are generated by the first converter CVT1 may be reduced. For example, when the first converter CVT1 is driven, the load of the pixel component14is comparatively reduced, so that a relatively dark screen may be displayed. Because the human eye more sensitively recognizes a difference between relatively dark gray scales, the display quality can be efficiently enhanced according to the present embodiment. In an embodiment, the surface area of the third transistor M3 and the surface area of the fourth transistor M4 is the same as each other. The surface area of the first transistor M1 and the surface area of the second transistor M2 may be the same as each other. The inductance of the second inductor L2 and the inductance of the third inductor L3 may be the same as each other. In other words, the second converter CVT2 and the third converter CVT3 may be configured to have the same specifications. The reason for this is for making uniform ripples of second power voltages that are simultaneously generated by the second converter CVT2 and the third converter CVT3 in a third phase to be described below, and thus preventing flicker from occurring in the pixel component14. In an embodiment of the third phase to be described below, the control signals PWM2 and PWM3 have the same frequency and phase. FIGS.5and6are diagrams for describing the control voltage generator1624and a gate driver (e.g.,16231) in accordance with an embodiment of the present disclosure. Referring toFIG.5, the control voltage generator1624in accordance with an embodiment of the present disclosure may include a comparator EAMP and a filter FLT. The comparator EAMP may generate a control voltage CTRL corresponding to a value obtained by multiplying a difference between a feedback voltage FBV and a reference voltage VREF by a gain gm. The filter FLT may be a low-pass filter. The filter FLT may be omitted, or other kinds of filters may be used. The first gate driver16231in accordance with an embodiment of the present disclosure may include a comparator CMP and a modulator MDL. Each of the second gate driver16232and the third gate driver16233may have the same configuration as the first gate driver16231, other than the fact that the second gate driver16232may receive a second select signal SEL2 and the third gate driver16233may receive a third select signal SEL3; therefore, redundant explanation thereof will be omitted. The comparator CMP may output a reset signal RST corresponding to a difference between the sensing information ISNS and the control voltage CTRL. The modulator MDL may include an S input terminal S configured to receive a first select signal SEL1, and an R input terminal R configured to receive a reset signal RST. The modulator MDL may include a Q output terminal Q configured to output a control signal PWM1, and a QB output terminal QB configured to output a control signal PWM1B. The control signal PWM1B may be an inverted signal of the control signal PWM1. For example, the modulator MDL may be an SR latch. Referring toFIG.6, the comparator CMP may output a reset signal RST having a logic high level when the sensing information ISNS reaches the control voltage CTRL. When the first select signal SEL1 having a logic high level is received, the modulator MDL generates a pulse of the control signal PWM1. For example, the control signal PWM1 may transition to a logic high level when the select signal SEL1 transitions to a logic high level. When the reset signal RST having a logic high level is received, the modulator MDL terminates the pulse of the control signal PWM1. For example, the control signal PWM1 may transition to a logic low level when the rest signal RST transitions to a logic high level. Furthermore, the modulator MDL may output a control signal PWM1B, which is an inverted signal of the control signal PWM1. In accordance with the present embodiment, a peak current of an inductor may be effectively controlled. FIGS.7to10are diagrams for describing a method of driving the power provider in accordance with an embodiment of the present disclosure. FIG.7illustrates a process in which the power provider16is operated in a sequence of a first phase PHS1, a second phase PHS2, and a third phase PHS3 in the case where power current IDC is increased. The power provider16may supply a second power voltage using the first inductor L1 and the second power supply162when the power current IDC flowing through the second power line ELVSSL is less than a first reference value of 0.3 A. In other words, the converter selector1622may generate the first select signal SEL1 (refer toFIGS.4and6) with reference to the sensing information ISNS when the power current IDC is less than the first reference value of 0.3 A. Here, the converter selector1622may generate neither the second select signal SEL2 nor the third select signal SEL3. For example, the converter selector1622may maintain the second select signal SEL2 and the third select signal SEL3 at a logic low level. In other words, in the first phase PHS1, the power provider16may use only the first converter CVT1 to generate the second power voltage. As described above, the first converter CVT1 is designed to be efficiently used in the case where low power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption. When the power current IDC is increased and is greater than the first reference value of 0.3 A and less than a second reference value of 0.7 A, the power provider16may supply the second power voltage using the second inductor L2, the first transistor M1, and the second power supply162. In other words, the converter selector1622may generate the second select signal SEL2 with reference to the sensing information ISNS when the power current IDC is increased and is greater than the first reference value of 0.3 A and less than the second reference value of 0.7 A. Here, the converter selector1622may generate neither the first select signal SEL2 nor the third select signal SEL3. For example, the converter selector1622may maintain the first select signal SEL1 and the third select signal SEL3 at a logic low level. In other words, in the second phase PHS2, the power provider16may use only the second converter CVT2 to generate the second power voltage. As described above, the second converter CVT2 is designed to be efficiently used in the case where relatively high power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption. When the power current IDC is increased and is greater than the second reference value of 0.7 A, the power provider16may supply the second power voltage using the second inductor L2, the third inductor L3, the first transistor M1, the second transistor M2, and the second power supply162. In other words, the converter selector1622may generate the second select signal SEL2 and the third select signal SEL3 with reference to the sensing information ISNS when the power current IDC is increased and is greater than the second reference value of 0.7 A. Here, the second select signal SEL2 and the third select signal SEL3 may have the same frequency and phase. Here, the converter selector1622does not generate the first select signal SEL1. For example, the converter selector1622may maintain the first select signal SEL1 at a logic low level. In other words, in the third phase PHS3, the power provider16may use the second converter CVT2 and the third converter CVT3 to generate the second power voltage. As described above, the second converter CVT2 and the third converter CVT3 are designed to be efficiently used in the case where relatively high power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption when high power is needed. Furthermore, because the second converter CVT2 and the third converter CVT3 may be designed to have the same specifications, ripples of second power voltages that are simultaneously generated by the second converter CVT2 and the third converter CVT3 may be made uniform, whereby flicker can be prevented from occurring in the pixel component14. In an embodiment of the present disclosure, during a transition period t1a to t2a during which the first phase PHS1 is switched to the second phase PHS2, the first converter CVT1 and the second converter CVT2 may be simultaneously driven. For example, the first converter CVT1 may continue to be driven during the transition period t1a to t2a and stop being driven after t2a. Hence, the output voltage may be prevented from rapidly varying attributable to a change of the converter to be used. The time point t1a may be a time point at which the current sensor1621senses that the power current IDC has reached the first reference value of 0.3 A. In an embodiment of the present disclosure, during a transition period t3a to t4a during which the second phase PHS2 is switched to the third phase PHS3, the second converter CVT2 and the third converter CVT3 may be simultaneously driven. For example, the third converter CVT3 begin being driven at a beginning of the transition period t3a without waiting for the transition period t3a to t4a to elapse. Hence, the output voltage may be prevented from rapidly varying attributable to a change of the converter to be used. The time point t3a may be a time point at which the current sensor1621senses that the power current IDC has reached the second reference value of 0.7 A. Referring toFIG.8, it can be seen that even if the power current IDC continuously increases, the maximum of inductor current IL in each phase PHS1, PHS2, PHS3 is limited to 0.3 A, so that the power provider16can be driven efficiently in terms of power consumption. FIG.9illustrates a process in which the power provider16is operated in a sequence of the third phase PHS3, the second phase PHS2, and the first phase PHS1 in the case where power current IDC is reduced. When the power current IDC is greater than a third reference value of 0.6 A, the power provider16may supply the second power voltage using the second inductor L2, the third inductor L3, the first transistor M1, the second transistor M2, and the second power supply162. In other words, the converter selector1622may generate the second select signal SEL2 and the third select signal SEL3 with reference to the sensing information ISNS when the power current IDC is greater than the third reference value of 0.6 A. Here, the second select signal SEL2 and the third select signal SEL3 may have the same frequency and phase. Here, the converter selector1622may not generate the first select signal SELL For example, the converter selector1622may maintain the first select signal SEL1 at a logic low level. In other words, in the third phase PHS3, the power provider16may use the second converter CVT2 and the third converter CVT3 to generate the second power voltage. As described above, the second converter CVT2 and the third converter CVT3 are designed to be efficiently used in the case where relatively high power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption when high power is needed. Furthermore, because the second converter CVT2 and the third converter CVT3 may be designed to have the same specifications, ripples of second power voltages that are simultaneously generated by the second converter CVT2 and the third converter CVT3 may be made uniform, whereby flicker can be prevented from occurring in the pixel component14. When the power current IDC is reduced and is greater than a fourth reference value of 0.2 A and less than the third reference value of 0.6 A, the power provider16may supply the second power voltage using the second inductor L2, the first transistor M1, and the second power supply162. In other words, the converter selector1622may generate the second select signal SEL2 with reference to the sensing information ISNS when the power current IDC is reduced and is greater than the fourth reference value of 0.2 A and less than the third reference value of 0.6 A. Here, the converter selector1622may generate neither the first select signal SEL2 nor the third select signal SEL3. For example, the converter selector1622may maintain the first select signal SEL1 and the third select signal SEL3 at a logic low level. In other words, in the second phase PHS2, the power provider16may use only the second converter CVT2 to generate the second power voltage. As described above, the second converter CVT2 is designed to be efficiently used in the case where relatively high power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption. The power provider16may supply the second power voltage using the first inductor L1 and the second power supply162when the power current IDC is reduced and is less than the fourth reference value of 0.2 A. In other words, when the power current IDC is reduced and less than the fourth reference value of 0.2 A, the converter selector1622may generate the first select signal SEL1. Here, the converter selector1622may generate neither the second select signal SEL2 nor the third select signal SEL3. For example, the converter selector1622may maintain the second select signal SEL2 and the third select signal SEL3 at a logic low level. In other words, in the first phase PHS1, the power provider16may use only the first converter CVT1 to generate the second power voltage. As described above, the first converter CVT1 is designed to be efficiently used in the case where low power is needed, so that the power provider16may provide the second power voltage efficiently in terms of power consumption. In an embodiment, the third reference value (0.6 A) is greater than the first reference value (0.3 A) and less than the second reference value (0.7 A). Here, the fourth reference value (0.2 A) is less than the first reference value (0.3 A). For example, the first reference value (0.3 A) may be 0.3 ampere, the second reference value (0.7 A) may be 0.7 ampere, the third reference value (0.6 A) may be 0.6 ampere, and the fourth reference value (0.2 A) may be 0.2 ampere. Because the first reference value (0.3 A) and the fourth reference value (0.2 A) are set to be different from each other, the first phase PHS1 and the second phase PHS2 may be prevented from being excessively frequently switched from one to another. Furthermore, because the second reference value (0.7 A) and the third reference value (0.6 A) are set to be different from each other, the second phase PHS2 and the third phase PHS3 may be prevented from being excessively frequently switched from one to another. In an embodiment of the present disclosure, during a transition period t1b to t2b during which the third phase PHS3 is switched to the second phase PHS2, the second converter CVT2 and the third converter CVT3 may be simultaneously driven. For example, the third converter CVT3 may continue to be driven during the transition period t1b to t2b and stop being driven after t2b. Hence, the output voltage may be prevented from rapidly varying attributable to a change of the converter to be used. The time point t1b may be a time point at which the current sensor1621senses that the power current IDC has reached the third reference value of 0.6 A. In an embodiment of the present disclosure, during a transition period t3b to t4b during which the second phase PHS2 is switched to the first phase PHS1, the first converter CVT1 and the second converter CVT2 may be simultaneously driven. For example, the second converter CVT2 may continue to be driven during the transition period t3b to t4b and stop being driven after t4b. Hence, the output voltage may be prevented from rapidly varying attributable to a change of the converter to be used. The time point t3b may be a time point at which the current sensor1621senses that the power current IDC has reached the fourth reference value of 0.2 A. Referring toFIG.10, there are illustrated examples of inductor currents IL2 and IL3 during the transition periods t3a to t4a and t1b to t2b between the second phase PHS2 and the third phase PHS3. The second inductor current IL2 may be current that flows through the second inductor L2. The third inductor current IL3 may be current that flows through the third inductor L3. FIGS.11and12are diagrams for describing effects of the power provider in accordance with an embodiment of the present disclosure. Referring toFIG.11, there is illustrated a graph showing the inductor current IL as a function of the power current IDC when the power provider16is operated using the single second converter CVT2, regardless of the second phase PHS2 and the third phase PHS3. The inductor current IL may be the second inductor current IL2. Here, as the power current IDC is increased, the second doctor current IL2 may be increased, regardless of a reference value Iref (e.g., the second reference value of 0.7 A). Referring toFIG.12, there is illustrated a graph showing the inductor current IL as a function of the power current IDC when the power provider16is operated using the second converter CVT2 and the third converter CVT3 reflecting the second phase PHS2 and the third phase PHS3. When the power current IDC is less than the reference value Iref (e.g., in the second phase PHS2), only the second converter CVT2 may generate the power current IDC. When the power current IDC is greater than the reference value Tref (e.g., in the third phase PHS3), the second converter CVT2 and the third converter CVT3 may generate the power current IDC together. Here, the inductor current IL may include the second inductor current IL2 and the third inductor current IL3. In accordance with an embodiment ofFIG.12, only the second converter CVT2 may be used in a relatively small-load period so that switching loss can be reduced. In consideration of the fact that the switching loss is affected by the capacitance of a transistor, the switching loss can be reduced because there is no effect of the capacitance of a transistor included in the third converter CVT3. In a relatively large-load period, the second converter CVT2 and the third converter CVT3 may be driven together so that conduction loss can be reduced. In consideration of the fact that the conduction loss is affected by on-resistance, a plurality of current paths are generated by driving the second converter CVT2 and the third converter CVT3 together, whereby the on-resistance can be reduced. In a power provider and a display device including the power provider in accordance with an embodiment of the present disclosure, a power voltage may be provided efficiently in terms of power consumption in response to the magnitude of power current. Referring back toFIG.4, according to an embodiment, certain elements may be omitted. For example, in a variation ofFIG.4, the third gate driver16233, the third inductor L3, the second transistor M2 and the fourth transistors M4 are omitted. In this variation, the power supply device is configured to supply a power voltage using the first inductor L1 and the power IC when power current flowing through the power line is less than a first reference value; and supply the power voltage using the second inductor L2, the first transistor M1, and the power IC when the power current is greater than the first reference value and less than a second reference value. Although the embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure as disclosed in the accompanying claims. | 48,147 |
11942869 | DETAILED DESCRIPTION A surge voltage generated by switching of the upper-lower arm circuit increases as a current change amount (current change rate) per unit time increases or a wiring inductance increases. Then, in the electric power conversion device, electric charges required for switching the upper-lower arm circuit are supplied from a smoothing capacitor. Therefore, when a length of a wiring connecting the upper-lower arm circuit and the smoothing capacitor is shortened, it may be possible to reduce the wiring inductance related to the surge voltage and reduce the surge voltage. For reducing an electric power loss in the electric power conversion device, the need for high-speed switching of the upper-lower arm circuit is increasing, and the need for reducing the surge voltage is also increasing. However, in a configuration of the conventional electric power conversion device, as described above, there is a limit in shortening the wiring length, and it may be difficult to further reduce the surge voltage. One example of present disclosure provides a power module applied to an electric power conversion device, and the electric power conversion device that are capable of further reducing the surge voltage as compared with the conventional structure. According to one example embodiment, a power module is applied to an electric power conversion device in which multiple upper-lower arm circuits are connected to an electric power line in parallel. The power module includes an upper-lower arm circuit having an upper arm and a lower arm, a capacitor connected to the upper-lower arm circuit in parallel, an upper wiring that connects the upper arm configuring the upper-lower arm circuit and a positive electrode terminal of the capacitor, a lower wiring that electrically connects the lower arm configuring the upper-lower arm circuit and a negative electrode of the capacitor, an electric power wiring connected to an electric power line, an upper wiring that connects an high potential line of the electric power line and the upper wiring, a lower electric power wiring that connects a lower potential line of the electric power line and the lower wiring, and an output wiring that connects at least one of the multiple main terminals of the upper arm and at least one of the multiple terminals of the lower arm. The output wiring includes a facing portion that faces at least one of the upper wiring or the lower wiring. The power module forms the following closed loop circuit that does not include the electric power line. That is, in the closed loop circuit, the positive electrode terminal of the capacitor, the upper wiring, the upper-lower arm circuit, the lower wiring, the negative electrode terminal of the capacitor are connected in series in this order, and the electric power line is not included. Therefore, when the electric charge required for the switching of the upper-lower arm circuit is supplied from the capacitor, the electric charge supply path does include the electric power line. Therefore, it may be possible to shorten the wiring of the path. On the other hand, when, in the conventional structure of the prior art literature, the smoothing capacitor supplies the electric charge, an electric charge supply path from the smoothing capacitor to the upper-lower arm circuit includes the electric power line. Therefore, it may not be possible to sufficiently shorten the wiring of the path. According to another example embodiment, as compared with the conventional structure, a power module can more easily shorten the wiring length that is one factor of the surge voltage occurrence. Accordingly, the wiring inductances related to the surge voltage can be reduced, and the surge voltage generated at the upper-lower arm circuit can be reduced. Moreover, since the closed loop circuit does not include the electric power line, it is difficult for the surge voltage to be superimposed on the self-surge voltage. Therefore, it may be possible to prevent the other upper-lower arm circuits from interfering with the surge voltage via the electric power line. According to another example embodiment, an electric power conversion device includes an electric power line connected to multiple upper-lower arm circuits in parallel, and a power module placed for each phase. The power module placed in a first phase among the multiple phases is a first power module. The power module placed in a second phase among the multiple phases is a second power module. In the first power module, an impedance of an electric path from the positive electrode terminal to the upper arm is an in-phase upper impedance. An impedance of an electric path from the positive electrode terminal corresponding to the first power module to the upper arm corresponding to the second power module is an interphase upper impedance. The interphase upper impedance is higher than the in-phase upper impedance. In the electric power conversion device, the power module is placed for each phase. Therefore, an effect of reducing the surge voltage by the closed loop circuit is provided for each power module of each phase. Further, an effect of preventing surge voltage interference with other upper-lower arm circuits via the electric power line is also provided for each power module of each phase. Hereinafter, multiple embodiments will be described with reference to the drawings. In the embodiments, functionally and/or structurally corresponding parts are denoted by the same reference numerals. First Embodiment An electric power conversion device of the present embodiment can be applied to a vehicle such as, for example, an electric vehicle (EV) or a hybrid vehicle (HV). In the following, an example in which the electric power is applied to the hybrid vehicle will be described. (Drive System) A schematic configuration of a drive system to which an electric power conversion device is applied will be described with reference toFIG.1. As shown inFIG.1, a drive system1of a vehicle includes a direct current power source2, motor generators3and4, an electric power conversion device5that converts electric power between the direct current power source2and the motor generators3and4. The direct current power source2is a secondary battery capable of charging and discharging such as a lithium ion battery or a nickel hydrogen battery. The motor generators3and4are three-phase alternating type rotation electric machines. The motor generator3functions as an electric generator alternator) that is driven by an engine (not shown) and generates electricity and functions as an electric motor (starter) that starts the engine. The motor generator4functions as a traveling drive source of the vehicle, that is, the electric motor. The motor generator4also functions as the electric generator during regeneration. The vehicle includes, as traveling drive sources, the engine and the motor generator4. The electric power conversion device5includes a converter6, inverters7and8, a control circuit portion9, a smoothing capacitor C2, and a filter capacitor C3. The converter6and the inverters7and8correspond to electric power converters. The converter6corresponds to a DC-DC converter that converts a direct voltage into a direct voltage having a different value. The inverters7and8correspond to a DC-AC converter. Each of these electric power converter includes a parallel circuit11including an upper-lower arm circuit10and a capacitor C1 The upper-lower arm circuit10includes switching elements Q1and Q2and diodes D1and D2. In the present embodiment, as the switching elements Q1and Q2, a n-channel type IGBT is employed. An upper arm10U includes the switching element Q1and a freewheeling diode D1connected in reverse parallel to the switching element Q1. A lower arm10L includes the switching element Q2and a freewheeling diode D2connected in reverse parallel to the switching element Q2. The switching elements Q1and Q2are not limited to the IGBT. For example, a MOSFET can be employed. As the diodes D1and D2, parasitic diodes can be employed. The upper arm10U is paced close to a VH line12H. The upper arm10U and the lower arm10L are connected in series between the VH line and a N line13. A P line12is an electric power line on the high potential side, and includes a VL line12L in addition to the VH line12H. The VL line12L is connected to a positive electrode terminal of the direct current power source2. Between the VL line12L and the VH line12H, the converter6is placed. A potential of the VH line12H is equal to or higher than a potential of the VL line12L. The N line13is connected to the negative electrode of the direct current power source2, and is referred to as a ground line. In such a manner, the upper-lower arm circuit10includes the upper arm10U and the lower arm10L that are connected in series between the electric power lines. A semiconductor device20described later configures one arm. A collector electrode of the switching element Q1is connected to the VH line12H. An emitter electrode of the switching element Q2is connected to the N line13. The emitter electrode of the switching element Q1and the collector electrode of the switching element Q2are connected. A positive electrode terminal of the capacitor C1is connected to the collector electrode of the switching element Q1of the upper arm10U. A negative electrode terminal of the capacitor C1is connected to the emitter electrode of the switching element Q2of the lower arm10L. That is, the capacitor C1is connected to the corresponding upper-lower arm circuit10in parallel. The parallel circuit11includes the upper-lower arm circuit10and the capacitor C1that are connected in parallel. The parallel circuit11has common wirings11P and11N. A connection point between the upper arm10U and the positive electrode terminal of the capacitor C1is connected to the VH line12H via the common wiring11P. A connection point between the lower arm10L and the negative electrode of the capacitor C1is connected to the N line13via the common wiring11N. In the present embodiment, the capacitor C1is placed separately from the smoothing capacitor C2and the filter capacitor C3. The capacitor C1may have a function of supplying electric charges required for switching of the switching elements Q1and Q2of the parallelly connected upper-lower arm circuit10. Due to the switching, an energy loss occurs, and a voltage between both ends of the upper arm and the lower arm drops. Therefore, the insufficient electric charges are supplied from the parallelly connected capacitor C1. Therefore, the capacitance of the capacitor C1is set to a value sufficiently smaller than the capacitance of the smoothing capacitor C2or the filter capacitor C3. For example, the capacitance of the smoothing capacitor C2is set to 1000 μF, and the capacitance of the capacitor C1is set to 10 μF to 20 μF. A power module110described later configures one parallel circuit11. The filter capacitor C3is connected between the VL line12L and the N line13. The filter capacitor C3is connected to the direct current power source2in parallel. For example, the filter capacitor C3removes a power source noise from the direct current power source2. Since the filter capacitor C3is placed on the lower voltage side as compared with the smoothing capacitor C2, the filter capacitor C3is also referred to as a lower voltage capacitor. At least one of the N line13or the VL line12L is provided with a system main relay (SMR) (not shown) between the direct current power source2and the filter capacitor C3. The converter6has the parallel circuit11and a reactor. In the present embodiment, the converter6is configured as a multi-phase converter, specifically, a two-phase converter. The converter6has two sets of parallel circuits11, and reactors R1and R2placed for each of the parallel circuits11. The parallel circuits11are connected between the VH line12H and the N line13in parallel. One end of each of the reactors R1and R2is connected to the VL line12L. The other end is connected to a connection point between the upper arm10U and the lower arm10L in the corresponding parallel circuit11via the boost wiring14. That is, the reactors R1and R2are placed between the VL line12L and the connection point of the corresponding upper-lower arm circuit10. The reactors R1and R2are connected between the VL line12L and the N line13in parallel to each other. The converter6converts the direct voltage into the direct voltage having the different value in accordance with a switching control by the control circuit portion9. The converter6has a function of boosting the direct voltage supplied from the direct current power source2. Further, the converter6has a drop function of charging the direct current power source2with use of the electric charges of the smoothing capacitor C2. The smoothing capacitor C2is connected between the VH line12H and the N line13. The smoothing capacitor C2is placed between the converter6and the inverters7and8. The converter6and the inverters7and8are connected in parallel. For example, the smoothing capacitor C2smoothes the direct voltage boosted by the converter6and accumulates the electric charge of the direct voltage. A voltage between the ends of the smoothing capacitor C2is a high direct voltage for driving the motor generators3and4. The voltage between the ends of the smoothing capacitor C2is set to be equal to or higher than a voltage between the ends of the filter capacitor C3. Since the smoothing capacitor C2is placed on the higher voltage side as compared with the filter capacitor C3, the smoothing capacitor C2is also referred to as a higher voltage capacitor. The inverter7is connected to the converter6via the smoothing capacitor C2. The inverter7has three sets of parallel circuits11. That is, the inverter7has the upper-lower arm circuits10for three phases. The connection point of the upper-lower arm circuit10in the U phase is connected to a U phase winding provided at a stator of a motor generator3. Similarly, the connection point of the upper-lower arm circuit10in the V phase is connected to a V phase winding of the motor generator3. The connection point of the upper-lower arm circuit10of the W phase is connected to a W phase winding of the motor generator3. The connection point of the upper-lower arm circuit10in each phase is connected to the winding in accordance with the corresponding phase via an output wiring15placed for each phase. The inverter7converts the direct voltage into a three-phase AC voltage in accordance with the switching control by the control circuit portion9, and outputs the three-phase AC voltage to the motor generator3. Thereby, the motor generator3is driven to generate a predetermined torque. In response to the output of the engine, the inverter7can convert the three-phase AC voltage generated by the motor generator3into the direct voltage in accordance with the switching control by the control circuit portion9, and output the direct voltage to the VH line12H. In such a manner, the inverter7performs bidirectional electric power conversion between the converter6and the motor generator3. Similarly, the inverter8is connected to the converter6via the smoothing capacitor C2. The inverter8has three sets of parallel circuits11. That is, the inverter8has the upper-lower arm circuits10for three phases. The connection point of the upper-lower arm circuit10of the U phase is connected to a U phase winding provided at a stator of a motor generator4. The connection point of the upper-lower arm circuit10of the V phase is connected to a V phase winding of the motor generator4. The connection point of the upper-lower arm circuit10of the W phase is connected to a W phase winding of the motor generator4. The connection point of the upper-lower arm circuit10in each phase is connected to the winding in accordance with the corresponding phase via the output wiring15placed for each phase. The inverter8converts the direct voltage into a three-phase AC voltage in accordance with the switching control by the control circuit portion9, and outputs the three-phase AC voltage to the motor generator4. Thereby, the motor generator3is driven to generate a predetermined torque. At the time of regenerative braking of the vehicle, in response to the rotational force of the vehicle wheels, the inverter8can convert the three-phase AC voltage generated by the motor generator4into the direct voltage in accordance with the switching control by the control circuit portion9, and output the direct voltage to the VH line12H. In such a manner, the inverter8performs bidirectional electric power conversion between the converter6and the motor generator4. The control circuit portion9generates the drive instruction for operating the switching elements of the inverters7and8, and outputs the drive instruction to a drive circuit portion (driver) (not shown). The control circuit portion9generates the drive instruction based on a torque request input from a higher-level ECU (not shown) or signals detected by various sensors. The various sensors include a current sensor that detects a phase current flowing in the wiring of each phase of each of the motor generators3and4, a rotation angle sensor that detects a rotation angle of the rotors of each of the motor generators3and4, a voltage sensor that detects a both end voltage of the smoothing capacitor C2, that is, the voltage of the VH line12H, a voltage sensor that detects a both end voltage of the filter capacitor C3, that is, the voltage of the VL line12L, and a current sensor that is provided at a boost wiring14and detects the current flowing in the reactors R1and R2. The electric power conversion device5has these sensors (not shown). Specifically, the control circuit portion9outputs a PWM signal as the drive instruction. The control circuit portion9includes, for example, a microcomputer. The drive circuit portion generates the drive signal based on the drive instruction from the control circuit portion9, and outputs the drive instruction to the gate electrode of switching elements Q1and Q2of the corresponding upper-lower arm circuit10. Thereby, the switching elements Q1and Q2are driven, that is, turned on and off. In the present embodiment, the drive circuit portion is placed for each upper-lower arm circuit10. Next, before the electric power conversion device5is described, the semiconductor device20and the power module110including the semiconductor device20will be described. The semiconductor device20and the power module110are the components of the electric power conversion device5. (Semiconductor Device) One example of the semiconductor device20applicable to the electric power conversion device5of the present embodiment will be described. The semiconductor device20described below configures one of the upper-lower arm circuit10, that is, one arm. That is, the upper-lower arm circuit10are configured by the two semiconductor devices. Since such a semiconductor device20is packaged in element units configuring one arm, the semiconductor device20is also referred to as one-in-one package. The semiconductor device20has a basic configuration same as the upper arm10U and the lower arm10L, for example, can be the common part. As shown inFIGS.2to7, the semiconductor device20includes a sealing resin body30, a semiconductor chip40, a conductive member50, a terminal60, a main terminal70, and a signal terminal80.FIG.5is a view in which the sealing resin body30is omitted fromFIG.2.FIG.6shows a state where the sealing resin body30was molded and an unnecessary portion of a lead frame100is not removed.FIG.7is a plan view showing a positional relationship between the semiconductor chip40and the main terminal70. InFIG.7, a part of the sealing resin body30, a conductive member50E, and the terminal60are omitted. In the following description, a plate thickness direction of the semiconductor chip40is shown as a Z direction and a direction orthogonal to the Z direction is shown as an X direction. Specifically, the arrangement direction of the main terminals70is shown as the X direction. A direction orthogonal to both of the Z direction and the X direction is shown as a Y direction. Unless otherwise specified, a shape along an XY plane defined by the X direction and the Y direction is a planar shape. The sealing resin body30is made of, for example, an epoxy resin. The sealing resin body30is formed by, for example, a transfer molding method. As shown inFIGS.2to4, the sealing resin body30has a first surface31and a second surface32opposite to the first surface31in the plate thickness direction of the semiconductor chip40in parallel to the Z direction. The first surface31and the second surface32are, for example, flat surfaces. The sealing resin body30has a lateral surface connecting the first surface31and the second surface32. In the present example, the sealing resin body30has a substantially rectangular shape in a plan view. The semiconductor chip40is provided by forming the element on a semiconductor substrate such as Si, SiC, or GaN. The semiconductor device20includes one semiconductor chip40. On the semiconductor chip40, elements (switching element and diode) configuring one arm is formed. That is, an RC (reverse conducting)-IGBT fi formed as the element. For example, when the element is used as the upper arm10U, the element formed on the semiconductor chip40functions as the switching element Q1and the diode D1. When the element is used as the lower arm10L, the element formed on the semiconductor chip40functions as the switching element Q2and the diode D2. The element has a vertical structure so that the main current flows in the Z direction. The element has the gate electrode (not shown). The gate electrode has a trench structure. As shown inFIG.3, the semiconductor chip40has a main electrode on each surface in the Z direction. Specifically, the semiconductor chip40has, as the main electrode, a collector electrode41on one surface, and has, as the main electrode, an emitter electrode42on a back surface opposite to the one surface. The collector electrode41also serves as a cathode electrode of the diode, and the emitter electrode42also serves as an anode electrode of the diode. The collector electrode41is formed on almost the entire of the one surface. The emitter electrode42is formed on a part of the back surface. As shown inFIG.3andFIG.7, the semiconductor chip40has a pad43that is an electrode for signal and is placed on the back surface where the emitter electrode42is formed. The pad43is formed at a position different from the emitter electrode42. The pad43is electrically separated from the emitter electrode42. The pad43is formed at an end on the side opposite to the formation region of the emitter electrode42in the Y direction. In the present example, the semiconductor chip40has five pads43. Specifically, the five pads43are provided for a gate electrode, a Kelvin emitter for detecting a potential of the emitter electrode42, a current sense, an anode potential of a temperature sensor (temperature-sensitive diode) for detecting a temperature of the semiconductor chip40, and a cathode potential. The five pads43are collectively formed on one end side in the Y direction in the semiconductor chip40having a substantially rectangular planar shape, and are formed side by side in the X direction. The conductive member50electrically relays the semiconductor chip40and the main terminal70. That is, the conductive member50functions as a wiring for the main electrode. In the present example, the conductive member also functions to radiate a heat of the semiconductor chip40(element) to the outside of the semiconductor device20. Therefore, the conductive member50is also referred to as a heat sink. The conductive member50is formed of at least a metal material such as Cu for securing an electrical conductivity and a thermal conductivity. The conductive members50are placed in pairs so as to sandwich the semiconductor chip40. Each of the conductive members50is placed so as to encompass the semiconductor chip40in a projection view from the Z direction. The semiconductor device20has, as the pair of the conductive members50, a conductive member50C placed close to the collector electrode41of the semiconductor chip40and the conductive member50E placed close to the emitter electrode42. The conductive member50C electrically relays the collector electrode41and a main terminal70C described later. The conductive member50E electrically relays the emitter electrode42and a main terminal70E described later. As shown inFIG.3,FIG.5, andFIG.7, the conductive member50C has a main portion51C that is a thick portion in the Z direction and an extension portion52C that is a portion thinner than the main portion51C. The main portion51C has a substantially planar shape having a substantially constant thickness. The main portion51C has a mounting surface53C close to the semiconductor chip40in the Z direction and a heat radiation surface54C opposite to the mounting surface53C. The extension portion52C extends from the end of the main portion51C in the Y direction. The extension portion52C extends in the Y direction with the same length in the X direction, that is, the same width as the main portion51C. A surface of the extension portion52C close to the semiconductor chip40is substantially flush with the mounting surface53C of the main portion51C. An opposite surface far from the semiconductor chip40is sealed by the sealing resin body30. The extension portion52C may be provided at, at least, the end close to the arrangement position of the main terminal70. In the present example, the extension portion52C is placed at each of the both ends of the main portion51C. InFIG.7. a boundary between the main portion51C and the extension portion52C is shown by a long dashed double-dotted line. As shown inFIG.3andFIG.5, the conductive member50E has a main portion51E that is a thick portion in the Z direction and an extension portion52E that is a portion thinner than the main portion51E. The main portion51E has the substantially planar shape having the substantially constant thickness. The main portion51E has a mounting surface53E close to the semiconductor chip40in the Z direction and a heat radiation surface54E opposite to the mounting surface53C. The extension portion52E extends from the end of the main portion51E in the Y direction. The extension portion52E extends in the Y direction with the same length in the X direction, that is, the same width as the main portion51E. A surface of the extension portion52E close to the semiconductor chip40is substantially flush with the mounting surface53E of the main portion51E. An opposite surface far from the semiconductor chip40is sealed by the sealing resin body30. The extension portion52E may be provided at, at least, the end close to the arrangement position of the main terminal70. In the present example, the extension portion52E is placed at each of the both ends of the main portion51E. In the present example, common parts are employed as the conductive members50C and50E. The mounting surface53C in the main portion51C of the conductive member50C is connected to the collector electrode41of the semiconductor chip40via a solder90. The connection method is not limited to solder joining. Most of the conductive member50C is covered with the sealing resin body30. The heat radiation surface54C of the conductive member50C is exposed from the sealing resin body30. The heat radiation surface54C is substantially flush with the first surface31. In the surface of the conductive member50C, a portion other than a connection portion with the solder90, the heat radiation surface54C, and a portion that continues from the main terminal70is covered with the sealing resin body30. The terminal60is placed between the semiconductor chip40and the conductive member50E. The terminal60has a substantially rectangular shape, and the planar shape (planar substantially rectangular shape) substantially conform with the emitter electrode42. Since the terminal60is positioned in the middle of the electric conductive path between the emitter electrode42of the semiconductor chip40and the conductive member50E and the thermal conductive path, the terminal60is formed of at least the metal material such as Cu for securing the electric conductivity and the thermal conductivity. The terminal60is placed to face the emitter electrode42and is connected to the emitter electrode42via a solder91. The connection method is not particularly limited to solder joining. The terminal60may be configured as a part of the lead frame100described later. The mounting surface53E in the main portion51E of the conductive member50E is electrically connected to the emitter electrode42of the semiconductor chip40via a solder92. Specifically, the conductive member50E and the terminal60are connected via the solder92. The emitter electrode42and the conductive member50E are electrically connected via the solder91, the terminal60, and the solder92. Most of the conductive member50E are covered with the sealing resin body30. The heat radiation surface54E of the conductive member50E is exposed from the sealing resin body30. The heat radiation surface54E is substantially flush with the second surface32. In the surface of the conductive member50E, a portion other than a connection portion with the solder92, portions that continue from the heat radiation surface54E and the main terminal70is covered with the sealing resin body30. The main terminals70are terminals via which the main current flows among external connection terminals for electrically connecting the semiconductor device20and an external device. The semiconductor device20includes the multiple main terminals70. The main terminal70is connected to the corresponding conductive member50. By processing the same metal member, the main terminal70may be integrally placed with the conductive member50. The main terminal70as the different member may be connected, and thereby may continue from the conductive member50. In the present example, as shown inFIG.6, the main terminal70is configured as a portion of the lead frame100together with the signal terminal80, and is a member different from the conductive member50. As shown inFIG.3, the main terminal70is connected to the corresponding conductive member50in the sealing resin body30. As shown inFIG.3andFIG.4, each of the main terminals70extends from the corresponding conductive member50in the Y direction, and protrudes from one lateral surface33of the sealing resin body30to the outside. The main terminal70extends from the inside of the sealing resin body30to the outside. The main terminal70is a terminal electrically connected to the main electrode of the semiconductor chip40. The semiconductor device20includes, as the main terminals70, the main terminal70C electrically connected to the collector electrode41and the main terminal70E electrically connected to the emitter electrode42. The main terminal70C is also referred to as the collector terminal, and the main terminal70E is also referred to as the emitter terminal. The main terminal70C is connected to the conductive member50C. Specifically, the main terminal70C is connected to a surface of one extension portion52C via a solder93, the one surface being close to the semiconductor chip40. The connection method is not particularly limited to solder joining. The main terminal70C extends in the Y direction from the conductive member50C and protrudes outward from the lateral surface33of the sealing resin body30. The main terminal70E is connected to the conductive member50E. Specifically, the main terminal70C is connected to one surface of one extension portion52E via a solder94, the one surface being close to the semiconductor chip40. The connection method is not particularly limited to solder joining. The main terminal70E extends from the conductive member50E in the Y direction that is the same direction as that of the main terminal70C, and protrudes outward from the same lateral surface33as that of the main terminal70C, as shown inFIGS.3and4. Details of the main terminals70C and70E will be described later. The signal terminals80are connected to the respective pads43of the semiconductor chip40. The semiconductor device20includes the multiple signal terminals80. In the present example, the multiple signal terminals are connected via a bonding wire95. The signal terminal80is connected to the bonding wire95inside the sealing resin body30. Five signal terminals80connected to the pads43extend in the Y direction, and protrude from the lateral surface33and a lateral surface34opposite to the lateral surface33in the sealing resin body30to the outside. The signal terminal80is configured as a part of the lead frame100. The signal terminal80may be integrally placed with the conductive member50C together with the main terminal70C by processing the same metal member. The lead frame100includes an outer peripheral frame portion101and a tie bar102in a state before cutting, as shown inFIG.6. Each of the main terminals70and each of the signal terminals80are fixed to the outer peripheral frame portion101via the tie bar102. After the sealing resin body30is molded, an unnecessary portion of the lead frame100such as the outer peripheral frame portion101or the tie bar102is removed. Thereby, the main terminal70and the signal terminal80are electrically separated. The semiconductor device20is obtained. As the lead frame100, either a material having a constant thickness or a deformed material having a non-constant thickness can be employed. In the semiconductor device20configured as described above, the sealing resin body30integrally seals a part of each of the semiconductor chip40and the conductive member50and a part of each of the terminal60, the main terminal70, and the signal terminal80. That is, elements configuring one arm are sealed. Therefore, the semiconductor device20is also referred to as “1-in-1 package”. The heat radiation surface54C of the conductive member50C is substantially flush with the first surface31of the sealing resin body30. The heat radiation surface54E of the conductive member50E is substantially flush with the second surface32of the sealing resin body30. The semiconductor device20has a double-sided heat radiation structure in which the heat radiation surfaces54C and54E are both exposed from the sealing resin body30. The semiconductor device20can be formed, for example, by cutting the conductive member50together with the sealing resin body30. The heat radiation surfaces54C and54E can also be formed by molding the sealing resin body30so as to be in contact with a cavity wall surface of a mold for molding the sealing resin body30. Next, the main terminal70will be described in detail. The main terminal70includes at least one of the main terminal70C or the main terminal70E. The main terminal70C and the main terminal70E are arranged in the X direction that is the plate width direction of the main terminal70so that plate surfaces of the main terminal70C and the main terminal70E do not face each other and lateral surfaces of the main terminal70C and the lateral surface of the main terminal70E face each other. The semiconductor device20includes multiple lateral surface facing portions formed by the adjacent main terminals70C and70E. The plate surface is a surface in the plate thickness direction of the main terminal70among the surfaces of the main terminal70. The lateral surface is a surface that connects the plate surfaces and is along the extension direction of the main terminal70. The remaining surfaces of the main terminal70are both end surfaces in the extension direction, that is, a protrusion tip surface and a rear end surface. At least a part of the lateral surfaces configuring the lateral surface facing portion may face with each other in the plate thickness direction of the main terminal70. For example, the lateral surfaces may be placed so as to shift in the plate thickness direction. However, it is more effective to face each other all over. It is sufficient that, at least, the facing surfaces face each other. It is preferable that the surfaces are substantially parallel to each other. A completely parallel state is more preferable. An area of the lateral surface of the main terminal70is smaller than that of the plate surface. The main terminals70C and the70E are placed so as to be adjacent to each other. By being adjacent to each other, the main terminal70C and the main terminal70E are alternately arranged in a configuration including the multiple main terminals70C and70E. The main terminals70C and70E are arranged in order. As shown inFIG.7, a main terminal group71includes three or more main terminals70continuously arranged in the X direction. The main terminals70C and70E are arranged next to each other, the main terminal group71includes both of the main terminals70C and70E, and at least one of the number of main terminals70C or the number of main terminals70E is two or more. At least a part of each main terminal70configuring the main terminal group71is placed in a predetermined region A1. The region A1is a region between, in the X direction, an extension line EL1virtually extending from one end surface44of the semiconductor chip40and an extension line EL2virtually extending from an end surface45opposite to the end surface44. In the X direction, a length between the extension lines EL1and EL2conforms with a width of the semiconductor chip40, that is, an element width. In the present example, the main terminals70C and70E extend in the same direction (Y direction) over their entire length. The main terminal70has a straight plane shape, and does not have an extension portion in the X direction. The thickness of the main terminal70C is thinner than that of the main portion51C, and, for example, is almost same as that of the extension portion52C. The thickness of the main terminal70E is thinner than that of the main portion51E, and, for example, is almost same as that of the extension portion52E. The thickness of the main terminal70is, overall, substantially constant, and the main terminals70C and70E have substantially the same thickness. A width W1of the main terminals70is, overall, substantially constant, and the main terminals70C and70E have the same width. An interval P1between the adjacent main terminals70in the X direction is also the same for all the main terminals70. The interval P1is also referred to as an inter-terminal pitch. Each of the main terminals70has two bent portions in the sealing resin body30. Thereby, the main terminal70has a substantially crank shape in a ZY plane. In the main terminal70, a portion close to the tip as compared with the bent portion has a flat plate shape, and a part of the flat plate shaped portion protrudes from the sealing resin body30. In the protrusion portion from the sealing resin body30, that is, the flat plate shaped portion, the main terminals70C and70E are placed at substantially the same positions in the Z direction, as shown inFIGS.3and4. In the flat plate shaped portion, the thickness directions of the main terminals70C and70E substantially conform with the Z direction. Thereby, almost the entire region of the lateral surface of the main terminal70C and almost the entire region of the lateral surface of the main terminal70E face each other in the Z direction. Further, the extension lengths of the flat shaped portions of the main terminals70C and70E are substantially the same. The main terminals70C and the main terminal70E are placed at substantially the same positions in the Y direction. Thereby, almost the entire regions of the flat shaped portions of the lateral surfaces of the main terminals70C and70E face each other. As shown inFIG.2,FIGS.5to7, the semiconductor device20includes an odd number of main terminals70, specifically, nine main terminals70. Four of the nine main terminals70are the main terminals70C, and the remaining five are the main terminals70E. The main terminals70C and70E are alternately placed in the X direction. Thereby, the semiconductor device20has eight lateral surface facing portions. At the both ends in the X direction, the main terminals70E are placed, and the main terminal group71includes seven main terminals70other than the main terminal70E placed at the both ends. The main terminal group71includes an odd number of (seven) main terminals70, specifically, four main terminals70C and three main terminals70E. The entire region of each of the two main terminals70E that does not configure the main terminal group71is placed outside the region A in the X direction. The number of main terminals70that configures the main terminal group71is larger than the number of main terminals70that does not configure the main terminal group71. Among the seven main terminals70included in the main terminal group71, a part of each of the two main terminals70C positioned at both ends is placed in the region A1in the X direction. The entire region of each of the remaining five main terminals70is placed in the region A1in the X direction. In such a manner, some of the main terminals70configuring the main terminal group71are entirely placed in the region A1, and the remaining main terminals70are partially placed in the region A1. In particular, in the present example, each of the multiple (five) main terminals70configuring the main terminal group71is entirely placed in the region A1. The main terminals70C and70E have the same width W1, and the interval P1between the main terminals70C and70E is also the same for all the main terminals70. A center of the width of the main terminal70E placed at the center in the X direction among the odd number of main terminals70is positioned on a center line CL passing through the center of the semiconductor chip40. In such a manner, the main terminals70C and70E are placed symmetrically with respect to the center line CL passing through the center of the semiconductor chip40in the X direction. The multiple main terminals70C are placed symmetrically with respect to the center line CL, and the main terminal70E are placed symmetrically with respect to the center line CL. The odd number of main terminals70included in the main terminal group71are placed symmetrically with respect to the center line CL. The extension direction of the center line CL is orthogonal to the Z direction and the X direction. Next, the effects of the semiconductor device20will be described. In the semiconductor device20, at least one of the number of main terminals70C or the number of main terminals70E are multiple, and the main terminals70C and70E are placed adjacent to each other in the X direction. The lateral surfaces of the adjacent main terminals70C and70E face each other. the direction of the main current at the main terminal70C is opposite to that at the main terminal70E. In the such a manner, the main terminals70C and70E are placed so as to cancel the magnetic fluxes generated when the main current flows. Therefore, it may be possible to reduce the inductance. In particular, in the present example, since the multiple lateral surface facing portions of the main terminals70C and70E are provided, it may be possible to effectively reduce the inductance. Since the multiple main terminals70having the same type are placed in parallel, it may be possible to reduce the inductance by parallelizing the lateral surface facing portions. The main terminal group71includes at least three main terminals70continuously arranged. At least a part of each main terminal70configuring the main terminal group71is placed in the region A1between, in the X direction, the extension lines EL1and EL2that extend from the both end surfaces44and45of the semiconductor chip40. That is, the multiple lateral surface facing portions are placed in the region A1. Thereby, it may be possible to simplify the current path between the main terminal70configuring the main terminal group71and the main electrode of the semiconductor chip40, specifically, shorten the current path. Therefore, it may be possible to reduce the inductance. As described above, according to the semiconductor device20, it may be possible to reduce the inductance of the main circuit wiring as compared with the conventional structure. The multiple main terminals70may be arranged in the X direction so that the lateral surfaces face each other. The main terminal group71may include at least three main terminals70. The at least three main terminals70may include at least one of the multiple main terminals70C or the main terminals70E, and be continuously arranged. Partially, the main terminals70having the same type may be continuously arranged. Thereby, since at least one of the multiple main terminals70C or the multiple main terminal70E are placed in parallel, it may be possible to reduce the inductance. Since the main terminal group71is provided, it may be possible to simplify the current path between the main terminal70configuring the main terminal group71and the main electrode of the semiconductor chip40. Thereby, it may be possible to reduce the inductance. Accordingly, the effects in accordance with the present example can be obtained. However, as shown in the present example, since the main terminals70C and70E are placed adjacent to each other, it may be possible to further reduce the inductance due to the effect of canceling the magnetic flux. In the main terminal group71, the main terminal70entirely placed in the region A1in the X direction is more preferable in respect of the simplification of the current path as compared with the main terminal70partially placed in the region A1. In the present example, some of the main terminals70configuring the main terminal group71are entirely placed in the region A1, and the remaining main terminals70are partially placed in the region A1. Since the main terminal group71includes the main terminal70that is more effective for simplifying the current path, it may be possible to effectively reduce the inductance. In particular, in this example, the multiple main terminal70entirely placed in the region are included. Since the multiple main terminals70that are more effective for simplifying the current path are included, it may be possible to more effectively reduce the inductance. In the present example, the number of main terminals70is odd. When the number is odd, it is easy to have symmetry in the X direction, and it may be possible to prevent the bias of the current path between the main terminal70and the semiconductor chip40. The arrangement order of the main terminals70in the X direction is the same regardless of the viewpoint from the first surface31or the viewpoint from the second surface32. Accordingly, it may be possible to improve freedom of placement of the semiconductor device20. In particular, in the present example, the main terminals70C and70E are placed symmetrically with respect to the center line CL of the semiconductor chip40in the X direction. Thereby, the main current of the semiconductor chip40symmetrically flows with respect to the center line CL. The main current flows almost evenly on the left side and the right side with respect to the center line CL. Accordingly, it may be possible to further reduce the inductance. In addition, it may be possible to suppress local heat generation. FIGS.8to10show another example. InFIGS.8to10, for convenience, the sealing resin body30and the signal terminal80are not shown. InFIGS.8to10, for convenience, the region A1is not shown, and the extension lines EL1and EL2defining the region A1are shown. InFIG.8, the semiconductor device20includes three main terminals70, specifically, one main terminal70C and two main terminals70E. That is, the semiconductor device includes two lateral surface facing portions. The main terminal group71includes all the main terminals70. The main terminal70C placed at the center is entirely placed, in the X direction, in the region A1. The main terminals70E at the both ends are partially placed in the region A1. InFIG.9, the semiconductor device20includes five main terminals70, specifically, two main terminals70C and three main terminals70E. That is, the semiconductor device includes four lateral surface facing portions. The main terminal group71includes all the main terminals70. Each of the main terminals70E at both ends is partially placed in the region A1. Each of the remaining three main terminals70is entirely placed in the region A1. InFIG.10, the semiconductor device20includes seven main terminals70, specifically, three main terminals70C and four main terminals70E. That is, the semiconductor device includes six lateral surface facing portions. The main terminal group71includes all the main terminals70. Each of the main terminals70E at both ends is partially placed in the region A1. Each of the remaining five main terminals70is entirely placed in the region A1. FIG.11a result obtained by performing a magnetic field analysis of a total inductance of the main terminals of the semiconductor device20. In this magnetic field analysis (simulation), a length (width) of the conductive member50in the X direction was set to 17 millimeters, and the interval P1of the main terminal70was set to 1.0 millimeter. In the main terminals70configuring the same semiconductor device20, the widths W1are set to be equal to each other. For example, when three main terminals70are provided, it is shown as three terminals inFIG.11FIG.11shows, as a comparative example, a configuration (two terminals) including only two main terminals. The nine terminals is a result of the same arrangement as the configuration shown inFIG.7. Similarly, the three terminals, the five terminals, and the seven terminals are results of the same arrangement as the configurations shown inFIGS.8to10. As the number of terminals increases, the width per terminal becomes narrower and the inductance (self-inductance) increases. However, the number of the lateral surface facing portions increases. The number of the main terminals70configuring the main terminal group71increases as the number of terminals increases up to the predetermined number of terminals. Therefore, it may be possible to reduce the inductance. As shown inFIGS.8to10, when the number of terminals is three, five, or seven, the main terminal group71includes all the main terminal70. That is, all the main terminals70are placed in the region A1. When the number of terminals is nine, as shown inFIG.7, the main terminal group71includes seven main terminals70. From the results ofFIG.11, when the main terminal group71includes there or more main terminals70, it is clear that the total inductance of the main terminals can be reduced as compared with the comparative example while the increase in the size is prevented. It is considered that, when the number of terminals is three or more, the effect of reducing the inductance exceeds the increase in inductance due to the decrease in the width, and the inductance is reduced. In particular, when the main terminal group71includes five or more main terminals70, the inductance can be reduced by half or less as compared with the comparative example. That is, it is clearly effective in reducing the inductance. The nine terminals include the seven main terminals70configuring the main terminal group71and the two main terminals70placed outside the region A1. Although the two main terminals70are placed outside the region A1in such a manner, more main terminals70than main terminals70that do not configure the main terminal group71, that is, most of the main terminals70are placed in the region A1. The number of lateral surface facing portions is also two more as compared with the seven terminals. Accordingly, the inductance lower than that of the seven terminals is shown. In the example, the example of the configuration in which the main terminals70E are placed at both ends, that is, the configuration in which the number of main terminals70E is larger than the number of main terminals70C has been shown. However, it is not limited to this. In the configuration of the odd number of main terminals70, the number of main terminals70C may be larger than the number of main terminals70E. The example in which the lengths of the protrusion portions of all the main terminal70from the sealing resin body30are same has been shown. However, it is not limited to this. In consideration of connectivity with the bus bar or the like, the protrusion portions of the adjacent main terminals70C and70E may be different from each other. In another example shown inFIG.12, the main terminal70C is longer than the main terminal70E. In another example shown inFIG.13, the number of main terminals70C is smaller than the number of main terminals70E. A cross-sectional area of the main terminal70C is larger than a cross-sectional area of the main terminal70E. Thereby, the total impedance of the main terminal70C and the total impedance of the main terminal70E are substantially matched. Accordingly, it may be possible to suppress the heat generation of a small number of main terminals70C. InFIG.13, the cross-sectional area of the main terminal70C is made larger than the cross-sectional area of the main terminal70E by increasing the width. However, the thickness of the main terminal70C may be thicker than that of the main terminal70E. Both of the width and the thickness may be adjusted. InFIG.13, the length of the small number of the main terminal70C in the extension direction is longer than the length of the main terminal70E. When the length is long, the cross-sectional area is large. Therefore, it may be possible to ensure the rigidity of the main terminal70.FIG.12andFIG.13show the example of the seven terminals. However, it is not limited to this. The example in which, at the protrusion portion from the sealing resin body30, the adjacent main terminals70C and70E face each other entirely in the extension direction. However, it is not limited to this. At a part of the protrusion portion, the lateral surfaces may not face each other. For example, the protrusion tip portion of at least one of the main terminal70C or the main terminal70E is bent, and thereby the lateral surface may not face at the protrusion tip portion. Even when the extension lengths are the same, the connectivity with the bus bar or the like can be improved. However, the effect of reducing the inductance is reduced. The example in which the number of main terminals70is odd and the number of main terminals70configuring the main terminal group71is odd has been shown. However, it is not limited to this. The main terminal group71may include an even number of (four or more) main terminals70. It is sufficient that the semiconductor device20includes at least one semiconductor chip40. For example, in a configuration in which the semiconductor device20includes the multiple semiconductor chips40and these semiconductor chips40are connected in parallel between the main terminals70C and70E, the arrangement of the main terminals70may be applied to each semiconductor chip40. All the main terminals70configuring the main terminal group71are entirely in the region A1. In another example shown inFIG.14, the main terminal group71includes five main terminals70among the seven main terminals70. The five main terminals70configuring the main terminal group71are entirely placed in the region A1. Thereby, it may be possible to simplify the current path with the main electrode of the semiconductor chip40. An even number of (four or more) of main terminals70may be provided. In another example shown inFIG.15, the semiconductor device20includes two main terminals70C and two main terminal70E. The main terminals70C and the main terminals70E are alternately placed. The width W1and the thickness of the four main terminals70are equal to each other. That is, the cross sectional areas orthogonal to the extension direction are equal to each other. The extension length in the Y direction of the four main terminals70is also equal to each other. All the main terminals70configure the main terminal group71. The two main terminals70C and70E placed at both ends are partially placed in the region A1in the X direction. The two main terminals70C and70E at the center are entirely placed in the region A1in the X direction. Even in the configuration, the multiple lateral surface facing portions of the main terminals70C and70E are provided. Therefore, it may be possible to effectively reduce the inductance. Since the main terminal group71is provided, it may be possible to simplify the current path between the main terminal70configuring the main terminal group71and the main electrode of the semiconductor chip40, and reduce the inductance. As described above, it may be possible to reduce the inductance of the main circuit wiring as compared with the conventional structure.FIG.11also shows the result of the four terminals. From the results ofFIG.11, even when the number of terminals is four, it is clear that the total inductance of the main terminals can be reduced as compared with the comparative example while the increase in the size is prevented. InFIG.15, all the main terminals70configure the main terminal group71. Therefore, it may be possible to effectively reduce the inductance. Even when the number of main terminals70is an even number, it is sufficient that three or more continuously arranged main terminals70configure the main terminal group71. Accordingly, in the configuration including the four main terminals70, three main terminals70configure the main terminal group71, and the remaining one main terminal70may be placed outside the region A1. As described above, when the number of main terminal70is the even number, the odd number of (three or more) main terminals70may configure the main terminal group71. When the number of main terminals70is the even number, the number of main terminals70C and the number of main terminals70E are same. Therefore, the main currents flowing at the main terminals70C and70E become equal. Thereby, it may be possible to suppress the variation in heat generation. In the example shown inFIG.15, the extension lengths of the main terminals70C and70E are equal, and the cross-sectional areas are equal. Thereby, the impedances of the main terminals70C and70E are substantially same. Accordingly, it may be possible to effectively prevent the variation in heat generation. The even number is not limited to four. The even number may be four or more. For example, a configuration including six main terminals70or a configuration including eight main terminals70may be employed. Similarly to the odd number, the protrusion portions may be different between the adjacent main terminals70C and70E. Further, the cross-sectional area of a main terminal having the longer protrusion portion among the main terminals70C and70E may be larger than the cross-sectional area of a main terminal having the shorter protrusion portion. Thereby, it may be possible to ensure the rigidity. Further, the impedances of the main terminal70C and the main terminal70E can be set to be equal to each other. At a part of the protrusion portion, the lateral surfaces may not face each other. As a part of the lead frame, a connection portion is further provided with at least one of the main terminal70C or the main terminal70E. At at least one of the main terminals70C or70E, the same main terminals may be connected to each other by the connection portion. In another example shown inFIG.16, the semiconductor device20includes five main terminals70, specifically, two main terminals70C and three main terminals70E. The lead frame100has a connection portion96that connects the main terminals70E to each other. The protrusion length in the main terminal70E from the sealing resin body30is longer than that in the main terminal70C. The connection portion96connects the protrusion tip portion of the main terminal70E. The connection portion96extends in the X direction, and is placed apart from the main terminal70C in the Y direction. The connection portion96is placed at the same position as that of the protrusion portions of the main terminals70C and70E in the Z direction. In such a manner, the main terminal70(main terminal70E) at the same potential is connected by the connection portion96, and thereby it may be possible to reduce the number of connection points with the bus bar. That is, it may be possible to improve the connectivity. In particular, inFIG.16, a large number of main terminals70E are connected. Thereby, in the configuration in which the same lead frame100is provided with the main terminals70C and70E and the connection portion96, it may be possible to reduce the connection point. Instead of the main terminal70E, the main terminal70C may be connected to the connection portion96. Of the main terminals70C and70E, the small number of terminals may be connected. The number of main terminals70and the arrangement are not limited to the example shown inFIG.16. When the connection portion96is provided with one of the main terminal70C and the main terminal70E, the connection portion96can be placed so as to continue from the protrusion portion of the main terminals70C and the70E. It may be combined with a configuration including the even number of main terminals70. Each of the main terminals70C and70E may be connected by the connection portion. In another example shown inFIG.17andFIG.18, the conductive members50C and50E include the main portion51C and does not include the extension portion52C, and the conductive member50E includes the main portion51E and does not include the extension portion52E. On the same lead frame, the conductive member50C, the main terminal70C, and the signal terminal80are placed. At a lead frame different from the lead frame including the main terminal70C, the conductive member50E and the main terminal70E are configured. The main terminal70C extends from the conductive member50C, and the main terminal70E extends from the conductive member50E.FIG.18is a cross-sectional view of the semiconductor device20along the XVIII-XVIII ofFIG.17. InFIG.17andFIG.18, a connection portion96C is placed on the lead frame close to the main terminal70C, and a connection portion96E is placed on the lead frame close to the main terminal70E. The connection portion96C connects the main terminals70C to each other at the protrusion tip portions. The connection portion96E connects the main terminals70E to each other at the protrusion tip portions. The protrusion portion of each of the main terminals70C and70E has a bent portion. Thereby, the connection portions96C and96E are separated from each other in the Z direction. That is, the connection portions96C and96E are placed at different positions in the Z direction. Accordingly, even when the extension lengths are same, the main terminals70C and the main terminal70E are respectively connected by the connection portions96C and96E. It may be possible to further reduce the number of connection points. In another example shown inFIG.19andFIG.20, the semiconductor device20includes multiple semiconductor chips40connected to each other in parallel. Specifically, the semiconductor device20includes, as the semiconductor chip40, a semiconductor chip40aand a semiconductor chip40b.FIG.19is a cross sectional view of the semiconductor device20corresponding to an XIX-XIX line shown inFIG.20. The collector electrodes41of the semiconductor chips40aand40bare connected to the mounting surface53C of the same conductive member50C. The emitter electrodes42of the semiconductor chips40aand40bare connected to the mounting surface53E of the same conductive member50E via the individually placed terminal60. In the present embodiment, two semiconductor chips40aand40bhave substantially the same planar shape, specifically, the substantially rectangular planar shape, and has the same size and the same thickness. The semiconductor chips40aand40bare positioned at substantially the same height in the Z direction, and placed horizontally in the X direction. As shown inFIG.20, a main terminal group72includes two or more main terminals70continuously arranged in the X direction. The semiconductor device20includes, as the main terminal group72, a main terminal group72acorresponding to the semiconductor chip40aand a main terminal group72bcorresponding to the semiconductor chip40b. At least a part of each main terminal70configuring the main terminal group72ais placed in an region A1abetween, in the X direction, extension lines EL1aand EL2athat extend from both end surfaces44aand45aof the semiconductor chip40a. At least a part of each main terminal70configuring the main terminal group72bis placed in an region A1bbetween, in the X direction, extension lines EL1band EL2bthat extend from both end surfaces44band45bof the semiconductor chip40b. The semiconductor device20includes five main terminals70. Specifically, the five main terminals70are two main terminals70C and three main terminals70E. The widths W1of the main terminals70are equal to each other, the thicknesses of the main terminals70are equal to each other, and the intervals P1of the main terminals70are equal to each other. The main terminal70E in the middle is placed outside the regions A1aand A1b. The main terminal group72aincludes two main terminals70C and70E placed closer to the semiconductor chip40athan the main terminal70E in the middle in the X direction. The main terminal group72bincludes two main terminals70C and70E placed closer to the semiconductor chip40bthan the main terminal70E in the middle. Further, the main terminals70C and70E configuring the main terminal group72aare entirely placed in the region A1a. Similarly, the main terminals70C and70E configuring the main terminal group72bare entirely placed in the region A1b. The five main terminals70are symmetrically placed with respect to a center line CLm passing through an elemental center of the two semiconductor chips40. The elemental center is a center position between the centers in the arrangement direction of the semiconductor chips40aand40b, the center line CLm is a virtual line that is orthogonal to the arrangement direction and passes through the elemental center line CL. In such a manner, in the semiconductor device20connected to the multiple semiconductor chips40in parallel, the main terminal70C and the main terminal70E are alternately arranged. The lateral surfaces of the adjacent main terminals70C and70E face each other. In such a manner, the multiple lateral surface facing portions of the main terminals70C and70E, specifically, four multiple lateral surface facing portions are provided. Therefore, it may be possible to effectively reduce the inductance. At least a part of each of the main terminals70C and70E configuring the main terminal group72ais placed in the region A1a. Accordingly, it may be possible to simplify the current path between the main terminals70C and70E configuring the main terminal group72aand the main electrode of the semiconductor chip40a, and thereby reduce the inductance. Similarly, at least a part of each of the main terminals70C and70E configuring the main terminal group72bis placed in the region A1b. Accordingly, it may be possible to simplify the current path between the main terminals70C and70E configuring the main terminal group72band the main electrode of the semiconductor chip40b, and thereby reduce the inductance. As described above, it may be possible to reduce the inductance of the main circuit wiring as compared with the conventional structure. The odd number of main terminals70are symmetrically placed with respect to the center line CLm of the two semiconductor chips40. In other words, the lateral surface facing portions are symmetrically placed with respect to the center line CLm. Therefore, the main currents of the semiconductor chips40aand40bsymmetrically flow with respect to the center line CLm. That is, the inductance for the semiconductor chip40aand the inductance for the semiconductor chip40bare substantially equal. In such a manner, since the inductances are equal to each other, it may be possible to prevent current imbalance. Although the example in which the two semiconductor chips40are connected in parallel, it is not limited to this. It can be also applied to a configuration in which three or more semiconductor chip40are connected in parallel. The number of main terminals70is also not limited. It is sufficient that each main terminal group72includes two or more main terminals70including the main terminals70C and70E. For example, seven main terminals70may be provided, and each of the main terminal groups72aand72bmay include three main terminals70. The connection portion96(86C,86E) shown inFIGS.16to18may be combined. The example in which the switching element and the diode are integrally formed on the same semiconductor chip40has been shown. However, it is not limited to this. The switching element and the diode may be formed on different tips. As the semiconductor device20having a both surface heat radiation structure, the example including the terminal60has been shown. However, it is not limited to this. A configuration that does not include the terminal60may be employed. For example, instead of the terminal60, a protrusion portion protruding toward the emitter electrode42may be provided on the conductive member50E. In addition, the example in which the heat radiation surfaces42C and42E are exposed from the sealing resin body30has been shown. However, the heat radiation surfaces54C and54E may not be exposed from the sealing resin body30. For example, the heat radiation surfaces54C and54E may be covered with an insulation member (not shown). The sealing resin body30may be molded in a state where the insulation material is attached to the heat radiation surfaces54C and54E. (Power Module) One example of the power module110applicable to the electric power conversion device5of the present embodiment will be described. The power module110configures a set of parallel circuits11. As shown inFIGS.21to27, the power module110includes the semiconductor device20, a cooler120, the capacitor C1, a P bus bar130, an N bus bar140, an output bus bar150, a drive substrate160, and an external connection terminal170, and a protective member180. AlthoughFIG.21andFIGS.23to26are plan views, internal elements are shown by solid lines in order that the internal elements of the protective member180are easily understood.FIG.27is a schematic view for illustrating the connection of the semiconductor device20, the capacitor C1, and each of the bus bars130,140, and150. The semiconductor device20has the 1-in-1 package structure. The power module110includes two semiconductor devices20. One semiconductor device20configures the upper arm10U, and the other configures the lower arm10L. That is, the semiconductor devices20are a semiconductor device20U configuring the upper arm10U and a semiconductor device20L configuring the lower arm10L. The basic configurations of the semiconductor devices20U and20L are almost the same as each other. Each of the semiconductor devices20U and20L includes seven main terminals70, specifically, three main terminals70C and four main terminals70E. The main terminals70C and70E are alternately arranged in the X direction. Hereinafter, the semiconductor chip40included in the semiconductor device20U and configuring the upper arm10U is referred to as a semiconductor chip40U. The semiconductor chip40included in semiconductor device20L and configuring the lower arm10L is referred to as a semiconductor chip40L. The semiconductor device20L has the same structure shown inFIG.12. The main terminal70C has the longer protrusion length from the sealing resin body30than that of the main terminal70E. The configuration of the semiconductor device20U is opposite to that of the semiconductor device20L. The main terminal70E has the longer protrusion length from the sealing resin body30than that of the main terminal70C. In such a manner, in the semiconductor device20U, the main terminal70E is longer. In the semiconductor device20L, the main terminal70C is longer. The main terminal70C of the semiconductor device20U and the main terminal70E of the semiconductor device20L have the same length. The main terminal70E of the semiconductor device20U and the main terminal70C of the semiconductor device20L have the same length. The semiconductor devices20U and20L are arranged in the X direction, the predetermined gap is provided between the semiconductor devices20U and20L. That is, the semiconductor devices20U and20L are arranged in the plate thickness direction of the semiconductor chip40, that is, the direction orthogonal to the Z direction. The first surfaces31of the sealing resin bodies30of the semiconductor devices20U and20L are arranged on the same side in the Z direction. The second surfaces32are arranged on the same side. The first surfaces31of the semiconductor devices20U and20L have a substantially flush positional relationship in the Z direction with each other, and the second surfaces have the substantially flush positional relationship in the Z direction with each other. For each of the semiconductor devices20U and20L, the protrusion portion of the signal terminal80from the sealing resin body30has a substantially L shape. The protrusion portion of the signal terminal80has one bent portion of approximately 90 degrees. In the protrusion portion of the signal terminal80, a portion from the root of the sealing resin body30to the bent portion extends in the Y direction. A portion from the bent portion to the protrusion tip extends in the Z direction and extends towards the side opposite to the capacitor C1. The cooler120mainly cools the semiconductor device20. The cooler120is formed of a material having excellent thermal conductivity, for example, an aluminum-based material. The cooler120includes a supply pipe121, a discharge pipe122, and a heat exchange portion123. The cooler120is also referred to as an in-module cooler since the cooler120is placed in the power module110. The heat exchange portion123is configured by a pair of plates124and125. The plates124and125are formed of the metal plate having the substantially rectangular plane shape. At least one of the plate124or125is pressed to have a shape bulging in the Z direction, for example, have a pot bottom shape having a shallow bottom. In the present example, the plate124has the pot bottom shape. Outer peripheral edges of the plates124and125are fixed by swage or the like, and the entire circumference are joined to each other by brazing or the like. Thereby, a flow path126is formed between the plates124and125. The heat exchange portion123has a flat tubular body as a whole. The cooler120has two heat exchange portions123. The heat exchange portions123are arranged in two stages in the Z direction. The two semiconductor devices20U and20L are sandwiched by the two heat exchange portions123in a state where the two semiconductor devices20U and L are arranged in the X direction. The two heat exchange portions123are placed so that the plates124face each other. One of the heat exchange portions123is placed close to the first surface31of the semiconductor device20. The other of the heat exchange portions123is placed close to the second surface32. In a configuration in which the heat radiation surfaces54C and54E are exposed from the sealing resin body30, an electric insulation member such as a grease, a ceramic plate, a resin member, or the like is placed between the semiconductor device20and the plate124of the heat exchange portion123. The supply pipe121is a tubular body including a flow path therein, and extends in the Z direction. The supply pipe121is placed at, in the X direction, one end of the heat exchange portion123having the substantially rectangular plane shape and, in the Y direction, the end close to the main terminal70. The supply pipe121communicates with each heat exchange portion123, and the flow path of the supply pipe121continues from the flow path126of the heat exchange portion123. In the Z direction, one end of the supply pipe121opens, and the other end is connected to the heat exchange portion123of the second stage. The flow path126of the heat exchange portion123of the first stage is connected to the flow path of the supply pipe121in the middle of the extension of the supply pipe121. The first stage is on the side near the open ends of the supply pipe121and the discharge pipe122, and the second stage is the side far from the open ends. A part of the supply pipe121protrudes from the open end of the supply pipe121to the outside of the protective member180. The discharge pipe122is a tubular body including a flow path therein, and extends in the Z direction. The discharge pipe122is placed at, in the X direction, an end opposite to the supply pipe121with respect to the heat exchange portion123having the substantially rectangular plane shape, and the end is close to the signal terminal80in the Y direction. The discharge pipe122communicates with each heat exchange portion123, and the flow path of the discharge pipe122continues from the flow path126of the heat exchange portion123. The discharge pipe122is open similarly to the supply pipe121in the Z direction. The end opposite to the open end is connected to the second stage heat exchange portion123. The flow path126of the heat exchange portion123of the first stage is connected to the flow path of the discharge pipe122in the middle of the extension of the discharge pipe122. A part of the discharge pipe122protrudes from the open end of the discharge pipe122to the outside of the protective member180. As shown by a long dashed double-dotted line arrow inFIG.26, the refrigerant flowing in from the supply pipe121expands the flow path126in the heat exchange portion123, and is discharged from the discharge pipe122. The supply pipe121and the discharge pipe122are placed at diagonal positions in the substantially rectangular plane shape. In such a manner, by providing the supply pipe121and the discharge pipe122at the diagonal positions, it may be possible to effectively cool the semiconductor chips40U and40L placed between the supply pipe121and the discharge pipe122in the X direction and the Y direction. Although not shown, an inner fin is placed inside the flow path126of the heat exchange portion123. The inner fin is a metal plate that is bent and formed in a wavy shape. By placing the inner fin, it may be possible to promote the heat transfer between each of the plates124and125and the refrigerant flowing through the flow path126. As the refrigerant flowing through the flow path126, a phase transition refrigerant such as water or ammonia or a non-phase transition refrigerant such as ethylene glycol can be used. The cooler120mainly cools the semiconductor device20. However, in addition to the cooling function, the cooler120may have a warming function when the environmental temperature is low. Then, the cooler120may be referred to as a temperature adjusting instrument. The refrigerant is referred to as a heat medium. The capacitor C1is placed in the vicinity of a set of the semiconductor devices20U and20L of the power module110. It is sufficient that the capacitor C1has, at least, a function of supplying the electric charge necessary for the switching. Therefore, the capacitance of the capacitor C1is set to, for example, 10 μF to 20 μF. The capacitor C1has the substantially rectangular parallelepiped shape. The capacitor C1has a flat shape. The thickness, that is, a length in the Z direction is set to be sufficiently smaller than a length in the X direction and a length in the Y direction. In such a manner, the capacitor C1is set to be small. As the capacitor C1, for example, a film capacitor can be used. In the present example, the capacitor has a plane rectangular shape in which the length the in the X direction is longer than that in the Y direction. In a projection view in the Z direction, most of the capacitor C1is placed at a position overlapping with the heat exchange portion123of the cooler120. In the same projection view, most of the capacitor C1overlaps with most of the semiconductor devices20U and20L, specifically, a portion other than the projection portion of the main terminal70and the projection portion of the signal terminal80. Accordingly, the capacitor C1and the semiconductor devices20U and20L are arranged in the Z direction. The capacitor C1having the flat rectangular shape is placed at a position where the both ends in the X direction do not overlap with the cooler120, that is, outside the cooler120. The capacitor C1is placed so that the heat exchange portion123is sandwiched by the capacitor C1and the semiconductor device20. The capacitor C1is placed on the opposite side to the semiconductor device20with respect to the heat exchange portion123. In the present example, the capacitor C1is placed on the opposite side to the semiconductor device20with respect to the heat exchange portion123of the first stage. That is, the capacitor C1is placed close to the open ends of the supply pipe121and the discharge pipe122. The capacitor C1is placed at a position closer to the semiconductor device20than the open ends of the supply pipe121and the discharge pipe122in the Z direction. In the capacitor C1, a surface close to the heat exchange portion123in the Z direction has a positive electrode terminal (not shown) for external connection, and a surface opposite to the positive electrode terminal has a negative electrode (not shown). The P bus bar130, the N bus bar140, and the output bus bar150are metal plate materials including a metal having excellent conductivity such as copper, for example. In the present example, the thickness of each bus bar is almost uniform. The P bus bar130, the N bus bar140, and the output bus bar150have substantially the same thickness. As the metal plate material, a plate material of which thicknesses is partially different can be used. The P bus bar130, the N bus bar140, and the output bus bar150are electrically separated from the cooler120. The P bus bar130includes a connection portion131, a common wiring portion132, and a parallel wiring portion133. The connection portion131is a portion connected to the positive electrode terminal of the capacitor C1. In the present example, in the projection view of the Z direction, the entire portion overlapping with the capacitor C1is the connection portion131. Although not shown, the connection portion131may be placed at the portion overlapping with the capacitor C1in the projection view in the X direction or the Y direction, that is, the lateral surface of the capacitor C1. The common wiring portion132extends from one end, in the Y direction, of the connection portion131. The common wiring portion132is a portion that functions as the common wiring11P in the P bus bar130. Thereby, the set of upper-lower arm circuits10in the power module110and the capacitor C1are not individually connected to the VH line12H but also are commonly connected. In the X direction, a length of the common wiring portion132, that is, a width is shorter than that of the connection portion131. In the X direction, the common wiring portion132continues from a central portion of the connection portion131. The common wiring portion132is substantially flush with the connection portion131and extends in the Y direction. A part of the common wiring portion132protrudes to the outside of the protective member180. The parallel wiring portion133functions as, at least, a wiring electrically connecting the positive electrode terminal of the capacitor C1and the upper arm10U of the upper-lower arm circuit10, that is, a wiring connecting the upper-lower arm circuit10and the capacitor C1in parallel. Further, in the present embodiment, the parallel wiring portion133also functions as a wiring electrically connecting the upper arm10U to the common wiring11P, that is, the common wiring portion132. The parallel wiring portion133extends from an end of the connection portion131and the end is opposite to the common wiring portion132. A width of the parallel wiring portion133is narrower than that of the connection portion131. The parallel wiring portion133is extended with a constant width. The parallel wiring portion133is placed on one side with respect to a center line CL1so as not to straddle the center line CL1bisecting the capacitor C1in the X direction (seeFIG.23). The parallel wiring portion133continues from the connection portion131at a position close to the semiconductor device20U (semiconductor chip40U) in the arrangement direction of the semiconductor devices20U and20L. The parallel wiring portion133is substantially L-shaped. The parallel wiring portion133includes a parallel portion134extending from a boundary portion with the connection portion131along the Y direction and a bent portion135that is bent with respect to the parallel portion134and extend along the Z direction. Therefore, the parallel portion134is also referred to as a Y direction extension portion. The bent portion135is also referred to as a Z direction extension portion. The parallel portion134extends in the Y direction towards the opposite side to the common wiring portion132. The parallel portion134is substantially flush with the connection portion131and extends in the Y direction. In the projection view in the Z direction, the parallel portion134overlaps with at least a part of each of the seven main terminals70C and70E of the semiconductor device20U. The parallel portion134extends to substantially the same position as the protrusion tip of the main terminal70C of the semiconductor device20U, and overlaps with the entire protrusion portion of the three main terminals70C in the projection view. The four main terminals70E extend to a position that is more far from the capacitor C1than a position of the parallel portion134. The bent portion135extends towards the opposite side to the capacitor C1in the Z direction. A plate thickness direction of the bent portion135is substantially parallel to the Y direction. In the present example, the entire of the bent portion135is a facing portion135afacing the output bus bar150in the Y direction. The surfaces of the facing portion135aand the output bus bar150in the plate thickness direction, that is, the plate surfaces face each other. At the tip of the facing portion135a, that is, the tip of the extension of the parallel wiring portion133, a convex portion136is formed so that the main terminal70C of the semiconductor device20U is connected. The convex portion136is placed for each main terminal70C. The main terminal70C is joined by laser welding or the like in a state where the main terminal70C is placed on a tip surface of the corresponding convex portion136. When the convex portion136is placed in such a manner, the main terminal70E passes through a concave portion at which the convex portion136is not placed. Therefore, the contact between the P bus bar130and the main terminal70E is prevented. The N bus bar140includes a connection portion141, a common wiring portion142, and a parallel wiring portion143. The connection portion141is a portion connected to the negative electrode terminal of the capacitor C1. In the present example, in the projection view of the Z direction, the entire portion overlapping with the capacitor C1is the connection portion141. Similarly to the connection portion131, the connection portion141may be placed at the portion overlapping with the capacitor C1in the projection view in the X direction or the Y direction, that is, the lateral surface of the capacitor C1. The capacitor C1and the connection portions131and141placed on both surfaces of the capacitor C1are electrically separated from the cooler120. Between the capacitor C1including the connection portions131and141and the cooler120, an electric insulation member is placed. The common wiring portion142extends from one end, in the Y direction, of the connection portion141. The common wiring portion142is a portion that functions as the common wiring11N in the N bus bar140. Thereby, the set of upper-lower arm circuits10in the power module110and the capacitor C1are not individually connected to the N line13but also are commonly connected. The width of the common wiring portion142is narrower than the width of the connection portion141, and substantially same as that of the common wiring portion132. In the X direction, the common wiring portion142continues from a central portion of the connection portion141. The common wiring portion142is substantially flush with the connection portion141and extends in the Y direction. A part of the common wiring portion132protrudes to the outside of the protective member180. The common wiring portions132and142conform with each other in the projection view in the Z direction. The common wiring portions132and142are arranged so as to face each other with an interval substantially equal to the thickness of the capacitor C1in the Z direction. Thereby, it may be possible to reduce the inductance of the main circuit wiring. The parallel wiring portion143functions as, at least, a wiring electrically connecting the negative electrode terminal of the capacitor C1and the lower arm10L of the upper-lower arm circuit10, that is, a wiring connecting the upper-lower arm circuit10and the capacitor C1in parallel. Further, in the present embodiment, the parallel wiring portion143also functions as a wiring electrically connecting the lower arm10L to the common wiring11N, that is, the common wiring portion142. The parallel wiring portion143extends from an end of the connection portion141and the end is opposite to the common wiring portion142. A width of the parallel wiring portion143is narrower than that of the connection portion141. The parallel wiring portion143is extended with a constant width. The parallel wiring portion143placed on the side opposite to the parallel wiring portion133with respect to the center line CL1so as not to straddle the center line CL1of the capacitor C1. The parallel wiring portion143continues from the connection portion141at a position close to the semiconductor device20L (semiconductor chip40L) in the arrangement direction of the semiconductor devices20U and20L. The parallel wiring portion143is substantially L-shaped. The parallel wiring portion143includes a parallel portion144extending from a boundary portion with the connection portion141along the Y direction and a bent portion145that is bent with respect to the parallel portion144and extend along the Z direction. The parallel portion144extends in the Y direction towards the opposite side to the common wiring portion142. The parallel portion144is substantially flush with the connection portion141and extends in the Y direction. The parallel portions134and144are laterally arranged in the X direction with an interval for ensuring the electrical insulation. The lateral surfaces of the parallel portions134and144face each other. Thereby, it may be possible to reduce the inductance of the main circuit wiring. In the projection view in the Z direction, the parallel portion144overlaps with at least a part of each of the seven main terminals70C and70E of the semiconductor device20L. The parallel portion144extends to substantially the same position as the protrusion tip of the main terminal70E of the semiconductor device20L, and overlaps with the entire protrusion portion of the four main terminals70E in the projection view. The three main terminals70C extend to a position that is more far from the capacitor C1than a position of the parallel portion144. Positions of protrusion tips of the main terminal70C of the semiconductor device20U and the main terminal70E of the semiconductor device20L are substantially same position in the Y direction. Thereby, positions of the tips of the extension of the parallel portions134and144are substantially same. The bent portion145extends towards the opposite side to the capacitor C1in the Z direction. A plate thickness direction of the bent portion145is substantially parallel to the Y direction. A position of the extended tip of the bent portion145is same as that of the extended tip of the bent portion135of the P bus bar130. The bent portions135and145are laterally arranged in the X direction with an interval for ensuring the electrical insulation. The lateral surfaces of the bent portions135and145face each other. Thereby, it may be possible to reduce the inductance of the main circuit wiring. In the present example, the position of the N bus bar140is more far from the semiconductor device20in the Z direction than that of the P bus bar130. A part of the bent portion145is a facing portion145afacing the output bus bar150in the Y direction. The plate surfaces of the facing portion145aand the output bus bar150face each other. At the tip of the facing portion145a, that is, the tip of the extension of the parallel wiring portion143, a convex portion146is formed so that the main terminal70E of the semiconductor device20L is connected. The convex portion146is placed for each main terminal70E. The main terminal70E is joined by laser welding or the like in a state where the main terminal70E is placed on a tip surface of the corresponding convex portion146. When the convex portion146is placed in such a manner, the main terminal70C passes through a concave portion at which the convex portion146is not placed. Therefore, the contact between the N bus bar140and the main terminal70C is prevented. The parallel wiring portion133and the main terminal70C of the semiconductor device20U connects the positive electrode of the capacitor C1to the collector electrode of the upper arm10U. The parallel wiring portion143and the main terminal70E of the semiconductor device20L connects the negative electrode of the capacitor C1to the emitter electrode of the lower arm10L. In such a manner, the parallel wiring portion133, the main terminal70C of the semiconductor device20U, the parallel wiring portion143, and the main terminal70E of the semiconductor device20L connect the upper-lower arm circuit10and the capacitor C1in parallel, and the parallel circuit11is configured. The common wiring portions132and142connect the parallel circuit to the VH line12H and the N line13that are an electric power line. The output bus bar150is a bus bar for connecting the connection point between the upper arm10U and the lower arm10L to a three-phase winding of the motor generator. The output bus bar150is also referred to as an O bus bar. The output bus bar150is placed, in the Y direction, not close to the signal terminal80but close to the main terminal70. The output bus bar150extends in the X direction without having the bent portion, when the plate thickness direction is the Y direction. The output bus bar150configures at least a part of the output wiring15. In the periphery of the output bus bar150, a current sensor (not shown) can be placed. The output bus bar150includes a wide width portion151having a wide length in the Z direction, that is, a wide width and a narrow width portion152having a width narrower than that of the wide width portion151. The narrow width portion152continues from one end of the wide width portion151, is substantially flush with the wide width portion151and extends in the X direction. The wide width portion151is entirely placed inside the protective member180. The narrow width portion152is partially placed inside the protective member180, and the remaining portion protrudes outside the protective member180. The wide width portion151is placed so as to substantially conform with, in the X direction, a region between an end of the parallel wiring portion143far from the center line CL1and an end of the parallel wiring portion133far from the center line CL1. In the X direction, the supply pipe121is placed close to the tip of the wide width portion151. The wide width portion151is provided with the predetermined interval from the bent portions135and145in the Y direction. For example, in the semiconductor device20U, the predetermined interval substantially conforms with a length obtained by subtracting a plate thickness of the output bus bar150from a length between the protrusion tips of the main terminals70C and70E. The wide width portion151is placed in a region, in the Z direction, from a position overlapping with the capacitor C1the plate125configuring the heat exchange portion123of the second stage. In the wide width portion151, multiple penetration holes153are formed. The main terminal70E of the semiconductor device20U and the main terminal70C of the semiconductor device20L are inserted into the penetration holes153. In the inserted state, the main terminal70is connected to the wide width portion151(output bus bar150) by the laser welding or the like. A facing portion154pfor the P bus bar130and a facing portion154nfor the N bus bar140are configured so as to avoid the penetration holes153. The facing portion154pof the output bus bar150and the facing portion135aof the P bus bar130face each other with the predetermined interval in the Y direction. The facing portion154nof the output bus bar150and the facing portion145aof the N bus bar140face each other with the predetermined interval in the Y direction. Since the supply pipe121exists, the width of the parallel wiring portion143is narrower than that of the parallel wiring portion133. Thereby, the width of the facing portion145ais narrower than that of the facing portion135a. However, in the capacitor C1, since the negative electrode terminal is placed on the side opposite to the heat exchange portion123, the extension length in the facing portion145ais obtained. The length of the facing portion145ain the Z direction is longer than that of the facing portion135a. Thereby, the facing area of the facing portion135aand the facing portion154pis substantially equal to the facing area of the facing portion145aand the facing portion154n. It may be possible to reduce the inductance while preventing the size in the X direction from increasing. The drive substrate160is formed by mounting an electronic component (not shown) on a printed substrate. The drive substrate160is formed with a drive circuit portion (driver) that receives the drive instruction from the control circuit portion9. The drive substrate160corresponds to a circuit board. The drive substrate160has a substantially rectangular planar shape. In the present example, the size of the drive substrate160is substantially same as that of the heat exchange portion123of the cooler120in the X direction. The size is longer than that of the heat exchange portion123in the Y direction. In the projection view from the Z direction, the drive substrate160is placed so as to overlap with most of the semiconductor devices20U and20L. Specifically, they are placed so as to overlap with each other except for a part of the main terminal70. In the Y direction, a part of the main terminal70, the bent portions135and145, the output bus bar150are placed so as not to overlap with the drive substrate160. On the side opposite to the main terminal70, the common wiring portions132and142protrude outward as compared with the drive substrate160. The drive substrate160is connected to the signal terminal80of the semiconductor device20. In the present embodiment, multiple penetration holes (not shown) are formed in the drive substrate160. The signal terminals80are inserted into the multiple penetration holes, and mounted. Thereby, a drive signal is output from the drive circuit portion formed on the drive substrate160via the signal terminal80. The signal terminals80are arranged in the X direction. The multiple signal terminals80are arranged in a line in the X direction, inserted, and mounted near one end of the drive substrate160in the Y direction. The external connection terminal170is a terminal for electrically connecting a control substrate (not shown) and the drive substrate160. In the control substrate, the control circuit portion9is formed. The drive substrate160is connected to the multiple external connection terminals170. In the present embodiment, multiple penetration holes (not shown) are formed in the drive substrate160. The external connection terminals170are inserted into the multiple penetration holes, and mounted. A part of the external connection terminals170transmits the drive instruction of the control circuit portion9to the drive circuit portion of the drive substrate160. The external connection terminal170is substantially L-shaped. The external connection terminal170has one bent portion of approximately 90 degrees. Of the external connection terminal170, a portion from the connection portion with the drive substrate160to the bent portion extends in the Z direction, and a portion from the bent portion to the tip extends toward the common wiring portions132and142in the Y direction. A portion of a predetermined range from the tip protrudes to the outside of the protective member180. The protective member180protects other elements configuring the power module110. The protective member180forms an outer shell of the power module110. As the protective member180, a sealing resin body integrally sealing the other elements, a preformed housing, or the like can be used. When the case is used, in order to improve the protection, a potting material or the like may be used in combination. In the present embodiment, as the protective member180, the sealing resin body is used. The sealing resin body is formed of a sealing material such as an epoxy resin, and is also referred to as a mold resin or a resin molded body. The sealing resin body is formed by, for example, a transfer molding method. The protective member180has, in the Z direction, a first surface181, and a second surface182opposite to the first surface181. The first surface181and the second surface182are planes orthogonal to the Z direction. The protective member180of the present embodiment has a substantially truncated square pyramid shape. Therefore, the protective member180has four lateral surfaces183to186. When the first surface181is a reference surface, each of the lateral surfaces183to186is also an inclined surface. An angle between each of the lateral surfaces183to186and the first surface181is an acute angle. Components configuring the power module110are the connection portion141of the N bus bar140, the capacitor C1, the connection portion131of the P bus bar130, the heat exchange portion123of the first stage, the semiconductor device20, the heat exchange portion123of the second stage, the drive substrate160that are arranged in a direction from the first surface181to the second surface182in this order. The supply pipe121and the discharge pipe122protrude from the first surface181to the outside of the protective member180. Nothing protrudes from the second surface182. Although not shown, the drive substrate160, the heat exchange portion123of the first stage, the semiconductor device20, the heat exchange portion123of the second stage, the connection portion141of the N bus bar140, the capacitor C1, the connection portion131of the P bus bar130may be arranged in a direction from the first surface181to the second surface182in this order. The common wiring portions132and142of the P bus bar130and the N bus bar140protrude, in the Y direction, from the lateral surface183close to the signal terminal80to the outside of the protective member180. From the lateral surface183, the external connection terminal170also protrudes. As shown inFIG.21, in the X direction, the common wiring portions132and142are placed between the external connection terminal170close to the semiconductor device20U and the external connection terminal170close to the semiconductor device20L. As shown inFIG.22, the external connection terminal170protrudes at positions close to the second surface182, and the common wiring portions132and142protrude at positions near the first surface181. Nothing protrudes from the lateral surface183and an opposite lateral surface184, that is, the lateral surface184close to the main terminal70. The narrow width portion152of the output bus bar150protrudes, in the X direction, from a lateral surface185close to the semiconductor device20U to the outside of the protective member180. Nothing protrudes from a lateral surface186opposite to the lateral surface185, that is, a lateral surface close to the semiconductor device20L. In such a manner, only the supply pipe121and the discharge pipe122protrude from the first surface181of the protective member180. Therefore, at a position close to the first surface181, a cooler different from the power module110is placed. Thereby, when the power module110is cooled, the different cooler is easily connected to the supply pipe121and the discharge pipe122. Since the lateral surface from which the common wiring portions132and142protrude is different from the lateral surface from which the output bus bar150protrudes, it may be possible to simplify the connection with the electric power line or the three phase winding. Here, the surge generated by switching of the upper-lower arm circuit10increases as a current change amount (current change rate) per unit time increases or the wiring inductance increases. In the power module110, the wiring inductance is reduced, and thereby the surge is reduced. Hereinafter, in the structure of the power module110, a structure that reduces the wiring inductance to enable the surge reduction will be described. FIG.28is a circuit diagram obtained by extracting the inverter7, the smoothing capacitor C2, and the motor generator3from the equivalent circuit diagram ofFIG.1, and shows the wiring inductance parasitic on the circuit. As shown in a dashed dotted line ofFIG.28, the power module110of each phase is connected in parallel between the P line12and the N line13, as described above. The wiring inductance generated between portions connected to each power module110in the P line12is referred to as an interphase upper inductance L2P. Specifically, the wiring inductance generated at the interphase portion between a connection portion with the common wiring portion132for the U phase in the P line12and a connection portion with the common wiring portion132for the V phase in the P line12is the interphase upper inductance L2P. Further, the wiring inductance generated at an interphase portion between a connection portion with the common wiring portion132for the V phase in the P line12and the connection portion with the common wiring portion132for the W phase in the P line12is the interphase upper inductance L2P. An impedance generated in proportion to the interphase upper inductance L2P is referred to as an interphase upper impedance. The wiring inductance generated at a portion connected to each power module110in the N line13is referred to as an interphase lower inductance L2N. Specifically, the wiring inductance generated at a connection portion with the common wiring portion142for the U phase in the N line13and the wiring inductance generated at a connection portion with the common wiring portion142for the V phase in the N line13are the interphase lower inductance L2N. The wiring inductance generated at a connection portion with the common wiring portion142for the V phase in the N line13and the wiring inductance generated at a connection portion with the common wiring portion142for the W phase in the N line13are the interphase lower inductance L2N. An impedance generated in proportion to the interphase lower inductance L2N is referred to as an interphase lower impedance. A wiring inductance of the electric path from the positive electrode terminal of the capacitor C1to the upper arm10U inside the power module110is referred to as an in-phase upper inductance L1P. Specifically, the inductances generated at the parallel portion134of the P bus bar130and the bent portion135are the in-phase upper inductances LIP. A wiring of a portion where the in-phase upper inductance LIP is formed is referred to as an upper wiring11Pa. An impedance generated in proportion to the in-phase upper inductance LIP is referred to as an in-phase upper impedance. A wiring inductance of the electric path from the negative electrode terminal of the capacitor C1to the lower arm10L inside the power module110is referred to as an in-phase lower inductance L1N. Specifically, the wiring inductances generated at the parallel portion144of the N bus bar140and the bent portion145are the in-phase lower inductances L1N. A wiring of a portion where the in-phase lower inductance L1N is referred to as a lower wiring11Na. An impedance generated in proportion to the in-phase lower inductance LIN is referred to as an in-phase lower impedance. Although each impedance has been described by taking the impedance as an example of the inverter7inFIG.28, each impedance also corresponds to the inverter8and the converter6as follows. That is, the power module110placed at a first phase among the phases is referred to as a first power module, and the power module110placed at a second phase is referred to as a second power module. An impedance of an electric path from the positive electrode terminal of the capacitor C1to the upper arm10U in the first power module corresponds to the in-phase upper impedance. An impedance of an electric path from the positive electrode terminal of the capacitor C1in the first power module to the upper arm10U in the second power module corresponds to the interphase upper impedance. An impedance of an electric path from the negative electrode terminal of the capacitor C1to the lower arm10L in the first power module corresponds to the in-phase lower impedance. An impedance of an electric path from the negative electrode terminal of the capacitor C1in the first power module to the lower arm10L in the second power module corresponds to the interphase lower impedance. A length of the wiring for forming the interphase upper inductance L2P is longer than a length of the wiring for forming the in-phase upper inductance L1P. Therefore, the interphase upper inductance L2P is larger than the in-phase upper inductance L1P, and the interphase upper impedance is larger than the in-phase upper impedance. A length of the wiring for forming the interphase lower inductance L2N is longer than a length of the wiring for forming the in-phase upper inductance L1P. Therefore, the interphase lower inductance L2N is larger than the in-phase lower inductance L1N, and the interphase lower impedance is larger than the in-phase lower impedance. Each of the interphase upper inductance L2P and the interphase lower inductance L2N is larger than a value obtained by adding the in-phase lower inductance LIN to the in-phase upper inductance LIP. An arrow Y1inFIG.28indicates a path in which the surge voltage is absorbed by the capacitor C1in a closed loop circuit formed in the parallel circuit11in the V phase. This surge voltage is generated when the switching elements Q1and Q2in the V phase are turned on and turned off. Similarly, also in the U phase and the W phase, the surge voltage is absorbed by the capacitor C1as shown by the arrow Y1. The surge voltage generated and absorbed in the same phase in such a manner is also referred to as a self-surge voltage in the following description. The closed loop circuit is a circuit formed by the parallel circuit11. In the closed loop circuit, the positive electrode terminal of the capacitor C1, the upper wiring11Pa, the upper-lower arm circuit10, the lower wiring11Na, and the negative electrode of the capacitor C1are connected in series in this order. The closed loop circuit does not include the electric power line. The closed loop circuit is referred to as a path in which the surge voltage is absorbed as described above, and is also referred to as a path in which the electric charges required for the switching of the switching elements Q1and Q2are supplied from the capacitor C1to the switching elements Q1and Q2. The closed loop circuit is a circuit that does not include the common wirings11P and11N. In other words, the P bus bar130is branched into a portion shown by a long dashed double-dotted line inFIG.28for forming the upper wiring11Pa and a portion for forming the common wiring11P. The common wiring11P of the P bus bar130is also referred to as an upper electric power wiring that connects the P line12and the upper wiring11Pa. The N bus bar140is branched into a portion shown by a long dashed double-dotted line inFIG.28for forming the lower wiring11Na and a portion for forming the common wiring11N. The common wiring11N of the N bus bar140is also referred to as a lower electric power wiring that connects the N line13and the lower wiring11Na. An arrow Y2inFIG.28indicates a path when the self-surge voltage generated in the V phase propagates from the closed loop circuit in the V phase to the closed loop circuit in the W phase via the electric power line. The surge voltage that interferes with the multiple upper-lower arm circuits10in such a manner is also referred to as an interference surge voltage in the following description. Similarly to the interference surge voltage propagating between the V phase and the W phase, the interference voltage may occur between the V phase and the U phase or between the W phase and the U phase. However, since the interphase upper inductance L2P is sufficiently larger than the in-phase upper inductance L1P, the interference surge voltage propagated from another phase to the own phase hardly occurs. The interference surge voltage is extremely smaller than the self-surge voltage. When the electric charge is supplied to the upper-lower arm circuit10connected in parallel, the electric charge is instantaneously supplied from the smoothing capacitor C2to the capacitor C1. Thereby, the capacitor C1can supply the electric charge again. Next, the effect of the power module110will be described. The power module110includes the upper-lower arm circuit10, the capacitor C1, the upper wiring11Pa, the lower wiring11Na, the common wiring11P as the upper electric power wiring, and the common wiring11N as the lower electric power wiring. The upper wiring11Pa connects the positive electrode terminal of the capacitor C1and the upper arm10U. The lower wiring11Na connects the negative electrode of the capacitor C1and the lower arm10L. The common wirings11P and11N respectively connect the upper wiring11Pa and the lower wiring11Na to the electric power lines. Accordingly, the power module110forms the closed loop circuit that does not include the electric power line. Therefore, when the electric charge required for the switching of the upper-lower arm circuit10is supplied from the capacitor C1, the electric charge supply path does include the electric power line. Therefore, the wirings of the path, that is, the upper wiring11Pa and the lower wiring11Na can be shortened. On the other hand, when the capacitor C1is abolished contrary to the present embodiment, the electric charge required for the switching is supplied from the smoothing capacitor C2. Then, since the electric power path for supplying the electric charges from the smoothing capacitor C2to the upper-lower arm circuit10includes the electric power line, the electric path may not be able to be sufficiently shortened. As described above, according to the power module110, it may be possible to easily shorten the wiring length that is one factor of the surge voltage occurrence as compared with the configuration in which the capacitor C1is abolished. Therefore, the wiring inductances LIP and LIN related to the self-surge voltage can be reduced, and the self-surge voltage generated at the upper-lower arm circuit10can be reduced. Moreover, since the closed loop circuit does not include the electric power line, it is difficult for the self-surge voltage to be superimposed on the self-surge voltage. Therefore, it may be possible to prevent the other upper-lower arm circuits10from interfering with the self-surge voltage via the electric power line. The power module110capable of reducing the surge voltage as described above is placed in each phase. Therefore, it may be possible to promote the prevention of the self-surge voltage interference between the upper-lower arm circuits10via the electric power line. Further, in the present example, the upper arm10U has the multiple main terminals70C connected to the upper wiring11Pa. The lower arm10L has the multiple main terminals70E connected to the lower wiring11Na. Therefore, the self-surge voltages of the adjacent main terminals70C and70E act so as to cancel each other, and it may be possible to reduce the in-phase upper inductance L1P and the in-phase lower inductance L1N. Thereby, the reduction of the self-surge voltage is promoted. Further, in the present example, the output bus bar150(that is, output wiring15) connecting the main terminal70E of the upper arm10U and the main terminal70C of the lower arm10L is provided. The output bus bar150has the facing portions154pand154nfacing the upper wiring11Pa and the lower wiring11Na. Therefore, the self-surge voltages act so as to cancel each other between the facing portions154pand154nof the output bus bar150and the upper wiring11Pa and the lower wiring11Na, and it may be possible to reduce the in-phase upper inductance LIP and the in-phase lower inductance LIN. Thereby, the reduction of the self-surge voltage is promoted. In particular, in the present example, in the configuration in which the semiconductor device20has the 1-in-1 package structure, the P bus bar130and the N bus bar140face the output bus bar150in the Y direction. In the projection view in the Y direction, the output bus bar150and the semiconductor device20overlap each other. In the Y direction, the facing portion135aof the P bus bar130is placed between the semiconductor chip40U and the output bus bar150. Similarly, in the Y direction, the facing portion145aof the N bus bar140is placed between the semiconductor chip40L and the output bus bar150. Accordingly, the current path from the P bus bar130to the output bus bar150via the semiconductor chip40U and the current path from the output bus bar150to the N bus bar140via the semiconductor chip40L are shown by the long dashed double-dotted line arrow inFIG.23. Accordingly, it may be possible to reduce the area of a current loop as compared with a 2-in-1 package in which two semiconductor chips configuring the upper-lower arm circuit10are provided in one package. Thereby, it may be possible to further reduce the self-surge voltage. Further, in the present example, the interphase upper impedance is larger than the in-phase upper impedance. The interphase lower impedance is larger than the in-phase lower impedance. Therefore, as shown by an arrow Y2ofFIG.28, it may be possible to prevent the surge voltage from propagating over the closed loop circuit of each phase and interfering with the circuit. Further, in the present example, the smoothing capacitor C2is connected to the upper-lower arm circuit10in parallel, and smooths the voltage of the electric power line. According to this, it may be possible to prevent the voltage of the electric power line from fluctuating. Since the electric charge is instantaneously supplied from the smoothing capacitor C2to the capacitor C1, it may be possible to suppress the capacitance of the capacitor C1. Thereby, it may be possible to reduce the size of the capacitor C1. As the semiconductor device20, the example in which two semiconductor devices20having the 1-in-1 package structure has been shown. However, the semiconductor device20is not limited to this. A semiconductor device having the 2-in-1 package structure in which the two arms (upper arm10U and lower arm10L) configuring the upper-lower arm circuit10is packaged in element units can be used. The arrangement of the main terminals70is not limited to the example. When the semiconductor device20has the 1-in-1 package, it is sufficient that the main terminals70includes at least one main terminal70C and at least one main terminal70E. The main terminals70having the same potential may be divided into multiple terminals. For example, the main terminal70C may be divided into multiple terminals. By parallelizing the multiple terminals. it may be possible to reduce the entire inductance of the divided terminals. When the semiconductor device20has the 2-in-1 package, it is sufficient that at least one main terminal70C close to the upper arm10U, at least one main terminal70E close to the lower arm10L, and at least one output terminal are provided. In an example shown inFIG.27, the common wiring portions132and142extend to the opposite sides of the connection portions131and141with respect to the parallel portions134and144. On the other hand, as shown inFIG.29, the common wiring portions132and142may extend to the parallel portions134and144with respect to the connection portions131and141. The upper arm10U and the lower arm10L have the different extension directions of the common wiring portions132and142. For example, the common wiring portions132and142may not be placed so as to face each other. Although, in the example shown inFIG.27, the upper arm10U and the lower arm10L have the multiple main terminals70C and70E, the upper arm10U and the lower arm10L may include one main terminal70C and one main terminal70E. Although, in the example shown inFIG.27, the main terminal70C and the main terminal70E are alternately arranged, the multiple main terminals70C may be arranged or the multiple main terminals70E may be arranged. Contrary to the example shown inFIG.27, the interphase upper impedance may be smaller than the in-phase upper impedance. The interphase lower impedance may be smaller than the in-phase lower impedance. As another example of the power module110, at least one of the cooler120of the power module110, the drive substrate160, or the protective member180may be abolished. The smoothing capacitor C2may be the abolished electric power conversion device5. The capacitor C1may be placed outside the protective member180. The structure of the cooler120may not be limited to the example. A part of the semiconductor device20configuring the upper-lower arm circuit10may be inserted into the flow path126inside the cooler120, and immersed in the refrigerant. In this configuration, the capacitor C1may be placed on the cooler120, and connected to the semiconductor device20. By immersion, it may be possible to suppress the surge voltage while cooling the semiconductor device20from both sides. Second Embodiment This embodiment is a modification example which is based on the preceding embodiment. In the embodiment, as the protective member180, the example of the sealing resin body has been shown. Instead of this, in this embodiment, as the protective member180, a case187and a sealing member188are used. As shown inFIGS.30to32, the power module110of the present embodiment includes the semiconductor device20, the cooler120, the capacitor C1, a P bus bar130, an N bus bar140, an output bus bar150, the drive substrate160, and the protective member180. InFIG.30, for convenience, the main terminal70of the semiconductor device20and the sealing member188are omitted. InFIG.31andFIG.32, the drive substrate160is omitted. Further, the elements configuring the power module110are shown in a simplified manner. The case187configuring the protective member180has a tubular shape. The case187has a substantially rectangular annular plane shape. The case187may be formed of the resin material or may be formed of the metal material. For example, a resin molded body formed by injection molding or a metal molded body formed by a die-casting method can be employed. An insert molded body using a metal component can be also employed. The case187extends in the Z direction. The case187has openings187aand187bat both ends in the Z direction. The case187has a penetration hole187c. The penetration hole187copens on an end surface187dclose to the opening187b, and communicates with a space of the tubular shaped inside. The penetration holes187care placed at both ends of the case187in the X direction. In the case187, at least, a part of the semiconductor device20, a part of the cooler120, the capacitor C1, a part of each of the bus bars130,140, and150are placed. Similarly to the preceding embodiment, the cooler120has the supply pipe121, a discharge pipe, and the heat exchange portions123in multiple stages. The semiconductor device20is placed between the heat exchange portions123. Also in the present embodiment, the semiconductor device20U configuring the upper arm10U and the semiconductor device20L configuring the lower arm10L are arranged in the X direction. The two semiconductor devices20U and20L are sandwiched by the two heat exchange portions123. In the present embodiment, a direction in which the supply pipe121and the discharge pipe122are arranged is along the X direction. Between the supply pipe121and the discharge pipe122, the semiconductor device20is placed. At one of the heat exchange portions123, a closing plate127is integrally placed. The closing plate127is plate so as to close the opening187aof the case187. The closing plate127is placed, for example, in a flat shape. The closing plate127is fixed to a surface of the heat exchange portion123, and the surface is opposite to a surface close to the semiconductor device20. As shown inFIG.31andFIG.32, the cooler120is assembled to the case187so that the closing plate127closes the opening187a. The closing plate127is fixed to the case187such adhesion, screw fastening, or the like. The closing plate127functions as a bottom of the case187. In the present embodiment, a step having a low inner periphery is placed at the end surface187eclose to the opening187a. An outer peripheral edge of the closing plate127is placed at a step portion of the end surface187e. In this placement state, the cooler120is fixed to the case187. The opening187acorresponds to an opening end. The capacitor C1forms a capacitor unit190together with the P bus bar130, the N bus bar140, and the output bus bar150. The capacitor unit190has a case191. The case191functions as a housing accommodating the capacitor C1. The case191functions as a terminal block holding each of the bus bars130,140, and150so that the outside is connectable. In such a manner, the capacitor C1, the P bus bar130, the N bus bar140, and the output bus bar150are integrally held. Similarly to the preceding embodiment, the P bus bar130is electrically connected to the main terminal70C of the semiconductor device20U. The N bus bar140is electrically connected to the main terminal70E of the semiconductor device20L. The output bus bar150is electrically connected to the main terminal70E of the semiconductor device20U and the main terminal70C of the semiconductor device20L. The capacitor unit190is placed on the cooler120in the case187. The capacitor unit190is placed on the heat exchange portion123on which the closing plate127is not placed, on the opposite side to the semiconductor device20. The common wiring portions132and142of the P bus bar130and the N bus bar140protrude to the outside of the case187via the penetration hole187con one end side in the X direction. The common wiring portions132and142extend to the opposite side to the heat exchange portion123in the Z direction. The output bus bar150protrudes to the outside of the case187via the penetration hole187cat an end opposite to the P bus bar130and the N bus bar140. The protrusion portion of the output bus bar150extends to the opposite side to the heat exchange portion123in the Z direction. The power module110further includes a current sensor200. The current sensor200detects the current flowing through the output bus bar150. Therefore, the current sensor200is placed in the vicinity of the output bus bar150. In the present embodiment, the current sensor200has a sensor main portion201and a lead202. At the sensor main portion201, an electromagnetic conversion element is formed. As the electromagnetic conversion element, for example, a magnetoresistive effect element such as a hole element, a GMR element, a TMR element, or the like can be employed. The lead202of the current sensor200is mounted on the drive substrate160, for example, inserted to be mounted. The case191has a recess191aon a surface close to the drive substrate160. The sensor main portion201detects the current (phase current) flowing through the bus bar150in a state where the current sensor200is inserted in the recess191aand placed. The drive substrate160is placed on the opposite side to the cooler120with respect to the capacitor unit190. In the present embodiment, the drive substrate160is placed so as to close the opening187bof the case187. The drive substrate160is fixed to the case187in a state of being placed on the end surface187dclose to the opening187b. The current sensor200is mounted on one end of the drive substrate160in the X direction. The drive substrate160has a convex161at an end close to the output bus bar150. The convex161protrudes to the opposite side to the opening187b, that is, the outside. The current sensor200is mounted on the convex161. The current sensor200extends in the Z direction in a state of being mounted on the drive substrate160. Outside the case187, the current sensor200is placed in the vicinity of the protrusion portion of the output bus bar150. The sealing member188configuring the protective member180seals at least a part of elements accommodated in the case187. As the sealing member188, the electric insulation material, for example, a resin or gel can be employed. The sealing member188may be referred to as a potting material. The sealing member188seals at least a part of the semiconductor device20and the capacitor C1. The sealing member188is preferably placed between members having different potentials. In the present embodiment, the closing plate127is placed as the bottom side, and the sealing member188is filled. The sealing member188is placed only in the periphery of the main terminals70so as to integrally cover all the main terminals70of the semiconductor device20. The sealing member188is placed between the main terminals70C and70E. In such a manner, in the present embodiment, the cooler120closes the opening187aof the case187. Therefore, in addition to the effects described in the preceding embodiment, it may be possible to simplify the configuration together with the sealing using the sealing member188. The case187including the cooler120has a bottomed tubular shape. Accordingly, the sealing member188is filled in the case187close to the opening187b. Thereby, the sealing member188is held in the case187, and the insulation between the main terminals70C and70E can be ensured. The different potentials insulated by the sealing member188is not limited to the potentials of the main terminals70C and70E. The different potentials may be potentials of the bus bars130,140, and150. The sealing member188may be placed between the main terminal70and the bus bar having a different potential from the main terminal70. In particular, in the present embodiment, since the sealing member188is placed on the periphery of the main terminal70, it may be possible to secure the insulation between the main terminals70C and70E while reducing the used amount of the sealing member188. The example in which the cooler120closes the opening187aof the case187has been shown. However, it is not limited to this. The drive substrate160may close the opening187aof the case187. The example in which the drive substrate160is placed close to the opening187ahas been shown. However, it is not limited to this. The drive substrate160may be placed on the opposite side to the capacitor unit190with respect to the cooler120. In this case, both of the drive substrate160and the cooler120may close the opening187a. The arrangement of the sealing member188in the case187is not limited to the example. For example, as shown inFIG.33, the sealing member188may be filled so as to completely seal also the heat exchange portion123close to the capacitor unit190. In this case, the electrically insulating sealing member188is placed between the heat exchange portion123and the main terminal70. Accordingly, it may be possible to reduce the distance between the heat exchange portion123(cooler120) and the main terminal70. InFIG.33, a protrusion portion123ais placed at the end close to the main terminal70in the heat exchange portion123. The protrusion portion123aprotrudes in the Z direction with respect to the arrangement portion of the semiconductor device20in the heat exchange portion123. The metal heat exchange portion123(protrusion portion123a) approaches the main terminal70, and thereby the inductance of the main terminal70can be reduced. Thereby, it may be possible to reduce the surge voltage. The case187may be filled with the sealing member188. The length of the case187in the Z direction is not particularly limited. The metal case187functions as a shielding plate against noise. When the metal case187is employed, the length of the case187in the Z direction may be longer than a laminate of the semiconductor device20, the cooler120, and the capacitor unit190. Thereby, it may be possible to effectively shield the external noise with use of the case187. Further, it may be possible to prevent the noise generated at the semiconductor device20from propagating to the outside. In the examples shown inFIGS.34to36, the metal case187further has a penetration hole187fcorresponding to the signal terminal80. The penetration hole187fopens on a portion close to the signal terminal80in an end surface80d, and communicates with the space of the tubular inside. The penetration hole187fextends in the Z direction. The penetration hole187fopens on one of four ends of the end surface187dhaving a substantially rectangular annular plane. The penetration hole187fopens on the edge different from the penetration hole187c. In the present embodiment, all the signal terminals80are inserted through one penetration hole187f. For each semiconductor device20, the penetration hole187fmay be separated. InFIG.35, for convenience, the drive substrate160is omitted. The signal terminal80has a bent portion, and has a substantially L-shape in the ZX plane. In the signal terminal80, a portion extending in the Z direction is inserted in the penetration hole187f. A part of the signal terminal80protrudes from the end surface187d. Since a part of the signal terminal80is surrounded by the metal case187, the case187can effectively shield the noise. The penetration hole opening on the side of the end surface187emay be placed in the case187, and the signal terminal80may protrude to the side of the end surface187e. Third Embodiment This embodiment is a modification example which is based on the preceding embodiments. In the embodiments, a branch structure from the electric power wirings (common wirings11N,11P) to the upper wiring11Pa and the lower wiring11Na is not particularly described. In this embodiment, in consideration of the heat influence, the branch structure is determined. FIG.37shows an equivalent circuit diagram of the power module110according to the present embodiment.FIG.37shows a circuit diagram obtained by extracting the inverter7, the smoothing capacitor C2, and the motor generator3from the equivalent circuit diagram inFIG.1. As shown inFIG.37, the upper wiring11Pa is divided into two portions based on a connection point Np with the common wiring11P (upper electric power wiring). The upper wiring11Pa is branched into two from the connection point Np. The upper wiring11Pa has a first wiring portion11Pb and a second wiring portion11Pc. The first wiring portion11Pb is a wiring portion electrically connecting the collector electrode of the upper arm10U and the connection point Np. The second wiring portion11Pc is a wiring portion electrically connecting the positive electrode terminal of the capacitor C1and the connection point Np. Each phase of the inverter7has the similar configuration. The lower wiring11Na is divided into two portions based on a connection point Nn with the common wiring11N (lower electric power wiring). The lower wiring11Na is branched into two from the connection point Nn. The lower wiring11Na has a first wiring portion11Nb and a second wiring portion11Nc. The first wiring portion11Nb is a wiring portion electrically connecting the emitter electrode of the lower arm10L and the connection point Nn. The second wiring portion11Pc is a wiring portion electrically connecting the negative electrode terminal of the capacitor C1and the connection point Nn. Each phase of the inverter7has the similar configuration. In such a manner, the upper wiring11Pa and the lower wiring11Na have first wiring portions11Pb and11Na from the connection points Np and Nn with the corresponding common wirings11P and11N (electric power wirings) to the corresponding arms. The upper wiring11Pa and the lower wiring11Na have second wiring portions11Pc and11Nc from the connection points Np and Nn to the corresponding terminals of the capacitor C1. In at least one of the upper wiring11Pa or the lower wiring11Na, the wiring resistances of the first wiring portions11Pb and11Nb are smaller than wiring resistances of the second wiring portions11Pc and11Nc. Here, in the upper wiring11Pa, a wiring resistance of the first wiring portion11Pb is Rpb and a wiring resistance of the second wiring portion11Pc is Rpc. In the lower wiring11Na, a wiring resistance of the first wiring portion11Nb is Rnb, and a wiring resistance of the second wiring portion11Nc is Rnc. For example, when the upper wiring11Pa satisfies the relationship, a wiring resistance Rpb (wiring resistance Rpc) is set. When the lower wiring11Na satisfies the relationship, a wiring resistance Rnb (wiring resistance Rnc) is set. FIG.38is a schematic diagram showing the power module110that satisfies the relationship.FIG.38shows the power module110in a simplified manner.FIG.38shows the semiconductor devices20(20U,20L), the P bus bar130, the N bus bar140, and the capacitor C1as elements configuring the power module110. Similarly to the preceding embodiments, the power module110may include at least one of the cooler120, the output bus bar150, the drive substrate160, or the protective member180in addition to the elements. When the power module110includes the protective member180, a sealing resin body, a molded resin case, a metal case, or the like can be used. When the case is used, the case is filled with a sealing material. Further, the protective member180may be configured with use of a film in which a metal is laminated on the resin surface. Such a film includes, for example, a laminated film in which a metal foil is attached to the resin, and a vapor deposition film in which a metal is vapor-deposited on the resin surface. As the metal, for example, aluminum can be used. The common wiring11P and the upper wiring11Pa are provided as the P bus bar130. The common wiring11N and the lower wiring11Na are provided as the N bus bar140. The P bus bar130includes the common wiring portion132and the parallel wiring portion133. The N bus bar140has the common wiring portion142and the parallel wiring portion143. InFIG.38, the common wiring portions132and142are connected to the corresponding parallel wiring portions133and143. The common wiring portion132corresponds to the common wiring11P. The common wiring portion142corresponds to the common wiring11N. In the direction in which the semiconductor device20and the capacitor C1are arranged, the parallel wiring portions133and143are placed between the semiconductor device20and the capacitor C1. The parallel wiring portions133and143are placed so that the plate surfaces face each other. In the arrangement direction, the connection portion131(not shown) is placed at one end of the parallel wiring portion133, and a connection portion with the semiconductor device20U is placed at the other end. In the arrangement direction, the connection portion141(not shown) is placed at one end of the parallel wiring portion143, and a connection portion with the semiconductor device20L is placed at the other end. In each of the parallel wiring portions133and143, the thickness is substantially uniform. In each of the parallel wiring portions133and143, the width in a direction orthogonal to the arrangement direction is substantially constant. The common wiring portion132is connected to the parallel wiring portion133at a position close to, in the arrangement direction, the semiconductor device20. The connection point corresponds to a connection point Np. The current path between the common wiring portion132and the semiconductor device20U and the current path between the common wiring portion132and the capacitor C1are branched from the common wiring portion132to both ends in the width direction as shown by broken line arrows. The current path of the semiconductor device20U is shorter than that of the capacitor C1. The wiring length of the semiconductor device20U from the connection point Np is shorter than that of the capacitor C1. Thereby, a wiring resistance Rpb (wiring resistance Rpc) is obtained. Similarly, the common wiring portion142is connected to the parallel wiring portion143at a position close to, in the arrangement direction, the semiconductor device20. The connection point corresponds to a connection point Nn. The current path between the common wiring portion142and the semiconductor device20L and the current path between the common wiring portion142and the capacitor C1are branched from the common wiring portion142to both ends in the width direction as shown by solid line arrows. The current path of the semiconductor device20L is shorter than that of the capacitor C1. The wiring length of the semiconductor device20L from the connection point Nn is shorter than that of the capacitor C1. Thereby, a wiring resistance Rnb (wiring resistance Rnc) is obtained. Here, the AC current and the DC current flow through the bus bars130and140. The AC current is a current at the time of switching the switching element. The DC current is a current in a steady state where the switching element is turned on. The capacitor C1ideally passes only the AC current. Accordingly, in the current path shown inFIG.38, mainly, the AC current flows on the side of the capacitor C1. The DC current and the AC current flow on the side of the semiconductor device20. The heat amount generated by the DC current is larger than the heat amount generated by the AC current. In the present embodiment, the wiring length of the semiconductor device20U from the common wiring portion132is shorter than that of the capacitor C1. Thereby, the wiring resistance Rpb (wiring resistance Rpc) is obtained. Since the wiring resistance Rpb of the path through which the DC current flows is small, the heat amount generated by the DC current can be reduced. Thereby, it may be possible to result the heat transferred to the capacitor C1. Similarly, the wiring length of the semiconductor device20L from the common wiring portion142is shorter than that of the capacitor C1. Thereby, a wiring resistance Rnb (wiring resistance Rnc) is obtained. Since the wiring resistance Rnb of the path through which the DC current flows is small, the heat amount generated by the DC current can be reduced. Thereby, it may be possible to reduce the heat transferred to the capacitor C1. The example in which the conditions of both of the wiring resistance Rpb (wiring resistance Rpc) and the wiring resistance Rnb (wiring resistance Rnc) are satisfied has been shown. However, it is not limited to this. It is sufficient that at least one condition is satisfied. When one of the conditions is satisfied, it may be possible to reduce the heat amount generated by the DC current as compared with a configuration that satisfies none of the conditions. The heat amount generated by the DC current is larger than the heat amount generated by the AC current. At least a part of the bus bars130and140is exposed, and thereby it may be possible to effectively dissipate the heat generated by the DC current. In the bus bars130and140, a part of portions through which the DC current flows, that is, portions corresponding to the first wiring portions11Pb and11Nb may be exposed from the sealing resin body or the sealing material. The present embodiment has shown the example in which the wiring length is shortened and the wiring resistance to the semiconductor device20is smaller than the wiring resistance to the capacitor C1. The cross-sectional area of the current path, for example, the thickness or the width may be changed, and thereby the wiring resistance to the semiconductor device20can be made smaller than the wiring resistance to the capacitor C1. Hereinafter, a more specific configuration example of the power module110is shown below. Also in each shown below,FIG.38shows the semiconductor devices20(20U,20L), the P bus bar130, the N bus bar140, and the capacitor C1as elements configuring the power module110. The power module110may include at least one of the cooler120, the output bus bar150, the drive substrate160, or the protective member180in addition to the elements. The power module110shown inFIG.39andFIG.40corresponds to the power module110shown in the preceding embodiment (seeFIG.30). The positive electrode terminal of the capacitor C1is placed at the lateral surface close to the signal terminal80in the Y direction. The negative electrode terminal is placed at the lateral surface close to the main terminal70in the Y direction. The P bus bar130includes the connection portion131, the common wiring portion132, the parallel wiring portion133, and a connection portion137. The common wiring portion132is placed close to one end of the capacitor C1in the X direction that is the longitudinal direction of the capacitor C1. The common wiring portion132is connected to the parallel wiring portion133. The common wiring portion132has one bent portion, and has a substantially L-shape in the ZX plane. The common wiring portion132has a portion of which thickness direction is substantially parallel to the Z direction and which extends from the parallel wiring portion133in the X direction, and a portion of which thickness direction is the X direction and which extends in the Z direction. The parallel wiring portion133is placed close to the lower surface that is the facing surface of the capacitor C1with the semiconductor device20. The parallel wiring portion133is placed between the capacitor C1and the semiconductor device20. The parallel wiring portion133extends in the Y direction. In the Y direction, on the one end side of the parallel wiring portion133, specifically, at a position close to the signal terminal80, the connection portion131is connected. The connection portion131is bent with respect to the parallel wiring portion133. The connection portion131is connected to the positive electrode terminal of the capacitor C1in the Y direction. In the parallel wiring portion133, an end opposite to the connection portion131is bent toward the main terminal70. The parallel wiring portion133has a substantially L-shape in the YZ plane. The connection portion137is connected to a bent tip of the parallel wiring portion133. The connection portion137has one bent portion, and has a substantially L-shape in the YZ plane. The connection portion137is connected to the main terminal70C of the semiconductor device20U. The P bus bar130has the connection portions137. The number of connection portions137is same as the number (four) of main terminals70C. The P bus bar130is formed of one metal plate without welding. The N bus bar140includes the connection portion141, the common wiring portion142, the parallel wiring portion143, a connection portion147, and a join portion148. The common wiring portion142is placed on the same side as the common wiring portion132. The common wiring portion142has one bent portion, and has a substantially L-shape in the ZX plane. The common wiring portion142is not connected to the parallel wiring portion143, and is connected to the join portion148. The common wiring portion142has a portion of which thickness direction is substantially parallel to the Z direction and which extends from the join portion148, and a portion of which thickness direction is the X direction and which extends in the Z direction. The extension portion of the common wiring portion142in the Z direction and the extension portion of the common wiring portion132in the Z direction are arranged in the Y direction. The extension portion of the common wiring portion142in the Z direction is placed at a position closer to, in the Z direction, the capacitor C1than the extension portion of the common wiring portion132in the X direction. The lateral surface of a part of the common wiring portion142and the lateral surface of the extension portion of the common wiring portion132in the X direction face each other. The join portion148is placed on the lateral surface of the capacitor C1close to the common wiring portions132and142, and is placed on an upper surface of the capacitor C1opposite to a surface close to the semiconductor device20. The common wiring portion142is connected to a lateral surface placement portion of the join portion148, and the connection portion141is connected to an upper surface placement portion. The join portion148joins the common wiring portion142and the connection portion141. The join portion148can be a part of the common wiring portion142. The connection portion141is bent with respect to the upper surface placement portion of the join portion148, and the negative electrode terminal of the capacitor C1is connected. The parallel wiring portion143is connected to an end of the connection portion141opposite to the join portion148. The parallel wiring portion143extends in the Y direction. In the parallel wiring portion143, an end opposite to the connection portion141is bent toward the main terminal70. The parallel wiring portion143has a substantially L-shape in the YZ plane. The parallel wiring portion143is placed to face the parallel wiring portion133. The connection portion147is connected to a bent tip of the parallel wiring portion143. The connection portion147has one bent portion, and has a substantially L-shape in the YZ plane. The connection portion147is connected to the main terminal70E of the semiconductor device20L. The N bus bar140has the connection portions147. The number of connection portions147is same as the number (five) of main terminals70E. The N bus bar140is formed of one metal plate without welding. In such a manner, in examples shown inFIG.39andFIG.40, on the side of the P bus bar130, the wiring resistance Rpb (wiring resistance Rpc) is satisfied. Thereby, it may be possible to reduce the heat amount generated by the DC current. In the N bus bar140, a position of the connection portion141is closer to the common wiring portion142than that of the connection portion147. The N bus bar140is placed on the upper surface of the capacitor C1. The P bus bar130is placed on the lower surface. Thereby, it may be possible to improve the heat dissipation of the capacitor C1. The output bus bar150(not shown) has the similar configuration to the preceding embodiment (FIG.30). The connection portion of the output bus bar150to the outside is placed on the opposite side to the common wiring portions132and142in the X direction so as to sandwich the capacitor C1between the output bus bar150and the common wiring portions132and142. The output bus bar150extends so as to face (stack on) the join portion148, the connection portion141, and the parallel wiring portion143. A connection portion is placed at the extension tip of the output bus bar150. The connection portion connects the main terminal70E of the semiconductor device20U and the main terminal70C of the semiconductor device20L. The cooler120(not shown) is placed so as to cool the semiconductor device20from both surfaces in the Z direction. One of the heat exchange portions123of the cooler120is placed between the semiconductor device20and the capacitor C1via the parallel wiring portion133of the P bus bar130. In an example shown inFIG.41, the placement of the terminal of the capacitor C1is opposite to the configuration shown inFIG.39. The negative electrode terminal of the capacitor C1is placed on the lateral surface close to the signal terminal80in the Y direction. The positive electrode terminal is placed on the lateral surface close to the main terminal70. The N bus bar140has the similar configuration to the P bus bar130of the example shown inFIG.39. The N bus bar140includes the connection portion141, the common wiring portion142, the parallel wiring portion143, and the connection portion147. The common wiring portion142is connected to the parallel wiring portion143. The parallel wiring portion143is placed between the lower surface of the capacitor C1and the semiconductor device20. The parallel wiring portion143extends in the Y direction, and is connected to the connection portion141on the side of the signal terminal80. On the opposite side to the connection portion141, the parallel wiring portion143is bent toward the main terminal70. The connection portion147is connected to a bent tip of the parallel wiring portion143. The P bus bar130includes the connection portion131, the common wiring portion132, the parallel wiring portion133, and the connection portion137. The common wiring portion132is close to the positive electrode terminal in the Y direction, and is connected to the parallel wiring portion133. The parallel wiring portion133is placed between the lower surface of the capacitor C1and the semiconductor device20. The parallel wiring portion133is placed between the parallel wiring portion143and the capacitor C1. The parallel wiring portion133extends in the Y direction. The end of the parallel wiring portion133close to the main terminal70is connected to the connection portions131and137. In the X direction, in the end of the parallel wiring portion133, a part close to the common wiring portions132and142is bent toward the main terminal70. The bent tip of the parallel wiring portion133is connected to the connection portion137. In the X direction, the remaining portion of the parallel wiring portion133extends in the Z direction, and is welded to be connected to a portion extending from the side of the connection portion131. In the following, the welded portion of the parallel wiring portion133may be referred to as a welded portion133a. In a configuration shown inFIG.41, the welded portion133ais placed at the current path between the common wiring portion132and the connection portion131, and a folded portion of the welded portion133ais long. Thereby, the P bus bar130satisfies the wiring resistance Rpb (wiring resistance Rpc). In the N bus bar140, a position of the connection portion141is closer to the common wiring portion142than that of the connection portion147. Instead of the configuration shown inFIG.39andFIG.41, the wiring resistance Rnb (wiring resistance Rnc) may be satisfied in the N bus bar140and the connection portion131may be closer to the common wiring portion132than the connection portion137in the P bus bar130. In an example shown inFIG.42, the positive electrode terminal of the capacitor C1is placed on the lower surface close to the semiconductor device20in the Z direction. The negative electrode is placed on the upper surface opposite to the lower surface. The P bus bar130includes the connection portion131(not shown), the common wiring portion132, the parallel wiring portion133, the connection portion137, and a join portion138. The join portion138joins the common wiring portion132and the parallel wiring portion133. The join portion138may be also referred to as a part of the common wiring portion132. The join portion138extends in the XY plane. One end is connected to the common wiring portion132. The other end is connected to the parallel wiring portion133. The parallel wiring portion133has a bent portion similarly toFIG.39. The bent tip is connected to the connection portion137. The parallel wiring portion133has the welded portion133aextending in the Z direction. The parallel wiring portion133extends from the welded portion133atoward the capacitor C1in the Y direction, and extends toward the lower surface of the capacitor C1via the bent portion. The tip of the parallel wiring portion133is connected to the connection portion131. The N bus bar140includes the connection portion141, the common wiring portion142, the parallel wiring portion143, the connection portion147, and the join portion148. The join portion148joins the common wiring portion142and the parallel wiring portion143. A part of the join portion148faces the join portion138. The parallel wiring portion143has a bent portion similarly toFIG.39. The bent tip is connected to the connection portion147. In the X direction, the bent portion of the parallel wiring portion143and the bent portion of the parallel wiring portion133are arranged. The parallel wiring portion143has a welded portion143aextending in the Z direction. The parallel wiring portion143extends from the welded portion143atoward the capacitor C1in the Y direction, and extends toward the upper surface of the capacitor C1via the bent portion. The tip of the parallel wiring portion143is connected to the connection portion141. A part of the parallel wiring portion143faces the parallel wiring portion133. In such a manner, in the example shown inFIG.42, on the side of the P bus bar130, the wiring resistance Rpb (wiring resistance Rpc) is satisfied. On the side of the N bus bar140, the wiring resistance Rnb (wiring resistance Rnc) is satisfied. The N bus bar140is placed on the upper surface of the capacitor C1. The P bus bar130is placed on the lower surface. In an example shown inFIG.43, similarly toFIG.42, the positive electrode terminal of the capacitor C1is placed on the lower surface close to the semiconductor device20in the Z direction. The negative electrode is placed on the upper surface opposite to the lower surface. It differs fromFIG.42in that the bus bars130and140do not have the weld portion. Similarly to the configuration shown inFIG.39, the substantially entire lengths, in the X direction, of the bent portions of the parallel wiring portions133and143face each other. Thereby, in a region wider than that of the example shown inFIG.42, the parallel wiring portions133and143face each other. In the example shown inFIG.43, on the side of the P bus bar130, the wiring resistance Rpb (wiring resistance Rpc) is satisfied. On the side of the N bus bar140, the wiring resistance Rnb (wiring resistance Rnc) is satisfied. The N bus bar140is placed on the upper surface of the capacitor C1. The P bus bar130is placed on the lower surface. Instead of the configurations shown inFIG.42andFIG.43, the negative electrode terminal of the capacitor C1may be placed on the lower surface and the positive electrode terminal may be placed on the upper surface. In an example shown inFIG.44, the negative electrode of the capacitor C1is placed on the lateral surface close to the common wiring portions132and142in the X direction. The positive electrode terminal is placed on the lateral surface opposite to the negative electrode. InFIG.44, for convenience, the main terminals70C and70E are omitted. InFIG.44, similarly toFIG.42, in the X direction, the bent portions of the parallel wiring portions133and143are arranged. The bent portion of the parallel wiring portion133is placed on the side farther from the common wiring portions132and142. The bent tip of the parallel wiring portion133is connected to the connection portion137. The parallel wiring portion133has the welded portion133a. The parallel wiring portion133has a Z direction extension portion including the welded portion133aand a portion extending toward the positive electrode terminal in the XY plane. The bent portion of the parallel wiring portion143is placed on the side closer to the common wiring portions132and142. The bent tip of the parallel wiring portion143is connected to the connection portion147. The parallel wiring portion143has the welded portion143a. The parallel wiring portion143has a Z direction extension portion including the welded portion143aand a portion extending toward the negative electrode terminal in the XY plane. In the example shown inFIG.44, on the side of the P bus bar130, the wiring resistance Rpb (wiring resistance Rpc) is satisfied. On the side of the N bus bar140, the wiring resistance Rnb (wiring resistance Rnc) is satisfied. Instead of the configuration shown inFIG.44, the positive electrode terminal of the capacitor C1may be placed on the lateral surface close to the common wiring portions132and142. The negative electrode may be placed on the lateral surface opposite to positive electrode terminal. Fourth Embodiment This embodiment is a modification example which is based on the preceding embodiments. The second embodiment has shown the example in which the power module110includes the current sensor200. In this embodiment, a configuration capable of improving an accuracy of the current detection by the current sensor200will be described. As shown inFIG.46, the power module110of the present embodiment includes the output bus bar150, the drive substrate160, and the current sensor200. The output bus bar150corresponds to an output wiring. The power module110has the substantially similar structure to that of the second embodiment (seeFIG.30). Although not shown, the power module110includes the semiconductor devices20(20U,20L) configuring the upper-lower arm circuit10. The main terminal70E of the semiconductor device20U configuring the upper arm10U and the main terminal70C of the semiconductor device20L configuring the lower arm10L are connected to the output bus bar150. Further, the power module110includes the capacitor C1, the cooler120, the P bus bar130, and the N bus bar140. The capacitor C1, the P bus bar130, the N bus bar140, and the output bus bar150are integrated as the capacitor unit190. The output bus bar150has a detected portion155and a bent portion156, as shown inFIG.46. The detected portion155is a portion of the output bus bar150where the current sensor200detects the current. The main portion201of the current sensor200is placed so as to detect the current flowing through the detected portion155. The detected portion155extends in one direction. In the present embodiment, the detected portion155extends in the X direction. In the detected portion155, a penetration portion155ais formed. The penetration portion155apenetrates between, in the detected portion155, a first surface155band a second surface155cthat are plate surfaces. The penetration portion155ais provided as a notch opening on the lateral surface. In the present embodiment, as the penetration portion155a, a penetration hole is employed. As shown inFIG.30, the current sensor200is mounted on the drive substrate160. The current sensor200extends from the drive substrate160toward the detected portion155in the Z direction. The main portion201is inserted into the recess191a(seeFIG.30) of the case191, and inserts the penetration portion155aof the output bus bar150. The main portion201is placed on the sides of both of the first surface155band the second surface155cvia the penetration portion155aAlthough not shown, the electromagnetic conversion elements are arranged on the side of each of the first surface155band the second surface155c. The bent portion156is bent with respect to the detected portion155. One end of the bent portion156is connected to the detected portion155. The bent portion156extends in a direction different from the detected portion155. The bent portion156of the present embodiment is the bent portion156at an angle of approximately 90 degrees with respect to the detected portion155, and extends in the Z direction. The bent portion156has a terminal portion156aand a facing portion156b. The terminal portion156ais placed on an end opposite to one end connected to the detected portion155in the bent portion156. The terminal portion156ais a portion connected to a different member, that is, a member different from the elements configuring the power module110. In the present embodiment, at the end of the output bus bar150, the terminal portion156ais placed. The facing portion156bextends from the terminal portion156atowards the detected portion155, and faces a different member together with the terminal portion156a. The end of the facing portion156b, specifically, the end farther from the detected portion155is connected to the terminal portion156a. The facing portion156bis a portion in a predetermined range from the terminal portion156ain the bent portion156. At least a part of the bent portion156other than the terminal portion156ais the facing portion156b. InFIG.46, as the different member, a bus bar241is exemplified. As described later, bus bars241and251correspond to different members.FIG.46shows a connection structure between the output bus bar150of the power module110and the bus bar241. As described later, the bus bar241is an element configuring the electric power conversion device5together with the power module110. The bus bar241has a terminal portion241aand an extension portion241b. The terminal portion241acorresponds to a connection portion of the bus bar. The terminal portion241ais a portion of the terminal portion156aof the output bus bar150in the bus bar241. The terminal portion156aand the terminal portion241aare connected by welding or the like. The terminal portions156aand241aare connected in a preferable state where the plate surfaces face each other. The output bus bar150and the bus bar241are connection portions of the terminal portions156aand241a, and are mechanically and electrically connected. In the present embodiment, the terminal portion241ais placed at the end of the bus bar241. An extension length of the terminal portion241ais substantially equal to an extension length of the terminal portion156a. The extension portion241bis a portion extending from the terminal portion241a. One end of the extension portion241bis connected to the terminal portion241a. A part of the extension portion241band the terminal portion241aare placed to face the terminal portion156aof the output bus bar150and the facing portion156b. In the extension portion241b, a predetermined portion from the terminal portion241ais placed to face the facing portion156b. In the present embodiment, the extension portion241bis bent at an angle of approximately 90 degrees in the middle of the path. The extension portion241bhas a bent portion241b1. In the bus bar241, a portion from the bent portion241b1towards the terminal portion241aextends in the Z direction. A portion from the bent portion241b1to the opposite side extends in the X direction and in a direction away from the detected portion155. The output bus bar150and the bus bar241have the substantially same extension length including the corresponding terminal portions156aand241ain the Z direction. Specifically, the extension lengths of the extension portion241bcloser to the terminal portion241athan the bent portion241b1and the terminal portion241aare substantially equal to the extension lengths of the facing portion156band the terminal portion156a. In the output bus bar150and the bus bar241, portions extending in the Z direction due to bending substantially entirely face each other. It is preferable that the plate surfaces of the output bus bar150and the bus bar241face each other. The bus bar251has the similar configuration to the bus bar241. FIG.47schematically shows the electric power conversion device5of the power module110shown inFIG.46. This electric power conversion device5has a connection structure between the output bus bar150and the bus bar241(and bus bar251) shown in FIG.46. The electric power conversion device5includes a housing220, an input terminal block230, an output terminal block240, a reactor module250, and a capacitor module260in addition to the power module110. Although the bus bar251is omitted to be shown, the electric power conversion device5further includes a control substrate on which a wiring member (for example, bus bar), a cooler, the control circuit portion9are formed. The wiring member electrically connects the elements configuring the electric power conversion device5. The cooler cools the elements in the housing220, for example, the power module110, the reactor module250, and the capacitor module260. The electric power conversion device5configures to eight upper-lower arm circuits10shown in the first embodiment (seeFIG.1). Therefore, the electric power conversion device5includes eight power modules110. The electric power conversion device5includes the two power modules110configuring the converter6, and the six power modules110configuring the inverters7and8. The multiple power modules110are arranged in the Y direction, for example. The power module110are placed so that the output bus bars150are placed on the same side in the X direction. The housing220accommodates the different elements configuring the power module110. The housing220is configured by assembling multiple members. A typical example is a combination of a case and a cover. As the members configuring the housing220, only metal members, only resin members, or a combination of the metal member and the resin member can be used. The housing220has a substantially rectangular plane shape. The input terminal block230is a portion for electrically connecting the direct current power source2and the electric power conversion device5. Although not shown, the input terminal block230has a positive electrode terminal, a negative electrode, and a housing holding the terminals. The positive electrode terminal is connected to the wiring member configuring the wiring member configuring the VL line12L. The negative electrode terminal is connected to the wiring member configuring the N line13. The input terminal block230is placed in the vicinity of one of the four corners of the housing220. In a wall surface of the housing220, an opening220ais formed. The input terminal block230can be electrically connected to the direct current power source2via the opening220a. The output terminal block240is a portion for electrically connecting the motor generators3and4and the electric power conversion device5. The output terminal block240has the multiple bus bars241connected to the multiple power modules110configuring the inverters7and8and a housing242holding these bus bars241. The bus bar241may be referred to as an output terminal. The bus bar241configures at least a part of the output wiring15. The output terminal block240is placed adjacent to one lateral wall, in the Y direction, of the housing220. In this lateral wall, an opening220bis formed. The output terminal block240can be electrically connected to the three-phase windings of the motor generators3and4via the opening220b. The bus bar241protrudes from the housing242to the opposite side to the lateral wall having the opening220b. The protrusion portion of the bus bar241has a substantially L-shape in the ZX plane, as shown inFIG.46. Each bus bar241is connected to the output bus bar150of the corresponding power module110in the connection manner. The reactor module250configures the reactors R1and R2of the converter6. The reactor module250and the capacitor module260are arranged in the Y direction. The reactor module250is placed adjacent to, for example, the input terminal block230in the Y direction. In the X direction, the power module110is placed between the reactor module250and the capacitor module260, and the output terminal block240. The reactor module250has multiple terminals (not shown). The reactor module250is electrically connected to the wiring member configuring the VL line12L via one terminal. The reactor module250is electrically connected to the output bus bar150of the power module110configuring the converter6via a bus bar251configuring another terminal and the boost wiring14. The connection manner between the bus bar251and the output bus bar150is similar to that between the bus bar241and the output bus bar150. The bus bar251has a terminal portion251aand an extension portion251b. The terminal portion251ais connected to the terminal portion156aof the output bus bar150. The extension portion251bhas a bent portion in the middle of the path. A portion from the bent portion to the terminal portion251aextends in the Z direction. The bus bars241and251correspond to the conductive members of the electric power conversion device5. The capacitor module260configures the smoothing capacitor C2and the filter capacitor C3. The capacitor module260accommodates, for example, a film capacitor in the case. In the X direction, the reactor module250is placed between the capacitor module260and the input terminal block230. In the Y direction, the power module110is placed between the capacitor module260and the output terminal block240. The capacitor module260has multiple terminals (not shown). The capacitor module260has terminals corresponding to the VH line12H, the VL line12L, and the N line13. The capacitor module260is electrically connected to the wiring member configuring the VH line12H via one terminal. The capacitor module260is electrically connected to the wiring member configuring the VL line12L via another terminal. The capacitor module260is electrically connected to the wiring member configuring the N line13via another terminal. In such a manner, in the present embodiment, the output bus bar150of the power module110is connected to the detected portion155, and has the bent portion156extending in a direction different from the detected portion155. Accordingly, as compared with a configuration excluding the bent portion, that is, a configuration extending from the detection portion in the X direction, it may be possible to prevent the size of the power module110, thus, the electric power conversion device5from increasing. FIG.48is a cross-sectional view showing a reference example of the power module. InFIG.48, the elements identical or related to the present embodiment are denoted by adding “r” to the tails of the reference numerals in the present embodiment. InFIG.48, a current flow at a certain time is indicated by a broken arrow. A magnetic field due to the current is indicated by a dashed dotted line. Although the magnetic field is generated concentrically around the current, inFIG.48, the concentric circles are shifted for easy understanding. Also in a power module110rshown inFIG.48, an output bus bar150rhas a detected portion155rand a bent portion156r. A tip of the bent portion156ris connected to a bus bar241r. The bus bar241rextends in the Z direction and in a direction away from the detected portion155. Accordingly, not only a magnetic field due to the current flowing through the detected portion155rbut also a current flowing through the bent portion156ract on an electromagnetic conversion element (not shown) of a current sensor200. Therefore, the current detection accuracy by the current sensor200may be reduced. On the other hand, in the present embodiment, the bent portion156extends from the terminal portion156atoward the detected portion155together with the terminal portion156aconnected to the bus bar241, and has the facing portion156bfacing the bus bar241together with the terminal portion156a. As shown inFIG.49, in a state where the terminal portion156ais connected to the terminal portion241a, the terminal portion156aand the facing portion156b, and the terminal portion241aand a part of the extension portion241bhave a folded structure. Therefore, the currents flow in the substantially opposite directions to each other. Accordingly, the magnetic field due to the current flowing through the terminal portion156aand the facing portion156bcan be canceled by the magnetic field due to the current flowing through the terminal portion241aand a part of the extension portion241b. As the result, it may be possible to prevent the magnetic field due to the current flowing to the bent portion156from acting on the current sensor200while having the bent portion156. Accordingly, the current sensor200can accurately detect the current flowing through the detected portion155. Although the bus bar241has been described, the similar applies to the bus bar251. InFIG.49, similarly toFIG.48, the current is indicated by a broken arrow, and the magnetic field is indicated by a dashed dotted line. As decrease above, according to the power module110and the electric power conversion device5of the present embodiment, it may be possible to prevent the size from increasing and prevent the reduction in the current detection accuracy that may be caused by the prevention of the increase. The facing portion156bmay be placed at at least a part of portion other than the terminal portion156ain the bent portion156. For example, an example shown inFIG.50may be employed. InFIG.50, only a part of the bent portion156other than the terminal portion156ais the facing portion156b. The output bus bar150and the bus bar241have different extension lengths including the corresponding terminal portions156aand241ain the Z direction. Specifically, the extension lengths of the facing portion156band the terminal portion156aare longer than the extension lengths of the extension portion241bcloser to the terminal portion241athan the bent portion241b1and the terminal portion241a. Also in the configuration shown inFIG.50, at the facing portion between the output bus bar150and the bus bar241, the magnetic fields can be canceled. Thereby, as compared with the configuration shown inFIG.48, it may be possible to prevent the reduction in the current detection accuracy by the current sensor200. However, a part of the bent portion156does not face the Z direction extension portion of the bus bar241. Therefore, it may be conceivable that the magnetic field by the current flowing through the non-facing portion of the bent portion156acts on the current sensor200. Accordingly, as shown inFIG.46andFIG.49, it is preferable that the output bus bar150and the bus bar241have the substantially same extension length including the corresponding terminal portions156aand241ain the Z direction. Specifically, it is preferable that the extension length of the extension portion241bcloser to the terminal portion241athan the bent portion241b1and the terminal portion241ais substantially equal to the extension length of the facing portion156band the terminal portion156a. According to this, the Z direction extension portions of the output bus bar150and the bus bar241substantially entirely face each other. There is not the non-facing portion or is the slight non-facing portion. Accordingly, it may be possible to effectively prevent the magnetic field other than the detection target from acting on the current sensor200. Thereby, it may be possible to further improve the current detection accuracy. FIG.50has shown the bus bar241. However, the similar configuration can apply to the bus bar251.FIG.50has shown the example in which the Z direction extension portion of the output bus bar150(bent portion156) is longer than that of the bus bar241. However, it is not limited to this. The portion closer to the terminal portion241athan the bent portion241b1may have the extension length longer than the extension length of the bent portion156. As the example to which the power module110is applied, the electric power conversion device5has been shown. However, it is not limited to this. That is, the different member connected to the output bus bar150is not limited to the elements configuring the electric power conversion device5. The different member is an element different from the power module110in a device including the power module110. For example, in an example shown inFIG.51, the power module110is applied to a rotary electric machine unit290. The rotary electric machine unit290includes, for example, three power modules110configuring the motor generator3, the smoothing capacitor C2, and the inverter. The rotary electric machine unit290includes the converter6and the filter capacitor C3. The smoothing capacitor C2and the power module110configure the electric power conversion device, and this electric power conversion device is integrated with the motor generator3. The power module110has the structure shown inFIG.46. The motor generator3includes a housing300accommodating a stator (not shown) and a rotor (not shown) and a cover301. At an outer surface of the housing300, a recess300ais formed. The recess300aaccommodates the smoothing capacitor C2and the power module110. In a state where the smoothing capacitor C2and the power module110are accommodated, the recess300ais closed by the cover301. A reference number300bindicates, in the housing300, a tubular portion placed around the end of a rotation shaft of the motor generator3. In the present embodiment, the smoothing capacitor C2is separated for each phase. The recess300ais formed for each phase. One recess300aof the housing300accommodates the smoothing capacitor C2and the power module110configuring the upper-lower arm circuit10of the U phase. Another recess300aaccommodates the smoothing capacitor C2and the power module110configuring the upper-lower arm circuit10of the V phase. Another recess300aaccommodates the smoothing capacitor C2and the power module110configuring the upper-lower arm circuit10of the W phase. InFIG.51, in order to show a structure in the recess300a, for convenience, a dashed dotted line indicates the cover301corresponding to the power module110of the V phase placed in the center. For the remaining two phases, a solid line indicates the cover301. The motor generator3includes a wiring member electrically connecting a wiring of the stator accommodated in the housing and the output bus bar150of the power module110. This wiring member includes a bus bar302. The bus bar302is held by the housing300, and one end protrudes into the recess300a. In the recess300a, the bus bar302is connected to the output bus bar150. The connection manner between the output bus bar150of the power module110and the bus bar302is same as the connection manner between the output bus bar150and the bus bars241and251. The bus bar302protrudes, for example, from the lateral surface of the recess300ainto the recess300a. The protrusion portion of the bus bar302has a substantially L-shape. Similarly to the bus bar241, the bus bar302has a terminal portion302aplaced at the end and an extension portion302bextending from the terminal portion302a. The terminal portion302ais connected to the terminal portion156aof the output bus bar150. The extension portion302bhas a bent portion (not shown), a portion closer to the terminal portion302athan the bent portion extends in one direction, and the extension portion302bfaces the terminal portion156aand the facing portion156b. Accordingly, by canceling the magnetic fields, it may be possible to prevent the reduction in the current detection accuracy while preventing the increase in the size. Similarly toFIG.46, the extension length of the extension portion302band the terminal portion302acloser to the terminal portion302athan the bent portion in the bus bar302is substantially equal to the extension length of the facing portion156band the terminal portion156a, and thereby it may be possible to further improve the current detection accuracy. Other Embodiment In the electric power conversion device5, a part of the power module110may be inserted into a flow path of an external cooler that is different from the cooler120and placed outside the power module110, and may be immersed in the refrigerant. For example, in the Y direction, only a part of the power module110may be immersed. Specifically, a placement part from the lateral surface184to the semiconductor device20and the capacitor C1may be immersed, and the lateral surface183may not be immersed. Then, the output bus bar150may be routed in the protective member180so as to protrude from the lateral surface183. The example in which the electric power conversion device5configures the multi-phase converter6, the inverters7and8for the motor generators3and4, the smoothing capacitor C2, and the filter capacitor C3has been shown. However, it is not limited to this. For example, the converter6is not limited to the multi-converter, and may be a single phase converter. The example in which the capacitor C1, the heat exchange portion123of the cooler120, the semiconductor device20are arranged in the Z direction has been shown. However, it is not limited to this. The capacitor C1may be placed in the vicinity of the semiconductor device20. For example, as shown inFIG.45, in the X direction that is a direction in which the semiconductor devices20U and20L are arranged, the capacitor C1and the semiconductor device20may be arranged. The capacitor C1has the positive electrode terminal close to one surface in the Z direction, and the negative electrode close to a surface opposite to the one surface. The P bus bar130includes the connection portion131, the common wiring portion132, the parallel wiring portion133, and the connection portion137. The common wiring portion132also serves as the connection portion131. The parallel wiring portion133extends from the common wiring portion132along the front surface of the capacitor C1in the Z direction. The parallel wiring portion133is bent in the middle of the capacitor C1in the Z direction, and extends in the X direction and in a direction away from the capacitor C1. The parallel wiring portion133has a portion extending from one end of the X direction extension portion in the Y direction to the main terminals70C and70E in the Z direction. The connection portion137is placed at the tip of the parallel wiring portion133. The N bus bar140has the similar structure to the P bus bar130. The N bus bar140includes the connection portion141, the common wiring portion142, the parallel wiring portion143, and the connection portion147. The common wiring portion142also serves as the connection portion141. The parallel wiring portion143extends from the common wiring portion142along the front surface of the capacitor C1in the Z direction. The parallel wiring portion133is bent in the middle of the capacitor C1in the Z direction, and extends in the X direction and in a direction away from the capacitor C1. The parallel wiring portion143has a portion from one end of the X direction extension portion in the Y direction toward the main terminals70C and70E in the Z direction. The connection portion147is placed at the tip of the parallel wiring portion143. The X direction extension portions of the parallel wiring portions133and143are placed to face each other. The Z direction extension portions of the parallel wiring portions133and143are connected to the connection portions137and147, and face each other. FIG.45also shows the semiconductor devices20(20U,20L), the P bus bar130, the N bus bar140, and the capacitor C1as elements configuring the power module110. The power module110may include at least one of the cooler120, the output bus bar150, the drive substrate160, or the protective member180in addition to the elements. In the above, the embodiments, the configurations, the aspects of the power module and the electric power conversion device according to the present disclosure are exemplified. The present disclosure is not limited to the above-described embodiments, each configuration and each aspect related to the present disclosure. For example, embodiments, configurations, and aspects obtained from an appropriate combination of technical elements disclosed in different embodiments, configurations, and aspects are also included within the scope of the embodiments, configurations, and aspects of the present disclosure. | 188,670 |
11942870 | The drawings have not necessarily been drawn to scale. Similarly, some components and/or operations may be separated into different blocks or combined into a single block for the purposes of discussion of some of the embodiments of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular embodiments described. On the contrary, the technology is intended to cover all modifications, equivalents, and alternatives falling within the scope of the technology as defined by the appended claims. DETAILED DESCRIPTION Example implementations are provided so that this disclosure will be thorough, and will fully convey the scope to persons skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of implementations of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example implementations may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example implementations, well-known processes, well-known device structures, and well-known technologies are not described in detail. The terminology used herein is for the purpose of describing particular example implementations only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. Although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the example embodiments. Spatially relative terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In an embodiment, a power supply receives AC power and generates a DC output voltage. The power supply may be divided into a primary section that converts AC power to a relatively high DC voltage. A secondary section converts this relatively high DC voltage into a well regulated lower DC voltage. In an embodiment, the current and/or power supplied by the primary to the secondary side is used by the secondary side in a closed-loop feedback system to limit the current drawn by the secondary side to a configurable value. FIG.1is a block diagram illustrating a power supply system. InFIG.1, system100comprises external system controller110, power supply unit120, and load150. Power supply unit120includes closed-loop input power (CLIP) circuitry122. CLIP122includes power limit storage123. External system controller110is operatively coupled to PSU120. External system controller110is operatively coupled to PSU120to provide PSU120with at least a input power limit115that is stored by power limit storage123. PSU120is operatively coupled to load150. PSU120is operatively coupled to load150to provide load150with a variable amount of output current125at a regulated DC voltage. PSU120also receives a varying indicator of measured input power116. It should be understood that for the purposes of this disclosure, because power supplies are supplied with a constant input voltage, but draw a varying amounts of input current depending upon load, input current and input power can be used interchangeably to refer to input power and/or input current. For the same reasons, input current limit and input power limit can be used interchangeably to refer to input power limits and/or input current limits. Likewise, because power supplies provide loads with a constant output voltage, but supply a varying amount of output current to that load, output current and output power can be used interchangeably to refer to output power and/or output current. input current limit and input power limit can be used interchangeably to refer to input power limits and/or input current limits. In an embodiment, the amount of output current125supplied to load150affects the amount of input current drawn by PSU120. Because the input current drawn by PSU120is indicated by measured input power116, CLIP can rely on a feedback loop to limit the input power to PSU120. This feedback loop includes a comparison of measured input power116to the input power limit115that is stored by power limit storage123, and the output current125. In other words, based on the input power limit115stored by power limit storage123and the measured input power116, CLIP adjusts the amount of current supplied to load150. This in-turn affects the measured input power completing the feedback loop. CLIP adjusts the amount of current supplied to load150to limit the measured input power116to at or below the amount of current indicated by power limit storage123. FIG.2is a block diagram illustrating a closed-loop input current/power limited power supply system. InFIG.2, system200comprises power controller210, power supply unit220, and AC power source228. Power supply unit220includes primary side circuitry221and secondary side circuitry230. Secondary side circuitry230includes compare (subtract)231, error indicator232, proportional-integral-derivative (PID)233, adjustment indicator234, reference current235, scaled current reference indicator236, scaler237, and regulator240. Regulator240includes compare (subtract)245, error indicator246, pulse-width modulation (PWM) controller241, plant242, regulated output243, and output current indicator244. AC power source228supplies varying power (varying current at a fixed voltage) to primary side circuitry221according to the needs of PSU220. Primary side circuitry221supplies varying current222(again, varying current at a fixed voltage) to plant242. Primary side circuitry221also provides a varying input current indicator225to compare231. Varying input current indicator225conveys information about the amount of current being supplied by power source228to primary side circuitry221. Compare231also receives input current limit215. Compare231subtracts input current indicator225from current limit indicator215to generate error indicator232. Thus, error indicator232is a measure of how close input current indicator225is to meeting or exceeding current limit indicator215. PID233receives error indicator232and outputs adjustment indicator234. Adjustment indicator234may be viewed as a percentage of full current capacity that regulator240is allowed to supply. Adjustment indicator234may vary between indications of from 0% to 100% (as with many feedback control systems.) Adjustment indicator234indicates 100% as long as error indicator232is positive (i.e., input current indicator225is less than input current limit215.) When error indicator232is negative (i.e., input current indicator225is greater than input current limit215) PID233fractionally reduces adjustment indicator234to decrease the amount of current output by regulator240. Scaler237effectively multiplies reference current235by adjustment indicator234and outputs scaled current reference indicator236. Thus, scaled current reference indicator236effectively sets the maximum current to be output by regulator240as a percentage of reference current235. In other words, when adjustment indicator234is indicating 100%, the maximum current allowed to be output by regulator240is reference current235. When adjustment indicator234is indicating 50%, the maximum current allowed to be output by regulator240is 50% of reference current235, and so on. Regulator240receives scaled current reference indicator236. Compare245receives scaled current reference indicator236and an output current indicator244provided by plant242. Compare245subtracts output current indicator244from scaled current reference indicator236to generate error indicator246. Thus, error indicator246is a measure of how close output current indicator244is to meeting or scaled current reference indicator236. PWM controller241receives error indicator246and controls plant242to provide a limited current on regulated output243according to error indicator246. Thus, it should be understood that compare245, PWM controller241, and plant242are parts of a secondary side feedback loop that limits the current output by regulated output243to a target value. It should also be understood that because plant242of regulator240receives current222from primary side circuitry221, regulator240, primary side circuitry221, compare231, PID233, and scaler237are part of a primary side feedback loop that limits input current from power source228. FIG.3is a flowchart illustrating a method of changing a power supply power limit. One or more steps illustrated inFIG.3may be performed by, for example, system100, system200, and/or their components. A command is received to change an input power limit (302). For example, PSU120may receive a command from external system controller110to change the input power limit115stored in power limit storage123. The actual input power is read (304). For example, CLIP122may receive measured input power116. Closed-loop control of the input power is resumed (306). For example, CLIP122may resume closed-loop control using the new input power limit115stored in power limit storage123and the measured input power116. FIG.4is a block diagram illustrating a system. coupled to a power supply. InFIG.4, system400includes AC power source428, primary side circuitry420, secondary side circuitry430, and load system450. Load system450include load451and system control410. Primary side circuitry420include primary controller421, AC-DC power converter429, and portion of DC-DC power converter440. Secondary side circuitry430includes the remaining portion of DC-DC power converter440, and secondary controller441. Primary side circuitry420and secondary side circuitry430are separated by isolation425. It should be understood that primary side circuitry420may be, include, or implement all or parts of primary side circuitry221. Secondary side circuitry430may be, include, or implement all or parts of secondary side circuitry230. Together, primary side circuitry420and secondary side circuitry430may be, include, or implement all or parts of CLIP122, PSU120, and/or PSU220. AC-DC power converter429receives AC power from AC power source428. AC-DC power converter429converts AC power from AC power source428to DC supply voltage Vbulk. Vbulkis provided to DC-DC power converter440. AC-DC power converter429is controlled by primary controller421. Primary controller421receives information about AC power source428(e.g., input current indicator). Primary controller421is operatively coupled to secondary controller441and system controller410. Primary controller421is operatively coupled to system controller410to transmit or receive commands and/or other information (e.g., input current limit indicator) used to control AC-DC power converter429. DC-DC power converter440receives DC supply voltage Vbulk. DC-DC power converter440converts DC power from DC supply voltage Vbulkto DC supply voltage Vout. Voutis provided to load system450and load451, in particular. Secondary controller441is operatively coupled to primary controller421and system controller410. Secondary controller441is operatively coupled to system controller410to transmit or receive commands and/or other information (e.g., output current limit indicator) used to control DC-DC power converter440. Secondary controller441is operatively coupled to primary controller421to transmit or receive commands and/or other information (e.g., input current indicator) used to control DC-DC power converter440. FIG.5is a flowchart illustrating a method of changing a power supply power limit. One or more steps illustrated inFIG.5may be performed by, for example, system100, system200, system400, and/or their components. An output current adjustment is generated based on an input power and an input power limit (502). For example, scaled current reference indicator236may be generated by compare231, PID233, and scaler237based on input current limit215and input current indicator225. An output voltage is regulated based on an output current and the output current adjustment (504). For example, regulator240may regulate output243based on scaled current reference indicator236and output current indicator244. FIG.6is a flowchart illustrating a method of changing a power supply power limit. One or more steps illustrated inFIG.6may be performed by, for example, system100, system200, system400, and/or their components. An output voltage is regulated using a closed-loop current feedback (602). For example, regulator240may regulate output243based on a closed feedback loop that includes output current indicator244. An error adjustment signal is generated based on a primary side input current and a target current limit (604). For example, scaled current reference indicator236may be generated by compare231, PID233, and scaler237based on input current limit215and input current indicator225. The error adjustment signal is used to limit an output current of the output voltage (606). For example, regulator240may, based on scaled current reference indicator236, limit the current provided by output243. FIG.7is a block diagram illustrating a computer system. In an embodiment, computer system700and/or its components include circuits, software, and/or data that implement, or are used to implement, the methods, systems and/or devices illustrated in the Figures, the corresponding discussions of the Figures, and/or are otherwise taught herein. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system100, system200, system400, and/or their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Data formats in which such descriptions may be implemented are stored on a non-transitory computer readable medium include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Physical files may be implemented on non-transitory machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½-inch floppy media, CDs, DVDs, hard disk drives, solid-state disk drives, solid-state memory, flash drives, and so on. Alternatively, or in addition, the functionally described herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), multi-core processors, graphics processing units (GPUs), etc. FIG.7illustrates a block diagram of an example computer system. Computer system700includes communication interface720, processing system730, storage system740, and user interface760. Processing system730is operatively coupled to storage system740. Storage system740stores software750and data770. Processing system730is operatively coupled to communication interface720and user interface760. Computer system700may comprise a programmed general-purpose computer. Computer system700may include a microprocessor. Computer system700may comprise programmable or special purpose circuitry. Computer system700may be distributed among multiple devices, processors, storage, and/or interfaces that together comprise elements720-770. Communication interface720may comprise a network interface, modem, port, bus, link, transceiver, or other communication device. Communication interface720may be distributed among multiple communication devices. Processing system730may comprise a microprocessor, microcontroller, logic circuit, or other processing device. Processing system730may be distributed among multiple processing devices. User interface760may comprise a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. User interface760may be distributed among multiple interface devices. Storage system740may comprise a disk, tape, integrated circuit, RAM, ROM, EEPROM, flash memory, network storage, server, or other memory function. Storage system740may include computer readable medium. Storage system740may be distributed among multiple memory devices. Processing system730retrieves and executes software750from storage system740. Processing system730may retrieve and store data770. Processing system730may also retrieve and store data via communication interface720. Processing system750may create or modify software750or data770to achieve a tangible result. Processing system may control communication interface720or user interface760to achieve a tangible result. Processing system730may retrieve and execute remotely stored software via communication interface720. Software750and remotely stored software may comprise an operating system, utilities, drivers, networking software, and other software typically executed by a computer system. Software750may comprise an application program, applet, firmware, or other form of machine-readable processing instructions typically executed by a computer system. When executed by processing system730, software750or remotely stored software may direct computer system700to operate as described herein. Implementations discussed herein include, but are not limited to, the following examples: Example 1: A method, comprising: generating an output current adjustment based on an input power and an input power limit; and, regulating an output voltage based on an output current and the output current adjustment. Example 2: The method of claim1, wherein the output current adjustment is further based on a constant current reference. Example 3: The method of claim2, wherein the output current adjustment is based on a difference between the input power and the input power limit. Example 4: The method of claim3, wherein the output current adjustment decreases the output current when the input power exceeds the input power limit. Example 5: The method of claim4, wherein the output current adjustment does not affect the output current when the input power is less than the input power limit. Example 6: The method of claim5, wherein the input power limit is configurable. Example 7: The method of claim6, wherein the input power is received from a primary side power supply. Example 8: A method of regulating a secondary side output current, comprising: regulating an output voltage using closed-loop current feedback; generating an error adjustment signal based on a primary side input current and a target current limit; and, using the error adjustment signal to limit an output current of the output voltage. Example 9: The method of claim8, wherein the error adjustment signal is further based on a constant current reference. Example 10: The method of claim9, wherein the error adjustment signal is based on a difference between the primary side input power and the target current limit. Example 11: The method of claim10, wherein the error adjustment signal causes the closed-loop current feedback to decrease the output current when the primary side input power exceeds the target current limit. Example 12: The method of claim11, wherein the error adjustment signal does not affect the output current when the primary side input power is less than the target current limit. Example 13: The method of claim12, wherein the target current limit is configurable. Example 14: The method of claim13, wherein the closed-loop current feedback includes a pulse-width modulation controller. Example 15: A power supply system, comprising: a secondary output voltage regulator that uses a closed-loop current feedback signal to produce an output voltage; an error adjustment signal that is based on a primary side input current and a target current limit; and, a current feedback combiner to, based on the error adjustment signal, change the closed-loop feedback signal to limit an output current. Example 16: The power supply system of claim15, wherein the secondary output voltage regulator includes a pulse-width modulation controller. Example 17: The power supply system of claim16, further comprising: a constant current reference. Example 18: The power supply system of claim17, further comprising: a constant current reference modulator to, based on the primary side input current and the target current limit, scale the constant current reference to produce the error adjustment signal. Example 19: The power supply system of claim18, wherein the target current limit is configurable by an external system. Example 20: The power supply system of claim18, further comprising: proportional-integral-derivative feedback to scale the constant current reference to produce the error adjustment signal. As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method, or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The included descriptions and figures depict specific embodiments to teach those skilled in the art how to make and use the best mode. For the purpose of teaching inventive principles, some conventional aspects have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the disclosure. Those skilled in the art will also appreciate that the features described above may be combined in various ways to form multiple embodiments. As a result, the invention is not limited to the specific embodiments described above, but only by the claims and their equivalents. | 24,928 |
11942871 | DETAILED DESCRIPTION The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of various embodiments of the techniques described herein for performing startup of an alternating current to direct current (AC-DC) converter using a self-biased gate driver architecture within a primary controller of the AC-DC converter. It will be apparent to one skilled in the art, however, that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in a simple block diagram format in order to avoid unnecessarily obscuring the techniques described herein. Thus, the specific details set forth hereinafter are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present disclosure. Reference in the description to “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” means that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the disclosure. Further, the appearances of the phrases “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” in various places in the description do not necessarily all refer to the same embodiment(s). The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in enough detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter but rather to enable one skilled in the art to practice, make, and/or use the subject matter. Described herein are various embodiments of techniques for performing startup of an AC-DC converter using a self-biased gate driver architecture within a primary controller of the AC-DC converter. For example, a primary field effect transistor (FET) can be coupled between a primary winding on a primary side of the AC-DC converter and the primary side controller. A gate driver, also of the primary side controller, is coupled to a gate of the primary FET to turn on, in response to a signal received from a startup controller of the primary side controller, the primary FET at startup when the secondary side is not active. Thus, the startup controller and the gate driver work together to initiate the AC-DC converter, along with a number of other functions performed by the primary side controller. In conventional primary side controllers with a discharge circuit (e.g., an X-cap discharge circuit), gate drivers, internal regulator powers the gate drive circuit with an external capacitor used to store charge. The charge is used to power the gate drivers when external line voltage source is unable to provide power when voltage goes below undervoltage threshold. Gate drive circuit is initiated during the first positive going ramp of AC input voltage. For a traditional primary side controller, startup happens in less than 4 ms. For nominal AC input, the full wave rectified voltage period of 120 Hz or 100 Hz signal is 10 ms or 8 ms respectively. For a secondary side controller, it can take the secondary side controller in the order of 30˜50 ms for a proper startup. Secondary side controller includes an MCU and/or any smart peripherals or auxiliary circuits. During this time of 30˜50 ms, the rectified input AC voltage received via the high voltage (HV) pin173can fall below the threshold voltage. When the rectified input voltage (e.g., a rectified AC voltage) at HV pin173drops below threshold voltage, primary side controller150is not powered using HV pin173. Input voltage can be below threshold voltage for 3˜4 ms. C3would need to be too large to store energy to supply primary side controller150for 3˜4 ms. Also, energy stored in C3needs to supply power to the primary side controller150for a total cumulative time of 30˜40 ms, time taken by secondary side controller102to boot up. Larger C3would also cause startup delay and take up board space. A better solution is to not switch during this period and only switch when input voltage exceeds threshold voltage. In another embodiment, during the period when there is no switching at startup, duty cycle is stalled and picks up from the previous saved state. During initial start-up, AC-DC converter goes through a soft start where duty cycle may start at 1% or 5% which is defined by the system. During startup duty cycle increases incrementally until it reaches a maximum duty cycle. This description is known as startup. If the duty cycle is allowed to increase incrementally when there is no GD172activity, the next time GD turns ON after a period of no switching will cause unneeded stress on primary switch116and Bridge rectifier110due to the sudden turn ON at an increased duty cycle. FIG.1is a schematic block diagram of an AC-DC converter100in which a primary side controller150reacts to a signals from a secondary side during startup according to various embodiments. In various embodiments, the AC-DC converter100is an apparatus or part of an electronic device that includes charging capability, such as, for example, laptop power supplies, a multi-outlet power strip, wall sockets with USB-PD type-C sockets, and the like. In some embodiments, the AC-DC converter100includes a transformer104having a primary winding (NP) on a primary side106electrically connected or coupled to an AC input, and a secondary winding (NS) on a secondary side108coupled to a DC output. Other devices that include AC-DC topologies, such as full-bridge converter, half-bridge converter, forward converter, and the like, are to be considered within the meaning of the term AC-DC converter as used herein. In various embodiments, on the primary side106, a rectifying circuit, such as a bridge rectifier110, and one or more input filters112,114, is coupled to a first terminal104aof the transformer104to rectify an AC input voltage and supply input power to the primary winding of the transformer104. The input filters can include a first input filter112having a capacitor (C1) coupled to or across an output of the rectifier110, and a second, RC filter114including a resistor or resistive element (R2) and a capacitor (C2) coupled in parallel between the first terminal104aof the transformer104and a cathode of a diode or rectifier (D2) having an anode coupled to a second terminal104bof the transformer. In some embodiments, the AC-DC converter100further includes a power switch (e.g., a field effect transistor (FET), a gallium nitride (GaN) switch, silicon carbide (SiC) switch, a bipolar junction transistor (BJT), and the like), such as a primary field effect transistor (FET)116having a first or drain node coupled to the second terminal104bof the transformer104, a second or gate node coupled to the primary side controller150, and a third or source node coupled to the primary side controller150and, through a current sensing element, such as a resistive element (RSENSE) to ground to sense a primary side current flowing through the primary winding when the primary FET116is closed or conducting. On the secondary side108, the AC-DC converter100includes a output capacitor121coupled between a third terminal104cof the transformer104and an electrical ground or ground terminal, and an filter capacitor120coupled between a source terminal of the FET136and an electrical ground provide a DC output voltage to an output interface or connector122. The output connector122can further be coupled to the secondary side controller102through a number of communication channels124to support various charging protocols. Suitable output connectors122can include those compatible with and supporting standard and proprietary charging protocols including Universal Serial Bus Power Delivery USB PD2.0 and USB PD3 with Programmable Power Supply (PPS), Qualcomm® Quick Charge, Samsung® AFC, and Apple® charging protocols. For example, the connector can include a Universal Serial Bus type C (USB-C) compatible connector where the AC-DC converter100is compliant with the USB PD protocol to provide a DC output voltage of about 3.3 VDC to about 21.5 VDC at an output current of about 0 to about 5000 milliamps (mA). In various embodiments, the AC-DC converter100further includes, on the secondary side108, a synchronous rectifier such as a synchronous rectifier (SR) FET126, coupled between a fourth terminal104dof the transformer104and the ground terminal of the DC output. The SR FET126includes a first or drain node coupled to the fourth terminal104dof the transformer104and the secondary side controller102to sense a voltage on the drain of the SR FET126; a second or gate node coupled to the secondary side controller to drive or control the SR FET126; and a third or source node coupled to the secondary side controller and the ground terminal of the DC output. The gate node of the SR FET126can be coupled to an SR-drive pin132of the secondary side controller102. Optionally, as in the embodiment shown, the secondary side further includes an additional or secondary switch136, such as a NFET, coupled between the third terminal104cof the transformer104and a positive DC output to enable the secondary side controller102to turn off the DC output to protect against over voltage and/or under voltage conditions. The secondary switch136includes a drain node coupled to a voltage bus (VBUS_IN) of the secondary side controller102; a gate node coupled to a voltage bus control pin (VBUS_CTRL)140to drive the additional secondary switch; and a source node coupled to a voltage bus (VBUS_OUT) and to the positive terminal of the DC output. (Not all pins illustrated.) In various embodiments, the AC-DC converter100further includes an isolation circuit or galvanic isolation barrier144to electrically isolate the secondary side108from the high AC input voltage present on the primary side106. The transformer104is generally considered part of the galvanic isolation barrier144. For example, the galvanic isolation barrier144can include various coils and magnetic core125of the transformer104, which functions as a flyback step-down transformer to provide power to the primary side controller150via an auxiliary winding coupled to aux (or “Aux”) pin (not illustrated). Further, the secondary side controller102may provide a signal to the primary side controller150from pins on the secondary side controller102, such as a feedback pin or pulse width modulation (PWM) drive pin (not illustrated). The galvanic isolation barrier144can further include additional circuits or elements between the secondary side controller102and the primary side controller150or the primary FET116. In corresponding embodiments, when the primary side power switch (e.g., the primary FET116) is closed, the primary side106of the flyback transformer is connected to the input voltage source. In this embodiment, the primary side106of the flyback transformer is coupled to the bridge rectifier110. As the primary current in the flyback transformer increases, energy is stored in the transformer magnetic field of the flyback transformer. The voltage induced in the secondary winding is negative and blocked by the secondary side power switch (e.g., the SR FET126). When the primary FET116(e.g., switch) is opened, the primary current decreases. The secondary voltage is positive, allowing current to flow from the flyback transformer. The energy stored in the transformer104is transferred to an output load, such as a USB charging device. The output capacitor120can be used to supply energy to the output load when the primary FET116is engaged. Thus, the flyback transformer, based on control of the primary FET116(e.g., a switch), can store energy and transfer the energy to the output of the AC-DC converter100. The primary side controller150can be implemented as an integrated circuit (IC) that is included as a component within the AC_DC converter100. The primary side controller150can be configured to receive a control (or pulse) signal138as one or more pulses, via a pulse transformer130, from the secondary side controller102across the galvanic isolation barrier144. The pulse signal138can be received through a PULSEIN pin. The primary side controller150can include a receiver151and a pulse width modulation (PWM) generator154to receive the pulse signal138from the secondary-side controller150. The primary side controller150can further include a free running oscillator156that supplies free running pulses to the PWM generator154, so that the PWM generator154can generate a free running PWM signal when the secondary side108is not active. The receiver151and PWM generator154can change the primary-side turn-on pulse based on output of the flyback transformer (e.g., error amplifier (EA) output) of the secondary side controller102. The primary-side turn-on pulse can be used to turn on the primary FET116as will be explained. In disclosed embodiments, the primary side controller150can also include a gate driver170and a startup controller160. The startup controller160is coupled to the receiver151, the PWM generator154, and the gate driver170to drive a gate of the primary FET116via a gate driver pin172. For example, the startup controller160can transmit a signal generated by the PWM generator154to the gate driver170to turn on the primary FET116. In this way, the gate driver170can turn on the primary FET116when the secondary side108is not active. In one embodiment, the primary side controller150, in order to apply the pulse signal138to the primary side FET116, is configured to receive a turn-on pulse from the secondary side controller102. The startup controller160can apply the turn-on pulse to the gate of the primary FET116via the gate driver170. The turn-on pulse causes the primary drain of the primary FET116to go low, e.g., a first voltage level corresponding to a first state or representing the digital value of one. Subsequently, the primary side controller150receives a turn-off pulse from the secondary side controller102. The startup controller160can apply the turn-off pulse to the gate of the primary FET116via the gate driver170. The turn-off pulse causes the primary drain of the primary FET116to go high, e.g., a second voltage level corresponding to a second state or representing the digital value of zero. With additional specificity and further reference to the primary side controller150, the PWM generator154, with the use of the free running oscillator156, supports a soft start of the primary side controller by gradually increasing the duty cycles from D/Cminto D/Cmaxusing an external capacitor (Cx) connected to a soft start (SS) pin. The duration for the free running PWM generation can be set by the external capacitor (Cx). An internal, e.g., 5 microampere, current source152can charge the external capacitor (Cx). The PWM generator154can set a maximum amplitude for the soft start, e.g., between 3 and 4 volts (e.g., 3.75 V). A frequency (FOSC) of the free running oscillator156can be set by an external resistor (Rx) of between 400 and 600 kilo-ohm (KΩ) (e.g., 500 KΩ) connected externally to a timing resistor (RT) pin158. A discharge switch155can discharge the external capacitor (Cx) after startup is complete. This cycle can be repeated with an auto-restart timer added between each soft start. Additionally, the primary side controller150can function to synchronize the secondary side pulses on the PULSEIN pin when the secondary side108becomes active. The PWM signal from the secondary side108can be coupled to the primary side using the pulse transformer130. The pulse transformer130can ensure proper frequency response and should have just an adequate Q-factor to avoid excessive overshoot in passing the PWM signal. The positive pulse from the pulse transformer130indicates a start of the PWM signal and a negative pulse from the pulse transformer130indicates a stop of the PWM. A set of comparators in the receiver151can be adapted to detect whether an incoming pulse is positive or negative. This information (positive or negative on the incoming pulse) can be sent to the startup controller160for proper timing in enabling the gate driver170to drive the primary FET116. In some embodiments, the AC-DC converter100includes a full wave AC rectified circuit135. The rectified circuit is coupled to the AC input and includes diode131, diode132, and capacitor133. The rectification circuit131may be coupled to the primary side controller150via pin175. In other embodiment, Primary side controller150includes a discharge circuit159that may cause capacitor133to be discharged internally in the primary side controller150. As discussed above, the primary side controller150may receive an AC-rectified voltage from the AC line which could be anywhere from 50Vac to 300Vac. In one embodiment, the startup controller160(and/or the primary side controller150) may turn on the primary FET116in response to receiving voltage on HV pin173exceeding the threshold voltage. The startup controller may operate the primary switch116at an initial duty cycle. For example, the initial duty cycle may be 1%, 5%, or some other appropriate value and incrementally increases with time. Turning on the primary switch116at the initial duty cycle (e.g., the primary FET116operates at the initial duty cycle) allows the primary side controller150to start supplying voltage to the secondary side controller102during the soft start. In one embodiment, the startup controller160(and/or the primary side controller150) may determine whether the pulse signal138has been received from the secondary side controller102via the PULSEIN pin. The pulse signals138may also be referred to as a control signal. The pulse signal138may be used by the primary side controller150to operate the primary FET116at a particular duty cycle, based on the pulse signal138, as discussed in more detail below. In some embodiments, the startup controller160may continually, periodically, etc., determine whether the pulse signal138has been received from the secondary side controller102via the PULSEIN pin. For example, the startup controller160may check the PULSEIN pin every 100 microseconds, every millisecond, or some other appropriate period of time, or may use an analog implementation. In one embodiment, the startup controller160(and/or the primary side controller150) may start a startup routine whereby to increase the duty cycle of the primary FET116when the pulse signal138has not been received from the secondary side controller102. Increasing the duty cycle of the primary FET116may allow more voltage to be provided to the secondary side108as the secondary side controller102continues to start (e.g., starts operation, initiates operation, boots, etc.). The secondary side controller102may take some time (e.g., 30 ms to 50 ms, or some other time) to fully boot up. In some embodiments, the startup controller160may increase the duty cycle of the primary FET116by a set amount. For example, the startup controller160may increase the duty cycle of the primary FET116by 1%, 5%, or some other appropriate amount. In other embodiments, the startup controller160may increase the duty cycle of the primary FET116based on configuration parameters, settings, a table of duty cycles, etc. In some embodiments, the startup controller160may continually, periodically, etc., increase the duty cycle of the primary FET116until the pulse signal138is received from the secondary side controller102. For example, each time the startup controller160checks for the pulse signal138and determines that the pulse signal138has not been received, the startup controller160may increase the duty cycle of the primary FET116. In one embodiment, the startup controller160may refrain, discontinue, stop, etc., increasing the duty cycle of the primary FET116if the pulse signal138is received from the secondary side controller102. For example, if the pulse signal138is received from the secondary side controller102via the PULSEIN pin, this may indicate that the secondary side controller102has completed startup, completed booting, is fully operational/functional, etc. When the secondary side controller102has completed starting up, the secondary side controller102may control the duty cycle for the primary FET116. The startup controller160may stop increasing or modifying the duty cycle of the primary FET116because the secondary side controller may now control the duty cycle of the primary FET116. In some embodiments, the startup controller160may set the duty cycle of the primary FET116based on the pulse signal138(e.g., a control signal) received from the secondary side controller102. For example, the pulse signal138may be a waveform or other signal that indicates when the primary FET116should be turned on and when the primary FET116should be turned off. The startup controller160may turn the primary FET116on and off based on the pulse signal138. In one embodiment, the startup controller160(and/or the primary side controller150) may determine whether a voltage of the AC-DC converter100is below an undervoltage threshold (UV). The undervoltage threshold may be the minimum voltage for operating the primary side controller150(e.g., the minimum voltage that allows the primary side controller120to continue startup and/or operation). For example, the undervoltage threshold may be 5V, 10V, 90V, or some other appropriate threshold voltage. In some embodiments, the startup controller160may continually, periodically, etc., determine whether the voltage of the AC-DC converter100is below the undervoltage threshold. For example, the startup controller150may determine whether the voltage of the AC-DC converter100is below the undervoltage threshold every 10 ms, 20 ms, etc. The startup controller160may use HV pin173to monitor the voltage of the AC-DC converter100. In other embodiment, the act of sensing rectified AC voltage to be below undervoltage threshold and stop switching is known as Brownout Protection. In one embodiment, the startup controller160(and/or the primary side controller150) may determine the state of the duty cycle of the primary FET116if the voltage of the AC-DC converter100is below the undervoltage threshold. For example, the startup controller160can analyze the duty cycle of the primary FET116to determine the current duty cycle. In another example, startup controller160may store the duty cycle for the primary FET116each time the startup controller160updates or increase the duty cycle. For example, if the startup controller160increases the duty cycle from 5% to 10%, then the current duty cycle would be 10%. The startup controller160may store some data or value indicating the 10% in a buffer, memory, cache, register, etc. In one embodiment, the startup controller160(and/or the primary side controller150) may also turn off the primary FET116if the voltage of the AC-DC converter100is below the undervoltage threshold. For example, the startup controller160may turn off the primary FET116to stop the flow of energy (e.g., the AC-DC current) to the secondary side controller102because the voltage is below the threshold at HV pin173. If the AC-DC converter100was allowed to switch, then the supply voltage on pin174would drop below threshold and may cause the primary side controller150to reset. In one embodiment, the startup controller160(and/or the primary side controller150) may determine if the voltage of the AC-DC converter100has increased to more than or equal to the undervoltage threshold. For example, the startup controller160may constantly, continually, periodically, etc., monitor the voltage of the AD-CD current, as discussed above. This may allow the startup controller160to determine if the voltage has increased to more than or equal to the undervoltage threshold. In one embodiment, the startup controller160may turn on the primary FET116at the last saved duty cycle when the AC voltage of the AC-DC converter100has increased to more than or equal to the undervoltage threshold. As discussed above, when the voltage of the AC-DC converter100goes below the undervoltage threshold, the startup controller160may store the current duty cycle of the primary FET116at the time when the voltage of the AC-DC converter100went below the undervoltage threshold (e.g., stores the current duty cycle). The startup controller160may turn on the primary FET if the AC voltage of the AC-DC converter100increases to more than or equal to the voltage threshold, at that last duty cycle (e.g., at the current duty cycle that was previously stored). In one embodiment, the startup controller160(and/or the primary side controller150) may determine whether the voltage of the AC-DC converter100is less than an undervoltage threshold for a period of time. For example, the primary side controller150may determine if the rectified AC voltage of the AC-DC converter100is lower than 90V, or some other appropriate voltage, for more than 60 ms, 100 ms, 120 ms, etc. If the AC voltage of the AC-DC converter100is lower than the undervoltage threshold for the period of time, the startup controller may cause the discharge circuit159to discharge the capacitor133. This will prevent injury to users of the AC-DC converter100. The startup controller160may use HV pin173to monitor the voltage of the AC-DC converter100. In one embodiment, the startup controller160(and/or the primary side controller150) may determine whether the voltage of the AC-DC converter100is greater than a overvoltage threshold. For example, the overvoltage threshold (OV) may be 400V, 500V, or some other appropriate voltage. If the voltage of the AC-DC converter100is greater than the overvoltage threshold, the startup controller will shut down, turn off, disable, etc., the primary FET116. This may also prevent damage to the power stage components like110,112, and RSENSE. In one embodiment, the startup controller160may stop determining whether the voltage of the AC-DC converter100is greater than the overvoltage threshold after the pulse signals138is received from the secondary side controller102. For example, after the secondary side controller102has started (e.g., started operation, started up, booted, etc.), the startup controller160may stop monitoring the voltage of the AC-DC converter100and may stop determining whether the voltage of the AC-DC converter100is greater than the overvoltage threshold. FIG.2is a graph illustrating an ideal startup voltage for V_REG at the SS pin138according to one embodiment. The soft startup means the voltage at the SS pin138slowly ramps up until hitting V_REG, which is maintained thereafter. After startup, including receipt of turn-on pulses from a secondary side controller150via the PULSEIN pin, the primary side controller150can instead be powered via the pin174by the transformer104. FIG.3a first graph300illustrating a voltage over time and a second graph350illustrating a duty cycle over time according to one embodiment. In graph300, the X-axis represents time and the Y-axis represents the rectified AC voltage of an AC-DC converter that is received by a primary side controller (e.g., primary side controller150illustrated inFIG.1). 0V (e.g., zero volts) and undervoltage threshold (UV) are indicated on the graph300. Thus, graph300illustrates different voltages (e.g., rectified AC voltages) of an AC-DC converter (that provides a current during startup) at different points in time. In graph350, the X-axis represents time and the Y-axis represents whether a FET (such as primary FET116illustrated inFIG.1) is on or off. Thus, graph350illustrates different duty cycles of the FET at different points in time. As illustrated, from time period T1-T2, the voltage is above the UV (e.g., an undervoltage threshold). During the time period T1-T2, the FET (e.g., switch) is operated at a first duty cycle and transitions to a second duty cycle that is larger than the first duty cycle (as indicated by the wider pulse). For example, the duty cycle may be periodically increased, as discussed above. At time period T2-T3, the voltage drops below undervoltage threshold and the FET is turned off. At time period T3-T4, the voltage goes above UV and the switch resumes operation at the second duty cycle. The FET is also transitioned to a third duty cycle at time period T3-T4. The third duty cycle is larger than the second duty cycle and the first duty cycle (as indicated by the wider pulse). At time period T4-T5, the voltage drops below UV and the FET is turned off. At time period T5-T6, the voltage goes above UV and the switch resumes operation at the third duty cycle. The duty cycle of the FET may be increased until control signals are received from the secondary side controller, as discussed above. The duty cycle of the FET may be increased until it hit the maximum duty and does an auto-restart (not illustrated) FIG.4is a flow diagram of a method400of operating an AC-DC converter that includes a primary side controller according to one embodiment. The method400can be performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), firmware, or a combination thereof. In one example embodiment, the method400is performed by processing logic included in primary side controller150(and/or in startup controller160therein) of the AC-DC controller100. The method400begins at block401where voltage, such as a rectified AC voltage, is received. For example, the AC-DC voltage may be received from a AC input. At block405, a FET (e.g., primary FET116illustrated inFIG.1) is turned on in response to receiving the AC-DC voltage at pin173. For example, the FET (or switch) may be turned on when the voltage exceeds an undervoltage threshold, as discussed above. The duty cycle of the FET may be set to an initial duty cycle. At block410, the duty cycle of the FET is increased. For example, the duty cycle may be increased by a set amount. At block415, the primary side controller determines whether a control signal has been received. For example, the primary side controller may determine whether a control signal has been received from a secondary side controller (e.g., secondary side controller102illustrated inFIG.1). If the control signal has been received, the primary side controller may set the duty cycle of the FET based on the control signal. For example, the control signal may indicate when to turn on the FET and when to turn off the FET and the method400may turn the FET on and off based on the control signal. If the control signal has not been received, the primary side controller may determine if the voltage of the AC-DC converter is less than an undervoltage threshold. If the voltage is not less than the undervoltage threshold, the primary side controller may increase the duty cycle of the FET at block410. If the voltage of the AC-DC converter is less than the undervoltage threshold, the primary side controller may turn off the FET and refrain from increasing the duty cycle at block425. The primary side controller may also store the current duty cycle so that the current duty cycle may be used when the FET is turned back on. At block430, the primary side controller may determine if the voltage is greater than or equal to the undervoltage threshold. For example, the primary side controller may determine if the voltage has increased up to or more than the undervoltage threshold. If the voltage is not greater than or equal to the undervoltage threshold, the primary side controller may proceed back to block430. If the voltage is greater than or equal to the undervoltage threshold, the primary side controller may turn on the FET at block440. As discussed above, the duty cycle of the FET may be set to the last duty cycle that was stored, recorded, etc., at block425. In the above description, some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on analog signals and/or digital signals or data bits within a non-transitory storage medium. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “receiving,” “communicating,” “modifying,” “measuring,” “determining,” “detecting,” “sending,” “comparing,” “maintaining,” “switching,” “controlling,” or the like, refer to the actions and processes of an integrated circuit (IC) controller, or similar electronic device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the controller's registers and memories into other data similarly represented as physical quantities within the controller memories or registers or other such information non-transitory storage medium. The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example’ or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an embodiment” or “one embodiment” throughout is not intended to mean the same embodiment or embodiment unless described as such. Embodiments descried herein may also relate to an apparatus (e.g., such as an AC-DC converter) for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise firmware or hardware logic selectively activated or reconfigured by the apparatus. Such firmware may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flash memory, or any type of media suitable for storing electronic instructions. The term “computer-readable storage medium” should be taken to include a single medium or multiple media that store one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The above description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 37,700 |
11942872 | DETAILED DESCRIPTION In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the attached drawings in the embodiments of the present application. Obviously, the embodiments described are only part but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor belong to the scope claimed in the present application. The multi-phase resonant circuit is a basic power unit commonly used at present. However, due to the error of electrical parameters of resonant elements in the multi-phase resonant circuit, the output currents of different phase resonant circuits in the multi-phase resonant circuit are often uneven, and switches and other elements in the multi-phase resonant circuit may be damaged due to overheating and other abnormalities. Please refer toFIG.1, which is a schematic view of the circuit structure of a multi-path resonant circuit provided according to an embodiment of the present application. As shown inFIG.1, the multi-path resonant circuit comprises at least two parallel N-phase resonant circuits, where N is an integer greater than or equal to 3. That is, the at least two N-phase resonant circuits are connected in parallel, and the number of phases N of each resonant circuit is an integer greater than or equal to 3. InFIG.1, two parallel N-phase resonant circuits are taken as an example. That is, the at least two parallel N-phase resonant circuits comprise a first N-phase resonant circuit10and a second N-phase resonant circuit20, and the first N-phase resonant circuit10and the second N-phase resonant circuit20are connected in parallel. A first resonant inductor in any phase resonant circuit of the first N-phase resonant circuit10is coupled with a second resonant inductor in any phase resonant circuit of the second N-phase resonant circuit20. Specifically, the first N-phase resonant circuit10comprises a first phase resonant circuit A1, a second phase resonant circuit A2, . . . , and a Nth phase resonant circuit AN, and the second N-phase resonant circuit20comprises a first phase resonant circuit B1, a second phase resonant circuit B2, . . . , and a Nth phase resonant circuit BN. A resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10serves as the first resonant inductor, and a resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20serves as the second resonant inductor, so that the resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10is coupled with the resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20to realize current sharing between the output current of the Nth phase resonant circuit AN of the first N-phase resonant circuit10and the output current of the first phase resonant circuit B1of the second N-phase resonant circuit20. Meanwhile, when N≥3, usually respective phase resonant circuits in the first N-phase resonant circuit10can achieve automatic current sharing, and respective phase resonant circuits in the second N-phase resonant circuit20can also achieve automatic current sharing. That is, the output currents of the first phase resonant circuit A1, the second phase resonant circuit A2, . . . , and the Nth phase resonant circuit AN can achieve automatic current sharing, i.e., the output currents of the first phase resonant circuit A1, the second phase resonant circuit A2, . . . , and the Nth phase resonant circuit AN are substantially equal. The output currents of the first phase resonant circuit B1, the second phase resonant circuit B2, . . . , and the Nth phase resonant circuit BN can also achieve automatic current sharing, i.e., the output currents of the first phase resonant circuit B1, the second phase resonant circuit B2, . . . , and the Nth phase resonant circuit BN are also substantially equal. Then, when the output current of the Nth phase resonant circuit AN of the first N-phase resonant circuit10is substantially equal to the output current of the first phase resonant circuit B1of the second N-phase resonant circuit20, both the output currents of the first N-phase resonant circuit and the second N-phase resonant circuit achieve current sharing, i.e., the output currents of the first phase resonant circuit A1, the second phase resonant circuit A2, . . . , and the Nth phase resonant circuit AN as well as the output currents of the first phase resonant circuit B1, the second phase resonant circuit B2, . . . , and the Nth phase resonant circuit BN are substantially equal. At this point, it is possible to reduce the probability that switches and other elements are damaged due to uneven output current. As shall be appreciated, in this embodiment, the resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10is coupled with the resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20as an example. In other embodiments, other two resonant inductors may be coupled. For example, the resonant inductor LA1of the first phase resonant circuit A1of the first N-phase resonant circuit10is coupled with the resonant inductor LB2of the second phase resonant circuit B2of the second N-phase resonant circuit20. At this point, the resonant inductor LA1is the first resonant inductor and the resonant inductor LB1is the second resonant inductor. For another example, a resonant inductor LA2of the second phase resonant circuit A2of the first N-phase resonant circuit10is coupled with a resonant inductor LB2of the second phase resonant circuit B2of the second N-phase resonant circuit20. At this point, the resonant inductor LA2is the first resonant inductor and the resonant inductor LB1is the second resonant inductor. In addition, in this embodiment, the first N-phase resonant circuit10and the second N-phase resonant circuit20are coupled only by one respective resonant inductor, so the structure is simpler and easy to expand. Furthermore, the complexity of control strategy can be reduced to avoid oscillation and instability. In an embodiment, if N is an even number, then the resonant inductors in the first N-phase resonant circuit may be coupled with the resonant inductors in the second N-phase resonant circuit in one-to-one correspondence. Taking the structure shown inFIG.1as an example, specifically, on the premise that the resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10is coupled with the resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20, the resonant inductor LA1of the first phase resonant circuit A1of the first N-phase resonant circuit10is coupled with the resonant inductor LB2of the second phase resonant circuit B2of the second N-phase resonant circuit20, and the resonant inductor LA2of the second phase resonant circuit A2of the first N-phase resonant circuit10is coupled with the resonant inductor LBNof the Nth phase resonant circuit BN of the second N-phase resonant circuit20, and so on. That is, the resonant inductors in the first N-phase resonant circuit10are all coupled with the resonant inductors in the second N-phase resonant circuit20, and each resonant inductor is coupled once. Meanwhile, any two resonant inductors may be coupled as long as they are coupled for once. For example, alternatively, on the premise that the resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10is coupled with the resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20, the resonant inductor LA2of the second phase resonant circuit A2of the first N-phase resonant circuit10may be coupled with the resonant inductor LB2of the second phase resonant circuit B2of the second N-phase resonant circuit20, and the resonant inductor LA1of the first phase resonant circuit A1of the first N-phase resonant circuit10may be coupled with the resonant inductor LBNof the Nth phase resonant circuit BN of the second N-phase resonant circuit20, and so on. In this way, the current sharing of the output currents of the first N-phase resonant circuit10and the second N-phase resonant circuit20can be better achieved. In another embodiment, if N is an even number, then (N−1) resonant inductors in the first N-phase resonant circuit may be coupled with (N−1) resonant inductors in the second N-phase resonant circuit in one-to-one correspondence. That is, N−1 resonant inductors are randomly selected from the N resonant inductors of the first N-phase resonant circuit, and N−1 resonant inductors are randomly selected from the N resonant inductors of the second N-phase resonant circuit, and the selected resonant inductors are coupled in one-to-one correspondence. The structure shown inFIG.1is still taken as an example. Specifically, on the premise that the resonant inductor LANof the Nth phase resonant circuit AN of the first N-phase resonant circuit10is coupled with the resonant inductor LB1of the first phase resonant circuit B1of the second N-phase resonant circuit20, the resonant inductor LA1of the first phase resonant circuit A1of the first N-phase resonant circuit10is coupled with the resonant inductor LB2of the second phase resonant circuit B2of the second N-phase resonant circuit20, and so on, and finally the resonant inductor LA2of the second phase resonant circuit A2of the first N-phase resonant circuit10and the resonant inductor LBNof the Nth phase resonant circuit BN of the second N-phase resonant circuit20are left uncoupled. That is, among the resonant inductors of the first N-phase resonant circuit10, all the other resonant inductors except for the resonant inductor LA2are coupled; and among the resonant inductors of the second N-phase resonant circuit20, all the other resonant inductors except for the resonant inductor LBNare coupled, and each resonant inductor is coupled once. Similarly, the current sharing of the output currents of the first N-phase resonant circuit10and the second N-phase resonant circuit20can be better achieved.FIG.2illustrates a structure of the first N-phase resonant circuit10and the second N-phase resonant circuit20, and in this embodiment, N=3 is taken as an example. As shown inFIG.2, the first N-phase resonant circuit10and the second N-phase resonant circuit20each comprise a 3-phase resonant circuit. Each phase resonant circuit comprises a bridge arm, a resonant inductor, a resonant capacitor, an isolation transformer and two diodes. For example, the first phase resonant circuit A1of the first N-phase resonant circuit10comprises a first switch tube Q1, a second switch tube Q2, a resonant inductor LA1, a resonant capacitor CA1, an isolation transformer T1, a first diode D1and a second diode D2. The first switch tube Q1and the second switch tube Q2form a bridge arm, the midpoint of which is P1, the first switch tube Q1forms the upper bridge arm of the bridge arm and the second switch tube Q2forms the lower bridge arm of the bridge arm. In this embodiment, by coupling the resonant inductor LA1of the first phase resonant circuit A1in the first N-phase resonant circuit10with the resonant inductor LB2of the second phase resonant circuit B2in the second N-phase resonant circuit20, the current sharing between the output current of the first phase resonant circuit A1in the first N-phase resonant circuit10and the output current of the second phase resonant circuit B2in the second N-phase resonant circuit20is achieved, and then, the current sharing of the output currents of the first phase resonant circuit A1, the second phase resonant circuit A2and the third phase resonant circuit A3in the first N-phase resonant circuit10as well as the first phase resonant circuit B1, the second phase resonant circuit B2and the third phase resonant circuit B3in the second N-phase resonant circuit20can be achieved. In an embodiment, the multi-path resonant circuit further comprises a controller, and the controller is connected with the switches in each bridge arm of the N-phase resonant circuit. Specifically, the controller is used to output a first set of driving signals to drive the switch tube in the upper bridge arm of each bridge arm in the N-phase resonant circuit to be turned on and turned off, and output a second set of driving signals complementary to the first set of driving signals to drive the switch tube in the lower bridge arm of each bridge arm in the N-phase resonant circuit to be turned on and turned off, so that the fundamental wave of the midpoint voltage of each bridge arm in the N-phase resonant circuit has the same phase as the corresponding first set of driving signals. The circuit structure shown inFIG.2is taken as an example for illustration. The controller (not shown in the figure) is connected with the switch tubes in each bridge arm of the N-phase resonant circuit. For example, the controller is connected with the first switch tube Q1and the second switch tube Q2in the bridge arm of the first N-phase resonant circuit, and both the first switch tube Q1and the second switch tube Q2are controlled by the controller. Please refer toFIG.3together, in which a curve L31is a driving signal of the first switch tube Q1; a curve L32is a driving signal of the second switch tube Q2; and a curve L33is the fundamental wave of the voltage at the midpoint P1of the bridge arm. Specifically, the controller outputs a driving signal (corresponding to the first set of driving signals at this point as shown by the curve L31) to drive the first switch tube Q1of the upper bridge arm of the bridge arm in the first N-phase resonant circuit to be turned on and turned off. The first switch tube Q1is turned on in the high-level period of the curve L31and turned off in the low-level period of the curve L31. The controller further outputs another driving signal (corresponding to the second set of driving signals at this point as shown by the curve L32) to drive the second switch tube Q2of the lower bridge arm of the bridge arm in the first N-phase resonant circuit to be turned on and turned off. The second switch tube Q2is turned on in the high-level period of the curve L32and turned off in the low-level period of the curve L32. Meanwhile, the phases of the curve L31and the curve L32are complementary, that is, the phases of the first set of driving signals and the second set of driving signals are complementary. In this case, as shown by the curve L33, the phase of the fundamental wave of the voltage at the midpoint P1of the bridge arm is the same as that of the first set of driving signals. In other words, by controlling the switch tubes in each bridge arm to be turned on and turned off by the controller, the phase of the fundamental wave of the voltage at the midpoint of each bridge arm can be controlled. In an embodiment, the first resonant inductor and the second resonant inductor are coupled to form a coupling inductor. The coupling inductor comprises a magnetic core, a winding of the first resonant inductor and a winding of the second resonant inductor. The magnetic core comprises two side posts and a center post arranged between the two side posts, and the winding of the first resonant inductor and the winding of the second resonant inductor are respectively wound on the two side posts of the magnetic core. In an embodiment, the magnetic core is made of a ferrite material, and the two side posts and the center post are all provided with an air gap. The structure of the multi-path resonant circuit shown inFIG.1is taken as an example for illustration. At this point, the resonant inductor LANis the first resonant inductor and the resonant inductor L K is the second resonant inductor. Referring toFIG.2andFIG.4together, as shown in part a ofFIG.4, a winding a201of the first resonant inductor is wound around a side post a202of the magnetic core, a winding a205of the second resonant inductor is wound around a side post a204of the magnetic core, and a center post a203of the magnetic core is arranged between the side post a202and the side post a204. The current i1of the winding a201of the first resonant inductor flows in from the homonymous end thereof, and the current i5of the winding a205of the second resonant inductor flows in from the homonymous end thereof. There is a broken part in each of the side post a202, the center post a203and the side post a204, and the broken part is the air gap. The desired inductance can be obtained by leaving an air gap in each of the side post a202and the side post a204. In order to realize magnetic coupling between the first resonant inductor and the second resonant inductor, it is necessary to arrange high magnetic resistance on the common magnetic flux path of the two resonant inductors, so the center post a203also needs to be provided with an air gap. It shall be noted that in other embodiments, the magnetic core may also be made of other materials, and no specific limitation is made thereto in the embodiments of the present application. For example, in an embodiment, the magnetic core is made of a magnetic powder core material, and no air gap may be provided. In addition, because the phase difference between the current i1and the current i5is 180°, although both the current i1and the current i5flow in from the homonymous ends in terms of nomenclature, in practical operation, the heteronymous ends are coupled and the magnetic flux flow direction is embodied in the form of heteronymous end coupling. Meanwhile, in this embodiment, the winding of the first resonant inductor and the winding of the second resonant inductor are wound on the two side posts of the magnetic core as an example. In other embodiments, other winding methods may also be adopted, and no specific limitation is made thereto in the embodiments of the present application as long as the magnetic coupling between the first resonant inductor and the second resonant inductor is achieved. Each magnetic flux in the structure of part a ofFIG.4is as shown in part b ofFIG.4, and as shown in part b ofFIG.4, it is known from the above description that each magnetic post (including the side post a202, the center post a203and the side post a204) is provided with an air gap in order to form magnetic resistance large enough. Therefore, in the representation of the magnetic path, Rm1, Rm2and Rm5respectively represent the magnetic resistance of the three magnetic posts. Φ1and Φ5respectively represent equivalent magnetic flux current sources formed by volt seconds on the winding a201of the first resonant inductor and the winding a205of the second resonant inductor. As can be seen from the flow direction of the magnetic flux shown in part b ofFIG.4, the magnetic flux is in a superimposed state at the center post a203. If current sharing is not achieved between the two resonant inductors, they may interact with each other through the change of magnetic potential of the center post a203so as to be coupled, so that the first resonant inductor and the second resonant inductor coupled at the heteronymous ends achieve the current sharing function. As shall be appreciated, this embodiment only illustrates a mode in which the first resonant inductor is coupled with the second resonant inductor, while other coupling modes may also be adopted in other embodiments, and no limitation is made thereto in the embodiments of the present application. For example, in another embodiment, a transformer may be added to realize the coupling between the first resonant inductor and the second resonant inductor. As shown inFIG.5, the multi-path resonant circuit further comprises a transformer TO, which comprises a first inductor L11and a second inductor L12. The first inductor L11is connected between the midpoint P1of the bridge arm in the resonant circuit corresponding to the first resonant inductor (which is the resonant inductor LA1at this point) and the first resonant inductor, and the second inductor L12is connected between a midpoint P5of the bridge arm in the resonant circuit corresponding to the second resonant inductor (which is the resonant inductor LB2at this point) and the second resonant inductor. In this embodiment, the transformer TO is a strong coupling transformer, which can also realize the coupling between the first resonant inductor and the second resonant inductor so as to achieve the current sharing of the output currents of the first N-phase resonant circuit and the second N-phase resonant circuit. In an embodiment, the at least two N-phase resonant circuits further comprise a third N-phase resonant circuit. A third resonant inductor in any phase resonant circuit of the third N-phase resonant circuit is coupled with a fourth resonant inductor in the resonant circuit with uncoupled resonant inductance in the first N-phase resonant circuit, or the third resonant inductor is coupled with a fifth resonant inductor in a resonant circuit with uncoupled resonant inductance in the second N-phase resonant circuit. Specifically, referring toFIG.6, the at least two N-phase resonant circuits further comprise a third N-phase resonant circuit30. A resonant inductor LD1of the first phase resonant circuit D1in the third N-phase resonant circuit30is coupled with the resonant inductor LBNof the Nth phase resonant circuit BN with uncoupled resonant inductance in the second N-phase resonant circuit20to realize current sharing between the output current of the second N-phase resonant circuit20and the output current of the third N-phase resonant circuit30. At this point, the resonant inductor LD1is the third resonant inductor and the resonant inductor LBNis the fifth resonant inductor. As shall be appreciated, in this embodiment, the coupling of the resonant inductor LD1and the resonant inductor LBNis taken as an example, while in other embodiments, we only need to find out an uncoupled resonant inductor in the first N-phase resonant circuit10and the second N-phase resonant circuit20and make it coupled with any resonant inductor in the third N-phase resonant circuit30, and no specific limitation is made thereto in the embodiments of the present application. For example, in an embodiment, the resonant inductor LD2may be coupled with the resonant inductor LB2, and in another embodiment, the resonant inductor LDNmay be coupled with the resonant inductor LBN. Meanwhile, a fourth N-phase resonant circuit and a fifth N-phase resonant circuit or the like may be continuously added with reference to the way of adding the third N-phase resonant circuit. The specific implementation is the same as the way of adding the third N-phase resonant circuit, and this is within the scope easily appreciated by those skilled in the art and thus will not be further described herein. In addition, since the method of current sharing is simpler, it is easy to expand. For example, in an embodiment, the multi-path resonant circuit further comprises a fourth N-phase resonant circuit, then a resonant inductor of any phase resonant circuit in the fourth N-phase resonant circuit may be coupled with the resonant inductor LB2shown inFIG.4to realize current sharing of the output currents of the fourth N-phase resonant circuit and the second N-phase resonant circuit20. In addition, in practical application, it can provide great advantages in the layout of PCB. In an embodiment, please refer toFIG.7, which is a schematic view of the layout of the PCB for the first N-phase resonant circuit10and the second N-phase resonant circuit20provided according to the embodiments of the present application, wherein N=3. Referring toFIG.2andFIG.7together, each phase resonant circuit comprises a bridge arm, a resonant cavity and a rectifying module. The bridge arm comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm each comprise a switch tube, the resonant cavity comprises a resonant inductor, a resonant capacitor and an isolation transformer, and the rectifying module comprises two diodes. For example, the first phase resonant circuit A1of the first N-phase resonant circuit10comprises a bridge arm111, a resonant cavity121and a rectifying module131. The upper bridge arm of the bridge arm111comprises a first switch tube Q1, and the lower bridge arm of the bridge arm111comprises a second switch tube Q2. The resonant cavity121comprises a resonant inductor LA1, a resonant capacitor CA1, and an isolation transformer T1. The rectifying module131comprises a first diode D1and a second diode D2. In this embodiment, the layout between the first N-phase resonant circuit10and the second N-phase resonant circuit20is compact and the area occupied by the circuits is small, so that the material loss is small and it is beneficial for realizing the current sharing function at a low cost and providing strong practicability. In an embodiment, the phase difference between the fundamental wave of the bridge arm midpoint voltage in a resonant circuit corresponding to the first resonant inductor and the fundamental wave of the bridge arm midpoint voltage in a resonant circuit corresponding to the second resonant inductor is k*180°, and k is an integer. The fundamental wave refers to the sine wave component whose period equal to the longest period of the complex periodic oscillation. Generally speaking, the fundamental wave is a sine wave with the same frequency as the switching frequency in the corresponding bridge arm. The circuit structure shown inFIG.2is taken as an example for illustration. In this embodiment, the resonant inductor LA1of the first phase resonant circuit A1in the first N-phase resonant circuit10is coupled with the resonant inductor LB2of the second phase resonant circuit B2in the second N-phase resonant circuit20, so that the resonant inductor LA1corresponds to the first resonant inductor and the resonant inductor LB2corresponds to the second resonant inductor. That is, the resonant circuit corresponding to the first resonant inductor is the first phase resonant circuit A1in the first N-phase resonant circuit10, and the resonant circuit corresponding to the second resonant inductor is the second phase resonant circuit B2in the second N-phase resonant circuit20. The midpoint of the bridge arm in the resonant circuit corresponding to the first resonant inductor is the midpoint P1of the bridge arm of the first phase resonant circuit A1in the first N-phase resonant circuit10, and the midpoint of the bridge arm in the resonant circuit corresponding to the second resonant inductor is the midpoint P4of the bridge arm of the second phase resonant circuit B2in the second N-phase resonant circuit20. The fundamental wave of the bridge arm midpoint voltage in the resonant circuit corresponding to the first resonant inductor is the fundamental wave of the voltage on the bridge arm midpoint P1(which is labeled as the first fundamental wave), and the fundamental wave of the bridge arm midpoint voltage in the resonant circuit corresponding to the second resonant inductor is the fundamental wave of the voltage on the bridge arm midpoint P2(which is labeled as the second fundamental wave). By configuring the phase difference between the first fundamental wave and the second fundamental wave to be k*180°, it is possible to ensure that there are driving signals with a phase difference of k*180° among different N-phase resonant circuits while driving the N-phase resonant circuits at the same frequency. The driving signals are the signals for driving the switch tubes in the bridge arm so as to realize the coupling between different resonant inductors. For example, in this embodiment, the phase difference between the first fundamental wave and the second fundamental wave is k*180°, then the phase difference between the driving signal of the bridge arm of the first phase resonant circuit A1in the first N-phase resonant circuit10and the driving signal of the bridge arm of the second phase resonant circuit B2in the second N-phase resonant circuit20is k*180°. At this point, the resonant inductor LA1may be coupled with the resonant inductor LB2to achieve current sharing. Referring toFIG.2andFIG.8together, a curve L81is a schematic view of a driving signal of the first switch tube Q1, which corresponds to the driving signal of the bridge arm of the first phase resonant circuit A1in the first N-phase resonant circuit10; a curve L82is a schematic view of the first fundamental wave; a curve L83is a schematic view of a driving signal of a ninth switch tube Q9, which corresponds to the driving signal of the bridge arm of the second phase resonant circuit B2in the second N-phase resonant circuit20; and a curve L84is a schematic view of the second fundamental wave, wherein K=1. Referring toFIG.8, as can be known from the curve L82and the curve L84, the phase difference between the first fundamental wave and the second fundamental wave is 180°. At this point, the phase difference between the driving signal of the first switch tube Q1and the driving signal of the ninth switch tube Q9is also 180°, and then the resonant inductor LA1and the resonant inductor LB2may be coupled to achieve current sharing. In an embodiment, the phase difference between the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the second phase resonant circuit in the N-phase resonant circuit is 360°/N. Furthermore, if the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the first N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the second N-phase resonant circuit are collocated fundamental waves, then the phase difference between the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the first N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the second N-phase resonant circuit is 180-360°/N. The collocated fundamental waves refer to the fundamental waves of the bridge arm midpoint voltage of the same phase resonant circuits for different N-phase resonant circuits. For example, the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit of the first N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit of the second N-phase resonant circuit are collocated fundamental waves, and the circuit structure of the first phase resonant circuit of the first N-phase resonant circuit is the same as that of the first phase resonant circuit of the second N-phase resonant circuit. For another example, the fundamental wave of the bridge arm midpoint voltage of the second phase resonant circuit of the first N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the second phase resonant circuit of the second N-phase resonant circuit are collocated fundamental waves, and the circuit structure of the second phase resonant circuit of the first N-phase resonant circuit is the same as that of the second phase resonant circuit of the second N-phase resonant circuit. Specifically, taking N=3 as an example, the phase difference between the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the second phase resonant circuit is 120°. The phase difference between the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the third phase resonant circuit is 240° or −120°. It is assumed that the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the first N-phase resonant circuit is 0° at the initial phase, then the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the second N-phase resonant circuit is 60° at the initial phase to meet the condition that the phase difference between the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the first N-phase resonant circuit and the fundamental wave of the bridge arm midpoint voltage of the first phase resonant circuit in the second N-phase resonant circuit is 180-360°/N. Furthermore, as can be known from the above embodiments, the phase of each fundamental wave is the same as the phase of the driving signal of the switch tube of the upper bridge arm, and thus the driving signal of the switch tube of each upper bridge arm can be obtained. The circuit structure shown inFIG.2is still taken as an example for illustration, and the driving signals at this point are as shown inFIG.9. Please refer toFIG.2andFIG.9together. As shown inFIG.9, a curve L91is a driving signal of the first switch tube Q1; a curve L92is a driving signal of a third switch tube Q3; a curve L93is a driving signal of a fifth switch tube Q5; a curve L94is a driving signal of a seventh switch tube Q7; a curve L95is a driving signal of the ninth switch tube Q9; and a curve L96is a driving signal of an eleventh switch tube Q11. Specifically, the first switch tube Q1starts to be driven to be turned on at the time of t0, the third switch tube Q3is turned on at the time of t2, and the fifth switch tube Q5starts to be turned on at the time of t4. The phase difference between the time of t0and the time of t2is 120°, and the phase difference between the time of t2and the time of t4is 120°. That is, the phase difference between the driving signal of the first switch tube Q1and the driving signal of the third switch tube Q3is 120°, and the phase difference between the driving signal of the third switch tube Q3and the driving signal of the fifth switch tube Q5is 120°. Furthermore, since one cycle is 360°, the phase difference between the driving signal of the first switch tube Q1and the driving signal of the fifth switch tube Q5is −120°. That is, for the first N-phase resonant circuit10, the phase difference between the fundamental wave (of which the phase is 0°) of the bridge arm midpoint voltage of the resonant circuit A1and the fundamental wave (of which the phase is 120°) of the bridge arm midpoint voltage of the resonant circuit A2is 120°. The phase difference between the fundamental wave (of which the phase is 0°) of the bridge arm midpoint voltage of the resonant circuit A1and the fundamental wave (of which the phase is 240°) of the bridge arm midpoint voltage of the resonant circuit A3is −120°. The phase difference between the fundamental wave (of which the phase is 120°) of the bridge arm midpoint voltage of the resonant circuit A2and the fundamental wave (of which the phase is 240°) of the bridge arm midpoint voltage of the resonant circuit A3is 120°. Similarly, for the second N-phase resonant circuit20, the phase difference between the fundamental wave (of which the phase is 60°) of the bridge arm midpoint voltage of the resonant circuit B1and the fundamental wave (of which the phase is 180°) of the bridge arm midpoint voltage of the resonant circuit B2is 120°. The phase difference between the fundamental wave (of which the phase is 60°) of the bridge arm midpoint voltage of the resonant circuit B1and the fundamental wave (of which the phase is 300°) of the bridge arm midpoint voltage of the resonant circuit B3is −120°. The phase difference between the fundamental wave (of which the phase is 180°) of the bridge arm midpoint voltage of the resonant circuit B2and the fundamental wave (of which the phase is 300°) of the bridge arm midpoint voltage of the resonant circuit B3is 120°. Then, driving signals with a phase difference of 180° can always be found for two parallel N-phase resonant circuits. For example, the phase difference between the driving signal of the first switch tube Q1and a driving signal of the eleventh switch tube Q11is 180°. The advantages of this arrangement are as follows: on the one hand, for the odd-numbered N-phase resonant circuit with N greater than or equal to 3, it helps to reduce the output ripple thereof; and on the other hand, the internal circulation of common-mode noise between two parallel N-phase resonant circuits can be realized to reduce external noise emission. However, it shall be noted that this is not the only arrangement mode. For example, two parallel N-phase resonant circuits may be enabled to work completely at the same phase and at the same frequency, so all the phase difference between the two circuits is always 0° (i.e., corresponding to the case where K is an even number, for example, K=0). At this point, only an inductive coupling mode opposite to the previous mode is required. For example, when K is an odd number, two resonant inductors are coupled at the homonymous ends, and when K is an even number, two resonant inductors are coupled at heteronymous ends. The following analysis and explanation are made with reference to the time period between the time of t1and the time of t2. During this time period, the first switch tube Q1, the fourth switch tube Q4, the sixth switch tube Q6, the seventh switch tube Q7, the tenth switch tube Q10and the twelfth switch tube Q12are turned on, and the other switch tubes are turned off, so the circuit structure shown inFIG.2may be equivalent to that shown inFIG.10. As shown inFIG.10, Vx1is an equivalent voltage source composed of the resonant capacitor CA1and the isolation transformer T1. Vx2is an equivalent voltage source composed of a resonant capacitor C A2and an isolation transformer T2. Vx3is an equivalent voltage source composed of a resonant capacitor CA3and an isolation transformer T3. Vx4is an equivalent voltage source composed of a resonant capacitor CB1and an isolation transformer T4. Vx5is an equivalent voltage source composed of a resonant capacitor C B2and an isolation transformer T5. Vx6is an equivalent voltage source composed of a resonant capacitor CB3and an isolation transformer T6. Furthermore, the resonant inductor LA1is coupled with the resonant inductor LB2. Under such relationships, it can be seen that the homonymous end of the resonant inductor LA1is in the direction of inductance withstanding positive voltage, while the heteronymous end of the resonant inductor LB2is in the direction of inductance withstanding positive voltage. Therefore, after combined with the driving waveforms, the actual operation is in a relationship where heteronymous ends are coupled. By expanding the resonant inductor LA1and the resonant inductor LB2in the circuit into a coupled inductor model, it can be seen that the coupling voltage generated by mutual inductance can perform mutual voltage compensation at this point, thereby realizing current sharing between the circuits. The strength of coupling may affect the degree of current sharing. An optimized design method is to make the coupling inductance half of the self-inductance, which can achieve better current sharing effect. Under this design method, the series resonant inductance required by the resonant cavity is equal to the self-inductance minus the coupling inductance. The coupling inductance is the inductance value of two coupled resonant inductors acting on each other, the self-inductance is the inductance value of the resonant inductor itself, and the series resonant inductance is the difference between the self-inductance and the coupling inductance. For example, if the resonant inductor LA1is coupled with the resonant inductor LB2, then the part of the inductance generated by the resonant inductor LA1that acts on the resonant inductor LB2is the coupling inductance MA1on a branch of the resonant inductor LB2, and the inductance generated by the resonant inductor LA1is the self-inductance L1of the resonant inductor LA1. The part of the inductance generated by the resonant inductor LB2that acts on the resonant inductor LA1is the coupling inductance M K on a branch of the resonant inductor LA1, and the inductance generated by the resonant inductor LB2is the self-inductance L2of the resonant inductor LB2. Then, when the resonant inductor LA1and the resonant inductor LB2are expanded into a coupled inductor model as shown inFIG.4, the following formulas can be obtained: L1=N2×(Rm5+Rm2)Rm1×Rm2+Rm1×Rm5+Rm2×Rm5(1) L5=N2×(Rm1+Rm2)Rm1×Rm2+Rm1×Rm5+Rm2×Rm5(2) MA1=MB2=N2×Rm2Rm1×Rm2+Rm1×Rm5+Rm2×Rm5(3) Lr1=N2×(Rm5+Rm2)-N2×Rm2×i5i1Rm1×Rm2+Rm1×Rm5+Rm2×Rm5(4) Lr5=N2×(Rm5+Rm2)-N2×Rm2×i1i5Rm1×Rm2+Rm1×Rm5+Rm2×Rm5(5)wherein N is the number of turns of the winding a201of the first resonant inductor or the number of turns of the winding a205of the second resonant inductor; Lr1is the series resonant inductance in the first phase resonant circuit A1of the first N-phase resonant circuit; Lr5is the series resonant inductance in the second phase resonant circuit B2of the second N-phase resonant circuit. It can be found that the magnitude of the series resonant inductance Lr1and the series resonant inductance Lr5all changes with the ratio of i1and i5. For example, for the series resonant inductance Lr1, when the current i5is larger than the current i1, Lr1decreases so that the current i1can get a larger growth rate at the same voltage, and the current i1increases and gradually approaches the current i5so that the difference between the current i1and the current i5becomes smaller and smaller, and thus the current sharing between the current i1and the current i5can be realized. The following is the test result of the multi-path resonant circuit provided according to the embodiments of the present application, wherein the input voltage is 400V and the output voltage is 680V. The test structure is as shown in Table 1. TABLE 1Output currentCoupled stateUncoupled stateFirst N-phaseFirst phase28.6220.7resonant circuitSecond phase28.320.2Third phase29.621.8Second N-phaseFirst phase30.338.5resonant circuitSecond phase29.938.5Third phase31.338.4 As shown in Table 1, when there is no coupled resonant inductor, that is, in the uncoupled state, the difference between the output currents of the first N-phase resonant circuit and the second N-phase resonant circuit is relatively large, which may lead to the damage of devices or the abnormality of the whole system. When there are coupled resonant inductors, that is, in the coupled state, the output currents of the first N-phase resonant circuit and the second N-phase resonant circuit are nearly equal to each other, and the current sharing effect is better, which can improve the stability of the system operation. An embodiment of the present application further provides a resonant converter, which comprises a multi-path resonant circuit as in any of the embodiments described above. Finally, it shall be noted that, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application. Under the idea of the present application, technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and many other variations in different aspects of the present application as described above are possible, and these variations are not provided in details for conciseness. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art shall appreciate that, the technical solutions described in the foregoing embodiments may still be modified or some of the technical features may be equivalently replaced. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of various embodiments of the present application. | 44,580 |
11942873 | DESCRIPTION OF EMBODIMENTS Embodiments of a secondary magnetic excitation generator-motor device according to the present invention will be described in detail below with reference to the accompanying drawings. The present invention is not limited to the embodiments. First Embodiment With reference toFIG.1, a device configuration according to a first embodiment of the present invention is described below. A three-phase AC system1is connected to a stator-side armature winding5of a winding induction machine through a main voltage transformer2, a phase reverse disconnector (89GM)3, and a synchronous circuit breaker (52G)4. A rotor-side excitation winding6is connected to an AC-side of a three-level NPC power converter7. Between a DC-side positive terminal and a neutral point terminal of the three-level NPC power converter7, a positive-side DC capacitor (CP)8and a first DC output terminal (VDC1) of a DC voltage source71are connected in parallel to each other. In contrast, between a DC-side negative terminal and the neutral point terminal of the three-level NPC power converter7, a negative-side DC capacitor (CN)12and a second DC output terminal (VDC2) of the DC voltage source71are connected in parallel to each other. An AC terminal of the DC voltage source71is connected in parallel to a first terminal of an excitation circuit breaker (52E)16, while a second terminal of the excitation circuit breaker (52E)16is connected in parallel to a terminal of the main transformer2on the winding generator motor-side. The DC voltage source71is constituted by an AC/DC power converter. For example, the DC voltage source71can be implemented by having a configuration in which the DC voltage source71is connected back to back to the DC-side positive terminal, the DC-side negative terminal, and the neutral point terminal of the three-level NPC power converter7. Next, a configuration of the control system of the three-level NPC power converter7is described. An automatic voltage regulator (AVR)29is provided to output a d-axis current command (I_Dref) such that the value of generator voltage VG becomes a set value. The value of generator voltage VG is computed on the basis of information from an instrument voltage transformer28at a stator-side armature terminal of the winding induction machine. An automatic voltage regulator (APR)31is provided to output a q-axis current command (I_Qref) such that the value of active power becomes a set value. The value of active power is computed on the basis of information from an instrument voltage transformer3and a main voltage-transformer terminal instrument current transformer30. A phase sensor32is provided to sense a phase θs of slip frequency which is equal to the difference between an AC-system frequency and a rotational frequency of the winding induction machine on the basis of information from a rotational phase sensor (PLG)55and a main voltage-transformer terminal instrument voltage transformer17, so as to input two-phase current commands (I_Dref and I_Qref) to a two-phase/three-phase coordinates converter33, from which three-phase current commands (IU_ref, IV_ref, and IW_ref) with the slip frequency are output. An excitation-current instrument current transformer34is provided between the three-level NPC power converter7and the terminals of the rotor-side excitation winding6of the winding induction machine to detect excitation current values (IU, IV, and IW), such that a three-phase/two-phase converter35computes two-phase current values (I_DfB and I_QfB) that are a steady-state DC amount. An excitation current regulator36outputs modulation factor commands (αU, αV, and αW) such that the two-phase current values (I_DfB and I_QfB) correspond with the two-phase current commands (I_Dref and I_Qref), and such that the excitation current values (IU, IV, and IW) correspond with the three-phase current commands (IU_ref, IV_ref, and IW_ref). These modulation factor commands (αU, αV, and αW) are input respectively to three units of PWM modulation circuits37,38, and39provided for respective phases, from which first modulation commands (MU1, MV1, and MW1) for respective phases are output. Meanwhile, the excitation current values (IU, IV, and IW) are input from the excitation-current instrument current transformer34to a second PWM modulation circuit40, from which second modulation commands (MU2, MV2, and MW2) are output. The excitation current values (IU, IV, and IW) are input from the excitation-current instrument current transformer34to a running-mode switching circuit41. The running-mode switching circuit41outputs a command value SW for simultaneously switching between the first modulation commands (MU1, MV1, and MW1) and the second modulation commands (MU2, MV2, and MW2). The running-mode switching circuit41also outputs a GB command for fixing ignition commands for all the self-arc-extinguishing elements to the off-side. In such a manner that when the command value SW is 0, the first modulation commands (MU1, MV1, and MW1) are selected, and when the command value SW is 1, the second modulation commands (MU2, MV2, and MW2) are selected, three units of switches42,43, and44for respective phases selectively output modulation commands (MU, MV, and MW). The modulation commands (MU, MV, and MW) are input to three units of pulse generation circuits45,46, and47for respective phases to execute on/off control on gate commands for the self-arc-extinguishing elements of the three-level NPC power converter7. With reference toFIG.3, an operation of a U-phase PWM modulation circuit37is described below. The PWM regulation modulation circuit37has a positive carrier between the neutral point (0) and the positive terminal (+1), and a negative carrier between the negative terminal (−1) and the neutral point (0). On the basis of the magnitude relation between these carriers and a modulation wave computed from an input-side modulation factor command αU, the PWM regulation circuit37outputs the modulation command MU1that is selected from among three values (+1, 0, and −1). A V-phase PWM modulation circuit38and a W-phase PWM modulation circuit39operate in the same manner as the U-phase PWM modulation circuit37, and therefore descriptions of the operation thereof are omitted to avoid redundant explanations. FIG.4illustrates an operation of the pulse generation circuit45in form of a table. First, descriptions are made on an operation of the pulse generation circuit45when a GB command issued from the running-mode switching circuit41shows level 0. When the modulation command MU is (+1), gate commands G_UP and G_UPC for self-arc-extinguishing elements UP and UPC are on, while the other gate commands are off. When the modulation command MU is (0), the gate command G_UPC for the self-arc-extinguishing element UPC and a gate command G_UNC for a self-arc-extinguishing element UNC are on, while the other gate commands are off. When the modulation command MU is (−1), a gate command G_UN for a self-arc-extinguishing element UN and the gate command G_UNC for the self-arc-extinguishing element UNC are on, while the other gate commands are off. In contrast, when the GB command shows level 1, the gate commands G_UP, G_UPC, G_UNC, and G_UN for the self-arc-extinguishing elements UP, UPC, UNC, and UN are off regardless of the value of the modulation command MU. FIG.5illustrates a configuration of the second PWM modulation circuit40. Absolute value computation devices101,102, and103calculate absolute values |IU|, |IV|, and |IW| of the excitation current values (IU, IV, and IW) input from the instrument current transformer34, respectively. Then, subtractors104,105, and106output a difference between the absolute values, and comparators107,108, and109output a sign determination result selectively from two values (0 and 1). The outputs from the comparators107,108, and109are input to a logic circuit110. The logic circuit110outputs a signal111that shows level 1 when the absolute value |IU| is smallest, or otherwise outputs the signal111that shows level 0. In the same manner as |IU|, the logic circuit110also outputs a signal112for |IV| and a signal113for |IW|. Meanwhile, comparators114,115, and116output the polarity of the excitation current values (IU, IV, and IW) selectively from two values (0 and 1). The comparator114outputs a signal117that shows level 1 when the excitation current value IU is positive, or otherwise outputs the signal117that shows level 0. In the same manner as IU, the comparators115and116also output a signal118for IV and a signal119for IW, respectively. The signals111,112,113,117,118, and119are input to a logic circuit120. The logic circuit120outputs three values (+1, 0, and −1) for respective phases to three-value selection output circuits121,122, and123. A U-phase three-value selection output circuit121outputs “0” as the second modulation output MU2when the absolute value of IU is smallest in three phases, outputs “+1” as the second modulation output MU2when IU is positive, and outputs “−1” as the second modulation output MU2when IU is negative. A V-phase three-value selection output circuit122and a W-phase three-value selection output circuit123operate in the same manner as the U-phase three-value selection output circuit121, and therefore descriptions of the operation thereof are omitted to avoid redundant explanations. FIG.6illustrates a configuration of the running-mode switching circuit41. Since like reference signs to those illustrated inFIG.5denote like constituent elements, descriptions thereof are omitted to avoid redundant explanations. A maximum-value selection output device202selectively outputs the maximum value of the absolute values |IU|, |IV|, and |IW| of the excitation current values (IU, IV, and IW) input from the instrument current transformer34. A minimum-value selection output device201selectively outputs the minimum value of the absolute values |IU|, |IV|, and |IW|. When the maximum value exceeds a set value I1, a comparator203outputs level 1, or otherwise outputs level 0. When the minimum value is equal to or smaller than a set value I2, a comparator204outputs level 1, or otherwise outputs level 0. A flip-flop205receives a set signal output from the comparator203, and a reset signal output from the comparator204, and on the basis of these signals, outputs a command value SW. When the command value SW shows level 0, the switches42,43, and44select the first modulation commands (MU1, MV1, and MW1). When the command value SW shows level 1, the switches42,43, and44select the second modulation commands (MU2, MV2, and MW2). The set values I1and I2are defined as “I1>I2”. The value of I1is set with reference to the maximum interrupting current of the self-arc-extinguishing elements of the three-level NPC power converter7to such a value as not to exceed the maximum interrupting current. FIGS.7and8illustrate an operation of the secondary magnetic excitation generator-motor device inFIGS.1to6when a ground fault has occurred in the three-phase AC system1at a time t0, and then the accidental phase is removed to resume a normal operation at a time tCB. During a period (from t1to t2) and a period (from t3to t4) inFIG.7, and during a period (from t5to t6) and a period (from t7to t8) inFIG.8, the command value SW shows level 1. Thus, the second modulation commands (MU2, MV2, and MW2) are selected. According to the configuration of the invention described in the present embodiment, the secondary magnetic excitation generator-motor device can be protected from an overcurrent without the need for bypassing the three-level NPC power converter7and without the need for blocking the gates. Therefore, the secondary magnetic excitation generator-motor device can precisely switch between two different modulation commands, and consequently can be protected from an overcurrent and can run continuously in a stable manner. Second Embodiment With reference toFIG.2, a device configuration according to a second embodiment of the present invention is described below. Between a DC-side positive terminal and the neutral point terminal of the three-level NPC power converter7, the positive-side DC capacitor (CP)8and a DC terminal of a first two-level power converter9are connected in parallel to each other. An AC terminal of the first two-level power converter9is connected to a first excitation voltage transformer11through a first harmonic suppression filter10. In contrast, between the neutral point terminal and a DC-side negative terminal of the three-level NPC power converter7, the negative-side DC capacitor (CN)12and a DC terminal of a second two-level power converter13are connected in parallel to each other. An AC terminal of the second two-level power converter13is connected to a second excitation voltage transformer15through a second harmonic suppression filter14. The first excitation voltage transformer11and a terminal of the second excitation voltage transformer15on the AC system-side is connected in parallel to a first terminal of the excitation circuit breaker (52E)16. A second terminal of the excitation circuit breaker (52E)16is connected in parallel to the terminal of the main voltage transformer2on the winding generator motor-side. Next, a configuration and an operation of the control system of the first two-level power converter9is described. A first power factor regulator (APFR1)19is provided to output a d-axis DC current command (IC1_Dref) such that the power factor becomes 1 on the basis of reactive power computed from information provided by the main voltage-transformer terminal instrument voltage transformer17provided at the terminal of the main voltage transformer2on the winding generator motor-side, and provided by a first instrument current transformer18provided between the first harmonic suppression filter10and the AC terminal. A first DC-voltage regulator (ADCVR1)21is provided to output a q-axis DC current command (IC1_Qref) such that a first instrument DC voltage transformer20detects a voltage VDCP in the positive-side DC capacitor8to regulate the voltage VDCP to a set value. A first two-level converter current regulator22executes on/off control on the gates to self-arc-extinguishing elements (RP1, SP1, TP1, RN1, SN1, and TN1) forming the first two-level converter9. Similarly to the first two-level power converter9, a configuration of the control system of the second two-level power converter13is described below. A second power factor regulator (APFR2)24is provided to output a d-axis DC current command (IC2_Dref) such that the power factor becomes 1 on the basis of reactive power computed from information provided by the main voltage-transformer terminal instrument voltage transformer17, and by a second instrument current transformer23provided between the second harmonic suppression filter14and the AC terminal. A second DC-voltage regulator (ADCVR2)26is provided to output a q-axis DC current command (IC2_Qref) such that a second instrument DC voltage transformer25detects a voltage VDCN in the negative-side DC capacitor12to regulate the voltage VDCN to a set value. A second two-level converter current regulator27executes on/off control on the gates to self-arc-extinguishing elements (RP2, SP2, TP2, RN2, SN2, and TN2) forming the second two-level converter13. According to the configuration of the first and second two-level power converters described above, two units of two-level converters (the first two-level converter9and the second two-level converter13) connected to the AC power supply and insulated from each other by two units of excitation voltage transformers (the first excitation voltage transformer11and the second excitation voltage transformer15) control the positive DC capacitor voltage VDCP and the negative DC capacitor voltage VDCN independently from each other. Therefore, even during a transition period such as at the occurrence of an accident in the system, balance between the voltages of two units of DC capacitors can still be maintained in a stable manner. According to the configuration of the invention described in the present embodiment, the two units of two-level converters can control their respective DC voltages independently from each other, and therefore can control the positive-side and negative-side DC capacitors so as to maintain balance between the values of these DC capacitors. Third Embodiment With reference toFIG.2, a device configuration according to a third embodiment of the present invention is described below. A bypass circuit48is provided between the excitation-current instrument current transformer34and the terminals of the rotor-side excitation winding6of the winding induction machine. It is allowable that the bypass circuit48is formed of power semiconductor elements. However, as illustrated in the present embodiment, it is also allowable to use a vacuum circuit breaker having achieved a remarkable technological progress, such as ensuring that the vacuum circuit breaker can properly operate 150k times. This bypass circuit is closed in accordance with an 86E command issued from the running-mode switching circuit41. In accordance with a GB command, the pulse generation circuits45,46, and47block the gates of the self-arc-extinguishing elements of the three-level NPC power converter7to stop the operation. FIG.6illustrates a circuit to output an operation command (86E command) for the bypass circuit48. A maximum-value selection circuit206selectively outputs the maximum value of the absolute values |IU|, |IV|, and |IW| of the excitation current values (IU, IV, and IW). When the maximum value exceeds a set value I3, a comparator207outputs a signal of level 1, or otherwise outputs a signal of level 0. The comparator207outputs a GB command and an 86E command via an OR circuit208. The set value I3is set larger than the set value I1(I3>I1). The reason for this is that while the value of overcurrent generated due to a ground fault or the like in the three-phase AC system1is reduced by impedance of the main voltage transformer2, the value of overcurrent generated at an occurrence of a fault in the winding induction machine of the main voltage transformer2is not reduced. The set value I3is set with reference to the maximum current generated due to a ground fault in the three-phase AC system1. Due to this setting, a fault in the device is distinguished from a fault in the three-phase AC system, so that when a fault has occurred in the device, the device can stop running immediately to be protected from the fault. Fourth Embodiment With reference toFIG.6, a device configuration and a circuit according to a fourth embodiment of the present invention is described below. Operations of output switches209,210, and211are described below. Hereinafter, an operation of a U-phase output switch209is described. A V-phase output switch210and a W-phase output switch211operate in the same manner as the U-phase output switch209, and therefore descriptions of the operations thereof are omitted to avoid redundant explanations. When |IU| is smallest, the signal111shows level 1 or otherwise shows level 0. The output switch209outputs |IU| that is an absolute value of the third-phase current when the signal111shows level 1, while outputting “0” when the signal111shows level 0. A maximum-value selection circuit212selectively outputs the maximum value of the absolute values |IU|, |IV|, and |IW| of the respective phase currents. When the maximum value selectively output by the maximum-value selection circuit212exceeds a set value I4, a comparator213outputs a signal of level 1, or otherwise outputs a signal of level 0. An on-delay circuit214outputs a signal of level 1 when the absolute value of the third-phase current is maintained for a set time or longer, and outputs a GB command and an 86E command via the OR circuit208. The set value I4is set smaller than the set value I1(I4<I1). The reason for this is that the third-phase current flows via any of the self-arc-extinguishing elements (UPC, UNC, VPC, VNC, WPC, and WNC). In general, since a self-arc-extinguishing element has a higher conduction loss than that in a diode connected in inverse parallel, the self-arc-extinguishing element has a lower overcurrent withstand capability. Due to this setting, time-limited overcurrent protection for the third phase enables the device to be safely protected from overcurrent. Fifth Embodiment With reference toFIG.2, a device configuration according to a fifth embodiment of the present invention is described below. When the positive-side DC capacitor voltage VDCP from the first instrument DC voltage transformer20exceeds a set value, a first overvoltage suppressor (OVP1)49executes on/off control on a switch circuit (CHV1)51formed of a self-arc-extinguishing element connected in series to a limiting resistance50such that the limiting resistance50consumes power so as to suppress an increase in the positive-side DC capacitor voltage VDCP. Similarly, when the negative-side DC capacitor voltage VDCN from the second instrument DC voltage transformer25exceeds a set value, a second overvoltage suppressor (OVP2)52executes on/off control on a switch circuit (CHV2)54formed of a self-arc-extinguishing element connected in series to a limiting resistance53such that the limiting resistance53consumes power so as to suppress an increase in the negative-side DC capacitor voltage VDCN. According to the configuration of the present invention, even when the second modulation commands (MU2, MV2, and MW2) are selected, the charging operation is still ensured for both the positive-side DC capacitor (CP)8and the negative-side DC capacitor (CN)12. This eliminates the need for a solution to a decrease in the DC voltage. Accordingly, it is only necessary to include a unit to suppress an increase in the DC voltage. Due to this configuration in which only a simple voltage suppression circuit is added, even at an occurrence of an accident in the system, the secondary magnetic excitation generator-motor device can still run continuously in a stable manner. However, in a case with the three-level NPC power converter, during a period for which the second modulation commands (MU2, MV2, and MW2) are selected, charging/discharging with the third-phase current becomes a factor of causing imbalance between the positive-side DC capacitor (CP)8and the negative-side DC capacitor (CN)12. However, the configuration of the present invention can reduce the positive-side DC voltage and the negative-side DC voltage independently from each other, so that the secondary magnetic excitation generator-motor device can achieve continuous and stable running even at an occurrence of an accident in the system. REFERENCE SIGNS LIST 1three-phase AC system2main voltage transformer3phase reverse disconnector (89GM)4synchronous circuit breaker (52G)5stator-side armature winding6rotor-side excitation winding7three-level NPC power converter8positive-side DC capacitor (CP)9first two-level power converter10first harmonic suppression filter11first excitation voltage transformer12negative-side DC capacitor (CN)13second two-level power converter14second harmonic suppression filter15second excitation voltage transformer16excitation circuit breaker (52E)17main voltage-transformer terminal instrument voltage transformer18first instrument current transformer19first power factor regulator (APFR1)20first instrument DC voltage transformer21first DC-voltage regulator (ADCVR1)22first two-level converter current regulator23second instrument current transformer24second power factor regulator (APFR2)25second instrument DC voltage transformer26second DC-voltage regulator (ADCVR2)27second two-level converter current regulator28instrument voltage transformer29automatic voltage regulator (AVR)30main voltage-transformer terminal instrument current transformer31automatic voltage regulator (APR)32phase sensor33two-phase/three-phase coordinates converter34excitation-current instrument current transformer35three-phase/two-phase converter36excitation current regulator37,38,39PWM modulation circuit40second PWM modulation circuit41running-mode switching circuit42,43,44switch45,46,47pulse generation circuit48bypass circuit49first overvoltage suppressor50,53limiting resistance51switch circuit (CHV1)52second overvoltage suppressor54switch circuit (CHV2)55rotational phase sensor (PLG)71DC voltage source101,102,103absolute value computation device104,105,106subtractor107,108,109,114,115,116comparator110,120logic circuit111,112,113,117,118,119signal121,122,123three-value selection output circuit201,206,212maximum-value selection output device202minimum-value selection output device203,204comparator205flip-flop208OR circuit209,210,211output switch214on-delay circuit | 24,879 |
11942874 | DESCRIPTION OF EMBODIMENTS Embodiments for implementing the present invention will be described in accordance with the accompanying drawings. Note that the same reference numerals will be assigned to portions which are identical or equivalent in respective drawings. Repetitive descriptions of the portions will be simplified or omitted as appropriate. Embodiment 1 FIG.1is a configuration diagram of an electric system to which a control system of a power converter in Embodiment 1 is applied. In the electric system inFIG.1, a plurality of DC power supplies1are provided outdoors. For example, the DC power supply1is a solar cell.FIG.1illustrates four DC power supplies1. An AC power supply2is operated by an electric power utility company, or the like. A distributed power supply conversion system3is connected between the plurality of DC power supplies1and the AC power supply2. The distributed power supply conversion system3includes a plurality of power converters4, a plurality of DC side switches5, a plurality of AC side switches7, an AC power supply side switch8and a control system9. Respective input units of the plurality of power converters4are connected to respective output units of the plurality of DC power supplies1. Each of the plurality of power converters4is provided so as to be able to convert DC power from each of the plurality of DC power supplies1into AC power. Each of the plurality of DC side switches5is connected between each of the plurality of DC power supplies1and each of the plurality of power converters4. Each of the plurality of DC side switches5is provided so as to be able to interrupt connection between each of the plurality of DC power supplies1and each of the plurality of power converters4when an overcurrent occurs between each of the plurality of DC power supplies1and each of the plurality of power converters4. Each of the plurality of AC side switches7is connected between each of the plurality of power converters4and the AC power supply2. Each of the plurality of AC side switches7is provided so as to be able to interrupt connection between each of the plurality of power converters4and each of a plurality of transformers6when an overcurrent occurs on respective AC sides of the plurality of power converters4. The AC power supply side switch8is provided between the plurality of AC side switches7and the AC power supply2. The AC power supply side switch8is provided so as to be able to interrupt connection between the plurality of AC side switches7and the AC power supply2when an overcurrent occurs between the plurality of AC side switches7and the AC power supply2. The control system9includes a plurality of control apparatuses10. The plurality of control apparatuses10are respectively provided at the plurality of power converters4. Each of the plurality of control apparatuses10includes a current control phase generating unit11and a carrier wave generating unit12. Each current control phase generating unit11generates a calculation result of an AC voltage phase for current control for the corresponding power converter4on the basis of an AC voltage of the AC power supply2. For example, each current control phase generating unit11generates a calculation result of an AC voltage phase for current control for the corresponding power converter4after calculating a d-axis voltage and a q-axis voltage on the basis of a U-phase voltage, a V-phase voltage and a W-phase voltage of the AC power supply2. The carrier wave generating unit12generates a calculation result of an AC voltage phase for generating a carrier wave for the corresponding power converter4on the basis of the AC voltage of the AC power supply2separately from the current control phase generating unit11. The carrier wave generating unit12generates a carrier wave on the basis of the calculation result of the AC voltage phase. For example, each carrier wave generating unit12generates a calculation result of the AC voltage phase for generating a carrier wave for the corresponding power converter4after calculating the d-axis voltage and the q-axis voltage on the basis of the U-phase voltage, the V-phase voltage and the W-phase voltage of the AC power supply2. The carrier wave generating unit12generates a carrier wave so that a phase of the carrier wave is in synchronization with the calculation result of the AC voltage phase for generating a carrier wave. An example of a method for generating a carrier wave will be described next usingFIG.2. FIG.2is a view for explaining an example of a method for generating a carrier wave by the control system of the power converter in Embodiment 1. InFIG.2, θSis a calculation result of the AC voltage phase for generating a carrier wave. θSis a periodic signal which changes between 0 and 2 π over time in a sawtooth waveform during an AC power supply period TS. A carrier wave c is calculated using the following expression (1). c=mod(NθS/(2π),1) (1) Here, N is a natural number. mod (NθS/(2π), 1) represents a remainder obtained by dividing NθS/(2π) by 1. mod (NθS/(2π), 1) satisfies the following expression (2). 0≤mod(NθS/(2π),1)<1 (2) In this event, c becomes a sawtooth wave which changes between 0 and 1 over time. A period of c is 1/N of a period of an AC voltage. Further, c=0 in a phase in which θS=0. In other words, a phase of c is in synchronization with the phase of the AC voltage. While a method for generating a carrier wave in which the phase of c is in synchronization with the phase of the AC voltage, and c becomes a sawtooth wave whose period is 1/N, has been described here, c may be calculated so as to be a triangle wave whose phase is in synchronization with the phase of the AC voltage and whose period is 1/N. Outline of the power converter4will be described next usingFIG.3. FIG.3is a configuration diagram of a power converter to which the control system of the power converter in Embodiment 1 is applied. As illustrated inFIG.3, the power converter4includes a U-phase upper switching element13a, a U-phase lower switching element13b, a V-phase upper switching element14a, a V-phase lower switching element14b, a W-phase upper switching element15aand a W-phase lower switching element15b. The U-phase upper switching element13aperforms switching operation on the basis of a gate signal gup. The U-phase lower switching element13bperforms switching operation on the basis of a gate signal gun. The V-phase upper switching element14aperforms switching operation on the basis of a gate signal gvp. The V-phase lower switching element14bperforms switching operation on the basis of a gate signal gvn. The W-phase upper switching element15aperforms switching operation on the basis of a gate signal gwp. The W-phase lower switching element15bperforms switching operation on the basis of a gate signal gwn. A method for generating a gate signal will be described next usingFIG.4. FIG.4is a configuration diagram of a control apparatus to which the control system of the power converter in Embodiment 1 is applied. As illustrated in (a) ofFIG.4, the control apparatus10includes a power control unit16, a first inverse dq transforming unit17, a U-phase proportional control unit18, a V-phase proportional control unit19, a W-phase proportional control unit20, a d-axis low-pass filter unit21, a q-axis low-pass filter unit22, and a second inverse dq transforming unit23. The power control unit16calculates a d-axis current command value id* and a q-axis current command value qd* on the basis of active power P and reactive power Q of the AC power supply2. The first inverse dq transforming unit17calculates a U-phase current command value iu*, a V-phase current command value iv* and a W current command value iw* on the basis of the d-axis current command value id* and the q-axis current command value iq* from the power control unit16, and a phase θ for current control from the current control phase generating unit11. The U-phase proportional control unit18performs proportional control on a deviation between the U-phase current command value iu* from the first inverse dq transforming unit17and a U-phase current actual value iuof the AC power supply2. The V-phase proportional control unit19performs proportional control on a deviation between the V-phase current command value iv* from the first inverse dq transforming unit17and a V-phase current actual value ivof the AC power supply2. The W-phase proportional control unit20performs proportional control on a deviation between the W-phase current command value iw* from the first inverse dq transforming unit17and a W-phase current actual value iwof the AC power supply2. The d-axis low-pass filter unit21applies a low-pass filter to a d-axis voltage actual value Vdof the AC power supply2. The q-axis low-pass filter unit22applies a low-pass filter to a q-axis voltage actual value Vqof the AC power supply2. The second inverse dq transforming unit23calculates a U-phase voltage reference value vuf, a V-phase voltage reference value vvfand a W-phase voltage reference value vwfon the basis of the d-axis voltage actual value from the d-axis low-pass filter unit21, the q-axis voltage actual value from the q-axis low-pass filter unit22, and the phase θ for current control from the current control phase generating unit11. The U-phase voltage command value vu* is generated by adding the U-phase voltage reference value vuffrom the second inverse dq inverse transforming unit and an output value of the U-phase proportional control unit18. The V-phase voltage command value vv* is generated by adding the V-phase voltage reference value vvffrom the second inverse dq inverse transforming unit and an output value of the V-phase proportional control unit19. The W-phase voltage command value vw* is generated by adding the W-phase voltage reference value vwffrom the second inverse dq inverse transforming unit and an output value of the W-phase proportional control unit20. As illustrated in (b) inFIG.4, the control apparatus10includes a U-phase comparing unit24, a U-phase logical negating unit25, and a U-phase deadtime generating unit26. The U-phase comparing unit24compares the U-phase voltage command value vu* with a value of a carrier wave based on the carrier phase generated by the carrier wave generating unit12. The U-phase logical negating unit25inverts the comparison result of the U-phase comparing unit24. The U-phase deadtime generating unit26outputs a gate signal gupin a case where the U-phase voltage command value vu* is greater than the value of the carrier wave. The U-phase deadtime generating unit26outputs a gate signal gunin a case where the U-phase voltage command value vu* is smaller than the value of the carrier wave. In this event, the U-phase deadtime generating unit26provides a deadtime for switching output between output of the gate signal gupand output of the gate signal gun. As illustrated in (c) ofFIG.4, the control apparatus10includes a V-phase comparing unit27, a V-phase logical negating unit28, and a V-phase deadtime generating unit29. The V-phase comparing unit27compares the V-phase voltage command value vv* with the value of the carrier wave based on the carrier phase generated by the carrier wave generating unit12. The V-phase logical negating unit28inverts the comparison result of the V-phase comparing unit27. The V-phase deadtime generating unit29outputs a gate signal gvpin a case where the V-phase voltage command value vv* is greater than the value of the carrier wave. The V-phase deadtime generating unit29outputs a gate signal gvnin a case where the V-phase voltage command value vv* is smaller than the value of the carrier wave. In this event, the V-phase deadtime generating unit29provides a deadtime for switching output between output of the gate signal gvpand output of the gate signal gvn. As illustrated in (d) ofFIG.4, the control apparatus10includes a W-phase comparing unit30, a W-phase logical negating unit31, and a W-phase deadtime generating unit32. The W-phase comparing unit30compares the W-phase voltage command value vw* with the value of the carrier wave based on the carrier phase generated by the carrier wave generating unit12. The W-phase logical negating unit31inverts the comparison result of the W-phase comparing unit30. The W-phase deadtime generating unit32outputs a gate signal gwpin a case where the W-phase voltage command value vw* is greater than the value of the carrier wave. The W-phase deadtime generating unit32outputs a gate signal gwnin a case where the W-phase voltage command value vw* is smaller than the value of the carrier wave. In this event, the W-phase deadtime generating unit32provides a deadtime for switching output between output of the gate signal gwpand output of the gate signal gwn. A main part of the control apparatus10will be described next usingFIG.5. FIG.5is a conceptual diagram of the main part of the control apparatus to which the control system of the power converter in Embodiment 1 is applied. At the control apparatus10inFIG.5, the current control phase generating unit11includes a current control dq transforming unit33, a current control filter unit34, and a current control PLL control unit35. The current control dq transforming unit33dq-transforms the AC voltage of the AC power supply2. The current control filter unit34applies a filter to the AC voltage which is dq-transformed by the current control dq transforming unit33. The current control PLL control unit35generates a phase for current control on the basis of the AC voltage to which the filter is applied by the current control filter unit34. The phase for current control is fed back to the dq transforming unit. At the control apparatus10inFIG.5, the carrier wave generating unit12includes a carrier dq transforming unit36, a carrier filter unit37, and a carrier PLL control unit38. The carrier dq transforming unit36dq-transforms the AC voltage of the AC power supply2. The carrier filter unit37applies a filter to the AC voltage which is dq-transformed by the carrier dq transforming unit36. The carrier PLL control unit38generates a calculation result of the AC voltage phase for a carrier on the basis of the AC voltage to which the filter is applied by the carrier filter unit37. The calculation result of the AC voltage phase for a carrier is fed back to the dq transforming unit. According to Embodiment 1 described above, carrier waves are respectively generated at a plurality of power converters4on the basis of the AC voltage of the common AC power supply2. Phases of the respective carrier waves are in synchronization with the phase of the common AC voltage. As a result, the phases of the respective carrier waves are in synchronization with each other. This synchronization does not require communication between the control apparatuses corresponding to the respective power converters4. It is therefore possible to synchronize carrier phases of the plurality of power converters4with a simpler and inexpensive configuration, so that it is eventually possible to prevent overflowing among the plurality of power converters4. Note that it is only necessary to generate a calculation result of the AC voltage phase for generating a carrier wave after applying a slower filter to the AC voltage of the AC power supply2. In this case, it is possible to minimize influence of a phase, a frequency, amplitude change, or the like, of the AC power supply2. As a result, even if a transient difference occurs in observation results of the AC voltage of the AC power supply2among the plurality of power converters4due to disturbance, or the like, of the AC power supply2, it is possible to keep synchronization of the carrier phases for the plurality of power converters4. Further, even if a frequency, a voltage, or the like, of the AC power supply2temporarily fluctuates, it is possible to generate a carrier wave which is stable during a certain period of time. In contrast, it is only necessary to generate a calculation result of the AC voltage phase for current control after applying a faster filter to the AC voltage of the AC power supply2. For example, it is only necessary to generate a calculation result of the AC voltage phase for current control after applying a filter faster than the filter for generating a calculation result of the AC voltage phase for generating a carrier wave, to the AC voltage of the AC power supply2. In this case, it is possible to achieve more favorable current control, so that it is eventually possible to follow change of a phase, a frequency, and the like, of the AC power supply2quickly. An example of the control apparatus10will be described next usingFIG.6. FIG.6is a hardware configuration diagram of the control apparatus to which the control system of the power converter in Embodiment 1 is applied. Respective functions of the control apparatus10can be implemented with a processing circuitry. For example, the processing circuitry includes at least one processor100aand at least one memory100b. For example, the processing circuitry includes at least one dedicated hardware200. In a case where the processing circuitry includes at least one processor100aand at least one memory100b, respective functions of the control apparatus10are implemented with software, firmware or combination of the software and the firmware. At least one of the software and the firmware is described as a program. At least one of the software and the firmware is stored in at least one memory100b. At least one processor100aimplements respective functions of the control apparatus10by reading out and executing a program stored in at least one memory100b. At least one processor100ais also referred to as a central processing unit, a processing apparatus, an arithmetic apparatus, a microprocessor, a microcomputer, or a DSP. For example, at least one memory100bis a non-volatile or volatile semiconductor memory such as a RAM, a ROM, a flash memory, an EPROM and an EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, or the like. In a case where the processing circuitry includes at least one dedicated hardware200, the processing circuitry is implemented with, for example, a single circuit, a complex circuit, a programmed processor, a parallelly programmed processor, an ASIC, an FPGA or combination thereof. For example, respective functions of the control apparatus10are respectively implemented at the processing circuitry. For example, the respective functions of the control apparatus10are collectively implemented at the processing circuitry. Part of the respective functions of the control apparatus10may be implemented at the dedicated hardware200, and the remaining part may be implemented at software or firmware. For example, functions of the current control phase generating unit11may be implemented at the processing circuitry as the dedicated hardware200, and functions other than the functions of the current control phase generating unit11may be implemented by at least one processor100areading out and executing the program stored in at least one memory100b. In this manner, the processing circuitry implements the respective functions of the control apparatus10by the hardware200, the software, the firmware or combination thereof. Embodiment 2 FIG.7is a conceptual diagram of a main part of a control apparatus to which a control system of a power converter in Embodiment 2 is applied. Note that the same reference numerals will be assigned to portions which are identical with or correspond to portions in Embodiment 1. Description of the portions will be omitted. At the control apparatus10in Embodiment 2, the carrier wave generating unit12generates a calculation result of the AC voltage phase for generating a carrier wave by correcting the phase for current control generated by the current control phase generating unit11. The carrier wave generating unit12includes a carrier zero-cross detecting unit39, a carrier proportional control unit40, and a carrier filter unit41. The carrier zero-cross detecting unit39detects a zero-cross point at the AC voltage of the AC power supply2. The carrier proportional control unit40calculates a correction amount of the carrier phase on the basis of the detection result of the zero-cross point by the carrier zero-cross detecting unit39and the carrier wave. The carrier filter unit41applies a filter to the calculation result of the AC voltage phase for current control generated by the current control PLL control unit35. The calculation result of the AC voltage phase for generating a carrier wave is generated by adding the correction amount from the carrier proportional control unit40to the calculation result of the AC voltage phase to which the filter is applied by the carrier filter unit. According to Embodiment 2 described above, the carrier wave generating unit12generates a carrier phase by correcting the phase for current control generated by the current control phase generating unit11. It is therefore possible to synchronize carrier phases of the plurality of power converters4with a simpler and inexpensive configuration in a similar manner to Embodiment 1, so that it is eventually possible to prevent overflowing among the plurality of power converters4. INDUSTRIAL APPLICABILITY As described above, the control system of the power converter according to the present invention can be utilized in an electric system. REFERENCE SIGNS LIST 1DC power supply2AC power supply3Distributed power supply conversion system4Power converter5DC side switch6Transformer7AC side switch8AC power supply side switch9Control system10Control apparatus11Current control phase generating unit12Carrier wave generating unit13aU-phase upper switching element13bU-phase lower switching element14aV-phase upper switching element14bV-phase lower switching element15aW-phase upper switching element15bW-phase lower switching element16Power control unit17First inverse dq transforming unit18U-phase proportional control unit19V-phase proportional control unit20W-phase proportional control unit21d-axis low-pass filter unit22q-axis low-pass filter unit23Second inverse dq transforming unit24U-phase comparing unit25U-phase logical negating unit26U-phase deadtime generating unit27V-phase comparing unit28V-phase logical negating unit29V-phase deadtime generating unitW-phase comparing unit31W-phase logical negating unit32W-phase deadtime generating unit33Current control dq transforming unit34Current control filter unitCurrent control PLL control unit36Carrier dq transforming unit37Carrier filter unit38Carrier PLL control unit39Carrier zero-cross detecting unitCarrier proportional control unit41Carrier filter unit100aProcessor100bMemory200Hardware | 22,833 |
11942875 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [PTL 1] JP 2016-181949 A As a power storage device that supplies electric power to the rotating electric machine, for example, only a first DC power supply may be provided without provision of a second DC power supply. In this case, when the windings of the respective phases are Y-connected and electric power is supplied to the rotating electric machine, switching drive such as PWM drive is performed on the first inverter, and the neutral point drive is performed on the second inverter. As compared with the neutral point drive, the switching drive causes great switching loss because of a large number of times of switching, per unit time, of the upper and lower arm switches constituting the inverters, which leads to accelerated deterioration of the upper and lower arm switches. Therefore, the first inverter and the second inverter become unbalanced in terms of the deterioration of the upper and lower arm switches. Such a problem rises not only in the case where electric power is supplied from the power storage device to the rotating electric machine, but is also common to the case where electric power is output from the rotating electric machine to the power storage device through power generation of the rotating electric machine. A technique capable of suppressing the unbalanced deterioration between in the first inverter and in the second inverter is desired. The present disclosure has been made in view of the above circumstances, and an object thereof is to provide a drive system capable of suppressing unbalanced deterioration between in a first inverter and in a second inverter. The present disclosure relates to a drive system for a rotating electric machine system, the rotating electric machine system including: a rotating electric machine including multi-phase windings, each of the multiphase windings having opposing first and second ends, and a power storage device performing at least one of a power receiving task and a power supplying task with respect to the rotating electric machine. The drive system includes: a first inverter that includes a first series circuit for each of the multi-phase windings, the first series circuit comprising an upper arm switch and a lower arm switch connected in series thereto, a first connection point between the upper arm switch and the lower arm switch for each phase winding being connected to the first end of a corresponding one of the multi-phase windings; a second inverter that includes a second series circuit for each of the multi-phase windings, the second series circuit comprising an upper arm switch and a lower arm switch connected in series thereto, a second connection point between the upper arm switch and the lower arm switch for each phase winding being connected to the second end of a corresponding one of the multi-phase windings; a selection unit that performs selection between a first setting and a second setting, the first setting representing that the first inverter is set to a switch drive inverter and the second inverter is set to a neutral-point drive inverter, the second setting representing that the second inverter is set to the switch drive inverter and the first inverter is set to the neutral-point drive inverter; and a drive control unit that performs: a switch drive task of performing on-off driving of the upper arm switch and lower arm switch of the switch drive inverter selected by the selection unit to thereby perform one of receiving of output power from the rotating electrical machine and supply of input power to the rotating electrical machine; and a neutral-point drive task of maintaining, in an on state, at least one of the upper arm switch and lower arm switch of the neural-point drive inverter selected by the election unit. In the drive system of the present disclosure, each of the first inverter and the second inverter is connected with the corresponding one of both ends of each phase wiring of the rotating electric machine, when at least one of a power receiving task and a power supplying task is performed between the power storage device and the rotating electric machine, selection between a first setting and a second setting is performed, the first setting representing that the first inverter is set to a switch drive inverter and the second inverter is set to a neutral-point drive inverter, the second setting representing that the second inverter is set to the switch drive inverter and the first inverter is set to the neutral-point drive inverter. As a result, it is possible to suppress unbalanced deterioration between the upper and lower arm switches in the first inverter and the upper and lower arm switches in the second inverter. First Embodiment Hereinafter, a first embodiment in which the drive system according to the present disclosure is applied to an in-vehicle rotating electric machine system100will be described with reference to the drawings. As shown inFIG.1, a drive system70according to the present embodiment includes a rotating electric machine10, a first inverter20, a second inverter30, and a control device50that controls the rotating electric machine10. The rotating electric machine10has functions of regenerative power generation and power running drive, and, specifically, is an MG (Motor Generator). The rotating electric machine10performs at least one of a power receiving task and a power supplying task with respect to a battery40. At the time of power running, the electric power supplied from the battery40gives a propulsive force to the vehicle, and, at the time of regeneration, the deceleration energy of the vehicle is used to generate electric power and outputs the electric power to the battery40. The rotating electric machine10has an open delta type three-phase winding11. The winding11is a multi-phase winding corresponding to each phase of U-phase, V-phase and W-phase. Each phase winding11includes a first winding portion12and a second winding portion13which are connected in series. A rotor of the rotating electric machine10is connected to drive wheels of the vehicle so as to enable power transmission. The rotating electric machine10is, for example, a synchronous machine. Each phase winding11of the rotating electric machine10is connected to the battery40, which is a DC power supply unit, via the first inverter20. The battery40is a rechargeable/dischargeable storage battery, specifically, an assembled battery in which a plurality of lithium ion storage batteries are connected in series. The battery40may be another type of storage battery. In the present embodiment, the battery40corresponds to the power storage device. Upper arm switches22(22A,22B and22C) are switching elements on a high potential side and lower arm switches23(23A,23B and23C) are switching elements on a low potential side. Each of upper arm switches22(22A,22B and22C) and the corresponding one of lower arm switches23(23A,23B and23C) constitutes a first series circuit, these first series circuits are connected in parallel, thereby to configure the first inverter20. At each phase, a first end of the winding11at the corresponding phase of the rotating electric machine10is connected to a connection point between the upper arm switch22and the lower arm switch23. In the present embodiment, voltage-controlled semiconductor switching elements are used as the switches22and23, and, more specifically, IGBTs are used. A freewheel diode24is connected to each of the switches in anti-parallel. Upper arm switches32(32A,32B and32C) are switching elements on a high potential side and lower arm switches33(33A,33B and33C) are switching elements on a low potential side. Each of upper arm switches32(32A,32B and32C) and the corresponding one of lower arm switches33(33A,33B and33C) constitutes a second series circuit, these second series circuits are connected in parallel, thereby to configure the second inverter30. At each phase, a second end of the winding11at the corresponding phase of the rotating electric machine10is connected to a connection point between the upper arm switch32and the lower arm switch33. In the present embodiment, voltage-controlled semiconductor switching elements are used as the switches32and33, and, more specifically, IGBTs are used. A freewheel diode34is connected to each of the switches in anti-parallel. The high potential side of the battery40and the high potential side of the first inverter20are connected by a first power supply wire LE1, and the low potential side of the battery40and the low potential side of the first inverter20are connected by a ground wire LG. Further, the high potential side of the first inverter20and the high potential side of the second inverter30are connected by a high potential side connection wire LU, and the low potential side of the first inverter20and the low potential side of the second inverter30are connected by a low potential side connection wire LD. Thus, the second inverter30is connected to the battery40via the first inverter20. In the present embodiment, the first power supply wire LE1and the ground wire LG correspond to a first connection wire. A drive changeover switch53is provided on the high potential side connection wire LU. In the present embodiment, a voltage-controlled semiconductor switching element is used as the drive changeover switch53, and, more specifically, an IGBT is used. A freewheel diode54is connected to the drive changeover switch53so that current flows from the second inverter30to the first inverter20in the forward direction. In the present embodiment, the drive changeover switch53corresponds to a third switch. The control device50acquires detected values from a voltage sensor51that detects power supply voltage Vbat of the battery40, a phase current sensor52that detects the current flowing through each phase winding11of the rotating electric machine10, and a rotation angle sensor (not shown) that detects the rotation angle of the rotating electric machine10, and the like, at the time of an operation in which power running or power generation of the rotating electric machine10is performed. Further, the control device50acquires detected values from a first temperature sensor58that detects a first temperature TM1which is the temperature of the first inverter20and a second temperature sensor59that detects a second temperature TM2which is the temperature of the second inverter30. The control device50controls the first inverter20and the second inverter30in order to control a controlled quantity of the rotating electric machine10to its command value based on the acquired detected values. The controlled quantity is, for example, torque. Specifically, in the control of the first inverter20, the control device50outputs a first drive signal SG1corresponding to each of the switches22and23to the switches22and23, in order to alternately turn the switches22and23into an on state (closed state) with a dead time in between. The first drive signal SG1takes either an on command to instruct exchanging to the on state of the switch or an off command to instruct exchanging to an off state (open state). Also, in the control of the second inverter30, the control device50outputs a second drive signal SG2corresponding to each of the switches32and33to the switches32and33, in order to alternately turn the switches32and33into the on state with a dead time in between. Further, the control device50acquires an operating state of the rotating electric machine10based on the acquired detected values. The operating state of the rotating electric machine10is, for example, a high-speed rotation state or a low-speed rotation state. The control device50generates a drive switching signal SKC and outputs the generated drive switching signal SKC to the drive changeover switch53, in order to perform the switching operation of the drive changeover switch53based on the acquired operation state. The control device50generates a first drive signal SG1and a second drive signal SG2so as to correspond to the generated drive switching signal SKC. Specifically, when the rotating electric machine10is in a high-speed rotation state, the drive changeover switch53is maintained in the on state, and the first inverter20and the second inverter30are driven by H-bridge. In the H-bridge drive, the first inverter20and the second inverter30are controlled by PWM performed drive so that the switches of different phases of the first inverter20and the second inverter30are synchronized. Hereinafter, the operation mode in which the first inverter20and the second inverter30are driven by H-bridge is referred to as a second mode. The PWM drive is intended to control the states of the upper and lower arm switches of each phase based on the comparison in magnitude between a target voltage, which is a target value of an output voltage to the rotating electric machine10, and a carrier signal such as a triangular wave signal. In the present embodiment, the PWM drive corresponds to switching drive. FIG.2shows a current path in the second mode at the time of power running of the rotating electric machine10. In the example shown inFIG.2, control is performed so that the U-phase upper arm switch of the first inverter20and the U-phase lower arm switch of the second inverter30, the V-phase lower arm switch of the first inverter20and the V-phase of the second inverter30of the upper arm switch, and the W-phase lower arm switch of the first inverter20and the W-phase upper arm switch of the second inverter30are synchronized. InFIG.2, the voltage sensor51, the phase current sensor52, and the like are not shown. The same applies toFIGS.3and4. As shown inFIG.2, when the upper arm switches22A and lower arm switches23B and23C of the first inverter20and the upper arm switches32B and32C and lower arm switch33A of the second inverter30are in the on state, current flows through paths indicated by arrows IH1to IH3. The paths indicated by the arrows IH1to IH3include the high potential side connection wire LU and the low potential side connection wire LD. Therefore, the second mode can be said to be an operation mode in which at least one of a power receiving task and a power supplying task with respect to the rotating electric machine10is performed via the high potential side connection wire LU and the low potential side connection wire LD. Also, when the rotating electric machine10is in a low-speed rotation state, the drive changeover switch53is maintained in the off state, and the first inverter20and the second inverter30are Y-connection-driven. In the Y-connection drive, one of the first inverter20and the second inverter30is controlled by the PWM drive, and the other is neutral point-driven. The neutral point drive is intended to maintain the upper arm switch on the side where the drive changeover switch53is provided in the on state, and to maintain the lower arm switch on the side where the drive changeover switch53is not provided in the off state, among the switches of the inverter involved. By the neutral point drive, the inverter involved serves as a neutral point, and the rotating electric machine10is Y-connected. Hereinafter, the operation mode in which the first inverter20and the second inverter30are Y-connection-driven is referred to as a first mode. FIG.3shows a current path in the first mode at the time of power running of the rotating electric machine10. In the example shown inFIG.3, the first inverter20on the battery40side is PWM-driven, and the second inverter30on the side opposite to the battery40is neutral point-driven. Specifically, in the first inverter20and the second inverter30, the PWM drive task of the switches22and23of the first inverter20is performed to preform supply of input power to the rotating electric machine10, and the neutral point drive task of maintaining the upper arm switch32of the second inverter30in the on state is performed. Therefore, the first mode can be said to be an operation mode in which at least one of a power receiving task and a power supplying task with respect to the rotating electric machine10is performed by the PWM drive and the neutral point drive. As shown inFIG.3, when the upper arm switches22A and lower arm switches23B and23C of the first inverter20and the upper arm switches32A,32B and32C of the second inverter30are in the on state, current flows through paths indicated by arrows IY1to IY3. As compared with the neutral point control, the PWM drive involves a large number of times of switching, per unit time, of the switches constituting the inverter, which leads to accelerated deterioration of the switches. Therefore, in the first mode in which the first inverter20and the second inverter30are Y-connection-driven, when the first inverter20is always PWM-driven and the second inverter30is always neutral point-driven, the first inverter20and the second inverter30are unbalanced in terms of the deterioration of the switches. The drive system70of the present embodiment includes a second power supply wire LE2, a first switch55, and a second switch56. The second power supply wire LE2connects the high potential side of the battery40and the high potential side of the second inverter30by a path different from that of the first power supply wire LE1and the high potential side connection wire LU. The first switch55is provided on the first power supply wire LE1, and the second switch56is provided on the second power supply wire LE2. In the present embodiment, voltage-controlled semiconductor switching elements are used as the switches55and56, and, more specifically, IGBTs are used. A freewheel diode57is connected to each of the switches55and56so that current flows from the corresponding inverter to the battery40in the forward direction. In the present embodiment, the second power supply wire LE2, the ground wire LG, and the low potential side connection wire LD correspond to a second connection line. In the first mode, the control device50performs, based on predetermined conditions, an exchange control processing to exchange the inverter on which the PWM drive is performed and the inverter on which the neutral point drive is performed, in the first inverter20and the second inverter30, the exchange control processing corresponds to selection between a first setting and a second setting, the first setting representing that the first inverter20is set to a PWM drive inverter and the second inverter is set to a neutral-point drive inverter, the second setting representing that the second inverter is set to the PWM drive inverter and the first inverter is set to the neutral-point drive inverter. In the exchange control processing, the control device50switches on one of the first switch55and the second switch56and switches off the other one. Specifically, in order to alternately turn the switches55and56into the on state with a dead time in between, a mode switching signal SMC corresponding to each of the switches55and56is output to each of the switches55and56. As a result, it is possible to suppress unbalanced deterioration of the switches between in the first inverter20and in the second inverter30. In the example shown inFIG.3, the first switch55is in the on state, and the drive changeover switch53and the second switch56are in the off state. In this case, the PWM drive task is performed using the first inverter20being switched on by the control device50, and the neutral point drive task is performed using the second inverter30being switched off by the control device50. Hereinafter, the Y-connection drive in which the first inverter20is PWM-driven and the second inverter30is neutral point-driven is referred to as a first Y-connection drive. FIG.4shows a current path in the first mode at the time of power running of the rotating electric machine10. In the example shown inFIG.4, the drive changeover switch53and the first switch55are in the off state, and the second switch56is in the on state. In this case, the PWM drive is performed on the second inverter30on the side of the second switch56controlled to the on state, and the neutral point drive is performed on the first inverter20on the side of the first switch55controlled to the off state. Hereinafter, the Y-connection drive in which the first inverter20is neutral point-driven and the second inverter30is PWM-driven is referred to as a second Y-connection drive. Therefore, the Y-connection drive includes the first Y-connection drive and the second Y-connection drive. As shown inFIG.4, when the upper arm switches22A,22B and22C of the first inverter20and the upper arm switches32A and lower arm switches33B and33C of the second inverter30are in the on state in the second Y-connection drive, current flows through paths indicated by arrows IY4to IY6. FIG.5shows a flowchart of exchange control processing. In the present embodiment, the flowchart of the exchange control processing at the time of power running of the rotating electric machine10is illustrated. The control device50repeatedly performs the exchange control processing at predetermined time intervals during the operation of the rotating electric machine10. When the exchange control processing is started, first, in step S10, it is determined whether the operation mode is the first mode. The operation mode is determined based on the operating state of the rotating electric machine10. If a negative determination is made in step S10, the exchange control processing ends. The control device50maintains the drive changeover switch53in the on state for switching to the second mode, and performs the second mode. On the other hand, if an affirmative determination is made in step S10, it maintains the drive changeover switch53in the off state and performs the first mode, in step S12. In the present embodiment, the processing in step S10corresponds to a mode control unit. In step S14, it is determined whether the Y-connection drive in the previous exchange control processing is the first Y-connection drive. The control device50stores therein the inverter which is PWM driven in the previous exchange control processing, and the control device50determines the Y-connection drive in the previous exchange control processing by the stored inverter. The previous exchange control processing is recent exchange control processing in which the Y-connection drive is performed, and, for example, means the previous exchange control processing when one of the first Y-connection drive and the second Y-connection drive is performed in the previous exchange control processing. If an affirmative determination is made in step S14, a first drive period YH1, which is a period during which the first Y-connection drive is continuously performed, is acquired in step S16. The control device50measures an elapsed period from the exchange between the first Y-connection drive and the second Y-connection drive, and acquires the elapsed period from exchanging from the second Y-connection drive to the first Y-connection drive as the first drive period YH1. In step S18, it is determined whether a predetermined reference period YK has elapsed in the first drive period YH1acquired in step S16. The predetermined reference period YK is a period during which it is possible to suppress an excessive temperature rise of the switches of the inverter which is PWM-driven by continuously performing the first Y-connection drive or the second Y-connection drive. In the present embodiment, the reference period YK corresponds to a predetermined period. If a negative determination is made in step S18, the exchange control processing ends. On the other hand, if an affirmative determination is made in step S18, the first temperature TM1is acquired using a first temperature sensor58in step S20. That is, the first temperature TM1of the first inverter20at which the PWM drive is performed in the first Y-connection drive is acquired. In step S22, it is determined whether the first temperature TM1acquired in step S22is higher than a predetermined threshold temperature Ttg. The predetermined threshold temperature Ttg is a temperature at which it is possible to suppress an excessive temperature rise of the inverter switches, and, specifically, is set to a temperature lower than the upper limit temperature of the switches. If a negative determination is made in step S22, the first Y-connection drive (S24to S28) is continued. Specifically, in step S24, the first switch55is maintained in the on state, and the second switch56is maintained in the off state. In the subsequent step S26, the PWM drive is performed on the first inverter20on the side of the first switch55controlled to the on state, and, in step S28, the neutral point drive is performed on the second inverter30on the side of the second switch56controlled to the off state. On the other hand, if an affirmative determination is made in step S22, the Y-connection drive is exchanged to the second Y-connection drive (S40to S44). Specifically, in step S40, the first switch55is switched off, and the second switch56is switched on. In the subsequent step S42, the neutral point drive is performed on the first inverter20on the side of the first switch55controlled to the off state, and, in step S44, the PWM drive is performed on the second inverter30on the side of the second switch56controlled to the on state. If a negative determination is made in step S14, a second drive period YH2, which is a period during which the second Y-connection drive is continuously performed, is acquired in step S32. The control device50acquires the elapsed period from the exchanging from the first Y-connection drive to the second Y-connection drive as a second drive period YH2. In the subsequent step S34, it is determined whether the predetermined reference period YK has elapsed in the second drive period YH2acquired in step S32. In the present embodiment, the processing in steps S16and S32corresponds to a drive period acquisition unit. If a negative determination is made in step S34, the exchange control processing ends. On the other hand, if an affirmative determination is made in step S34, the second temperature TM2is acquired using a second temperature sensor59in step S36. That is, the second temperature TM2of the second inverter30at which the PWM drive is performed in the second Y-connection drive is acquired. In the subsequent step S38, it is determined whether the second temperature TM2acquired in step S36is higher than the predetermined threshold temperature Ttg. In the present embodiment, the processing in steps S20and S36corresponds to a drive period acquisition unit. If a negative determination is made in step S38, the second Y-connection drive (S40to S44) is continued. On the other hand, if an affirmative determination is made in step S38, the Y-connection drive is exchanged to the first Y-connection drive (S24to S28). In the present embodiment, the processing in steps S22and S38corresponds to a selection unit, and the processing in steps S24to S28and S40to S44corresponds to a drive control unit. When the first Y-connection drive or the second Y-connection drive is performed, in step S30, the inverter on which the PWM drive is performed in the first Y-connection drive or the second Y-connection drive is stored, and the exchange control processing ends. Subsequently,FIG.6shows a transition between the first Y-connection drive and the second Y-connection drive in the exchange control processing. Here,FIG.6(a)shows a transition between the first Y-connection drive and the second Y-connection drive;FIG.6(b)shows a transition of the state of the first switch55;FIG.6(c)shows a transition of the state of the upper arm switch22of the first inverter20; andFIG.6(d)shows a transition of the state of the lower arm switch23of the first inverter20. Further,FIG.6(e)shows a transition of the state of the second switch56;FIG.6(f)shows a transition of the state of the upper arm switch32of the second inverter30; andFIG.6(g)shows a transition of the state of the lower arm switch33of the second inverter30. Further,FIG.6(h)shows a transition of the first temperature TM1, andFIG.6(i)shows a transition of the second temperature TM2. As shown inFIGS.6(a) to6(g), when the first Y-connection drive is started at time t11, the first switch55is maintained in the on state, and the PWM drive is performed on the switches22and23of the first inverter20. On the other hand, the second switch56is maintained in the off state, and the neutral point drive is performed on the switches32and33of the second inverter30. As compared with the neutral point drive, the PWM drive involves a larger number of times of switching, per unit time, of the switches constituting the inverter. As a result, the switches22and23of the first inverter20deteriorate faster than the switches32and33of the second inverter30. Further, as shown inFIGS.6(h) and6(i), the first temperature TM1rises from an initial temperature TS1, while the rise of the second temperature TM2from the initial temperature TS2is suppressed. When the first temperature TM1reaches the threshold temperature Ttg at time t12when the reference period YK has elapsed from the time t11, the Y-connection drive is exchanged from the first Y-connection drive to the second Y-connection drive. That is, the reference period YK can be said to be a period during which the temperature of the PWM-driven inverter reaches the threshold temperature Ttg by continuously performing the first Y-connection drive or the second Y-connection drive. When Y-connection drive is exchanged to the second Y-connection drive at the time t12, the first switch55is maintained in the off state, and the neutral point drive is performed on the switches22and23of the first inverter20. On the other hand, the second switch56is maintained in the on state, and the PWM drive is performed on the switches32and33of the second inverter30. Therefore, the deterioration of the switches22and23of the first inverter20is suppressed, as compared with the switches32and33of the second inverter30. As a result, it is possible to suppress unbalanced deterioration of the switches between in the first inverter20and in the second inverter30. Further, as shown inFIGS.6(h) and6(i), the second temperature TM2rises from the initial temperature TS2, while the first temperature TM1falls from the threshold temperature Ttg. As a result, excessive rise of the temperature of the switches in the first inverter20and the second inverter30is suppressed. When the second temperature TM2reaches the threshold temperature Ttg at time t13when the reference period YK has elapsed from the time t12, the Y-connection drive is exchanged again from the second Y-connection drive to the first Y-connection drive. After that, at time t14and the like, exchanging between the first Y-connection drive and the second Y-connection drive is repeated. According to the present embodiment described in detail above, the following effects can be obtained.In the drive system70of the present embodiment, when at least one of a power receiving task and a power supplying task is performed between the battery40and the rotating electric machine10, the inverter on which the PWM drive is performed and the inverter on which the neutral point drive is performed can be mutually exchanged, in the first inverter20and the second inverter30, that is, alternate selection between the first setting and the second setting is performed. As a result, it is possible to suppress unbalanced deterioration of the switches between in the first inverter20and in the second inverter30.Specifically, the first switch55is provided on the first power supply wire LE1that connects the high potential side of the battery40and the high potential side of the first inverter20.Also, the second switch56is provided on the second power supply wire LE2that connects the high potential side of the battery40and the high potential side of the second inverter30. One of the first switch55and the second switch56is controlled to the on state, and the PWM drive is performed on the inverter on the side of the switch controlled to the on state. Further, the other switch is controlled to the off state, and the neutral point drive is performed on the inverter on the side of the switch controlled to the off state. Therefore, of the first switch55and the second switch56, the switch to be controlled to the on state is mutually exchanged, thereby making it possible to exchange the inverter on which the PWM drive is performed and the inverter on which the neutral point drive is performed.In particular, in the drive system70of the present embodiment, the first switch55and the second switch56are voltage-controlled semiconductor switching elements, more specifically, IGBTs. Therefore, the switching speeds of the first switch55and the second switch56can be increased as compared with the case of relay switches, and the inverter on which PWM drive is performed and the inverter on which the neutral point drive is performed can be mutually exchanged rapidly.In the drive system70of the present embodiment, the high potential side connection wire LU and the low potential side connection wire LD for performing the second mode are provided. Further, the drive changeover switch53is provided on the high potential side connection wire LU, and maintained in the off state in the first mode. Therefore, among the switches constituting the inverter on which the neutral point drive is performed in the first mode, the upper arm switch is in a non-conducting state with the battery40, while the lower arm switch is in a conductive state with the battery40. Therefore, even when the lower arm switch is maintained in the on state, the inverter involved cannot serve as a neutral point.Therefore, in the drive system70of the present embodiment, when the neutral point drive is performed in the first mode, the upper arm switch on the side where the drive changeover switch53is provided is maintained in the on state, and the lower arm switch on the side where the drive changeover switch53is not provided is maintained in the off state. As a result, the inverter involved can appropriately serve as a neutral point.In the drive system70of the present embodiment, in the first mode, when the reference period YK has elapsed in the first drive period YH1and the second drive period YH2, the inverter on which the PWM drive is provided and the inverter on which the neutral point drive is performed are mutually exchanged, that is, alternate selection between the first setting and the second setting is performed. Therefore, it is possible to suppress unbalanced deterioration of the switches due to unbalanced period during which the PWM drive is performed in the first inverter20and the second inverter30.In the drive system70of the present embodiment, when the first temperature TM1and the second temperature TM2are higher than the threshold temperature Ttg, the inverter on which PWM drive is performed and the inverter on which the neutral point drive is performed are mutually exchanged, that is, alternate selection between the first setting and the second setting is performed. Therefore, it is possible to suitably suppress unbalanced deterioration of the switches due to an excessive temperature rise of the inverter on which the PWM drive is performed, in the first inverter20and the second inverter30. Second Embodiment Hereinafter, a second embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. The present embodiment is different in that the drive system70is provided with a second ground wire LG2instead of the second power supply wire LE2. The second ground wire LG2connects the low potential side of the battery40and the low potential side of the second inverter30and is a route different from the ground wire LG and the low potential side connection wire LD. In the present embodiment, the first power supply wire LE1is referred to as power supply wire LE, and the ground wire LG is referred to as first ground wire LG1. InFIG.7, the same contents as those shown inFIG.1above are designated by the same reference numerals for convenience, and the description thereof will be omitted. The present embodiment is different in that the drive system70includes a second drive changeover switch63, a third switch65, and a fourth switch66instead of the drive changeover switch53, the first switch55, and the second switch56. The second drive changeover switch63is provided on the low potential side connection wire LD. In the present embodiment, voltage-controlled semiconductor switching elements are used as the second drive changeover switch63, and, more specifically, an IGBT is used. The second drive changeover switch63is operated to be switched by a drive changeover signal SKC. A freewheel diode64is connected to the drive changeover switch63so that current flows from the first inverter20to the second inverter30in the forward direction. In the present embodiment, the second drive changeover switch63corresponds to the third switch. The third switch65is provided on the first power supply wire LG1, and the fourth switch66is provided on the second power supply wire LG2. In the present embodiment, voltage-controlled semiconductor switching elements are used as the switches65and66, and, more specifically, IGBTs are used. The third and fourth switches65and66are operated to be switched by the drive changeover signal SMC. A freewheel diode67is connected to each of the switches65and66so that current flows from the battery40to the corresponding inverter in the forward direction. In the present embodiment, the third switch65corresponds to the first switch, the fourth switch66corresponds to the second switch, and the power supply wire LE, the high potential side connection wire LU, and the second ground wire LG2correspond to the second connecting line. In the present embodiment, the third switch65is in the on state and the second drive changeover switch63and the fourth switch66are in the off state at the time of the first Y-connection drive in the first mode. In this case, the PWM drive is performed on the first inverter20on the side of the third switch65controlled to the on state, and the neutral point drive is performed on the second inverter30on the side of the fourth switch66controlled to the off state. Further, at the time of the second Y-connection drive in the first mode, the second drive changeover switch63and the third switch65are in the off state, and the fourth switch66is in the on state. In this case, the PWM drive is performed on the second inverter30on the side of the fourth switch66controlled to the on state, and the neutral point drive is performed on the first inverter20on the side of the third switch65controlled to the off state.According to the present embodiment described above, the third switch65is provided on the first ground wire LG1that connects the low potential side of the battery40and the low potential side of the first inverter20. Also, the fourth switch66is provided on the second ground wire LG2that connects the low potential side of the battery40and the low potential side of the second inverter30. One of the third switch65and the fourth switch66is controlled to the on state, and the PWM drive is performed on the inverter on the side of the switch controlled to the on state. Further, the other switch is controlled to the off state, and the neutral point drive is performed on the inverter on the side of the switch controlled to the off state. Therefore, of the third switch65and the fourth switch66, the switch to be controlled to the on state is exchanged, thereby making it possible to exchange the inverter on which the PWM drive is performed and the inverter on which the neutral point drive is performed.In particular, in the drive system70of the present embodiment, the third switch65and the fourth switch66are provided on the low potential side of the battery40. Therefore, since the potential applied to the third switch65and the fourth switch66is lower than that when these switches are provided on the high potential side of the battery40, the deterioration of these switches65and66can be suppressed. Third Embodiment Hereinafter, a third embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment and the second embodiment. The present embodiment is different in that the drive system70is provided with a second ground wire LG2in addition to the second power supply wire LE2. InFIG.8, the same contents as those shown inFIGS.1and7above are designated by the same reference numerals for convenience, and the description thereof will be omitted. The present embodiment is different in that the drive system70includes a second drive changeover switch63, a third switch65, and a fourth switch66in addition to the drive changeover switch53, the first switch55, and the second switch56. In the present embodiment, the drive changeover switch53is referred to as a first drive changeover switch53, and the ground wire LG is referred to as a first ground wire LG1. In the present embodiment, the first switch55and the third switch65are in the on state and the first drive changeover switch53, the second drive changeover switch63, the second switch56and the fourth switch66are in the off state at the time of the first Y-connection drive in the first mode. In this case, the PWM drive is performed on the first inverter20on the side of the first switch55and the third switch65controlled to the on state, and the neutral point drive is performed on the second inverter30on the side of the second switch56and the fourth switch66controlled to the off state. Further, at the time of the second Y-connection drive in the first mode, the first drive changeover switch53, the second drive changeover switch63, the first switch55and the third switch65are in the off state, and the second switch56and the fourth switch66are in the on state. In this case, the PWM drive is performed on the second inverter30on the side of the second switch56and the fourth switch66controlled to the on state, and the neutral point drive is performed on the second inverter20on the side of the first switch55and the third switch65controlled to the off state.According to the present embodiment described above, the first and third switches55and65are provided on the first power supply wire LE1and the first ground wire LG1that connect the battery40and the first inverter20. Further, the second and fourth switches56and66are provided on the second power supply wire LE2and the second ground wire LG2that connect the battery40and the second inverter30. One switch group of the first and third switches55and65and the second and fourth switches56and66is controlled to the on state, and the PWM drive is performed on the inverter on the side of the switch group controlled to the on state. Further, the other switch group is controlled to the off state, and the neutral point drive is performed on the inverter on the side of the switch group controlled to the off state. Therefore, of the first and third switches55and65and the second and fourth switches56and66, the switches to be controlled to the on state are exchanged, thereby making it possible to exchange the inverter on which the PWM drive is performed and the inverter on which the neutral point drive is performed.In particular, in the drive system70of the present embodiment, the first drive changeover switch53is provided on the high potential side connection wire LU, and the second drive changeover switch63is provided on the low potential side connection wire LD. In the first mode, the first drive changeover switch53and the second drive changeover switch63are maintained in the off state. Therefore, in the inverter on which the neutral point drive is performed in the first mode, both the upper arm switch and the lower arm switch can be maintained in the off state, and the current flowing in the inverter involved can be distributed to the upper arm switch side and the lower arm switch side. As a result, it is possible to suppress electric power loss in the inverter on which the neutral point drive is performed, as compared with the case where only one of the upper arm switch and the lower arm switch is in the off state. Other Embodiments Each of the above embodiments may be modified as follows and carried out.In each of the above embodiments, the exchange control processing at the time of power running of the rotating electric machine10has been described, but the exchange control processing may be performed at the time of power generation of the rotating electric machine10. Even at the time of power generation of the rotating electric machine10, the first mode and the second mode are mutually exchanged depending on the operating state of the rotating electric machine10, and in the first mode, the first Y-connection drive and the second Y-connection drive may be mutually exchanged based on predetermined conditions.In each of the above embodiments, as the predetermined conditions for exchanging between the first Y-connection drive and the second Y-connection drive in the first mode, the drive periods YH1and YH2during which the Y-connection drive is continuously performed and the temperatures TM1and TM2of the inverters20and30have been illustrated. However, the predetermined conditions are not limited thereto.For example, the first Y-connection drive and the second Y-connection drive may be mutually exchanged, that is, alternate selection between the first setting and the second setting is performed, each time when the operation of the rotating electric machine10is stopped. As a result, when the rotating electric machine10is stopped, the first Y-connection drive and the second Y-connection drive can be mutually exchanged. The time when the rotating electric machine10is stopped includes a period from when a stop command of the rotating electric machine10is issued to when the rotation of the rotating electric machine10is stopped and a stop period immediately before the rotating electric machine10starts to rotate after a start command of the rotating electric machine10is issued, not limited to the period during which the rotating electric machine10is stationary.Also, for example, the first Y-connection drive and the second Y-connection drive may be mutually exchanged, that is, alternate selection between the first setting and the second setting is performed, each time when the operation mode of the rotating electric machine10is switched to the first mode. As a result, the drive changeover switch53, and the first switch55and second switch56, can be mutually exchanged in synchronization, so that the exchange control processing can be simplified.Also, for example, the first Y-connection drive and the second Y-connection drive may be mutually exchanged, that is, alternate selection between the first setting and the second setting is performed, each time one of the power generation function of the rotating electric machine10and the power running function of the rotating electric machine10is switched to the other thereof. For example, the current path in the second Y-connection drive (see the arrows IY4to IY6inFIG.4) may be longer than the current path in the first Y-connection drive (see the arrows IY1to IY3inFIG.3). In this case, the first Y-connection drive having a relatively short path is performed at the time of power running of the rotating electric machine10, thereby making it possible to effectively suppress the electric power loss of the battery40and to suppress over discharge of the battery40.In each of the above embodiments, the examples in which the first switch55and the second switch56are IGBTs have been illustrated, but the first switch55and the second switch56may be MOSFETs. Further, because the first switch55and the second switch56are smaller in number of times of switching than the switches22and23of the first inverter20and the switches32and33of the second inverter30, the first switch55and the second switch56may be bidirectional switches, e.g., relay switches, having a lower switching speed than that of semiconductor switching elements. Since relay switches have a smaller on-resistance than that of semiconductor switching elements, it is possible to suppress electric power loss in the drive system70. Further, the first switch55, the second switch56, and the drive changeover switch53may be bidirectional switches. In each of the above embodiments, the PWM drive has been exemplified as the switching drive, but the present invention is not limited thereto. For example, rectangular drive may be performed. The rectangular drive is a drive to make control so that the upper and lower arm switches are turned on once each with a dead time in one cycle of electric angle, and the switching patterns of the upper and lower arm switches at each phase shift by 120°. Moreover, overmodulation drive may be carried out. The overmodulation drive is a drive to make control to keep the upper and lower arm switches at each phase in the on state over a plurality of carrier cycles so that the maximum value of the output voltage to the rotating electric machine10is 2/it times the power supply voltage Vbat of the battery40.In each of the above embodiments, the example in which the first mode and the second mode are mutually exchanged depending on the operating state of the rotating electric machine10has been illustrated, but the mode does not always have to be switched to the second mode. If the mode is not switched to the second mode, the second power supply wire LE2and the second ground wire LG2may be provided, and neither the high potential side connection wire LU nor the low potential side connection wire LD may be provided.The switches included in the first inverter20and the second inverter30are not limited to IGBTs, and may be, for example, MOSFETs. In this case, body diodes of MOSFETs can be used as the diodes reversely connected to the switches, and it is not necessary to use any freewheel diode separately from the MOSFETs.The rotating electric machine10is not limited to a three-phase rotating electric machine, but may be a two-phase or four-phase or more rotating electric machine. The first inverter20and the second inverter30may be any inverters having a serial connection circuit of upper and lower arm switches for the number of the phases of the rotating electric machine10. For example, in the case of two-phase rotating electric machine, a connection point between a first set of upper and lower arm switches connected in series to each other and a connection point between a second set of upper and lower arm switches connected in series to each other are connected via inductive load (for example, winding). Although the present disclosure has been described in accordance with the Examples, it is understood that the present disclosure is not limited to the Examples and structures. The present disclosure is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure. | 51,447 |
11942876 | DESCRIPTION OF EMBODIMENTS FIG.1is a configuration diagram of a power conversion device10according to an embodiment. As illustrated inFIG.1, the power conversion device10is provided so as to be interposed between a direct-current power supply device8and a power grid40. The power conversion device10includes a direct current-side relay12, a direct-current capacitor13, a power conversion circuit14, an alternating-current reactor15, an alternating-current capacitor16and an alternating current-side relay17. The power conversion device10further includes an instrument current transformer (CT)51, an instrument voltage transformer (VT)52, an instrument current transformer (CT)53, an instrument voltage transformer (VT)54and an instrument current transformer (CT). The power conversion device10further includes an MPPT controller18, a first subtractor19, a direct-current voltage controller20, a first adder21, a first coordinate conversion section22, a second subtractor23, a current controller24and a PWM drive circuit25. The power conversion device10further includes a phase-locked loop circuit (PLL circuit)30and a power control instruction value calculation section31. The direct current-side relay12is connected to the direct-current power supply device8. Direct-current input power from the direct-current power supply device8is supplied to a first end of the direct current-side relay12. The direct-current power supply device8may be, for example, a power supply that is either a solar panel or a storage battery or may include both of these power supplies. The storage battery may include any of various known secondary batteries or fuel batteries. The direct-current power supply device8may be formed by a wind power generator and an AC/DC converter device. The direct-current power supply device8may be any of various renewable energy power generation device. The power conversion circuit14is interposed between the direct-current power supply device8and the power grid40and forms a serial circuit jointly with the direct-current power supply device8and the power grid40. This power grid is also generally called a power system. The power system is a system for supplying power to power receiving facilities of consumers. The power system is a system integrating power generation, transformation, transmission and distribution. The power conversion circuit14performs conversion between direct-current power and alternating-current power. A direct-current end of the power conversion circuit14is connected to a second end of the direct current-side relay12. The power conversion circuit14is, for example, a three-phase voltage-type inverter circuit including a plurality of semiconductor switching devices. A first end of the direct-current capacitor13is connected to a wiring (for example, a busbar) between the direct current-side relay12and the power conversion circuit14. A second end of the direct-current capacitor13is connected to a reference potential such as a ground. The direct-current capacitor13is charged with a direct-current voltage VDCappearing on the direct-current side of the power conversion circuit14. The alternating-current reactor15is connected in series to an alternating-current end of the power conversion circuit14. A first end of the alternating current-side relay17is connected to the alternating-current reactor15. A second end of the alternating current-side relay17is connected to the power grid40. A first end of the alternating-current capacitor16is connected to a wiring (for example, a busbar) connecting the alternating-current reactor15and the alternating current-side relay17. A second end of the alternating-current capacitor16is connected to a reference potential such as a ground. The instrument current transformer (CT)51converts a direct current iDCinto an instrument value. The direct current iDCis a current flowing between the direct-current power supply device8and the power conversion circuit14. The instrument voltage transformer (VT)52converts the direct-current voltage VDCinto an instrument value. The direct-current voltage VDCis a voltage between the direct-current power supply device8and the power conversion circuit14and is a voltage of the direct-current capacitor13. The instrument current transformer (CT)53converts a three-phase alternating-current output current iACinto an instrument value. The three-phase alternating-current output current iACis a current flowing between the power conversion circuit14and the alternating-current reactor15. The instrument voltage transformer (VT)54converts a system voltage VGridinto an instrument value. The system voltage VGridis a three-phase alternating-current voltage between the alternating-current capacitor16and the power grid40. The instrument current transformer (CT)55converts a system current iGridinto an instrument value. The system current Grid is a three-phase alternating current between the alternating-current capacitor16and the power grid40. The direct current iDCand the direct-current voltage Vic are input to the MPPT controller18. The first subtractor19calculates a difference between an instruction value V*DCoutput by the MPPT controller18and the direct-current voltage VDC. The MPPT controller18maximally extracts direct-current power from the direct-current power supply device8by means of MPPT control. The direct-current voltage controller20performs direct-current voltage control based on a result of the subtraction by the first subtractor19. The first adder21adds up an output value of the direct-current voltage controller20and a d-axis current instruction value i*d. The d-axis current instruction value i*dis an instruction value output by a later-described power controller34. The first coordinate conversion section22performs dq-axes/abc-axes conversion, that is, coordinate conversion from two phases to three phases. The first coordinate conversion section22calculates a three-phase alternating-current instruction value i*ACbased on a result of the addition by the first adder21and a q-axis current instruction value i*q. The q-axis current instruction value i*qis an instruction value output by the later-described power controller34. The second subtractor23calculates a difference between the three-phase alternating-current instruction value i*ACand the three-phase alternating-current output current iAC. The current controller24calculates a current instruction value based on an output of the second subtractor23. The PWM drive circuit25generates a pulse width modulation signal (PWM signal) according to the current instruction value of the current controller24. The PWM drive circuit25transmits the PWM signal to the power conversion circuit14as a drive signal for the semiconductor switching devices. The PLL circuit30outputs a phase instruction value based on a system alternating-current voltage phase of the power grid40. The PLL circuit30outputs a phase instruction value θ* based on the system voltage VGrid, a d-axis system voltage Vdand a q-axis system voltage Vq. The d-axis system voltage Vdand the q-axis system voltage Vqare output from a later-described second coordinate conversion section32. A specific circuit of the PLL circuit30will be described later with reference toFIG.2. The power control instruction value calculation section31calculates a power control instruction value based on the phase instruction value θ* from the PLL circuit30. The power control instruction value is used for control of the power conversion circuit14. In the embodiment, more specifically, the power control instruction value includes the d-axis current instruction value i*dand the q-axis current instruction value i*q. The power control instruction value calculation section31calculates the d-axis current instruction value i*dand the q-axis current instruction value i*qbased on the phase instruction value θ* from the PLL circuit30, the system voltage VGrid, the system current iGridand the three-phase alternating-current output current iAC. The power control instruction value calculation section31may have a DC/AC conversion mode and an AC/DC conversion mode. In the DC/AC conversion, the power control instruction value calculation section31calculates the power control instruction value in such a manner that the power conversion circuit14converts direct-current power into alternating-current power. In the AC/DC conversion mode, the power control instruction value calculation section31calculates the power control instruction value in such a manner that the power conversion circuit14converts alternating-current power into direct-current power. The power control instruction value calculation section31includes the second coordinate conversion section32, a third coordinate conversion section33and the power controller34. The second coordinate conversion section32performs abc-axis/dq-axis conversion, that is, conversion from three phases to two phases. Consequently, the second coordinate conversion section32calculates the d-axis system voltage Vdand the q-axis system voltage Vqfrom the system voltage VGrid. The third coordinate conversion section33performs abc-axis/dq-axis conversion, that is, conversion from three phases to two phases. Consequently, the third coordinate conversion section33calculates a d-axis system current idand a q-axis system current iqfrom the system current iGrid. The power controller34calculates the d-axis current instruction value i*dand the q-axis current instruction value i*qbased on the above calculated values (Vd, Vq) from the second coordinate conversion section32and the above calculated values (id, iq) from the third coordinate conversion section33. In the below description, for convenience sake, suffix “k” for indicating a time series of control steps is provided to a phase difference θ. It is assumed that a phase difference calculated by the PLL circuit30in current control step k is a current phase difference θk. In this case, a phase difference calculated in previous step k−1, which is a step one step before, is represented by a previous phase difference θk−1. Also, a phase difference calculated in next control step k+1 is represented by a next phase difference θk+1. FIG.2is a diagram illustrating a configuration of the PLL circuit30according to the embodiment. As illustrated inFIG.2, the PLL circuit30includes a phase difference calculation section30a, a phase difference subtractor30b, a phase difference correction section30c, a feedback correction section30d, a second adder30eand a phase instruction value generation section30f. The phase difference calculation section30acalculates the phase difference θkin a predetermined control cycle (k−1, k, k+1, . . . ). The phase difference θkrepresents a deviation of the phase instruction value θ* from a system alternating-current voltage phase θVGridof the power grid40. The phase difference calculation section30acalculates the current phase difference θkbased on the d-axis system voltage Vdand the q-axis system voltage Vq. The current phase difference θkrepresents a degree of deviation of a system voltage phase from a preset reference phase. The phase difference subtractor30bcalculates a difference between the current phase difference θkand the previous phase difference θk−1stored in advance. In the embodiment, a difference value obtained by subtracting a value of one phase difference from a value of another phase difference is represented by θkdand is also simply referred to as “difference magnitude θkd”. The phase difference correction section30cis configured to perform correction of the difference magnitude θkdaccording to the value of the difference magnitude θkd. More specifically, if the difference magnitude θkdexceeds a predetermined reference value θth, the phase difference correction section30cadds a predetermined first correction amount θAto the current phase difference θk. Consequently, the corrected phase difference (θk+θA) is output. On the other hand, if the difference magnitude Oka does not exceed the reference value θth, the phase difference correction section30cdoes not add the first correction amount θAto the current phase difference θk. As a result, the uncorrected phase difference θkis output. The feedback correction section30dcalculates a second correction amount θthbased on the difference magnitude θkd. The second correction amount θfbis a feedback correction amount. As an example, the feedback correction section30dis configured to include a proportional control (P control) block and an integral control (I control) block. The second adder30eadds up an output value of the phase difference correction section30cand an output value of the feedback correction section30d. The phase instruction value generation section30foutputs the phase instruction value based on an output of the feedback correction section30d. More specifically, the phase instruction value generation section30fgenerates the phase instruction value θ* based on an output value of the second adder30e. Accordingly, the phase instruction value generation section30fis configured to output the phase instruction value θ* based on the current phase difference θk, the first correction amount θAand the second correction amount θth. Since correction using both the first correction amount θAand the second correction amount θfbis performed, both the following capability and control stability can be ensured. As described above, the power conversion device10according to the embodiment enables adding the first correction amount θAto the current phase difference θkonly if the difference magnitude θkdis increased and exceeds the reference value θth. On the other hand, if the difference magnitude θkdremains not exceeding the reference value θth, the first correction amount θAis not added. Therefore, the first correction amount θAcan freely be set to a proper value from the perspective of use only when there is an abrupt change of the system voltage phase. Consequently, the capability of following the system voltage phase θVGridcan be enhanced. As a result, an unintended increase of the direct-current voltage of the direct-current capacitor at the time of a system disturbance can be suppressed. Effects of the embodiment will more specifically be described below. According to the embodiment, a function that suppresses a direct-current voltage increase at the time of a system disturbance is provided in a system-connected inverter. When an inverter is connected, the phase on the power grid40side may abruptly change. In this case, there arise problems such as overvoltage occurring as a result of control failing to follow the abrupt change and the direct-current capacitor13being charged with a voltage from the system side. A typical PLL function is intended to measure a phase of a system voltage VGridand calculate a phase instruction value θ of an inverter so as to follow the phase. In the conventional techniques, upon occurrence of a system disturbance, the PLL circuit often fails to follow an abrupt phase change of a system voltage. If an inverter phase instruction deviates from the system voltage phase, no correct calculation for dq conversion is performed. As a result, no correct power control instruction value is calculated. In such case, depending on the phase instruction value θ*, a malfunction, such as the direct-current capacitor being charged from the power grid40side even in a case where the direct-current capacitor13should be discharged, may occur. Regarding this point, as illustrated inFIG.2, the PLL circuit30according to the embodiment includes the phase difference correction section30cat a stage following the phase difference calculation section30a. The phase difference correction section30C compares the previous phase difference θk−1and the current phase difference θkin terms of phase relationship. If the phase largely deviates, the first correction amount θAis added to the current phase difference θk. Consequently, it is possible to forcibly add an offset if the phase largely deviates. As a result, the following capability at the time of a system disturbance can be improved. As a result, the aforementioned direct-current voltage increase can be suppressed. REFERENCE SIGNS LIST 8direct-current power supply device10power conversion device12direct current-side relay13direct-current capacitor14power conversion circuit15alternating-current reactor16alternating-current capacitor17alternating current-side relay18MPPT controller19first subtractor20direct-current voltage controller21first adder22first coordinate conversion section23second subtractor24current controller25PWM drive circuit30PLL circuit (phase-locked loop circuit)30aphase difference calculation section30bphase difference subtractor30cphase difference correction section30dfeedback correction section30esecond adder30fphase instruction value generation section31power control instruction value calculation section32second coordinate conversion section33third coordinate conversion section34power controller40power gridiACthree-phase alternating-current output currentVDCdirect-current voltageVGridsystem voltageθ* phase instruction valueθAfirst correction amountθthsecond correction amountθk−1previous phase differenceθkcurrent phase differenceθkddifference magnitudeθthreference phase (reference value)θVGridsystem alternating-current voltage phaseθVGridsystem voltage phase | 17,448 |
11942877 | DETAILED DESCRIPTION The inventors of the present invention have devised, through research, experiments, and trials, that surface charge density, surface morphology/topology, dielectric property, etc. of triboelectric materials can affect the power output and stability of triboelectric generators. The inventors of the present invention have also devised, through research, experiments, and trials, that triboelectric generators with adhesion interfaces (between different triboelectric materials) tend to generate more surface charges than non-adhesion interfaces (between different triboelectric materials), but the adhesion interfaces require more energy than non-adhesion interfaces for separation. The inventors of the present invention have realized that the optimization of adhesion of the interface and surface charge density is an engineering problem that needs to be addressed. FIG.1schematically shows a triboelectric generator100in one embodiment of the invention. The triboelectric generator100is operable in at least a contact-separation mode (also referred to as “vertical contact-separation mode”). The triboelectric generator100includes a first triboelectric material layer102T and a second triboelectric material layer104T, which are made of different materials, i.e., materials with different rankings in the triboelectric series, or with different tendencies to gain or lose electrons. At least one of the first triboelectric material layer102T and the second triboelectric material layer104T is a dielectric material. A surface102TS of the first triboelectric material layer102T and a surface104TS of the second triboelectric material layer104T are arranged in facing relationship. The surfaces102TS,104TS are arranged to contact with and separate from each other to generate surface charges by virtue of the contact electrification. The surfaces102TS,104TS define a charge or electron transfer interface. The triboelectric generator100also includes a first electrode layer102E is attached to the first triboelectric material layer102T at a surface opposite to the surface102TS, and a second electrode layer104E attached to the second triboelectric material layer104T at a surface opposite to the surface104TS. The first electrode layer102E and the second electrode layer104E are arranged to be electrically connected via an electrical connection that provides an electron flow path. The electrical connection may have one or more electrical components (e.g., resistive, capacitive components). The first and second electrode layers102E,104E induce charges from the surfaces102TS,104TS by virtue of electrostatic induction. The potential difference between the first and second electrode layers102E,104E, generated as the surfaces102TS,104TS contact with and separate from each other, can drive charges (electrons) to flow through the electrical connection. The first electrode layer102E and the second electrode layer104E are made of metal or metal alloy, such as Ni/Ag, which may be in the form of a tape conductive on both sides. The first triboelectric material layer102T, and in particular the first surface102TS, is formed by a polymer material and an organic semiconductor material arranged in the polymer material. Without wishing to be bound by theory, the polymer material can be polymer with abundant —OH groups and the organic semiconductor material can be any organic semiconductor material, provided that the following criteria are met: (1) the polymer material (or polymer matrix) has a different solubility than the organic semiconductor material (which facilitates phase change during solvent evaporation); (2) one of the polymer material and the organic semiconductor material acts as a hydrogen bonding donor, another acts as a hydrogen bonding acceptor (desired intermolecular interactions); and (3) the organic semiconductor material, in the form of semiconductor molecules, has coplanar structure, pi-pi stacking, and C≡N functional group (which facilitates formation of surface topography after phase separation). In some embodiments, the polymer material is polyvinyl alcohol (PVA). The molecular weight of the PVA may be between 10,000 and 300,000, or between 60,000 and 200,000, although other values or ranges are also contemplated. In some embodiments, the organic semiconductor material is 7,7,8,8-tetracyanoquinodimethane (TCNQ). In some embodiments, the first triboelectric material layer102T is a TCNQ-PVA material, e.g., a TCNQ-PVA blend film, and the first surface102TS is a TCNQ-modified PVA surface, which is patterned or rough (e.g., nano or/micro meter scale surface roughness). The TCNQ-PVA material may have an uneven distribution of TCNQ, with a first phase, which includes the surface102TS, having a higher concentration of TCNQ than a second phase. The TCNQ-PVA material or blend film can be formed by facilitating phase separation (e.g., by film-casting, spin-coating, etc.) of a TCNQ-PVA solution containing 0.25 w/v % to 1 w/v %, 0.5 w/v % to 1 w/v %, 0.5 w/v % to 0.75 w/v %, 0.75 w/v % to 1 w/v %, about 0.5 w/v %, about 0.75 w/v %, or about 1 w/v % of TCNQ. Details of a film-casting operation in some embodiments of the invention is provided below. In some embodiments, the TCNQ-PVA material or TCNQ-PVA blend film may be made by: obtaining a TCNQ-PVA solution containing X w/v % TCNQ and facilitating phase separation (e.g., by film-casting, spin-coating, etc.) the TCNQ-PVA solution to obtain a TCNQ-PVA blend film, where X may be between 0.25-0.1, 0.5-0.1, 0.75-0.1, 0.5-0.75, about 0.75, about 1, or about 0.5. The TCNQ-PVA solution may be obtained by mixing TCNQ with a PVA solution (in accordance with the w/v %), preferably with stirring and/or heating, to obtain a homogeneous solution with a single mixed phase in solution form. the TCNQ and PVA solution. The PVA solution may be obtained by mixing PVA and water such as deionized water, preferably with stirring and/or heating. The mixing of PVA and water and the mixing of the TCNQ to the PVA solution can be performed as a one-step solution fabrication process. In some embodiments, the film-casting operation may include casting the TCNQ-PVA solution, e.g., placing the TCNQ-PVA solution in a container; and then drying, e.g., air-drying, the TCNQ-PVA solution to form a TCNQ-PVA material or TCNQ-PVA blend film. The formed TCNQ-PVA material or TCNQ-PVA blend film can be removed from the contained and, if necessary, cut into desired shape and/or size. In some embodiments, the air-drying is performed under a fume hood (i.e., placing the container with the TCNQ-PVA solution under a fume hood), which can provide a relatively fast evaporation speed to affect the phase separation process. Preferably, the fume hood has a face velocity of at least 0.35 m/s during the air-drying. The drying speed can be improved by performing low-temperature heating (e.g., heating at 60° C. or below). The second triboelectric material layer104T, in particular the second surface104TS, is formed by a relatively-tribo-negative material (relative with respect to the first triboelectric material of the first triboelectric material layer102T). In some embodiments, the second triboelectric material layer104T is formed by a tribo-negative material, such as silicone rubber or polydimethylsiloxane (PDMS). In some embodiments, the interface provided by the surfaces102TS,104TS is a substantially non-adhesion interface with no or negligible chemical bonding between the two surfaces102TS,104TS when they are in contact. The triboelectric generator100may further include a first substrate layer attached to the first electrode layer102E on a side of the first electrode layer102E opposite to the side connected with the first triboelectric material layer102T, and a second substrate layer attached to the second electrode layer104E on a side of the second electrode layer104E opposite to the side connected with the second triboelectric material layer104T. The first and second substrate layers may be made of polymers, such as polyethylene terephthalate (PET). The first substrate layer, the first electrode layer102E, and the first triboelectric material layer102T may form a first stack (stacked layers). The second substrate layer, the second electrode layer104E, and the second triboelectric material layer104T may form a second stack (stacked layers). The first and/or second stacks may be flexible. In some embodiments, the triboelectric generator100includes a mechanism that biases the triboelectric generator100in a separated configuration in which the surfaces102TS,104TS are spaced apart or separated. A force may be applied, e.g., by a user, to overcome the bias. In some other embodiments, the triboelectric generator100includes a mechanism that biases the triboelectric generator100in a contact configuration in which the surfaces102TS,104TS are in contact. A force may be applied, e.g., by a user, to overcome the bias. In yet some other embodiments, the triboelectric generator100includes a mechanism that cause relative motion of the surfaces102TS,104TS along a direction substantially perpendicular to the surfaces102TS,104TS, to facilitate consecutive contact and separation of the surfaces102TS,104TS. The relative motion may be periodic. In yet some other embodiments, the triboelectric generator100includes none of these mechanisms. FIG.2shows a simplified triboelectric series showing various tribo-positive and tribo-negative materials. The following description mainly uses PVA (and TCNQ-modified PVA) and silicone rubber as example of tribo-positive and tribo-negative materials. PVA can be used as a matrix, and it is non-toxic, biocompatible, may have desirable optical properties, and numerous hydroxyl groups suitable for some applications. If PVA and silicone rubber are used as tribo-positive and negative materials respectively, their contacting interface would provide a relatively strong adhesion, making them unsuitable for use as a tribo-material pair for triboelectric generators. In one embodiment the invention provides a facile solution fabrication process that leverages solvent-evaporation induced phase separation to alter the surface properties of a polymer material, which can be used as a triboelectric material. The polymer material may be modified by organic semiconductor molecules. In one embodiment, PVA is used as polymer material and TCNQ is used as organic semiconductor molecules to modify PVA. TCNQ has a different solubility compared with PVA, is a small organic semiconductor molecule, and can function as a strong electron acceptor owing to its abundant π electrons and CN groups. TCNQ is generally insoluble in water at room temperature but can be partially soluble at a higher temperature (e.g., 80° C.) to form a bluish mixture. When TCNQ is mixed with PVA at a higher temperature (e.g., 80° C.), the solubility of TCNQ is enhanced due to the significantly lower surface tension of PVA compared to water, the solubility of TCNQ is enhanced (in PVA vs in water) and a transparent dark greenish TCNQ/PVA blend can be obtained. FIG.3shows the molecular structures of PVA, TCNQ, and their interactions in a TCNQ/PVA blend film in one embodiment of the invention. TCNQ, as a hydrogen bond acceptor, tends to form various hydrogen bonding interactions with hydrogen bond donor PVA and water in the polymer blends, thereby forming one mixed phase at a higher temperature (e.g., 80° C.) in solution. FIG.4illustrates a method400of making a triboelectric material for a triboelectric generator in one embodiment of the invention. The method400begins in step402, in which a solution of an organic semiconductor material and a polymer material is obtained. Then, the method400proceeds to step404, in which the solution is film casted to obtain an organic semiconductor material—polymer material blend film, which can be used as a triboelectric material for a triboelectric generator. Without wishing to be bound by theory, the polymer material can be polymer with abundant —OH groups and the organic semiconductor material can be any organic semiconductor material, provided that the following criteria are met: (1) the polymer material (or polymer matrix) has a different solubility than the organic semiconductor material (which facilitates phase change during solvent evaporation); (2) one of the polymer material and the organic semiconductor material acts as a hydrogen bonding donor, another acts as a hydrogen bonding acceptor (desired intermolecular interactions); and (3) the organic semiconductor material, in the form of semiconductor molecules, has coplanar structure, pi-pi stacking, and C≡N functional group (which facilitates formation of surface topography after phase separation). FIG.5illustrates the preparation of the TCNQ/PVA blend film, as an exemplary implementation of the method400inFIG.4. In this example of the preparation, a 10% (w/v) PVA (Mowiol® 10-98, molecular weight: ˜61,000, Sigma-Aldrich) solution is prepared by dissolving 6 g of PVA in 50 mL of deionized (DI) at 80° C. under vigorous mechanical stirring for 2 hours. Then, X g of 7,7,8,8-tetracyanoquinodimethane (TCNQ, 98%, Sigma-Aldrich) are mixed with 10 mL of 10% (w/v) PVA solution to obtain X % (w/v) of TCNQ/PVA solution, where X is between 0.25-1. The solution is stirred at 80° C. and atmospheric pressure for 1 hour to obtain homogeneous solution. The blends are then casted in plastic petri-dish and dried, or air-dried, under a fume hood operating at a face velocity of 0.35 m/s overnight at room temperature and atmospheric pressure. The resulting film, which is flexible, is peeled off from petri-dish and cut into suitable size. Other volume and/or concentration of PVA may be used in other examples. In the method, when the homogeneous solution is subjected to film-casting, TCNQ with lower solubility tends to solidify first, due the difference in solubilities of PVA and TCNQ, and the interaction parameter χ23of TCNQ and PVA became stronger along with the decreasing temperature. As a result, TCNQ emerges ahead of (closer to the surface of) the PVA matrix under a certain water evaporation rate, triggering phase separation, resulting in the evolution of surface nano-/micro-structures or roughness, which is mainly controlled by the thermodynamic and chemical properties of the homogeneous TCNQ/PVA solution, in particular by Flory-Huggins interactions χ23associated with temperature change and composition concentrations. The coplanar molecule network of TCNQ is beneficial for the face-to-face π-π stacking, which is useful for stabilizing the phase-separated structure, as evidenced by the change in surface topographies with TCNQ ratio (0.25, 0.5, 0.75, and 1 w/v %). It should be noted that the above-described chemical volume, ratio, conditions (temperature, pressure, etc.), etc., described with reference toFIG.5could be different in other examples. The amount of PVA may be different, e.g., the molecular weight of PVA can be larger than about 60,000, e.g., at about 140,000 to about 190,000. In such case the w/v % of PVA in the preparation may not be 10%. The stirring and/or mixing temperature, pressure, and/or duration may be different. The drying or air-drying temperature, pressure, and/or duration may be different. TCNQ/PVA blend films with 0.25, 0.5, 0.75, and 1 w/v % TCNQ are prepared in accordance with the above method. A PVA-only film is also prepared in accordance with the above method (but without adding TCNQ). These films are tested and investigated to determine the role of TCNQ and the effect of phase separation on the surface properties, hydrophobicity, and surface morphology/roughness of the TCNQ/PVA blend films. FIG.6shows water contact angles of the formed PVA-only film and TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ). As shown inFIG.6, as the dosage of TCNQ increases from 0 w/v % to 0.5 w/v %, the water contact angle increases from 44° to 93°, and as the dosage of TCNQ further increases from 0.5 w/v % to 1 w/v %, water contact angle does not further increase. FIG.7shows the average surface roughness (Ra), root-mean-square (Rq) roughness, and peak-to-valley (Rz) roughness of the formed PVA-only film and the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ). As shown inFIG.7, the TCNQ loading or dosage affects the phase separation process and hence the surface roughness. As shown inFIG.7, the surface roughness increases when TCNQ increases from 0 w/v % to 1 w/v %, reaching a maximum at 0.5 w/v % TCNQ loading, where the micrometer-scale of Rzis more than ten-fold larger than that of Raand Rq. When TCNQ loading increases from 0.5 w/v % to 1 w/v %, no further increase in roughness is observed. This is in agreement with the water contact angle results. It has been found that introducing TCNQ in the PVA matrix affects the micrometer-scale roughness and the phase separation-derived morphology, and the intermolecular hydrogen bonding interactions between TCNQ and PVA contributes to the surface topography change in the nanometer-scale. FIG.8shows optical microscope images of the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ) and PVA-only film. It can be seen that surface nano-microstructures are formed on the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ) but not on the PVA-only film. The density or pattern density of the surface nano-microstructures increases as the amount of TCNQ increases. FIG.9shows a setup constructed using a mechanical tester for quantifying the vertical separation force at the adhesion interface (in this example, 2×2 cm2) of the corresponding surfaces of PVA-silicone rubber and corresponding surfaces of TCNQ/PVA-silicone rubber. The test results, i.e., the interfacial adhesion measure, are shown inFIG.10. As shown inFIG.10, at a ramping rate of 20 mm/min under relative humidity (RH) of 65% and 20° C., the maximum interfacial adhesion of the PVA-silicone rubber interface is as about 20 kPa, and the maximum interfacial adhesion of the TCNQ/PVA (0.25 w/v % of TCNQ)-silicone rubber interface is about 3.4 kPa. By further increasing the TCNQ loading in TCNQ/PVA blend film, non-adhesion interfaces with even less or substantially zero interfacial adhesion can be measured. FIG.11shows X-ray diffraction (XRD) patterns of the PVA film and the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ). By increasing the loading of TCNQ in TCNQ/PVA blend films, the intensity of diffraction peaks of TCNQ (JCPDS 33-1899) gradually increases, while the intensity of the characteristic peak of PVA at ˜19.6° corresponding to (101) crystalline phase decreases, which suggests that TCNQ affects the crystallinity of PVA. The decline in crystallinity with increasing TCNQ indicates the intermolecular interaction between TCNQ and PVA affects the packing of PVA chains. FIG.12shows attenuated total reflectance Fourier transform infrared (ATR-FTIR) spectra of the PVA-only film and the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ), which reveals the intermolecular interactions in the TCNQ/PVA blend films. Attributed to strong electron withdrawing capability of C≡N groups of TCNQ, the —OH bands of PVA shifts from 3270 to 3253 cm−1with increasing load of TCNQ, which is due to formation of hydrogen bonds (—C≡N . . . H—O complex) between hydroxyl and cyanide groups. The decrease in intensity of —OH bands, C—H bands (2910-2935 cm−1), and C—O bands (1089 cm−1) further verifies the strong interactions between PVA and TCNQ. While the C—H stretching bands at 860 cm−1belong to TCNQ, the characteristic C≡N stretching bands at 2138-2192 could not be observed, which confirms the hydrogen bonds between C≡N and —OH. The molecular interactions between TCNQ and PVA in the TCNQ/PVA blend films in turn affects the mechanical and thermal properties of the blend films. FIG.13shows the tensile stress-strain curves of the PVA-only film and the TCNQ/PVA blend films (with 0.25, 0.5, 0.75, and 1 w/v % TCNQ). The elongation at break of PVA (o %) is 240% and decreases as TCNQ loading increases, to 200%, 170%, and 133% for 0.25% and 0.5 w/v %, 0.75 w/v %, and 1 w/v % TCNQ/PVA blend films, respectively. FIG.14shows a triboelectric generator1400in one embodiment of the invention and its operation principle. The triboelectric generator1400includes a TCNQ/PVA blend film (0.5 w/v % TCNQ) as the tribo-positive material, silicone rubber as the tribo-negative material, Ni/Ag conductive tapes as the top and bottom electrodes attached to the TCNQ/PVA blend film and the silicone rubber respectively, and PET substrate attached to the Ni/Ag conductive tapes. In operation of the triboelectric generator1400, when TCNQ/PVA and silicone rubber are brought into contact, surface charges are generated at the interface due to the contact electrification, leaving positively charged TCNQ/PVA and negatively charged silicone rubber (state I). Benefiting from the adhesion-free interface, no extra work is needed to separate the two surfaces. Owing to the electrostatic induction, opposite charges induced at the electrodes drive electrons flow through the external circuit, generating a negative current signal (state II), until an equilibrium state is established when the two surfaces are fully separated (state III). Once the surfaces approach each other again under external stimuli, electrons on the electrodes flow in an opposite direction to reach a new equilibrium so as to generate a positive current (state IV). Alternating current (AC) signals are thus generated upon continuous (e.g., periodic) contact and separation. A triboelectric generator is fabricated based on the design of the triboelectric generator1400, with TCNQ/PVA blend film (0.5 w/v % TCNQ) and a size (surface area) of 3×3 cm2. In this prototype, the TCNQ/PVA material film and the silicone rubber layer (and the electrodes and substrates) have with dimension of 3×3 cm2. The TCNQ/PVA material film has an average thickness of ˜150 μm. The silicon rubber layer has a thickness of ˜180 μm. Double-sided conductive Ni/Ag tape are used as the electrodes, and polyethylene terephthalate (PET) (200 μm) is used as the substrate layers. The various tests below are performed on this triboelectric generator prototype (3×3 cm2, with TCNQ/PVA blend film (0.5 w/v % TCNQ)) unless otherwise specified. Tests are performed to determine the output characteristics (open-circuit voltage Voc, short-circuit current density Jsc, and short-circuit charge density Qsc) of the fabricated triboelectric generator. The tests are carried out under input force of ˜5 N at a frequency of 2 Hz. The test results are shown inFIGS.15-17. It is found that the device can generate an open-circuit voltage (Voc) of 520 V, short-circuit current density (Jsc) of 218 mA/m2, and short-circuit charge density (Qsc) of 110 μC/m2. Although not specifically illustrated, it has also been found that the magnitude of the open-circuit voltage Vocand of the short-circuit current density Jscare generally proportional to the device size (obtained by comparing triboelectric generator (TCNQ/PVA blend film with 0.5 w/v % TCNQ) of different sizes (1×1, 2×2, 3×3, and 4×4 cm2)). FIGS.18and19show output voltage and current density, and instantaneous peak power (density) of the triboelectric generator (TCNQ/PVA blend film with 0.5 w/v % TCNQ) at different external load resistances. As shown inFIG.18, with increasing load resistance from 20 kΩ to 342 MΩ, the output voltage of triboelectric generator gradually increases, while the current density gradually decreases. As shown inFIG.19, the maximum instantaneous peak power density calculated by P=I2R/area can reach as high as 41 W/m2(equivalent to 36.9 mW) at a load resistance of 1 MΩ. FIG.20shows the average power density of the triboelectric generator (TCNQ/PVA blend film with 0.5 w/v % TCNQ) at different external load resistances. As shown inFIG.20, as the load resistance increases from the order of kΩ to MΩ, the average power density (mW m−2Hz−1) generally increases, peaks at 19.4 mW m−2Hz−1at a load resistance of 1 MΩ. FIG.21shows charging of capacitors (1, 2.2, and 10 μF) using the triboelectric generator (TCNQ/PVA blend film with 0.5 w/v % TCNQ). By using triboelectric generator to continuously charge capacitors for only 30 s, capacitors of 1, 2.2, and 10 μF can reach 8.3, 6.0, and 1.3 V, respectively, with corresponding stored energy of 34.4, 39.6, and 8.45 μJ, respectively. FIG.22illustrates an application of the triboelectric generator2200(3×3 cm2, TCNQ/PVA blend film with 0.5 w/v % TCNQ and silicone rubber) for lighting up LEDs. As shown inFIG.22, 300 green LEDs (rated 0.06 W each) in serial connection are successfully lit up by manually tapping the triboelectric generator2200(to consecutively separate and contact the tribo-positive TCNQ/PVA layer and the tribo-negative silicone rubber layer). FIG.23Aillustrates applications of the triboelectric generator (3×3 cm2, TCNQ/PVA blend film with 0.5 w/v % TCNQ and silicone rubber) for powering an electronic watch (e-watch) through charging a 10-μF capacitor by manually tapping the triboelectric generator with a small force of 1˜2 N and a low frequency of 4 Hz. The voltage changes across the capacitor after three charging/discharging cycles of the e-watch and its snapshot at fully charged state are shown inFIG.23A. With the capacitor charged to 5 V, the e-watch can sustain operation for 6 s. FIG.23Billustrates applications of the triboelectric generator (3×3 cm2, TCNQ/PVA blend film with 0.5 w/v % TCNQ and silicone rubber) for powering a timer through charging a 10-μF capacitor by manually tapping the triboelectric generator with a small force of 1˜2 N and a low frequency of 4 Hz, andFIG.23Cshows the corresponding simplified circuit diagram forFIGS.23A and23B. FIG.24Aillustrates applications of the triboelectric generator (3×3 cm2, TCNQ/PVA blend film with 0.5 w/v % TCNQ and silicone rubber) for wirelessly powering LEDs, andFIG.24Bshows the corresponding simplified circuit diagram. As illustrated inFIG.24A, the triboelectric generator can wirelessly lit up LEDs using a power transmission circuit with two inductor coils arranged at a distance d (inductance L1=L2=35 pH, 10 turns, diameter of 14 cm). 24-serially-connected green LEDs can be wirelessly lit up at a transmission distance d of 2 cm and 17-serially-connected green LEDs can be wirelessly lit up at a transmission distance d of 5 cm. Significantly, the applications inFIGS.22to24Bdemonstrate that the triboelectric generator can serve as a biomechanical energy harvester, and may be an effective and high-performance wearable power source for wearable electronics by harvesting biomechanical energy. The embodiments of the invention have provided a blend film comprising a low dosage (less than 5 w/v %, preferably less than 1 w/v %) of organic semiconductor molecules and a water-soluble polymer matrix, which can be fabricated through a facile and scalable solution process. By optimizing the amount of organic semiconductor molecules in the polymer matrix, a triboelectric material with desirable interfacial properties can be obtained. The intermolecular hydrogen bonding interactions and nano/micro meter-scale surface roughness induced by phase separation in the fabrication method enables formation of a triboelectric material, or surface, that can interact with another triboelectric surface of different material, to form a substantially non-adhesion interface therebetween, to provide a corresponding triboelectric generator. Such triboelectric generator may supply sufficient power to drive small electronics, hence is a promising power source for wearable electronics. In some embodiments, the non-adhesion interface is resultant from intermolecular hydrogen bonding interactions and solvent-evaporation induced phase separation in the making process. The phase separation between the organic semiconductor and polymer matrix can induce nano/micrometer surface roughness, generating a micro-scale convex pattern topography, with increasing pattern density along with increasing loading of the organic semiconductor. The embedded organic semiconductor can change the hydrophilicity of the polymer matrix. The triboelectric generator of the present invention can be used as an energy harvester, in particular a biomechanical energy harvester, arranged to harvest daily human motions, such as jogging, running, and exercising. The harvested energy can be used to drive personal electronics so as to realize self-powered wearable electronics (e.g., without other power source). The triboelectric generator can be used as a wearable power source for powering various sensors for human healthcare monitoring, such as heart rate, blood pressure, breath analysis, and various other applications. It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments to provide other embodiments of the invention. Various (non-exhaustive) exemplary variations are set forth in the summary. The described embodiments of the invention should be considered in all respects as illustrative, not restrictive. | 29,328 |
11942878 | DETAILED DESCRIPTION Exemplary applications of apparatuses and methods according to the present disclosure are described in this section. These examples are being provided solely to add context and aid in the understanding of this disclosure. It will thus be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the present disclosure. Other applications are possible, such that the following examples should not be taken as limiting. In the following detailed description, references are made to the accompanying drawings, which form a part of the description and in which are shown, by way of illustration, specific embodiments of the present disclosure. Although these embodiments are described in sufficient detail to enable one skilled in the art to practice the invention, it is understood that these examples are not limiting; such that other embodiments may be used, and changes may be made without departing from the spirit and scope of the disclosure. As the term is used herein, “electroadhesion” refers to the coupling of two objects using electrostatic forces. Electroadhesion as described herein may use electrical control of these electrostatic forces to permit temporary and detachable attachment between two objects. This electrostatic adhesion holds two surfaces of these objects together by Coulomb attraction or by increasing the formation of Wenzel-Cassie domains between a device surface and a target surface. Wenzel-Cassie domain formation can be initiated or enhanced by increasing the surface energy of a microstructured surface. As utilized herein, the term “hierarchical microstructure”, when used to describe three-dimensional plastic webs, matrices of protrusions, porosities, and any surface geometrical modification which has been caused to conform to the surface of a three-dimensional forming structure so that both surfaces thereof exhibit the three-dimensional pattern of said forming structure, said pattern not readily visible to a normal human eye when the perpendicular distance between the viewer's eye and the plane of the microstructure is about 12 inches. It will be understood that the microstructures may be defined as any geometric shape and may include portions which are flat, rounded, spherical, pyramidal, pillar-shaped, or the like. The cross-section of a single microfeature of the microstructure may be circular, square, triangular, circular fluted, rectangular, or other geometric shape, including combinations thereof. In general, as utilized herein the term “macroscopic” is used to refer to structural features or elements which are readily visible to a normal human eye when the perpendicular distance between the viewer's eye and the plane of the web is about 12 inches. The present disclosure describes devices with a microstructured surface where part of the surface may comprise discrete areas of charge. In some embodiments, charge may be applied with a charge source and discrete electrodes embedded in a surface. In some embodiment, charge can also be generated environmentally. It will be understood that the application or development of a charge in one embodiment may be generated by multiple and/or different sources. One embodiment utilizing electroadhesivity is illustrated inFIG.1. An electroadhesive device100may include a charge source102which may be connected to electrodes104embedded in a dielectric substrate106. The charge source102may charge one half of the electrodes108with positive charge and the other half of the electrodes110with negative charge. When the power source is switched on, the powered electroadhesive device100may attract substrate112. Switching the charge source102off may cause substrate112and the dielectric substrate106to no longer be attracted to each other. Zinc is known to generate an electric potential when placed in a wet environment. Referring toFIG.2, an electro-microstructured device200may include a flat polymeric substrate202which may include complex-pillars204. The complex pillars204may be comprised of base pillars206and top pillars208. The base pillars206may be spaced in a triangular array with a pitch (center-to-center distance) of 50 microns. Base pillars206may have a vertical height210of 100 microns and a diameter212of 20 microns. The vertical surface of the base pillars206may include triangular-profiled fins214having a width of 5 microns. Top pillars208may have a diameter216of 2 microns and a vertical height218of 5 microns. The top pillars208may be disposed on the top surface of the base pillars206being arranged in a triangular array with a pitch of 4 microns. In some embodiments, base pillars206may be of two types, depicted as type A220and type B222. Type A220base pillars may include top pillars208disposed on the top surface, and further, the top surface224of the top pillars208may include zinc particulate deposits (0.1 to 1.0 microns in diameter). Type B222base pillars may include top pillars208disposed on the top surface, and further, the top surface224of the top pillars208may include silver particulate deposits (0.1 to 1.0 microns in diameter). The metal particulates may be adhered using a solution that may include the polymer substrate202, for example a solution of ethanol and non-crosslinked polyurethane polymer. When the device200is implanted in a body, the zinc may develop a voltage of −0.6 V and the silver may develop a voltage of +0.2 V. Type A and B pillars220,222may be spaced gap between each pillar of approximately 30 microns, which is determined by the pitch measured center to center of each pillar minus the diameter of each pillar (50 micron pitch−20 micron diameter), which may generate a field gradient of 26 kV/m. The adhesive forces may be found to be proportional to the square of the field gradient. The electroadhesive forces generated may be subject to the contact area between the electro-adhesive surface and the target surface, and also to the polarization property or dielectric constant of the target substrate. The contact area may be directly subject to the substrate surface textures of both surfaces, the electro-adhesive surface and target surface. As such, it may be necessary to take the substrate surface texture into consideration when developing the microstructure surface. One way to remove variability due to surface texture may be to construct the electroadhesive aspect on a multiplicity of scales, called hierarchical scaling. The microstructured electroadhesive surfaces of the present disclosure may adhere to both conductive and insulating surfaces. The principles of generating electroadhesive forces on conductive versus insulating substrate materials are different and are further detailed herein. Electroadhesion on conductive surfaces may be based on electrostatic induction as disclosed herein, whereas the electroadhesion on insulting surfaces may be due mainly to electrical polarization. The modelling of the electroadhesive forces on conductive substrates can be approximated by theories based on parallel capacitance, i.e., coplanar capacitance. The modelling of the electroadhesive forces on insulating substrates can be modelled by a complicated dynamic polarization process. In the embodiment depicted inFIG.2the electrodes of type A220and type B222may be exposed. The fluid interface may act as the dielectric layer between the electrodes of type A and type B pillars220,222. In cases where the fluid interface is substantially conductive, electrodes may be coated with a polymer solution that includes a suitable dielectric. For conductive substrates, Coulomb forces may be dominant if the volume resistivity of the dielectric material covering the electrodes is greater than approximately 1014 Ωcm. In comparison, Johnsen-Rahbek forces may be dominant if the volume resistivity is between approximately 1010 and 1012 Ωcm. Although a saturated electroadhesive force can be obtained for conductive substrates quickly (usually within 1 s), in some embodiments, a dynamic electrostatic attraction force generation process is desired. For example, in embodiments where short-term reversibility of the adhesion is desired, the reversibility may be obtained when the galvanic potential of the electrodes is slowed by tailoring the porosity of the dielectric and thus delaying the development of the galvanic potential. Embodiments as depicted inFIG.2, where the electrodes are not galvanic, but are externally charged, may allow for many dynamic functionalities. Electroadhesive devices of the present disclosure may use the electrostatic force between the target surface and the microstructured electroadhesive surface at the microscopic level. For Coulomb-type electrostatic surfaces, the electrostatic force may be generated by the dielectric polarization due to the electric potential difference. Based on the charge (or electrode) configuration, microstructured electroadhesive surfaces may be classified into two types: monopolar (plate-plate-capacitors) and bipolar (interdigitated electrodes). These basic electrode configurations may be disposed on a variety of hierarchical levels. When the electrodes are externally charged, then complex mixtures of these basic electrode configurations may further be possible. Referring now toFIG.3, an externally charged electro-microstructured device300comprising a flat polymeric substrate302may include complex-pillars304. The complex-pillars may be comprised of base pillars306and top pillars308. The base pillars306may be spaced in a triangular array with pitch (center-to-center distance) of 50 microns. Base pillars306may have a vertical height of 100 microns and may have a diameter of 20 microns. Additionally, the base pillars306may include triangular profile fins314having a diameter of 5 microns. Top pillars308may include a diameter of 2 microns a vertical height of 5 microns. The top pillars308may include a pitch of 4 microns center-to-center. In some embodiments, the top pillars308may be arranged in a triangular array. In some embodiment, base pillars306may include two types of pillars320,322. Base pillars306may include type A pillars320, which may comprise top pillars308disposed hierarchically thereon, and wherein the top surface324of the top pillars308may include a gold layer deposited thereon. Additionally, the top pillars308may further include conductors326which may be embedded in the substrate and traverse into the hierarchical complex. Base pillars306may further include type B pillars322, which may comprise top pillars308disposed hierarchically thereon, and wherein the top surface328of the top pillars308may include a gold layer deposited thereon. Additionally, the top pillars308may further include conductors332which may be embedded in the substrate and traverse into the hierarchical complex. In one embodiment, the flat polymeric substrate302may include deposited gold circular layer334which may be in contact with conductors336. In some embodiments, the gold layer may be coated or left exposed, or may include one area that is coated, and another area that is exposed. In some embodiments, the electrode configuration may be obtained by charging the gold layer of type A pillars and gold layer of type B pillars with a potential difference. In one embodiment, +0.5 V on conductors326and −0.5 V on conductors332may create a charge by the potential difference of the conductors. In another embodiment, conductors336can be charged differently from conductors charging the gold layer(s). When gold layers324and328develop a field gradient, the electrode configuration may be approximately monopolar. When gold layers324and328are charged differently, the electrode configuration may be bipolar. The electrode geometry and spacing as disclosed herein may act synergistically with the microstructured surface. In some embodiments, the microstructured surface is hierarchically stacked, which may provide the opportunity to layer electrodes in a monopolar configuration on different hierarchical levels. Within a hierarchical level, the electrodes may further be spaced in a bipolar configuration. For externally supplied charge, different regions of the electro-microstructured device may be monopolar and other regions bipolar. Monopolar type microstructured electroadhesive surfaces may generate adhesive forces. In this embodiment, one of the electrodes may contact the target surface where a second electrode is insulated from the target surface by a dielectric layer. The target surface may be conductive such that a capacitor is formed between the electrode and the conductive target surface. A bipolar type microstructured electroadhesive surface may typically be constituted by interlacing electrodes of two charged regions. In this embodiment, the electrodes may be insulated from the target surface by a dielectric layer. The space between the electrodes may be filled with an electrical insulator. For a microstructured device, a Wenzel-Cassie interface may be formed wherein air bubbles are trapped between electrodes. The air bubbles may act as insulators. In some embodiments, the trapped substance may be oil, attracted by a hydrophobic substrate. When the oil is trapped, e.g., between base pillars, it may act as an insulator and a dielectric. When alternating positive and negative charges are induced on the adjacent electrodes and the device is placed in contact with a target surface, the electric fields may produce opposite charges on the target surface and thus may cause electrostatic adhesion between the electrodes and the induced charges on the target surface. One important distinction of the monopolar configuration is that each hierarchical level may not be continuous. The configuration is advantageous because the non-continuity creates “holes” or gaps between the plates. This configuration may be counter-intuitive based on the prior art because the electric field may be highest in the dielectric between the two electrodes, not on the target surface to which the device contacts. The gaps may allow the electric field to essentially “leak” through to the target surface. This “leakage” may create a stronger electric field than the conventional bipolar design. This is because the hierarchical design may allow the gap between electrodes to be significantly decreased. Gap size may have a strong effect on adhesion force per unit area. In this configuration, smaller gaps may be possible because the hierarchical design may allow for a dielectric with a high voltage breakdown constant compared to a standard bipolar design. Further considerations as to the gap size between electrodes is dependent on any residual material, external particles, and trapped air in the gaps. Because of the susceptibility of the gaps to these issues, the addition to the surface of microstructures may play an important role. By designing the microstructure to have a particular juxtaposition of surface energies, interface constituents can be attracted or repelled. Generally, the prior art has relied on electrode structure as being macroscopic, typically greater than several millimeters. In such macroscopic designs, the electroadhesive stresses and energy can be estimated by empirical equations. However, these equations fail at the microstructured level. Furthermore, there is a lack of theoretical models to reveal the relationship between the adhesive force and the microstructure parameters, which are disclosed herein. Optimal design principles are unavailable for electroadhesive and electrorepulsive devices as used in the prior art. Some progress has been made on the electrostatic-levitation problem, but this model applies to macroscopic electrodes. When microscopic electrodes are involved, one must pay particular attention to optimization of the electric charging rate with respect to the geometrical parameters of electrodes, if one's goal is to create a surface that is cyclically electroadhesive and non-electroadhesive. One example may include the development of a foot surface of a wall-climbing robot. It will be understood that the following examples may employ four-layer and five-layer hierarchical textures, although in practice any number of layers (so long as hierarchical) may be sufficient for most applications. With regards to electroadhesion on a conductive target surface, an electrostatic induction phenomenon may occur where the formation of negative charges on one side and positive charges on the opposite side of a target conductor may be induced by an external electrostatic field produced by a charged electrode embedded in an insulator comprising the microstructured surface. It will be understood that “conducting materials” may generally refer to materials consisting of a large amount of mobile free charge carriers. In some embodiment, wet tissue may cause the concentration of free mobile charge carriers to be of the same order as that of the number of molecules. These charges may rearrange themselves quickly and easily. Equal and opposite charges may be induced on the surface of a target conductive substrate after the application of a high field gradient on the electro-microstructured surface/device. The electroadhesive forces between the device and the target surface may then be formed. In some embodiment, the electro-microstructured device may be monopolar, bipolar, and/or even tripolar. In the prior art, the dipole design has generally been the most frequently used design in electroadhesive applications. For coulomb type dipolar electro-microstructured devices, the electroadhesive forces between the device and the target substrate may be derived from a series of parallel connections of several ideal capacitors having dielectrics in series. Specific attention may be paid to particular parameters to effectively product the electroadhesive forces including the air gap between the device and the target substrate, the dielectric thickness, the capacitances of the dielectric material, the capacitance of the interface between the dielectric and the target substrate surface. The total capacitance between the device and target substrate, and between the pad and substrate, may depend on the number of electrodes, the effective electroadhesive area, the permittivity of the interface volume and the relative permittivity of the dielectrics. The electroadhesive force varies as the square of the total capacitance. The Johnsen-Rahbek force occurs when imperfect dielectrics with finite volume resistivity, such as semi-conductive materials interact with high charge mobility target substrates. Current leakage or charge transfer may occur through the contacting points between the device and the target substrate. In some embodiments, a strong electrostatic attractive force may be generated at the interface by the accumulation of charge in the non-contact areas. The small gaps characteristic of hierarchical microstructures surfaces may be responsible for these strong Johnsen-Rahbek adhesion forces. The adhesion of a Johnsen-Rahbek electro-microstructure device may depend on the potential difference applied across the interface, rather than a field gradient applied through the dielectric layer. Johnsen-Rahbek electrostatic attractive force is independent of the dielectric material between the device and target substrate. Particular parameters that may be identified to producing these forces in microstructured devices may include the capacitance of the non-contact areas, the potential difference across the interfaces, and the potential difference across the non-contacting areas. In some embodiments, the stacked hierarchical structure may be optimal for both gap placement and electrode placement. Generally, adhesion due to the Coulomb potential may be much smaller than the Johnsen-Rahbek force, especially in embodiments where the interface gap is smaller than the thickness of the dielectric material. In embodiments for cyclic adhesive devices, the detachment time may be much faster when the Coulomb force is utilized. Additionally, less current leakage in the Coulomb configuration may result in lower power consumption. In some embodiments, the electro-microstructured device may involve the total polarization comprising the sum of the electronic polarization, the ionic polarization, the orientational polarization, the space charge polarization, the hopping polarization, the interfacial polarization, the spontaneous polarization, and other types of polarizations such as the nomadic polarization. For embodiments with contacting electro-microstructured devices, the orientational polarization and interfacial polarization may account for generation of the electroadhesive forces. The electroadhesion phenomenon can be contactless both on conductive substrates and insulating substrates. For embodiments with non-contacting electro-microstructured devices, the atomic and electric polarization may account for the generation of the electroadhesive force. It should be understood that in devices of the current disclosure, electroadhesion may strengthen over time. The steady state value of the adhesion force may generally be much larger than the initial value. The time period to reach the steady state value may depend on various design parameters. Embodiments which include particular monopolar electrode geometry, the electrodes may generally be arranged in a spatially periodic pattern. Generally, the length of the electrode may be much larger than its width and/or thickness, and the electrode area may be much larger than the area between individual electrodes. For this reason, symmetric patterns may be preferred in some embodiments. One of skill in the art will appreciate the inclusion of hierarchical structures in the various embodiments of this disclosure. Analyzing the performance of a hierarchically structured electroadhesive device, one may consider each hierarchical scale as an added layer and performs calculations as if the device were a composite device with an effective dielectric constant. The effective dielectric constant may be evaluated by the parallel mixing rule. The calculation reveals that electroadhesion may be reduced as the height of each hierarchical layer increases. Therefore, in some embodiments, the height of the hierarchical layers may decrease as the dimensions decrease, thus more layers may increase the electroadhesion properties of the device. Some embodiments may combine the electroadhesive force with the van der Waals force of the microstructured surface to generate a strong adhesion. The microstructures having dimensions down to the micro or even nanoscale may generate strong adhesive forces. Therefore, the very smallest structures may not only decrease the gap between the device and target surface, but also enhance the attraction force in absolute terms. In one embodiment an electroadhesive device may be capable of generating both electroadhesive and van der Waals forces. Another parameter that may be of use is the inclusion of semi-conductive materials for an insulation layer or a microstructure substrate which may enhance the electrostatic clamping forces at lower electrical field levels. This increased clamping force may be attributable to the Johnsen-Rahbek effect that may take place at the boundary between the metal electrode and the surrounding semi-conductive material. Accordingly, lower voltages and currents can be used to achieve the same clamping forces when using a semi-conductive insulator rather than a fully dielectric insulator. Although it is known that polyurethanes work well as semi-conductive materials, various other materials may also be used. These other semi-conductive materials may typically have a bulk resistivity that ranges from about 107 to 1013 Ωm, with a more preferable range being about 109 to 1012 Ωm. Various polyurethanes, nitrile halogenated or latex rubbers, and certain silicones, for example, may be used as a suitable insulating material for some embodiments of the disclosed electroadhesive devices. One example of a material that works well is the Deerfield polyurethane PT7811. In some embodiments, additive particles, dopants, and/or solutions may be included to enhance the conductivity of an otherwise insulating polymer. These additive particles may include, but are not limited to, carbon, quaternary salts, and plasticizers such as Dioctyl Phthalate or DilsoOctyl Phthalate. In one embodiment using such material, it may be able to achieve clamping forces up to about 70 psi. In one embodiment that utilizes a coating over the electrodes rather than a full insulating layer, the coating may be of about 10 to 30 micrometers thick. In other embodiments, the use of semi-conductive insulators may allow for the use of insulating layers that may be up to 100 microns thick. In various embodiments, the insulation material may include a compliant material with an elastic modulus less than about 1 GPa, which may facilitate better clamping. In addition to the use of highly resistive materials in some embodiments of the disclosed adhesive devices, semiconducting materials with different properties may also provide benefits when applied as the electrodes themselves. In one embodiment, various polyurethanes or other materials may be used at least on the surfaces of one or more electrodes. For embodiments with highly resistive electrodes, a static-dissipating conductive strip material may have a surface resistivity ranging from about 0.1 to 1000 MΩ/square, a thickness of about 1 to 50 micrometers, be relatively inexpensive and readily available, and be mechanically and electrically robust. More preferably, the surface resistivity may range from 1 to 100 MΩ/square. It is contemplated that one embodiment may include carbon particles mixed with relatively soft polyurethanes. Such polyurethanes can be sprayed on, dip coated, or otherwise applied to the appropriate electrode surface in any suitable manner. Other alternatives for electrode materials may utilize nanotubes, which may be conductive at much lower loading levels. Still another option may include graphite electrodes with a thin coating as a sealing layer that may be applied, such as by spraying. Embodiments with this sealing layer may include very low carbon black loading, or in some embodiments none at all. Other options may involve adding a plasticizer or a soft polyurethane blended in tetrahydrofuran. Diisooctyl phthalate may also be used as a polyurethane plasticizer. Various specific examples of materials that have been found to work well include Dupont 100XC10E7, Scicron ABF-300, and TMF-300 materials. The following are embodiments which may be directed to the design of electro-microstructured surfaces. These embodiments are not meant to be exhaustive, but rather examples of the principles disclosed to guide one in the practice of this patent. Example 1. Tissue Scaffold with Electro-Selection of Cell Type Biomaterials are widely used in the medical field to maintain, improve, and/or restore diseased tissues or organs. The successful integration of biomaterials with host tissue may depend on substratum surface properties, as well as host tissue quality and the surrounding environment. The embodiment defined more fully below may utilize these various factors to allow better incorporation of the host tissue and biomaterial. Referring toFIG.4, a tissue scaffold400may include microstructured pillars402arranged on a polymer substrate404. The microstructured pillars402may be arranged in rows. In some embodiment, the rows of microstructured pillars402may further include smaller pillars406disposed between two opposing rows of microstructured pillars. Two opposing rows of microstructured pillars402may include a spacing of approximately 10 microns408abetween the two rows. Additionally, the microstructured pillars402within the same row may also be spaced approximately 10 microns apart,408b. Microstructured pillars402may include an interior portion410which may include electrodes412along the centerline of the microstructured pillars as shown inFIG.4A. Some electrodes412may be electrically connected by conductors414,416. The conductors414may have a positive potential, and the conductors416may have a negative potential, thereby a field gradient may be created in region418located between the two opposing rows of microstructured pillars402. The opposing rows of microstructured pillars402may be positioned such that a symmetry relation is created, as illustrated by squares420,422, and424. Within each square is a Y-shaped configuration426with base428and left bifurcation430and right bifurcation432. Left and right bifurcations may connect to an adjacent base as illustrated at434, thus creating a repetitive pattern on the polymer substrate404. In some embodiments, microstructured pillars404may be approximately 10 microns tall and approximately 3 microns in diameter with a circular cross section. Smaller pillars406may be approximately 3 microns tall and approximately 1 micron in diameter with a circular cross section. In one embodiment, open region436of the substrate surface404may be populated with ridges438, and wherein the ridges may be approximately 10 microns tall and approximately 3 microns in thickness with a rectangular cross section. In some embodiments, cells disposed about the periphery440of the tissue scaffold400may be caused to move along the pathways411between opposing rows of microstructured pillars402. In some embodiments, the Y-shaped configuration426may encourage the formation of blood vessels by endothelial cells. Example 2. A Contactless Brake Utilizing Reversible Wenzel-Cassie Domain Creation Referring toFIG.5, a braking system500may include a braking element502and a rotating element512. Braking element502may include with a surface that comprises a first hierarchical level504, a second hierarchical level506, and a third hierarchical level508. In some embodiments, the first hierarchical level504may have a square cross-section. In some embodiments, the second hierarchical level506may have a circular cross-section. And in some embodiments, the third hierarchical level508may have a circular cross-section. In some embodiments, the braking element502may include two or more bearing channels510. In some embodiments, rotating element512may include a surface that may be smooth. In other embodiments, rotating element512may include a surface with microstructures disposed thereon. In some embodiments, the rotating element512may include a surface with both a smooth portion and a microstructured portion. In some embodiments, the rotating element may include at least two bearing channels514. The bearing channel510of the braking element502and the bearing channel514of the rotating element may be aligned and create a cavity. The cavity in some embodiments may contain at least one ball bearing516. Additionally, the cavity may also contain an anti-friction composition518that coats and/or surrounds the at least one ball bearing516. In some embodiments, the bearing channels510and514may be located along the peripheral sides of the braking element502and rotating element512, thereby creating an interior chamber520. In some embodiments, the interior chamber520may be sealed and in which is contained a hydrophilic liquid522and an insoluble hydrophobic liquid524. The volume of the hydrophilic liquid522and insoluble hydrophobic liquid524may vary dependent on the application. In some embodiments, there may be more hydrophilic liquid522volume than insoluble hydrophobic liquid524, In other embodiments, there may be more insoluble hydrophobic liquid524volume than hydrophilic liquid522. And in some embodiments, the volumes of each liquid522,524may be approximately the same. It will be understood that while the term “liquid” is used herein, the term will also encompass semi-liquids, gels, viscous compositions, and the like. In some embodiments, the insoluble hydrophobic liquid524is of a smaller volume than the hydrophilic liquid522such that when braking element500is in motion the hydrophobic liquid may form small balls532while being disposed in the hydrophilic liquid. Some embodiments of the rotating element512may include the surface comprising a first hierarchical level526, a second hierarchical level528, and third hierarchical level530. The first hierarchical level526, may have a square cross section. The second hierarchical level528may have a circular cross section. The third hierarchical level may also have a circular cross section. In some embodiments, the combined hierarchical microstructures526,528and530may produce a hydrophobic effect. Similarly, in some embodiments, combined hierarchical microstructures504,506,508of the braking element502may also produce a hydrophobic effect. As a practical perspective, one embodiment of the braking system500may be used such that the braking element502is unpowered and the rotating element512is rotating and in motion. When this state occurs, the small balls532of hydrophobic liquid524may be caused to come into contact with microstructures528,530, of the rotating element512and microstructures506,508of the braking element502. In this embodiment, the small balls532may themselves act as microscopic ball bearings. The hydrophilic liquid522may flow, or move, in the voids created between microstructures526and the braking element surface, and between microstructures504and the rotating element surface. In some embodiments, the first hierarchical level504may contain alternating electrodes534,536between adjacent microstructures. Electrode534may be positively charged and electrode536may be negatively charged. Powering electrodes534and536may cause the second and third hierarchical microstructures506,508to transition from a Cassie state to a Wenzel state. When this transition occurs, the hydrophobic liquid524may migrate from second and third hierarchical microstructures506,508disposed on the braking element502to the second and third hierarchical microstructures528,530on the rotating element512. This transition of the hydrophobic liquid may create locking Wenzel-Cassie state which causes to the rotating element512to decrease its rotation. Example 3. A Blood Filtering Device Using Structured Water Valving and Charge Repulsion Sialylated glycoproteins on the surface of red blood cells may be responsible for generating a negative electric zeta potential. Referring toFIG.6, a blood filtering device600may include a surface having complex pillars disposed thereon. The complex pillars may be hierarchically arranged and include a first pillar602and a second pillar604. The second pillar604may be arranged on top of the first pillar602in a hierarchical fashion. In some embodiments, the complex pillars may be arranged in rows606. In some embodiments, the rows of complex pillars may further be arranged such that multiple rows608are located adjacent and parallel to each other creating columns. In some embodiments, each of the first pillars602may include an electrode610associated with it. In embodiments with at least three parallel rows608, the rows may be electrically configured such that two adjacent columns612may be of the same electrical charge, and the third column614may be of the opposite charge. For example, the two adjacent columns612may be positively charged and the third column614may be negatively charged. Due to such a configuration, the space between the adjacent columns612and614, having opposing electrical charges, creates a structured water state615in which the polarity of the water causes the water molecules to align and may exclude particulates such as red blood cells616. Embodiments having this or a similar configuration may result in a valve-like mechanism that may exclude particulates but allow water flow in the channel618. The two positively charged columns of pillars612,620may undergo a sinusoidal variation in potential which may cause red blood cells616to be attracted and then pass in direction622along a line of spatially varying surface energy. In some embodiments, an inlet624may be configured to allow ingress of whole blood under slight pressure. The ingress of whole blood through inlet624may then travel along the rows and columns of microstructured pillars. While,FIG.6shows a plane of orientation perpendicular to gravity, it is anticipated that other embodiments may include different configuration which may be advantageous. In on embodiment, arranging the parallel rows and columns vertically may create a chimney effect. Furthermore, it may be effective to arrange the red blood cell conducting channels in the direction opposite of gravitational pull and the filtrate conducting channels in the direction of the gravitational force. In this opposing-type configuration, one imagines a chimney-drain configuration, where the chimney effect may be achieved by a spatially varying gradient and the drain effect may be achieved by gravitational force. In the filtration of other constituents of blood, such as platelets, this chimney-drain arrangement may be reversed. Example 4. A Hierarchically Electro-Microstructured Adherent Device Referring now toFIG.7, electro-microstructured adherent device700is disclosed and may include complex pillars702. In some embodiments, the complex pillars702may be flexibly pliant, and in some embodiments, the complex pillars may be rigid. In some embodiments, the complex pillars702may be arranged in a regular pattern or in a random pattern. In certain embodiments, the random pattern of complex pillars702may be preferred to promote adhering of the device700to surfaces of varying microstructure. The complex pillars702may be of any cross-sectional shape. In some embodiments, the cross-section may be circular or elliptical. In embodiments with an elliptical cross section, the major axes of the ellipses may be arranged randomly or in a concentric pattern. In some embodiments, complex pillars702may be comprised of first pillars704, on which are stacked second pillars706, and on which are further stacked third pillars708, thus incorporating a hierarchical structure. The first pillars704may be spaced apart from each other on centers of length equal to their total height of the entire hierarchical structure. In some embodiments, the first pillars704may be between 100 to 1000 microns in height. The second pillars706may be between 35 and 100 microns in height. The third pillars708may be between 1 and 35 microns in height. In some embodiments, the third pillars708may be spaced on centers of length between 0.1 and 1.5 the length of the pillars708height. In some embodiments, the complex pillars702may be disposed on a substrate710of the device700. The substrate710may have a thickness, into which are embedded positively charged electrodes712and negatively charge electrodes714. In some embodiments, adjacent to every positively charged electrode712is a negatively charged electrode714. In some embodiments, electroadhesion of the device700to a target surface may be generated by charging electrodes712,714via conductive lines716,718. Example 5. A 4-Level Hierarchical Arrangement of Electrodes and Surface Microstructures on an Electro-Microstructure Device Referring now toFIG.8, a single 4-level microstructure800is illustrated. In some embodiments, the microstructure800may be used to replace the complex pillars702as disclosed in Example 4. In some embodiments, the overall electrode structure of Example 4 may remain the same with the 4-level microstructure800. In one embodiment, the first microstructure802may be hemispherical and is disposed about the surface810of the device. The second microstructure804may be cylindrical and disposed about the first microstructure802. The third microstructure806may be cylindrical and disposed about the second microstructure804. The fourth microstructure808may be of a circular, fiber-like construction and disposed about the third microstructure806. Electrode812may be hemispherical and contoured in a similar geometry as to the first microstructure702. Electrode812may be associated with and charged by lead816. Example 6. A Superhydrophobic/Superhydrophilic Transforming Electro-Microstructured Device Referring now toFIGS.9A and9B, a superhydrophobic/superhydrophilic transforming electrostructure device900is illustrated.FIG.9Adepicts a superhydrophilic state904, andFIG.9Bdepicts a superhydrophobic state902. The electrostructure device900may include a substrate layer906. Disposed about the substrate layer906may be first pillars908and second pillars910. The first and second pillars908,910may be arranged hierarchically. In some embodiments, the first pillars908may have a cross-section that is hexagonally shaped. In some embodiments, the second pillars910may have a cross-section that is circular. In some embodiments, the substrate layer906may include a thickness in which is disposed electrodes914. In some embodiments, a second electrode912may be disposed about the second pillars910. Further, in some embodiments, a final hydrophobic coating layer916may also be included. In one embodiment, the second electrode912may be disposed about the top of the second pillar910. The second electrode912may be arranged to cover the entirety of the top surface of the second pillar910or may partially cover the top surface. In one embodiment, the electrode may be of an opposite charge as the first electrode914. The first electrode914may be disposed within the thickness of the substrate layer906and may generally be located in the areas between the first pillars908. When electrodes912,914are of opposite charge then the structure may have superhydrophilic characteristics (FIG.9A) and achieve a Wenzel wetting state918. When electrodes912,914are of the same charge then the structure may exhibit superhydrophobic characteristics (FIG.9B) and achieve a Cassie non-wetting state920. Example 7. A Spiral Field Effect Electro-Microstructured Device Referring now toFIG.10, a spiral field effect electro-microstructure device1000is illustrated. In some embodiments, such spiral structures may be useful in rapidly reversing the hydrophilic/hydrophobic state of devices. Device1000may be comprised of conical pillars1002with ridges1004on the pillar's outer wall. In one embodiment, two conical pillars1006,1008may be adjacent to one another and wherein, between them is generated a rising surface energy in a downward direction1010. This rising surface energy may generate a capillary force in said downward direction1010. In some embodiments, the conical pillar1002may have an interior in which is disposed an electrode1012. In one embodiment, the electrode1012may be arranged in a spiral configuration. The spiral configuration may be uniform, or the spiral configuration may taper outward as the diameter of the conical pillar1002increases. When the electrode1012is unpowered, the surface may be Wenzel wetting. When the electrode1012is powered, in embodiments where the electrode tapers outward, the field intensity increases as the electrode becomes more tightly wound toward the peak of the conical pillar1002. When two adjacent conical pillars1006,1008with tapered electrodes1016,1018have opposing charges, then the surface energy gradient may be reversed in comparison to the uncharged state, resulting in a Cassie wetting state. Example 8. An Electroadhesive Microstructured Device for Wet Conductive Surfaces Referring now toFIG.11, an electro-microstructure device1100for adhesion to wet conductive surfaces is illustrated. Device1100may include a substrate layer1102, first pillars1104with ridges1106, second pillars1108, electrodes1110, and conductors1112. In some embodiments, the substrate material may be hydrophilic and naturally wetting. The device1100may be configured such that when the device contacts a wet conductive surface, the water may be quickly wicked away as shown by the arrows1114. When the water is quickly wicked away, the electrodes1110may come in close proximity to conductive surface1116, which may greatly enhance the electroadhesion of the device1100. Example 9. An Electro Adhesive Microstructured Device for Nonconductive Surfaces Referring now toFIG.12, an electro-microstructured device1200for adhesion to a wet non-conductive surface is illustrated. Device1200may include a substrate layer1202, first pillars1204with ridges1206, second pillars1208, electrodes1210,1212, and conductors1214,1216. In some embodiments, the substrate material may be hydrophilic and naturally wetting. The device1200may be configured such that when the device contacts a wet nonconductive surface the water may be quickly wicked away. When the water is quickly wicked away, the electrodes1210may come into close proximity in a monopolar configuration. Thus, although there have been described particular embodiments of the present disclosure of a new and useful Microstructured Field Effect Devices, it is not intended that such references be construed as limitations upon the scope of this disclosure except as set forth in the following claims. | 45,341 |
11942879 | DETAILED DESCRIPTION A method and system are disclosed for the generation of electrical energy for use in numerous applications. The method is general in its applications and can be applied to many electrically powered devices, such as portable tools, sensors, optical devices, lighting, heating, cooling, breathing apparatus, medical devices, timing devices, portable computers, cell phones, powered cooling or heating devices as well as other similar and larger stationary applications where a convenient and powerful supply of electrical energy is needed. The need for such a device and method is well documented. More specifically, there is a need to have a more general and better converter of mechanical, electrical, solar, electromagnetic, and other energies from one form to electrical energy. A converter that has better input tolerance to different energy forms, if it be DC, AC, heat, EM radiation, or other sources of energy with variable frequencies, periods, and intensities, with the capabilities to be able to output different voltages, waveforms, and currents to the application loads they are connected and having the commonality of a single simple electrical output, is very much needed. Additionally, the converter should work with very low temperature differences between the ambient temperature and the heat source. As such it should be termed a “waste heat converter”. A product of the devices described herein is electrical energy. The electrical energy formed can be moved in a facile manner to other areas outside of the defined areas and volumes desired to be cooled. Because of this facile and uniquely fast method for the movement of the converted energy, this process is a desirable way to make a “heat collector”, from the standpoint of compact design and reliability. The process produces a “heat collector” cold sink as a by-product of its electrical production, and there are multiple applications of this cold sink to everyday processes. The Carver Voltaic Effect (CVE) is a kinetic physical effect that can be used to provide significant electrical power. The CVE can be described as the minute transient increase in the power of a single power transmission transient in electrical conductors or in energy transfers in materials through space. The term “kinetic” is used to describe the transitory nature of the effect. It can be detected during transitory events, such as fast voltage changes and some other phase and state changes in materials. Embodiments of the devices described herein are constructed to take advantage of this phenomena (i.e., the CVE) by the conversion of thermal energy to electrical energy. The magnitude of the CVE is associated with large dV/dt values (changes in voltage with respect to time). Understanding the operation and manufacture of the device includes the recognition of the presence of an etalon in the output circuit and methods for the implementation and manufacture of the etalon are disclosed. FIG.1is a CVE circuit100for converting thermal energy into electrical energy. A square wave generator105generates a square wave pulse train (continuous pulses) that enters a primary side of a coupled inductor110. The coupled inductor's secondary side is connected to a nonlinear resistive device, or as is sometimes called, a negative resistance device112, such as a thyristor. The negative resistance is optional and not used in many cases. The negative resistance device112serves as a device to limit the current from the secondary side to a certain value determined by its internal construction based upon the input voltage. It will not conduct meaningful current until the voltage exceeds a certain amount in the positive direction and will not conduct in the negative voltage range until the voltage is more negative than a certain amount. For example, the two voltages may be +25V and −25V. Because of this voltage characteristic, the output of the secondary side of the coupled inductor is always certain to exceed +25V and −25 Volts provided sufficient power is available to overcome parasitic losses. The negative resistance device can be any device that can provide this type of action. Example devices include, but are not limited to, the following:1. Gas discharge lamps2. Spark gaps3. Zener diodes4. Thyristors5. Triacs6. Gunn diodes7. Diodes (all kinds)8. Silicon controlled rectifiers (SCR)9. Switching devices controlled by a logic circuit As the driving electronics for the transformer (or coupled inductor) cause the output of the secondary to swing from positive to negative, very fast transitions from the >25V to more negative than −25V will take place. These high dV/dt transients are then utilized to produce fast voltage swings desired for the CVE to be utilized. Thus, the larger the dV/dt (higher voltage, less time), the more pronounced the CVE. The square wave in combination with the negative resistance device112help to achieve this goal. In this example, the capacitor C1114and the inductor116form an oscillatory circuit that further amplifies the effects of the current with its voltage swings to produce a useful output at C2118. The C2capacitor118is in turn connected to one or more rectification diodes, shown generally at120to produce both a positive and negative voltage output, V+ and V−, respectively. The oscillatory circuit formed by the capacitor114and inductor116can generate a signal oscillating at a frequency greater than the frequency of the square wave input signal. A thermal exchanger130provides a thermal conduction path for the materials to have a continual influx of thermal energy for conversion to electrical energy. The thermal exchanger can be any device used to receive heat into the circuit. In one example, a tube (e.g., a conductive tube or non-conductive tube) is used that is filled with material having a desired permittivity and permeability. Potential materials include air, water, methanol, ethanol, and acetamide (or a solution in liquids such as water or ethanol). Ferrite slurries can also be used. The material can be pumped or circulated through the tube using an external pump, not shown. Alternatively, the solid materials can be immobilized within the resonant cavity. Subsequently liquids can be pumped through the tube to provide heat exchange to the materials and the tube itself. The tube can be any desired length. For example, the tube can be 1 ft to 5 ft in length. The tube can be any desired shape in cross-section such as round, square, rectangular, elliptical, a flat-sided oval, or a custom shape. Any geometric shape can be used (e.g., an N-sided polygon or a folded shape). Whatever the cross-section, the tube can be elongated with a cavity therein through which fluid can pass. The tube can be an etalon as described herein. The tube can be made of conductive material and can be a solid conductor. FIG.2shows a generic version of the circuit200. An optional driver210can be a continuous pulse generator that supplies a continuous stream of pulses with high dV/dt. This provides the starting impulse to the device. It can serve as the on/off switch to run the device and it can help control the frequency at which the device is operated. A dV/dt device220is shown.FIG.1showed the dV/dt device as a transformer or a coupled inductor110to indicate at least one way of generating a high dV/dt pulse or series of pulses. Alternatives to this could be a capacitor or capacitor array, a mechanical switch, or other spinning or rotation devices that bring an electrical (charge) or magnetic field (magnet) in proximity to another coil, capacitor, inductor, or another magnet or magnetic field. The CVE device may have one or more significant active devices incorporated within it. Examples are the negative resistance devices, such as a thyristor or Zener diode. The CVE emitter230is shown coupled to a thermal exchanger240. The thermal exchanger can, in turn, be coupled to a CVE receiver250. The rapid formation of a dV/dt charge on the emitter230leads to the production of a “wave” of energy from the emitter. In this antenna-like mode, the emitter may be in contact with a material other than a vacuum or air. The material may have the properties of having a different dielectric constant or magnetic permeability characterized by its relative permittivity or permeability. It may also be in contact with a conductive material. The emitter230and receiver250can be a wide variety of materials (e.g., copper, brass, bronze, stainless steel, graphene) that create impedance changes at the ends of the etalon chamber. Indeed, anything can be used, so long as it changes the permittivity, permeability, or both with respect to the material between the emitter and receiver. Thus, the emitter230couples the circuit to the thermal exchanger240(which can be an etalon) and transmits a signal to the thermal exchanger. The receiver250receives the signal once it passes through the thermal exchanger. The thermal exchanger240is shown as being between the CVE emitter and the CVE receiver. It may, in fact, be surrounding the emitter and the receiver. For example, where the thermal exchanger is a tube (e.g., an etalon) having a cavity therein, the emitter230and receiver250can be mounted in respective ends of the tube. The thermal exchanger provides the needed thermal conduction path for the materials to have a continual influx of thermal energy for conversion to electrical energy. The materials may also be electrically conductive. The thermal exchanger can be any device used to inject heat into the circuit. In one example, a tube (e.g., a conductive tube or non-conductive tube) is used that is filled with material having a desired permittivity and permeability. Potential materials include air, water, methanol, ethanol, and acetamide (or a solution in liquids such as water or ethanol). Ferrite slurries can also be used. The material can be pumped or circulated through the thermal exchanger using an external pump, not shown. Alternatively, the solid materials can be immobilized within the resonant cavity. Subsequently liquids can be pumped through the cavity to provide heat exchange to the materials and the cavity itself. Thus, the material can have a dual purpose of acting as a medium between the CVE emitter and CVE receiver and acting as a thermal exchanger having an external source that is circulated through the thermal exchanger. Electronic waves can be transmitted between the CVE emitter and CVE receiver and the permittivity and permeability of the materials contained therein can impact the resonant frequency. The CVE receiver250is shown coupled to the thermal exchanger. It may or may not be in contact (e.g., air gapped or spaced) with the thermal exchanger240. The receiver250, by electrical induction from the wave, electrical contact with the thermal exchanger, or by electrical contact with the emitter230has the increased energy provided by the CVE. The receiver harvests the converted heat into an electrical conduction path to either be utilized directly by a load260or to be conditioned by a conditioning circuit270. The load260can be any desired load and can have a resistive component (e.g., a light bulb). The conditioning circuit270are shown connected to the CVE receiver250. This circuit270is typically a circuit to convert the AC signal (or pulsed DC) into another frequency range or convert to a DC voltage or voltages. An example conditioning circuit can be a full bridge rectifier and capacitor. An electrical load280receives an output of the conditioning circuits270. The load may be anything that uses electrical energy. It is similar to the direct use of the electrical energy load260but it may require conditioning from module270. Module260is the direct use of the output of the CVE receiver250. This output has typical AC signal characteristics. Resistive loads would be acceptable for this type of electrical characteristic as either square or sinusoidal waves. FIG.3is a circuit300in which the negative resistance device345is used in conjunction with the emission of the dV/dt wave as shown by connection to component320. As previously stated, the negative resistance device is optional. A pulse generator310is coupled to an inductor or transformer312. The output of the secondary of the coupled inductor or transformer312is referenced to a voltage indicated by V340. The negative resistance device345is coupled to the inductor. The emission of the wave from component320can be coupled to the receiving component350. The receiving component350can also be connected to a load360. The connection between the receiving component320and the receiving component350is shown by a dashed bidirectional arrow and can be a vacuum, air, or other dielectric materials either homogeneous or heterogenous. Conductive materials can also be used. FIG.4is a circuit400using an etalon for amplification. The dV/dT device410can be any pulse generator. Alternatively, as shown above, the dV/dT device can be a transformer coupled to a negative resistance device, as is shown inFIG.3. The combination of elements420,430comprise a resonance cavity similar to an etalon or Fabry-Perot interferometer. It can be similar to the description of the thermal exchanger130. It is shown without a load. It may be utilized without an attached load by either emission of electrically induced waves or by simply being a higher voltage source reference for reference applications. With a load (e.g. resistive), the etalon can produce amplified power from the dV/dt device by capturing the thermal energy between the emitter and the receiver and the coupling component itself, particularly but not exclusively, when resonance occurs. Activation frequencies can be used that are much lower than optical frequencies. In most cases, the lowest fundamental wavelength in the resonance cavity is very long compared to the relative sizes of the other components. In order to reduce the size of the resonance cavity, higher relative permittivity or permeability materials can be used to significantly reduce the length of the etalon involved. This area of the device is shown by the dotted double-headed arrow between components420and430. In the case of a high permittivity capacitors, relative permittivity in the ranges of 3 to ≥20,000 are not uncommon. Higher permittivity materials are known. These materials provide for a highly decreased etalon length by similar factors such as the square root of the inverse of the relative permittivity multiplied by the relative permeability. An etalon440is shown between the components420,430. The etalon (wave resonant cavity) chamber can be considered as one (or more) of the oscillator components. This particular etalon differs from a purely electrical conductivity element by involving emitted electrical waves rather than electrical current oscillation in a conductor. A hollow etalon also provides the ability to fill the resonance cavity with a material that has a permittivity (and/or a magnetic permeability) that is greater than vacuum or air. This increased permittivity/permeability decreases the fundamental oscillation length. Folding (or coiling) the length helps reduce the overall size. The etalon cavity may be where most of the heat conversion to electrical energy will take place. Fluid can be moved through the etalon's cavity. The fluid will be constantly cooled by the resonance of the dV/dt waves while the movement of the etalon fluid provides a way to effectively get heat into the resonance volume by carrying the heat from an external source. Or, simple heat conduction/convection into the resonance cavity volume can be used to provide the heat from an external heat source, possibly using a second fluid (e.g. water) or heat pipe. The etalon440is shown as a cylindrical tube, in this embodiment, with a cavity extending therethrough. A pump450is used to pump fluid through the etalon440. A heat sink460is used to extract heat from the ambient environment and pass the heat to the fluid. The etalon can then convert the heat to electrical energy. The etalon can be filled with materials that have different permittivities and permeabilities, such as air, water, methanol, ethanol, and acetamide (e.g. in a solution of water or ethanol). Higher permittivity materials allow a lower drive frequency to be used and still be at resonance. The etalon can have a dual purpose of acting as an electrical coupling between the component420and the component430and also acting as a thermal exchanger. The emitter420and receiver430can be a wide variety of materials (e.g., copper, brass, bronze, stainless steel, graphene) that create impedance changes at the ends of the etalon chamber. Different electrical elements can also be used as the emitter420and receiver430, such as inductors and capacitors. Indeed, anything can be used, as long as it changes the permittivity, permeability, or both with respect to the material between the emitter and receiver. The load should be selected so as to have proper impedance matching with the source, as is well known in the laser, transmission, and antenna fields. FIG.5is a circuit500that is an additional schematic representation of the material510in between the etalon's reflective surfaces,520and530. The thermal energy material510is in the transmissive path and/or reflective path of the wave coming from the emitter or the reflected wave from the receiver. Due to the CVE, the power in the wave is augmented by each traverse of the wave between the surfaces. In this way the material510is cooled, since the energy required for the increase in energy in the wave is obtained from the thermal energy contained in the material itself due to the law of conservation of energy. To achieve resonance in a given cavity, the cavity's shape must be taken into account. Square or round shapes may be used as well as oval, elliptical, polygonal, and other geometrical shapes. Also, the material filling a resonance cavity plays a part in determining the frequency of resonance. Increasing the permittivity or permeability of the material filling a given cavity changes its resonance to a lower frequency. In the case of the frequency of electrical waves, the resonant frequency of the cavity is related to the square root of the inverse of the relative permittivity multiplied by the relative permeability of the material vs a pure vacuum. Thus, higher permeability and higher permittivity materials can lead to reduced physical sizes of the etalon cavity. Higher permittivity materials (Thermal Energy Material) may be used to provide an etalon cavity that is substantially shorter (thereby smaller) than that with vacuum or air-filled cavity. Additionally, the material510may be thermally conductive to facilitate thermal transfer into the cavity from the environment or heat source. Liquid materials are attractive in that they can be circulated to facilitate heat transfer. Materials that can be used are those that are transmissive to the wave itself. Some materials (or mixtures, suspensions, or slurries thereof) that may be used but are not the limitation for use are as follows:1. Barium titanate2. Other Perovskite mixed metal titanates3. Ferrite4. Inorganic Oxides5. Air6. Organic alcohols7. Organic materials that may be transmissive to the wave8. Conductive metals9. Semiconductive materials10. Species of carbon (e.g. graphite, graphene, Fullerenes)11. Materials which themselves re-resonate at other frequencies (e.g. phosphors, rhodamine) via harmonic generation12. Water or water with dissolved salts, liquids, or other species suspended or homogeneous. Materials can be used to partially fill or fully fill the cavity to provide a pathway for thermal conduction to the etalon cavity. The load540can be any desired electrical load, such as a load having a resistive component. The dV/dt device550is similar to those described above. As an example of the device, the following set of components can be used.1. Transformer (coupled inductor), 10:1 ratio, 2 A current rating, 700 uH secondary inductance2. 0.01 uF, 1000 V ceramic capacitor3. 254 uH ferrite single inductor, 10 A inductor4. Copper tube (⅝″ OD×½″ ID×24 inches length)5. Powdered ferrite (125 mesh)6. Resistive load (110 Ohm, 100 W metal film resistor)7. 2 pc Copper wire (10 AWG×1″ long)8. Zener Diode (1N5388) Using the schematic shown inFIG.1, the copper tube is first packed with the ferrite powder. One piece each of the copper wire is inserted into each end of the tube and used to make connection to the remainder of the circuit. The transformer is driven by means of a pulsed current source at a frequency of 1 Hz to several GigaHertz. The exact frequency required can be tuned by maximizing the ratio of power produced to the power necessary to drive the transformer's primary. The secondary of the transformer is attached to one piece of the copper wire in the copper tube. The other end of the copper tube with the remaining wire is attached to a negative resistance device such as a Zener diode. The other end of the diode is attached to an inductor. The remaining connection is led back to the secondary of the transformer's output. Electrical energy can be obtained by attachment of a capacitor to almost any portion of the above secondary circuit as a tap to the voltage produced in the resonance circuit. The remaining lead on the capacitor can optionally connect to a rectifier circuit for further conversion to an AC, pulsed DC, or smoothed DC output by conventional means. FIG.6is a flowchart for generating power according to an embodiment. In process block610, a continuous stream of pulses is generated, such as by a pulse generator. The pulse generator can generate pulses having a dV/dt of 100V/μs or even 10,000 to 100,000 V/μs or higher. Specific use cases have used between 3 to 10V/μs. In some cases, 1V/μs can be used. In process block620, the continuous stream of pulses is applied to a tube having a cavity extending therethrough. The tube can be conductive and have fluid continuously pumping through the cavity (process block630). The fluid can be warmed by a heat sink or other heating element. The fluid can be cooled as it passes through the tube due to the CVE. At process block640, an electrical signal can be output from the tube having a greater power than was output by the pulse generator due to conversion of thermal energy of the fluid to electrical energy. In some embodiments, an oscillator can be used to generate pulses at a greater frequency than the pulse generator. FIG.7shows another embodiment of a CVE circuit700(also called a “CVE transformer”). The circuit700includes an oscillator702, which includes a capacitor704and an inductor706to form an LC or tank circuit. Although the capacitor704and inductor706are shown coupled in series on opposite sides of an electrical element708, they can be coupled in series and positioned together on one side of the electrical element. The circuit700further comprises a heat sink720, which provides additional surface area that can allow for the absorption of additional heat722from a heat source, or from multiple different heat sources. The heat sink720can be thermally coupled to the electrical element708so as to allow heat transfer therebetween (e.g., direct contact). The heat source can include any source which is warmer than the electrical element708including ambient air in which the heat sink resides. The circuit700can operate similar to the circuits described above, wherein a pulse generator730can generate either a single electrical pulse, or a series of electrical pulses having a high dV/dt ratio. The oscillator702can generate an oscillating signal in response to each pulse and the electrical element708can convert thermal energy into electrical energy by cooling off and increasing the power of the electrical pulses output by the pulse generator730. The heat sink720can absorb the heat722to provide the electrical element708with a constant source of thermal energy that can be converted to electrical energy. Accordingly, the electrical power provided to a load740is greater than the electrical power produced by the pulse generator730. Further advantages that the CVE transformer are the ease of accepting practically any electrical input form (AC, DC, etc.) with virtually any frequency or mixture of frequencies. It also has the benefit of its electrical output being a consistently known AC waveform relatively easily transformed to a broad array of electrical formats. Even in the cases where the desired electrical output waveform and voltage is the same as the input, the CVE transformer can provide value in removing and “cleaning” the input waveform into a more consistent specified output. Removal of spurious AC signals, DC offsets, and other forms of unspecified contamination of the power can be obtained. In addition, the frequency range of the input waveform can be both higher and lower than that of the output without having to modify the circuit in any way to use both the high frequencies and the low frequency components of the input simultaneously. Thus, the full energy content of the input can be more readily utilized. This is especially useful for input power that has frequencies above several hundred kHz where simple rectification of the electrical signal can be very inefficient. Applications that can benefit from the CVE transformer include, but are not limited to, suppression of electrical noise in mass electric transportation due to lighting strikes, electric energy impulses from nuclear explosions, chemical weapons, sun related phenomena, and other high energy events that may impact electronics and electrical supplies. Other applications that may need to supplement one or more of the electrical inputs along with additional energy from the conversion of other heat or energy sources to an electrical output are also good uses. Other forms of energy beside electrical energy may be input into the “CVE transformer”. The energy inputs are either heat or an energy source that can be converted to heat. Examples are kinetic energy (flywheel), acoustic, optical, electromagnetic radiation, magnetic, chemical, nuclear (atomic), and gravity potential. All of these energy sources can ultimately lead to the production of heat energy. FIG.8is another example of a CVE circuit800including a CVE drive802(shown in dashed lines) that can be used. In this example, a voltage supply810can be used to supply a stream of pulses in conjunction with a switch812. The switch812can be controlled by a microprocessor (not shown). The switch812is coupled to a first winding820of an inductor822. A second winding824of the inductor822is coupled to a capacitor830and an inductor832coupled in series and used as a secondary oscillator. An etalon840can be used as an electrical element and provides the energy transformation of heat to electrical energy using the cooling effect of the pulses generated by the voltage supply810and switch812, in conjunction with the secondary oscillator formed by the capacitor830and the inductor832. Due to the injection of heat into the etalon840, increased energy can be supplied to a load circuit850than is supplied by the voltage supply810. FIG.9shows the CVE drive910(which can be any CVE circuit described above) used in conjunction with Carnot engine920so that the engine performs more efficiently. The Carnot engine920includes a hot sink930, which supplies energy to a working fluid940. The working fluid performs work, which can be power or work per unit time. The working fluid discharges residual heat to a cold sink950. The thermal source from the hot sink930may be anything that can be put into thermal contact with the working fluid940and that has a higher temperature than the working fluid. The thermal source may be a gas, liquid, or solid material, preferably in close contact with the working fluid. The maximum thermodynamic efficiency is related to the absolute temperatures of the hot sink and the cold sink and is defined by the following formula: η=1−(TC/TH). A reduction in the temperature of the cold sink950improves the efficiency of the Carnot cycle engine. Thus, the CVE module910can be used in conjunction with the cold sink950to ensure that the cold sink950maintains or lowers its temperature by pulling any heat from the cold sink950. The heat extracted from the cold sink950can, in turn, be used to produce electrical power960in excess of any supplied power to the CVE cooling module910. Thus, the temperature of the cold sink950of the Carnot engine920can be lowered, heat can be supplied to the CVE device, and electrical power is produced along with the power produced by the Carnot engine. Greater efficiency is obtained by having a lower temperature cold sink, and the additional energy from the CVE device can be obtained as an additional boost to the efficiency. The electrical element of the CVE device can include a wide variety of materials including copper and other conductive materials. Graphene, graphite, and other carbon structures are known to be used as thermal conductive pathways as well as being electrically conductive materials. Electrically non-conductive materials can also be used and include water, saltwater, organic amides, glycols, alcohols, and other high permittivity materials or permeability materials such ferrite, iron, and other such ferromagnetic materials. The input frequency of the signal supplied to the electrical element can be in the frequency range of 0.1 Hz to 5 GHz. The cold sink950is capable of extracting heat from gases to provide cooled gases. Additionally, the cold sink950can extract heat from a liquid to provide a cooled liquid. Still further, the cold sink950can extract heat from a solid to provide a cooled solid. Any of the gas, liquid or solid can be circulated to provide continuous contact with the working fluid. The electrical element of the CVE can also include one or more sheets1010of conductive material, such as is shown inFIG.10, separated by insulators1020. The sheets desirably have a large surface area and can be square-shaped or rectangular-shaped. The sheets1010are coupled together by wires or by folding a sheet to make a continuous conductive surface, such as is shown at1030, so that the electrical pulses of the CVE can pass through the conductive sheets. Any number of sheets can be coupled together. Through the use of the layered structure, the electrical element cools efficiency. The layers1010utilize the “skin effect” of the materials to provide a lower resistance to the conducted current. This reduction in resistance and increase in surface area increases the overall current density for a given voltage drop across the material and provides for a higher effective thermal cooling (W/kg/K). FIG.11is an additional example of the electrical element1110of the CVE having an electrical coating1120on the surface thereof. For example, a silver coated conductive structure can be used to form not only the solid single layer exchanger as shown, but also the multilayer structure ofFIG.10. The enhanced conductivity of, for example, silver on a copper plate provides a greater current density in the electrical element versus being uncoated. Other highly conductive materials beside silver and copper can be used to coat less expensive or more desirable materials. The layered structure can be in electrical and physical contact from layer to layer or alternatively a thin non-conductive coating between layers can additionally serve to electrically insulate the layers from each other. In some instances, the conductive coating forms an electrically insulative layer of oxides. An example of such a material is aluminum with an anodized or oxidative treatment to provide a non-conductive coating. FIG.12shows the electrical element of the CVE formed of concentric cylinders1200. The tubular shape is then more conducive to a heat exchange fluid being circulated with its confines or with external circulation over its surface. A cylinder1210can be made of material as described above. An external coating1220can be applied to the outer surface of the cylinder1210. This coating may be silver, aluminum, nickel, chromium, or other highly conductive material such as graphene or other carbon structures. Additionally, an insulative coating1230can be applied to the coating1220. Alternatively, the sequence of layers can be rearranged to provide for essentially the same cylinder suitable for fluid thermal heat sources. Building sequential cylinder elements outwardly provides the same effect and can be used. The materials of the electrical element or cold sink may also be coated with an external coating to not only provide decreased resistance but also to enhance the absorption of heat, electromagnetic waves, electric waves, and resistance to corrosion. The coatings can be used to vastly increase the absorption of electrical waves, especially in the case of nonconductive exchanger materials. This has a large effect on the cooling ability of the device per unit weight. This is due to the fact that the capability of the cooling by the CVE effect can be more effective if the temperature drop of the interface is minimized. Thus, for a small thermal drop, the rate of thermal heat transfer at the surface of the cold sink is generally the limitation for the wattage capabilities of the CVE. Conductive coatings that may be used include, gold, silver, palladium, platinum, rhodium, nickel, and other stainless formulations. Organic polymers coatings such as Puralene® and Parylene and their derivatives, as well as sacrificial anodes, can be used to provide superior corrosion resistance. Electrolytic anodization process can be used to provide insulative and physical protections. Carbon filled polymeric coatings can be used to provide enhanced EM radiation absorption and emission. Other materials are known for the absorption of EM waves and electric fields could also be used. Other forms of energy beside electrical energy may be input into the CVE drive. The energy inputs are either heat or an energy source that can be converted to heat. Examples are kinetic energy (flywheel), acoustic, optical, electromagnetic radiation, magnetic, chemical, nuclear (atomic), and gravity potential. All of these energy sources can ultimately lead to the production of heat energy. Applications that can benefit from the CVE circuit include, but are not limited to, suppression of electrical noise in mass electric transportation due to lighting strikes, electric energy impulses from nuclear explosions, chemical weapons, sun related phenomena, and other high energy events that may impact electronics and electrical supplies. FIG.13is a flowchart of a method according to one embodiment. In process block1310, a continuous stream of pulses is generated. For example, inFIG.1, the pulse generator105can generate a stream of pulses into the inductor110. As further examples, the pulse generator310ofFIG.3or the pulse generator730ofFIG.7can be used. Still further, the voltage supply810in conjunction with the switch812can be used to generate a continuous stream of pulses. In process block1320, the continuous stream of pulses is applied to a conductor that receives heat from a cold sink. The conductor can be an etalon, as shown at440inFIG.4. Alternatively, the conductor can be a wire. The cold sink can be from a Carnot engine, such as is shown inFIG.9. In process block1330, an electrical signal can be output from the conductor and supplied to an output load, such as load740inFIG.7. The output electrical signal can be boosted by converting heat from one or more of the heat sources to electrical energy. FIG.14is another example of a CVE circuit1400including a CVE drive1402(shown in dashed lines) that can be used. In this example, a voltage supply1410can be used to supply one or more pulses in conjunction with a switch1412. The switch1412can be controlled by a controller1413, which turns the switch ON and OFF in succession to establish one or more pulses. The controller1413can be a processor or microcontroller. Alternatively, the controller1413can include one or more thyristors. The switch1412is coupled to a first winding1420of an inductor1422. A second winding1424of the inductor1422is coupled to a capacitor1430and an inductor1432coupled in series and used as a secondary oscillator. An etalon1440can be used as an electrical element and provides the energy transformation of heat to electrical energy using the cooling effect of the pulses generated by the voltage supply1410and switch1412, in conjunction with the secondary oscillator formed by the capacitor1430and the inductor1432. Due to the injection of heat into the etalon1440, increased energy can be supplied to a load circuit1450than is supplied by the voltage supply1410. An input to the controller1413is a voltage from node1415, which is positioned between inductors1424and1432. Examination of the voltage at node1415reveals an AC waveform when excitation of the etalon1440occurs through a pulse of energy into the primary of inductor1422. Oscillation within the etalon1440takes place at a given frequency, f1, that may be greater than the oscillation frequency observed at point1415. However, this oscillation in the etalon1440induces the oscillation through the elements1430and1432. The oscillation at point1415can be further enhanced by more pulses from the excitation switch1412. This can increase the magnitude of the pulses driving the etalon's oscillation and also inhibit the oscillations as well. The switch1412is connected to the voltage supply1410to pulse the primary of the transformer1422. Enhancement of the existing oscillations by timing the additional pulses of1412to be in phase with the existing pulse can result in greatly improved voltage levels for the oscillations. Thus, by adapting the phase and/or the frequency of the switch1412to match the phase and/or frequency of the voltage at node1415, an improvement in voltage levels is achieved. The controller1413provides the pulse's phase timing necessary to prevent destructive interference with the existing wave and to promote constructive interference with the oscillation. In one example, thyristors acting as the controller1413are used and when a voltage level reaches a positive threshold (e.g., 100 V), the switch1412is switched and when the voltage level reaches a negative threshold (e.g., −100V), the switch is switched again. Although node1415is used to obtain the phase information, other nodes can be used as well. Whatever node is used for phase information, it provides the necessary phase information for the controller1413to enhance the oscillation, or alternatively to provide pulses to deconstruct the oscillation. This latter case could provide a valuable means of rapidly shutting the output off in the event of excess output. In view of the many possible embodiments to which the principles of the disclosed invention may be applied, it should be recognized that the illustrated embodiments are only preferred examples of the invention and should not be taken as limiting the scope of the invention. Rather, the scope of the invention is defined by the following claims. We therefore claim as our invention all that comes within the scope of these claims. | 39,405 |
11942880 | DETAILED DESCRIPTION FIG.1Aillustrates a rotary power tool, which is a core drill10in the illustrated embodiment. The core drill10includes a housing15, a first or rear handle20, and a second or auxiliary handle25. A generally D-shaped gap30is defined between the rear handle20and the housing15. The gap30provides clearance for a user's fingers when the user grasps the rear handle20. In the illustrated embodiment, the rear handle20includes a base portion35at its lower end that extends to the housing15. As such, the gap30is an aperture that is fully bounded about its perimeter by the rear handle20, the base portion35, and the housing15. In other embodiments, the base portion35may not connect to the housing15. The illustrated housing15is a clamshell housing having left and right cooperating halves40,45and includes a motor housing portion50and a drive housing55. An electric motor (seeFIG.3) is mounted in the motor housing portion50. The illustrated core drill10is cordless and includes a battery pack60that provides power to the motor. The battery pack60is removably coupled to a battery pack receptacle or battery pack interface, which is located underneath the motor housing portion50in the illustrated embodiment. In other embodiments, the core drill10may be a corded tool configured to receive power from a wall outlet or other remote power source. An actuator or trigger65is provided on the rear handle20and energizes the motor when depressed by a user. In some embodiments, the core drill10includes an easy hole start switch. FIG.1Billustrates an example power tool100according to some embodiments. The power tool100includes a housing105, a battery pack interface110configured to receive a battery pack, a driver115(e.g., a chuck or bit holder), a motor housing120, an actuator or a trigger125, a handle130, and an easy hole start switch135. The motor housing houses a motor400(seeFIG.3). A longitudinal axis extends from the driver115through a rear of the motor housing120. During operation, the driver115rotates about the longitudinal axis. The longitudinal axis may be approximately perpendicular with the handle130. The easy hole start switch135may be a switch that moves between two positions, a switch that can be pressed to indicate an ON position and release to indicate an OFF position, etc. The easy hole start switch135may be configured to be switched to the ON position such that an easy hole start operation is enabled. The easy hole start operation will be described in detail below (seeFIGS.6A-8). In some embodiments, the easy hole start operation may be automatically enabled such that the actuation of the trigger125begins the easy hole start operation. WhileFIGS.1A and1Billustrate specific power tools10,100with a rotational output, it is contemplated that the easy hole start operation described herein may be used with multiple types of power tools, such as other drills, drivers, powered screw drivers, powered ratchets, grinders, right angle drills, impact drivers, impact wrenches, rotary hammers, pipe threaders, or another type of power tool that experiences rotation about the longitudinal axis. FIG.2illustrates a battery pack150. The battery pack includes a housing105and a device interface portion160for connecting the battery pack150to a device (e.g., power tool10,100). The battery pack150includes a plurality of battery cells within the housing105. The battery pack150provides current to the motor400. A controller300for the power tool10,100is illustrated inFIG.3. The controller300is electrically and/or communicatively connected to a variety of modules or components of the power tool10,100. For example, the illustrated controller300is connected to indicators345, sensors350(e.g., a current sensor, a voltage sensor, a speed sensor, a voltage sensor, a temperature sensor, an accelerometer, the proximity sensor140, etc.), a user interface355, the easy hole start switch135, the trigger125(via a trigger switch380), a power switching network365, and a power input unit370. The controller300includes a plurality of electrical and electronic components that provide power, operational control, and protection to the components and modules within the controller300and/or power tool10,100. For example, the controller300includes, among other things, a processing unit305(e.g., a microprocessor, an electronic processor, an electronic controller, a microcontroller, or another suitable programmable device), a memory325, input units330, and output units335. The processing unit305includes, among other things, a control unit310, an arithmetic logic unit (“ALU”)315, and a plurality of registers320(shown as a group of registers inFIG.3), and is implemented using a known computer architecture (e.g., a modified Harvard architecture, a von Neumann architecture, etc.). The processing unit305, the memory325, the input units330, and the output units335, as well as the various modules connected to the controller300are connected by one or more control and/or data buses (e.g., common bus340). The control and/or data buses are shown generally inFIG.3for illustrative purposes. The use of one or more control and/or data buses for the interconnection between and communication among the various modules and components would be known to a person skilled in the art in view of the embodiments described herein. The memory325is a non-transitory computer readable medium and includes, for example, a program storage area and a data storage area. The program storage area and the data storage area can include combinations of different types of memory, such as a ROM, a RAM (e.g., DRAM, SDRAM, etc.), EEPROM, flash memory, a hard disk, an SD card, or other suitable magnetic, optical, physical, or electronic memory devices. The processing unit305is connected to the memory325and executes software instruction that are capable of being stored in a RAM of the memory325(e.g., during execution), a ROM of the memory325(e.g., on a generally permanent basis), or another non-transitory computer readable medium such as another memory or a disc. Software included in the implementation of the power tool10,100can be stored in the memory325of the controller300. The software includes, for example, firmware, one or more applications, program data, filters, rules, one or more program modules, and other executable instructions. The controller300is configured to retrieve from the memory325and execute, among other things, instructions related to the control processes and methods described herein. In other embodiments, the controller300includes additional, fewer, or different components. The battery pack interface110is connected to the controller300and is configured to couple with a battery pack150. The battery pack interface110includes a combination of mechanical (e.g., a battery pack receiving portion) and electrical components configured to and operable for interfacing (e.g., mechanically, electrically, and communicatively connecting) the power tool100with the battery pack150. The battery pack interface110is coupled to the power input unit370. The battery pack interface110transmits the power received from the battery pack150to the power input unit370. The power input unit370includes active and/or passive components (e.g., voltage step-down controllers, voltage converters, rectifiers, filters, etc.) to regulate or control the power received through the battery pack interface110and to the controller300. In some embodiments, the battery pack interface110is also coupled to the power switching network365. The operation of the power switching network365, as controlled by the controller300, determines how power is supplied to the motor400. References herein are made with respect to the power tool100, but can be similarly made with respect to the power tool10. The controller300drives the motor400to rotate driver115in response to the user's actuation of the trigger125. The driver115may be coupled to the motor400via an output shaft. Depression of the trigger125actuates a trigger switch380, which outputs a signal to the controller300to drive the motor400, and therefore the driver115. The controller drives the motor400via control signals that include pulse width modulated (PWM) signals. In some embodiments, the controller300controls the power switching network365(e.g., a FET switching bridge) to drive the motor400. For example, the power switching network365may include a plurality of high side switching elements (e.g., FETs) and a plurality of low side switching elements (e.g., FETs). The controller300may control each FET of the plurality of high side switching elements and the plurality of low side switching elements to drive each phase of the motor400. When the trigger125is released, the controller300may apply a braking force to the motor400. For example, the power switching network365may be controlled to more quickly decelerate the motor400. The controller300is configured to drive the motor400according to an easy hole start operation. During the easy hole start operation, the motor400rotates the driver115at a first or reduced speed. The motor400receives a reduced amount of power from the power switching network365(e.g., 10% power). In some embodiments, when the easy hole start switch135is in the ON position, the motor400receives reduced power and operates at a reduced speed. For example, the controller300may control the FETs of the power switching network365to supply power to the motor400with a reduced PWM duty cycle to drive the motor400at a reduced speed. In some embodiments, the controller300drives the motor400at the reduced speed until a predetermined time threshold or time interval (e.g., 120 seconds) is reached. In some embodiments, the controller300drives the motor400at the reduced speed and gradually increases the speed to a target speed value (e.g., full speed, a desired speed set by the user, etc.). In some embodiments, if the easy hole start operation persists until a predetermined time threshold (e.g., two minutes), the controller300may turn off the power tool100, deenergize the motor400, and/or apply the braking force to the motor400to stop the operation of the motor400. The easy hole start switch135controls the easy hole start operation of the power tool100. The easy hole start switch135may be switched between an ON position and an OFF position by the user. In some embodiments, the easy hole start operation is automatically applied to the power tool100by the controller300. In such embodiments, upon actuation of the trigger125, the easy hole start operation is applied. The user can set the reduced speed value, the target speed value, and the predetermined time threshold via the user interface355. The user interface may be a touchscreen on the power tool100, buttons on the power tool100, a mobile device that communicates with the power tool100over a network, etc. The indicators345are also connected to the controller300and receive control signals from the controller300to turn ON and OFF or otherwise convey information based on different states of the power tool100. The indicators345include, for example, one or more light-emitting diodes (LEDs), a display screen, etc. The indicators345can be configured to display conditions of, or information associated with, the power tool100. For example, the indicators345can display information relating to the charge state of the battery pack150, such as the charging capacity. The indicators345may also display information relating to a fault condition, or other abnormality, of the power tool100. In addition to or in place of visual indicators, the indicators345may also include a speaker or a tactile feedback mechanism to convey information to the user through audible or tactile outputs. In some embodiments, the indicators345display information relating to an easy hole start condition. For example, one or more LEDs are activated upon detection of the easy hole start switch135being in the ON position. FIG.4illustrates a circuit diagram395of the power switching network365. The power switching network365includes a number of high side power switching elements365A,365B,365C and a number of low side power switching elements365D,365E,365F (seeFIG.5). The controller300provides the control signals to control the high side FETs365A,365B,365C and the low side FETs365D,365E,365F to drive the motor400based on the easy hole start operation. For example, in response to detecting the easy hole start switch135being in the ON position and the trigger125being actuated, the controller300provides control signals to the FETs365A,365B,365C and365D,365E,365F to selectively enable and disable the FETs365A,365B,365C and365D,365E,365F to drive the motor400at a reduced speed (e.g., 10% of maximum speed). In some embodiments, once the motor400is driven at a reduced speed until a predetermined time threshold is reached, the controller300provides the control signals to selectively enable and disable the FETs365A,365B,365C and365D,365E,365F (e.g., sequentially, in pairs) to increase the speed of the motor400to a target speed (e.g., full speed, a desired speed set by the user, etc.). More particularly, to drive the motor400, the controller300enables a first high side FET365A,365B,365C and first low side FET365D,365E,365F pair (e.g., by providing a voltage at a gate terminal of the FETs) for a first period of time. In response to determining that a rotor of the motor400has rotated based on the sensors350, the controller300disables the first FET pair, and enables a second high side FET365A,365B,365C and a second low side FET365D,365E,365F. In response to determining that the rotor of the motor400has rotated based on the sensors350, the controller300disables the second FET pair, and enables a third high side FET365A,365B,365C and a third low side FET365D,365E,365F. This sequence of cyclically enabling pairs of high side FETs365A,365B,365C and low side FETs365D,365E,365F repeats to drive the motor400. In some embodiments, the easy hole start operation is automatically applied when the trigger125is actuated. Further, in some embodiments, the control signals include pulse width modulated (PWM) signals having a duty cycle that is set in proportion to the amount of trigger pull of the trigger125, to thereby control the speed or torque of the motor400. FIGS.6A-6Fillustrates graphs of the easy hole start operation experienced by the power tool100.FIG.6Ashows a linear relationship of motor speed with time during an easy hole start operation600, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at a reduced speed value (e.g., 0%, 10% of full speed, etc.) and gradually increases at a linear rate until it reaches a target speed value605(e.g., full speed, a desired speed set by the user, etc.). When the motor speed reaches the target speed value605, the easy hole start operation ends. The motor speed persists at the target speed value605during target speed operation until the trigger125is released. In some embodiments, the initial reduced speed value is settable or configurable (e.g., by a user). For example, the reduced speed value can be set to 15% of maximum speed. The power tool100quickly accelerates up to the reduced speed value and then gradually, linearly increases speed up to the target speed value605. FIG.6Bshows a linear relationship of motor speed with time during an easy hole start operation610, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at a reduced speed value (e.g., 0%, 10% of full speed, etc.) and gradually increases at a linear rate until reaching a predetermined time threshold615(e.g., 120 seconds). When the predetermined time threshold615is reached and the motor400has not reached the target speed value605, the easy hole operation ends. For example, in response to reaching the predetermined time threshold615, the motor400is shut off. FIG.6Cshows a stepwise relationship of motor speed with time during an easy hole start operation620, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at reduced speed value (e.g., 0%, 10% of full speed, etc.) and increases according to a step-wise function until it reaches a target speed value625(e.g., full speed, a desired speed set by the user, etc.). When the motor speed reaches the target speed value625, the easy hole start operation ends. The motor speed persists at the target speed value625during target speed operation until the trigger125is released.FIG.6Dshows a stepwise relationship of motor speed with time during an easy hole start operation630, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at a reduced speed value (e.g., 0%, 10% of full speed, etc.) and gradually increases according to a step-wise function until reaching a predetermined time threshold635(e.g., 120 seconds). When the predetermined time635is reached and the motor400has not reached the target speed value625, the easy hole operation ends. For example, in response to reaching the predetermined time635, the motor400is shut off. FIG.6Eshows a nonlinear (e.g., exponential, polynomial, etc.) relationship of motor speed with time during an easy hole start operation640, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at a reduced speed value (e.g., 0%, 10% of full speed, etc.) and gradually increases at a nonlinear rate until it reaches a target speed value645(e.g., full speed, a desired speed set by the user, etc.). When the motor speed reaches the target speed value645, the easy hole start operation ends. The motor speed persists at the target speed value645during target speed operation until the trigger125is released.FIG.6Fshows a non-linear relationship of motor speed with time during an easy hole start operation650, according to some embodiments. Upon actuation of the trigger125of the power tool100, the motor speed starts at a reduced speed value (e.g., 0%, 10% of full speed, etc.) and gradually increases at a nonlinear rate until reaching a predetermined time threshold655(e.g., 120 seconds). When the predetermined time655is reached, the easy hole operation ends. For example, in response to reaching the predetermined time655, the motor400is shut off. FIG.7illustrates an easy hole start method700executed by the controller300of the power tool100. At block705, the controller300detects the actuation of the actuator or trigger125of the power tool100. The actuation of the trigger125is when the user depresses the trigger125. At block710, the controller300drives the motor400at a low speed value. As previously described, the controller300sends control signals to the power switching network365. The power switching network365includes a number of high side power switching elements365A,365B,365C and a number of low side power switching elements365D,365E,365F for driving the motor400. The controller300sends a control signal to the power switching network365to initially drive the switching elements such that they drive the motor400in a range of, for example, 1%-15% of a full speed of the motor400during the easy hole start operation. The easy hole start operation may persist in the range of 10 to 150 seconds. At block715, the controller300gradually increases the motor speed to a target speed value during a predetermined time period or threshold. In some embodiments, the speed of the motor400is gradually increased continuously during the easy hole start operation. As described above, the controller300may increase the speed linearly, according to a stepwise function, nonlinearly, etc. In some embodiments, the controller300continuously compares the instant speed of the motor to the target speed value during the gradual increase of the speed. For example, the controller300may compare the instant speed to the target speed to determine whether the instant speed has reached the target speed value. At block720, the controller300operates the motor400at the target speed value. The controller300then operates the motor400at the target speed value until, for example, the trigger125is released. FIG.8illustrates an easy hole start process or method800executed by the controller300of the power tool100. At block805, the controller300detects that the easy hole start switch135is in the ON position. As described above, the ON position may be when the easy hole start switch135is pressed or when the easy hole start switch135is slid to the ON position. At block810, the controller300detects the actuation of the actuator or trigger125of the power tool100. The actuation of the trigger125is when the user depresses the trigger125. At block815, the controller300drives the motor400at a low speed value. As previously described, the controller300sends control signals to the power switching network365. The power switching network365includes a number of high side power switching elements365A,365B,365C and a number of low side power switching elements365D,365E,365F for driving the motor400. The controller300sends a control signal to the power switching network365to drive the power switching elements such that they drive the motor400in a range of, for example, 1%-15% of a full speed of the motor400during the easy hole start operation. At block820, the controller300compares the time the motor400has been driven during the easy hole start operation to a predetermined time threshold. The predetermined time threshold may be in a range of, for example, 10 to 150 seconds. If the motor400has been driven for a time greater than the predetermined time threshold without reaching the target speed, then the method proceeds to block825. At block825, then the motor400is turned off. If the motor400has not been driven for a time greater than the predetermined time threshold, then the method proceeds to block830. At block830, the motor speed is gradually increased to a target speed value. If, at block835, the motor speed has not yet reached the target speed value, the method800returns to block820. If, at block835, the motor speed has reached the target speed value, the motor400is driven at the target speed value (block840). The controller300can then operate the motor400at the target speed value until the trigger125is released. Thus, embodiments described herein provide, among other things, systems and methods for performing an easy hole start operation for drilling power tools. Various features and advantages are set forth in the following claims. | 22,657 |
11942881 | DETAILED DESCRIPTION In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which it is shown by way of illustration specific examples or embodiments that can be implemented, and in which the same reference numerals and signs can be used to designate the same or like components even when they are shown in different accompanying drawings from one another. Further, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure rather unclear. The terms such as “including”, “having”, “containing”, “constituting” “make up of”, and “formed of” used herein are generally intended to allow other components to be added unless the terms are used with the term “only”. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. Terms, such as “first”, “second”, “A”, “B”, “(A)”, or “(B)” may be used herein to describe elements of the disclosure. Each of these terms is not used to define essence, order, sequence, or number of elements etc., but is used merely to distinguish the corresponding element from other elements. When it is mentioned that a first element “is connected or coupled to”, “contacts or overlaps” etc. a second element, it should be interpreted that, not only can the first element “be directly connected or coupled to” or “directly contact or overlap” the second element, but a third element can also be “interposed” between the first and second elements, or the first and second elements can “be connected or coupled to”, “contact or overlap”, etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that “are connected or coupled to”, “contact or overlap”, etc. each other. When time relative terms, such as “after,” “subsequent to,” “next,” “before,” and the like, are used to describe processes or operations of elements or configurations, or flows or steps in operating, processing, manufacturing methods, these terms may be used to describe non-consecutive or non-sequential processes or operations unless the term “directly” or “immediately” is used together. In addition, when any dimensions, relative sizes etc. are mentioned, it should be considered that numerical values for an elements or features, or corresponding information (e.g., level, range, etc.) include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.) even when a relevant description is not specified. Further, the term “may” fully encompasses all the meanings of the term “can”. A motor parameter measuring device10is described below with reference to the accompanying drawings, according to an embodiment of the disclosure. FIG.1is a block diagram illustrating a motor parameter measuring device10according to the disclosure. According to the disclosure, the motor parameter measuring device10may include a torque receiver110, a motor constant calculator120, and a parameter calculator130. The torque receiver110may receive the motor torque of the motor20rotated by external force. The motor20is a machine that obtains rotational force from electrical energy and may include a stator and a rotor. The motor20in the disclosure is described as, e.g., a permanent magnet synchronous motor (PMSM) but is not limited thereto. The torque receiver110may receive the torque of the motor20, measured by a motor performance tester, such as a torque meter or a servo motor, or may include a motor performance tester to directly measure the motor torque. The motor performance tester may rotate the motor20at a constant velocity or measure the torque of the motor20. The motor constant calculator120may calculate the motor constant based on the motor torque. Specifically, the motor constant calculator120may calculate the motor constant Ke based on the motor torque T based on Equation 1 below. T=32(Ke+P2(Iq-Id)Id)IqT=32KeIqKe=T23Iq[Equation1] In an embodiment, the motor constant calculator120may flow the synchronous coordinate system q-axis current while gradually increasing the q-axis current. For example, if the maximum allowable current of the motor20is 100 A, the motor constant calculator120may increase the current from 10 A gradually by 10 A and flow the current, calculating the motor constant at each point. In this case, the motor constant may be calculated, with the synchronous coordinate system d-axis current fixed to 0. As described above, the output of the motor20decreases as the current increases and, based thereupon, the motor parameter measuring device10may more accurately calculate the motor constant. It is also possible to derive the motor constant Ke without a separate additional device in a combination with a controller, e.g., an electronic control unit (ECU) and to identify the trend of changes in motor constant according to the current. FIG.2is a view illustrating calculation of a parameter of a motor20by forming a closed circuit according to an embodiment. Referring toFIG.2, the parameter calculator130may control the inverter210connected with the motor20to form a closed circuit and calculate the parameter of the motor20based on the current generated by the rotating motor20in the closed circuit. Specifically, the parameter calculator130may calculate the parameter of the motor20based on Equation 2 below. [vdvq]=[Ra+ddtLd-ωLqωLqRa+ddtLd][idiq]+[0ωΨa][Equation2] The parameter calculator130may apply the synchronous coordinate system d-axis voltage and q-axis voltage each of which is 0, calculating the parameter of the motor20. The parameters of the motor20may include, e.g., resistance R, synchronous coordinate system d-axis inductance Ld, and q-axis inductance Lq. The parameter may be calculated based on Equation 3 below. R=23TWIpeak2Ld=-(RIq+WmKe)WmP2IdLq=-RIqIqWmP2[Equation3] In the inverter210, the first high-side switching element211-1has a complementary relationship with the first low-side switching element211-2. Thus, the inverter210may control the first high-side switching element211-1to be open and control the second high-side switching element212-1and third high-side switching element213-1, which are connected in parallel with the first high-side switching element211-1and have the same structure, to be open. As a result, the first low-side switching element211-2, the second low-side switching element212-2, and the third low-side switching element213-2may be shorted, forming a closed circuit connected with the three phases of the motor20as shown inFIG.2. Conventional motor parameter measurement methods have several factors that may cause an error in calculating motor parameters. For example, the conventional methods perform measurement using additional devices and different methods and thus cause an error between the devices, influencing the accuracy of the motor parameter. Accordingly, the accuracy of resistance or inductance which is a small value may be degraded. In contrast, as described above, the motor parameter measuring device10may measure motor parameters simply and quickly by using a controller used for driving the motor20in the same facility while measuring the basic parameters of the motor20. FIG.3is a view illustrating a result of measuring a motor parameter according to an embodiment. Referring toFIG.3, a ofFIG.3shows a result of measuring the motor20by a conventional motor parameter measurement method, and b ofFIG.3shows a result of measuring the motor20according to the disclosure. The result of the conventional motor parameter measurement exhibits a larger measurement error than the result of measuring the motor20according to the disclosure. In other words, the result obtained by the conventional motor parameter measurement method has a larger variation than the result of measuring the parameter of the motor according to the disclosure. As described above, the disclosure may calculate a variation in inductance according to the current since the current is changed depending on the rotation velocity. Further, individual measurements may derive independent results and may calculate all of the parameter values of the motor20, such as the resistance of the measurement circuit, synchronous coordinate system d-axis inductance, and q-axis inductance. FIGS.4,5, and6are views illustrating detection of an error in a current sensor according to a measured current of a motor20according to an embodiment. The parameter calculator130may detect an error in the current sensor based on whether the synchronous coordinate system d-axis current or q-axis current ripples. FIG.4is a view illustrating the current value measured when the current sensor ofFIG.4is in a normal state. Specifically, if the motor20is shorted and rotated at a specific velocity, the output voltage may be fixed to 0. In this case, if the current flowed through the motor20by the counter-electromotive force is measured, the synchronous coordinate system d-axis current and q-axis current in the normal state of the current sensor may be measured within a predetermined current range. However, if ripples occur in the measured synchronous coordinate system d-axis current and q-axis current as shown inFIGS.5and6, the parameter calculator130may determine that an error has occurred in the current sensor. Whether the error comes from an offset or gain may be determined according to the order of the ripples caused in the measured synchronous coordinate system d-axis current and q-axis current. Referring toFIG.5, it may be identified that the first-order ripple occurs in the measured synchronous coordinate system d-axis current and q-axis current and, if the first-order ripple occurs in the measured synchronous coordinate system d-axis current and q-axis current, the parameter calculator130may determine that an offset error has occurred in the current sensor. Referring toFIG.6, it may be identified that the second-order ripple occurs in the measured synchronous coordinate system d-axis current and q-axis current and, if the second-order ripple occurs in the measured synchronous coordinate system d-axis current and q-axis current, the parameter calculator130may determine that a gain error has occurred in the current sensor. In an embodiment, the measured synchronous coordinate system d-axis current and q-axis current where the first-order ripple and the second-order ripple have occurred may have the same order. Described below is a method for measuring the parameters of the motor20using the motor parameter measuring device10capable of performing the above-described operations. FIG.7is a flowchart illustrating a motor20parameter measurement method according to the disclosure. Referring toFIG.7, according to the disclosure, a motor parameter measuring method may comprise a torque reception step S710receiving a motor torque of a motor20rotated by an external force, a motor constant calculation step S720calculating a motor constant based on the motor torque, and a parameter calculation step S730controlling an inverter210connected with the motor20to form a closed circuit and calculating a parameter of the motor20based on a current generated by the rotating motor in the closed circuit. The motor constant calculation step S720may flow the synchronous coordinate system q-axis current while gradually increasing the q-axis current and may calculate the motor constant whenever the current increases. In other words, the motor parameter measuring device10may calculate the motor constant according to the current. The motor constant calculation step S720may calculate the motor constant with the synchronous coordinate system d-axis current fixed to 0. The parameter calculation step S730may calculate the parameter by applying the synchronous coordinate system q-axis voltage and d-axis voltage of 0. The parameter calculation step S730may detect an error in the current sensor based on whether the synchronous coordinate system d-axis current or q-axis current ripples. The parameter calculation step S730may control the high-side switching element or low-side switching element for each phase of the inverter to simultaneously turn on, forming a closed circuit. As described above, according to the disclosure, the motor parameter measuring device and method may measure motor parameters simply and quickly by using a controller used for driving the motor in the same facility while measuring basic motor characteristics. The above description has been presented to enable any person skilled in the art to make and use the technical idea of the present disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and the accompanying drawings provide an example of the technical idea of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Thus, the scope of the present disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims. The scope of protection of the present disclosure should be construed based on the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included within the scope of the present disclosure. | 14,016 |
11942882 | DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. The present invention will be described in the context of motor control, and in particular embodiments, a multi-stage control method to start a PMSM, e.g., from standstill. The disclosed multi-stage control method is able to start the PMSM reliably and smoothly, even with a large load. The disclosed start-up control method may be applicable to other types of motors besides PMSM. FIG.1illustrates a schematic view of a permanent magnet synchronous motor (PMSM)50, in an embodiment. Note thatFIG.1is a high-level abstract of the PMSM intended to facilitate subsequent discussion. For simplicity, not all features of the PSMS50are illustrated inFIG.1. FIG.1illustrates a rotor15, a stator13, and windings11A,11B, and11C of the stator13. The windings11A,11B, and11C are connected to a three-phase power supply through nodes A, B, and C, respectively. The rotor15has permanent magnets embedded therein. The three-phase power supply generates a rotating magnetic field. The rotor15is driven (e.g., rotated) through the magnetic interaction between the rotating magnetic field and the magnetic field of the permanent magnets in the rotor15. The arrow16inFIG.1illustrates the direction of the magnetic moment of the rotor15(e.g., pointing from the south magnetic pole to the north magnetic pole of the rotor15), which may also be referred to as the direction of the rotor15.FIG.1further illustrates a two-axis coordinate system α-β defined by two orthogonal axes a and p. The two-axis coordinate system α-β is a stationary coordinate system referenced to the stator13. As one skilled in the art readily appreciates, the three-phase currents ia, ib, and ic(which are in a three-axis coordinate system) supplied to the windings11A,11B, and11C may be converted into current components iαand iβin the two-axis coordinate system α-β by a Clarke transformation: ia=ia, and iβ=−(ia+2ib)√{square root over (3)}. Note that the sum of the phase currents ia, ib, and icis zero (e.g., ia+i-+ic=0). Since the three-phase currents ia, ib, and ic, are time-varying, the current components iαand iβtransformed in the two-axis coordinate system α-β are also time varying, and may be represented by a rotating phasor in the two-axis coordinate system α-β. FIG.1further illustrates a two-axis coordinate system d-q defined by two orthogonal axes d and q. The two-axis coordinate system d-q is attached to the rotor15and rotates with the rotor15. For example, the axis d is aligned with the magnetic moment of the rotor15. One skilled in the art will also appreciate that the current components iαand ip in the two-axis coordinate system α-β may be transformed into current components idand iqin the two-axis coordinate system d-q by a Park transformation: id=iasin θ+iβcos θ, iq=iacos θ−iβsin θ, where the transformation angle θ used in the Park transformation is the angle of rotation between the two-axis coordinate system α-β and the two-axis coordinate system d-q. The transformation angle θ may be referred to as the transformation angle θ of the Park transformation, or the rotation angle θ between the Clarke transformation and the Park transformation. FIG.2illustrates a block diagram of a PMSM system100with field oriented control (FOC), in an embodiment. As illustrated inFIG.2, the PMSM system100includes a permanent magnet synchronous motor (PMSM)101, an inverter103coupled to the PMSM101, a control block150, and a controller115. The PMSM101may be the PMSM50ofFIG.1. In the example ofFIG.2, the rotor of the PMSM101does not have positions sensors, and therefore, the PMSM system100may also be referred to as a PMSM system with sensorless FOC. The inverter103may be, e.g., a DC-AC converter that generates the three-phase driving voltages (or the three-phase currents) supplied to the windings11A/11B/11C of the stator of the PMSM101. The control block150includes control loops for controlling operation of the PMSM101. The controller115may be, e.g., a micro-controller, that controls the operation of PMSM101by sending control signals and reference signals to the control block150. For example, as discussed in more details below, the controller115may generate control signals and reference signals for switching between difference phases of operation during start-up of the PMSM101. Note that the control block150inFIG.1is illustrated to show the functionalities of the control loops. The control block150may be formed by circuits/components outside of the controller115, in some embodiments. In some embodiments, some portions of the control block150, or all of the control block150, are formed as a software program executed by the controller115. For example, the PMSM system100may include a memory (e.g., a non-volatile memory) that stores a computer program (e.g., instructions), which when executed by the controller115, performs the functionalities of the control block150. As illustrated inFIG.2, the control block150includes a shunt current detection and reconstruction block105, which performs winding current detection and reconstruction to generate estimates of the phase currents ia, ib, and ic, in the windings of the PMSM101, which are denoted as ia,b,cinFIG.2. Methods for winding current detection and reconstruction are known in the art, and therefore, are not discussed here. The estimated phase currents ia, ib, and ic, are transformed by a Clarke transformation block107into current components iaand iβin the two-axis coordinate system α-β, which are denoted as iα,βinFIG.2. Clarke transformation is discussed above, thus not repeated here. The current components iαand iβin the two-axis coordinate system α-β are transformed into current component idand iqin the two-axis coordinate system d-q by a Park transformation. Park transformation is discussed above, thus not repeated. Note that depending on the switching position of the switch113, the transformation angle θ used in the Park transformation may be an angle θ* provided by the controller115, or an angle θESTprovided by a position and speed estimation block11of the control block150. The angle θESTis an estimate of the rotation angle θ (see, e.g.,FIG.1) between the two-axis coordinate system α-β and the two-axis coordinate system d-q, in some embodiments. Since the two-axis coordinate system d-q rotates with the rotor15, the angle θESTmay also be referred to as an (estimated) angle between the rotor15and the two-axis coordinate system α-β, or as an (estimated) angle between the rotor15and the stator13. As illustrated in the example ofFIG.2, based on the current components iαand iβand outputs of an inverse Park transformation block133(e.g., voltage signal Vaand Vg discussed below), the position and speed estimation block11provides the angle θEST, and provides a rotation speed f, as an estimate of the rotation speed of the rotor15of the PMSM101. Position and speed estimation are known in the art, thus are not discussed here. The switch113is controlled by the controller115to select, at different phases of the start-up process, different inputs (e.g., θ* or θEST) as the transformation angle θ used in the Park transformation. Details of the start-up process are discussed hereinafter. Still referring toFIG.2, the current component iqand idare compared with a first reference current value Iq** and a second reference current value Id**, respectively, to generate a first error signal124and a second error signal126. For example, the current component iqis subtracted from the first reference current value Iq** to generate the first error signal124, and the current component idis subtracted from the second reference current value Id** to generate the second error signal126. In some embodiments, the first reference current value Iq** is a reference current value used for controlling a torque current component (e.g., iq), and the second reference current value Id** is a reference current value used for controlling a flux current component (e.g., id). Therefore, the control block150ofFIG.2has two control loops: a first control loop that uses the first reference current value Iq** and is driven by the first error signal124, and a second control loop that uses the second reference current value Id** and is driven by the second error signal126. In the example ofFIG.2, the feedforward path of the first control loop includes the PI circuit127, the circle limitation block131, the inverse Park transformation block133, the SVPWM block135, and the inverter103. The feedback path of the first control loop includes the shunt current detection and reconstruction block105, the Clarke transformation block107, the Park transformation block109, and the position and speed estimation block11. The feedforward path of the second control loop includes the PI circuit129, and shares other functional blocks (e.g.,131,133,135, and103) with the feedforward path of the first control loop. The feedback path of the second control loop includes the same functional blocks (e.g.,105,107,111, and113) as the feedback path of the first control loop. As will be described in detail below, depending on the position of the switch121, the first control loop may be referred to as a torque control loop or a speed control loop. In particular, when the switch121selects the reference current value Iq1*, the first control loop is referred to as a torque control loop, and when the switch121selects the reference current value Iq2*, the first control loop is referred to as a speed control loop. Notably, in the example ofFIG.2, the second reference current value I** has a constant value of zero. Depending on the position of the switch121, the first reference current value Iq** may be a reference value Iq1* provided by the controller115, or may be a reference value Iq2* provided by a proportional-integral (PI) circuit117. The switch121is controlled by the controller115to select, at different phases of the start-up process, different reference current values (e.g., Iq1* or Iq2*). Details of the start-up process are discussed hereinafter. The first error signal124and the second error signal126are sent to PI circuits127and129, respectively. Proportional-integral (PI) circuits are widely used in control theory and are known in the art, thus not discussed here. The outputs of the PI circuits127and129are voltages Vqand Vqin the two-axis coordinate system d-q, respectively. The circle limitation block131checks whether the amplitude of the voltages (e.g., √{square root over (Vq2+Vd2)}) is within a pre-determined level (e.g., on a circle), and modifies (e.g., scales, or reduces at least one of the voltages Vdand Vq) the voltages Vdand Vqif the amplitude is larger than the pre-determined level, so that the amplitude of the modified voltages Vdand Vqis within the pre-determined level. The voltage signals at the output of the circle limitation block131is rotated back to the two-axis coordinate system α-β by an inverse Park transformation block133, to generate voltage signal Vaand Vβ, which are denoted as Vα,βinFIG.2. The voltage signal Vaand Vβare then transformed to voltages Va, Vb, and Vcusing an inverse Clarke transformation. In some embodiments, the voltages Va, Vb, and Vc, are used by a space vector pulse width modulation (SVPWM) block135to generate PWM signals, which PWM signals are used to drive the inverter103to generate the three-phase voltages (or three-phase currents) supplied to the windings of the PMSM101. In the example ofFIG.2, the inverse Clarke transformation function is combined with (e.g., implemented as a part of) the SVPWM block135to improve implementation efficiency. Inverse Park transformation and inverse Clarke transformation perform the inverse operations of the Park transformation and the Clarke transformation, respectively, details are not discussed here. The SVPWM block is known and used in the art, thus details are not discussed here. Operation of the PMSM system100during start-up of the PMSM101is a multi-phase process (also referred to as a multi-stage process) performed under the control of the controller115. The switching between the different phases (also referred to as different stages) of the multiple-phase process, or gear-switching, is discussed in detail below with reference toFIGS.3-5. FIG.3illustrates various signals during the start-up process of the PMSM system100ofFIG.2, in an embodiment. In particular, curve201illustrates the first reference current value Iq**, curve203illustrates the angle θ*, curve207illustrates the rotation speed of the rotor15, and the dashed line205illustrates the expected rotation speed of the rotor15during phase3of the start-up process. The x-axis ofFIG.3shows time, and the y-axis shows the values of the various signals. The start-up process of the PMSM system100may be partitioned into phases1-5, with time instants0, t1, t2, t3, and t4indicating the beginning of each of the phases. Referring toFIG.3, the start-up process starts at time instant o. The rotor15may be stopped (e.g., at standstill) at an unknown, random angular position prior to time instant o. In phase1of the start-up process, which is between time instant0and time instant t1, the rotor15is set to a known position by aligning the direction (e.g., the magnetic moment or the north magnetic pole of the rotor15) of the rotor15to a known direction, such as a pre-determined direction set by the controller115. In some embodiments, in phase1, the controller115switches the switch113to a position such that the angle θ* provided by the controller115is used as the transformation angle θ of the Park transformation block109(and the inverse Park transformation block133), and the controller115switches the switch121to a position such that the reference current value Iq1* provided by the controller115is used as the first reference current value Iq**. In the example ofFIG.3, the angle θ* has a constant value of, e.g., 90 degrees, between time instant0and time instant t2. The reference current value Iq1* provided by the controller115increases gradually from zero at time instant o to a pre-determined value at time instant t1, and remains constant between time instants t1and t4. By increasing the reference current value Iq1gradually from zero to the pre-determined value, overshoot of the rotor15may be avoided.FIG.4Ashows the aligning of the rotor15in phase1. Referring temporarily toFIG.4A, the rectangular shape in dashed line shows the position of the rotor15(illustrated as a magnetic bar with a north magnetic pole N and a south magnetic pole S) at time instant o, and the rectangular shape in solid line shows the position of the rotor15at time instant t1.FIG.4Aalso illustrates two current components Ivssqand Ivssd(which are generated by setting the angle θ* and the reference current value Iq1* as discussed above) in the two-coordinate system d-q, which is rotated by 90 degrees from the two-axis coordinate system α-β. Due to the interaction of magnetic forces, the rotor15turns to align with the direction of the current component Ivssq(e.g., a torque current component). Therefore, phase1is also referred to as a rotor positioning stage, or a rotor alignment stage. Referring back toFIG.3, phase2of the start-up, which is between time instants t1and t2, is used for the rotor15to settle down at the direction of the current component Ivssq. Phase2may last, e.g., between about 500 ms and about 1000 ms, so that the rotor15, which may oscillate around the direction of the current component Ivssq, settles down and stops at that direction. Phase2may also be referred to as a rotor settling stage or a rotor stabilization stage. Note that in phase2and phase3of the start-up process, the switches113and121remain at the same respective locations as in phase1. Next, at time instant t2, the direction of the current component Ivssqis changed abruptly (e.g., instantly or suddenly, instead of a gradual change) to rotate 90 degrees from the direction of the current component Ivssqin phase2. In some embodiments, to change the direction of the current component Ivssqabruptly, the controller115changes the value of the angle θ* suddenly from 90 degrees to 180 degrees, as illustrated by the spike, or a sudden change, in the value of the curve203at time instant t2.FIG.4Billustrates the abrupt change of the direction of the current component Ivssq. Referring temporarily toFIG.4B, at time instant t2, the direction of the current component Ivssqis rotated suddenly by 90 degrees from its position inFIG.4A. Due to inertia, the rotor15is still aligned to the same (vertical) direction as inFIG.4A. As a result, the direction of the magnetic moment (e.g., the flux direction) of the rotor15and the direction of the current component Ivssqhas a 90 degree offset (e.g., are perpendicular to each other), which maximizes the torque on the rotor15to start rotating the rotor15. Referring back toFIG.3, after the abrupt change of the direction of the current component Ivssqat time instant t2, the start-up process enters phase3, which is between the time instants t2and t3. During phase3, the controller115changes the value of the angle θ* continuously over a pre-determined range. For example, the controller115may sweep the angle θ* from −180 degree to 180 degree repeatedly (e.g., for multiple circles, as illustrated by the values of the curve203in phase3), or may sweep only a fraction of a circle. Sweeping the angle θ* effectively drags the rotor15to rotate with the rotating magnetic field generated by the currents in the stator windings. Note that in phase1, phase2, and phase3of the start-up process, the switch113does not select the output of the position and speed estimation block11. As such, the feedback paths of the first and second control loops of the control block150are not closed, and therefore, the first control loop and the second control loop of the control block150are open (also referred to as in open-loop state). Due to the open-loop status of the control loops, the rotor15are dragged along by the rotating magnetic field, but synchronization between the rotor and the rotating magnetic field are not guaranteed. Therefore, phase3is also referred to as an asynchronous driving stage. The dashed line205inFIG.3illustrates the expected speed of the rotor during phase3. The curve207shows the actual (e.g., measured, or estimated) rotation speed of the rotor. As illustrated inFIG.3, the rotation speed of the rotor increases gradually in phase3. Next, at time instant t3, the switch113ofFIG.2switches to a position such that the output θESTof the position and speed estimation block111is selected as an input (e.g., the transformation angle) of the Park transformation block109(and the inverse Park transformation block133), and therefore, the first control loop and the second control loop of the control block150are now closed (also referred to as in closed-loop mode). The start-up process now enters phase4, which is between time instants t3and t4. Note that in phase4, the switch121still selects the reference current I*1from the controller115. The reference current Iq1* may be set to a value (e.g., a constant value during phases2-4) corresponding to a large torque current component, such that a large torque is generated on the rotor15to drive the rotor15and to increase the rotation speed of the rotor15. Due to the position of the switch121in phase1-phase4, the first control loop of the control block150is also referred to as a torque control loop during phase1-phase4. The torque control loop is in open-loop mode in phases1-3, and is in closed-loop mode in phase4. Therefore, phase4is also referred to as the torque closed-loop control stage. Note that the angle θ* is no longer used for controlling the PMSM101after time instant t3, and therefore, its value is “don't care” for the PMSM system100after time instant t3. In the example ofFIG.3, in phase4and phase5, the angle θ* keeps its value at the end of phase3(e.g., at time instant t3). In phase4, the torque control loop provides a large torque to increase the rotation speed of the rotor. The torque control loop also has a quicker response time than the speed control loop described below. These characteristics advantageously reduces the possibility of the rotor and the rotating magnetic flux becoming out of synchronization, thereby reducing or preventing motor start failure. As illustrated inFIG.3, the rotation speed of the rotor increases continuously during phase4. When the rotation speed of the rotor reaches a pre-determined (e.g., at time instant t4), the start-up process enter phase5. At time instant t4, the controller115switches the switch121to a position such that the output Iq2* of the PI circuit117is selected as the first reference current value Iq**, and the start-up process enters phase5. Note that in phase5, the switch113still selects the output of the position and speed estimation block11, as in phase4. Note that the output Iq2* is computed by: subtracting an estimated rotation speed fr(which is generated by the position and speed estimation block111) from a target rotation speed fr* provided by the controller115to generate a speed error signal120, and send the speed error signal120to the PI circuit117. The output of the PI circuit117is the output Iq2*, which is used as the first reference current value Iq** in phase5. Due to the position of the switch121in phase5, the first control loop of the control block150is also referred to as a speed control loop, which speed control loop is in closed-loop mode. Phase5is also referred to as the speed closed-loop control stage. As illustrated by the curve201inFIG.3, in phase5, the first reference current value Iq** varies over time, because the estimated rotor rotation speed f varies over time. The curve207shows the rotation speed of the rotor, which oscillates around a target rotation speed. FIG.5illustrates various signals during start-up of the PMSM system ofFIG.2, in another embodiment. The signals shown inFIG.5may corresponds to a detailed view (e.g., a zoomed-in portion) ofFIG.3, or may be generated using different settings (e.g., difference reference current settings and/or different target rotation speed settings) for the PMSM system100.FIG.5shows curves201,207, and209between time instants t2and t4, where time instants t2, t3, and t4inFIG.5correspond to time instants t2, t3, and4inFIG.3. InFIG.5, the curve201shows the first reference current value Iq**, the curve207shows the actual (e.g., measured) rotation speed of the rotor, and the curve209shows the phase current of one of the three-phase currents supplied to the windings of the stator. FIG.6illustrates a load torque of a compressor, in an embodiment. As illustrated inFIG.6, the load torque may vary depends on the mechanical rotation angle of the rotor. If, during the start-up process, the rotor is at an angle with high load torque, it may be hard to switch into the speed control loop at that angle, due to, e.g., the relative slow response time and lower torque of the speed control loop. The presently disclosed multi-stage method, by abruptly changing the direction of the current component Ivssqat time instant t2(to start the motor at maximum torque), and by using the asynchronous driving stage and the torque closed-loop control stage (which provides large torque and fast response time) to speed up the rotor to a stable, pre-determined rotation speed, ensures a smooth transition to the final speed closed-loop control stage, and avoids or reduces motor start failure. FIG.7illustrates a flow chart of a method1000of starting a PMSM with field oriented control (FOC), in an embodiment. It should be understood that the embodiment method shown inFIG.7is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated inFIG.7may be added, removed, replaced, rearranged, or repeated. Referring toFIG.7, at block1010, a control loop of the PMSM is set in open-loop mode. At block1020, while the control loop is in open-loop mode: a first direction for a first current component of the PMSM is set; a rotor of the PMSM is positioned along the first direction; after positioning the rotor, a second direction for the first current component is abruptly set, wherein the second direction is perpendicular to the first direction; and after abruptly setting the second direction, the rotor is asynchronously driven to rotate the rotor. At block1030, after asynchronously driving the rotor for a first period of time, the control loop is operated in a first closed-loop mode. At block1040, after operating the control loop in the first closed-loop mode for a second period of time, the control loop is operated in a second closed-loop mode different from the first closed-loop mode. Disclosed embodiments may achieve advantages. For example, the disclosed multi-stage method abruptly changes the direction of the current component Ivssqat time instant t2, this allows the motor to start at a maximum torque. After the asynchronous driving stage, the torque closed-loop control stage provides a large torque and fast response time to further speed up the rotor. Transition to the speed closed-loop control stage is performed after the rotor speed reaches a stable, pre-determined rotation speed. This ensures a smooth start-up process, and avoids or reduces motor start failure. The disclosed method is able to start PMSM at high load previously unachievable. For example, consider a scenario where while a refrigerator compressor (e.g., a PMSM) is running, the power is suddenly lost, and then comes back on. The resulting internal pressure in the compressor is very high, and the compressor may need to start with suction pressure at 0.1 MPa and exhaust pressure at 0.6 MPa. A conventional start-up control method without the presently disclosed method may not be able to start the compressor. The disclosed method herein, however, is able to smoothly start the compressor up with the high back pressure. Example embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein. Example 1. In an embodiment, a method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: opening a first control loop of the PMSM; setting a first direction for a first current component of the PMSM; aligning a rotor of the PMSM to the first direction; after aligning the rotor, setting a second direction for the first current component, where the second direction is rotated from the first direction by 90 degrees; after setting the second direction, starting the rotor while the first control loop of the PMSM remains open; after starting the rotor, increasing a rotation speed of the rotor by operating the first control loop in a first closed-loop mode; and after increasing the rotation speed of the rotor, controlling the rotation speed of the rotor by operating the first control loop in a second closed-loop mode different from the first closed-loop mode. Example 2. The method of Example 1, wherein setting the second direction comprises changing a direction of the first current component from the first direction to the second direction abruptly. Example 3. The method of Example 1, wherein operating the first control loop in the second closed-loop mode comprises setting the first control loop in the second closed-loop mode after the rotation speed of the rotor reaches a pre-determined rotation speed. Example 4. The method of Example 1, wherein the first current component is perpendicular to a second current component of the PMSM, wherein the first current component and the second current component are obtained by transforming phase currents supplied to windings of a stator of the PMSM using a Clarke transformation followed by a Park transformation. Example 5. The method of Example 4, wherein aligning the rotor comprises aligning a magnetic moment of the rotor with the first direction of the first current component. Example 6. The method of Example 4, wherein the first control loop is driven by a first error signal, wherein the PMSM further has a second control loop driven by a second error signal, wherein the first error signal is a first difference between a first reference current value and the first current component of the PMSM, and the second error signal is a second difference between a second reference current value and the second current component of the PMSM. Example 7. The method of Example 6, wherein the second reference current value has a constant value of zero. Example 8. The method of Example 6, wherein setting the first direction for the first current component comprises: setting a transformation angle of the Park transformation to a first angle; and setting the first reference current value to a pre-determined current value. Example 9. The method of Example 8, wherein setting the second direction for the first current component comprises setting the transformation angle of the Park transformation to a second angle, wherein the second angle is rotated 90 degrees from the first angle. Example 10. The method of Example 9, wherein the starting the rotor comprises sweeping the transformation angle of the Park transformation across a pre-determined range of angles. Example 11. The method of Example 8, wherein setting the first reference current value comprises gradually increasing the first reference current value from zero to the pre-determined current value, wherein the first reference current value remains at the pre-determined current value after aligning the rotor and before operating the first control loop in the second closed-loop mode. Example 12. The method of Example 11, wherein operating the first control loop in the second closed-loop mode comprises: calculating a difference between a target rotation speed of the rotor and an estimated rotation speed of the rotor; sending the calculated difference to a Proportional-Integral (PI) circuit; and using an output of the PI circuit as the first reference current value for the first control loop. Example 13. In an embodiment, a method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: setting a control loop of the PMSM in open-loop mode; and while the control loop is in open-loop mode: setting a first direction for a first current component of the PMSM; positioning a rotor of the PMSM along the first direction; after positioning the rotor, abruptly setting a second direction for the first current component, wherein the second direction is perpendicular to the first direction; and after abruptly setting the second direction, asynchronously driving the rotor to rotate the rotor. The method further includes: after asynchronously driving the rotor for a first period of time, operating the control loop in a first closed-loop mode; and after operating the control loop in the first closed-loop mode for a second period of time, operating the control loop in a second closed-loop mode different from the first closed-loop mode. Example 14. The method of Example 13, wherein the PMSM has a second current component perpendicular to the first current component, wherein the first current component and the second current component are in a two-axis coordinate system that is rotating with the rotor, wherein the first current component and the second current component are related to three-phase currents supplied to windings of a stator of the PMSM through a Clarke transformation and a Park transformation. Example 15. The method of Example 14, wherein asynchronously driving the rotor comprises: providing, by a controller of the PMSM, a transformation angle for the Park transformation, wherein the transformation angle sweeps cross a pre-determined range of angles; computing a first error signal by subtracting the first current component from a first reference current value provided by the controller of the PMSM, wherein the first reference current value has a first constant value; computing a second error signal by subtracting the second current component from a second reference current value having a second constant value; and generating driving voltages for the windings of the stator of the PMSM based on the first error signal and the second error signal. Example 16. The method of Example 15, wherein operating the control loop in the first closed-loop mode comprises: estimating an angle between the rotor and the stator of the PMSM and using the estimated angle as the transformation angle of the Park transformation; computing a third error signal by subtracting the first current component from the first reference current value having the first constant value; computing a fourth error signal by subtracting the second current component from the second reference current value having the second constant value; and generating the driving voltages for the windings of the stator of the PMSM based on the third error signal and the fourth error signal. Example 17. The method of Example 16, wherein operating the control loop in the second closed-loop mode comprises: estimating the angle between the rotor and the stator of the PMSM and using the estimated angle as the transformation angle of the Park transformation; computing a fifth error signal by subtracting the first current component from a third reference current value, wherein the third reference current value is calculated based on a target rotation speed of the rotor and an estimated rotation speed of the rotor; computing a sixth error signal by subtracting the second current component from the second reference current value having the second constant value; and generating the driving voltages for the windings of the stator of the PMSM based on the fifth error signal and the sixth error signal. Example 18. In an embodiment, a permanent magnet synchronous motor (PMSM) system with field oriented control (FOC) includes: a PMSM motor; an inverter coupled to the PMSM motor; and a controller coupled to the inverter, wherein the controller is configured to start the PMSM by: setting a control loop of the PMSM in open-loop mode; while the control loop is in open-loop mode: setting a first direction for a first current component of the PMSM; positioning a rotor of the PMSM along the first direction; after positioning the rotor, abruptly setting a second direction for the first current component, wherein the second direction is perpendicular to the first direction; and after abruptly setting the second direction, asynchronously driving the rotor to rotate the rotor; after asynchronously driving the rotor for a first period of time, operating the control loop in a first closed-loop mode; and after operating the control loop in the first closed-loop mode for a second period of time, operating the control loop in a second closed-loop mode different from the first closed-loop mode. Example 19. The PMSM system of Example 18, wherein the controller is configured to supply a reference value for the control loop, wherein after positioning the rotor and before operating the control loop in the second closed-loop mode, the reference value has a constant value. Example 20. The PMSM of Example 19, wherein after operating the control loop in the second closed-loop mode, the reference value has a time-varying value. While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments. | 36,470 |
11942883 | FIG.1shows a machine10in which a motor12moves a slide14to and fro. For this purpose, the motor12drives a crank16which in turn moves the slide14via a connecting rod18. The motor12is controlled by a drive control26(seeFIG.2andFIG.3). In this respect, the motor12together with the crank16is considered as the first component K1and the slide14together with the connecting rod18is considered as the second component K2. The design of the machine10shown here is purely exemplary and only serves to illustrate the creation of the simulation model. The simulation model can in this respect also be created for considerably more complex machines10having a plurality of components. FIG.2shows the procedure for creating a simulation model, i.e. the initialization phase. For this purpose, a three-dimensional model of the machine10is generated by CAD software20. The three-dimensional model is transferred to a simulation environment22(e.g. industrialPhysics). In the simulation environment, a secondary simulation model25is first generated from the three-dimensional model. The simulation environment22is linked to the drive control26in the initialization phase. In the initialization phase, the drive control26executes an execution program28by means of a movement setpoint generator (not shown). The movement setpoint generator repeatedly supplies the (simulated) angular position f of the drive axis of the motor12to the simulation environment22. The simulation environment22calculates the respective position x of the slide14from the angular position f by means of the secondary simulation model25. The position x of the slide14is then transmitted to the drive control26, wherein the drive control26generates a transfer function x(f) from the angular position f and from the position x of the slide, said transfer function x(f) then being part of a simulation model24. The transfer function x(f) is stored as a value table having a large number of value pairs (f and x) in the drive control26. Mechanical parameters of the mechanical system of the machine10are additionally provided or calculated in the simulation environment22. For example, the overall moment of inertia (Jload) to be overcome by the motor12, the speed-dependent torque (VISC) to be overcome by the motor12and the static torque (STAT) to be overcome by the motor can be determined in this respect. The drive control26forms the simulation model24from the transfer function x(f) and from the determined or specified parameters. The data required for this purpose is transferred from the secondary simulation model25from the simulation environment22by means of a data line, for example. The use of the simulation model24in operation is shown inFIG.3.FIG.3therefore shows the operating phase. In the operation of the machine10, there is no connection between the drive control26and the simulation environment22, but the simulation model24is rather solely executed by the drive control26. An execution program28accesses the simulation model24in this respect and carries out a simulation based on the simulation model24. Based on the data obtained in the simulation, e.g. a torque to be applied/to be provided by the motor12, the execution program28carries out a feedforward control30of the motor12to achieve an improved running behavior of the motor12in this manner. In addition, the simulation model24and also the secondary simulation model25can still be updated and/or improved by measurements at the machine10. For this purpose, the simulation environment22and the drive control26can be coupled to one another again, as shown inFIG.2. The improvement and/or the update can also be performed in the drive control26itself. Alternatively or additionally, the improvement and/or the update can also take place in the simulation environment22. For this purpose, the measurements can be transferred from the drive control26to the simulation environment22, as shown by an arrow inFIG.2. REFERENCE NUMERAL LIST 10machine12motor14slide16crank18connecting rod20CAD software22simulation environment24simulation model25secondary simulation model26drive control28execution program30feedforward controlK1first componentK2second componentf motor movementx(f) transfer function | 4,233 |
11942884 | MODE(S) FOR CARRYING OUT INVENTION The following describes embodiments of the present invention with reference to the drawings. The present invention is not limited to the following embodiments, but may be implemented in various manners. In patent document 1, a model of a vehicle is defined by a mathematical expression. When expressed as a block diagram and a transfer function using a Laplace operator, the model is expressed by Gp(S) inFIG.1. Basically, the vehicle model is the same as inFIG.4of patent document 1. However, a model becomes complicated due to factors such as gear ratios, a tire radius, etc. Therefore, a general concept of a per-unit system is used to transform the vehicle model to a normalized model based on a rated torque and a rated rotational speed. As a result, the unit system is unified, so that gear ratios, a tire radius, etc., do not appear explicitly, and the control block diagram is simplified. Although description of terms, “per-unit system” and “normalization”, is omitted, the rotational inertia of a motor and the inertia of a vehicle body are each replaced by a time constant until the rated speed is reached after the rated torque is inputted. By introducing the time constants, it becomes possible to quantitatively compare a plurality of inertial components with each other, and use the time constants for judgment about approximation. Variables and constants inFIG.1are defined as follows.TJm: a time constant equivalent to motor inertia,TJw: a time constant equivalent to driving wheel inertia (a combined value of driving wheels),TJm: a time constant equivalent to vehicle mass,Kd: a torsional stiffness coefficient of driveline,Kt: a coefficient relating to friction between tire and road surface,ωm: a motor angular speed,ωw: a driving wheel angular speed,ωm: a vehicle speed,Tm: a motor torque,Td: a driving wheel torque,Tt: a torque between tire and road surface, andTF: an external force applied to vehicle (disturbance torque component). In the above description, “T” is used for variables relating to torque, and “TJ” is used for time constants produced by conversion from rotational inertias, in order to avoid confusion between torques and time constants. For description of a control system, an actual plant and a model used in a control section are described. This may be likely to cause confusion between them. Therefore, for distinguishing a coefficient or variable relating to the control model, a symbol “{circumflex over ( )}” is added to the beginning of the coefficient or variable, in second and following embodiments. Integral blocks are represented by transfer functions in mathematical expression (1), where “s” is the Laplace operator. Gd(s)=Kds,Gm(s)=1TJm·s,Gw(s)=1TJw·s,GM(s)=1TJM·s(1) A subtractor11subtracts the driving wheel torque Tdfrom the motor torque (output torque command) Tmto output the motor torque (motor-accelerating torque) TmA. A Gm(s) block12multiplies the output of the subtractor11by a transfer function Gm(s) to output the motor angular speed ωm. A subtractor13subtracts the driving wheel angular speed ωwfrom the motor angular speed ωm. A Gd(s) block14multiplies the output of the subtractor13by a transfer function Gd(s) to output the driving wheel torque Td. A subtractor15subtracts the torque Tt between tires and a road surface from the driving wheel torque Td. A Gw(s) block16multiplies the output of the subtractor15by a transfer function Gw(s) to output the driving wheel angular speed ωw. A subtractor17subtracts the vehicle speed ωMfrom the driving wheel angular speed ωw. A Ktblock18multiplies the output of the subtractor17by a coefficient Ktrelating to friction between the tires and the road surface, and outputs the torque Ttbetween the tires and the road surface. A subtractor19subtracts the external force (disturbance torque component) TFapplied to the vehicle from the torque Ttbetween the tire and the road surface. A GM(s) block20multiplies the output of the subtractor19by a transfer function GM(s) to output the vehicle speed ωM. The subtractors15,17,19and blocks16,18,20are defined as a transfer function GTdWw(s). The configuration ofFIG.1is a multi-stage feedback configuration. Accordingly, as the disturbance component TFis ignored and the blocks are developed in order from the bottom, this model system is expressed by transfer functions of mathematical expressions (2) and (3). Namely, as the section from the torsional torque of the elastic shaft (driving wheel torque) Tdto the tire speed (driving wheel angular speed) ωwis defined as a transfer function GTdWw(s), GTdWw(s) is expressed by mathematical expression (2). GTdWw(s)=ωwTd=1TJw·s1+1TJw·s·GWwTt(s)=1TJw·s1+1TJw·s·TJM·sTJMKt·s+1=1(TJw+TJM)·s·TJMKt·s+11Kt·TJw·TJMTJw+TJM·s+1(2) The transfer function Gp(s), which is a transfer function of the entire model from the electromagnetically generated motor torque (output torque command) Tmto the motor rotational speed (angular speed) ωm, is a product of an integral term and a third order term as expressed by mathematical expression (3). Here, the sum of rotational inertias is represented by TJΣ=TJm+TJw+TJM. Gp(s)=ωmTm=1TJ∑·s·TJwTJMKt·Kd·s3+TJw+TJMKd·s2+TJMKt·s+1TJm·TJw·TJMTJ∑·Kt·Kd·s3+TJm·(TJw+TJM)TJ∑·Kd·s2+(TJM·TJw)TJ∑·Kt·s+1(TJ∑=TJm+TJw+TJM)(3) The integral term in mathematical expression (3) contains a time constant equivalent to a combined component of all of the rotational inertias. Correcting coefficients so as to separate the integral term into a combination of an integral term of the motor rational inertia, Gm(s)=1/(TJm·s), and Fp(s), as in mathematical expression (4), gives a filter section (Fp(s)) expressed by mathematical expression (5). Gp(s)=Gm(s)·Fp(s)(4)Fp(s)=TJmTJΣ·TJw·TJMKt·Kd·s3+TJw+TJMKd·s2+TJMKt·s+1TJm·TJw·TJMTJΣ·Kt·Kd·s3+TJm·(TJw+TJM)TJΣ·Kd·s2+TJM·(TJm+TJw)TJΣ·Kt·s+1(5) In a first embodiment, mathematical expression (5) is simplified and then used for vibration suppression control. Mathematical expressions (4) and (5) represent the configuration ofFIG.1. This configuration is approximated to reduce the number of components as shown inFIG.2. This approximation is described in terms of transfer functions. The approximation is applied to mathematical expression (2), which corresponds to replacing GTdWw(s) inFIG.1with GTdWw2(s) inFIG.2. The transfer function GTdWw2(s) inFIG.2includes: a Dsblock21that multiplies the driving wheel torque Tdby a slip coefficient Dsto output a tire slip speed ωslip; a 1/TJwM(s) block22that integrates the driving wheel torque Tdby the combined rotational inertia TJwMof the tires and the vehicle body to output the tire and vehicle body speed ωwM; and an adder23that sums the speeds ωslipand ωwMto output the driving wheel angular speed ωw. Mathematical expression (2) is composed of a product of an integral term and a first order filter. The coefficients in the denominator of the first order filter are approximated as mathematical expression (6). 1Kt·TJw·TJMTJw+TJM1Kt·TJw·TJMTJMTJwKt⪡1(6) In general, when the inertia of the vehicle body and the rotational inertia of the tires are compared in terms of time constants, the time constant of the tires is much smaller (TJM>>TJw). Furthermore, the tire coefficient Kthas a large value (Kt>>1). From these two characteristics, it can be seen that the coefficient of the denominator of the first order filter part in mathematical expression (2) is much smaller than 1 with reference to a relationship in mathematical expression (6). The denominator of this first order filter part represents characteristics of a low-pass filter (LPF), where the reciprocal of mathematical expression (6) corresponds to a corner frequency. The fact that mathematical expression (6) has a small value means that this LPF attenuates only fairly high frequency components. Accordingly, if the corner frequency is sufficiently high with respect to a resonant frequency or a band of compensation of the vibration suppression control, it can be considered irrelevant from the vibration suppression control. By regarding the value of mathematical expression (6) as zero and approximating the denominator side of the first order filter part to a unity gain (=1), the mathematical expression (2) is approximated to mathematical expression (7), which is equivalent to a sum of a proportional term Dsin mathematical expression (8) and an integral with the time constant TJwMin mathematical expression (9). GTdWw2(s)=··(TJM/Kt)·s+1(TJw+TJM)·s=TJM(TJw+TJM)·Kt+1(TJw+TJM)·s=Ds+1TJwM·s(7)Ds=TJM(TJw+TJM)·Kt(8)TJwM=TJw+TJM(9) As in mathematical expression (9), TJwMrepresents the combined rotational inertia of the tires and the vehicle body. In mathematical expression (8), D s is a coefficient representing a tire slip characteristic, and corresponds to a slip coefficient for calculating the slip speed ωslipthat is caused by the driving force (driving wheel torque) Tdapplied to the tire axle. By applying the above approximation, mathematical expressions (4) and (5) are simplified to mathematical expressions (10) and (11). Gp(s)=··Gp2(s)=Gm(s)·Fp2(s)(10)Fp2(s)=s2+Kd·Ds·s+KdTJwMs2+Kd·Ds·s+Kd·(1TJwM+1TJm)(11) By simplifying the third order filter Fp(s) expressed by mathematical expression (5) to the second order filter Fp2(S) expressed by mathematical expression (11), characteristics can be represented in a general system with a natural frequency of a second order equation and a viscosity ratio, and control design can be carried out using a model approximated into a two-inertia system. Ends of the elastic shaft are connected to the motor shaft and the tire axle. The vibration suppression control uses a difference in speed between both ends and a torsional phase, wherein the torsional phase is produced by time-integrating the speed difference. If there is no need to refer to individual speeds of the motor and tires, the integral terms in the block diagram shown inFIG.2can be commonized and reduced as shown inFIG.3(approximate model of this embodiment). First, the integral time constants TJmand TJwMare isolated and used to calculate individual acceleration components (Amand AwM). Then, the difference between these accelerations is integrated to calculate the speed difference (torsional speed). Furthermore, since the component obtained by differentiating the motor speed is used for the vibration suppression control as described below, it is modified so that the input component TmAto the integral term of the motor is outputted. With the configuration shown inFIG.3, the number of integrators can be reduced to two. This output component TmAis produced by subtracting a reaction force (driving wheel torque) Td, which corresponds to a torque transmitted to the elastic shaft and is applied to the output shaft of the motor, from the electromagnetic torque (Tm) generated between the stator and rotor of the motor. Since the output component TmAis proportional to the acceleration Am of the motor, the output component TmAis henceforth referred to as “motor-accelerating torque”. InFIG.3, the same parts as those inFIGS.1and2are denoted by the same reference numerals. A divider25divides the motor-accelerating torque TmA, which is obtained by subtracting the driving wheel torque Tdfrom the output torque command Tmby the subtractor11, by the time constant equivalent to the rotational inertia of the motor (TJm), and outputs the motor side acceleration Am. A divider26divides the driving wheel torque Tdby the combined rotational inertia TJwMof the tires and the vehicle body to output the vehicle body side acceleration AwM. A subtractor27obtains a deviation between the motor-side acceleration Am and the vehicle-side acceleration AwM. An integrator28time-integrates the outputted deviation to produce a relative speed (ωm-ωwM) between the motor and the vehicle body. A subtractor29subtracts the tire slip speed ωslip, which is produced by multiplying the driving wheel torque Tdby the slip coefficient Ds, from the motor/vehicle relative speed (ωm-ωwM) to produce a motor/tire relative speed (relative torsional speed of the elastic shaft) ωd. A Gd(s) block14multiplies the motor/tire relative speed ωd, which is outputted from the subtractor29, by a transfer function Gd(s) to output the driving wheel torque Td. When represented by a transfer function, the configuration ofFIG.3is expressed by GPTmA2(s) in mathematical expression (12), which is equal to the second order filter FP2(s) in mathematical expression (11). It is known that in a two-inertia system, the denominator represents resonant characteristics and the numerator represents anti-resonant characteristics. A second order mathematical expression like mathematical expression (12) can be treated in terms of a natural frequency and a damping ratio. In this embodiment, this mathematical expression (12) is used for designing a vibration suppression control. GpTmA2=s2+(Kd·Ds)·s+Kd·1TJwMs2+(Kd·Ds·s)+Kd·(1TJm+1TJwM)=s2+2·ζa·ωa·s+ωa2s2+2·ζr·ωr·s+ωr2(12)wheres: a Laplace operator,ωr=√/(Kd·(1/TJm+1/TJwM),ωa=√/(Kd·(1/TJwM)),ζr=(Kd·Ds)/(2·ωr),ζa=(Kd·Ds)/(2·ωa),Ds=TJM/(TJw+TJM)·Kt,TJm: a time constant equivalent to motor inertia,TJw: a time constant equivalent to driving wheel inertia (a combined value of multiple driving wheels),TJM: a time constant equivalent to vehicle mass,Kd: a torsional stiffness coefficient of driveline (gears, an elastic shaft, etc.),Kt: a coefficient relating to friction between tire and road surface, andTJwM=TJw+TJM. First Embodiment FIG.4(a)shows an example of configuration of a vibration suppression control system according to the first embodiment, in which feedback compensation of Gcomp(s) is applied to a controlled plant GP(s). In Gcomp(s), a measured speed ωmis differentiated by 1/{circumflex over ( )}Gm(s) of a differentiator31to produce a motor-accelerating torque component TmA*, which is caused to pass through a band-pass filter Fcomp(s) (vibration suppression control filter) to produce a compensation torque component TFcomp, which is fed back to an input torque command Tref. Namely, a subtractor32subtracts the compensation torque component TFcompfrom the input torque command Trefto output an output torque command Tm. Mathematical expression (13) is employed for this bandpass filter Fcomp(s). In mathematical expression (13), ζAis a sole adjustable parameter, and except for this parameter, the natural frequency and damping ratio of mathematical expression (12) are used. Fcomp(s)=2·(ζΛ-ζr)·ωr·ss2+2·ζa·ωa·s+ωa2(13) The plant side inFIG.4(a)can be separated into the integral term Gm(s) of the motor and the filter part GPTmA(s), and Gm(s) of the actual plant and Gm(s) of the control model are approximated to be equal to each other as shown inFIG.4(b). As the filter section GPTmA(s) is also approximated to GPTmA2(s), only a feedback FP-comp(s) and Gm(s) remain as shown inFIG.4(c). Accordingly, it is sufficient to approximate FP-comp(s) as in mathematical expression (14), and design Fcomp(s) to have stable characteristics. Fp-comp(s)=Fp(s)1+Fp(s)·Fcomp(s)=··GpTmA2(s)1+GpTmA2(s)·Fcomp(s)(14) Substituting the mathematical expression (12) for the approximate model and mathematical expression (13) for the compensation filter into mathematical expression (14) yields a second order mathematical expression (15). Fp-comp(s)=··Fp2(s)1+Fp2(s)·Fcomp(s)=s2+2·ζa·ωa·s+ωa2s2+2·ζr·ωr·s+ωr21+s2+2·ζa·ωa·s+ωa2s2+2·ζr·ωr·s+ωr2·2·(ζA-ζr)·ωr·ss2+2·ζa·ωa·s+ωa2=s2+2·ζa·ωa·s+ωa2s2+2·ζA·ωr·s+ωr2(15) Since the adjustable parameter ζAcorresponds to the viscosity ratio of the denominator, setting “ζA=1” makes the denominator have a double root and thereby makes the system become stable, which means that the band pass filter Fcomp(S) has been designed suitably. Actually, model errors exist, so that it is required to set ζAto a small value. Ideally, it is sufficient to set ζAas ζA=1. Mathematical expression (15) is obtained by approximating the filter characteristic part of the plant to mathematical expression (11). The use of the approximate model makes it easy to design the compensator. According to the first embodiment, by approximating the configuration ofFIG.1to the model configuration of two-inertia system inFIG.2, it is possible to reduce the order of the transfer function as in mathematical expression (10) and mathematical expression (11). Furthermore, by modifying the model to output the motor-accelerating torque as shown inFIG.3, it is possible to express the characteristics by a general system based on a second order filter with a natural frequency and a viscosity ratio of a second order mathematical expression. This makes it possible to easily grasp the characteristics of resonance and anti-resonance of a controlled object. By using this simplified second order mathematical expression, it is possible to easily design the filter characteristics of the feedback control of mathematical expression (13) required for constructing the vibration suppression control ofFIG.4(a). Second Embodiment The vibration suppression control designed in the first embodiment still has issues. It is required to take countermeasures against gear backlash and tire coefficient (friction coefficient) fluctuations. As a preliminary step, in this section as a second embodiment, a method is proposed for realizing a disturbance torque observer using the approximate model ofFIG.3. FIG.5shows an example of configuration of a general disturbance torque observer. Symbols and variables are defined for components as follows.Gp(s): a model of a plant to be controlled,{circumflex over ( )}GP(s): a model in control,Kg: an observer gain,{circumflex over ( )}ωm: a motor speed estimated by control model,Tmdist: a disturbance torque component converted to motor shaft torque, and{circumflex over ( )}Tobs: an estimated disturbance torque. Originally, a gradient such as on a climbing road acts as an external force on the vehicle body, and a decelerating force due to braking acts as a disturbance torque on the tire axle. However, since only the motor speed is measured, these disturbance torque components are collectively defined as Tmdist, which is a quantity produced by conversion to the motor shaft. This disturbance torque is estimated as {circumflex over ( )}Tobsby a disturbance torque observer. FIG.5shows a general structure, in which subtracting Tmdistfrom the output torque command Tmby the subtractor41yields a quantity, and the quantity is inputted to the plant model Gp(s) to output a speed corresponding to the measured speed ωm. On the observer side, a subtractor44subtracts {circumflex over ( )}Tobsfrom the output torque command Tmto produce a quantity, which is inputted to the model {circumflex over ( )}GP(s) to calculate the estimated speed {circumflex over ( )}ωm; a subtractor42calculates a difference between the estimated speed {circumflex over ( )}ωmand the measured speed ωmfrom the plant; a gain multiplier43multiplies the difference by an observer gain Kg to produce the estimated disturbance torque {circumflex over ( )}Tobs, and feeds the estimated disturbance torque {circumflex over ( )}Tobsback to the subtractor44to which the model input torque is inputted. In the second embodiment, the general configuration ofFIG.5is further modified to a configuration shown inFIG.6. InFIG.4(a)showing the vibration suppression control according to the first embodiment, the torque accelerating the motor (motor-accelerating torque component) TmA* is calculated by application of 1/Gm(s)=(TJm·s), which corresponds to differentiation, to the measured speed. On the other hand, the model inFIG.3also outputs TmAequivalent to TmA*. Accordingly, by using the approximate model inFIG.3and replacing the speed difference component ({circumflex over ( )}ωm-ωm) inFIG.5with the difference in motor-accelerating torque ({circumflex over ( )}TmA-TmA*) (output of a subtractor51), it is possible to implement a disturbance torque observer that uses TmA*, which has already been calculated in the vibration suppression control. For actual implementation in a digital controller, the second order transfer function of mathematical expression (12) is used to suppress a discrete time error. InFIG.6, the same parts as inFIGS.3and5are denoted by the same reference numerals. The estimated motor-accelerating torque component {circumflex over ( )}TmA(=({circumflex over ( )}TJm·s)·{circumflex over ( )}ωm), which is outputted from a subtractor11in the approximate model GPTmA2(s), is taken into a subtractor51. The subtractor51calculates the difference between the estimated motor-accelerating torque component {circumflex over ( )}TmAand the motor-accelerating torque component TmA*(=({circumflex over ( )}TJm·s)·ωm) that is produced by causing the motor angular speed ωmto pass through a differentiator31. The output ({circumflex over ( )}TJm·s)·Δωmof the subtractor51is integrated by an integrator52and then multiplied by the observer gain Kgof a gain multiplier43to produce the estimated disturbance torque {circumflex over ( )}Tobs. Furthermore, inFIG.6, the slip coefficient Dsand the torsional stiffness coefficient Kdrelate to the control model, and accordingly, they are expressed as slip coefficient {circumflex over ( )}Dsand torsional stiffness coefficient {circumflex over ( )}Kd. A divider25divides the estimated motor-accelerating torque component {circumflex over ( )}TmAby a time constant {circumflex over ( )}TJmequivalent to the rotational inertia of the motor to produce the motor side acceleration. A divider26divides the shaft torsional torque {circumflex over ( )}Tdby the combined rotational inertia {circumflex over ( )}TJwMof the tires and the vehicle body to produce the vehicle body side acceleration. A subtractor27calculates the difference between the dividers25and26, and an integrator28integrates the outputted difference over time to produce the relative speed {circumflex over ( )}ωdbetween the motor and the vehicle body. By multiplying the shaft torsional torque {circumflex over ( )}Tdby the slip coefficient {circumflex over ( )}Dsof a Dsblock21, the tire slip speed is calculated. A subtractor29calculates the difference between the tire slip speed and the motor/vehicle relative speed {circumflex over ( )}ωd, wherein the calculated difference is time-integrated in a Gd(s) block14and thereby converted into the torsional phase of the elastic shaft. The torsional phase is multiplied by the torsional stiffness coefficient {circumflex over ( )}Kdof the driveline to produce the shaft torsional torque {circumflex over ( )}Td. The subtractor11and the subtractor44may be integrated into a single subtractor that subtracts the estimated disturbance torque {circumflex over ( )}Tobsand the shaft torsional torque {circumflex over ( )}Tdfrom the output torque command Tm. As described above, {circumflex over ( )}TmAfrom the model GPTmA2(s) can be used without changed from the output inFIG.3, wherein there is no need to differentiate the speed on the model side. However, since this difference is a differential component of speed, the integral 1/({circumflex over ( )}TJm·s) is added after difference calculation in order to restore a speed difference. Finally, the value obtained after the integration is multiplied by the observer gain Kgto produce the estimated disturbance torque {circumflex over ( )}Tobs. Thereby,FIG.6becomes equivalent toFIG.5in terms of characteristics. In the following embodiments, vibration suppressing control is realized by using two types of signals TmA* and {circumflex over ( )}TmAindicated by broken lines inFIG.6. FIG.7shows a combination of the disturbance torque observer shown inFIG.6and the vibration suppression control shown inFIG.4(a), as an example of configuration of the second embodiment. InFIG.7, the same parts as inFIG.6andFIG.4(a)are denoted by the same reference numerals. InFIG.7, a block60is a combination of the functions of the integrator52and the gain multiplier43shown inFIG.6. InFIG.7, the model section (GPTmA2(s)) ofFIG.6is collectively shown as a block {circumflex over ( )}GPTmA2(s). If it is implemented as a model that is not approximated as the model inFIG.1, calculation takes a longer time. If it is implemented as multiple element blocks as shown inFIG.3, transformation to a sampled data system may cause errors due to discrete time. However, by transforming to a second order filter form like {circumflex over ( )}GPTmA2(s) of mathematical expression (12) and then transforming to a sampled data system, it is also possible to suppress errors due to discrete time. According to the second embodiment, by configuring the disturbance torque observer shown inFIG.6using the simplified model ofFIG.3, it is possible to estimate the disturbance torque component converted to the motor shaft. Adoption of {circumflex over ( )}GPTmA2(s) for the model section as shown inFIG.7, serves to simplify the configuration, because the intermediate component of the vibration suppression control of the first embodiment can be used. Furthermore, when the section of {circumflex over ( )}GPTmA2(s) inFIG.7is expressed by a single transfer function, the transfer function has the form of a second order filter as in mathematical expression (12). Accordingly, even with transformation into a sampled data system for implementation in a controller, it is possible to suppress errors due to discrete time. Third Embodiment FIG.8shows a vibration suppression control according to a third embodiment, which employs the vibration suppression control according to the first embodiment and the disturbance torque observer according to the second embodiment. This differs fromFIG.7in a feedback signal source, wherein the input to the bandpass filter Fcomp(s) is modified from TmA* on the speed measurement side to the estimated value {circumflex over ( )}TmAon the model side. These signals usually converge to approximately the same value, because the disturbance torque observer operates so as to equate the components TmA* and {circumflex over ( )}TmAwith each other. However, compared with the method of the first embodiment, the third embodiment is characterized in that it is possible to suppress hunting caused by backlash and disturbance components due to model errors such as when the tire coefficient varies. In patent document 1, a prefilter is added to a torque command input section for removing frequency components near resonance. In addition, since an inverse characteristic (1/Gp(s)) of an ideal model in which no disturbance is taken into account is used for vibration suppression, there is a problem that compensation performance is adversely affected by a model error when it is present. Furthermore, since this inverse characteristic has a high gain near an anti-resonant frequency, low-frequency vibration may occur conversely. In order to solve these problems, in the third embodiment, both the torque command and the measured speed are inputted to the model, and the internal state of the model is used for feedback control for vibration suppression. By ignoring the measured speed component of the two input components to the model, and taking out only the torque command, the model, and the vibration suppression feedback, it is possible to produce an effect equivalent to that of a prefilter. In other words, it acts to suppress a frequency component contained in the torque command which causes resonance. Therefore, the configuration of the third embodiment requires no prefilter inserted as in patent document 1. Furthermore, as the observer gain K g is increased, the prefilter effect becomes smaller, and instead, the effect of vibration suppression control based on speed measurement equivalent to that of the first embodiment becomes larger. By including two types of functions in this way, it is possible to produce an effect of suppressing the vibration component due to resonance, similar to patent document 1 and the first and second embodiments. Furthermore, patent document 1 and the first and second embodiments have a problem of being susceptible to nonlinearity, model errors, etc. For example, during a period of gear backlash, only the rotational inertia of the motor accelerates, resulting in a large change in the speed of the motor. It is conceivable that this causes excessive compensation of the vibration suppression control, and thereby causes hunting behavior. A model error due to variation in road surface friction (tire coefficient) is conceivable to cause a design error in the compensation filter, thereby cause a deviation in a frequency characteristic for compensation, and thereby distort a response waveform. As described above, the effect of these error components is particularly likely to appear as components in the anti-resonant band where the gain of the compensation filter is high. On the other hand, when the third embodiment is employed and the observer gain Kgis set so that the operating band of the disturbance torque observer contains the anti-resonant frequency, the low-frequency vibration component near the anti-resonant frequency can be estimated as a disturbance torque. The estimated disturbance torque component is to correct the value of compensation of the vibration suppression control, thereby suppressing low-frequency vibration components from being caused by hunting due to backlash and variation in road surface friction. Therefore, by employing the disturbance torque observer to use the motor-accelerating torque, which includes the influence of disturbance, for vibration suppression control, it is possible to produce an effect of realizing robustness that can maintain stability even when there are influences of factors such as nonlinearity and model errors. Fourth Embodiment FIG.8shows a block diagram showing a continuous data system, ignoring a delay in speed measurement. However, actual speed measurement is implemented by periodically sampling phase information obtained from a rotation sensor such as a resolver or encoder, and calculating the speed based on a phase difference and a time difference between samples. Accordingly, speed measurement has a delay due to a sample interval, a calculation time, etc. Furthermore, since the motor drive device employs an electric current control or the like to control the torque, there is also a delay in response of the electric current control. InFIG.9, these delay times are combined into a dead time component L1 and expressed as a delay1, e−L1s(delay part61). ωm_dlyafter this delay is an actually measured speed component. With respect to the third embodiment, the fourth embodiment further employs a measure for reducing the influence of the dead time.FIG.9shows an example of configuration of the fourth embodiment. InFIG.9, the same parts as inFIG.6are denoted by the same reference numerals. InFIG.9, in order to make the estimated torque of the disturbance torque observer accurate, a dead time component L2 as a delay2, e−L2s(delay part62) is inserted to the disturbance torque observer side, wherein the dead time component L2 is equal to the dead time component L1 on the speed measurement side, to ensure time matching between both components before subtraction by a subtractor51. The delay part62constitutes a delay compensating means of the present invention. The measured speed component including the delay time L1 is used to calculate a motor-accelerating torque TmA_dly*, which is outputted from a differentiator31. Since functions of electric current control and speed measurement are not implemented in the model of the disturbance torque observer, the delay processing (delay part62) with the delay time (L2) equal to the delay time L1 is inserted to the estimated motor-accelerating torque ({circumflex over ( )}TmA) in the disturbance torque observer, to calculate a quantity ({circumflex over ( )}TmA_dly), and the difference between this quantity ({circumflex over ( )}TmA_dly) and the aforementioned quantity (TmA_dly*) is calculated to produce the difference component of the motor-accelerating torque of the disturbance torque observer, which is outputted from the subtractor51. The fourth embodiment differs from patent document 2 in that the motor-accelerating torque component {circumflex over ( )}TmAof the disturbance torque observer is used as a feedback component of the vibration suppression control (inputted to the bandpass filter Fcomp(s)), and {circumflex over ( )}TmAcontains no delay. Namely, the component ({circumflex over ( )}TmA) extracted from the preceding stage of the delay2(delay part62) is used for vibration suppression control as indicated by a dashed line from the disturbance torque observer inFIG.9. InFIG.10showing another example of configuration of the fourth embodiment, it is assumed that there is more noise in speed measurement than in the case ofFIG.9. In general, in order to suppress speed disturbance due to noise, a low-pass filter LPF (high band cutoff filter) is often added to the subsequent stage of the differentiator31for filtering the result of speed measurement. This adds an LPF delay the subsequent stage of the dead time component L1, thereby further delaying the component TmA_dly*. Therefore, it is required to add an LPF to {circumflex over ( )}TmA_dlyon the model side for time matching. However, the configuration ofFIG.10is such that a low-pass filter70is inserted in the subsequent stage of the subtractor51inFIG.9that calculates the difference between TmA_dly* and {circumflex over ( )}TmA_dly. In the configuration that the single low-pass filter70is inserted in the subsequent stage of calculation of the difference between the motor-accelerating torque components with as little delay as possible and time matching, there is no need to consider time matching for a delay time due to the added low-pass filter70. This is another example of configuration of the fourth embodiment for realizing delay time matching. It is a The point is that time matching between the actual device side and the model side can be achieved. Although there are various configurations for achieving time matching between the actual vehicle side and the model side, the present disclosure includes only two examples shown inFIGS.9and10. The fourth embodiment produces the following effects. In patent document 2, in order to correct the influence of a delay time (dead time) due to speed measurement and others, an equivalent delay is inserted into an input component to the ideal model 1/Gp(s) so as to ensure time matching for a speed difference component between the model and the actual vehicle. However, the signal used for feedback control also contains this dead time delay, so that an error occurs under conditions where a torque command changes rapidly. Therefore, it is required to remove high-frequency components with a prefilter. In the system of the fourth embodiment, the difference component between the observer model and the actual vehicle is time-matched using a delay, as in patent document 2. However, the vibration suppression control component resulting from the torque command is a signal containing no delay. Accordingly, the effect of suppressing the vibration component caused by change in the torque command includes no delay in compensation. From a different point of view, the time delay in speed measurement cannot be corrected, but the command of torque to be generated by the motor can be grasped at the time of control calculation. Also, since the time constant of the vehicle body side is large, fluctuations in measured speed due to disturbance torque are relatively slow, but the motor side speed changes greatly depending on the torque command. Therefore, since the compensation component based on speed measurement is less affected by a delay, time matching by delaying is adopted for the compensation component based on speed measurement. In contrast, the compensation component based on the torque command is configured to contain no delay. Namely, by time-matching the difference in the disturbance torque observer, it is possible to accurately estimate the disturbance torque and to produce an effect of applying predictive compensation for the dead time when the torque command rapidly changes. Fifth Embodiment FIG.11shows an example of configuration according to a fifth embodiment. For input to the bandpass filter Fcomp(s), a function of switching is added between the system based on the differential component of the measured speed in the first and second embodiments and the system based on the disturbance torque observer in the third and fourth embodiments. When the torque command is fixed to zero, such as at the time of starting, it is desirable to suppress the disturbance on the load side as quickly as possible with high priority. In such a case, the first and second embodiments, which use only speed measurement, are more suitable. Furthermore, there may be special conditions in which the road surface condition changes in synchronization with the resonant frequency. In such a case, it is desirable to improve the response of the compensation signal. Therefore, as shown inFIG.11, the second embodiment and the third embodiment are combined, and a configuration is added in which both of the motor-accelerating torque components are weighted and added, thereby adding a function of switching between both signals and a function of gain adjustment. InFIG.11, the same parts as inFIG.9are denoted by the same reference numerals. A multiplier81multiplies the motor-accelerating torque component TmA_dly* on the speed measurement side (on the output side of the differentiator31) by a weighting factor KFB1. A multiplier82multiplies the motor-accelerating torque component {circumflex over ( )}TmAon the model {circumflex over ( )}GPTmA2(s) side by a weighting factor KFB2. The weighting factors KFB1and KFB2are variable. An adder83sums the outputs of the multipliers81and82and inputs the result of summation to the bandpass filter Fcomp(s). A signal selection and weight control section80is composed of the multipliers81and82and adder83. The function of the fifth embodiment in which the signal selection and weight control section80is provided is not limited toFIG.9, and may be applied to the configurations ofFIGS.7,8, and10as well. FIG.11shows an example of configuration in which a delay2(delay part62) is provided. The configuration ofFIG.11may be replaced with a configuration without the delay2. By relative increase and decrease with time, it is possible to switch slowly between the two types of signals (control systems). Furthermore, by increasing or decreasing the sum of the two types of weighting coefficients, it is possible to adjust the amount of feedback of the vibration suppression control. According to the example of configuration of the fifth embodiment, immediately after the inverter in the motor drive device is released from its gate cutoff state (in which all switching elements of the inverter are cut off), which corresponds to engine starting, the system is preferably operated to carry out the vibration suppression control based on speed measurement according to the first embodiment, thereby suppressing the disturbance quickly. After the state of the disturbance torque observer is stabilized, the switching weighting coefficients KFB1and KFB2may be gradually shifted to the system according to the third and fourth embodiments. By shifting the coefficients linearly with time, it is possible to prevent shocks due to switching of the control system. <Results of Verification of Behavior and Effects of Embodiments> Since it is an object of the present invention to improve characteristics of vibration suppression control, behavior and effects are verified by investigating transient responses such as step responses through numerical simulations. FIG.12shows a model used as an actual plant. The configuration ofFIG.12employs a detailed model system Gp(S) based on the configuration ofFIG.1, wherein a load torque caused by the gradient of a road surface is represented by TMdist(corresponding to TFinFIG.1), and changes in the road surface friction coefficient are simulated by adding a multiplier85for multiplication by an adjustment coefficient KKtafter multiplication by the tire coefficient in the Ktblock18. Gear backlash is simulated by adding a phase nonlinear function (backlash phase±θBL) part86to the torsional phase of the elastic shaft. The Gd(s) (=Kd/s) block14inFIG.1is composed of an integrator87and a Kdblock88separated from each other. This model is solely employed as the plant, wherein set values are changed for switching of presence/absence of disturbance, presence/absence of coefficient change, and presence/absence of backlash. The parameters of this plant model are set by the per-unit system, to define a virtual model having a resonant frequency of 10 Hz and an anti-resonant frequency of 1.5 Hz, for investigation of characteristics of compensation. The tire coefficient is set large as Kt=25.0 p.u. The control system is configured as shown inFIG.13. The configuration ofFIG.13is produced by modifying the configurationFIG.11partly as follows. The plant model Gp(S) receives input of the backlash phase±θBL, the adjustment coefficient KKtfor road surface change, and the disturbance force (equivalent torque) TMdist(t) applied to the vehicle body. The delay parts61,62are replaced with low-pass filters91and92(LPF1and LPF2) with time constants TLPF1and TLPF2. A low-pass filter93(LPF3) with a time constant TLPF3is provided between the input torque command Tref(t) and the subtractor32. Furthermore, the signal selection and weight control section80is replaced with a SelFB switch94for switching between {circumflex over ( )}TmAand TmA_dlyfor input to the bandpass filter Fcomp(s). A multiplier95is provided on the output side of the bandpass filter Fcomp(s) for multiplying by a weighting coefficient (gain correction value) KFB. Basically, the first to fourth embodiments can be simulated by this configuration. Feedback compensation can be invalidated by setting KFBto zero, wherein KFBis to be multiplied by the vibration suppression control component. Switching between the configuration of the first and second embodiments and the configuration of the third and fourth embodiments can be performed by switching the SelFB switch94. The time matching of the disturbance torque observer is simulated by the first order delay filters LPF1(91) and LPF2(92). The LPF characteristics can be equivalently disabled by setting the time constants TLPF1and TLPF2to 0 s. Elements inFIGS.12and13are as follows.Tref(t): an input torque command,Tmdist(t): a disturbance force applied to vehicle body (equivalent torque),Gp(S): a plant model simulating a vehicle (FIG.12),±θBL: a gear backlash phase of an actual model (when set to zero, it means no backlash),KKt: an adjustment coefficient for variation in the road surface of the actual model (1.0: the friction of the actual road surface matches the model; <1: when the road surface is in a slip state),{circumflex over ( )}GPTmA2(S): a disturbance torque observer model (mathematical expression (12)),ΔTJm: a time constant equivalent to the rotational inertia of the model,Kg: a feedback gain of the disturbance torque observer,Fcomp(S): a filter section for vibration suppression control (mathematical expression (13), ζA=1),KFB: a gain correction for a feedback component of vibration suppression control (when set to zero, it means no compensation),LPF1: a low-pass filter simulating a speed measurement delay (TLPF1: a time constant; TLPF1=0 means no delay),LPF2: a low-pass filter inside the observer for matching with the speed measurement delay (TLPF2: a time constant; TLPF2=0 means no delay),{circumflex over ( )}Tobs: an estimated torque by the disturbance torque observer,TFcomp: a compensation torque component by the vibration suppression control,TmA_dly: a differential component of a measured motor speed on the actual plant side (with a delay), and{circumflex over ( )}TmA, {circumflex over ( )}TmA_dly: a differential component of a measured motor speed on the model side (with no delay; with a delay). In order to investigate transient response characteristics, an input pattern of input torque command Tref(t) and load disturbance torque TMdist(t) is set as shown inFIG.14. This is an example of characteristics for evaluating: characteristics of response of the torque command; the vibration component when the reaction force applied to the vehicle body is changed transiently; and effects of backlash when the torque is returned to zero.t=1.0 s to 2.0 s: acceleration with 100% torque,t=2.0 s to 4.0 s: coasting with 0% torque,t=4.0 s to 5.0 s: deceleration by reaction force of 50% torque (uphill gradient), andt=5.0 s˜: reaction force of 0% torque; coasting. However, the actual torque command does not have such a steeply changing step waveform. Accordingly, the low-pass filter93(LPF3) (10 ms) is added to soften the rise a little. As described below, the output of this filter93is indicated by a waveform labeled as “TrefLp”. In order to simulate the characteristics of the first to fourth embodiments, set values are combined as shown in Table 1 below. TABLE 1±θBLk_KtTLPF3SelFBKFBTLPF1TLPF2to be studiedFIG. 1601.05 ms—0——no vibration suppressioncontrolFIG. 1701.05 msTmAdet1.000vibration suppressioncontrol (speedmeasurement anddifferentiation system,without backlash, withouttire slip)FIG. 18±0.0011.05 msTmAdet1.000vibration suppressioncontrol (speedmeasurement anddifferentiation system, withbacklash, without tire slip)FIG. 19±0.0010.35 msTmAdet1.000vibration suppressioncontrol (speedmeasurement anddifferentiation system, withbacklash, with tire slip)FIG. 2001.05 msTmAobs1.000vibration suppressioncontrol (torque observersystem, without backlash,without tire slip)FIG. 21±0.0011.05 msTmAobs1.000vibration suppressioncontrol (torque observersystem, with backlash,without tire slip)FIG. 22±0.0010.35 msTmAobs1.000vibration suppressioncontrol (torque observersystem, with backlash, withtire slip)FIG. 23±0.0011.00 msTmAobs1.05 ms0vibration suppressioncontrol (torque observersystem, with backlash,without tire slip, with delayin speed measurement,without time compensation)FIG. 24±0.0011.00 msTmAobs1.05 ms5 msvibration suppressioncontrol (torque observersystem, with backlash, withtire slip, with delay inspeed measurement, withtime compensation) <Behavior and Effects of Vibration Suppression Control Using Model Approximated to Two-Inertia System and Speed Measurement Information (First Embodiment)> FIG.15demonstrates validity of the model approximation employed in the first embodiment, where the characteristics of GTdWw(s) in mathematical expression (2) and the characteristics of GTdEw2(s) in mathematical expression (7) are compared in Bode diagrams. As can be seen fromFIG.15(a), a difference in gain occurs at 50 Hz or more. Namely, the difference occurs only in frequency components higher than the resonant frequency of 10 Hz. Furthermore, inFIG.15(b), as Gp(S) in mathematical expression (3) and Gp2(S) in mathematical expressions (10) and (11), each of which is a transfer function from the motor input torque to the motor speed, are compared, it can be seen that the characteristics of the two almost overlap with each other, and the error of the approximate model is small, and this approximate model can also be used for control. FIG.16shows characteristics when the vibration suppression control is disabled (KFB=0) for comparison with the first embodiment. InFIG.16, the motor rotational speed corn, the relative torsional speed ωdand torsional torque Tdof the elastic shaft, etc., each show a large vibration around 10 Hz near the resonant frequency, after a change in the torque command, wherein damping is slow. On the other hand,FIG.17shows a response when the vibration suppression control according to the first embodiment and the design method using the approximate model are employed. As compared withFIG.16, vibration does not occur even when the torque command changes rapidly. Immediately after the start of acceleration at time instant 1 s, the motor speed ωmincreases for a short period of time in order to generate a torsional phase of the elastic shaft corresponding to the input torque. However, when the torsional phase, namely, the transmitted torque Td, has reached a target value, then the motor speed W m returns to a normal line, and thereafter increases in conformance with the tire speed ωw. From this behavior, it can be confirmed that the vibration due to resonance is suppressed and the acceleration is stabilized. This is also true when the torque command returns to zero at t=2 s. However, when a disturbance force is applied to the vehicle body at t=4 s, the compensation torque component TFcomposcillates. Vibration occurs in the motor speed corn as well, although the amplitude of the vibration is small. The speed fluctuation is thus amplified by the vibration suppression control. The vibration component caused by this disturbance is a frequency component considerably lower in frequency than that inFIG.16and near the anti-resonant frequency of 1.5 Hz. The following two effects can be confirmed with reference to such change characteristics of the torque command and the disturbance torque. First, even when the vibration suppression control is configured by approximatingFIG.1as shown inFIG.2like a two-inertia system, it is possible to produce an adequate effect of vibration suppression with respect to changes in the torque command. Second, it has a disadvantage of generating low-frequency vibrations near the anti-resonant frequency in response to disturbance torque. This means that it is required to modify the method for designing the compensation filter of mathematical expression (13) or add a disturbance suppression function. Therefore, the latter disturbance suppression function is proposed. <Behavior and Effects of Load Disturbance Torque Observer (Second Embodiment)> InFIGS.16and17shown in the previous section, only the estimation function of the disturbance torque observer in the configuration ofFIG.6using the approximate model inFIG.3is enabled (Kg≠0). With reference to behavior of estimation of the estimated disturbance torque {circumflex over ( )}Tobsindicated by dashed-dotted lines inFIGS.16and17, it is confirmed that the disturbance torque can be stably estimated, where a small component occurs at t=1 s and at t=2 s but vanishes soon, although there is a response delay when the disturbance torque is started and released at t=4 s and at t=5 s. As described above, the vibration caused by disturbance torque, which is a problem of vibration suppression control, is affected by the inertia of the vehicle to be a low frequency component. In order to produce a response enough to compensate for the low frequency component, K g is set. Therefore, it can be seen that even with the configuration of the second embodiment, the disturbance torque observer can perform a normal estimating action. <Behavior and Effects of Vibration Suppression by Disturbance Torque Observer (Third Embodiment)> Before describing effects of the third embodiment, the following describes examples of waveforms for explaining two types of problems to be solved. First, the following describes effects of backlash. When the gear backlash component (≠θBL≠0) is set in the model of the actual plant under the conditions ofFIG.17in which the first embodiment is employed, the characteristics vary as shown inFIG.18. When the torque command changes, the vibration can be suppressed in the same manner as inFIG.17. However, after the disturbance torque occurs at t=4 s, an abnormal vibration, in which hunting continues, occurs. This is because when the torque command is equal to zero, a backlash, namely, a special state, in which tooth faces of the gears are out of contact with each other, occurs. This causes a problem of continuous low-frequency vibration. Next, the following describes the effect of model errors. When the friction of the road surface is further reduced and only the tire coefficient is changed to 0.3 times (KKt=0.3) with respect to the condition ofFIG.18, the characteristics vary as shown inFIG.19. During the period from t=1 s to t=2 s, it is not in a backlash region, because the torque command is applied, but there is a problem of low frequency vibration due to model errors. Furthermore, when the torque command returns to zero at and after t=2 s, hunting occurs due to backlash with this disturbance as a vibration source. In summary, the systems of the first and second embodiments have problems of two types of low-frequency vibration phenomena, namely, the hunting phenomenon due to backlash, and the influence of model errors. These problems are addressed by the third embodiment. Also inFIGS.18and19, only the estimation function of the disturbance torque observer is enabled. Although not yet used for control, the estimated disturbance torque {circumflex over ( )}Tobscontains not only the disturbance torque but also the vibration torque component described above. In view of the characteristics of estimation, it is expected that the vibration suppression control using the disturbance torque observer is effective. The following describes an example of behavior and effects of the third embodiment as compared with characteristics showing the above problems. First,FIG.20shows characteristics when the vibration suppression control system is switched from the first embodiment to the third embodiment under the same ideal plant conditions as inFIG.17. With respect to changes in the torque command from t=1 s to t=2 s, similar stable characteristics are maintained. Furthermore, the problematic low-frequency vibration near anti-resonance from t=4 s to t=6 s is also suppressed. Therefore, it can be confirmed that the vibration suppression control of the present invention does not cause abnormal low-frequency vibrations. Next, under the conditions in which only backlash is set as inFIG.18, stable characteristics are obtained with the system of the present invention as shown inFIG.21. With respect to changes in the torque command from t=1 s to t=2 s, stable characteristics is maintained. Furthermore, hunting due to backlash that occurs after the input of the disturbance torque after t=4 s is suppressed. Finally, under the condition where both backlash and model errors exist as inFIG.19, characteristics shown inFIG.22are obtained with the system of the present invention. The low-frequency vibration while the torque command is inputted from t=1 s to t=2 s, which is the issue in the configuration ofFIG.19, is suppressed significantly. No vibration occurs due to backlash after t=2 s. With reference to the estimated disturbance torque {circumflex over ( )}Tobsduring this period, it can be inferred that the disturbance estimation function contributes to vibration suppression, because the disturbance estimation works in contrast to the situation where there is no model error. After t=4 s, stability is maintained as inFIGS.20and21. <Behavior and Effects of Vibration Suppression Control where Time Matching with Speed Measurement is Added to Disturbance Torque Observer (Fifth Embodiment)> FIG.23shows an example of characteristics when a delay time in electric current control and speed measurement is simulated as LPF1(TLPF1) under the same condition in which only backlash is set as inFIG.18. The vibration suppression control remains the same as in the third embodiment, and LPF2is set to no delay (TLPF2=0) because the time matching measure is not yet adopted on the observer side. In order to clarify the characteristics of the problem, the time constant of LPF3inserted in the torque command input section is also changed to zero (TLPF3=10 ms→0 ms), and the torque command is rapidly changed stepwise. Since the effect of improving the characteristics appears when the torque command changes, the waveforms are drawn as enlarged in the time axis direction only during the period of t=0.5 s to 2.5 s. Since there is only a low frequency component at the time of disturbance torque, there is no difference in stability, which is omitted. InFIG.23, there is a problem that an error occurs in the estimated torque of the observer due to the influence of the delay time in speed measurement. After rapid changes in the command at t=1 s and t=2 s, distortion and residual vibration of about one cycle appear in the pulse-like waveform of the estimated disturbance torque {circumflex over ( )}Tobs. Accordingly, the waveform of vibration suppression compensation TFcompafter t=2 s does not immediately return to zero, and is distorted stepwise in a converging waveform due to an estimation error. As a result, this distortion is also superimposed on the waveform of the torque command Tmthat is outputted to the motor drive section. FIG.24shows characteristics when the compensation for the delay in speed measurement as shown inFIG.9is adopted toFIG.23. Specifically, the delay time of LPF2on the model side is set equal to the delay time of LPF1on the speed measurement side (TLPF2=TLPF1=5 ms). With this time delay matching, the vibration components in the waveforms of the estimated disturbance torque {circumflex over ( )}Tobsand the vibration suppression compensation TFcompare suppressed, so that the output torque command Tmhas a smooth waveform containing no overshoot, no distortion, and no vibration. Therefore, it can be confirmed that the characteristics of the vibration suppression control can be improved by matching the motor-accelerating torque of the observer and the differential component of the measured speed in terms of time. Problems in First to Fifth Embodiments (Method for Configuration of Observer, Combination with Speed Measurement System, and Time Matching Measure) The basic principles described in the first to fifth embodiments are shown with models and transfer functions based on a continuous data system. However, when it is put to practical use, it is required to be implemented to form a digital control. This causes some problems.To implement the system as a program for a digital arithmetic unit, etc., it is required to transform the system to a sampled data system suitable for digital control. When time is approximated to time values that are discrete by a sampling interval, the discretization causes errors.For speed measurement, a filter is used to suppress the effects of phase time difference and measurement noise. Since there is a time delay component due to the filter, an error occurs in the observer estimation due to time mismatching as compared with the speed on the model side with no delay. In particular, during transient response, the error becomes large, so that time matching measures are required. Although details are described below, examples of resonance characteristics are first shown inFIGS.39,40, and41, to facilitate understanding of the problem. These are examples of resonance and its suppression effect when the torque command is changed in a trapezoidal shape.FIG.39(A) shows characteristics of acceleration/deceleration when no vibration suppression control is employed.FIG.39(B) is a partial view ofFIG.39(A) enlarged in time. InFIG.39(A), (a) shows the torque command and the torsional torque Tdof the driveline shaft, (b) shows the shaft torsional speed, and (c) shows the motor-accelerating torque component TmA. As compared with the data shown in the first to fifth embodiments, the torque command Tref_LPFis changed to a trapezoidal shape, but breakpoints of the trapezoid still behave as a vibration source to cause overshoots and residual vibrations as resonance phenomena. It can be seen that the steeper the change in the break point, the greater the amplitude of the vibration, which does not attenuate even during acceleration. In the sixth and following embodiments, this is stabilized as shown inFIG.40(sixth embodiment) andFIG.41(seventh embodiment). When it can be stably controlled, components hidden in the vibration become clear. The waveform of ΔωmWinFIG.40(b)shows a speed difference between both ends of the driveline mechanism (speed difference between the motor shaft and the tire axle), and corresponds to a time-differential component of the shaft torsional phase (shaft torsional speed), because backlash is not yet considered. When the transmitted torque of the elastic shaft is increased or decreased at a constant gradient, it is required to increase or decrease the shaft torsional phase, so that it can be seen that the amplitude of the shaft torsional speed is constant. (Countermeasures Against Backlash Elements in Driveline) Reduction gears are used in a driveline mechanism of a vehicle. Gears have play called backlash. This occurs in the vicinity of zero torque where the polarity of the motor torque switches between positive and negative, wherein the gear teeth are not meshed, so that the transmitted force, namely, the reaction force to the motor shaft, is also equal to zero. Therefore, if the rotational inertia of the motor is small, the motor speed rapidly increases even if the motor torque is not so large. At an end of a backlash period, the teeth of the gears collide with each other, causing an abnormal vibration and sound called “rattling shock”. Against this phenomenon, a countermeasure has been adopted, in which, when the motor torque command crosses zero, the rate of change of the motor torque command is reduced to lengthen the period of time during which the torque command is small, thereby allowing the teeth to come into contact with each other softly. InFIG.41(seventh embodiment), backlash is ignored in both the control and the actual vehicle. In contrast,FIG.42is presented for investigating the influence of addition of backlash only in the actual plant side without modification of the control system. InFIG.42, (a) shows the shaft torsional torque Tdthat shows a distortion to stick to zero in the vicinity of the zero-crossing point, due to backlash. InFIG.42, (b) shows the shaft torsional speed on which a pulse-like waveform, which does not appear inFIG.41, is superimposed. For clearly indicating where in the pulse the backlash period is, a waveform indicated by a broken line is added as a supplement. Only during the backlash period, the waveform of the shaft torsional speed indicated by a solid line is traced, and except for the backlash period, the value is held. During the period when the solid line and the broken line overlap with each other, backlash is occurring. With reference to the enlarged view ofFIG.42(B), the shaft torsional speed of (b) has a pulse-like waveform that rapidly increases immediately after the start of backlash and rapidly decreases after the end of backlash. Since there is no reaction force from the elastic shaft, the motor solely rapidly accelerates. When the teeth collide, the accelerated inertial energy is converted into elastic energy of torsion of the shaft, resulting in deceleration. As the amplitude of this pulse waveform increases, the relative speed between teeth at the end of the backlash increases, and the rattling shock also increases. Patent document 3 discloses a method of backlash control, which is characterized by estimating a period of occurrence of backlash by using a reference model. According to patent document 3, by increasing the torque command outside of the backlash period and suppressing the torque command to a low level only during the backlash period, it suppresses degradation of the response characteristics as a whole, and reduces the rattling shock. In the time-enlarged view ofFIG.42(B), zero-crossing of the torque command Tref_LPFoccurs around 1.5 s and around 2.1 s, wherein the enlarged range is selected so as to include two types, fast change and slow change. Due to fast and slow changes, a difference occurs in behavior of Tm, which is the control output, in the vicinity of zero-crossing. When change of the torque command is gradual, such as around 1.5 s, the control output Tmis throttled to around zero during the backlash, namely, during the period when Tdis equal to zero, so as to produce an effect of backlash control that suppresses rapid changes in the shaft torsional speed shown in the second row. However, when the torque command changes rapidly, as at 2.1 s in the latter half, the control output Tmis not sufficiently throttled, and the shaft torsional speed becomes large, namely, the motor acceleration becomes rapid, since the disturbance torque observer has a limit of response. In view of the foregoing, in order to reduce the rattling shock at the time of rapid torque change, which cannot be sufficiently suppressed only by adoption of the sixth and seventh embodiments, the eighth and ninth embodiments are presented to have an extended function of reducing a wide range of rattling shocks. (Limitation of Sampled Data System) The configurations of the first to fifth embodiments are each shown in the form of a continuous data system model. However, in recent years, a computer processor called a CPU (Central Processing Unit) is often used as a controller, where a control algorithm is implemented as a digital control handling discrete-time digital values. Digital control has the following limitations. (a) Sampled Data System (Discrete Time) Even a continuous input signal is converted to discrete time sample values and then handled. Internal state quantities are also updated with reference to sample timings. Execution of a program takes time, which causes a delay in an output signal by a maximum of one sampling. (b) Restrictions on Number of Significant Digits A quantity on a signal is also treated as an encoded digital value, which causes problems about the number of significant digits and resolution. A dynamic range also varies depending on an encoding method such as fixed point encoding method or floating point encoding method. (c) Discrete Calculation Error With a digital control based on a sampled data system, in order to obtain a result close to that of a continuous data system, there is a method of applying iterative operation such as the Runge-Kutta method to approximate an integral. Furthermore, for a configuration that has many integral elements and a feedback loop, there is also a method of transforming into a multivariable state equation or the like and solving a system of simultaneous differential equations. On the other hand, there is also a simple method for implementation using the backward difference method or the like although some errors occur. In the sixth to ninth embodiments, it is desired to realize a real-time control with a built-in CPU. Therefore, it is required to be implemented to have a simple algorithm and a short calculation time as much as possible. Accordingly, an integral is approximated to a simple backward difference, and a feedback loop is approximated by insertion of a sample delay, and convergence operation is thereby omitted. Therefore, there is a concern that a calculation error may increase with respect to a continuous data system. In the following embodiments, the foregoing is referred to as a method of transformation to sampled data system, a calculation error in sampled data system, etc. Sixth Embodiment The following embodiments also employ the models, variables, and transfer functions, which are defined in the first to fifth embodiments.FIG.25is a block diagram showing a basic vehicle model composed of three kinds of inertial bodies (motor, tires, and vehicle body) and spring elements of a torque transmission mechanism (gears, and an elastic shaft). FIG.25differs fromFIG.1in that the subtractor10subtracts the disturbance torque component (equivalent component obtained by conversion to motor shaft) Tdistfrom the motor torque (output torque command) Tmto output a quantity that is inputted to the subtractor11. The other configuration is the same as inFIG.1. Variables and constants inFIG.25are the same as those described withFIG.1. The model Gp(s) inFIG.25is approximated to a model shown inFIG.26in which a transfer function has a reduced order, as in the first embodiment (mathematical expressions (1) to (12) are adopted). InFIG.26, the same parts as inFIG.25andFIG.2are denoted by the same reference numerals. FIG.29shows a disturbance torque observer constructed using the model ofFIG.26, as described below. The disturbance torque observer estimates the disturbance torque component TdistofFIG.25, wherein {circumflex over ( )}Tobsand {circumflex over ( )}Tdare subtracted from AT m at the same point. Therefore, the estimated disturbance torque {circumflex over ( )}Tobsmay be regarded as a component for correcting the shaft torsional torque component {circumflex over ( )}Tdof the model. In the configuration ofFIG.29, the estimated motor-accelerating torque is calculated as {circumflex over ( )}TmA={circumflex over ( )}Tm−({circumflex over ( )}Tobs+{circumflex over ( )}Td). The relationship between the estimated motor-accelerating torque {circumflex over ( )}TmAand the estimated motor speed {circumflex over ( )}ωmis expressed by differentiation and integration as in mathematical expression (16). ∧TmA=ddt(∧ωm),∧ωm=∫(∧TmA)·dt(16) In the following embodiments, examples of configuration are proposed for implementing the foregoing with a sampled data system. FIG.27shows an overall configuration of a continuous data system that is a base of the sixth embodiment. First, the following describes variables and element blocks inFIG.27. [Description of Variables]Tref: an input torque command, which is a value of the shaft output torque of the motor requested by an upper command device,ΔTcomp: a compensation torque component, which is an output of the vibration suppression control (outputted from a vibration suppression control filter150),Tm: an output torque command of the control device, which is also an input to a disturbance torque observer120. This torque is generated by the motor drive device in the subsequent stage.ωm: a rotational speed of the actual motor,θm, t: a rotational phase and time of the actual motor, which are latched by an RD converter130at time instants of sampling, wherein the speed is calculated based on a time difference component by a speed calculation part140in the subsequent stage.ωm_det: a measured motor rotational speed calculated based on the measured values (θm_det, t_det) of (θm, t) by the speed calculation part140. The sum of (1) a dead time from output of Tmfrom the control device to torque generation in the actual vehicle, and (2) a dead time from actual rotational speed ωmto measured rotational speed ωm_detis described as L1 (delay block1is e−L1s).{circumflex over ( )}Tobs: a disturbance torque component estimated by the disturbance torque observer120(estimated disturbance torque), which is an estimate of TdistinFIG.25, wherein disturbance forces applied to the vehicle body, such as TF, are converted and estimated herein,{circumflex over ( )}ω: an estimated motor speed outputted from a reference model (121) in the disturbance torque observer,{circumflex over ( )}TmA: an estimated motor-accelerating torque outputted from the reference model (121) in the disturbance torque observer,{circumflex over ( )}ωm_dly: a signal component produced by delaying {circumflex over ( )}ωm by a delay2of e−L2sin a delay part62, for matching with a delay1of e−L1sin the speed calculation part140, andΔωm: a speed deviation component produced by a subtractor51as a deviation between the estimated motor speed ({circumflex over ( )}ωm_dly) of the model and the measured motor speed (ωm_det), wherein the speed deviation component is multiplied by an observer gain Kgby a gain multiplier43to produce the estimated torque {circumflex over ( )}Tobs. [Description of Blocks](a) Prefilter part (PRE-LPF)100: a filter that removes high frequency components from an external torque command Tref, and contains a torque limiter that defines upper and lower limits. The output Tref_LPFis used as an input to vibration suppression control.(b) Plant (actual vehicle)110: a plant of an actual vehicle corresponding to Gp(S) inFIG.25and mathematical expression (3). Drive devices such as inverters are ignored. The output torque command Tmis inputted, and then the motor rotational speed ωmis outputted, wherein the motor rotational speed ωmis time-integrated by an integrator28to determine a motor rotational phase θm.(c) Disturbance torque observer120(Tdist_OBS): a part of vibration suppression control, which is composed of a speed deviation calculation section (delay part62, subtractor51), which takes account of a vehicle model part (121) and time matching, and a feedback section based on the observer gain Kg.(d) Vehicle model121: a model part in the disturbance torque observer120, which simulates the vehicle corresponding toFIG.26. The torque command Tmis inputted, and the motor rotational speed {circumflex over ( )}ωmcorresponding to {circumflex over ( )}Gp(S) in mathematical expression (10) is outputted, and the estimated motor-accelerating torque {circumflex over ( )}TmAcorresponding to GTdWw2(s) in mathematical expression (12) is outputted.(e) RD converter130: a measurement circuit for speed measurement, which outputs a rotational phase θm_detusing a resolver and a resolver/digital converter (RD converter). In speed measurement, both the phase θm_detand time t_detare sampled simultaneously.(f) Speed calculation part140: a part that calculates a measured motor speed based on a signal of the RD converter.(g) Vibration suppression control filter150: a filter Fcomp(s) that calculates a vibration suppression control component ΔTcompfor suppressing resonance due to the elastic shaft, which corresponds to the bandpass filter of mathematical expression (13). Next, the following describes the configuration ofFIG.27. First, the prefilter part100removes a high frequency band from the input torque command Tref, and apply limitation with the upper and lower limits, to calculate Tref_LPF. The compensation torque ΔTcomp, which is produced by the vibration suppression control, is subtracted from Tref_LPF, to produce the control output torque Tm. Tmis also an input to the disturbance torque observer120in the vibration suppression control system. The motor speed is calculated based on the measured values (θm_det, t_det) of the rotational phase θmand the time t by the speed calculation part140. For example, the measured speed ωm_detis determined by dividing a phase difference from a past sample value by a time difference. Although the detailed configuration of the disturbance torque observer120(Tdist_OBS) is described below, the output of the disturbance torque observer120is the estimated component {circumflex over ( )}TmAof the motor-accelerating torque that is used for vibration suppression control. The estimated component {circumflex over ( )}TmAis caused to pass through the vibration suppression control filter150(Fcomp(s)) to produce a compensation torque ΔTcomp, which is subtracted from Tref_LPFto produce Tm. FIG.28shows a control section that is produced by transforming the control section shown inFIG.27into a sampled data system.FIG.28shows the whole of the control section, wherein only the prefilter part100is shown in detail. The prefilter part100includes a low-pass filter KLPFthat suppresses a high frequency band of the input torque command Tref, and is also provided with a torque limiter101(TLIM0) (first torque limiter) that defines a maximum value.FIG.28shows a simple example of configuration that is produced by transformation by the backward difference method, wherein a delay operator of a delay part103is represented by “z−1”, and a sample period thereof is represented by Tc. The output of torque limiter101(Tref_LPF) is delayed by a delayer103, and the output of delayer103is subtracted from the input torque command Trefby a subtractor104, and the output of subtractor104is caused to pass through the low-pass filter KLPF, and is thereafter added to the output of the delayer103by an adder105. The output of addition of the adder105is inputted to the torque limiter101. InFIG.28, the output Tmof the vibration suppression control is produced by subtracting the compensation torque ΔTcomp, which is the output of the vibration suppression control filter150, from the output Tref_LPFof the prefilter part100. The output Tmis also an input torque command to the disturbance torque observer120. It is required to insert a delay z−1into the feedback section, so that a delayer161is inserted in the subsequent stage of the vibration suppression control filter150. As the number of delayers increases, errors increase. Therefore, the delayer161is inserted in this position in consideration of reduction of the number of delayers. FIG.29shows an example of configuration of the disturbance torque observer120.FIG.29shows a base continuous data system model, which employs the reduced order model ofFIG.26. The model Gp2(s) inFIG.29has the same configuration as the disturbance torque observer model {circumflex over ( )}GPTmA2(S) according to the second embodiment shown inFIG.6, where the delay part62, subtractor51, gain multiplier43, and subtractor44are also shown. FIG.30shows a sampled data system produced by transformation fromFIG.29, showing an example of configuration in which time integration is replaced with integration by backward difference. FIG.30differs fromFIG.29in that: the output ({circumflex over ( )}TmA) of the subtractor11is caused to pass through an integral coefficient multiplier Tc/TJmand an integrating part122, which composed of a delayer having a delay operator z−1, and an adder, to produce the estimated motor rotational speed {circumflex over ( )}ωm; the estimated shaft torsional speed {circumflex over ( )}ωdis caused to pass through an integration coefficient multiplier {circumflex over ( )}Kd·Tc, an integrating part123, which is composed of a delayer having a delay operator z−1, and an adder, and a delayer124having a delay operator z−1, to produce an estimated shaft torsional torque {circumflex over ( )}Td; the estimated shaft torsional torque {circumflex over ( )}Tdis caused to pass through the integral coefficient multiplier Tc/TJm, and an integrating part125, which is composed of a delayer having a delay operator z−1, and an adder, to produce {circumflex over ( )}ωWM; and a delayer126having a delay operator z−1is inserted in the subsequent stage of the gain multiplier43. By subtracting the estimated value of the disturbance torque {circumflex over ( )}Tobsfrom the torque command inputted to the model, the speed deviation converges to decrease so that the disturbance torque and the estimated value match each other. The delay part62(e−L2sblock) inFIG.30is inserted for time matching, as described below in detail with reference toFIG.32. FIG.31shows another form ofFIG.30. The motor model part of {circumflex over ( )}DGp2inFIG.30may be implemented by using the second order transfer function of mathematical expression (12). Therefore, coefficients of a second order IIR filter127(Infinite Impulse Response Filter) are designed directly from mathematical expression (12) and implemented as {circumflex over ( )}DGpTmA2_IIR2 ({circumflex over ( )}Tm-{circumflex over ( )}TmAtransformation block of the present invention). {circumflex over ( )}ωm, which is used for calculating the estimated disturbance torque {circumflex over ( )}Tobs, is produced by time-integrating the output component {circumflex over ( )}TmAof the second order IIR filter127by an integral coefficient multiplier Tc/TJmand an integrating part122. Referring back toFIG.28, the torque command Trefis processed by the prefilter part100that is a first order LPF based on backward difference, to produce Tref_LPFwhose rapid changes are suppressed. The prefilter part100is not required to perform a function to remove the resonant frequency component as a notch filter, and but removes high frequency components that cannot be compensated for by the vibration suppression control at the subsequent stage. The disturbance torque observer120receives input of the output torque command component Tm, which is produced by subtracting the compensation torque component ΔTcompof the vibration suppression control from the output Tref_LPFof the prefilter part100, and the measured speed component ωm_det, which is calculated by the speed calculation part140, and outputs the estimated motor-accelerating torque component {circumflex over ( )}TmAthat is calculated by the vehicle model. The vibration suppression control filter150calculates the vibration suppression compensation torque component ΔTcomp, wherein the vibration suppression compensation torque component ΔTcompis subtracted from Tref_LPFto produce the torque command Tmas a quantity that is produced by application of the vibration suppression control compensation, wherein the torque command Tmis used as an output of the controller. In the drive system, this torque command Tmis fed to the drive device at the subsequent stage, to cause the actual motor to generate a motor torque corresponding to the torque command Tm. The vibration suppression control thus configured using the disturbance torque observer120is expected to produce three types of effects in accordance with the input signal, as already described in the third embodiment. The following discusses the transfer function from the torque command Tref_LPFto the output Tmwhere the speed measurement side input to the disturbance torque observer120is fixed to zero and thereby invalidated. As the feedback section including the disturbance torque observer120and the vibration suppression control filter150is transformed into an integrated transfer function, this transfer function is equivalent to a kind of band elimination filter. Namely, this produces an effect of outputting a torque command produced by removing a torque component in the resonant band contained in the torque command Tref_LPF. On the other hand, the following discusses the effect of vibration suppression based on speed measurement where the torque command side input to the disturbance torque observer120is fixed at zero and thereby invalidated. Then, as a second effect, an effect of vibration suppression control based on speed differential feedback is produced, which is known as an effect of general PID control or the like. With reference to the example ofFIG.31, the disturbance torque observer120operates so that the speed deviation becomes zero, namely, the model speed and the measured speed become equal to each other. Since {circumflex over ( )}TmAis the input signal to the integrator that generates the model speed {circumflex over ( )}ωm, {circumflex over ( )}TmAcorresponds to the differential of {circumflex over ( )}ωm, and may be regarded as an approximation of the differential component of measured speed under convergence behavior by the observer. Since {circumflex over ( )}TmAis used for vibration suppression control via the vibration suppression control filter150, this produces an effect similarly to a differential feedback type vibration suppression control based on speed measurement. This serves to suppress the resonant component caused by the disturbance forces applied to the vehicle body and driveline mechanism. Furthermore, the disturbance torque observer is configured to feed back the deviation component between the information from the reference model and the information from the speed measurement to the model input, so that even if there is a difference in parameters between the reference model and the actual vehicle, this produces an effect of suppressing an error component resulting from the difference. This effect is a third effect, wherein robustness is ensured to suppress deterioration of performance of the vibration suppression control even if errors or fluctuations occur in parameters. FIG.32shows a configuration of the speed measurement section (RD converter130and speed calculation part140) and the section that calculates the deviation Δωmbetween the estimated speed {circumflex over ( )}ωmand the detected speed ωm_det, which is used in the disturbance torque observer. The delay block e−L2s(delay part62) corresponding to the delay time L2 is inserted on the estimated speed Δωmside for time matching. Although omitted inFIGS.27and28, many delay components exist in this control system. A calculation time is required until a control output is produced in response to an interrupt signal from the CPU. There is also a delay in electric current control and others in the drive device at the subsequent stage. Furthermore, in a configuration in which the speed is measured using a position sensor, it is required to calculate the speed using the phase difference in a certain amount of time difference, which causes a delay in measurement. If an LPF is inserted for noise removal, this adds a further delay component. InFIG.27, the delay time due to speed measurement is represented by Ln, and the sum of the delay times including others is represented by L1. On the other hand, since the model section of the disturbance torque observer calculates the model using sample values of the torque command, the estimated speed of the model can be regarded as a component at a sample time instant. Therefore, if the deviation is calculated without correction, the deviation is produced as a difference between the components shifted in time by the time L1 from each other. This time mismatch causes an error during transient response. In view of the foregoing, in calculation of the speed deviation of the disturbance torque observer as shown inFIG.32, for matching with the delay time L1, the delay block e−L2scorresponding to the time L2 equal to the delay time L1 is inserted to the model side. Regarding the correction for delay times, a delay component due to electric current control from an interrupt time instant to a phase measurement time instant, etc., and a delay component in the speed measurement calculation section are shown separately. The calculation time and the response time of the electric current control are relatively short and vary little, but the speed measurement delay varies depending on the calculation method, LPF, etc. This is because these are discussed separately. The following proposes a time matching method adapted to the speed measurement method. InFIG.32(a), the speed measurement section (RD converter130) samples the rotational phase θmand its corresponding time t by a measurement circuit, and reads values by the CPU as the phase θm_detand time t_det. Then, a delayer141having a delay operator z−ndelays the phase θm_det, and a subtractor142subtracts a value of θm_detn-samplings before, which is outputted from the delayer141, from the value of θm_detat the current time. Also, a delayer143having a delay operator z−ndelays t_det, and a subtractor144subtracts a value of t_detn-samplings before, which is outputted from the delayer143, from the value of t_detat the current time. Then, a calculator145divides a phase difference, which outputted from the subtractor142, by a time difference, which is outputted from the subtractor144, to calculate the measured speed ωm_det. Here, the z−nblock corresponds to n-cascaded z−1blocks. With the z−nblock, the difference between the value at the current time and the value n-samplings before is calculated. FIG.32shows an example of configuration of the deviation calculation section (subtractor51) for calculation of a deviation between the model and the speed measurement calculation section (140), and the time matching section e−L2s(delay part62). The delay time due to the current control of the motor drive device is assumed to be substantially constant, and is compensated for by α-time delay calculations by a delayer65(z−α). In the subsequent stage, correction is made for the delay time due to speed measurement. There are various methods for speed measurement. When the phase difference at n-sample interval is used as shown inFIG.32(a), a delay time equivalent to that in speed measurement can be generated by inserting (n+1) samples moving average calculation. The reason why the multiple (n-times) sampling interval is set for speed measurement is that the measured phase data contains measurement errors and noise, and the accuracy of speed measurement is to be improved by reducing the noise component ratio (measurement error) by increasing the phase difference and time difference for difference calculation. However, increasing the number n raises a problem of an increase in time delay (expressed as e−Lns) in exchange for accuracy. Therefore, a delay corresponding to Ln is also inserted for the estimated speed on the disturbance torque observer side for time matching. FIG.33(b)illustrates an equivalent delay time by the moving average calculation inFIG.33(a). When n=4, the measured speed is calculated based on the phase difference of 4×Tcbetween sample timings d0 (n=0) and d4 (n=4), so that the delay time is equal to (ΔTLn=2×Tc), where a time instant of measurement is defined as a central time instant of the measurement time period. Therefore, when a moving average of (n+1) times is inserted into the model side, in case of (n+1)=5, the average value ma(5) of d0 to d5 is outputted, and this central time instant defines a delay time (2×Tc) equivalent to the delay in speed measurement. Inserting a delay in the model side for time matching may seem to reduce the effect of vibration suppression. However, the vibration suppression to the torque command, which is required to respond quickly, employs ΔTmAat the preceding stage of the delay block, and thereby is not affected by the time matching. The speed deviation information containing the delay is only used for estimating the disturbance torque that changes relatively slowly, so that the performance is not adversely affected so much. The speed measurement section inFIG.32(a)is based on the assumption that the phase measurement is implemented by a CPU interrupt signal and software, etc., and the interrupt interval Tc, which is constant, contains a variation of ΔT. Therefore, a time instant is measured simultaneously with measurement of the phase, for calculating an accurate time difference. If the speed measurement is implemented as a digital logic circuit, the sample time instant t_det can be accurately synchronized with the sample period Tc, so that the time difference may be replaced with a constant sample period of n·Tcas shown inFIG.32(b). InFIG.32(b), the phase difference outputted from the subtractor142is divided by the constant sample period n·Tcby a divider146to output the measured speed ωm_det The speed measurement section inFIG.32(c)is an example in which the time difference and the filter are configured by a technique called incomplete differentiation or pseudo differentiation. By a first order filter by backward difference (first order delay filter based on sampled data system), a component before being added to a previous value is extracted, and divided by time Tc, to produce a component based on combination of speed measurement by time difference and first order filtering (LPF). On the other hand, by using a first order filter having the same configuration on the model side for time matching, it is possible to insert a delay equivalent to that on the speed measurement side. InFIG.32(c), the first order filter based on backward difference on the speed measurement side includes: a subtractor152that subtracts the output of a delayer151from the phase measured by the RD converter130(speed measurement circuit); a multiplier153having a filter coefficient KLP, through which the output of the subtractor152passes; and an adder154that sums the output of the multiplier153and the output of the delayer151. The delayer151delays the output of the adder154. A divider155divides the output of the multiplier153, which is before being added to the previous value by the adder154, by the time Tc. The first order filter based on backward difference on the model side includes: a delayer65that delays Δωmby a-times delay calculation; a subtractor163that subtracts the output of the delayer162from the output of the delayer65; a multiplier164having a filter coefficient KLP, through which the output of the subtractor163passes; and an adder165that sums the output of the multiplier164and the output of the delayer162. The delayer162delays the output of the adder165. In the case of backward difference, the multiplication coefficient KLPof the multipliers153and164is set as KLP=Tc/(Tc+TLPF), where TLPFis a filter time constant. The sixth embodiment described above produces the following effects.(a) The accuracy of calculation of the reference model can be improved.(b) Since various time matching measures are made with respect to speed measurement and LPF, the accuracy of the deviation (difference) between the reference model and the speed measurement is improved, and the accuracy of disturbance torque estimation is improved. In this way, it is possible to improve the accuracy and response performance of the disturbance torque observer, and thereby improve the stability of vibration suppression control using the disturbance torque observer. Seventh Embodiment FIG.34shows a seventh embodiment that employs the system using the deviation of the motor-accelerating torque as in the third and fourth embodiments.FIG.34shows an overall configuration of a continuous data system. The continuous data system is transformed into a sampled data system, which has the same overall configuration as inFIG.28. In this embodiment, only the disturbance torque observer and the speed calculation are modified. InFIG.34, the same parts as inFIG.27are denoted by the same reference numerals. FIG.34differs from the example of configuration of the sixth embodiment in that the input to the deviation part (subtractor51) of the disturbance torque observer120is modified to a difference {circumflex over ( )}TmAbetween the estimated motor-accelerating torque component {circumflex over ( )}TmA_dlyand the time-differential component TmA_detcalculated by a speed calculation part141. The deviation component {circumflex over ( )}TmAof the motor-accelerating torque, which is the output of the subtractor51, is finally returned to the speed deviation component Δωmby time integration (integrator52), so that the disturbance torque observer can be configured as in the sixth embodiment. Thereby, the output of the vehicle model121in the disturbance torque observer120can be used for both vibration suppression control and disturbance torque estimation. This eliminates the need to calculate the estimated motor speed {circumflex over ( )}ωm. InFIG.34, the prefilter part100shown inFIGS.27and28is omitted for illustration purposes. FIG.35(a)shows an example of configuration produced by transforming the disturbance torque observer120ofFIG.34into a sampled data system, and corresponds toFIG.30of the sixth embodiment. Since the estimated motor speed Δωmis not required, the number of items corresponding to integration can be reduced by moving the integrating parts (122,125), which are positioned at the subsequent stage of the integral coefficients of ΔTJmand {circumflex over ( )}TJWMin the model {circumflex over ( )}DGp2shown inFIG.30, to a position subsequent to the subtractor27in the model {circumflex over ( )}DGp1, and combining the integrating parts into a single integrating part128. The difference output from the subtractor51is caused to pass through an integration coefficient multiplier Tc/{circumflex over ( )}TJmand the integrating part122, which is composed of a delayer having a delay operator z−1, and an adder, and is thereafter inputted to the gain multiplier43, to estimate the disturbance torque. FIG.35(b)corresponds toFIG.31of the sixth embodiment, wherein the integration (integration coefficient multiplier Tc/{circumflex over ( )}TJmand integrating part122) in the model {circumflex over ( )}DGp2is moved to the subsequent stage of the deviation calculation by the subtractor51, and accordingly, the model {circumflex over ( )}DGp2ofFIG.31is simply implemented by only a second order IIR filter127( DGpTmA2_IIR2) ({circumflex over ( )}Tm-{circumflex over ( )}TmAtransformation block of the present invention). The reason why the output of the vehicle model is set to the estimated motor-accelerating torque {circumflex over ( )}TmAin the seventh embodiment is that it is desirable that the two integral terms {circumflex over ( )}TJmand {circumflex over ( )}TJWMare moved to the subsequent stage of the difference calculation and thereby reduced to one integral term. For digital calculation of the sampled data system, it is expected that as the number of integrators decreases, errors decrease, and the accuracy gets enhanced. FIG.36shows details of the difference calculation of the motor-accelerating torque and the configuration of the part for integrating the difference in the seventh embodiment.FIG.36(a)corresponds toFIG.32(a)of the sixth embodiment, in which the output from the model side is changed to the motor-accelerating torque only, and on the other hand, a time differentiation is added to the speed measurement side while being approximated to a time difference calculation. The speed measurement side ofFIG.36(a)differs from that ofFIG.32(a)in that the time differentiation is added. The measured motor rotational speed ωm_detoutputted from a calculator145is caused to pass through a delayer132having a delay operator z−1; a subtractor133calculates a difference between the output of the delayer132and ωm_det; and the difference outputted from the subtractor133is caused to pass through a differentiator134having a coefficient TJm/Tc. The addition of the time differential calculation to the speed measurement side causes an increase in the delay time component. In order to compensate for this increase, an output of a moving average calculation part66is caused to pass through a two-samples moving average calculation part67to obtain TmA_dly, and the output of the subtractor51is caused to pass through the integration coefficient multiplier Tc/{circumflex over ( )}TJmand the integrating part122composed of a delayer having a delay operator z−1, and an adder, to obtain Δωm. Although not shown, the calculation part for ωm_detinFIG.36(a)may be replaced with a configuration corresponding toFIG.32(b)of the sixth embodiment. Namely, the RD converter130, the delayers141and143, the subtractors142and144, and the calculator145inFIG.36(a) may be replaced with the RD converter130, the delayer141, the subtractor142, and the divider146inFIG.32(b). FIG.36(b)shows a configuration in which an IIR filter (first order filter with a filter coefficient KLP) is employed for filtering after speed measurement and time differentiation as shown inFIG.32(c). Since the IIR filter is expected to produce an LPF effect, and some noise is allowed to occur in speed measurement, the sample interval for speed measurement is set to n=1. FIG.36(b)differs fromFIG.32(c)in that a differentiating function is provided between the RD converter130and the subtractor152, wherein the differentiating function is composed of a delayer135having the delay operator z−1, a subtractor136for calculating a deviation from the output of the delayer135, and a multiplier137for multiplying the output of the subtractor136by a coefficient 1/Tc. In order to cancel this differentiation, an integral coefficient multiplier Tc/{circumflex over ( )}TJmand an integrator122are provided on the output side of the subtractor51. Furthermore, the divider155inFIG.32(c)is a part of the speed calculation section, and is therefore moved as an element137to a position immediately subsequent to the subtractor136. While the speed measurement side ofFIG.36(a)employs the delayer132for difference calculation in the time differentiation section, a function of the first order delay filter is employed instead inFIG.36(b). Although the first order delay filter serves originally for the speed, the time differential component of the speed can be extracted by extracting {circumflex over ( )}TmA_detfrom the input part of the integrating part inside the filter. In other words, the function of the delayer132is included in the delayer151, resulting in a slightly simplified configuration. On the other hand, in the model side ofFIG.36(b), the input signal itself is changed from the model estimated speed {circumflex over ( )}ωmto its differential component, the motor-accelerating torque {circumflex over ( )}TmA. Others are the same as inFIG.32(c), where as in the sixth embodiment, the first order delay filter is inserted, and the moving average calculator67is provided subsequent to the delayer65for matching with an increase in the delay time in the speed measurement side which is caused by the differential calculation. As described above, according to the seventh embodiment, various time matching measures are made with respect to speed measurement and LPF as in the sixth embodiment, so that the accuracy of the deviation (difference) between the reference model and the speed measurement is improved, and the accuracy of disturbance torque estimation is improved. In this way, it is possible to improve the accuracy and response performance of the disturbance torque observer, and thereby improve the stability of vibration suppression control using the disturbance torque observer. Eighth Embodiment In order to suppress the rattling shock due to gear backlash, it is desirable to reduce the motor torque during the backlash period, to suppress rapid changes in speed. However, if the motor torque is limited to zero, the backlash phase does not change, so that it takes longer time to eliminate the play. Therefore, it is desirable to accelerate the motor at an upper limit speed corresponding to an allowable shock level, and pass through a condition of backlash as quickly as possible, and thereby shorten the period during which the torque command is limited. For this purpose, it is required to accurately estimate the start and end of backlash. In view of the foregoing, with respect to the configurations of the sixth and seventh embodiments, the eighth embodiment is additionally provided with a function of estimating the backlash period and a function of suppressing the torque command to a small value during the backlash period. FIG.37shows an example of overall configuration of the eighth embodiment, andFIG.38shows an example of configuration of a backlash period detection section200. The elements already described in the sixth and seventh embodiments are the speed calculation part140, the disturbance torque observer (Tdist_OBS)120, the vibration suppression control filter150(Fcomp), etc. Furthermore, as indicated by the one-dot chain line in the disturbance torque observer120inFIGS.27and34, a function is added to output the component (Tm-{circumflex over ( )}TmA) as the estimated shaft torsional torque {circumflex over ( )}Td, and is used for estimation. InFIG.37, a compensation torque subtractor201(subg) is provided for subtracting the compensation torque component ΔTcompfor vibration suppression from the output of the adder105in the prefilter part100. On the output side of the compensation torque subtractor201, torque limiters are provided for limiting the output torque command Tm, wherein a first torque limiter101(TLIM0) has a first torque limit value, and a second torque limiter102(TLIM1) has a second torque limit value that has a narrower width between upper and lower limits than the first torque limit value. On the output side of the torque limiters101and102, there is a switch swA for selecting the output of the torque limiters101and102, and when the backlash period detection section200described below detects backlash, selecting the output of the second torque limiter102. The output (Tm) of the switch swA is added by an adder108(addg) to the pre-delay compensation torque component ΔTcompdirectly outputted from the vibration suppression control filter150, and the output of addition of the adder108is inputted to a delayer103that is used for holding the previous value. The disturbance torque observer120receives input of the output torque command Tmlimited by the torque limiter selected by the switch swA and the motor rotational speed ωm_detmeasured by the speed calculation part140, and outputs the estimated motor-accelerating torque component {circumflex over ( )}TmA, and the estimated shaft torsional torque {circumflex over ( )}Tdthat is the component of Tm-{circumflex over ( )}TmA. The backlash period detection section200receives input of the output torque command Tmoutputted from the torque limiter selected by the switch swA and the estimated shaft torsional torque {circumflex over ( )}Tdoutputted from the disturbance torque observer120, estimates the backlash period, and outputs a logic signal “S_BL” (backlash detection signal) indicating the status of the backlash period. When the logic signal S_BL is used for manipulation of the torque command, it corresponds to a feedback signal. Therefore, a backlash detection signal S_BLz, which is produced by delaying the input signal by one sampling by a delayer202, is used as an operation signal for the switch swA. In this embodiment, the backlash detection signal S_BLz is configured to output “1” during the backlash period, so that the switch swA selects a “=1” side, namely, selects the torque limiter102having a smaller width between upper and lower limits. This limits the magnitude of the torque command during the backlash period to prevent rapid acceleration of the motor. FIG.38shows a main part of the backlash period detection section200, which includes:a switch swB that is fixed to a “=d” side to receive input of the estimated torsional torque {circumflex over ( )}Td;a divider210(torque-to-phase transformation section) configured to perform transformation into an estimated shaft torsional phase {circumflex over ( )}θd;a backlash start timing detection section220configured to detect a zero cross point of the estimated shaft torsional phase ({circumflex over ( )}θd) as a start timing of the backlash period;a torsional speed estimation section230configured to estimate the shaft torsional speed {circumflex over ( )}ωd_divTd by time-differentiating the estimated shaft torsional phase {circumflex over ( )}θd;a speed change estimation section240configured to estimate a change component {circumflex over ( )}ωd_BLof the motor speed during the backlash period by time-integrating the output torque command TminFIG.37by a time constant {circumflex over ( )}TJmequivalent to the rotational inertia of the motor;a torsional displacement estimation section250configured to calculate an estimated phase change amount {circumflex over ( )}ΔθBLcorresponding to backlash by: calculating by an adder251a sum of the shaft torsional speed, which is estimated by the torsional speed estimation section230, an initial torsional speed {circumflex over ( )}ωd_ini, which is stored in a latch circuit sh1at the start timing of the backlash period detected by the backlash start timing detection section220, and the speed change component {circumflex over ( )}ωd_BLduring the backlash period, which is estimated by the speed change estimation section240; and time-integrating the sum; anda backlash end detection section260configured to detect an end of the backlash period by comparing the phase change amount ΔθBL, which is estimated by the torsional displacement estimation section250, with an absolute value of backlash phase width θBLand a margin width Δθ as set values; andwherein the backlash period is detected based on the backlash start timing (trigger signal E_Set) detected by the backlash start timing detection section220and the backlash end (S_Rst) detected by the backlash end detection section260. Next, the following describes details ofFIGS.37and38. The switch swB inFIG.38is fixed to the “=d” side in the eighth embodiment, and is fixed to a “=r” side in the ninth embodiment. Accordingly, in the eighth embodiment, {circumflex over ( )}Tdis used as an input to the shaft torsional phase estimation calculation (divider210). A backlash period prediction section is divided into two sections, the backlash start timing detection section220and the backlash end detection section260. Based on the detection signals (E_Set, S_Rst) indicating the start timing and end, the logic signal “S_BL” indicating the status of the backlash period is outputted by a flip-flop sr1composed of an SR-FF (set-reset flip-flop). In the shown example, it is configured to output “=1” during the backlash period. Next, the following describes configuration of the backlash start timing detection section220. {circumflex over ( )}Tdobtained by the disturbance torque observer120inFIGS.27and34corresponds to a reaction force from the elastic shaft, and is therefore converted to the shaft torsional phase {circumflex over ( )}θdby dividing by the stiffness coefficient Kdin the divider210(torque-to-phase converter). The backlash start timing detection section220detects the zero cross timing at which the polarity of the phase {circumflex over ( )}θdswitches between positive and negative, and outputs the start timing in the form of trigger signals. The trigger signals have two types according to the direction of phase change, wherein “E_For” is outputted for the direction from negative to positive, and “E_Rev” is outputted for the direction from positive to negative. These signals are combined into the single backlash start timing trigger signal E_Set by a logical sum circuit221(OR), and outputted from the backlash start timing detection section220. This start timing is inputted and used as a trigger signal for the flip-flop sr1(SR-FF). Furthermore, for detecting the end of the backlash, information on the direction of change in the phase is required. Therefore, the E_For and E_Rev trigger signals are latched, and the status signal “S_FR” indicating the polarity of the direction is also outputted. Next, the following describes a method for detecting the end of backlash. The component {circumflex over ( )}Tdcannot be used for this purpose. The component {circumflex over ( )}Tdis constantly compensated by the vibration suppression control based on disturbance estimation by the disturbance torque observer, so that the motor-accelerating component during the backlash period is also compensated to change the output torque command Tm. In other words, since {circumflex over ( )}Tdalso changes rapidly, it becomes impossible to accurately estimate the shaft torsional phase based on {circumflex over ( )}Td. Therefore, estimation of the end of backlash is implemented by combination with another prediction method. The configuration thereof is depicted at the bottom ofFIG.38. If there is no backlash and vibration is suppressed as in the waveform of the shaft torsional speed ΔωmWshown inFIG.40(b), the shaft torsional speed becomes almost constant when the polarity changes while the shaft torque changes at a constant gradient. Since this speed is required for estimating the backlash period, a function is added for estimating the shaft torsional speed from the component {circumflex over ( )}Td. For this purpose, the shaft torsional phase {circumflex over ( )}θd, which is produced by conversion from the component {circumflex over ( )}Tdby the divider210, is used, and time-differentiated by the torsional speed estimation section230, to calculate the shaft torsional speed {circumflex over ( )}ωd_divTd. This estimated shaft torsional speed is held as the initial torsional speed value {circumflex over ( )}ωd_iniby the backlash start timing trigger signal E_Set outputted from the backlash start timing detection section220, using the latch circuit sh1. The torsional speed estimation section230is composed of a delayer231, a subtractor232and a divider233for time differentiation. However, since the torque command Tmon the motor side changes even during the backlash period, the speed change component {circumflex over ( )}Δωd_BLis also estimated by time-integrating Tmwith the time constant {circumflex over ( )}TJmof the motor. The time integration with the time constant TJmis performed by an integration coefficient multiplier Tc/{circumflex over ( )}TJmand an integrator241composed of a delayer having a delay operator z−1and an adder. The speed change component {circumflex over ( )}Δωd_BLis reset to zero by a switch sw3, which is switch-controlled by the backlash detection signal S_BLz estimated at the previous sampling timing until start of the backlash period. During the backlash period, the switch sw3is switched to the adder side to the integrating part241to estimate the change component only. Then, the change component {circumflex over ( )}Δωd_BLis added and corrected by the adder251to the initial speed {circumflex over ( )}ωd_inilatched by the latch circuit sh1, to produce a quantity that is regarded as the shaft torsional speed {circumflex over ( )}ωd_BLduring the backlash period. Finally, in the torsional displacement estimation section250, the shaft torsional speed {circumflex over ( )}ωd_BLis time-integrated to estimate the phase change amount {circumflex over ( )}ΔθBLcorresponding to the backlash. This time integration is performed by a multiplier252with the sample period Tc, and an integrator253composed of a delayer having a delay operator z−1and an adder. The initial value of the phase change amount {circumflex over ( )}ΔθBLat the start of backlash is also reset to zero by a switch sw4whose switching is controlled by the backlash detection signal S_BLz. During the backlash period, the switch sw4is switched to the adder side to the integrating part253to estimate the phase change. The integral coefficient multiplier Tc/{circumflex over ( )}TJm, the integrating part241, and the switch sw3constitute the changing speed estimation section240. The adder251corresponds to a compensating section for correcting the initial speed by the change component. In the position subsequent to the adder251, the multiplier252, the integrator253, and the switch sw4constitute the torsional displacement estimation section250. Next, the following describes configuration of the backlash end detection section260. The direction (positive/negative signs, positive/negative polarity) of the phase displacement to be estimated depends on the positive/negative polarity (S_FR) of the initial shaft torsional speed. Accordingly, a reference phase to be compared for determination of the end of backlash is required to be shifted depending on the positive/negative polarity. In view of the foregoing, reference phase setting parts261pand261nare provided for setting two kinds of determination reference phases in accordance with the positive/negative polarity. Switches sw2fand sw2rare switch-controlled by the status signal S_FR outputted from the backlash start timing detection section220, to shift the determination reference phases, which are latched by latch circuits sh2fand sh2rat the timing of the backlash start timing trigger signal E_Set. A determination phase width θp as a reference, which is latched by the latch circuit sh2f, is inputted to a “b” input terminal of a comparator cmpf. This is compared with the estimated phase change amount ΔθBLinputted to an “a” input terminal, to detect a state of ({circumflex over ( )}ΔθBL>θp). A determination phase width θn as a reference, which is latched by the latch circuit sh2r, is inputted to an “a” input terminal of a comparator cmpr. This is compared with the estimated phase change amount {circumflex over ( )}ΔθBLinputted to a “b” input terminal, to detect a state of (θn>{circumflex over ( )}ΔθBL). Outputs of determination of the comparators cmpf and cmpr are caused to pass through the logical sum circuit262to produce the backlash end signal S_Rst, and reset the flip-flop sr1. In the reference phase setting parts261pand261n, a reference phase width of backlash is set as an unsigned absolute value θBL, and a determination value is set by adding the margin width Δθ and then setting the positive/negative sign depending on the direction of change. Furthermore, even during the backlash period, the polarity of the torque command Tmmay change to reverse the direction of rotation. Accordingly, for the reverse direction, the determination level is set to about the margin width Δθ close to zero, thereby making it possible to output the end of backlash immediately in response to reverse. The determination phase widths θp and θn are compared with the estimated phase change amount {circumflex over ( )}ΔθBLto determine the end, and the signal S_BL of SR-FF (flip-flop sr1) is reset. The above is an example of configuration of the backlash period estimation section. The reference phase setting parts261pand261n, the switches sw2fand sw2r, the latch circuits sh2fand sh2r, the comparators cmpf and cmpr, and the logical sum circuit262constitute the backlash end detection section260. The flip-flop sr1outputs the backlash detection signal S_BL during the period from being set by the backlash start timing trigger signal E_set to being reset by the backlash end signal S_Rst. The estimated phase change amount {circumflex over ( )}ΔθBLis a change amount of the difference between the motor phase and the tire phase from the start of the backlash, and corresponds to an estimated phase of gear backlash play. When the play phase reaches the set backlash phase (θp, θn), the end of the backlash period is determined by the comparators cmpf, cmpr and logical sum circuit262. Referring back toFIG.37, the following describes a method of limiting the torque command based on the backlash detection signal S_BL. There are two types of upper and lower limit blocks in the prefilter part100. The first upper and lower limit block TLIM0(torque limiter101) is a conventional one, and the other second upper and lower limit block TLIM1(torque limiter102) serves for limitation during the backlash period and sets a torque width (torque limit value) to a second torque limiter value smaller than the first upper and lower limit block TLIM0(torque limiter101). The switch swA is switched to a backlash limit side (TLIM1side) only when the backlash detection signal S_BLz is indicating the backlash period. This limits the magnitude of the torque command during the backlash period, and thereby prevents acceleration of the motor. However, if the compensation component ΔTcompof the vibration suppression control is subtracted at the subsequent stage of the upper/lower limit block, the compensation component ΔTcompis not subject to this limiting function. Therefore, the subtracting compensation part (compensation torque subtractor201) is moved to the preceding stage of the limiter. With this configuration, when the switch swA is switched back from the backlash side (=1) to the normal side (=0), the output of the prefilter part100changes rapidly, thereby causing resonance. Therefore, in order to ensure a bumpless feature, a system is adopted in which the compensation component ΔTcompis subtracted at subg (compensation torque subtractor201) and the same compensation component ΔTcompis added at addg (adder108) immediately before holding of the previous value (delayer103). The foregoing is an example of configuration of the detection of the backlash period and the method of limiting the torque command during the backlash period. The torque limitation during the backlash period does not need to be activated in all situations where the torque crosses zero, specifically, in situations where the rate of change of the torque command inputted from the outside is gradual. The vibration suppression control with the disturbance torque observer also operates to limit the torque command during the backlash period. Therefore, it is sufficient to cause the limitation by the backlash detection signal S_BL and TLIM1(torque limiter102) to be activated only when the limitation by the vibration suppression control is inadequate. Next, the following describes the principles of the phase estimation. As described above, in the systems to which the sixth and seventh embodiments are applied, {circumflex over ( )}Tdcannot be used to detect the end of backlash. Therefore, since the combined rotational inertia of the tires and the vehicle body is large, and the torque command is also near zero, it is assumed that a speed change of the tire side during a short time is small, and the method described above is adopted. If the rotational speeds of both ends of the gearing can be measured, the speed difference ΔωmW(t) is calculated based on the motor side speed ωm(t) and the tire side speed ωw(t) as in mathematical expression (17), and the relative phase θBL(Δt) between the gear teeth during the backlash period can be calculated by time integration for the elapsed time Δt from the backlash start time t0 as in mathematical expression (18). Δωmw(t0+Δt)=··ωm(t0+Δt)-ωw(t0+Δt)(17)θBL(Δt)=∫t0t0+Δt(Δωmw(t))dt(18) ΔωmW(t) is a time derivative of the sum of two types of phase components, i.e. a phase component of shaft torsion and a phase component of backlash. ΔωmW(t) indicates the shaft torsional speed until immediately before the occurrence of backlash, and indicates the relative speed during the period of gear play because the shaft torque during the backlash period is equal to zero. However, since the tire side speed cannot be measured, the tire side speed is approximated using other information as in mathematical expression (19). ∧Δωmw(t0+Δt)=··ωm(t0+Δt)-∧Δωw(t0)=··Δωm(Δt)+(ωm(t0)-∧Δωw(t0))=Δωm(Δt)+Δωmw(t0)(19) First, on the assumption that the tire speed changes little, an initial value is held and substituted as {circumflex over ( )}ωw(t0+Δt)≈{circumflex over ( )}ωw(t0). Next, the motor side speed is separated into a speed change Δωm(Δt) and an initial speed ωm(t0) as ωm(t0+Δt)=Δωm(Δt)+ωm(t0). Then, as in the third line of the mathematical expression (19), the right side is reduced into two elements, namely, the first term of the right side is reduced to the motor side speed change Δωm(Δt), and the second term of the right side is reduced to the initial value of the torsional speed Δωmw(t0)=(ωm(t0)−{circumflex over ( )}ωw(t0)). Thus, this is handled in a form where a variable term and a constant term are separated from each other. For the constant term, the speed, which is produced by time-differentiating the phase {circumflex over ( )}θdby the torsional speed estimation section230, is used, wherein the phase {circumflex over ( )}θdis estimated from {circumflex over ( )}Td. For the variable term, the motor speed change Δωm(Δt) during the backlash is estimated by integrating the torque command Tmby mathematical expression (20). Δωm(Δt)=1TJm∫0Δt(Tm(t))dt(20) Advantageously, all of the input torque to the motor serves as a torque component that accelerates the motor, because no reaction force is applied to the motor output shaft. Therefore, the rotational inertia TJmof the motor may be used as the integral time constant as in the integral coefficient multiplier Tc/{circumflex over ( )}TJmof the speed change estimation section240. By mathematical expression (19) and the approximation of mathematical expression (20), it is possible to calculate an approximate value of the shaft torsional speed that changes during the backlash period. Then, by applying the integral calculation of mathematical expression (18) to the approximate value, it is possible to calculate an estimated value of the backlash phase. Then, by comparing the estimated value of the backlash phase with the preset backlash phase width, the end of the backlash is detected. For description based on correspondence between the mathematical expressions described above andFIG.38, the input signal {circumflex over ( )}Tdis divided by the stiffness coefficient Kdto calculate the torsional phase {circumflex over ( )}θd; the torsional phase {circumflex over ( )}θdis time-differentiated to calculate {circumflex over ( )}ωd_divTd corresponding to Δωmw(t); and {circumflex over ( )}ωd_divTd is sampled by the latch circuit sh1to obtain {circumflex over ( )}ωd_inicorresponding to the initial value Δωmw(t0). The torque command Tm, which is the other input signal, is time-integrated to calculate {circumflex over ( )}Δωd_BLcorresponding to the motor side speed change Δωm(Δt); the sum of {circumflex over ( )}Δωd_BLand {circumflex over ( )}ωd_iniis calculated by the adder251to determine {circumflex over ( )}ωd_BLcorresponding to (t0+Δt); and {circumflex over ( )}ωd_BLis time-integrated by the torsional displacement estimation section250to estimate {circumflex over ( )}θBLcorresponding to {circumflex over ( )}θBL(Δt). The initial value of Δωm(Δt) in mathematical expression (20) and the initial value of {circumflex over ( )}θBL(Δt) in mathematical expression (18) are zero at the start time t0. Accordingly, while the backlash detection signal S_BLz is at “0”, namely, during a standby period where no backlash occurs, {circumflex over ( )}ωd_BLand {circumflex over ( )}θBLare reset to zero values by the switches sw3and sw4. In this way, it is possible to estimate the amount of change in the backlash phase by the configuration ofFIG.38. Then, the estimated amount of change is compared with the phase widths θp, θn, which are set by the reference phase setting parts261p,261n, to detect the end of backlash. As described above, the backlash phase widths, which are set comparison references, have two kinds corresponding to torque change directions, namely, a kind corresponding to the positive direction, and a kind corresponding to the negative direction. Accordingly, selection is made by the switches sw2fand sw2rand latch circuits sh2hand sh2r. The system of the eighth embodiment requires some assumptions and measures. First, at the start of estimation, the actual torque is required to be estimated wherein the estimated value of the disturbance torque observer is sufficiently converged. If large torque changes occur repeatedly in a short period of time, it is impossible to accurately estimate the start timing of backlash, so that an error occurs in the estimation of the initial speed, and the detection of the end becomes inaccurate. In this regard, it is conceivable that it is when the torque command is small that the torque polarity repeatedly changes in a short time. As described with reference toFIG.42, the systems of the sixth and seventh embodiments are effective for suppressing the torque command, so that when the torque command is small, there is no problem even if the estimation operation of the eighth embodiment is stopped and the limiter switching is not performed. Furthermore, since the phase of backlash varies from one machine to another, the estimated period varies. In this regard, it is preferable that the response be quiet even if the response is slightly delayed, rather than the period during which the torque is reduced is shortened to allow the occurrence of the rattling shock. Therefore, the backlash start determination is set to a level such that a backlash start can be detected a little earlier than zero-crossing of the torque (zero-cross edge detection by the backlash start timing detection section220). This may be implemented by adding Δθ as an appropriate margin phase to the set values of the reference phase setting parts261p,261n, to delay detection. FIG.43is a time chart showing an example of characteristics when the system of the eighth embodiment is additionally applied to the seventh embodiment. This is an example of behavior under the same conditions as inFIG.42. The behavior regarding the prediction operation during the backlash period is shown in the time chart ofFIG.44. InFIGS.43(A) and43(B) where waveforms (b) show the shaft torsional speed, it can be confirmed that the speed change width of the shaft torsional speed during the backlash period can be significantly suppressed as indicated by a section where the solid line and the dashed line overlap with each other. Furthermore, the control output Tmis forcibly suppressed to a small value, and as shown in waveforms (c), the motor-accelerating torque TmAand the correction amount ΔTcompof the vibration suppression control are both suppressed to small values. Since the estimated shaft torque {circumflex over ( )}Tdin waveforms (d) has a waveform similar to the actual torsional torque until the backlash starts, it can be seen that the start timing can be detected by zero-cross detection. However, during the subsequent backlash period, the component {circumflex over ( )}Tdis suppressed to be small, but it is not suppressed to near zero. Therefore, the torque limiter is added. Regarding the estimated torque {circumflex over ( )}Tobsof the disturbance torque observer, an estimation error occurs due to a pulsation remaining even after the backlash. However, the estimated torque {circumflex over ( )}Tobsconverges to a normal estimated value within 0.1 s. Therefore, it is conceivable that the backlash estimation can be thereafter performed again. FIG.44shows behavior of the function of estimating the backlash period, wherein in waveforms (a), a dashed line indicates the torsional speed estimated based on the input of {circumflex over ( )}Td. Here, {circumflex over ( )}ωd_iniheld at the start is drawn with a solid line. In waveforms (b), a solid line indicates the component Δωm(Δt) ({circumflex over ( )}Δωd_BL) estimated by integrating the motor torque command, and a dashed line indicates the sum of the component Δωm(Δt) ({circumflex over ( )}Δωd_BL) and the initial value {circumflex over ( )}ωd_ini({circumflex over ( )}ωd_BL) It can be confirmed that even if the torque command is limited, it is possible to generate a speed sufficient to terminate the backlash in a short time. In waveforms (c), solid lines indicate the phase {circumflex over ( )}θdcalculated from the torque estimation {circumflex over ( )}Td, and the component {circumflex over ( )}ΔθBLestimated using the mathematical expression (18), a dashed line indicates θp, and a broken line indicates θn, wherein θp and θn are to be compared with {circumflex over ( )}ΔθBL. Waveforms (d) indicate the timing signals E_Set and S_Rst, and the backlash detection signal S_BL produced by latching the timing signals E_Set and S_Rst. For comparison, the backlash period detected from the actual plant model is also drawn with a dashed line at the bottom. It can be seen that the backlash period can be estimated almost accurately. Ninth Embodiment In the eighth embodiment, the slip phase and speed are estimated using the input/output difference component {circumflex over ( )}Tdof the disturbance torque observer. In the ninth embodiment, the torque command Tmis used instead for input information. Specifically, the switch swB ofFIG.38is set to the “=r” side to input Tm, which is caused to pass through the divider210to be transformed into the shaft torsional phase {circumflex over ( )}θd, thereby providing the torque command Tmas a substitute of an information source for estimating {circumflex over ( )}θd. Since the torque command is near zero, this approximation can be adopted if the compensation component of the vibration suppression control has converged. Since a backlash occurs when the torsional torque of the shaft is near zero, the estimated shaft torque {circumflex over ( )}Tdcalculated by the disturbance torque observer and Tmare approximately equal to each other. Therefore, with regard to backlash prediction, there is little difference even if the signal is replaced. Other operations are the same as in the eighth embodiment.FIGS.45and46show an example of characteristics in correspondence toFIGS.43and44. The characteristics ofFIGS.45and46are almost the same as those ofFIGS.43and44. It has been confirmed that the operation is possible even with the approximation. Comparing the examples of characteristics of the eighth embodiment and the ninth embodiment, it seems that there is little superiority or inferiority due to variation in system. Accordingly, for practical use, it is conceivable that which is to be selected is determined according to the amount of noise contained in speed measurement. By expanding the configuration of the sixth and seventh embodiments with addition of the functions of the eighth and ninth embodiments, it is possible to estimate the backlash start time and end time, and furthermore, reduce the torque command during the backlash period, and thereby suppress the amount of acceleration of the motor. This reduces the kinetic energy resulting from acceleration, and reduce the shock when the gear teeth collide at the end of the backlash. In this system, backlash cannot be accurately estimated in a region where the torque command is small or when the torque changes slowly. However, the vibration suppression control using the disturbance torque observer of the sixth and seventh embodiments also has a function of reducing the output torque command when the motor rapidly accelerates during the backlash period. Therefore, the eighth and ninth embodiments are not required to operate over the entire region, and are only required to operate only when the rate of change of the torque command is large enough to facilitate estimation of the backlash period. In other words, by combining the sixth or seventh embodiment with the eighth or ninth embodiment, it is possible to suppress rattling shocks caused by a wide range of backlash. | 134,250 |
11942885 | DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS FIG.1schematically shows a device100in a top view. In the example, device100includes a receptacle102for the transport of objects. Receptacle102may be designed as a surface, trough, or grating. Device100is designed in the example for the purpose of moving one or multiple objects in a movement direction104of device100. A Cartesian coordinate system including x axis, y axis, and z axis is shown inFIG.1. A position of device100is indicated in the example with reference to an origin of the Cartesian coordinate system. In the example, a position of a point106is defined as the position of device100, which is located in the example in the center of a receptacle102designed as a surface. Other definitions of the position, for example, based on polar or cylinder coordinates, are also possible. Point106may be situated at another point of device100. Device100is movable with respect to this coordinate system in the example. One pose of device100is defined in the example by the position, a roll angle ϕ around the x axis, a pitch angle θ around the y axis, and a yaw angle Ψ around the z axis. It may be provided that a Cartesian coordinate system fixed with respect to device100is defined, roll angle ϕ being defined around a x axis, pitch angle θ being defined around a y axis, and yaw angle Ψ being defined around a z axis of this fixed Cartesian coordinate system. Device100includes at least one driving element110. In the example, driving element110includes a permanent magnet. Instead of a permanent magnet, a magnetic coil may also be provided. The at least one driving element110is designed in the example as a permanent magnet. Optionally, at least one magnetic coil may be provided alternatively or additionally to the permanent magnet as driving element110. In this case, a control unit112may be provided, which is designed in this aspect to activate the at least one driving element110for a movement of device100. Electrical lines for the activation connect control unit112to the at least one driving element110. These are not shown inFIG.1. Device100may include an energy store114, which is designed to supply control unit112and the at least one driving element110with electrical energy. Electrical lines for the energy supply connect energy store114to control device112and the at least one driving element110. These are not shown inFIG.1. Energy store114is a battery in the example. Instead of a battery, a capacitor may also be provided. Instead of energy store114, a current collector may also be provided for the permanent energy supply of device100. In the example, device100includes a plurality of driving elements110, which are situated in a matrix-shaped arrangement schematically shown in the top view inFIG.1. In the example, two rows each including 13 permanent magnets are provided, which extend in the x direction and form columns in the y direction, i.e., a total of 26 permanent magnets are provided. If device100moves with respect to the coordinate system, the pose changes, i.e., the matrix-shaped arrangement of driving elements110moves in the coordinate system and may rotate, roll, pitch, and/or yaw. A top view of a conveyor device200is schematically shown inFIG.2. The Cartesian coordinate system is shown inFIG.2. Conveyor device200is fixed with respect to the Cartesian coordinate system. Conveyor device200includes a plurality of actuators202. In the example, seen in the top view, the actuators are situated in the form of a matrix in rows, which extend in the x direction and form columns in the y direction. In the example, each of actuators202includes at least one permanent magnet. In the example, a Halbach array or a Halbach element is provided. The Halbach array includes three permanent magnets of different magnetic orientation in the example. In the example, the three permanent magnets are situated in one row. One of the outer permanent magnet elements is oriented in the example in such a way that the magnetic north pole points in the negative z direction. This is indicated inFIG.2by a circle. The other of the outer permanent magnet elements is oriented in the example in such a way that the magnetic north pole points in the positive z direction. This is indicated inFIG.2by a dot. A middle magnet element situated between the two outer permanent magnets is oriented in such a way that its north pole points toward the element pointing in the positive z direction. Another magnetic orientation is also possible. It is also possible to provide electromagnets instead of the permanent magnets. In the example, conveyor device200includes at least one receiver device204, which is schematically shown in the top view inFIG.1. The at least one receiver device204is designed in the example to receive information about a pose of device100. Receiver device204is designed in the example to receive information about a position of device100. In the example, each of actuators202includes an electric motor, which is designed to rotate the Halbach array around an axis of rotation which is situated in parallel to the z axis. A magnetic field generated in sum by a superposition of the individual magnetic fields of all actuators202on a conveyor side206of conveyor device200may thus be deliberately influenced. The magnetic field is used, on the one hand, to repel the permanent magnets of device100in order to establish a distance from conveyor device200. On the other hand, the magnetic field is used to move device100with respect to conveyor device200. An activation device208is designed to activate actuators202. In the example, a rotation angle α around the axis of rotation of this actuator202is set by activation device208for an actuator202. In the example, activation device208is designed to activate each of actuators202individually using a separate rotation angle α. Activating groups of actuators202jointly using the same rotation angle may also be provided. Activation device208is designed to receive sensor signals from receiving devices204. Electrical lines connect activation device208for activating actuators202to actuators202in the example. Electrical lines connect activation device208for detecting sensor signals to the at least one receiving device204in the example. In the example, viewed from the right, the first three columns of actuators202are aligned in parallel to the x direction. This corresponds in the example to a particular rotation angle α=0°. The two columns of actuators202adjoining to the left thereon are rotated by 90° clockwise in this example. This corresponds in the example to a particular rotation angle α=+90°. The column of actuators202adjoining to the left thereon is rotated by 90° counterclockwise in this example. This corresponds in the example to a particular rotation angle α=−90°. Actuators202adjoining to the left thereon are aligned in this example like the first three columns. In the example, this means a particular rotation angle α=0°. Device100or a sensor system is designed in the example to send a present pose of device100to the at least one receiving device204. Device100or the sensor system is designed in the example to send a present position of device100to the at least one receiving device204. It is unimportant for the activation how the pose or the position of device100is determined in the Cartesian coordinate system. The pose or the position is received during operation of conveyor device200, for example, continuously, for example, cyclically or at irregular time intervals, by receiving device204. A determination of the pose and/or a position determination is carried out repeatedly during operation of conveyor device200. Activation device208may also be designed to receive information about the pose using receiving device204and to determine the pose therefrom. A piece of information about the pose of device100may be generated in different ways. For the operation of activation device208, it is unimportant how the actual value for the pose is determined. For example, a sensor or a camera-based system may be provided for determining the pose. The position determination may take place as a function of information about a position which is received at receiving device204. It may be provided that as a function of a last known pose of device100, only those actuators202are activated, which, knowing the geometry of device100and conveyor device200, may provide a significant contribution to the movement of device100. This significantly reduces the amount of data. InFIG.3, conveyor device200and device100are shown in a side view. The reference numerals for elements which are already described inFIG.1andFIG.2are retained inFIG.3. In the Halbach array, the arrow tips indicate the location of the magnetic north pole of the particular permanent magnets. Device100is located in the view shown inFIG.3at a distance from conveyor device200. The distance is generated in the example by the superimposed magnetic fields of the permanent magnets. The distance is shown uniformly inFIG.3. Due to pitch and/or roll movements, in particular also with yaw movements, an unequal distance of individual areas of device100from conveyor device200may occur. A regulation or control of a movement and the distance of device100with respect to conveyor device200is described hereinafter. A device400for activating conveyor device200is schematically shown inFIG.4. Device400includes a model402and a control unit404. Device400optionally includes a forward model406, a database408, and a training device410for a training of model402. Device400includes at least one memory412for model402and at least one computing device414. Computing device414and memory412are designed in the example to carry out the method described hereinafter. In database408, information about a plurality of actual values for the pose is stored for a training of model202. In the example, Pactual denotes an actual value of a pose and Psetpoint denotes a setpoint value for a pose. Control unit404is designed to determine, as a function of an actual value of a pose Pactual and a setpoint value of a pose Psetpoint, a control deviation e and to determine, as a function of control deviation e, a setpoint value for a torque Tsetpoint and a setpoint value for a force Fsetpoint, using which device100is to be moved by conveyor device200. Control unit404may be a state regulator, for example, an LQ controller, which is designed to determine setpoint value for torque Tsetpoint and setpoint value for force Fsetpoint as a function of a predefinable trajectory. Control unit404may be designed to determine, as a function of a gravitational force acting on device100, a pilot control value for setpoint value for torque Tsetpoint and/or setpoint value for force Fsetpoint, which at least partially compensates for the gravitational force. The gravitational force is determined in the example as a function of a weight of device100and/or as a function of a weight of an object which device100carries or is predefined as a parameter. The weight may be determined or predefined as a parameter. In the example, the poses are vectors including elements x, y, z, ϕ, θ, Ψ and control deviation e is a vector including elements for corresponding differences of the individual elements. In the example, control unit404includes a first PID controller, which determines setpoint value for force Fsetpoint as a function of the elements of control deviation e, which indicate the control deviation with respect to position x, y, z. In the example, control unit404includes a second PID controller, which determines setpoint value for torque Tsetpoint as a function of the elements of control deviation e, which indicate the control deviation with respect to angles ϕ, θ, Ψ. The PID controllers are regulators having a proportional, an integrating, and a differentiating component. Other deterministic control units may also be used. An optional filter416may be provided, which filters actual values of pose Pactual before model402or as part of model402. No filter416is preferably used for a training. Model402is designed to determine, as a function of actual value for pose Pactual, setpoint value for torque Tsetpoint, and setpoint value for force Fsetpoint, a setpoint value αsetpoint for the activation of at least one actuator202of conveyor device200. Model402is already trained in one aspect to determine, as a function of setpoint values for poses, setpoint values for torques, and setpoint values for forces, setpoint values for the activation of the at least one actuator202. Further input variables for model402may include historic data of poses or actual values of the at least one actuator202. Model402is designed in another aspect, using training device410, as a function of setpoint values for poses, setpoint values for torques, and setpoint values for forces, to be trained using setpoint values for the activation of the at least one actuator202. Training device410is designed to determine at least one parameter W for model402. In the example, training device410is designed to determine a plurality of parameters W. Training device410is designed in the example to determine parameter W as a function of a cost function, which is defined as a function of a difference between a desired value for force Fdes and a modeled value for force F, on the one hand, and a difference between a desired value for torque Tdes and a modeled value for torque T, on the other hand, for example based on L1 norms. l1=∥Fdes−F∥+∥Tdes−T∥ For example, the cost function is defined by a sum of the L1 norm of the difference between desired value for force Fdes and modeled value for force F, on the one hand, and the L1 norm of the difference between desired value for torque Tdes and the modeled value for torque T, on the other hand. In the example, training device410is designed to determine a plurality of the differences for a plurality of desired values and actual values assigned to one another and to carry out a gradient descent method, using which parameters W are determined which minimize these differences. An aspect of device400for activating conveyor device200is shown inFIG.5. In this aspect, device400includes control unit404, optionally filter416, memory412for model402, and computing device414. Model402is already trained in this aspect. The demand on the computing power of computing device414which is usable for this device400is thus lower than the demand on a computing device414, which computes in a training method using training device410and forward model406. It is advantageous if the training method for training model402is carried out using forward model406in particular to determine the modeled values and training device410and subsequently model402thus trained is used without training device410and without forward model406to activate conveyor device200. Forward model406is used in the training to handle, with a null space, the regulation of six degrees of freedom including 36 actuators in the example. Instead of supervised learning, in which model402learns to determine a setpoint value αsetpoint for rotation angle α for each actuator which corresponds as well as possible to a reference value for setpoint value αsetpoint from the training data, model402is trained in the training method to determine a setpoint value αsetpoint for rotation angle α, for which forward model406determines a modeled value for torque T and a modeled value for force F, which minimize the cost function. The cost function is a function of the modeled value for torque T, the modeled value for force F, desired value for torque Tdes, and desired value for force Fdes. It may be provided that, as schematically shown inFIGS.6A and6B, only one group602of actuators202of conveyor device200are selected from actuators202of conveyor device200and jointly activated by model402. Device400is designed in this case for the purpose of determining group602of actuators202as a function of a present position of device100. Model402is designed in this case to output a setpoint value αsetpoint only for the activation of actuators202of group602of conveyor device200. Two different positions of device100on conveyor device200are shown inFIGS.6A and6B. InFIG.6A, first actuators202of a first group602are shown. InFIG.6B, second actuators202of a second group602are shown. Due to a continuous position change of device100, the two groups602overlap. In the above-described matrix-shaped arrangement of actuators202, second actuators202are determined, for example, in that actuators602of the right side of group602shown inFIG.6Aare removed from first group602, assigned to remaining actuators202of second group602, and one column of actuators are newly added on the left side of second group602shown inFIG.6B. The origin of the Cartesian coordinate system fromFIG.6Ais accordingly shifted to the left forFIG.6B. Control unit404determines continuous values for the shift of the origin on the basis of control deviation e, since setpoint values for poses Psetpoint thus also shift like actual values for poses Factual. Model402determines in this aspect setpoint value αsetpoint only for the activation of actuators202of first group602which are activated for the movement of device100. When device100moves, instead of first group602, second group202is activated. Since the configuration of actuators202of first group602differs from the configuration of actuators202of second group602, a discontinuity may occur upon the transition from first group602to second group602. In the example, actuators202of first group602are situated in a first matrix in which indices of columns and rows in the first matrix define an actual position of actuator202of first group602. For second group602, a second matrix is defined accordingly. Various actuators202, having an inter-actuator distance to one another in columns and rows in this example, are situated in the space in the form of a matrix. An actual pose is defined in the space for first group602. An actual pose shifted in relation to the actual pose is defined in the space for second group602. The discontinuity relates in this example to actuators202, which are substituted in first group602and in second group602when either the index for the column or the index for the row or both indices change due to a shift of device100with respect to conveyor device200. In the training, for each actual position of an actuator202, in each case an actual position shifted by precisely the inter-actuator distance is also given in the training data. The cost function is, for example, additively expanded in this case so that actuator202, which is physically the same, but whose matrix index is changed due to the shifted position, has the same setpoint value αsetpoint assigned in both cases, thus the difference is zero. This is achieved in that for the training a coordinate system for setpoint value for pose Psetpoint and actual value for pose Pactual is defined using an origin. A location of the origin with respect to conveyor device200is determined in this aspect as a function of a movement of device100with respect to conveyor device200. In the example, a spatial position of the origin is determined for first group602with respect to actuators202of first group602. Upon a transition from first group602to second group602, the same location of the origin is determined with respect to actuators202of second group602. In the example, for each of the groups, the same location of the origin is determined in the center of the two-dimensional matrix arrangement of actuators202which are assigned to the particular group. For the training, setpoint value for pose Psetpoint and actual value for pose Pactual are indicated with respect to this origin. Model404thus trained is usable for each of the groups, since for model402, in the event of a change of the location of the origin, no jump of setpoint value αsetpoint and no jump of actual value for pose Pactual occurs. An exemplary additional quality measure for this purpose is defined by setpoint values αsetpoint determined by model402, for example based on an L1 norm, as l2=∥g(αsetpoint)−f(αsetpoint_shifted)∥ g and f being sorting functions, which are defined, for example, by a particular characteristic map which assigns a target value to a setpoint value. For example, the cost function is defined by an L1 norm of a difference of a result vector of sorting function g for setpoint value αsetpoint and a result vector of sorting function f for a shifted setpoint value αsetpoint_shifted. In the example, the setpoint value may be implemented as a vector for the actual pose. The setpoint value is ascertained by resorting the elements of the vector, so that physically the same actuator202receives the same vector index under the shifted actual pose after the resorting for the calculation of the quality measure. Actuators202which are not present in both groups are sorted out by sorting functions g and f. In the training of this model402, for example, an optimization is determined with the aid of the sum of quality measure l1and additional quality measure l2. A method for activating conveyor device200is described hereinafter on the basis ofFIG.7. This method may be carried out using device400, without a database408, a forward model406, and a training device410being required in device400. Rather, this method may be carried out solely using control unit404and trained model402. The method for activating conveyor device200provides that in a step700, an actual value for a pose Pactual of a device100movable by conveyor device200by a magnetic force action is received. Subsequently, a step702is carried out. In step702, control deviation e for control unit404is determined as a function of actual value for pose Pactual and a setpoint value for pose Psetpoint. Setpoint value for pose Psetpoint may be predefined arbitrarily. In the example, setpoint value for pose Psetpoint is predefined in such a way that device100is moved with consistent distance from conveyor device200and following a profile of conveyor device200. Subsequently, a step704is carried out. Control unit404may be the state regulator, in particular the LQ controller. In this case, the trajectory for setpoint values for pose Psetpoint may be predefined In step704, as a function of actual value for pose Pactual and setpoint value for pose Psetpoint, setpoint value for torque Tsetpoint and setpoint value for force Fsetpoint are determined, using which device100is to be moved by conveyor device200. In step704, in the example setpoint value for torque Tsetpoint and setpoint value for force Fsetpoint are determined by control unit404as a function of control deviation e. Subsequently, a step706is carried out. If control unit404is the state regulator, setpoint value for torque Tsetpoint and setpoint value for force Fsetpoint may be determined as a function of the trajectory. It may be provided that as a function of a gravitational force acting on device100, a pilot control value is determined for setpoint value for torque Tsetpoint and/or setpoint value for force Fsetpoint which at least partially compensates for the gravitational force. In step706, as a function of actual value for pose Psetpoint, setpoint value for torque Tsetpoint, and setpoint value for force Fsetpoint, and as a function of model402, a setpoint value αsetpoint is determined for the activation of at least one actuator202of conveyor device200. Model402is trained to determine setpoint values for the activation of the at least one actuator202as a function of setpoint values for poses, setpoint values for torques, and setpoint values for forces. The at least one actuator202is designed to be rotatable with respect to conveyor device200in one aspect. Setpoint value αsetpoint for the at least one actuator202characterizes in this aspect a rotation angle for actuator202with respect to conveyor device200. Subsequently, a step708is carried out. An increment may also be provided for this rotation angle starting from a present rotation angle of actuator202. In step708, the at least one actuator202is activated as a function of setpoint value αsetpoint for the activation of at least one actuator202. If not all actuators202are activated, actuators202which are not activated still generate the same magnetic field. A magnetic force action which moves device100is thus generated by a superposition of the magnetic fields of actuators202in the area in which device100is located. In the example, the at least one actuator202includes a Halbach array, by which the magnetic field for influencing the movement of device100is generatable. In the example, model402is trained to determine a plurality of setpoint values αsetpoint for rotation angles α of various actuators202. In steps706and708, a magnetic field for moving device100is generatable by a superposition of magnetic fields which are generatable by the Halbach array of the plurality of different actuators202. Model402is trained in this example to determine706the plurality of setpoint values αsetpoint for rotation angles α of various actuators202in such a way that the magnetic field moves device100essentially using the torque predefined by setpoint value for torque Tsetpoint and the force predefined by setpoint value for force Fsetpoint. Since a forward model does not have to be determined for this purpose, this procedure is very efficient and therefore requires significantly less computing power and/or computing time in relation to the use of a forward model Steps700through708are carried out repeatedly in this example in this order for a sequence of setpoint values Psetpoint for the pose. Device100is thus moved using conveyor device200. The method subsequently ends. Steps700through708were described for actuators202which include permanent magnets. For actuators202which include an electromagnetic element, a corresponding method is used to generate a magnetic field to move device100. Model402is trained in this case to determine a plurality of setpoint values Isetpoint for various actuators202in step706. Isetpoint denotes in the example a current using which an electromagnetic field is to be generated by the electromagnetic element. A magnetic field for moving device100is generated in this case by a superposition of magnetic fields of a plurality of the electromagnetic elements of various actuators202with a magnetic field of at least one electromagnet or permanent magnet at device100. Model402is trained to determine the plurality of setpoint values Isetpoint for various actuators202in step706in such a way that the magnetic field in step708moves device100essentially using the torque predefined by setpoint value for torque Tsetpoint and the force predefined by setpoint value for force Fsetpoint. In one example, model402includes an artificial neural network, in particular including a multilayer perceptron architecture. A setpoint value αsetpoint is determined, for example, as a function of values of an output layer of the artificial neural network. The artificial neural network is designed in the example for a regression of rotation angles. The output layer, for example, continuously outputs output values as floating-point numbers, the output values continuously defining rotation angles between 0° and 359° within the scope of the accuracy of the floating-point numbers. In this example, the rotation angle for one of actuators202is set as a function of the initial value. For the determination of the plurality of setpoint values αsetpoint for rotation angles α of various actuators202, a number of output layers corresponding to the number of actuators202may be provided in model402. It may be provided that several of actuators202in group602are combined. Model402may include outputs only for actuators202of group602in this case. In this case, a correspondingly modified method is used to activate conveyor device200, which is described hereinafter with reference toFIG.8. In a step800, as a function of actual value for pose Pactual, a plurality of actuators202is assigned to a group602of actuators202. Group602is defined, for example, as a 6×6 matrix of actuators202, which are situated in a top view of conveyor device200in a square area, over which device100is presently held floating by the magnetic forces. The assignment takes place in the example as a function of the position determination. If a plurality of devices100are to be movable by conveyor device200, multiple instances of model402may be provided. Each of the instances of model402is designed in this case to activate conveyor device200to move one of devices100. Preferably, disjoint groups602of actuators202are defined for this purpose and each of groups602is activated by another of models402. In a step802, a particular setpoint value αsetpoint for rotation angle α is determined for the plurality of actuators202of group602. In the example, model402trained for the number of actuators202from group602is used. Particular setpoint value αsetpoint is determined in the example as described in steps700through706. In a step804, the magnetic field for influencing the movement of device100is only generated by a group602of actuators202. Steps800through804are repeated as a function of the information about actual value Pactual of the pose. Different actuators202are thus grouped in various groups602and activated. The method for activating conveyor device200may be used for training model402. For the training of model402, in a step900, training data are provided, in particular from database408. The training data include values from a value range valid for the particular desired value. The training data are either predefined or are drawn in the training from a random distribution. In the example, the training data each include a pose Pactual, a desired value for the torque, and a desired value for the force, which are assigned to one another as a tuple. In the example, one of the tuples is randomly drawn in step900. Subsequently, a step902is carried out. In step902, a setpoint value αsetpoint for the activation of the at least one actuator202of conveyor device200is determined as a function of the tuple drawn. For this purpose, for example, a method as described in step706is used. It may be provided that control unit404is used in the training. In this case, a desired value for the torque and a desired value for the force may be determined as a function of drawn pose Pactual and a setpoint value Psetpoint for the pose contained in the tuple. In the example, the training is independent of whether model402is trained for all or only for a previously selected group602of actuators202. Subsequently, a step904is carried out. In step904, a modeled value for the torque and a modeled value for the force are determined as a function of setpoint value αsetpoint for the activation of the at least one actuator202of conveyor device200, independently of actual value for pose Pactual, and as a function of in particular stochastic or deterministic forward model406for conveyor device200and device100. Depending on model402used, in the example a setpoint value αsetpoint is determined either for all actuators202of the conveyor device or for each actuator202from group602of actuators. Subsequently, a step906is carried out. In step906, the at least one parameter W of model402is determined as a function of a gradient descent method. In the training, it is calculated for the evaluation of this cost function for this gradient descent method by stochastic or deterministic forward model406which modeled value for the torque and which modeled value for the force as a function of setpoint value αsetpoint that model402has determined would be set by conveyor device200. In the training, conveyor device200is not activated, but rather simulated by forward model406. In the training, a very precise forward model406may be used. The operation of conveyor device200after the training may take place without this precise forward model406. Parameters W are, for example, weights and/or parameters of activation functions of the artificial neural network. Parameters W may also relate to other parameters of the artificial neural network. A plurality of pairs of poses Pactual and setpoint values for poses Psetpoint assigned to one another are provided in the example in repetitions of steps902through906. Actual values for torque Tactual and actual values for force Factual are determined as a function of the plurality of pairs and the at least one parameter W of model402is determined as a function of poses Pactual from the plurality of pairs and actual values determined for this purpose for torque Tactual and actual values for force Factual in the gradient descent method. The training is carried out, for example, using the function which is defined as a function of the difference between setpoint value for force Fsetpoint and the actual value for force F, on the one hand, and the difference between setpoint value for torque Tsetpoint and the actual value for torque T, on the other hand. The method ends, for example, when a quality criterion has been met or all provided tuples have been used. The tuples may be provided repeatedly in iterations for training. In this case, the method may then end when a predefined number of iterations has been carried out. | 33,473 |
11942887 | DETAILED DESCRIPTION The following description relates to systems and methods for operating an electric machine. The electric machine may be part of a vehicle, aircraft, or other system.FIG.1shows one example where the system and methods may be included in a vehicle.FIGS.2-3Bshow example system configurations for a dual segmented motor drive. A space vector hexagon that shows how voltages may be supplied to the dual segmented motor drive is shown inFIG.4. The dual segmented motor may be controlled via a field oriented control scheme as shown inFIG.5. Finally, a flowchart of a method for controlling a dual segmented motor drive is shown inFIG.6. While the dual segmented motor drive is described herein, the approach may be applied to other electric machines as well, such as solenoids. FIG.1shows an example vehicle10that includes a dual segmented motor drive106. In this example, the dual segmented motor drive106is applied to operate vehicle steering; however, it may be deployed for other uses including, but not limited to braking actuators, propulsion motors, transmission shifting actuators, and throttle actuators. In this example, vehicle10includes a front side110and a rear side111. Front side110includes front wheels102, which may articulate right and left via shafts102aand102b. Shafts102aand102bmay be moved to the right or left via dual segmented motor drive106. Dual segmented motor drive106includes an electric motor104. Controller15may operate dual segmented motor drive106by sending control signals to activate and deactivate transistors and other electrical components that are included in dual segmented motor drive106. Controller15includes read-only (non-transitory memory)15a, a processor15b, and random access memory15c. Controller15may provide command signals to duel segmented motor drive in response to input received from position sensor108. Position sensor108may be coupled to steering wheel109to sense a position of steering wheel109. Controller15may also receive input from sensors177, which may include electric current sensors, battery voltage sensors, vehicle speed sensors, ambient temperature sensors, etc. Controller15may receive input and provide status information to human/machine interface16. Human/machine interface16may be a touch screen, pushbuttons, or other known human/machine interfaces. In this example, rear wheels103are not steerable, but in other examples positions of rear wheels103may also be adjusted. Lateral, vertical, and longitudinal directions for vehicle10are indicated at175. Turning now toFIG.2, a schematic view of a dual segmented motor drive106is shown. Dual segmented motor drive106includes a first inverter202for transforming direct current into alternating current and a second inverter204for transforming direct current into alternating current. The direct current may be supplied via power source210(e.g., a battery or a battery in combination with an alternator (not shown)). First inverter202and second inverter204may supply three phase electric power to electric machine104(e.g., an electric motor). Alternatively, inverters202and204may provide single phase AC to a single phase electric machine104. Dual segmented motor drive106is shown electrically coupled to positive terminal210bof power source210and negative terminal210aof power source210. Switch or transistor203may selectively couple positive electric power rail220of first inverter202to positive terminal210bof power source210. Similarly, switch or transistor205may selectively couple positive electric power rail224of second inverter204to positive terminal210bof power source210. First inverter202includes a capacitor206to reduce voltage ripple (e.g., changes in voltage level) to a voltage of positive electric power rail220. First inverter202may be comprised of an array of transistors212that includes transistors that are electrically coupled in series and transistors that are electrically coupled in parallel. For example, transistor250is coupled in series with transistor252via conductor253, and conductor253is an output of a first electrical power phase A for first inverter202. Transistor250is also electrically coupled to positive electric power rail220and transistor252is electrically coupled to negative voltage rail222. Transistor254is coupled in series with transistor256via conductor255, and conductor255is an output of a second electrical power phase B for first inverter202. Transistor254is also electrically coupled to positive electric power rail220and transistor256is electrically coupled to negative voltage rail222. Transistor258is coupled in series with transistor260via conductor259, and conductor259is an output of a third electrical power phase C for first inverter202. Transistor258is also electrically coupled to positive electric power rail220and transistor260is electrically coupled to negative voltage rail222. The transistors for electric power phases A, B, and C are arranged in parallel. Second inverter204includes a capacitor208to reduce voltage ripple (e.g., changes in voltage level) to a voltage of positive electric power rail224. Second inverter204may be comprised of an array of transistors214that includes transistors that are electrically coupled in series and transistors that are electrically coupled in parallel. In particular, transistor262is coupled in series with transistor264via conductor263, and conductor263is an output of a first electrical power phase A′ for second inverter204. Transistor262is also electrically coupled to positive electric power rail224and transistor264is electrically coupled to negative voltage rail226. Transistor266is coupled in series with transistor268via conductor267, and conductor267is an output of a second electrical power phase B′ for second inverter204. Transistor266is also electrically coupled to positive electric power rail224and transistor268is electrically coupled to negative voltage rail226. Transistor270is coupled in series with transistor272via conductor271, and conductor271is an output of a third electrical power phase C′ for second inverter204. Transistor270is also electrically coupled to positive electric power rail224and transistor272is electrically coupled to negative voltage rail226. The transistors for electric power phases A′, B′, and C′ are arranged in parallel. The capacitance values of capacitors206and208may be significantly smaller than for a system that provides redundancy via a second motor. This is because the ripple voltage of first inverter202and the ripple voltage of second inverter204may be substantially lower than for systems that supply electric power to a motor via a sole inverter. Electric motor104includes windings that are segmented into two groups, in particular, a first group A, B, C and a second group A′,B′,C′. Windings of the two groups are not electrically coupled together when electric motor104is not coupled to one or more inverters. The first group of windings is electrically coupled to the first inverter202and the second group of windings is electrically coupled to the second inverter204. Windings A, B, and C are electrically coupled together at node280such that windings A, B, and C are arranged in a “Y” configuration. Windings A′, B′, and C′ are electrically coupled together at node282such that windings A′, B′, and C′ are arranged in a “Y” configuration. Windings A and A′ may occupy same slots in an armature of electric machine as shown inFIGS.3A and3B. Similarly, windings B and B′ may occupy same slots in an armature of electric machine as shown inFIGS.3A and3B. Likewise, windings C and C′ may occupy same slots in an armature of electric machine as shown inFIGS.3A and3B. Windings A may receive a first electric power phase from first inverter202via conductor253. Windings B may receive a second electric power phase from first inverter202via conductor255. Windings C may receive a third electric power phase from first inverter202via conductor259. Windings A′ may receive a first electric power phase from second inverter204via conductor263. Windings B′ may receive a second electric power phase from second inverter204via conductor267. Windings C′ may receive a third electric power phase from second inverter204via conductor271. Electric power phase B supplied from inverter202may be 120 electrical degrees out of phase with electric power phase A. Electric power phase C supplied from inverter202may be 120 electrical degrees out of phase with electric power phase B. Electric power phase B′ supplied from inverter204may be 120 electrical degrees out of phase with electric power phase A′. Electric power phase C′ supplied from inverter204may be 120 electrical degrees out of phase with electric power phase B′. Electric power phase A supplied from inverter202may be in phase with electric power phase A′. Electric power phase B supplied from inverter202may be in phase with electric power phase B′. Electric power phase C supplied from inverter202may be in phase with electric power phase C′. Referring now toFIG.3A, a cross section of a stator300for electric motor104is shown. In this example, stator300is configured as a two pole three phase stator. Poles302and304are wrapped by phase windings A and A′. Phase windings A and A′ exit stator300at terminals310and312. Poles332and330are wrapped by phase windings B and B′. Phase windings B and B′ exit stator300at terminals314and316. Poles334and336are wrapped by phase windings C and C′. Phase windings C and C′ exit stator300at terminals318and320. Slots399may be at least partially filled via windings A, A′,B, B′, C, and C′. In this example, the pole pairs are separated by120mechanical degrees, but in other examples, the pole separation may be less than 120 mechanical degrees as shown inFIG.3B. The first segment of windings A, B, and C is tied together at node280. The second segment of windings A′, B′, and C′ is tied together at node282. Thus, phase windings A and A′ may be arranged together so that both the first and second inverters may simultaneously provide electric current to induce rotation of a rotor (not shown) within stator300via common poles. Likewise, phase windings B and B′ may be arranged together to induce rotation of the rotor. Further, phase windings C and C′ may be arranged together to induce rotation of the rotor. Referring now toFIG.3B, a cross section of a portion of an alternative stator350for electric motor104is shown. In this example, stator350includes a plurality of slots355for an increased number of poles. Slots355are shown being wrapped with windings A, A′, B, B′, C, and C′. The slots of stator350are arranged closer together than slots399ofFIG.3Aso that a greater number of poles may be provided. Each of the windings A, A′, B, B′, C, and C′ may occupy two slots (not shown) to provide two poles for each winding. Thus, the system ofFIGS.1-3Bprovides for an electric machine, comprising: a stator; windings for one or more electric power phases wrapping the stator, the windings being segmented into a first half and a second half, windings included in the first half not electrically coupled to windings included in the second half. The electric machine includes where the one or more electric power phases is a single electric power phase. The electric machine includes where the one or more electric power phases is three electric power phases. The electric machine includes where the windings include a winding for a first electric power phase in the first half, a winding for a second electric power phase in the first half, a winding for a third electric power phase in the first half, a winding for a first electric power phase in the second half, a winding for a second electric power phase in the second half, and a winding for a third power phase in the second half. The electric machine includes where the winding for the first electric power phase in the first half is positioned in a first slot of the stator, and where the winding of the first electric power phase in the second half is positioned in the first slot of the stator. The electric machine includes where the winding for the second electric power phase in the first half is positioned in a second slot of the stator, and where the winding of the second electric power phase in the second half is positioned in the second slot of the stator. The electric machine includes where the winding for the third electric power phase in the first half is positioned in a third slot of the stator, and where the winding of the third electric power phase in the second half is positioned in the third slot of the stator. The system ofFIGS.1-3Balso provides for an electric system, comprising: a stator; windings for one or more electric power phases wrapping the stator, the windings being segmented into a first half and a second half, windings included in the first half not electrically coupled to windings included in the second half; a first inverter electrically coupled to the windings included in the first half; and a second inverter electrically coupled to the windings included in the second half. The electric system further comprises a first switch to selectively couple the first inverter to a power source. The electric system further comprises a second switch to selectively couple the second inverter to the power source. The electric system further comprises a controller including executable instructions to operate the first and second inverters to supply electric power to the windings. The electric system further comprises additional instructions to open the first switch in response to an indication of degradation of the electric system. Referring now toFIG.4, a space vector hexagon for the dual segmented motor shown inFIGS.2-3Bis shown. The space vector hexagon is shown having six states (100, 110, 010, 011, 001, and 101) that may have non-zero magnitudes. There are also two states with zero magnitude (000 and 111). The states identify the status of transistors or switches in an inverter. For example, state 100 indicates that transistor250of inverter202is on, transistor254of inverter202is off, and transistor258of inverter202is off. Similarly, state 010 indicates that transistor250of inverter202is off, transistor254of inverter202is on, and transistor258of inverter202is off, and so on. Since electric motor104has segmented windings, state 100 also indicates that transistor262of inverter204is on, transistor266of inverter204is off, and transistor270of inverter204is off. Similarly, state 010 indicates that transistor262of inverter204is off, transistor266of inverter204is on, and transistor270of inverter204is off, and so on. The length of vectors v1 (dashed line) and v2 (solid line) indicate the voltages that may be applied to the terminals of motor104. The inverter switching sequence for the inverter transistors may be controlled to generate voltage vectors of varying magnitude and direction of pulse width modulation periods that may drive the inverters. The switching sequences may provide a continuously rotating space vector. Referring now toFIG.5, a block diagram for one half of a field oriented control scheme500for a dual segmented motor is shown. Field oriented control scheme500may be implemented as executable instructions in non-transitory memory of controller15shown inFIG.1. In this example, inverter202is driven via signals generated by field oriented control scheme500. The field oriented control scheme500adjusts phase commands Va, Vb, and Vc in response to a reference electric machine speed. Field oriented control scheme500includes several proportional/integral controllers that are identified by PI. Signal summing junctions are indicated as502and electric current supplied to electric motor104is sensed via electric current sensors505. Transforms and inverse transforms for converting time domain signals into a rotating reference frame are provided in blocks508,511, and510. Block509may generate pulse width modulation (PWM) signals for commanding inverter202. A position and speed estimate for motor104may be generated via block514. A similar field oriented control scheme may be provided for second inverter204. Referring now toFIG.6, an example method for operating a dual segmented motor is shown. Method600may be at least partially implemented as executable instructions stored in controller memory in the system ofFIG.1. Further, method600may include actions taken in the physical world to transform an operating state of the system ofFIGS.1-3B. At602, method600determines system operating conditions. System operating conditions may include, but are not limited to driver demand torque/power, vehicle speed, steering angle, motor speed, motor position, and ambient temperature. Method600proceeds to604. At604, method600judges if operation of a dual segmented motor is requested. Operation of the dual segmented motor may be requested via a human/machine interface or based on conditions as determined via a controller. If method600judges that operation of the dual segmented motor is requested, the answer is yes and method600proceeds to606. Otherwise, the answer is no and method600proceeds to604. At604, method600deactivates first and second inverters via opening two switches (e.g., switches203and205ofFIG.2). By opening the two switches, electric power may not be delivered to the dual segmented motor (e.g.,104) included in the dual segmented motor drive106. Method600proceeds to exit. At606, method600judges if degradation of a dual segmented motor drive is present. Degradation of the dual segmented motor drive may be present within one or both inverters or within a dual segmented motor. In one example, method600may judge that degradation of the dual segmented motor drive is present if an electrical current is not at an expected level. Thus, if electric current that is delivered to the motor is greater than is expected, method600may judge that the dual segmented motor drive is degraded. In addition, method600may judge that degradation of the dual segmented motor drive is present if less than an expected amount of electric current is supplied to the motor. In still other examples, dual segmented motor drive degradation may be based on other conditions such as but not limited to inverter temperature, motor temperature, and motor speed. The dual segmented motor drive may include a first group of windings and a second group of windings for a motor. If current supplied to one or more phase windings (e.g., A-C or A′-C′) is less than or greater than expected, method600may judge that the inverter and/or windings that are associated with the higher or lower electric current may be degraded. In this way, method600may differentiate which portion of the dual segmented motor drive may be degraded. If method600judges that degradation of the dual segmented motor drive is present, the answer is yes and method600proceeds to612. Otherwise, the answer is no and method600proceeds to608. At612, method600opens a switch that is associated with the windings and/or inverter that is determined to be degraded. For example, if electrical current supplied to winding A is less than expected, then switch203may be opened so that first inverter202and windings A-C may be deactivated. On the other hand, if electrical current supplied to winding C′ is less than expected, then switch205may be opened so that second inverter204and windings A′-C′ may be deactivated. Method600proceeds to614. At614, method600continues to supply electric power to the inverter other than the inverter with the switch that has been opened. By continuing to supply power to the other inverter and windings, the dual segmented motor may continue to rotate, thereby allowing a system to continue to operate. Method600proceeds to616. At616, method600indicates degradation of the inverter or motor that was determined to be receiving less than or greater than an expected amount of current. Method600may provide the indication via a visual or audible means (e.g., a human/machine interface). Method600returns to602. At608, method600activates first and second inverters (e.g.,202and204) via closing two switches (e.g.,203and205) to allow power to flow to the two inverters. Method600proceeds to610. At610, method600delivers three phase electric power to two different sets of windings of a motor. The three phase power may be provided via pulse width modulating signals that operate transistors of first and second inverters via a field oriented control scheme as shown inFIG.5. For example, three phase power may be supplied to phases A, B, and C of a motor via a first inverter. Additionally, three phase power may be supplied to phases A′, B′, and C′ of the motor via a second inverter. The voltage (e.g., magnitude and phase of the voltage) of phase A windings may be aligned with the voltage of phase A′ windings, the voltage of phase B windings may be aligned with the voltage of phase B′ windings, and the voltage of phase C windings may be aligned with the voltage of phase C′ windings. In other examples, where the motor is a single phase motor, single phase electric power may be delivered to single phase windings of a single phase motor via two sets of windings. Thus, the system and method described herein is not limited to three phase systems. Method600returns to602. In this way, redundancy to operation of a motor may be provided without the additional mass of a second motor. Further, system cost and complexity may be reduced. Note that the example control and estimation routines included herein can be used with various powertrain and/or vehicle system configurations. The control methods and routines disclosed herein may be stored as executable instructions in non-transitory memory and may be carried out by the control system including the controller in combination with the various sensors, actuators, and other motor hardware. Further, portions of the methods may be physical actions taken in the real world to change a state of a device. The specific routines described herein may represent one or more of any number of processing strategies such as event-driven, interrupt-driven, multi-tasking, multi-threading, and the like. As such, various actions, operations, and/or functions illustrated may be performed in the sequence illustrated, in parallel, or in some cases omitted. Likewise, the order of processing is not necessarily required to achieve the features and advantages of the example examples described herein, but is provided for ease of illustration and description. One or more of the illustrated actions, operations and/or functions may be repeatedly performed depending on the particular strategy being used. Further, the described actions, operations and/or functions may graphically represent code to be programmed into non-transitory memory of the computer readable storage medium in the motor control system, where the described actions are carried out by executing the instructions in a system including the various motor hardware components in combination with the electronic controller. One or more of the method steps described herein may be omitted if desired. It will be appreciated that the configurations and routines disclosed herein are exemplary in nature, and that these specific examples are not to be considered in a limiting sense, because numerous variations are possible. For example, the above technology can be applied to vehicle systems, manufacturing systems, process systems, and transportation systems that include different types of actuators including different types of motors and actuators. The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various systems and configurations, and other features, functions, and/or properties disclosed herein. The following claims particularly point out certain combinations and sub-combinations regarded as novel and non-obvious. These claims may refer to “an” element or “a first” element or the equivalent thereof. Such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements. Other combinations and sub-combinations of the disclosed features, functions, elements, and/or properties may be claimed through amendment of the present claims or through presentation of new claims in this or a related application. Such claims, whether broader, narrower, equal, or different in scope to the original claims, also are regarded as included within the subject matter of the present disclosure. | 24,611 |
11942888 | DETAILED DESCRIPTION The present disclosure is described below in detail in conjunction with drawings and examples. It is to be understood that the examples described herein are intended to illustrate and not to limit the present disclosure. Additionally, it is to be noted that for ease of description, merely part, not all, of the structures related to the present disclosure are illustrated in the drawings. It is to be noted that a capacitor control method in the present application is applicable to multiple types of power tools such as a lawn mower, a riding lawn mower, and a snow thrower. The snow thrower is used as an example for illustration. Referring toFIG.1, a power tool100includes walking wheels101, a main body102, and a handle device103. An operation member is disposed on the handle device103and configured to control the snow thrower to walk. The handle device103is detachably connected to the main body102. Referring toFIG.2which is a circuit diagram of the power tool, a power interface10, a driver circuit20, a controller30, a motor40, a capacitor50, a capacitor switch60, and a temperature detection unit70may be included. The power interface10is configured to be connected to a power supply so as to supply electricity to the power tool. In an example, the power supply connected to the power interface may be alternating current mains. In an example, the power supply connected to the power interface10may also be a battery pack. The battery pack may be composed of a group of battery units. For example, the battery units may be connected in series as a single power supply branch to form a1P battery pack. Of course, the battery pack may be composed of two or more groups of battery units. The driver circuit20is connected between the controller30and the motor40and has multiple semiconductor switching elements for switching an energized state of the motor. The type of the motor40is not limited in the present application. In an example, the driver circuit20is electrically connected to a stator winding of each phase of the motor40so as to transfer a current of the power supply to the stator winding to drive the motor to rotate. In an example, the driver circuit20may include multiple switching elements. Each gate terminal of the switching elements is electrically connected to the controller30and configured to receive a control signal from the controller30. Each drain or source of the switching elements is connected to the stator winding of the motor40. Each of the switching elements receives the control signal from the controller30to change a respective on or off state, thereby changing a current applied by the power supply to the stator winding of the motor40. In an example, the switching elements in the driver circuit20may be a three-phase bridge driver circuit which includes six controllable semiconductor power devices (for example, field-effect transistors (FETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), or the like) or any other type of solid state switch, for example, an IGBT, a BJT, or the like. To rotate the motor40, the driver circuit20has multiple driving states. In one driving state, the stator winding of the motor40generates one magnetic field. The controller30outputs a corresponding control signal to the switching element in the driver circuit20according to a rotor position or a counter-electromotive force of the motor such that the driver circuit20switches a driving state. Therefore, the stator winding generates a changing magnetic field to drive a rotor to rotate, implementing the rotation or commutation of the motor40. It is to be noted that any other circuit and control manner which can drive the motor40to rotate or commutate may be used in the present disclosure. A circuit structure of the driver circuit20and the control of the driver circuit20by the controller30are not limited in the present disclosure. The capacitor50can filter out current spikes in the power supply to avoid an impact on the motor and prevent the working performance of the tool from being affected. In the present application, the capacitor50may be an electrolytic capacitor or an ordinary capacitor. Since a low-temperature capacitor has a small decay in capacity at a very low temperature, the low-temperature capacitor can work normally at a low temperature. However, a normal-temperature capacitor has a large decay in capacity at a very low temperature, thereby affecting the performance of a control system. In general, only a specific power tool used in winter (such as a snow thrower) uses the low-temperature capacitor, and a general power tool used in all seasons uses only the normal-temperature capacitor. Therefore, for a power tool (such as the lawn mower) used at a normal temperature and sometimes used at a low temperature, the performance of the control system may be affected because a capacitor in a control circuit has a rapid decay in capacity at a low temperature. For example, the motor cannot be started or cannot work normally after being started. The capacitor switch60is connected to the capacitor50and configured to control a working state of the capacitor. Optionally, the capacitor switch60may be a controllable semiconductor power device such as a FET, a BJT, or an IGBT or any other type of solid state switch such as the IGBT or the BJT. The temperature detection unit70is configured to detect a temperature of a related object and transmit the temperature to the controller30so that the controller30can control an on or off state of the capacitor switch60accordingly. In an example, the related object may be the capacitor, the motor, or a working environment in which the tool is currently located. That is, the temperature detection unit may detect a temperature of the capacitor, a temperature of the motor, or a temperature of the working environment of the tool or may simultaneously detect the temperatures of one or more of the capacitor, the motor, or the working environment of the tool. In the present application, the temperature detection unit70may be a patch sensor such as a chip resistor which is attached to the capacitor and configured to detect the temperature or may be any other component capable of detecting the temperature. In the present application, the temperature detection unit70is disposed so that the working state of the capacitor50is controlled in conjunction with the capacitor switch60, which can prevent the working performance of the capacitor from being affected at the low temperature. In a specific implementation, the controller30may acquire the temperature of the capacitor detected by the temperature detection unit70. When the temperature is lower than a temperature threshold, the controller30controls the capacitor switch to be in a first on or off state such that the capacitor works in a first working state. When the preceding temperature is higher than the temperature threshold, the controller30controls the capacitor switch to be in a second on or off state such that the capacitor works in a second working state. For example, the preceding temperature threshold may be a specific temperature value such as −30° C. or may be a temperature range such as a range between −25° C. and −35° C. If the temperature threshold is the temperature range, the controller30may control the capacitor switch60to be in the first on or off state when the detected temperature is lower than a minimum value in the temperature range and control the capacitor switch60to be in the second on or off state when the temperature is higher than a maximum value in the temperature range. It is to be understood that the magnitude or range of the preceding temperature threshold may be defined according to actual requirements. It is to be noted that the first working state of the capacitor50is a working state at the low temperature, and the second working state of the capacitor50is a working state at the normal temperature. No absolute boundary exists for defining the preceding normal and low temperatures. For example, the normal temperature may be from −40° C. to 105° C., and the low temperature may be from −55° C. to 85° C. That is, the lowest temperature of the normal temperature is higher than the lowest temperature of the low temperature, and the highest temperature of the normal temperature is higher than the highest temperature of the low temperature. The normal temperature and the low temperature herein are defined according to an ambient temperature that can be accepted by the capacitor that works normally and are not defined in a normal sense. It is to be noted that a lowest effective use temperature of the capacitor50in the first working state is lower than a lowest effective use temperature of the capacitor50in the second working state. In an example, the capacitor switch is controlled such that the capacitor has different working states to adapt to a change from a high temperature to the low temperature. Thus, the power tool is provided which is free from an effect of the ambient temperature and has stable working performance. In an example, as shown inFIG.3, the capacitor50includes a first capacitor501and a second capacitor502. The first capacitor501is connected to a first switch601, and the second capacitor502is connected to a second switch602. That is, working states of the two capacitors are controlled by two switches, respectively. In this example, when the detected temperature is lower than the temperature threshold, the controller30controls the first switch601to be turned on such that the first capacitor501is in a working state and controls the second switch602to be turned off such that the second capacitor502is in a non-working state. When the temperature is higher than the temperature threshold, the first switch601is turned off such that the first capacitor501is in the non-working state and the second switch602is turned on such that the second capacitor502is in the working state. It is to be noted that the first capacitor501is the low-temperature capacitor, can work at the low temperature, and will not have a large decay in capacity even if the ambient temperature is very low so that the working performance of the tool is not affected; the second capacitor502is the normal-temperature capacitor, can work normally at the normal temperature, and will be affected by the low temperature to greatly decay in capacity so that the performance of the tool is affected. It is to be understood that in a circuit shown inFIG.3, the temperature detection unit70can simultaneously detect the temperature of the first capacitor501and the temperature of the second capacitor502, and the controller30controls the working state of the first capacitor501according to the temperature of the first capacitor501and controls the working state of the second capacitor502according to the temperature of the second capacitor502; alternatively, the controller30may control the working states of the two capacitors separately by integrating the temperatures of the two capacitors. Alternatively, two temperature acquisition modules may be used to collect the temperatures of the two capacitors respectively and transmit the temperatures to the controller. In this example, the low-temperature capacitor and a high-temperature capacitor and corresponding control switches are respectively disposed, and a capacitor to be switched to is selected according to the temperature of the capacitor so that the tool adaptively adjusts the capacitors in a simple and direct control manner when working at different temperatures, ensuring the stable working performance of the tool. In an example, a control circuit shown inFIG.4is different from the control circuit shown inFIG.3in that the second switch602does not exist. That is, the second capacitor502is always in the working state no matter what the current temperature is. In a specific implementation, when the detected temperature is lower than the temperature threshold, the controller30controls the first switch601to be turned on such that the first capacitor501is in the working state. In this example, the second capacitor502, which is the normal-temperature capacitor, is configured to be in the working state; and merely the working state of the low-temperature capacitor, the first capacitor501, is controlled. On the basis that the original circuit is changed as little as possible, the capacitor to be switched to can be selected according to the temperature of the capacitor by simply adding the second capacitor and the control switch so that the tool adaptively adjusts the capacitors when working at different temperatures, ensuring the stable working performance of the tool. In an example of the present application, no additional capacitor is required, and the capacitor can be controlled by the control circuit shown inFIG.5to adapt to a change between different temperatures so that the power tool adapts to a change of the ambient temperature. Specifically, the capacitor switch60includes a third switch603and a fourth switch604; the third switch603is connected between the power supply and the capacitor50and configured to control a charging state of the capacitor; and the fourth switch604is connected in parallel to the capacitor50and is configured to control a discharging state of the capacitor50. In a specific implementation, when the detected temperature is lower than the temperature threshold, the controller30may control the third switch603and the fourth switch604to be in complementary on or off states at a certain frequency. The so-called complementary on or off states refer to that the fourth switch604is turned off while the third switch603is turned on and that the third switch603is turned off while the fourth switch604is turned on. In the preceding manner, the capacitor can be charged and discharged at a certain frequency, thereby gradually increasing the temperature of the capacitor. Further, when the temperature of the capacitor is higher than the temperature threshold, the controller30controls the third switch603to be turned on and the fourth switch604to be turned off to make the capacitor work normally. In this example, no additional capacitor is required and merely two control switches together with a simple control manner can increase the temperature of the capacitor itself, that is, an ambient temperature at which the capacitor works, thereby fundamentally avoiding a significant decrease in performance when the capacitor works at the low temperature and ensuring the stable working performance of the power tool. In an example of the present application, the first capacitor has a lowest effective use temperature lower than a lowest effective use temperature of the second capacitor. The lowest effective use temperature refers to a lowest ambient temperature at which the capacitor works normally without a significant decay in capacity. That is, the low-temperature capacitor may work at a lower ambient temperature and maintain a relatively small decay in capacity. However, while maintaining a relatively small decay in capacity, the normal-temperature capacitor works at a temperature higher than the lowest temperature at which the low-temperature capacitor normally works. A control method of a power tool is described below in conjunction withFIG.6. The method includes steps described below. In S101, a temperature of a capacitor is acquired. In this example, the preceding capacitor includes a first capacitor and a second capacitor, that is, a normal-temperature capacitor and a low-temperature capacitor. The first capacitor is connected to a first switch, the second capacitor is connected to a second switch, and the two switches are respectively configured to control working states of the corresponding capacitors. It is to be understood that when a switch is turned on, a capacitor connected to the switch is in a working state, and when the switch is turned off, the capacitor connected to the switch is in a non-working state. In S102, when the temperature is lower than a temperature threshold, the first switch is controlled to be turned on and the second switch is controlled to be turned off. In S103, when the temperature is higher than the temperature threshold, the first switch is controlled to be turned off and the second switch is controlled to be turned on. Another control method of a power tool is described below in conjunction withFIG.7. The method includes steps described below. In S201, a temperature of a capacitor is acquired. In this example, the capacitor refers to merely a normal-temperature capacitor. However, the capacitor is connected to two control switches. That is, a third switch is connected between a power supply and the capacitor and configured to control a charging state of the capacitor; and a fourth switch is connected in parallel to the capacitor and configured to control a discharging state of the capacitor. In S202, when the temperature is lower than a temperature threshold, the third switch and the fourth switch are controlled to be in complementary on or off states at a certain frequency. The complementary on or off states refer to that the fourth switch is turned off while the third switch is turned on and that the fourth switch is turned on while the third switch is turned off. In S203, when the temperature is higher than the temperature threshold, the third switch is controlled to be turned on and the fourth switch is controlled to be turned off. It is to be noted that the above are merely preferred examples of the present disclosure and the technical principles used therein. It should be understood by those skilled in the art that the present disclosure is not limited to the examples described herein. Those skilled in the art can make various apparent changes, adaptations, and substitutions without departing from the scope of the present disclosure. Therefore, although the present disclosure has been described in detail through the preceding examples, the present disclosure is not limited to the preceding examples and may include more other equivalent examples without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claim. | 18,342 |
11942889 | DESCRIPTION OF EMBODIMENTS Comparative Example Before describing the present embodiment, a comparative example for comparison with the present embodiment will be described with reference toFIGS.1and2. FIG.1is a configuration diagram of a motor control device in a case where the present embodiment is not applied. This motor control device is used by being mounted on a vehicle that is a hybrid electric vehicle. As a secondary battery101, a nickel hydrogen secondary battery, a lithium ion secondary battery, or the like is used. The secondary battery101calculates an available current limit DC_LMT1from a temperature and a remaining capacity. A DC current sensor113detects a DC current IDC1of an inverter104to be described later. Further, the secondary battery101has a built-in DC voltage sensor and detects a DC voltage HVDC output from the secondary battery101. The current limit DC_LMT1, the detected DC current DC1, and the DC voltage HVDC are input to a torque limit calculation unit116to be described later. The contactor102is arranged between the secondary battery101and the inverter104. When the contactor102is turned off, the secondary battery101and the inverter104are electrically cut off. When the contactor102is turned on, the secondary battery101and the inverter104are electrically connected, and the power of the secondary battery101is supplied to the inverter104. A smoothing capacitor103smoothens an input voltage of the inverter104. The inverter104is connected to the smoothing capacitor103on a DC side and is connected to a stator of a motor106on a three-phase AC side. The inverter104uses a switching element to convert a DC voltage and an AC voltage to each other. A phase current detector105is connected to UVW phases between an AC side of the inverter104and the motor106to detect U-phase, V-phase, and W-phase currents. The motor106generates torque according to the U-phase, V-phase, and W-phase currents output from the inverter104in response to acceleration and deceleration of the vehicle or a torque command for cranking. The torque generated by the motor106is used for cranking an engine109and acceleration and regeneration assistance of the vehicle. An angle sensor107detects a rotor angle of the motor106and calculates a motor speed SPD. The angle sensor107is, for example, a resolver or the like. A clutch108is arranged between the motor106and the engine109. The motor106and the engine109are mechanically cut off when the clutch108is turned off, and the motor106and the engine109are mechanically connected when the clutch108is turned on. When the clutch108is turned on after an ignition key is turned on or when an accelerator operates, the motor106cranks the engine109. The engine109generates a driving force that causes the vehicle to travel. The torque limit calculation unit116calculates a torque limit TQ_LMT1based on the current limit DC_LMT1from the secondary battery101, the DC current DC1detected by the DC current sensor113, the U-phase, V-phase, and W-phase currents output from the inverter104, and a rotation speed of the motor106. The vehicle controller110is a host controller that transmits a torque command value TQ1for acceleration and deceleration or cranking. The vehicle controller110calculates the torque command value TQ1with the torque limit TQ_LMT1received from the torque limit calculation unit116as an upper limit. The current command calculation unit111calculates a current command and a current phase command based on the torque command value TQ1. The current control unit112generates a PWM signal based on the current command, the current phase command, detection values of the U-phase, V-phase, and W-phase currents, and motor rotor angle information. FIGS.2(A)to (C) are graphs illustrating characteristics of the motor control device in the case where the present embodiment is not applied.FIG.2(A)illustrates the torque of the motor,FIG.2(B)illustrates the DC current DC1,FIG.2(C)illustrates the rotation speed of the motor, and all horizontal axes represent the elapsed time. As described above with reference toFIG.1, the secondary battery101calculates the available current limit DC_LMT1from the temperature and the remaining capacity. The torque limit calculation unit116calculates the torque limit TQ_LMT1based on the current limit DC_LMT1. Here, when required torque TQ_COM determined based on accelerator opening information by a driver reaches the torque limit TQ_LMT1as illustrated inFIG.2(A), the following problems are likely to occur. First, the DC current DC1overshoots beyond the current limit DC_LMT1as illustrated inFIG.2(B). Second, even if the required torque TQ_COM reaches the torque limit TQ_LMT1, the DC current DC1becomes less than the current limit DC_LMT1(over-limitation of DC current) with the passage of time as illustrated inFIG.2(B)so that it is difficult to fully utilize the output of the motor106. According to the present embodiment described below, even if the required torque TQ_COM reaches the torque limit TQ_LMT1, the DC current DC1does not exceed the current limit DC_LMT1, and then, the DC current DC1approaches the current limit DC_LMT1so that the output of the motor106can be fully utilized. Embodiment FIG.3is a configuration diagram of a motor control device according to the present embodiment. The same parts as those in the comparative example illustrated inFIG.1will be denoted by the same reference signs, and the description thereof will be omitted. This motor control device is also used by being mounted on a vehicle that is a hybrid electric vehicle similarly to the comparative example. In the present embodiment, a first torque calculation unit114, a second torque calculation unit115, and a torque limit correction unit117are newly provided. The first torque calculation unit114receives inputs of a current limit DC_LMT1from a secondary battery101, a DC current IDC1from a DC current sensor113, U-phase, V-phase, and W-phase currents from a phase current detector105, and a motor speed SPD from an angle sensor107. The first torque calculation unit114calculates first torque TQ_DC currently generated by a motor106based on the DC current DC1using a calculation method similar to a torque limit calculation unit116, which will be described later, and outputs the first torque TQ_DC to the torque limit correction unit117. The second torque calculation unit115receives inputs of the current limit DC_LMT1from the secondary battery101, the U-phase, V-phase, and W-phase currents from the phase current detector105, and the motor speed SPD from the angle sensor107. The second torque calculation unit115calculates second torque TQ_UVW currently generated by the motor106based on the U-phase, V-phase, and W-phase currents, and outputs the second torque TQ_UVW to the torque limit correction unit117. The torque limit calculation unit116uses a torque limit characteristic map of “current limit and torque limit” measured in advance to calculate a torque limit TQ_LMT1based on the current limit DC_LMT1as will be described later. The torque limit correction unit117receives inputs of the current limit DC_LMT1from the secondary battery101, the DC current DC1from the DC current sensor113, the first torque TQ_DC from the first torque calculation unit114, and the second torque TQ_UVW from the second torque calculation unit115. The torque limit correction unit117compares the first torque TQ_DC from the first torque calculation unit114with the second torque TQ_UVW from the second torque calculation unit115to calculate a variation degree KP1of the first torque calculation unit114. Then, the torque limit correction unit117corrects the torque limit TQ_LMT1using the variation degree KP1and calculates a torque limit TQ_LMT2. Next, details of the torque limit calculation unit116will be described.FIGS.4(A) and4(B)illustrate Example 1 of the torque limit calculation unit116,FIGS.5(A) and5(B)illustrate Example 2 of the torque limit calculation unit116, andFIGS.6(A) and6(B)illustrate Example 3 of the torque limit calculation unit116. The torque limit calculation unit116may have any of configurations of Examples 1 to 3. Example 1 of the torque limit calculation unit116will be described with reference toFIGS.4(A) and4(B).FIG.4(A)is a view illustrating the configuration of Example 1 of the torque limit calculation unit116.FIG.4(B)is a view illustrating a torque limit characteristic map401in Example 1 of the torque limit calculation unit116. InFIG.4(A), the current limit DC_LMT1is an available DC limit value calculated from a temperature and a remaining capacity of the secondary battery101. A voltage HVDC is a voltage from a DC voltage sensor of the secondary battery101. The motor rotation speed SPD is a rotation speed of the motor calculated from the angle sensor107. The torque limit characteristic map401illustrated inFIG.4(B)is a map illustrating the relationship between the “current limit and torque limit” measured in an experiment. As illustrated inFIG.4(B), an x axis represents the current limit DC_LMT1, a y axis represents the torque limit TQ_LMT1, and a z axis represents the voltage HVDC. Note that a graph on the z axis is omitted, but the relationship between the current limit DC_LMT1on the x axis and the torque limit TQ_LMT1on the y axis illustrated inFIG.4(B)is defined according to the motor rotation speed SPD (rotation speeds a, b, and so on) for each value of the voltage HVDC. The torque limit calculation unit116can obtain a specific torque limit TQ_LMT1from the y axis for a specific motor rotation speed SPD when a value on the z axis is determined according to the voltage HVDC and the current limit DC_LMT1is input to the x axis. Example 2 of the torque limit calculation unit116will be described with reference toFIGS.5(A) and5(B).FIG.5(A)is a view illustrating the configuration of Example 2 of the torque limit calculation unit116.FIG.5(B)is a view illustrating a system loss characteristic map505of “torque limit and system loss”. The torque limit calculation unit116multiplies the current limit DC_LMT1and the voltage HVDC using a multiplier501, subtracts a system loss from a result of the multiplication using a subtractor502, and divides a result of the subtraction by the motor rotation speed SPD using a divider503, thereby obtaining the torque limit TQ_LMT1. The system loss is obtained using the system loss characteristic map505of the “torque limit and system loss” illustrated inFIG.5(B). InFIG.5(B), an x axis represents the torque limit TQ_LMT1, a y axis represents the system loss, and a z axis represents the voltage HVDC. Note that a graph on the z axis is omitted, but the relationship between the torque limit TQ_LMT1on the x axis and the system loss on the y axis illustrated inFIG.5(B)is defined according to the motor rotation speed SPD (rotation speed a, b, and so on) for each value of the voltage HVDC. When a value on the z axis is determined according to the voltage HVDC and the previously calculated torque limit TQ_LMT1is input to the x-axis, it is possible to obtain a specific system loss from the y axis for a specific motor rotation speed SPD. Example 3 of the torque limit calculation unit116will be described with reference toFIGS.6(A) and6(B).FIG.6(A)is a view illustrating the configuration of Example 3 of the torque limit calculation unit116.FIG.6(B)is a view illustrating a system efficiency characteristic map605of “torque limit and system efficiency”. The torque limit calculation unit116multiplies the current limit DC_LMT1, the voltage HVDC, and the system efficiency using a multiplier601, and divides a result of the multiplication by the motor rotation speed SPD using a divider602, thereby obtaining the torque limit TQ_LMT1. The system efficiency is obtained using a system efficiency characteristic map605of “torque limit and system efficiency” illustrated inFIG.6(B). InFIG.6(B), an x axis represents the torque limit TQ_LMT1, a y axis represents the system efficiency, and a z axis represents the voltage HVDC. Note that a graph on the z axis is omitted, but the relationship between the torque limit TQ_LMT1on the x axis and the system efficiency on the y axis illustrated inFIG.6(B)is defined according to the motor rotation speed SPD (rotation speed a, b, and so on) for each value of the voltage HVDC. When a value on the z axis is determined according to the voltage HVDC and the previously calculated torque limit TQ_LMT1is input to the x-axis, it is possible to obtain a specific system efficiency from the y axis for a specific motor rotation speed SPD. Next, the first torque calculation unit114will be described.FIG.7(A)illustrates Example 1 of the first torque calculation unit114,FIG.7(B)illustrates Example 2 of the first torque calculation unit114, andFIG.7(C)illustrates Example 3 of the first torque calculation unit114. The first torque calculation unit114may have any of configurations of Examples 1 to 3. Example 1 of the first torque calculation unit114will be described with reference toFIG.7(A).FIG.7(A)is a view illustrating the configuration of Example 1 of the first torque calculation unit114. InFIG.7(A), the DC current DC1is a current value detected by the DC current sensor113and is a current value input to an inverter104. A voltage HVDC is a voltage from a DC voltage sensor of the secondary battery101. The motor rotation speed SPD is a rotation speed of the motor calculated from the angle sensor107. A first torque characteristic map701is not illustrated, but is similar to the torque limit characteristic map401illustrated inFIG.4(B). That is, the current limit of the torque limit characteristic map401illustrated inFIG.4(B)is replaced with the DC current DC1in the first torque characteristic map701of this example. Further, the torque limit of the torque limit characteristic map401illustrated inFIG.4(B)is replaced with the first torque TQ_DC. Then, the first torque characteristic map701illustrating the relationship between the “DC current DC1and first torque” measured in an experiment is set in advance. As a result, the first torque calculation unit114can obtain specific first torque TQ_DC from the y axis for a specific motor rotation speed SPD when the value on the z axis is determined according to the voltage HVDC and the DC current DC1is input to the x axis. Example 2 of the first torque calculation unit114will be described with reference toFIG.7(B).FIG.7(B)is a view illustrating the configuration of Example 2 of the first torque calculation unit114. The configuration of Example 2 of the first torque calculation unit114is similar to that of the torque limit calculation unit116illustrated inFIGS.5(A) and5(B). Although the current limit DC_LMT1is used in Example 2 of the torque limit calculation unit116, but the DC current DC1is used instead of the current limit DC_LMT1in this example, which is a difference. The first torque calculation unit114multiplies the DC current DC1and the voltage HVDC using a multiplier702, subtracts a system loss from a result of the multiplication using a subtractor703, and divides a result of the subtraction by the motor rotation speed SPD using a divider704, thereby obtaining the first torque TQ_DC. The system loss is obtained by using a system loss characteristic map of “first torque and system loss” in which the torque limit on the x axis illustrated inFIG.5(B)is replaced with the first torque TQ_DC. Example 3 of the first torque calculation unit114will be described with reference toFIG.7(C).FIG.7(C)is a view illustrating the configuration of Example 3 of the first torque calculation unit114. The configuration of Example 3 of the first torque calculation unit114is similar to that of the torque limit calculation unit116illustrated inFIGS.6(A) and6(B). Although the current limit DC_LMT1is used in Example 3 of the torque limit calculation unit116, but the DC current DC1is used instead of the current limit DC_LMT1in this example, which is a difference. The first torque calculation unit114multiplies the DC current DC1, the voltage HVDC, and the system efficiency using a multiplier705, and divides a result of the multiplication by the motor rotation speed SPD using the divider704, thereby obtaining the first torque TQ_DC. The system efficiency is obtained by using a system efficiency characteristic map of “first torque and system efficiency” in which the torque limit on the x axis illustrated inFIG.6(B)is replaced with the first torque TQ_DC. Next, the second torque calculation unit115will be described.FIG.8(A)is a view illustrating a configuration of the second torque calculation unit115, andFIG.8(B)is a view illustrating a second torque characteristic map801. InFIG.8(A), U-phase, V-phase, and W-phase currents are currents detected from the phase current detector105connected to UVW phases between an AC side of the inverter104and the motor106. A voltage HVDC is a voltage from a DC voltage sensor of the secondary battery101. The motor rotation speed SPD is a rotation speed of the motor calculated from the angle sensor107. The second torque characteristic map801illustrated inFIG.8(B)is a map illustrating the relationship between the “U-phase, V-phase, and W-phase currents and second torque” measured in an experiment. As illustrated inFIG.8(B), an x axis represents the U-phase, V-phase, and W-phase currents, a y axis represents the second torque TQ_UVW, and a z axis represents the voltage HVDC. Note that a graph on the z axis is omitted, but the relationship between the U-phase, V-phase, and W-phase currents on the x axis and the second torque TQ_UVW on the y axis illustrated inFIG.8(B)is defined according to the motor rotation speed SPD (rotation speed a, b, and so on) for each value of the voltage HVDC. The second torque calculation unit115can obtain specific second torque TQ_UVW from the y axis for a specific motor rotation speed SPD when the value on the z axis is determined according to the voltage HVDC and the U-phase, V-phase, and W-phase currents are input to the x axis. Note that the second torque TQ_UVW may be obtained by a torque equation expressed in the following Formula (1). [Formula 1] T−Pn·{Φ·Ia·cos β+(Ld−Lq)·Ia2·sin 2β} (1) Here, Φ is an interlinkage magnetic flux, Pn is the number of pole pairs, Ld and Lq are inductances of the motor106, Ia is the U-phase, V-phase, and W-phase currents, and β is a current phase angle. The current phase angle is a phase angle of the motor106calculated from the angle sensor107. The interlinkage magnetic flux, the number of pole pairs, and the inductance are default parameters of the motor106. The torque limit correction unit117receives input of the torque limit TQ_LMT1from the torque limit calculation unit116, the first torque TQ_DC from the first torque calculation unit114, and the second torque TQ_UVW from the second torque calculation unit115. The torque limit correction unit117compares the first torque TQ_DC with the second torque TQ_UVW to estimate a variation degree of a product. The variation degree is calculated from the following Formula (2). The torque limit TQ_LMT1is corrected using this variation degree, and the corrected torque limit TQ_LMT2is calculated by the following Formula (3). Variation degree=Second torque TQ_UVW/First torque TQ_DC (2) torque limit TQ_LMT2=torque limit TQ_LMT1×Variation degree (3) Note that it is necessary to set calculation cycles of the first torque calculation unit114, the second torque calculation unit115, and the torque limit correction unit117to be sufficiently fast in order to ensure the responsiveness of the torque correction operation. There is a detection delay in the DC current DC1required to obtain the first torque TQ_DC or the U-phase, V-phase, and W-phase currents required to obtain the second torque TQ_UVW. Further, there is also a calculation delay in the first torque calculation unit114and the second torque calculation unit115. Therefore, it is necessary to perform appropriate synchronization by Formula (2) and Formula (3) according to the variation degree. A vehicle controller110is a host controller that transmits required torque TQ_COM for acceleration and deceleration or cranking. The vehicle controller110calculates the required torque TQ_COM with the torque limit TQ_LMT2received from the torque limit correction unit117as a limit, and outputs the required torque TQ_COM to the current command calculation unit111. FIGS.9(A) to9(C)are graphs illustrating characteristics of the motor control device according to the present embodiment.FIG.9(A)illustrates the torque of the motor,FIG.9(B)illustrates the DC current DC1,FIG.9(C)illustrates the rotation speed of the motor, and all horizontal axes represent the elapsed time. As illustrated inFIG.3, the secondary battery101calculates the available current limit DC_LMT1from a temperature and a remaining capacity. The torque limit calculation unit116calculates the torque limit TQ_LMT1based on the current limit DC_LMT1and the like. Here, as illustrated inFIG.9(A), the required torque TQ_COM determined based on accelerator opening information by a driver reaches the torque limit TQ_LMT2. At this time, the DC current DC1does not overshoot beyond the current limit DC_LMT1, the torque limit TQ_LMT2does not change suddenly, either, and the DC current can approach the current limit DC_LMT1. As a result, the output of the motor can be fully utilized. FIGS.10(A) to10(E)are graphs illustrating detailed characteristics of the motor control device according to the present embodiment.FIG.10(A)illustrates the torque of the motor,FIG.10(B)illustrates the DC current DC1,FIG.10(C)illustrates the torque,FIG.10(D)illustrates the variation degree,FIG.10(E)illustrates the rotation speed of the motor, and all horizontal axes represent the elapsed time. The torque limit TQ_LMT1illustrated inFIG.10(A)is a torque limit calculated based on the current limit DC_LMT1and using the torque limit characteristic map401of the “current limit and torque limit”. The torque limit TQ_LMT2is a torque limit obtained by correcting the torque limit TQ_LMT1using the variation degree KP1. The required torque TQ_COM is required torque determined based on the accelerator opening information by the driver, and is limited to the torque limit TQ_LMT2. The current limit DC_LMT1illustrated inFIG.10(B)is an available DC limit value calculated from a temperature and a remaining capacity of the secondary battery101. The DC current DC1is a detection value or an estimation value of a current input to the inverter104. As illustrated inFIG.10(B), the DC current DC1does not overshoot beyond the current limit DC_LMT1. The first torque TQ_DC illustrated inFIG.10(C)is drive torque of the motor estimated based on the DC current DC1using the first torque characteristic map701of the “DC current DC1and first torque” and the like. The second torque TQ_UVW is drive torque of the motor estimated based on the U-phase, V-phase, and W-phase currents flowing through the motor using the second torque characteristic map801of the “U-phase, V-phase, and W-phase currents and second torque” and the like. Since the second torque TQ_UVW has passed through the inverter104, the torque becomes lower than the first torque TQ_DC due to the loss. The variation degree KP1illustrated inFIG.10(D)represents a variation degree of a product estimated by comparing the second torque TQ_UVW and the first torque TQ_DC. The motor rotation speed SPD illustrated inFIG.10(E)is a rotation speed of the motor calculated from the angle sensor107. Next, an additional function of the torque limit correction unit117will be described with reference toFIGS.11(A) to11(F). The DC current DC1or the U-phase, V-phase, and W-phase currents has the detection delay, and the first torque calculation unit114and the second torque calculation unit115have the calculation delay, and thus, there is a possibility that the responsiveness of the torque limit correction by the torque limit correction unit117deteriorates. Alternatively, when the vehicle accelerates suddenly and there is not enough time for the torque limit correction, the DC current DC1is likely to exceed the current limit DC_LMT1within a short period of time. Therefore, when the DC current DC1exceeds the current limit DC_LMT1, the torque limit correction unit117lowers the corrected torque limit TQ_LMT2by current feedback control to calculate a final torque limit TQ_LMT2′. FIGS.11(A) to11(F)are graphs illustrating detailed characteristics of the motor control device when the additional function is added to the torque limit correction unit117.FIG.11(A)illustrates the torque of the motor,FIG.11(B)illustrates the DC current DC1,FIG.11(C)illustrates the torque,FIG.11(D)illustrates the variation degree,FIG.11(E)illustrates feedback torque TQ_FB1,FIG.11(F)illustrates the rotation speed of the motor, and all horizontal axes represent the elapsed time. As illustrated inFIG.11(A), the torque limit TQ_LMT1is a torque limit calculated based on the current limit DC_LMT1and using the torque limit characteristic map401of the “current limit and torque limit”. The torque limit TQ_LMT2is a torque limit obtained by correcting the torque limit TQ_LMT1using the variation degree KP1. The torque limit TQ_LMT2′ is a final torque limit obtained by subtracting the feedback torque TQ_FB1from the corrected torque limit. The required torque TQ_COM is required torque determined based on the accelerator opening information by the driver, and is limited to the torque limit TQ_LMT2′. The current limit DC_LMT1illustrated inFIG.11(B)is an available DC limit value calculated from a temperature and a remaining capacity of the secondary battery101. The DC current DC1is a detection value or an estimation value of a current input to the inverter104. The first torque TQ_DC illustrated inFIG.11(C)is drive torque of the motor estimated based on the DC current DC1using the first torque characteristic map701illustrating the relationship between the “DC current DC1and first torque” and the like. The second torque TQ_UVW is drive torque of the motor estimated based on the U-phase, V-phase, and W-phase currents flowing through the motor using the second torque characteristic map801illustrating the relationship between the “U-phase, V-phase, and W-phase currents and second torque” and the like. The variation degree KP1illustrated inFIG.11(D)is a variation degree of a product estimated by comparing the second torque TQ_UVW and the first torque TQ_DC. The variation degree is a case where the response speed is insufficient due to the detection delay in the DC current DC1or the U-phase, V-phase, and W-phase currents, the calculation delay in the first torque calculation unit114and the second torque calculation unit115, or the sudden acceleration of the vehicle. The feedback torque TQ_FB1illustrated inFIG.11(E)is reduced torque generated by current feedback control such that the DC current DC1does not exceed the current limit DC_LMT1when exceeding the current limit DC_LMT1. The current feedback control is provided as the additional function in the torque limit correction unit117. The motor rotation speed SPD illustrated inFIG.11(F)is a rotation speed of the motor calculated from the angle sensor107. In this manner, when the DC current DC1exceeds the current limit DC_LMT1after the required torque TQ_COM reaches the torque limit TQ_LMT2, the feedback torque TQ_FB1is subtracted from the torque limit TQ_LMT2to obtain the final torque limit TQ_LMT2′, thereby reducing the overshoot time of the DC current. According to the above-described embodiment, the following operational effects are obtained. (1) The motor control device includes: the inverter104which supplies the U-phase, V-phase, and W-phase currents to the motor106; the torque limit calculation unit116which calculates the torque limit from the current limit of the secondary battery101that supplies DC current to the inverter104; the first torque calculation unit114, which calculates the first torque based on the DC current supplied to the inverter104; the second torque calculation unit115which calculates the second torque based on the U-phase, V-phase, and W-phase currents; and the torque limit correction unit117which corrects the torque limit using the first torque and the second torque. As a result, even if required torque reaches the torque limit, the DC current does not exceed the current limit, and the output of the motor can be fully utilized by approaching the current limit. Note that the motor control device mounted on and used in the hybrid electric vehicle has been described as an example in the above embodiment, but the present invention is not limited thereto. For example, the present invention may be applied to a motor control device used by being mounted on a pure electric vehicle that does not use an engine, a motor control device used for an industrial motor, or the like. Any motor control device that controls a motor using a secondary battery is included in the scope of the present invention. The present invention is not limited to the above-described embodiment, and other modes, which are conceivable inside a scope of a technical idea of the present invention, are also included in a scope of the present invention as long as characteristics of the present invention are not impaired. REFERENCE SIGNS LIST 101secondary battery102contactor103smoothing capacitor104inverter105phase current detector106motor107angle sensor108clutch109engine110vehicle controller111current command calculation unit112current control unit113DC current sensor114first torque calculation unit115second torque calculation unit116torque limit calculation unit117torque limit correction unit | 29,808 |
11942890 | DETAILED DESCRIPTION Hereinafter, embodiments will be described in detail with reference to the drawings. The same or corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated. Overall Configuration of a Motor Drive System FIG.1is a block diagram showing an example of a configuration of a motor drive system. Referring toFIG.1, a motor drive system100includes a three-phase brushless DC motor30, an inverter circuit20, and a semiconductor device10for controlling the inverter circuit20. 1. Brushless DC Motor The brushless DC motor30includes a Y-connected stator windings31U,31V,31W, and a rotor having one or more pole pairs (not shown). The rotor is driven to rotate in synchronization with a three-phase AC supplied from the inverter circuit20to the stator windings31U,31V,31W. A node of the stator windings31U,31V,31W is referred to as a neutral point32. In the following, the case where the stator windings31is Y-connection is shown inFIG.1, but a technology of the present disclosure has the same effect when the stator windings31is Δ-connection. 2. Inverter Circuit The inverter circuit20includes MOS (Metal Oxide Semiconductor) transistor UP, UN, VP, VN, WP, and WN. The MOS transistor UP is provided on a U-phase upper arm, and the MOS transistor UN is provided on a U-phase lower arm. The MOS transistor VP is provided on a V-phase upper arm, the MOS transistor VN is provided on a V-phase lower arm. The MOS transistor WP is provided on a W-phase upper arm, the MOS transistor WN is provided on a W-phase lower arm. The upper arm is also referred to as the high side, and the lower arm is also referred to as the low side. Further, the inverter circuit20includes a shunt resistor23for detecting a current between the two phases. The following is a brief description of these connections. The MOS transistor UP and the MOS transistor UN is connected in series between a first power supply node21and a connection node24in this arrangement order, the first power supply note21being supplied to an external input voltage VM (also referred to as a power supply voltage VM) and the node24connection being provided at low-potential side. The shunt resistor23is connected between the connection node24and a second power supply node22which provides a ground voltage GND. The output node TU is a connection node between the MOS transistor UP and the MOS transistor UN. The output node TU is connected to one end of the U-phase stator winding31U. Similarly, the MOS transistor VP and the MOS transistor VN are connected in series between the first power supply node21and the connection node24in this arrangement order. The output node TV is a connection node between the MOS transistor VP and the MOS transistor VN. The output node TV is connected to one end of the V-phase stator winding31V. Similarly, the MOS transistor WP and the MOS transistor WN are connected in series between the first power supply node21and the connection node24in this arrangement order. The output node TW is a connection node between the MOS transistor WP and the MOS transistor WN. The output node TW is connected to one end of the W-phase stator winding31W. Each of the MOS transistor UP, UN, VP, VN, WP, WN has a reverse-biased body diode (not shown) connected in parallel. Therefore, when both the transistor of the upper arm and the lower arm on the same phase are in off state, a regeneration current flows through the body diodes. InFIG.1, All MOS transistors UP, UN, VP, VN, WP, WN are composed of N-channel MOS transistors. Alternatively, either of MOS transistors UP, VP, WP of the upper arm and the MOS transistors UN, VN, WN may be NMOS. In this case, the other MOS transistors are PMOS. Alternatively, all of the MOS transistor UP, UN, VP, VN, WP, WN may be composed of P-channel MOS transistors. Further, other types of field effect transistors may be used as a semiconductor switching element composing the inverter circuit20instead of the MOS transistor. Alternatively, a bipolar transistor or Insulated Gate Bipolar Transistor (IGBT) may be used instead of the MOS transistor. However, when other types of transistors are used, it is necessary to connect a flywheel diode in anti-parallel with each transistor. The reason for this is to allow the current to flow through regeneration pass when both the transistors of the upper arm and the lower arm on the same phase are the off state. 3. Semiconductor Device The semiconductor device10includes a switch circuit61, a virtual neutral point generating circuit70, a differential amplifier63, an amplifier65, a microcontroller unit (MCU)40. The switch circuit61and the differential amplifier63configures a detector60for detecting the voltage of the output node of the non-energized phase of the inverter circuit20. The switch circuit61is connected to the output nodes TU, TV, TW. In response to a phase select signals SLU, SLV, SLW outputted from the MCU40, the switch circuit61connects a detection node62to one of the output nodes TU, TV, TW corresponding to the selected phase. The virtual neutral point generating circuit70gives a virtual neutral point72having a voltage having the same role as the neutral point32of the brushless DC motor30. The virtual neutral point generating circuit70includes resistive elements71U,71V,71W. The resistor element71U is connected between the virtual neutral point72and the output node TU. The resistive element71V is connected between the virtual neutral point72and the output node TV. The resistive element71W is connected between the virtual neutral point72and the output node TW. The resistive elements71U,71V,71W have equal resistance value to each other. The differential amplifier63amplifies the difference between the voltage Vd at the detection node62and a reference voltage Vref. The voltage of the neutral point32or virtual neutral point72is used as the reference voltage Vref. The amplifier65amplifies a voltage that occurs in the shunt resistor23. Thus, it is possible to detect the motor current flowing between U-phase, V-phase and W-phase. The MCU40incorporates a computer including a CPU (Central Processing Unit) and memory into one integrated circuit. The MCU40realizes various functions by executing a program stored in the memory. Referring now toFIGS.1and2, the configuration and function of MCU10will be described. FIG.2is a block diagram showing a configuration example of the MCU ofFIG.1. InFIG.2, the MCU40is configured by a computer including a CPU (Central Processing Unit)41, RAM (Random Access Memory)4, and a nonvolatile memory43. The MCU40further includes interface (IF) circuit44,46, analog-to-digital (AD) converters45,48, and a gate control signal generation circuit47. The MCU40further includes a bus49for interconnecting these components. Two or more components, such as the CPU41, may be provided. The CPU41operates in accordance with instructions included in programs stored in the nonvolatile memories43, thereby controlling the entire motor drive system100. The program may be provided as a non-transitory storage medium or may be provided over a network. The RAM42is used as a main memory in which CPU41operates. The nonvolatile memory43stores various setting values necessary for the operation of the program and the program. The nonvolatile memory43may be a mask ROM (Random Access Memory) or an EEPROM (Electrically Erasable Programmable ROM) or the like. Alternatively, the nonvolatile memory43may be a NOR flash memory, a NAND flash memory, or the like. The nonvolatile memory43may further includes a SSD (Solid State Drive) or a hard disk. The IF circuit44is a circuit for receiving an input of the operation command value11from outside. The IF circuit46is a circuit for outputting a phase select signal SLU, SLV, SLW to the switch circuit61based on a command from CPU41. The IF circuits44and46, for example, provide input/output isolation, leveling, and timing adjustment between an internal circuitry of the MCU40and an external circuitry. The AD converter45converts an output signal Vout of the differential amplifier63to a digital signal. The AD converter48converts an output signal Id of the amplifier65to a digital signal. The AD converters45and48may have any known circuit configuration. The gate control signal generation circuit47, based on a command from CPU41, generates a gate control signal GUP, GUN, GVP, GVN, GWP, GWN of the MOS transistor UP, UN, VP, VN, WP, WN. The gate control signal generation circuit47, for example, generates a gate control signal based on PWM (Pulse Width Modulation) control based on comparing a gate voltage command value of each MOS transistor to a value of a carrier signal. Instead of the MCU40having the above configuration, a controller configured by a dedicated circuit such as ASIC (Application Specific Integrated Circuit) may be used. Alternatively, at least two of ASIC, FPGA (Field Programmable Gate Array, CPU, and the like may be combined to configure a controller. Energization Pattern Next, a description will be given of six energization patterns in the case of 120 degrees energization method. In this embodiment, the MCU40controls the brushless DC motor30by 120 degrees energization method. The 120 degrees energization method uses 120 degrees of an electric angle half cycle as an energization period and remaining 60 degrees of the electric angle half cycle as a de-energization period. The BEMF can be detected in the de-energization period. In a three-phase brushless DC motor, there are six energization patterns since the energized phase is switched every electrical angle 60 degrees. Note that the disclosed technique can be applied even when the energization period is more than 120 degrees and less than 180 degrees of the electric angle half cycle, as long as the BEMF generated in the non-energization period can be measured. It should be noted that the energization period and the de-energization period of the above 120 degrees energization method is different from the voltage applying period (also referred to as on period) and the regeneration period (also referred to as off period) of the PWM control. The energization period includes a plurality of voltage applying periods of the PWM control and a plurality of regeneration periods. FIG.3is a diagram for explaining the six energization pattern in the case of 120 degrees energization method. InFIG.3, 6 energization patterns of currents a-f are shown. (a) Referring toFIG.3, the MOS transistor WP of a W-phase upper arm and the MOS transistor VN of the V-phase lower arm is controlled to on state, the other transistors are controlled to the off state. Thus, the motor current flows from the W-phase stator winding31W to the V-phase stator winding31V. The U-phase stator winding31U is de-energized and the zero-crossing point of BEMF is observable. In the following description, this energization pattern is referred to as energization pattern a. Further, in the energization pattern a, the U-phase is referred to as “non-energized phase”, the W-phase is referred to as “upstream-side energized phase”, the V-phase is referred to as “downstream-side energized phase”. Motor current flows in the direction from the stator winding of the upstream-side energized phase to the stator winding of the downstream-side energized phase. The same definition is applied to other energization patterns. When executing the PWM control in the energization pattern a, the MCU40maintains the W-phase upper arm in the on state, and executes the PWM control in the V-phase. Alternatively, the MCU40maintains the V-phase lower arm in the on state and executes PWM control in the W-phase. In the former case, the regeneration current flows through the W-phase upper arm and the V-phase upper arm. In the latter case, the regeneration current flows through the W-phase lower arm and the V-phase lower arm. (b) The MOS transistor WP of the W-phase upper arm and the MOS transistor UN of the U-phase lower arm of the inverter circuit20are controlled to the on state, the other transistors are controlled to the off state. Thus, the motor current b flows from the W-phase stator winding31W to the U-phase stator winding31U. V-phase stator winding31V is in the non-energized state, zero-crossing point of BEMF can be observed. In the following description, this energization pattern is referred to as an energization pattern b. When executing the PWM control in the energization pattern b, the MCU40maintains the W-phase upper arm in the on state, executes the PWM control in the U-phase. Alternatively, the MCU40maintains the U-phase lower arm in the on state and executes PWM control in the W-phase. In the former case, the regeneration current flows through the W-phase upper arm and the U-phase upper arm. In the latter case, the regeneration current flows through the W-phase lower arm and the U-phase lower arm. (c) When the MOS transistor VP of the V-phase upper arm and the MOS transistor UN of the U-phase lower arm are controlled to the on state and the other transistors are controlled to the off state, the motor current c flows from the V-phase stator winding31V to the U-phase stator winding31U. The W-phase stator winding31W is in the non-energized state, zero-crossing point of BEMF can be observed. In the following description, referred to the energization pattern c. When executing the PWM control in the energization pattern c, the MCU40maintains the V-phase upper arm in the on state, executes the PWM control in the U-phase. Alternatively, the MCU40maintains the U-phase lower arm in the on state and executes PWM control in the V-phase. In the former case, the regeneration current flows through the V-phase upper arm and the U-phase upper arm. In the latter case, the regeneration current flows through the V-phase lower arm and the U-phase lower arm. (d) When the MOS transistor VP of the V-phase upper arm and the MOS transistor WN of W-phase lower arm are controlled to the on state, and the other transistors are controlled to the off state, the motor current d flows from the V-phase stator winding31V to the W-phase stator winding31W. The U-phase stator winding31U is de-energized and the zero-crossing point of BEMF is observable. In the following description, this energization pattern is referred to as an energization pattern d. When executing the PWM control in the energization pattern d, the MCU40maintains the V-phase upper arm in the on state, executes the PWM control in the W-phase. Alternatively, the MCU40maintains the W-phase lower arm in the on state and executes PWM control in the V-phase. In the former case, the regeneration current flows through the V-phase upper arm and the W-phase upper arm. In the latter case, the regeneration current flows through the V-phase lower arm and the W-phase lower arm. (e) When the MOS transistor UP of the U-phase upper arm and the MOS transistor WN of W-phase lower arm are controlled to the on state, and the other transistors are controlled to the off state, the motor current e flows from the U-phase stator winding31U to the W-phase stator winding31W. The V-phase stator winding31V is in the non-energized state, zero-crossing point of BEMF can be observed. In the following description, this energization pattern is referred to as an energization pattern e. When executing the PWM control in the energization pattern e, the MCU40maintains the U-phase upper arm in the on state, and executes the PWM control in the W-phase. Alternatively, the MCU40maintains the W-phase lower arm in the on state and executes PWM control in the U-phase. In the former case, the regeneration current flows through the U-phase upper arm and the W-phase upper arm. In the latter case, the regeneration current flows through the U-phase lower arm and the W-phase lower arm. (f) When the MOS transistor UP of the U-phase upper arm and the MOS transistor VN of V-phase lower arm are controlled to the on state, and the other transistors are controlled to the off state, the motor current f flows from the U-phase stator winding31U to the V-phase stator winding31V. The W-phase stator winding31W is in the non-energized state, zero-crossing point of BEMF can be observed. In the following description, this energization pattern is referred to as an energization pattern f. When executing the PWM control in the energization pattern f, the MCU40maintains the U-phase upper arm in the on state, executes the PWM control in the V-phase. Alternatively, the MCU40maintains the V-phase lower arm in the on state and executes PWM control in the U-phase. In the former case, the regeneration current flows through the U-phase upper arm and the V-phase upper arm. In the latter case, the regeneration current flows through the U-phase lower arm and the V-phase lower arm. By controlling the inverter circuit20so as to flow a current to the brushless DC motor30in the order of the energization pattern a, b, c, d, e, f described above, the energized phase is sequentially switched, the rotor of the brushless DC motor30also rotates in synchronization with the rotating electromagnetic field. In this specification, for convenience, this rotation direction is referred to as a clockwise (CW) direction. On the other hand, when switching the energization pattern in the order opposite to the above order, the energized phase also switches in the reverse order. That is, when controlling the inverter circuit20so as to flow a current to the brushless DC motor30in the order of the energization pattern f, e, d, c, b, a, the energized phase is switched in the order opposite to the above order. Therefore, the rotor of the brushless DC motor30also rotates in synchronization with the rotating electromagnetic field. This direction of rotation is referred as a counterclockwise rotation (CCW) direction in this specification. FIG.4is a timing chart showing a waveform of a gate control signal supplied to each MOS transistor. InFIG.4, an example of the waveform for each energization pattern when the regeneration current flows through the lower arm and does not flow through the upper arm is shown. The waveform shown inFIG.4is conceptual and not exactly the same as the actual waveform. When the gate applied voltage is at the high (H) level, the corresponding MOS transistor is controlled to the on state. When the gate applied voltage is at the low (L) level, the corresponding MOS transistor is controlled to the off state. InFIG.4, the non-energized phase is referred as a high-impedance (High-Z) phase. Summary of Motor Drive Operation In the present embodiment, the motor driving operation is broadly divided into three modes. Hereinafter, an outline thereof will be described first. In a first mode, the MCU40estimates an initial position of the magnetic pole of the rotor in a stop state. The detection of the initial magnetic pole position, for example, an inductive sense is used. In the inductive sense, for example, when a voltage to the extent that the rotor does not rotate in the six energization patterns shown inFIG.3is applied to the stator windings31, the difference in current flowing through the stator windings31is detected. The current flowing through the stator windings31is detected by a voltage generated in the shunt resistor23. In the case of brushless DC motor30having a saliency, since the inductance in a d-axis direction is reduced, it is possible to detect the magnetic pole position based on the current change in the winding. Further, in the case of the brushless DC motor30of non-saliency, by detecting the decrease in inductance due to magnetic saturation based on the current change, it is possible to detect the magnetic pole position. Specifically, the current I flowing through the stator windings31is represented by formula (1) I=V/R[1−exp(−t·R/L)] (1) Where R represents the winding resistance of the stator windings31, L represents the inductance, V represents the applied voltage. In a second mode, an initial starting torque is given to the rotor by the PWM drive based on the initial magnetic pole position detected in the first mode. Applying the starting torque is also referred as a kick. In the present embodiment, in order to estimate the magnetic pole position of the rotor, mutual induced voltage in the stator windings31of the non-energized phase generated by the current magnetic field of the stator windings31of the energized phase is detected. As described later, the mutual induced voltage is obtained by the difference between the induced voltage of the non-energized phase during the voltage applying period by the PWM control, and the induced voltage of the non-energized phase of the regeneration period immediately after (or immediately before) the voltage applying period. In the present disclosure, the second mode is referred as mutual induction detection drive. Specifically, magnetic flux ϕ1 is represented by formula (2). ϕ1=B1S=μn1I1S(2) Where n1 represents the number of windings of the stator windings31in the energized phase, L1 represents the winding current, S represents the cross-sectional area of the coil, μ represents the permeability, and B1 represents the magnetic flux density by the current magnetic field. Further, the magnetic flux of the non-energized phase ϕ{circumflex over ( )}2 is represented by formula (3), and the induced voltage e{circumflex over ( )}2 is represented by formula (4). ϕ2∝ϕ1/K(3) e2∝n2·Δϕ2/Δt(4) Where n{circumflex over ( )}2 represents the number of turns of the stator winds31of the non-energized phase. K is a proportionality factor that varies with the position of the rotor, and Δϕ2/Δt is the time rate of change (i.e., derivative) of the magnetic flux ϕ2. FIG.4shows an example of the voltage waveform of the gate control signal GUP, GUN, GVP, GVN, GWP, GWN in the second mode. That is, in the second mode, in order to increase the detection accuracy of the induced voltage during the regeneration period, it is desirable that the inverter circuit20is controlled so that the regeneration current flows through the lower arm as shown inFIG.4, Incidentally, if it is not necessary to increase the detection accuracy, it is not necessary to flow the regeneration current only to the lower arm. For example, the regeneration current may flow through the upper arm. In the third mode, the brushless DC motor30is driven based on the estimated magnetic pole position based on the zero-cross point of BEMF, When the magnitude of BEMF detected in the second mode reaches a predetermined magnitude, the driving mode shifts from the second mode to the third mode. In this disclosure, the third mode is referred as a BEMF detection drive mode. Here, the induced voltage by BEMF refers to the voltage generated in the stator windings31by the rotation of the rotor. Specifically, the induced voltage V by BEMF is represented by formula (5). V=Blv=2πrNBl(5) Where B represents the magnetic flux by the permanent magnet provided in the rotor, v represents the relative speed between the surface of the rotor and the stator windings31, r represents radius of rotation of the rotor, N represents the speed of rotation of the rotor. For simplicity, assume that the coil is a square with one side l. As the waveform of the gate control signal GUP, GUN, GVP, GVN, GWP, GWN in the third mode, the voltage waveform ofFIG.4or other voltage waveforms may be used. For example, the voltage waveform ofFIG.4may be modified so that the phase for performing PWM control is not continuous. Several modified examples of the waveforms shown inFIG.4are described. In the case of energization pattern b, U-phase may be PWM controlled, the gate control signal GWP may be controlled to H level, the gate control signal GWN may be controlled to L level. In the case of energization pattern d, W-phase is PWM controlled, the gate control signal GVP is controlled to H level, the waveform ofFIG.4is changed so that the gate control signal GVN is controlled to L level. In the case of the energization pattern f, the V-phase is PWM controlled, the gate control signal GUP is controlled to H level, the waveform ofFIG.4is changed so that the gate control signal GUN is controlled to L level. In this case, the waveform of energization patterns a, c, e are not changed. Details of Motor Drive Operation FIG.5is a flowchart showing an example of a driving process of the brushless DC motor. Hereinafter, with reference toFIGS.1and5, a description will be given of the driving process of the brushless DC motor30. The detected value of the external input voltage VM is input to the MCU40. In step S10ofFIG.5, the MCU40determines whether the external input voltage VM is equal to or higher than a preset start voltage. The MCU40proceeds the process to step S20when the external input voltage VM is equal to or higher than the start voltage. In step S20, the MCU40sets the gate control signal GUP, GUN, GVP, GVN, GWP, GWN to a low level. This causes the MOS transistor UP, UN, VP, VN, WP, WN to be in all off-state (high-impedance state). In the next step S30, the MCU40, by detecting the induced voltage (BEMF) of each phase while switching on the three phases of the switching circuit61in order, to detect the rotation direction of the rotor. The MCU40, when the rotation direction of the rotor is the forward rotation that is a direction by the operation command value11, the process proceeds to step S70(BEMF detection drive). The MCU40, when the rotation direction of the rotor is the reverse rotation that is a reverse direction to the direction specified by the operation command value11, the process proceeds to step S100(3 phase short brake). The MCU40, when the magnitude of BEMF is equal to or less than a threshold, the rotor is determined to be no rotation, the process proceeds to step S40. In step S40, the MCU40detects the initial magnetic pole position by using, for example, the inductive sense. In the next step S50, the MCU40, based on the initial magnetic pole position detected in step S40, applies a voltage to the stator windings31in the energization pattern the initial torque is increased most. For example, in step S40, it is assumed that the smallest self-inductance is detected in the energization pattern d. In this case, to rotate in the CW direction, the MCU40controls the inverter circuit20so as to apply a voltage to the stator windings31in the energization pattern f. In step S60, the MCU40executes the mutual induction detection drive (mode2). Details of the mutual induction detection drive will be described later with reference toFIGS.7to9. In step S60, when the MCU40determined that the rotation speed is insufficient, the process returns to step S50, and applies an initial torque in the next energization pattern. If the rotation of the rotor cannot be detected even if a kick time exceeds the maximum kick time Tmax, the MCU40determines a timeout. In this case, the MCU40detects the initial magnetic pole position of the rotor by returning the process to step S40. When detecting that the rotation speed of the rotor has reached the specified rotation speed, the MCU40proceeds process to step S70. In step S70, the MCU40executes BEMF detection drive (mode3). Specifically, based on the zero-cross point of BEMF to be detected in the non-energized phase, the MCU40estimate the position and speed of the rotor. The MCU40drives the brushless DC motor30by PWM control so that appropriate torque is applied to the rotor based on the estimated the position and speed of the rotor. When no BEMF detection error is detected (NO in step S80), and the external input voltage VM is equal to or higher than the start voltage (NO in step S90), the MCU40continues to execute the step S70. When BEMF detection error is detected (YES in step S80), and the external input voltage VM is less than the start voltage (YES in step S90), the MCU40proceed the process to step S100. In step S100, the MCU40disconnects the external input voltage VM so that the external input voltage VM is not provided to the first power supply node21. The MCU40then sets the gate control signal GUP, GUN, GVP, GVN, GWP, GWN to H-level so that all MOS-transistor UP, UN, VP, VN, WP, WN are conductive. Thus, three phase short brake is applied to the brushless DC motor30. In step S110, the MCU40sets the phase select signal SLU, SLV, SLW so that any one phase of the switch circuit61is turned on. In this state, for example, when the MCU40controls so that U-phase of the switch circuit61is turned on, the MCU40monitors a terminal voltage between the output node TU and the virtual neutral point72. Until the magnitude of the terminal voltage (or the maximum value) is equal to or less than the stop threshold set in advance, the MCU40continues to execute the three phases short brake (step S100). When the magnitude (or maximum value) of the terminal voltage becomes equal to or less than the stop threshold (YES in step S110), the MCU40returns the process to the first step S10. FIG.6is an example of a current waveform of each phase of the motor drive system ofFIG.1. The magnitude of the applied current and the current applying time may have been deformed to facilitate understanding of the figure and are not proportional to the actual current. Referring toFIG.6, from time t0to time t10corresponds to the mode1(initial magnetic pole position detection). From time t10to time t20corresponds to mode2(mutual induction detection drive). Time t20and later correspond to mode3(BEMF detection drive). At time t0to time t10, the MCU40applies a voltage to the stator windings31in the order of the six energization patterns a to f described inFIG.3by controlling the inverter circuit20. In this case, the voltage applied to the stator windings31and its applying time is limited to the extent that the rotor does not rotate. The MCU40detects the current flowing through the stator windings31in the respective energization patterns (i.e., the voltage generated in the shunt resistor23). Based on the detection results, the MCU40determines the energization pattern when the self-inductance is lowest. At time t20from time t10, the MCU40applies a start torque to the brushless DC motor30by controlling the inverter circuit. First, at time t10, the MCU40applies a voltage based on the PWM control to the stator windings31in the energization pattern most applied torque is increased based on the position of the rotor detected by the inductive sense. In the case ofFIG.6, first, a voltage is applied in the energization pattern f. The voltage applying period of the PWM control, a current flows from the U-phase upper arm to the V-phase lower arm through the stator windings31. The regeneration period of the PWM control, the regeneration current flows in the direction of the V-phase lower arm from the U-phase lower arm through the stator windings31. The MCU40detects the induced voltage of the W-phase that is the non-energized phase by the detector60. The MCU40estimates the mutually induced voltage and BEMF based on the detected induced voltage of the non-energized phase. Specific methods for estimating mutually induced voltage and VEMF will be discussed below with reference toFIGS.7-9. At time t11, the mutual induced voltage detected in the W-phase of the non-energized phase becomes substantially zero (i.e., the absolute value of the mutually induced voltage is smaller than the threshold value). At this time, since the absolute value of BEMF detected by the W-phase of the non-energized phase is not equal to or greater than the threshold voltage Vth, the MCU40switches the energization pattern. That is, the MCU40applies a voltage based on the PWM control to the stator windings31in the next energization pattern a by controlling the inverter circuit20. In the energization pattern a, during the voltage applying period of the PWM control, a current flows from the W-phase upper arm to the V-phase lower arm through the stator windings31. The regeneration period of the PWM control, the regeneration current flows in the direction of the V-phase lower arm from the W-phase lower arm through the stator windings31. The MCU40detects the induced voltage of the U-phase is the non-energized phase by the detector60. At time t12, mutual induced voltage detected in the U-phase of the non-energized phase becomes substantially zero (i.e., the absolute value of the mutually induced voltage is smaller than the threshold value). At this time, since the absolute value of BEMF detected by the U-phase of the non-energized phase is not equal to or greater than the threshold voltage Vth, the MCU40switches the energization pattern. That is, the MCU40applies a voltage based on the PWM control to the stator windings31in the next energization pattern b by controlling the inverter circuit20. In the energization pattern b, during the voltage applying period of the PWM control, a current flows from the W-phase upper arm to the U-phase lower arm through the stator windings31. During the regeneration period of the PWM control, the regeneration current flows in the direction of the U-phase lower arm from the W-phase lower arm through the stator windings31. The MCU40detects the induced voltage of the V-phase that is the non-energized phase by the detector60. At time t13, mutual induced voltage detected in the V-phase of the non-energized phase becomes substantially zero (i.e., the absolute value of the mutually induced voltage is smaller than the threshold value). At this time, since the absolute value of BEMF detected by the V-phase of the non-energized phase is equal to or greater than the threshold voltage Vth, the MCU40switches the drive mode from mode2to mode3at the next time t20. At time t20, the MCU40applies a voltage based on the PWM control to the stator windings31in the energization pattern d by controlling the inverter circuit20. During energization by the energization pattern d, the MCU40detects the zero-crossing point of BEMF of the U-phase of the non-energized phase by the detector60. BEMF in mode3is detected via CR filter. At a time t21elapsed 30 degrees at an electric angle from the detection time of the zero-cross point, the MCU40switches the energization pattern from the energization pattern d to the energization pattern e. Hereinafter, similarly, the energization pattern is switched at each time t22to t26based on detection of the zero-cross point of BEMF of the non-energized phase. Detailed Operation of Mutual Induction Detection Drive FIG.7is a flowchart showing a detailed operation of the mutual induction detection drive in step S60ofFIG.5. In step S200ofFIG.7, the MCU40determines whether the elapsed time Tkick from the kick start (referred to as kick time Tkick) exceeds a predetermined minimum kick time Tmin. The MCU40proceeds the process to the step S210if the kick time Tkick exceeds the smallest kick time Tmin (YES at the step S200). In a step S210, the MCU40detects the induced voltage A of the non-energized phase at the timing when the PWM pulse is on. The MCU40detects the induced voltage B of the non-energized phase at the timing when the PWM pulse is then off. Variable C, which is a value obtained by subtracting the induced voltage B from the induced voltage A corresponds to the induced voltage based on mutual induction. Incidentally, when the rotor is rotating, each of the induced voltage A and the induced voltage B, it also includes a BEMF. By subtracting the induced voltage B from the induced voltage A, BEMF is canceled. More precisely, an offset value center_m of the differential amplifier63near the half of the external input voltage VM, and an offset value center_d of the differential amplifier63near the ground voltage GND are considered. In step S220, the MCU40calculates the variable C by formula (6). (A−center_m)−(B−center_d) (6) The MCU40stores the calculated C in the memory. In the following step S230, the MCU40stores the absolute value of (A−center_m) in the memory as the variable D. Instead of the absolute value of (A−center_m), the absolute value of (B−center_d) may be stored in the memory as a variable D. When the induced voltages based on mutual induction (i.e., the variables C) are 0, the absolute value of (A−center_m) or the absolute value of (B−center_d) will be equal to the absolute value of BEMF. In the following step S240, the MCU40determines whether the energization pattern is either of a or c or e, or either of b or d or f. As an example, the MCU40proceeds the process to step S250if the rotation direction of the rotor is the CW direction described inFIG.3and the energization pattern is b or d or f. The MCU40proceeds the process to step S260if the rotation direction of the rotor is CW direction and the energization pattern is a or c or e. The MCU40proceeds the process to step S260if the rotation direction of the rotor is is the CCW direction described inFIG.3, and the energization pattern is b or d or f. The MCU40proceeds the process to step S250if the rotation direction of the rotor is the CCW direction and the energization pattern is a or c or e. Since the CW direction and the CCW direction are for convenience, the processing may proceed in the opposite direction to the above. First, the process proceeds to the step S250is described. When the variable C calculated by the above formula (6) is positive at the kick start time point, the process proceeds to the step S250. In the step S250, the MCU40determines whether or not the variable C is greater than the threshold voltage +margin1. The MCU40processes to step S310if the variable C is greater than the +margin1(YES in step S250). In step S310, if the kick time Tkick is greater than the maximum kick time Tmax (YES in step S310), the MCU40stops the kick and determines that it's time out (step S320). On the other hand, in step S310, if the kick time Tkick is equal to or less than the maximum kick time Tmax, the MCU40returns the process to step S210. In step S250, if the variable C is equal to or smaller than margin1value (NO in step S250), the MCU40proceeds the process to step S270. In step S270, the MCU40determines whether or not the kick time Tkick is equal to or less than the target kick time Tspeed. When the kick time Tkick exceeds the target kick time Tspeed (NO in step S270), the MCU40determines that the rotation speed is insufficient (step S300). In this instance, the MCU40returns the process to S50ofFIG.5, and starts kicking with the following energization pattern. On the other hand, when the kick time Tkick in the step S270is equal to or less than the target kick time Tspeed (YES in the step S270), the MCU40proceeds the process to the step S280. In the following step S280, the MCU40determines whether or not the variable D stored in the step S230is equal to or greater than a threshold value. The variable D is equal to or greater than the threshold corresponds to the absolute value of BEMF being equal to or greater than the threshold voltage Vth. When the variable D is equal to or greater than the threshold value (YES in step S280), the MCU40determines that the variable D has reached the specified rotation speed (step S300). In this instance, the MCU proceeds the process to BEMF detection drive in S70ofFIG.5. Next, the case where the process proceeds to step S260as a result of the determination in step S240is described. In this case, the variable C calculated by the above equation (6) corresponds to a negative case at the kick start time. In step S260, the MCU40determines whether the variable C is less than the threshold voltage −margin1. The MCU40proceeds the process to step S310if the variable C is less than −margin1(YES at step S260). Since the subsequent process has been described in step S250, the explanation will not be repeated. If the variable C is greater than or equal to −margin1value (NO in step S260), the MCU40proceeds the process to step S270. Since the subsequent process has been described in step S250, the explanation will not be repeated. In the above, the MCU may determine whether or not the absolute value of the variable C is equal to or less than the threshold voltage of +margin1without dividing the process according to the energization patterns. In this instance, instead of the steps S240, S250, S260, a step determining whether or not the absolute value of the variable C is equal to or less than +margin1is provided. Specifically, the MCU40proceeds the process to step S310when the absolute value of the variable C is larger than +margin1, and proceeds the process to step S270when the absolute value of the variable C is equal to or smaller than +margin1. Example of Mutual Induction Detection Drive FIGS.8A and8Bare examples of an output waveform of a differential amplifier ofFIG.1in the mutual induction detection drive. InFIGS.8A and8B, in the case of the energization pattern b, the waveform of the voltage between the output node TV of the V-phase which is the non-energized phase and the virtual neutral point72, and the waveform of the U-phase current are shown.FIG.8Ashows a case where the rotor is not rotating, andFIG.8Bshows a case where the rotor is rotating. The horizontal axis of each graph corresponds to the position of the rotor. That is,FIGS.8A and8Bshow a waveform synthesizing output waveforms having different position of the rotor. The more to the right, the output waveform at the position where the rotor rotates in more CW direction is shown. Referring toFIG.8A, the voltage A′ and voltage B′ are detected, the voltage A′ being a voltage when the voltage applied state in the PWM control, and the voltage B′ being a voltage when the regeneration current immediately thereafter is flowing. From the formula (6) above, the variable C is calculated by formula (7) C=(A′−center_m)−(B′−center_d) (7) By detecting when the positive and negative of the above variable C is changed, it is possible to detect the position of the rotor every electrical angle 60 degrees. The γ point corresponds to when the variable C=0. Referring toFIG.8B, the voltage A in a voltage applied state in the PWM control, and the voltage B when the regeneration current flows immediately after the voltage applied state are detected. From the formula (6) above, the variable C is calculated by formula (8) C=(A−center_m)−(B−center_d) (8) Here, the voltage waveform ofFIG.8Bwhen the rotor is rotating, it can be considered that BEMF is added to the voltage waveform ofFIG.8Athe rotor is not rotating. Therefore, the formula (8) above is rewritten like below. C=(A′+BEMF−center_m)−(B′+BEMF−center_d) (9) Since BEMF is cancelled, the above formula (9) becomes the same as the above formula (7). That is, the value of the variable C when the rotor is stopped is equal to the value of the variable C when the rotor is rotating. Therefore, by determining the polarity of the variable C, the same accuracy even when the rotor is rotating even when the rotor is stopped, it is possible to detect the position of the rotor. When the variable C is 0, a formula (10) is established. A′−center_m=B′−center_d=0 (10) Therefore, the absolute value of (A−center_m) or the absolute value of (B−center_d) calculated as the variable D above is equal to the absolute value of BEMF. That is, the peak value level of the BEMF can be detected. InFIGS.8A and8B, margin1is a determination threshold for determining the polarities of C. That is, in the polarity determination of the actual variable C, the position of the rotor is detected at a position before the γ point inFIGS.8A and8B. Since the waveform of BEMF is close to a sinusoidal waveform, it does not affect the detection accuracy of BEMF even if it deviates about 30 degrees at an electric angle from the position of the rotor when the variable C=0. FIGS.9A,9B and9Care diagrams for explaining the position of the rotor at the positions of the α point, the β point, and the γ point inFIGS.8A and8B. InFIGS.9A,9B and9C, cross-sectional view of the brushless DC motor30when the pole logarithm is 2 is shown conceptually.FIG.9Ashows the case of the α point, andFIG.9Bshows the case of the β point, andFIG.9Cshows the case of the γ point inFIGS.8A and8Brespectively. In the case of energization pattern b, the winding current flows from the W-phase to the U-phase, the voltage of the V-phase is the non-energized phase is detected. As shown inFIG.9A, the α point represents the position of the rotor 120 degrees of electric angle before from γ point. In this case, + voltage is generated in the V-phase. As shown inFIG.9B, the β point indicates the position of the rotor 90 degrees of electric angle before from γ point. In this case, BEMF detected in the V phase is approximately 0. As shown inFIG.9C, the γ point indicates the position of the rotor when the variable C, i.e., the induced voltage based on mutual induction is 0. Effect As described above, according to the brushless DC motor30of the present disclosure, the position of the rotor is detected by utilizing the induced voltage generated in the non-energized phase by mutual induction based on the current magnetic field of the energized phase. Thus, prior to the sensorless control based on the detection of the zero-cross point of BEMF becomes feasible, at the time of initial start of the brushless DC motor30, it is possible to detect the position of the rotor. Here, by obtaining the difference between the induced voltage of the non-energized phase during the voltage applying period of the PWM control, and the induced voltage in the non-energized phase immediately after or before the induced voltage during the regeneration period, it is possible to detect the position of the rotor without being affected by BEMF. Therefore, in the case where the rotor is no rotation and the case of the rotor is in rotation, it is possible to use the same determination threshold to detect the timing at which the difference is 0. In addition, the magnitude of BEMF can be detected from the mutual induced voltage when the above difference is nearly zero. Until now, large-constant CR filtering was required to detect BEMF when PWM-frequency is lower, but present embodiment can detect with high accuracy without using CR filtering. Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof. | 46,612 |
11942891 | DETAILED DESCRIPTION An electric machine such as a generator may include permanent magnets for the field of the main generator and/or exciter. The permanent magnets may be included in either the rotor or the stator. For example, the electric machine may include a main generator with a wound-field and an exciter with a permanent magnet field. Other embodiments of electrical machines include permanent magnet brush-type DC machines, permanent magnet brushless DC machines, series-wound or universal machines, induction AC machines, synchronous AC machines, synchronous reluctance machines, switched reluctance machines, among others. Any machine may be used as a motor, selectively between a motor and a generator, or entirely as a generator. A voltage regulator may control the generator output through feedback control. For example, the voltage regulator may receive sensor data of an electrical parameter (e.g., voltage, current, power). The sensor data may be compared to a reference value based on a target output of the generator. The target output may be a set value, or a variable value determined by the voltage regulator. Based on the comparison, the voltage regulator may determine a difference (e.g., error signal) for controlling (increasing or decreasing) another parameter (e.g., field current, rotational velocity, air gap, field to armature alignment, or others). In one example, the field current is adjusted by increasing or decreasing the current flow to an exciter stator, resulting in a lower or higher voltage at the armature in the main generator stator. FIG.1illustrates an example rotor assembly600for an electric machine. The rotor assembly600may include an exciter armature601, a main field coil assembly602, a cooling fan603, drive discs604, a coupling605, a rotor controller606, a sensor607, a rotor communication device608, and a rotor bearing609. Additional, different, or fewer components may be included. The coupling605and/or drive discs604couple the rotor assembly600to a prime mover such as an engine. The coupling605may be a fixed connection between the rotor assembly600and the engine via drive discs604. Alternate devices that connect the rotor assembly600to the engine include a splined shaft, a compliant member, or a fully constrained connection may be utilized under appropriate conditions. It should be noted that while engine is used as a term to describe the prime mover, converting fuel to a rotational speed and torque applied to a generator, any apparatus capable of providing mechanical torque and rotation or of requiring mechanical torque and rotation may be coupled to an electrical machine, operating as a motor or a generator. An electrical machine may also provide torque without causing rotation, such as to hold a position against a load. Thus, rotation is not required to define a device as an electrical machine. In general, the generator or genset, may generates electrical energy or power from mechanical energy. The motor, on the other hand, receives electrical energy and converts it to mechanical energy by producing load torque. A power source or prime mover produces a driving torque. This torque will oppose the load torque and cause rotation of the rotor of the electric machine at some velocity. The prime mover may be an internal combustion engine. An internal combustion engine may have performance characteristics where the available torque may vary with the rotational velocity. As such, the engine may not provide adequate torque at lower velocity. If the load torque for the engine is greater than the available torque, speed decreases. The electric machine may be coupled to an internal combustion engine as the prime mover, operating at some nominal velocity. The electric machine may have an electrical load as electrical energy. This load will be converted to a mechanical energy as torque. As larger loads are applied, greater torque may be created. As greater load torque is applied to the engine, velocity or speed may decrease. If torque is not reduced, the engine speed may continue to decrease. It may be advantageous to reduce the load to a level where the engine may overcome this torque and bring the speed back to the nominal value. Further, the engine maybe be configured for a constant speed or a variable speed that varies based on the load. Likewise, the alternator may be included in a variable speed generator. In any of these examples, a voltage regulator may provide feedback control to maintain the desired output target voltage of the electric machine. In addition, the resistance of the load impacts the response of output control. The following embodiments provide systems and techniques for maintaining a desired speed in an electrical machine under a load resistance that varies in time. An electrical load may have a real component and a reactive component. The electric load includes the real component, measured in electric watts, which is directly related to the resulting load torque. The real component, or watts, can be calculated as the product of the real component of the load current and the applied voltage. The real component of the load current is dependent on the resistive component or resistance of the load and the applied voltage, where current equals voltage divided by resistance (Ohm's Law). Electrical load has the mathematical relationship where watts is equal to the squared value of applied voltage divided by the resistance of the load (Joule's Law). Further, power can be seen to be proportional to the voltage squared, and inversely proportional to resistance. The electrical load applied to an electric machine may have a resistive component, resulting in an applied load torque to the prime mover. The applied torque will be dependent on the resistance of the load and the applied voltage. The applied torque may then be modified by changing the applied voltage or the resistance of the load. For example, to reduce the load torque, the applied voltage could be reduced. If an electrical load is applied to an electric machine, there will be a resulting load torque applied to the prime mover. If the applied torque (predetermined or empirically determined) to cause a drop in speed, it may be concluded the applied torque is greater than that which the prime mover can provide at the operating speed/velocity. If the applied voltage is reduced sufficiently, the torque may drop to a level where the prime mover can maintain the desired speed. Thus, a change in resistance of the load impacts the implied torque on the prime mover, and operation of the voltage regulator is adjusted to maintain the desired speed and target voltage of the electrical machine. For the rotor assembly600of an electrical machine shown inFIG.1, the engine turns the rotor assembly600, rotating the exciter armature601along with the field coil assembly602. The engine may also turn the cooling fan603. The cooling fan603may force air across the field coil assembly602, the rotor controller606, and/or the exciter armature601, any of which may expel heat as current flows through the windings or other electrical components. Some electrical machines, such as sealed machines, liquid-cooled machines and high-efficiency machines, may not require a cooling fan to maintain the internal components to a stable temperature. In addition, some electrical machines, such as induction machines, brushless DC machines, and switched reluctance machines, may contain fewer rotating elements in the rotor assembly. Further, some electrical machines, such as large synchronous machines and brush-type DC machines may contain more or different rotating elements in the rotor assembly. FIG.2illustrates an example rotor stator assembly610for an electric machine. The stator assembly610includes a stator chassis611, a set of leads612, armature613, an end bracket614, an exciter field assembly615, and a stator communication device618. Additional, different, or fewer components may be included. The rotor assembly600may fit inside the stator assembly610. The exciter field assembly615may be aligned with the exciter armature601. The stator chassis611may be aligned with the field coil assembly602. In the example machine, the exciter armature601includes exciter armature windings, and the exciter field assembly615includes permanent magnets as a source of magnetic flux. As the exciter armature windings rotate within the stator assembly610, through the magnetic field, one or more currents are generated in the exciter armature windings. Two or more wires or other electrical conductors connect the exciter armature windings to the field coil assembly602through the rotor controller606. The current from the exciter armature windings supplies current to the field coil assembly602. In the example machine, a stator communication device618provides a signal to a rotor communication device608, which then affects the amount of current passing through the rotor controller606to the field coil assembly602. For the example stator assembly610, the stator includes the armature windings613and the permanent magnet exciter field615. As the field coil assembly602rotates within the stator assembly610, and the magnetic field generated by the field coil assembly602, currents are induced in the armature613. The current from the windings613is carried by the leads612to a load. While the term windings may refer to conductive wires wrapped around a material, which may be ferromagnetic, the term windings may be extended to refer to any arrangement of conductive materials which encompasses a volume through which magnetic flux may flow. Similarly, coils, commonly referring to a grouping of conductive wires wound around a bobbin, ferrous member or other core, may be extended to include conductive material in multiple paths around a point in space. FIG.3illustrates an example voltage regulator100for a generator having a dynamic voltage-to-frequency (V/F) ratio. The voltage regulator100includes a voltage calculator102, a selection module103, and a memory111or other data storage devices for multiple V/F ratios110A-D. Calculations, determinations, and identifications described as being performed at the voltage regulator100may be performed specifically by the voltage calculator102. Data values received at or calculated by the voltage regulator100may be stored in the memory. In addition, the voltage regulator100may include a control circuit113, which may be referred to as a controller, for dynamically adjusting a target output of the generator in response to the V/F ratios110A-D. This function may alternatively be performed at the voltage calculator102(i.e., the voltage calculator102and the control circuit113may be implemented by a single device). Additional, different, or fewer components may be included. The voltage regulator100is coupled to a generator101. The voltage regulator100may be electrically and physically coupled to a generator101. The generator101provides power to a load (e.g., one or more circuits of a home, building, boat, vehicle, etc.). The generator101may include one or more sensing circuits for measured electrical parameters of the generator101or of the load connected to the generator101. For example, a resistance sensing circuit generates sensor data for resistance as measured resistance122. The resistance may be the resistance of a load. The resistance may be a component of the complex impedance of the load, including a reactance component. The resistance may be measured at the output of the generator101. The resistance may be a value representing a percentage of a reference value. Thus, the voltage regulator100receives resistance data for an output of the generator101. In addition, a voltage sensing circuit generates sensor data for the output of the generator101as measured voltage123. Other sensing circuits such as a current sensing circuit, a power sensing circuit, or others are possible. The voltage may be measured at the output of the generator101. Thus, the voltage regulator100receives voltage data for an output of the generator. As an alternative to the measured resistance122, the resistance may be a predetermined value. For example, certain loads may have predefined resistances. For example, a motor may be associated with a first predetermined resistance, a light may be associated with a second predetermined resistance, and other devices may have other predetermined resistances. The voltage regulator100(e.g., control circuit113) receives a target voltage121(or target output) for the generator101. The target voltage121may be stored in memory of the voltage regulator100. That is, the target voltage121may be associated with the rated output of the generator101. Alternatively, the target voltage121may be received from a user input. The user may provide an input to a keypad, button, or other device at the generator101or the voltage regulator100. The user may enter information on a computing device (e.g., laptop, mobile phone, etc.) that is configured to transmit the user input to the voltage regulator100. Additional information regarding user inputs and communication from other examples herein may be implemented by the voltage regulator100. The target voltage121may be dependent on a frequency of the output signal or speed of the engine that rotates the prime mover of the generator101. The frequency may be measured by a rotation sensor generating a feedback signal for an output shaft of the engine, a control signal for the engine, or measured by an electrical sensor detecting one of the internal parameters of the generator (e.g., frequency of output from the exciter armature601), or from the main output of the generator101. The control signal may be from an input device for setting the speed of the engine or rotor. The feedback signal may be generated by a sensor such as a rotation sensor. The rotation sensor may magnetically, optically or mechanically measure the rotation of the output shaft. Thus, the feedback signal may be indicative of the speed of the output shaft. Also, the feedback signal could be derived from the output of the generator101. The voltage regulator100may calculate shaft output characteristics such as speed or torque as a function of the output voltage or current. The voltage regulator100(e.g., selection module103) selects a voltage-frequency ratio based on the resistance data. Alternatively, the voltage regulator may receive frequency or engine speed141from a sensor or from an engine control unit (ECU). The voltage regulator100may query a database or a curve using the frequency or engine speed141to determine the voltage-frequency ratio. The voltage regulator100calculates an output adjustment for the generator in response to the selected voltage-frequency ratio and the voltage data. FIG.4illustrates an example a dynamic frequency to voltage ratio chart. The horizontal axis is the frequency of the output signal or speed of the engine. The horizontal axis values may be the relative value (percent of, fraction of) compared to a reference for the respective signal. For any given frequency, a voltage value is determined from the point on the selected ratio chart or curve, as defined by the vertical axis. The voltage value may be a percentage of nominal voltage. The nominal voltage may be the set target voltage. Thus, when the corresponding voltage value is 90%, for a particular frequency value, then 90% of the set target voltage is used. The voltage regulator100may calculate the output adjustment based on the nominal voltage and add the target output for voltage regulation to the output adjustment. The voltage regulator100may store multiple voltage-frequency curves as shown inFIG.4, as curves150A-D. The voltage regulator100(e.g., selection module103) selects one of the voltage-frequency curves in response to the measured resistance122. For example, the voltage regulator100may compare the measured resistance122to one or more reference values or ranges. When the measured resistance122is in a first range (e.g., between a first minimum and first maximum), the first curve150A is selected. When the measured resistance122is in a second range (e.g., between a second minimum and second maximum), the second curve150B is selected. When the measured resistance122is in a third range (e.g., between a third minimum and third maximum), the third curve150C is selected. When the measured resistance122is in a fourth range (e.g., between a fourth minimum and fourth maximum), the fourth curve150D is selected. The voltage regulator100may use the same ranges (or thresholds) to switch between the curves150A-D. For example, moving from the second curve150B to the third curve150C occurs when the measured resistance moves from the second range to the third range. However, different thresholds may be used when transitioning between the curves150A-D. For example, the ranges (first range, second range, third range, and fourth range) are used when the measured resistance122is initially detected (e.g., when the load is initially connected to the electric machine or when the electric machine is turned on). Subsequently, modified ranges may be used for transitioning between the curves150A-D. The ranges may be narrowed or widened. The thresholds of the ranges may be increased or decreased by a predetermined amount. In another example, an additional transition test may be applied before the voltage regulator100transitions between the curves150A-D. The transition test may be a speed threshold or a voltage threshold. For example, once the voltage regulator100has selected one of the curves150A-D, the voltage regulator does not transition to another of the curves150A-D until both the measured resistance122has been detected in another range and the transition test has been satisfied such that the speed of the electric machine has fallen before a transition speed threshold and/or the output voltage of the electric machine has fallen below a transition output threshold. The transition speed threshold may be a predetermined percentage of the rated speed. The transition output threshold may be a predetermined percentage of the nominal voltage. Each of the curves150A-D may include multiple regions. The curves150A-D may include a low frequency region that is substantially horizontal, a high frequency region that is substantially horizontal, and a transition region. The transition region of each curve150A-D may be defined by a slope. Each of curves150A-D may include a different slope for the transition region. The slope extends from a first frequency value (the highest frequency for the low frequency region) to a second frequency level (the lowest frequency for the high frequency region). That is, the slope for a first curve of the plurality of voltage-frequency curves is different than the slope for a second curve of the plurality of voltage-frequency curves. Each of curves150A-D may have different transition regions. That is, the high frequency region for the first curve may begin at a higher frequency than the next curve, and so on. Similarly, the lower frequency regions may be defined by different values. As an alternative to the selection of the voltage-frequency curves, the voltage regulator100may modify the voltage-frequency ratio or a voltage-frequency curve in response to the resistance data or other sensing circuit data. Modified curves or new curves may be stored in memory. FIG.5illustrates an example control system for the voltage regulator100. The control system may include a processor300, a memory352, and a communication interface353for interfacing with devices or to the internet and/or other networks346. In addition to the communication interface353, a sensor interface may be configured to receive data from the sensor310or data from any source. The components of the control system may communicate using bus348. The control system may be connected to a workstation or another external device (e.g., control panel) and/or a database for receiving user inputs, system characteristics, and any of the values described herein. Optionally, the control system may include an input device355and/or a sensing circuit in communication with any of the sensors. The sensing circuit (e.g., sensor310) receives sensor measurements from other components as described above. The input device355may include a touchscreen, a keyboard, a microphone for voice inputs, a camera for gesture inputs, and/or other inputs. Optionally, the control system may include a drive unit340for receiving and reading non-transitory computer media341having instructions342. Additional, different, or fewer components may be included. The processor300is configured to perform instructions342stored in memory352for executing the algorithms described herein. A display350may be supported by the generator101or provided otherwise. The display350may be combined with the user input device355. FIG.6illustrates an example flowchart for the control system ofFIG.5. Additional, different, or fewer acts may be included. At act S101, the processor300or the communication interface353receives or identifies resistance data for the output of the generator101. The resistance data may be measured through the current and voltage at the output of the generator100. The resistance data may be a set value. The resistance data may be calculated based on the load devices connected to the generator100. The resistance data may be entered by the user (e.g., via the user input device355). At act S103, the processor300or the communication interface353receives or identifies voltage data for the output of the generator101. The voltage data may be sampled at the output of the generator101or elsewhere on the load circuit. At act S105, the processor300selects a voltage-frequency ratio based on at least the resistance data. The memory352may include one or more arrays or tables of voltage and frequency/speed pairs A particular table or array is selected by the processor300in response to at least the resistance data. For example, each table or array may be associated with a resistance range such that detected resistances within the range cause the processor300to select the corresponding table or array. Other factors, such as the output voltage, may be used in selected the table or array. At act S107, the processor300calculates an output adjustment for the generator101in response to the selected voltage-frequency ratio and the voltage data. The output adjustment may be implemented by changing the field current of the generator101. The output adjustment may be implemented internally by the voltage regulator of the generator101. The output adjustment may be provided by the display350to a user or through communication interface353to a server or central computer. At step S109, the processor300determines the appropriate modifications for the voltage-frequency ratio array/table and saves the new curve data in memory352. For example, once an initial array/table is selected, the ranges for other arrays/tables may be modified in order to lessen the effect of rapid switching between arrays/tables. In other examples, the array/tables may be modified over time in response to the measured output of the generator. The processor300may include a general processor, digital signal processor, an application specific integrated circuit (ASIC), field programmable gate array (FPGA), analog circuit, digital circuit, combinations thereof, or other now known or later developed processor. The processor300may be a single device or combinations of devices, such as associated with a network, distributed processing, or cloud computing. The memory352may be a volatile memory or a non-volatile memory. The memory352may include one or more of a read only memory (ROM), random access memory (RAM), a flash memory, an electronic erasable program read only memory (EEPROM), or other type of memory. The memory352may be removable from the network device, such as a secure digital (SD) memory card. In addition to ingress ports and egress ports, the communication interface353may include any operable connection. An operable connection may be one in which signals, physical communications, and/or logical communications may be sent and/or received. An operable connection may include a physical interface, an electrical interface, and/or a data interface. The communication interface353may be connected to a network. The network may include wired networks (e.g., Ethernet), wireless networks, or combinations thereof. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMax network. Further, the network may be a public network, such as the Internet, a private network, such as an intranet, or combinations thereof, and may utilize a variety of networking protocols now available or later developed including, but not limited to TCP/IP based networking protocols. While the computer-readable medium341(e.g., memory352) is shown to be a single medium, the term “computer-readable medium” includes a single medium or multiple media, such as a centralized or distributed database, and/or associated caches and servers that store one or more sets of instructions. The term “computer-readable medium” shall also include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processor or that cause a computer system to perform any one or more of the methods or operations disclosed herein. In a particular non-limiting, exemplary embodiment, the computer-readable medium can include a solid-state memory such as a memory card or other package that houses one or more non-volatile read-only memories. Further, the computer-readable medium can be a random access memory or other volatile re-writable memory. Additionally, the computer-readable medium can include a magneto-optical or optical medium, such as a disk or tapes or other storage device to capture carrier wave signals such as a signal communicated over a transmission medium. A digital file attachment to an e-mail or other self-contained information archive or set of archives may be considered a distribution medium that is a tangible storage medium. Accordingly, the disclosure is considered to include any one or more of a computer-readable medium or a distribution medium and other equivalents and successor media, in which data or instructions may be stored. The computer-readable medium may be non-transitory, which includes all tangible computer-readable media. In an alternative embodiment, dedicated hardware implementations, such as application specific integrated circuits, programmable logic arrays and other hardware devices, can be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various embodiments can broadly include a variety of electronic and computer systems. One or more embodiments described herein may implement functions using two or more specific interconnected hardware modules or devices with related control and data signals that can be communicated between and through the modules, or as portions of an application-specific integrated circuit. Accordingly, the present system encompasses software, firmware, and hardware implementations. In accordance with various embodiments of the present disclosure, the methods described herein may be implemented by software programs executable by a computer system. Further, in an exemplary, non-limited embodiment, implementations can include distributed processing, component/object distributed processing, and parallel processing. Alternatively, virtual computer system processing can be constructed to implement one or more of the methods or functionality as described herein. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and anyone or more processors of any kind of digital computer. Generally, a processor may receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer may also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. The illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The illustrations are not intended to serve as a complete description of all of the elements and features of apparatus and systems that utilize the structures or methods described herein. Many other embodiments may be apparent to those of skill in the art upon reviewing the disclosure. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. Additionally, the illustrations are merely representational and may not be drawn to scale. Certain proportions within the illustrations may be exaggerated, while other proportions may be minimized. Accordingly, the disclosure and the figures are to be regarded as illustrative rather than restrictive. While this specification contains many specifics, these should not be construed as limitations on the scope of the invention or of what may be claimed, but rather as descriptions of features specific to particular embodiments of the invention. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. One or more embodiments of the disclosure may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any particular invention or inventive concept. Moreover, although specific embodiments have been illustrated and described herein, it should be appreciated that any subsequent arrangement designed to achieve the same or similar purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the description. It is intended that the foregoing detailed description be regarded as illustrative rather than limiting and that it is understood that the following claims including all equivalents are intended to define the scope of the invention. The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention. | 32,143 |
11942892 | DETAILED DESCRIPTION OF THE DRAWINGS Briefly, the present invention, amongst other features, provides a hybrid assembly for removably and adjustably mounting solar panels on a surface. Before particularly discussing the hybrid assembly itself, components of the hybrid assembly will first be discussed. Generally, the hybrid assembly consists of components of a “rail-based” system and components of a “rail-less” or “non-rail-based” system. A rail-based system generally includes at least one rail that extends an entire length or width of at least one solar panel of a plurality of solar panels that are utilized in a solar panel array. The rail mounts the solar panel(s) to a surface, such as the roof of a home or building. The rail may also be referred to as a continuous mounting beam. As will be further discussed below, such rails may be either a trim-rail, a single rail, or a shared rail. However, the present invention is not limited to these particular types of rails. A rail-less or non-rail-based system generally includes a component that does not extend the entire length or width of a solar panel, but rather, is a mounting structure that only attaches to a discrete portion of a solar panel, or discrete portions of adjacent solar panels, for example, at the adjacent corners of four adjacent solar panels arranged in a 2 by 2 orientation with two adjacent solar panels in a first row and two adjacent solar panels in a second row directly above or below the first row. Such a component may also be referred to as a micro-rail. A short micro-rail only attaches to a discrete portion of a solar panel, or to discrete portions of at-most two adjacent solar panels. Thus, in a rail-less or non-rail-based system, each component that can support a solar panel connects together only immediate next-door neighbor solar panels. As described above and as will be further described below, these immediate next-door neighbor solar panels are a maximum of four when a micro-rail is used, and three in an installation where the micro-rail is used around an obstacle in the mounting surface, and two when a short micro-rail is used. In contrast, in a rail-based system, the component that can support a solar panel, i.e., the rail, can also connect together remote panels. Remote panels are not immediate next-door neighbors to each of the connected panels. Thus, connected remote panels have one or more intermediate panels separating them. As will be further discussed below, utilizing a rail-based system component, e.g., a rail, in the front row of a solar panel array provides a benchmark or baseline to construct the remaining solar array with the modules being in a more stable position and it is easier to align and square the array and the modules. Also, having the first (lower-most) structure mounted to the roof being a structurally stiff and strong piece of racking (i.e., a rail, which may be a trim-rail), makes it safer for the installer to stand on a steeply pitched roof. By also using rail-less or non-rail-based system components in the rest of the array, this allows the installer the flexibility to work around obstructions, e.g., vents, skylights, etc., without needing to cut/modify a rail. This also allows for mixing of the orientation of the solar panel modules within a row. Thus, in the hybrid solar panel mounting assembly of the present invention, a combination of rail-based system components and rail-less system components are used to mount a plurality of solar panels in a solar panel array to a surface. Below is provided exemplary embodiments of components of rail-based systems and non-rail-based systems that may be utilized in the hybrid solar panel mounting system of the present invention. However, the present invention is not limited to these particular embodiments of components of rail-based systems and non-rail-based systems. Rail-Based System Components Trim-Rail Assembly FIG.1illustrates a trim-rail assembly10in accordance with the principles of the present invention. The trim-rail assembly10includes a trim-rail100, a splice200, a connector300, a mounting bracket, or footer,400, and a track500. The trim-rail100can be further seen inFIG.2. Trim-rail100includes both a rail110and a trim120, where the rail110and trim120are integrated as a single, monolithic structure. Thus, the trim-rail100includes a rail110that extends an entire length or width of at least one solar panel of a plurality of solar panels that are utilized in a solar panel array. The rail110of the trim-rail100mounts the solar panel(s) to a surface, such as the roof of a home or building. Since the rail110extends the entire length or width of at least one solar panel of a plurality of solar panels that are utilized in a solar panel array, so does the trim120. Rail110can have an “I-beam” shape in cross-section. InFIG.2, trim120has a generally curved surface which extends downwardly and outwardly from the top of the trim-rail100to a lower portion of the trim-rail100and then downwardly to a lowest-most portion of the trim-rail100. Trim-rail100can be an extruded product. Thus, inFIG.2, the trim120can provide for an aesthetically-pleasing front surface for the trim-rail100when the trim-rail100is used as the front-most rail in the hybrid solar panel mounting assembly of the present invention. Additionally, the trim-rail100can also assist in providing for a fire protection mechanism by further restricting the flow of air under the trim-rail100, and thus under the photovoltaic module(s) that are mounted on the trim-rail100. Thus, inFIG.2, because the rail110and the trim120of the trim-rail100are a single, monolithic integrated structure, there is no need to mount the trim120on a separate rail. The integrated structure of the trim-rail100provides for both mounting a solar panel(s) to a surface by the rail110and providing a trim120for the rail. Further yet because the trim120and the rail110are a single integrated structure, the trim120is part the rigid structure of the trim-rail100, and thus, it is also a rigid structure itself. As such, the trim120also directly supports the solar panel modules. In some embodiments, the wall thickness of trim120can be the same as the wall thickness of rail110. InFIG.2, the rail110includes a first track112A and a second track112B at a bottom of the rail110. The bottom of the rail is the portion of the rail that is closest to the mounting surface. As will be further discussed below, the tracks112A,12B are able to receive within them mounting hardware that is used to mount the rail110, and thus trim-rail100, on the footer400. The tracks are provided on both sides of the rail110so that the footer400may be mounted on either side of the rail110. InFIG.2, a vertical wall114, i.e., vertical with respect to the surface on which the trim-rail100is mounted, is provided extending from the bottom of the rail110. Extending perpendicularly from the vertical wall114are lower ledge114A and upper ledge114B. Lower ledge114A extends further from wall114than upper ledge114B. An edge of a solar panel(s) that is mounted on trim-rail100is positioned on trim-rail100between ledges114A,114B. The bottom of the solar panel is supported on lower ledge114A and the top of the solar panel is disposed under, and in engagement with, upper ledge114B. Thus, the edge of the solar panel is secured on trim-rail100between lower ledge114A and upper edge114B of rail110. InFIG.2, trim-rail100also defines a hollow chamber116which is bounded by trim120, vertical wall114, and a bottom wall116A. FIG.3further illustrates an embodiment of splice200. Splice200is used to splice together two adjacent trim-rails100. As can be understood, and as can be seen inFIG.1, a first end of the splice200is received within hollow chamber116of a first adjacent trim-rail100. A second end of the splice200would be received within a hollow chamber116of a second adjacent trim-rail100. Thus, the splice200rigidly joins a first trim-rail to a second adjacent trim-rail. InFIG.3, the splice200has a structure that is complementary to the trim-rail100. Thus, the splice200has a trim-like portion200A that has a contour that is complementary to trim120of trim-rail100. Thus, when splice200is received within hollow chamber116of a trim-rail100, the trim-like portion200A of splice200generally engages with the inside wall of trim120of trim-rail100. Similarly, inFIG.3, the splice200has a vertical wall200B. Thus, when splice200is received within hollow chamber116of a trim-rail100, the vertical wall200B of splice200generally engages with the inside wall of vertical wall114of trim-rail100. Thus, inFIG.3, the splice200is firmly engaged within respective hollow chambers116of adjacent trim-rails100. Although not required, inFIG.4, splice200can be further secured within the adjacent trim-rails100by use of respective connector300. As such, splice200also has a structure210that receives within it a portion of connector300, which can also be further seen inFIG.4. Structure210includes slot211. Connector300includes two straps301A and301B. The two straps301A and301B are bent such that they are received with slot211and engage into splice200to secure connector300on splice200. InFIG.2, trim-rail100also includes upper flange118A and lower flange118B on vertical wall114and connector300includes an upper strap302A and a lower strap302B. Upper strap302A engages with upper flange118A to prevent the connector300from being slipped any further into trim-rail100. Lower strap302B then engages with the outer edge of wall114and lower flange118B. InFIG.1, at least portions of connector300engage into both trim-rail100and splice200to electrically bond the trim-rail100to the splice200. These portions can be the respective straps301A,301B. As mentioned above,FIG.1shows an embodiment of footer400and track500. The footer400is variably positionable on the trim-rail100along either slot112A or112B. The footer400is generally L-shaped with a first, upright leg401and a second, flat leg402. The upright leg401is “upright” in the sense that it extends perpendicularly to the surface on which the footer400is mounted. The flat leg402is “flat” in the sense that it extends parallel to the surface on which the footer400is mounted. The upright leg401contains at least one aperture, through which a securement mechanism, which may be a bolt and a nut, extends. As shown inFIG.1, two, or more, apertures may be provided, such that the position of the trim-rail100with respect to the upright leg401of the footer400may be adjusted by use of the securement mechanism in the different apertures. The shaft of the bolt extends through an aperture of the upright leg401and the nut, or other structure, of the securement mechanism is disposed within the slot112A of trim-rail100, or slot112B if the footer400is placed on the opposing side of the trim-rail100. As the bolt is threaded down on the nut, the footer400is secured at a position on the trim-rail100along the slot112A. The flat leg402of the footer also contains an aperture, and an additional securement mechanism, which may be a lag bolt, extends through the aperture and into a slot501of the track500, in the same manner as discussed above with respect to the slot of the trim-rail100, such that the footer400is also variably positionable on the track500along the slot501of the track. Thus, as discussed above inFIG.1, the footer400is variably positionable on both the trim-rail100along a slot, and the track500along a slot, via the respective securement mechanisms that are disposed through the footer400and are received in the respective slots. By loosening the nuts on the bolts, while the nuts remain in the slots, the footer and securement mechanisms may be moved and positioned anywhere along the longitudinal length of the trim-rail and the track, and then tightened to secure the footer400on the trim-rail100and track500at a desired positioned. This provides a benefit since, as will be further discussed later in this specification, the footer is not constrained to a single position on the trim-rail or track, but rather, it can be variably positioned on the trim-rail and track. FIG.5provides another embodiment for the trim-rail assembly10of the present invention. This embodiment also includes a trim-rail100, splice200, connector300, and track500, as in the embodiment ofFIG.1. As can be seen inFIG.5, the footer400has a different configuration. Footer400of the embodiment ofFIG.5includes slots410that mate with a tab(s)119in the trim-rail100in a tongue-and-groove type mating configuration. The horizontal slots are positioned one above the other vertically on the footer and may extend the entire length of the upright leg. As such, the vertical position of the trim-rail100with respect to the footer400can be variably adjusted by engaging the tab119of the trim-rail100in different slots410of the footer400. Further, the mating of the slots and the tab(s) can provide for a stronger structural connection between the footer and the trim-rail. As discussed above, a single tab can be received within a slot or multiple tabs can be received within multiple slots. Further, inFIG.5, the footer400does not have to include an aperture in the flat leg to receive a securement mechanism, which may be a lag bolt, to extend through the aperture and into the slot of the track. The footer may have an aperture defined by a separate structure403that is integrated between the upright leg and flat leg, as can be seen inFIG.5. The structure403has a diagonal surface that extends (e.g., at 45 degrees) from the upright leg in a direction down to the flat leg. Additionally in the embodiment ofFIG.5, the splice200has an extension220of the body at the lower end of the splice. This extension is received with a track of the trim-rail100. This can provide for a stronger structural connection between the splice and the trim-rail. Extension220also covers slot112B from direct view. Dual Track Rail and Triple Track Rail Rail-Based Systems This embodiment of a rail-based system includes one or more dual track rails, which can be also referred to as a single rail, and one or more unique clamps that may be interconnected to a footing grid. This embodiment is also disclosed in U.S. Pat. No. 8,128,044, the disclosure of which is expressly incorporated by reference herein. FIG.6illustrates the rail-based system for removably and adjustably mounting a device on a surface in an operative environment. As shown, the system is an apparatus for removably and adjustably mounting one or more photovoltaic modules on a surface such as a roof. Referring initially toFIG.6, the system for removably and adjustably mounting a device on a surface is shown and generally designated10. The system for removably and adjustably mounting a device on a surface10includes at least one rail12. In a preferred embodiment, at least one rail12is formed of extruded aluminum, but the material used is not a material consideration to the invention. As shown perhaps best by cross-reference betweenFIGS.8-12, at least one rail12is formed with at least two tracks14a,b, i.e., it is a dual track rail. Both of at least two tracks14a,binclude a channel16a,b, perhaps best shown inFIGS.8and9, extending the length of at least one rail12substantially coincident with the longitudinal axis of at least one rail12. Each channel16a,bin at least two tracks14a,bis formed with a slot18a,b. Slots18a,bextend the length of at least one rail12substantially coincident with the longitudinal axis of at least one rail12. In addition, slot18ain channel16aof at least one rail12is formed substantially at a right angle A to slot18bin any other of at least two tracks14a,b, as shown diagrammatically inFIG.8. As shown inFIGS.8,9and12, at least one rail12is formed with a body20. Body has a proximal end22, a distal end24, and a hollow chamber26between proximal end22and distal end24of body20. Hollow chamber26contributes to the light weight yet structural rigidity of at least one rail, and therefore to its ease of handling during installation of system for removably and adjustably mounting a device on a surface10. In a preferred embodiment, at least one rail12also is formed with opposing sides28a, band opposing shoulders30a,b. As further shown inFIG.8, body20includes channel16bformed in opposing side28bfor slidably engaging the rail on hardware described below. Channel16bis formed with slot18bextending along the longitudinal axis of at least one rail12. In a preferred embodiment, slot18a,balso includes opposing jaws32a,bmonolithically protruding from slot18a,bsubstantially along the longitudinal axis of the channel16a,b. Body20further includes channel16a. Channel16ais formed in opposing shoulder30aas shown inFIGS.8and9. Channel16aalso contributes, in combination with channel16b, to making at least one rail12slidably engageable with the one or more footings36. As will be apparent to a person skilled in the art, channel16aand channel16benable at least one rail12to be slidable engageable with one or more footings36. As also shown by cross-reference amongFIGS.13-16, a system for removably and adjustably mounting a device on a surface10also includes one or more clamps34a,b. As shown best by reference toFIGS.13and15, one or more clamps34aare formed as a duct42. Duct42includes at least two opposing flanges44a,b. Opposing flanges44a,bof one or more clamps34aare substantially perpendicular to one another. One or more clamps34amay also be described as formed with a plate46and monolithic opposing side walls48extending substantially in the same direction at substantially right angles B from plate46. Opposing side walls48include a lower inner edge50and an upper face52. A fin54extends from upper face52substantially along the longitudinal axis of one or more clamps34a,b. One or more clamps34aalso includes at least one hole56through plate46for securing one or more clamps34aas described below. In an alternative embodiment of one or more clamps, one or more clamps34bis formed with a leg58having a base60as shown best inFIG.16. From base60of leg58a descending member62monolithically extends from base60. In addition, from base60of leg58an ascending member64monolithically extends from base60in a direction substantially opposite the direction of descending member62. As also shown inFIG.16, one or more clamps34binclude means66for connecting base60to at least one rail12. One or more clamps34balso includes means70for variably positioning one or more clamps34bin channel16aof at least one rail12. FIG.6also shows a device68that may be mounted on surface40using the rail-based system. In a preferred embodiment of the present invention, device68is a photovoltaic module68′, also shown inFIG.7. Photovoltaic module68′ is formed with an edge72. In a photovoltaic environment for application of the rail-based system, edge72holds one or more photovoltaic panels74. As also shown best inFIGS.6and7, footing grid38includes one or more footings36. In combination, the one or more footings36compose a network of keepers76. In the preferred embodiment, each of the network of keepers76is L-shaped and constructed of metal. Neither the shape nor material of the keepers76is a material limitation of the system. Each of keepers76may be fastened to surface40. If surface40is a roof of a building, keepers76may be attached to surface40by inserting lag bolts (not shown) through keepers76into rafters78beneath surface40. Once installed, keepers76form a grid, as shown inFIG.1, on which at least one rail12of the present invention is removably connectable. Using the principal embodiment of the system, in operation one or more clamps34a,bare variably positionable not only on at least one rail12, but also on footing grid38for demountably securing module68′ to footing grid38, as shown by reference toFIG.6. As shown inFIG.14, a preferred embodiment of fin54a,bincludes a serrated surface55that grips edge72of module68′ with significant torsional rigidity, but because of the use of conventional hardware for attaching one or more clamps34a,bto edge72of module68′, one or more clamps34a,bare quickly and safely repositionable. As further shown by cross-reference betweenFIGS.6and9, channel16a, during installation, may be slidably engaged with at least one rail12and to footing grid38. As shown inFIG.9, slot18aincludes opposing jaws32a,bmonolithically protruding from slot18asubstantially along the longitudinal axis of channel16a. Jaws32a,bcontribute to making one or more clamps34a,bslidable and removably engageable, and therefore allow the system to be not only mounted, but reconfigured on surface40. Channel16balso contributes, in combination with first channel16a, to making at least one rail12slidably engageable, and repositionable, with one or more clamps34a,b. As will be apparent to a person skilled in the art, channel16aand channel16benable at least one rail12to be slidable engageable with not only one or more clamps34a,b, but also with footers36comprising footing grid38. While the system for removably and adjustably mounting a device on a surface10as shown in drawingFIGS.6through16is one embodiment of the rail-based system, it is only one such embodiment, it is not intended to be exclusive, and is not a limitation of the system. The particular system for removably and adjustably mounting a device on a surface as shown and disclosed in detail in this instrument is fully capable of obtaining the objects and providing the advantages stated, but this disclosure is merely illustrative of the presently preferred embodiments of this system invention, and no limitations are intended in connection with the details of construction, design or composition. Further optimizations in connection with the system are achieved by including features and elements desirable for increasing the range and variety of different applications and environments in which the system may be used. In at least one such additional optimization of the system, an apparatus and method for positioning a module on an object is provided. The rail-based system includes one or more rails having at least three rails (a “triple track rail” or “triple track rails”) used in combination with at least one connector bracket. FIG.17illustrates the apparatus for positioning a module on an object in an operative environment. As shown, the system includes an apparatus for removably and adjustably mounting one or more photovoltaic modules on an object such as a pole or roof. Referring initially toFIG.17, the apparatus for positioning a module on an object is shown and generally designated100. The apparatus100for positioning a module68′ on an object includes at least one rail102. In a preferred embodiment, at least one rail102is formed of extruded aluminum, but neither the materials used nor the extrusion method of manufacture is material to the system. As shown perhaps best by cross-reference amongFIGS.18,19A and19B, at least one rail102is formed with at least three tracks104a,b,c, i.e., it is a triple track rail which can be also referred to as a single rail. Two of at least three tracks104a,b,cinclude a channel106a,b. For illustrative purposes, as best shown by cross-reference amongFIGS.18,19A and19B, two of the at least three tracks104a,b,care shown with channels106a,bextending the length of at least one rail102substantially parallel to the longitudinal axis of at least one rail102. Each channel106a,bin at least two tracks104a,bis formed with a slot108a,bthat for illustrative purposes are shown as slots108a,b. Slot108a,bextends the length of at least one rail102substantially parallel to the longitudinal axis of at least one rail102. In addition, slot108ain channel106aof at least one rail102is formed substantially at a right angle A to slot108bas shown diagrammatically inFIG.19B. As shown inFIGS.18,19A and19B, at least one rail102also is formed with a body110. Body110has a proximal end112, a distal end114as best shown inFIG.18, and a hollow chamber116between proximal end112and distal end114of body110as best shown inFIG.19B. Hollow chamber116contributes to the light weight yet structural rigidity of at least one rail, and therefore to its ease of handling during installation of apparatus while positioning a module68′ on an object. In a preferred embodiment, as best shown inFIGS.18and19B, at least one rail102also is formed with opposing sides118a,band opposing shoulders120a,b. In operation, as further shown inFIGS.19B and20, tracks104a,bpermit at least one rail102to be slidably engageable on hardware described below. In a preferred embodiment, as shown by cross-reference betweenFIGS.18and19B, slot108a,balso includes opposing jaws122a,bmonolithically protruding from slot108a,bsubstantially along the longitudinal axis of channel106a,b. Channel106ais formed in opposing shoulder120aas shown inFIG.19B. Channel106aalso contributes, in combination with channel106b, to making at least one rail102slidably engageable with the one or more footers36. Apparatus for positioning a module on an object100, as shown by cross-reference betweenFIGS.18and19B, also includes a cavity124formed in body110of at least one rail102. Cavity124is formed through at least one opposing side118a,b, and for illustrative purposes is shown inFIG.19Bas being formed through at least one opposing side118b. As also shown inFIG.19B, an opening126is formed in opposing side118b. Opening126in opposing side118bis defined by a boss128also formed in opposing side118bas well as by a shelf130. In a preferred embodiment, shelf130is formed monolithically from edge132in opposing side118bthat is opposite boss128. Shelf130also extends monolithically into hollow chamber116to form a partition134that is best shown inFIG.19B. Partition134merges monolithically into beam136in slot108a, as best shown inFIG.19B. In addition, as also shown inFIG.19B, a beam138extends through hollow chamber116between opposing sides118a,bof rail102. In operation, beam138resists compressive and similar forces applied against rail102, thus enhancing the rigidity and longevity of apparatus for positioning a module on an object100when installed. Also in a preferred embodiment, hollow chamber116is formed with a substantially semicircular passage140, as best shown inFIGS.18and19B. In operation, use of semicircular passage140instead of, for example, a passage having a rectangular shaped cross-section, also contributes to resisting compressive and other forces on apparatus for positioning a module on an object100after installation and mounting of rail102on module68′. In a preferred embodiment, at least one semicircular groove142is formed in at least one of the opposing sides118a,bas shown inFIG.18, for assisting an installer in drilling one or more additional holes (not shown) through opposing sides118a,bfor securing a mounting device (not shown) in which electrical or other lines may be secured. Also included in the rail-based system for positioning a module on an object100are one or more connector brackets144, as shown by cross-reference betweenFIGS.19B and20. One or more connector brackets144is formed to be demountably attachable to at least one rail102and to device68or module68′. To achieve that object, one or more connector brackets144is monolithically formed with a first flange146and a second flange148substantially at a right angle as shown diagrammatically as Angle B inFIG.20. First flange146is formed with a lip150. In addition, first flange146is formed with a bore152. In operation, bore152is provided for insertion of a fastener153through bore152to secure connector bracket144to device68or module68′. In a preferred embodiment, one or more connector brackets144further comprises an elbow154. Elbow154is substantially L-shaped, and extends monolithically at substantially a right angle from second flange148as shown diagrammatically as Angle C inFIG.20. Elbow154is shaped and configured for detachable engagement with cavity124formed in hollow chamber116of body110. As shown best inFIG.19B, elbow154is engageable with boss128as well as beam136. In operation, with respect toFIGS.17-21, as will be evident to one skilled in the art, the unique combination of one or more connector brackets144, cavity124, and three tracks104formed in at least one rail110(collectively, the “combined components”) permits installation of apparatus for positioning a module on an object100in a wide variety of alternative ways. For example, as shown inFIG.21, module68′ is typically formed with a collector side156and a back side158. The term “collector side” refers generally to that side of module68′ that collects solar energy radiation from the sun. The term “back side” refers generally to that side of module68′ that does not collect solar energy radiation from the sun. The combined components permit an installer to select module68′ having at least collector side156and back side158, constructed with at least two opposing edges160a,bhaving a plurality of holes162a,b. The combined components permit an installer to position module68′ collector side156down, mount at least one rail102on the back side158of module68′, and reposition the combined components collector side156up to install the combined components on the object68. Alternatively, the combined components allow an installer to install the components either top down or bottom up. Low Profile Rail Rail-Based System This embodiment of a rail-based system includes a low profile, shared rail. This embodiment is also disclosed in U.S. Pat. No. 7,600,349, the disclosure of which is expressly incorporated by reference herein. As shown inFIGS.22through34, a low profile mounting system is provided that in its broadest context includes at least one rail12, which can be a shared rail. At least one track14is formed in rail12with opposing jaws16ab. Opposing jaws16a,bdefine a slot18. Opposing jaws16a,bare disposed in rail12asymmetrically to the longitudinal axis of rail12and to each other. At least one ledge20monolithically extends from rail12for holding an object such as the frame22of a solar panel24. A coupler26is provided for demountably connecting solar panel24to rail12. A cleat28also is provided for attaching the low profile mounting system to a surface30. A connector connects rail12to cleat28. As shown inFIG.22, rails12a, bare mounted on a surface30. Surface30is a roof34.FIG.22also shows solar panels24a, bbounded by frames22a, b. During installation frames22a, bare connected to rails12a, b. Rails12a, bare secured to roof34. In general, rails12a, bare secured to roof34in part using footers or footings (in this document, a “footing36”). A number of footings36a, btraditionally have been used to secure rails12a, bto roof34. Footings36a, bmay be L-shaped and constructed of metal or other materials. Footings36a, bmay be attached to roof34by inserting lag bolts (not shown) through passages (not shown) in footings34a, binto rafters38beneath roof34. As also shown inFIG.22, in a conventional mounting configuration, solar panels24a, bare mounted top-down onto rails12a, b. This may present an aesthetically displeasing appearance because solar panels24a, band rails12a, bpresent an undesirably excessive elevation. What is desirable is to easily, quickly, and securely mount solar panels24a, bon a surface30that produces a low profile that is comparatively inconspicuous and as indiscernible as possible. Low profile mounting system10, as shown in different embodiments inFIGS.23through34, allows an installer to achieve a low profile that is comparatively inconspicuous and as indiscernible as possible. In the embodiment of low profile mounting system10illustrated by cross-reference betweenFIGS.23and24, rail12is shown to be mountable on a surface30known as a stanchion or stand-off (in this document, a “stanchion40”) rather than on roof34. Stanchion40is useful because of the aforementioned variety of materials used to manufacture a roof34and coverings for roof34. For example, if the covering for roof34is made of tile, bolting a rail12directly to a tile on roof34, through a tile (not shown), is undesirable because the tiles may crack or break. To avoid that problem, one or more tiles are removed, stanchion40is installed on roof34, and solar panel24is attached to stanchion40. To achieve a lower profile than conventional installation apparatus allow, in the embodiment of low profile mounting system illustrated by cross-reference betweenFIGS.23and24, rail12is shown to include at least one ledge20. As shown, rail12is formed with an upper surface44, a lower surface46, and opposing walls48a,bmonolithically connected to upper surface44and lower surface46. At least one ledge20extends at a substantially right angle from opposing walls48a,bin opposite directions from the longitudinal axis through rail12. Rather than mount solar panel24top-down, thus raising the total elevation of an installed mounting system, at least one ledge20ballows installation of frame22of solar panel24closer to surface30. As also shown in the embodiment shown inFIGS.23and24, rail12includes plurality of tracks14a, b. Plurality of tracks14a, bis formed in rail12with opposing jaws16a-ddefining slots18a, b. In addition, in the embodiment shown inFIGS.23and24, opposing jaws16a, band opposing jaws16c, dare disposed in rail12asymmetrically to each other and to the longitudinal axis of rail12. The term “asymmetrically” as used in this document means that slot18ais directionally disposed differently than slot18b. As indicated, at least one coupler26is provided. Coupler26includes an attachment device50. In the embodiment shown inFIGS.23and24, attachment device50is a first bolt52and a first nut54. Coupler26also includes a clamp56. Clamp56, as shown inFIGS.23and24, is substantially a U-shaped gutter56aformed with an orifice58and opposing fins60. The head62of first bolt52is slidably insertable into slot18aof track14to extend through opposing jaws16a, band, by deploying first nut54on first bolt52, U-shaped gutter56amay be clamped into ducts64a, bformed on a conventional frame22of solar panel24. Clamp56as shown in all embodiments of low profile mounting system10may be a short segment, or may extend the entire length of rail12to enhance the aesthetic appearance of an installed low profile mounting system10, and to aid in resisting wind and rain penetration into the components of low profile mounting system10. FIGS.23and24also show that a second bolt66and a second nut68are included. Head70of second bolt66is slidably insertable into track14bto extend through slot18b. An opening72is provided in an extension74of stanchion40. Second bolt66is inserted through opening72, second nut68is inserted on second bolt66, and the embodiment of low profile mounting system10as shown inFIGS.23and24is securely attached to stanchion40, which in turn has been attached to roof34. Solar panel24thus provides a low visual profile. In the embodiment low profile mounting system10illustrated by cross-reference toFIGS.25and26, low profile mounting system10is shown to include a plurality of ledges20a, bon rail12for holding a pair of solar panels22aand22b. In this sense, mounting system10is a “shared” rail system.FIGS.25and26also show an embodiment of low profile mounting system10that includes at least one cleat28. Further, the embodiment shown inFIGS.25and26shows a clamp56bin the form of a substantially flat planar surface or plate76. Clamp56bis another embodiment of clamp56useful in providing a pleasing configuration to an assembled low profile mounting system10and for securing ducts64a, bof a plurality of frames22a, bon plurality of ledges20a, bon rail12. Further, cleat28includes at least one hole78. As shown, cleat28includes holes78a, b, c. Holes78a, bare used to attach cleat28to roof34using lag bolts or similar connectors. Hole78ais used to attach cleat28to rail12by inserting second bolt66into slot18band through hole78c, and attaching second nut68to second bolt66. As a result, a secure, easily installable, and aesthetically pleasing installation of low profile mounting system10is achieved. In another embodiment of low profile mounting system10, as shown inFIGS.27and28, an alternative clamp56is provided as clamp56c. Clamp56cis useful in connection with variations of frame22formed with a plurality of ducts64a, bas shown best inFIG.28. Clamp56calso is formed as a gutter, but with opposing arms80a, blong enough to be removably insertable into ducts64a, bto hold frame22of solar panel24tightly against ledge20a, bwhen locked into position using attachment device50. In the embodiment of low profile mounting system10illustrated inFIGS.29and30, clamp56a, as shown by cross-reference betweenFIGS.23and24in connection with a single frame22of solar panel24being attached to stanchion40, is shown to be equally useful when disposed in a configuration in which a plurality of opposing frames22c, dare mounted on a rail12that in turn is mounted on cleat28for attachment to roof34. In another embodiment of low profile mounting system10, as shown by cross-reference betweenFIGS.31and32, rail12is shown with a track14band a longitudinal cavity82formed in upper surface44of rail12c. As shown, longitudinal cavity82is shaped to receive an attachment device50. Attachment device50, as shown inFIG.32, includes first bolt52. A receptor body84also is monolithically formed adjacent longitudinal cavity82. As shown inFIG.32, first threads86are formed in receptor body84for matable connection with second threads88formed on first bolt52. Further, as also shown inFIG.32, clamp56dis formed with a contoured cross-sectional configuration for both aesthetics and for gripping frame22of solar panel24a, b, and includes parallel nubs90a, b. Parallel nubs90a, bare designed to fit tightly along exterior surfaces92a, bof longitudinal cavity82. In the embodiment of low profile mounting system10illustrated inFIGS.33and34, longitudinal cavity82ais shown to be useful as a scribe guide94for inserting into rail12an attachment device50in the form of a screw50e. As shown, receptor body84also includes a groove96. As also shown, two detents98a,bare formed in receptor body84. A variation of clamp56d, namely56e, is provided with comparatively longer parallel nubs90c, dthat are insertable into two detents98a, bin receptor body84. Receptor body84also includes opposing fins100a,b. Screw50eis removably insertable through clamp56einto receptor body84. Screw50eextends into the chamber102formed in rail12. Screw50eis held in place in part by opposing fins100a,b. In all embodiments shown inFIGS.22through34, end plates104, as best shown inFIG.31, may be placed across low profile mounting system10to further add to the aesthetic appearance of an assembled low profile mounting system10, and to preclude entry of water, wind, and other elements into low profile mounting system10. AlthoughFIGS.22through34shows embodiments of low profile mounting system10in which components of low profile mounting system10are in certain positions in relationship to one another, the components may be located in any number of other positions. Although the number of alternative attachment devices and connectors are shown, other fasteners may be used. The low profile mounting system shown in drawingFIGS.22through34includes a number of non-exclusive embodiments that are merely illustrative of the disclosed low profile mounting system10. Rail-Less or Non-Rail-Based System Components FIG.35is a cross-section of an embodiment of a rail-less or a non-rail-based system or apparatus10for mounting photovoltaic modules, with a photovoltaic module1mounted thereon, in accordance with an embodiment of the rail-less system. This embodiment of a rail-less or non-rail-based system is also disclosed in U.S. patent application Ser. No. 14/515,990, filed on Oct. 16, 2014, the disclosure of which is expressly incorporated by reference herein. InFIG.35, the apparatus10includes a bracket100(micro-rail), a clamp200, and a footer400. An attachment mechanism300secures the clamp200to the bracket100. InFIG.35, the bracket100defines slots112A and112B on opposing sides of the bracket100in a lower portion110A of the bracket100. Slots112A and112B extend along an entire longitudinal length L of the bracket100, as can be seen at least inFIG.36. InFIG.35, the bracket100includes a first ledge120on a first side110C of the bracket100and a second ledge122on a second, opposing side110D of the bracket100. The opposing sides extend along the longitudinal length of the bracket100and between the lower portion110A and an upper portion110B of the bracket100. The bracket100defines a cavity130between the upper portion110B of the bracket100and the lower portion110A of the bracket100and includes an extension member140on the upper portion110B of the bracket100. The extension member140defines a cavity142within the extension member140. InFIG.35, as mentioned above, the apparatus10also includes a clamp200that is securable onto the bracket100and on the upper portion110B of the bracket100. The clamp200includes two opposing legs210,212where the extension member140of the bracket100is disposed between the two opposing legs210,212of the clamp200when the clamp200is secured to the bracket100. A plurality of attachment mechanisms300, as can be seen inFIG.36, secure the clamp200to the bracket100on the upper portion110B of the bracket100. The attachment mechanisms may be bolts or screws. InFIG.35, the clamp200also includes a first wing220on a first side200A of the clamp200and a second wing222on a second side200B of the clamp200. As will be further discussed below, the wings220,222cooperate with the ledges120,122of the bracket100, respectively, to secure multiple photovoltaic modules in the apparatus10. Clamp200also extends along the entire longitudinal length L of the bracket100, as can be seen inFIG.36, and thus, along the entire longitudinal length of the apparatus10. InFIG.35, the apparatus10also includes a footer400, as mentioned above. The footer400is variably positionable on the bracket100along either slot112A or112B, as can be further seen inFIGS.36-42. The footer400is generally L-shaped with a first, upright leg401and a second, flat leg402. The upright leg401is “upright” in the sense that it extends perpendicularly to the surface on which the footer400is mounted. The flat leg402is “flat” in the sense that it extends parallel to the surface on which the footer400is mounted. The upright leg contains at least one aperture, through which a securement mechanism410, which may be a bolt and a nut, extends. As shown inFIG.36, two, or more, apertures may be provided, such that the position of the bracket100with respect to the upright leg401of the footer400may be adjusted by use of the securement mechanism in the different apertures. The shaft of the bolt extends through an aperture of the upright leg401and the nut, or other structure, of the securement mechanism410is disposed within the slot112A of bracket100, or slot112B if the footer400is placed on the opposing side of the bracket100. As the bolt is threaded down on the nut, the footer400is secured at a position on the bracket100along the slot112A. The flat leg402of the footer also contains an aperture, and an additional securement mechanism, which may be a lag bolt, extends through the aperture and into a roof structure, e.g., a rafter, to secure the flat leg402, and thus the footer400, to the roof structure. Thus, inFIG.35, as discussed above, the footer400is variably positionable on the bracket100along the slot112A via the securement mechanism410that is disposed through the footer400and is received in the slot112A. By loosening the nut on the bolt, while the nut remains in slot112A, the footer and securement mechanism may be moved and positioned anywhere along the longitudinal length of the bracket, and then tightened to secure the footer400on the bracket100at a desired positioned. This provides a benefit since, as will be further discussed later in this specification, the footer is not constrained to a single position on the bracket, but rather, it can be variably positioned on the bracket such that it can be co-located at the position of a roof structure, e.g., a rafter, to which the footer is to be mounted. InFIG.35, further included in apparatus10are first bonding clip500and second bonding clip510. First bonding clip500, and first and second bonding clips500,510, can be seen inFIG.35Aand at least inFIG.36. The first bonding clip500and the second bonding clip510are both disposed only on the first side110C of the bracket100and are disposed on opposing longitudinal ends of the first ledge120of the bracket100. Bonding clips500,510include similar structure, and as can best be seen inFIGS.1A and1B, the first bonding clip500, and thus second bonding clip510, includes teeth512on an upper side520and a lower side522of the bonding clips. As can be particularly seen inFIG.35A, the first bonding clip500and the second bonding clip510are each formed generally in a U-shape. As can be seen at least inFIG.35andFIG.35B, the first ledge120of the bracket100includes a depression120A on its upper side and a portion of the first bonding clip500is disposed in the depression120A. Similarly, a portion of the second bonding clip510is also disposed in the depression120A at an opposite longitudinal end of the depression120A. As will be further discussed below, bonding clips500,510electrically bond the photovoltaic modules to the apparatus10. As can be seen at least inFIG.37, the first ledge120of the bracket100, the second ledge122of the bracket100, the first wing220of the clamp200, and the second wing222of the clamp200each extend along the entire longitudinal length of the apparatus10. With this structure of the apparatus10, as can be seen when considering at leastFIG.35,FIG.36, andFIG.44, a first photovoltaic module land a second photovoltaic module2are mountable on the first side110C of the bracket100and the first side200A of the clamp200between the first ledge120of the bracket100and the first wing220of the clamp200where the first photovoltaic module1is adjacent to the second photovoltaic module2. InFIG.35, the he securement mechanisms300are threaded into respective apertures in clamp200and extension member140of bracket100to lower the clamp200with respect to bracket100, and thus, clamp the photovoltaic modules1,2between the first ledge120of bracket100and first wing220of clamp200. Securement mechanisms300also electrically bond the clamp200to the bracket100. As can be understood when consideringFIG.36, when the first photovoltaic module land the second photovoltaic module2are clamped between the first ledge120and first wing220, the teeth512on the upper side520of bonding clip500engage with the first photovoltaic module land the teeth512on the lower side522of bonding clip500engage with ledge120. Similarly, the teeth512on the upper side520of bonding clip510engage with the second photovoltaic module2and the teeth512on the lower side522of bonding clip510also engages with ledge120. As such, the photovoltaic modules1,2are electrically bonded to the apparatus10through bonding clips500,510. As can also be understood particularly when consideringFIGS.43and44, on the opposing, second side110D of the bracket100and the opposing, second side200B of the clamp200, a third photovoltaic module3and a fourth photovoltaic module4are mountable on the second side110D of the bracket100and the second side200B of the clamp200between the second ledge122of the bracket100and the second wing222of the clamp200, where the third photovoltaic module3is adjacent to the fourth photovoltaic module4. As such, the apparatus10can be disposed between 3 or 4 photovoltaic modules of an array of photovoltaic modules to mount the 3 or 4 photovoltaic modules to a roof structure. Thus, respective corners of the 3 or 4 photovoltaic modules are secured in the apparatus10. If the apparatus10is used on the edge of the array, only 2 photovoltaic modules are mounted in the apparatus on one side of the apparatus. FIG.37is a perspective view of the apparatus10for mounting photovoltaic modules ofFIG.35in a first position of the footer400with respect to the bracket100. As discussed above, the footer400is variably positionable on the bracket100along the slot112A. As shown inFIG.37, the footer400is positioned at the far left side of the bracket100along slot112A in this Figure. FIGS.38and39show the footer400positioned at other locations on the bracket100along the slot112A. InFIG.38, the footer400is positioned in the middle of the bracket100along slot12A and inFIG.39the footer400is positioned at the far right side of the bracket100along slot112A. It is only required that one footer be used in the apparatus10. FIGS.40-42correlate toFIGS.37-39, respectively, regarding the positioning of the footer400with respect to the bracket100. As can be understood, when the apparatus is used on a roof to mount photovoltaic modules on the roof, the bracket100may not always align with a rafter A of the roof at the same position on the bracket100. Thus, with the present invention, the footer400is variably positionable on the bracket100such that the position of the footer400can be co-located with the position of the rafter A. FIG.43illustrates an alternative embodiment of an apparatus10A for mounting photovoltaic modules in accordance with the principles of the present invention. The same reference characters are used for the same elements for the embodiments ofFIGS.35and43. As can be seen, the apparatus10A ofFIG.43includes the same elements as the apparatus10ofFIG.35. A difference between the embodiments is the longitudinal length A of the apparatus of the two embodiments. In the embodiment ofFIG.43, the longitudinal length A of apparatus10A is much shorter than the longitudinal length of apparatus10, thus it can generally be referred to as including a “short micro-rail”, which can be about 3″ long. This is because, as can be seen inFIG.44, and as discussed above, apparatus10(with a micro-rail) can be used to mount three-four photovoltaic modules in both the East-West (E-W) direction and the North-South (N-S) direction. Apparatus10A (with a short micro-rail) is only used to mount at-most two photovoltaic modules in the N-S direction at the E-W ends of the photovoltaic array. Thus, the apparatus10is longer (e.g., 17.5 inches) than apparatus10A (e.g., 3 inches) to provide greater support for the mounted photovoltaic modules. Another difference is that apparatus10A may only include a single bonding clip500. As discussed above, inFIG.43, the apparatus10A includes the same elements as apparatus10. Thus, apparatus10A includes a short bracket100(short micro-rail), a clamp200, and a footer400(not shown inFIG.43). An attachment mechanism300secures the clamp200to the bracket100. InFIG.43, the bracket100defines slots112A and112B on opposing sides of the bracket100in a lower portion110A of the bracket100. Slots112A and112B extend along an entire longitudinal length L of the bracket100. InFIG.43, the bracket100includes a first ledge120on a first side110C of the bracket100and a second ledge122on a second, opposing side110D of the bracket100. The bracket100defines a cavity130between the upper portion110B of the bracket100and the lower portion110A of the bracket100and includes an extension member140on the upper portion110B of the bracket100. The extension member140defines a cavity142within the extension member140. InFIG.43, the clamp200includes two opposing legs210,212where the extension member140of the bracket100is disposed between the two opposing legs210,212of the clamp200when the clamp200is secured to the bracket100. An attachment mechanism300secures the clamp200to the bracket100on the upper portion110B of the bracket100. InFIG.43, the clamp200also includes a first wing220on a first side200A of the clamp200and a second wing222on a second side200B of the clamp200. As can be further seen inFIG.44, a plurality of apparatuses10and10A can be used to mount an array of photovoltaic modules. As can be seen inFIGS.45-48, the apparatus10, and10A, may further include a trim assembly600. The trim assembly600includes trim610and a trim mounting bracket620. The trim mounting bracket620is mountable on the bracket100and the trim610is mountable on the trim mounting bracket620. As shown inFIG.45, the trim610is an elongated structure with a curved form. As shown inFIG.46, the trim mounting bracket620includes two trim mounting structures621,622. Both of these mounting structures621,622are generally U-shaped. Trim mounting bracket620also includes two bracket mounting structures623,624. Mounting structure623is generally U-shaped and mounting structure624includes two legs that both have an outwardly extending tab on the ends of the legs. As can be seen inFIGS.47and48, trim mounting bracket620is mounted on bracket100by engaging bracket mounting structure623on a ridge150of the bracket100and by engaging bracket mounting structure624in the slot112A of the bracket100. The outwardly extending tabs on the ends of the legs of mounting structure624engage behind structure of the bracket that defines slot112A. As such, the trim mounting bracket620may be easily positioned at different positions on the bracket100, i.e., adjusted East-West on the apparatuses, along slot112A. InFIG.48, An attachment device625, which may be a screw with a pointed end, is disposed through an aperture in trim mounting bracket620and within slot112A to engage with bracket100internal to the slot112A. The screw cuts into the bracket100to electrically bond the trim mounting bracket620to the bracket100. InFIG.48, the trim610is mounted in the trim mounting bracket620by placing a lower portion612of the trim610in the lower trim mounting structure622and by placing an upper portion614of the trim610in the upper trim mounting structure621. Thus, the trim610can be snapped into the trim mounting bracket620and no attachment holes are required in the trim610, thus aesthetically enhancing the trim. InFIG.48, an attachment device626, which may also be a screw with a pointed end, is disposed through an aperture in trim mounting bracket620and in engagement with the upper portion614of trim610that is disposed within trim mounting structure621. The screw cuts into the trim610to electrically bond the trim610to the trim mounting bracket620, and thus the bracket100. InFIG.48, a lowest-most portion600A of the trim assembly600extends below a lowest-most portion100E of the bracket100. As such, the trim assembly provides for a fire protection mechanism since the flow of air under the mounting apparatus10,10A, and thus under the photovoltaic modules that are mounted on the mounting apparatus10,10A, is restricted by the trim assembly600which extends below the bracket100. InFIGS.45-48, a longitudinal length of the trim610is much longer than the longitudinal length A of the apparatus10. As such, a single trim610can extend across numerous apparatuses10,10A, and thus, be mounted across numerous adjacently mounted apparatuses. Further, the position of trim610is East-West adjustable in the trim mounting bracket620depending upon the area it is to cover and can be cut to size depending upon the area to be covered. Also, due to the curved form of the trim610, adjacent trims610may overlap each other in a nestable/telescoping manner when installed, or during storage and shipping of the trims. The nestable/telescoping feature allows one size trim to fit a variety of photovoltaic module lengths regardless of portrait or landscape module orientation, without the need for cutting the trim to length; only positioning is required. Further, inFIGS.45-48, the East-West adjustability of the trim mounting bracket620on the apparatuses and the E-W adjustability of the trim610within the trim mounting bracket620are also benefits. Further yet, the trim610helps to provide alignment of a plurality of apparatuses10,10A that may be installed in a line, e.g., during installation of a first row of photovoltaic modules in an array. Additionally, inFIG.49, the apparatus10may also include a micro-inverter mounting bracket700, where the micro-inverter mounting bracket700is mountable on the bracket100. As can be seen inFIGS.49and50, the micro-inverter mounting bracket700is generally L-shaped with a first, upright leg701and a second, flat leg702. The upright leg701is generally perpendicular to the flat leg702. InFIG.49, the micro-inverter mounting bracket700, like trim mounting bracket620, is also mountable in the slot112A of the bracket100. The upright leg701of micro-inverter mounting bracket700has a micro-inverter mounting bracket mounting structure711at its lower end. This structure711is similar to structure624of trim mounting bracket620for mounting in slot112A. As such, mounting structure711also includes two legs that both have an outwardly extending tab on the ends of the legs. As can be seen inFIG.50, micro-inverter mounting bracket700is mounted on bracket100by engaging micro-inverter mounting bracket mounting structure711in the slot112A of the bracket100. The outwardly extending tabs on the ends of the legs of mounting structure711also engage behind the structure of the bracket that defines slot112A. As such, the micro-inverter mounting bracket700, like trim mounting bracket620, may be easily positioned at different positions on the bracket100, i.e., adjusted East-West on the apparatus. InFIG.49, an attachment device720, which may be a screw with a pointed end, is disposed through an aperture in leg701of micro-inverter mounting bracket700and within slot112A to engage with bracket100internal to the slot112A. The screw cuts into the bracket100to electrically bond the micro-inverter mounting bracket700to the bracket100. InFIG.49, the flat leg702of micro-inverter mounting bracket700includes a flange712that receives within it an end of a mounting plate801that is associated with a micro-inverter800. When the end of the mounting plate801is received within the flange712, the plate801rests on flat leg702. An attachment device722, which may be a screw or a bolt, is disposed through respective apertures in flat leg702and plate801to mount the micro-inverter800on the bracket100, and thus, apparatus10. This structure also serves to keep the micro-inverter at a proper height location relative to the roof, the apparatus, and the photovoltaic module that the micro-inverter is associated with. The attachment device722also electrically bonds the mounting plate801of micro-inverter800to the micro-inverter mounting bracket700. InFIG.49, also similar to trim mounting bracket620, micro-inverter mounting bracket700is East-West adjustable on bracket100. Further, the micro-inverter mounting bracket700may be installed on either side of mounting bracket100, i.e., either the North or South side. Hybrid Solar Panel Mounting Assembly As discussed above, the present invention provides a hybrid assembly for removably and adjustably mounting solar panels on a surface. The hybrid assembly consists of components of a “rail-based” system and components of a “rail-less” or “non-rail-based” system. As discussed, utilizing a rail-based system component, e.g., a rail, in the front row of a solar panel array provides a benchmark or baseline to construct the remaining solar array with the modules being in a more stable position and it is easier to align and square the array and the modules. By using rail-less or non-rail-based system components in the rest of the array, this allows the installer the flexibility to work around obstructions, e.g., vents, skylights, etc., without needing to cut/modify a rail. This also allows for mixing of the orientation of the solar panel modules within a row. Thus, in the hybrid solar panel mounting assembly of the present invention, a combination of rail-based system components and rail-less system components are used to mount a plurality of solar panels in a solar panel array to a surface. FIG.51illustrates a known configuration of a rail-less or non-rail-based system. As can be seen, a plurality of photovoltaic modules A are disposed in a solar panel array. A skirt1is disposed on the first row of the modules. However, this skirt is not capable of supporting the modules on a surface because the skirt is merely attached only to the modules, and not to the surface. The skirt is used for aesthetic purposes and for providing for a fire protection mechanism by restricting the flow of air under the photovoltaic modules on which the trim is attached. Further in the known configuration of the rail-less or non-rail-based system ofFIG.51, the system includes short micro-rails2(short brackets100discussed previously, e.g., inFIG.43) and micro-rails3(brackets100also discussed previously, e.g., inFIG.41), in addition to any other hardware described above for mounting the solar panels to the short micro-rails and micro-rails. As described above, two adjacent solar panel modules are mounted on the short micro-rails2and either two or four solar panel modules are mounted on the micro-rails3. Thus, only rail-less or non-rail-based system components are used in the known configuration ofFIG.51. Because the various rail-less or non-rail-based, and rail-based, system components have been described previously, and since the components are generally fully disposed under the solar panels of the solar panel array, the reference characters and reference lines that are associated with these components point to the locations of these components in the array in the various embodiments. FIGS.52-59disclose various configurations for the components of the hybrid solar panel mounting assembly of the present invention. As shown inFIG.52, the hybrid mounting assembly also includes short micro-rails2and micro-rails3. Two adjacent solar panel modules are mounted on the short micro-rails2and either two or four solar panel modules are mounted on the micro-rails3. However, the hybrid mounting assembly of the present invention also includes components of a rail-based system. In this embodiment, the component of the rail-based system is the trim-rail100described earlier in this specification inFIG.1, and represented inFIG.52by reference character4. As such, the trim-rail4is used as the front-most rail in the hybrid solar panel mounting assembly ofFIG.52, and thus, on the first row of solar panels in the array to mount the first row of solar panels. As such, trim-rail4provides a benchmark or baseline to construct the remaining solar array with the modules A being in a more stable position and it is easier to align and square the array and the modules. Use of the trim-rail4in the hybrid mounting assembly also provides the other benefits discussed previously in this patent application. In the context of the present invention, a rail, as defined above, is a component of a rail-based system. A micro-rail and a short micro-rail, as also defined above, are not components of a rail-based system since they are not rails. As such, the micro-rail and the short micro-rail, even though they contain the word “rail” in the names given in this specification for these components of a rail-less or non-rail-based system, are not components of a rail-based system, but rather, are components of a rail-less or non-rail-based system. As shown inFIG.53, the hybrid mounting assembly also includes short micro-rails2and micro-rails3, as used in the embodiment ofFIG.52. However, the hybrid mounting assembly of this embodiment also includes a rail5of a rail-based system, in addition to any other hardware described above for mounting the solar panels to the rail, as described in embodiments earlier in this specification, or which can be embodied as other embodiments of a rail. The rail5is only used to mount solar panels A that are disposed on one side of the rail5. Rail5extends the entire width of the solar panel array, encompassing three solar panels in this embodiment, and thus, three rows of solar panels, and is disposed on a North-South extending edge of the array. A trim on the front of the array is optional. The embodiment ofFIG.54uses a shared rail6on the first row of solar panels and also includes short micro-rails2and micro-rails3, as shown. The embodiment ofFIG.55uses two shared rails6on the first two rows of solar panels and also includes short micro-rails2and micro-rails3. Thus, the adjacent solar panels of the first two rows are mounted on the second rail5. The embodiment ofFIG.56uses a shared rail6on the first row of solar panels and also includes short micro-rails2and micro-rails3at the corners of a hole or obstruction in the solar panel array. Thus, here, the use of the micro-rails3allows the installer the flexibility to work around the hole or obstruction without needing to cut/modify any rails. However, the rail is still used in the assembly, as discussed above. The embodiment ofFIG.57uses shared rails6on the front edge of the first row of solar panels and on the back edge of the last row (at the North end) of solar panels. A trim-rail is used on the front edge of the first row of solar panels. The rails again extend across the three solar panels of the respective row. The assembly also includes short micro-rails2and micro-rails3. The embodiment ofFIG.58uses a shared rail6between the first two rows of solar panels and uses a trim-rail4on the front edge of the first row of solar panels. Thus, the adjacent solar panels of the first two rows are mounted on the rail5. Short micro-rails2and micro-rails3are also used. The embodiment ofFIG.59uses a trim-rail4on the first row of solar panels and also includes short micro-rails2and micro-rails3at the corners of a hole or obstruction in the solar panel array. Of course, other embodiments of combinations of components of a rail-based mounting system and a rail-less mounting system can be contemplated within the scope of the present invention. Additional Rail-Less or Non-Rail-Based System Components FIGS.60-62illustrate an embodiment of a height adjustable solar panel mounting assembly in accordance with the principles of the present invention. This height adjustable mounting assembly can be used as a micro-rail3and a short micro-rail2, i.e., brackets, of the present invention. As can be seen, the assembly3010includes an upper bracket3100, a lower bracket3200(which together form a mounting bracket for mounting solar panels), a stanchion3300, a helical drive3400, and a base (track)3500. First clamping bolt3602clamps the upper bracket3100down to lower bracket3200when one or more solar panels are installed in slots10A,10B. Second clamping bolt3302provides a clamping force to secure an “I”-shaped side clamp3310to a bottom portion of stanchion3300, i.e., when stanchion3300is secured onto base3500. Stop bar3220runs sideways across the width of lower bracket3200and serves as a stop to abut against, and align, the solar panel(s) when installed in slot10A. Stop bar3220also prevents the solar panel(s) from touching the upper portion of stanchion3300. Bonding pin3604is disposed in a hole located in recessed channel3222in lower bracket3200. Bonding pin3604serves to pierce the anodized aluminum coating on the solar panel and electrically interconnect (ground) the solar panel to the lower bracket3200of assembly3010. InFIG.61, the lower bracket3200has been removed from the view to more clearly illustrate helical drive3400disposed within stanchion3300. Stanchion3300includes two vertical arms: first arm3306and second arm3308. Disposed across the tops of arms3306and3308is an integral bridge segment3310which connects across the two tops. Second aperture3312, located below a clamping wing of upper bracket3100and having a centerline that is co-linear with first aperture3102, is disposed within bridge3310and provides vertical access for tool3600, e.g., an Allen wrench, to engage with a patterned, e.g., hexagonal, aperture3402in helical drive3400. FIG.62is a side view of the embodiment of the height adjustable solar panel mounting assembly3010shown inFIGS.60-61. Upper bracket3100includes a vertical wall3106that has a lower end that engages with a slot3201that is disposed within, and lays across the width of, lower bracket3200. Lower bracket3200includes an integral pair of symmetric stiffening ribs3202,3204disposed underneath the mounting plane3207of lower bracket3200, which serve to respectively stiffen the distal extents, i.e., wings3240,3242, of lower bracket3200. Hollow space3210is disposed (on both sides) in-between stiffening rib3202,3204and the horizontal plane (mounting plane3207) of lower bracket3200. Disposed in-between the two stiffening ribs3202,3204is an integral, rectangular “box”3206that mechanically surrounds, engages, and supports, i.e., couples, helical drive3400to lower bracket3200. The upper and lower interior horizontal ledges of box3206rest on, i.e., couple to, the upper and lower horizontal surfaces of drive3400, respectively. Support box3206transfers vertical motion of helical drive3400to vertical motion of lower bracket3200. In contrast to the embodiment ofFIG.62, in embodiments of the present invention, the upper bracket3100and the lower bracket3200can be manufactured as a single, monolithic, integral part. This can be manufactured as a single extrusion, for example. Additional Trim-Rail Assembly FIG.63illustrates a second embodiment of a trim-rail4000of the trim-rail assembly of the present invention with integrated clamping. Trim-rail4000includes both a rail4300and a trim4200and integrated clamping ledges4010,4030where the rail4300, trim4200, and clamping ledges4010,4030are integrated as a single, monolithic structure. Thus, the trim-rail4000includes a rail4300that extends an entire length or width of at least one solar panel of a plurality of solar panels that are utilized in a solar panel array. The rail4300of the trim-rail4000mounts the solar panel(s) to a surface, such as the roof of a home or building, via connection to a footer (not shown). Since the rail4300extends the entire length or width of at least one solar panel of a plurality of solar panels that are utilized in a solar panel array, so does the trim4200. Rail4300can have an “I-beam” shape in cross-section including a horizontal lower flange4110and a horizontal upper flange4120, both connected by a vertical web4140. InFIG.63, trim4200has a generally curved exterior surface4040that extends downwardly and outwardly from the top of the trim-rail4000to a lower vertical portion4050of the trim-rail4000and then downwardly to a lowest-most vertical portion4070of the rail4300. Trim-rail4000is a hollow beam, including a hollow interior volume (hollow chamber)4130. Trim-rail4000can be manufactured as an extruded product. The top portion of trim-rail4000is smoothly rounded over and it makes a smooth transition with upper ledge4010. Thus, inFIG.63, the trim4200can provide for an aesthetically-pleasing front surface for the trim-rail4000when the trim-rail4000is used as the front-most rail in the hybrid solar panel mounting assembly of the present invention. Additionally, the trim-rail4000can also assist in providing for a fire protection mechanism by further restricting the flow of air under the rail portion4300, and thus under the photovoltaic module(s) that are mounted on the trim-rail4000. Lower vertical extension4070of rail4300aids in restricting airflow underneath trim-rail4000. Thus, inFIG.63, because the rail portion4300and the trim portion4200of the trim-rail4000are a single, monolithic, integrated structure, there is no need to mount a trim piece4200on a separate rail. The integrated structure of the trim-rail4000design provides for both mounting a solar panel(s) to a surface by the rail4300and providing a trim4200for the rail. Further yet, because the trim4200and the rail4300are a single integrated structure, the trim4200is part of the rigid structure of the trim-rail4000, and thus, it is also a rigid structure itself. As such, the trim4200also directly supports the solar panel modules. In some embodiments, the wall thickness of trim portion4200can be the same as the wall thickness of rail portion4300. InFIG.63, the rail4300includes a first track4090formed between the upper flange4120and the lower flange4110. The bottom flange4110of the rail4300is the portion of the rail4300that is closest to the mounting surface, e.g., the roof. As will be further discussed below, the track4090is able to receive within it mounting hardware, e.g., the head of a bolt, that is used to mount the rail4300and thus trim-rail4000, on a footer (seeFIGS.65-66). The track4090is provided on one side of the rail4300so that the footer may be mounted on the inside of the rail4300. Opposite of the track4090, on the other side of web4140, is a small hollow volume4060. Lower flange4110contains a raised outside lip4080which is used to constrain the head of a bolt inserted into track4090. On the outer edge of upper flange4120is a horizontally extending flange4150that extends along the longitudinal length of trim-rail4000and which serves to lock into a horizontal groove (not shown) of an attached footer (seeFIGS.65-66). InFIG.63, a vertical wall4100, i.e., vertical with respect to the surface on which the trim-rail4000is mounted, is provided extending upwards from the top flange4120of the rail4300. Next, extending perpendicularly, i.e., horizontally, from the vertical wall4100is horizontal segment4160which intersects with vertical wall section4020on the right-hand side of trim-rail4000(as viewed inFIG.63). Vertical wall section4020extends downwardly from the top portion of trim4040. Extending horizontally from vertical section4020is a lower ledge (shelf)4030and an upper ledge (wing)4010. The gap between the upper ledge4010and lower ledge4030defines a slot10A into which a solar panel (or panels) is inserted. Lower ledge4030extends considerably further outwards from vertical wall4020than upper ledge4010. An edge of a solar panel(s) that is mounted on trim-rail4000is positioned between ledges4030and4010. The bottom of the solar panel is supported on lower ledge4030and the top of the solar panel is disposed under, and in engagement with, upper ledge4010. Thus, the edge of the solar panel is secured on trim-rail4000between lower ledge4030and upper edge4010of trim section4200. InFIG.63, trim-rail4000also includes a hollow chamber4130which is bounded on six sides by trim walls4040and4050, vertical walls4100and4020, and bottom walls4120and4160. Chamber4130receives splice5000within it (seeFIG.64). FIG.64illustrates an embodiment of splice5000. Splice5000is used to splice together two adjacent trim-rails4000. A first end of the splice5000is securely received within hollow chamber4130of a first adjacent trim-rail4000. A second end of the splice5000would be securely received within a hollow chamber4130of a second adjacent trim-rail4000. Thus, the splice5000rigidly joins and aligns a first trim-rail4000to a second adjacent trim-rail4000by firmly engaging within respective hollow chambers4130of adjacent trim-rails4000. InFIG.64, the structure of splice5000has a geometry that is complementary and close-fitting to that of trim-rail4000. Thus, the splice5000has a trim-like portion5100that has a contour (profile) that is complementary to trim walls4040,4050of trim section4200. Thus, when splice5000is received within hollow chamber4130of a trim-rail4000, the trim-like portion5100of splice5000generally engages with the inside wall of trim4200of trim-rail4000. Splice5000has a hollow chamber5200and a connector5300. InFIG.64splice5000can be further secured within the adjacent trim-rails4000by use of spring connector (interlock)5300. As such, splice5000also has an internal structure that receives within it a portion of connector5300(seeFIG.4for details of a similar connector300). Connector5300includes a pair of outwardly-bent spring straps, i.e., tabs,5302,5304that are bent such that they are received with splice5000and firmly engage into splice5000to secure connector5300on splice5000. At least portions of connector5300engage into both trim-rail4000and splice5000to electrically bond the trim-rail4000to the splice5000and, hence, to an adjoining trim-rail4000. These portions can be the respective straps5302and5304. FIG.65is a side view of the second embodiment of the trim-rail4000mounted to a footer and a base, hereinafter referred to as a footer assembly6000.FIG.66is a perspective view of the footer assembly. Trim-rail4000is removably mounted to footer assembly6000using fastener6050with the fastener's head mounted in track4090. Footer mounting assembly6000includes a footer bracket6010which includes a pair of vertical arms6012and6014which each include a plurality of horizontal ledges (teeth)6022. For example, arm6014can include 8 levels of ledges6022. The grooves, i.e., slots,6020that are disposed in-between adjacent ledges6022engage and interlock with horizontally protruding flange4150on trim-rail4000. The distance between adjacent ledges6022can be, for example, ⅛″, which gives a total vertical height adjustment capacity of 2″. InFIG.66, an open vertical slot6030is disposed in-between vertical arms6012and6014. The shank of fastener (bolt)6050passes through slot6030and engages with a tri-drive nut6040on the distal side of arms6012,6014. As will be further explained later in this specification, the tri-drive nut6040can be driven by three different sized tools: (a) a large hexagonal socket wrench, e.g., ⅝″, (b) a smaller socket wrench, e.g., Yz″, and (c) an Allen wrench tool. Use of three alternative drive tools gives the installer large flexibility for selecting and using a single tool during installation. Referring still toFIGS.65and66, footer bracket6010further includes an integral horizontal flat leg6016which gives the footer6010an “L-shape.” Flat leg6016further includes an upwards-facing horizontal lip6018. Flat leg6016is disposed within, and is captured by, a pair of “ ”-shaped side clamps7000,7020. Clamps7000,7020are compressed by a fastener, e.g., bolt,7030, which provides a clamping and locking force onto horizontal leg6016. The lower lip7040of side clamp7020engages in a side groove8030that is horizontally-disposed along the longitudinal length of base (track)8000. Side clamp7000clamps onto base8000through engagement in side groove8032. Base8000is rigidly fixed to a roof with a lag screw (not shown) that is disposed through aperture8010. A hollow chamber8020is disposed along the length of base8000. Footer bracket6010further includes a lower leg6060, the bottom of which rests on the upper surface8002of base8000. FIGS.67and68are perspective views of another embodiment of a solar panel mounting bracket according to the present invention. This embodiment is generally the same as that illustrated inFIGS.60-62, except that the overall length, L, is much greater inFIGS.67and68than inFIGS.60-62. In one example, the length L of micro-rail bracket9000can be 17.5″ long, which is approximately equal to Yz of a maximum expected rafter spacing, e.g., 24″, plus 5.5″, where the extra length equates to 2.5″-3.0″ of overhang at either end of the bracket9000. The width, W, of base track8000can be, for example, 1.5″ wide. InFIGS.67and68, the length, L, of micro-rail bracket9000is much longer than the width, W, of base track8000. In some embodiments, the aspect ratio, L/W, of the bracket's length (L) to the width (W) of the base track can be greater than 10. Alternatively, the aspect ratio L/W can be greater than 10 and less than 15. Alternatively, the aspect ratio L/W can equal approximately 12 (17.5/1.5). Alternatively, the length, L, can be less than or equal to (Yz of the spacing between adjacent roof rafters)+5.5 inches. Micro-rail bracket9000can include a pair of threaded fasteners, e.g., cap screws,9400and9402, disposed at opposite ends of bracket9000. Micro-rail bracket9000can also include a pair of bonding pins9300,9302disposed at opposite ends of bracket9000and located on the clamping side of bracket9000. Referring toFIG.67, micro-rail bracket9000includes an upper clamping portion9200and a lower base supporting member9100. Disposed within base supporting member9100is a series of three rectangular-shaped apertures9602,9604, and9606, located at the east end, middle, and west end of the bracket9000, respectively. These apertures9602,9604, and9606are sized to accept a single vertical structural support tower (stanchion)9500of the height adjustable mounting assembly, which engages with the helical drive and which is attached to base track8000. In between each aperture9602,9604,9606is a solid bridge segment9802,9804, respectively, which separates each aperture. Depending on where the micro-rail bracket9000is positioned with respect to the underlying roof rafters (Central location, West end, or East end), the support tower9500can be variably-discretely placed within one of the three apertures9602,9604, and9606. For example,FIG.68shows the support tower9500being located in aperture9606at the West end of micro-rail bracket9000. In this way, the support tower9500is variably-discretely positionable with respect to the longitudinal axis of bracket9000, i.e., in one of three fixed positions. In general, a plurality of discrete locations can be used to provide variable-discrete positioning of the support tower9500in bracket9000. The number of discrete locations can be, for example, 1, 2, 3, 4, or 5, depending on the length of bracket9000. Bracket9000further includes three tool-access holes9702,9704, and9706that are located directly above each of the three rectangular-shaped apertures9602,9604, and9606, respectively, for providing easy access to adjust the helical vertical drive mechanism (and, thus, adjust the PV module height off the deck). In this way, the base track8000is not confined to a single position on bracket9000, but, rather, can be variably positioned at three different discrete locations along the length of bracket9000in order to co-locate the position of the base track8000with an underlying rafter on the roof structure. In another embodiment, with reference toFIG.69, bridge segments9802and9804are eliminated and replaced with open space. In this embodiment, then, apertures9602,9604and9606are merged into one single continuous open slot9900, as shown inFIG.69, within which tower9500can be continuously variably-positioned in the East-West direction. As such, as can be seen, the tower is movable within the slot and along a length of the slot, where the length of the slot is at least two times the length of the tower. In addition, discrete tool-access holes9702,9704,9706are replaced by a single, continuous access slot9910that runs in the East-West direction. Further Rail-Less or Non-Rail-Based System Components FIGS.70-71illustrate an apparatus for mounting photovoltaic modules according to another embodiment of the present invention. A floating clamp assembly10000for holding solar panels together is disclosed, which can also be a bracket of a rail-less or non-rail-based system. The floating clamp assembly10000basically includes the same structure of an upper bracket10100and a lower bracket10200as per the upper bracket3100and lower bracket3200of the bracket of the embodiment ofFIGS.60-62, with the exceptions that, as can be seen, the lower bracket10200does not include the lower structure of the lower bracket3200and does not includes apertures for a stanchion and a tool. Thus, as can be seen, the assembly10000includes an upper bracket10100and a lower bracket10200(which together form a mounting bracket for mounting solar panels). Upper bracket10100includes a first arm10110, a second arm10120, a base10130, and a bottom wall10140that has a lower end that engages with a slot10234that is disposed within, and lays across the width of, lower bracket10200. Lower bracket10200includes a first arm10210and a second arm10220. First and second clamping bolts10300,10302clamp the upper bracket10100down to lower bracket10200when one or more solar panels are installed in each of slots10A,10B, which are defined between the respective arms of the upper and lower brackets. Stop bar10222runs sideways across the width of lower bracket10200and serves as a stop to abut against, and align, the solar panel(s) when installed in slot10A. Bonding pins10230are disposed in respective holes located in recessed channel10232in lower bracket10200. Bonding pins10230serves to pierce the anodized aluminum coating on the solar panel(s) and electrically interconnect (ground) the solar panel(s) to the lower bracket10200of assembly10000. As can be seen inFIG.70, when solar panels A and B are respectively disposed in slots10A and10B, solar panel B is loosely captured within slot10B when the clamping bolts10300,10302are tightened. The gap between solar panel B and the first arm10110of upper bracket10100is approximately 1 mm. The assembly10000is referred to as a “floating splice” since the assembly is supported above the surface on which the solar panels are otherwise mounted, and thus, the splice only contacts the solar panels and does not contact the surface. In an installation, slot10A is a South-facing side of the assembly and slot10B is a North-facing side of the assembly. The bonding pins make an electrical connection to the frames of clamped solar panels with a steady-state electrical resistance less than or equal to 0.010 Ohms, as measured per the Bonding Path Resistance Test specification described in UL 2703. In an embodiment, the upper bracket and the lower bracket are a single-piece, continuous, integral object. Multi-Drive Nut FIGS.72-74illustrate a first embodiment of a multi-drive nut for attaching to a fastener, as discussed previously. A multi-drive bolt or screw includes a head and a threaded shank. The head is a multi-drive nut11000with a body, internal threads, a proximal end11200and a distal end11202, and three concentric drive mechanisms for driving the nut. The three concentric drive mechanisms are disposed on an outside of the body and include a first external drive11102and a second external drive11104. Thus, the multi-drive nut11000can be driven, i.e., rotated, by two differently sized, externally applied tools. For example, a large hexagonal socket wrench, e.g., ⅝″, can be used with first external drive11102and a smaller hexagonal socket wrench, e.g., W′, can be used with second external drive11104. The larger diameter external drive11102is disposed near the proximal end11200of the nut and the smaller diameter external drive11104is disposed near the distal end11202of the nut. Further, the multi-drive nut includes a third drive mechanism, which is disposed inside the body and is an internal drive11106, which may be driven by, for example, an Allen wrench tool. The internal drive11106is disposed at the distal end11202of the nut. Optionally, the hollow shaft of the internal drive11106may extend along the entire length of the multi-drive nut, with openings at both the proximal and distal ends. The multi-drive nut also includes a flanged base11108which includes a plurality of angled, radial serrations that are disposed around the circumference of the flanged base. A threaded aperture11101is included at the proximal end11200for receiving a threaded shank. FIGS.75-76illustrate a second embodiment of a multi-drive nut for attaching to a fastener, as discussed previously. The head is also a multi-drive nut12000with a body and including internal threads, a proximal end12200and a distal end12202, and five concentric drive mechanisms for driving the nut. The five concentric drive mechanisms include a first external drive12102, a second external drive12104, and a third external drive12106. Thus, the multi-drive nut11000can be driven, i.e., rotated, by three differently sized, externally applied tools. The largest diameter external drive12102is disposed near the proximal end12200of the nut and the smallest diameter external drive12106is disposed near the distal end12202of the nut, and the drive12104that is sized between the largest and smallest drives is disposed between the largest12102and smallest12106drives. Further, the multi-drive nut includes fourth and fifth drive mechanisms, which are internal drives12108and12110, which may be driven by, for example, differently sized Allen wrench tools (hex socket). The internal drive12110is disposed at the distal end12202of the nut and the internal drive12108is disposed intermediate the distal end12202and the proximal end12200. Internal drive12110is larger than internal drive12108. As such, internal drive12110has a larger radius from the centerline of the nut than does internal drive12108. The multi-drive nut12000also includes a flanged base12112which also can include a plurality of angled, radial serrations that are disposed around the circumference of the flanged base. A threaded aperture12101is included at the proximal end12200for receiving a threaded shank. In other embodiments, the multi-drive nut can be an un-threaded cap end of a multi-drive bolt or a multi-drive screw. Whereas the external drives are disclosed as being hexagonal in shape, they may also be a square or triangular drive. The internal drives may be a hex drive, or a Torx™ drive, a star drive, a square drive, or a triangular drive, or combinations thereof. Use of these alternative drive tools gives the installer large flexibility for selecting and using a single tool during installation. The disclosed number of external drives and internal drives may be used in any combination, separately, or in any number. FURTHER RAIL-LESS OR NON-RAIL-BASED SYSTEM COMPONENTS FIG.77shows an exploded perspective view of another embodiment of a floating splice assembly according to the present invention. This embodiment is similar to what is shown previously inFIGS.70and71, and whereas otherwise noted, uses the same reference numbers for the same parts. InFIG.77, the lower bracket10200further includes a symmetric pair of stiffening ribs (wings)10400and10410and adjoining pair of vertical walls, disposed underneath the horizontal arms10210and10220, respectively. These stiffening ribs serve to stiffen the lower bracket and to increase its bending strength along the long axis. A slot10500is defined between the adjoining pair of vertical walls. Floating clamp assembly10000further includes three slots10700for receiving fastening cap bolts10300,10302, and10304. A pair of bonding pins10600can be seen, which are press-fit into respective holes. The length of floating splice10000can be about 9 inches, in some embodiments. Upper bracket10100is a “clamp and capture/catch” type of attachment bracket, where 1 or 2 solar panels are clamped on side10A and where 1 or 2 solar panels are captured (catched) on the opposite side10B. The foregoing disclosure has been set forth merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof. | 91,448 |
11942893 | DETAILED DESCRIPTION One aspect of the disclosure is directed to a single-axis solar tracking system for split-cell, multi-panel-in-landscape, or multi-panel-in-portrait solar arrays including a series of mechanically independent single-axis solar tracking platforms capable of performing backtracking in such a manner that allows for increased total power generation during low sun elevation conditions by intentionally shading a percentage of panel modules (e.g., those panel modules closest to the horizon), thereby allowing for a lower angle of incidence on unshaded module portions. Another aspect of the disclosure is directed to a mechanism for determining the power-optimal transition back to backtracking for single-cell or single panel (e.g., single-panel-in-portrait or single-panel-in-landscape) solar arrays. Individual tracking platforms may operate independently, may be self-powered, and may not require communications with other tracking platforms in the system. In other aspects, a wireless communication network and a system of supervisory control systems may be included. FIG.1illustrates a backtracking system100for single-cell or single panel (e.g., single-panel-in-portrait or single-panel-in-landscape) solar array according to an aspect. The backtracking system100includes multiple rows of solar trackers111a,111b. Although two rows of solar trackers111a,111bare illustrated inFIG.1, the backtracking system100may include more than two rows of solar trackers, e.g., 20 rows of solar trackers. Each row of solar tracker111a,111bincludes piers112which support a single-cell or single-panel solar module114. The solar modules114are rotatably coupled to the piers112and are mechanically driven by motors116. Controllers118operate the motors116to drive the solar modules114to a desired angle. Each of the controllers118may include a memory, which stores instructions for performing the methods described herein and operating the motors116, a processor, which is coupled to the memory and executes the instructions, and a motor driver circuit, which is coupled to and controlled by the processor according to the executed instructions. The memory may include volatile and non-volatile memory. For example, the memory may include random access memory (RAM) and read-only memory (ROM). The processor may be an application specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessor, or any other suitable circuit for performing the methods described herein and controlling the motor driver based on the instructions stored in memory. As illustrated inFIG.1, each row of solar trackers111a,111bmay include a controller118. In some aspects, there may be more than one controller118coupled to each row of solar trackers111a,111b. In aspects, the controllers118may include communications circuitry, such as wireless or wired communications circuitry. In the case where the controllers118include wired communications circuitry, the controllers118may connected to each via a communications line or cable. The communications line or cable may be integrated with a power cable that may connect to each row of solar trackers111a,111b. The backtracking system100may also include a supervisory controller (not shown). The supervisory controller may include wireless or wired communications circuitry configured to communicate with each of the controllers118so that the supervisory controller, which may implement a supervisory control system or form part of a system of supervisory control systems, can manage and/or coordinate operation of each row of solar trackers111a,111b. In some aspects, the supervisory controller may communicate with the controllers118via a wireless communications network. Backtracking systems100for single-cell or single panel solar arrays operate by reducing the solar tracking angle115in accordance with the following relationship between the sun elevation angle105and the solar tracker angle115: where θsis the sun elevation angle105relative to the horizon, θtis the solar tracker angle115relative to the zenith, and GCR is the ground coverage ratio. The sun elevation angle105may be obtained from a sun position calculator, which may be implemented by software that determines the sun elevation angle105based on celestial trajectories, which may be stored in a database of a supervisory control system and accessed, as needed, by the controllers118. The GCR may be expressed as the span or width (top to bottom) of the solar array divided by the pier-to-pier distance L between rows of support piers112, assuming uniform spacing between rows of piers, as illustrated inFIG.1. The backtracking systems of the disclosure provide backtracking that result in shading avoidance between rows during low sun elevation angle105conditions. They also result in a low angle of incidence upon all solar modules114in the tracking system100. As demonstrated inFIG.2, as the angle of incidence on the solar modules114increases, the relative light transmission decreases considerably after 30 degrees. Considering the drastic reduction in photovoltaic output power associated with a high angle of incidence of the sun102on the solar modules114, it is desirable to reduce the angle of incidence of the sun102on the solar modules114during backtracking. FIG.3illustrates a backtracking system including a single-axis solar tracker equipped with split-cell or multi-panel solar arrays314a,314b, which may be arranged in portrait and/or landscape solar arrays. The split-cell solar arrays314a,314bmay be formed by cutting a standard solar cell into two halves314a,314band bus-barring them together. When the split-cell solar module is unshaded, the current splits to flow around the two halves314a,314bof the split-cell solar module and then, before flowing out of the split-cell solar module, the current from the two halves314a,314bis combined. The split-cell or multi-panel solar arrays314a,315bare capable of operating in such a manner that allows for shading of a portion of solar modules during backtracking conditions. For example, solar module segment314a, which may be one half of a split-cell module or a panel of a multi-panel module, is unshaded, while solar module segment314b, which may be the other half of the split-cell module or another panel of the multi-panel module, is shaded. The backtracking operation for a split-cell or multi-panel solar array may be described by a suitable sun elevation angle to solar tracker angle relationship. For example, the backtracking operation for a split-cell or multi-panel solar array may be described by the following relationship: θt=2tan-1(tan(θS)-1-4(1GCR)2+tan2(θS)2GCR+1) where θsis the sun elevation angle relative to the horizon, θtis the solar tracker angle relative to the zenith, and GCR is the ground coverage ratio. In other aspects, where the terrain on which the backtracking system is installed is non-horizontal or otherwise irregularly shaped so that adjacent rows of solar arrays are at different heights, the sun elevation angle to tracking angle relationship may be described as: θt=2tan-1(-((4Δh2+4Δh+1)tan2(θS)-4GCR2+1)+(2Δh+1)tan(θS)2GCR+1) where θsis the sun elevation angle relative to the horizon, θtis the solar tracker angle relative to the zenith, GCR is the ground coverage ratio, and Δh is the difference in height between adjacent piers112. Electrical separation between segments of a split-cell module or between panels in multi-panel arrays allows for increased power generation from unshaded panels and/or segments via decreased angle of incidence by operating at backtracking angles that shade a portion of the panels within the array. In contrast, traditional systems operate at angles of incidence to avoid inter-panel shading. The backtracking system of the disclosure may actively adjust the sun elevation angle to solar tracking angle relationship to account for variations in GCR and automatically switch back to traditional backtracking if the controller118determines that by doing so the total power generation may be increased. This may be conducted, e.g., autonomously, based on a method illustrated in the flow diagram ofFIG.4. After starting at block402, the sun elevation angle is calculated at block404. Then, a traditional single-cell or single-panel backtracking angle is calculated at block406and a split-cell or multi-panel backtracking angle is calculated at block408. Blocks406and408may be performed simultaneously or in parallel as illustrated inFIG.4. Alternatively, blocks406and408may be performed in sequence. For example, block406may be performed first and block408may be performed second or vice versa. Δt block410, a traditional relative light transmission (RLT) is calculated based on the traditional backtracking angle and a split-cell or multi-panel RLT is calculated based on the split-cell/multi-panel backtracking angle. The traditional RLT and the split-cell or multi-panel RLT may be calculated based one or more suitable models. For example, the traditional RLT and the split-cell or multi-panel RLT may be calculated based on the IEC 61853-2 standard model, the theoretical air/glass interface model, and/or the empirical model developed by the Sandia National Laboratories for glass superstrate PV modules, as described, for example, in “Validation of IEC 61853-2 standard (Draft): Angle of incidence effect on photovoltaic modules,” published in the 2013 IEEE 39th Photovoltaic Specialists Conference (PVSC) (16-21 Jun. 2013), the entire contents of which are incorporated herein by reference. Additionally or alternatively, the traditional RLT and the split-cell or multi-panel RLT may be calculated according to the method described, for example, in “Calculation of the PV modules angular losses under field conditions by means of an analytical model,” Solar Energy Materials & Solar Cells 70 (2001) 25-38, the entire contents of which are incorporated by reference herein. In this example method, the RLT is based on the following angular factor, f1α. The experimental value of such a parameter can be obtained by dividing the short-circuit current (Isc) at an angle α by the product of the short-circuit current at normal incidence (α=0) and the cosine of the angle α: fIα=Isc(α)Isc(0)1cosα≅1-R¯(α)1-R¯(0) For crystalline (x-Si) and amorphous silicon (a-Si) technologies, with or without antireflective coatings, the reflectanceR(α) of a PV module may be calculated according to the following expression: R¯(α)=R¯(0)+[1-R¯(0)][exp(-cosa/ar)-exp(-1/ar)1-exp(-1/αr)], where α is the irradiance angle of incidence and αrthe angular losses coefficient, an empirical dimensionless parameter to fit in a particular case. At block412, a diffuse fraction index (DFI) is determined and the method determines whether the DFI is greater than a DFI limit. The DFI may be calculated according to the equation DFI=1−(DNI/GHI), where the direct normal irradiance (DNI) and the global horizontal irradiance (GHI) are directly measured using a pyranometer. Alternatively, the GHI may be measured and a model may be used to estimate the DFI. In response to determining that the DFI is greater than a DFI limit, a DFI tracking angle is selected as the angle to which the solar module is driven by the motor of the solar tracker at block414and the method400ends. Exceeding the DFI limit may result in the panels becoming more horizontal. In response to determining that the DFI is not greater than a DFI limit at block412, the method400includes determining whether twice the single-cell or single-panel RLT is greater than the split-cell or multi-panel RLT at block416. In response to determining that twice the single-cell or single-panel RLT is greater than the split-cell or multi-panel RLT at block416, the split-cell or multi-panel backtracking angle is selected at block418as the angle to which the solar module is driven by the motor of the solar tracker and the method400ends. On the other hand, in response to determining that twice the single-cell or single-panel RLT is not greater than the split-cell or multi-panel RLT, the single-cell or single-panel backtracking angle is selected at block420as the angle to which the solar module is driven by the motor of the solar tracker and the method400ends. Examples of resulting tracking profiles or tracker angles with respect to the sun elevation angle are shown inFIGS.5A and5B.FIG.5Aillustrates the tracker angles for split-cell or two-panel backtracking and for single-cell or single-panel backtracking (traditional backtracking) for a ground clearance ratio (GCR) of 50%. For sun elevation angles between 75 degrees and 90 degrees, the tracker angle for split-cell or two-panel backtracking quickly rises from 15 degrees to 60 degrees and then falls to 0 degrees at approximately a constant rate for sun elevation angles between 75 degrees and 90 degrees. For sun elevation angles between 0 degrees and 60 degrees, the tracker angle for single-cell or single-panel backtracking rises from 0 degrees to 60 degrees. Then, for sun elevation angles between 60 degrees and 90 degrees, the tracker angle for single-cell or single-panel backtracking falls back to 0 degrees. In some aspects, at typical GCRs and latitudes, the split-cell backtracking may turn off when the sun elevation angle is at approximately 75 degrees. In other aspects, the split-cell backtracking may turn off when the sun elevation angle is at approximately 70 degrees. FIG.5Billustrates the tracker angles for split-cell or two-panel backtracking and for single-cell or single-panel backtracking (traditional backtracking) for a GCR of 35%. For sun elevation angles between about 78 degrees and 90 degrees, the tracker angle for split-cell or two-panel backtracking quickly rises from about 25 degrees to 60 degrees and then falls to 0 degrees at approximately a constant rate for most the sun elevation angles between about 78 degrees and 90 degrees. For sun elevation angles between 0 degrees and 60 degrees, the tracker angle for single-cell or single-panel backtracking rises from 0 degrees to 60 degrees and then plateaus until the sun elevation reaches about 70 degrees. And then for sun elevation angles between about 70 degrees and 90 degrees, the tracker angle for single-cell or single-panel backtracking falls back to 0 degrees. While several aspects of the disclosure have been shown in the drawings, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular aspects. | 14,768 |
11942894 | DETAILED DESCRIPTION The present disclosure relates to, among other things, a driveline joint capable of connecting two or more shafts together at their ends for the purpose of transmitting torque through a driveline while permitting some degree of angular misalignment. The driveline joint may include a shaft coupling, two or more bearings, and a number of fasteners corresponding to the number of bearings. The shaft coupling may be positioned inside a driveline shaft that includes, for example, a tubing extending along a driveline. The driveline shaft may include a number of slots positioned axially around the tubing (e.g., cut and/or otherwise formed into the surface of the tubing) near both ends through which the fasteners of the driveline joint may be inserted to couple the shaft coupling to the driveline shaft. In some embodiments, the driveline joint may include a pressure plate for limiting axial movement of the driveline joint and/or mitigating vibrations experienced by the driveline and/or the driveline joint. The driveline joint according to the present disclosure may provide a number of advantages over existing methods and/or systems of connecting segments of a driveline and transmitting torque through the driveline. The driveline joint may be built using a number of components that may be fabricated in high volumes. As such, deploying the driveline joint may include lower costs relative to existing methods and/or systems of connecting driveline segments. The driveline joint may decrease operating costs of an array of PV modules. Because the driveline joint may include a number of replaceable components, maintenance costs and/or time of the array of PV modules may be decreased. Embodiments of the present disclosure are explained with reference to the accompanying figures. FIGS.1A and1Billustrate a side view of an example embodiment of a driveline joint100according to the present disclosure. The driveline joint100may include a driveline shaft110in which a shaft coupling130is positioned. The driveline shaft110may include a number of slots, one of which is denoted at115, through which one or more fasteners, one example of which is denoted at134, may be inserted. The fasteners134may secure one or more bearings132to the surface of the shaft coupling130. In some embodiments, a pressure plate120may be positioned in the driveline shaft110such that a surface of the pressure plate120is aligned with a base surface138of the shaft coupling130. The shaft coupling130may be coupled to an output shaft140(such as shown inFIG.2) of a gear box (not shown), and the driveline shaft110may span between two gear boxes that each include the shaft coupling130. The gear box may affect rotation of the output shaft, and the shaft coupling130may transmit the torque of the output shaft to a driveline such that the orientation of an array of PV modules coupled to the driveline shaft110may be rotated. In some embodiments, the shaft coupling130may include one or more mechanisms for securing and/or preventing dislocation of the output shaft of a gear box. For example, as illustrated inFIG.1B, the shaft coupling130may include an opening136in which the output shaft140of the gear box may be keyed to the shaft coupling130. Additionally or alternatively, the shaft coupling130may include a threaded interior surface, one or more clasps, or other arrangement for securing the output shaft to the shaft coupling130. In some embodiments, as is shown inFIG.1B, and inFIG.2, the driveline joint100may include one or more of the pressure plates120. The pressure plate120may limit axial movement between the shaft coupling130and the driveline shaft110by applying spring force to the shaft coupling130. In these and other embodiments, the spring force from the pressure plate120may bias the fasteners134towards one end of the slots115such that the fasteners134may still move within the slots115by overcoming the spring force but are otherwise biased to remain in a stationary location within the slots. For example, when there is a mismatch between joints at either end of the driveline shaft110, the driveline shaft110may experience play in a longitudinal direction. The pressure plate120may reduce, eliminate, or remove some of the play by applying the spring force. Additionally or alternatively, the pressure plate120may reduce, eliminate, or remove vibrations as experienced when the gear box(es) are causing rotation of the driveline shaft110. Additionally or alternatively, the pressure plate120may decrease sliding movement of the fasteners134within the slots115and reduce rattling in the driveline joint100, such as in circumstances in which the driveline is installed at an incline. As such, the pressure plate120may mitigate damage to the driveline joint100caused by movement of the array of PV modules and/or forces on the components of the array of PV modules caused by weather conditions (e.g., wind, rain, hail, snow, among others) and/or human actions (e.g., maintenance work on the array of PV modules, unintentional impacts, among others), as well as mitigating damage due to repeated motions, rattling, vibrations, among others, caused by play along the driveline shaft110. In some embodiments, the pressure plate120may include a number of tabs122in which each tab122is configured to interface with one of the slots115. As such the number of tabs122may correspond to the number of slots115, and/or the tabs122may be arranged equidistant from one another around the circumference of the pressure plate120to facilitate interfacing with the slots115. In these and other embodiments, the tabs122may include an inclined body such that the surface124of the pressure plate120is not aligned with the surface126of the tabs122, which may provide the spring force (as denoted by the arrow) capable of being exerted on the shaft coupling130. For example, a given pressure plate may include inclined tabs oriented such that the plane of the surface of the given pressure plate is closer to a given shaft coupling than the plane in which the tabs are situated (e.g., a central body128of the pressure plate120may be oriented towards the distal end112of the driveline shaft110with the opening and the tabs122extending from the central body away from the distal end112and are seated in the slots115towards the middle of the driveline shaft110). Additionally or alternatively, the pressure plate120may be oriented in the opposite direction. In this example, pressure applied toward the surface of the given pressure plate by the shaft coupling130may affect a spring pressure in the opposite direction (e.g., in a direction opposite to the orientation of the arrow). Additionally or alternatively, the surface of the pressure plate120may include a central post and/or one or more protruding bumpers129(in whichFIG.1Billustrates an embodiment including the protruding bumpers129). The shape of the central post and/or the bumpers129may be based on the shape of the shaft coupling130such that one or more surfaces of the shaft coupling130may be positioned flush against the pressure plate120. Additionally or alternatively, two pressure plates may be included in the driveline joint100such that a first pressure plate is positioned against a first base surface of the shaft coupling130, and a second pressure plate is positioned against a second base surface of the shaft coupling130. For example, the first pressure plate may be positioned as described above, with the tabs seated in the end of the slot towards the middle of the driveline shaft110, and the second pressure plate may be positioned with the tabs seated in the end of the slot towards the distal end of the driveline shaft110(e.g., the end with the opening). By using two pressure plates, a spring force may be applied to the fasteners (and thereby to the shaft coupling130) in both longitudinal directions of the driveline shaft110. By providing the spring force in both directions, the motion, play, vibrations, or other motions in both longitudinal directions may be accounted for and/or mitigated. In some embodiments, one or more of the components of the driveline joint100, such as the driveline shaft110, the pressure plate120, the shaft coupling130, the bearings132, and/or the fasteners134, may be manufactured to reduce the cost of the driveline joint100relative to existing joints, such as u-joints. For example, the driveline shaft110may include a cylindrical tube in which the tubing is manufactured from steel via a rolled-tubing process and/or using materials such as extruded aluminum, cast iron, high-density polyethylene, or polyvinyl chloride. As additional or alternative examples, the pressure plate120may be manufactured using a stamping process, and the bearings132may be manufactured via an injection molding process. FIG.1Cillustrates a frontal view of the example embodiment of the driveline joint100according to the present disclosure.FIG.1Dillustrates a side view of the example embodiment of the driveline joint100including and example of angular misalignment of the driveline shaft110and the shaft coupling130according to the present disclosure. FIG.2illustrates an exploded view of the example embodiment of the driveline joint100according to the present disclosure. The bearings132and the fasteners134may maintain alignment of the shaft coupling130inside the driveline shaft110. In some circumstances, a given array of PV modules may be installed on an uneven surface such that a non-flat slope exists between two or more gear boxes140. In these and other circumstances, angular misalignment between the shaft coupling130and the driveline shaft110may be compensated for by the bearings132and the fasteners134. As illustrated inFIGS.1C and2, the shaft coupling130may include one or more of the bearings132and a corresponding number of the fasteners134. In some embodiments, the lateral surface130aof the shaft coupling130may include two or more equally spaced openings131against which the bearings132may be positioned. As shown inFIG.1B, the bearings132may include an opening133through which each of the fasteners134may be inserted. In these and other embodiments, one or more surfaces of bearings132may be configured to fit flush against the lateral surface130aof the shaft coupling130and/or the interior lateral surface110aof the driveline shaft110. For example, a given bearing may include a rounded (e.g., spherical) bearing having an arced bottom surface132aconfigured to be positioned directly (e.g., flush) against a cylindrical shaft coupling and a rounded (e.g., spherical) top surface132bconfigured to be positioned directly (e.g., flush) against the interior surface110aof a cylindrical driveline shaft. Stated another way, the spherical curve of the top surface132bof the bearings132may be selected to match the curve of the inner surface110aof the driveline shaft110. The rounded top surface132bof the given bearing may allow two driveline shafts110attached to the shaft coupling to pivot at the point where the axes of the driveline shafts110intersect. Additionally or alternatively, the openings133in the bearings132and/or the openings131in the shaft coupling130may be threaded, partially threaded, or smooth-bored depending on the type of fasteners134used to couple the bearings132and the shaft coupling130. For example, a given first set of fasteners may include screws having fully threaded bodies, and a given second set of fasteners may include screws having partially threaded bodies. Bearings and/or shaft couplings secured using the given first set of fasteners may include openings having fully threaded interior surfaces, and bearings and/or shaft couplings secured using the given second set of fasteners may include openings having partially threaded interior surfaces. As another example, a given third set of fasteners may include studs, pins, bolts, or any other fasteners that may be pressed, bonded, drilled, or otherwise coupled to the bearings and the shaft coupling130. In some embodiments, the lengths of the slots115may be sized based on a maximum angle of misalignment possible for the driveline joint100. For example, an output shaft142of the gear boxes140at either end of the driveline shaft110may be oriented in different directions (e.g., may not be directly co-linear with each other), and the driveline joint100may facilitate operation despite that misalignment and the length of the slots115may be based on the magnitude of the misalignment. In these and other embodiments, the maximum angle of misalignment for different driveline joints100may differ based on the angle of the incline at which the array of PV modules is installed. To compensate for axial misalignment of the shaft coupling130, the lengths of the slots115may be sized such that the fasteners134do not contact either end of the slots115in the driveline shaft110during rotation of the driveline shaft110. As such, the length of the slots115may be increased for driveline shafts110installed on inclined surfaces relative to driveline shafts110installed on flatter surfaces. As illustrated inFIG.1D, the driveline shaft110and the shaft coupling130are misaligned at an angle of p. In some embodiments, the driveline joint100compensates for angular misalignment between the driveline shaft110and the shaft coupling130by allowing the fasteners134coupling the shaft coupling130to the driveline shaft110to shift around in the slots115. In some embodiments, the driveline shaft110may be a sheath or other covering that may be bonded, coupled, or otherwise attached at an end of a beam between gear boxes140. Additionally or alternatively, the driveline shaft110may be formed as part of the beam between the gear boxes140, such as a solid beam with hollow ends, or a hollow beam along its entire length between the gear boxes140. While illustrated as including three slots115, any number of slots may be included. For example, the driveline shaft110may include two slots, four slots, five slots, six slots, to accommodate differing numbers of bearings132and/or fasteners134being used to couple the output shaft130to the driveline shaft110. FIG.3illustrates a perspective view of a second example embodiment of a driveline joint200according to the present disclosure. The driveline joint200may include a driveline shaft205to which an outer housing210may be coupled via a connecting hinge220. The outer housing210may facilitate coupling of the driveline shaft205to a shaft coupling230including a keyed opening236that allows coupling of an output shaft (not shown) to the driveline shaft205via the shaft coupling230. In some situations, the shaft coupling230and/or coupling components associated with the shaft coupling230, such as spherical bearings232, may include dimensions that do not fully align with the dimensions of the driveline shaft205. For example, the driveline shaft205may include a first exterior cross-sectional diameter, while the shaft coupling230includes a second interior cross-sectional diameter (e.g., substantially the same size as or even larger than the driveline shaft205). As such, attaching the shaft coupling230directly to the driveline shaft205may involve an intermediary component, such as the outer housing210, that accounts for differences in dimensions, geometry, or other characteristics between the shaft coupling230and the driveline shaft205. In these and other situations, the outer housing210may be an extension of the driveline shaft205. Additionally or alternatively, the outer housing210may be a separate component that is attachable to an end of the driveline shaft205. In some embodiments, the outer housing210may include a flared portion214that includes a larger interior diameter than the rest of the outer housing210. Both the flared portion214and an unflared portion212of the outer housing210may include features that allow the outer housing210to be coupled to the driveline shaft205and/or the shaft coupling230. For example, the unflared portion212of the outer housing210may include one or more openings218through which fasteners226may be inserted to secure the outer housing210to the driveline shaft205as illustrated inFIG.3. As another example, the flared portion214of the outer housing210may include one or more oblong openings216through which fasteners may be inserted to secure the outer housing210to the shaft coupling230as illustrated inFIG.3. Although illustrated inFIG.3as having a corresponding number of openings as the components to which the outer housing210is coupled, the flared portion214and/or the unflared portion212may include any number of features that allow coupling of the outer housing210to other driveline components. For example, the flared portion214and/or the unflared portion212may include any number of openings so that the outer housing210may be coupled to driveline components of various specifications (i.e., including different numbers of corresponding openings). As another example, the outer housing210may include grooves, notches, tabs, or any other features that may be used to secure the outer housing210to other driveline components. In some embodiments, the outer housing210may be coupled to the driveline shaft205via the connecting hinge220. The connecting hinge220may include a clasp222with a semi-circular shape that includes a loop224at each end of the clasp222. The loops224may be aligned with the opening218through the lateral surface of the outer housing210, such as along the unflared portion212, and an opening (not shown) in the underlying driveline shaft205. One or more fasteners226may be inserted through the loop224and the aligned openings to secure the clasp222, the outer housing210, and the driveline shaft205together. Although illustrated as a peg-like component, the fastener226may be a rod that extends through the unflared portion212of the outer housing210. Additionally or alternatively, the fastener226may be any fastening component, such as a pin, a bolt, a nut, and/or a screw. After securing the connecting hinge220to at least the outer housing210, the clasp222may be rotated along an axis228formed by the one or more fasteners226that are inserted through the loops224and the openings in the outer housing210; rotating the clasp222along the axis formed by the fasteners226may allow the connecting hinge220to provide an additional securing force for locking the outer housing210and the driveline shaft205together. In some embodiments, the flared portion214of the outer housing210may be coupled to the shaft coupling230via one or more spherical bearings232and corresponding fasteners234. Each of the spherical bearings232may include an opening (not shown) through which the fasteners234may be inserted. By aligning the openings of the spherical bearings232with one or more of the openings216in the flared portion214of the outer housing210and one or more openings in the shaft coupling230, the fasteners234may secure the spherical bearings232to the outer surface231of the shaft coupling230and/or the inner surface211of the outer housing210. Each of the spherical bearings232may include a curved profile such that an inner surface232band an outer surface232aof each spherical bearing232is rounded like a surface of a sphere. The curved profile of the spherical bearings232may allow some degree of rotation between the shaft coupling230and the outer housing210to account for misalignments, vibrations, and/or movements between the shaft coupling230and the outer housing210in a similar or comparable manner to the spherical bearings132ofFIGS.1A-1D and2. The shaft coupling230may include a keyed opening236that provides an interface for an output shaft, a U-joint, another driveline shaft piece, or any other components. The keyed indent may include a notch238, and any driveline component that includes a corresponding notch shape may be inserted through the keyed opening236. After insertion through the keyed opening236, a set screw, a bolt, or any other type of fastener (such as a set screw340as illustrated inFIGS.4A and4B) may be used to secure the driveline component in place relative to the shaft coupling230. For example, an output shaft attached to a gearbox at the end of the driveline may include such a notched end, and the output shaft may be inserted into and locked in place via the keyed opening236of the shaft coupling230by the set screw or any other fastener. FIG.4Aillustrates a perspective view of a third example embodiment of a driveline joint300according to the present disclosure, andFIG.4Billustrates an exploded view of driveline joint300. The driveline joint300may include an outer housing310, a shaft coupling330, an annulus ring334, a pin336, and a connecting hinge320. In some embodiments, the outer housing310may have a flared shape that is the same as or similar to the flared shape of the outer housing210described above in relation to the driveline joint200FIG.3. Additionally or alternatively, an unflared portion312of the outer housing310may be coupled to a driveline shaft305via the connecting hinge320in the same or a similar manner as the unflared portion212is coupled to the driveline shaft205via the connecting hinge220as described in relation to the driveline joint200. A flared portion314of the outer housing310may include an inner diameter that allows placement of the annulus ring334within the interior of the flared portion314and one or more openings316through which the pin336may be inserted. As illustrated inFIG.4B, the shaft coupling330may include one or more openings332that may align with openings in the annulus ring334and the openings316of the outer housing310. Once aligned, the pin336may be inserted through the openings of the shaft coupling330, the annulus ring334, and the outer housing310to secure the three components together. In some embodiments, the pin336may be locked in place to prevent the pin336from sliding out and allowing misalignment of one or more of the shaft coupling330, the annulus ring334, and/or the outer housing310. For example, the pin336may include a threaded outer surface, and a nut may be threaded onto the top and/or the bottom of the pin336to prevent sliding of the pin336. As additional or alternative examples, a wire lock, a C-hinge, a perpendicular screw, an interference fit, or any other locking mechanisms may be used to fix the position of the pin336. In some embodiments, the annulus ring334may include a spherical shape that is the same as or similar to the shape of the spherical bearings232described above in relation to the driveline joint200ofFIG.2in the form of a ring. Stated another way, the annulus ring334may take the shape of a hollow sphere with portions clipped off of either end. The annulus ring334may include a curved outer and inner profile like a surface of a sphere so that the shaft coupling330may be allowed some degree of rotation and movement when coupled to the outer housing310. For example, the spherical curvature of the outer surface of the annulus ring334may correspond to the curvature of the inner surface of the flared portion314of the outer housing310. The annulus ring334may operate in the same or similar manner as the spherical bearings132ofFIGS.1A-1DandFIG.2such that the pin336may travel within the slot to accommodate the misalignment between the shaft coupling330and the driveline shaft305with the annulus ring334acting as a bearing between the flared portion314of the outer housing310and the shaft coupling330. As illustrated inFIG.4A, for example, the opening316includes a substantially greater width than a cross-sectional profile of the pin336. Any misalignment between the shaft coupling330and the driveline shaft305may cause the pin336to shift within the opening316because of the curvature of the annulus ring334without causing damage to the outer housing310, the shaft coupling330, or the rest of the driveline shaft305. In other words, the pin336and the annulus ring334may function as a joint between the shaft coupling330and the outer housing310that allows some degree of rotational mobility, which may accommodate any misalignment between the shaft coupling330and the outer housing310within some tolerance limit. Terms used in the present disclosure and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open terms” (e.g., the term “including” should be interpreted as “including, but not limited to.”). Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is expressly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. Further, any disjunctive word or phrase preceding two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both of the terms. For example, the phrase “A or B” should be understood to include the possibilities of “A” or “B” or “A and B.” All examples and conditional language recited in the present disclosure are intended for pedagogical objects to aid the reader in understanding the present disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the present disclosure. | 27,020 |
11942895 | DETAILED DESCRIPTION One of the disclosed embodiments is described below with reference to the drawings. Herein, the term “vertical direction” refers to the direction perpendicular to the paper surface of a top view of a power generation module connected body inFIG.3A, etc. The term “upward” refers to the direction to the front from the paper surface in the drawing, and the term “downward” refers to the direction opposite to the upward direction. The term “front side” refers to the upward facing side of the power generation module connected body in an unfolded state, and the term “back side” refers to a side opposite to the front side. The term “row direction A” refers to the rightward direction in top a view of a power generation module connected body inFIG.3A, etc., and the term “column direction B” refers to the downward direction in the top view. FIG.1is a block diagram illustrating a schematic structure of a power generation device1according to one of the disclosed embodiments. As illustrated inFIG.1, the power generation device1according to this embodiment includes a power generation module connected body10and a main body20. The power generation device1can be supplied with power from a commercial power supply via an AC adapter30. The AC adapter30includes a power outlet31and an AC/DC converter32. The AC/DC converter32receives input of an AC voltage from the commercial power supply via the power outlet31, converts the input AC voltage to a DC voltage, and supplies the DC voltage to the main body20. The power generation module connected body10includes a plurality of power generation modules P and a connection portion11. The connection portion11mechanically and electrically connects the power generation modules P to each other. Each power generation module P is a flat panel in appearance.FIG.1illustrates four power generation modules P, but the number of the power generation modules P is not limited to 4. Each power generation module P includes a power generation section12. The power generation section12is, for example, a solar cell made of solar cells configured to photoelectrically convert incident light, such as sunlight or room light, and outputs electric power. The power generation section12is not limited to a solar cell and may be a power generator that generates electric power utilizing energy other than incident light, such as geothermal heat. The power generation module P includes a substrate (not illustrated) for supporting the power generation section12, extraction wiring (not illustrated) for extracting electric power generated by the power generation section12, and the like, in addition to the power generation section12. Solar cells used as the power generation section12are broadly classified into two types: inorganic solar cells in which an inorganic material is used and organic solar cells in which an organic material is used. Examples of inorganic solar cells include Si solar cells in which silicon (Si) is used and compound solar cells in which a compound is used. Examples of organic solar cells include thin-film solar cells such as low-molecular vapor deposition-type solar cells in which an organic pigment is used, polymer coating-type solar cells in which a conductive polymer is used, and coating-conversion-type solar cells in which a conversion-type semiconductor is used; and dye-sensitized solar cells formed from titania, an organic dye, and an electrolyte. Other examples of solar cells included used as the power generation section12include organic/inorganic hybrid solar cells and solar cells in which a perovskite compound is used. In the present disclosure, a thin panel-shaped solar cell panel is used as the solar cell, and a dye-sensitized solar cell formed using a plastic film or the like is preferable. The thin panel-shaped solar cell panel is not limited to a panel formed using a plastic film or the like, and may be any type as long as it is a similar thin panel. The main body20includes an interface21, a booster circuit section22, a power generation module voltage detection section23, an AC adapter voltage detection section24, a rechargeable battery25, an external interface (IF)26, a charge/discharge control circuit27, and a controller28. The interface21is a device for mechanically and electrically connecting each power generation module P to the main body20. The interface21may connect the power generation module P removably. The interface21outputs electric power supplied from the connected power generation module P, to the booster circuit section22. The booster circuit section22boosts the voltage of the electric power supplied from the power generation module P via the interface21to a predetermined voltage required for charging the rechargeable battery25, and outputs the resultant voltage to the charge/discharge control circuit27. The power generation module voltage detection section23detects a voltage (power generation module voltage) supplied from the power generation module P connected to the interface21of the main body20to the booster circuit section22via the interface21, and outputs the result of the detection to the controller28. The AC adapter voltage detection section24detects a voltage (AC adapter voltage) supplied from the AC adapter30to the charge/discharge control circuit27, and outputs the result of the detection to the controller28. The rechargeable battery25is a battery that can be charged and discharged, such as a lead-acid battery or a lithium ion secondary battery. The external interface (IF)26is an interface capable of connecting to an external device and supplying electric power to the connected external device. The external IF26is not limited, and is, for example, a connector (USB connector) using a USB (Universal Serial Bus) interface or a cable having a connector at its end. The external IF26connects to the external device and, for example in response to a charging request from the external device, supplies electric power to the external device. The power generation device1can be mechanically and electrically attached to and removed from various devices to be charged, such as a mobile phone, a smartphone, a tablet device, and a personal computer, via the external IF26. The charge/discharge control circuit27performs charge/discharge control among the booster circuit section22, the AC adapter30, the rechargeable battery25, and the external device connected via the external IF26. The controller28controls operation of each section of the main body20. For example, the controller28controls the charge/discharge control circuit27to control paths for charging and discharging, based on the detection result of the power generation module voltage detection section23, the detection result of the AC adapter voltage detection section24, the charge level of the rechargeable battery25, and so on. The structure of the power generation module connected body10included in the power generation device1is described in more detail below, with reference toFIGS.2to6.FIGS.2to5are illustrations of the power generation module connected body10according to this embodiment in an unfolded state.FIG.2is a perspective view,FIG.3Ais a top view,FIG.3Bis a front view,FIGS.4A to4Care partially enlarged sectional views along the row direction, andFIG.5is a bottom view. Herein, the “unfolded state” is a state in which, in order to generate electric power using the power generation device1, the power generation modules P are unfolded so as not to overlap each other, such that the power generation module connected body10is planar as a whole. In contrast to the unfolded state, the “stored state” refers to a state in which, in order to store the power generation device1, adjacent power generation modules P are folded so that all power generation modules P overlap in the vertical direction, as described later with reference toFIGS.9A and9B. The unfolded state and the stored state are defined for the sake of convenience, to describe the state of the power generation module connected body10. The power generation module connected body10may be used for power generation with some of the power generation modules P being folded, or stored with some of the power generation modules P being not folded. As illustrated inFIGS.2and3A, the power generation module connected body10has the power generation modules P arranged in a matrix of 5 rows and 5 columns, in an unfolded state. The power generation modules P are mechanically and electrically connected by the connection portion11in the row direction A and in the column direction B. Specifically, as illustrated inFIG.3A, the connection portion11includes row-direction connection portions13and column-direction connection portions14, so that power generation modules P which are adjacent to each other along the row direction A are connected together with the row-direction connection portions13and power generation modules P which are adjacent to each other along the column direction B are connected together with the column-direction connection portions14. At least one of the row-direction connection portion13and the column-direction connection portion14includes a conductor that electrically connects the power generation modules P. In this example, each power generation module P is rectangular in top view. Each power generation module P may be covered with a casing to provide environmental resistance. Although it is preferable that each power generation module P has a certain degree of flexibility, each power generation module P has at least such rigidity that is higher than that of the connection portion11between the power generation modules P and resists folding. Each power generation module P is preferably covered on its periphery with a frame which is a rigid member with particularly high rigidity. By covering the power generation module P with such a frame, for example, flexural deformation of the power generation module P caused by stress from the connection portion11can be prevented. Hereinafter, as illustrated inFIG.3A, the length along the row direction A of the row-direction connection portions13(hereinafter “row-direction length” as appropriate) is defined as C, and the length along the column direction B of the column-direction connection portions14(hereinafter “column direction length” as appropriate) is defined as D. The length along the column direction B of the row-direction connection portions13(hereinafter “column-direction width” as appropriate) is defined as E, and the length along the row direction A of the column-direction connection portions14(hereinafter “row-direction width” as appropriate) is defined as F. The length along the row direction A of the power generation modules P is defined as WR, and the length along the column direction B of the power generation modules P is defined as WC. Each power generation module P has the power generation section12exposed upward, as illustrated inFIG.2. The power generation module P includes extraction wiring connected to the power generation section12. The power generation module P extracts electric power generated by the power generation section12through the extraction wiring, and outputs the electric power to, for example, the interface21of the main body20via the connection portion11and/or other power generation modules P. The power generation section12in the power generation module P may be disposed to be capable of receiving incident light in a direction other than from above, for example, from below, to generate power. The connection portion11is a connection member having flexibility. The connection portion11mechanically connects the power generation modules P in the row direction A and in the column direction B, and is configured so that the power generation modules P connected via the connection portion11are foldable. The connection portion11preferably has higher flexibility than the power generation modules P from the viewpoint of foldability. The connection portion11includes a conductor (not illustrated) that electrically connects the power generation modules P. The conductor is located to electrically connect any adjacent power generation modules P to each other. The thickness of the connection portion11in the vertical direction is not greater than the thickness of the power generation modules P in the vertical direction. The thickness of the connection portion11in the vertical direction is preferably less than the thickness of the power generation modules P in the vertical direction, as illustrated inFIGS.4A to4C. As illustrated inFIGS.4A to4C, preferably, at least one of the row-direction connection portion13and the column-direction connection portion14as the connection portion11is located along the lower end of the power generation module connected body10and includes a conductor layer112and a protective layer113stacked in the vertical direction. The conductor layer112is a layer including a conductor, and is composed of, for example, a conductive member such as a conductive cable and/or a flexible board. The protective layer113is composed of, for example, a covering member for protecting and/or reinforcing the conductor layer112. For example, the connection portion11may have the protective layer113and the conductor layer112arranged in the order mentioned upward from the lower end as illustrated inFIG.4A, have the conductor layer112and the protective layer113arranged in the order mentioned upward from the lower end as illustrated inFIG.4B, or have the protective layer113, the conductor layer112, and the protective layer113arranged in the order mentioned upward from the lower end as illustrated inFIG.4C. In the case where the protective layer113is located closer to the lower end than the conductor layer112as illustrated inFIGS.4A and4C, when folding the power generation module connected body10between adjacent power generation modules P, the protective layer113or the power generation module P is located on the inner side of the conductor layer112. This prevents an excessive bending force on the conductor layer112, and suppresses a break of the conductor. In the case where the protective layer113is located above the conductor layer112as illustrated inFIGS.4B and4C, the conductor layer112can be further protected and/or reinforced. The connection portion11is configured to satisfy the relationship “row-direction length C≥2L”, where L is the thickness in the vertical direction of the power generation modules P as illustrated inFIGS.4A to4C. In the case where the connection portion11is present above or below the power generation module P, the thickness L in the vertical direction of the power generation modules P is taken as thickness of the whole power generation module connected body10including the thickness of the connection portion11, as illustrated inFIGS.4A to4C. For example, the thickness L in the vertical direction of the power generation modules P is preferably 3 mm or less from the viewpoint of production technology. The lower limit of the thickness of the power generation modules P is preferably about 10 μm. Let n be the number (integer of 2 or more) of columns of the plurality of power generation modules P arranged in a matrix. When the column-direction length of the column-direction connection portions14in the y-th column is defined as Dy, in the power generation module connected body10, a first type row201satisfying the relationships D1≥2L and Dy≥Dy−1+2L (seeFIG.3A) and a second type row202satisfying the relationships Dn≥2L and Dy≥Dy+1+2L (seeFIG.3A) are alternately arranged along the column direction B. In other words, the column-direction length D of the column-direction connection portions14is 2L or more for the first type row201in the first column and increases by 2L or more with each increase in the number of columns. The column-direction length D of the column-direction connection portions14is 2L or more in the last column for the second type row202and increases by 2L or more with each decrease in the number of columns. In detail, as illustrated inFIG.3A, the column-direction length D of the 5 column-direction connection portions14which connect together the 5 power generation modules P (P11, P12, P13, P14, P15) of the first row and the 5 power generation modules P (P21, P22, P23, P24, P25) of the second row which are adjacent in the column direction B satisfies the relationships D1≥2L, D2≥D1+2L, D3≥D2+2L, D4≥D3+2L, D5≥D4+2L sequentially from the first column, forming the first type row201. Likewise, the column-direction length D of the 5 column-direction connection portions14which connect together the 5 power generation modules P (P31, P32, P33, P34, P35) of the third row and the 5 power generation modules P (P41, P42, P43, P44, P45) of the fourth row which are adjacent in the column direction B satisfies the relationships D1≥2L, D2≥D1+2L, D3≥D2+2L, D4≥D3+2L, D5≥D4+2L sequentially from the first column, forming the first type row201. Meanwhile, the column-direction length D of the 5 column-direction connection portions14which connect together the 5 power generation modules P (P21, P22, P23, P24, P25) of the second row and the 5 power generation modules P (P31, P32, P33, P34, P35) of the third row which are adjacent in the column direction B satisfies the relationships D1≥D2+2L, D2≥D3+2L, D3≥D4+2L, D4≥D5+2L, D5≥2L sequentially from the first column, forming the second type row202. Likewise, the column-direction length D of the 5 column-direction connection portions14which connect the 5 power generation modules P (P41, P42, P43, P44, P45) of the fourth row and the 5 power generation modules P (P51, P52, P53, P54, P55) of the fifth row which are adjacent in the column direction B satisfies the relationships D1≥D2+2L, D2≥D3+2L, D3≥D4+2L, D4≥D5+2L, D5≥2L sequentially from the first column, forming the second type row202. In this way, in the power generation module connected body10, the first type row201and the second type row202are alternately arranged along the column direction B. In the example illustrated inFIG.3A, the column-direction length D of the 5 column-direction connection portions14which connect together the 5 power generation modules P (P11to P15) of the first row and the 5 power generation modules P (P21to P25) of the second row which are adjacent in the column direction B satisfies the relationships D2=D1+2L, D3=D2+2L, D4=D3+2L, D5=D4+2L. In this case, the power generation modules P in the first row are offset with respect to each other by a distance equal to length L in the direction opposite to the column direction B. Hence, the power generation modules P in the n-th column are offset with respect to the power generation modules P in the first column by a distance equal to length L×(n−1) in the direction opposite to the column direction B. In the example illustrated inFIG.3A, the power generation module P15at the far right is offset with respect to the power generation module P11at the far left by a distance equal to length 4L in the direction opposite to the column direction B. The column-direction width E of the row-direction connection portions13satisfies the relationship E=WC−L×(n−1). Because the power generation module connected body10has 5 columns of power generation modules P (n=5) in this example, the relationship E=WC−4L is satisfied. Further, as illustrated inFIG.3A, opposing ends in the column direction B of the plurality of row-direction connection portions13arranged in the same row are aligned along the row direction A. At this point of time, the positions of one ends in the column direction B (upper ends inFIG.3A) of the respective the row-direction connection portions13which connect together the 5 power generation modules P (P11to P15) of the first row are aligned in the column direction B with the position of one end in the column direction B (upper end inFIG.3A) of the power generation module P11which is positioned lowermost in the column direction B among the 5 power generation modules P of the first row inFIG.3A. Further, the positions of the other ends in the column direction B (lower ends inFIG.3A) of the respective row-direction connection portions13which connect together the power generation modules of the first row are aligned in column direction B with the position of the other end (lower end inFIG.3A) of the power generation module P15positioned uppermost in the column direction B among the 5 power generation modules P of the first row inFIG.3A. Thus, opposing ends in the column direction B of the row-direction connection portions13do not protrude outward in the column direction B beyond any of the power generation modules P connected together with the row-direction connection portions13. It is thus possible to improve the storability of the power generation module connected body10. The relationship above that holds true for the row-direction connection portions13which connect together the power generation modules P (P11to P15) of the first row also holds true for the row-direction connection portions13which connect together the power generation modules P (P31to P35) of the third row, and for the row-direction connection portions13which connect together the power generation modules P (P51to P55) of the fifth row. For the row-direction connection portions13which connect together the power generation modules P (P21to P25) of the second row and the row-direction connection portions13which connect together the power generation modules P (P41to P45) of the fourth row, a relationship in which the above relationship is reversed left and right holds true. When the power generation module connected body10is configured such that the column-direction width E of the row-direction connection portions13satisfies the relationship E≤WC−L×(n−1), opposing ends in the column direction B of the plurality of row-direction connection portions13arranged in the same row can be aligned in the row direction A, thus improving design. As illustrated inFIGS.4A to4C, when the connection portion11is located to cover the entire surface along the lower end of the power generation module connected body10, opposing ends in the column direction B of the plurality of row-direction connection portions13arranged in the same row are aligned along the row direction A. With this configuration, it is possible to simplify the shape of the outer periphery of the connection portion11. Because it is possible to simplify the machining process of the connection portion11, it is possible to increase productivity. FIG.6is an enlarged view of another example of the column-direction width E of the row-direction connection portions13. In the example illustrated inFIG.6, the column-direction length D of the column-direction connection portions14which connect together the two power generation modules P (P11, P12) of the first row and the two power generation modules P (P21, P22) of the second row which are adjacent in the column direction satisfies the relationship D2=D1+2L. In this case, the power generation module P12positioned right to the power generation module P11is offset with respect to the power generation module P11by a distance equal to length L in the direction opposite to the column direction B. In the example illustrated inFIG.6, the column-direction width E of the row-direction connection portions13satisfies the relationship E=WC−L. The position of one end in the column direction B (upper end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P11and P12is aligned in column direction B with the position of one end in the column direction B (upper end inFIG.6) of the power generation module P11. Further, the position of the other end in the column direction B (lower end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P11and P12is aligned in column direction B with the position of the other end in the column direction B (lower end inFIG.6) of the power generation module P12. In the example illustrated inFIG.6, as opposed to the first row, the power generation module P22of the second row is offset with respect to the power generation module P21of the second row by a distance equal to length L in the column direction B. The position of one end in the column direction B (upper end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P21and P22is aligned in column direction B with the position of one end in the column direction B (upper end inFIG.6) of the power generation module P22. Further, the position of the other end in the column direction B (lower end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P21and P22is aligned in column direction B with the position of the other end in the column direction B (lower end inFIG.6) of the power generation module P21. FIG.6illustrates a row-direction connection portion13which connects together the power generation modules P (P11, P12) of the first and second columns in the first row, and a row-direction connection portion13which connects together the power generation modules P (P21, P22) of the first and second columns in the second row. The same relationship holds true for any row-direction connection portion13. Specifically, when the first row is taken as an example, the power generation module P13of the third column (not illustrated) is offset with respect to the power generation module P12of the second column by a distance equal to length L in the direction opposite to the column direction B. The position of one end in the column direction B (upper end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P (P12, P13) of the second and third columns is aligned in column direction B with the position of one end in the column direction B (upper end inFIG.6) of the power generation module P12. Further, the position of the other end in the column direction B (lower end inFIG.6) of the row-direction connection portion13which connects together the power generation modules P (P12, P13) of the second and third columns is aligned in column direction B with the position of the other end in the column direction B (lower end inFIG.6) of the power generation module P13. At this point of time, the row-direction connection portion13which connects together the power generation modules P (P12, P13) of the second and third columns is offset with respect to the row-direction connection portion13which connects together the power generation modules P (P11, P12) of the first and second columns by a distance equal to length L in the direction opposite to the column direction B. Thus, when the column-direction width E of the row-direction connection portions13satisfies the relationship E=WC−L, as opposed to the example illustrated inFIG.3A, opposing ends in the column direction B of the plurality of row-direction connection portions13arranged in the same row are offset with respect to each other by a distance equal to length L along the column direction B. Thus, even if the column-direction width E of the row-direction connection portions13does not satisfy the relationship E≤WC−L×(n−1), the power generation module connected body10is configured such that the relationship E≤WC−L is satisfied. With this configuration, it is possible to prevent opposing ends in the column direction B of the row-direction connection portions13from protruding outward in the column direction B beyond any of the power generation modules P connected together with the row-direction connection portions13. It is thus possible to improve the storability of the power generation module connected body10. With reference toFIGS.7A to9B, a process in which the power generation module connected body10according to this embodiment is folded from an unfolded state to be in a stored state is described below. FIG.7Ais a top view of the power generation module connected body10in a state of being folded in the row direction (hereafter referred to as “row direction folded state” as appropriate).FIG.7Bis a front view of the power generation module connected body10in a state of being folded in the row direction. As a result of being folded in the row direction A from the unfolded state illustrated inFIGS.3A and3B, the power generation module connected body10is put in a row direction folded state as illustrated inFIGS.7A and7B. In detail, as a result of alternate folding (i.e. accordion folding) in the row direction between power generation modules P of columns adjacent in the row direction, the power generation module connected body10is put in a row direction folded state. First, the power generation modules P (P11, P21, P31, P41, P51) of the first column are folded so as to overlap the back side of the power generation modules P (P12, P22, P32, P42, P52) of the second column (mountain folding). Next, the power generation modules P of the first and second columns overlapping in the vertical direction are folded so as to overlap the front side of the power generation modules P (P13, P23, P33, P43, P53) of the third column (valley folding). Next, the power generation modules P of the first to third columns overlapping in the vertical direction are folded so as to overlap the back side of the power generation modules P (P14, P24, P34, P44, P54) of the fourth column (mountain folding). Then, the power generation modules P of the first to fourth columns overlapping in the vertical direction are folded so as to overlap the front side of the power generation modules P (P15, P25, P35, P45, P55) of the fifth column (valley folding). By accordion-folding the power generation module connected body10in the row direction so as to alternate between mountain folding and valley folding in this way, the row direction folded state illustrated inFIGS.7A and7Bcan be achieved. The parts subjected to mountain folding and the parts subjected to valley folding may be replaced with each other. As described above, the row-direction connection portions13are configured to satisfy the relationship “row-direction length C≥2L”. Accordingly, the length of the row-direction connection portions13between power generation modules P is sufficient in both of the parts subjected to mountain folding and the parts subjected to valley folding as illustrated inFIG.7B, enabling smooth folding. FIG.8is a partially enlarged sectional view of the power generation module connected body10in a row direction folded state, along the column direction. As illustrated inFIG.8, folding is made so that the length D along the column direction of the column-direction connection portions14which connect together the power generation modules P of the first row (P11, P12, P13, P14, P15) and the power generation modules P of the second row (P21, P22, P23, P24, P25) which are adjacent in the column direction increases in the downward direction. Likewise, folding is made so that the column direction length D of the column-direction connection portions14which connect together the power generation modules P of the third row and the power generation modules P of the fourth row which are adjacent in the column direction increases in the downward direction (not illustrated). On the other hand, folding is made so that the column direction length D of the column-direction connection portions14which connect together the power generation modules P of the second row and the power generation modules P of the third row which are adjacent in the column direction, and the column-direction length D of the column-direction connection portions14which connect together the power generation modules P of the fourth row and the power generation modules P of the fifth row which are adjacent in the column direction increase in the upward direction. FIG.9Ais a top view of the power generation module connected body10in a stored state.FIG.9Bis a side view of the power generation module connected body10in a stored state. As a result of accordion-folding the power generation modules P of the rows in the column direction from the row direction folded state illustrated inFIGS.7A and7Band overlapping all power generation modules P, the power generation module connected body10is put in a stored state illustrated inFIGS.9A and9B. First, the power generation modules P (P11, P12, P13, P14, P15) of the first row overlapping in the vertical direction are folded so as to overlap the front side of all of the power generation modules P (P21, P22, P23, P24, P25) of the second row overlapping in the vertical direction (valley folding). Next, the power generation modules P of the first and second rows overlapping in the vertical direction are folded so as to overlap the back side of all of the power generation modules P (P31, P32, P33, P34, P35) of the third row overlapping in the vertical direction (mountain folding). Next, the power generation modules P of the first to third rows overlapping in the vertical direction are folded so as to overlap the front side of all of the power generation modules P (P41, P42, P43, P44, P45) of the fourth row overlapping in the vertical direction (valley folding). Then, the power generation modules P of the first to fourth rows overlapping in the vertical direction are folded so as to overlap the back side of all of the power generation modules P (P51, P52, P53, P54, P55) of the fifth row overlapping in the vertical direction (mountain folding). By accordion-folding the power generation module connected body10in a row direction folded state in the column direction so as to alternate between mountain folding and valley folding in this way, the stored state illustrated inFIGS.9A and9Bcan be achieved. When the power generation module connected body10transitions to a stored state by being further folded from a row direction folded state, the surfaces of adjacent power generation modules P can be made to overlap each other in the part in which the column direction length D of the column-direction connection portions14which connect together the power generation modules P adjacent in the column direction increases in the downward direction as illustrated inFIG.8. By such folding, the column direction width D of the column-direction connection portions14which connect together power generation modules P with a longer distance in the vertical direction in a folded state is longer, so that the power generation module connected body10can be folded smoothly. In more detail, the column direction width D of the column-direction connection portions14is 2L or more longer than the column direction width D of the column-direction connection portions11located immediately on the inner side in a folded state, and therefore smooth folding can be achieved without being obstructed by the column-direction connection portions14located on the inner side. The storability in a folded state can thus be improved. Modifications of the power generation module connected body10are described below.FIG.10is a top view of a power generation module connected body10ain an unfolded state according to the first modification of the power generation module connected body10. The power generation module connected body10ahas a configuration similar to that of the power generation module connected body10except for the configuration described below. In the case of the power generation module connected body10a, the row-direction width C of the row-direction connection portions13of the connection portion11asatisfies the following relationships. The power generation module connected body10ahas, alternately along the row direction A, a first type column203satisfying the relationships C1≥2L and Cx≥Cx−1+2L (seeFIG.10) and a second type column204satisfying the relationships Cm≥2L and Cx≥Cx+1+2L (seeFIG.10), where m is an integer of 2 or more which represents the number of rows of the power generation modules P arranged in a matrix and Cxis the row-direction length of the row-direction connection portions13in the x-th row. In other words, the row-direction length C of the row-direction connection portions13is 2L or more in the first row for the first type column203and increases by 2L or more with each increase in the number of rows. The row-direction length C of the row-direction connection portions13is 2L or more in the last row for the second type column204and increases by 2L or more with each decrease in the number of rows. In detail, in the power generation module connected body10aas illustrated inFIG.10, the row-direction length C of the row-direction connection portions13which connect together the power generation modules P (P11, P21, P31, P41, P51) of the first column and the power generation modules P (P12, P22, P32, P42, P52) of the second column which are adjacent in the row direction A satisfies the relationships C1≥C2+2L, C2≥C3+2L, C3≥C4+2L, C4≥C5+2L, C5≥2L sequentially from the first row, forming the second type column204. Likewise, the row-direction length C of the row-direction connection portions13which connect together the power generation modules P (P13, P23, P33, P43, P53) of the third column and the power generation modules P (P14, P24, P34, P44, P54) of the fourth column which are adjacent in the row direction A satisfies the relationships C1≥C2+2L, C2≥C3+2L, C3≥C4+2L, C4≥C5+2L, C5≥2L sequentially from the first row, forming the second type column204. Meanwhile, the row-direction length C of the connection portions13which connect together the power generation modules P (P12, P22, P32, P42, P52) of the second column and the power generation modules P (P13, P23, P33, P43, P53) of the third column which are adjacent in the row direction A satisfies the relationships C1≥2L, C2≥C1+2L, C3≥C2+2L, C4≥C3+2L, C5≥C4+2L sequentially from the first row, forming the first type column203. Likewise, the row-direction length C of the connection portions13which connect together the power generation modules P (P14, P24, P34, P44, P54) of the fourth column and the power generation modules P (P15, P25, P35, P45, P55) of the fifth column which are adjacent in the row direction A satisfies the relationships C1≥2L, C2≥C1+2L, C3≥C2+2L, C4≥C3+2L, C5≥C4+2L sequentially from the first row, forming the first type column203. Thus, in the power generation module connected body10a, the first type row201and the second type row202are alternately arranged along the column direction. In the power generation module connected body10a, the first row is the first type row201and the first column is the second type column204, or the first row is the second type row202and the first column is the first type column203. In other words, the power generation module connected body10asatisfies the condition wherein the first row is the first type row201and the first column is the second type column204, or the condition wherein the first row is the second type row202and the first column is the first type column203. Specifically, as illustrated inFIG.10, in the power generation module connected body10a, the first row is the first type row201and the first column is the second type column204. The power generation module connected body10ahaving the structure described above can be folded from any of the row direction and the column direction to be in a stored state, in addition to having the same advantageous effect as that of the power generation module connected body10. Moreover, the power generation module connected body10asatisfies the condition wherein the first row is the first type row201and the first column is the second type column204, or the condition wherein first row is the second type row202and the first column is the first type column203. Hence, each power generation module P is prevented from being far from both of a power generation module P adjacent in the row direction and a power generation module P adjacent in the column direction. The stability of the power generation modules P can thus be improved. As with the column-direction width E of the row-direction connection portions13discussed above for the power generation module connected body10, the row-direction width F of the column-direction connection portions14of the power generation module connected body10asatisfies the relationship F≤WR−L. Further, opposing ends in the row direction A of the column-direction connection portions14do not protrude outward along the row direction A beyond any of the power generation modules P connected with the row-direction connection portions14. Thus, it is possible to further improve the storability of the power generation module connected body10awhile providing the same advantageous effect as that of the power generation module connected body10. Further, in the example illustrated inFIG.10, the row-direction width F of the column-direction connection portions14satisfies the relationship F≤WR−L×(m−1). In this example, the power generation module connected body10ahas 5 rows of power generation modules P (m=5), satisfying the relationship F≤WR−4L. In the example illustrated inFIG.10, F=WR−4L holds. Also as illustrated inFIG.10, opposing ends in the row direction A of the plurality of column direction-connection portions14arranged in the same column are aligned. Thus, it is possible to further improve the design and productivity of the power generation module connected body10awhile providing the same advantageous effect as that of the power generation module connected body10. FIG.11is a top view of a power generation module connected body10a′ in an unfolded state according to a modification of the power generation module connected body10a. The power generation module connected body10a′ has the same configuration as the power generation module connected body10aexcept for the configuration described below. As illustrated inFIG.11, the row-direction connection portions13of the power generation module connected body10a′ are each divided into two along the column direction B. Similarly, the column-direction connection portions14of the power generation module connected body10a′ are each divided into two along the row direction A. Even in the case of a power generation module connected body10a′ which includes row-direction connection portions13and column-direction connection portions14having such a configuration, with the row-direction connection portions13and column-direction connection portions14being included that satisfy the same relationships as those of the power generation module connected body10a, it is possible to provide the same advantageous effect as that of the power generation module connected body10a. FIG.12Ais a partially enlarged sectional view of a power generation module connected body10bin an unfolded state according to a second modification of the power generation module connected body10. The power generation module connected body10bhas the same configuration as the power generation module connected body10except that the power generation modules P are located above and below a connection portion11b. In addition to the same advantageous effect as that of the power generation module connected body10, the power generation module connected body10bhas an effect of, when folded between adjacent power generation modules P, reducing the burden on the connection portion11bassociated with the folding, because the power generation modules P are located on the inner side of the connection portion11b. FIG.12Bis a partially enlarged sectional view of a power generation module connected body10cin an unfolded state according to a third modification of the power generation module connected body10. The power generation module connected body10chas the same configuration as the power generation module connected body10except that a connection portion11cis located to connect adjacent power generation modules P to each other near the vertical center of the power generation modules P. In addition to the same advantageous effect as that of the power generation module connected body10, the power generation module connected body10chas an effect of, when folded between adjacent power generation modules P, reducing the burden on the connection portion11cassociated with the folding, because the power generation modules P are located on the inner side of the connection portion11c. FIG.13is a top view of a power generation module connected body10din an unfolded state according to a fourth modification of the power generation module connected body10. The power generation module connected body10dis the same as the power generation module connected body10except that power generation modules P′ which are circular in top view are used instead of the power generation modules P which are rectangular in top view. In this case, as illustrated inFIG.13, the row-direction length C of the row-direction connection portions13at the connection portion11dis equal to the shortest interval along the row direction A between the power generation modules P′ connected together by the row-direction connection portions13. Likewise, as illustrated inFIG.13, the column-direction length D of the column-direction connection portions14at the connection portion11dis equal to the shortest interval along the column direction between the power generation modules P′ connected together by the column-direction connection portions14. The length WR′ along the row direction A of the power generation modules P′ and the length WC′ along the column direction B of the power generation modules P′ are both equal to the diameter of circles which denote the power generation modules P′. As long as the connection portion11dsatisfies the relationships described above, the power generation modules P′ are not limited to be circular in top view and may have any other shape in top view, such as a polygon. The above merely describes one of the disclosed embodiments, and a variety of modifications may be made within the scope of the claims. For example, while the arrangements of the power generation modules P and P′, the connection portions11to11d, and the like are described above using rows and columns, such rows and columns are defined for the purpose of illustration, and may be replaced with each other. Moreover, the upward direction and the downward direction are defined for the purpose of illustration, and may be replaced with each other. Although the above describes the power generation module connected bodies10to10din which the power generation modules P or P′ are arranged in a matrix of 5 rows and 5 columns, the power generation modules P or P′ may be arranged in a matrix of 2 rows or more and 2 columns or more. In each of the connection portions11to11daccording to this embodiment, for example, the conductor layer112may be composed of a flexible printed circuit board (FPC) in which a conductor such as copper foil is sandwiched between insulators such as a base film and a cover film. In this case, each of the connection portions11to11ddoes not need include the protective layer113because the conductor layer112composed of an FPC has a protection function. FIGS.14A to14Cillustrate examples of the power generation module connected body10(10ato10d) in which, when the conductor layer112is composed of an FPC, the conductor layer112is located so as to connect adjacent power generation modules P or P′ near the vertical center. The power generation module connected body10(10ato10d) refer to the power generation module connected body10,10a,10b,10cor10d, and means that the configurations illustrated inFIGS.14A to14Care applicable to any of the power generation module connected bodies described above. As illustrated inFIGS.14A to14C, when the conductor layer112is composed of an FPC, each of the connection portions11to11dmay include the protective layer113. The protective layer113may be located to cover the power generation module P or P′ excluding part of the front side as illustrated inFIG.14A. Alternatively, the protective layer113may be located to cover the connecting part between the power generation module P or P′ and the conductor layer112from above and below as illustrated inFIG.14B. Alternatively, the protective layer113may be located to cover the conductor layer112from above and below as illustrated inFIG.14C. As mentioned above with reference toFIGS.4A to4C, in the case where the conductor layer112and/or the protective layer113is present above or below the power generation module P, P′, the thickness L of the power generation module P, P′ in the vertical direction is taken to be the thickness of the whole power generation module connected body10to10dincluding the thickness of the conductor layer112and/or the protective layer113. The form of connection of the main body20to the power generation modules P, P′ in the power generation device1according to this embodiment is not limited. For example, the main body20may be integrated with any of the power generation modules P, P′, or connected to an end of any of the power generation modules P, P′. The main body20may be removable from the power generation module P, P′. The power generation module connected bodies10to10daccording to this embodiment are not limited to be used together with the main body20to form the power generation device1, and may be used independently of the main body20. In detail, the power generation module connected bodies10to10daccording to this embodiment may include, for example, an interface having the same functions as the external IF26of the main body20and, when an external device is connected directly to the interface, supply electric power to the connected external device. As one aspect of the power generation modules P, P′ according to this embodiment, photoelectric conversion modules including the above-mentioned solar cells as the power generation section12may be used. As one aspect of the power generation module connected bodies10to10daccording to this embodiment, a photoelectric conversion module connected body using the above-mentioned photoelectric conversion modules may be used. As one aspect of the power generation device1, a photoelectric conversion device including the above-mentioned photoelectric conversion module connected body may be used. Each structure described with regard to the power generation module connected bodies10to10daccording to this embodiment is also applicable to any panel connected body including any flat panels not limited to the power generation modules P, P′ and any connection portion not limited to a connection portion including a conductor. INDUSTRIAL APPLICABILITY It is therefore possible to provide a panel connected body, a power generation module connected body and a power generation device having improved storability in a folded state. REFERENCE SIGNS LIST 1power generation device10,10a,10a′,10b,10c,10dpower generation module connected body11,11a,11b,11c,11dconnection portion12power generation section13row-direction connection portion14column-direction connection portion20main body21interface22booster circuit section23power generation module voltage detection section24AC adapter voltage detection section25rechargeable battery26external interface27charge/discharge control circuit28controller30AC adapter31power outlet32AC/DC converter112conductor layer113protective layer201first type row202second type row203first type column204second type columnA row directionB column directionC row-direction length of row-direction connection portionD column-direction length of column-direction connection portionE column-direction width of row-direction connection portionF row-direction width of column-direction connection portionL thickness of power generation module in vertical directionP, P′ power generation moduleWR, WR′ length of power generation module along row directionWC, WC′ length of power generation module along column direction | 52,038 |
11942896 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION In the figures,1indicates a photovoltaic system. The photovoltaic system1comprising one or more photovoltaic modules2. Each photovoltaic module2has a plurality of photovoltaic panels (not illustrated), preferably connected in series, for forming a group (or module) of photovoltaic panels. The photovoltaic modules2are connected to an inverter3. A protection switch5is inserted in a connecting branch4which connects the photovoltaic modules2(or a single photovoltaic module2) to the inverter3; the photovoltaic system1comprises a plurality of protection switches5, inserted between the inverter3and respective photovoltaic modules2. A further electric protection6is inserted downstream of the inverter3, between the inverter3and an AC electric mains network7. 8indicates an opening coil of the protection switch5. That coil8is a relay for activating the protection switch5. The photovoltaic system1also comprises at least one protection device9, configured to detect the presence of an electric arc in the photovoltaic system1. The protection device9is inserted in the connecting branch4which connects the photovoltaic modules2to the inverter3. The branch4is defined by a cable comprising un first conductor4A and a second conductor4B. Of the first conductor4A and the second conductor4B, one is positive and the other is negative. Hereinafter, for the sake of simplicity, the first conductor4A will be referred to as the positive conductor4A and the second conductor4B as the negative conductor4B. Nevertheless, the first conductor4A could be negative and the second conductor4B could be negative. The protection device9is configured to generate a fault signal, in response to the detection of an electric arc. The protection device9is connected to the opening coil8of the protection switch5, in order to open the switch by means of the fault signal. The protection device9comprises a first sensor10couplable to an electric cable for detecting the current flowing through it. Operatively, the first sensor10is coupled to the connecting branch4which connects the modules2to the inverter3. The first sensor10preferably comprises a first ring101of ferromagnetic material (for example ferrite). That simplifies installation of the device9on pre-existing systems1, avoiding cutting the cables. Preferably, the first ring101has a first and a second half-ring which are movable relative to each other between an open position and a closed position. That further simplifies installation of the device9on pre-existing systems1, also avoiding having to detach one end of a cable from a terminal or having to open a connector. The protection device9comprises a second sensor19couplable to the electric cable for detecting a second signal, representing the direct current (or low frequency alternating) component of the current flowing through it. Operatively, the second sensor19is coupled to the connecting branch4which connects the modules2to the inverter3. The second sensor19preferably comprises a second ring191of ferromagnetic material (for example ferrite). It should be noticed that, in one embodiment the second sensor19is interposed between the first sensor10and the inverter3. It another embodiment the first sensor10is interposed between the second sensor19and the inverter3. Preferably, the second ring191(similarly to the first ring) has a first and a second half-ring which are movable relative to each other between an open position and a closed position. The second sensor19also comprises a Hall effect probe192. Preferably, the Hall effect probe192is coupled to the second ring191. In one embodiment, only the first conductor4A is inserted into the first ring101and into the second ring191(whilst the second conductor4B is not). In one embodiment, only the second conductor4B is inserted into the first ring101and into the second ring191(whilst the first conductor4A is not). In one embodiment, both of the conductors, positive4A and negative4B of the cable which defines the connecting branch are inserted into the first ring101and into the second ring191, parallel to each other in the same direction. In another embodiment, the conductors, positive4A and negative4B are inserted into the first ring101and into the second ring191in opposite directions. In other words, having defined a direction of the cable from the module2to the inverter3, the first conductor4A passes first in the first ring101and then in the second ring191(in the direction of the cable), whilst the second conductor4B passes first in the second ring191and then in the first ring101(in the direction of the cable). Therefore, the first conductor4A and the second conductor4B pass each other in opposite directions. In a further embodiment, the conductors, positive4A and negative4B are inserted into the first ring101in opposite directions, and into the second ring191in the same direction. Therefore, the first conductor4A and the second conductor4B pass each other in opposite directions only at the first ring101. Thanks to these system solutions with insertion of the first conductor4A and the second conductor4B passing each other in opposite directions, there is greater efficiency in identifying disturbances in several operating conditions. In one embodiment, the device9comprises a third sensor26, configured to detect a residual current (and therefore to detect a ground fault). The third sensor26comprises a third ring of ferromagnetic material. In one embodiment, the third sensor26is interposed between the second sensor19and the inverter3. The third sensor26is connected to the processor14(that is to say, to the circuit board11) for sending it a signal representing the residual current. In one embodiment, the device9comprises a third threshold comparator, interposed between the third sensor26and the processor14. The processor14(that is to say, the circuit board11) is configured to open the protection switch5as a function of the signal generated by the third sensor (that is to say, as a function of the threshold value of the third threshold comparator being exceeded). In one embodiment, the processor14(that is to say, the circuit board11) is configured to generate an alarm signal as a function of the signal generated by the third sensor. The protection device9also comprises a circuit board11. Preferably, the first sensor10and the second sensor19are separate from the circuit board11for easy installation and to reduce interference and overheating. The protection device9(in particular the circuit board11of the protection device9) comprises a conditioning stage12for a signal generated by the first sensor10. The conditioning stage12has a bandpass filter, for conditioning the signal generated by the sensor10. The protection device9(in particular the circuit board11of the protection device9) comprises a first comparator13(preferably a threshold comparator); the first comparator13has a first, preset, adjustable voltage reference value and is configured to receive as input the first conditioned signal. The protection device9(in particular the circuit board11of the protection device9) comprises a second comparator20(preferably a threshold comparator); the second comparator20has a second, preset, adjustable voltage reference value and is configured to receive as input the second signal generated by the second sensor19. Moreover, the protection device9(in particular the circuit board11of the protection device9) comprises a processor14for generating a fault signal as output from the protection device9. It should be noticed that the first comparator13and/or the second comparator20could also be defined by the processor14. The protection device9(in particular the circuit board11of the protection device9) also comprises a counter15or timer. The processor14is programmed to activate the counter in response to the first signal generated and conditioned exceeding the first reference value (of the first comparator13), combined with the second signal generated exceeding the second reference value (of the second comparator20). In one embodiment, the processor14is programmed to generate the fault signal as a function of a further case of the first signal exceeding the first reference value, combined with a further case of the second signal exceeding the second reference value, a predetermined time interval after the first combined values being exceeded. It should be noticed that, preferably, the predetermined time interval is adjustable, that is to say, can be set to another value. That increases the possibilities for adapting the protection device9to the conditions of the system1into which it is inserted, during the step of installing, making the device itself particularly reliable and robust. Therefore, preferably, the processor14is configured to allow an adjustment of the predetermined time interval. Moreover, preferably, the protection device9(in particular the circuit board11of the protection device9) comprises a memory16. Preferably, the protection device9(in particular the circuit board11of the protection device9) comprises an indicator17, having at least one on configuration and one off configuration. Preferably, the indicator17is a light indicator (for example an LED or another warning light), but may also be acoustic or of another type. Preferably, the processor14is programmed to record in the memory16data representing a fault signal generating event; that is to say, the processor14is programmed to record in the memory the events of detection of electric arcs in the photovoltaic system1into which the protection device9is inserted. Preferably, the processor is programmed to set the indicator17in the on configuration, if the fault signal is generated, that is to say, following detection of an electric arc in the photovoltaic system1into which the protection device9is inserted. The protection device9also comprises a power source18, preferably 200V AC. The conditioning stage12is preferably configured to cut the frequencies lower than a minimum value (for example 20 kHz) and higher than a maximum value (for example 2.5 MHz). Moreover, the system1comprises a plurality of modules2(that is to say, groups or arrays of modules2), each of which is connected to the inverter3by means of a respective connecting branch4. For example, the system1may comprise six groups of modules2(in which the modules of each group are connected to each other in series). The system comprises a plurality of protection devices9, each inserted into a respective branch4to detect the presence of an electric arc in the respective module2(or group of modules2) and to generate a fault signal which opens a respective protection switch5. The system1, according to one aspect of this invention, comprises a processing unit22connected to the protection devices9of the modules2(or groups of modules2), in particular to the circuit boards11of the protection devices9. In one embodiment, the system1also comprises an output unit23of the processing unit22. The output unit23may include, for example, a screen and/or a warning light. Moreover, the processing unit22(and/or the circuit board11) may include an ethernet communication cable and/or a system for connection to the wi-fi network. The processing unit22(and/or the circuit board11) also has an IP address. In one embodiment, the system1also comprises an input unit24of the processing unit22. The input unit24may be local or remote. The input unit24may include, for example, one or more pushbuttons or a keyboard. Preferably, the input unit24is configured to allow the operator, during system1set-up, to control the selector of each device9in order to select a filter defining a respective pass band for each device9, and/or to start, for each device9, an adjustment command in order to automatically perform a scan of the frequency interval, in order to select the appropriate bandpass filter (as illustrated in this description) excluding false positives. Moreover, the input unit24may be configured to perform polling in order to verify a condition of the system or part of it. In one embodiment, the system1also comprises a power source25of the processing unit22. According to one aspect of this invention, in addition two or more cables, defining respecting connecting branches4which connect respective modules2(or groups of modules2) to the inverter, are connected to a single, multi-channel protection device9. In one embodiment, that multi-channel protection device9comprises a plurality of first sensors10and a plurality of second sensors19, configured to detect the currents flowing through respective branches4and connected to a single circuit board11(in particular, to a single processor14). In this embodiment, the circuit board11therefore has a plurality of inputs. The circuit board11may comprise, for each first sensor10, a respective conditioning stage12and a respective first comparator13and, for each second sensor19, a respective second comparator20(in this way, it is possible to set different pass band and threshold values for the various modules2or groups of modules); or, the first sensors10of the plurality may be connected to a single conditioning stage12and to a single first comparator13and the second sensors19of the plurality may be connected to a single second comparator20(in this way, there is an obvious saving in terms of costs). Preferably, the circuit board11(that is to say, the processor14) is configured to divide a period of time into portions dedicated to the respective modules2or groups of modules2. In one embodiment, two or more cables4are inserted into a first ring101(defining a single first sensor10) and into a second ring191(defining a single second sensor19). In this way, if a fault signal is detected, all of the modules2concerning the two or more cables4are disconnected (by opening of a switch5); on the other hand, there is a saving in terms of costs. It should be noticed that there is also a solution in which two or more cables4of respective modules (or strings) are inserted into the same first ring101and second ring191and the positive and negative conductors of each cable4pass each other in opposite directions as described above. This invention also makes available a method for protecting a (direct current) electrical system1. In one embodiment, the system1is a photovoltaic system. The photovoltaic system1has at least one photovoltaic module2provided with a plurality of photovoltaic panels (preferably connected in series), an inverter3connected downstream of the photovoltaic modules2, a protection switch5inserted between the inverter and the photovoltaic module. The photovoltaic system1is also equipped with at least one protection device9, preferably inserted in a connecting branch4which connects the photovoltaic module2to the inverter, in order to detect the presence of an electric arc in the system1and generate a fault signal; the fault signal is an activation signal of a coil8(that is to say, a relay) for opening the protection switch5. Installation of the protection device9comprises steps of coupling the sensor10of the protection device9to the system1, and adjusting (that is to say, setting) the protection device9, to adapt the protection device9to the system1to which it is coupled. Coupling the protection device9to the system1involves inserting a cable, defining the connecting branch4which connects the photovoltaic module2to the inverter3, into a first through hole of the protection device9: that first through hole is defined by a first ring101of ferromagnetic material forming the sensor10. Coupling the protection device9to the system1involves inserting the cable into a second through hole of the protection device9: that second through hole is defined by a second ring191of ferromagnetic material to which a Hall effect probe192is coupled. The second ring191and the probe192form the sensor19. In one embodiment, the cable comprises un first conductor4A and a second conductor4B. In one embodiment, the first conductor4A is a positive wire and the second conductor4B is a negative wire (in another embodiment, vice versa). A first direction of insertion and a second direction of insertion (opposite to the first direction) are defined. The first direction of insertion is defined from the one or more modules2to the inverter3, the second direction of insertion is defined from the inverter3to the one or more modules2. In one embodiment, the first conductor4A is inserted into the first ring101in the first direction of insertion and the second conductor4B is inserted into the first ring101in the second direction of insertion. Therefore, the first conductor4A and the second conductor4B pass each other in opposite directions at the first ring101. In one embodiment, the first conductor4A is inserted into the first ring101and into the second ring191in the first direction of insertion and the second conductor4B is inserted into the first ring101and into the second ring191in the second direction of insertion. Therefore, the first conductor4A and the second conductor4B pass each other in opposite directions at the first ring101and the second ring191. These embodiments make the system particularly effective at distinguishing between disturbances and an electric arc. Moreover, the method in one embodiment comprises inserting the cable4(that is to say, the first conductor4A and the second conductor4B) into a third ring of ferromagnetic material defining a third sensor26. The third sensor26detects a residual current, and therefore a ground fault. The third sensor26is connected to the processor14which, as a function of the signal generated by the third sensor26, opens the protection switch5. Adjusting the protection device9comprises a step of setting a first voltage reference value of a first comparator13. Adjusting the protection device9comprises a step of setting a second voltage reference value of a second comparator20. Moreover, it comprises a step of setting a predetermined time interval (for the timer15, that is to say, for the processor14). The processor14is programmed to generate the fault signal as a function of a first signal generated by the first sensor10(and conditioned by the conditioning stage12) exceeding the first reference value, combined with the second signal generated by the second sensor19exceeding the second reference value, in at least two successive moments after the predetermined time interval. In particular, the condition of the second signal exceeding the second reference value is a condition necessary for the second signal exceeding the first reference value in at least two successive moments within the predetermined time interval to be indicative of the presence of an electric arc. Those adjusting steps occur after test steps performed on the photovoltaic system1, in two operating conditions: in the presence of a simulated electric arc and one in the absence of an electric arc in the system, but with the system operating (with its normal effectiveness). Preferably, adjusting the protection device comprises setting or adjusting the bandpass filter of the conditioning stage12. Preferably, adjusting the protection device9, in particular with reference to the conditioning stage12, comprises selecting one filter of three or more bandpass filters, defining respective bands occupying different, consecutive portions of a predetermined frequency interval. That adjusting is performed as a function of the amplitude values of the signal generated and conditioned (that is to say, downstream of the conditioning module), in the above-mentioned two operating configurations of the photovoltaic system1. The following paragraphs, listed with alphanumeric references, are example, non-limiting ways of describing this invention. A. Device9for protecting a direct current electrical system1having one or more modules2from electric arcs, the device comprising:a (first) sensor10provided with a (first) ring of ferromagnetic material configured to generate a (first) signal, representing a current flowing through a cable inserted into the ring;a conditioning stage, having a bandpass filter, for conditioning the (first) signal generated by the (first) sensor;a (first) threshold comparator, having a (first), preset, adjustable voltage reference value, the (first) comparator being configured to receive as input the (first) signal conditioned by the conditioning stage;a processor, programmed to generate a fault signal in response to an occurrence of the first signal exceeding the (first) reference value of the (first) comparator13. A1. The device9according to paragraph A, comprising a counter15, wherein the processor14is programmed:to activate the counter15upon occurrence of the first signal exceeding the (first) reference value of the (first) comparator13;to generate a fault signal as a function of the amplitude of the (first) signal generated and conditioned staying above the (first) reference value for at least a predetermined time interval. A2. The device9according to paragraph A or paragraph A1.1, further comprising:a second sensor19, configured to generate a second signal representing a direct current component of the current flowing through the cable;a second threshold comparator20, having a second, preset, adjustable voltage reference value, the second comparator20being configured to receive as input the second signal generated by the second sensor19, wherein the processor14is programmed to generate a fault signal in response to the occurrence of both of the following conditions, combined:the first signal exceeds the first reference value of the first comparator13,the second signal exceeds the second reference value of the second comparator20. A2.1. The device9according to paragraph A2, including a counter15, wherein the processor14is programmed:to activate the counter15upon occurrence of both the conditions of the first signal exceeding the first reference value of the first comparator13and the second signal exceeding the second reference value of the second comparator20;to generate a fault signal as a function of the amplitude of the first signal generated and conditioned staying above the first reference value and the amplitude of the second signal staying above the second reference value, for at least a predetermined time interval. A2.2. The device9according to paragraph A2 or paragraph A2.1, wherein the bandpass filter of the conditioning stage12has a pass band placed in an interval of frequencies which are higher than the frequency of the component detected by the second sensor19. A3. The device9according to any one of paragraphs A and A2.2, wherein the conditioning stage12has two or more bandpass filters, operatively connected in parallel and defining bands which occupy different, consecutive portions of a predetermined frequency interval, and wherein the device further comprises a selector connected to the conditioning stage12and configured to set a bandpass filter alternative to the other bandpass filter or filters. A3.1. The device9according to paragraph A3, wherein the processor14is configured to save in a database, for the fault signal generated by the processor, a record including the voltage value of the output signal from the conditioning stage upon occurrence of the fault signal and/or a piece of information relative to the bandpass filter selected when the fault signal occurred. A3.1.1. The device9according to A3.1, further comprising a user interface21, connected to the processor14and programmed to receive from a user, upon occurrence of the fault signal generated by the processor, a false positive indication (or command), wherein the record further includes the false positive indication. A3.1.2. The device9according to paragraph A3.1 or paragraph A3.1.1, wherein the record also includes a time indication relative to the moment in which the fault signal occurred. A3.1.3. The device9according to any one of paragraphs A3.1 to A3.1.2, wherein the record also includes a radiation to earth value at the moment in which the fault signal occurred. A3.1.4. The device9according to any one of paragraphs A3.1 to A3.1.3, wherein the record also includes a value of power supplied by the electrical system1at the moment in which the fault signal occurred. A4. The device9according to any one of paragraphs A to A3.1.4, comprising a screen connected to the processor14and configured to display in real time the voltage value of the first signal conditioned by the conditioning stage12. A5. The device9according to any one of paragraphs A to A4, comprising a screen connected to the processor14configured to display in real time the voltage of the first signal generated by the first sensor10, upstream of the conditioning stage12, in a spectrum of frequencies of the first signal. A6. The device9according to any one of paragraphs A to A5, comprising a second sensor19and a screen connected to the processor14, wherein the second sensor is configured to generate a second signal representing a direct current component of the current flowing through the cable, wherein the screen is also configured to display in real time the voltage value of the second signal generated by the second sensor19. B. A direct current electrical system1, comprising: one or more modules2; an inverter3connected downstream of the one or more modules2; one or more protection switches5inserted between the inverter3and the modules2; at least one protection device9, inserted in a connecting branch4which connects the one or more modules2to the inverter3, in order to detect the presence of an electric arc in the system1and generate a fault signal and transmit it to the protection switch5in order to open the switch, wherein the protection device9is a protection device according to any one of paragraphs A to A5.1. C. An inverter3comprising a protection device9according to one of paragraphs A to A5.1. D. A method for protecting an electrical system1having one or more modules2, wherein the method comprises the following steps: providing a protection switch5and a protection device9; installing the protection switch and the protection device in a connecting branch which connects the one or more modules2, wherein the protection device9is programmed to generate a fault signal and transmit it to the protection switch in order to open the switch, wherein the step of installing includes the following sub-steps:inserting a cable, defining the connecting branch4which connects the one or more modules2, into a first through hole of the protection device9, the first through hole being defined by a first ring101of ferromagnetic material forming a first sensor10configured to generate a first signal, representing a current flowing through the cable;adjusting the protection device9by setting a first reference value of a first threshold comparator13configured to receive the first signal downstream of a conditioning stage12connected downstream of the first sensor10. D1. The method according to paragraph D, wherein the step of installing includes a sub-step of connecting a second sensor19to the cable defining the connecting branch4, wherein the second sensor is configured to generate a second signal representing a direct current component of the current flowing through the cable, wherein the sub-step of adjusting the protection device9includes setting a second reference value of a second threshold comparator20configured to receive the second signal, and wherein the fault signal is generated as a function of the occurrence of both of the following conditions, combined: —the first signal exceeds the first reference value of the first comparator13, —the second signal exceeds the second reference value of the second comparator20. D2. The method according to paragraph D or paragraph D1, comprising a step of setting one bandpass filter of two or more bandpass filters of the conditioning stage12, operatively connected in parallel and defining bands which occupy different, consecutive portions of a predetermined frequency interval, the setting being performed by means of a selector. D2.1. The method according to paragraph D2, comprising a step of saving in a database, for the fault signal generated by the processor, a record including the voltage value of the output signal from the conditioning stage upon occurrence of the fault signal and/or a piece of information relative to the bandpass filter active when the fault signal occurred. D2.1.1. The method according to paragraph D2.1, comprising a step of receiving, upon occurrence of the fault signal generated by the processor, a false positive indication (or command), wherein the record further includes the false positive indication. D2.1.2. The method according to paragraph D2.1 or paragraph D2.1.1, wherein the record also includes a time indication relative to the moment in which the fault signal occurred. D2.1.3. The method according to any one of paragraphs D2.1 to D2.1.2, wherein the record also includes a radiation to earth value at the moment in which the fault signal occurred. D2.1.4. The method according to any one of paragraphs D2.1 to D2.1.3, wherein the record also includes a value of power supplied by the electrical system1at the moment in which the fault signal occurred. D3. The method according to any one of paragraphs D to D2.1.4, comprising a step of displaying in real time on a screen the voltage value of the first signal conditioned by the conditioning stage12. D4. The method according to any one of paragraphs D to D3, comprising a step of displaying in real time on a screen the voltage of the first signal generated by the first sensor10, upstream of the conditioning stage12, in a spectrum of frequencies of the first signal. D4.1. The method according to paragraph D4 comprising a step of displaying in real time on a screen a direct current component of the current flowing through the cable, wherein the screen is also configured to display in real time the voltage value of the second signal generated by the second sensor19. E. A database comprising a plurality of records, each record being associated with a fault signal generated by a device for protecting a direct current electrical system1from electric arcs, comprising a (first) sensor10provided with a (first) ring of ferromagnetic material configured to generate a (first) signal, representing a current flowing through a cable inserted into the ring; a conditioning stage, having a bandpass filter, for conditioning the (first) signal generated by the (first) sensor; a (first) threshold comparator, having a preset, adjustable (first) voltage reference value, the (first) comparator being configured to receive as input the (first) signal conditioned by the conditioning stage; a processor programmed to generate a fault signal in response to the (first) signal exceeding the (first) reference value of the (first) comparator13, wherein each record includes one or more of the following data:the voltage value of the output signal from the conditioning stage upon occurrence of the fault signal and a piece of information relative to the bandpass filter for which the fault signal occurred;a piece of information relative to the bandpass filter active in the conditioning stage when the fault signal occurred;a false positive indication (or command);a time indication relative to the moment in which the fault signal occurred;a radiation to earth value at the moment in which the fault signal occurred;a value of power supplied by the electrical system1at the moment in which the fault signal occurred;a temperature of the modules at the moment in which the fault signal occurred;a piece of information relative to the time elapsed since installation and/or last maintenance. F. A method for calibrating a device9for protecting a direct current electrical system1having one or more modules2and an inverter from electric arcs, the method comprising the following steps:with the inverter switched on, analysis of a spectrum of frequencies of a noise generated by the inverter, by means of a spectrum analyser comprising an oscilloscope, to detect a signal representing the inverter noise in its spectrum of frequencies;setting, as a function of the analysis of the spectrum of frequencies of the noise, a bandpass filter of a conditioning stage of the device, of two or more bandpass filters operatively connected in parallel and defining bands which occupy different, consecutive portions of a predetermined frequency interval, wherein the bandpass filter selected defines, between the two or more bandpass filters, the frequency band in which the noise generated by the inverter is lowest;setting a voltage reference value in a threshold comparator of the device, in which the voltage reference value is higher than the voltage of the signal representing the inverter noise in the selected frequency band. F1. The method according to claim F, wherein the analysis of the spectrum of frequencies is also performed during a switch off and new switch on of the inverter. | 33,232 |
11942897 | DETAILED DESCRIPTION Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics. Referring toFIGS.1to3, an embodiment of a crystal oscillator200according to the present disclosure includes an oscillating substrate2, a hollow frame3, a first electrode4, and a second electrode5. The oscillating substrate2includes a first surface21, a second surface22opposite to the first surface21, a side surface25interconnecting the first surface21and the second surface22, and an oscillating portion23. The oscillating portion23has a main oscillating region231having a first thickness (T1), and a thinned region232having a second thickness (T2). The second thickness (T2) of the thinned region232is smaller than the first thickness (T1) of the main oscillating region231. In this embodiment, the first thickness (T1) of the main oscillating region231is not greater than 50 μm, and the second thickness (T2) of the thinned region232is not greater than 10 μm. The oscillating substrate2is made of a piezoelectric material having a characteristic resonant frequency, such as quartz crystal. In certain embodiments, the thinned region232has a through hole2321that penetrates through the oscillating portion23(seeFIG.2) to thereby decrease the total weight of the crystal oscillator200. In certain embodiments, the second thickness (T2) of the thinned region232is zero, in other words, the thinned region232is formed as the through hole2321. The hollow frame3is disposed on the second surface22of the oscillating substrate2, and surrounds the oscillating portion23. The hollow frame3is used to increase a thickness of the crystal oscillator200and provides a pick-up position, which facilitates disposing the crystal oscillator200in an electronic component. The hollow frame3may be made of an insulating material or a photoresist material. There are no particular limitations on the width, shape, and disposition of the hollow frame3. The first electrode4includes a first electrode portion41formed on the first surface21of the oscillating substrate2, and a first extending electrode portion42extending from the first electrode portion41on the first surface21along the side surface25to the second surface22. In this embodiment, the first electrode portion41is formed within a projection of the oscillating portion23on the first surface21, and the first extending electrode portion42is located on the side surface25and the second surface22outside the hollow frame3. The second electrode5is disposed on the second surface22of the oscillating substrate2, and includes a second electrode portion51and a second extending electrode portion52extending from the second electrode portion51toward the first extending electrode portion42on the second surface22. A projection of the second electrode portion51on the second surface22of the oscillating substrate2partially overlaps a projection of the first electrode portion41on the second surface22of the oscillating substrate2. The second electrode portion51is located on the oscillating portion23. The second electrode portion51has at least one opening511in positional correspondence with the thinned region232. The position and number of the opening511may vary depending on needs. The second electrode portion51may have a single opening511. Each of the first electrode4and the second electrode5may be made of a conductive material, such as gold, silver, or aluminum. The first electrode4and the second electrode5may be made of the same or different materials. In this embodiment, the second surface22of the oscillating substrate2includes two spaced-apart peripheral areas24that are located at a same side of the second surface22, and that are located outside the oscillating portion23and exposed from the hollow frame3. The first extending electrode portion42extends onto one of the peripheral areas24, and the second extending electrode portion52extends from the second electrode portion51onto the other one of the peripheral areas24. In addition, the two spaced-apart peripheral areas24are located on a peripheral region of the oscillating substrate2that is located outside the main oscillating region231and that has a thickness that is the same as that of the main oscillating region231, so that the first extending electrode portion42and the second extending electrode portion52are located at the same level and at the same side of the second surface22, which is conducive for externally connecting to other electronic components. By the formation of the thinned region232which may have a reduced second thickness (T2) or be in the form of the through hole2321, the total weight of the crystal oscillator200can be further decreased. Referring toFIGS.4to6, this disclosure also provides a method for making the embodiment of the crystal oscillator200, which includes the following steps S81to S88. In step S81, the first electrode portion41is formed on a surface of a piezoelectric substrate60, so as to obtain a first semi-finished product300. In this step, the piezoelectric substrate60is made of quartz crystal, and the first electrode portion41is formed by depositing or printing a conductive material on the surface of the piezoelectric substrate60. In step S82, the first semi-finished product300is attached to a temporary substrate7with the first electrode portion41facing the temporary substrate7, to thereby support the piezoelectric substrate60and prevent the piezoelectric substrate60from breaking during subsequent processes. In step S83, the piezoelectric substrate60of the first semi-finished product300is thinned, so as to obtain the thinned piezoelectric substrate6having the first thickness (T1) that is smaller than the thickness of the piezoelectric substrate60. In this step, the piezoelectric substrate60of the first semi-finished product300is thinned by a polishing process or a chemical etching process, so as to obtain the thinned piezoelectric substrate6having the first surface21on which the first electrode portion41is formed. In step S84, the second electrode5is formed on the second surface22of the thinned piezoelectric substrate6opposite to the temporary substrate7. The second electrode5includes the second electrode portion51having at least one opening511, and the second extending electrode portion52. The detailed structure of the second electrode5may be referred back toFIGS.1and3and the relevant description thereof. The second surface22of the thinned piezoelectric substrate6is exposed from the at least one opening511. In this step, the second electrode5is formed by depositing or printing a conductive material on the second surface22of the thinned piezoelectric substrate6. In step S85, the first extending electrode portion42that extends from the first electrode portion41is formed on the side surface25of the thinned piezoelectric substrate6and the second surface22of the thinned piezoelectric substrate6. In this step, the first extending electrode portion42is formed by depositing or printing a conductive material on the side surface25and the second surface22of the thinned piezoelectric substrate6. In certain embodiments, according to processing requirements, step S85may be conducted after step S83and before step S84. In certain embodiments, step S84may be conducted by forming a portion of the first extending electrode portion42and the second extending electrode portion52on the second surface22of the thinned piezoelectric substrate6, simultaneously. Afterwards, a silver paste is formed on the side surface25of the thinned piezoelectric substrate6to interconnect the first electrode portion41on the first surface21and the portion of the first extending electrode portion42on the second surface22, so as to obtain the first electrode4. In this embodiment, the silver paste and the portion of the first extending electrode portion42constitute the first extending electrode portion42. As shown inFIG.6, in step S86, a hollow frame3is formed on the second surface22of the thinned piezoelectric substrate6. The hollow frame3surrounds the second electrode portion51, and is disposed on the second extending electrode portion52. It is noted that, according to the material of the hollow frame3, step S86may be implemented in a different manner. For example, the hollow frame3can be formed by applying a photoresist material on the second surface22of the thinned piezoelectric substrate6, and subjecting the photoresist material to photolithography. For another example, the hollow frame3can be formed using an insulating material in advance, followed by attaching the hollow frame to the second surface22of the thinned piezoelectric substrate6. In step S87, a portion of the thinned piezoelectric substrate6in positional correspondence with the at least one opening511of the second electrode portion51is etched using the second electrode5as a mask, so as to obtain a second semi-finished product400. The etched portion of the thinned piezoelectric substrate6is defined as the thinned region232. An unetched portion of the thinned piezoelectric substrate6in positional correspondence with the second electrode portion51is defined as the main oscillating region231. The thinned piezoelectric substrate6having the main oscillating region231and the thinned region232constitutes the aforesaid oscillating substrate2(seeFIG.6). The second thickness (T2) of the thinned region232is smaller than the first thickness (T1) of the main oscillating region231. In certain embodiments, the second electrode portion51is formed with a plurality of openings511, and, in step S87, the portion of the thinned piezoelectric substrate6in positional correspondence with some of the openings511of the second electrode portion51may be etched to form the through holes2321in the thinned piezoelectric substrate6. In certain embodiments, the portion of the thinned piezoelectric substrate6in positional correspondence with all of the openings511may be etched all the way through. In such cases, the thinned region232is composed of the through holes2321, and the second thickness (T2) of the thinned region232is zero. It is noted that, the thinned region232may be composed of a through hole2321. In step S88, the temporary substrate7is removed from the first electrode portion41on the first surface21of the thinned piezoelectric substrate6. Procedure for implementing step S88may be chosen according to the procedure for attaching the temporary substrate7on the first electrode portion41in step S82. For example, when step S82is conducted using a photosensitive adhesive or a thermo-sensitive adhesive, step S88may be conducted using light radiation or heat application so as to decompose the photosensitive adhesive or the thermo-sensitive adhesive, thereby removing the temporary substrate7from the first electrode portion41. The crystal oscillator200of this invention has the following advantages. Firstly, because the first and second surfaces21,22of the piezoelectric substrate60(i.e., the thinned piezoelectric substrate6) are flat, formation of the first electrode portion41and the second electrode5would not be adversely affected by the surface morphology of the piezoelectric substrate60(i.e., the thinned piezoelectric substrate6). Secondly, compared with the conventional crystal oscillator, the thickness of the thinned piezoelectric substrate6(i.e., the first thickness (T1)) is reduced, the length of the first extending electrode portion42that extends to the second surface22of the thinned piezoelectric substrate6can be reduced, so as to simplify the process for making the first electrode4and the second electrode5. Thirdly, the total thickness of the oscillating substrate2of the crystal oscillator200can be adjusted by thinning the piezoelectric substrate60to obtain the thinned piezoelectric substrate6, followed by etching the portion of the thinned piezoelectric substrate6. In addition, the crystal oscillator200can attain the expected oscillation frequency because the first thickness (T1) of the main oscillating region231disposed between the first electrode portion41and the second electrode portion51remains the same. In sum, by etching the portion of the thinned piezoelectric substrate6in positional correspondence with the at least one opening511using the second electrode5as a mask, the weight of the oscillating substrate2can be decreased, thereby further decreasing the weight of the crystal oscillator200and ensuring that the crystal oscillator200can attain the expected oscillation frequency. In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment. It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure. While the disclosure has been described in connection with what are considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements. | 14,220 |
11942898 | DETAILED DESCRIPTION Table 1 summarizes a list of acronyms employed throughout this specification as an aid to understanding the described embodiments: TABLE 1CMOSComplementary Metal-CRCognitive RadioOxide SemiconductorFETField Effect TransistorHEMTHigh-Electron-MobilityTransistorICIntegrated CircuitLUTLook Up TableMEMSMicro-ElectroMechanicalPAPower AmplifierSystemsPSIMPhase-Switched ImpedancePS-TMNPhase-Switched TunableModulationimpedance MatchingNetworkRFRadio FrequencySDRSoftware Defined RadioTMNTunable impedanceWPTWireless PowerMatching NetworkTransferZCSZero Current SwitchingZVSZero Voltage Switching Described embodiments are directed toward phase-switched, tunable matching networks (PS-TMNs) and phase-switched, impedance modulation amplifiers (PSIMs). Both the phase-switched, tunable matching networks and the phase-switched, impedance modulation amplifiers include phase-switched variable network reactance elements. When configured in the context of PS-TMNs and phase-switched, impedance modulation amplifiers, such phase-switched variable network reactance elements provide rapid, high bandwidth, continuous impedance matching over a wide impedance range, while operating efficiently at high power levels without requiring high bias voltages or currents. PS-TMNs might be employed alone, or might also be employed in combination with other matching techniques such as discrete switched reactance banks. PS-TMNs might be employed in a variety of reconfigurable and adaptive RF systems, for example, RF front ends for software-defined radio (SDR) and cognitive radio (CR) applications that operate over a wide range of frequency bands, at different bandwidths, and in accordance with a variety of communication standards. PS-TMNs might also be employed in other RF applications, such as drivers for RF plasma loads to compensate for rapid load variations, or in wireless power transfer (WPT) systems to compensate for impedance mismatches between the transmitter and receiver to maximize transferred power and/or efficiency. The PSIMs may be operable as zero voltage switching (ZVS) radio frequency (RF) amplifiers. Such PSIM amplifiers might employ a PS-TMN to operate over a large frequency range by efficiently modulating output power over a wide frequency range and/or matching into highly variable loads (e.g., loads that are variable over a wide impedance range). Referring toFIG.1, a radio frequency (RF) system100includes a phase-switched tunable impedance matching network (PS-TMN)112coupled between a source102, having an impedance ZS, and a load114, having an impedance ZL. In some applications, source102, control circuit106and PS-TMN112(and other elements of RF system100) are coupled to a power supply voltage (e.g., VDC) and ground. Control circuit106is coupled to PS-TMN112and provides control signals to PS-TMN112so as to control operation of PS-TMN112. In response to such control signals, PS-TMN112provides a desired impedance transformation characteristic. It should be appreciated that control circuit106might be an internal component to PS-TMN112, or might be an external component coupled to PS-TMN112or some portions of control circuit106(or functions provided by control circuit106may be internal to PS-TMN112while other portions of control circuit106may be external to PS-TMN112) In some embodiments, control circuit106controls operation of PS-TMN112based, at least partially, upon information received from an optional feedforward circuit104coupled to source102and/or an optional feedback circuit110coupled to load114. In some embodiments, optional feedforward circuit104includes adaptive predistortion circuit107and control circuit106includes look up table (LUT)108. For example, as will be described in greater detail below, some embodiments might employ one or more non-linear control techniques (e.g., by control circuit106) to determine appropriate control signals for PS-TMN112, such as employing fixed or adaptable look-up tables (e.g., LUT108) to store predetermined control signal information, feedback (e.g., by feedback circuit110) and/or feedforward compensation (e.g., by feedforward circuit104) to adaptively adjust control signal information, or performing digital predistortion of the control signals (e.g., by predistortion circuit107), or other similar techniques. PS-TMN112includes one or more phase-switched reactance elements116(1)-116(N). As will be described in greater detail below, phase-switched reactance elements116(1)-116(N) might be implemented using one or more capacitive elements (e.g., capacitors), one or more inductive elements (e.g., inductors), or a combination of both. Phase-switched reactance elements116(1)-116(N) can be controlled to adjust the effective impedance (ZS,INand ZL,IN) presented to the terminals of PS-TMN112at a desired frequency. The phase-switched reactance elements116(1)-116(N) are switched, for example by either a shunt or a series switch, and the effective impedance of the phase-switched reactance elements is controlled by adjusting the phase and/or duty-cycle of the shunt or series switch. In some embodiments, the desired frequency might be the RF frequency of operation of RF source102(e.g., the frequency of the signal provided from RF source102to PS-TMN112). By modulating the effective impedance at a desired frequency of operation of RF system100(e.g., by adjusting the impedance of phase-switched reactive elements116(1)-116(N)), it is possible to adjust, tune, change or otherwise manipulate the impedance presented by PS-TMN112to source102and/or load114. For example, phase-switched reactance elements116(1)-116(N) allow PS-TMN112to present a desired impedance (ZS,IN) to PS-TMN112from source102and a desired impedance (ZL,IN) into PS-TMN112from load114. The control signals provided to PS-TMN112operate to control the timing of turning on and/or off the switches of phase-switched reactance elements116(1)-116(N) with respect to the RF signal provided from source102. The switching provides the effective reactance values of phase-switched reactance elements116(1)-116(N) that effect the desired impedance transformation of PS-TMN112. Feedforward information might include information about the effective input impedance of PS-TMN112, the timing of RF waveforms, specified signal levels and/or impedance levels, etc. Feedback information might include measured information about the effective load impedance and/or power reflected from the load, the timing of RF waveforms, etc. Thus, in some embodiments, PS-TMN112might be employed to provide a desired impedance transformation between source102and load114. For example, PS-TMN112might provide an impedance match between source102and load114. Alternatively, the impedance of PS-TMN112might be adjusted to compensate for variations in the impedance (ZL) of load114such that source102is coupled to a more stable impedance (e.g., ZS,IN) provided by PS-TMN112. Referring toFIG.2, sinusoidal current source202, having a current I, drives an illustrative phase-switched variable reactance200. The phase-switched variable reactance is here shown as including a parallel combination of a capacitor204and switch206to provide the phase-switched variable reactance as phase-switched variable capacitance200. Capacitor204has a physical capacitance C0, and a voltage VC. The state of switch206is controlled by a characteristic of signal Q. For example, switch206provides a low impedance signal path between its terminals (e.g., switch206is “on” or “closed”) when signal Q has a logic high value, and switch206provides a high impedance signal path between its terminals (e.g., switch206is “off” or “open”) when signal Q has a logic low value. Thus, switch206could be considered to switch capacitor204into the circuit when the switch is open (current I flows into capacitor204), and out of the circuit when the switch is closed (current I flows through the closed switch and bypasses capacitor204). If switch206is always off (open), then the effective capacitance, CEFF, of phase-switched variable capacitance200presented to source202is equivalent to the physical capacitance, C0, of capacitor204. Alternatively, if switch206is always on (closed), then the low impedance path between the terminals of switch206effectively “shorts” capacitor204, and phase-switched variable capacitance200behaves as an infinite capacitor in the sense that the voltage across capacitor204remains zero irrelevant of current I. The effective capacitance, CEFF, of capacitor204can theoretically be controlled between C0and infinity by controlling the conduction angle of switch206over an AC cycle of sinusoidal current source202from 0 to 2π. As used herein, a conduction angle is the angle of the sinusoidal signal at which switch206is turned on. The conduction angle with which the switch is turned on may be entirely determined by a switching signal Q (e.g., the switching angle) or partly determined by switching signal Q and partly by circuit waveforms such as voltage VCand current I. Referring toFIG.3, illustrative waveforms of the current I and capacitor voltage VC(e.g., the voltage of capacitor204) are shown with respect to the switch control signal, Q, as a function of a cycle angle θ. In particular, curve302shows I(θ), curve306shows VC(θ) and curve304shows Q(θ) for a half-wave switched capacitor. As shown inFIG.3, every cycle of I(θ), switch206is turned off (opened) a radians after I(θ) transitions from negative to positive (e.g., switch206is on/closed until a radians into the positive half-cycle of I(θ)). Switch206remains off (open) until after the capacitor voltage rings down to zero. Biasing the switch into its conductive state (e.g., turning the switch on or closing the switch) after the capacitor voltage rings down to zero ensures zero-voltage-switching (ZVS) turn on of switch206. If the switch includes a diode that naturally prevents the voltage from going negative, the timing of actively turning switch Q on may be relaxed, since it will naturally commutate “ON” when the switch voltage reaches zero and the active turn-on signal can be issued while the diode conducts. The capacitor C0across the switch provides snubbing of the turn off transition, providing zero-voltage-switching (ZVS) turn off of switch206. As shown inFIG.3, when I(θ) is a purely sinusoidal current source, switch206remains off (open) until the conduction angle of the switch is reached (e.g., at 2α). Thus, for a half-wave switched capacitor, switch206is turned on and off once per cycle of the RF signal from source102(e.g., I(θ) as shown by curve302). Adjusting a sets where in the cycle switch206turns on and off (e.g., controls the conduction angle of switch206) and hence controls the voltage at which the capacitor peaks. Thus, there is a relationship between the switching angle (α) and the magnitude of the fundamental component of VC(θ) at the switching frequency. Consequently, the effective capacitance, CEFF, of capacitor204can be represented as a function of α: CEFF=C0·ππ-α+sin(α)·cos(α)(1a) Referring toFIG.4, it is also possible to implement a phase-switched variable reactance as a switched inductor network that allows continuous control of its effective inductance at the switching frequency. Such a switched inductor network is shown inFIG.4as phase-switched variable inductance400and corresponds to the topological dual of the switched capacitor network200shown inFIG.2. As shown inFIG.4, illustrative phase-switched variable inductance400includes a series combination of inductor404and switch406being driven by a sinusoidal voltage source402with a voltage V. Inductor404has a physical inductance L0, and an inductor current IL. The state of switch406is controlled by the signal Q, for example, switch406might be on (e.g., closed) when signal Q has a logic high value, and off (e.g., open) when signal Q has a logic low value. Thus, switch406could be considered to switch inductor404into the circuit when the switch is closed (applying voltage V to inductor404), and out of the circuit when the switch is open (no voltage is applied to inductor404). Similarly to the switched-capacitor implementation of a phase-switched variable reactance described in regard toFIG.2, the effective inductance LEFFof phase-switched variable inductance400at the switching frequency can be modulated from a base value L0to infinity. For example, if switch406is always on (closed), then the effective inductance, LEFF, of phase-switched variable inductance400seen by source402is equivalent to the physical inductance, L0, of inductor404. Alternatively, if switch406is always off (open), then inductor404behaves as an infinite inductor in the sense that the current through inductor404remains zero irrelevant of voltage V. The effective inductance, LEFF, of inductor404can ideally be controlled between Lo and infinity by controlling the conduction angle of switch406over an AC cycle of sinusoidal voltage source402from 0 to 2π. Referring toFIG.5, illustrative waveforms of the current I and voltage VCof capacitor204are shown with respect to the switch control signal, Q, as a function of a cycle angle θ. As a result of the properties of topological duality, the voltage waveform of the switched capacitor network shown inFIG.3is analogous to the current waveform of the switched inductor network shown inFIG.5, and vice versa. In particular, curve502shows IL(θ), curve506shows V(θ) and curve504shows Q(θ) for a half-wave switched inductor. As shown inFIG.5, every cycle of V(θ), switch406is turned on (closed) a radians after V(θ) transitions from negative to positive (e.g., switch406is off/open until a radians into the positive half-cycle of V(θ)). Switch406remains on (closed) until after the inductor current rings down to zero. Since the switch has an inductor in series with it, zero-current-switching (ZCS) turn on of the switch can be achieved. Turning the switch off at the time when the inductor current rings down to zero ensures zero-current-switching (ZCS) turn off of switch406. In duality with the capacitive circuit, utilization of diode(s) as part of switch Q can enable natural commutation (turn off) of the switch and relax detailed active timing of the turn-off moment of the switching control waveform. As shown inFIG.5, when V(θ) is a purely sinusoidal voltage source, switch406remains on (closed) until the conduction angle of the switch is reached (e.g., at 2α). Adjusting a sets where in the cycle switch406turns on and off (e.g., controls the conduction angle of switch406) and hence controls the current at which the inductor peaks. Thus, similarly to the switched-capacitor implementation of a phase-switched variable reactance described in regard toFIG.2, there is a relationship between the switching angle (α) and the magnitude of the fundamental component of IL(θ) at the switching frequency. Consequently, the effective inductance, LEFF, of inductor404can be represented as a function of α: LEFF=L0·ππ-α+sin(α)·cos(α)(1b) As a result of topological duality, expression (1b) for the effective inductance is the same as that of expression (1a) for the effective capacitance. Expression (1a) is consistent with the intuitive expectation for infinite effective capacitance when the switch is always in the on state (α=π) and predicts the equivalence between CEFFand C0when the switch is permanently off (α=0). Expression (1b) is similarly consistent with the intuitive expectation for infinite effective inductance when the switch is always in the off state (α=0) and predicts the equivalence between LEFFand L0when the switch is permanently on (α=π). Thus, in accordance with expressions (1a) and (1b), the effective capacitance CEFFor the effective inductance LEFFat the switching frequency can be modulated by controlling the conduction angle of the switch associated with the capacitor or inductor. Referring toFIG.6, the normalized effective capacitance, CEFF/C0, or the normalized effective inductance LEFF/L0, is shown by curve602at the switching frequency. For the capacitive circuit this is the same thing as the normalized admittance YEFF/Y0while for the inductive circuit this is the same as the normalized reactance, XEFF/X0. As a result of topological duality, the normalized effective admittance YEFF/Y0of the phase-switched capacitor circuit ofFIG.2is the same as the normalized reactance, XEFF/X0of the phased-switched inductor network shown inFIG.4. As shown inFIG.6, the normalized effective capacitance CEFF(or inductance LEFF) increases rapidly with a and approaches infinity as a approaches π (e.g., 180 degrees). Referring toFIG.7, curve702shows the total harmonic distortion of the capacitor voltage (inductor current) versus a for a purely sinusoidal current (voltage) excitation source. The practical range over which CEFFor LEFFcan be modulated depends on the amount of harmonic distortion that can be present in the network. As a increases towards π (e.g., the conduction angle of the switch increases), the ringing of the capacitor voltage VC(e.g., curve306) or of the inductor current IL(e.g., curve502) is limited to a shorter time period. As shown inFIG.7, this results in significant harmonic content of the capacitor voltage for large YEFF/Y0or XEFF/X0(e.g., CEFF/C0or LEFF/L0) ratios (e.g., the total harmonic distortion increases as a increases). The amount of harmonic distortion allowed in a given system depends on specified limits of harmonic content allowed into the source and/or load and the amount of filtering that is necessary or desired. Note thatFIG.7shows the harmonic distortion of the phase-switched variable reactance (e.g., the harmonic distortion of the capacitor voltage of phase-switched variable capacitance200, or the harmonic distortion of the inductor current of phase-switched variable inductance400), and not the harmonic content that is actually injected into the source and/or load of the RF system (e.g., source102and load114). In some embodiments, the phase-switched variable reactance (e.g., phase-switched variable capacitance200or phase-switched variable inductance400) includes additional filtering components (not shown inFIGS.2and4) to reduce harmonic content injected into the source and/or load (e.g., source102and load114). As described in regard toFIGS.3and5, the phase-switched variable reactance (e.g., phase-switched variable capacitance200or phase-switched variable inductance400), are half-wave switched, where the switch is operated so that the capacitor voltage (curve306ofFIG.3) and inductor current (curve502ofFIG.5) are unipolar. However, other switching schemes are also possible. For example,FIGS.8and9show illustrative waveforms of the current I and voltage V with respect to the switch control signal, Q, as a function of a cycle angle θ, for the switched capacitor network shown inFIG.3and the switched inductor network shown inFIG.5, respectively. In particular, as shown inFIG.8, curve802shows I(θ), curve806shows VC(θ) and curve804shows Q(θ) for a full-wave switched capacitor. As shown inFIG.9, curve902shows IL(θ), curve906shows V(θ) and curve904shows Q(θ) for a full-wave switched inductor. When phase-switched variable capacitance200is full-wave switched, the switch (e.g., switch206) is turned off twice every cycle of I(θ) (e.g., Q(θ) is zero), with the off periods being centered around the instants when the current I(θ) is zero. For a purely sinusoidal excitation current I(θ), this results in a bipolar capacitor voltage waveform VC(θ). Capacitor voltage VC(θ) has zero DC average value. Similarly, when phase-switched variable inductance 400 is full-wave switched, the switch (e.g., switch 406) is turned on twice every cycle of V(θ) (e.g., Q(θ) has a logic high value), with the on periods being centered around the instants when the voltage V(θ) is zero. For a purely sinusoidal excitation voltage V(θ), this results in a bipolar inductor current waveform IL(θ), which also has zero DC average value. Thus, for a full-wave switched capacitor (or inductor), switch206is turned on and off twice per cycle of the RF signal from source102(e.g., I(θ) as shown by curve802). As with half-wave switching (e.g., as shown inFIGS.3and5), the effective capacitance CEFFand the effective inductance LEFFat the switching frequency can be modulated by controlling the switching angle, α, of the switch. The effective capacitance, CEFF, of capacitor204can be represented as a function of a for a full-wave switched capacitor: CEFF=C0·π2·[π-α+sin(α)·cos(α)](2a) Similarly, the effective inductance, LEFF, of inductor404can be represented as a function of α: LEFF=L0·π2·[π-α+sin(α)·cos(α)].(2b) Thus, the effective capacitance/inductance that can be achieved for a given switching angle, a, with full-wave switched networks (e.g., relationships (2a) and (2b)) is half the effective capacitance/inductance that can be achieved with half-waved switched networks (e.g., relationships (1a) and (1b)). However, full-wave switched networks inherently result in reduced harmonic content of the capacitor voltage and inductor current compared to half-wave switched networks for the same switching angle, a (i.e. the switching angle which controls the total switch conduction angle). On the other hand, implementing full-wave switching requires the switch has to operate at twice the operating frequency (e.g., to switch twice per cycle). Further, for capacitive modulation, bidirectional blocking switches are required, which can complicate switch implementation with typical semiconductor switches. Relationships (1) and (2) above show that the effective capacitance and inductance for the switched networks shown inFIGS.2and4can be based upon the switching angle, α, for purely sinusoidal excitation signals. For excitation signals that are not purely sinusoidal, the effective reactance can be controlled by appropriately selecting the timing or switching angle, α, at which the switch turns off (or on) although relationships (1) and (2) cannot calculate an exact value of α. Together with the circuit waveforms that determine zero-voltage (or zero current) points (for switch turn on (or off), switching angle a determines the total conduction angle of the switch during the cycle. For excitation signals that are not purely sinusoidal, an adaptable look-up table (e.g., LUT108), feedback circuit110or feedforward circuit104(including optional digital predistortion circuit107) might be employed to determine the required value of a for a given desired effective reactance. Phase-switched variable capacitance200and phase-switched variable inductance400can be employed as building blocks for implementing phase-switched variable reactances and other adjustable circuits such as TMNs. Particularly, some applications could benefit substantially from variable reactances whose value can be controlled over a range spanning both capacitive and inductive reactances, and/or by modulating the effective reactance over a more limited range. Augmenting phase-switched variable capacitance200and/or phase-switched variable inductance400with additional reactive components can provide a wider range of variable reactances. FIGS.10A-10Dshow illustrative embodiments of phase-switched reactance circuits that include both capacitive and inductive elements, thereby expanding a range over which the impedance of the phase-switched reactance circuit can be tuned as compared to the single-element circuits shown inFIGS.2and4. For example,FIG.10Ashows phase-switched reactance circuit1002that includes inductor1012in series with phase-switched capacitor1013. Phase-switched capacitor1013includes switch1016in parallel with capacitor1014, similarly as described in regard toFIG.2.FIG.10Bshows phase-switched reactance circuit1004that includes inductor1024in series with capacitor1022, with the series combination of inductor1024and capacitor1022arranged in parallel with phase-switched capacitor1025. Capacitor1022is not phase-switched and, thus, is shown as CDC. Phase-switched capacitor1025includes switch1028in parallel with capacitor1026, similarly as described in regard toFIG.2.FIG.10Cshows phase-switched reactance circuit1006that includes capacitor1032in parallel with phase-switched inductor1033. Phase-switched inductor1033includes switch1036in series with inductor1034, similarly as described in regard toFIG.4.FIG.10Dshows phase-switched reactance circuit1008that includes inductor1042in parallel with capacitor1044, with the parallel combination of inductor1042and capacitor1044arranged in series with phase-switched capacitor1045. Inductor1042is not phase-switched and, thus, is shown as LDC. Phase-switched inductor1045includes switch1048in series with inductor1046, similarly as described in regard toFIG.4. As would be understood by one of skill in the art, circuit variants other than the ones illustrated inFIGS.10A-10Dare also possible. For example, placing a capacitor in series with a phase-switched capacitor provides a net effective impedance having a maximum capacitance equal to the series combination of the capacitor and the physical capacitance of the phase-switched capacitor, and a minimum capacitance equal to the series combination of the capacitor and the phase-switched capacitance value. As described in regard toFIGS.6and7, a tradeoff exists for phase-switched variable capacitance200and phase-switched variable inductance400between their variable reactance range and the amount of harmonic content injected into the rest of the system. In other words, the range over which the effective reactance can be controlled is limited by the amount of harmonic content that can be tolerated within the system (e.g., by source102and/or load114). Some embodiments might employ additional or external filtering components to reduce harmonic content injected to source102and/or load114. However, in some embodiments, it might not be possible to employ additional filtering components. Referring toFIGS.11and12, in cases where additional filtering components are not employed, the harmonic content can be reduced by combining phase-switched variable capacitance200and phase-switched variable inductance400with one or more digitally controlled capacitor or inductor matrices that are not phase-switched. Such hybrid switched networks include an RF switch operated at the RF frequency of operation and with controlled phase and duty cycles with respect to the RF waveform. The hybrid switched network also includes digital switches associated with one or more capacitors or inductors in the switched matrix. The digital switches are typically operated at a much lower frequency than the RF frequency, but could be operated up to the RF frequency (e.g., on a cycle-by-cycle basis) determined by the control bandwidth of the effective reactance CEFFor LEFF. Referring toFIG.11, hybrid switched network1100includes a phase-switched reactance (e.g., capacitor C01116and parallel switch1118) and digitally controlled capacitor network1102. Although shown as a phase-switched variable capacitance (e.g., capacitor C01116and parallel switch1118) coupled in parallel with digitally controlled capacitor network1102and load114, in other embodiments, the phase-switched reactance might be implemented as a phase-switched variable inductance (e.g., such as shown inFIG.4) coupled in series with digitally controlled capacitor network1102and load114, or as one of the phase-switched reactance circuits shown inFIGS.10A-D, or other equivalent circuits. Digitally controlled capacitor network1102includes a plurality of capacitors and associated switches, shown as capacitors1104,1108, and1112, and switches1106,1110, and1114. In some embodiments, each of capacitors1104,1108, and1112have a unique capacitance value, allowing the capacitance value of digitally controlled capacitor network1102to be varied across a large capacitance range. For example, as shown inFIG.11, capacitors1104,1108, and1112might increase from the phase-switched capacitor base value (e.g., C0) in increments of C0until reaching a maximum capacitance value (e.g.,(2·2N−1)·C0), where N is the number of capacitors in digitally controlled capacitor network1102). Switches1106,1110, and1114are coupled in series with corresponding ones of capacitors1104,1108, and1112and are operable to adjust the capacitance of digitally controlled capacitor network1102by connecting (or disconnecting) the respective capacitors. Switches1106,1110, and1114might operate based upon one or more control signals from control circuit106. As described, switches1106,1110, and1114generally operate at a frequency less than the RF frequency to adjust the capacitance value of digitally controlled capacitor network1102. Referring toFIG.12, hybrid switched network1200includes a phase-switched reactance (e.g., inductor L01216and series switch1218) and digitally controlled inductor network1202. Although shown as a phase-switched variable inductance (e.g., inductor L01216and series switch1218) coupled in series with digitally controlled inductor network1202and in parallel with load114, in other embodiments, the phase-switched reactance might be implemented as a phase-switched variable capacitance (e.g., such as shown inFIG.2), or as one of the phase-switched reactance circuits shown inFIGS.10A-D, or other equivalent circuits. Digitally controlled inductor network1202includes a plurality of inductors and associated switches, shown as inductors1206,1210, and1214, and switches1204,1208, and1212. In some embodiments, each of inductors1206,1210, and1214have a unique inductance value, allowing the inductance value of digitally controlled inductor network1202to be varied across a large inductance range. For example, as shown inFIG.12, inductors1206,1210, and1214and1218might increase from the phase-switched inductor base value (e.g., L0) by increments of Lo until reaching a maximum inductance value. Switches1204,1208, and1212are coupled in parallel with corresponding ones of inductors1206,1210, and1214and are operable to adjust the inductance of digitally controlled inductor network1202by connecting (or shorting, e.g., providing a low-impedance path to bypass the inductor) the respective inductors. Switches1204,1208, and1212might operate based upon one or more control signals from control circuit106. As described, switches1204,1208, and1212generally operate at a frequency less than the RF frequency to adjust the capacitance value of digitally controlled inductor network1202. Digitally controlled capacitor network1102and digitally controlled inductor network1202expand the range over which the reactance of the phase-switched reactance (e.g., capacitor C01116and parallel switch1118, or inductor L01216and series switch1218) can be continuously varied without introducing excessive harmonic content to source102and/or load114. For example, the embodiments shown inFIGS.11and12employ digitally controlled capacitor network1102(or digitally controlled inductor network1202) to control the base value C0(or L0) of the switched networks1100(or1200). The switch of the phase-switched reactance (e.g., switch1118or switch1218) can be operated to step-up the base capacitance C0(or inductance L0) by a factor determined by relationships (1) and (2) described above. For example, the effective capacitance CEFFat the switching frequency of hybrid switched capacitor network1100can be controlled between a lower capacitance value C0and an upper capacitance value by half-wave switching the RF switch with the switching angle, α, varying from 0 to approximately π/2 as shown inFIG.3. As shown inFIG.7, RF switch operation with a switching angle, α, less than π/2 (90 degrees) corresponds to a peak harmonic distortion of less than approximately 35%. Thus, the hybrid switched networks (e.g.,1100and1200) allow continuous control of the effective reactance at the switching frequency over a wide capacitive (or inductive) range with minimum harmonic distortion and without the need for adjustable bias voltages or currents. In various embodiments, the RF switch of TMN112(e.g., switch206or switch406) can be implemented as one of or a combination of various types of switching elements, for example based upon the RF frequency or other operating parameters of RF system100. For example, lateral or vertical FETs, HEMTs, thyristors, diodes, or other similar circuit elements might be employed. Phase-switched variable capacitance200and phase-switched variable inductance400can be employed as circuit elements within more complex phase-switched tunable matching networks (PS-TMNs), for example a Pi-network topology PS-TMN (Pi-TMN), although other network topologies are possible, such as L-networks, T-networks, or other similar networks.FIG.13shows a schematic of illustrative RF system1300including an RF source1301coupled to Pi-TMN1302, which is coupled to an RF load1303. Pi-TMN1302includes two variable shunt capacitive susceptances B11310and B21314. In illustrative embodiments, RF source1301is commonly a power amplifier or the output of another RF system. As shown inFIG.13, RF source1301can be represented by its Norton equivalent circuit as including current source1304in parallel with source resistance RS1306and source susceptance BS1308. Similarly, RF load1303can be represented as including load resistance RL1318in parallel with load susceptance BL1316. The source and load impedances, ZSand ZL, respectively, can be expressed as: ZS=(RS−1+jBS)−1(3) ZL=(RL−1+jBL)−1(4). Thus, it can be shown that the susceptances B1and B2required to match the load impedance ZLto the source impedance ZSare given by: B1=RS±RLRS-X2X-BS(5)B2=RSRL(RS±RLRS-X2X)-BL.(6) Thus, Pi-TMN1302can be employed to match load impedance ZLto source impedance ZSby adjusting the values of variable shunt capacitive susceptances B11310and B21314. As shown inFIG.13, embodiments of Pi-TMN1302include two variable shunt capacitive susceptances B11310and B21314, and a fixed inductive reactance X1312, although numerous other implementations of a Pi-TMN are possible, such as employing variable shunt inductive susceptances and a fixed capacitive reactance, implementing all three reactive branches as variable components, etc. It should, of course, be appreciated that it is also possible to realize an L-section TMN having one variable shunt-path element and one variable series-path element. Other types of networks, might also be employed. As described in greater detail below, ground-referenced variable capacitors are highly suitable for realization with phase-switched variable reactance networks at RF frequencies. Referring toFIG.14, an illustrative range of load impedances that can be matched by Pi-TMN1302is shown as shaded region1402in Smith chart plot1400(normalized to RS). For example, the impedance values represented by shaded region1402might be achieved by an illustrative Pi-TMN having X=RSand susceptance B1variable over a range of 1/RSto 4/RS, and susceptance B2variable over a range of 1/RSto 2/RS. As shown inFIG.14, Pi-TMN1302is able to match the impedance of RF source1301to a load impedance that varies over approximately a 10:1 resistance range and a 5:1 reactance range (both capacitively and inductively). To do so, Pi-TMN1302modulates B1over a 1:4 range and B2over a 1:2 range, which can be achieved employing a phase-switched variable reactance network such as shown inFIGS.2and4. FIG.15shows an illustrative embodiment of phase-switched Pi-TMN circuit1502to achieve the matching range shown inFIG.14for a source impedance (e.g., RS1506) of 50Ω. The inductive reactance X is chosen to be equivalent in value to the Norton-equivalent source resistance RS(e.g., 50Ω). As shown inFIG.15, the variable capacitive susceptances B1and B2are implemented as half-wave phase-switched capacitors (e.g., phase-switched capacitor200ofFIG.2). Variable capacitive susceptance B1includes phase-switched capacitor CP21514and FET switch1512, which is controlled by switching control signal q2, which has a switching angle, α2. Variable capacitive susceptance B2includes phase-switched capacitor CP11520and FET switch1522, which is controlled by switching control signal q1, which has a switching angle, α1. In an illustrative embodiment, phase-switched Pi-TMN circuit1502operates at 27.12 MHz and is capable of matching a 50Ω source impedance to a load impedance that varies over approximately a 10:1 resistance range and a 5:1 reactance range (both capacitively and inductively), by properly adjusting the switching angles (α1and α2) of the switches and the phase shift between them (e.g., by adjusting switching control signals q1and q2). Implementing variable capacitive susceptances B1and B2as half-wave FET-switched capacitor networks provides zero-voltage-switched (ZVS) operation of the switches, and allows each variable reactance to be implemented with a single, ground-referenced switch (e.g., FET1512for variable capacitive susceptance B1and FET1522for variable capacitive susceptance B2). ZVS operation is desired in switched systems as it reduces switching power loss and improves the overall system efficiency. Furthermore, the output (drain-to-source) capacitance of FETs1512and1522are in parallel with phase-switched capacitors CP1and CP2and, thus can be added to the shunt capacitances and utilized as part of the TMN. In illustrative Pi-TMN circuit1502, inductive reactance X1312shown inFIG.13is implemented as a series-resonant circuit including inductor LS21516and capacitor CS21518disposed in series between variable susceptances B1and B2, which are disposed as shunt elements (e.g., coupled to ground). Inductor LS21516and capacitor CS21518are selected to have an inductive impedance approximately equal to the source impedance (e.g., 50Ω) at the desired frequency. In the embodiment shown inFIG.15, two additional series-resonant circuits are included, one as an input filter and one as an output filter of Pi-TMN circuit1502to limit the amount of harmonic content injected into the source and the load as a result of the switching. For example, capacitor CS11508and inductor LS11510act as a series-resonant input filter between source1504and Pi-TMN circuit1502. Similarly, inductor LS31524and capacitor CS31526act as a series-resonant output filter between load1528and Pi-TMN circuit1502. The quality factor, Q, of the series-resonant circuit of LS21516and CS21518controls the interaction between phase-switched capacitor CP11520and phase-switched capacitor CP21514. For example, increasing the quality factor Q (e.g., by increasing the values of LS21516and CS21518) reduces the interaction between phase-switched capacitor CP11520and phase-switched capacitor CP21514, although increasing the quality factor Q also reduces the effective bandwidth of the network. For example, for phase-switched Pi-TMN circuit1502to achieve the matching range shown inFIG.14for a source impedance (e.g., RS1506) of 50Ω at an illustrative desired frequency in the range of about 27 MHz, phase-switched capacitor CP11520might have a physical value, C0, of 130 pF, and phase-switched capacitor CP21514might have a physical value, C0, of 100 pF. To achieve the desired quality factor Q by the series-resonant circuit between phase-switched capacitor CP11520and phase-switched capacitor CP21514, capacitor CS21518might have a value of 0.01 μF, and inductor LS21516might have a value of 297 nH. To achieve the desired input and output filtering by the series-resonant circuits, capacitors CS11508and CS31526might have a value of 23.4 pF, and inductors LS11510and LS31524might have a value of 1.47 μH. Further, FETs1512and1522might have an on-state resistance of 10 mΩ, and the body diode of each FET might have a forward voltage of 0.4 V and an on-state resistance of 10 mΩ. Switching of FETs1512and1522is synchronized to their drain current based upon the switching angle α, which is based upon the desired effective capacitance of capacitors CP1and CP2. As described above for half-wave phase-switched capacitors, FETs1512and1522are turned off after their drain current crosses from negative to positive, and then turned on again once their respective drain voltages ring down to zero. The appropriate value of a for each of FETs1512and1522can be calculated by determining the required B1and B2susceptances for a desired load impedance ZLas given by relationships (5) and (6). Once each capacitive susceptance B1and B2is known, that value can be plugged in as CEFF(C0is a known value as the physical capacitance of the capacitor) in relationship (1a) (for a half-wave phase-switched capacitor) or relationship (2a) (for a full-wave phase-switched capacitor) to determine values of a that correspond to the desired susceptance values. As described, for phase-switched networks having non-purely sinusoidal current excitation, relationships (1) and (2) might not result in an exact value of a to achieve the desired susceptance. Further, nonlinearity of the drain-to-source switch capacitances and the mutual interaction of the two switched networks (e.g., capacitive susceptances B1and B2) might also result in inaccurate calculation of α. Thus, some embodiments employ non-linear control techniques (e.g., by control circuit106) to determine the appropriate values of α, such as fixed or adaptable look-up tables (e.g., LUT108), feedback (e.g., by feedback circuit110), feedforward compensation (e.g., by feedforward circuit104), digital predistortion of the switching angles (e.g., by predistortion circuit107), or other similar techniques. To set the correct value of switching control parameter a for each of FETs1512and1522for Pi-TMN circuit1502to achieve a given impedance, LUT108might store predetermined switching angles (e.g., α1and α2) corresponding to various load impedances. For example, table 2 shows an illustrative list of possible load impedances that Pi-TMN circuit1502can match to a 50Ω source and the corresponding values of switching angles α1and α2for the switch control signals q1and q2: TABLE 2Load Impedance ZL(Ω)α1(degrees)α2(degrees)48.8 + 10.90j0.00.0103 + 8.12j78.195.7165 − 0.923j87.991.8282 + 3.20j97.685.9524 − 19.30j107.079.11000 + 15.90j117.072.2 Table 2 shows that it is possible for Pi-TMN circuit1502to match a 50Ω source impedance to a load impedance that varies resistively over at least a factor of 10:1. Based upon the switching angles (α1and α2) listed in Table 2 and the plot of effective reactance (e.g., CEFF/C0or LEFF/L0) versus as shown as inFIG.6, it can be shown a 2:1 modulation of the effective capacitances can achieve impedance matching for a load impedance varying resistively over a 10:1 range. Other types of systems can also employ the phase-switched networks described herein. For example, a wide range of systems can benefit from RF power amplifiers (PA) that deliver power at a particular frequency or over a particular band of frequencies. Such PAs might beneficially control output power over a wide range and maintain high efficiency across its operating range. Conventional linear amplifiers (e.g., class A, B, AB, etc.) offer the benefits of wide-range dynamic output power control and high fidelity amplification, but have limited peak efficiency that degrades rapidly with power back-off. On the other hand, switching PAs (e.g., inverters such as class D, E, F, Φ, etc.), offer high peak efficiency, but only generate constant envelope signals (at a constant supply voltage) while remaining in switched mode. One technique for output power control in a switching PA is through load modulation, where the load of the PA is modulated by an external network. In described embodiments, the load of the PA is modulated by a phase-switched tunable matching network (TMN) (e.g., a network including one or more phase-switched variable capacitances200or phase-switched variable inductances400, such as Pi-TMN circuit1502). For example, an impedance transformation of a phase-switched TMN might control the output power of a PA. Referring toFIG.16, such a phase-switched impedance modulation (PSIM) amplifier is shown as PSIM amplifier1600. PSIM amplifier1600includes RF power amplifier (or inverter)1602that generates RF power at a particular frequency, or over a particular range of frequencies. RF PA1602is coupled to a power supply (e.g., voltage VDCand ground) and phase-switched TMN1604. Phase-switched TMN1604is coupled to RF load1606, which has a load impedance ZL. Phase-switched TMN1604is coupled to controller1608, which controls operation of the TMN, for example by providing control signals to switches of the TMN based upon the switching angles (e.g., α) to achieve a desired impedance. Although not shown inFIG.16, in some embodiments, controller1608is coupled to RF PA1602and also controls operation of the PA. Phase-switched TMN1604adaptively controls transforming the load impedance ZLto an impedance presented to PA1602. For example, phase-switched TMN1604may control the output power of PA1602by modulating the load presented to PA1602(e.g., ZTMN) and/or to compensate for frequency and/or load impedance variations to provide high efficiency and desired power to the load. In various embodiments, PA1602is (1) a switching inverter, (2) an amplitude-modulated linear PA, or (3) a combination of these (e.g., depending on desired output). For example,FIG.17shows a block diagram of illustrative PSIM amplifier,1700, that includes switching PA1702(e.g., a class E, F or Φ PA, etc.) that includes a single switch (e.g., FET1706). In other embodiments, other types of PAs might be employed, such as linear PAs (e.g., class A, B, AB or C) or other switching PAs that use more than one switch to convert DC power to RF power (e.g., class D, inverse-D, etc.). As described, modulating the effective loading impedance ZTMNseen by the PA looking into the phase-switched TMN (e.g., TMN1604or1710) controls the output power over the operating power range of the PSIM amplifier (e.g., amplifiers1602and1702). Additionally, the operating power range of the PSIM amplifier can be further extended by also employing amplitude modulation of the PA drive signal for large output power back off. Some embodiments might also employ other power modulation techniques such as discrete or continuous drain modulation of the power amplifier. Drain modulation of the PA modulates (e.g., switches) a bias voltage applied to a bias terminal of the PA. For example, one drain modulation technique might switch the bias voltage among multiple discrete voltage levels or continuously adjusting the bias voltage across a voltage range. In addition to performing impedance modulation and output power control of the RF PA, a phase-switched TMN (e.g., TMN1604or1710) can also compensate for variation in the load impedance ZL. For example, the phase-switched TMN can be continuously tuned to match a variable load impedance to a desired RF inverter loading impedance, ZTMN, for a given output power level, by employing the phase-switched TMN to compensate for variations in the amplifier's loading network impedance as the operating frequency changes and, thus, maintain ZVS operation. Thus, a PSIM amplifier (e.g., PSIM amplifiers1600and1700) dynamically controls the output power it delivers to a widely varying load impedance, such as an RF plasma load, across a large frequency range. Therefore, a PSIM amplifier (e.g., PSIM amplifiers1600and1700) allows (1) efficient dynamic control of output power over a wide power range; (2) the ability to impedance match and deliver power into a wide-ranging load, and (3) fully zero-voltage-switching (ZVS) operation across a frequency range for frequency-agile operation. Although the block diagrams of PSIM amplifiers1600and1700shown inFIGS.16and17show PSIM amplifiers as a cascade combination of an RF PA (e.g., RF PAs1602and1702) with a phase-switched TMN (e.g., phase-switched TMNs1604and1710), other embodiments integrate the PS-TMN into the design of the RF PA. As a result, such integrated PSIM amplifiers can be viewed as an RF amplifier including two or more switches, where a first switch (or group of switches) is principally responsible for generating RF power from DC input power, and a second switch (or group of switches) is principally responsible for modulating the effective impedance presented by a load network to the RF amplifier. In most embodiments, the second switch (or group of switches) will not convert DC power to RF power (e.g., the second switch provides zero power conversion from DC to RF), although in some embodiments, the second switch may convert some power from DC to RF or RF to DC. In most embodiments a PSIM amplifier can be a zero-voltage switching (ZVS) amplifier with the switching transistors operating substantially in switched-mode and turning on and off under zero-voltage switching, enabling high efficiency to be achieved. In other implementations, a PSIM amplifier might provide switched-mode operation (e.g., saturated operation) over some of its operating range (e.g., while delivering high output power) and utilize linear-mode operation over other portions of its range. For example,FIG.18Ashows a schematic of an illustrative topology for PSIM amplifier1800A. As shown, PSIM amplifier1800A is coupled to DC source1802coupled in series with inductor LF, which is in turn coupled to the parallel combination of transistor1804and capacitor CF. Inductor LF, capacitor CF, and FET1804generally operate to generate RF output power to the rest of the network from the DC source. Branch reactance X1is coupled between capacitor CFand node N2, which is coupled to a Pi-TMN including reactance X2coupled between a first phase-switched reactance (e.g., FET1806, branch reactance XS2, and phase-switched variable reactance XP2) and a second phase-switched reactance (e.g., FET1808, branch reactance XS3, and phase-switched variable reactance XP3). Branch reactance X1is coupled between the Pi-TMN at node N1and the load impedance ZL. The branch reactances X1, X2, X3, XS2, XS3,and the phase-switched variable reactances XP2and XP3can be implemented as various different reactive networks depending on the required functionality of the design. FIG.18Bshows an illustrative design1800B of the PSIM amplifier topology shown inFIG.18A. As shown inFIG.18B, the phase-switched variable reactances (comprising FET switches1806and1808and phase-switched capacitors CP2and CP3) are implemented with half-wave phase-switched capacitor network such as described in regard toFIGS.2and3. As shown inFIG.18B, the three switches1814,1816and1818are mutually isolated at DC (e.g., by capacitors CS1, CS2and C3, respectively. FET switch1814is responsible for generating all the RF power, while FET switches1816and1818are responsible for transforming and modulating the impedance presented by load ZLto the DC-to-RF portion of the circuit (e.g., at the output port of switch1814at node N2). FIG.18Cshows an illustrative design1800C of the PSIM amplifier topology shown inFIG.18A. Network1800C is similar to network1800B, although in network1800C, the phase-switched capacitor networks (e.g., FET1826and capacitor CP2and FET1828and capacitor CP3) are connected in series with capacitors CP4and CP5, respectively. This decreases the sensitivity of the PSIM amplifier to variations in the effective reactance of the switched capacitor networks. FIG.18Dshows an illustrative design1800D of the PSIM amplifier topology shown inFIG.18Awhere FET switches1834and1836are DC coupled (e.g., via inductor LS1), and thus, potentially, one or both of FET switches1834and1836can be used to convert DC power into RF power or vice-versa. FET switch1838, on the other hand, is DC-isolated (e.g., by capacitors CS2and CS3) and, thus, is used only for impedance matching to the load impedance ZL. FIG.18Eshows an illustrative design1800E of the PSIM amplifier topology shown inFIG.18Awhere all three FET switches1844,1846and1848are DC coupled (e.g., via inductor LS2), while only the load is DC-isolated (e.g., by capacitor CS3). Thus, in such an embodiment, all three FET switches1844,1846and1848can potentially be used to convert between DC power and RF power and/or be responsible for impedance matching of the network to the load, though it is not necessary that all three provide each function. As shown inFIG.18E, the switched capacitor network of capacitor CF and FET switch1844is in parallel with the phase-switched network of capacitor CP2, inductor L2and FET switch1846. As a result, some embodiments could combine these two networks into a single switched reactive network having an input current that matches the sum of the input currents of the two switched reactive networks associated with FETs1844and1846. Thus, in some embodiments, the three-switch PSIM shown inFIG.18Ecan be implemented as a two-switch PSIM, such as shown inFIGS.19and20. Referring toFIG.19, a schematic of an illustrative topology for two-switch PSIM1900is shown. Two-switch PSIM1900is coupled to RF source1902coupled in series with inductor LF, which is in turn coupled to the parallel combination of FET1904and capacitor CF. Branch reactance X1is coupled between capacitor CFand a phase-switched reactance network including reactance XS2coupled in series with the parallel combination of phase-switched reactance XP2and FET1906. Branch reactance X2is coupled between the phase-switched reactance network and the load impedance ZL. The branch reactances X1, X2and XS2, and the phase-switched variable reactance XP2can be implemented as various different reactive networks depending on the required functionality of the design. Either one of switch FETs1904and1906, or both of switches1904and1906, can be used to convert between DC power and RF power. Referring toFIG.20, an illustrative implementation of two-switch PSIM2000is shown having branch reactance X1implemented as inductor LS1and capacitor CS1. Capacitor CS1provides DC isolation between FET switches2004and2006. Thus, FET switch2004generates RF power and FET switch2006modulates the impedance presented to the source. FIG.21shows an illustrative implementation of a three-switch PSIM amplifier2100. PSIM amplifier2100operates over a 20.86 MHz to 27.12 MHz frequency range (a factor of 1.3 in frequency). Further, PSIM amplifier2100provides the ability for 10: 1 dynamic control of the output power delivered to the load having an impedance, ZL, of 50Ω with a ±10% impedance variation (resistive and reactive). PSIM amplifier2100includes RF PA (inverter)2102, Pi-TMN2104, branch filter2106, and load impedance ZL. RF PA2102includes FET switch2108, inductor LFand an output network formed by capacitors CFand CS1and inductor LS1. In the embodiment shown inFIG.21, RF PA2102is a modified class E inverter with FET switch2108converting between DC power and RF power. Pi-TMN2104includes a first phase-switched capacitor (e.g., CP2and FET2110) and a second phase-switched capacitor (e.g., CP1and FET2112). Branch filter2106includes inductor LS3and capacitor CS3coupled between Pi-TMN2104and load ZL. RF PA2102maintains zero-voltage-switching (ZVS) and high efficiency at different output power levels when Pi-TMN 2104 maintains the inverter load impedance ZTMNas an approximately resistive load at the frequency of operation of RF PA2102. RF PA2102generates peak RF power when ZTMNis 50Ω (e.g., matches load impedance ZL). Dynamic control of power back off of RF PA2102can be achieved by Pi-TMN2104modulating ZTMN. For operation over a 20.86 MHz to 27.12 MHz frequency range, the illustrative embodiment of PSIM amplifier2100shown inFIG.21employs inductor LFhaving a value of 113 nH, capacitor CFhaving a value of 180 pF, capacitor CS1having a value of 15.2 pF, inductor LS1having a value of 3.81 μH, phase-switched capacitor CP2having a physical value, C0, of 152 pF, inductor LS2having a value of 381 nH, capacitor CS2having a value of 0.01 μF, phase-switched capacitor CP1having a physical value, C0, of 152 pF, inductor LS3having a value of 3.81 μH, and capacitor CS3having a value of 15.2 pF. In some embodiments, Pi-TMN2104employs half-wave switched capacitor networks (e.g., capacitor CP2and FET2110and capacitor CP1and FET2112). The series reactive network branch formed by capacitor CS2and inductor LS2has a 50Ω inductive impedance at a frequency of 20.86 MHz and also DC isolates the two switched networks (e.g., capacitor CP2and FET2110and capacitor CP1and FET2112). The impedance of capacitor CS2and inductor LS2sets the resistive range over which ZTMNof Pi-TMN2104can be modulated. The series resonant network formed by capacitor CS3and inductor LS3provides additional filtering of the load current IL and prevents DC currents and high-frequency harmonic content being coupled to the load ZL. Pi-TMN2104can modulate the impedance, ZTMN, presented to RF PA2102by appropriately driving FET switches2110and2112, for example by adjusting the conduction angles of the FETs. By modulating the impedance ZTMNpresented to RF PA2102, Pi-TMN2104can control the output power that is delivered from RF PA2102to load ZL. FIG.22shows an illustrative impedance range (e.g., shaded region2202) over which ZTMNof Pi-TMN2104can be adjusted at 20.86 MHz.FIG.23shows an illustrative impedance range (e.g., shaded region2302) over which ZTMNof Pi-TMN2104can be adjusted at 27.12 MHz. Smith charts2200and2300are normalized to 50Ω. Shaded regions2202and2302illustrate that Pi-TMN2104can match load impedance ZLover a 10:1 range by varying phase-switched capacitor CP1over a 1:6 impedance range (e.g., varying the switching angle, α1, of FET2112over approximately 0 degrees to 125 degrees) and varying phase-switched capacitor CP1over a 1:10 impedance range (e.g., varying the switching angle, α2, of FET2110over approximately 0 degrees to 135 degrees). Furthermore, ZTMNcan be modulated to account for a ±10% variation in the load impedance ZL(both resistive and reactive) at the frequency of operation of RF PA2102. To set the correct value of switching angle, α1, of FET2112and switching angle, α2, of FET2110for Pi-TMN2104to achieve a given impedance, LUT108might store predetermined switching angles (e.g., α1and α2) corresponding to various impedances. For example, table 3 shows an illustrative list of possible impedances ZTMNthat can be matched to a 50Ω load impedance ZLand the corresponding switching angles (e.g., α1and α2). The values of table 3 might be determined based upon simulation of PSIM amplifier2100, where FETs2110and2112are modeled having an on-state resistance of 10 mΩ and a body diode having a 0.4 V forward voltage drop. The output power listed in table 3 includes power delivered at the fundamental and higher frequencies when the PSIM amplifier is supplied with a 48 VDC power supply. TABLE 3SwitchingTMNOutputFrequencyα1α2ImpedancePower(MHz)(degrees)(degrees)ZTMN(Ω)(W)27.1282.148.655.5 + 6.06j19.827.1264.468.3125 − 1.60j12.327.1261.366.450.0 − 1.14j3.520.860.100.1048.9 − 1.20j58.620.8614687.749.8 − 5.90j5.4 As described, PSIM amplifier2100maintains zero-voltage-switching of all FET switches across a wide range of output power, loading impedance, and frequency of operation. For example, for illustrative PSIM amplifier2100to deliver an output power of 58.6 W to 50Ω load ZL at 20.86 MHz with a power supply voltage of 48 VDC, TMN2102is required to provide nearly a 1:1 impedance match (e.g., ZL=ZTMN=50Ω). Under this operating condition, the required effective shunt capacitance at nodes N1and N2is equivalent to the CP1and CP2capacitances, respectively, and hence FET switches2110and2112are off during the entire cycle and the drain voltage waveforms of FET switches2110and2112would be sinusoidal. As another example, for illustrative PSIM amplifier2100to deliver an output power of 3.50 W to 50Ω load ZLat 27.12 MHz with a power supply voltage of 48 VDC, TMN2102is required to provide an impedance ZTMN of approximately 50Ω (as shown in Table 3). Under this operating condition, the required effective shunt capacitance at nodes N1and N2is higher than the CP1and CP2capacitances, respectively, and hence FET switches2110and2112are turned on for a certain portion of the cycle while maintaining ZVS. Despite high frequency harmonic content of the drain voltage waveforms of FET switches2110and2112, the load current ILflowing through load ZLshould remain nearly sinusoidal. Thus, PSIM amplifier2100is capable of providing dynamic output power control while matching into a variable load across a range of switching frequencies. Referring now toFIG.25A, a pulse width modulation (PWM) generator2500includes a phase shifting circuit2504which includes one or more phase-shifting elements2504a-2504N with each phase shifting element having inputs and outputs. PWM shifting circuit2504receives one or more reference signals from reference signal source2502and provides one or more phase shifted signals2510at outputs thereof. PWM generator further includes a PWM waveform combiner2506configured to receive signals provided thereto from phase-shifting circuit2504, combine such signals and provide a PWM signal at an output thereof. Thus, PWM generator2500receives one or more reference signals2508and generates one or more PWM signals2508with the ability to dynamically control pulse width and phase with respect to reference signal2502. In particular, PWM generator2500is configured to generate one or more PWM signals2508having predetermined pulse widths and phase shifts relative to reference signals2502. Reference signal source2502and PWM signal2508are here shown in phantom since they are not properly a part of PWM generator2500. Reference signals provided by2502may be provided as any arbitrary, periodic waveform including, but not limited to, periodic voltage and current waveforms having a variety of waveform shapes including but not limited to, sinusoidal waveforms (e.g. sine waves, cosine waves, or portions there of etc.), rectangular waveform, square waveforms, triangular waveforms, or any combination thereof. Although for purposes of clarity reference is sometimes made hereinbelow to a reference signal being a voltage waveform, those of ordinary skill in the art will appreciate that current waveforms may also be used in accordance with the described concepts. Further, any other signal derived from current and/or voltage signals may also be used as a reference. In embodiments, an input of at least one phase-shifting element in phase shifting circuit2504is configured to receive at least one reference signal2502. In other embodiments, inputs of two or more phase shifting elements2504may be configured to receive at least one reference signal2502. Examples of different phase-shifting circuit architectures will be discussed below with reference toFIGS.26and27. As will become apparent from the description herein below, each phase-shifting element of phase-shifting circuit2504is configured to generate a phase-shifted signal2510relative to received reference signals2502at its respective output based upon a respective phase-shift parameter. Phase shift parameters are provided from a controller2509which is here shown in phantom since it is not properly a part of PWM generator2500. Each phase-shifting element can include analog and/or digital circuitry configured to apply a phase shift to a signal received at its input to generate the phase-shifted signal at its output phase-shifting elements may comprise, for example, any of In-phase/In-quadrature (“IQ”) circuits, phase-locked loop (“PLL”) circuits, or any combination thereof. In embodiments, a phase-shift parameter can include a predetermined phase shift and/or predetermined pulse width used to generate a signal having a particular phase-shift (e.g. used in the generation of a phase-shifted signals2510). According to some embodiments, each phase-shifting element2504is configured to receive a respective predetermined phase-shift parameter from controller2509. Controller2509may be provided, for example, as any type of processing circuitry including, but not limited to, a digital signal processor (“DSP”), a computer, a microprocessor, a microcontroller, or any combination thereof. As will be described in detail below in conjunction with at leastFIG.27, in some embodiments, a first phase-shifting element2504acan be configured to receive at least one reference signal2502at its input while a second phase-shifting element2504bcan be configured to receive at its input a generated phase-shifted signal (e.g. one of signals2510) from another (i.e. a different) phase-shifting element (e.g. the first phase-shifting element2504a). In embodiments, each phase-shifting element2504a-2504N is configured to shift the phase of signals received at its input based upon a respective phase-shift parameter in order to generate a corresponding one of phase-shifted signals2510a-2510N generally denoted2510. In embodiments, some phase-shifting elements may be configured to shift the phase of a received reference2502in order to generate a phase-shifted signal2510while others may be configured to shift the phase of generated phase-shift signals2510received from another phase-shifting element2504. For example, a phase-shifting element2504can receive a phase-shift parameter comprising a phase shift ϕ. This phase-shifting element2504may then generate a phase-shifted signal2510at its output by shifting the phase of a signal received at its input (e.g. a reference signal2502or generated phase-shifted signal) according to the phase shift ϕ. Waveform combiner2506is configured to receive the one or more generated phase-shifted signals2510A-2510N generated by phase-shifting elements2504A-2504N. Waveform combiner2506is configured to combine the phase-shifted signals provided (e.g. phase-shifted signals2510) thereto and generate PWM signals2508. Waveform combiner2506can include analog/digital circuitry configured to generate, compare, summate, combine, detect, or amplify PWM signals2508. Such circuitry may include, but is not limited to, edge detectors, analog or digital logic gates, operational amplifier, comparators, or any combination thereof. In some embodiments, waveform combiner2506is configured to generate one or more PWM signals2508according to received phase-shifted signals2510, while in other embodiments waveform combiner2506can be configured to generate two or more PWM signals2508according to received phase-shifted signals2510. By generating PWM signals2508according to the received phase-shifted signals2510, the generated PWM signals2508have phase-shifts and pulse widths relative to reference signals2502. These phase-shifted and pulse width adjusted signals are determined from the phase-shift parameters applied by phase-shifting elements2504in generating the phase-shifted signals2510. In some embodiments, phase-shift parameters are determined and stored in a memory or other storage device (e.g. a memory which may be part of or separate form controller2509, for example). It should be appreciated that in some embodiments the phase shift parameters are determined based on the PWM signal duty-cycle and phase shift that is required by a particular application of the PWM generator. These parameters may be pre-stored in the controller2509or in a separate external controller/memory. Typically, the phase shift parameters need to be dynamically adjusted depending upon the specific application, and so, an external system controller could be tasked with estimating/calculating these parameters based on various inputs from the system and passing them to PWM controller2509. As such, a person of ordinary skill in the art should appreciate that desired phase-shifts and pulse widths of the generated PWM signals2508relative to reference signals2502can be achieved through selecting the phase-shift parameters necessary to achieve the desired phase-shifts and pulse widths. In embodiments, controller2509can be configured to determine phase-shift parameters for respective phase-shifting elements2504based upon desired phase-shift and pulse widths for generated PWM signals2508. For example, controller2509can be configured to determine a desired phase shift and pulse width for a generated PWM signal2508relative to a reference signal2502. Based on the desired phase shift and pulse width, controller2509can determine phase-shift parameters using empirical or analytical techniques In more detail, the phase shift parameters may be determined based upon feedback or feedforward techniques or a combination of both. for one or more phase-shifting elements2504so that the phase-shifting elements generate phase-shifted signals2510that can, in turn, be used to generate a PWM signal2508having the desired phase shift and pulse width relative to a reference signal2502. Further, as will be described in detail herein below, generating PWM signals2508according to the received phase-shifted signals2510, the pulse width and phase of each generated PWM signal2508can be independently adjusted over a 0° to 360° range with arbitrarily fine resolution that is not affected by the operating frequency (e.g. the frequency of reference signal2508). The generated PWM signals2508are capable of maintaining phase and frequency lock to reference signal2502for a wide modulation range of the reference signal frequency. In embodiments, PWM generator100is suitable for generating accurate and dynamically adjustable PWM waveforms for high-frequency and very-high-frequency applications. PWM generator100has particular value in applications in which reference signal2508is derived from some radio frequency (“RF”) input source with respect to which precise timing of the PWM signal must be maintained, including PSIM-based tunable matching networks and PSIM amplifiers. Referring now toFIG.25B, a portion of an illustrative PWM signal Q(θ)2508generated by PWM generator (e.g. such as PWM generator2500described in conjunction withFIG.25A), has a pair of pulses2508a,2508b. Each of the pulses2508a,2508bhas a pulse widthw2512and is locked in phase and frequency to a reference signal VREF(θ)2502. PWM signal Q(θ)2508can be generated as discussed above in conjunction withFIG.25A. In the example embodiment ofFIG.25B, the generated PWM signal Q(θ)2508has a phase shift ϕ (identified by reference numeral2514) relative to reference signal VREF(θ)2502. Here, phase shift ϕ2514is defined between the rising edge of PWM signal Q(θ)2508and the negative-to-positive transition of reference signal VREF(θ) It should be noted that this definition of PWM phase shift is used throughout this disclosure. The phase shift2514illustrated inFIG.25Bis considered a positive phase shift. It should also be noted that the definition of phase shift is only truly unique between two sinusoidal signals at the same frequency. When describing the relationship between a PWM and sinusoidal signal such as inFIG.25B, the definition of phase shift is arbitrary. The phase shift definition used herein is only chosen for the sake of convenience. However, if one desires, one can define phase shift any other way, as long as the definition uniquely describes the relationship between the two signals inFIG.25B. If that is the case, phase shift based on one definition can always be converted to phase shift based on another definition without loss of generality. The phase shift definition has no effect on the circuit implementation. As discussed above, one of ordinary skill in the art will appreciate that desired pulse widths w2512and phase shifts ϕ2514relative to a reference signal2502can be achieved via selected values of phase-shift parameters provided to PWM generator2504necessary for phase-shifting elements2504to achieve the desired phase shift. Referring now toFIG.26, a PWM generator circuit2600includes a pair of phase-shifting elements2016,2018coupled such that processing of a reference signal2602occurs in parallel. Such an architecture is referred to herein as a “parallel architecture.” Phase shifting elements2620,2622may be the same as or similar to phase shifting elements2504a-2504N described above in conjunction withFIG.25. In a parallel architecture, inputs of at least two phase-shifting elements, are configured to receive a common reference signal (here reference signal2602), which may be the same as or similar to reference signals2502. Each phase-shifting element2616,2618is configured to generate a respective phase-shifted signal at its output based upon the received reference signal2602and a received predetermined phase-shift parameter provided from control signals2620,2632which may be provided from one or more controllers (such as controller2509described above in conjunction withFIG.25). Phase-shifting elements2616,2618are each configured to generate a phase-shifted signal by applying a phase-shift to a received reference signal2602according to a respective phase-shift parameter included in respective ones of controller signals2620,2622. According to embodiments, each phase-shifting element2616,2618can be configured to receive a respective one of control signals2620,2622. Control signals2620,2622can include one or more predetermined phase-shift parameter for each of the respective phase-shifting element2616,2618. In embodiments, control signals2620,2622can be generated by a processing circuitry such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof. In the illustrative embodiment ofFIG.26, phase-shifting element2616is configured to receive control signal2620which includes a phase-shift parameter including a phase-shift of ϕ. Further, phase-shifting element2618can be configured to receive control signal2622which includes a phase-shift parameter including a phase-shift of ϕ and a pulse width of w. Phase-shifting elements produce phase-shifted signals A, B at respective outputs thereof. Waveform combiner2606is configured to receive the phase-shifted signals A, B generated at the outputs of phase-shifting elements2616,2618. Waveform combiner2606can be the same as or similar to waveform combiner2506(FIG.25A). In response to phase-shifted signals A, B provided thereto, waveform combiner2606generates a PWM signal2608. PWM signal2608has phase-shift and pulse width characteristics according to the received phase-shifted signal. A generated by phase-shifting element2616and phase-shifted signal B generated by phase-shifting element2618. In the illustrative embodiment ofFIG.26, phase-shifted signals A and B are phase-locked to the reference signal2602and phase-shifted according to the respective phase shift valves (ϕ and w+ϕ) of the phase-shifting element from which they were generated. In embodiments, phase-shifted signals A and B can then be appropriately combined e.g. via waveform combiner2606to synthesize PWM signal2608with pulse width w and phase ϕ that is phase-locked to reference signal2602. One of ordinary skill in the art should appreciate that the amount of phase shift that is necessary for phase-shifting elements2616,2618to generate a desired PWM waveform2608is highly dependent upon the actual implementation of waveform combiner2608. It should also be appreciated that whileFIG.26shows a parallel architecture with only two phase-shifting elements, it should be noted that the parallel architecture can implemented using three or more phase-shifting elements. The number of phase shifting elements to include in a phase-shifter circuit is selected in accordance with the needs of a particular application. Factors to consider in selecting the number of phase shifting elements to include in a PWM generator include but is not limited to the number of rising/falling edges that the PWM waveform must have during a single period. In the simplest terms, each phase-shifting element controls the position of one rising or falling edge of the of the PWM waveform in relation to the start of its period. For example, inFIG.26, the PWM waveform has a single pulse every period and hence, it has only one rising and one falling edge; phase shifting element2616sets the position of the rising edge, and phase shifting element2618sets the position of the falling edge. In more complicated PWM waveforms, where it may be required to have more than one pulse each period there need to be more falling and rising edges, and more phase shifting elements are needed to control all the edges. For example, inFIG.28, Q has two pulses repeating every single period and a total of four edges in a period. Hence, to control the relative position of each of these edges, four phase-shifting elements are required. Another reason for having more phase-shifting elements than the required minimum is system redundancy and reliability. For example, inFIG.26an additional redundant phase-shifting element (identical to2616) can be implemented to produce another copy of signal A. In the case that one of the phase-shifting elements fails, the waveform combiner can automatically select the other copy of signal A. Referring now toFIG.27, PWM generator circuit2700or more simply, a PWM generator, includes a pair of phase shifting elements2716,2718with a first one of the phase shifting elements (here phase shifting elements2716) having an input configured to receive a reference signal2702and having an output coupled to both an input of a waveform combiner2706and an input of a second phase-shifting element (here phase-shifting element2718). An output of the second phase shifting element is coupled to a second input of waveform combiner2706. Such an architecture is referred to herein as a “cascade architecture.” In a cascade architecture, a first phase-shifting element2716, which may be the same as or similar to phase-shifting elements2504(FIG.1) is configured to receive reference signal2702at its input. The first phase-shifting element2716is configured to generate phase-shifted signal A at its output based upon reference signal2702and a respective predetermined phase shift parameter (provided, for example, by a controller such as controller2509described above in conjunction withFIG.25A). For example, phase-shifting element2716can be configured to generate phase-shifted signal A by shifting the phase of reference signal2702according to a predetermined phase-shift parameter. As discussed above with reference toFIG.26, a phase-shift element may be configured to receive a control signal that includes a predetermined phase-shift parameter. For example, in the illustrative embodiment ofFIG.27, phase-shifting element2716is configured to receive control signal2720that includes a phase-shift parameter ϕ. The cascaded architecture further includes a second phase-shifting element2718configured to receive, at its input, phase-shifted signal A generated by phase-shifting element2716. The second phase-shifting element2718is configured to generate phase-shifted signal B at its output based upon phase-shifted signal A and a respective phase-shift parameter. For example, in the illustrative embodiment ofFIG.27, phase-shifting element2718is configured to generate phase-shifted signal B by shifting the phase of phase-shifted signal B according to a predetermined phase-shift parameter here shown as (ϕ+w). Waveform combiner2706, which may be the same as or similar to waveform combiner2506(FIG.25A), is configured to receive the phase-shifted signals generated at the outputs of phase-shifting elements2716,2718and to generate PWM signal2708having a desired pulse width and a phase-shift relative to reference signal2702. In the illustrative embodiment ofFIG.27, phase-shifting elements2716,2718are configured to generate phase-shifted signals A and B phase-locked to the reference signal2702and phase-shifted with respect to reference signal2702by phase-shifts ϕ and ϕ+w respectively. However, the phase-shifting elements2716,2718in the cascade architecture introduce a phase shift of only ϕ and w (i.e. phase shifting element2716introduces phase shift ϕ and phase shifting element2718introduces phase shift w). In a parallel architecture on the other hand, phase-shifting elements phase shift the reference signal by ϕ and ϕ+w (e.g. inFIG.26, phase shifting element2616introduces phase shift ϕ and phase shifting element2618introduces phase shift ϕ+w). In general, for generating the same PWM waveform, the phase-shifting elements in a parallel architecture need to be able to introduce larger phase shifts and operate over a wider phase-shifting range compared to those in a cascaded architecture. A cascade architecture, on the other hand, a generated-PWM waveform may suffer from more jitter compared to the PWM waveform generated with a parallel architecture. The choice of one system architecture over the other is dependent upon a variety of factors including but not limited to the specific application and the requirements for the generated PWM waveform, and on the characteristics of the circuits available to implement them. Although the range of phase shift that each phase-shifting element can produce is an important deciding factor in the choice of cascaded versus paralleled architecture, dynamic behavior and transient response of the PWM generator is also highly dependent on the generator architecture. Paralleled architectures allow one to independently control the dynamics with which the rising and falling edges of the PWM waveform can be adjusted. In cascaded architectures on the other hand, the dynamics with which one can control the pulse of the PWM waveform is a combination of the dynamic responses of all the phase shifting elements. For generating single-pulse PWM waveforms (i.e. one PWM pulse per cycle of the periodic reference signal2502) such as the one shown inFIG.25B, architectures with two phase-shifting elements are sufficient (seeFIGS.26and27). However, by employing more phase-shifting elements, one can generate even more sophisticated PWM signals, including waveforms having multiple pulses and multiple related PWM signals (e.g., as may be used to drive the multiple switches in a multi-switch amplifier or converter). Referring now toFIG.28, a PWM generator2800is configured to generate a dual-pulse PWM waveform2808and includes at least four phase-shifting elements2824-2830each having outputs coupled to inputs of a waveform combiner2806. A first set of phase-shifting elements2824,2826are each configured to received reference signal2802at their respective inputs. Phase-shifting elements2824,2826are each configured to generate a phase-shifted signal at their respective outputs according to reference signal2802and a respective phase-shift parameter. For example, in the illustrative embodiment ofFIG.28, phase-shifting element2824is configured to generate a phase-shifted signal at its output by shifting the phase of reference signal2802according to phase-shifting element's2824respective phase-shift parameter (ϕ). Likewise, phase-shifting element2826is configured to generate a phase-shifted signal at its output by shifting the phase of reference signal2802according to phase-shifting element's2826respective phase-shift parameter (ϕ+α+γ). A second set of phase-shifting elements2828,2830are each configured to receive, at their inputs, a phase-shifted signal generated by respective ones of the first set of phase-shifting element2824,2826. For example, in the illustrative embodiment ofFIG.28, phase-shifting element2828is configured to receive, at its input, the phase-shifted signal generated by phase-shifting element2824and phase-shifting element2830is configured to receive, at its input, the phase-shifted signal generated by phase-shifting element2826. The phase-shifting elements2828,2830of the second set are each configured to generate a phase-shifted signal at their respective outputs based upon a phase-shifted signal generated by a phase-shifting element of the first set and a respective phase-shift parameter. For example, in the illustrative embodiment ofFIG.28, phase-shifting element2828is configured to generate a phase-shifted signal by further shifting the phase of the phase-shifted signal generated by phase-shifting element2824provided to the input of phase-shifting element2828. Phase-shifting element2828shifts the phase of the signal provided thereto by a phase of (∝). Similarly, phase-shifting element2830is configured to generate a phase-shifted signal by shifting the phase of the phase-shifted signal generated by phase-shifting element2826according to phase-shifting element's2830respective phase-shift parameter (β). Waveform combiner2806receives the phase-shifted signals generated at the output of phase-shifting elements2824-2830at inputs thereof, combines the signals provided thereto and generates PWM signal2808according to the received phase-shifted signal. In embodiments, PWM signal2808is a dual-pulse PWM waveform (i.e. a pair of pulses which occur within a single cycle of a reference signal waveform) having a first pulse width and phase-shift relative to reference signal2802and a second pulse width and phase-shift relative to reference signal2802. By using two sets of phase-shifting elements to generate PWM signal2808, it is possible to generate a dual-pulse PWM waveform. In the illustrative embodiment ofFIG.28, PWM waveform2808includes a dynamically and independently controlled phase ϕ with pulse widths α and β, and spacing between the pulses y while maintaining phase and frequency lock to the reference signal2802. One possible way to achieve this behavior is to design the waveform combiner in this example to toggle its output Q whenever one of its four inputs undergoes a negative-to-positive transition. For instance, suppose that Q is logic low when REF undergoes a negative-to-positive transition atθ=0. The level of output signal Q remains low until the output of phase-shifting element2824undergoes a negative-to-positive transition atθ, at which point output signal Q toggles to logic high. Output signal Q remains at logic level high for (a degrees at which point the negative-to-positive transition of the output of the phase-shifting element2828resets Q. Similarly, the negative-to-positive transitions on the outputs of phase-shifting elements2826and2830cause another pulse of width β to follow the first one with a pulse spacing of γ. In this fashion, very complex multi-pulse PWM waveforms can be generated that remain phase- and frequency-locked to a reference signal input. Note that in the example ofFIG.28, both paralleling and cascading of phase-shifting elements is employed—i.e. it is a hybrid architecture. Referring now toFIG.29, a PWM generator2900includes a pair of phase-shifting elements2916,2918coupled in a parallel architecture. Phase shifting elements2916,2918may be the same as or similar to the phase shifting elements described above in conjunction withFIGS.25Am26. PWM generator2900also includes a phase detector2932which receives a portion of the reference signal at an input thereof. Phase detector2932also receives at an input thereof, a feedback signal from an output of a waveform combiner2906. Outputs of phase detector2932are coupled to phase shifting elements2916,2918. In embodiments, phase detector2932is configured to receive a portion of reference signal2902and a portion of PWM output signal2908and is configured to monitor (i.e. measure, detect, compute or otherwise determine) the phase between PWM signal2908and reference signal2902. Phase detector2932can include analog and/or digital circuitry configured to detect and compare the phases of two or more signals and can include a DSP, microprocessor, computer, microcontroller. Waveform combiner2908may be the same as or similar to waveform combiner2508(FIG.25). In embodiments, there may be significant propagation delays associated with the circuitry of waveform combiner2908. Such propagation delays result in phase modulation of the waveform combiner's2908output (i.e. the phase of the output signal of the waveform combiner may have a frequency variation which may interrupt the phase lock between reference signal2902and PWM waveform2902. In embodiments, phase detector2932can be configured to compare the phase between PWM signal2908and reference signal2902to a phase threshold. A phase threshold corresponds to a value for a phase indicating that the phase between PWM signal2908and reference signal2902has become too great. In other words, a phase threshold can include a value that indicates that PWM signal2908and reference signal2902are no longer in phase lock. In embodiments, phase detector2932can be configured to generate one or more phase correction signals when PWM signal2908and reference2902are determined to be no longer in phase lock. Phase correction signals can include data indicating an adjustment to one or more phase-shift parameters of respective phase-shifting elements in order to place PWM signal2908and reference signal2902in phase lock. Thus, phase correction signals include data to correct for the propagation delays causing PWM signal2908and reference signal2902to no longer be in phase lock. In embodiments, each phase-shifting element2916,2918is configured to receive a phase correction signal and, in response to the phase correction signal, adjust its phase-shift parameter. By adjusting the phase-shift parameter of a phase-shifting element2916,2918, the phase-shifted signal generated by the phase-shifting element2916,2918is also adjusted. Because PWM signal2902is generated by waveform combiner2908according to received phase-shifted signals, adjusting the phase-shift parameters allows for a correction in the PWM signal2902generated by waveform combiner2906. Referring now toFIG.30, PWM generation system3000includes a plurality of PWM generators3036a-3036N each of which may be the same as or similar to any of PWM generators2500,2600,2700,2800,2900described above in conjunction withFIGS.25A,26,27,28and29, respectively. Each PWM generators3036a-N is configured to receive reference signal3002. In the illustrative embodiment ofFIG.30, each PWM generator3036a-N includes at least two phase-shifting elements3016a-N,3018a-N configured to generate one or more phase shifted signals based upon reference signal3002and phase-shift parameters associated with each phase-shifting element3016a-N,3018a-N. For example, PWM generator3036aincludes phase-shifting elements3016a,3018awhich are configured to generate two or more phase-shifted signals based upon reference signal3002and phase-shift parameters associated with phase-shifting elements3016a,3018a. Each phase-shifted signal generated by a phase-shifting element A-N3016a-N,3018a-N, is provided to a respective waveform combiner3006a-N in order to generate a respective PWM signal3008a-N. In this way, multiple PWM signals3008a-N frequency and phase locked to reference signal3002can be generated with each PWM signal3008a-N having a respective pulse width and phase-shift relative to reference signal3002. In embodiments, each phase-shifting element3016a-N,3018a-N, is configured to receive a phase-shift parameter from a controller3034. Controller3034can include a processing circuitry such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof. In embodiments, controller3034is configured to receive an input comprising desired pulse widths and phase shifts relative to a reference signal3002for one or more desire PWM signals3008It should be appreciated that desired PWM pulse widths/phases can also be an input supplied by a user, or be pre-determined and stored in some look-up table in memory. Typically, however, desired pulse widths and phases will be determined by the controller in relation to some sort of system feedback whether it is impedance levels or some other measured voltage/current/power signals within the system. In embodiments, controller3034can receive an input comprising desired pulse widths and phase shifts relative to a reference signal3002from a computer, a microcontroller, a processor, a graphic user interface, an interaction device (i.e. a keyboard, a mouse, a touchscreen, etc.), or any combination thereof—to name a few. Based upon these desired pulse widths and phase shifts relative to a reference signal3002, controller3034is configured to determine the phase-shift parameters for each phase-shifting element necessary to achieve the desired pulse widths and phase shifts and provide them to the respective phase-shift elements. By having controller3034determine and provide the phase-shift parameters to the phase-shifting elements necessary to achieve the desired pulse widths and phase shifts, each PWM waveform3008A-N generated by PWM generation system300can be dynamically and independently adjusted by controller3034. In many applications, there is a need to generate multiple PWM waveforms that are properly synchronized with respect to each other. This is of particular interest in many kinds of converters where one needs to accurately commutate between two or more switches. For example, driving the switches in a half-bridge would require the generation of two PWM waveforms with controllable duty-ratio and separately controlled dead time for each transition. Both the phase and pulse width w of each PWM waveform can be dynamically and independently adjusted by a controller. One of skill in the art will appreciate that although the illustrative embodiment ofFIG.30shows all N of PWM generators3036a-N being based on the paralleled architecture (FIG.26), other architectures may be used, such as a cascading architecture, or any combination of the two. Depending on the specific requirements of an application, PWM generators with different architectures and/or implementations can be connected together and fed with a common reference signal. One of skill in the will note that characteristics of a particular PWM generation architecture are highly dependent on the implementation details of the phase-shifting elements and the waveform combiner. PWM generation architectures with phase-shifting element implementations based on both IQ modulators and phase-locked loops, as discussed below. Designs based on IQ modulators and phase-locked loops often allow one to control phase shift over a wide operating frequency range while preventing phase shift modulation with frequency variation. One of ordinary skill will note that there are other possible methods for implementing phase-shifting elements such as programmable/voltage-controlled delay lines and delay-locked loops. RegardingFIGS.31-35, embodiments of PWM generators are provided based on phase-shifting elements implemented with IQ modulators. In embodiment, IQ modulators allow for an RF carrier signal to be modulated according to a diverse range of amplitude, frequency and phase modulation operations. Referring now toFIG.31, PWM generation circuit3100implemented as an IQ modulator that includes an amplitude and phase shifting circuit3152having a first input configured to receive a local oscillator (LO) signal3140. PWM generation circuit further comprises a pair of optional amplifiers3144,3146. In this illustrative embodiment, a first one of the amplifiers is configured to receive an in-phase signa component I (also referred to herein a IBBand identified with reference numeral3138) and a second one of the pair of amplifiers is configured to receive a quadrature-phase signal component Q (also referred to herein as QBBand identified with reference numbered3140). Amplifiers3144,316receive the respective ones of IQ signals provided thereto and provide appropriately amplified signals to inputs of respective ones of a pair of mixers (or multipliers)3418,3150. Mixers3148,3150receive on second inputs thereof appropriately phase and amplitude adjusted LO signals from amplitude and phase shifting circuit3152. Outputs of mixers3148,3150are coupled to inputs of a summing circuit3154. Summing circuit3154appropriately sums the signals provided thereto provide a phase shift signal3110(an example of which is illustrated and described in conjunction withFIG.25Babove) Thus, IQ modulator is configured to receive a local oscillator (“LO”)3140which may be a signal the same or similar as reference signal2502. IQ modulator3100is configured to split LO3140into two orthogonal signal components I3138and Q3132. Signal Component I3138represents an in-phase component relative to LO3140, in other words component I3138and LO3140have the same phase. Component Q3132represents the quadrature component of LO3140which has a phase shift with reference to LO3140. For example, component Q3132can have a phase shift of 90° or π/2 radians with respect to LO3140. In embodiments, one or more signals derived from LO3140can be generated by amplitude and phase-shifting circuit3152. Amplitude and phase-shifting circuit3152can include analog and/or digital circuits configured to shift the phase and/or amplitude of LO3140in order to generate one or more signals derived from LO3140. In embodiments, amplitude and phase-shifting circuit3152is configured to generate signals derived from LO3140to be applied to component I3138(IBB) and a signal derived from LO3140to be applied to component Q3132(QBB). In embodiments, amplitude and phase-shifting circuit3152is configured to generate baseband signals in order to achieve a desired phase shift of LO3140. In embodiments, component I3138is provided to multiplier3148. In some embodiments, component I3138may first be provided to an amplifier3144before being provided to multiplier3148. It should be appreciated that amplifiers3144,3146can be used in general for any input signal conditioning, buffering or amplification/attenuation. It should be understood that although in this illustrative embodiment circuits3144,3146are schematically illustrated as amplifiers, the actual function of circuits3144/3146is highly dependent on the specific implementation of the IQ modualtor. Further, a signal derived from LO3140generated by amplitude and phase-shifting circuit3152is also provided to multiplier3148. Multiplier3148is configured to multiply component I3138and the signal derived from LO3140provide the product to adder3154. Likewise, component Q3142is provided to multiplier3150. In some embodiments component Q3142may be provided to an amplifier3146before being provided to multiplier3150. Further, a second signal derived from LO3140generated by amplitude and phase-shifting circuit3152is provided to multiplier3150. Multiplier3150is configured to multiply component Q3142and the signal derived from LO3140and provide the product to adder3154. Each multiplier3148,3150comprises analog and/or digital circuits configured to multiply two or more signals together. Adder3154includes analog and/or digital circuits configured to summate two or more signals together. Adder3154is configured to generate a phase shifted signal3110by summating the products provided by multiplier3148and multiple3150. In other words, adder3154is configured to generate a phase-shifted signal according to LO3140and the generated baseband signals IBBand QBB. In embodiments, the output of an IQ modulator can be expressed as: RF(t)=IBBcos(ωt)-Qbbsin(ωt)=(IBB2+QBB2cos(ωt+tan-1QBBIBB)[EQ1] Wherein RF(t) represents the phase-shifted signal generated by the IQ modulator. For the sake of simplicity, it can be assumed that the LO3140is split into the two orthogonal cos(ωt) and −sin(ωt) signals. Any absolute phase offset in LO3140will result in an identical absolute phase offset in the phase-shifted signal. As EQ. 1 suggests, by keeping IBB2+QBB2constant and adjusting the ratio of QBBto IBB, phase shift θ can be controlled between the local oscillator input and the RF output, while maintaining a constant RF magnitude. In embodiments, using the IQ modulator in this fashion—strictly as a phase modulator—is particularly suitable for implementing the phase-shifting elements required for PWM generation. Referring now toFIG.32, a phasor diagram (i.e. a polar plot) of an example I/Q modulation is provided. Represented in the polar view is QBB3242along the Y-axis, IBB3238along the X-axis of the plot, with the phase shifted signal3210generated by an I/Q modulator represented as a phasor between the two. As can be seen fromFIG.32, IBB3238essentially controls the real component of the phase-shifted signal phasor, while QBBsets its imaginary component. Thus, one of skill in the art will appreciate that by appropriately controlling the two base-band signals IBBand QBBone can independently modulate both the amplitude and phase of the phase-shifted signal3210. In embodiments, frequency modulation is also possible by appropriately modulating the phase of the output. As can be seen fromFIG.32, keeping IBB2+QBB2constant and adjusting the ratio of QBBto IBB., phase shift θ can be controlled between the LO3240input and the phase-shifted signal output3110, while maintaining a constant phase-shifted signal magnitude. Using the IQ modulator in this fashion—strictly as a phase modulator—is particularly suitable for implementing the phase shifting elements required for PWM generation. It should be noted that although the phase of the PWM waveform may vary with frequency for a fixed set of baseband inputs I and Q, the pulse width 11′ (in electrical degrees) remains constant and is not affect by frequency modulation. This is mainly due to the symmetric structure and the balanced path delays of the architecture ofFIG.33(referred to herein as a parallel architecture). It should also be appreciated that if the band-pass filters of the two IQ modulators inFIG.33have identical frequency-phase response, then a frequency variation will cause an identical phase offset to both IQ1and IQ2. However, the pulse width of the PWM waveform is equal to the differential phase of the two logic gate inputs with respect to the REF signal. Thus, if the propagation delays from IQ1and IQ2to the output Q are also matched, frequency modulation only causes a common mode phase shift to the logic gate inputs, and hence does not affect the pulse width w. This is one reason for using comparators with matched propagation delays in a common package (i.e. the comparators are implemented in the same integrated circuit package and hence, they are exposed to similar manufacturing process variables and temperatures resulting in nearly matched propagation delays) for the implementation of the waveform combiner. One of skill in the art will appreciate that if modulation of the PWM waveform phase ϕ with frequency for constant base-band inputs I and Q is undesirable for a particular application, a number of approaches can be pursued to alleviate this issue. For instance, I and Q can be tuned in response to a frequency variation to correct for any phase error in ϕ. This approach, however, requires an accurate measure of the frequency-phase response of the IQ modulators and the propagation delays associated with the waveform combiner circuitry. Furthermore, the controller that synthesizes the I and Q signals must keep track of the operating frequency—this may be undesirable and cumbersome for some applications. To achieve accurate phase control of the phase-shifting elements, a look-up table is implemented into a controller, the same or similar as controller3034, which maps a set of base-band I and Q values to a phase shift between the IQ output of the phase shifting element and its reference signal. In an example embodiment, the I and Q values are synthesized with 12-bit OACs, and so they can only take one of4096discrete values. To create the look-up table, one of the baseband inputs is swept over its entire digital range, while the other one is adjusted to keep the magnitude of I2+Q2roughly constant as suggested by (I). The phase shift between REF and IQ is measured for each of the4096pairs of base-band inputs and stored in the look-up table. This control approach corrects for any non-linarites in the DAC transfer functions, mismatches in the gain of the base-band channels of the IQ modulator, and the insertion phase of the output band-pass filter at a particular operating frequency. Referring now toFIG.33, a PWM generator3300includes one or more phase-shifting elements realized as a pair of IQ modulators as shown. The reference signal to which the PWM waveform is synchronized is fed to both IQ modulators and serves as their local oscillator input. A pair of DACs controlled with a microcontroller can be used to synthesize the appropriate values for the I and Q signals for each IQ modulator and thus control the Phase shift of their out outputs IQ1and IQ2with respect to the REF signal. In the illustrative embodiment ofFIG.33, PWM generator3300includes a waveform combiner3306implemented with a pair of comparators and a single logic gate here shown as an gate, here provided as an AND gate. It should be appreciated that in the example implementation shown inFIG.33, the logic AND gate has one inverting input. The gate is shown like this merely to simplify circuit complexity. In reality, however, the circuitry may be implemented with an AND gate with two non-inverting inputs along with a NOT gate at one of its inputs. Another way to implement the same circuit functionality is to reverse (i.e. flip) the +/−connections of comparator3368(which negates its output) and feeding the outputs of the two comparators to an AND gate with two non-inverting inputs. In fact, the latter is the actual circuit implementation that we have used in the construction of our prototype The output Q of waveform combiner3306is asserted (logic-high) only during the time when signal IQ1is positive and signal IQ2is negative. Thus, to generate a PWM waveform with pulse width w and phase ϕ, the IQ modulator outputs IQI and IQ2must be phase-shifted with respect to the REF signal by ϕ and ϕ+w respectively. It should be appreciated that, the resolution with which w and ϕ can be controlled depends upon the resolution with which the DACs can synthesize the I and Q inputs of the two IQ modulators. It should be noted that the implementation of the waveform combiner inFIG.33limits the pulse width of the output PWM waveform to a maximum of1800which corresponds to IQ1and IQ2being1800out-of-phase. As described below, however, this limitation can be alleviated with a different realization of the waveform combiner. In one embodiment, an IQ modulator-based implementation of a single phase-shifting element utilizes an L TC5598 (Analog Devices Inc.) chip which provides an integrated realization of an IQ modulator having differential base-band I and Q inputs and differential LO input. The differential voltages at the I and Q inputs are converted to currents that in turn drive double-balanced mixers. The outputs of these mixers are summed and applied to a buffer, which converts the differential mixer signals to a 50 n single-ended buffered RF output. The L TC5598 allows operation over a 5 MHz to1600MHz local oscillator frequency range, while supporting more than 400 MHz of base-band bandwidth, which enables very fast adjustment of a PWM waveform. The I and Q inputs are synthesized with a pair of 12-bit DACs (AD5624, Analog Devices Inc.); their single-ended outputs are buffered and converted to differential signals with a pair of fully differential operational amplifiers (L TC6362, Linear Technology). The DACs are controlled with a microcontroller through a standard SPI serial interface. A passive impedance matching network and a I: 1 balun (TC I-I TG2+, Mini-Circuits) convert the differential LO input of the IQ modulator to a single-ended 50 n reference input REF. Referring now toFIG.34, a plot of phase shift command vs. measure phase shift error illustrates good correspondence between a commanded phase shift and the phase shift achieved in response to such a commanded phase shift. In some embodiments, to control the phase shift produced by an IQ modulator-based phase-shifting element, the appropriate I and Q inputs must be provided to the IQ modulator. One way to determine these inputs is through the use of a look-up table. A pre-determined look-up table stored in the controller's memory lists the I and Q signal values that are required to produce a certain commanded phase shift. This look-up table can be pre-computed or measured empirically. AsFIG.34suggests, with this look-up table approach one can control the phase of the phase-shifting element outputs (e.g. phase-shifted signals IQ1and IQ2in the circuit ofFIG.33can be controlled to within 0.5° over the entire 360° range of commanded phase shift). If desirable, the control accuracy can be further improved by using DACs with higher number of bits to synthesize the I and Q inputs. Referring now toFIG.35, a plot of phase shift command vs. measured phase shift standard deviation (STD) illustrates the standard deviation of the measured phase error achieved in a prototype circuit. The standard deviation of the measured phase error inFIG.35can be thought of as an indirect measure of the jitter in the output of the prototype IQ modulator-based phase-shifting element.FIG.35shows the certainty with which the phase error measurements inFIG.34are made for a given commanded phase shift over the entire −180° to 180° range. FIG.35serves as an important metric that validates the phase error measurements ofFIG.34. As noted above, the standard deviation of the measured phase error inFIG.35can be thought of as a measure of the jitter in the outputs of the phase-shifting elements and it is mainly attributed to jitter in the reference signal and the oscilloscope acquisition system with which the phase measurements were performed. Thus,FIG.35serves to validate the measurements of phase error inFIG.34.FIG.35basically illustrates that the measured phase errors shown inFIG.34are accurate to within approximately ±0.1°. In other words,FIG.34shows the measured phase error, andFIG.35shows how certain that measurement is (what is known as standard deviation). Next described is the use of phase-locked loops (PLL) in implementing phase-shifting elements for PWM waveform generation. Also described is a design example of a cascaded PWM generation architecture having a plurality of phase-shifting elements comprising PLL's. In general, PLL-based approaches for generating a variable duty cycle waveform allows dynamic control of both angular pulse width and phase ϕ (relative to a reference signal) independently from frequency, i.e. frequency modulation affects neither w nor ϕ. Angular pulse width, here refers to the width of the pulse of the PWM waveform expressed in degrees out of a 360° cycle (one full period). For example, a PWM waveform with a 100 nsec period and a 25 nsec pulse width has a 90° angular pulse width (a quarter of a single period). By using this notion of angular pulse widths, one can describe the width of a pulse with relation to its period without the need to specify a frequency. This is somewhat similar to the notion of using 0-100% duty cycle to describe PWM waveforms. Referring now toFIG.36, a circuit3600capable of generating a variable duty cycle waveform includes a phase shifting circuit3604comprising a pair of phase-shifting elements3604a,3604b. Phase-shifting elements3604a,3604beach comprise a PLL3616,3618with a first one of the PLLs3616having an input3616aconfigured to receive a reference signal3602. PLL3616provides a phase-shifted signal A at an output3616bthereof. PLL output3616bis coupled though a signal path to a first input of a waveform combiner3606. A portion of PLL output signal A is also coupled to both an input3618aof a second PLL3618as well as through a time delay circuit3674to a feedback input3616cof PLL3616. Thus, the first and second phase-shifting element3604a,3604bare coupled such that a phase-shifted output signal generated by a first phase-shifting element3604aserves as a reference signal (i.e. an input signal) of a second phase-shifting element3604b. Thus, the phase-shifting elements3604a,3604bare said to be coupled in a so-called “cascade” architecture. Time delay element3674introduces a time delay T in the feedback path of PLL3616. The time delay T is selected to match a propagation delay through the waveform combiner circuitry3603from input3606a(i.e. signal A input inFIG.36) to output3606C (i.e. signal Q output inFIG.36). Such delay may possibly include switch gate driver delay as well as any other delay. As will be described in detail below time delay element3674introduces a time delay τ selected to substantially reduce (and ideally eliminate) the dependence of phase shift φ on frequency modulation. In response to signals provided to the input3618athereof, PLL3618provides a phase-shifted signal B at an output3618bthereof. Output3618bof PLL3618is coupled though a signal path to a second input of waveform combiner3606. A portion of PLL output signal B is also coupled to a feedback input3618cof PLL3618. Waveform combiner3606combines the signals provided thereto at inputs3606a,3606band provides a PWM signal3608having a desired waveform at output3606c. Waveform combiner3606combines the signals provided thereto using any of the techniques described herein or any other technique suitable to produce the PWM signal3608. Each PLL module3616,3618generates a respective output signal A, B at the respective outputs3616b,3618bsuch that the signals fed back to the respective feedback inputs are frequency-locked to the input signal provided to the respective input3616a,3618aand is phase-shifted with respect to it (i.e. phase-shifted with respect to the respective input signal) by a certain amount. The PLL modules3616,3618thus allow direct control the of the phase shift between the input and the feedback signals. This phase shift may be digitally controlled (e.g., via a microcontroller (pC)3662or via some other source of control) and can be adjusted from −180° to +180° with an arbitrary resolution. The resolution may depend, for example, upon the implementation of the PLLs. Depending upon the implementation of a PLL-based phase-shifting element, the phase shift it produces is typically controlled by the means of an analog current or voltage signal. It is the resolution with which this analog signal can be synthesized that ultimately determines the resolution with which phase shift can be controlled. Often, the analog control signal is synthesized with a digital-to-analog converter (DAC). The DAC itself could be a part of the microcontroller, or can be a part of the design of the PLL phase-shifting element. In the former case, the microcontroller directly synthesizes the analog control signal, and in this case it is indeed the resolution of the microcontroller that determines the resolution with which phase shift can be controlled. In the latter case, however, the microcontroller can digitally control the DAC that is part of the PLL phase-shifting element. In this case, it is the PLL implementation that determines the resolution with which one can control phase shift. FIG.36is thus an example of a cascaded PWM waveform generator having phase-shifting elements implemented using phase-locked loop modules coupled to a waveform combiner. In embodiments, the waveform combiner may be implemented using one or more logic gates such as a single AND gate. Such an approach allows the generation of a PWM waveform having a dynamically adjustable duty-cycle and phase cp. It should be noted that with a waveform combiner provided from a single logic gate, the angular pulse width w of the PWM waveform may be limited to a maximum of 180°. Considering circuit3600ofFIG.36, if the time delay element T in the feedback path of PLL3616is zero and PLL3616(PLL1) is commanded to provide a phase shift of between its input and feedback signal, this causes output signal A (i.e. the output of PLL3616) to be frequency-locked to the reference input REF and phase-shifted with respect to it by ϕ (assuming τ=0). In this example, a phase shift of between the reference signal REF and the output signal A implies that a rising edge of the output signal pulse lags the negative-to-positive transition in the reference signal by a phase of ϕ. Similarly, suppose that PLL3618(PLL2) is commanded to provide a phase shift of w between its input and feedback signals. Since the output of PLL1serves as the input of PLL2, signal B has a phase shift of w with respect to signal A and hence lags the reference signal REF by a phase shift of ϕ+w. In one embodiment signals A and B may be combined with a logic AND gate to produce the output signal Q having an angular pulse width w and a phase shift ϕ between its rising edge and the negative-to-positive transition of the REF signal. It should be noted that in this scenario, signal B is first inverted before being logically combined (i.e. via an AND logic gate) with signal A. It should also be noted that due to a propagation delay of the waveform combiner circuitry, any frequency modulation of the REF signal will cause a corresponding change in the phase shift ϕ of the PWM waveform. This dependence of the PWM waveform phase on frequency may be substantially reduced (and ideally eliminated) by tuning the time delay τ in the feedback path of PLL1to match the propagation delay of the waveform combiner logic gate(s) (e.g. an AND gate). To clarify this further, suppose that PLL1inFIG.36is commanded to provide a phase shift Φ between its input and feedback signals. A time delay of τ in the feedback path of PLL1will cause the output signal A to lead the signal at feedback input3616c(also denoted FB inFIG.36) by time τ. If the time delay τ matches the propagation delay of the waveform combiner, then signal Q will be in phase with the signal at feedback input3616c(FB), and hence, output signal Q will lag the reference signal REF by a phase corresponding to the commanded phase shift. Thus, the phase of the PWM waveform will be set by the commanded phase shift of PLL3616and will not be affected with frequency variation. It should be noted that the amount of propagation delay that can be compensated by the feedback loop in this fashion while guaranteeing PLL stability depends upon the phase margin and bandwidth of the PLL feedback loop. PLL designs having high loop bandwidth can tolerate only small amount of loop delay and hence require the use of logic circuitry in the waveform combiner having a sufficient operational speed to support such operation. On the other hand, being able to fully compensate the propagation delay of waveform combiners having large propagation delays (as may be the case when using transistor gate drivers as logic gates) necessitates the design of a PLL with slow loop bandwidth and thus limits the speed with which phase of the PWM waveform can be adjusted. Although a waveform combiner comprising only a single logic gate (e.g. a single AND logic gate having an inverted input coupled to PLL output3618b) is relatively simple to implement, it only allows generation of a PWM waveform having a maximum angular pulse width of 180 degrees (50% duty cycle) which corresponds to signals A and B being 180 degrees out-of-phase. Furthermore, this is only possible if both signals A and B have 50% duty-cycle. Many applications, however, require the ability to control the duty-cycle of PWM waveforms over a wider range. Thus, an alternative implementation of a waveform combiner which alleviates the above-noted limitations is described below in conjunction withFIG.37. In general overview,FIG.37is a cascaded phase-locked PWM generator 3700 having a waveform combiner provided from edge detectors coupled to a D-type flip-flop. This approach allows dynamic adjustment of PWM phase ϕ and angular pulse width w over a 360° range. As discussed above, time delay element τ included in a feedback path of a first PLL receiving a reference signal is selected to substantially match the propagation delay through the waveform combiner circuitry from an input A to an output Q and thus eliminate the dependence of Φ on frequency modulation. Referring now toFIG.37, an illustrative circuit for PWM waveform generation includes a pair of phase shifting elements3704,3704coupled to a waveform combiner3706. Phase shifting elements3704,3704may be the same as or similar to the phase shifting elements3604a,3604bdescribed above in conjunction withFIG.36. In this illustrative embodiment, waveform combiner3706comprises a pair of edge detectors3778,3780each of which receives inputs from respective ones of phase shifting elements3704,3704. Edge detectors3778,3780are here implemented with a logic gate (here illustrated as an AND logic gate having an inverter coupled to one input thereof). One of ordinary skill in the art will appreciate, of course, that edge detectors may be implemented using any type of circuits. One of ordinary skill in the art will further appreciate that any type of circuit capable of detecting signal edges (e.g. rising and/or falling edges of a signal) may also be used. The output of a first one of the edge detectors, here edge detector3778, is coupled to a clock input CLK of a D-type flip-flop 3782. The output of a second one of the edge detectors, here edge detector3780, is coupled to a reset input RESET of the D-flip-flop3782. The D input of flip-flop3782is coupled to a reference signal (here a logic signal has a value of a logic 1). This D-type flip-flop arrangement alleviates the above-noted limitation of the circuit ofFIG.36. Since the D input of the flip-flop is coupled to a signal having a logic-high signal level, a rising edge on the CLK input sets output signal Q high (i.e. a logic-high signal level), while a rising edge on the RES input clears Q (i.e. sets the output signal Q to a logic-low signal level). The edge detectors3778,3780at the inputs of the combiner generate a pulse to drive the flip-flop when a rising edge occurs on signals A or B. It should, of course, also be appreciated that depending upon the implementation of the flip-flop, the use of edge-detectors may not be required. For flip-flops with an asynchronous reset input, the output signal Q will be forced to a logic-low signal level as long as RES is logic-high irrelevant of the CLK input. In such cases, it is important to use edge detectors to prevent the flip-flop from “skipping” the rising edge of signal A while signal B is logic-high. When using edge detectors, the maximum PWM pulse width that can be obtained is roughly equal to the time period of the REF signal minus the pulse width of the edge detector output. It should thus be appreciated that waveform combiner3706allows control of the angular pulse width and phase of the PWM waveform over nearly a 360° range. In some applications it may be desirable or necessary to generate a plurality of related “single-pulse” PWM waveforms. In general, a PWM waveform can comprise multiple pulses in a single period with various pulse widths and spacing between the pulses. In such a “multi-pulse” PWM waveform, the pulse pattern repeats every cycle at the PWM waveform frequency. For example, inFIG.28, each 360° cycle of the generated PWM waveform has two pulses with widths α and β. A PWM waveform comprising only a single pulse every 360° cycle (one full period) is termed here “single-pulse PWM waveform”. Circuits and systems capable of generating such a plurality of such single-pulse PMW waveforms might be used, for example, to drive complementary switches in a half-bridge with controllable duty ratio and separately controllable dead-times between switches. In other applications, it may be desirable or necessary to provide controllable overlap on times, rather than controllable dead times, or more than two related single-pulse waveforms.FIG.38shows an example design of a PWM generation system capable of generating a plurality of, here two, PWM waveforms that are phase- and frequency-locked to a common reference signal REF. Referring now toFIG.38, a PWM generation system3800includes a reference signal source3802which generates a reference signal. The reference signal is provided to inputs of each of a plurality of PLL-based PWM generators3836a-3836N. PLL-based PWM generators3836a-3836N may be the same as or similar to PWM generator3700described above in conjunction withFIG.37. Taking PWM generator3836aas representative of PWM generators3836a-3836N, PWM generator includes a pair of PLLs3816a,3816bcoupled in a cascade configuration. As described above, in a cascade configuration, a first one of the PLL's3816areceives reference signal from reference signal source3802at an input thereof and output of PLL3816ais coupled to an input of a second, different PLL3818such that a phase-shifted output signal from PLL3816aserves as a reference signal (i.e. an input signal) of PLL3818a. As described above, an output of PLL3816ais coupled through a time delay circuit3874ato a feedback input of PLL3816a. The phase-shifted signals generated by PLLs3816a,3818aare provided to inputs of a waveform combiner to generate a PWM output signal Q at an output3808aof PWM generator3836a. PMW generation system3800further includes a controller3834. Controller3834provides phase-shift parameter values to phase-shifting elements in each of the PWM generators3836a-3836N. In particular, controller3834provides phase-shift parameter values3812a-3812N to respective ones of PLLs3816a-3816N,3838a-3838N. Thus, in the case where system3800comprises two of the PLL-based PWM generators3836fed with the same reference signal, the system is capable of independently controlling the phase shift ϕ1, ϕ2and the pulse widthw1,w2of two PWM waveforms Q1and Q2, respectively. The circuit ofFIG.38can be used, for example, to generate drive signals for two complimentary switches in a half-bridge circuit with controllable duty-cycle and dead time. In an embodiment having two PWM generators3836and in which a reference signal frequency may vary over a range of 5 MHz to 20 MHz, the PWM waveforms Q1and Q2may be provided having approximately 25% duty-cycle and 25% symmetric dead time, i.e. the dead time at each transition is about 25% of the PWM period. The rising edges of Qi and Q2may be 180° apart and aligned with the maximums and minimums of the reference signal respectively. In such an embodiment, as frequency varies over the entire 5 MHz to 20 MHz range, PWM duty-cycle, dead times and phase shift are not affected. Referring now toFIG.39, an illustrative PWM generation system3900includes first and second phase shifting elements3904a,3904bcoupled such that a phase-shifted output signal generated by a first PLL3916serves as a reference signal (input) of a second PLL3918. Thus, PLLs3916,3918are coupled in the so-called cascade architecture described above in conjunction withFIG.36. However, in contrast to the cascade arrangement described above in conjunction withFIG.36, in the illustrative embodiment ofFIG.39, a feedback signal provided to FB input3916cof PLL3916is taken directly from an output of a waveform combiner3906(i.e. a portion of output signal Q is provided to a feedback input3916cof PLL3916). System controller3934provides phase-shift parameters to phase shifting elements3904a,3904band in particular, to PLLs3916,3918. The phase-shift parameters comprise at least one or more phase shift values. In the example ofFIG.39, system controller3934provides a phase-shift value of ϕ to phase shifting element3904aand provides a phase-shift value of w to phase shifting element3904b. Providing phase-shifting element3904awith a predetermined phase-shift value of ϕ forces PLL3916to adjust the phase of its output signal (i.e. signal A inFIG.39) until the phase shift between the reference signal REF and the feedback signal provided to the FB input of PLL3916is a phase of ϕ. As described above, since the phase-shifting elements3916,3918are coupled in the so-called cascade configuration, this results in phase-shifting element3904bproducing a phase-shifted signal B having a phase shift of ϕ +w. The phase-shifted signal produced by phase-shifting elements3904a,3904bare combined in the waveform combiner3906to generate PWM signal3908(i.e. output signal Q) having a phase shift ϕ and a pulse width w. Thus, the phase of the PWM waveform with respect to reference signal REF can be directly controlled as frequency varies without the need to compensate for propagation time delays in waveform combiner circuitry. Referring now toFIG.40a flow diagram of process for generating a PWM signal having a desired pulse width and phase shift relative to a reference signal begins in processing block4002, in which a PWM generator receives a reference signal. Such a PWM generator may be the same as or similar to any of the PWM generators described herein and is configured to receive at least one reference signal. The reference signal may be the same as or similar to any of the reference signals described herein (including, but not limited to, reference signal)2502described above in conjunction withFIG.25B). In embodiments, the PWM generator can include at least one phase-shifting element, which may be the same as or similar to phase-shifting elements2504. The phase-shifting elements of the PWM generator may have either a parallel architecture, a cascade architecture, or both, as discussed above with reference toFIGS.26and27. Processing then proceeds to processing block4004in which at least one phase-shifting element of the PWM generator generates a phase-shifted signal at an output thereof. Such a phase-shifted signal may be the same as or similar to phase-shifted signals2508described in conjunction withFIG.25B. The phase shift of the phase-shifted signal may be based upon the reference signal(s) provided in processing block4002as well as based upon a respective predetermined phase-shift parameter. A phase-shift parameter can include a predetermined phase shift and/or predetermined pulse width used in the generation of the phase-shifted signal. For example, the predetermined phase-shift parameter can include a desired phase-shift for a respective phase-shifting element to apply to a reference signal in order to generate a phase-shifted signal. In embodiments, some phase-shifting elements can be configured to generate a phase-shifted signal by phase-shifting a reference signal according to a predetermined phase-shift parameter while other phase-shifting elements can be configured to generate a phase-shifted signal by phase-shifting a phase-shifted signal generated by another phase-shifting element. In embodiments, the predetermined phase-shift parameters can be generated by a controller which may be the same as or similar to any of the controllers described herein. The controller can be configured to generate the predetermined phase-shift parameters based upon desired pulse widths and phases relative to a reference signal for a PWM signal generated by the PWM generator. In embodiments, the controller is configured to provide the generated, predetermined phase-shift parameters to respective phase-shifting elements. Processing then proceeds to processing block4006in which the phase-shifted signals generated in processing block4004are combined to generate one or more PWM signals. The phase-shifted signals generated in processing block4004may be combined using a variety of techniques including any of the techniques described herein. For example, the phase-shifted signals maybe combined by providing the phase-shifted signals to a waveform combiner which may be the same as or similar to any of the waveform combiners described herein. For example, the waveform combiner can operate to compare, summate, detect, divide, (or any combination thereof) the received shifted signals to generate PWM signals. In embodiments, the generated PWM signals have a desired pulse width and phase shift relative to the reference signal based upon the predetermined phase-shift parameters of the phase shifting elements. Referring now toFIG.41A, an illustrative power generation and delivery system4100having first and second ports4127,1429includes a phase-switched and tunable impedance matching network4188(PSIM TMN) having an input coupled to port4127and having an output coupled to port4129. A means for monitoring impedance at port4127is coupled between port4127and PSIM TMN input4188aand a means for monitoring impedance4196is coupled between PSIM TMN output4188band port4129. The means for monitoring impedance4194,4196may measure, detect compute or otherwise determine impedances at one or both of ports41274129. Use of such means allows impedance to be determined dynamically. PSIM TMN4188includes one or more phase-switched impedance (PSIM) elements with N PSIM elements4190a-N here being shown. In embodiments, PSIM elements4190a-N may be the same as or similar to the phase-switched elements described herein (e.g. phase-switched reactance elements116discussed above with reference toFIG.1). Each PSIM element4190a-N is coupled to a PWM generation circuit4136which comprises at least one PWM generator. In embodiments, PWM generators in PWM generation circuit4136may be the same as or similar to the PWM generators described herein. PSIM element4190a-N are configured to be responsive to PWM signals provided by PWM generation circuit4136. In particular, in response to PWM signals generated by PWM generation circuit4136, PSIM TMN4088adjusts an impedance present at (i.e. looking into) either, or both of, the first and second ports4127,4129. In embodiments, portions of signals provided to and from PSIM TMN4188are coupled to PWM generators4136. It should be appreciated that the input/output signals of the TMN inFIG.41Acan be used as reference signals for the PWM generators to properly synchronize the switching of the PSIM elements to currents/voltages in the TMN network. As indicated byFIG.41A, one can also use external SYNC signals as reference for the PWM generator. PWM generators4136are each configured to receive at least one reference signal and at least one control signal. Control signals may be provided, for example, by a controller4184which may be the same as or similar to any of the controllers described herein. In the illustrative embodiment ofFIG.41A, M reference signals designated as SYNC 1−M, are shown (with M≤N) where N refers to the number of PSIM elements. It should, of course be appreciated that in general, the PWM generator can take-in an arbitrary number M of SYNC signals, and there is no real need to constraint M≤N (i.e. in some embodiments, it may be desirable or even necessary for M>N). For example, the PWM generator can take in more SYNC signals than there are PSIM elements and dynamically switch which SYNC signal to use for which PSIM element based on internal control or some command from the system controller. In response to the signals provided thereto, PWM generator, circuit4136generates at least one PWM signal having a pulse width and a phase shift relative to a reference signal. Reference signals can include signals which may be the same as or similar to reference signals described herein (such as, for example, reference signal2502described above in conjunction withFIG.25). PWM signals generated by PWM signal generators4136are provided to the at least one PSIM elements4190a-N. Each PWM generator4136can include one or more phase-shifting elements configured to generate phase-shifted signals (based, at least in part, upon phase-shift parameters provided from controller4184) and one or more waveform combiners configured to generate at least one PWM signal based upon the generated phase-shifted signals. In embodiments, PSIM TMN4188is configured to adjust the impedances presented at PORT1and/or PORT2according to the pulse widths and phase shifts relative to reference signals of the PWM signals generated by PWM signal generators4136. In other words, the impedances presented at PORT1and/or PORT2are determined based upon the pulse widths and phase shifts (relative to reference signals) of the PWM signals generated by PWM signal generator circuit4136. The desired impedance values presented at PORT1and/or PORT2may be achieved by appropriately selecting the values for the pulse widths and phase shifts of the PWM signals provided to PSIM TMN. After reading the description provided herein, one of ordinary skill in the art will further appreciate that desired values for the impedance presented at PORT1and/or PORT2may be achieved by selecting appropriate phase-shift parameters that are provided to the phase-shifting elements of PWM generators included in PWM generation circuit4136. In embodiments, predetermined phase-shifting parameters can be provided to the phase-shifting elements of PWM generators by system controller4184. System controller4184can include a DSP, processor, microprocessor, computer, microcontroller, or any combination thereof—to name a few. In some embodiments, system controller4184is configured to generate predetermined phase-shift parameters based upon desired values for the pulse widths and phase shifts relative to reference signals of the PWM signals generated by PWM generators4136. In other embodiments, system controller4184is configured to generate predetermined phase-shift parameters based upon desired values for the impedance presented at PORT1and/or PORT2. In some embodiments, the means for monitoring impedance4149,4196may be provided as one or more current and/or voltage (I-V) probes with at least one I-V probe coupled to PORT1and at least one I-V probe coupled to PORT2. Each I-V probe is configured to monitor (e.g. measure, detect compute or otherwise determine) a load impedance and/or impedance loading of PORTs1and2and provide a signal representative of the monitored load impedance and/or impedance loading to system controller4184. In embodiments, system controller4184is configured to adjust generated, predetermined phase-shift parameters provided to the phase-shifting elements4190a-4190N so as to adjust the values of the impedances at PORT1and/or PORT2to desired values. Thus, system controller4184can control the PWM generators and PSIM TMN4188based upon the monitored load impedance and/or impedance loading monitored (e.g. measured, detected, or otherwise determined) at PORT1and/or PORT2. Referring now toFIG.41B, an illustrative RF power generation and delivery system4100includes a system controller having a first output coupled to an RF input of an inverter4186and a second output coupled to an input of a PWM generation circuit4136. PWM generation circuit4136includes one or more PWM generators each of which may be the same as or similar to any of the PWM generators described herein. An output of RF inverter4186is coupled to an input of a PSIM TMN4188. An output of PSIM TMN4188is coupled to a load4192. PSIM TMN4188includes a plurality of PSIM elements4190a-N. Each PSIM element4190a-N is coupled to at least one PWM generator of PWM generation circuit4136. PWM generators in PWM generation circuit4136are configured to generate PWM signals having pulse widths and phase shifts relative to a reference signal. The PWM generators inFIG.41Bcan take a reference signal from the control system, from the input/output of the TMN, any internal current/voltage signal from the TMN, or any other externally provided SYNC signal similar toFIG.41A(as indicated by the dashed lines). The particular widths and phase shifts provided by the PWM generators are based upon phase-shift parameters provided by system controller4184. Some of the phase shift parameters provided by the control system are responsible for controlling the phase of the generated PWM waveform with respect to a reference signal, and other phase shift parameters control the pulse width of the PWM waveforms. In general, the phase-shift parameters that control PWM pulse width have to be adjusted dynamically and are often determined through some sort of feedback (e.g. measurements of TMN input/load impedance, reflected power at the TMN ports, etc.). These can also be controlled/overwritten directly by a user. The phase shift parameters that control the phase of the PWM waveforms typically do not need to be dynamically adjusted and can be pre-stored in a look-up table which can be obtained by a system calibration. In general, however, these phase shift parameters can also be determined based on feedback (e.g. voltage and current waveforms in the TMN, power lost in the PSIM devices, etc.) and may be dynamically adjusted by the control system (or overwritten by a user) to meet the demands of the system. In response to signals provided to and/or from PWM generation circuit, PSIM TMN4188adjusts impedances presented at its input and output. Thus, with RF inverter coupled to an input of4188and a load coupled to an output of PSIM TMN4188, in response to PWM signals generated by PWM generators4136, the impedance presented to RF inverter4186and/or load4092may be adjusted. In embodiments, system controller4184may generate values of predetermined phase-shift parameters provided to PWM generation circuit4136such that desired values for impedances presented to RF inverter4186and/or load4092may be achieved. One of ordinary skill in the art will appreciate that the desired values for impedances presented to RF inverter4186and/or load4092will depend on the operation, use, design, etc. of the RF power generation and delivery system. Referring now toFIG.42, an illustrative rf power generation and delivery system4200includes an RF inverter or amplifier4286having an output coupled to an input of a PSIM TMN4288. PSIM TMW4288includes at least one PSIM element. RF inverter4286is here illustrated as a voltage source4203and resistor RS4205. An I-V probe4294is coupled between the RF inverter and the PSIM TMN. A load4298having a load impedance ZLis coupled to the output of PSIM TMN4288. An I-V probe is coupled between PSIN TMN4288and load4298. The system further includes a PWM waveform generator4236(including phase-shifting element A4216, phase-shifting element B4218, and waveform combiner4206), I-V probes4294,4296, and system controller4284. Thus, in this illustrative embodiment, PSIM TMN4288is coupled, at its input, to RF inverter or amplifier4286and, at its output, to a load4298and is configured to adjust an impedance presented to RF inverter or amplifier4286and an impedance presented to load4298. In embodiments, the PSIM element includes capacitors CS14207, CS24217, and CP1, inductors LS14209and LS24215, and transistor q1. Transistor q1is configured to receive a drive signal4208from PWM generator4236, and in response thereto adjust the impedances presented at the input and/or output terminals of PSIM TMN4288(i.e. adjust the impedances presented to RF inverter or amplifier4286and/or load4298). The drive signal can be provided as a PWM signal generated by PWM generator4236using any of the techniques described herein. An input of PSIM TMN4288is coupled to an input of PWM generator4236(here through a level adjust circuit4233which may comprise, for example, an attenuator) so that a signal (e.g. voltage signal) at the input of PSIM TMN4288is provided to PWM4236as a reference signal4202. In embodiments, the signal at the input of PSIM TMN4288may first be provided to attenuator4284before being provided as reference signal4202ensure compatibility with the PWM generator's4236internal circuitry. In this illustrative embodiment, PWM generator4236is provided having a parallel architecture. Thus, reference signal4202is provided to both phase-shifting elements A, B4216,4218with each phase-shifting element configured to generate a phase-shifted signal4210A,4210B based upon respective predetermined phase-shift parameters. In embodiments, the predetermined phase-shift parameters can be provided to phase-shifting elements4216,4218by system control4284. It should, of course, be appreciated that in other embodiments it may be desirable or necessary to provide PWM generator4236having a cascade architecture. I-V probes4294,4296are configured to monitor (e.g. detect, measure, compute or otherwise determine) the impedances presented to load4298and RF inverter4286and provide the monitored impedances to system control4284. In embodiments, system control4284is configured to generate predetermined phase-shift parameters based upon the monitored impedances to achieve desired values for the monitor the impedances presented to load4298and RF inverter4286. Referring now toFIG.43, an illustrative rf power generation and delivery system4300includes a PSIM TMN4388with input and output terminals and two PSIM elements; an RF inverter or amplifier4386(including voltage source4303and resistor RS4305); PWM waveform generators A, B4236A,4326B (each including a first phase-shifting element4316A,B and a second phase-shifting element4318A,B, and waveform combiner4306A,B); I-V probes4394,4396, and a system controller4384. In embodiments, PSIM TMN4388is coupled, at its input, to RF inverter or amplifier4386and, at its output, to a load4398and is configured to adjust an impedance presented to RF inverter or amplifier4386and an impedance presented to load4298. A first PSIM element includes a transistor q14321configured to receive a drive signal and in response thereto adjust an impedance presented at the output terminal of PSIM TMN4288(i.e. adjust the impedance presented to load4398). In embodiments, the drive signal for q14321can be provided as a PWM signal generated by PWM generator4336A. A second PSIM element includes a transistor q24311configured to receive a drive signal and in response thereto adjust the impedance presented at the input terminal of PSIM TMN4388(i.e. adjust the impedance presented to RF inverter or amplifier4386). In embodiments, the drive signal for q24311can be provided as a PWM signal generated by PWM generator4336B. Each PWM generator4336is configured to generate a PWM signal based upon predetermined phase-shift parameters provided to its phase-shifting elements4316,4318. In embodiments, these phase-shifting parameters can be generated by system control4384, with system control4384configured to generate predetermined phase-shift parameters based upon desired values for the impedance presented at the inputs and outputs of PSIM TMN4388. Each PWM signal generated by PWM generators4336A,B has a pulse width and phase shift relative to a respective reference signal provided to the PWM generator. In embodiments, the reference signal provided to PWM generator A4336A can include one or more signals (e.g. a voltage signal) at the output of PSIM TMN4388and the reference signal provided to PWM generator B4336B can include one or more signals (e.g. a voltage signal) at the input of PSIM TMN4388. Due to this, PWM generator A4336A generates a PWM signal with a pulse width and phase shift relative to the signals at the output of PSIM TMN4388and PWM generator B4336B generates a PWM signal with a pulse width and phase shift relative to the signals at the input of PSIM TMN4388. In embodiments, I-V probes4396,4398on the input and output ports of the PSIM TMN4338monitor the impedances presented at the inputs and outputs of PSIM TMN4338based on which system control4384can control each PWM generator4336and the operation of RF inverter or amplifier4386(e.g. operating frequency, output power). Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the claimed subject matter. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” As used in this application, the words “exemplary” and “illustrative” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” or “illustrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “exemplary” and “illustrative” is intended to present concepts in a concrete fashion. Additionally, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. To the extent directional terms are used in the specification and claims (e.g., upper, lower, parallel, perpendicular, etc.), these terms are merely intended to assist in describing the embodiments and are not intended to limit the claims in any way. Such terms, do not require exactness (e.g., exact perpendicularity or exact parallelism, etc.), but instead it is intended that normal tolerances and ranges apply. Similarly, unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about”, “substantially” or “approximately” preceded the value of the value or range. Some embodiments might be implemented in the form of methods and apparatuses for practicing those methods. Further, as would be apparent to one skilled in the art, various functions of circuit elements might also be implemented as processing blocks in a software program. Described embodiments might also be implemented in the form of program code embodied in tangible media, such as magnetic recording media, hard drives, floppy diskettes, magnetic tape media, optical recording media, compact discs (CDs), digital versatile discs (DVDs), solid state memory, hybrid magnetic and solid state memory, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the claimed invention. Described embodiments might also be implemented in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium or carrier, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the claimed invention. When implemented on a processing device, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. Such processing devices might include, for example, a general purpose microprocessor, a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a microcontroller, an embedded controller, a multi-core processor, and/or others, including combinations of the above. Described embodiments might also be implemented in the form of a bitstream or other sequence of signal values electrically or optically transmitted through a medium, stored magnetic-field variations in a magnetic recording medium, etc., generated using a method and/or an apparatus as recited in the claims. Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here. It should be understood that the steps of the methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely illustrative. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments. It will be further understood that various changes in the details, materials, and arrangements of the parts that have been described and illustrated herein might be made by those skilled in the art without departing from the scope of the following claims. | 153,241 |
11942899 | DETAILED DESCRIPTION The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments of the disclosure relate to envelope tracking (ET) voltage correction in a transmission circuit. The transmission circuit includes a transceiver circuit and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and provides the RF signal(s) to the power amplifier circuit(s). The power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit (e.g., filter/multiplexer circuit). Notably, when the power amplifier circuit(s) is coupled to the RF front-end circuit, an output reflection coefficient (e.g., S22) of the power amplifier circuit(s) can interact with an input reflection coefficient (e.g., S11) of the RF front-end circuit to create a voltage distortion filter on an output stage of the power amplifier circuit(s), which can cause unwanted distortion in the modulated voltage across a modulation bandwidth of the RF signal(s). In this regard, in embodiments disclosed herein, the transceiver circuit is configured to apply at least one complex filter to apply a complex filter(s) to the time-variant modulation vector and/or the RF signal(s) to compensate for a voltage distortion filter created across the modulation bandwidth of the RF signal(s) by coupling the power amplifier circuit with the RF front-end circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulted from the voltage distortion filter to thereby improve efficiency and linearity of the power amplifier circuit(s) across the modulation bandwidth of the RF signal(s). Before discussing the transmission circuit according to the present disclosure, starting atFIG.2, a brief discussion of an existing transmission circuit is first provided to help understand how an unwanted voltage distortion filter may be created when a power amplifier circuit is coupled to an RF front-end circuit, such as a filter/multiplexer circuit. FIG.1Ais a schematic diagram of an exemplary existing transmission circuit10, wherein an unwanted voltage distortion filter HIV(s) may be created on a power amplifier circuit12when the power amplifier circuit12is coupled to an RF front-end circuit14. Notably, in the unwanted voltage distortion filter HIV(s), “s” is a notation of Laplace transform. The existing transmission circuit10includes a transceiver circuit16, an envelope tracking (ET) integrated circuit (ETIC)18, and a transmitter circuit20, which can include an antenna(s) (not shown) as an example. The transceiver circuit16is configured to generate an RF signal22associated with a time-variant voltage envelope24and provides the RF signal22to the power amplifier circuit12. The transceiver circuit16is also configured to generate a time-variant target voltage VTGT, which is associated with a time-variant target voltage26that tracks the time-variant voltage envelope24of the RF signal22. The ETIC18is configured to generate a modulated voltage VCChaving a time-variant modulated voltage28that tracks the time-variant target voltage26of the time-variant target voltage VTGTand provide the modulated voltage VCCto the power amplifier circuit12. The power amplifier circuit12is configured to amplify the RF signal22based on the modulated voltage VCCto a time-variant output voltage VOUTassociated with a time-variant output voltage envelope30. The power amplifier circuit12then provides the amplified RF signal22to the RF front-end circuit14. The RF front-end circuit14may be a filter circuit that performs further frequency filtering on the amplified RF signal22before providing the amplified RF signal22to the transmitter circuit20for transmission. FIG.1Bis a schematic diagram providing an exemplary illustration of an output stage32of the power amplifier circuit12inFIG.1A. Common elements betweenFIGS.1A and1Bare shown therein with common element numbers and will not be re-described herein. The output stage32can include at least one transistor34, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor34can include a base electrode B, a collector electrode C, and an emitter electrode E. The base electrode B is configured to receive a bias voltage VBIASand the collector electrode C is configured to receive the modulated voltage VCC. The collector electrode C is also coupled to the RF front-end circuit14and configured to output the amplified RF signal22at the output voltage VOUT. In this regard, the output voltage VOUTcan be a function of the modulated voltage VCC. Understandably, the power amplifier circuit12will operate with good efficiency and linearity when the time-variant modulated voltage28is aligned with the time-variant output voltage envelope30. FIG.2is a schematic diagram of an exemplary equivalent model36providing an exemplary illustration of the voltage distortion filter HIV(s) created by a coupling between the power amplifier circuit12and the RF front-end circuit14in the existing transmission circuit10ofFIG.1A. Elements inFIGS.1A and1Bare referenced inFIG.2without being re-described herein. In the equivalent model36, VPAand ZPArepresent the output stage32of the power amplifier circuit12and an inherent impedance of the power amplifier circuit12, respectively, and Z11represents an inherent impedance associated with an input port of the RF front-end circuit14. Herein, VOUTrepresents an output voltage associated with the RF signal22before the power amplifier circuit12is coupled to the RF front-end circuit14, and V′OUTrepresents an output voltage associated with the RF signal22after the power amplifier circuit12is coupled to the RF front-end circuit14. Hereinafter, the output voltages VOUTand V′OUTare referred to as “non-coupled output voltage” and “coupled output voltage,” respectively, for distinction. A Laplace transform representative of the coupled output voltage V′OUTcan be expressed in equation (Eq. 1) below. VOUT′(s)=VOUT(s)*[1-TPA(s)]*[1+TI(s)]2*[1-TPA(s)*TI(s)]=VOUT(s)⋆HIV(s)(Eq.1)HIV(s)=[1-TPA(s)]*[1+TI(s)]2*[1-TPA(s)*TI(s)] In the equation (Eq. 1) above, TPA(s) represents a reflection coefficient looking back into the output stage32of the power amplifier circuit12and TI(s) represents a reflection coefficient looking into the RF front-end circuit14. Notably, TPA(s) and TI(s) are complex filters containing amplitude and phase information. In this regard, the TPA(s), the TI(s), and, therefore, the voltage distortion filter HIV(s) are dependents of such factors as modulation bandwidth, RF spectrum, and/or voltage standing wave ratio (VSWR). The equation (Eq. 1) shows that the coupled output voltage V′OUTwill be altered from the non-coupled output voltage VOUTby the voltage distortion filter HIV(s) when the power amplifier circuit12is coupled to the RF front-end circuit14. Moreover, the variation of the non-coupled output voltage VOUTcaused by the voltage distortion filter HIV(s) can happen across an entire modulation bandwidth of the RF signal22. As a result, the coupled output voltage V′OUTmay become misaligned from the modulated voltage Vccacross the modulation bandwidth of the RF signal22, thus causing unwanted distortion in the RF signal22. According to various embodiments disclosed herein, it is possible to modify the modulated voltage Vccto compensate for the voltage distortion filter HIV(s) to thereby reduce or eliminate the difference between the non-coupled output voltage VOUTand the coupled output voltage V′OUTacross the modulation bandwidth of the RF signal22. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter HIV(s) across the modulation bandwidth of the RF signal22. FIG.3is a schematic diagram of an exemplary transmission circuit38configured according to an embodiment of the present disclosure to compensate for the unwanted voltage distortion filter HIV(s) in the existing transmission circuit10ofFIG.1A. The transmission circuit38is configured to transmit an RF signal40modulated in a wide modulation bandwidth. Herein, a modulation bandwidth refers to a range of RF frequencies that the RF signal40may be modulated onto. For example, if the RF signal40can be modulated between 2554 MHz and 2654 MHz, the modulation bandwidth will then be 100 MHz. In a non-limiting example, the RF signal40can be modulated in a modulation bandwidth of 200 MHz or higher and transmitted in a millimeter wave RF spectrum. The transmission circuit38includes a transceiver circuit42, a power amplifier circuit44, and an ETIC46. The power amplifier circuit44is coupled to a transmitter circuit48(e.g., an antenna circuit) via an RF front-end circuit50. In a non-limiting example, the RF front-end circuit50can include one or more of a filter circuit and a multiplexer circuit (not shown). The filter circuit may be configured to include a filter network, such as an acoustic filter network with a sharp cutoff frequency. The power amplifier circuit44may be identical to or functionally equivalent to the power amplifier circuit12inFIG.1B. As such, the power amplifier circuit44may also include the output stage32as in the power amplifier circuit12. The transceiver circuit42includes a signal processing circuit52and a target voltage circuit54. The signal processing circuit52is configured to generate the RF signal40from a time-variant modulation vector bMOD→ associated with time-variant amplitudes. The time-variant modulation vector bMOD→ may be generated by a digital baseband circuit (not shown) in the transceiver circuit42and includes both in-phase (I) and quadrature (Q) components. Since the time-variant modulation vector bMOD→ is generated in a digital domain, the I and Q components can thus provide a time-variant digital representation of the time-variant amplitudes of the time-variant modulation vector bMOD→. The signal processing circuit52further includes a modulator circuit56, which is configured to generate the RF signal40in an analog domain based on the time-variant modulation vector bMOD→ and modulate the RF signal40onto a selected frequency that falls within the modulation bandwidth of the transmission circuit38. Understandably, since the modulator circuit56generates the RF signal40from the time-variant modulation vector bMOD→, the RF signal40will be associated with a time-variant power envelope PENVthat tracks the time-variant amplitudes of the time-variant modulation vector bMOD→. Accordingly, the I and Q components can also provide a digital representation of the time-variant power envelope PENVof the RF signal40. The target voltage circuit54is configured to generate a modulated target voltage VTGTas a function of the time-variant modulation vector bMOD→. The ETIC46is configured to generate a modulated voltage Vccbased on the modulated target voltage VTGTand provide the modulated voltage Vccto the power amplifier circuit44. The power amplifier circuit44, in turn, amplifies the RF signal40from an input power PINto an output power POUT, which corresponds to an output voltage VOUT, based on the modulated voltage VCC. The RF front-end circuit50may perform further processes (e.g., filtering, frequency conversion, etc.) on the RF signal40. As a result, the RF front-end circuit50may cause the RF signal40to have another output voltage VOUT1, which can be different from the output voltage VOUT. Subsequently, the RF front-end circuit50provides the RF signal40to the transmitter circuit48for transmission in the selected frequency. Understandably, the closer the modulated voltage Vcccan track the time-variant power envelope PENVof the RF signal40, the better efficiency and linearity can be achieved at the power amplifier circuit44. However, the voltage distortion filter HIV(s) resulting from coupling the power amplifier circuit44with the RF front-end circuit50can change the non-coupled output voltage VOUTto the coupled output voltage V′OUT. As a result, the power amplifier circuit44can cause undesired instantaneous excessive compression and/or spectrum regrowth in the modulation bandwidth of the transmission circuit38. As such, it is desirable to reduce the undesired instantaneous excessive compression and/or spectrum regrowth across the modulation bandwidth of the transmission circuit38. As previously described inFIG.1B, the output voltage VOUTis a function of the modulated voltage VCC. In this regard, it is possible to reduce or even eliminate the difference between the non-coupled output voltage VOUTand the coupled output voltage V′OUTby generating the modulated voltage Vccto compensate for the voltage distortion filter HIV(s). Given that the ETIC46is configured to generate the modulated voltage Vccbased on the modulated target voltage VTGT, it is thus possible to reduce or even eliminate the difference between the non-coupled output voltage VOUTand the coupled output voltage V′OUTby generating the modulated target voltage VTGTto compensate for the voltage distortion filter HIV(s). In this regard, the transceiver circuit42further includes an equalizer circuit58. The equalizer circuit58is configured to apply an equalization filter HEQ(s) to the time-variant modulation vector bMOD→prior to generating the modulated target voltage VTGT. In an embodiment, the equalization filter HEQ(s) can be described by equation (Eq. 2) below. HEQ(s)=1/HRF(s) (Eq. 2) In the equation (Eq. 2) above, HRF(s) represents a transfer function of the RF front-end circuit50, which can be expressed as a ratio between VOUT1and VOUT. In this embodiment, the equalizer circuit58is configured to apply the equalization filter HEQ(s) to the time-variant modulation vector bMOD→ to thereby generate a filtered time-variant modulation vector bMOD-F→. In an embodiment, the transceiver circuit42includes a digital frequency equalizer60. The digital frequency equalizer60is configured to apply a digital frequency equalization filter HF(s) to the time-variant modulation vector bMOD→ to generate an equalized time-variant modulation vector bMOD-E→. In a non-limiting example, the digital frequency equalization filter HF(S) can be described by equation (Eq. 3) below. HF(S)=[1/HET(S)]*[1/HRF(s)] HET(S)=HIQ(s)*HPA(s)*HIV(s) (Eq. 3) In the equation (Eq. 3), HIQ(s) represents a transfer function of the signal processing circuit52, and HPA(s) represents a voltage gain transfer function of the power amplifier circuit44. In this regard, HET(S) is a combined complex filter configured to match a combined signal path filter that includes the transfer function HIQ(s), the voltage gain transfer function HPA(s), and the voltage distortion filter HIV(s). The target voltage circuit54is further configured to include a vector-to-real (V2R) converter62that is coupled to the equalizer circuit58. The V2R converter62is configured to extract a selected real parameter XRfrom the filtered time-variant modulation vector bMOD-F→. In a non-limiting example, the selected real parameter XRcan be a real parameter representing the output voltage VOUT, the input power PIN, or the output power POUT. The target voltage circuit54can also include a scaler64coupled to the V2R converter62. The scaler64can be configured to scale the selected real parameter XRbased on a scaling factor66to generate a scaled real parameter XRS. In an embodiment, the scaling factor66can be determined according to an average power (e.g., root-mean-square average) of the RF signal40. In a non-limiting example, the scaling factor66can be adapted between different timeslots or mini timeslots. The target voltage circuit54also includes an ET look up table (LUT) circuit68. The ET LUT circuit68includes a single LUT (not shown) predetermined according to the selected frequency of the RF signal40to correlate the modulated target voltage VTGTwith various types of input parameters. In one example, the LUT can be configured to correlate the modulated target voltage VTGTwith the selected real parameter XRthat represents the output voltage VOUT. In this regard, if the selected real parameter XRextracted by the V2R converter62indeed represents the output voltage VOUT, the ET LUT circuit68can simply look up the LUT based on the selected real parameter XRor the scaled real parameter XRSto generate the modulated target voltage VTGT. In case the selected real parameter XRextracted by the V2R converter62represents something different from the output voltage VOUT(e.g., the other output voltage VOUT1), the target voltage circuit54may further include a unit converter70to convert the selected real parameter XRto a predefined parameter configured in the LUT. Accordingly, the ET LUT circuit68can generate the modulated target voltage VTGTfrom the LUT based on the converted real parameter XR. As mentioned earlier, the LUT in the ET LUT circuit68may be predetermined based on the selected frequency of the RF signal40. As the voltage distortion filter HIV(s) causes the frequency response of the output voltage VOUTto change, it is equivalent to moving the output voltage VOUTaway from the selected frequency to a different frequency. In this regard, extracting the selected real parameter XRfrom the filtered time-variant modulation vector bMOD-F→ is equivalent to moving the LUT along with the frequency change of the output voltage VOUT. As a result, the modulated target voltage VTGTgenerated based on the LUT can compensate for the frequency shift of the output voltage VOUT. The signal processing circuit52may further include a memory digital predistortion (mDPD) circuit72, which is coupled between the digital frequency equalizer60and the modulator circuit56. The mDPD circuit72can be configured to digitally pre-distort the equalized time-variant modulation vector bMOD-E→ to generate a pre-distorted time-variant modulation vector bMOD-DPD→. Accordingly, the modulator circuit56is configured to generate the RF signal40from the pre-distorted time-variant modulation vector bMOD-DPD→ and provide the RF signal40to the power amplifier circuit.44. FIG.4is a schematic diagram of an exemplary transmission circuit74configured according to another embodiment of the present disclosure to compensate for the unwanted voltage distortion filter HIV(s) in the existing transmission circuit10ofFIG.1A. Common elements betweenFIGS.3and4are shown therein with common element numbers and will not be re-described herein. The transmission circuit74includes a transceiver circuit76that includes a digital frequency equalizer circuit78and an analog frequency equalizer circuit80. The digital frequency equalizer circuit78is configured to apply a digital frequency equalization filter HF1(s) to the time-variant modulation vector bMOD→ to generate an equalized time-variant modulation vector bMOD-E→. Herein, the mDPD circuit72is configured to digitally pre-distort the equalized time-variant modulation vector bMOD-E→ to generate the pre-distorted time-variant modulation vector bMOD-DPD→. Accordingly, the modulator circuit56is configured to generate the RF signal40from the pre-distorted time-variant modulation vector bMOD-DPD→. The analog frequency equalizer circuit80is configured to apply an analog frequency equalization filter HF2(s) to the RF signal40to provide the RF signal40to the power amplifier circuit44. The digital frequency equalization filter HF1(5) and the analog frequency equalization filter HF2(s) can be expressed in equation (Eq. 4) below. HF1(s)=1/HRF(s);HF2(s)=1/HET(s) (Eq. 4) In this embodiment, the equalizer circuit58is configured to apply the equalization filter HEQ(s) to the first equalized time-variant modulation vector bMOD-E1→. The equalization filter HEQ(s) is equal to 1. FIG.5is a graphic diagram providing an exemplary illustration of a modulation bandwidth82in which the transmission circuit38ofFIG.3and the transmission circuit74ofFIG.4can be configured to compensate for the unwanted voltage distortion filter in the existing transmission circuit ofFIG.1A. Elements inFIGS.3and4are referenced in conjunction withFIG.5and will not be redescribed herein. In this example, the modulation bandwidth82is bounded by a lower frequency84and an upper frequency86. The LUT in the ET LUT circuit68inFIGS.3and4is initially determined based on a selected frequency88that falls between the lower frequency84and the upper frequency86. In this regard, the selected real parameter XRextracted from the filtered time-variant modulation vector bMOD-F→ is equivalent to moving the LUT from the selected frequency88to any other frequency within the modulation bandwidth82. Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow. | 24,948 |
11942900 | Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. DETAILED DESCRIPTION In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention. Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale. An amplifier is an electronic circuit which provides an output which is a scaled version of its input. There may be more than one input to the amplifier and the inputs may be added or subtracted by different scaling factors to produce the output. An amplifier which subtracts one input from another is typically referred to as a differential amplifier. An amplifier which adds one input to another may be referred to as a summing amplifier. The inputs may be voltages or currents and the output may be a voltage or a current. A voltage input may produce a current output and a current input may produce a voltage output. An operational amplifier produces a voltage output from voltage inputs, whereas a transconductance amplifier produces a current output from voltage inputs. The scaling factor is typically referred to as the gain. An amplifier that has a voltage output from a voltage input has a dimensionless gain, whereas a transconductance amplifier has a gain with the units of transconductance (e.g., current divided by voltage). Amplifiers may be utilized in closed loop control systems, such as switched mode power converters. The amplifier may receive a sensed signal and a reference (or target) at its inputs and outputs an error signal representative of the difference between the sensed signal and the reference magnified by some gain. For closed loop control systems, the error signal is further processed to provide a control signal which is then utilized by the control system to regulate the sensed signal. The additional processing of the error signal is generally referred to as compensation. Amplifiers are used with compensation circuits to provide stability to the amplifier and the control system. In other words, compensation circuits are utilized to shape the magnitude and phase of the transfer function of the amplifier with frequency to achieve the desired frequency response of the amplifier. FIG.1illustrates an example amplifier with compensation100which receives a sense signal112and reference114and outputs a control signal116. The amplifier102shown is a transconductance amplifier with gain G. The inputs to amplifier102are voltages while the output of amplifier102is a current. Amplifier102receives the sensed signal112at is non-inverting input and a reference REF114at its inverting input. In the depicted example, the output of the amplifier102is a current signal substantially equal to the gain G multiplied by the difference between the sensed signal112and reference REF114(e.g., G(SENSED SIGNAL—REF). If the sensed signal112is greater than the reference REF114, current is sourced by the amplifier102(e.g., current is provided by the amplifier102to capacitance C1104). If the sensed signal112is less than reference REF114, current is sinked by the amplifier102to return110(e.g., current is sinked from capacitance C1104to the amplifier102). In the depicted example, compensation is provided by capacitance C1104and resistance R1106. As shown, capacitance C1104is coupled to the output of amplifier102and resistance R1106is coupled to capacitance C1104and return110. The voltage across resistance R1106is denoted as voltage VZ118. Resistance R2is coupled across capacitance C1104and resistance R1106and may be used to limit the low frequency gain of amplifier102. Capacitance C1104and resistance R1106is generally referred to as Type II compensation of the transconductance amplifier102. The transfer function of an output to an input of a circuit, also referred to as the frequency response, is the Laplace transform of the output divided by the input. A “zero” generally refers to the frequencies which result in the numerator of the transfer function becoming zero, and hence the transfer function is substantially zero. A “pole” generally refers to the frequencies which result in the denominator of the transfer function becoming zero, and hence the transfer function is infinite. The frequencies of the poles and zeros generally determine how the magnitude and phase of the transfer function respond over varying frequencies. As such, designing control systems with these poles and zeros in mind can determine the stability of the circuit. For the example shown inFIG.1, the transfer function (e.g., frequency response) of the control signal116to the difference between the sensed signal112and reference114is determined by the gain G of amplifier102, resistances R1106, R2109, and capacitance C1104, with resistance R1106contributing the “zero” of the frequency response while capacitance C1104contributing the “pole” of the frequency response. The values selected for the gain G, resistances R1106, R2109, and capacitance C1104determine the frequency of the pole and zero for the compensated amplifier100shown inFIG.1. The transfer function of the control signal116to the difference between the sensed signal112and reference114ofFIG.1is shown as equation (1), where “s” represents a complex number: CONTROLSENSED-REF=GR2sR1C1+1S(R1+R2)C1+1(1) As such, the zero and pole for the transfer function ofFIG.1may be shown in equations (2) and (3): fZ_FIG1=12πR1C1(2)fP_FIG1=12π(R1+R2)C1(3) If the amplifier102, resistances R1106, R2109, and capacitance C1104are external discrete components, there are very few limitations for selecting the values for the gain G, resistances R1106, R2109, and capacitance C1104to have the desired frequency response and locations for the pole and zero. However, if the amplifier102, resistances R1106, R2109, and capacitance C1104are internal components within an integrated circuit, there is a limit to the sizes and values which may be selected for the components due to the physical constraints of integration. As such, there is a limit to the frequency response of the compensated amplifier100shown inFIG.1. For example, for a frequency response with a magnitude of about 50 decibels (dB) with a 100 picofarad (pF) capacitance for capacitance C1104, the pole is about 25 hertz (Hz) and generally the zero should be around 300 Hz. However, with a 100 pF capacitance for capacitance C1104, the resistance R1106would be around 5.3 megaohms (MΩ), a value which is difficult to integrate into an integrated circuit. Solutions to compensate an amplifier as shown inFIG.1may include passive components, such as resistances and capacitances. In solutions that include passive components, the compensated amplifier100may be partially integrated. The first amplifier102may integrated while the resistances R1106and R2109and capacitance C1104may be external components. This would generally require a separate pin for compensation in the package which houses the integrated circuit that includes the first amplifier102. Embodiments in accordance with the teachings of the present disclosure include a compensated amplifier that utilizes an additional amplifier to provide compensation. In various examples, a first amplifier provides a first error signal representative of a difference between the inputs of the first amplifier. An integrator receives the first error signal and integrates the first error signal. The output of the integrator may be referred to as an integrated error. In the various examples, a second amplifier is also included which is also responsive to the inputs of the first amplifier. For instance, in one example, the second amplifier receives the same inputs as the first amplifier and provides a second error signal representative of a difference between the inputs of the first amplifier. The second error signal is then added to the integrated error to compensate the first amplifier. In one example, the sum of the integrated error from the integrator and the second error signal is utilized as a control signal for a control system, which may be utilized for example in a switched mode power converter. In various examples, the first amplifier, integrator, and second amplifier may all be integrated within an integrated circuit in accordance with the teachings of the present invention. To illustrate,FIG.2Aillustrates a functional block diagram of one example of a compensated amplifier200in accordance with the teachings of the present invention. As shown in the depicted example, the compensated amplifier200includes a first amplifier202, a second amplifier206, an integrator204, and an arithmetic operator208. In the example depicted inFIG.2A, first amplifier202is implemented with a differential amplifier and second amplifier206is implemented with a differential amplifier. In the example depicted inFIG.2A, arithmetic operator208is illustrated as an adder (e.g., “+”), which is configured to perform addition. However, it should be appreciated that a subtraction may be considered an addition of a negative value that may be performed by arithmetic operator208. In one example, the compensated amplifier200may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. In the depicted example, compensated amplifier200includes an input that is coupled to receive a sensed signal212and a reference signal214. Compensated amplifier200also includes an output that is coupled to output a control signal222. In the example depicted inFIG.2A, first and second amplifiers202and206are coupled to the input to receive the sensed signal212and reference signal214. In one example, sensed signal212is representative of a sensed quantity to be regulated while reference signal214is representative of a target value to which the sensed quantity is regulated. The compensated amplifier200provides signal compensation for the difference between the sensed signal212and the reference signal214and outputs the control signal222. Control signal222may then be utilized to control one or more parameters to regulate the sensed signal212. In other words, the second amplifier206, integrator204, and arithmetic operator208provide signal compensation for the first error signal216of the first amplifier202. As shown in the example ofFIG.2A, first amplifier202is coupled to receive the sensed signal212and the reference signal214and outputs a first error signal216. Functionally, the first amplifier202provides an output which is a scaled version of the difference between its inputs. The scaling factor may be referred to as the gain. As shown, the first error signal216is the difference between sensed signal212and reference signal214multiplied by the gain of first amplifier202. In another example, the first error signal216may be the difference between reference signal214and sensed signal212multiplied by the gain of first amplifier202. Example implementations of the first amplifier202include an operation amplifier with gain A1, or a transconductance amplifier with gain G1. For an example of the first amplifier202implemented with an operational amplifier, the sensed signal212and the reference signal214are voltages and the first error signal216is a voltage. For an example of the first amplifier202implemented with a transconductance amplifier, the sensed signal212and the reference signal214are voltages and the first error signal216is a current. As shown in the depicted example, integrator204receives the first error signal216and integrates the first error signal216to output an integrated error218. The integrated error218may be a voltage or current signal. One example of integrator204may be a capacitance. In one example, first amplifier202and integrator204may be implemented with an operational amplifier integrator. In the example illustrated inFIG.2A, second amplifier206is coupled to receive the sensed signal212and the reference signal214and outputs the second error signal220. It is appreciated therefore that the inputs of the first amplifier206are coupled together with the inputs of the second amplifier206to receive the sensed signal212and the reference signal214. Functionally, the second amplifier206also provides an output that is responsive to the sensed signal212and the reference signal214, which in one example is a scaled value of the difference between the sensed signal212and the reference signal214. The scaling factor is referred to as the gain. In the example illustrated inFIG.2A, the second error signal220is the difference between sensed signal212and reference signal214multiplied by the gain of second amplifier206. In another example, the second error signal220may be the difference between reference signal214and sensed signal212multiplied by the gain of second amplifier206. Examples of the second amplifier206include an operational amplifier with gain A2, or a transconductance amplifier with gain G2. For an example of the second amplifier206implemented with an operational amplifier, the sensed signal212and the reference signal214are voltages and the second error signal220is a voltage. For an example of the first amplifier206implemented with a transconductance amplifier, the sensed signal212and the reference signal214are voltages and the second error signal220is a current. As shown in the example depicted inFIG.2A, arithmetic operator208receives the integrated error218and second error signal220and outputs the control signal222. As shown, the control signal222is the summation of the integrator error218and second error signal220. While the arithmetic operator208depicted inFIG.2Aillustrates addition (e.g., “+”), it should be appreciated that subtraction may also be utilized and may be considered the addition of a negative value. As will be discussed further, the properties of the first amplifier202, integrator204, and second amplifier208determines the transfer function between the control signal222and the difference between the sensed signal212and reference signal214in accordance with the teachings of the present invention. FIG.2Billustrates a functional block diagram of another example of a compensated amplifier201in accordance with the teachings of the present invention. It is appreciated that the example compensated amplifier201depicted inFIG.2Bshares similarities with the example compensated amplifier200depicted inFIG.2A, and similarly named and numbered elements described above are coupled and function similarly below. For instance, as shown in the example depicted inFIG.2B, the compensated amplifier201includes a first amplifier202, a second amplifier207, an integrator204, and an arithmetic operator208. In the example, the first amplifier202and second amplifier207are configured to be responsive to the sensed signal212and the reference signal214to generate the first error signal216and the second error signal220, respectively. In the example depicted inFIG.2B, arithmetic operator208is illustrated as an adder (e.g., “+”), which is configured to perform addition. However, it should be appreciated that a subtraction may be considered an addition of a negative value that may be performed by arithmetic operator208. One difference between example compensated amplifier201ofFIG.2Band example compensated amplifier200ofFIG.2A, is that in the example depicted inFIG.2Bfirst amplifier202is implemented with differential amplifier and second amplifier207is implemented with an amplifier having an input coupled to the output of first amplifier202. Thus, the second amplifier207of example compensated amplifier201replaces the second amplifier206of compensated amplifier200. As shown in the example depicted inFIG.2B, second amplifier207is coupled to receive the first error signal216, which is responsive to the sensed signal212and the reference signal214, and outputs the second error signal220in response. In one example, the compensated amplifier201may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. In the example depicted inFIG.2B, compensated amplifier201also receives the sensed signal212and the reference signal214at its input and outputs a control signal222. As mentioned, first amplifier202of compensated amplifier201also receives sensed signal212and reference signal214. In one example, sensed signal212is representative of a sensed quantity to be regulated while reference signal214is representative of the target value to which the sensed quantity is regulated. The compensated amplifier201provides signal compensation for the difference between the sensed signal212and the reference signal214and outputs the control signal222. Control signal222may then be utilized to control one or more parameters to regulate the sensed signal212. In other words, the second amplifier207, integrator204, and arithmetic operator208provide signal compensation for the first error signal216of the first amplifier202in accordance with the teachings of the present invention. As shown, first amplifier202is coupled to receive the sensed signal212and the reference signal214and outputs the first error signal216. Functionally, the first amplifier202provides an output which is a scaled version of the difference between its inputs. The scaling factor may be referred to as the gain. As shown, the first error signal216is the difference between sensed signal212and reference signal214multiplied by the gain of first amplifier202. In another example, the first error signal216is the difference between reference signal214and sensed signal212multiplied by the gain of first amplifier206. Examples of the first amplifier202include an operation amplifier with gain A1, or a transconductance amplifier with gain G1. For an example of the first amplifier202implemented with an operational amplifier, the sensed signal212and the reference signal214are voltages and the first error signal216is a voltage. For an example of the first amplifier202implemented with a transconductance amplifier, the sensed signal212and the reference signal214are voltages and the first error signal216is a current. As shown in the depicted example, integrator204receives the first error signal216and integrates the first error signal216to output an integrated error218. The integrated error218may be a voltage or current signal. One example of integrator204may be a capacitance. In the example illustrated inFIG.2B, second amplifier207is coupled to the output of the first amplifier202to receive the first error signal216to output the second error signal220in response. Functionally, the second amplifier207provides an output that is a scaled value of its input, the first error signal216, which is responsive to the sensed signal212and the reference signal214. The scaling factor is referred to as the gain. Thus, the second error signal220is the first error signal216multiplied by the gain of second amplifier207. As shown in the example depicted inFIG.2B, arithmetic operator208receives the integrated error218and second error signal220and outputs the control signal222. As shown, the control signal222is the summation of the integrator error218and second error signal220. While the arithmetic operator208depicted inFIG.2Aillustrates addition (e.g., “+”), it should be appreciated that subtraction may also be utilized and may be considered the addition of a negative value. As will be discussed further, the properties of the first amplifier202, integrator204, and second amplifier207determines the transfer function between the control signal222and the difference between the sensed signal212and reference signal214in accordance with the teachings of the present invention. FIG.2Cillustrates example straight-line Bode plot diagrams of the magnitude and phase of the frequency response of the control signal to the difference between the sensed signal and reference in an example compensated amplifier in accordance with the teachings of the present invention. It should be appreciated that the straight-line Bode diagrams shown inFIG.2Care approximations of the frequency response of the compensated amplifiers discussed in this disclosure. As shown inFIG.2C, the upper plot illustrates the magnitude224of the frequency response of the of the control signal to the difference between the sensed signal and reference with the x-axis being frequency in Hertz (Hz) and the y-axis being the magnitude in decibels (dB). The lower plot illustrates the phase226of the frequency response of the control signal to the difference between the sensed signal and reference with the x-axis being frequency in Hertz (Hz) and the y-axis being the phase in degrees. As shown, the compensated amplifier has one pole with a pole frequency fP231and one zero with a zero frequency fZ232. It should be appreciated that poles generally contribute to a decrease in phase while zeros contribute increases in phase. As shown in the upper plot, the magnitude224is substantially constant at value A1for frequencies less than the pole frequency fP231of the compensated amplifier and is substantially constant at value A2for frequencies greater than the zero frequency fZ232. Between the pole frequency fP231and the zero frequency fZ232, the magnitude224decreases from value A1to value A2. The value A1is substantially equal to k times A2, or mathematically: A1=kA2. With the zero frequency fZ232and pole frequency fP231as shown inFIG.2C, the ratio of k is therefore mathematically: k=fZfP. The phase226is shown in a dark solid line in the lower plot ofFIG.2C. The phase226is substantially zero degrees for frequencies below one-tenth the pole frequency, e.g., fP/10, and for frequencies greater than ten times the zero frequency, e.g., 10 fZ. A pole to the system contributes a phase decrease of 45 degrees per decade (e.g., −45°/decade) while a zero contributes phase increases of 45 degrees per decade (e.g., +45°/decade). At one-tenth the pole frequency fP10, the phase226decreases at with a slope of 45 degrees per decade (e.g., −45°/decade). At the pole frequency fP231, the phase is substantially minus 45 degrees (e.g., −45°). The thin dashed line in the lower plot ofFIG.2Cbetween one-tenth the zero frequency fZ10 and ten times the pole frequency 10 fPillustrates the trajectory contributed by the pole of the compensated amplifier, while the dotted line between one-tenth the zero frequency fZ10 and ten times the pole frequency 10 fPillustrates the trajectory contributed by the zero of the compensated amplifier. As shown, between one-tenth the zero frequency fZ10 and ten times the pole frequency 10 fP, the phase226is substantially constant as the decrease contributed by the pole is substantially offset by the increase contributed by the zero. At ten times the pole frequency 10 fP, the phase226increases with a slope of 45 degrees per decade (e.g., +45°/decade). At the zero frequency fZ232, the phase226is also substantially minus 45 degrees (e.g., −45°). At ten times the zero frequency 10 fZ, the phase226has reached zero degrees. The phase margin ϕM233is shown as the difference between zero degrees and the minimum phase value reached. FIG.3is a schematic of one example of a compensated amplifier300in accordance with the teachings of the present invention. It is appreciated that the example compensated amplifier300illustrated inFIG.3may be an example of compensated amplifier200shown inFIG.2A, and that similarly named and numbered elements described above are coupled and function similarly below. As shown in the depicted example, compensated amplifier300is shown as receiving at its input, the sensed signal312and reference signal314, and outputting the control signal322. For the example shown, sensed signal312, reference314, and control signal322are voltages. Compensated amplifier300is also shown including a first amplifier302, a capacitance C1304(e.g., capacitor C1), a second amplifier306, and a resistance R2309(e.g., resistor R2). In the depicted example, first amplifier302may be implemented with a differential amplifier and second amplifier306may be implemented with a differential amplifier. It should be appreciated that the first amplifier302is one example of first amplifier202, second amplifier306is one example of second amplifier206, and capacitance C1304is one example of integrator204ofFIG.2A. As will be discussed further, the addition provided by arithmetic operator208ofFIG.2Ais performed in conjunction with the capacitance C1304, which is coupled to the output of second amplifier306ofFIG.3. In one example, the compensated amplifier300may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. The first amplifier302is shown as a transconductance amplifier with gain G1. The first amplifier302receives the sensed signal312at its non-inverting input and the reference signal314at its inverting input. The output of the first amplifier302is the first error signal IIE316. For the example shown, the sensed signal312and reference signal314are voltages while the first error signal IIE316is a current. The first error signal IIE316ofFIG.3is substantially the difference between the sensed signal312and reference signal314multiplied by the gain G1, or mathematically: I1E_FIG3=G1(VSENSED−VREF) (4) The direction of current for the first error signal IIE316depends on whether the sensed signal312is greater or less than the reference signal314. If the sensed signal312is greater than the reference signal314, the first error signal IIE316is sourced to the capacitance C1304(e.g., the current flows from the output of the first amplifier302to the capacitance C1304). If the reference signal314is greater than the sensed signal312, the first error signal IIE316is sinked to return310(e.g., the current flows to the output of the first amplifier302). The second amplifier306is shown as an operational amplifier with gain A2. First amplifier302and second amplifier306are referenced to return310. The second amplifier306receives the sensed signal312at its non-inverting input and the reference signal314at its inverting input. The output of the second amplifier306is the second error signal V2E320. For the example shown, the sensed signal312, reference signal314, and second error signal V2E320are voltages. The second error signal V2E320ofFIG.3is substantially the difference between the sensed signal312and reference signal314multiplied by the gain A2, or mathematically: V2E_FIG3=A2(VSENSED−VREF) (5) As shown in the illustrated example, resistance R2309is coupled between the output of first amplifier302and return310. In the example, resistance R2309may be used to limit the low frequency gain of first amplifier302. Capacitance C1304is coupled between the output of the first amplifier302and the output of second amplifier306. The voltage across the capacitance C1is the integrated error VINT318. Control signal322is a voltage taken from a node coupled to the output of the first amplifier302, resistance R2309and capacitance C1304. As shown inFIG.3, the control signal322ofFIG.3is substantially the sum of the integrator error VINT318across capacitance C1304and the second error signal V2E320, or mathematically: VCONTROL_FIG3=VINT+V2E_FIG3. (6) In various examples, it is appreciated that the implementation of the compensated amplifier300shown inFIG.3may be utilized to replace the compensated amplifier100shown inFIG.1to remove the external components and integrate the components into an integrated circuit. For the example shown inFIG.1, the control signal116is substantially the sum of the voltage across capacitance C1104and resistance R1106(shown as voltage VZ118). In one example, the values for the gain G1of the first amplifier302, resistance R2309, capacitance C1304and gain A2of the second amplifier306may be selected such that the second error signal V2E320ofFIG.3is substantially equal to the voltage VZ118shown inFIG.1. As such, the compensated amplifier300shown inFIG.3may be utilized to replace the compensated amplifier100shown inFIG.1. For example, the transfer function between the control signal322and the difference between the sensed signal312and reference signal314for the compensated amplifier300ofFIG.3may be substantially: CONTROLSENSED-REF=(A2+G1R2)sA2R2A2+G1R2C1+1SR2C1+1.(7) If gain A2is much less than the product of gain G1and resistance R2309, or mathematically: A2<<G1R2, the approximation of the transfer function between the control signal322and the difference between the sensed signal312and reference signal314for the compensated amplifier300ofFIG.3may be substantially: CONTROLSENSED-REF=G1R2sA2G1C1+1SR2C1+1.(8) If the gain A2and gain G1are selected such that the quotient of gain A2divided by gain G1is substantially equal to the value of resistance R1106ofFIG.1, or mathematically: A1G1=R1, then the frequency of the zero for the compensated amplifier300ofFIG.3may be substantially: fZ_FIG3=12πA2G1C1.(9) As such, the frequency of the zero for the compensated amplifier300ofFIG.3may be selected without the use of an external resistor R1106as shown inFIG.1. As previously mentioned, the resistance value needed for resistor R1106ofFIG.1may be physically unrealistically large to be integrated into an integrated circuit chip. Conversely, if the resistance value selected for resistor R1106is fixed forFIG.1, the resultant capacitance C1104may be physically unrealistically large to be integrated into an integrated circuit chip. By eliminating the need resistance R1106shown inFIG.1, the compensated amplifier300as shown inFIG.3may be integrated in either a hybrid or monolithic integrated circuit in accordance with the teachings of the present invention. FIG.4is a schematic of another example of a compensated amplifier400in accordance with the teachings of the present invention. It is appreciated that the example compensated amplifier400illustrated inFIG.4may be another example of the example compensated amplifier300illustrated inFIG.3or the example compensated amplifier200shown inFIG.2A, and that similarly named and numbered elements described above are coupled and function similarly below. As shown in the depicted example, compensated amplifier400is shown as receiving at its input, the sensed signal412and reference signal414, and outputting the control signal422. For the example shown, sensed signal412, reference signal414, and control signal422are voltages. However, it should be appreciated that in another example, the control signal422may be a current. Compensated amplifier400is also shown including a first amplifier402, a capacitance C1404(e.g., capacitor C1), a second amplifier406, resistance R2409(e.g., resistor R2), a third amplifier411, and resistance R3425(e.g., resistor425). In the depicted example, first amplifier402may be implemented with a differential amplifier, second amplifier406may be implemented with a differential amplifier, and third amplifier411may be implemented with a differential amplifier. It should be appreciated that the first amplifier402is one example of first amplifier202, second amplifier406is one example of second amplifier206, and capacitance C1404is one example of integrator204ofFIG.2A. As will be discussed further detail below, the addition provided by arithmetic operator208ofFIG.2Ais performed at node423inFIG.4. As mentioned, it is appreciated that the example depicted inFIG.4shares many similarities withFIG.3, and that similarly named and numbered elements described above are coupled and function similarly below. At least one difference between the example depicted inFIG.4and the example depicted inFIG.3is the second amplifier406depicted inFIG.4is shown as a transconductance amplifier. In one example, the compensated amplifier400may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. The first amplifier402is shown as a transconductance amplifier inFIG.4with gain G1and is referenced to return410. The first amplifier402receives the sensed signal412at its non-inverting input and the reference signal414at its inverting input. The output of the first amplifier402is the first error signal IIE416. For the example shown, the sensed signal412and reference signal414are voltages while the first error signal IIE416is a current. The first error signal IIE416inFIG.4is substantially the difference between the sensed signal412and reference signal414multiplied by the gain G1, or mathematically: I1E_FIG4=G1(VSENSED−VREF) (10) The direction of current for the first error signal IIE416depends on whether the sensed signal412is greater or less than the reference signal414. If the sensed signal412is greater than the reference signal414, the first error signal IIE416is sourced to the capacitance C1404(e.g., the current flows from the output of the first amplifier402to the capacitance C1404). If the reference signal414is greater than the sensed signal412, the first error signal IIE416is sinked to return410(e.g., the current flows to the output of the first amplifier402). The example second amplifier406inFIG.4is shown as a transconductance amplifier with gain G2and referenced to return410. The second amplifier406receives the sensed signal412at its non-inverting input and the reference signal414at its inverting input. The output of the second amplifier406is the second error signal I2E420. For the example shown, the second error signal I2E420is a current. The second error signal I2E420inFIG.4is substantially the difference between the sensed signal412and reference signal414multiplied by the gain G2, or mathematically: I2E_FIG4=G2(VSENSED−VREF) (11) The direction of current for the second error signal I2E420depends on whether the sensed signal412is greater or less than the reference signal414. If the sensed signal412is greater than the reference signal414, the second error signal I2E420is sourced to node423(e.g., the current flows from the output of the second amplifier406to node423). If the reference signal414is greater than the sensed signal412, second error signal I2E420is sinked to return410(e.g., the current flows from node423to the output of the second amplifier406). Capacitance C1404is coupled between the output of first amplifier402and return410and integrates the first error signal IIE416. Resistance R2409is coupled across capacitance C1404and may be used to limit the low frequency gain of amplifier402. The voltage across the capacitance C1404is the integrated error VINT418. Third amplifier411is shown as a transconductance amplifier with gain G3and referenced to return410. In the depicted example, the third amplifier411provides a voltage to current converter, which is configured to convert the integrated error VINT418into a current, IINT419. The third amplifier411is coupled to receive the integrated error VINT418at its non-inverting input and its inverting input is coupled to return410. The output of the third amplifier406is the integrated error current IINT419, which is a current signal. The integrated error current IINT419ofFIG.4is substantially the integrated error VINT418multiplied by the gain G3, or mathematically: IINT_FIG4=G3VINT. (12) Control signal422is a voltage taken from node423. As shown, the output of the third amplifier411and resistance R3426are coupled to node423. Since the integrated error current IINT419and second error signal I2E420are currents, the summation of the integrated error current IINT419and second error signal I2E420occurs at node423. As shown inFIG.4, the resistance R3426is coupled to the node423and the control signal422ofFIG.4is the voltage drop across resistance R3426, which is substantially equal to the resistance value of resistance R3426multiplied by the sum of the integrated error current IINTand the second error signal I2E420, or mathematically: VCONTROL_FIG4=R3(IINT+I2E_FIG4). (13) Although control signal422is a voltage in the example shown inFIG.4, it is appreciated that another example, the control signal422could also be a current signal in accordance with the teachings of the present invention. FIG.5is a schematic of yet another example of a compensated amplifier500in accordance with the teachings of the present invention. It is appreciated that the example compensated amplifier500illustrated inFIG.5may be another example of the example compensated amplifier400illustrated inFIG.4, or another example of the example compensated amplifier300illustrated inFIG.3or the example compensated amplifier200shown inFIG.2A, and that similarly named and numbered elements described above are coupled and function similarly below. As shown in the depicted example, compensated amplifier500is shown as receiving at its input, the sensed signal512and reference signal514, and outputting the control signal522. For the example shown, sensed signal512, reference signal514, and control signal522are voltages. However, it should be appreciated that in another example, the control signal522may be a current. Compensated amplifier500is also shown including a first amplifier502, a capacitance C1504(e.g., capacitor C1), a second amplifier506, resistance R2509(e.g., resistor R2), and resistance R4521(e.g., resistor R4). In the depicted example, first amplifier502may be implemented with an operational amplifier and second amplifier506may be implemented with a differential amplifier. It should be appreciated that the first amplifier202and integrator204of the example depicted inFIG.2Aare implemented with an operational amplifier integrator inFIG.5with the first amplifier502along with resistance R2509and capacitance C1504. It is also noted that the second amplifier506ofFIG.5is one example of the second amplifier206ofFIG.2A. As will be discussed further, the addition provided by arithmetic operator208ofFIG.2Ais provided inFIG.5by utilizing a resistance R4521that is coupled to the output of the first amplifier502. The control signal522is shown as the voltage at a node523between resistance R4521and an output of second amplifier506. In one example, the compensated amplifier500may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. As mentioned, first amplifier502is shown inFIG.5as an operational amplifier with gain A1. The first amplifier502, capacitance C1504, and resistance R2509are coupled together as an operational amplifier integrator. In particular, the operational amplifier integrator that includes first amplifier502, capacitance C1504, and resistance R2509is coupled to provide a negative output that is proportional to the integral of the difference between the reference signal514and the sensed signal512. For the example shown, the sensed signal512and reference signal514are voltages. As shown in the depicted example, the reference signal514is coupled to the non-inverting input of the first amplifier502while the sensed signal512is coupled to the inverting input of first amplifier502through resistance R2509as shown. Capacitance C1504is coupled between the output of the first amplifier502and the inverting input of first amplifier502. The output of the first amplifier502, which is coupled as an operational amplifier integrator with capacitance C1504and resistance R2509as discussed, is denoted as the negative integrated error, e.g., −VINT518. The first amplifier502is referenced to return510. The second amplifier506is shown as a transconductance amplifier with gain G2. The second amplifier506receives the sensed signal512at its non-inverting input and the reference signal514at its inverting input. The output of the second amplifier506is the second error signal I2E520. For the example shown, the second error signal I2E520is a current. The second amplifier506is referenced to return510. The second error signal I2E520ofFIG.5is substantially the difference between the reference signal514and the sensed signal512multiplied by the gain G2, or mathematically: I2E_FIG5=G2(VREF−VSENSED) (14) The direction of the second error signal I2E520depends on whether the reference signal514or the sensed signal512is greater. If the reference signal514is greater than the sensed signal512, the second error signal I2E520is sourced to resistance R4521(e.g., the direction of current is from the output of the second amplifier to node523). However, if the sensed signal512is greater than the reference signal514, the second error signal I2E520is sinked to return510(e.g., the direction of current is from node523to the output of the second amplifier506). As shown in the example depicted inFIG.5, one end of resistance R4521is coupled to the output of the first amplifier502and capacitance C1504while the other end of resistance R4is coupled to node523. The voltage drop across the resistance R4521is denoted as V2E519and may be the voltage value of the second error signal I2E520. As shown, the resistance R4521acts as a current to voltage converter, which converts the current value of the second error signal I2E520to the voltage V2E519. As such, the voltage V2E519ofFIG.5is the value of resistance R4521multiplied by the current value of the second error signal I2E520, or mathematically: V2E_FIG5=R4I2E. (15) The control signal522is substantially the voltage at node523. In the depicted example, the control signal522ofFIG.5is substantially the sum of the voltage of the integrator error −VINT518and the voltage drop V2E519across resistance R4519, which representative of the second error signal I2E520, or mathematically: VCONTROL_FIG5=−VINT+V2E_FIG5. (16) FIG.6is a schematic of still another example of a compensated amplifier600in accordance with the teachings of the present invention. It is appreciated that the example compensated amplifier600illustrated inFIG.6may be another example of compensated amplifier500illustrated inFIG.5, or another example of compensated amplifier400illustrated inFIG.4, or another example of the example compensated amplifier300illustrated inFIG.3or the example compensated amplifier200shown inFIG.2A, and that similarly named and numbered elements described above are coupled and function similarly below. As shown in the depicted example, compensated amplifier600is shown as receiving at its input, the sensed signal612and reference signal614, and outputting the control signal622. For the example shown, sensed signal612, reference signal614, and control signal622are voltages. However, it should be appreciated that in another example, the control signal622may be a current. Compensated amplifier600is also shown including a first amplifier602, a capacitance C1604(e.g., capacitor C1), a second amplifier606, resistance R2609(e.g., resistor R2), a summing amplifier608, resistance R6624(e.g., resistor R6), and resistance R7627(e.g., resistor R7). In the depicted example, first amplifier602may be implemented with an operational amplifier and second amplifier606may be implemented with an operational amplifier. Similar to the example depicted inFIG.5, it should be appreciated that the first amplifier202and integrator204of the example depicted inFIG.2Aare implemented with an operational amplifier integrator inFIG.6with the first amplifier602along with resistance R2609and capacitance C1604. It is also noted that the second amplifier606ofFIG.6is one example of second amplifier206ofFIG.2A. As will be discussed further, the addition provided by arithmetic operator208ofFIG.2Ais provided inFIG.6by summing amplifier. The control signal622is shown as the output of the summing amplifier608. In one example, the compensated amplifier600may be implemented in an integrated circuit, such as a hybrid or monolithic integrated circuit. As mentioned, the first amplifier602is shown inFIG.6as an operational amplifier with gain A1. The first amplifier602, capacitance C1604, and resistance R2609are coupled together as an operational amplifier integrator. In particular, the first amplifier602, capacitance C1604, and resistance R2609are coupled to provide a negative output that is proportional to the integral of the difference between the reference signal614and the sensed signal612. For the example shown, the sensed signal612and reference signal614are voltages. As shown in the depicted example, reference signal614is coupled to the non-inverting input of the first amplifier602while the sensed signal612is coupled to inverting input of first amplifier602through resistance R2609. Capacitance C1604is coupled between the output of the first amplifier602and the inverting input of first amplifier602. The output of the first amplifier602, which is coupled as an operational amplifier integrator with capacitance C1604and resistance R2609as discussed, is denoted as the negative integrated error, e.g., −VINT618. The first amplifier602is referenced to return610. The second amplifier606is shown as an operational amplifier with gain A2. Resistances R6and R7are coupled as a feedback circuit for the second amplifier606. The sensed signal612is coupled to the inverting input of the second amplifier606through resistance R6624, while the non-inverting input is coupled to receive the reference signal614. Resistance R7627is shown as being coupled between the output of the second amplifier606and its inverting input. The output of the second amplifier606is the second error signal V2E620. For the example shown, the second error signal V2E620is a voltage. The second amplifier606is referenced to return610. The second error signal V2E620ofFIG.6is substantially equal to the difference between the reference signal614and the sensed signal612multiplied by the ratio between resistance R7and R6plus the reference signal614, or mathematically: V2E_FIG6=VREF+(VREF-VSENSED)R7R6.(17) As shown in the depicted example, a summing amplifier608is coupled to receive the negative integrated error, −VINT618, and the second error signal V2E620. In the depicted example, summing amplifier608is configured to generate the control signal622ofFIG.6, which is substantially equal to the sum of the negative integrated error, −VINT618, and the second error signal V2E620, or mathematically: VCONTROL_FIG6=−VINT+V2E_FIG6. (18) FIG.7illustrates an example of a switched mode power converter700in a flyback configuration with a controller762including an example compensated amplifier701in accordance with the teachings of the present invention. It is appreciated that any of the example compensated amplifiers200,201,300,400,500,600discussed above inFIGS.2A-6may be utilized for compensated amplifier701ofFIG.7, and that similarly named and numbered elements described above are coupled and function similarly below. As shown in the example depicted inFIG.7, power converter700includes controller762including an example compensated amplifier701in accordance with an embodiment of the present disclosure. The illustrated power converter700further includes a clamp circuit740, energy transfer element T1742, an input winding744of the energy transfer element T1742, an output winding746of the energy transfer element T1742, a power switch SP748, an input return747, an output rectifier752, an output capacitor CO754, an output return759, and an output sense circuit760. As shown the depicted example, controller762includes compensated amplifier701, which is coupled to receive a reference signal REF714and a sensed signal712from the sense circuit760. In the depicted example, the sensed signal712is a feedback signal representative of the output of the power converter700. Compensated amplifier701is configured to generate a control signal722in response to the sensed signal712and the reference signal REF714. A drive modulator764is coupled to generate a drive signal DR765to control switching of the power switch SP748in response to the control signal722received from compensated amplifier701. Further shown inFIG.7are an input voltage VIN738, a drain current ID750, an output voltage VO753, an output current IO755, and an output quantity UO756. In the illustrated example, the power converter700is shown as having a flyback topology. Further, the input of power converter700is galvanically isolated from the output of the power converter700, such that input return747is galvanically isolated from output return759. Since the input and output of power converter700are galvanically isolated, there is no direct current (dc) path across the isolation barrier of energy transfer element T1742, or between input winding744and output winding746, or between input return747and output return759. It is appreciated that other known topologies and configurations of power converters may also benefit from the teachings of the present disclosure. In operation, the power converter700provides output power to a load758from an unregulated input voltage VIN738. In one embodiment, the input voltage VIN738is a rectified and filtered ac line voltage. In another embodiment, the input voltage VIN738is a dc input voltage. The input voltage VIN738is coupled to the energy transfer element742. In some examples, the energy transfer element742may be a coupled inductor, transformer, or an inductor. The energy transfer element742is shown as including two windings, input winding744(also referred to as a primary winding) and output winding746(also referred to as a secondary winding). However, in other examples the energy transfer element742may have three or more windings. As shown, the input winding744of the energy transfer element T1742is further coupled to the power switch SP748and the power switch SP748is further coupled to input return747. Coupled across the input winding744is the clamp circuit740. The clamp circuit740limits the maximum voltage on the power switch SP748. Output winding746is coupled to the output rectifier752, which is exemplified as a diode in the depicted example. However, in another example, the output rectifier may be exemplified as a transistor used as a synchronous rectifier. Output capacitor CO754is shown as being coupled to the output rectifier752and the output return759. The power converter700further includes circuitry to regulate the output quantity UO756, which in one example may be the output voltage VO753, output current IO755, or a combination of the two. The output sense circuit760is configured to sense the output quantity UO756to provide the sensed signal712, which is representative of the output of the power converter700, to the compensated amplifier701of controller762as shown. As discussed in the various examples above, compensated amplifier701is configured to generate the control signal722in response to the sensed signal712and the reference signal REF714. In one example, the controller762may be formed as part of an integrated circuit that is manufactured as either a hybrid or monolithic integrated circuit. In one example, the power switch SP748may also be integrated in a single integrated circuit package with the controller762. Further, it should be appreciated that both the controller762and power switch SP748need not be included in a single package and may be implemented in separate packages or a combination of combined/separate packages. It should be appreciated that the controller762may include a primary-side controller referenced to input return747and a secondary-side controller referenced to output return759with galvanic isolation between the primary-side controller and secondary-side controller. In one example, the power switch SP748may be a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT a gallium nitride (GaN) based transistor, or a silicon carbide (SiC) based transistor. In another example the power switch may be a is a cascode switch including a normally-on first switch and a normally-off second switch coupled together in a cascode configuration. The first switch may generally be a GaN or SiC based transistor while the second switch may be a MOSFET, BJT, or IGBT. In one example, the controller762may be coupled to receive a current sense signal representative of the drain current ID750of the power switch SP748in addition to the sensed signal712to generate the drive signal DR765. In various examples, the drive modulator764of controller762is configured to generate the drive signal DR765to the power switch SP748in response to the control signal722to control various switching parameters of the power switch SP748to control the transfer of energy from the input of the power converter700to the output of the power converter700through the energy transfer element742. Example of such parameters include switching frequency (or switching period), duty cycle, on-times, off-times, or varying the number of pulses per unit time of the power switch SP748. In addition, the power switch SP748may be controlled by driver modulator764such that the drive signal DR765has a fixed switching frequency or a variable switching frequency. The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention. Although the present invention is defined in the claims, it should be understood that the present invention can alternatively be defined in accordance with the following examples: Example 1. A compensated amplifier for use in a power converter controller, comprising a first amplifier coupled to receive a sensed signal and a reference signal and configured to generate a first error signal in response to the sensed signal and the reference signal; a second amplifier coupled to the first amplifier and configured to generate a second error signal in response to the sensed signal and the reference signal; an integrator coupled to the first amplifier and configured to generate an integrated error signal in response to the first error signal; and an arithmetic operator coupled to the integrator and to the second amplifier, wherein the arithmetic operator is configured to generate a control signal in response to the integrated error signal and the second error signal. Example 2. The compensated amplifier of example 1, wherein an input of the first amplifier and an input of the second amplifier are coupled together to receive the sensed signal and the reference signal to generate the first error signal and the second error signal, respectively, in response to the sensed signal and the reference signal. Example 3. The compensated amplifier of example 1 or 2, wherein an input of the first amplifier is coupled to receive the sensed signal and the reference signal to generate the first error signal in response to the sensed signal and the reference signal and the second amplifier is coupled to an output of the first amplifier to generate the second error signal in response to the sensed signal and the reference signal. Example 4. The compensated amplifier of example 1 to 3, wherein the first amplifier comprises a first transconductance amplifier. Example 5. The compensated amplifier of example 1 to 4, wherein the second amplifier comprises a differential amplifier, wherein the integrator comprises a capacitor coupled between an output of the first amplifier and an output of the second amplifier, and wherein the compensated amplifier further comprises a resistor coupled between the output of the first amplifier and a return. Example 6. The compensated amplifier of example 1 to 5, wherein the second amplifier comprises a second transconductance amplifier, wherein the integrator comprises a capacitor coupled between an output of the first amplifier and a return, and wherein the compensated amplifier further comprises a first resistor coupled between the output of the first amplifier and the return. Example 7. The compensated amplifier of example 1 to 6, wherein the compensated amplifier further comprises a third amplifier having an input coupled to the capacitor and an output coupled to the arithmetic operator, wherein the third amplifier comprises a third transconductance amplifier; and a second resistor coupled between the output of the third amplifier and the return. Example 8. The compensated amplifier of example 1 to 7, wherein the compensated amplifier includes an operational amplifier integrator having a first input coupled to receive the sensed signal, a second input coupled to receive the reference signal, and an output configured to provide the integrated error signal. Example 9. The compensated amplifier of example 1 to 8, wherein the operational amplifier integrator comprises the first amplifier, wherein the first amplifier comprises a first operational amplifier having the first input coupled to receive sensed signal through a first resistor, and the second input coupled to receive the reference signal, wherein an output of the first operational amplifier is coupled to the output of the operational amplifier integrator; and the integrator, wherein the integrator comprises a capacitor coupled between the output of the first operational amplifier and the first input of the first operational amplifier. Example 10. The compensated amplifier of example 1 to 9, wherein the second amplifier comprises a transconductance amplifier, wherein compensated amplifier further comprises a second resistor coupled between the output of the first operational amplifier and an output of the transconductance amplifier, and wherein the control signal is taken from a node between the second resistor and the output of the transconductance amplifier. Example 11. The compensated amplifier of example 1 to 10, wherein the second amplifier comprises a second operational amplifier, wherein the second operational amplifier incudes a first input coupled to receive the sensed signal, wherein the second operational amplifier incudes a second input coupled to receive the reference signal, and wherein an output of the second operational amplifier is coupled to the first input of the second operational amplifier. Example 12. The compensated amplifier of example 1 to 11, wherein the arithmetic operator comprises a summing amplifier having a first input coupled to the output of the first operational amplifier, wherein the summing amplifier has a second input coupled to the output of the second operational amplifier, and wherein the summing amplifier has an output coupled to generate the control signal. Example 13. A controller for use in a power converter, comprising: a driver modulator configured to generate a drive signal in response to a control signal to control switching of a power switch of the power converter to regulate transfer of energy from an input of the power converter to an output of the power converter; and a compensated amplifier configured to generate the control signal in response to a reference signal and a sensed signal representative of the output of the power converter, wherein the compensated amplifier comprises a first amplifier coupled to receive the sensed signal and the reference signal and configured to generate a first error signal in response to the sensed signal and the reference signal; a second amplifier coupled to the first amplifier and configured to generate a second error signal in response to the sensed signal and the reference signal; an integrator coupled to the first amplifier and configured to generate an integrated error signal in response to the first error signal; and an arithmetic operator coupled to the integrator and the second amplifier and configured to generate a control signal in response to the integrated error signal and the second error signal. Example 14. The controller of example 13, wherein an input of the first amplifier and an input of the second amplifier are coupled together to receive the sensed signal and the reference signal to generate the first error signal and the second error signal, respectively, in response to the sensed signal and the reference signal. Example 15. The controller of example 13 or 14, wherein an input of the first amplifier is coupled to receive the sensed signal and the reference signal to generate the first error signal in response to the sensed signal and the reference signal, and wherein an input of the second amplifier is coupled to an output of the first amplifier to generate the second error signal in response to the sensed signal and the reference signal. Example 16. The controller of example 13 to 15, wherein the first amplifier comprises a first transconductance amplifier. Example 17. The controller of example 13 to 16, wherein the second amplifier comprises a differential amplifier, wherein the integrator comprises a capacitor coupled between an output of the first amplifier and an output of the second amplifier, wherein the compensated amplifier further comprises a resistor coupled between the output of the first amplifier and a return. Example 18. The controller of example 13 to 17, wherein the second amplifier comprises a second transconductance amplifier, wherein the integrator comprises a capacitor coupled between an output of the first amplifier and a return, and wherein the compensated amplifier further comprises a first resistor coupled between the output of the first amplifier and the return. Example 19. The controller of example 13 to 18, wherein the compensated amplifier further comprises: a third amplifier having an input coupled to the capacitor and an output coupled to the arithmetic operator, wherein the third amplifier comprises a third transconductance amplifier; and a second resistor coupled between the output of the third amplifier and the return. Example 20. The controller of example 13 to 19, wherein the compensated amplifier includes an operational amplifier integrator having a first input coupled to receive the sensed signal, a second input coupled to receive the reference signal, and an output configured to generate the integrated error signal. Example 21. The controller of example 13 to 20, wherein the operational amplifier integrator comprises: the first amplifier, wherein the first amplifier comprises a first operational amplifier having the first input coupled to receive sensed signal through a first resistor, and having the second input coupled to receive the reference signal, wherein an output of the first operational amplifier is coupled to the output of the operational amplifier integrator; and the integrator, wherein the integrator comprises a capacitor coupled between the output of the first operational amplifier and the first input of the first operational amplifier. Example 22. The controller of example 13 to 21, wherein the second amplifier comprises a transconductance amplifier, wherein compensated amplifier further comprises a second resistor coupled between the output of the first operational amplifier and an output of the transconductance amplifier, wherein the control signal is taken from a node between the second resistor and the output of the transconductance amplifier. Example 23. The controller of example 13 to 22, wherein the second amplifier comprises a second operational amplifier, wherein the second operational amplifier incudes a first input coupled to receive the sensed signal, wherein the second operational amplifier incudes a second input coupled to receive the reference signal, and wherein an output of the second operational amplifier is coupled to the first input of the second operational amplifier. Example 24. The controller of example 13 to 23, wherein the arithmetic operator comprises a summing amplifier having a first input coupled to the output of the first operational amplifier, wherein the summing amplifier has a second input coupled the output of the second operational amplifier, wherein the summing amplifier has an output coupled to generate the control signal. | 66,293 |
11942901 | DETAILED DESCRIPTION OF SOME EMBODIMENTS The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. When an amplifier is turned on, the active amplification devices within the amplifier turn on and hence some level of self-heating of the amplifier is realized such that a temperature at and/or around the amplifier may increase. In some cases, an amplifier may have multiple amplification stages which may each experience some level of self-heating. This ‘self-heating’ effect may result in a decrease of gain of the amplifier and/or gain variation over time which may cause degradation of the error vector magnitude (EVM) of the amplifier (which is a measure of linearity). For amplifiers that are pulsed and are used in modulated systems (e.g., with peak-to-average signals), the gain variation over time may be even further degraded, which may result in a degraded dynamic EVM (DEVM). EVM degradation for a 4 ms pulse has been shown to be directly related to gain decrease over the pulse width. Some general mobile power amplifiers may not be suitable for use with controllers that can shape the bias versus time to compensate for self-heating of transistors. Gallium arsenide (GaAs) power amplifiers in particular may not be capable of supporting complex bias circuits to offset gain roll-off versus time. Passive circuits requiring no analog processing can help compensate for the gain roll-off versus time. FIG.1illustrates a comparison graph100showing an ideal gain plot and a practical gain plot. A first plot102provides ideal gain performance: when the amplifier is turned on, the ideal amplifier immediately reaches a peak gain value and maintains the peak gain value indefinitely. In comparison, a second plot104provides an example of practical gain performance: when the amplifier turns on, there is a period of delay before the amplifier ramps up to a peak gain value and gradually decreases from the peak gain value over time. Practical gain performance as illustrated by the second plot104creates various instances of error106, or in other words, differences from the ideal gain performance. Error106is measured inFIG.1beyond a “tref” (e.g., beginning of preamble) point. It is advantageous to minimize the error as much as possible for an amplifier. Some embodiments described herein provide devices and/or methods for reducing gain error. In some embodiments, a circuit for a power amplifier may be configured to self-correct and/or otherwise respond to heating at an amplifier network of the power amplifier. Moreover, a power amplifier may include various devices configured to detect heating at and/or near the amplifier network. Responses to heating may be performed automatically in response to detected heating. Some embodiments may be configured for use with multi-stage (e.g., two or more amplification stages) while some embodiments may be configured for use with single-stage amplifiers as well or alternatively. FIG.2provides an illustration of a gain compensation circuit200in accordance with some embodiments. The circuit200may include an amplifier network201including a first-stage amplifier202, a second-stage amplifier212, and/or a third-stage amplifier222. A first resistor204, second resistor214, and/or first transistor206may be included in a bias network203configured to bias the first-stage amplifier202with a reference current (“Iref”). The first resistor204may be coupled to the second resistor214(e.g., at a first node208) and/or the second resistor214may be coupled to the first transistor206(e.g., at a second node218). In some embodiments, the emitter and/or collector of the first transistor206may be coupled to the base of the first transistor206such that the first transistor206may be configured to act a bias diode. The circuit200may further include a second transistor216and/or a third transistor226. Together, the second transistor216and third transistor226may form a current mirror210and may draw some amount of the reference current. The current value of the reference current may be determined by the size of the current mirror210and/or the respective resistance values of the first resistor204, second resistor214, a third resistor224coupled to the second transistor216(and/or coupled to the second resistor214and/or first transistor206at the second node218), and/or a fourth resistor234coupled to the third transistor226and/or the second transistor216at a third node228. The fourth resistor234may also or alternatively be coupled to the first resistor204and/or the second resistor214at the first node208. In some embodiments, the third transistor226may be positioned in the circuit200as closely as possible to one of the amplifiers (e.g., the second-stage amplifier212) such that the third transistor226may be thermally linked to at least one of the amplifiers. The term “thermally linked” is used herein according to its broad and ordinary meaning and may refer to a physical and/or non-physical connection between multiple devices wherein heating at one of the devices causes heating at another of the devices. Similarly, the term “thermally isolated” is used herein according to its broad and ordinary meaning and may refer to an absence of a physical and/or non-physical connection between multiple devices wherein heating at one of the devices does not cause heating at another of the devices. While the third transistor226is shown inFIG.2as being in close proximity to and/or thermally linked to the second-stage amplifier212, the third transistor226may be additionally or alternatively positioned in close proximity to and/or thermally linked to the first-stage amplifier202and/or the third-stage amplifier222. In some embodiments, heating (e.g., self-heating as a result of turning on) of the amplifier network201(e.g., at the second-stage amplifier212) may cause heating of the third amplifier226. When a temperature of the third amplifier226increases, it may create a temperature difference (e.g., delta) between the third amplifier226and the second amplifier216. The second transistor216may be positioned such that the second transistor216may be thermally isolated from the second-stage amplifier212. For example, the second transistor216may be positioned a suitable distance from the second-stage amplifier212such that any heating of the second-stage amplifier212may have a null and/or minimal impact on the second transistor216. In this way, the second transistor216may sense an ambient temperature at and/or around the circuit200and/or may not be impacted by heating at the amplifier network201. Accordingly, temperature increases at the amplifier network201may directly affect temperature of the third transistor226but not the second transistor216. The proximity between the third transistor226and the second-stage amplifier212(and/or first-stage amplifier202and/or third-stage amplifier222) may be process-dependent. For example, there may be a process limitation for how close one transistor can be to another. The third transistor226and second-stage amplifier212(and/or first-stage amplifier202and/or third-stage amplifier222) may be as close as possible based on the process limitations. For example, the proximity of devices may be limited to no closer than approximately three microns. Accordingly, the third transistor226may be situated approximately three microns from the second-stage amplifier212. In some embodiments, an array of amplifiers may be included in the circuit200and/or the third transistor226may be situated between multiple amplifiers (e.g., between the second-stage amplifier212and the third-stage amplifier222) to increase the amount of heat sensed at the third transistor226. When the second-stage amplifier212(or other amplifier of the amplifier network201) experiences some level of self-heating, the third transistor226may likewise heat up due at least in part to the proximity of the third transistor226to the second-stage amplifier212. As a result of heating at the second-stage amplifier212and/or the third transistor226, the current mirror210may draw less reference current. Due at least in part to the current mirror210drawing less current, a higher level of current may be drawn by the first transistor206, which may accordingly boost a current value and/or gain value of the first-stage amplifier202. In some embodiments, an amount of gain increase at the first-stage amplifier202may be approximately equal to an amount of gain decrease at the second stage amplifier212and/or at the third-stage amplifier222. The third resistor224may be coupled to the emitter or collector of the second transistor216and may be configured to reduce the base voltage (Vbe) across the second transistor216. For example, as a result of temperature increase at the third transistor226, the third resistor224may facilitate a reduction of Vbe across the second transistor216and/or the third transistor226. The fourth resistor234may be coupled to the emitter or collector of the third transistor226and/or may be coupled to the base of the second transistor216. In some embodiments, the fourth resistor234may be configured to set an amount of current consumed and/or drawn by the current mirror210. In some cases, the lower the amount of power dissipated by the circuit200, the better the circuit200may be able to sense temperature changes in the amplifier network201. When the second-stage amplifier212(or other amplifier(s)) heats up, feedback may be generated in the circuit200to cause the current to rise in the first-stage amplifier202(and/or other amplifier(s)). With the rise in current, the gain of the circuit200may increase as well. The gain at the second-stage amplifier212may decrease with increase in heat. Therefore, by increasing the current and/or gain at the first-stage amplifier202, the net gain delta over time of the amplifier network may be approximately zero. The second transistor216may be thermally isolated from the amplifier network (e.g., situated a sufficient distance from the amplifier network that heating from the amplifiers causes minimal impact at the second transistor216) such that the second transistor216is configured to sense the ambient temperature of the semiconductor die. In some embodiments, the second transistor216and third transistor226may share a common node. For example, the base of the second transistor216may be coupled to a fifth resistor244and the base of the third transistor226may be coupled to a sixth resistor254. The fifth resistor244and/or sixth resistor254may be coupled at the third node228. Accordingly, the second transistor216and the third transistor226may have an equal current. If the temperature at the second transistor216and the third transistor226is the same, an equal voltage may be applied to the second transistor216and the third transistor226at the third node228. As the third transistor226heats up, the base voltage of the third transistor226may decrease. Accordingly, the voltage and current at the second transistor216may decrease as well. As a result, less current may be drawn at the second resistor214. The voltage on the collector of the first transistor206may increase which may in turn increase the voltage at the base of the second transistor216. The increase of voltage at the first transistor206may cause an increase of bias voltage and/or current at the first-stage amplifier202. While the amplifier network201inFIG.2includes three stages/amplifiers, the amplifier network201may alternatively include a single stage, two stages, or more than three stages. The level of compensation required to achieve a net zero (or as close as possible to net zero) gain may be different for different numbers of stages of the amplifier network201. For example, for an amplifier network201including a single stage, the required compensation for the circuit200may be compensating for only the single stage. Accordingly, less feedback may be generated for a single-stage amplifier network201. The amount of bias may not be increased for single-stage and/or two-stage amplifier networks201. Moreover, for a single-stage amplifier network201, the third transistor226(or other device) may sense the temperature of the single amplifier. The third transistor226may be configured and/or situated to sense temperature at any stage of the amplifier network201. In some cases, each successive stage of an amplifier network201may have a temperature increase because each successive stage may have an increasing periphery and may accordingly generate more heat. Moreover, by sensing temperature at a successive stage (e.g., the second-stage amplifier212and/or the third-stage amplifier222), gain compensation may be performed by changing gain values at the first-stage amplifier202. Changing gain at the first-stage amplifier202may be relatively simpler than changing gain at successive stages due to the linearity of the amplifier network201. The current and/or gain of the first-stage amplifier202may advantageously be changed without greatly affecting linearity. Successive stages may be biased down to a greater extent as far as current density in comparison to the first-stage amplifier202because the successive stages may be larger. In some cases, the second-stage amplifier212may have a more consistent temperature rise independent of output power than other stages. Accordingly, the second-stage amplifier212may provide a desirable balance between temperature increase and thermal dissipation without being situated within the control loop. FIG.3provides another circuit300for gain correction in accordance with some embodiments. In some embodiments, a first resistor304and/or a second resistor314may be configured to set a current difference for the circuit300. The circuit300may include a control transistor306configured to sense an ambient temperature of the circuit300. In some embodiments, the control transistor306may be configured to provide approximately 4× temperature sensing. The circuit300may additionally or alternatively comprise a second transistor316, which may be coupled in parallel to the control transistor306and/or in series with the second resistor314. FIG.4provides another circuit400for gain correction in accordance with some embodiments. In some embodiments, the circuit300and the circuit400may be combined/coupled into a single schematic. The circuit400may include a sensing transistor406configured to sense changes in temperature from other devices of the circuit400and/or other circuits near the circuit400. FIG.5provides a comparison graph between conventional devices and devices in accordance with one or more embodiments herein. Embodiments described herein (represented by a first plot505) may advantageously provide an increase in gain (e.g., an approximately 0.15 dB increase for an increase of approximately 12 degrees) over conventional devices. In some cases, gain compensation may have an effect of “softening” the turn-on characteristics of a power amplifier. Gain compensation may add a thermal time constant to a bias circuit. There may be a trade-off between 90 μs (and 300 μs) and 4 ms EVM performance. It may be desirable to determine a set point that provides a performance compromise. FIG.6provides several gain versus time plots over a 4 ms burst in accordance with some embodiments described herein. Each plot may represent a different compensation amount setting. A first plot605represents a conventional (e.g., uncompensated) circuit while other plots, including a second plot610, may represent a circuit with temperature compensation features as described herein, which may provide improvements in gain over the 4 ms burst. The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 19,290 |
11942902 | DETAILED DESCRIPTION OF SOME EMBODIMENTS The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. Referring toFIG.1, one or more features of the present disclosure generally relate to a wireless system or architecture50having an amplification system52. In some embodiments, the amplification system52can be implemented as one or more devices, and such device(s) can be utilized in the wireless system/architecture50. In some embodiments, the wireless system/architecture50can be implemented in, for example, a portable wireless device. Examples of such a wireless device are described herein. FIG.2shows that the amplification system52ofFIG.1typically includes a radio-frequency (RF) amplifier assembly54having one or more power amplifiers (PAs). In the example ofFIG.2, three PAs60a-60care depicted as forming the RF amplifier assembly54. It will be understood that other numbers of PA(s) can also be implemented. It will also be understood that one or more features of the present disclosure can also be implemented in RF amplifier assemblies having other types of RF amplifiers. In some embodiments, the RF amplifier assembly54can be implemented on one or more semiconductor die, and such die can be included in a packaged module such as a power amplifier module (PAM) or a front-end module (FEM). Such a packaged module is typically mounted on a circuit board associated with, for example, a portable wireless device. The PAs (e.g.,60a-60c) in the amplification system52are typically biased by a bias system56. Further, supply voltages for the PAs are typically provided by a supply system58. In some embodiments, either or both of the bias system56and the supply system58can be included in the foregoing packaged module having the RF amplifier assembly54. In some embodiments, the amplification system52can include a matching network62. Such a matching network can be configured to provide input matching and/or output matching functionalities for the RF amplifier assembly54. For the purpose of description, it will be understood that each PA (60) ofFIG.2can be implemented in a number of ways.FIGS.3A-3Eshow non-limiting examples of how such a PA can be configured.FIG.3Ashows an example PA having an amplifying transistor64, where an input RF signal (RF_in) is provided to a base of the transistor64, and an amplified RF signal (RF_out) is output through a collector of the transistor64. FIG.3Bshows an example PA having a plurality of amplifying transistors (e.g.,64a,64b) arranged in stages. An input RF signal (RF_in) is provided to a base of the first transistor64a, and an amplified RF signal from the first transistor64ais output through its collector. The amplified RF signal from the first transistor64ais provided to a base of the second transistor64b, and an amplified RF signal from the second transistor64bis output through its collector to thereby yield an output RF signal (RF_out) of the PA. In some embodiments, the foregoing example PA configuration ofFIG.3Bcan be depicted as two or more stages as shown inFIG.3C. The first stage64acan be configured as, for example, a driver stage; and the second stage64bcan be configured as, for example, an output stage. FIG.3Dshows that in some embodiments, a PA can be configured as a Doherty PA. Such a Doherty PA can include amplifying transistors64a,64bconfigured to provide carrier amplification and peaking amplification of an input RF signal (RF_in) to yield an amplified output RF signal (RF_out). The input RF signal can be split into the carrier portion and the peaking portion by a splitter. The amplified carrier and peaking signals can be combined to yield the output RF signal by a combiner. FIG.3Eshows that in some embodiments, a PA can be implemented in a cascode configuration. An input RF signal (RF_in) can be provided to a base of the first amplifying transistor64aoperated as a common emitter device. The output of the first amplifying transistor64acan be provided through its collector and be provided to an emitter of the second amplifying transistor64boperated as a common base device. The output of the second amplifying transistor64bcan be provided through its collector so as to yield an amplified output RF signal (RF_out) of the PA. In the various examples ofFIGS.3A-3E, the amplifying transistors are described as bipolar junction transistors (BJTs) such as heterojunction bipolar transistors (HBTs). It will be understood that one or more features of the present disclosure can also be implemented in or with other types of transistors such as field-effect transistors (FETs). FIG.4shows that in some embodiments, the amplification system52ofFIG.2can be implemented as a high-voltage (HV) power amplification system70. Such a system can include an HV power amplifier assembly54configured to include HV amplification operation of some or all of the PAs (e.g.,60a-60c). As described herein, such PAs can be biased by a bias system56. In some embodiments, the foregoing HV amplification operation can be facilitated by an HV supply system58. In some embodiments, an interface system72can be implemented to provide interface functionalities between the HV power amplifier assembly54and either or both of the bias system56and the HV supply system58. FIG.5shows that in some embodiments, a power amplification system500can be implemented as a cascode amplifier510with an adjustable bias signal. The cascode amplifier510includes a first transistor511of a common emitter (CE) stage (also referred to as an RF stage). The emitter of the first transistor511is coupled to a ground voltage. The base of the first transistor511is coupled, via a capacitor561and an input matching component581to an RF input. The base of the first transistor511is also coupled to a biasing component520that biases the common emitter stage. The biasing component520provides a CE biasing signal, e.g., a bias voltage or a bias current, that biases the first transistor511. The CE biasing signal may be powered by voltage from a battery (Vbatt) that is at least partially fed to the base of the first transistor511when a CE bias component521(as controlled by a bias controller530) biases a CE bias transistor541. The CE biasing signal may have a fixed value (e.g., a voltage or a current with a fixed value). The collector of the first transistor511is coupled to the emitter of a second transistor512of a common base stage. The cascode amplifier510includes a second transistor512of a common base (CB) stage (also referred to as a cascode stage). The emitter of the second transistor512is coupled to the collector of the first transistor511. The collector of the second transistor512is coupled, via an inductor570, to a supply voltage (Vcc). An RF output (an amplified version of the RF input) is output from the collector of the second transistor512. The RF output passes through an output matching component582(which may also perform bandpass filtering) and can be transmitted via an antenna590. The base of the second transistor512is coupled, via a capacitor562, to the ground voltage. The base of the second transistor512is also coupled to the biasing component520that biases the common base stage. The biasing component520provides a CB biasing signal, e.g., a bias voltage or a bias current, that biases the second transistor512. The CB biasing signal may be powered by voltage from the battery (Vbatt) that is at least partially fed to the base of the second transistor512when a CB bias component522(as controlled by the bias controller530) biases a CB bias transistor542. The strength of the CB biasing signal provided by the CB bias component522may be variable (or adjustable) depending on a number of factors as described further below. The common base stage of a cascode power amplifier in a bipolar process may introduce an increase in the effective minimum Vce or knee voltage of the amplifying device. The minimum Vce may reduce the signal swing for the amplifier which may ultimately reduce the amplifier efficiency. As the saturation point of the amplifier may be a function of the BE (base-emitter) and BC (base-collector) junctions within the second transistor512, as well as parasitic resistance terms, the minimum Vce may also demonstrate a sensitivity to temperature and device current. The impact of this minimum Vce may be more significant at lower output powers as the system supply voltage (Vcc) is decreased towards the minimum Vce voltage. Thus, as mentioned above, the biasing component520may adjust the CB biasing signal (e.g., a cascode bias voltage) to improve or optimize performance of the power amplification system500. For example, the biasing component520may adjust the CB biasing signal such that overhead for temperature and high current is reduced at lower current and alternate temperature conditions. In one embodiment, the CB bias signal is a fixed voltage, selected to support worst case conditions. However, this may result in excessive margin under nominal and low power conditions which reduces the efficiency of the power amplification system500. Thus, in other embodiments, the CB bias signal provided by the biasing component520is a variable voltage. In some implementations, the bias controller530generates a reference voltage and feeds the reference voltage to the CB bias component522. Based on reference voltage, the CB bias component522, using the battery voltage and the CB bias transistor542, generates the CB bias signal and provides the CB bias signal to the base of the second transistor512. In some implementations, the CB bias component522is a buffer amplifier. The reference voltage generated by the bias controller530may be adjusted based upon temperature and output power such that the minimum Vce variation is compensated to improve performance. For example, at high power, the BE junction voltage may be greater than at lower power, and the biasing component520may provide a CB bias signal with a higher voltage to prevent saturation of the common emitter stage. As another example, at lower output power, the BE junction voltage may be less than at higher power, and the biasing component520may provide a CB bias signal with a lower voltage. Similarly, with respect to temperature, the BE junction voltage and saturation voltage may increase with decreased temperature, and the biasing component520may provide a CB bias signal with a higher voltage in low temperature conditions relative to high temperature conditions. To reduce collector current in a low power mode (LPM), the supply voltage (Vcc) may be reduced. However, the common base stage may saturate if the supply voltage is too low without also lowering the voltage of the CB bias signal. However, the common emitter stage of the cascode power amplifier may saturate if a CB bias signal with too low a voltage is applied. Thus, as described above, the biasing component520may adjust the voltage of the CB bias signal under various power and temperature conditions. In one embodiment, the biasing component520includes a temperature sensor531that detects temperature. For example, the biasing component520may include a thermistor. In some implementations, as shown inFIG.5, the bias controller530includes a temperature sensor531. In some implementations, the bias controller530receives a temperature signal (e.g., via an input terminal) indicative of the temperature of the power amplification system500. In one embodiment, the biasing component520includes a power sensor532that detects a power condition of the power amplification system500. The power condition can be a power mode of the power amplification system500, e.g. a default mode or a lower power mode. The power condition can be an output power of the power amplification system500. The power condition can be the supply voltage applied to the cascode amplifier510. For example, the biasing component520may be coupled to RF output (e.g., via a coupler) or to the supply voltage (Vcc) to determine to determine the power mode, the output power, or the supply voltage. In some implementations, as shown inFIG.5, the bias controller530includes a power sensor532. In some implementations, the bias controller530receives a power signal (e.g., via an input terminal) indicative of the power condition of the power amplification system500. In some implementations, the biasing component520determines a voltage (or other characteristic) of the CB biasing signal using an analog circuit that outputs a particular bias voltage at certain temperatures and/or power conditions. In some implementations, the biasing component520determines a voltage (or other characteristic) of the CB biasing signal using a digital circuit that stores a table533of bias voltage values in respective association with a plurality of temperature values and/or power condition indicia. Accordingly,FIG.5shows a power amplification system500including a first transistor511having a base coupled to a radio-frequency input and a second transistor512having an emitter coupled to a collector of the first transistor511and a collector coupled to a radio-frequency output. The power amplification system further includes a biasing component520configured to apply a fixed biasing signal (e.g., a bias signal with a fixed voltage) to the base of the first transistor511and to apply an adjustable biasing signal (e.g., a bias signal with an adjustable voltage) to the base of the second transistor512. As described above, the biasing component520can be configured to apply the adjustable biasing signal based on a temperature of the power amplification system500. The biasing component520can apply a higher adjustable biasing signal (e.g., a bias signal with a higher voltage) in response to a lower temperature and a lower adjustable biasing signal (e.g. a bias signal with a lower voltage) in response to a higher temperature. As also described above, the biasing component520can be configured to apply the adjustable biasing signal based on a power condition of the power amplification system. The biasing component520can apply a higher adjustable biasing signal in response to a higher output power and lower adjustable biasing signal in response to a lower output power. FIG.6shows example plots of the gain of a power amplification system (e.g, the power amplification system500ofFIG.5) as a function of supply voltage (Vcc) for various common base bias voltages. The left half ofFIG.6shows the result of the common base stage saturation point voltage decreasing with lower common base bias voltage. The right half ofFIG.6(particularly the two lowest lines) shows the result of the common emitter stage saturating at low cascode bias voltages. FIG.7shows example plots of the output power of a power amplification system (e.g, the power amplification system500ofFIG.5) as a function of supply voltage (Vcc) for various common base bias voltages. The left half ofFIG.6shows that a lower common base bias voltage supports increased linear power at lower supply voltage conditions. The right half ofFIG.7(particularly the two lowest lines) shows that a saturated common emitter stage limits power independent of supply voltage. FIG.8shows an example plot of the AMAM (amplitude-modulation to amplitude-modulation) response of a power amplification system (e.g. the power amplification system500ofFIG.5) for various common base bias voltages. The example plot shows the calculated gain plotted against the measured output power. As the compression characteristic of a cascode amplifier may be a combination of the common base stage compression (e.g., as a result of saturation) as well as the common base stage compression (e.g., as a result of saturation), the gain characteristic of the amplifier can be impacted through the common base bias voltage applied to the cascode amplifier. Different modulation standards may be optimized under different compression characteristics and the common base bias voltage can be adjusted to compensate and improve performance for a given modulation standard and switched between multiple modulation standards. Thus, in some implementations, the biasing component520ofFIG.5is configuration to apply to the adjustable biasing signal (e.g., to the second transistor512) based on a modulation standard of the radio-frequency input. FIG.9shows that in some embodiments, some or all of a power amplification system (e.g., the power amplification system500ofFIG.5) can be implemented in a module. Such a module can be, for example, a front-end module (FEM). In the example ofFIG.9, a module300can include a packaging substrate302, and a number of components can be mounted on such a packaging substrate. For example, an FE-PMIC component304, a power amplifier assembly306, a match component308, and a duplexer assembly310can be mounted and/or implemented on and/or within the packaging substrate302. The power amplifier assembly306may include a cascode system307such as that shown inFIG.5. Other components such as a number of SMT devices314and an antenna switch module (ASM)312can also be mounted on the packaging substrate302. Although all of the various components are depicted as being laid out on the packaging substrate302, it will be understood that some component(s) can be implemented over other component(s). In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc. FIG.10depicts an example wireless device400having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can be generally depicted by a dashed box300, and can be implemented as, for example, a front-end module (FEM). Referring toFIG.10, power amplifiers (PAs)420can receive their respective RF signals from a transceiver410that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver410is shown to interact with a baseband sub-system408that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver410. The transceiver410can also be in communication with a power management component406that is configured to manage power for the operation of the wireless device400. Such power management can also control operations of the baseband sub-system408and the module300. The baseband sub-system408is shown to be connected to a user interface402to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system408can also be connected to a memory404that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user. In the example wireless device400, outputs of the PAs420are shown to be matched (via respective match circuits422) and routed to their respective duplexers424. Each of the power amplifiers420may correspond to the power amplifier ofFIG.5and/or being included in a cascode system307such as that shown inFIG.5. Such amplified and filtered signals can be routed to an antenna416through an antenna switch414for transmission. In some embodiments, the duplexers420can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,416). InFIG.10, received signals are shown to be routed to “Rx” paths (not shown) that can include, for example, a low-noise amplifier (LNA). A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS. As described herein, one or more features of the present disclosure can provide a number of advantages when implemented in systems such as those involving the wireless device ofFIG.10. For example, the features may offer the advantage of improved and/or optimized efficiency performance over the entire power and temperature operating range of a power amplifier. Additionally, the bias of the cascode amplifier impacts the AMAM (amplitude-modulation to amplitude-modulation) characteristic of the common emitter stage. As another example, adjustment of the cascode biasing signal can provide improvement in linearity for the power amplifier. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 23,866 |
11942903 | DETAILED DESCRIPTION OF THE INVENTION As shown inFIGS.1-9of the drawings, one exemplary embodiment of the present invention is generally shown as a monolithic substrate differential pair thermocouple amplifier100. The monolithic substrate differential pair thermocouple amplifier100uses inputs of direct current power10and direct current ground20and a temperature differential across a thermocouple300to provide an amplified output signal110across an output pair120with positive output terminal122and minus output terminal124. Beginning at the bottom ofFIG.1, a hot mounting substrate200is provided and the thermocouple hot junction310is mounted onto hot mounting substrate200and provides a signal across the hot junction minus output312and hot junction positive output314to the thermocouple cold junction320. The thermocouple cold junction320provides an output across cold junction minus output322and cold junction positive output324. The thermocouple cold junction320is mounted on a ceramic isolation base400off of the hot mounting substate200. The thermocouple cold junction320includes a cold junction minus output322and cold junction positive output324. The cold junction minus output322is electrically connected to the first base710of the first silicon carbide negative positive negative transistor700. Cold junction positive output324is electrically connected to the second base760of the second SiC NPN transistor750. As may be understood fromFIG.1, the first Silicon Carbide (SiC) negative positive negative (NPN) transistor700and second SiC NPN transistor750are made on a SiC silicon carbide monolithic substrate500separated from the hot mounting substrate200by the ceramic isolation base400. The direct current power10and direct current ground20are provided onto the ceramic isolation base400. An input capacitor12is mounted on the ceramic isolation base400and is electrically connected across direct current power10and direct current ground20. The first collector720of the first SiC NPN transistor700is connected through a collector resistor810to direct current power10. The first emitter730of the first SiC NPN transistor700is connected to direct current ground20. A first base capacitor600is connected from the first base710of the first SiC NPN transistor700to direct current ground20. The second collector770of the second SiC NPN transistor750is connected through a second collector resistor820to direct current power10. The second emitter780of the second SiC NPN transistor750is connected to direct current ground20. A second base capacitor650is connected from the second base760of second SiC NPN transistor750to direct current ground20. In this manner, two Silicon Carbide (SiC) negative positive negative (NPN) transistors700,750are realized monolithically on a monolithic substrate300as a differential pair680. This differential pair680is mounted on the same ceramic isolation substrate400as the thermocouple cold junction320. Because the two transistors are mounted in thermal sensitive proximity to each other, the high thermal conductivity of the SiC substrate500keeps the transistors700,750base-emitter junctions at nearly the same temperature. This means their kT/q sensitivities tract together, this can be referred to as their thermal voltage sensitivities track each other. The base connections710,760are tied to the positive324and negative322terminals of a thermocouple cold junction320. Since the gain of the transistors700,750is so high, even very small thermal power (V and I) generated by the thermocouple300(at the hot junction310) create differential base currents. The base currents are then amplified to the collector currents creating a differential voltage across the output load resistors. Using SiC allows the amplifier to operate at high temperature, reducing the cable length between the cold junction and the hot junctions, thereby improving noise immunity. So for example, we could have the amplifier and cold junction in a region of a jet engine that is 400 degrees C. and the hot junction in a region of a jet engine that is 800 degrees C. The cable is shorter than if the amplifier has to be operated at 25 degrees C. REFERENCE NUMBERS direct current power10direct current ground20monolithic substrate differential pair thermocouple amplifier100amplified output signal110output pair120positive output terminal122minus output terminal124hot mounting substrate200thermocouple300thermocouple hot junction310hot junction minus output312hot junction positive output314thermocouple cold junction320cold junction minus output322cold junction positive output324ceramic isolation base400silicon carbide monolithic substrate500first base capacitor600second base capacitor650differential pair680first silicon carbide negative positive negative transistor700first base710first collector720first emitter730second silicon carbide negative positive negative transistor750second base760second collector770second emitter780input capacitor800first capacitor terminal802second capacitor terminal804first collector resistor810second collector resistor820 From the foregoing, it will be seen that this invention well adapted to obtain all the ends and objects herein set forth, together with other advantages which are inherent to the structure. It will also be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims. Many possible embodiments may be made of the invention without departing from the scope thereof. Therefore, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense. When interpreting the claims of this application, method claims may be recognized by the explicit use of the word ‘method’ in the preamble of the claims and the use of the ‘ing’ tense of the active word. Method claims should not be interpreted to have particular steps in a particular order unless the claim element specifically refers to a previous element, a previous action, or the result of a previous action. Apparatus claims may be recognized by the use of the word ‘apparatus’ in the preamble of the claim and should not be interpreted to have ‘means plus function language’ unless the word ‘means’ is specifically used in the claim element. The words ‘defining,’ ‘having,’ or ‘including’ should be interpreted as open ended claim language that allows additional elements or structures. Finally, where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements. | 6,798 |
11942904 | DETAILED DESCRIPTION Various embodiments are described hereinafter with reference to the figures, in which exemplary embodiments are shown. The claimed invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout. Like elements will, thus, not be described in detail with respect to the description of each figure. It should also be noted that the figures are only intended to facilitate the description of the embodiments. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated embodiment needs not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular embodiment is not necessarily limited to that embodiment and can be practiced in any other embodiments even if not so illustrated, or if not so explicitly described. The features, functions, and advantages may be achieved independently in various embodiments or may be combined in yet other embodiments. Before describing exemplary embodiments illustratively depicted in the several figures, a general introduction is provided to further understanding. As discussed above, there is a desire for wireless communications to increase data rates and decrease latency of communications. For systems using time domain duplexing (TDD), the transition time between uplink (UL) and downlink (DL) may interfere with meeting the desired specifications. For example, release 16 of the 5G NR standard by 3GPP allows for a 10 μs transmitter transient period. Future releases of the standard or other standards may shorten this time requirement to increase performance. For example, transient periods of 1 μs or shorter may be required. In some base station transmitter systems, a limiting factor for the transition period is the settling time of a gate bias voltage. In some power amplifiers, a bias voltage is applied to a portion of the electric circuit. The applied bias voltage may directly affect the behavior of the power amplifier, specifically the gain of the amplifier. The bias voltage may be adjusted when the power amplifier is not utilized, for example during the UL portion of a TDD mode communication. Under release 16 of the 5G NR standard, a settling time of 10 μs is permissible. Since the gate voltage affects the gain of the amplifier, transmitting while the gate voltage is not settled may result in a severe non-linear effect which may cause adjacent channel leakage and inter-carrier interference in cellular base stations. To counteract the non-linear effects of the gate bias voltage, the systems and methods described further herein may be able to invert or change the power amplifier input signal such that the signal at the output of the power amplifier will still be linear and can be readily demodulated by a user equipment without interfering with devices using adjacent channels. Stated another way, if a power amplifier has a non-linearity ‘x’, a device may be configured to add inverse non-linearity ‘1/x’ that will be cancelled out by the non-linearity ‘x’ of the power amplifier. As such, the signal at the output of the power amplifier is clean and linear. Generally, the process of adding in the non-linearity in advance is called predistorting or predistortion. When distortion is added digitally, the predistortion may be referred to as digital predistortion (DPD). For example, in order to mitigate the gain difference while the gate voltage is settling, a predistortion may be applied to the signal being transmitted. A digital predistortion circuit for example may increase the amplifier input signal level when the gain of the amplifier is lower than desired and decrease the amplifier input signal when the gain is higher than desired. In addition to the gain being dependent on the gate voltage, it may also be dependent on the signal input voltage as well. It is desirable to compensate for each of these effects. A digital predistortion system may predistort based on a time-varying gate bias signal, such as when the gate bias signal is transitioning. The DPD system be aware of when the gate bias voltage is transitioning. As such, it may time the predistortion filter such that it aligns with the transition of the gate bias voltage. A digital model of the transient gate voltage may be used in combination with one or more other filters to pre-distort the transmitted signal. In some examples, when the gate bias voltage is switched on, the signal first overshoots the desired voltage, then oscillates about the desired voltage until settling. The digital model may reflect this oscillation. In other amplifier configurations, the gate bias voltage transition may not oscillate, but rather rise slowly. The digital model in that case would reflect this transient. In some examples, the digital predistortion filter is based on a Taylor series approximation of the ideal gain function. Each term of the Taylor series approximation may be a separate block to which the input signal is applied. Adjustments that are common to each term may be shared. For example, the derivative portion of each Taylor series term may be a separate block, and each of those blocks may be combined with a power of the gate voltage. In some examples, the digital predistortion system may be utilized with a Doherty amplifier. For example, each amplifier portion (the carrier amplifier and the peaking amplifier) may have an input which is generated by a respective digital predistortion system. The digital predistortion systems may not be completely independent, but have some shared components. With the above general understanding borne in mind, various embodiments for providing methods and circuits for predistortion for power amplifiers are generally described below. Because one or more of the above-described embodiments are exemplified using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein. Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation. Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth. The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA. Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence. In general, each of these programmable logic devices (“PLDs”), the functionality of the device is controlled by configuration data provided to the device for that purpose. The configuration data can be stored in volatile memory (e.g., static memory cells, as common in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic. As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG.1illustrates an exemplary FPGA architecture100. The FPGA architecture100includes a large number of different programmable tiles, including multi-gigabit transceivers (“MGTs”)101, configurable logic blocks (“CLBs”)102, random access memory blocks (“BRAMs”)103, input/output blocks (“IOBs”)104, configuration and clocking logic (“CONFIG/CLOCKS”)105, digital signal processing blocks (“DSPs”)106, specialized input/output blocks (“I/O”)107(e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)110. In some embodiments, the FPGA architecture100includes an RF data converter subsystem, which contains multiple radio frequency analog-to-digital converters (RF-ADCs) and multiple radio frequency digital-to-analog converters (RF-DACs). In various examples, the RF-ADCs and RF-DACs may be individually configured for real data or can be configured in pairs for real and imaginary I/O data. In at least some examples, the FPGA architecture100may implement an RFSoC device. In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)111having connections to input and output terminals120of a programmable logic element within the same tile, as shown by examples included at the top ofFIG.1. Each programmable interconnect element111can also include connections to interconnect segments122of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element111can also include connections to interconnect segments124of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments124) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments124) can span one or more logic blocks. The programmable interconnect elements111taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA. In an example implementation, a CLB102can include a configurable logic element (“CLE”)112that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)111. A BRAM103can include a BRAM logic element (“BRL”)113in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile106can include a DSP logic element (“DSPL”)114in addition to an appropriate number of programmable interconnect elements. An IOB104can include, for example, two instances of an input/output logic element (“IOL”)115in addition to one instance of the programmable interconnect element111. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element115typically are not confined to the area of the input/output logic element115. In the example ofFIG.1, an area (depicted horizontally) near the center of the die (e.g., formed of regions105,107, and108shown inFIG.1) can be used for configuration, clock, and other control logic. Column109(depicted vertically) extending from this horizontal area or other columns may be used to distribute the clocks and configuration signals across the breadth of the FPGA. Some FPGAs utilizing the architecture illustrated inFIG.1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, PROC110spans several columns of CLBs and BRAMs. PROC110can include various components ranging from a single microprocessor to a complete programmable processing system of microprocessor(s), memory controllers, peripherals, and the like. In one aspect, PROC110is implemented as a dedicated circuitry, e.g., as a hard-wired processor, that is fabricated as part of the die that implements the programmable circuitry of the IC. PROC110can represent any of a variety of different processor types and/or systems ranging in complexity from an individual processor, e.g., a single core capable of executing program code, to an entire processor system having one or more cores, modules, co-processors, interfaces, or the like. In another aspect, PROC110is omitted from architecture100, and may be replaced with one or more of the other varieties of the programmable blocks described. Further, such blocks can be utilized to form a “soft processor” in that the various blocks of programmable circuitry can be used to form a processor that can execute program code, as is the case with PROC110. The phrase “programmable circuitry” can refer to programmable circuit elements within an IC, e.g., the various programmable or configurable circuit blocks or tiles described herein, as well as the interconnect circuitry that selectively couples the various circuit blocks, tiles, and/or elements according to configuration data that is loaded into the IC. For example, portions shown inFIG.1that are external to PROC110such as CLBs102and BRAMs103can be considered programmable circuitry of the IC. In some embodiments, the functionality and connectivity of programmable circuitry are not established until configuration data is loaded into the IC. A set of configuration data can be used to program programmable circuitry of an IC such as an FPGA. The configuration data is, in some cases, referred to as a “configuration bitstream.” In general, programmable circuitry is not operational or functional without first loading a configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuitry. The circuit design specifies, for example, functional aspects of the programmable circuit blocks and physical connectivity among the various programmable circuit blocks. In some embodiments, circuitry that is “hardwired” or “hardened,” i.e., not programmable, is manufactured as part of the IC. Unlike programmable circuitry, hardwired circuitry or circuit blocks are not implemented after the manufacture of the IC through the loading of a configuration bitstream. Hardwired circuitry is generally considered to have dedicated circuit blocks and interconnects, for example, that are functional without first loading a configuration bitstream into the IC, e.g., PROC110. In some instances, hardwired circuitry can have one or more operational modes that can be set or selected according to register settings or values stored in one or more memory elements within the IC. The operational modes can be set, for example, through the loading of a configuration bitstream into the IC. Despite this ability, hardwired circuitry is not considered programmable circuitry as the hardwired circuitry is operable and has a particular function when manufactured as part of the IC. FIG.1is intended to illustrate an exemplary architecture that can be used to implement an IC that includes programmable circuitry, e.g., a programmable fabric. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top ofFIG.1are purely exemplary. For example, in an actual IC, more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. Moreover, the FPGA ofFIG.1illustrates one example of a programmable IC that can employ examples of the interconnect circuits described herein. The interconnect circuits described herein can be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements. It is noted that the IC that may implement the methods and circuits for predistortion for power amplifiers is not limited to the exemplary IC depicted inFIG.1, and that ICs having other configurations, or other types of ICs, may also implement the methods and circuits for predistortion for power amplifiers. FIG.2is a block diagram illustrating a power amplifier circuit200(also referred to as amplifier200). Amplifier200is exemplary as the methods and devices described herein may be applied to a number of different amplifier configurations. The devices illustrated inFIG.2may each be understood to be discrete devices, comprised of multiple devices, or intrinsic properties (e.g. intrinsic resistance of a trace or parasitic capacitance). As shown, TDD bias control202may be used to control switch208and select a bias voltage to be applied to the gate of transistor214. When the amplifier is turned on, voltage Vgon204is applied, and when it is turned off, voltage Vgoff206is applied. The bias voltage sets the DC operating point (Q-point) of the amplifier producing gate voltage Vg(t)220around which the input signal Vinis centered. The transistor214in combination with supply voltage Vd210amplifies voltage Vin216. A signal having a voltage proportional to Vin216is driven across the load RL218through capacitor212. Load RL218may be, for example, an antenna. There are additional intrinsic devices not illustrated, such as intrinsic inductance which may be present allowing for the device to oscillate. The gain of amplifier200may depend on the bias voltage applied at the gate Vg(t)220. When switching to a transmitting mode from a non-transmitting mode, TDD bias control202may be used to control switch208and switch from Vgoff206to Vgon204. When this happens, Vg(t)220may not instantly reach the applied voltage, but rather there will be a transient period during which Vg(t)220will settle. During this transient period, the gain of the amplifier will change over time. A signal applied at Vin216during this transient period will be amplified in a non-linear way, which may cause problems including noise in unintended frequency channels. This noise may be characterized as an adjacent channel power ratio (ACPR) which is a ratio between the total power of adjacent channel to the main channel's power. In order to maintain ACPR within acceptable levels, a signal may not be applied at Vin216until the bias voltage has sufficiently settled after transitioning. Vin216may be predistorted as described herein such that the signal may be transmitted earlier while the bias signal is still settling. FIG.3Ais a block diagram illustrating an exemplary power amplifier circuit300. The amplifier circuit is similar to that shown inFIG.2. For example, power amplifier circuit300includes Vgon304, Vgoff306, TDD bias control302, bias voltage switch308, Vin316, Vg(t)320, transistor314, supply voltage Vd310, capacitor312, and load RL318which behave in a similar manner as their respective parts Vgon204, Vgoff206, TDD bias control202, switch208, Vin216, Vg(t)220, transistor214, supply voltage Vd210, capacitor212, and load RL218. discussed with respect toFIG.2. The amplifier300may, for example, be a relatively lower power amplifier for a small cell base station. The devices illustrated inFIG.3Amay each be understood to be discrete devices, comprised of multiple devices, or intrinsic properties (e.g. intrinsic resistance of a trace or parasitic capacitance). There may be a resistance324and inductance334between the bias voltage switch308and the input to the power amplifier package332. There may be a capacitor328between transistor314and ground. There may also be a capacitor312in series with load RL318. The components of the circuit together cause the transient response to a step in the gate voltage Vg(t) which may oscillate as described below with respect toFIG.4B. FIG.3Bis a block diagram illustrating an exemplary power amplifier circuit350. The amplifier circuit is similar to that shown inFIG.2. For example, power amplifier circuit350includes Vgon304, Vgoff306, TDD bias control302, bias voltage switch308, Vin(t)316, and Vg(t)320which behave in a similar manner as their respective parts Vgon204, Vgoff206, TDD bias control202, switch208, Vin216, and Vg(t)220discussed with respect toFIG.2. Additional features which may be the same as amplifier200such as transistor214are omitted for clarity. The amplifier350may, for example, be a relatively larger power amplifier for a macro cell base station. The devices illustrated inFIG.3Bmay each be understood to be discrete devices, comprised of multiple devices, or intrinsic properties (e.g. intrinsic resistance of a trace or parasitic capacitance). There may be a resistance324between the bias voltage switch308and the input to the power amplifier package332. There may be a capacitor328external to the power amplifier package332input. There may also be a resistance326and a capacitor330in series with resistance326within the power amplifier package332. The larger capacitance both inside and outside the power amplifier package332may cause the transient response to a step in the gate voltage Vg(t) to differ from that of power amplifier300as described below with respect toFIG.4C. FIG.4Aillustrates a schematic diagram400aof an exemplary transitioning gate voltage. The upper portion represents a cellular base station TDD communication scheme alternating between UL and DL periods over time. Corresponding to the UL and DL periods, the lower portion illustrates the bias voltage applied at Vg(t)220changing between Vgoffduring UL, and Vgonduring DL. While schematically this transition is represented as happening instantly, in reality the transition time is non-zero. During DL, the gate voltage is turned on so that the amplifier may function as intended. During UL, the amplifier is not needed as the system is receiving a signal rather than transmitting, so the gate bias voltage may be turned off to conserve power. FIG.4Billustrates a schematic diagram400bof an exemplary transitioning gate voltage. This may be the bias voltage transition, for example, of a small-cell base station power amplifier. The amplifier may be an amplifier200as discussed with reference toFIG.2. The resistance, inductance, and capacitance (including intrinsic devices) may cause a ringing to occur. The ringing may be dampened such that eventually the voltage substantially settles to the desired voltage as shown. The amount of time it takes to settle may be on the order of about 10 μs. A dampened oscillation such as the one in schematic diagram400bin an RLC circuit (such as at the input of amplifier200) with input of a step signal (such as switching from Vgoffto Vgon) can be described by the following 2nddifferential equation: d2vg(t)dt2+2αdvg(t)dt+ω02vg(t)=0where:α=R2L,ω02=1LC Solving for the gate voltage with respect to time gives: vg(t)=(vgoff-vgon)sin(ωt+θ)sin(θ)e-αt+vgon This is the voltage illustrated in diagram400b. As shown, the voltage rises beyond Vgonand oscillates until settling near Vgon. Without predistortion, the system may need to wait for delay time410before transmitting using the power amplifier so that the gate voltage, and therefore the amplifier gain, is steady. The difference between vg(t) and vgon(the error voltage) after a power amplifier is turned on due to the bias circuit RLC effect is: Δvg=(vgoff-vgon)sin(ωt+θ)sin(θ)e-αtwhere:ω=ω02-α2,sin(θ)=11+(αω)2 replacing the constants with A, the voltage difference is: Δvg=Asin(ωt+θ)e-αtwhere:A=vgoff-vgonsin(θ) FIG.4Cillustrates a schematic diagram400cof an exemplary transitioning gate voltage. In some examples, larger power amplifiers (for example power amplifier350) may have larger bias capacitance and larger capacitance inside the power amplifier package. For this reason, the shape of the transient may be different than for a micro cell. A RC2 circuit such as that shown inFIG.3Bcan be described by the following 2ndderivative equation: (RC*rcr)*d2vg(t)dt2+((R+r)cr+RC)*dvg(t)dt+vg(t)=vin the solution is: vg(t)=α2α2-α1(vgoff-vgon)(e-α1t-α1α2e-α2t)+vgonwhere:α1,2=-(((R+r)cr+RC)±((R+r)cr+RC)2-4(RC)(rcr))2(RC)(rcr) This is the voltage illustrated in schematic diagram400c. As can be seen, rather than oscillating like the voltage in diagram400b(although some small oscillations may be present), the rise time is slow, which can be explained by the larger capacitance of the circuit. The shape of the slope may be substantially monotonic, however a small amount of noise or minor oscillations (e.g. less than 10% of the height of the entire slope) in the signal may cause local non-monotonicity. Without predistortion, the system may need to wait for delay time420before transmitting using the power amplifier so that the gate voltage, and therefore the amplifier gain, is steady. The difference in voltage from the final on voltage (the error voltage) is: Δvg(t)=α2α2-α1(vgoff-vgon)(e-α1t-α1α2e-α2t) With an understanding of possible gate voltage transient responses, we now turn to a discussion of a digital predistortion system which may compensate for the time-varying gain due to the transient of the gate voltage. As discussed above, a power amplifier gain is a function of gate bias voltage vg. When a power amplifier gain is changing with time it will generate severe non-linear effects, which cause excessive adjacent channel leakage and inter-carrier interference, for example in cellular base stations. Digital predistortion (DPD) may be used to compensate the power amplifier non-linear effect. Hence, the DPD gain may be based on the amplifier gain, and so will also be a function of gate voltage vg(t) and input voltage x(t): GainDPD=GainDPD(Vgon+Δvg(t),x(t)) This says that the DPD gain is a function of the gate voltage vg(t) and the input voltage x(t), e.g. vin(t), which each vary in time. The gate voltage vg(t) may be divided into the final fixed voltage Vgon, and a time varying error voltage Δvg(t). The DPD gain may be approximated by a series expansion, such as a Taylor series expansion, taken to some finite number of terms K as shown here: GainDPD≅GainDPD(Vgon,x(t))+∑k=1KdkGainDPD(vg=Vgon,x(t))dvgk(Δvg(t))k In the formula above, the 0thterm of the series expansion is separated out of the summation. This term may be understood to represent the DPD gain with constant gate bias Vgon. The remaining components within the summation may be understood to represent the DPD gain which compensate for the time varying component of vg. Multiplying the gain by the input x provides the DPD function. In the digital (sampled) domain, this may be represented as: DPD=DPDmain+∑k=1KDPDRLCk*(Δvg)kwhereDPDmain=x(n)*GainDPD(Vgon,x(n))DPDRLCk=x(n)*dkGainDPD(vg=vgon,x(n))dvgk A factor of k! has been omitted from the denominator of each of the summation terms above as that is a constant for each term which may simply be a scaling factor applied in each DPD block (e.g. signal path). As may be seen in the equation, each of the summation terms includes the kth derivative of GainDPDwith respect to vg. The K chosen for the summation affects the accuracy of the approximation. More specifically, the series expansion approximates the function most closely at Vgon, and generally diverges more the further vg(t) is from Vgon. The more terms included, the further vg(t) may be from Vgonand still approximate the function closely enough to sufficiently compensate for the distortion. In an example, three terms of the summation are used (K=3), although any number may be used depending on the requirements. Generally, the shorter the permissible delay period before transmitting after turning on the gate voltage, the more terms that are needed. FIG.5is a schematic diagram of an exemplary digital predistortion (DPD) system500. DPD system500may be used to implement the DPD function described above. DPD input x(n)502may be the signal to be transmitted by an amplifier connected to DPD output532(also referred to as output532). DPDmainblock504may apply the DPD function described above, namely x(n)*GainDPD(Vgon, x(n)) which represents the DPD gain for constant gate bias voltage. DPDRLCblocks506a-506cmay apply the function as described above for the terms including the derivative of the gain function, namely x(n)*dkGainDPD(vg=vgon,x(n))dvgk. As the error voltage Δvg(or a power of Δvg) is multiplied by each of the summation terms in the equations above, Δvgis modeled by bias voltage error voltage provider514(e.g., using a function generator) so that it may be multiplied by the outputs of the DPDRLCblocks. Bias voltage error voltage provider514generates the model of the error voltage starting at a time associated with the gate voltage switching. Time counter508provides a counter signal which may be used by bias voltage error voltage provider514to time the signal it generates. In order to align the generated error voltage with the actual error voltage accurately, a delay generator512may provide a delay which is added to the counter signal using combiner510. For example, combiner510may be an adder. Adding a positive value to the counter in effect advances the error voltage model forward in time relative to input signal x(n)502. Time counter508, combiner510, delay generator512, and bias voltage error voltage function514may together be considered an error model provider. The error model provider may be composed of circuitry, software, or a combination of the two. The output of DPDRLCblock506cis combined with the generated error model signal Δvg(n) generated by bias voltage error voltage provider514to provide intermediate signal536using combiner524(here a multiplier). Combiners516and518may be used to generate powers of Δvg(n), for example (Δvg(n))2and (Δvg(n))3. These correspond to the (Δvg)kterms in the equations above. As such, the Δvg(n) powers are combined with the outputs of the corresponding DPDRLCblocks506aand506busing corresponding combiners520and522. The combined DPDRLCand Δvg(n){circumflex over ( )}k terms are combined (added) with the DPDmainblock504output using combiners (e.g., adders)526,528, and530to generate DPD output532. As discussed above, fewer or more DPDRLCterms may be used depending on the requirements. Each successive DPDRLCblock includes the next derivative of the gain function, any constant scaling factor, and is multiplied by a corresponding (Δvg(n))kterm and summed to the other multiplied terms to generate the output532. The various DPD blocks and combiners may be implemented using circuitry, software, or some combination. The generated model of the error voltage Δvg(n) may be generated in a number of different ways. In one example, bias voltage error voltage provider514may include a block generating an oscillating signal with a sampling frequency Fsfollowing the form of sin(ωFs(n+ndelay)+θ) and a block generating a decaying signal following the form of e -αFs(n+ndelay). These blocks may then be multiplied together to form a decaying oscillation approximation of a gate voltage transient such as the one discussed with respect toFIG.4B. The error voltage model may run continuously or may terminate after a predetermined amount of time after which it outputs a fixed value until another transition occurs. In another example, bias voltage error voltage provider514may include a block generating a decaying exponential function with a sampling frequency Fsand the form of e -α1Fs(n+ndelay) and another block generating a decaying exponential function having the form of e-αFs(n+ndelay). The second block (containing the α2term) may be combined (multiplied) by a constant −α1/α2, the result of which may be combined (added) to the output of the first block to generate the resulting gate voltage model. This effectively produces a model such as the non-oscillating function described above with respect toFIG.4C. For each of the above described methods of generating a model error voltage, the implementation details may vary. For example, some functions or portions of functions may be implemented as lookup tables rather than math logic units. Lookup tables may be interpolated as necessary to provided additional accuracy. For example, the sin( ) function may be implemented as a lookup table. In some instances the sample rates of the functions or portions of the functions may vary and later by decimated, interpolated, or otherwise filtered as necessary to balance design constraints such as timing and logic element constraints. As the gate voltage transient response may be different with different components and different conditions, it may be necessary to adjust parameters of the various blocks described above at different points. For example, default parameters may be set based on known component values (e.g. capacitance and resistance values) of the circuit. Adjustments may be made when doing initial testing or bring-up of the system to tune the parameters based on actual values. Variations over time, voltage, temperature, or other factors may require adjustments to be made automatically by the system. A cellular base station may monitor the actual voltages of the system such that it may update parameters to adjust for any perceived changes. A base station may monitor parameters such as temperature, and/or measure the gate voltage directly. This information may be used to adjust the parameters that are inputs to the equations which model the gate voltage behavior. Component behavior over temperature may be determined either empirically or by reference to an existing component model library. FIG.6illustrates a schematic diagram of an infinite impulse response (IIR) filter which may also be used to generate a model gate voltage function to be used with bias voltage error voltage provider514. A step (e.g. a step from Vgoffto Vgon) may be generated at the input of the IIR filter such that the timing corresponds to the actual gate voltage transition. The gate voltage equation discussed with reference toFIG.4Bmay be represented in the digital domain with a sampling frequency Fsas such: vg(n)=(1-a+b)vg(n-1)-bvg(n-2)+avbias(n)wherea=11+2αFsω02+Fs2ω02andb=Fs2ω021+2αFsω02+Fs2ω02andα=R2L,ω02=1LC To implement the above equation, IIR filter600includes a number of functional blocks. Block604stores constant “a” which is combined (multiplied) by the input signal with combiner602. Combiner606adds this scaled input signal to a feedback signal. The feedback signal comprises delay signals from delay generators614and616. Delay generator614feeds its output to delay generator616and combiner610. Combiner610multiplies delay from delay generator614by constant block612which outputs parameter 1−a+b. Delay generator616feeds its output to combiner618, which combines the delay from delay generator616with constant620(e.g., output the parameter “−b”). The outputs of combiners610and618are combined (e.g., added) together with combiner608whose output is added to the scaled input with combiner606as stated above. By utilizing feedback, the impulse response is able to continue indefinitely without an excessive amount of stored coefficients as may be needed for a finite impulse response (FIR) filter. As will be shown inFIG.7, the input to the IIR filter600may be a step signal which is configured to step when the gate voltage switches on a power amplifier. The step signal filtered through the IIR filter may then generate a model which approximates the actual transient gate voltage. Subtracting Vgonfrom the model may produce an error voltage. This step signal in combination with the IIR filter and subtraction may be used as another method to generate the bias voltage error signal as discussed above with reference toFIG.5. As discussed above with reference to DPD system500, the IIR filter600may have parameters adjusted at different points. Additionally, implementation details such as lookup tables and modifying sample rates may be utilized to increase performance. FIG.7is a schematic diagram of an exemplary digital front-end (DFE) system700. DFE system700combines elements already discussed such as a DPD system and a power amplifier. The power amplifier illustrated in DFE system700is a Doherty amplifier in a multi-inputs single-output architecture. A Doherty amplifier combines a class AB carrier amplifier738(also referred to as a carrier amplifier738) with a class C peaking amplifier740(also referred to as a peaking amplifier740). The peaking amplifier740is designed such that it only functions when the input signal is above a certain threshold, such that carrier amplifier738is assisted when more power is required. The outputs of the individual amplifiers are combined through a resistive element742and fed through an impedance matching device744which provides the output which may drive an antenna. Switching block702provides a step signal which is fed into an IIR filter704, which may be IIR filter600. The step signal provider simulates a step from VgcULto VgcDLwhich are respectively the gate bias voltage of the carrier amplifier during uplink, and the gate bias voltage of the carrier amplifier during downlink. The step signal provider put through the IIR filter704produces a simulated model of the transient response to the gate voltage at the carrier amplifier when switched. In order to produce an error voltage Δvg, combiner708adds a negative version of the final gate voltage (−VgcDL) from constant block706. DPD block710takes the error voltage output of combiner708and applies it to one or more DPD blocks such as the DPDRLCblocks described with reference toFIG.5. The input signal x(n) is also provided to DPD block710which is used as described with reference toFIG.5. A separate DPD system may be provided for the peaking amplifier, which is constructed in a similar manner to the DPD system for the carrier amplifier. Switching block712, IIR filter714, constant block716, combiner718, and DPD block720may be configured to behave in a similar manner to switching block702, IIR filter704, constant block706, combiner708, and DPD block710respectively. One difference between the DPD system for the peaking amplifier, however, is the simulated gate voltages used are VgpULand VgpDLwhich are respectively the gate bias voltage of the peaking amplifier during uplink, and the gate bias voltage of the peaking amplifier during downlink. The DPDmainterm discussed with reference toFIG.5may be provided individually for each DPD block710and720, or there may be a shared DPDDoherty722which provides a combined DPD block that accounts for the gain of the Doherty amplifier when each of the carrier amplifier738and the peaking amplifier740are biased with their downlink gate bias voltage. DPDDohertytakes the input signal x(n) as an input and applies its predistortion to generate dpdoDohertywhich is combined with the outputs of DPD block710and DPD block720using combiners724and726respectively. The output of combiner724contains the predistorted digital signal for the carrier amplifier which is turned into an analog signal using digital to analog converter (DAC)730. Driver734buffers the output of DAC730in order to drive the carrier amplifier738. Likewise, the output of combiner726contains the predistorted digital signal for the peaking amplifier. This digital signal is delayed with a 90 degree phase shift by delay block728. The output of delay block728is converted to an analog signal by DAC732. The output of DAC732is buffered by driver736which drives the peaking amplifier740. While the same signal x(n) is desired to be transmitted using both amplifiers comprising the Doherty amplifier, each of the carrier amplifier and the peaking amplifier have different gains, and as such their inputs may be predistorted individually. By applying digital predistortion as described, DFE system700may compensate for the effects of the transient gate voltages and permit the DFE system700to transmit a signal earlier while the gate voltages are still settling, while substantially decreasing ACPR. FIG.8is a flow diagram illustrating a method800for performing a digital predistortion process in a DPD system. Method800may be performed by components such as those described with reference toFIGS.1-3and5-7. Blocks in method800may be performed in a different order than that shown. Also, some blocks may be omitted, and additional blocks may be included which are not illustrated. At block802, a DPD system receives an input signal at a first signal path configured to generate a first signal based on the input signal. The first signal path may include a DPD block such as the DPDRLCblocks discussed with reference toFIG.5. At block804, the DPD system generates an error model signal modeled after a gate bias error voltage associated with an amplifier. As discussed above, multiple methods may be used to generate the error model signal. A signal may be generated directly modeled after the gate voltage signal as discussed with reference toFIG.5. A step signal may be passed through an IIR filter and a constant gate voltage subtracted from the IIR filter output as discussed with respect toFIGS.6-7. At block806, the DPD system combines the first signal and the error model signal534to generate a first intermediate signal536. For example, this may be performed by a combiner such as combiner524in DPD system500. At block808, the DPD system generates an output signal based at least on the first intermediate signal. It is noted that various configurations (e.g., the components of the amplifier200, the amplifier circuits300and350, the DPD system500, the IIR filter600, and the DFE system700) are exemplary only and not intended to be limiting beyond what is specifically recited in the claims that follow. It will be understood by those skilled in the art that other configurations may be used. Also, while an exemplary DFE system700is illustrated, the DPD system disclosed herein may be used to in other communication systems. Although particular embodiments have been shown and described, it will be understood that it is not intended to limit the claimed inventions to the preferred embodiments, and it will be obvious to those skilled in the art that various changes and modifications may be made without department from the spirit and scope of the claimed inventions. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense. The claimed inventions are intended to cover alternatives, modifications, and equivalents. | 44,565 |
11942905 | DETAILED DESCRIPTION The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Similarly, any steps described herein may be interchangeable with other steps, or combinations of steps, in order to achieve the same or substantially similar result. Moreover, some of the method steps can be carried serially or in parallel, or in any order unless specifically expressed or understood in the context of other method steps. FIG.1schematically shows an electronic device10. The electronic device10comprises a non-linear electronic component12and an equalizer circuit14. In general, the electronic device10may be any kind of signal-processing electronic device or signal-generating electronic device. For example, the electronic device10may be established as a measurement instrument, as a broad-band amplifier, as an analog-to-digital converter, as a digital-to-analog converter, or as a signal generator. In some embodiments, the electronic device10may be established as an oscilloscope. The non-linear electronic component12may be any electronic component that is configured to process an input signal x, thereby generating an output signal y. For example, the non-linear electronic component12may be an amplifier, an analog-to-digital converter, or a digital-to-analog converter. Therein, the dependence of the output signal y on the input signal x is not linear, but comprises higher order terms. Accordingly, the output signal y is a function of the input signal x and can be written as follows y=A·x+O(x2),i.e. as a linear term plus higher order terms. Therein, y=(y(n=0), y(n=1), . . . )Tis a vector comprising the output signal samples y(n), and x=(x(n=0), x(n=1), . . . )Tis a vector comprising the input signal samples x(n). The non-linear terms may cause unwanted distortions of the output signal y. In order to counteract these distortions, the equalizer circuit14is configured to equalize the output signal y, e.g. pre-distort a signal processed, such that the unwanted distortions are removed from the output signal y. For this purpose, the equalizer circuit14comprises, for example, a Volterra filter circuit16with filter coefficients that are adapted to remove the unwanted perturbations from the output signal y. The functionality of the Volterra filter circuit16will be described in more detail hereinafter. FIG.2schematically shows a second embodiment of the electronic device10, wherein the electronic device10is established as a signal generator. For example, the electronic device10may be established as an arbitrary signal generator. Accordingly, the non-linear electronic component12may be established as any component being configured to generate a predetermined output signal y or to convert a digital input signal x to an analog output signal y. The electronic device10comprises a control circuit18that is configured to generate the input signal x, wherein the input signal x comprises instructions for the electronic component12to generate the output signal y. The equalizer circuit14may be interconnected between the control circuit18and the non-linear electronic component12. Accordingly, the equalizer circuit14or the Volterra filter circuit16is configured to adapt the input signal x such that the output signal y does not comprise any non-linear distortions. In other words, the Volterra filter circuit16is configured to pre-compensate, also called pre-distort, the non-linear distortions that would be caused by the non-linear electronic component12. Alternatively, the electronic device10ofFIG.2may be established as a digital-to-analog converter. Accordingly, the equalizer circuit14or the Volterra filter circuit16is configured to adapt the digital input signal x such that the analog output signal y does not comprise any non-linear distortions. In other words, the Volterra filter circuit16is configured to pre-compensate the non-linear distortions that would be caused by the non-linear electronic component12. The equalizer circuit14needs to be properly calibrated, i.e. the filter coefficients of the Volterra filter circuit16need to be properly set, such that the Volterra filter circuit16correctly equalizes the output signal y. The correct filter coefficients for the Volterra filter circuit can be obtained by a method of determining filter coefficients of the equalizer circuit14. One example of the method is described in the following with reference toFIG.3. Without restriction of generality, the representative method is described in the following in the context of the electronic device10ofFIG.1. However, it is to be understood that the method can readily be adjusted for the electronic device10ofFIG.2. An input signal x is provided (step S1). In general, the input signal x is a calibration signal that is used in order to calibrate the equalizer circuit14. Accordingly, the input signal x may have known properties, i.e. a known spectrum, known amplitudes and/or known phases. The input signal x may be received from an external electronic device, for example from a signal generator or from a device under test. Alternatively, the input signal x may be generated by another internal electronic component of the electronic device10. The input signal x is processed by the non-linear electronic component12, thereby generating the output signal y (step S2). A first mathematical model is provided, wherein the first mathematical model describes the non-linear electronic component12in terms of a first Volterra series. In general, Volterra series can be used in order to describe non-linear systems that are frequency-dependent and independent of a signal level. The output signal y can then be written in terms of the input signal x as follows: y(t/Ta)=∑m=1Mym(t/Ta)=∑m=1M∑μ0=0Lm,0-1…∑μm-1=0Lm,m-1-1hm(μ0,…,μm-1)·∏α=0m-1x(t/Ta-μa)(E.1) Therein, M is the maximum order of the Volterra series, hm(μ0, . . . ) are multi-dimensional impulse responses, and Lm,μis the length of the impulse response for the dimension μ and for the order m. In other words, the non-linear electronic component12can be described as a Volterra filter, and may also be called Volterra system, wherein Lm,μis the length of the Volterra filter of order m for the dimension μ. This interpretation will be used in the following. The filter coefficients hm(t0/Ta, . . . , tm-1/Ta) of the Volterra system are ambiguous, as multiple filter coefficients lead to the same product signal x(t0/Ta,…,tm-1/Ta)=∏α=0m-1x(ta/Ta)(E.2)in equation (E.1). Therein, Tais the sampling time associated with the input signal x, i.e. fa=1/Tais the sampling frequency of the input signal x. For example, the filter coefficients {h2(t0/Ta,t1/Ta),h2(t1/Ta,t0/Ta)} (E.3)of a Volterra system of order m=2 yield the same product signal x(t0/Ta, t1/Ta). Likewise, the following filter coefficients of a Volterra system of order m=3 yield the same product signal x(t0/Ta, t1/Ta, t2/Ta): {h3(t0/Ta,t1/Ta,t2/Ta),h3(t2/Ta,t0/Ta,t1/Ta),h3(t1/Ta,t2/Ta,t0/Ta),h3(t2/Ta,t1/Ta,t0/Ta),h3(t1/Ta,t0/Ta,t2/Ta),h3(t0/Ta,t2/Ta,t1/Ta),} (E.4) Accordingly, there is a certain freedom of choice when describing the non-linear electronic component12in terms of the Volterra series of equation (E.1). In some embodiments, the ambiguous filter coefficients hmmay be chosen such that only one coefficient of a set of ambiguous coefficients is non-zero. Alternatively, the ambiguous filter coefficients may be chosen to be all equal to each other, such that a transfer function of the Volterra system has an additional symmetry. The Fourier transform of equation (E.1) yields the spectrum Y of the output signal Y: Y(f/fa)=∑m=1MYm(f/fa)=∑m=1M∑f0/fa=0N-1⋯∑fm-1/fa=0a-1Hm(f0/fa,…,fm-1/fa)·∏a=0m-1X(fa/fa)·δ1(f/fa-f0/fa-…-fm-1/fa)(E.5) Therein, X(f/fa)=∑t/Ta=0N-1x(t/Ta)·e-j·2n·t/Ta·f/fa(E.6)is the spectrum of the input signal x, and Hm(f0/fa,…,fm-1/fa)=∑t0/Ta=0N-1⋯∑tm-a/Ta=0N-1hm(t0/Ta,…,tm-1/Ta)·e-j·2n·(t0/Ta·f0/fa+…+tm-a/Ta·fm-1/fa)(E.7)is the transfer function of the Volterra system, i.e. the transfer function of the non-linear electronic component12. Moreover, N is the length of the Fourier transform, and δ1(f/fa) is a Kronecker-delta-operator, which operates with respect to its argument modulo 1: δ1(f/fa)=δ(mod{f/fa,1}). (E.8) Transfer functions of real-valued Volterra systems have a complex conjugate symmetry: Hm(−f0/fa, . . . ,−fm-1/fa)=H*m(f0/fa, . . . ,fm-1/fa). (E.9) If the impulse responses hm(t0/Ta, . . . , tm-1/Ta) are symmetric, then transfer functions of Volterra systems of order m=2 have the additional symmetry H2(f0/fa,f1/fa)=H2(f1/fa,f0/fa) (E.10)while the transfer functions of Volterra systems of order m=3 have the additional symmetry H3(f0/fa,f1/fa,f2/fa)=H3(f2/fa,f0/fa,f1/fa)=H3(f1/fa,f2/fa,f0/fa)=H3(f2/fa,f1/fa,f0/fa)=H3(f1/fa,f0/fa,f2/fa)=H3(f0/fa,f2/fa,h1/fa) (E.11) In other words, the transfer functions are equal to each other at points where the individual frequencies fμ/faare interchanged arbitrarily. From equation (E.5) it can be seen that the sampling rate faassociated with the input signal x is sufficient to characterize the non-linear electronic component12as a Volterra system. Accordingly, the sampling rate does not need to be enhanced, e.g. via an interpolation. If the input signal x is established as a multi-frequency signal comprising a number NTof different signal components having different predefined frequencies fμ/fa, amplitudes Aμand phases ϕμ, the input signal can be written as X(f/fa)=∑μ=0Nτ-1Aμ·ejϕμ·[δ1(f/fa-fμfa)+δ1(f/fa+fμ/fa)](E.12) In this case, the output signal spectrum Y is given by Ym(f/fa)=∑μ0=0NT-1-∑μm-1=0NT-1Hm(fμ0fa,…,fμm-1fa)∏a=0m-1Aμa·ej·∑α=1mϕμα·[δ1(ffa-∑a=0m-1fμafa)+δ1(ffa-∑α=0m-1fμafa)].(E.13) It is noted that the multi-dimensional impulse responses of some Volterra systems, for example of low-noise amplifiers, are weakly occupied, i.e. most of the components of the multi-dimensional impulse responses are equal to zero. If only filter coefficients of the main diagonal of the impulse responses are non-zero, the Volterra series may also be called a “memory polynomial”. If only few diagonals of the impulse responses are non-zero, the Volterra series may also be called an “extended memory polynomial”: y(t/Ta)=∑m=aMym(t/Ta)=∑m=aM∑μ0=0L-1∑μ1=μ0-Dm-1μ0+Dm,1⋯∑μm-1=μ0-Dm-1,m-1μ0+Dm-1,m-1hm(μ0,…,μm-1)·∏a=0m-1x(Ta-μa).(E.14) Therein, the term 2Dm,μ+1 describes the number of diagonals of the impulse response of the Volterra system of order m with respect to dimension μ. Based on the input signal x, the output signal y, and the first Volterra series, impulse responses and/or transfer functions of the non-linear electronic component12are determined (step S3). In the following, two different embodiments are described with respect to the input signal that both allow for determining the impulse responses and/or transfer functions of the non-linear electronic component12. It has turned out that restricting the analysis to the order M=3 is sufficient in both variants. According to a first embodiment, the input signal x may be established as a broad-band noise signal. Equation (E.1) can be rewritten in a matrix-vector-notation as follows: y(t/Ta)=X(t/Ta)·h.(E.15) The vector h=[h1(0), . . . ,h1(L1−1),h2(0,0), . . . ,h2(L2,0−1,L2,1−1),h3(0,0,0), . . . ,h3(L3,0−1,L3,1−L3,2−1)]T(E.16)comprises all filter coefficients of the impulse responses of order m=1, 2, 3, wherein only one filter coefficient of each set of ambiguous filter coefficients is taken into account. The matrix X__(t/Ta)=[x_T(t/Ta)⋮x_T(t/Ta…N+1)](E.17)comprises vectors x(t/Ta)=[x(t/Ta), . . . ,x(t/Ta−L1−1),x(t/Ta)·x(t/Ta), . . . ,x(t/Ta−L2,0+1)·x(t/Ta−L2,1+1),x(t/Ta)x(t/T)·x(t/Ta), . . . ,x(t/Ta−L3,0+1)·x(t/Ta−L3,1+1)·x(t/Ta−L3,0+1)]T, (E.18)that comprise the corresponding product signals of the filter coefficients. The vector y(t/Ta)=[y(t/Ta), . . . ,y(t/Ta−N+1)]T(E.19)comprises the sample points of the output signal y of the non-linear electronic component12. In order to determine the impulse responses and/or transfer functions of the non-linear electronic component12, a cost functional K is provided, wherein the cost functional K describes a mean error signal power: K=ē2(t/Ta)=[X(t/Ta)·h−y(t/Ta)]T·[X(t/Ta)·h−y(t/Ta)]. (E.20) The cost functional is minimized by the following choice of filter coefficients: h=[(XT(t/Ta)·X(t/Ta)]−1·[X(t/Ta)·y(t/Ta)] (E.21) It is noted that the correlation matrix C(t/Ta)=[XT(t/Ta)·X(t/Ta)] (E.22)needs to be inverted in order to determine the filter coefficients according to equation (E.21). A broad-band noise signal comprises a lot of different frequencies. As can be seen in equation (E.13), several different signal components having different frequencies contribute to the same output signal frequency. In other words, there is a superposition of contributions from different input signal frequencies contributing to the same output signal frequency. Such superpositions can occur within the same order m of the Volterra system and/or across different orders m of the Volterra system. For example, within the order m=2, all frequencies {−fin/fa,+fin/fa} always superpose to give an output frequency of zero. Within the order m=3, the input frequencies {−fin,0/fa, +fin,0/fa, +fin,1/fa} always yield an output frequency fout/fa=fin,1/fa. An example for such superpositions between different orders are input frequencies {0.15,0.15} for m=2 and {0.1,0.1,0.1} for m=3, which both yield an output frequency of fout/fa=0.3. Thus, using a broad-band noise signal as input signal x leads to a systematically overdetermined computation problem. It has turned out that that the correlation matrix defined in equation (E.22) has a rather high condition, i.e. a high amplification factor of errors, which further complicates the matrix inversion. Moreover, the correlation matrix comprises expectation values of higher order, namely rxo(T0/Ta,T1/Ta,…,To-1/Ta)=E{∏μ=0o-1ϰ(t/Ta-Tμ/Ta)}.(E.23) More precisely, depending on the maximum order M of the Volterra system, the correlation matrix comprises expectation values of the orders o={2,3, . . . ,2M}(E.24) These problems can be counteracted by enhancing the numeric precision for the matrix inversion and/or by enhancing the observation length N for determining the correlation matrix. However, this may considerably increase the necessary computation time. According to a second embodiment, the input signal x may be established as a multi-frequency signal comprising a pre-defined number NTof signal components having different frequencies. The output signal of the Volterra system then comprises spectral components having output frequencies fout,a/fa=mod{∑μ=0m-1fin,μ,a/fa,1},(E.25)which are generated by groups of m input frequencies {fin,0,α/fa, . . . , fin,m-1,α/fa}, wherein frequencies within a group α may be partially or completely the same. If the amplitudes and phases of the input signal x are known and the amplitudes and phases of the output signal y are determined, the transfer functions Hm({fin,0,α/fa, . . . , fin,m-1,α/fa}) can be determined at the spectral positions {fin,0,α/fa, . . . , fin,m-1,α/fa} of the frequency group α. As described above in the context of the input signal being established as a broad-band noise signal, different groups of input frequencies can contribute to the same output frequency. Accordingly, several contributions associated with different transfer functions superpose, and the transfer functions may not be determinable at these spectral positions. It has turned out that there are different classes of such ambiguities, namelythe ambiguities originate within a single order m of the Volterra system;the ambiguities originate across different orders m of the Volterra system;the ambiguities are systematic, i.e. they cannot be avoided by choosing another set of input frequencies; andthe ambiguities are non-systematic, i.e. they can be avoided by choosing another set of input frequencies. Accordingly, the input frequencies of the input signal x are chosen such that only the systematic ambiguities remain and there are no non-systematic ambiguities. The correct input frequencies can, for example, be found by solving a corresponding optimization problem with an intelligent search technique. It is noted that in order to fully characterize a Volterra system of maximum order M=3, a minimum number NT=3 of different signal components having different frequencies is required. The transfer functions Hmof the Volterra system (i.e. of the non-linear electronic component12) Hm(f0fa,…,fm-1fa)=c(m)Ncomb(m,f0/fa,…,fm-1/fa)·Aout(fout/fa)∏μ=0m-1Ain(fμ/fa)·ej·ϕiyt(fout/fa)-j·∑μ=0m-1ϕin(fu/fa)(E.26)at the spectral positions {f0/fa, . . . , fm-1/fa} depend on the amplitude Aout(fout/fa) and the phase ϕout(fout/fa) of the output signal that are associated with the input frequencies {f0/fa, . . . , fm-1/fa}. Moreover, the transfer functions Hmdepend on the amplitudes Ain(fμ/fa) and the phases ϕin(fμ/fa) of the components of the input signal x. In equation (E.26), the factor c(m) is a scaling factor that depends on the order m, wherein c(1)=1, c(2)=2, and c(3)=4. The factor Ncombis a combinatorial factor, wherein:Ncomb(m=1)=1;Ncomb(m=2, f0/fa, f1/fa) is equal to 1 if f0=f1and is equal to 2 otherwise; andNcomb(m=3, f0/fa, f1/fa, f2/fa) is equal to 1 if all frequencies are identical, equal to 3 if two frequencies are identical, and equal to 6 if all frequencies are different from each other. It has turned out that the transfer functions Hmdetermined according to equation (E.26) are symmetric, and the associated impulse responses hmare axisymmetric. Put differently, the transfer functions Hmare sampled with the multi-frequency input signal x. In some embodiments, the individual signal components of the input signal x are non-equidistant in frequency domain, i.e. the value of fi−fjis different for each pair of frequencies fi, fjof the input signal. In order to determine the transfer functions Hmaccording to equation (E.26), the amplitudes Aμand phases ϕμof the output signal y have to be determined. The output signal y can be written as y(t/Ta)=∑μ=0NT-1Aμ·sin(2π·fμ/fa·t/Ta+ϕμ)=∑μ=0NT-1Cμ·sin(2π·fμ/fa·t/Ta)+Dμ·cos(2π·fμ/fa·t/Ta)(E.27) Equation (E.27) can be re-written in matrix-vector-notation as follows: y(t/Ta)=X(t/Ta)·h(E.28) The vector h=[C0,D0,C1,D1, . . . ,CNT−1,DNT−1]T(E.29)comprises all amplitudes of the sine terms and of the cosine terms in equation (E.27). The matrix X__(t/Ta)=[x_T(t/Ta)⋮x_T(t/Ta-N+1)](E.30)comprises the vectors x(t/Ta)=[sin(2π·f0/fa·t/Ta),cos(2π·f0/fa·t/Ta), . . . ,sin(2π·fNT−1/fa·t/Ta),cos(2π·fNT−1/fa·t/Ta)]T(E.31)which comprise the sample points associated with the sine terms and the cosine terms. N is the number of samples that is used for determining the amplitudes and phases. The vector y(t/Ta)=[y(t/Ta), . . . ,y(t/Ta−N+1)]T(E.32)comprises the samples of the output signal y. In order to determine the amplitudes Cμand Dμ, a cost functional K is provided, wherein the cost functional K describes a mean error signal power: K=ē2(t/Ta)·[X(t/Ta)·h−y(T/Ta)]T·[X(t/Ta)·h−y(T/Ta)] (E.33) The cost functional is minimized by the following amplitude vector: h=[XT(t/Ta)·X(t/Ta)]−1·[XT(t/Ta)·y(t/Ta)] (E.34) The inverse of the correlation matrix XT(t/Ta)·X(t/Ta) (E.35)can be determined a priori, and may be saved in a memory for later usage. The phases ϕμcan then be determined from the equation ϕμ=atan(Dμ/Cu) (E.36) The amplitudes Aμcan then be determined according to the equation Aμ=Cμ/sin(ϕμ) (E.37) There are two special cases at f/fa=0 and f/fa=−½. In these cases, only the amplitude Aμhas to be determined. Thus, in these cases the parameter Dμhas to be set to zero in equations (E.27) and (E.29). Optionally, the impulse responses hmof the non-linear electronic component12may be determined based on the determined transfer functions Hm(step S4). Equation (E.7) can be reformulated in matrix-vector notation as follows: y=X·h.(E.38) The vector h=[hm(0, . . . ,0),hm(Lm−1, . . . ,Lm−1)]T(E.39)comprises all impulse responses of the non-linear electronic component12(the impulse responses may also be called filter coefficients of the Volterra system representing the non-linear electronic component12). The reference vector y=[Hm(f0/fa, . . . ,f0/fa), . . . ,Hm(fN-1/fa, . . . ,fN-1/fa)]T(E.40)comprises the transfer functions Hmof the non-linear electronic component12, i.e. of the Volterra system. The matrix X=[x_T(f0/fa,…,f0/fa)⋮x_T(fN-1/fa,…,f0/fa)](E.41)comprises vectors x(f0/fa, . . . ,fm-1/fa)=[e−j·2π·[f0/fa·0+ . . . +]fm-1/fa·0, . . . ,e−j·2π·[f0/fa·(Lm−1)+ . . . +fm-1/fa(Lm-1)]]T(E.42)that comprise the exponential functions of the respective Fourier transforms. The following cost functional K is provided, wherein the cost functional K describes a mean spectral error signal power: K=Ē2=[X·h−y]T·diag{W}·[X·h−y].(E.43) Therein, the vector W=[W(f0/fa, . . . ,f0/fa), . . . ,W(fN-1/fa, . . . ,fN-1/fa)]T(E.44)is a spectral weighting function. Via the spectral weighting function, the spectral quality of the Volterra system can be controlled. The cost functional K is minimized by the following filter coefficients (i.e. impulse responses) of the Volterra system: h=[diag{W}·XT·X]−1·[(diag{W}·XT·y](E.45) It has turned out that the minimization problem defined by equations (E.38) to (E.45) is not ambiguous, and that the correlation matrix diag{W}·XT·X(E.46)only has a small or moderate condition. The inverse of the correlation matrix can be determined a priori, and may be saved in a memory for later usage. The transfer functions Hmdo not have to be sampled in an equidistant manner. However, the maximum frequency distance puts an upper boundary on the length Lmof the impulse response hm(t0/Ta, . . . , tm-1/Ta): Lm≤1maxu,v{❘"\[LeftBracketingBar]"fμ/fa-fv/fa❘"\[RightBracketingBar]"}(E.47) It is noted that the minimization technique described in equations (E.38) to (E.47) can also be used for memory polynomials or otherwise pruned Volterra series. In that case, the impulse responses that are equal to zero have to be deleted from equation (E.39). Filter coefficients of the Volterra filter circuit16are determined based on the determined transfer functions Hmof the non-linear electronic component12(step S5). In some embodiments, the filter coefficients of the Volterra filter circuit16are determined by a Pth order inverse technique, as will be described in more detail below. In general, the Volterra filter circuit16is described by a second mathematical model, more precisely by a second Volterra series, analogously to equation (E.1). First, the Pth order inverse technique will be described in time domain. The filter coefficients heq,1of order m=1 of the Volterra filter circuit16are defined by the following equation: y(k)=∑μ0heq,1(μ0)·∑α0h1(αo)·x(k-μ0-α0)=x(k).(E.48) Therein, hm(k0, k1, . . . , km-1) are the impulse responses of the Volterra system (i.e. of the non-linear electronic system12) that have already been determined, while heq,mare the desired impulse responses, i.e. the filter coefficients of the Volterra filter circuit16. In order for the output signal y(k) of the equalizer circuit14to be equal to the input signal x(k) of the non-linear electronic component12, the condition ∑μ0heq,1(μ0)·h1(-μ0)=1(E.49)has to be fulfilled for μ0+α0=0, while the condition ∑μ0heq,1(μ0)·h1(D-μ0)=0(E.50)has to be fulfilled for μ0+α0=D≠0. Equations (E.49) and (E.50) define a system of equations that can be solved by a minimum square error technique. For the second order, i.e. m=2, the following condition has to be fulfilled: ∑μ0∑μ1heq,2(μ0,μ1)·x(k-μ0)·x(k-μ1)=-∑α0heq,1(α0)∑β0∑β1h2(β0,β1)·[∑γ0heq,1(γ0)·x(k-α0-β0-γ0)]·[∑γ1heq,1(γ1)·x(k-α1-β1-γ1)].(E.51) This leads to the following expression for the second order filter coefficients of the Volterra filter circuit16: heq,2(μ0,μ1)=-∑α0heq,1(α0)·∑β0∑β1h2(β0,β1)·heq,1(μ0-α0-β0)·heq,1(μ1-α1-β1).(E.52) For the third order, i.e. m=3, the condition is that there should be no distortions of order m=3 at the output of the Volterra filter circuit16. In a shortened notation, this condition can be expressed as Q3=K1H3+K2[H1+H2]−K2H1−K2H2−K3H1=0 (E.53)wherein Kmrepresents the Volterra filter circuit16at order m, and wherein Hmrepresents the Volterra system (i.e. the non-linear electronic component12) at order m. K1and K2have already been determined above, cf. equations (E.50) and (E.52). The third order contribution of the Volterra filter circuit16is then given by K3=−K1H3K1−K2[H1+H2]K1+K2H1K1+K2H2K1=−K1H3K1−K2[H1+H2]K1+K2+K2H2K1=T(1)+T(2)+T(3)+T(4). (E.54) In the following, the explicit expressions for the terms T(μ)are given: T(1)=-∑α0heq,1(α0)·∑β0∑β1∑β2h3(β0,B1,β2)·[∑γ0heq,1(γ0)·x(k-α0-β0-γ0)]·[∑γ1heq,1(γ1)·x(k-α0-β1-γ1)]·[∑γ2heq,1(γ2)·x(k-α0-β2-γ2)](E.55)T(2)=-∑α0∑α1heq,2(α0,α1)·[x(k-α0)+T(5)]·[x(k-α1)+T(6)]T(5)=∑β0∑β1h2(β0,β1)·[∑γ0heq,1(γ0)·x(k-α0-β0-γ0)]·[∑γ1heq,1(γ0)·x(k-α0-β1-γ1)]T(6)=∑β2∑β3h2(β2,β3)·[∑γ2heq,1(γ2)·x(k-α1-β2-γ2)]·[∑γ3heq,1(γ0)·x(k-α1-β3-γ3)]T(3)=+∑α0∑α1heq,2(α0,α1)·x(k-α0)·x(k-α1)T(4)=+∑α0∑α1heq,2(α0,α1)·[∑β0∑β1h2(β0,β1)·{∑γ0heq,1(γ0)·x(k-α0-β0-γ0)}·{∑γ1heq,1(γ1)·x(k-α0-β1-γ1)}]·[∑β2∑β3h2(β2,β3)·{∑γ2heq,1(γ0)·x(k-α1-β2-γ2)}·{∑γ3heq,1(γ3)·x(k-α1-β3-γ3)}] For the calculation of the impulse response heq,3of the third order of the Volterra filter circuit16, only product signals x(k0)·x(k1)·x(k2) with three sample values may contribute. It has turned out that terms that do not meet this condition completely cancel each other. Accordingly, it holds -∑α0∑α1heq,2(α0,α1)·T(5)·T(6)=-T(4)-∑α0∑α1heq,2(α0,α1)·x(k-α0)·x(k-α1)=-T(3).(E.56) The result for the third order filter coefficients of the Volterra filter circuit16has two contributions, namely heq,3(1)and heq,3(2), which are given by heq,3(1)(μ0,μ1,μ2)=-∑a0heq,1(α0)·∑β0∑β1∑β2h3(β0,B1,β2)·heq,1(μ0-α0-β0)·heq,1(μ1-α0-β1)·heq,1(μ2-α0-β2)(E.57)heq,3(2)(μ0,μ1,μ2)=-∑α1Leq.1heq,2(μ0,α1)·∑β2β3h2(β2,β3)·heq,1(μ1-α1-β2)·heq,1(μ2-α1-β3)-∑α0Leq,1-1heq,2(α0,μ1)·∑β0β1h2(β0,β1)·heq,1(μ0-α0-β0)·heq,1(μ1-α0-β1) The third order filter coefficients of the Volterra filter circuit16are then given by heq,3(μ0,μ1,μ2)=heq,3(1)(μ0,μ1,μ2)+heq,3(2)(μ0,μ1,μ2) (E.58) With the same technique, filter coefficients heq,m(k0, k1, k2) of extended memory polynomials or pruned impulse responses can be determined. In this case, only sample times lying on the diagonals of the impulse responses heq,m(k0, k1, k2) are considered. The determined impulse responses heq,m(k0, k1, k2) may not be the final filter coefficients for the Volterra filter circuit16. Instead, the determined impulse responses heq,m(k0, k1, k2) may serve as reference impulse responses heq,ref,m(k0, k1, k2) for determining the final filter coefficients of the Volterra filter circuit16, as will be described in more detail below. Alternatively to the time-domain technique described above, the filter coefficients of the Volterra filter circuit16can also be determined by a Pth order inverse technique in frequency domain. First, equation (E.5) is formulated for the maximum order M=3, and the innermost summation is performed, resulting in Y(f/fa)=H1(f/fa)·X(f/fa)+∑α=0N-1H2(α,f/fa-αmod1)·X(α)·X(f/fa-αmod1)+∑β0=0N-1∑β1=0N-1H3(β0,β1,f/fa-β0-β1mod1)·X(β0)·X(β1)·X(f/fa-f/fa-β0-β1mod1).(E.59) The condition for the first order of the Volterra filter circuit16is Y(f/fa)=Heq,1(f/fa)·H1(f/fa)·X(f/fa)=X(f/fa). (E.60) This immediately yields the following result for an arbitrary input signal spectrum X(f/fa): Heq,1(f/fa)=1H1(f/fa)(E.61) The condition for the second order of the Volterra filter circuit16is ∑μ=0N-1Heq,2(μ,f/fa-μmod1)·X(μ)·X(f/fa-μmod1)=-Heq,1(f/fa)·∑α=0N-1H2(α,f/fa-αmod1)·[Heq,1(α)·X(α)]·[Heq,1(f/fa-αmod1)·X(f/fa-αmod1)].(E.62) This yields the following result: Heq,2(f0/fa,f1/fa)=−Heq,1(f0/fa+f1/famod 1)·H2(f0/fa,f1/fa)·Heq,1(f0/fa)·Heq,1(f1/fa). (E.63) For the third order of the Volterra filter circuit16, the frequency-domain analogues of the terms given in equation (E.55) are determined. The result is T(1)=-Heq,1(f/fa)·∑β0=0N-1∑β1=0N-1H3(β0,β1,f/fa-β0-β1mod1)·[Heq,1(β0)·X(β0)]·[Heq,1(β1)·X(β1)]·[Heq,1(f/fa-β0-β1mod1)·X(f/fa-β0-β1mod1)],(E.64)T(2)=-∑α=0N-1Heq,2(α,f/fa-α)·[X(α)+T(5)(α)]·[X(f/fa-αmod1)+T(6)(f/fa-αmod1)]T(6)(f/fa-αmod1)=∑β=0N-1Heq,2(β,f/fa-α-βmod1)·[Heq,1(β)·X(β)]·[Heq,1(f/fa-α-βmod1)·X(f/fa-α-βmod1)]T(3)=+∑α=0N-1Heq,2(α,f/fa-α)·X(α)·X(f/fa-α)T(4)=+∑α=0N-1Heq,2(α,f/fa-α)·{∑β0=0N-1H2(β0,α-β0mod1)·[Heq,1(β0)·X(β0)]·[Heq,1(α-β0mod1)·X(α-β0mod1)]}·{∑β1=0N-1H2(β1f/fa-α-β1mod1)·[Heq,1(β1)·X(β1)]·[Heq,1(β1,f/fa-α-β1mod1)·X(β1,f/fa-α-β1mod1)]} For the calculation of the transfer function Heq,3of the third order of the Volterra filter circuit16, only product spectra X(f0/fa)·X(f1/fa)·X(f2/fa) with three frequencies may contribute. It has turned out that terms that do not meet this condition completely cancel each other. Accordingly, it holds T(2)=-∑α=0N-1Heq,2(α,f/fa-α)·T(5)·T(6)=-T(4)-∑α-0N-1Heq,2(α,f/fa-α)·X(α)·X(f/fa-α)=-T(3).(E.65) The result for the third order transfer function of the Volterra filter circuit16has two contributions, namely Heq,3(1)and Heq,3(2), which are given by Heq,3(1)(f0/fa,f1/fa,f2/fa)=-Heq,1(f0/fa+f1/fa+f2/famod1)·H3(f0/fa,f1/fa,f2/fa)·Heq,1(f0/fa)·Heq,1(f0/fa)·Heq,1(f2/fa).(E.65)Heq,3(2)(f0/fa,f1/fa,f2/fa)=-Heq,2(f0/fa+f1/fa+f2/famod1)·Heq,2(f0/fa,f1/fa)·Heq,1(f2/fa)-Heq,2(f1/fa+f2/famod1,f0/fa)·Heq,2(f1/fa,f2/fa)·Heq,1(f2/fa). The third order transfer function of the Volterra filter circuit16is then given by Heq,3(f0/fa,f1/fa,f2/fa)=Heq,3(1)(f0/fa,f1/fa,f2/fa)+Heq,3(2)(f0/fa,f1/fa,f2/fa) (E.67) With the technique described in equations (E.59) to (E.67), reference transfer functions Heq,ref,m(f0/fa, . . . , fm-1/fa) are determined in the frequency domain. Alternatively, the reference transfer functions may be determined based on the reference impulse responses heq,ref,m(k0, k1, k2) by a Fourier transform. The (final) filter coefficients heq,mof the Volterra filter circuit16can then be determined by a minimum square technique as described in equations (E.38) to (E.47) applied to the reference transfer functions Heq,ref,m(f0/fa, . . . , fm-1/fa). Therein, a desired structure can be imposed on the filter coefficients heq,m, e.g. a memory polynomial structure, an extended memory polynomial structure, or otherwise pruned impulse responses. With the spectral weighting function W, the spectral quality of the Volterra filter circuit16can be controlled. It has turned out that a particular high equalization accuracy for equalizing unwanted non-linear disturbances is achievable this way. It is to be understood that while the representative method(s) above is described in the context of the single non-linear electronic component12causing the non-linear distortions, the method(s) can readily be applied to several non-linear electronic components and/or to a whole non-linear electronic system comprising several non-linear electronic components that are interconnected. Accordingly, filter coefficients of the Volterra filter circuit16may be adapted such that the equalizer circuit14is configured to equalize the non-linear electronic system. In other words, the Volterra filter circuit16processes the output signal y of the non-linear electronic component12, thereby generating an equalized output signal yeqthat corresponds to the output signal y of the non-linear electronic component12, but with the non-linear distortions removed. FIG.4shows one possible implementation of the equalizer circuit14with the Volterra filter circuit16. The equalizer circuit14is established, for example, as a digital filter circuit. The Volterra filter circuit16comprises several short-length finite impulse response (FIR) filters20that are arranged in parallel. The FIR filters20each are established in hardware. For example, the FIR filters20each may comprise FPGAs and/or ASICs. Each of the short-length FIR filters20is configured to receive signal samples that are associated with the output signal y of the non-linear electronic component12(the output signal of the y of the non-linear electronic component12is the input signal of the equalizer circuit14). In the following, the output signal y of the non-linear electronic component is denoted as “filter input signal”, and the equalized output signal yeqis denoted as “filter output signal”. Each short-length FIR filter20receives a product of at least two filter input signal samples, i.e. the filter input signal associated with each short-length FIR filter20comprises a product of at least two filter input signal samples, i.e. a product x(t0/Ta-0,⋯,t0/Ta-μm-1)=∏a=0m-1x(t0/Ta-μα).(E.68) The short-length FIR filters20are each configured to determine one term of the second Volterra series as defined in equation (E.1) or (E.14), but with the impulse responses h being replaced by the determined filter coefficients heq. Therein, different FIR filters20are associated with different diagonals of the second Volterra series. In general, the number of necessary FIR filters20depends on the maximum order M of the second Volterra series and on the number of non-zero diagonals of the second Volterra series. As already explained above, the maximum order of the second Volterra series is M=3. For example, the second Volterra series may comprise D2=D3=2 non-zero diagonals. In this case, one FIR filter20is necessary for determining the first order (m=1) term of the second Volterra series. Two FIR filters20are necessary for determining the second order (m=2) term of the second Volterra series. Four FIR filters20are necessary for determining the third order (m=3) term of the third order Volterra series. Thus, in the representative example shown inFIG.4, the Volterra filter circuit16comprises seven FIR filters20. Each FIR filters20determines one term of the second Volterra series based on the filter input signal y and based on the filter coefficients heq. Thus, the output signal of each FIR filter20is associated with one term of the second Volterra series, i.e. with a certain diagonal of the second Volterra series. The output signals of all FIR filters20are summed by a summation circuit22, thereby generating the equalized output signal yeq. It has turned out that product signals as defined in equation (E.68) can be processed in a particularly resource-efficient manner by short-length FIR filters. Thus, the present disclosure provides a particularly resource-efficient equalizer circuit for equalizing non-linear systems. In some embodiments, it has turned out that the equalizer circuit14described above is capable of equalizing the filter input signal y in real time, even at high sample rates up to several 10 GHz. Certain embodiments disclosed herein utilize circuitry (e.g., one or more circuits) in order to implement protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph. It will be further appreciated that the terms “circuitry,” “circuit,” “one or more circuits,” etc., can be used synonymously herein. In an embodiment, circuitry includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof. In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof). In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein. In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation. In an embodiment, circuitry includes an implementation comprising one or more processors or portions thereof and accompanying software, firmware, hardware, and the like. In some embodiments, an equalizer circuit for equalizing a non-linear electronic system is provided. The equalizer circuit may comprise a Volterra filter circuit. In some embodiments, an electronic device comprises the equalizer circuit. In some embodiments, the equalization circuit is configured (e.g., programmed) to provide an input signal; process the input signal by the non-linear electronic system, thereby obtaining an output signal; providing a first mathematical model, wherein the first mathematical model describes the non-linear electronic system in terms of a first Volterra series; providing a second mathematical model, wherein the second mathematical model describes the Volterra filter circuit in terms of a second Volterra series; determining reference transfer functions of the Volterra filter circuit by a Pth order inverse technique based on the first Volterra series; and determining filter coefficients of the Volterra filter circuit based on the determined reference transfer functions and based on the second Volterra series. In other embodiments, the equalization circuit is configured (e.g., programmed) to carry out any one of the appended method claims. Various embodiments of the present disclosure or the functionality thereof may be implemented in various ways, including as non-transitory computer program products. A computer program product may include a non-transitory computer-readable storage medium storing applications, programs, program modules, scripts, source code, program code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and/or the like (also referred to herein as executable instructions, instructions for execution, program code, computer program instructions, and/or similar terms used herein interchangeably). Such non-transitory computer-readable storage media include all computer-readable media (including volatile and non-volatile media). Embodiments of the present disclosure may also take the form of an apparatus, system, computing device, computing entity, and/or the like executing instructions stored on computer-readable storage media to perform certain steps or operations. The computer-readable media include cooperating or interconnected computer-readable media, which exist exclusively on a processing or processor system or distributed among multiple interconnected processing or processor systems that may be local to, or remote from, the processing or processor system. However, embodiments of the present disclosure may also take the form of an entirely hardware embodiment performing certain steps or operations. Various embodiments are described above with reference to block diagrams and/or flowchart illustrations of apparatuses, methods, systems, and/or computer program instructions or program products. It should be understood that each block of any of the block diagrams and/or flowchart illustrations, respectively, or portions thereof, may be implemented in part by computer program instructions, e.g., as logical steps or operations executing on one or more computing devices. These computer program instructions may be loaded onto one or more computer or computing devices, such as special purpose computer(s) or computing device(s) or other programmable data processing apparatus(es) to produce a specifically-configured machine, such that the instructions which execute on one or more computer or computing devices or other programmable data processing apparatus implement the functions specified in the flowchart block or blocks and/or carry out the methods described herein. These computer program instructions may also be stored in one or more computer-readable memory or portions thereof, such as the computer-readable storage media described above, that can direct one or more computers or computing devices or other programmable data processing apparatus(es) to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the functionality specified in the flowchart block or blocks. The computer program instructions may also be loaded onto one or more computers or computing devices or other programmable data processing apparatus(es) to cause a series of operational steps to be performed on the one or more computers or computing devices or other programmable data processing apparatus(es) to produce a computer-implemented process such that the instructions that execute on the one or more computers or computing devices or other programmable data processing apparatus(es) provide operations for implementing the functions specified in the flowchart block or blocks and/or carry out the methods described herein. It will be appreciated that the term computer or computing device can include, for example, any computing device or processing structure, including but not limited to a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof. Accordingly, blocks of the block diagrams and/or flowchart illustrations support various combinations for performing the specified functions, combinations of operations for performing the specified functions and program instructions for performing the specified functions. Again, it should also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, or portions thereof, could be implemented by special purpose hardware-based computer systems or circuits, etc., that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions. In the foregoing description, specific details are set forth to provide a thorough understanding of representative embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the embodiments disclosed herein may be practiced without embodying all of the specific details. In some instances, well-known process steps have not been described in detail in order not to unnecessarily obscure various aspects of the present disclosure. Further, it will be appreciated that embodiments of the present disclosure may employ any combination of features described herein. Although the method and various embodiments thereof have been described as performing sequential steps, the claimed subject matter is not intended to be so limited. As nonlimiting examples, the described steps need not be performed in the described sequence and/or not all steps are required to perform the method. Moreover, embodiments are contemplated in which various steps are performed in parallel, in series, and/or a combination thereof. As such, one of ordinary skill will appreciate that such examples are within the scope of the claimed embodiments. The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about,” “approximately,” “near,” etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase “at least one of A and B” is equivalent to “A and/or B” or vice versa, namely “A” alone, “B” alone or “A and B.”. Similarly, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed. Throughout this specification, terms of art may be used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed. | 46,475 |
11942906 | DETAILED DESCRIPTION FIG.2is a transmitter200according to one embodiment of the present invention. As shown inFIG.2, the transmitter200comprises a mixer210, a harmonic impedance adjustment circuit220, a transformer230, an amplifier240, a harmonic impedance adjustment circuit250and a transformer260. The transmitter200of this embodiment can be applied to any electronic device that requires wireless communication, that is, the transmitter200receives baseband signals BB_I and BB_Q and generates corresponding output signals to an antenna for transmission. In a basic operation of the transmitter200, the mixer210mix the baseband signals BB_I and BB_Q with oscillation signals LO_I and LO_Q to generate mixed signals V_I and V_Q, respectively, wherein the mixed signals V_I and V_Q are used as a differential signal. Specifically, the mixer210can be implemented by using two mixers110and120shown inFIG.1, that is the mixer210mixes the baseband signal BB_I with the oscillation signal LO_I to generate the mixed signal V_I, and the mixer220further mixes the baseband signal BB_Q with the oscillation signal LO_Q to generate the mixed signal V_Q. Description of the prior art mentions that the image signal of the transmitter200cannot be completely eliminated due to non-ideal factors. However, in addition to the three non-ideal factors mentioned in the prior art, components behind the mixer210may also cause harmonic mixing and affect the effect of image suppression. Specifically, due to the non-ideal factors of the mixer210, and the oscillation signals LO_I and LO_Q may contain high-order frequency components due to non-ideal factors, the mixed signals V_I and V_Q will cause the generation of image signals due to the harmonic mixing in the subsequent components. Four examples are given as follows: (1) assuming that the mixed signals V_I and V_Q have harmonic components of (3*fLO+fBB) and (2*fLO), respectively, the harmonic mixing caused by the subsequent amplifier will make the subsequent signal has an image signal with a frequency of (fLO+fBB). (2) assuming that the mixed signals V_I and V_Q have harmonic components of (4*fLO) and (3*fLO−fBB) respectively, the harmonic mixing caused by the subsequent amplifier will make the subsequent signal has an image signal with a frequency of (fLO+fBB). (3) assuming that the mixed signals V_I and V_Q have harmonic components of (2*fLO−2*fBB) and (fLO-3*fBB) respectively, the harmonic mixing caused by the subsequent amplifier will make the subsequent signal has an image signal with a frequency of (fLO+fBB). (4) assuming that the mixed signals V_I and V_Q have harmonic components of (2*fLO) and (fLO−fBB) respectively, the harmonic mixing caused by the subsequent amplifier will make the subsequent signal has an image signal with a frequency of (fLO+fBB). The above-mentioned ‘fLO’ is a frequency of the oscillation signals LO_I and LO_Q, and ‘fBB’ is a frequency of the baseband signals BB_I and BB_Q. Therefore, in order to solve the above-mentioned harmonic mixing problem, this embodiment provides the harmonic impedance adjustment circuit220between the two output nodes N1and N2of the mixer210to reduce part of the harmonic components of the mixed signals of V_I and V_Q. For example, the harmonic impedance adjustment circuit220can reduce the strength of the harmonic components corresponding to 2*fLO, 3*fLOand/or 4*fLOin the mixed signals V_I and V_Q, so as to reduce the strength of the image signal generated due to the harmonic mixing. After the harmonic impedance adjustment circuit220reduces the strength of the harmonic components of the mixed signals V_I and V_Q to generate adjusted mixed signals, the transformer230and the amplifier240process the adjusted mixed signals to generate amplified signals A_I and A_Q. Then, by designing the harmonic impedance adjustment circuit250between two output nodes N3and N4of the amplifier240to reduce the strength of the harmonic components corresponding to 2*fLO, 3*fLOand/or 4*fLOof the amplified signals A_I and A_Q, the strength of the image signal generated due to the harmonic mixing can be further reduced. Finally, the amplified signals A_I and A_Q are processed by the transformer260and then transmitted to the antenna for transmission to other electronic devices. FIG.3is a diagram illustrating a harmonic impedance adjustment circuit300according to one embodiment of the present invention, wherein the harmonic impedance adjustment circuit300can be used to implement the harmonic impedance adjustment circuit220and/or harmonic impedance adjustment circuit250shown inFIG.2. For the convenience of description, the following embodiments use the harmonic impedance adjustment circuit300as the harmonic impedance adjustment circuit220for description. As shown inFIG.3, the harmonic impedance adjustment circuit300comprises two capacitors C1and C2, wherein the capacitor310is coupled/embedded between the node N1and a ground voltage, and the capacitor C2is coupled/embedded between the node N2and the ground voltage. In this embodiment, the harmonic impedance adjustment circuit300comprises an odd mode and an even mode, wherein the odd mode corresponds to the main components (differential signals) of the mixed signals V_I and V_Q, and a transmission path of the main components of the mixed signals V_I and V_Q in the odd mode can be called a differential path; and the even mode corresponds to the even-order harmonic components of the mixed signals V_I and V_Q, and a transmission path of the even-order harmonic components of the mixed signals V_I and V_Q can be called a common-mode path. Specifically, assuming that the capacitance of the capacitors310and320are both 2*C1, for the main components (differential signals) of the mixed signals V_I and V_Q in the odd mode, the harmonic impedance adjustment circuit300can be regarded as a capacitor with the capacitance C1coupled/embedded between the nodes N1and N2; and for the harmonic components of each of the mixed signals V_I and V_Q in the even mode, the harmonic impedance adjustment circuit300can be regarded a capacitor with the capacitance 2*C1coupled/embedded to the ground voltage. Therefore, by using the harmonic impedance adjustment circuit300, the impedance on the common-mode path can be greatly reduced, so as to effectively reduce the strength of the harmonic components corresponding to 2*fLOand 4*fLOin the mixed signals V_I and V_Q. FIG.4is a diagram illustrating a harmonic impedance adjustment circuit400according to another embodiment of the present invention, wherein the harmonic impedance adjustment circuit400can be used to implement the harmonic impedance adjustment circuit220and/or harmonic impedance adjustment circuit250shown inFIG.2. For the convenience of description, the following embodiments use the harmonic impedance adjustment circuit400as the harmonic impedance adjustment circuit220for description. As shown inFIG.4, the harmonic impedance adjustment circuit400comprises two capacitors410,420and an inductor430, wherein the capacitor410is coupled/embedded to the node N1and a node N5, the capacitor420is coupled/embedded between the node N2and the node N5, and the inductor430is coupled/embedded between the node N5and the ground voltage. In this embodiment, the harmonic impedance adjustment circuit400comprises an odd mode and an even mode, wherein the odd mode corresponds to the main components (differential signals) of the mixed signals V_I and V_Q, and a transmission path of the main components of the mixed signals V_I and V_Q in the odd mode can be called a differential path; and the even mode corresponds to the even-order harmonic components of the mixed signals V_I and V_Q, and a transmission path of the even-order harmonic components of the mixed signals V_I and V_Q can be called a common-mode path. Specifically, assuming that the capacitance of the capacitors410and420are both 2*C1, and the inductor430has the inductance L1, for the main components (differential signals) of the mixed signals V_I and V_Q in the odd mode, the harmonic impedance adjustment circuit400can be regarded as a capacitor with the capacitance C1coupled/embedded between the nodes N1and N2; and for the harmonic components of each of the mixed signals V_I and V_Q in the even mode, the harmonic impedance adjustment circuit400can be regarded as a capacitor with the capacitance 2*C1and an inductor with the inductance 2*L1connected in series. In this embodiment, since the capacitance of the capacitors410and420involve the main components of the mixed signals V_I and V_Q and are not suitable for arbitrary changes, the designer can mainly design the inductance L1of the inductor430to make the impedance corresponding to its oscillation frequency is greatly reduced, so as to achieve the purpose of reducing specific harmonic components. Specifically, assuming that the designer knows that the harmonic components with frequency (2*fLO2*fBB) will affect the image rejection effect, the inductance L1of the inductor430can be designed to reduce harmonic component with frequency (2*fLO−2*fBB), that is 2*fLO-2*fBB=12πL1*C1. In practice, since ‘fBB’ is much smaller than ‘fLO’, the harmonic impedance adjustment circuit400can be regarded as reducing the harmonic components of the frequency of the oscillation signals LO_I and LO_Q by two, three or four times. FIG.5is a diagram illustrating a harmonic impedance adjustment circuit500according to another embodiment of the present invention, wherein the harmonic impedance adjustment circuit500can be used to implement the harmonic impedance adjustment circuit220and/or harmonic impedance adjustment circuit250shown inFIG.2. For the convenience of description, the following embodiments use the harmonic impedance adjustment circuit500as the harmonic impedance adjustment circuit220for description. As shown inFIG.5, the harmonic impedance adjustment circuit500comprise capacitors510,520,540,550and inductors530and560, wherein the capacitor510is coupled/embedded between the node N1and a node N6, the capacitor520is coupled/embedded between the node N2and the node N6, the inductor530is coupled between the node N6and the ground voltage, the capacitor540is coupled/embedded between the node N1and a node N7, the capacitor550is coupled/embedded between the node N2and the node N7, and the inductor560is coupled/embedded between the node N7and the ground voltage. In this embodiment, the harmonic impedance adjustment circuit400comprises an odd mode and an even mode, wherein the odd mode corresponds to the main components (differential signals) of the mixed signals V_I and V_Q, and the even mode corresponds to the even-order harmonic components of the mixed signals V_I and V_Q. Specifically, assuming that the capacitance of the capacitors510,520,540and550are all C1, the inductance of the inductor530is L1, and the inductance of the inductor560is L2, for the main components (differential signals) of the mixed signals V_I and V_Q in the odd mode, the harmonic impedance adjustment circuit500can be regarded as a capacitor with the capacitance C1coupled/embedded between the nodes N1and N2; and for the harmonic components of each of the mixed signals V_I and V_Q in the even mode, the harmonic impedance adjustment circuit500can be regarded as two sets of capacitor and inductor connected in series (one is a capacitor with the capacitance C1and an inductor with the inductance 2*L1connected in series, and the other one is a capacitor with the capacitance C1and an inductor with the inductance 2*L2connected in series). In this embodiment, since the capacitance of the capacitors510,520,540and550involve the main components of the mixed signals V_I and V_Q and are not suitable for arbitrary changes, the designer can mainly design the inductance L1of the inductor530and the inductance L2of the inductor540to make the impedance corresponding to its oscillation frequency is greatly reduced, so as to achieve the purpose of reducing specific harmonic components. Specifically, assuming that the designer knows that the harmonic components with frequency (2*fL0-2*fBB) and frequency (3*fLO−fBB) will affect the image rejection effect, the inductance L1of the inductor530can be designed to reduce harmonic component with frequency (2*fLO−2*fBB), and the inductance L2of the inductor560can be designed to reduce harmonic component with frequency (3*fLO−fBB). In the embodiment ofFIG.2, the step of reducing harmonic components is performed by using the harmonic impedance adjustment circuit220coupled between the terminals N1and N2, and the harmonic impedance adjustment circuit250coupled between the terminals N3and N4; and the two output paths of the mixer210do not have harmonic filters to avoid affecting the main components of the mixed signals V_I and V_Q. It should be noted that the transmitter200shown inFIG.2is only an example for illustration, and is not a limitation of the present invention. In other embodiments of the present invention, the number/position of the transformers may be changed, or the harmonic impedance adjustment circuit250may be removed from the transmitter200. Briefly summarized, in the transmitter of the present invention, by setting a harmonic impedance adjustment circuit to reduce the strength of specific harmonic components, the problem of image signals generated by these harmonic signals due to harmonic mixing can be effectively improved. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 13,765 |
11942907 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. The terms used in the disclosure are selected based on general terms currently widely used in the art in consideration of functions regarding the disclosure, but the terms may vary according to the intention of those of ordinary skill in the art, precedents, or new technology in the art. Also, some terms may be arbitrarily selected by the Applicant, and in this case, the meaning of the selected terms will be described in the detailed description of the disclosure. Thus, the terms used herein should not be construed based on only the names of the terms but should be construed based on the meaning of the terms together with the description throughout the disclosure. Throughout the specification, when a portion “includes” an element, unless otherwise described, another element may be further included, rather than the presence of other elements being excluded. The term used in the example embodiments such as “unit” or “module” indicates a unit for processing at least one function or operation, and may be implemented in hardware or software, or in a combination of hardware and software. It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Furthermore, the connecting lines, or connectors shown in the various figures presented are intended to represent functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device. Example embodiments of the disclosure will be described in detail in order to fully convey the scope of the disclosure and enable one of ordinary skill in the art to embody and practice the disclosure. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. FIG.1is a block diagram showing a configuration of an amplifier100according to an example embodiment. Referring toFIG.1, the amplifier100may include an input circuit110, a biasing circuit120, and an output circuit130. In the amplifier100shown inFIG.1, only components related to the example embodiments are shown. Therefore, it is apparent to those skilled in the art that the amplifier100may further include other general-purpose components in addition to the components shown inFIG.1according to other embodiments. The amplifier100may be a device that increases an input signal at a constant rate and may be implemented in the form of a chip. For example, the amplifier100may be implemented in the form of the chip and mounted on various mobile devices such as a mobile phone and a smart speaker. The amplifier100may be implemented as an independent device and used in connection with an external device such as a speaker. Also, the amplifier100may be a class-AB amplifier. The input circuit110may convert the input signal into a current. The input signal may mean a signal input to the input circuit110from the outside. For example, the input signal may be a voltage, but is not limited thereto. The input circuit110may convert a voltage input to the input circuit110into a current. There may be a plurality of input signals. For example, the number of input signals may be two or four, but is not limited thereto. In other words, the amplifier100may receive 2 inputs or 4 inputs. The input circuit110will be described later in detail with reference toFIG.2. According to another example embodiment, the number of input signal may be different than two or four. The biasing circuit120may reduce a voltage change of an output end of the input circuit110. According to an example embodiment, the output end may be the output node of the input circuit110. The output end of the input circuit110may refer to a point at which the converted current is output from the input circuit110and is input to the biasing circuit120. The biasing circuit120may reduce the voltage change of the output end of the input circuit110and may reduce an output swing of the output end of the input circuit110. However, the disclosure is not limited thereto, and as such, according to another example embodiment, the output end of the input circuit110may refer to a point at which the converted current is output from the input circuit110and is input to a circuit different from the biasing circuit120. According to another example embodiment, However, the disclosure is not limited thereto, and as such, according to another example embodiment, the output end of the input circuit110may refer to a point at which the converted current is output from the input circuit110and is input to a circuit different from the biasing circuit120. As such, the converted current output from the input circuit110is input to the biasing circuit120through an intermediate circuit. The output circuit130may include at least one switching element for reducing the voltage change of the output end of the input circuit110and may provide an output signal. The at least one switching element may reduce the voltage change of the output end of the input circuit110and may reduce the output swing of the output end of the input circuit110. The switching element may include a switching element such as a bipolar junction transistor (BJT), a metal-oxide-semiconductor field effect transistor (MOSFET), but is not limited to types of the listed switching elements. In addition, the output circuit130may mean an output end of the class-AB amplifier. The output circuit130will be described later in detail with reference toFIG.5. The at least one switching element of the output circuit130may be connected to the biasing circuit120. The biasing circuit120may be connected to the at least one switching element to form a feedback loop for reducing the voltage change of the output end of the input circuit110. The biasing circuit120will be described later in detail with reference toFIG.3. In the case of designing the amplifier100, when the output swing of a specific point increases, a nonlinearity of the amplifier100increases and a distortion increases, and thus it is desirable to reduce the output swing of the specific point when designing the amplifier100. For instance, when the voltage change at a specific point in the amplifier increases, a nonlinearity of the amplifier100increases and a distortion increases. The amplifier100according to the disclosure may include the biasing circuit120for reducing the voltage change of the output end of the input circuit110, thereby reducing the output swing of the output end of the input circuit110. Accordingly, the voltage of the output end may be stabilized, and the linearity of the amplifier100may increase. FIG.2is a diagram illustrating an amplifier200according to an example embodiment. Referring toFIG.2, the amplifier200may include an input circuit210and an output circuit220. The amplifier200, the input circuit210, and the output circuit220ofFIG.2may respectively correspond to the amplifier100, the input circuit110, and the output circuit130ofFIG.1, and thus redundant descriptions are omitted. Meanwhile, inFIG.2, the biasing circuit120ofFIG.1is omitted, but the disclosure is not limited thereto. As such according to another example embodiment, the biasing circuit120may be added the structure inFIG.1. According to an example embodiment, the unlabeled elements of the output circuit220may correspond to the respective labeled elements in the output circuit520inFIG.5. The input circuit210may include an input module211. According to an example embodiment, the input module211may convert an input signal into a current. According to an example embodiment, the input module211may be a transconductor, a Gm cell, or the like that converts a voltage into a current. According to an example embodiment, the input signal may include a first input signal in1and a second input signal in2. According to an example embodiment, each of the first input signal in1and the second input signal in may be input to the input module211and converted into the current, and the converted current may be provided to the output circuit220and a biasing circuit. The first input signal in1and the second input signal in may be differential signals. For example, the input module211may convert differential voltages by the first input signal in1and the second input signal in into the current. The input module211may control an output current based on transconductance (gm). The input module211may include a switching element. For example, the input module211may be configured as one or more N-channel metal oxide semiconductor (NMOS) transistors. As another example, the input module211may be configured as one or more P-channel metal oxide semiconductor (PMOS) transistors. As another example, the input module211may be configured as a combination of the NMOS and PMOS transistors. However, the disclosure is not limited thereto, and as such, according to another example embodiment, an internal structure of the input module211may be constructed as necessary. The input circuit210may further include a correction circuit212. The correction circuit212may provide current to the output circuit220or the biasing circuit. According to another example embodiment, the correction circuit212may provide current to the output circuit220and the biasing circuit. Each of the first input signal in1and the second input signal in2may be input to the input module211and converted into the current, and the converted current may be provided to the correction circuit212. The correction circuit212may correct a transconductance of the switching element of the input module211. For example, when the first input signal in1is applied as a gate voltage of one of the PMOS transistors of the input module211, and the second input signal in2is applied as a gate voltage of another of the PMOS transistors of the input module211, the correction circuit212may increase or decrease the transconductance of the PMOS transistors. According to an example embodiment, the input circuit210may convert and output an input signal into a differential input current. The differential input current may include a first signal Gmin1and a second signal Gmin2, and the first signal Gmin1and the second signal Gmin2may refer to currents in a differential relationship with each other. The first signal Gmin1and the second signal Gmin2may be provided to the output circuit220and the biasing circuit. The differential input current may refer to two currents having a phase difference of 180° degrees. In other words, the differential input current may be a current having an opposite polarity, or a current in which a same amount decreases and increases from an arbitrary reference current. For example, the differential input current may mean the first signal Gmin1and the second signal Gmin2within the range of −3 μA to 3 μA with respect to 0 μA. In addition, the differential input current may mean the second signal Gmin2and the first signal Gmin1within the range of 1 μA to 3 μA with respect to 2 μA. As another example, the differential input current may mean the first signal Gmin1and the second signal Gmin2swinging within the range of −3 μA to 3 μA with respect to 0 μA. In addition, the differential input current may mean the second signal Gmin2and the first signal Gmin1swinging within the range of 1 μA to 3 μA with respect to 2 μA. The correction circuit212may include switching elements Mi1, Mi2, Mi3, Mi4, Mi5, Mi6, and Mi7. The switching element Mil may be connected to a power voltage VDD. The switching element Mi2may be connected to the power voltage VDD. The switching element Mi3may be connected to the switching element Mil. The switching element Mi4may be connected to the switching element Mi2. The switching element Mil and the switching element Mi2may be connected to each other. The switching element Mi3and the switching element Mi4may be connected to each other. The switching element Mil and the switching element Mi3may form a cascode, and the switching element Mi2and the switching element Mi4may form a cascode. A proximity effect may be overcome by using several switching elements Mi1, Mi2, Mi3, and Mi4in the correction circuit212. The switching element Mi5may be connected to the switching element Mi3. The switching element Mi6may be connected to the switching element Mi4. The switching element Mi7may be connected to the switching element Mi5. The switching element Mi5and the switching element Mi6may be connected to each other. The switching element Mi5and the switching element Mi6may be connected to the input module211. A node Ni4between the switching element Mi5, the switching element Mi6and the switching element Mil may be connected to the input module211. The node Ni4may be connected to the input module211and thus the correction circuit212may receive the converted current from the input module211. A node Ni5between the switching element Mi3and the switching element Mi5may be connected to the output circuit220. A node Ni6between the switching element Mi4and the switching element Mi5may be connected to the output circuit220. The input circuit210may be connected to the output circuit220, and thus the first signal Gmin1and the second signal Gmin2may be transmitted to the output circuit220. For example, the first signal Gmin1may pass through the node Ni6, and the second signal Gmin2may pass through the node Ni5. The correction circuit212may include the NMOS transistors Mi5, Mi6, and Wand the PMOS transistors Mi1, Mi2, Mi3, and Mi4. A source of the switching element Mil and a source of the switching element Mi2may be connected to the power voltage VDD. A gate of the switching element Mil and a gate of the switching element Mi2may be connected to each other. A source of the switching element Mi3may be connected to a drain of the switching element Mil. A source of the switching element Mi4may be connected to a drain of the switching element Mi2. A gate of the switching element Mi3and a gate of the switching element Mi4may be connected to each other. The switching element Mil and the switching element Mi3may form a cascode, and thus the same type of switching element may be used. In addition, the switching element Mi2and the switching element Mi4may form a cascode, and thus the same type of switching element may be used. A drain of the switching element Mi5may be connected to a drain of the switching element Mi3, and a drain of the switching element Mi6may be connected to a drain of the switching element Mi4. A gate of the switching element Mi5and a gate of the switching element Mi6may be connected to each other. A drain of the switching element Mi7may be connected to a source of the switching element Mi5, and a source of the switching element Mi7may be connected to a ground. A node Ni4between the source of the switching element Mi5and the drain of the switching element Mi7may be connected to the output end of the input module211. A source of the switching element Mi6may be connected to the output end of the input module211. A node Nis between the drain of the switching element Mi3and the drain of the switching element Mi5may be connected to the output circuit220. A node Nis between the drain of the switching element Mi4and the drain of the switching element Mi5may be connected to the output circuit220. FIG.3is a diagram illustrating an operation of an amplifier300including a biasing circuit310according to an example embodiment. Referring toFIG.3, the amplifier300may include the biasing circuit310and an output circuit320. The amplifier300and the output circuit320ofFIG.3respectively correspond to the amplifier200and the output circuit220ofFIG.2, and the biasing circuit310ofFIG.3corresponds to the biasing circuit120ofFIG.1, and thus the redundant description is omitted. Although the input circuit210and some elements of the output circuit220fromFIG.2are omitted in the illustration inFIG.3, they may be added. The first signal Gmin1and the second signal Gmin2may refer to current converted from the input circuit. The output circuit320may include a first switching element M3. The first switching element M3may be connected to an output end of the input circuit210and may reduce a voltage change of a node N1between the first switching element M3and the output end of the input circuit210. The first switching element M3may be stacked on a switching element M1. The switching element M1and the first switching element M3may form a cascode, and an output swing of the node N1may be reduced due to a cascode shielding property. The biasing circuit310may include a first amplification circuit311. The first amplification circuit311may amplify a voltage of the output end of the input circuit. For example, the first amplification circuit311may amplify a voltage of the node N1connected to the output end of the input circuit210. The first amplification circuit311may be connected to the first switching element M3to form a feedback loop for reducing the voltage change of the output end of the input circuit210. The feedback loop connected to the first amplification circuit311and the first switching element M3may reduce the voltage change of the node N1between the first switching element M3and the output end of the input circuit210. The first amplifier circuit311may amplify the voltage of the node N1by using the voltage of the node N1as an input. A current flowing through the first switching element M3may change based on the amplified voltage of the node N1. The voltage of the node N1may change according to a change in the current flowing through the first switching element M3. The voltage of the node N1may have a reduced voltage change due to the feedback loop. An input end of the first amplifier circuit311may be connected to the node N1between the first switching element M3and the output end of the input circuit210, and the output end of the first amplifier circuit311and the first switching element M3may be connected to form the feedback loop. For example, when the first switching element M3is an NMOS, the input end of the first amplification circuit311and the source of the first switching element M3are connected, and the output end of the first amplification circuit311and the gate of the first switching element M3may be connected to form the feedback loop. The first amplifier circuit311may amplify the voltage of the node N1by using the voltage of the node N1as an input. The current flowing from the drain to the source of the first switching element M3may change by the amplified voltage of the node N1. Accordingly, the voltage of the source of the first switching element M3may change. The feedback loop may reduce a voltage change of the source of the first switching element M3. The first amplification circuit311may increase the transconductance of the first switching element M3. The feedback loop connected to the first amplification circuit311and the first switching element M3may increase the transconductance of the first switching element M3. The feedback loop may be formed to be a transconductance (gm) boosting circuit. The transconductance (gm) boosting circuit may be of the same or similar form as a gain boosting circuit. The transconductance (gm) boosting circuit may reduce an output impedance. The feedback loop may be a negative feedback loop, and a voltage inside the feedback loop may be stabilized. According to an example embodiment, even though a current is input into the feedback loop, the voltage in the feedback loop may be stabilized, which may correspond to a current change but no voltage change. Thus, the output impedance may be reduced. When the output impedance is reduced, an increased current change occurs at the same voltage change, which may mean that the transconductance increases. The transconductance may increase to a range. According to an example embodiment, the range may be a preset range, which may be a range designated by a user, a range required when designing the amplifier300, etc. The feedback loop may increase the transconductance of the first switching element M3. The increase in the transconductance may result in a reduction in the voltage change of the node N1, and a total harmonic distortion (THD) may be reduced. When the THD is reduced, a linearity of the amplifier300may be improved and a distortion may be reduced. The first amplification circuit311may receive a first operating voltage Vbias1and a voltage of the output end of the input circuit210. For example, a positive input end of the first amplification circuit311may receive the first operating voltage Vbias1, and a negative input end may receive the voltage of the node N1between the first switching element M3and the output end of the input circuit210, but the disclosure is not limited thereto. The first operating voltage Vbias1may be a voltage applied to the first amplification circuit311so as to set an operating point of the first amplification circuit311. The first operating voltage Vbias1may be a DC voltage or a common mode voltage. The first operating voltage Vbias1may be applied from outside or inside the amplifier300. The first amplification circuit311may bias a first bias voltage of the first switching element M3based on the first operating voltage Vbias1and the voltage of the output end of the input circuit210. The first bias voltage may mean a voltage applied to the first switching element M3to set the operating point of the first switching element M3. The first bias voltage may be the DC voltage. When the first switching element M3is an NMOS transistor, the first bias voltage may be determined according to a gate voltage of the first switching element M3. Because an output of the first amplification circuit311and the gate of the first switching element M3are connected to each other in the feedback loop, the first bias voltage may be biased by the feedback loop. The first amplifier circuit311may amplify the voltage of the node N1by using the first operating voltage Vbias1and the voltage of the node N1as inputs. The current flowing through the first switching element M3may change by the amplified voltage of the node N1. The voltage of the node N1may change due to a change in the current flowing through the first switching element M3. The voltage change of the node N1due to the current change may be reduced by the feedback loop and the first operating voltage Vbias1. For example, the voltage of the node N1may be biased to the first operating voltage Vbias1by the feedback loop. A stability problem of switching elements may arise when the first bias voltage of the first switching element M3is biased in the form of a cascode by stacking several diode type switching elements between a power voltage or ground in a single power source and both power sources. When a minor change in the power voltage occurs, operating points of the switching elements may change, and the switching elements may be sensitive to a process voltage temperature (PVT). The first bias voltage of the first switching element M3may be easily set through the first operating voltage Vbias1and the feedback loop that is a negative feedback. In addition, the first switching element M3may be insensitive to PVT because the first bias voltage may be easily set. The biasing circuit310may reduce a voltage change provided from a differential input current. The voltage provided from the differential input current may mean a voltage provided from the differential input current to the input of the first amplification circuit311. The first amplification circuit311may amplify the voltage provided from the first signal Gmin1by using the voltage of the node N1that is the voltage provided from the first signal Gmin1as an input. The current flowing through the first switching element M3may change by the voltage provided from the amplified first signal Gmin1. The voltage change may be reduced by the feedback loop and the first operating voltage Vbias1in the voltage provided from the first signal Gmin1due to the current change. In other words, the voltage change of the node N1which is the voltage provided from the first signal Gmin1may be reduced. According to an example embodiment, the output circuit320may include switching elements M2and M4and the connection of the gates of the switching elements M1, M2and M4may be connected to a bias voltage applied to each of switching elements so as to set an operating point of each of the switching elements. FIG.4is a diagram illustrating an amplifier400including a first amplification circuit411and a second amplification circuit412according to an example embodiment. Referring toFIG.4, the amplifier400may include a biasing circuit410and an output circuit420. The biasing circuit410may include the first amplification circuit411and the second amplification circuit412. The amplifier400, the biasing circuit410, the output circuit420, and the first amplification circuit411ofFIG.4respectively correspond to the amplifier300, the biasing circuit310, the output circuit320, and the first amplification circuit311ofFIG.3, and thus redundant descriptions are omitted. Although the input circuit210and some elements of the output circuit220inFIG.2are omitted inFIG.4, they may be added. The first signal Gmin1and the second signal Gmin2may refer to current converted from the input circuit210. The output circuit420may include a second switching element M4. The second switching element M4may be connected to an output end of the input circuit210, and may reduce a voltage change of a node N2between the second switching element M4and the output end of the input circuit210. The switching element M2and the second switching element M4may form a cascode. An output swing of the node N2may be reduced due to a cascode shielding property. The first switching element M3and the second switching element M4may be different types of switching elements. For example, when the first switching element M3is an NMOS transistor, the second switching element M4may be a PMOS transistor. In addition, when the first switching element M3is a PMOS transistor, the second switching element M4may be an NMOS transistor, but is not limited thereto. The biasing circuit410may include a second amplification circuit412. The second amplification circuit412may amplify a voltage of the output end of the input circuit210. For example, the second amplification circuit412may amplify the voltage of the node N2connected to the second amplification circuit412. The first amplification circuit411and the second amplification circuit412may be different from each other. The types of switching elements included in the first amplification circuit411and the second amplification circuit412may be different from each other. In addition, a connection relationship between the switching elements included in the first amplification circuit411and the second amplification circuit412may be different from each other. For example, when the first amplification circuit411includes an NMOS transistor and a PMOS transistor, a switching element corresponding to the NMOS transistor of the first amplification circuit411may change from the second amplification circuit412to the PMOS transistor. A switching element corresponding to the PMOS transistor of the first amplification circuit411may change to the NMOS transistor in the second amplification circuit412. The first amplification circuit411may be connected to the first switching element M3to form a feedback loop for reducing the voltage change of the output end of the input circuit210. The second amplification circuit412may be connected to the second switching element M4to form the feedback loop for reducing the voltage change of the output end of the input circuit210. A feedback loop connected to the second amplification circuit412and the second switching element M4may reduce a voltage change of the node N2between the second switching element M4and the output end of the input circuit210. The second amplification circuit412may amplify the voltage of the node N2by using the voltage of the node N2as an input. A current flowing through the second switching element M4may change based on the amplified voltage of the node N2. The voltage of the node N2may change according to a change in the current flowing through the second switching element M4. The voltage change of the node N2may be reduced based on the feedback loop connected to the second amplification circuit412and the second switching element M4. The feedback loop connected to the first switching element M3and the feedback loop connected to the second switching element M4may reduce voltage changes of the node N1and the node N2, respectively. An input end of the second amplification circuit412may be connected to the node N2between the second switching element M4and the output end of the input circuit210, and an output end of the second amplification circuit412and the second switching element M4may be connected to form the feedback loop. For example, when the second switching element M4is the PMOS transistor, the input end of the second amplification circuit412and a source of the second switching element M4may be connected to each other, and the output end of the second amplification circuit412and a gate of the second switching element M4may be connected to form the feedback loop. The feedback loop connected to the second switching element M4may reduce a voltage change of the source of the second switching element M4. The second amplification circuit412may increase a transconductance of the second switching element M4. The feedback loop connected to the second switching element M4may increase the transconductance of the second switching element M4. The feedback loop connected to the second switching element M4may be formed to be a transconductance (gm) boosting circuit. The feedback loop connected to the second switching element M4may increase the transconductance of the second switching element M4, and the feedback loop connected to the first switching element M3may increase the transconductance of the first switching element M3. The second amplification circuit412may receive a second operating voltage Vbias3and a voltage of an output end of the input circuit210. For example, a positive input end of the second amplification circuit412may receive the voltage of the node N2between the second switching element M4and the output end of the input circuit210, and a negative input end may receive the second operating voltage Vbias3, but the disclosure is not limited thereto. The second operating voltage Vbias3may be a voltage applied to the second amplification circuit412so as to set an operating point of the second amplification circuit412. The second operating voltage Vbias3may be a DC voltage or a common mode voltage. The second operating voltage Vbias3may be applied from outside or inside the amplifier400. The second operating voltage Vbias3and the first operating voltage Vbias1may be the same or may have a differential relationship, but are not limited thereto. For example, both the first operating voltage Vbias1and the second operating voltage Vbias3may be 3 mV. As another example, the first operating voltage Vbias1and the second operating voltage Vbias3may be +3 mV and −3 mV, respectively. The second amplification circuit412may bias a second bias voltage of the second switching element M4based on the second operating voltage Vbias3and the voltage of the output end of the input circuit. The second bias voltage may mean a voltage applied to the second switching element M4so as to set the operating point of the second switching element M4. The second bias voltage may be a DC voltage. When the second switching element M4is a PMOS transistor, the second bias voltage may be determined according to a gate voltage of the second switching element M4. Because an output of the second amplification circuit412and a gate of the second switching element M4are connected to each other, the second bias voltage may be biased by the feedback loop connected to the second switching element M4. The second amplification circuit412may amplify the voltage of the node N2by using the second operating voltage Vbias3and the voltage of the node N2as inputs. The current flowing through the second switching element M4may change based on the amplified voltage of the node N2. The voltage of the node N2may change according to a change in the current flowing through the second switching element M4. The voltage change of the node N2due to the current change may be reduced by the feedback loop connected to the second switching element M4and the second operating voltage Vbias3. For example, the voltage of the node N2may be biased to the second operating voltage Vbias3based on the feedback loop connected to the second switching element M4. According to an example embodiment, the connection of the gates of the switching elements M1and M2may be connected to a bias voltage applied to each of switching elements so as to set an operating point of each of the switching elements. FIG.5is a diagram illustrating an example of a circuit diagram of an amplifier500according to an example embodiment. Referring toFIG.5, the amplifier500may include a biasing circuit510and an output circuit520. The biasing circuit510may include a first amplification circuit511. The amplifier500, the biasing circuit510, the output circuit520, and the first amplification circuit511ofFIG.5respectively correspond to the amplifier400, the biasing circuit410, and the output circuit420, and the first amplification circuit411ofFIG.4, and thus redundant descriptions are omitted. Although the input circuit210ofFIG.2is omitted in the illustration inFIG.5, it may be added. The first signal Gmin1and the second signal Gmin2may mean current converted from the input circuit210. The first amplification circuit511may include switching elements Mb1, Mb2, Mb3, and Mb4and a current source Ib. The switching element Mb1may be connected to the power voltage VDD. The switching element Mb2may be connected to the power voltage VDD. The switching element Mb1and the switching element Mb2may be connected to each other. The switching element Mb3may be connected to the switching element Mb1. A node Nb1between the switching element Mb1and the switching element Mb2may be connected to a node Nb2between the switching element Mb1and the switching element Mb3. The switching element Mb4may be connected to the switching element Mb2. The switching element Mb1and the switching element Mb2are current mirrors and may serve as current sources. The switching element Mb3may be connected to the first operating voltage Vbias1. The switching element Mb4may be connected to the node N1between an output end of the first signal Gmin1and the first switching element M3. A node Nb4between the switching element Mb2and the switching element Mb4may be connected to the first switching element M3to form a feedback loop. The switching element Mb3may amplify the first operating voltage Vbias1. The switching element Mb4may amplify a voltage of an output end of the first signal Gmin1. The current source Ibmay be connected between a node Nb3between the switching element Mb3and the switching element Mb4and a ground GND. The current source Ibmay provide a bias current Ibto the first amplification circuit511and the output circuit520. The first amplification circuit511may include NMOS transistors Mb3and Mb4and PMOS transistors Mb1and Mb2. A source of the switching element Mb1and a source of the switching element Mb2may be connected to the power voltage VDD. A gate of the switching element Mb1and a gate of the switching element Mb2may be connected to each other. The gate of the switching element Mb1may be connected to a drain of the switching element Mb1. A drain of the switching element Mb3may be connected to the drain of the switching element Mb1. A gate of the switching element Mb3may be connected to the first operating voltage Vbias1, and a source of the switching element Mb3may be connected to the current source Ib. A drain of the switching element Mb4may be connected to a drain of the switching element Mb2, and a source of the switching element Mb4may be connected to the current source Ib. A drain of the switching element Mb4may be connected to the first switching element M3, and a gate of the switching element Mb4may be connected to the node N1to form the feedback loop. The current source Ibmay be connected to the source of the switching element Mb3and the source of the switching element Mb4, and may be connected to the ground GND. The output circuit520may include the first switching element M3, the second switching element M4, a third switching element Mo3, a fourth switching element Mo1, and switching elements M1, M2, Mo2, Mo4, Mo5, and Mo6. The fourth switching element Mo1may be connected to the power voltage VDD. The third switching element Mo3may be connected to the fourth switching element Mo1. The switching element Mo2may be connected to the power voltage VDD. The switching element Mo2may be connected to an output signal OUT. The switching element Mo2may be connected to the fourth switching element Mo1and the third switching element Mo3. The switching element Mo2may compensate for a frequency characteristic of the amplifier500. The first switching element M3may be connected in parallel with the third switching element Mo3. The switching element M2may be connected in parallel with the third switching element Mo3and the first switching element M3. The switching element M1may be connected to the first switching element M3, and the second switching element M4may be connected to the switching element M2. The switching element M1and the first switching element M3may form a cascode, and the switching element M2and the second switching element M4may form a cascode. The cascade may be formed such that output swings of the node N1between the switching element M1and the first switching element M3and the node N2between the switching element M2and the second switching element M4may be reduced. The switching element Mo4may be connected to the switching element M1in parallel, and may be connected to the second switching element M4in parallel. One end of the switching element Mo5may be connected to the switching element Mo4, and the other end of the switching element Mo5may be connected to the ground GND. The switching element Mo6may be connected to a node N3between the second switching element M4and the switching element M1. The switching element Mo6may be connected to the ground GND. The switching element Mo6may be connected to the output signal OUT. The switching element Mo6may compensate for a frequency characteristic of the amplifier500. The node N1between the first switching element M3and the switching element M1may be connected to the first signal Gmin1. The node N2between the second switching element M4and the switching element M2may be connected to the second signal Gmin2. The output circuit520may include NMOS transistors M1, M3, Mo4, Mo5, and Mo6and PMOS transistors M2, M4, Mo1, Mo2, and Mo3. A source of the fourth switching element Mo1may be connected to the power voltage VDD, and a source of the third switching element Mo3may be connected to a drain of the fourth switching element Mot A source of the switching element Mo2may be connected to the power voltage VDD. A gate of the switching element Mo2may be connected to a drain of the third switching element Mo3, and a drain of the switching element Mo2may be connected to the output signal OUT. The switching element Mo2may be connected to the output signal OUT to compensate for the frequency characteristic of the amplifier500. The drain of the first switching element M3may be connected to the drain of the third switching element Mo3, and the source of the switching element M2may be connected to the drain of the third switching element Mos. The drain of the switching element M1may be connected to the source of the first switching element M3, and the source of the first switching element M3and the drain of the switching element M1may be connected to the first signal Gmin1. The source of the second switching element M4may be connected to the drain of the switching element M2, and the source of the second switching element M4and the drain of the switching element M2may be connected to the second signal Gmin2. The first switching element M3, the second switching element M4, the switching element M1, and the switching element M2may form a mesh structure. The mesh structure may reduce a voltage change of the source of the first switching element M3. Also, the mesh structure may reduce a voltage change of the source of the second switching element M4. The drain of the switching element Mo4may be connected to the source of the switching element M1and the drain of the second switching element M4. The drain of the switching element Mo5may be connected to the source of the switching element Mo4, and the source of the switching element Mo5may be connected to the ground GND. The drain of the switching element Mo6is connected to the output signal OUT, the gate of the switching element Mo6may be connected to the drain of the second switching element M4, and the source of the switching element Mo6may be connected to the ground GND. The switching element Mo6may be connected to the output signal OUT, thereby compensating for the frequency characteristic of the amplifier500. A gate of the first switching element M3may be connected to the first amplification circuit511and the node N1may be connected to the first amplification circuit511to form the feedback loop. According to an example embodiment the connection of the gates of the fourth switching element Mo1, the third switching element Mo3, and the switching elements M1, M2, Mo4, and Mo5may be connected to a bias voltage applied to each of switching elements so as to set an operating point of each of the switching elements. However, the disclosure is not limited thereto. The source of the first switching element M3may be connected to the input end of the first amplification circuit511, and the gate of the first switching element M3may be connected to the output end of the first amplification circuit511to form the feedback loop. The feedback loop connected to the first switching element M3may bias a first bias voltage of the first switching element M3and reduce a voltage change applied to the source of the first switching element M3. In the output circuit520, a gate of the second switching element M4may be connected to an output end of a second amplification circuit which is a circuit of a different type from the first amplification circuit511to form the feedback loop. The feedback loop connected to the second switching element M4may bias a second bias voltage of the second switching element M4and reduce a voltage change applied to the source of the second switching element M4. The output circuit520may further include capacitors Cc1and Cc2that increase a bandwidth of the output signal OUT. The capacitors Cc1and Cc2may be used as compensation capacitors. The capacitor Cc1may be connected between the node Not between the third switching element Mo3and the fourth switching element Mo1and the output end of the output circuit. The third switching element Mo3may be connected in parallel to the first switching element M3and the second switching element M4. The third switching element Mo3may be connected in parallel to the switching element M1and the switching element M2. In addition, the third switching element Mo3may be connected to the capacitor Col. The fourth switching element Mo1may be connected to the third switching element Mo3and the switching element Mo2. Further, the fourth switching element Mo1may be connected to the capacitor Cc1. When the third switching element Mo3and the fourth switching element Mo1are PMOS transistors, the capacitor Cc1may be connected to the drain of the third switching element Mo3and the source of the fourth switching element Mo1, and may be connected to the output signal OUT. When the capacitor Cc1is directly connected to the output of the input circuit, the capacitor Cc1may operate as a feedforward path, thereby forming a positive zero. The positive zero may refer to a situation in which as a signal given at a compensation front end goes to a high frequency, more components directly pass through the capacitor Cc1such that a phase of the signal is not reversed and the signal is transmitted. The third switching element Mo3may be connected between the output end of the input circuit and the capacitor Cc1, and thus the capacitor Cc1may not be directly connected to an output of the input circuit, and no positive zero may be formed. In addition, when the third switching element Mo3is a PMOS transistor, the capacitor Cc1is connected to the source of the third switching element Mo3, and thus a current may be buffering due to an effect of a common gate amplifier. Accordingly, the bandwidth of the output signal OUT may increase, and a frequency compensation may be facilitated. The capacitor Cc2may perform the same role as the capacitor Cc1. The capacitor Cc2may be connected between the node No2between the switching element Mo4and the switching element Mo5and the output end of the output circuit. The switching element Mo4may be connected in parallel to the first switching element M3and the second switching element M4. The switching element Mo4may be connected in parallel to the switching element M1and the switching element M2. In addition, the switching element Mo4may be connected to the capacitor Cc2. The switching element Mo5may be connected to the switching element Mo4and the switching element Mos. One end of the switching element Mo5may be connected to the ground GND, and the other end may be connected to the capacitor Cc2. When the switching element Mo4and the switching element Mo5are NMOS transistors, the capacitor Cc2may be connected to the drain of the switching element Mo5and the source of the switching element Mo4, and may be connected to the output signal OUT. The first switching element M3may include either NMOS transistor or PMOS transistor, and the second switching element M4may include a switching element of a different type from the type of the first switching element M3. For example, when the first switching element M3is an NMOS transistor, the second switching element M4may be a PMOS transistor. The first switching element M3, the switching element M2, the second switching element M4, and the switching element M1may be formed in a mesh structure. The first switching element M3is cascoded to the switching element M1. When the switching element M1is an NMOS transistor, the first switching element M3may be an NMOS transistor. The second switching element M4is cascoded to the switching element M2. When the switching element M2is a PMOS transistor, the second switching element M4may be a PMOS transistor. The mesh structure may reduce voltage changes of the nodes N1and N2to which the mesh structure and the output end of the input circuit are connected due to a cascode shielding property. In addition, the mesh structure may reduce the output swing of the nodes N1and N2. Although,FIG.5illustrates a mesh structure with four switching elements, the disclosure is not limited thereto, and as such, according to another example embodiment, the number of switching elements within the mesh structure may different than four. For instance, the number of switching elements within the mesh structure may be greater than four or less than four. In the output circuit520, the fourth switching element Mo1, the third switching element Mo3, the switching element M2, and the switching element Mo2may form a translinear loop to perform a rail-to-rail output. In addition, the switching element Mo4, the switching element Mo5, the switching element M1, and the switching element Mo6may form the translinear loop to perform the rail-to-rail output. InFIG.5, the circuit configuration of the amplifier500according to an example embodiment is shown, but it is generally understood by those skilled in the art that various combinations of NMOS transistor or PMOS transistor forming each switching element may be configured according to modifications of other example embodiment. FIG.6is a diagram illustrating a circuit diagram of an amplifier600including a first circuit610and a second circuit620according to an example embodiment. Referring toFIG.6, the amplifier600may include the first circuit610and the second circuit620. The first circuit610may include a first input circuit611, a first biasing circuit612, and a first output circuit613. The first circuit610may output a first output signal OUT1, and the first output signal OUT1may refer to an output signal output from the first output circuit613. Meanwhile, the amplifier600, the first biasing circuit612, the first output circuit613, and the first amplification circuit614ofFIG.6respectively correspond to the amplifier500, the biasing circuit510, the output circuit520, and the first amplification circuit511ofFIG.5, and the first input circuit611ofFIG.6corresponds to the input circuit210ofFIG.2, and thus redundant descriptions are omitted. For instance, the unlabeled elements of the input circuits610and620may correspond to the respective labeled elements in the input circuit210inFIG.2. The second circuit620may output a second output signal OUT2, and the second output signal OUT2may refer to an output signal output from the second output circuit623. The second output signal OUT2may be a signal having a differential relationship with the first output signal OUT1. The second circuit620may include a second input circuit621, a second biasing circuit622, and a second output circuit623, and the second biasing circuit622may include a third amplification circuit624. The second input circuit621may convert a third input signal in and a fourth input signal in4into current. According to an example embodiment, the second input circuit621includes a node Ng2connected to the third input signal in and the fourth input signal in4. The current converted from the second input circuit621may be a differential input current, and the differential input current may include a third signal Gmin3and a fourth signal Gmin4. The second biasing circuit622may reduce a voltage change of an output end of the second input circuit621. The second biasing circuit622may include a third amplification circuit624that amplifies a voltage of the output end of the second input circuit621. The second output circuit623may include a fifth switching element M7connected to the output end of the second input circuit621so as to reduce the voltage change of the output end of the second input circuit621. The third amplification circuit624may be connected to the fifth switching element M7to form a feedback loop for reducing the voltage change of the output end of the second input circuit621. An input end of the third amplification circuit portion624may be connected to a node N5between the fifth switching element M7and the output end of the second input circuit portion621, and the output end of the third amplification circuit624may be connected the fifth switching element M7to form a feedback loop. Also, an input end of the third amplification circuit624may be connected to the first operating voltage Vbias1. The feedback loop connected to the fifth switching element M7may reduce a voltage change of the node N5of the output end of the second input circuit621. Further, the feedback loop connected to the fifth switching element M7may increase a transconductance of the fifth switching element M7and may bias a bias voltage of the fifth switching element M7. The bias voltage of the fifth switching element M7may mean a voltage applied to the fifth switching element M7so as to set an operating point of the fifth switching element M7. The bias voltage of the fifth switching element M7may be a DC voltage. The second output circuit623may include a sixth switching element M8. The sixth switching element M8and the fifth switching element M7may be different types of switching elements. For example, when the fifth switching element M7is an NMOS transistor, the sixth switching element M8may be a PMOS transistor. As another example, when the fifth switching element M7is a PMOS transistor, the sixth switching element M8may be an NMOS transistor, but is not limited thereto. The second biasing circuit622may include a fourth amplification circuit. The sixth switching element M8may amplify the voltage of the output end of the second input circuit621and may amplify a voltage of the node N6connected to the fourth amplification circuit. The fourth amplification circuit and the third amplification circuit624may be different. An input end of the fourth amplification circuit may be connected to the node N6between the sixth switching element M8and the output end of the second input circuit621, and the output end of the fourth amplification circuit may be connected to the sixth switching element M8to form a feedback loop. Also, an input end of the fourth amplification circuit may be connected to a second operating voltage. The feedback loop connected to the sixth switching element M8may reduce a voltage change of the node N6of the output end of the second input circuit621. The feedback loop connected to the sixth switching element M8may increase the transconductance of the sixth switching element M8and may bias the bias voltage of the sixth switching element M8. The bias voltage of the sixth switching element M8may mean a voltage applied to the sixth switching element M8so as to set an operating point of the sixth switching element M8. The bias voltage of the sixth switching element M8may be a DC voltage. The second output circuit623may further include capacitors Cc3and Cc4that increase a bandwidth of the second output signal OUT2. The capacitors Ccs and Cc4may be used as compensation capacitors. The capacitor Cc3may be connected between a node Ns1between a switching element Ms1and a switching element Ms3and an output end of the second output circuit623. The switching element Ms3may be connected in parallel to the fifth switching element M7and the sixth switching element M8, and the switching element Ms1may be connected to the switching element Ms3. The capacitor Cc4may be connected between a node Ns2between a switching element Ms4and a switching element Ms5and the output end of the second output circuit623. The switching element Ms4may be connected in parallel to the fifth switching element M7and the sixth switching element M8, and the switching element Ms5may be connected to the switching element Ms4. Each of the first circuit610and the second circuit620may include two input signals. For example, the first circuit610may include the first input signal in1and the second input signal in2, and the second circuit620may include the third input signal in and the fourth input signal in4. According to an example embodiment, the first input circuit611includes a node Ng1connected to the first input signal in1and the second input signal in2. In addition, each of the first circuit610and the second circuit620may include one output signal. For example, the first circuit610may include the first output signal OUT1, and the second circuit620may include the second output signal OUT2. The first circuit610and the second circuit620may be connected to each other. The first biasing circuit612and the first output circuit613may be connected to the second biasing circuit622and the second output circuit623. For example, the switching element Ms1of the second circuit620may be connected to the power voltage VDD. The switching element Ms9of the second circuit620may be connected to the first operating voltage Vbias1. The node Ns3between the switching element Ms1and the switching element Ms9of the second circuit620may be connected to the node Nos between the fourth switching element Mo1and the switching element Mb3of the first circuit610. Further, the node Nos may be connected to the first output circuit613, and the node Ns3may be connected to the second output circuit623. As the first circuit610and the second circuit620are connected to each other, the amplifier600may receive four input signals of the first input signal in1, the second input signal in2, the third input signal in3, and the fourth input in4, and may output the two output signals of the first output signal OUT1and the second output signal OUT2. Also, a common mode CM of the first output signal OUT1and the second output signal OUT2may be controlled. By controlling the common mode CM, errors due to an abnormal influence may not be easily transferred to the output signal, and a THD may be reduced. The second input circuit621, the second biasing circuit622, the second output circuit623, and the third amplification circuit624may respectively have the same functions and structures as those of the first input circuit611, the first biasing circuit612, the first output circuit613, and the first amplification circuit614. According to an example embodiment, the third amplification circuit624may include switching elements Ms8, Ms9, Ms7and a current source Ib2. Moreover, according to an example embodiment, the output circuit623may include switching elements M5, M6and Ms6and node N7. According to an example embodiment, the gates of the switching elements that are connected to “o” indicates that the gates of these switching element may be connected to a bias voltage applied to each of switching elements so as to set an operating point of each of the switching elements. FIG.7is a diagram illustrating an output signal of an amplifier according to an example embodiment. Referring toFIG.7, the output signal of the amplifier may include a first output signal710output from a first circuit and a second output signal720output from a second circuit. The vertical axis of the graph ofFIG.7may indicate voltage V, and the horizontal axis of the graph ofFIG.7may indicate time t. InFIG.7, the first and second output signals710and720are shown in the form of a sine wave, but are not limited thereto, and may be shown in the form of a square wave or the like. The output signal may swing with respect to a common mode voltage Vcm. The first output signal710and the second output signal720may refer to voltages having a differential relationship with each other. The voltages having the differential relationship may be voltages having opposite polarities, or voltages in which the same amount increases or decreases from an arbitrary reference voltage. When the first circuit and the second circuit are not connected to each other, the common mode voltage Vcmof the first output signal710and the common mode voltage Vcmof the second output signal720may be different from each other, and loss of the first output signal710and the second output signal720may increase. However, when the first circuit and the second circuit are connected to each other, the common mode voltage Vcmof the first output signal710and the second output signal720may be equally controlled, and the first output signal710and the second output signal720may swing with respect to the same common mode voltage Vcm. FIG.8is a diagram illustrating an application form of an amplifier810according to an example embodiment. Referring toFIG.8, the amplifier810may have four input signals and two output signals. The amplifier810ofFIG.8corresponds to the amplifier600ofFIG.6, and thus redundant descriptions are omitted. The amplifier810may operate as a buffer by connecting an output end of the amplifier810to an input end of the amplifier810. For example, a positive output end of the amplifier810may be connected to a negative input end of the amplifier810, and a negative output end of the amplifier810may be connected to the other negative input end of the amplifier810such that the amplifier810operates as the buffer having a gain of 1. The amplifier810may be provided before driving a final load after passing through a device that performs an amplification function and a device that performs signal processing such as a filter. The amplification function may be an arbitrary function. The amplifier810may be disposed before driving the final load, thereby separating the final load from the device that performs the amplification function and the device such as the filter. Accordingly, an abnormal operation of the device that performs signal processing may be prevented, and a signal processing result may be stable regardless of a load. Further, the amplifier810may minimize distortion of an output of the device that performs signal processing and transmit the distortion to the load. The device that performs signal processing may be a digital to analog converter (DAC), a microphone, a low noise amplifier (LNA), and the load may be a speaker or an analog to digital converter (ADC), but the present disclosure is not limited thereto. The amplifier810may be applied to a variety of application820. The application820may be a mobile audio amplifier, a smart speaker mic array signal input amplifier, an amplifier fora mobile phone receiver, etc., but is not limited thereto. For example, the amplifier810may be mounted on a mobile device and used as the mobile audio amplifier, and may amplify a signal input from a microphone of the mobile device and transmit the signal to a speaker of the mobile device. The amplifier810may be utilized in low power, high resolution, and low noise sensor applications. For example, the amplifier810may be used to transmit an audio signal output from a piezo microphone to a speaker. The amplifier810may be used in high resolution sensing multi-channel applications. For example, the amplifier810may be used in a small bio-medical device and an implant device. In addition, the amplifier810may be used for a wearable device, a mobile phone, or the Internet of Things (IoT). FIG.9is a flowchart illustrating an operation of a biasing circuit according to an example embodiment. Descriptions of operations of an amplifier ofFIG.9are related to the example embodiments described in the drawings ofFIGS.1to8, and thus the descriptions given in the drawings ofFIGS.1to8may also be applied to the method ofFIG.9even though omitted below. Referring toFIG.9, in operation910, the biasing circuit may receive a first operating voltage and a voltage of an output end of an input circuit. The biasing circuit may include a first amplification circuit, and the first amplification circuit may receive a first operating voltage and the voltage of the output end of the input circuit. For example, the first amplification circuit may receive a first operating voltage from a positive input end, and may receive the voltage of the output end of the input circuit from a negative input end. In operation920, the biasing circuit may amplify the voltage of the output end of the input circuit. The first amplification circuit may amplify and output the voltage of the output end of the input circuit. An output end of the first amplification circuit may be connected to at least one switching element, and the at least one switching element may reduce a voltage change of the output end of the input circuit. For example, when the at least one switching element is a MOSFET, the output end of the first amplification circuit may be connected to a gate of the MOSFET. In operation930, the biasing circuit may bias a bias voltage of the at least one switching element based on the first operating voltage and the amplified voltage of the output end of the input circuit. For example, when the at least one switching element connected to the biasing circuit is the first switching element, the biasing circuit may bias the bias voltage of the first switching element based on the first operating voltage and the amplified voltage of the output end of the input circuit. As another example, when the first switching element is the MOSFET, the biasing circuit may bias a gate voltage of the MOSFET based on the first operating voltage and the amplified voltage of the output end of the input circuit. In addition, the biasing circuit may reduce a voltage change of the output end of the input circuit. The output end of the input circuit and the input end of the first amplifier circuit may be connected to each other, and the output end of the first amplifier circuit may be connected to the at least one switching element to form a feedback loop. The voltage change of the output end of the input circuit may be reduced by the formed feedback loop. Meanwhile, the above described example embodiments may be written in a program executable on a computer, and may be implemented on a general purpose digital computer that operates the program using a computer readable recording medium. In addition, the structure of data used in the above described embodiments may be recorded on a computer readable recording medium through various means. The computer readable recording medium includes a storage medium such as a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), an optical reading medium (e.g., CD ROM, DVD, etc.). It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. Therefore, it should be understood that the example embodiments are to be considered in an illustrative rather than a restrictive sense. The scope of the rights is set forth in the appended claims rather than the foregoing description and should be interpreted as including all differences within the equivalent range thereto. It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more example embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 67,472 |
11942908 | DETAILED DESCRIPTION At present, a widely used technical solution is to integrate the PA, LNA, filter, duplexer and switch into a single chip to form a Power Amplifier Module integrated Duplexer (PAMiD), and the PAMiD together with an antenna form a complete architecture of radio frequency front-end. With this technical solution, the area occupied by each radio frequency device can be reduced, however, such integration reduces the debugging freedom of each device, which brings great inconvenience to the radio frequency engineers' debugging in practical applications, and results in that each radio frequency device and module cannot achieve its own superior performance. At present, a widely used technical solution is to integrate the PA, LNA, filter, duplexer and switch into a single chip to form a Power Amplifier Module integrated Duplexer (PAMiD), and the PAMiD together with an antenna form a complete architecture of radio frequency front-end. With this technical solution, the area occupied by each radio frequency device can be reduced, however, such integration reduces the debugging freedom of each device, which brings great inconvenience to the radio frequency engineers' debugging in practical applications, and results in that each radio frequency device and module cannot achieve its own superior performance. In an implementation, an architecture of radio frequency front-end is illustrated inFIG.1, andFIG.1illustrates an architecture of radio frequency front-end of Multi-Mode Multi-Band (MMMB), herein, the architecture of radio frequency front-end includes a PAMiD, an Antenna Matching Network (ANT_MN) and an Antenna (ANT), herein, the PAMiD includes a PA, a Power Amplifier Matching Network (PA_MN), a first switch (SW1) and a second switch (SW2), and multiple branches TX1, TX2, TXn are included between the first switch and the second switch, and each branch includes a filter or a duplexer, and the input end and the output end of the filter or the duplexer are provided with an Input Matching Network (IMN) (IMN1, IMN2, IMNn) and an Output Matching Network (OMN) (OMN1, OMN2, OMNn), respectively, and RFIN in the figure represents a Radio Frequency Input. With this implementation, a large number of devices can be integrated and a large area of board layout can be reduced, however, this implementation reduces the freedom of debugging, which brings great inconvenience to the radio frequency engineers during the debugging, and the PAMiD cannot achieve superior performance through debugging. For example, after the channel TX1is debugged, a group of common end impedance Z_ant1with superior performance for the channel TX1is obtained through the debugging, and the superior common end impedance Z_ant refers to the impedance at the input end of the antenna matching network; When the channel TX2is debugged, the channel TX2is found to have a relatively poor operating performance, and at this time, because the matching network of the PAMiD has been fixed, the channel TX2can operate in a better performance state by adjusting the antenna matching network only, and at this time, the common end impedance at the input end of the antenna matching network is Z_ant2, however, after the antenna matching network is adjusted, and when the PAMiD operates in the channel TX1, the common end impedance is still Z_ant2, and Z_ant2is not the common end impedance that allows the channel TX1to operate with superior performance, as a result, there is a possibility that the performance of the debugged channel TX1will deteriorate. By analogy, it would be a great workload to debug all the channels well, and there is no guarantee that each branch of the PAMiD will operate with superior performance. The Smith chart of the impedance matching process in this implementation is illustrated inFIGS.2A and2B. InFIG.2A, after the impedance matching is performed on the channel TX1, the common end impedance of the radio frequency architecture is Z_ant1, and at this time, the impedance Z_TX1of the channel TX1can reach the target area, but the impedance Z_TX2of the channel TX2cannot reach the target area. InFIG.2B, after the impedance matching is performed on the channel TX2, the common end impedance of the radio frequency architecture is Z_ant2, and at this time, the impedance Z_TX2of the channel TX2can reach the target area, however, the impedance Z_TX1of the channel TX1cannot reach the target area at this time, which will lead to a possible deterioration of the performance of the channel TX1. In view of the problems in the previous implementation, in another implementation of an architecture of radio frequency front-end as illustrated inFIG.3, based on the implementation ofFIG.1, each channel between the SW1and the filter or the duplexer is turned off, and the input matching network IMN1, IMN2, . . . IMNn originally provided between the SW1and the filter or the duplexer are replaced with an off-chip matching network MN1, MN2, . . . MNn, and the architecture of radio frequency front-end of this implementation allows the impedance matching of each channel of the circuit of radio frequency front-end to be debugged individually without affecting the other channels, overcoming the inflexibility brought about by the solution of the first implementation. However, with this implementation, a large number of matching networks are still retained and does not significantly reduce the area of board layout of the architecture of radio frequency front-end, while increasing the cost. With the increase of the number of chip channels, the off-chip wiring will become more complicated, so this implementation is not a superior solution. Based on the analysis of the above two implementations, various embodiments of the disclosure are provided. In some embodiments of the disclosure, each branch in the PA and the PAMiD operates in a superior state by providing one or more tunable matching networks between the PA and the antenna, which are configured to adjust the impedance of the output end of the PA and/or the impedance of the input end of the antenna, so that the architecture of radio frequency front-end can maintain a better operating performance in the multiple radio frequency channels. By adjusting the impedance of the tunable matching network to achieve the impedance matching of the radio frequency architecture, the architecture of radio frequency front-end has the following advantages. Debugging flexibility: the tunable matching network can be individually debugged and matched according to various different channels, without affecting other channels during the debugging, thus reducing the workload during the debugging. High performance: the impedance matching and debugging of each channel are performed individually during the debugging, and by debugging each channel individually, each channel can be debugged to superior performance without affecting the performance of other channels. Low cost: a large number of matching networks are not required, and the inherent cost of adopting the tunable matching networks is low. Small occupied area: the high degree of integration can reduce the area of board layout. The embodiments of the disclosure provide an architecture of radio frequency front-end, the architecture of radio frequency front-end includes a PAMiD, an antenna and at least one tunable matching network. The PAMiD includes a power amplifier, and the at least one tunable matching network is located between the power amplifier and the antenna, and is configured to adjust the impedance of the output end of the power amplifier and/or the impedance of the input end of the antenna. In some embodiments of the disclosure, the tunable matching network includes at least one type of the following components: an inductor, a capacitor, a resistor, a transmission line or a switch; herein, the impedance value in the tunable matching network is adjustable. In some embodiments,FIG.4is a schematic diagram of a tunable matching network of some embodiments of the disclosure, herein, Zin represents the impedance common to the tunable matching network and the load on the right side of the tunable matching network, and Zload represents the impedance of the load on the right side of the tunable matching network, i.e., Zload is the actual impedance of the load prior to the matching of the load, and Zin is the impedance of the load after the impedance matching of the load, herein the tunable matching network will be appropriately designed in order that the tunable matching network can be set up for different Zloads, so that the Zin can be adjusted to the desired impedance point without the addition of additional matching network components. For the tunable matching network inFIG.4, three forms of topological structures illustrated in theFIGS.5A,5B, and5Ccan be adopted, and it should be noted that the implementation of the tunable matching network includes, but is not limited to the three forms inFIGS.5A,5B, and5C, and other implementations of topological structures can also be adopted, as long as the function of the impedance matching can be realized.FIG.5Aillustrates a Π-type matching network,FIG.5Bis an L-type matching network, andFIG.5Cis a T-type matching network, and Z1, Z2and Z3inFIGS.5A,5B, and5C can be inductors, capacitors, resistors, transmission lines or switches, and furthermore, Z1, Z2and Z3can be reactance with fixed values or variable values, but at least one of Z1, Z2or Z3in the matching network is a variable reactance. Alternative implementation of variable reactance includes, but not limited to, the following forms: an electrically modulated varactor, an array of variable capacitors, a switching inductor or an array of resistors. An implementation of variable reactance that can be adopted in the embodiments of the disclosure may be an array of variable capacitors ofFIG.6. InFIG.6, a Bias Control circuit, an inductor L1, capacitors (C11, C12, C13, C21, C22, C23) and several switches are included. With the array of variable capacitors ofFIG.6, the capacitance value of the capacitors connected to the matching network can be changed by switching on and off the switching elements, thereby changing the impedance of the matching network, and achieving the purpose of adjusting the impedance value of the matching network. In some embodiments of the disclosure, the PAMiD further includes a first switch, a second switch and multiple branches located between the first switch and the second switch. Each of the multiple branches comprises a filter or a duplexer, and the input end and the output end of the filter or the duplexer are provided with an input matching network and an output matching network, respectively. It should be noted that in the embodiments of the disclosure, the adjustment of the impedance value of the tunable matching network can be achieved in several ways, and the adjustment of the impedance value of the tunable matching network is achieved by software control in the embodiments, and the impedance value of the entire tunable matching network is adjusted by controlling the reactance value of the variable reactance in the tunable matching network by software, and when the PAMiD operates in various different channels, the impedance value of the tunable matching network can be set separately by software, so as to achieve the purpose of the impedance matching and debugging of each branch of the PAMiD separately. In some embodiments of the disclosure, the at least one tunable matching network includes at least one of: at least one first tunable matching network, at least one second tunable matching network, or at least one third tunable matching network. In an alternative implementation of the disclosure, the first tunable matching network is located between the power amplifier and the first switch. In an alternative implementation of the disclosure, a power amplifier matching network (PA_MN) is further provided between the power amplifier and the first switch, and the PA_MN is integrated into the PAMiD. The first tunable matching network is located between the power amplifier matching network and the first switch. In an alternative implementation of the disclosure, the first tunable matching network is integrated into the PAMiD; or, the first tunable matching network is independently provided outside of the PAMiD. It should be noted that in embodiments of the disclosure, the first switch corresponds to SW1in the drawings, the second switch corresponds to SW2in the drawings, multiple branches corresponds to TX1, TX2, . . . TXn in the drawings, the input matching network corresponds to IMN1, IMN2, . . . IMNn in the drawings, the output matching network corresponds to OMN1, OMN2, . . . OMNn in the drawings, the filter corresponds to Filter in the drawings, the duplexer corresponds to Duplexer in the drawings, the antenna corresponds to ANT in the drawings, and the antenna matching network corresponds to ANT_MN in the drawings. In the drawings of the embodiments of the disclosure, RFIN represents the radio frequency input end, and MN represents the matching network. In some embodiments,FIG.7is a schematic diagram of a first tunable matching network integrated into the PAMiD. Herein, the originally non-tunable PA_MN provided in the original PAMiD is set to be the first tunable matching network of the embodiment of the disclosure, and the first tunable matching network is integrated into the PAMiD and is located between the power amplifier and the first switch. FIG.8is a schematic diagram of a first tunable matching network independently provided outside of the PAMiD; herein, the first tunable matching network is located between the PA_MN and the first switch. In another alternative implementation, a first tunable matching network can also be provided between the power amplifier and the PA_MN. The implementation ofFIG.7has a higher degree of integration than that of the implementation ofFIG.8. Both implementations ofFIG.7andFIG.8are capable of achieving debugging each channel of the PAMiD individually and achieving the impedance matching of the radio frequency architecture through setting the first tunable matching network by setting the software, so that the architecture of radio frequency front-end operates in different channels, and that the power amplifier may operate in a better state, so that the radio frequency architecture achieves a superior operating performance, with characteristics such as debugging flexibility, high performance, low cost, small occupied area, etc. In an alternative implementation of the disclosure, the second tunable matching network is located between the second switch and the antenna. In an alternative implementation of the disclosure, an antenna matching network is further provided between the second switch and the antenna. The second tunable matching network is located between the antenna matching network and the antenna; or, The second tunable matching network is located between the second switch and the antenna matching network. In an alternative implementation of the disclosure, in a case that the second tunable matching network is located between the second switch and the antenna matching network, the second tunable matching network is integrated into the PAMiD; or, The second tunable matching network is independently provided between the PAMiD and the antenna matching network. In some embodiments,FIG.9. is a schematic diagram of a second tunable matching network located between a second switch and an antenna matching network and integrated into the PAMiD;FIG.10is a schematic diagram of a second tunable matching network located between an antenna matching network and an antenna. Herein, the implementation ofFIG.9has a higher degree of integration than that of the implementation ofFIG.10. Both implementations ofFIG.9andFIG.10are capable of achieving debugging each channel of the PAMiD individually and achieving the impedance matching of the radio frequency architecture through setting the first tunable matching network by setting the software, so that the architecture of radio frequency front-end operates in different channels, and that the power amplifier may operate in a better state, so that the radio frequency architecture achieves a superior operating performance, with characteristics such as debugging flexibility, high performance, low cost, small occupied area, etc. In an alternative implementation of the disclosure, the third tunable matching network is located in the branch of the PAMiD. In an alternative implementation of the disclosure, the third tunable matching network is an input matching network in the branch; or, The third tunable matching network is an output matching network in the branch. FIG.11is a schematic diagram of a third tunable matching network located in the branch of the PAMiD, and one or more third tunable matching networks may be provided in multiple branches of the PAMiD inFIG.11, herein, the third tunable matching network may be located at the front of the filter in each branch or may be located at the rear of the filter, and may replace the input matching network and/or the output matching network originally located at the front of the filter. By adjusting the third tunable matching network of each branch of the PAMiD, the performance of the branch in which the third tunable matching network is located may be adjusted individually, so that the channel in which the branch is located has superior performance during operation, herein, the adjustment of the impedance value of the third tunable matching network may still be achieved by software control. In the embodiments of the disclosure, the first tunable matching network, the second tunable matching network and the third tunable matching network may be used in combination, and multiple tunable matching networks may be included in the architecture of radio frequency front-end.FIGS.12-17illustrate several alternative implementations of the disclosure. Herein, the integration of a tunable matching network into the PAMiD can improve the degree of integration of the architecture of radio frequency front-end. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.12. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is integrated into the PAMiD, and the antenna matching network is provided between the second switch and the antenna, and the second tunable matching network is provided between the antenna matching network and the antenna, and when each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance values of the first tunable matching network and the second tunable matching network, and when the PAMiD operates in different branches, the impedance values of the first tunable matching network and the second tunable matching network can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.13. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is independently provided outside of the PAMiD, and the antenna matching network is provided between the second switch and the antenna, and the second tunable matching network is provided between the antenna matching network and the antenna, and when each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance values of the first tunable matching network and the second tunable matching network, and when the PAMiD operates in different branches, the impedance values of the first tunable matching network and the second tunable matching network can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.14. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is integrated into the PAMiD, and the antenna matching network is provided between the second switch and the antenna, and the second tunable matching network is provided between the second switch and the antenna matching network and is integrated into the PAMiD, and when each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance values of the first tunable matching network and the second tunable matching network, and when the PAMiD operates in different branches, the impedance values of the first tunable matching network and the second tunable matching network can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.15. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is independently provided outside of the PAMiD, and the antenna matching network is provided between the second switch and the antenna, and the second tunable matching network is provided between the second switch and the antenna matching network and is integrated into the PAMiD, and when each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance values of the first tunable matching network and the second tunable matching network, and when the PAMiD operates in different branches, the impedance values of the first tunable matching network and the second tunable matching network can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.16. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is integrated into the PAMiD, and when each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance value of the first tunable matching network, and when the PAMiD operates in different branches, the impedance value of the first tunable matching network can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. In an alternative implementation of the disclosure, the architecture of radio frequency front-end adopts the solution of the architecture as illustrated inFIG.17. Herein, the first tunable matching network is a power amplifier matching network, which is located between the power amplifier and the first switch and is integrated into the PAMiD, and the antenna matching network is provided between the second switch and the antenna, and the second tunable matching network is provided between the antenna matching network and the antenna, and the third tunable matching network is provided at the input end of the filter of the branch TX2of the PAMiD. When each channel of the PAMiD is debugged, each channel of the PAMiD can be debugged in turn by setting the impedance values of the first tunable matching network and the second tunable matching network, and the branch TX2is adjusted by setting the impedance value of the third tunable matching network, and when the PAMiD operates in different branches, the impedance values of the tunable matching networks in the architecture of radio frequency front-end can be adjusted by software control, so that the architecture of radio frequency front-end can achieve superior operating performance in multiple radio frequency channels. It should be noted that the technical solutions of the disclosure have multiple implementations, and are not limited to the solutions of several architectures listed inFIGS.12-17, and the addition or subtraction of one or more tunable matching networks in the above implementations, or the combination of the above implementations, all belong to the scope of protection of the disclosure as long as they can achieve the purpose of the disclosure. In several embodiments provided in the disclosure, it should be appreciated that the disclosed method and the smart device may be implemented in other ways. The above-described embodiments of device are merely illustrative, for example, the division of the units is only a division based on logical functions, and there may be other divisions in actual implementations, e.g., multiple units or components may be combined, or may be integrated into another system, or some features may be ignored, or may not be performed. In addition, the coupling, direct coupling or communication connection between the components illustrated or discussed may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or otherwise. The above-mentioned units illustrated as separate components may be or may not be physically separated, and the components illustrated as units may be or may not be physical units, i.e., they may be located in one place or distributed to multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solutions of the embodiments. In addition, all the functional units in the embodiments of the disclosure may be integrated into a second processing unit, and each unit may also be used separately as a single unit, and two or more units may also be integrated into a single unit; the above integrated units may be realized either in the form of hardware or in the form of hardware together with software functional units. The terms “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, elements referred to as “first” and “second” may include one or more of the features either explicitly or implicitly. In the description of the present disclosure, “a plurality” indicates two or more unless specifically defined otherwise. In the present disclosure, the terms “installed,” “connected,” “coupled,” “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, or integrated, unless otherwise explicitly defined. These terms can refer to mechanical or electrical connections, or both. Such connections can be direct connections or indirect connections through an intermediate medium. These terms can also refer to the internal connections or the interactions between elements. The specific meanings of the above terms in the present disclosure can be understood by those of ordinary skill in the art on a case-by-case basis. In the description of the present disclosure, the terms “one embodiment,” “some embodiments,” “example,” “specific example,” or “some examples,” and the like may indicate a specific feature described in connection with the embodiment or example, a structure, a material or feature included in at least one embodiment or example. In the present disclosure, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and reorganized. While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any claims, but rather as descriptions of features specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Thus, particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking or parallel processing may be utilized. It is intended that the specification and embodiments be considered as examples only. Other embodiments of the disclosure will be apparent to those skilled in the art in view of the specification and drawings of the present disclosure. That is, although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise. Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the example embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures. | 31,084 |
11942909 | DETAILED DESCRIPTION In order to make the purpose, technical solutions and advantages of the disclosure clearer, the technical solutions of the embodiments of the disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the disclosure, and apparently, the described embodiments are only a part of the embodiments of the disclosure, not all of them. Based on the embodiments of the disclosure, all other embodiments obtained by those ordinarily skilled in the art without paying any creative work belong to the protection scope of the disclosure. The embodiments of the disclosure and the features in the embodiments may be arbitrarily combined with each other without conflict. A feedback circuit employed in a feedback amplifier is typically a single type, and signals input to the amplifier may be of different types. As such, a single feedback circuit typically cannot meet the requirements of different types of signals input to the amplifier. FIG.1illustrates an amplifier of an embodiment of the disclosure, which structurally includes an input circuit101, an amplification circuit102and at least two feedback circuits103a-103n. Herein, n is a positive integer greater than or equal to 2. In practical applications, the value of n may be consistent with the number of types of input signals that may be received by the input circuit101, or may be less than the number of types of input signals that may be received by the input circuit101, which may be set flexibly depending on the actual situation. For convenience of description, the amplification circuit102is regarded as including an input end and an output end. Each of the feedback circuits includes a first end and a second end. Herein, the input circuit101is connected with the input end of the amplification circuit102; the output end of the amplification circuit102is connected with a first end of each of the feedback circuits103a-103n, respectively; and a second end of each of the feedback circuits103a-103nis connected with the input circuit101respectively. Equivalently, the input circuit101receives an input signal (Din). The amplification circuit102amplifies the input signal to obtain an amplified signal generated for the input signal. Herein, at least a part of the amplified signal is fed back to an input end of the input circuit101through a target feedback circuit of the at least two feedback circuits103a-103n. The signal fed back to the input circuit101through the target feedback circuit is referred to as feedback signal. It may be understood that in addition to the input signal (Din), the input circuit101may receive a feedback signal (Df) generated for such input signal. In the case that there is a feedback signal, both the input signal Din and the feedback signal Df are input to the amplification circuit102and amplified by the amplification circuit102. It may be understood that the feedback signal of the embodiments of the disclosure being fed back to the input end of the input circuit101through which feedback circuit, is determined by the type of the input signal that is input to the input circuit101. Equivalently, each of the feedback circuits corresponds to different types of input signals, and for different types of input signals, the feedback circuit corresponding to the type of the signal is determined from at least two feedback circuits103a-103n, as the target feedback circuit for each type of input signal. In terms of implementing functionality, the input circuit101is configured to receive an input signal and a feedback signal. The amplification circuit102is configured to amplify the input signal and the feedback signal to obtain an amplified signal; herein, the feedback signal is fed back to the input circuit by feeding back at least a part of the amplified signal through a target feedback circuit; and the target feedback circuit is a feedback circuit that depends on the type of the input signal in the at least two feedback circuits103a-103n. Specifically, the amplification circuit102may be implemented by power amplifiers made of Gallium Arsenide (GaAs), Silicon-On-Insulator (SOI), Silicon-based (Si-based), etc., it may also be implemented by power amplifiers with structures such as Heterojunction Bipolar Transistor (HBT), Complementary Metal Oxide Semiconductor (CMOS), Cascode and Stack, and the implementation thereof is not limited to the above amplification devices or structures. In the above solution, the amplifier includes at least two feedback circuits103a-103n, and for different types of input signals, the feedback circuit corresponding to the type of the signal is determined from the at least two feedback circuits103a-103n, as the target feedback circuit for each type of input signal, and the feedback signal generated for the corresponding type of input signal is input to the input circuit101through the target feedback circuit, so as to realize amplification of the input signal and the feedback signal generated for such input signal through the amplification circuit102. The amplifier of such type of design may at least meet the requirements of different types of input signals. It may be understood that the amplifier of the embodiments of the disclosure is a feedback amplifier. The feedback signals generated for different types of input signals are fed back to the input circuit101through different feedback circuits, and are amplified by the amplification circuit102to realize the normal amplification function of the amplifier. In an alternative solution, the input circuit101may also pre-process the input signal and the feedback signal in the case of receiving the input signal and the feedback signal generated for such input signal. Specifically, the pre-processing includes filtering out interference signals of the input signal and the feedback signal, and transmitting the input signal and the feedback signal filtered out of the interference signals to the amplification circuit102as input signals of the amplification circuit102. The signal input to the amplification circuit102is a signal that has been filtered out of the interference signal, and there is no interference in the signal to be amplified, thereby improving the stability of the amplification of the amplifier. In specific implementation, when receiving an input signal, the input circuit101may receive the input signal in a wired way (e.g., by circuit connection) or wireless way (e.g., by antenna), and the input signal is an alternate current signal (AC signal), a direct current signals (DC signal) or a combination of DC signal and AC signal. It may be understood that in the embodiments of the disclosure, only the input signal is input into the input circuit101at the initial stage, and the amplification circuit102feeds back at least a part of the amplified signal generated for the input signal to the input circuit101through the target feedback circuit in the case that the input circuit101only receives the input signal, so as to generate a feedback signal for the input signal. It may be understood that a feedback stage is entered after the initial stage, and in the feedback stage, in addition to the input signal, the input circuit101may receive the feedback signal, and transmits the received feedback signal and input signal to the amplification circuit102, which amplifies the two signals to obtain amplified signals of the two signals. At least a part of the amplified signals is fed back to the input circuit101through the target feedback circuit again, as a new feedback signal. The input circuit101transmits the new feedback signal to the amplification circuit102for amplification thereof again. Such repeated feedback forms a closed loop to complete the amplification function of the feedback amplifier. As illustrated inFIG.2, in the embodiments of the disclosure, the type of the input signal includes a first type and a second type; herein the input signal of the second type includes a first subtype and a second subtype. Specifically, the signal of the first type is the second-generation communication technology (2G) signal used by the communication device operating in the Global System for Mobile Communication (GSM) network mode, and the signal of the second type is the 2.75th generation communication technology (2.75G) signal used by the communication device operating in the Enhanced Data Rate for GSM Evolution (EDGE) network mode, and vice versa. The signal of the first type may also be 2G signal, and correspondingly, the signal of the second type is the third-generation communication technology (3G) signal, the fourth-generation communication technology (4G) signal or the fifth-generation communication technology (5G) signal; and vice versa. The signal of the first type may also be 3G signal, and correspondingly, the signal of the second type is 4G or 5G signal; and vice versa. The signal of the first type may also be 4G signal, and correspondingly, the signal of the second type is 5G signal; and vice versa. Herein, taking the signal of the first type being a 2G signal and the signal of the second type being a 2.75G signal as an example. The signal of the first subtype is a large signal of the 2.75G signal, and the signal of the second subtype is a small signal of the 2.75G signal. Herein, the small signal and the large signal are classified according to the power of the signal, which is determined by the performance of the amplification circuit102. The input signal is classified into a large signal and a small signal according to the power thereof. Generally, the large signal which is a signal with a power greater than or equal to 25 dBm (decibel relative to one milliwatt), will cause the operating state of the amplification circuit102to enter into the saturation region from the linear amplification region due to excessive power thereof, while a small signal which is a signal with power less than 10 dBm, will cause the amplification circuit102to operate in the linear amplification region. The small signal does not require too high gain, but requires better gain linearity, while the large signal is opposite thereto. The above takes the signal of the first subtype being a large signal of 2.75G signal and the signal of the second subtype being a small signal of 2.75G signal as an example, and vice versa. For the 2G signal, it's unnecessary to distinguish between the large signal and the small signal. In an alternative embodiment, as illustrated inFIG.2, taking the amplifier including two feedback circuits (a first feedback circuit103aand a second feedback circuit103b), and the signal of the first subtype being a large signal of 2.75G signal and the signal of the second subtype being a small signal of 2.75G signal as an example, and in the case that the input signal is the signal of the first type or the first subtype, the first feedback circuit103aof the two feedback circuits103aand103bis used as the target feedback circuit based on the type of the input signal. The circuit structure of the first feedback circuit103ais illustrated with reference to the circuit inFIG.4. The first feedback circuit103aincludes a first capacitive element C1, a first resistor R1 and a second resistor R2; herein, a first end of the first capacitive element C1 is connected with the input end of the amplification circuit102; a second end of the first capacitive element C1 is connected with one end of the first resistor R1; the other end of the first resistor R1 is connected with one end of the second resistor R2; and the other end of the second resistor R2 is connected with the output end of the amplification circuit102. It may be understood thatFIG.4is only one specific implementation of the first feedback circuit103a, in which the first capacitive element C1 can be implemented by other capacitive circuits; and the resistors R1 and R2 may also be implemented by other components which are equivalent to resistors. Generally, the electrical attribute values of the first resistor R1, the second resistor R2 and the first capacitive element C1 are set according to the actual situation, so that in the case that the input signal is the signal of the first type or the first subtype, at least a part of the amplified signal may be fed back to the input circuit101through the first feedback circuit103a, specifically through the second resistor R2, the first resistor R1 and the first capacitive element C1 sequentially, so as to feed back the feedback signal to the input circuit101. It may be understood that at least a part of the amplified signal enters the first feedback circuit103a, and then flows through the second resistor R2 and the first resistor R1 sequentially for voltage division thereof, so as to control the signal amplitude of the obtained feedback signal. The remaining signal after at least a part of the amplified signal being voltage divided by the first resistor R1 and the second resistor R2 passes through the first capacitive element C1, which is configured to filter out the DC component, thereby obtaining a feedback signal. It should be known that the feedback signal is the AC component of the remaining signal after at least a part of the amplified signal is voltage divided by two resistors. In the above solution, for the input signal of the first type (2G signal) or the first subtype (a large signal of 2.75G signal), the first feedback circuit103amay be used as the target feedback circuit of these types of input signals, that is, the first feedback circuit103ais a feedback circuit for the input signal of the type corresponding to the 2G signal or the large signal of 2.75G signal, and in the case that the input signal is the 2G signal or the large signal of 2.75G signal, the first feedback circuit103ais selected as the feedback circuit for transmitting the feedback signal of such type of signal. As illustrated inFIG.2, in the case that the input signal is the signal of the second type, the target feedback circuit is the second feedback circuit103bof the two feedback circuits. Specifically, in the case that the input signal is the signal of the second type such as the small signal of 2.75G signal, the second feedback circuit103bis used as the target feedback circuit for transmitting the feedback signal of such type of input signal. In the embodiments of the disclosure, the circuit structure of the second feedback circuit103bis illustrated with reference to the circuit inFIG.5. The second feedback circuit103bincludes a second capacitive element C2 and a third resistor R3; herein, a first end of the second capacitive element C2 is connected with the input end of the amplification circuit102; a second end of the second capacitive element C2 is connected with one end of the third resistor R3; and the other end of the third resistor R3 is connected with the output end of the amplification circuit102. It may be understood thatFIG.5is only one specific implementation of the second feedback circuit103b, in which the second capacitive element may be implemented by other capacitive circuits; and the resistor R3 may also be implemented by other components which are equivalent to resistors. Generally, the electrical attribute values of the third resistor R3 and the second capacitive element C2 are determined according to the actual situation, so that in the case that the input signal is the signal of the second subtype, at least a part of the amplified signal is fed back to the input circuit101through the third resistor R3 and the second capacitive element C2 sequentially. That is, in the embodiments of the disclosure, the second feedback circuit103bconverts at least a part of the amplified signal into a desired feedback signal. In the case that the input signal is the small signal of 2.75G signal, at least a part of the amplified signal is voltage divided while passing through the third resistor R3, consumes a part of the power of at least a part of the amplified signal, and inputs at least a part of the amplified signal other than the signal that has been voltage divided by the third resistor R3 to the second capacitive element C2. The second capacitive element C2 filters out the DC component of the signal, leaving the AC component thereof. The AC signal obtained by filtering out the DC component is input to the input circuit101as a feedback signal. In the case that the first feedback circuit103ais illustrated inFIG.4and the second feedback circuit103bis illustrated inFIG.5, the amplifier also includes a selection circuit106(as illustrated inFIG.8) to select a target feedback circuit; and a first end of the selection circuit106is connected with the output end of the amplification circuit102; a second end of the selection circuit106is connected with the first feedback circuit103a, specifically with the second resistor R2; and a third end of the selection circuit106is connected with the second feedback circuit103b, specifically with the third resistor R3. At least a part of the amplified signal is output from the output end of the amplification circuit102and input from the first end of the selecting circuit106, and the selecting circuit106selects a target feedback circuit for the at least a part of the amplified signal according to the type of the input signal. Specifically, the selection circuit106is configured to select the first feedback circuit as the target feedback circuit in the case that the input signal is of the first type and the first subtype, and to output the at least a part of the amplified signal from the second end of the selection circuit106into the first feedback circuit103a. While the selection circuit106is configured to select the second feedback circuit103bas the target feedback circuit in the case that the input signal is of the second subtype, and the at least a part of the amplified signal is output from the third end of the selection circuit106into the second feedback circuit103b. In the embodiments of the disclosure, the second feedback circuit103bmay also be implemented by another circuit structure. As illustrated inFIG.6, the second feedback circuit103bincludes a first capacitive element C1, a first resistor R1 and a turn-on circuit DT; herein, a first end of the first capacitive element C1 is connected with the input end of the amplification circuit102; a second end of the first capacitive element C1 is connected with one end of the first resistor R1; the other end of the first resistor R1 is connected with one end of the turn-on circuit; and the other end of the turn-on circuit DT is connected with the output end of the amplification circuit102. In the case that the input signal is the signal of the second subtype such as the small signal of 2.75G signal, at least a part of the amplified signal is fed back to the input circuit101through the turn-on circuit, the first resistor R1 and the first capacitive element C1 sequentially. Herein, the turn-on circuit DT is configured to be turned on in the case that the input signal is the signal of the second subtype such as the small signal of 2.75G signal; and to be turned off in the case that the input signal is the signal of the first type or the first subtype such as 2G signal or the large signal of 2.75G signal. Specifically, at least a part of the amplified signal enters the second feedback circuit103b, and in the case that the input signal is the signal of the second subtype, the turn-on circuit DT is turned on and operates normally, and at least a part of the amplified signal passes through the first resistor R1 and consumes a part of the power, and then passes through the first capacitive element C1 to filter out the DC signal of the signal, take the AC signal with the DC component filtered out as a feedback signal, and input the feedback signal into the input circuit101. In the above solution, for the input signal of the second subtype, the second feedback circuit103bis selected as the feedback circuit of such type of input signal. For the input signal of the first type or the first subtype, the first feedback circuit103ais selected as the feedback circuit of such type of input signal. The second feedback circuit103bhas less resistance than the first feedback circuit103a. That is, the second feedback circuit103bhas a smaller impedance than the first feedback circuit103a. The second feedback circuit103bhas a smaller impedance than the first feedback circuit103a, therefore, in the case that the input signal is the signal of the second subtype, less power of at least a part of the amplified signal is consumed by the second feedback circuit103b, and a larger feedback signal is obtained, and the amplifier obtains a deeper feedback. Such deeper feedback avoids that when amplifying the signal of the second subtype, the operating state of the amplification circuit102easily enters into the saturation region from the linear amplification region due to the excessive signal input to the amplification circuit102, thereby failing to realize normal amplification of the amplification circuit102. Such design of the second feedback circuit103bavoids the amplification circuit102operating in the saturation region, and allows the amplification circuit102to operate in the linear amplification region to the maximum extent, so as to achieve normal amplification and meet the requirements for better gain linearity of the input signal of the second subtype. It may be understood that the first feedback circuit103ahas a larger impedance than the second feedback circuit103b, so the feedback signal, obtained by the first feedback circuit103a, of at least a part of the amplified signal is smaller, and the amplifier obtains a shallower feedback, which may obtain a larger gain of the amplification circuit, however, the improvement on the gain linearity is relatively small, which meets the requirements for high gain of the input signals of the first type and the first subtype. In the above solution, in the case that the input signal is the small signal of 2.75G signal, the second feedback circuit103bis determined as the target feedback circuit, and the turn-on circuit DT is turned on, and since the second feedback circuit103bhas a smaller impedance than the first feedback circuit103a, then in the case that the input signal is the signal of the second subtype, less power of at least a part of the amplified signal is consumed by the second feedback circuit103b, obtaining a larger feedback signal, and the amplifier obtains a deeper feedback, thereby ensuring the phenomenon that when amplifying the signal of the second subtype, the operating state of the amplification circuit102enters into the saturation region from the linear amplification region due to the excessive signal input to the amplification circuit102and cannot realize stable amplification, does not occur. In specific implementation, the turn-on circuit DT of the embodiments of the disclosure may be realized in two ways: First Implementation: the turn-on circuit DT is a diode or a field effect transistor such as CMOS. The turn-on voltage may be selected to allow the diode or the field-effect transistor to be turned on in the case that the input signal is the small signal of 2.75G signal, and to allow the diode or the field-effect transistor to be turned off in the case that the input signal is 2G signal or the large signal of 2.75G signal. Second Implementation: as illustrated inFIG.6, the turn-on circuit DT includes a switching unit and a diode which are connected in sequence. Herein, the switching unit is configured to be switched off in the case that the input signal is of the first type; and to be switched on in the case that the input signal is of the second type. Specifically, the switching unit may operate in a switched-off or switched-on state. Which state the switching unit operates in, may be determined based on the network mode of the communication device. For example, in the case that the communication device operates in GSM network mode and is set to use 2G, the switching unit is in the switched-off state. In the case that the communication device operates in EDGE network mode or other network modes, the switching unit may be set in the switched-on (closed) state. In practical applications, the amplifier of the embodiments of the disclosure is not only applied to the adjustment of gain and the improvement in linearity of 2G signal and 2.75G signal, but also applied to the adjustment of gain and the improvement in linearity of signals in 3G, 4G or 5G communication technologies, etc. In the case that the communication device switches from the EDGE network mode or other network modes to the GSM network mode (for example, switching from 5G, 4G, 3G or 2.75G to 2G), the switching unit is in the switched-off state. In the case that the communication device operates in 5G, 4G, 3G or 2.75G, the switching unit is in the closed state. The diode is configured to be turned off in the case that the input signal is of the first subtype; and turned on in the case that the input signal is of the second subtype. As illustrated inFIG.3, in the embodiments of the disclosure, the amplifier also includes a power supplying circuit104and an inductive element105; the power supplying circuit104is connected with the power supplying end of the amplification circuit102and configured to supply power to the amplification circuit102so that the amplification circuit102operates in the linear amplification region; and one end of the inductive element105is connected with the power supplying circuit104, and the other end of the inductive element105is connected with the power supplying end of the amplification circuit102, and the inductive element105is configured to isolate the AC signal of at least a part of the amplified signal. In specific implementation, the power supply is a DC power supply, which provides the operating voltage for the amplification circuit102, so that the amplification circuit102operates in the linear amplification region, and realizes the normal amplification of signals. The amplification factor of the amplification circuit102may be changed by adjusting the operating voltage, for example, in the case that the operating voltage is VCC1, then, the amplification factor is A1, and in the case that the operating voltage is VCC2, the amplification factor is A2. However, in the embodiments of the disclosure, in order for the amplification circuit102to achieve stable amplification, when amplifying different types of input signals, the amplification factor of the amplification circuit102is the same, i.e., the operating voltage provided by the power supply for the amplification circuit102is fixed. The amplification circuit102is configured to amplify the input signal and the feedback signal when operating in the linear amplification region. It may be understood that in addition to being able to amplify the input signal and the feedback signal to obtain the amplified signal, the amplification circuit102is able to determine at least a part of the amplified signal. For example, the amplification circuit102may sample the amplified signal, and input the sampled signal to the target feedback circuits103a-103n, and feed it back to the input circuit101through the target feedback circuits. In the above solution, the amplification circuit102may operate in the linear amplification region by means of the power supplying circuit104and the inductive element105to realize its normal operation. Next, an amplifier disclosed in the embodiments of the disclosure will be described in detail with reference toFIGS.7to9.FIG.7is a schematic diagram of an implementation of the circuit structure of an amplifier of an embodiment of the disclosure.FIG.8is a schematic diagram of another implementation of the circuit structure of an amplifier of an embodiment of the disclosure. The first implementation of the circuit, as illustrated inFIG.7, includes a first feedback circuit103a(implemented by the circuit inFIG.4) and a second feedback circuit103b(implemented by the circuit inFIG.6), an input circuit101, an amplification circuit102, a power supplying circuit104and an inductive element105. Herein, the first feedback circuit103aand the second feedback circuit103bshare the first capacitive element C1 and the first resistor R1. The power supplying circuit104is a DC power supply VCC, and the turn-on circuit DT includes a switching unit and a diode. The amplification circuit102is an amplifier (PA). The inductive element105is an inductor L. It may be understood thatFIG.7illustrates an implementation of the circuit of a feedback amplifier. When the input signal is 2G signal in GSM mode, the switching unit of the turn-on circuit is in a switched-off state, and the target feedback circuit is the first feedback circuit103a. The input circuit101receives such type of input signal, and most of the input signal is transmitted to PA as the input signal of the PA, and the PA amplifies the signal input to itself to obtain an amplified signal. At least a part of the amplified signal obtains a feedback signal Df through the first feedback circuit103a, which is fed back to the input circuit101. Other signal except the at least a part of the amplified signal is output as an output signal Dout. Specifically, at least a part of the amplified signal is voltage divided by resistors R2 and R1 sequentially, and the capacitor C1 filters out the DC component of the remaining signal after voltage division, leaving the AC component thereof, and the capacitor C1 inputs the filtered signal to the input circuit101as a feedback signal. When the input signal is the large signal of 2.75G signal in EDGE mode, the switching unit is in a closed state. The reason why the first feedback circuit103ais selected as the target feedback circuit in this case will be explained below. The input circuit101receives such type of input signal, and the minority part of the input signal flows through the capacitor C1 and the closed switching unit sequentially, forming a first voltage V1 at the negative electrode of the diode (the left side of the diode). The majority part of the input signal is transmitted to PA as the input signal of the PA, and the PA amplifies the signal input to itself to obtain an amplified signal. At least a part of the amplified signal forms a second voltage V2 at the positive electrode of the diode (the right side of the diode). Since the input signal is a large signal, V1 and V2 are both large signals. V2-V1 is a small signal, the value of V2-V1 is less than or equal to the turn-on voltage Vgs of the diode, and the diode is turned off. With the diode turned off, the second feedback circuit103bmay not be used, and the first feedback circuit103amay be used as the target feedback circuit. At least a part of the amplified signal output by the amplification circuit102flows through the second resistor R2, the first resistor R1 and the first capacitive device C1 of the first feedback circuit103asequentially to obtain a feedback signal, which is fed back to the input circuit101. Other signal except the at least a part of the amplified signal is output as an output signal Dout. Specifically, at least a part of the amplified signal is voltage divided by resistors R2 and R1 in sequence, and the capacitor C1 filters out the DC component of the remaining signal after voltage division, leaving the AC component thereof, and the capacitor C1 inputs the filtered signal to the input circuit101as a feedback signal. When the input signal is the small signal of 2.75G signal in EDGE mode, the switching unit is in a closed state. The reason why the second feedback circuit103bis selected as the target feedback circuit in this case will be explained below. The input circuit101receives such type of input signal, and the minority part of the input signal flows through the capacitor C1 and the closed switching unit sequentially, forming a first voltage V1 at the negative electrode of the diode (the left side of the diode). The majority part of the input signal is transmitted to PA as the input signal of the PA, and the PA amplifies the signal input to itself to obtain an amplified signal. At least a part of the amplified signal forms a second voltage V2 at the positive electrode of the diode (the right side of the diode). Since the input signal is a small signal, V2 (a signal amplified by PA) is a large signal, V1 is a small signal, V2-V1 is a large signal, and the value of V2-V1 is greater than the turn-on voltage Vgs of the diode, and the diode is turned on. With the diode turned on, the first feedback circuit103a(the resistor R2 of the first feedback circuit103ais bypassed) may not be used, and the second feedback circuit103bmay be used as the target feedback circuit. At least a part of the amplified signal output by the amplification circuit102flows through the diode, the switching unit, the resistor R1 and the capacitor C1 of the second feedback circuit103bsequentially to obtain a feedback signal, which is fed back to the input circuit101. Other signal except the at least a part of the amplified signal is output as an output signal Dout. Specifically, at least a part of the amplified signal is voltage divided by the resistor R1, and the capacitor C1 filters out the DC component of the remaining signal after voltage division, leaving the AC component thereof, and the capacitor C1 inputs the filtered signal into the input circuit101as a feedback signal. Another specific implementation of the amplifier, as illustrated inFIG.8, includes a first feedback circuit103a(implemented by the circuit inFIG.4) and a second feedback circuit103b(implemented by the circuit inFIG.5), a selection circuit106, an input circuit101, a power supplying circuit104and an inductive element105. Herein, a first end of the selection circuit106is connected with the output end of the amplification circuit102; a second end of the selection circuit106is connected with the first feedback circuit103a, specifically the second resistor R2; and a third end of the selection circuit106is connected with the second feedback circuit103b, specifically the third resistor R3. The power supplying circuit104is a DC power supply VCC. The amplification circuit102is PA. The inductive element105is an inductor L. It may be understood thatFIG.8illustrates another implementation of the circuit of a feedback amplifier. When the input signal is 2G signal in GSM mode and the large signal of 2.75G signal in EDGE mode, the selection circuit106selects the first feedback circuit103aas the target feedback circuit, and when the input signal is the small signal of 2.75G signal in EDGE mode, the selection circuit106selects the second feedback circuit103bas the target feedback circuit. Specifically, the selection circuit106may be a single-pole-double-throw (SPDT) switch, with one end connected with the input end of the amplification circuit102, and the other end connected with the first feedback circuit103awhen the input signal is 2G signal and the large signal of 2.75G signal, and connected with the second feedback circuit103bwhen the input signal is the small signal of 2.75G signal. The selection circuit106may also be a relay that controls the switch connected with the first feedback circuit103ato pull up and the switch connected with the second feedback circuit103bto fall down when the input signal is 2G signal and the large signal of 2.75G signal, and vice versa when the input signal is the small signal of 2.75G signal. Specifically, when the input signal is 2G signal and the large signal of 2.75G signal, they are both large signals. The reason why the first feedback circuit103bis selected as the target feedback circuit in this case will be explained below. The input circuit101receives such type of input signal, and most of the input signal is transmitted to PA as the input signal of the PA, and the PA amplifies the signal input to itself to obtain an amplified signal. According to the type of signal for the input signal being the large signal, the selection circuit106connects with the first feedback circuit103aby turning on the output end of the amplification circuit102, and selects the first feedback circuit103aas the target feedback circuit, so that at least a part of the amplified signal flows through the resistor R2, the resistor R1 and the capacitor C1 of the first feedback circuit103asequentially to obtain a feedback signal, which is fed back to the input circuit101. Other signal except the at least a part of the amplified signal is output as an output signal Dout. Specifically, at least a part of the amplified signal is voltage divided by resistors R2 and R1 sequentially, and the capacitor C1 filters out the DC component of the remaining signal after voltage division, leaving the AC component thereof, and the capacitor C1 inputs the filtered signal to the input circuit101as a feedback signal. Specifically, when the input signal is the small signal of 2.75G signal, it is a small signal. The reason why the second feedback circuit103bis selected as the target feedback circuit in this case will be explained below. The input circuit101receives such type of input signal, and most of the input signal is transmitted to PA as the input signal of the PA, and the PA amplifies the signal input to itself to obtain an amplified signal. According to the type of signal for the input signal being the small signal, the selection circuit106connects with the second feedback circuit103bby turning on the output end of the amplification circuit102, and selects the second feedback circuit103bas the target feedback circuit, so that at least a part of the amplified signal flows through the resistor R3 and the capacitor C2 of the second feedback circuit103bsequentially to obtain a feedback signal, which is fed back to the input circuit101. Other signal except the at least a part of the amplified signal is output as an output signal Dout. Specifically, at least a part of the amplified signal is voltage divided by the resistor R3, and the capacitor C2 filters out the DC component of the remaining signal after voltage division, leaving the AC component thereof, and the capacitor C2 inputs the filtered signal to the input circuit101as a feedback signal. It should be noted herein that in the above solution, the input circuit101subtracts the input signal from the feedback signal after receiving the input signal and the feedback signal, and the subtracted signal is taken as the input of the PA. Those skilled in the art should know that in the embodiments of the disclosure, the feedback signal which is fed back to the input circuit101by at least one of the first feedback circuit103aor the second feedback circuit103bis a negative feedback signal, and the input signal, together with the negative feedback signal, are taken as the input signal of the PA. In the case that the input signal of the PA is only the input signal received by the input circuit101, it is equivalent to reducing the signal input to the PA, so as to avoid the effect that the amplification circuit102easily switches from the linear operation region to the saturation region and cannot realize normal amplification due to the excessive signal input to the amplification circuit102. The feedback circuit of the embodiments of the disclosure allows the feedback signal to be negative feedback, which ensures the PA to operate in the linear operation region and ensures the normal amplification of the PA. The input signal, together with the negative feedback signal, are taken as the input signal of the PA to achieve the effect of suppressing the power of the input signal (a negative feedback effect). It can be seen that in the embodiments of the disclosure, at least two feedback circuits103a-103nare provided for the amplifier, and for different types of input signals, corresponding feedback circuits are selected as target feedback circuits from the at least two feedback circuits103a-103n, and different feedback circuits get different negative feedback signals, that is, different feedback circuits have different degrees of suppression of the input signal (different depths of negative feedback). For example, in the case that the input signal is the large signal (the large signal of 2G signal and the large signal of 2.75G signal), the first feedback circuit103ais selected as the target feedback circuit, and since the impedance of the first feedback circuit103ais larger than that of the second feedback circuit103b, the consumption of at least a part of the amplified signal is greater, and the obtained feedback signal has a relatively shallow feedback. In the case that the input signal is the small signal (the small signal of 2.75G signal), the second feedback circuit103bis selected as the target feedback circuit, and since the impedance of the second feedback circuit103bis smaller than that of the first feedback circuit103a, the consumption of at least a part of the amplified signal is smaller, and the obtained feedback signal has a relatively deep feedback. By suppressing the power of different types of input signals by different feedback circuits, the power range of the signal that is linearly amplified by the amplification circuit102may be extended, that is, the linearity of the amplification gain may be improved. With reference toFIG.9, how to improve the gain linearity by the amplifier of the embodiments of the disclosure will be described in detail below. As illustrated inFIG.9, the power-gain diagram of the amplifier of the embodiments of the disclosure is illustrated, herein the power is the power of the input signal. In the case that the circuit structure of the amplifier is not provided with at least two feedback circuits103a-103n, the amplification circuit102may linearly amplify the input signal with power in the range of P0-P3, with a gain of g, however, when the power of the input signal is greater than P3, the gain of the amplification circuit102begins to attenuate, and it attenuates by 1 dB (decibel) when the power of the input signal is P1. In the case that the circuit structure of the amplifier is provided with at least two feedback circuits103a-103n, the amplification circuit102may linearly amplify the input signal with power in the range of P0-P1, with a gain of g, and when the power of the input signal exceeds P1, the gain of the amplification circuit102begins to attenuate, and it attenuates by 1 dB when the power of the input signal reaches P2. Herein, P0 is the minimum power of the input signal that allows the amplification circuit102to operate in the linear amplification region, and P2>P1>P3>P0. It may be understood that the amplifier of the embodiments of the disclosure improves the gain linearity of the amplification circuit102by adding at least two feedback circuits103a-103n, specifically extending the power range of the linearly amplified signal by the amplification circuit102, thereby making the amplification performance of the amplifier more stable. In the above solution, according to the type of the input signal, one feedback circuit is selected from at least two feedback circuits103a-103n, as the target feedback circuit, and at least a part of the amplified signal passes through the target feedback circuit to obtain a negative feedback signal, which is input to the input circuit101. The amplification circuit102then amplifies the signal obtained by adding the negative feedback signal and the input signal. Herein, the signal input to the amplification circuit102is the signal after the input signal is pulled down (adding the input signal and the negative feedback signal is equivalent to the absolute value of the input signal subtracting the negative feedback signal), and compared with the case that the signal input to the amplification circuit102is the input signal received by the input circuit101, the signal that has been pulled down is input to the amplification circuit102, which is equivalent to suppressing the signal input to the amplification circuit102, thereby improving the linearity of the amplification gain. In addition, for different input signals input to the input circuit101, the corresponding feedback circuit is selected as the target feedback circuit, which meets different requirements of gains of different types of input signals and makes the amplification performance of the amplifier more stable. As illustrated inFIG.10, the embodiments of the disclosure also provide an amplification method, which is applied to an amplifier. The amplifier includes an input circuit101, an amplification circuit102and at least two feedback circuits103a-103n; herein, the input circuit101is connected with an input end of the amplification circuit102; an output end of the amplification circuit102is connected with one end of each of the feedback circuits respectively; a second end of each of the feedback circuits is connected with the input circuit101respectively. In S1001: receiving, by the input circuit101, an input signal and a feedback signal. In S1002: amplifying, by the amplification circuit102, the input signal and the feedback signal to obtain an amplified signal. Herein, the feedback signal is fed back to the input circuit101by feeding back at least a part of the amplified signal through a target feedback circuit; and the target feedback circuit is a feedback circuit that depends on the type of the input signal in the at least two feedback circuits103a-103n. In the above solution, the type of the input signal includes a first type and a second type; herein the input signal of the second type includes a first subtype and a second subtype. In the case that the input signal is a signal of the first type or the first subtype, the target feedback circuit is a first feedback circuit103aof the at least two feedback circuits103a-103n. In the case that the input signal is a signal of the second subtype, the target feedback circuit is a second feedback circuit103bof the at least two feedback circuits103a-103n. In the above solution, the first feedback circuit103aincludes a first capacitive element, a first resistor and a second resistor; herein, a first end of the first capacitive element is connected with the input end of the amplification circuit102; a second end of the first capacitive element is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor; and the other end of the second resistor is connected with the output end of the amplification circuit102. Herein, in the case that the input signal is a signal of the first type or the first subtype, at least a part of the amplified signal is fed back to the input circuit101through the second resistor, the first resistor and the first capacitive element sequentially. In the above solution, the second feedback circuit103bincludes a second capacitive element and a third resistor; herein, a first end of the second capacitive element is connected with the input end of the amplification circuit102; and a second end of the second capacitive element is connected with one end of the third resistor. Herein, in the case that the input signal is a signal of the second subtype, at least a part of the amplified signal is fed back to the input circuit101through the third resistor and the second capacitive element sequentially. In the above solution, the second feedback circuit103bincludes a first capacitive element, a first resistor and a turn-on circuit; herein, a first end of the first capacitive element is connected with the input end of the amplification circuit102; a second end of the first capacitive element is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the turn-on circuit; and the other end of the turn-on circuit is connected with the output end of the amplification circuit. In the case that the input signal is a signal of the second subtype, at least a part of the amplified signal is fed back to the input circuit through the turn-on circuit, the first resistor and the first capacitive element sequentially. In the above solution, the amplifier also includes a selection circuit106; a first end of the selection circuit106is connected with the output end of the amplification circuit102; a second end of the selection circuit106is connected with the first feedback circuit103a; and a third end of the selection circuit106is connected with the second feedback circuit103b. With the selection circuit106, the first feedback circuit103ais selected as the target feedback circuit in the case that the input signal is of the first type and the first subtype, and the second feedback circuit103bis selected as the target feedback circuit in the case that the input signal is of the second subtype. In the above solution, the turn-on circuit is turned on in the case that the input signal is the signal of the second subtype; and is turned off in the case that the input signal is the signal of the first type or the first subtype. In the above solution, the turn-on circuit includes a switching unit and a diode which are connected in sequence. Herein, the switching unit is switched off in the case that the input signal is of the first type; and is switched off in the case that the input signal is of the second type. The diode is turned off in the case that the input signal is of the first subtype; and is turned on in the case that the input signal is of the second subtype. In the above solution, the amplifier also includes a power supplying circuit104; by connecting the power supplying circuit104with the power supplying end of the amplification circuit102to supply power to the amplification circuit102so that the amplification circuit102operates in the linear amplification region. The amplification circuit102operates in the linear amplification region and amplify the input signal and the feedback signal. It should be noted that for the amplification method of the embodiments of the disclosure, the principle of the amplification method to solve the problem is similar to that of the above-mentioned amplifier, therefore, the implementation process and implementation principle of the amplification method may refer to the description of the implementation process and implementation principle of the above-mentioned amplifier, and the repetition of descriptions will not be repeated. In several embodiments provided in the disclosure, it should be understood that the disclosed device and method may be implemented in other ways. The above-mentioned device embodiments are merely illustrative, for example, the division of the units is only a division based on logical functions, and there may be other divisions in actual implementations, e.g., multiple units or components may be combined, or may be integrated in another system, or some features may be ignored, or may not be performed. In addition, the coupling, or direct coupling, or communication connection between the components illustrated or discussed may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or otherwise. The above-mentioned units illustrated as separate components may be or may not be physically separated, and the components illustrated as units may be or may not be physical units, i.e., they may be located in one place or distributed to multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solutions of the embodiments. In addition, each functional unit in each of the embodiments of the disclosure may be all integrated in a processing unit, or each unit may be separately present as a single unit, or two or more units may be integrated in a single unit; the above integrated units may be realized either in the form of hardware or in the form of hardware together with software functional units. Those skilled in the art may understand that all or a part of the steps to realize the above-mentioned embodiments of the method may be realized by hardware related to program instructions, and the above-mentioned program may be stored in a computer readable storage medium, and when the program is executed, the steps including the above-mentioned embodiments of the method are executed; and the above-mentioned storage medium include various medium that may store program codes, such as mobile storage devices, Read-Only Memory (ROM), Random Access Memory (RAM), magnetic disks or optical disks, etc. In some embodiments of the disclosure, an amplifier can include at least two feedback circuits, and for different types of input signals, the corresponding feedback circuits may be determined from the at least two feedback circuits as the target feedback circuit, so that the feedback signal may be fed back by the target feedback circuit to realize normal amplification of the amplifier. The amplifier of the embodiments of the disclosure may at least meet the requirements of different types of input signals, and the amplifier is highly practical and feasible. The terms “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, elements referred to as “first” and “second” may include one or more of the features either explicitly or implicitly. In the description of the present disclosure, “a plurality” indicates two or more unless specifically defined otherwise. In the present disclosure, the terms “installed,” “connected,” “coupled,” “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, or integrated, unless otherwise explicitly defined. These terms can refer to mechanical or electrical connections, or both. Such connections can be direct connections or indirect connections through an intermediate medium. These terms can also refer to the internal connections or the interactions between elements. The specific meanings of the above terms in the present disclosure can be understood by those of ordinary skill in the art on a case-by-case basis. In the description of the present disclosure, the terms “one embodiment,” “some embodiments,” “example,” “specific example,” or “some examples,” and the like may indicate a specific feature described in connection with the embodiment or example, a structure, a material or feature included in at least one embodiment or example. In the present disclosure, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and reorganized. While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any claims, but rather as descriptions of features specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Thus, particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking or parallel processing may be utilized. It is intended that the specification and embodiments be considered as examples only. Other embodiments of the disclosure will be apparent to those skilled in the art in view of the specification and drawings of the present disclosure. That is, although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise. Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the example embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures. | 57,678 |
11942910 | DETAILED DESCRIPTION OF EMBODIMENTS The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. FIG.1is a schematic diagram of one example of a communication network10. The communication network10includes a macro cell base station1, a small cell base station3, and various examples of user equipment (UE), including a first mobile device2a, a wireless-connected car2b, a laptop2c, a stationary wireless device2d, a wireless-connected train2e, a second mobile device2f, and a third mobile device2g. Although specific examples of base stations and user equipment are illustrated inFIG.1, a communication network can include base stations and user equipment of a wide variety of types and/or numbers. For instance, in the example shown, the communication network10includes the macro cell base station1and the small cell base station3. The small cell base station3can operate with relatively lower power, shorter range, and/or with fewer concurrent users relative to the macro cell base station1. The small cell base station3can also be referred to as a femtocell, a picocell, or a microcell. Although the communication network10is illustrated as including two base stations, the communication network10can be implemented to include more or fewer base stations and/or base stations of other types. Although various examples of user equipment are shown, the teachings herein are applicable to a wide variety of user equipment, including, but not limited to, mobile phones, tablets, laptops, IoT devices, wearable electronics, customer premises equipment (CPE), wireless-connected vehicles, wireless relays, and/or a wide variety of other communication devices. Furthermore, user equipment includes not only currently available communication devices that operate in a cellular network, but also subsequently developed communication devices that will be readily implementable with the inventive systems, processes, methods, and devices as described and claimed herein. The illustrated communication network10ofFIG.1supports communications using a variety of cellular technologies, including, for example, 4G LTE and 5G NR. In certain implementations, the communication network10is further adapted to provide a wireless local area network (WLAN), such as WiFi. Although various examples of communication technologies have been provided, the communication network10can be adapted to support a wide variety of communication technologies. Various communication links of the communication network10have been depicted inFIG.1. The communication links can be duplexed in a wide variety of ways, including, for example, using frequency-division duplexing (FDD) and/or time-division duplexing (TDD). FDD is a type of radio frequency communications that uses different frequencies for transmitting and receiving signals. FDD can provide a number of advantages, such as high data rates and low latency. In contrast, TDD is a type of radio frequency communications that uses about the same frequency for transmitting and receiving signals, and in which transmit and receive communications are switched in time. TDD can provide a number of advantages, such as efficient use of spectrum and variable allocation of throughput between transmit and receive directions. In certain implementations, user equipment can communicate with a base station using one or more of 4G LTE, 5G NR, and WiFi technologies. In certain implementations, enhanced license assisted access (eLAA) is used to aggregate one or more licensed frequency carriers (for instance, licensed 4G LTE and/or 5G NR frequencies), with one or more unlicensed carriers (for instance, unlicensed WiFi frequencies). As shown inFIG.1, the communication links include not only communication links between UE and base stations, but also UE to UE communications and base station to base station communications. For example, the communication network10can be implemented to support self-fronthaul and/or self-backhaul (for instance, as between mobile device2gand mobile device2f). The communication links can operate over a wide variety of frequencies. In certain implementations, communications are supported using 5G NR technology over one or more frequency bands that are less than 6 Gigahertz (GHz) and/or over one or more frequency bands that are greater than 6 GHz. For example, the communication links can serve Frequency Range 1 (FR1), Frequency Range 2 (FR2), or a combination thereof. In one embodiment, one or more of the mobile devices support a HPUE power class specification. In certain implementations, a base station and/or user equipment communicates using beamforming. For example, beamforming can be used to focus signal strength to overcome path losses, such as high loss associated with communicating over high signal frequencies. In certain embodiments, user equipment, such as one or more mobile phones, communicate using beamforming on millimeter wave frequency bands in the range of 30 GHz to 300 GHz and/or upper centimeter wave frequencies in the range of 6 GHz to 30 GHz, or more particularly, 24 GHz to 30 GHz. Different users of the communication network10can share available network resources, such as available frequency spectrum, in a wide variety of ways. In one example, frequency division multiple access (FDMA) is used to divide a frequency band into multiple frequency carriers. Additionally, one or more carriers are allocated to a particular user. Examples of FDMA include, but are not limited to, single carrier FDMA (SC-FDMA) and orthogonal FDMA (OFDMA). OFDMA is a multicarrier technology that subdivides the available bandwidth into multiple mutually orthogonal narrowband subcarriers, which can be separately assigned to different users. Other examples of shared access include, but are not limited to, time division multiple access (TDMA) in which a user is allocated particular time slots for using a frequency resource, code division multiple access (CDMA) in which a frequency resource is shared amongst different users by assigning each user a unique code, space-divisional multiple access (SDMA) in which beamforming is used to provide shared access by spatial division, and non-orthogonal multiple access (NOMA) in which the power domain is used for multiple access. For example, NOMA can be used to serve multiple users at the same frequency, time, and/or code, but with different power levels. Enhanced mobile broadband (eMBB) refers to technology for growing system capacity of LTE networks. For example, eMBB can refer to communications with a peak data rate of at least 10 Gbps and a minimum of 100 Mbps for each user. Ultra-reliable low latency communications (uRLLC) refers to technology for communication with very low latency, for instance, less than 2 milliseconds. uRLLC can be used for mission-critical communications such as for autonomous driving and/or remote surgery applications. Massive machine-type communications (mMTC) refers to low cost and low data rate communications associated with wireless connections to everyday objects, such as those associated with Internet of Things (IoT) applications. The communication network10ofFIG.1can be used to support a wide variety of advanced communication features, including, but not limited to, eMBB, uRLLC, and/or mMTC. FIG.2Ais a schematic diagram of one example of a communication link using carrier aggregation. Carrier aggregation can be used to widen bandwidth of the communication link by supporting communications over multiple frequency carriers, thereby increasing user data rates and enhancing network capacity by utilizing fragmented spectrum allocations. In the illustrated example, the communication link is provided between a base station21and a mobile device22. As shown inFIG.2A, the communications link includes a downlink channel used for RF communications from the base station21to the mobile device22, and an uplink channel used for RF communications from the mobile device22to the base station21. AlthoughFIG.2Aillustrates carrier aggregation in the context of FDD communications, carrier aggregation can also be used for TDD communications. In certain implementations, a communication link can provide asymmetrical data rates for a downlink channel and an uplink channel. For example, a communication link can be used to support a relatively high downlink data rate to enable high speed streaming of multimedia content to a mobile device, while providing a relatively slower data rate for uploading data from the mobile device to the cloud. In the illustrated example, the base station21and the mobile device22communicate via carrier aggregation, which can be used to selectively increase bandwidth of the communication link. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous, and can include carriers separated in frequency within a common band or in different bands. In the example shown inFIG.2A, the uplink channel includes three aggregated component carriers fUL1, fUL2, and fUL3. Additionally, the downlink channel includes five aggregated component carriers fDL1, fDL2, fDL3, fDL4, and fDL5. Although one example of component carrier aggregation is shown, more or fewer carriers can be aggregated for uplink and/or downlink. Moreover, a number of aggregated carriers can be varied over time to achieve desired uplink and downlink data rates. For example, a number of aggregated carriers for uplink and/or downlink communications with respect to a particular mobile device can change over time. For example, the number of aggregated carriers can change as the device moves through the communication network and/or as network usage changes over time. FIG.2Billustrates various examples of uplink carrier aggregation for the communication link ofFIG.2A.FIG.2Bincludes a first carrier aggregation scenario31, a second carrier aggregation scenario32, and a third carrier aggregation scenario33, which schematically depict three types of carrier aggregation. The carrier aggregation scenarios31-33illustrate different spectrum allocations for a first component carrier full, a second component carrier fUL2, and a third component carrier fUL3. AlthoughFIG.2Bis illustrated in the context of aggregating three component carriers, carrier aggregation can be used to aggregate more or fewer carriers. Moreover, although illustrated in the context of uplink, the aggregation scenarios are also applicable to downlink. The first carrier aggregation scenario31illustrates intra-band contiguous carrier aggregation, in which component carriers that are adjacent in frequency and in a common frequency band are aggregated. For example, the first carrier aggregation scenario31depicts aggregation of component carriers fUL1, fUL2, and fUL3that are contiguous and located within a first frequency band BAND1. With continuing reference toFIG.2B, the second carrier aggregation scenario32illustrates intra-band non-continuous carrier aggregation, in which two or more components carriers that are non-adjacent in frequency and within a common frequency band are aggregated. For example, the second carrier aggregation scenario32depicts aggregation of component carriers fUL1, fUL2, and fUL3that are non-contiguous, but located within a first frequency band BAND1. The third carrier aggregation scenario33illustrates inter-band non-contiguous carrier aggregation, in which component carriers that are non-adjacent in frequency and in multiple frequency bands are aggregated. For example, the third carrier aggregation scenario33depicts aggregation of component carriers fUL1and fUL2of a first frequency band BAND1with component carrier fUL3of a second frequency band BAND2. FIG.2Cillustrates various examples of downlink carrier aggregation for the communication link ofFIG.2A. The examples depict various carrier aggregation scenarios34-38for different spectrum allocations of a first component carrier fDL1, a second component carrier fDL2, a third component carrier fDL3, a fourth component carrier fDL4, and a fifth component carrier fDL5. AlthoughFIG.2Cis illustrated in the context of aggregating five component carriers, carrier aggregation can be used to aggregate more or fewer carriers. Moreover, although illustrated in the context of downlink, the aggregation scenarios are also applicable to uplink. The first carrier aggregation scenario34depicts aggregation of component carriers that are contiguous and located within the same frequency band. Additionally, the second carrier aggregation scenario35and the third carrier aggregation scenario36illustrates two examples of aggregation that are non-contiguous, but located within the same frequency band. Furthermore, the fourth carrier aggregation scenario37and the fifth carrier aggregation scenario38illustrates two examples of aggregation in which component carriers that are non-adjacent in frequency and in multiple frequency bands are aggregated. As a number of aggregated component carriers increases, a complexity of possible carrier aggregation scenarios also increases. With reference toFIGS.2A-2C, the individual component carriers used in carrier aggregation can be of a variety of frequencies, including, for example, frequency carriers in the same band or in multiple bands. Additionally, carrier aggregation is applicable to implementations in which the individual component carriers are of about the same bandwidth as well as to implementations in which the individual component carriers have different bandwidths. Certain communication networks allocate a particular user device with a primary component carrier (PCC) or anchor carrier for uplink and a PCC for downlink. Additionally, when the mobile device communicates using a single frequency carrier for uplink or downlink, the user device communicates using the PCC. To enhance bandwidth for uplink communications, the uplink PCC can be aggregated with one or more uplink secondary component carriers (SCCs). Additionally, to enhance bandwidth for downlink communications, the downlink PCC can be aggregated with one or more downlink SCCs. In certain implementations, a communication network provides a network cell for each component carrier. Additionally, a primary cell can operate using a PCC, while a secondary cell can operate using a SCC. The primary and secondary cells may have different coverage areas, for instance, due to differences in frequencies of carriers and/or network environment. License assisted access (LAA) refers to downlink carrier aggregation in which a licensed frequency carrier associated with a mobile operator is aggregated with a frequency carrier in unlicensed spectrum, such as WiFi. LAA employs a downlink PCC in the licensed spectrum that carries control and signaling information associated with the communication link, while unlicensed spectrum is aggregated for wider downlink bandwidth when available. LAA can operate with dynamic adjustment of secondary carriers to avoid WiFi users and/or to coexist with WiFi users. Enhanced license assisted access (eLAA) refers to an evolution of LAA that aggregates licensed and unlicensed spectrum for both downlink and uplink. Examples of Adaptive Power Amplifier Biasing 5G provides enhanced flexibility in signaling, including a variable number of resource blocks (RBs) for control over signal bandwidth allocation. For example, certain 5G signals have a carrier bandwidth that can be adjusted up to about 100 MHz in frequency range 1 (FR1), with further flexibility in widening signal bandwidth by carrier aggregation. The variation in signal bandwidth provides a number of challenges to power amplification. For example, one performance specification of a power amplifier is adjacent channel power ratio (ACPR), which is based on power amplifier linearity. Poor ACPR can lead to a number of issues, such as degradation in signal reception on adjacent channels. The bandwidth of a biasing circuit directly effects the amount of ACPR created in the power amplifier, which in turn effects adjacent channel performance. For example, increasing the bandwidth of the biasing circuit allows more noise/spurs to reach the input of the power amplifier, since wider bandwidth provides less noise rejection. Thus, a trade-off is present between noise/spur rejection and linearity effects. There is a need for a power amplifier system suitable for handling wide bandwidth RF signals, while still maintaining performance for narrow bandwidth signals. Apparatus and methods for adaptive power amplifier biasing are provided herein. In certain embodiments, a power amplifier system includes a power amplifier that provides amplification to an RF signal, and a power amplifier bias control circuit that generates a bias signal of the power amplifier based on a bandwidth signal indicating a bandwidth of the RF signal. The power amplifier bias control circuit has a bandwidth that adapts to the bandwidth of the RF signal as indicated by the bandwidth signal. Thus, a narrow bias circuit bandwidth can be used for narrow signal bandwidth while a wide bias circuit bandwidth can be used for wide signal bandwidth. Accordingly, the bandwidth of the power amplifier bias control circuit can widen in response to the bandwidth signal indicating an increase in the bandwidth of the RF signal, and narrow in response to the bandwidth signal indicating a decrease in the bandwidth of the RF signal. In certain implementations, the power amplifier bias control circuit includes a bias circuit that generates a bias input signal, and a controllable filter that is controlled by the bandwidth signal and generates the bias signal of the power amplifier based on filtering the bias input signal. Accordingly, in certain implementations, the bandwidth signal is used to control a filtering characteristic of a filter of the power amplifier bias control circuit. The bandwidth signal can be provided to the power amplifier bias control circuit in a wide variety of ways, including from a baseband processor or by a self-detection circuit that automatically adapts the biasing bandwidth based on detecting the allocated bandwidth of the RF signal. In one example, the power amplifier bias control circuit is configured to receive the bandwidth signal as a digital data over a serial interface, such as a Mobile Industry Processor Interface Radio Frequency Front End (MIPI RFFE) bus. In another example, the power amplifier system further includes a detector that generates the bandwidth signal based on detecting the bandwidth of the RF signal. FIG.3is a schematic diagram of a power amplifier system50according to one embodiment. The power amplifier system50includes a power amplifier41and a power amplifier bias control circuit42. In the illustrated embodiment, the power amplifier41is powered by a power amplifier supply voltage VCC. Additionally, the power amplifier41amplifiers an RF input signal RFINto generate an RF output signal RFOUT. As shown inFIG.3, the power amplifier bias circuit42receives a bandwidth signal RFBW indicating a bandwidth of the RF input signal RFIN. Additionally, the power amplifier bias circuit42generates a bias signal BIAS of the power amplifier41based on the bandwidth signal RFBW. In certain implementations, the power amplifier bias control circuit42has a bandwidth that adapts to the bandwidth of the RF input signal RFINas indicated by the bandwidth signal RFBW. Accordingly, the bandwidth of the power amplifier bias control circuit42widens in response to the bandwidth signal RFBW indicating an increase in the bandwidth of the RF input signal RFIN, and narrows in response to the bandwidth signal RFBW indicating a decrease in the bandwidth of the RF input signal RFIN. Thus, a narrow bias circuit bandwidth is used for narrow signal bandwidth while a wide bias circuit bandwidth is used for wide signal bandwidth. FIG.4Ais a schematic diagram of a power amplifier system60according to another embodiment. The power amplifier system60ofFIG.4Ais similar to the power amplifier system50ofFIG.3, except that the power amplifier system60is coupled to a baseband processor53over a serial interface54. As shown inFIG.4A, the baseband processor53provides the power amplifier bias control circuit42with the bandwidth signal RFBW over the serial interface54. Thus, the bandwidth signal RFBW is provided by sending digital data over an interface or bus, in this embodiment. FIG.4Bis a schematic diagram of a power amplifier system70according to another embodiment. The power amplifier system70ofFIG.4Bis similar to the power amplifier system50ofFIG.3, except that the power amplifier system70further includes a directional coupler63and a detector64. In the illustrated embodiment, the directional coupler64generates a coupled signal based on sensing the RF input signal RFIN. Additionally, the detector64processes the coupled signed to generate the bandwidth signal RFBW. Accordingly, the bandwidth signal RFBW is generated by detecting the bandwidth of the RF input signal RFIN, in this embodiment. FIG.5is a schematic diagram of a power amplifier system80according to another embodiment. The power amplifier system80includes a power amplifier bias control circuit72and a power amplifier that includes a power amplifier transistor73, an input DC blocking capacitor74, and an output choke inductor75. In the illustrated embodiment, the base of the power amplifier transistor73receives the RF input signal RFINby way of the input DC blocking capacitor74. Additionally, the base of the power amplifier transistor73receives the bias signal BIAS from the power amplifier bias control circuit72. Furthermore, the emitter of the power amplifier transistor73is electrically connected to ground, and the collector of the power amplifier transistor73generates the RF output signal RFOUT. The collector of the power amplifier transistor73also receives a power amplifier supply voltage VCCby way of the output choke inductor75. AlthoughFIG.5illustrates one implementation of a power amplifier, skilled artisans will appreciate that the teachings described herein can be applied to a variety of power amplifier structures, such as multi-stage power amplifiers and power amplifiers employing other transistor structures. For example, in some implementations a bipolar power amplifier transistor can be omitted in favor of employing a field-effect transistor (FET), such as a silicon FET, a gallium arsenide (GaAs) high electron mobility transistor (HEMT), or a laterally diffused metal oxide semiconductor (LDMOS) transistor. In the illustrated embodiment, the power amplifier bias control circuit72includes a bias circuit77and a controllable filter78. As shown inFIG.5, the bias circuit77is powered by a battery voltage VBATTfrom a battery, and generates a bias input signal BIAS_IN for the controllable filter78. Additionally, the controllable filter78is controlled by the bandwidth signal RFBW and generates the bias signal BIAS for the power amplifier transistor73based on filtering the bias input signal BIAS_IN. Thus, the bandwidth signal RFBW controls a filtering characteristic of the controllable filter78. FIG.6is a schematic diagram of a power amplifier system110according to another embodiment. The power amplifier system110includes a power amplifier41, a directional coupler63, a power amplifier bias control circuit82, a detector84, and an analog-to-digital converter (ADC)85. Although one embodiment of a power amplifier system is depicted inFIG.6, the teachings herein are applicable to power amplifier systems implemented in a wide variety of ways. As shown inFIG.6, the power amplifier41amplifies an RF input signal RFINto generate an RF output signal RFOUT. Additionally, the power amplifier41is powered by a power amplifier supply voltage VCC, and receives a bias signal BIAS from the power amplifier bias control circuit82. With continuing reference toFIG.6, the directional coupler63senses the RF input signal RFINto generate a coupled signal that is provided to the detector84. The detector84processes the coupled signal to generate a bandwidth signal RFBW indicating the bandwidth of the RF input signal RFIN. The bandwidth signal RFBW is analog in this embodiment, and is converted to a multi-bit digital control signal SET<1:m> by the ADC85. Additionally, the multi-bit digital control signal SET<1:m> has m bits that are used to control the bandwidth of the power amplifier bias control circuit82, where m is an integer greater than 2, for instance, four or more. In the illustrated embodiment, the power amplifier bias control circuit82includes a bias circuit77and a controllable filter88. The bias circuit77receives a battery voltage VBATTand generates a bias input signal BIAS_IN. Additionally, the controllable filter88includes bandwidth control transistors91a,91b, . . .91m, shunt capacitors92a,92b, . . .92m, and series resistors93a,93b, . . .93m,93n. As shown in the embodiment ofFIG.6, the series resistors93a,93b, . . .93m,93nare electrically connected in series between the bias input signal BIAS_IN and the bias signal BIAS, while the shunt capacitors92a,92b, . . .92mare in shunt to the bias path through the series resistors93a,93b, . . .93m,93n. Additionally, the shunt capacitors92a,92b, . . .92mare selectively connected to ground or disconnected from ground using the bandwidth control transistors91a,91b, . . .91m, respectively. As shown inFIG.6, the bandwidth control transistors91a,91b, . . .91mare controlled by individual bits of the multi-bit digital control signal SET<1:m>, in this embodiment. Thus, the multi-bit digital control signal SET<1:m> is used to select an active number of the shunt capacitors92a,92b, . . .92m, in this embodiment. With continuing reference toFIG.6, the detector84includes an input series resistor95, an input shunt capacitor96, an input series capacitor97, a zero crossing comparator98, an output series resistor99, and an output shunt capacitor100, in this embodiment. The zero crossing comparator98serves to compare zero crossing of a high pass filtered detection signal Vhi to a low pass filtered detection signal Vlw to thereby extract the bandwidth of the RF input signal RFIN. Circuitry for processing the RF input signal RFINto generate the high pass filtered detection signal Vhi and the low pass filtered detection signal Vlw is not show inFIG.6. FIG.7Ais a graph of one example of ACPR for a 10 MHz RF signal bandwidth and a bias circuit bandwidth of 5 MHz.FIG.7Bis a graph of one example of ACPR for a 10 MHz RF signal bandwidth and a bias circuit bandwidth of 15 MHz.FIG.7Cis a graph of one example of ACPR for a 10 MHz RF signal bandwidth and a bias circuit bandwidth of 25 MHz. As shown inFIGS.7A-7C, increasing bias circuit bandwidth for a given signal bandwidth improves ACPR. FIG.8is a schematic diagram of a detector140according to one embodiment. In the illustrated embodiment, the detector140includes an RF to baseband detection circuit131and a bandwidth extractor132. As shown inFIG.8, the RF to baseband detection circuit141generates a baseband detection signal BBDET based on the RF input signal RFIN. In certain implementations, the RF to baseband detection circuit141is implemented as a root mean square (RMS) detector. However, other implementations are possible. The bandwidth extractor132processes the baseband detection signal BBDET to generate a bandwidth signal RFBW indicating a bandwidth of the RF input signal RFIN. In certain implementations, the bandwidth is detected based on processing the baseband detection signal BBDET to generate a high pass detection signal and a low pass detection signal, and comparing zero crossings of the high pass detection signal to zero crossings of the low pass detection signal. In certain implementations, the bandwidth signal RFBW is analog, and an ADC is included for generating a digital representation of the bandwidth signal RFBW. FIG.9is a schematic diagram of a detector190according to another embodiment. The detector190includes an RF to baseband detection circuit171and a bandwidth extractor172. The baseband detection circuit171includes a first RF differential detector173and a second RF differential detector174. Additionally, the bandwidth extractor172includes a high pass filter175, a low pass filter176, a first input resistor177, a second input resistor178, a comparator180, a first feedback resistor181, a second feedback resistor182, an output series capacitor144, a first output shunt resistor145, a diode146, a second output shunt resistor147, an output series resistor148, an output shunt capacitor149, and an output shunt current source150(which in certain implementations represents a leakage current). In the illustrated embodiment, the first RF differential detector173and the second RF differential detector174process the RF input signal RFINto generate a first differential baseband detection signal and a second differential baseband detection signal, respectively. Additionally, the high pass filter175high pass filters the first differential baseband detection signal to generate a high pass filtered signal for a first input of the comparator180, while the low pass filter176low pass filters the second differential baseband detection signal to generate a low pass filtered signal for a second input of the comparator180. In certain implementations, the high pass filter175and/or the low pass filter176are controllable. The output of the comparator180serves to generate pulses representing a comparison of zero crossings of the high pass filtered signal to zero crossings of the low pass filtered signal. In this example, the comparator180is implemented as an operational amplifier. However, other implementations are possible. The output pulses from the comparator180are processed by the output circuitry of the bandwidth extractor190to generate the bandwidth signal RFBW indicating a bandwidth of the RF input signal RFIN. In certain implementations, the bandwidth signal RFBW is further processed by a detection signal linearization circuit (see for example, the detection signal linearization circuitry ofFIGS.11and12) and/or converted to a digital signal using an ADC. FIG.10is a schematic diagram of an RF to baseband detection circuit200according to one embodiment. The RF to baseband detection circuit200ofFIG.10illustrates one embodiment of a detector for detecting the bandwidth of an RF signal. The RF to baseband detector200is implemented as a root mean square (RMS) detector, in this example. However, the teachings herein are applicable detectors implemented in a wide variety of ways. Accordingly, other implementations are possible. With continuing reference toFIG.10, the RF to baseband detection circuit200receives an RF input signal RFIN, and processes the RF input signal RFINto generate a differential detection signal corresponding to a difference between a non-inverted detection signal BBDET+ and an inverted detection signal BBDET−. The RF to baseband detection circuit200includes a first detection n-type field effect transistor (NFET)201, a second detection NFET202, a bias NFET203, a first biasing resistor211, a second biasing resistor212, a third biasing resistor213, a first detection resistor214, a second detection resistor215, an input capacitor221, and a filter capacitor222. The input capacitor221couples the RF input signal RFINto a gate of the first detection NFET201while providing DC voltage blocking. The first biasing resistor211and the second biasing resistor212control the DC bias voltages of the first detection NFET201and the second detection NFET202, respectively. The DC bias voltage level is based on a magnitude of a bias current provided through the bias NFET203and the third bias resistor213. The current through the first detection NFET203and the first detection resistor214changes in relation to the RF input signal RFIN. Additionally, the filter capacitor222operates to filter the voltage across the first detection resistor214. Thus, the non-inverted detection signal BBDET+ changes with the RF input signal RFIN. The non-inverted detection signal BBDET+ also includes a DC component that is based on DC biasing, including for example, a magnitude of the bias current Ibias. To compensate for DC biasing, the second detection NFET202the second detection resistor215are used to generate the inverted detection signal BBDET−, which has a DC component that tracks the DC component of the non-inverted detection signal. By using differential signaling, a detection signal that changes with an RMS value of the RF input signal RFINis provided, while compensating or correction for a DC bias offset or error. In the illustrated embodiment, the RF to baseband detection circuit200includes the first detection resistor214and the filter capacitor222, which serve to control the bandwidth of RMS detection. In certain implementations, at least one of the first detection resistor214or the filter capacitor222is controllable to provide flexibility in selecting an RMS detector bandwidth desired for a particular application and/or to compensate for process, voltage, and/or temperature (PVT) variation. FIG.11is a schematic diagram of a detection signal linearization circuit250according to one embodiment. The detection signal linearization circuit250ofFIG.11illustrates one embodiment of linearization circuitry for enhancing the performance of a detector. However, the teachings herein are applicable to detectors implemented in a wide variety of ways. Accordingly, other implementations are possible. The detection signal linearization circuit250is used to generate a bandwidth signal RFBW, which changes in relation to a signal bandwidth indicated by an input differential detection signal corresponding to a difference between a non-inverted detection signal VDET+ and an inverted detection signal VDET−. For example, the input differential detection signal to the detection signal linearization circuit250can correspond to an output of a bandwidth extractor (for instance, the bandwidth extractor132ofFIG.8or the bandwidth extractor172ofFIG.9), and the detection signal linearization circuit250can serve to linearize the detection signal to aid in processing by downstream circuitry (for instance, an ADC and/or a power amplifier bias control circuit). The detection signal linearization circuit250includes a first converter cell251, a second converter cell252, and a third converter cell253arranged in a cascade. As indicated by the ellipses, a desired number of converter cells can be included to achieve desired operating characteristics. In certain implementations, the detection signal linearization circuit250includes three or more cascaded converter cells. As shown inFIG.11, the first converter cell251generates a first current I1based on the input differential detection signal VDET+, VDET−. Additionally, the first converter cell251provides a first down-shifted detection signal to the second converter cell252based on down-shifting the voltage of the input detection signal VDET+, VDET−. The second converter cell252generates a second current I2based on the first down-shifted differential detection signal. The second converter cell252further provides a second down-shifted detection signal to the third converter cell253based on down-shifting the voltage of the first output detection signal. Furthermore, the third converter cell253generates a third current I3based on the second down-shifted detection signal. As shown inFIG.11, in the illustrated embodiment, the converter cells each include non-inverted input voltage VIN+, inverted input voltage VIN−, non-inverted output voltage VOUT+, inverted output voltage VOUT−, and output current Tout terminals. As shown inFIG.11, the currents from the converter cells251-253are summed to generate a total current ITOT, which flows through the impedance255to generate the bandwidth signal RFBW. In certain implementations, the impedance255is connected to a positive reference voltage, such as a power high supply voltage. FIG.12is a schematic diagram of one embodiment of a converter cell300for the detection signal linearization circuit250ofFIG.11. The converter cell300includes a first differential transistor pair including a first p-type field effect transistor (PFET)301and a second PFET302, and a second differential transistor pair including a third PFET303and a fourth PFET304. The converter cell300further includes a first load transistor pair including a fifth PFET305and a sixth PFET306, and a second load transistor pair including a first NFET311and a second NFET312. As shown inFIG.12, the first load transistor pair serves as a load to the first differential transistor pair, and the second load transistor pair serves as a load to the second differential transistor pair. The first differential transistor pair301-302amplifies a voltage difference between the differential input signal IN+, IN−. Additionally, the amplified voltage difference provided by the first differential transistor pair301-302is further amplified by the second differential transistor pair303-304to generate a differential output signal VOUT+, VOUT−. The current through the second NFET312is mirrored using the mirror NFET313to generate an output current Ioutfor the converter cell300. FIG.13Ais a graph of transient simulation results for one example of a detector detecting an RF signal with 10 RBs. FIG.13Bis a graph of transient simulation results for one example of a detector detecting an RF signal with 72 RBs. With reference toFIGS.13A and13B, transient simulation results showing plots of detection signal voltage versus time are provided for one implementation of the detector190ofFIG.9. Plots are included for a high pass filtered detection signal (detectRF_HPF) outputted from the high pass filter175and for a low pass filtered detection signal (detectRF_LPF) outputted from the low pass filter176. As shown by the example results ofFIGS.13A and13B, the number of zero crossings of the high pass filtered detection signal increases as the number of allocated RBs is increased. By comparing a number of zero crossings of the high pass filtered detection signal to a number of zero crossings of the low pass filtered detection signal, the number of RBs and thus the signal bandwidth can be detected. FIG.14Ais a graph of transient simulation results for one example of a detector detecting an RF signal with 10 RBs. FIG.14Bis a graph of transient simulation results for one example of a detector detecting an RF signal with 20 RBs. FIG.14Cis a graph of transient simulation results for one example of a detector detecting an RF signal with 30 RBs. FIG.14Dis a graph of transient simulation results for one example of a detector detecting an RF signal with 40 RBs. FIG.14Eis a graph of transient simulation results for one example of a detector detecting an RF signal with 50 RBs. FIG.14Fis a graph of transient simulation results for one example of a detector detecting an RF signal with 60 RBs. FIG.14Gis a graph of transient simulation results for one example of a detector detecting an RF signal with 70 RBs. FIG.14His a graph of transient simulation results for one example of a detector detecting an RF signal with 80 RBs. FIG.14Iis a graph of transient simulation results for one example of a detector detecting an RF signal with 90 RBs. FIG.14Jis a graph of transient simulation results for one example of a detector detecting an RF signal with 100 RBs. With reference toFIGS.14A-14J, transient simulation results showing plots of detection signal voltage versus time are provided for one implementation of the detector190ofFIG.9. Plots are included for a high pass filtered detection signal (detectRF_HPF) outputted from the high pass filter175and a low pass filtered detection signal (detectRF_LPF) outputted from the low pass filter176. The example results ofFIGS.14A-14Jshow that a comparison of the zero crossings of the high pass filtered detection signal to the zero crossings of the low pass filtered detection signal indicates the number of allocated RBs, which in turn indicates signal bandwidth. FIG.15is a graph of one example of detector voltage versus number of RBs. The graph corresponds to simulation results for one implementation of the detector190ofFIG.9in which the detector's output voltage is linearized using the signal detector linearization circuitry ofFIGS.11-12. In the example ofFIG.15, the detector voltage increase in relation to the number of RBs allocated to the RF signal. Additionally, detector voltage versus number of allocated RBs has a relatively linear slope. Although various examples of simulations results have been shown inFIGS.13A-15, simulation results can vary based on a number of factors, including, but not limited to, design implementation, simulation models, simulation parameters, and/or simulation tools. Accordingly, other results are possible. FIG.16is a schematic diagram of one embodiment of a mobile device800. The mobile device800includes a baseband system801, a transceiver802, a front end system803, antennas804, a power management system805, a memory806, a user interface807, and a battery808. The mobile device800can be used communicate using a wide variety of communications technologies, including, but not limited to, 2G, 3G, 4G (including LTE, LTE-Advanced, and LTE-Advanced Pro), 5G NR, WLAN (for instance, WiFi), WPAN (for instance, Bluetooth and ZigBee), WMAN (for instance, WiMax), and/or GPS technologies. The transceiver802generates RF signals for transmission and processes incoming RF signals received from the antennas804. It will be understood that various functionalities associated with the transmission and receiving of RF signals can be achieved by one or more components that are collectively represented inFIG.16as the transceiver802. In one example, separate components (for instance, separate circuits or dies) can be provided for handling certain types of RF signals. The front end system803aids is conditioning signals transmitted to and/or received from the antennas804. In the illustrated embodiment, the front end system803includes antenna tuning circuitry810, power amplifiers (PAs)811, low noise amplifiers (LNAs)812, filters813, switches814, and signal splitting/combining circuitry815. However, other implementations are possible. For example, the front end system803can provide a number of functionalities, including, but not limited to, amplifying signals for transmission, amplifying received signals, filtering signals, switching between different bands, switching between different power modes, switching between transmission and receiving modes, duplexing of signals, multiplexing of signals (for instance, diplexing or triplexing), or some combination thereof. In certain implementations, the mobile device800supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD), and may be used to aggregate a plurality of carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous, and can include carriers separated in frequency within a common band or in different bands. The antennas804can include antennas used for a wide variety of types of communications. For example, the antennas804can include antennas for transmitting and/or receiving signals associated with a wide variety of frequencies and communications standards. In certain implementations, the antennas804support MIMO communications and/or switched diversity communications. For example, MIMO communications use multiple antennas for communicating multiple data streams over a single radio frequency channel. MIMO communications benefit from higher signal to noise ratio, improved coding, and/or reduced signal interference due to spatial multiplexing differences of the radio environment. Switched diversity refers to communications in which a particular antenna is selected for operation at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on a variety of factors, such as an observed bit error rate and/or a signal strength indicator. The mobile device800can operate with beamforming in certain implementations. For example, the front end system803can include amplifiers having controllable gain and phase shifters having controllable phase to provide beam formation and directivity for transmission and/or reception of signals using the antennas804. For example, in the context of signal transmission, the amplitude and phases of the transmit signals provided to the antennas804are controlled such that radiated signals from the antennas804combine using constructive and destructive interference to generate an aggregate transmit signal exhibiting beam-like qualities with more signal strength propagating in a given direction. In the context of signal reception, the amplitude and phases are controlled such that more signal energy is received when the signal is arriving to the antennas804from a particular direction. In certain implementations, the antennas804include one or more arrays of antenna elements to enhance beamforming. The baseband system801is coupled to the user interface807to facilitate processing of various user input and output (I/O), such as voice and data. The baseband system801provides the transceiver802with digital representations of transmit signals, which the transceiver802processes to generate RF signals for transmission. The baseband system801also processes digital representations of received signals provided by the transceiver802. As shown inFIG.16, the baseband system801is coupled to the memory806of facilitate operation of the mobile device800. The memory806can be used for a wide variety of purposes, such as storing data and/or instructions to facilitate the operation of the mobile device800and/or to provide storage of user information. The power management system805provides a number of power management functions of the mobile device800. In certain implementations, the power management system805includes a PA supply control circuit that controls the supply voltages of the power amplifiers811. For example, the power management system805can be configured to change the supply voltage(s) provided to one or more of the power amplifiers811to improve efficiency, such as power added efficiency (PAE). As shown inFIG.16, the power management system805receives a battery voltage from the battery808. The battery808can be any suitable battery for use in the mobile device800, including, for example, a lithium-ion battery. FIG.17is a schematic diagram of a power amplifier system860according to one embodiment. The illustrated power amplifier system860includes a baseband processor841, a transmitter/observation receiver842, a power amplifier (PA)843, a directional coupler844, front-end circuitry845, an antenna846, a PA bias control circuit847, and a PA supply control circuit848. The illustrated transmitter/observation receiver842includes an I/Q modulator857, a mixer858, and an analog-to-digital converter (ADC)859. In certain implementations, the transmitter/observation receiver842is incorporated into a transceiver. The baseband processor841can be used to generate an in-phase (I) signal and a quadrature-phase (Q) signal, which can be used to represent a sinusoidal wave or signal of a desired amplitude, frequency, and phase. For example, the I signal can be used to represent an in-phase component of the sinusoidal wave and the Q signal can be used to represent a quadrature-phase component of the sinusoidal wave, which can be an equivalent representation of the sinusoidal wave. In certain implementations, the I and Q signals can be provided to the I/Q modulator857in a digital format. The baseband processor841can be any suitable processor configured to process a baseband signal. For instance, the baseband processor841can include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Moreover, in some implementations, two or more baseband processors841can be included in the power amplifier system860. The I/Q modulator857can be configured to receive the I and Q signals from the baseband processor841and to process the I and Q signals to generate an RF signal. For example, the I/Q modulator857can include digital-to-analog converters (DACs) configured to convert the I and Q signals into an analog format, mixers for upconverting the I and Q signals to RF, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier843. In certain implementations, the I/Q modulator857can include one or more filters configured to filter frequency content of signals processed therein. The power amplifier843can receive the RF signal from the I/Q modulator857, and when enabled can provide an amplified RF signal to the antenna846via the front-end circuitry845. The front-end circuitry845can be implemented in a wide variety of ways. In one example, the front-end circuitry845includes one or more switches, filters, duplexers, multiplexers, and/or other components. In another example, the front-end circuitry845is omitted in favor of the power amplifier843providing the amplified RF signal directly to the antenna846. The directional coupler844senses an output signal of the power amplifier823. Additionally, the sensed output signal from the directional coupler844is provided to the mixer858, which multiplies the sensed output signal by a reference signal of a controlled frequency. The mixer858operates to generate a downshifted signal by downshifting the sensed output signal's frequency content. The downshifted signal can be provided to the ADC859, which can convert the downshifted signal to a digital format suitable for processing by the baseband processor841. Including a feedback path from the output of the power amplifier843to the baseband processor841can provide a number of advantages. For example, implementing the baseband processor841in this manner can aid in providing power control, compensating for transmitter impairments, and/or in performing digital pre-distortion (DPD). Although one example of a sensing path for a power amplifier is shown, other implementations are possible. The PA supply control circuit848receives a power control signal from the baseband processor841, and controls supply voltages of the power amplifier843. In the illustrated configuration, the PA supply control circuit848generates a first supply voltage VCC1for powering an input stage of the power amplifier843and a second supply voltage VCC2for powering an output stage of the power amplifier843. The PA supply control circuit848can control the voltage level of the first supply voltage VCC1and/or the second supply voltage VCC2to enhance the power amplifier system's PAE. The PA supply control circuit848can employ various power management techniques to change the voltage level of one or more of the supply voltages over time to improve the power amplifier's power added efficiency (PAE), thereby reducing power dissipation. One technique for improving efficiency of a power amplifier is average power tracking (APT), in which a DC-to-DC converter is used to generate a supply voltage for a power amplifier based on the power amplifier's average output power. Another technique for improving efficiency of a power amplifier is envelope tracking (ET), in which a supply voltage of the power amplifier is controlled in relation to the envelope of the RF signal. Thus, when a voltage level of the envelope of the RF signal increases the voltage level of the power amplifier's supply voltage can be increased. Likewise, when the voltage level of the envelope of the RF signal decreases the voltage level of the power amplifier's supply voltage can be decreased to reduce power consumption. In certain configurations, the PA supply control circuit848is a multi-mode supply control circuit that can operate in multiple supply control modes including an APT mode and an ET mode. For example, the power control signal from the baseband processor841can instruct the PA supply control circuit848to operate in a particular supply control mode. As shown inFIG.17, the PA bias control circuit847receives a bias control signal from the baseband processor841, and generates bias control signals for the power amplifier843. In the illustrated configuration, the bias control circuit847generates bias control signals for both an input stage of the power amplifier843and an output stage of the power amplifier843. However, other implementations are possible. The PA bias control circuit847can be implemented in accordance with any of the embodiments herein. FIG.18Ais a schematic diagram of one embodiment of a packaged module900.FIG.18Bis a schematic diagram of a cross-section of the packaged module900ofFIG.18Ataken along the lines18B-18B. The packaged module900includes radio frequency components901, a semiconductor die902, surface mount devices903, wirebonds908, a package substrate920, and an encapsulation structure940. The package substrate920includes pads906formed from conductors disposed therein. Additionally, the semiconductor die902includes pins or pads904, and the wirebonds908have been used to connect the pads904of the die902to the pads906of the package substrate920. The semiconductor die902includes a power amplifier system945, which can be implemented in accordance with any of the embodiments herein. The packaging substrate920can be configured to receive a plurality of components such as radio frequency components901, the semiconductor die902and the surface mount devices903, which can include, for example, surface mount capacitors and/or inductors. In one implementation, the radio frequency components901include integrated passive devices (IPDs). As shown inFIG.18B, the packaged module900is shown to include a plurality of contact pads932disposed on the side of the packaged module900opposite the side used to mount the semiconductor die902. Configuring the packaged module900in this manner can aid in connecting the packaged module900to a circuit board, such as a phone board of a mobile device. The example contact pads932can be configured to provide radio frequency signals, bias signals, and/or power (for example, a power supply voltage and ground) to the semiconductor die902and/or other components. As shown inFIG.18B, the electrical connections between the contact pads932and the semiconductor die902can be facilitated by connections933through the package substrate920. The connections933can represent electrical paths formed through the package substrate920, such as connections associated with vias and conductors of a multilayer laminated package substrate. In some embodiments, the packaged module900can also include one or more packaging structures to, for example, provide protection and/or facilitate handling. Such a packaging structure can include overmold or encapsulation structure940formed over the packaging substrate920and the components and die(s) disposed thereon. It will be understood that although the packaged module900is described in the context of electrical connections based on wirebonds, one or more features of the present disclosure can also be implemented in other packaging configurations, including, for example, flip-chip configurations. Applications Some of the embodiments described above have provided examples in connection with wireless devices or mobile phones. However, the principles and advantages of the embodiments can be used for any other systems or apparatus that have needs for power amplifiers. Such power amplifiers can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include, but are not limited to, memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, an automobile, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wrist watch, a clock, etc. Further, the electronic devices can include unfinished products. CONCLUSION Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “can,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or states are included or are to be performed in any particular embodiment. The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 61,740 |
11942911 | DESCRIPTION OF EMBODIMENTS Hereinafter, a radio-frequency power amplifier device according to embodiments will be described with reference to the drawings. It should be noted that the embodiments described below each show a specific example of the present disclosure. The values, shapes, materials, constituent elements, the arrangement and connection of the constituent elements, etc. in the following embodiments are mere examples, and therefore are not intended to limit the scope of the present disclosure. Additionally, among the constituent elements in the following embodiments, those not recited in any one of the independent claims indicating the broadest concepts are described as optional constituent elements. Moreover, the respective figures are schematic diagrams and are not necessarily precise illustrations. In the figures, elements that are essentially the same have the same reference signs, and duplicate description may be omitted or simplified. Furthermore, in the Description, the terms “above” and “below” in the configuration of a radio-frequency power amplifier device do not refer to the upward (vertically upward) direction and downward (vertically downward) in terms of absolute space. Those terms are defined by relative positional relationships based on a stacking order in a stacked structure. Moreover, the terms “above” and “below” apply not only when two constituent elements are disposed spaced apart and some other constituent element is interposed between the two constituent elements, but also when two constituent elements are disposed in close proximity to each other such that the two constituent elements are in contact with each other. Furthermore, in the Description and the drawings, an X-axis, a Y-axis, and a Z-axis represent three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, a stacked direction of each resin layer in a multilayer submount substrate included in a radio-frequency power amplifier device is a Z-axis direction, and two axes parallel to a principal surface of the multilayer submount substrate are an X-axis direction and a Y-axis direction. In addition, a “plan view” in the Description refers to a view of the radio-frequency power amplifier device from the Z-axis direction. Moreover, in the Description, terms indicating relationships between elements, such as “orthogonal” and “the same”, terms indicating the shapes of elements, such as “rectangular” and “obround”, numerical values, and numerical value ranges are not expressions that indicate only the strict meanings but are expressions that mean substantially equivalent ranges and include, for example, an error of approximately several percent (e.g., approximately 10%). Furthermore, in the Description, “disposed” is an expression meaning “placed”, “mounted”, “provided”, or “wired”. Embodiment 1 A radio-frequency power amplifier device according to Embodiment 1 will be described with reference toFIG.1AtoFIG.1C.FIG.1Ashows an example of a plan view of radio-frequency power amplifier device200according to Embodiment 1.FIG.1Bshows an example of a cross sectional structural view of radio-frequency power amplifier device200according to Embodiment 1, taken along section line IB-IB inFIG.1A. InFIG.1B, hatching of each of resin layers (first resin layer116, second resin layer117, third resin layer118) is omitted for the sake of simplicity. Multilayer submount substrate100is a stacked substrate in which a plurality of resin layers (e.g., epoxy-based resin layers) are stacked, and is a multilayer submount substrate including three resin layers (first resin layer116, second resin layer117, and third resin layer118) in Embodiment 1. Multilayer submount substrate100is produced by stacking, for example, prepreg layers and metal layers (wiring layers) above and below a core substrate (a single-layer substrate covered on both surfaces with metal) as the center. In Embodiment 1, multilayer submount substrate100is a resin triple-layer and metal quadruple-layer substrate in which metal layers and resin layers are alternately stacked. It should be noted that the number of resin layers of multilayer submount substrate100is not limited to three, and may be at least two. Moreover, a method of preparing multilayer submount substrate100and a resin material are not limited to the above examples. Multilayer submount substrate100includes: first resin layer116; second resin layer117; third resin layer118; first wiring layer103on a first principal surface101side (a Z-axis plus side) of first resin layer116; second wiring layer104between first resin layer116and second resin layer117; third wiring layer105between second resin layer117and third resin layer118; and fourth wiring layer106on a second principal surface102side (a Z-axis minus side) of third resin layer118. Multilayer submount substrate100includes the following mounted on first principal surface101: carrier amplifier semiconductor device11for amplifying a first radio-frequency signal; peak amplifier semiconductor device12for amplifying a second radio-frequency signal; and bias power supply semiconductor device13that supplies a bias power supply voltage to carrier amplifier semiconductor device11and peak amplifier semiconductor device12. Radio-frequency power amplifier device200is a radio-frequency power amplifier device of a hybrid type (Doherty type) in which carrier amplifier semiconductor device11and peak amplifier semiconductor device12are disposed (provided). Carrier amplifier semiconductor device11and peak amplifier semiconductor device12each are also referred to as a Doherty amplifier. Carrier amplifier semiconductor device11is an amplifier that performs class AB operation or class B operation and amplifies a first radio-frequency signal, and operates in the entire output power range of radio-frequency power amplifier device200. Carrier amplifier semiconductor device11is a semiconductor chip including an amplifier (carrier amplifier). Peak amplifier semiconductor device12is an amplifier that performs class C operation and amplifies a second radio-frequency signal, and operates only in an operating range in which the output power of radio-frequency power amplifier device200is high. Peak amplifier semiconductor device12is a semiconductor chip including an amplifier (peak amplifier). Carrier amplifier semiconductor device11is supplied with a power supply voltage via carrier amplifier power supply wiring43, and peak amplifier semiconductor device12is supplied with a power supply voltage via peak amplifier power supply wiring44. Carrier amplifier power supply wiring43is connected to the drain electrode of an amplifier included in carrier amplifier semiconductor device11, and peak amplifier power supply wiring44is connected to the drain electrode of an amplifier included in peak amplifier semiconductor device12. Bias power supply semiconductor device13comprises, for example, gallium arsenide (GaAs), and is configured to output a carrier-amplifier bias power supply voltage and a peak-amplifier bias power supply voltage to carrier amplifier semiconductor device11and peak amplifier semiconductor device12, respectively, and to control these bias power supply voltages independently of each other. Bias power supply semiconductor device13is a semiconductor chip capable of outputting a carrier-amplifier bias power supply voltage and a peak-amplifier bias power supply voltage. Radio-frequency power amplifier device200includes first radio-frequency signal wiring1and second radio-frequency signal wiring2as radio-frequency signal wiring. First radio-frequency signal wiring1through which the first radio-frequency signal passes is provided in first wiring layer103provided on first principal surface101of multilayer submount substrate100. First radio-frequency signal wiring1transmits the first radio-frequency signal to carrier amplifier semiconductor device11. The first radio-frequency signal is an example of a radio-frequency signal. Second radio-frequency signal wiring2through which the second radio-frequency signal passes is provided in first wiring layer103provided on first principal surface101of multilayer submount substrate100. Second radio-frequency signal wiring2transmits the second radio-frequency signal to peak amplifier semiconductor device12. The second radio-frequency signal is an example of a radio-frequency signal. Radio-frequency power amplifier device200includes carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32. Carrier-amplifier bias power supply wiring31to which the carrier-amplifier bias power supply voltage outputted from bias power supply semiconductor device13is supplied is provided in third wiring layer105. Carrier-amplifier bias power supply wiring31supplies the carrier-amplifier bias power supply voltage to carrier amplifier semiconductor device11. In Embodiment 1, the carrier-amplifier bias power supply voltage is directly applied to the gate electrode of the amplifier included in carrier amplifier semiconductor device11. The carrier-amplifier bias power supply voltage is a bias voltage (gate bias voltage) supplied to the amplifier included in carrier amplifier semiconductor device11. Peak-amplifier bias power supply wiring32to which the peak-amplifier bias power supply voltage outputted from bias power supply semiconductor device13is supplied is provided in third wiring layer105. Peak-amplifier bias power supply wiring32supplies the peak-amplifier bias power supply voltage to peak amplifier semiconductor device12. In Embodiment 1, the peak-amplifier bias power supply voltage is directly applied to the gate electrode of the amplifier included in peak amplifier semiconductor device12. The peak-amplifier bias power supply voltage is a bias voltage (gate bias voltage) supplied to the amplifier included in peak amplifier semiconductor device12. Bias power supply semiconductor device13is connected to analog power supply wiring36. Analog power supply wiring36is power supply wiring for connecting bias power supply semiconductor device13and an external device (control device) of radio-frequency power amplifier device200, and supplies a power supply voltage to bias power supply semiconductor device13. Second radio-frequency signal wiring2and carrier-amplifier bias power supply wiring31intersect in a plan view. In Embodiment 1, second radio-frequency signal wiring2and carrier-amplifier bias power supply wiring31are orthogonal at an intersection portion thereof in the plan view. It can also be said that radio-frequency power amplifier device200includes intersection portion100aincluding a structure in which radio-frequency signal wiring and bias power supply wiring intersect (three-dimensionally intersect) in a plan view of multilayer submount substrate100. When the second radio-frequency signal of peak amplifier semiconductor device12and a carrier-amplifier-semiconductor bias power supply signal (e.g., a carrier-amplifier bias power supply voltage) interfere, the operation of carrier amplifier semiconductor device11or peak amplifier semiconductor device12becomes unstable. Moreover, a problem such as no distortion compensation by DPD (no low distortion characteristics achieved) occurs. Accordingly, it is possible to reduce intersignal interference by arranging sets of signal wiring to be mutually orthogonal to reduce an overlapping portion in a plan view. Additionally, it is possible to further reduce the intersignal interference by disposing first shield pattern121set to a ground electric potential in a region of second wiring layer104including intersection portion100ain the plan view. First shield pattern121is a solid pattern disposed in a region, which corresponds to intersection portion100a, of second wiring layer104between first wiring layer103and third wiring layer105. The region corresponding to intersection portion100ais a region having a predetermined range that includes intersecting portions. It can also be said that the region corresponding to intersection portion100ais a region having a predetermined range that includes intersection portion100ain a plan view. A plan view shape of first shield pattern121is a rectangular shape, but the present disclosure is not limited to this example. It should be noted that first shield pattern121is not limited to being provided in second wiring layer104, and may be provided in any of wiring layers between a wiring layer in which carrier-amplifier bias power supply wiring31or peak-amplifier bias power supply wiring32is provided and a wiring layer in which second radio-frequency signal wiring2is provided. In addition, the solid pattern includes a solid pattern that is partially slit. FIG.1Cshows an example of a plan view of each of wiring layers in intersection portion100aof radio-frequency power amplifier device200according to Embodiment 1. (a) ofFIG.1Cis a plan view of first wiring layer103, (b) ofFIG.1Cis a plan view of second wiring layer104, (c) ofFIG.1Cis a plan view of third wiring layer105, and (d) ofFIG.1Cis a plan view of fourth wiring layer106. In (c) ofFIG.1C, W denotes the width (length in the Y-axis direction) of carrier-amplifier bias power supply wiring31, and P denotes a space between one or more connection vias131and carrier-amplifier bias power supply wiring31. As shown in (b) ofFIG.1C, a plan view shape of first shield pattern121is, for example, a rectangular shape elongated in an extension direction (the X-axis direction) of carrier-amplifier bias power supply wiring31. Moreover, first shield pattern121also serves as a radio-frequency-signal ground electric potential wire for second radio-frequency signal wiring2. When second radio-frequency signal wiring2is a microstrip line, immediately before second radio-frequency signal wiring2overlaps first shield pattern121in a plan view, ground electrode pattern123is a radio-frequency-signal ground electric potential wire, and first shield pattern121becomes a radio-frequency-signal ground electric potential wire in an overlapping portion. In order to make a characteristic impedance of the line of second radio-frequency signal wiring2the same value before and after the overlapping, it is necessary to decrease the width of second radio-frequency signal wiring2in the overlapping portion, and a transmission loss increases. Moreover, when the width of second radio-frequency signal wiring2remains the same before and after the overlapping, the characteristic impedance varies, so a reflection loss occurs. For this reason, it is desirable that the width (length in the Y-axis direction) of first shield pattern121be narrow as much as possible. Here, with regard to space P, the following describes, as an example, intersignal interference (isolation) for a line space between two microstrip lines (e.g., quarter-wave lines having a characteristic impedance of 50Ω) having width W that are provided in the same wiring layer. A simulation of isolation for a line space between the two microstrip lines shows that isolation is −39 dB when the line space is three times as large as width W, and intersignal interference between the lines has no effect when the line space becomes more than three times as large as width W. In other words, intersignal interference measures should be taken for a range within a distance that is three times as large as width W. Likewise, in order to prevent noise of carrier-amplifier bias power supply wiring31from causing intersignal interference with other lines, intersignal interference measures should be taken for a range within a distance that is three times as large as width W of carrier-amplifier bias power supply wiring31. To put it differently, space P should be made within a distance that is three times as large as width W of carrier-amplifier bias power supply wiring31. As shown in (c) ofFIG.1C, a plurality of ground electric potential connection vias131are spaced apart from each other in an extension direction of carrier-amplifier bias power supply wiring31, on both sides of carrier-amplifier bias power supply wiring31within a distance that is three times as large as width W of carrier-amplifier bias power supply wiring31(P<3×W). As shown in (c) ofFIG.1C, carrier-amplifier bias power supply wiring31is located between the plurality of ground electric potential connection vias131in a plan view. It should be noted that a value of three times is an example and is determined appropriately. The plurality of connection vias131are connected to first shield pattern121of second wiring layer104and ground electrode pattern123provided in fourth wiring layer106. In other words, first shield pattern121is connected to ground electrode pattern123via the plurality of connection vias131and connection via pattern111provided in third wiring layer105. Connection via pattern111is in a rectangular shape elongated in the extension direction of carrier-amplifier bias power supply wiring31, to electrically connect the plurality of connection vias131. Connection via131is also referred to as a ground connection via. In such radio-frequency power amplifier device200, as shown inFIG.1B, carrier-amplifier bias power supply wiring31is surrounded by first shield pattern121, the plurality of connection vias131, and ground electrode pattern123in a cross-section view. Although only carrier-amplifier bias power supply wiring31is indicated in the above configuration, a configuration in which two sets of bias power supply wiring, carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32, are surrounded by first shield pattern121, the plurality of connection vias131, and ground electrode pattern123is entirely acceptable. In addition, ground electric potential connection via131may be a through via or a filled via. It is possible to take further interference prevention measures by surrounding, in a tunnel shape, carrier-amplifier bias power supply wiring31or peak-amplifier bias power supply wiring32that is signal wiring with which the interference is to be prevented. Such a configuration makes it possible to achieve the downsizing and adjustment-free function of a set board, adjust each of carrier amplifier semiconductor device11and peak amplifier semiconductor device12to an optimum bias point, and further reduce interference between a radio-frequency signal and a bias signal. Accordingly, radio-frequency power amplifier device200becomes capable of achieving low distortion characteristics due to a highly efficient operation and DPD. It should be noted thatFIG.1Cis a diagram illustrating an example of the shape of a ground electric potential connection via. The shape of ground electric potential connection via131is not limited to a circular shape in a plan view of radio-frequency power amplifier device200, and may be an obround shape. For example, connection vias131in an obround shape may be spaced apart from each other along carrier-amplifier bias power supply wiring31. Since it is possible to reduce a ratio of space between connection vias131by causing the plan view shape to be the obround shape, an interference prevention effect is further achieved. Moreover, the carrier-amplifier bias power supply voltage or the peak-amplifier bias power supply voltage outputted from bias power supply semiconductor device13may be directly applied to carrier amplifier semiconductor device11or peak amplifier semiconductor device12, respectively, or may be converted and then applied thereto. Embodiment 2 FIG.2is a diagram illustrating an example of a wire connection between carrier amplifier semiconductor device11and multilayer submount substrate100according to Embodiment 2. In Embodiment 2, an example in which carrier amplifier semiconductor device11contains first gate bias circuit21will be described. First gate bias circuit21is an example of a bias circuit, is supplied with a bias power supply voltage from bias power supply semiconductor device13, and supplies a bias voltage (gate bias voltage) to gate electrode151. Carrier amplifier semiconductor device11is disposed on die pad (die pad layer)124provided in first wiring layer103of multilayer submount substrate100, and includes transistor150included in a carrier amplifier, and first gate bias circuit21that supplies a gate bias voltage to gate electrode151of transistor150. A carrier-amplifier bias power supply voltage is supplied to input terminal161of first gate bias circuit21, and a gate bias voltage is outputted from output terminal162of first gate bias circuit21. Since a threshold voltage of transistor150varies for each of semiconductor chips, it is possible to perform bias control with higher accuracy by providing, in first gate bias circuit21, a circuit that compensates a variation in threshold. The carrier-amplifier bias power supply voltage outputted from bias power supply semiconductor device13is supplied from first wiring pattern107provided in first wiring layer103of multilayer submount substrate100to input terminal161of first gate bias circuit21via first connecting wire141. Though not shown inFIG.2, first wiring pattern107is electrically connected to carrier-amplifier bias power supply wiring31. A gate bias voltage is outputted from output terminal162of first gate bias circuit21to second wiring pattern108via second connecting wire142. The gate bias voltage is supplied from second wiring pattern108to gate electrode151of transistor150included in the carrier amplifier via a plurality of third connecting wires143(four inFIG.2). Second connecting wire142connects second wiring pattern108of first wiring layer103and output terminal162of first gate bias circuit21. Third connecting wire143connects second wiring pattern108and a gate terminal connected to gate electrode151. An increase in output voltage requires an increase in transistor size (Wg) of a power amplifier. An increase in transistor size results in an increase in the number of gate fingers, and there is a possibility that amplifying a radio-frequency signal in this state causes loop oscillation. For this reason, generally, loop oscillation measures are taken by inserting resistor152of approximately 2Ω to 5Ω between gate electrodes connected in parallel when the transistor size is increased. Since resistor152is connected between the gate electrodes, supplying a gate bias voltage from first gate bias circuit21directly to closest gate electrode151causes an electric potential difference in the gate bias voltage supplied to gate electrode151due to a voltage drop by resistor152. This electric potential difference can contribute to the uneven operation of transistor150. Accordingly, the gate bias voltage is supplied from first gate bias circuit21to gate electrode151of transistor150included in the carrier amplifier once via a wiring pattern (e.g., second wiring pattern108) provided in first wiring layer103of multilayer submount substrate100. Moreover, an input signal to carrier amplifier semiconductor device11that amplifies the first radio-frequency signal is connected from third wiring pattern109to gate electrode151of transistor150included in the carrier amplifier via a plurality of fourth connecting wires144(four inFIG.2). The input signal is inputted via a path different from the path of the gate bias voltage. The configuration shown inFIG.2makes it possible to reduce the interference between the radio-frequency signal and the bias signal (gate bias voltage), which enables achieving the low distortion characteristics due to the highly efficient operation and the DPD. It should be noted that although Embodiment 2 has described the example in which first gate bias circuit21is provided in carrier amplifier semiconductor device11, a gate bias circuit may be provided in peak amplifier semiconductor device12. In this case, a second radio-frequency signal and a gate bias voltage may be inputted to the gate electrode of a transistor included in a peak amplifier via a different path. In addition, a peak-amplifier bias power supply voltage is supplied to an input terminal of the gate bias circuit of peak amplifier semiconductor device12via a wiring pattern electrically connected to peak-amplifier bias power supply wiring32. Moreover, though not shown inFIG.2, when carrier amplifier semiconductor device11further contains a capacitor for matching, second wiring pattern108may be connected to a terminal of the capacitor with a connecting wire. Since the connecting wire can be viewed as an inductor component in a radio-frequency wave, a matching circuit including the inductor component obtained by combining the connecting wire to the terminal of the capacitor and third connecting wire143can be configured. Furthermore, as shown inFIG.2, drain electrode153of transistor150is connected to fourth wiring pattern110via fifth connecting wires145. Additionally, although source electrode154of transistor150is disposed between gate electrode151and drain electrode153in a plan view, the present disclosure is not limited to this example. Embodiment 3 FIG.3shows an example of a cross sectional structural view for illustrating signal interference measures by an arrangement of vias in resin layers of multilayer submount substrate100according to Embodiment 3.FIG.3is a cross-sectional view of a region of multilayer submount substrate100other than intersection portion100aof radio-frequency signal wiring and bias power supply wiring. It should be noted that the following mainly describes differences from Embodiment 1, and the description of the same or similar content as Embodiment 1 will be omitted or simplified. The region other than intersection portion100ais, for example, a region in which first shield pattern121is not provided in a plan view. As shown inFIG.3, in first resin layer116that is a single resin layer, ground electric potential connection via pattern111and connection via131that is set to a ground electric potential are disposed between (i) radio-frequency signal connection via132connected to first radio-frequency signal wiring1that transmits the first radio-frequency signal to carrier amplifier semiconductor device11and (ii) bias power supply connection via133connected to peak-amplifier bias power supply wiring32that supplies a peak-amplifier bias power supply voltage. Connection via pattern111and connection via131are connected to ground electrode pattern123. Bias power supply connection via133is supplied with the peak-amplifier bias power supply voltage. By disposing connection via131, which is the ground electric potential, between radio-frequency signal connection via132and bias power supply connection via133that are provided in the same resin layer of multilayer submount substrate100, it is possible to prevent signal interference between the connection vias provided in the same resin layer. It should be noted that Embodiment 3 has described the example in which bias power supply connection via133is connected to peak-amplifier bias power supply wiring32, bias power supply connection via133may be connected to carrier-amplifier bias power supply wiring31. In addition, connection via131, which is the ground electric potential, may be located between radio-frequency signal connection vias or bias power supply voltage connection vias that are provided in the same resin layer. Moreover, when a plurality of bias power supply connection vias133are connected to peak-amplifier bias power supply wiring32or carrier-amplifier bias power supply wiring31, in a plan view, a plurality of ground electric potential connection vias131may be spaced apart from each other in an arrangement direction of the plurality of bias power supply connection vias133, within a distance that is three times as large as width W (seeFIG.1C) of peak-amplifier bias power supply wiring32or carrier-amplifier bias power supply wiring31along a row of the plurality of bias power supply connection vias133. Accordingly, since the plurality of connection vias131are disposed in the arrangement direction of the plurality of bias power supply connection vias133, it is possible to further prevent the signal interference between the connection vias provided in the same resin layer. Furthermore, in multilayer submount substrate100, types of the ground electric potential may include a radio-frequency-signal ground electric potential that is a reference electric potential of the first and second radio-frequency signals, and a bias-power-supply ground electric potential that is a reference electric potential of the carrier-amplifier bias power supply voltage and the peak-amplifier bias power supply voltage. An electric potential of a ground electric potential connection via may be the bias-power-supply ground electric potential. The radio-frequency-signal ground electric potential and the bias-power-supply ground electric potential each are connected to a ground (ground electric potential) of a different system. The radio-frequency-signal ground electric potential and the bias-power-supply ground electric potential may be connected to a common ground outside radio-frequency power amplifier device200. In other words, the radio-frequency-signal ground electric potential and the bias-power-supply ground electric potential may be each connected to a different ground in radio-frequency power amplifier device200. It should be noted that the radio-frequency-signal ground electric potential and the bias-power-supply ground electric potential may be connected to a common ground (e.g., ground electrode pattern123) in radio-frequency power amplifier device200. Here, another example of the shape of a connection via will be described with reference toFIG.4.FIG.4shows an example of a plan view of each of wiring layers in intersection portion100aof radio-frequency power amplifier device200according to Embodiment 3.FIG.4is a diagram illustrating another example of the shape of a ground electric potential connection via. As shown inFIG.4, the shape of ground electric potential connection via131may be an obround shape in a plan view of radio-frequency power amplifier device200. In a plan view, carrier-amplifier bias power supply wiring31is located between a pair of connection vias131in the obround shape. It can also be said that radio-frequency power amplifier device200includes, in third wiring layer105, one connection via131disposed on each of both sides of the width of carrier-amplifier bias power supply wiring31in an extension direction of carrier-amplifier bias power supply wiring31. Since no space is formed between the connection vias by causing the shape to be the obround shape, the interference prevention effect is further achieved. The longer axis of the obround shape is parallel to, for example, the extension direction of carrier-amplifier bias power supply wiring31. Embodiment 4 FIG.5shows an example of a plan view of radio-frequency power amplifier device300in which microcontroller unit semiconductor device17is mounted on multilayer submount substrate100according to Embodiment 4. Radio-frequency power amplifier device300according to Embodiment 4 differs from radio-frequency power amplifier device200according to Embodiment 1 in microcontroller unit semiconductor device17mounted therein. By mounting microcontroller unit semiconductor device17on multilayer submount substrate100, it is possible to control a carrier-amplifier bias power supply voltage and a peak-amplifier bias power supply voltage with higher accuracy even when an environment changes. For example, by storing a parameter for temperature change into microcontroller unit semiconductor device17in advance, it is possible to vary a bias voltage in response to the temperature change, based on the parameter. Microcontroller unit semiconductor device17is a semiconductor chip or a package product that controls each of semiconductor devices on multilayer submount substrate100. Microcontroller unit semiconductor device17controls the operation of bias power supply semiconductor device13in accordance with the temperature of radio-frequency power amplifier device300(e.g., the ambient temperature of radio-frequency power amplifier device300). Microcontroller unit semiconductor device17outputs, for example, a correction value corresponding to a temperature to bias power supply semiconductor device13. The correction value may be a value for correcting a bias power supply voltage outputted by bias power supply semiconductor device13. Microcontroller unit semiconductor device17causes bias power supply semiconductor device13to, for example, keep an idle current of a transistor (e.g., transistor150) constant by adjusting a bias voltage applied to the gate electrode of the transistor to reduce a variation in idle current due to temperature change. It should be noted that although a temperature is obtained by, for example, a sensor disposed on a set board on which radio-frequency power amplifier device300is mounted, the present disclosure is not limited to this example. Microcontroller unit semiconductor device17is connected to digital signal wiring35that inputs and outputs digital signals. There is a possibility that digital signal noise occurring when digital signals are propagated affects the first and second radio-frequency signals to degrade the properties of radio-frequency power amplifier device300, the digital signals being inputted and outputted between microcontroller unit semiconductor device17and an external device of radio-frequency power amplifier device300and between microcontroller unit semiconductor device17and bias power supply semiconductor device13. Accordingly, by disposing at least one of carrier-amplifier bias power supply wiring31, peak-amplifier bias power supply wiring32, analog power supply wiring36connected to bias power supply semiconductor device13, or a ground electric potential wire (not shown) between (i) digital signal wiring35that propagates digital signals and (ii) first radio-frequency signal wiring1and second radio-frequency signal wiring2that transmit the first and second radio-frequency signals of carrier amplifier semiconductor device11and peak amplifier semiconductor device12, the digital signal noise is absorbed, which makes it possible to reduce interference from the digital signal noise. The ground electric potential wire is a reference electric potential wire (ground wire) for bias power supply wiring, radio-frequency signal wiring, etc. For example, a plurality of ground electric potential wires are disposed. As a result, at least one of carrier-amplifier bias power supply wiring31, peak-amplifier bias power supply wiring32, analog power supply wiring36or the ground electric potential wire serves as a shield, which makes it possible to prevent the noise of digital signal wiring35from affecting the first and second radio-frequency signals. It should be noted that disposing an other wire between digital signal wiring35and first radio-frequency signal wiring1and second radio-frequency signal wiring2means disposing an other wire to cause a virtual line (straight line) connecting any point of digital signal wiring35and any other points of first radio-frequency signal wiring1and second radio-frequency signal wiring2to interest the other wire. It should be noted that disposing a plurality of ground electric potential wires between digital signal wiring35and first radio-frequency signal wiring1and second radio-frequency signal wiring2makes it possible to further prevent the interference. Moreover, in multilayer submount substrate100, types of the plurality of ground electric potential wires include a radio-frequency-signal ground electric potential wire that is a reference electric potential of the first radio-frequency signal and the second radio-frequency signal, and a digital-signal ground electric potential wire that is a reference potential of a digital signal. The plurality of ground electric potential wires may be mutually different types of ground electric potential wires. For example, the plurality of ground electric potential wires may include a radio-frequency-signal ground electric potential wire and a digital-signal ground electric potential wire, and the radio-frequency-signal ground electric potential wire and the digital-signal ground electric potential wire may be mutually different types (systems) of ground electric potential wires. This makes it possible to effectively prevent the noise of digital signal wiring35from affecting the first and second radio-frequency signals, compared to a case in which the radio-frequency-signal ground electric potential wire and the digital-signal ground electric potential wire are the same type of ground electric potential wires. Furthermore, the digital-signal ground electric potential wire may be disposed closer to the digital signal wiring than to the radio-frequency signal wiring, and the radio-frequency-signal ground electric potential wire may be disposed closer to the radio-frequency signal wiring than to the digital signal wiring. This makes it possible to effectively prevent the noise of digital signal wiring35from affecting the first and second radio-frequency signals. Moreover, in a plan view of multilayer submount substrate100, a region including digital signal wiring35may be distinguished from a region including the radio-frequency signal wiring by the digital-signal ground electric potential wire. Accordingly, since the digital-signal ground electric potential wire serves as a shield, it is possible to effectively prevent the noise of digital signal wiring35from affecting the first and second radio-frequency signals. It should be noted that the term “distinguished” means that digital signal wiring35is disposed only in one region distinguished by the digital-signal ground electric potential wire in a plan view, and the radio-frequency signal wiring is disposed only in an other region distinguished by the digital-signal ground electric potential wire. It should be noted that in the case shown inFIG.5, each of carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32intersects second radio-frequency signal wiring2in a plan view. In this case, first shield pattern121is provided over carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32in the plan view. In a cross-sectional view, carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32may be surrounded collectively or individually by first shield pattern121, the plurality of connection vias131, and ground electrode pattern123. Embodiment 5 FIG.6shows an example of a plan view of radio-frequency power amplifier device400according to Embodiment 5. As shown inFIG.6, driver amplifier semiconductor device14that amplifies a third radio-frequency signal and divider171that divides the third radio-frequency signal amplified by driver amplifier semiconductor device14into a first radio-frequency signal and a second radio-frequency signal are mounted on multilayer submount substrate100. The other constituent elements are the same as those of radio-frequency power amplifier device200according to Embodiment 1, and thus the description thereof will be omitted. Driver amplifier semiconductor device14is a semiconductor chip that includes a driver amplifier that drives a carrier amplifier and a peak amplifier, and is a pre-amplifier for carrier amplifier semiconductor device11and peak amplifier semiconductor device12. Driver amplifier semiconductor device14is disposed closer to a radio-frequency-signal input side than carrier amplifier semiconductor device11and peak amplifier semiconductor device12. Driver amplifier semiconductor device14amplifies the third radio-frequency signal transmitted via third radio-frequency signal wiring3. Bias power supply semiconductor device13is configured to output a bias power supply voltage for driver to driver amplifier semiconductor device14in addition to a carrier-amplifier bias power supply voltage and a peak-amplifier bias power supply voltage, and to control these bias power supply voltages independently of each other. The bias power supply voltage for driver is an example of a bias power supply voltage. Divider171is implemented by, for example, a Wilkinson coupler, but the present disclosure is not limited to this example. Mounting driver amplifier semiconductor device14in radio-frequency power amplifier device400eliminates the need to mount a driver amplifier on a set board, which makes it possible to contribute to the downsizing of the set board. Embodiment 6 FIG.7shows an example of a plan view of radio-frequency power amplifier device500according to Embodiment 6. A driver amplifier semiconductor device is first monolithic semiconductor device18that includes carrier driver amplifier semiconductor device15that is a pre-amplifier for carrier amplifier semiconductor device11, and peak driver amplifier semiconductor device16that is a pre-amplifier for peak amplifier semiconductor device12. Carrier amplifier semiconductor device11and peak amplifier semiconductor device12are second monolithic semiconductor device19and third monolithic semiconductor device20, respectively. It should be noted that a monolithic semiconductor device means a single-chip semiconductor device. Carrier driver amplifier semiconductor device15is a semiconductor chip that includes a driver amplifier that drives a carrier amplifier. Carrier driver amplifier semiconductor device15is supplied with a power supply voltage via carrier driver amplifier power supply wiring41. Peak driver amplifier semiconductor device16is a semiconductor chip that includes a driver amplifier that drives a peak amplifier. Peak driver amplifier semiconductor device16is supplied with a power supply voltage via peak driver amplifier power supply wiring42. At least one of carrier driver amplifier semiconductor device15or peak driver amplifier semiconductor device16may contain a capacitor for matching. First radio-frequency signal wiring1connected to carrier driver amplifier semiconductor device15or second radio-frequency signal wiring2connected to peak driver amplifier semiconductor device16is provided in first wiring layer103of multilayer submount substrate100. Carrier-driver-amplifier bias power supply wiring33supplied with a carrier-driver-amplifier bias power supply voltage outputted from bias power supply semiconductor device13or peak-driver-amplifier bias power supply wiring34supplied with a peak-driver-amplifier bias power supply voltage outputted from bias power supply semiconductor device13is provided in third wiring layer105. At least one of first radio-frequency signal wiring1or second radio-frequency signal wiring2intersects at least one of carrier-driver-amplifier bias power supply wiring33or peak-driver-amplifier bias power supply wiring34in a plan view. For example, the intersection portions are orthogonal in the plan view. In Embodiment 6, first radio-frequency signal wiring1and second radio-frequency signal wiring2are orthogonal to carrier-driver-amplifier bias power supply wiring33at intersection portions100band100c, respectively. Second shield pattern122set to a ground electric potential is disposed in second wiring layer104of intersection portions100band100c. A plurality of ground electric potential connection vias131are spaced apart from each other in an extension direction (the Y-axis direction in the example shown inFIG.7) of carrier-driver-amplifier bias power supply wiring33or peak-driver-amplifier bias power supply wiring34, on both sides along carrier-driver-amplifier bias power supply wiring33or peak-driver-amplifier bias power supply wiring34within a distance that is three times as large as the width of carrier-driver-amplifier bias power supply wiring33or peak-driver-amplifier bias power supply wiring34. The plurality of connection vias131are connected to second shield pattern122of second wiring layer104and ground electrode pattern123of fourth wiring layer106. Second shield pattern122is provided, for example, in a rectangular shape to cover intersection portions100band100cin a plan view. In addition, second shield pattern122is provided over, for example, first radio-frequency signal wiring1and second radio-frequency signal wiring2in the plan view. Embodiment 7 FIG.8shows an example of a plan view of radio-frequency power amplifier device600according to Embodiment 7. Radio-frequency power amplifier device600includes microcontroller unit semiconductor device17on first principal surface101of multilayer submount substrate100. An arrangement space between microcontroller unit semiconductor device17and carrier amplifier semiconductor device11is wider than an arrangement space between microcontroller unit semiconductor device17and peak amplifier semiconductor device12. It can also be said that carrier amplifier semiconductor device11is located at a greater distance from microcontroller unit semiconductor device17than peak amplifier semiconductor device12is in a plan view. Carrier amplifier semiconductor device11and microcontroller unit semiconductor device17are disposed, for example, on a diagonal line of multilayer submount substrate100in the plan view. Microcontroller unit semiconductor device17and peak amplifier semiconductor device12are disposed, for example, close to a side of multilayer submount substrate100on the same side (in the example shown inFIG.8, a side of multilayer submount substrate100on a Y-axis minus side out of a Y-axis plus side and the Y-axis minus side) in the plan view. Peak amplifier semiconductor device12operates only when a power range of radio-frequency power amplifier device600is high, whereas carrier amplifier semiconductor device11operates in the entirety of the output range. For this reason, further increasing the space between carrier amplifier semiconductor device11and microcontroller unit semiconductor device17makes it possible to reduce the effect of digital signal noise. Embodiment 8 FIG.9Ashows an example of a plan view of radio-frequency power amplifier device700according to Embodiment 8 when a bias circuit is disposed in each of amplifiers of radio-frequency power amplifier device700. As shown inFIG.9A, carrier amplifier semiconductor device11and peak amplifier semiconductor device12include carrier amplifier bias circuit22and peak amplifier bias circuit23, respectively, each of which supplies a bias voltage to the gate electrode of a transistor included in an amplifier. Carrier amplifier semiconductor device11contains carrier amplifier bias circuit22, and peak amplifier semiconductor device12contains peak amplifier bias circuit23. At least one of carrier driver amplifier semiconductor device11or peak driver amplifier semiconductor device12may contain a capacitor for matching. Carrier amplifier bias circuit22is supplied with a carrier-amplifier bias power supply voltage from bias power supply semiconductor device13, and outputs a bias voltage to the gate electrode of a carrier amplifier. Peak amplifier bias circuit23is supplied with a peak-amplifier bias power supply voltage from bias power supply semiconductor device13, and outputs a bias voltage to the gate electrode of a peak amplifier. Carrier amplifier bias circuit22is disposed close to an outer perimeter side of carrier amplifier semiconductor device11that faces and is close to (e.g., faces and is closest to) an outer perimeter side of peak amplifier semiconductor device12when carrier amplifier semiconductor device11and peak amplifier semiconductor device12are disposed on multilayer submount substrate100. Peak amplifier bias circuit23is disposed close to an outer perimeter of peak amplifier semiconductor device12that faces and is close to an outer perimeter side of carrier amplifier semiconductor device11when carrier amplifier semiconductor device11and peak amplifier semiconductor device12are disposed on multilayer submount substrate100. In the example shown inFIG.9A, carrier amplifier bias circuit22is disposed on a peak amplifier semiconductor device12side (close to a side on the Y-axis minus side) of second monolithic semiconductor device19in a plan view, and peak amplifier bias circuit23is disposed on a carrier amplifier semiconductor device11side (close to a side on the Y-axis plus side) of third monolithic semiconductor device20in the plan view. For example, causing carrier amplifier bias circuit22and peak amplifier bias circuit23to face and be closest to each other makes it easy to lay out carrier-amplifier bias power supply wiring31and peak-amplifier bias power supply wiring32, and further makes it easy to lay out first shield pattern121and ground electric potential connection vias131for use in the prevention of interference. Moreover, carrier driver amplifier semiconductor device15and peak driver amplifier semiconductor device16include carrier driver amplifier bias circuit24and peak driver amplifier bias circuit25, respectively. Carrier driver amplifier semiconductor device15contains carrier driver amplifier bias circuit24, and peak driver amplifier semiconductor device16contains peak driver amplifier bias circuit25. At least one of carrier driver amplifier semiconductor device15or peak driver amplifier semiconductor device16may contain a capacitor for matching. Carrier driver amplifier bias circuit24is supplied with a carrier-amplifier bias power supply voltage from bias power supply semiconductor device13, and outputs a bias voltage to the gate electrode of a carrier driver amplifier. Peak driver amplifier bias circuit25is supplied with a peak-amplifier bias power supply voltage from bias power supply semiconductor device13, and outputs a bias voltage to the gate electrode of a peak driver amplifier. Carrier driver amplifier bias circuit24is disposed close to an outer perimeter side of carrier driver amplifier semiconductor device15that is located remotely from (e.g., located most remotely from) an outer perimeter side of peak driver amplifier semiconductor device16when carrier driver amplifier semiconductor device15and peak driver amplifier semiconductor device16are disposed on multilayer submount substrate100. Peak driver amplifier bias circuit25is disposed close to an outer perimeter side of peak driver amplifier semiconductor device16that is located remotely from an outer perimeter side of carrier driver amplifier semiconductor device15when carrier driver amplifier semiconductor device15and peak driver amplifier semiconductor device16are disposed on multilayer submount substrate100. In the example shown inFIG.9A, carrier driver amplifier bias circuit24is disposed on an opposite side (the Y-axis plus side) of peak driver amplifier semiconductor device16of first monolithic semiconductor device18in a plan view, and peak driver amplifier bias circuit25is disposed on an opposite side (the Y-axis minus side) of carrier driver amplifier semiconductor device15of first monolithic semiconductor device18in the plan view. Since the driver amplifiers are reduced in transistor size, causing carrier driver amplifier bias circuit24and peak driver amplifier bias circuit25to be located most remotely from each other makes it easy to lay out the matching circuits of carrier driver amplifier semiconductor device15and peak driver amplifier semiconductor device16. Here, a circuit configuration of bias power supply semiconductor device13and a bias circuit will be described with reference toFIG.9B.FIG.9Bshows an example of a circuit diagram illustrating bias power supply semiconductor device13and a bias circuit according to Embodiment 8. Carrier amplifier bias circuit22, peak amplifier bias circuit23, carrier driver amplifier bias circuit24, and peak driver amplifier bias circuit25may have the same circuit configuration. Carrier amplifier bias circuit22will be described with reference toFIG.9B. Carrier amplifier semiconductor device11is configured to include second transistor Tr2. Bias power supply semiconductor device13is configured to be capable of controlling carrier amplifier bias circuit22, peak amplifier bias circuit23, carrier driver amplifier bias circuit24, and peak driver amplifier bias circuit25individually. As shown inFIG.9B, bias power supply semiconductor device13and second monolithic semiconductor device19are provided on multilayer submount substrate100. Bias power supply semiconductor device13is provided in a region external to second monolithic semiconductor device19on multilayer submount substrate100. Bias power supply semiconductor device13according to Embodiment 8 is a control device (enable control circuit) that controls the active state of a bias voltage applied to the gate of first transistor Tr1. Bias power supply semiconductor device13is configured to include, for example, switch element13athat selectively outputs a voltage lower than a threshold voltage of first transistor Tr1and a voltage higher than the threshold voltage via terminal t3in response to a change in voltage Ven (High voltage/Low voltage) applied to terminal t1. Switch element13ais configured to include a plurality of transistors. Moreover, terminals t1and t2that are input terminals of bias power supply semiconductor device13and terminal t3that is an output terminal of bias power supply semiconductor device13are provided on multilayer submount substrate100. Terminal t1is supplied with voltage Ven via analog power supply wiring36, and terminal t2is supplied with voltage Vgg via analog power supply wiring36. Voltage Ven is an enable voltage. Voltages Ven and Vgg are power to carrier amplifier bias circuit22. Terminal t3is connected to terminal t4of second monolithic semiconductor device19via carrier-amplifier bias power supply wiring31. Second monolithic semiconductor device19includes: first transistor Tr1for power amplification provided on multilayer submount substrate100; and carrier amplifier bias circuit22that includes second transistor Tr2provided on multilayer submount substrate100and applies a bias voltage to the gate of first transistor Tr1. First transistor Tr1and second transistor Tr2each are a high-electron-mobility transistor (HEMT) that includes a nitride semiconductor such as gallium nitride (GaN), but the present disclosure is not limited to this example. Carrier amplifier bias circuit22includes resistor R1, second transistor Tr2, and resistor R2that are connected in series. A connection point between one end of resistor R1and the drain of second transistor Tr2is equivalent to a bias voltage output node of carrier amplifier bias circuit22, and is connected to the gate of first transistor Tr1. The other end of resistor R1is grounded. Second transistor Tr2is disposed outside a transmission path for radio-frequency signals inputted to first transistor Tr1. It should be noted that the transmission path for radio-frequency signals is a path on which most of the radio-frequency signals inputted to terminal t6via first radio-frequency signal wiring1are transmitted. One end of resistor R2is connected to the gate of second transistor Tr2, and the other end of resistor R2is connected to the source of second transistor Tr2. Furthermore, second monolithic semiconductor device19includes: terminal t4connected to the one end of resistor R2; terminal t5connected to carrier amplifier power supply wiring43; terminal t6connected to the gate of first transistor Tr1; and terminal t7connected to the drain of first transistor Tr1. It should be noted that the source of first transistor Tr1is grounded. When Low voltage is inputted as voltage Ven to terminal t1of bias power supply semiconductor device13, a voltage lower than a threshold voltage of second transistor Tr2is outputted from terminal t3and inputted to the one end of resistor R2. As a result, a gate voltage of second transistor Tr2becomes lower than the threshold voltage of second transistor Tr2, and second transistor Tr2is put into an off state in which no drain current flows. In contrast, when High voltage is inputted as voltage Ven to terminal t1of bias power supply semiconductor device13, a voltage higher than a threshold voltage of second transistor Tr2is outputted from bias power supply semiconductor device13and applied to the one end of resistor R2. The voltage applied to the one end of resistor R2causes a gate voltage of second transistor Tr2to be higher than the threshold voltage of second transistor Tr2, and second transistor Tr2is put into an on state in which a drain current flows. As stated above, in Embodiment 8, first transistor Tr1as an amplifier and second transistor Tr2that generates a bias voltage are included in the same chip. Second transistor Tr2has the same device property as first transistor Tr1. Accordingly, since it is possible to cancel a variation in threshold voltages of first transistor Tr1and second transistor Tr2, it is possible to control the operation of first transistor Tr1with high accuracy. It should be noted that although carrier amplifier bias circuit22shown inFIG.9Bis an example of a circuit that supplies a bias voltage to the gate of first transistor Tr1, a circuit configuration is not limited to this example. For example, the other end of resistor R1need not be grounded, and a voltage generated by bias power supply semiconductor device13may be applied to the other end of resistor R1. It should be noted that bias power supply semiconductor device13shown inFIG.1Aetc. may have both the configurations of bias power supply semiconductor device13and carrier amplifier bias circuit22shown inFIG.9B. Next, a pattern of driver amplifier power supply wiring will be described with reference toFIG.10AandFIG.1013.FIG.10Ais a perspective view of an example of a pattern of driver amplifier power supply wiring according to Embodiment 8.FIG.1013shows an example of a cross sectional structural view of the pattern of the driver amplifier power supply wiring according to Embodiment 8, taken along section line XB-XB inFIG.10A. As shown inFIG.10AandFIG.10B, peak driver amplifier power supply wiring42that supplies power to peak driver amplifier semiconductor device16is disposed on second wiring layer104that is a lower layer, on which first monolithic semiconductor device18, of die pad124provided in first wiring layer103of multilayer submount substrate100is disposed. In addition, peak driver amplifier power supply wiring42is disposed to stay within an outer perimeter boundary of die pad124in a direction (the X-axis direction in the example shown inFIG.10A) orthogonal to an extension direction (the Y-axis direction in the example shown inFIG.10A) of carrier driver amplifier power supply wiring41or peak driver amplifier power supply wiring42in a plan view of radio-frequency power amplifier device700. In the examples shown inFIG.10AandFIG.10B, die pad124encompasses peak driver amplifier power supply wiring42in a plan view. There is a possibility that the protrusion of peak driver amplifier power supply wiring42beyond the outer perimeter boundary causes interference with the first or second radio-frequency signal, and the properties degrade. Disposing peak driver amplifier power supply wiring42in the wiring layer that is the lower layer of die pad124enables die pad124to serve as a shield pattern and reduce interference between peak driver amplifier power supply wiring42and the first or second radio-frequency signal. Although peak driver amplifier power supply wiring42is disposed in second wiring layer104in the above configuration, peak driver amplifier power supply wiring42may be provided in a further lower wiring layer (e.g., third wiring layer105). It should be noted that thermal via134is a via for thermally connecting ground electrode pattern123and die pad124. Embodiment 9 FIG.11shows an example of a plan view of radio-frequency power amplifier device500aaccording to Embodiment 9. As shown inFIG.11, a driver amplifier semiconductor device includes: carrier driver amplifier semiconductor device15that is a pre-amplifier for carrier amplifier semiconductor device11and is first monolithic semiconductor device18a; and peak driver amplifier semiconductor device16that is a pre-amplifier for peak amplifier semiconductor device12and is second monolithic semiconductor device19a. Additionally, carrier amplifier semiconductor device11and peak amplifier semiconductor device12are included in third monolithic semiconductor device20a. The above configuration makes it easy to lay out a parallel-plate coupler (parallel-plate type coupler) that divides a radio-frequency signal into the first radio-frequency signal to be inputted to carrier driver amplifier semiconductor device15and the second radio-frequency signal to be inputted to peak driver amplifier semiconductor device16. It should be noted that in the example shown inFIG.11, the parallel-plate coupler is disposed outside radio-frequency power amplifier device500a. Embodiment 10 Although Embodiment 9 has described the example in which the parallel-plate coupler is disposed outside radio-frequency power amplifier device500a, a parallel-plate coupler may be mounted on a radio-frequency power amplifier device. In Embodiment 10, a radio-frequency power amplifier device on which a parallel-plate coupler is mounted will be described with reference toFIG.12AandFIG.12B. FIG.12Ashows an example of a plan view of radio-frequency power amplifier device800according to Embodiment 10.FIG.12Bshows an example of a cross sectional structural view of a parallel-plate coupler according to Embodiment 10, taken along section line XIIB-XIIB inFIG.12A. As shown inFIG.12A, radio-frequency power amplifier device800includes divider172that is a pre-amplifier for carrier driver amplifier semiconductor device15and peak driver amplifier semiconductor device16. Divider172divides a third radio-frequency signal inputted from third radio-frequency signal wiring3into a first radio-frequency signal to be inputted to carrier driver amplifier semiconductor device15and a second radio-frequency signal to be inputted to peak driver amplifier semiconductor device16. In Embodiment 10, divider172includes a parallel-plate coupler. As shown inFIG.12B, radio-frequency power amplifier device800includes the parallel-plate coupler provided between main line4provided in first wiring layer103of multilayer submount substrate100and sub-line5provided in second wiring layer104that faces first wiring layer103. Space H2between sub-line5included in the parallel-plate coupler and fourth wiring layer106that is set to a ground electric potential and faces and is closest to sub-line5may be at least three times as large as space H1between main line4and sub-line5included in the parallel-plate coupler. Such a configuration makes it easy to provide a parallel-plate 3 dB coupler. It should be noted that by at least one of adjusting the thickness of each resin layer or adjusting the number of layers of multilayer submount substrate100, it is possible to adjust space H1and space H2. At least one of the thickness of each resin layer or the number of layers of multilayer submount substrate100is adjusted to cause space H2to be at least three times as large as space H1. It should be noted that although divider172includes the parallel-plate coupler inFIG.12B, it is entirely acceptable to cause radio-frequency power amplifier device800to contain a Wilkinson coupler instead of the parallel-plate coupler. Moreover, in Embodiment 10, carrier driver amplifier power supply wiring41that supplies power to carrier driver amplifier semiconductor device15may be disposed in a wiring layer that is a lower layer, on which second monolithic semiconductor device19ais disposed, of die pad124(seeFIG.10AandFIG.1013) provided in first wiring layer103of multilayer submount substrate100. Alternatively, peak driver amplifier power supply wiring42that supplies power to peak driver amplifier semiconductor device16may be disposed in a wiring layer that is a lower layer, on which first monolithic semiconductor device18ais disposed, of die pad124provided in first wiring layer103of multilayer submount substrate100. In a plan view of radio-frequency power amplifier device800, carrier driver amplifier power supply wiring41or peak driver amplifier power supply wiring42may be disposed to stay within the outer perimeter boundary of die pad124in a direction orthogonal to the extension direction of carrier driver amplifier power supply wiring41or peak driver amplifier power supply wiring42. As stated above, even when carrier amplifier semiconductor device11and peak amplifier semiconductor device12are included in a single chip, die pad124may be used as a shield pattern of at least one of carrier driver amplifier power supply wiring41or peak driver amplifier power supply wiring42. Although one or more radio-frequency power amplifier devices according to one or more aspects of the present disclosure have been described above based on the respective embodiments, the present disclosure is not limited to these embodiments. Forms obtained by making various modifications conceived by a person skilled in the art to the embodiments or forms obtained by combining the constituent elements in the different embodiments may be included in the scope of the one or more aspects of the present disclosure, as long as they do not depart from the essence of the present disclosure. Moreover, with regard to the one or more radio-frequency power amplifier devices according to the one or more aspects of the present disclosure, carrier amplifier semiconductor device11and peak amplifier semiconductor device12may each include a transistor comprising a nitride such as GaN. A Si substrate, a SiC substrate, etc. may be used as a semiconductor substrate. Furthermore, carrier amplifier semiconductor device11and peak amplifier semiconductor device12may each include a LDMOS transistor including a Si substrate. Moreover, carrier amplifier semiconductor device11and carrier driver amplifier semiconductor device15may each include a transistor comprising a nitride such as GaN. A Si substrate, a SiC substrate, etc. may be used as a semiconductor substrate. Furthermore, carrier amplifier semiconductor device11and carrier driver amplifier semiconductor device15may each include a LDMOS transistor including a Si substrate. Moreover, peak amplifier semiconductor device12and peak driver amplifier semiconductor device16may each include a transistor comprising a nitride such as GaN. A Si substrate, a SiC substrate, etc. may be used as a semiconductor substrate. Furthermore, carrier amplifier semiconductor device12and peak driver amplifier semiconductor device16may each include a LDMOS transistor including a Si substrate. Moreover, carrier amplifier semiconductor device11and peak amplifier semiconductor device12may each include, for example, a transistor comprising a nitride such as GaN and a LDMOS transistor including a Si substrate. A substrate used for a semiconductor substrate of carrier amplifier semiconductor device11may have a superior (higher) thermal conductivity than a substrate used for a semiconductor substrate of peak amplifier semiconductor device12does. As an example, a SiC substrate may be used for the semiconductor substrate of carrier amplifier semiconductor device11, and a Si substrate may be used for the semiconductor substrate of peak amplifier semiconductor device12. As another example, a transistor comprising a nitride provided on a SiC substrate may be used for carrier amplifier semiconductor device11, and a transistor comprising a nitride provided on a Si substrate may be used for peak amplifier semiconductor device12. Such a configuration makes it possible to decrease a channel temperature of carrier amplifier semiconductor device11. Additionally, using a SiC substrate more expensive than a Si substrate only for carrier amplifier semiconductor device11that generates a lot of heat makes it possible to reduce costs. Furthermore, carrier amplifier semiconductor device11and carrier driver amplifier semiconductor device15may each include, for example, a transistor comprising a nitride such as GaN and a LDMOS transistor including a Si substrate. A substrate used for a semiconductor substrate of carrier amplifier semiconductor device11may have a superior (higher) thermal conductivity than a substrate used for a semiconductor substrate of carrier driver amplifier semiconductor device15does. As an example, a SiC substrate may be used for the semiconductor substrate of carrier amplifier semiconductor device11, and a Si substrate may be used for the semiconductor substrate of carrier driver amplifier semiconductor device15. As another example, a transistor comprising a nitride provided on a SiC substrate may be used for carrier amplifier semiconductor device11, and a transistor comprising a nitride provided on a Si substrate may be used for carrier driver amplifier semiconductor device15. Such a configuration makes it possible to decrease a channel temperature of carrier amplifier semiconductor device11. Additionally, using a SiC substrate more expensive than a Si substrate only for carrier amplifier semiconductor device11that generates a lot of heat makes it possible to reduce costs. Moreover, a transistor comprising a nitride such as GaN on a Si substrate may be used for carrier amplifier semiconductor device11, and a transistor including a LDMOS on a Si substrate may be used for peak amplifier semiconductor device12. By causing the semiconductor substrates to be identical Si substrates, it is possible to form carrier amplifier semiconductor device11and peak amplifier semiconductor device12into a single chip. Furthermore, a transistor comprising a nitride such as GaN on a Si substrate may be used for carrier amplifier semiconductor device11, and a transistor including a LDMOS on a Si substrate may be used for carrier driver amplifier semiconductor device15. By causing the semiconductor substrates to be identical Si substrates, it is possible to form carrier amplifier semiconductor device11and carrier driver amplifier semiconductor device15into a single chip. INDUSTRIAL APPLICABILITY The radio-frequency power amplifier device according to the present disclosure is useful for a radio-frequency power amplifier device on which a Doherty amplifier and a bias power supply semiconductor device that supplies a power supply voltage to the Doherty amplifier are mounted. REFERENCE SIGNS LIST 1first radio-frequency signal wiring2second radio-frequency signal wiring3third radio-frequency signal wiring4main line5sub-line11carrier amplifier semiconductor device12peak amplifier semiconductor device13bias power supply semiconductor device13aswitch element14driver amplifier semiconductor device15carrier driver amplifier semiconductor device16peak driver amplifier semiconductor device17microcontroller unit semiconductor device18,18afirst monolithic semiconductor device19,19asecond monolithic semiconductor device20athird monolithic semiconductor device21first gate bias circuit22carrier amplifier bias circuit23peak amplifier bias circuit24carrier driver amplifier bias circuit25peak driver amplifier bias circuit31carrier-amplifier bias power supply wiring32peak-amplifier bias power supply wiring33carrier-driver-amplifier bias power supply wiring34peak-driver-amplifier bias power supply wiring35digital signal wiring36analog power supply wiring41carrier driver amplifier power supply wiring42peak driver amplifier power supply wiring43carrier amplifier power supply wiring44peak amplifier power supply wiring100multilayer submount substrate100a,100b,100cintersection portion101first principal surface102second principal surface103first wiring layer104second wiring layer105third wiring layer106fourth wiring layer107first wiring pattern108second wiring pattern109third wiring pattern110fourth wiring pattern111connection via pattern116first resin layer117second resin layer118third resin layer121first shield pattern122second shield pattern123ground electrode pattern124die pad131connection via132radio-frequency signal connection via133bias power supply connection via134thermal via141first connecting wire142second connecting wire143third connecting wire144fourth connecting wire145fifth connecting wire150transistor151gate electrode152resistor153drain electrode154source electrode161input terminal162output terminal171,172divider200,300,400,500,500a,600,700,800radio-frequency power amplifierH1, H2, P spaceR1, R2resistort1, t2, t3, t4, t5, t6, t7terminalTr1first transistorTr2second transistorW width | 72,823 |
11942912 | DETAILED DESCRIPTION This disclosure is directed to, in part, amplifiers that include impedance circuits that are configured to adapt to various contexts. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and an impedance circuit coupled to the gain circuit, such as coupled to an input node for the gain circuit. The impedance circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The impedance circuit can operate based on a current gain mode to change an impedance for the variable-gain amplifier. For example, the switching-capacitive arm can be controlled to change an input inductance for the different gain modes of the variable-gain amplifier. The switching-capacitive arm can include one or more capacitors and/or one or more switches configured to enable or disable the one or more capacitors. In embodiments, the techniques and architectures discussed herein provide a tunable circuit that is configured to adapt an input impedance for a particular context, such as a gain mode, operating frequency, wireless system, or other operation mode. For example, an amplifier can include a switching-capacitive arm that is coupled to an input side of the amplifier and that is tunable to provide a desired impedance. The switching-capacitive arm can be adapted to match an output impedance and/or provide a desired return loss (e.g., an S11 parameter) for various modes of operation of the amplifier. As such, the techniques and architectures discussed herein can improve return loss, in comparison to other solutions that include poor return loss in at least one mode of operation. Further, in some embodiments, by implementing one or more capacitors in a switching-capacitive arm, which occupy less area than one or more inductors, the techniques and architectures discussed herein can conserve area on a device (e.g., a front-end module, semiconductor die, or other device), in comparison to implementing many inductors in various configurations. Although many embodiments are discussed herein in the context of variable-gain amplifiers, the techniques and architectures can be implemented in a wide variety of contexts, such as any type of amplifier or circuit. FIG.1illustrates an example radio-frequency device100having various features relevant to certain aspects of the present disclosure. The radio-frequency device100includes an RF module110, a transceiver130, a controller120, and an antenna140. The transceiver130can be configured to convert between analog signals and digital signals. The transceiver130can include a digital-to-analog converter, an analog-to-digital converter, a local oscillator for modulating or demodulating a baseband signal to or from a carrier frequency, a baseband processor that converts between digital samples and data bits (e.g., voice or other types of data), or other components. The RF module110can perform processing on an analog signal received from on an antenna140or received from the transceiver130. The RF module110can include filters, power amplifiers, low noise amplifiers, band select switches, attenuators, matching circuits, and/or other components. In some embodiments, the RF module110can be referred to as a front-end module (FEM), which can be physically close to the antenna140(e.g., to reduce attenuation to cable loss). The controller120can communicate with the transceiver130and/or the RF module110to facilitate various functionality discussed herein. The RF module110can include an amplifier150configured to amplify signals received and/or sent via the antenna140. The amplifier150can include a gain circuit160configured to amplify a signal received at the amplifier150and an impedance circuit170that is configured to change an impedance (e.g., input inductance) based on a gain mode of the amplifier150and/or another parameter. In examples, the amplifier150can include a variable-gain amplifier configured to provide a plurality of gain modes. To illustrate, the amplifier150can be configured to provide a first amplification gain for a first gain mode, a second amplification gain for a second mode, a third amplification gain for a third mode, and so on. The controller120can control a gain mode of the amplifier150, an impedance selected for the impedance circuit170, and/or an impedance selected for a degeneration circuit (discussed in further detail below). For example, the controller120can provide a control signal to the amplifier150to control an amount of gain provided by the amplifier150, control an amount of impedance of the impedance circuit170, and/or control an amount of impedance of a degeneration circuit. In some embodiments, the impedance circuit170can be controlled to provide noise matching (e.g., ideal noise matching), gain matching, or other types of impedance matching at any frequency(ies) of interest. The impedance circuit170can allow the amplifier150to be coupled to a desired or target input inductance for particular gain modes and/or signal amplitudes. For example, the amplifier150can implement the impedance circuit170with a first configuration to provide an impedance-matched circuit for a first gain mode and implement the impedance circuit170with a second configuration to provide an impedance-matched circuit for a second gain mode. This can provide a desired return loss (e.g., a relatively good S11 parameter) for various modes of operation of the amplifier150. As such, the amplifier150can achieve targeted or improved performance (in comparison to other amplifiers) by using the impedance circuit170that is configurable to provide tailored impedance for different gain modes. The controller120can be configured to generate and/or send control signals to components of the radio-frequency device100. In examples, the controller120can send a control signal to the amplifier150to control a gain mode of the amplifier150. For example, the controller120can provide a control signal to the amplifier150indicative of a desired or targeted gain. Each gain mode can be associated with a different amount of amplification. Further, in examples, the controller120can send a control signal to the amplifier150to configure an impedance of the amplifier150(e.g., to set a configuration of the impedance circuit170). For example, the controller120can provide a control signal to the amplifier150indicative of a desired or targeted input inductance. In some embodiments, the controller120generates a control signal based on a quality of service (QoS) metric associated with a signal. A QoS metric can include a metric associated with a signal(s) received or sent via the antenna140, such as a signal strength, a bit error rate, a data throughput, a transmission delay, a signal-to-to-noise ratio, or any other metric. In some embodiments, the controller120can be configured to receive a signal from a component of the radio-frequency device100and determine a control signal to provide to another component based on the received signal. For example, the controller120can generate a control signal based on a signal received from a communications controller, which can be based on a QoS metric of a received signal. In some embodiments, the controller120provides control signals based on specifications provided by the mobile industry processer interface alliance (MIPI® Alliance). In some embodiments, the amplifier150can include a step-variable gain amplifier configured to amplify received signals with a gain of one of a plurality of configured amounts indicated by a control signal. Further, in some embodiments, the amplifier150can include a continuously-variable gain amplifier configured to amplify received signals with a gain proportional to or dictated by a control signal. Moreover, in some embodiments, the amplifier150can include a step-variable current amplifier configured to amplify received signals by drawing a current of one of plurality of configured amounts indicated by a control signal. Furthermore, in some embodiments, the amplifier150can include a continuously-variable current amplifier configured to amplify received signals by drawing a current proportional to a control signal. In some embodiments, the antenna140includes a primary antenna and a diversity antenna. The primary antenna and the diversity antenna can be physically spaced apart such that a signal at the primary antenna and the diversity antenna are received with different characteristics. For example, the primary antenna and the diversity antenna can receive the signal with different attenuation, noise, frequency response, and/or phase shift. The transceiver130can use both of the signals with different characteristics to determine data bits corresponding to the signal. In some implementations, the transceiver130selects between the primary antenna and the diversity antenna based on the characteristics, such as selecting the antenna with the highest signal-to-noise ratio. In some embodiments, the transceiver130combines signals from the primary antenna and the diversity antenna to increase the signal-to-noise ratio of the combined signal. In some embodiments, the transceiver130processes the signals to perform multiple-input/multiple-output (MIMO) communication. As noted above, in some embodiments, the diversity antenna can be physically spaced apart from the primary antenna. Here, the diversity antenna can be coupled to the transceiver130by a transmission line, such as a cable, a printed circuit board (PCB) trace, or another component. In examples, the transmission line is lossy and/or attenuates the signal received at the diversity antenna before it reaches the transceiver130. In some embodiments, the antenna140is configured to receive signals within multiple cellular frequency bands and/or wireless local area network (WLAN) frequency bands. In such embodiments, the radio-frequency device100can include a multiplexer, switching network, and/or filter assembly coupled to a diversity antenna that is configured to separate the diversity signal into different frequency ranges. For example, the multiplexer can be configured to include a low pass filter that passes a frequency range that includes low band cellular frequencies, a bandpass filter that passes a frequency range that includes low band WLAN signals and mid-band and high-band cellular signals, and a high pass filter that passes a frequency range that includes high-band WLAN signals. As another example, the multiplexer can have a variety of different configurations such as a diplexer that provides the functionality of a high pass filter and a low pass filter. The amplifier150can be implemented within a low noise amplifier (LNA), a power amplifier (PA), and/or any other component. For example, the RF module110can include an LNA configured to receive a signal from the antenna140and amplify the signal using the amplifier150. In some embodiments, multiple variable-gain amplifiers are implemented on the radio-frequency device100. For example, a first module can be implemented with a first variable-gain amplifier to amplify a signal from a diversity antenna and a second module can be implemented with a second variable-gain amplifier to amplify a signal from a primary antenna. In examples, a module associated with a diversity antenna can be referred to as a diversity receiver front-end module and/or can be located physically close to the diversity antenna. FIG.2illustrates an example amplifier250that includes a gain circuit260coupled to an impedance circuit270in accordance with one or more embodiments. The gain circuit160can be configured to receive an input signal and to generate an amplified output signal. For example, the amplifier250can receive an input signal via the input node, amplify the signal using the gain circuit260, and provide an amplified output signal via the output node. The impedance circuit270can be configured to provide a plurality of different impedances for the gain circuit260. In some embodiments, the amplifier250is implemented as a variable-gain amplifier and a selected impedance is based on a gain mode of the amplifier250. For example, the impedance circuit270can be configured to provide a first impedance for a first gain mode, a second impedance for a second gain mode, a third impedance for a third gain mode, and so on. FIG.3illustrates an example amplifier350that includes a gain circuit and an impedance circuit370in accordance with one or more embodiments. Here, the amplifier350can receive an input signal at an input node and provide an output signal at an output node. The amplifier350includes a transistor362that can amplify the input signal, such as based on a gain mode that is selected. The transistor362includes a gate or a base coupled to the input node and the impedance circuit370, a drain or a collector coupled to the output node and one or more components364, and a source or an emitter coupled to one or more components366. The transistor362can be coupled to a ground pad368via the one or more components366. The ground pad368can be configured to connect to a ground or other voltage potential. The example ofFIG.3illustrates the amplifier350configured as a common-source amplifier. However, the amplifier350can be implemented in other configurations. The one or more components364and/or the one or more components366can include one or more inductors, one or more capacitors, one or more transistors, or other components. Although illustrated inFIG.3, in some embodiments the one or more components364and/or the one or more components366can be eliminated. The transistor362, the one or more components364, the one or more components366, and/or a supply voltage (labeled “VDD”) can be referred to as the gain circuit. However, in some embodiments, one or more components of the impedance circuit370can additionally, or alternatively, be part of the gain circuit. The transistor362can be implemented as a single device or multiple devices, such as multiple transistors in a cascoded configuration. The transistor362can include a field-effect transistor (FET) (e.g., N-type or P-type device), such as a junction FET (JFET), insulated gate FET (e.g., a metal-oxide-semiconductor FET (MOSFET), a complementary metal-oxide-semiconductor (CMOS), etc.), and so on. Further, the transistor362can include a Bipolar junction transistor (BJT) (e.g., an NPN transistor, a PNP transistor, etc.), such as a heterojunction bipolar transistors (HBT), etc. For ease of illustration, the transistor362is shown in many examples as an FET, such as an n-type (or p-type) MOSFET. However, the transistor362can be implemented as any type of transistor. The impedance circuit370(sometimes referred to as the “input matching circuit370”) can include an inductor372and a switching-capacitive arm coupled in parallel to the inductor372. Although the inductor372is illustrated inFIG.3, in some embodiments another component is used, such as one or more capacitors, one or more resistors, one or more transistors, and so on. The switching-capacitive arm can include a capacitor374and a switch376coupled in series, as illustrated. Although a single capacitor and a single switch are illustrated inFIG.3, any number of capacitors and/or switches can be implemented in parallel or series with each other and/or the inductor372. In some embodiments, multiple switching-capacitive arms are implemented in parallel, such as that illustrated inFIG.8. The transistor376can be implemented as a wide variety of switches, such as voltage-controlled switches, current-controlled switches, etc. For example, the switch376can be implemented as a transistor, a mechanical switch, etc. A transistor can include a field-effect transistor (FET) (e.g., N-type or P-type device), such as a junction FET (JFET), insulated gate FET (e.g., a metal-oxide-semiconductor FET (MOSFET), a complementary metal-oxide-semiconductor (CMOS), etc.), and so on. Further, a transistor can include a Bipolar junction transistor (BJT) (e.g., an NPN transistor, a PNP transistor, etc.), such as a heterojunction bipolar transistors (HBT), etc. In embodiments, the amplifier350can be configured to operate in a plurality of gain modes (e.g., the amplifier350is implemented as a variable-gain amplifier). Each gain mode can be associated with a different amount of gain. For example, an input signal can be amplified by a first amount of amplification when the amplifier350is configured in a first gain mode, an input signal can be amplified by a second amount of amplification that is different than the first amount of amplification when the amplifier350is configured in a second gain mode, and so on. To set a gain mode, a controller (not illustrated) can provide a control signal to the amplifier350or another component to set the amplifier350to the gain mode. In some embodiments, the supply voltage (labeled “VDD”) can be configured to set a gain mode of the amplifier350. For example, the supply voltage can be controlled to provide a first voltage for a first gain mode, provide a second voltage for a second gain mode, and so on. The impedance circuit370can be configured based on a gain mode. In particular, a configuration of the switching-capacitive arm of the impedance circuit370can be adjusted based on a gain mode in which the amplifier350is operating. For example, in a first gain mode, the switch376can be placed in a closed state to allow a current to pass through the capacitor374(e.g., a closed circuit configuration), and in a second gain mode, the switch376can be placed in an open state to prevent a current from passing through the capacitor374(e.g., an open circuit configuration). By changing the configuration of the switching-capacitive arm, the amplifier350can change an impedance (e.g., inductance) for the amplifier350to provide a particular performance characteristic, such as to match an input impedance to an output impedance for multiple modes of operation. Further, by implementing the capacitor374, instead of inductors in a variety of configurations, the amplifier350can efficiently use area on a device. In some embodiments, an inductor can occupy an area that is ten times (or more) larger than an area occupied by capacitor. As such, the amplifier350can substantially reduce an area needed to implement an amplifier that is configured to provide multiple gain modes. FIGS.4A-4Billustrate example configurations of the amplifier350ofFIG.3for multiple gain modes in accordance with one or more embodiments. In particular,FIG.4Aillustrates the amplifier350configured to operate in a high-gain mode, whileFIG.4Billustrates the amplifier350configured to operate in a low-gain mode. Although particular configurations are illustrated for the amplifier350inFIGS.4A-4B, the configurations can be swapped and/or other configurations can be used. Further, although configurations are illustrated for two gain modes inFIGS.4A-4B, any number of gain modes can be implemented with any number of configurations and/or levels of amplification. A high-gain mode can generally be associated with more amplification than a low-gain mode. In one example, a high-gain mode can be associated with more than a first threshold of amplification, while a low-gain mode can be associated with less than the first threshold of amplification or less than a second threshold of amplification that is less than the first threshold of amplification. For instance, a high-gain mode can be associated with more than 20 dB of amplification, while a low-gain mode can be associated with less than 20 dB of amplification. In a high-gain mode, as illustrated inFIG.4A, the switching-capacitive arm of the impedance circuit370can be set to an open circuit configuration. In particular, the switch376is implemented with an open state so that the switching-capacitive arm is viewed as an open circuit (e.g., current passes through just the arm with the inductor372). Here, the inductance of the impedance circuit370is lower, since the switching-capacitive arm with the capacitor374is not a conducting path. In contrast, in a low-gain mode, as illustrated inFIG.4B, the switching-capacitive arm of the impedance circuit370is set to a closed-circuit configuration. In particular, the switch376is implemented with a closed state so that the switching-capacitive arm is viewed as a closed circuit (e.g., current passes through the arm with the inductor372and the switching-capacitive arm). Here, the inductance of the impedance circuit370is higher, since the switching-capacitive arm with the capacitor374is now a conducting path. In some embodiments, an amplifier, such as any of the amplifiers discussed herein, can provide a plurality of gain modes for a variety of purposes. For example, multiple gain modes can be used to convert received signals of different signal strengths to a relatively consistent signal strength (e.g., to a specific value or within a threshold to a specific value). To illustrate, multiple gain modes can be utilized to amplify received signals as a first radio-frequency device changes location relative to a second radio-frequency device and a signal strength of the received signals communicated between the first and second radio-frequency devices changes. In particular, an amplifier can use a first gain mode when the first radio-frequency device is a first distance from the second radio-frequency device and use a second gain mode when the first radio-frequency device is a second distance from the second radio-frequency device. FIG.4Cillustrates an example smith chart402to show characteristics of the amplifier350ofFIG.4Athat is configured to operate in a high-gain mode in accordance with one or more embodiments. The impedance circuit370can be implemented in an open state for the high-gain mode to provide a matched circuit, as illustrated by a point406inFIG.4C. The point406represents a Z value (e.g., impedance) of 1. As such, the amplifier350can provide a desired return loss (e.g., a relatively good S11 parameter) when operating in the high-gain mode. FIG.4Dillustrates an example smith chart404to show characteristics of the amplifier350ofFIG.4Bthat is configured to operate in the low-gain mode in accordance with one or more embodiments. The impedance circuit370can be implemented in a closed state for the low-gain mode to provide a matched circuit, as illustrated by a point408inFIG.4D. The point408represents a Z value (e.g., impedance) of 1. As such, the amplifier350can provide a desired return loss (e.g., a relatively good S11 parameter) when operating in the low-gain mode. FIG.5illustrates an example amplifier550with an impedance circuit570that includes a transistor576implemented as a switch in accordance with one or more embodiments. Here, the amplifier550can receive an input signal at an input node and provide an output signal at an output node. The amplifier550includes a transistor562to amplify the input signal. The transistor562includes a gate or a base coupled to the input node and the impedance circuit570, a drain or a collector coupled to the output node and one or more components564, and a source or an emitter coupled to one or more components566. The transistor562can be coupled to a ground pad568via the one or more components566. The one or more components564and/or the one or more components566can include one or more inductors, one or more capacitors, one or more transistors, or other components. In some embodiments, the amplifier550is implemented as a variable-gain amplifier configured for different gain modes. The impedance circuit570can include an inductor572and a switching-capacitive arm coupled in parallel to the inductor572. The switching-capacitive arm can include a capacitor574and the transistor576coupled in series, as illustrated. Although a single capacitor and a single transistor are illustrated inFIG.5, any number of capacitors and/or transistors can be implemented in parallel or series with each other and/or the inductor572. In this example, the transistor576is implemented to enable or disable the switching-capacitive arm (e.g., the capacitor574). Here, a controller520is coupled to a gate of the transistor576to control the transistor576by placing the transistor576in an open state (e.g., off state) or closed state (e.g., on state). In particular, the controller520can provide a control signal, such as a voltage or current signal, to bias the transistor576. In some embodiments, the controller520also provides a control signal to a supply voltage component to set a supply voltage. While in other embodiments, a separate controller is implemented to communicate with the supply voltage component. Although the controller520is shown outside the impedance circuit570, in some embodiments the controller520is part of the impedance circuit570. In some embodiments, the amplifier550is implemented with some components located on a first device552and some components located on a second device554, where the first device552can connect to the second device554at pads556. In some embodiments, the pads556are part of the second device554, as illustrated inFIG.5, while in other embodiments the pads556are part of the first device552or a combination of the second device554and the first device552. In the example ofFIG.5, the input node and the inductor572are located on the first device552and the one or more components564, the one or more components566, the ground pad568, the transistor562, the transistor576, and the capacitor574are located on the second device554. However, the components of the amplifier550can be arranged in a variety of manners on the first and second devices552and554. For example, the input node, the output node, the inductor572, the one or more components564, the one or more components566, the ground pad568, the transistor562, the transistor576, and/or the capacitor574can be arranged on a same device or multiple devices in a variety of configurations (e.g., two, three, four, etc. dies). Each of the first device552and the second device554can include a die, a substrate, a module, or any other medium or element configured to implement components. The inductor572and/or the capacitor574can have a variety of values. In some embodiments, the inductor572can have an inductance of 1 nH to 30 nH and the capacitor can have a capacitance of 100 fF to 100 pF. Although other inductance or capacitance values can be implemented. In some embodiments, the inductor572includes a fixed value (e.g., the inductor572is not variable). FIG.6an example amplifier650with an impedance circuit670and a degeneration circuit that includes multiple inductors in accordance with one or more embodiments. Here, the amplifier650can receive an input signal at an input node and provide an output signal at an output node. The amplifier650includes a transistor662to amplify the input signal. The transistor662includes a gate or a base coupled to the input node and the impedance circuit670, a drain or a collector coupled to the output node and one or more components664, and a source or an emitter coupled to a degeneration circuit that includes components666. The transistor662can be coupled to a ground pad668via the components666. The impedance circuit670can include an inductor672and a switching-capacitive arm coupled in parallel to the inductor672. The switching-capacitive arm can include a capacitor674and a switch676coupled in series, as illustrated. In some embodiments, the amplifier650is implemented as a variable-gain amplifier configured for different gain modes. In this example, the degeneration circuit includes a first inductor666A coupled to a second inductor666B and a switch666C. The switch666C can include a transistor, a mechanical switch, or another type of switch. The switch666C can be enabled or disabled to change a degeneration inductance for the amplifier650, such as to operate for different gain modes. For example, the switch666C can be controlled to operate in a closed state when the amplifier650is operating in a first gain mode (e.g., a high-gain mode), and can be controlled to operate in an open state when the amplifier650is operating in a second gain mode (e.g., a low-gain mode). The degeneration circuit can be controlled to increase performance of the amplifier650(in comparison to other amplifiers) by increasing linearity, reducing noise, helping with stability, and/or lowering input reflections, for example. As such, the amplifier650can achieve targeted or improved performance by using the degeneration circuit that is configurable to provide tailored inductances for different gain modes. Although the degeneration circuit is coupled to a source or an emitter of the transistor662in the example ofFIG.6, the degeneration circuit can be coupled to other portions of the transistor662, such as the gate, the drain/collector, the body, etc. FIG.7an example amplifier750with an impedance circuit770and a degeneration circuit that includes an inductor and a capacitor in accordance with one or more embodiments. Here, the amplifier750can receive an input signal at an input node and provide an output signal at an output node. The amplifier750includes a transistor762to amplify the input signal. The transistor762includes a gate or a base coupled to the input node and the impedance circuit770, a drain or a collector coupled to the output node and one or more components764, and a source or an emitter coupled to a degeneration circuit that includes components766. The transistor762can be coupled to a ground pad768via the components766. The impedance circuit770can include an inductor772and a switching-capacitive arm coupled in parallel to the inductor772. The switching-capacitive arm can include a capacitor774and a switch776coupled in series, as illustrated. In some embodiments, the amplifier750is implemented as a variable-gain amplifier configured for different gain modes. In this example, the degeneration circuit includes an inductor766A coupled in parallel to a capacitor766B and a switch766C. The switch766C can include a transistor, a mechanical switch, or another type of switch. The switch766C can be enabled or disabled to change a degeneration inductance for the amplifier650, such as to operate for different gain modes. For example, the switch766C can be controlled to operate in an open state when the amplifier750is operating in a first gain mode (e.g., a high-gain mode), and can be controlled to operate in a closed state when the amplifier750is operating in a second gain mode (e.g., a low-gain mode). The degeneration circuit can be controlled to increase performance of the amplifier750(in comparison to other amplifiers) by increasing linearity, reducing noise, helping with stability, and/or lowering input reflections, for example. As such, the amplifier750can achieve targeted or improved performance by using the degeneration circuit that is configurable to provide tailored inductances for different gain modes. Although the degeneration circuit is coupled to a source or an emitter of the transistor762in the example ofFIG.7, the degeneration circuit can be coupled to other portions of the transistor762, such as the gate, the drain/collector, the body, etc. FIG.8illustrates an example amplifier850with an impedance circuit870that includes multiple switching-capacitive arms in accordance with one or more embodiments. Here, the amplifier850can receive an input signal at an input node and provide an output signal at an output node. The amplifier850includes a transistor862to amplify the input signal. The transistor862includes a gate or a base coupled to the input node and the impedance circuit870, a drain or a collector coupled to the output node and one or more components864, and a source or an emitter coupled to one or more components866. The transistor862can be coupled to a ground pad868via the one or more components866. The one or more components864and/or the one or more components866can include one or more inductors, one or more capacitors, one or more transistors, or other components. In some embodiments, the amplifier850is implemented as a variable-gain amplifier configured for different gain modes. The impedance circuit870can include an inductor872and multiple switching-capacitive arms coupled in parallel to the inductor872and each other. The switching-capacitive arms include capacitors874(1)-874(N) and switches876(1)-876(N). In particular, each switching-capacitive arm includes a capacitor874and a transistor876coupled in series. In some embodiments, the multiple switching-capacitive arms can be implemented to more finely tune the amplifier850and/or to tune the amplifier850to more gain modes, in comparison to other amplifiers. For example, the amplifier850can be implemented with five to eight gain modes, with the impedance circuit870including four to seven switching-capacitive arms for the gain modes. In other examples, any number of gain modes can be implemented with any number of switching-capacitive arms. FIG.9illustrates an example flow diagram of a process900of controlling an amplifier in accordance with one or more embodiments. The process900can be implemented by any of the components discussed herein, such as any component of a radio-frequency device. At902, a control signal(s) regarding a gain mode can be generated. For example, a controller can generate a control signal indicating a gain mode and/or an impedance (e.g., input impedance, degeneration inductance, etc.) to implement for the gain mode. The controller can generate the control signal based on a variety of factors, such as a QoS metric, a signal from another component, etc. At904, the control signal(s) can be sent to one or more components to configure an amplifier for the gain mode. For example, a controller can send a control signal to one or more components of an amplifier, such as an impedance circuit, a degeneration circuit, and/or a supply voltage component, to configure the one or more components of the amplifier to implement a gain mode that is selected for operation. The control signal can configure a component of the amplifier by setting a supply voltage, biasing a transistor of an impedance or degeneration circuit to an on or off state, etc. As such, an impedance circuit of a variable-gain amplifier can be configured to provide a tailored amount of impedance for a gain mode. At906, an input signal can be received. For example, an amplifier can receive a signal from an antenna. Alternatively, or additionally, an amplifier can receive a signal from a transceiver or another component of a radio-frequency device of the amplifier. At908, the input signal can be amplified based on the gain mode. For example, an amplifier that is configured for the gain mode, such as with a tailored amount of input impedance and/or degeneration inductance, can amplify the input signal with an amplification amount that is associated with the gain mode. At910, the amplified signal can be provided to one or more components. For example, a variable-gain amplifier can provide an amplified signal as an output signal to one or more components of a radio-frequency device associated with the amplifier. For instance, the amplified signal can be provided to a transceiver of the radio-frequency device, an antenna of the radio-frequency device, and so on. FIG.10illustrates example biasing circuitry1000for a transistor1002in accordance with one or more embodiments. The transistor1002can be representative of any of the transistors discussed herein. That is, any of the transistors discussed herein can be biased in a similar manner as that of the example biasing circuitry1000of the transistor1002. As such, although not illustrated in some cases, any of the transistors discussed herein can be connected to any number of biasing circuits to control the transistors. In the example ofFIG.10, a source and/or a drain of the transistor1002is connected to a source/drain biasing circuit1004that applies a biasing voltage to the source and/or the drain of the transistor1002, a body of the transistor1002is connected to a body biasing circuit1006that applies a biasing voltage to the body of the transistor1002, and a gate of the transistor1002is connected to a gate biasing circuit1008that applies a biasing voltage to the gate of the transistor1002. The source/drain biasing circuit1004, the body biasing circuit1006, and/or the gate biasing circuit1008can apply voltages that are more or less than a value to control the transistor1002(e.g., place the transistor in an on or off state). In some embodiments, the source/drain biasing circuit1004, the body biasing circuit1006, and/or the gate biasing circuit1008are implemented as a controller. Further, in some embodiments, the transistor1002is implemented as a transistor stack that includes multiple transistors connected in series. FIG.11illustrates an example radio-frequency module1100in accordance with one or more embodiments. The radio-frequency module1100includes a packaging substrate1102, a semiconductor die1104mounted on the packaging substrate1102, an amplifier1106implemented on the semiconductor die1104, and a controller1108implemented on the semiconductor die1104. The amplifier1106can include any of the amplifiers discussed herein. Similarly, the controller1108can include any of the controllers discussed herein. In some embodiments, the amplifier1106is implemented within a low noise amplifier (LNA)1110provided on the semiconductor die1104. Alternatively, or additionally, the amplifier1106is implemented within a power amplifier (PA)1112. The amplifier1106can also be implemented within other amplifiers. Further, in some embodiments, multiple amplifiers are implemented within different components (e.g., a first amplifier is implemented within the LNA1110and a second amplifier is implemented within the PA1112). Although illustrated as separate components, in some cases the controller1108is implemented as part of the amplifier1106. In some embodiments, the radio-frequency module1100can be a front-end module (FEM). As shown, the amplifier1106can include a gain circuit1114coupled to an impedance circuit1116. Although the gain circuit1114and the impedance circuit1116are illustrated as being implemented on the same semiconductor die and packaging substrate, in some embodiments the gain circuit1114and the impedance circuit1116are implemented on different semiconductor dies and/or packaging substrates. For example, the gain circuit1114can be implemented on a first semiconductor die and the impedance circuit1116can be implemented on a second semiconductor die. In some embodiments, a capacitor and/or an inductor of the impedance circuit1116can be surface mounted. Further, in some embodiments, the controller1108and the amplifier1106can be implemented on different semiconductor dies and/or packaging substrates. FIG.12illustrates an example radio-frequency device1200in accordance with one or more embodiments. As shown, the radio-frequency device1200can include a baseband sub-system1202, a transceiver1204, a power amplifier (PA) module1206, a duplexer1208, a switch1210, one or more antennas1212, a power management system1214, a battery1216, a memory1218, and a user interface1220. The baseband sub-system1202, the transceiver1204, the PA module1206, the duplexer1208, the switch1210, one or more antennas1212, the power management system1214, the battery1216, the memory1218, and/or the user interface1220can be in communication with each other. The baseband sub-system1202can be connected to the user interface1220to facilitate various input and/or output of voice and/or data provided to and/or received from a user. The baseband sub-system1202can also be connected to the memory1218that is configured to store data and/or instructions to facilitate operation of the radio-frequency device1200and/or to provide storage of information for a user. The transceiver1204can generate radio-frequency (RF) signals for transmission and/or process incoming RF signals received from the one or more antennas1212. The transceiver1204can interact with the baseband sub-system1202that is configured to provide conversion between data and/or voice signals suitable for a user and/or RF signals suitable for the transceiver1204. The transceiver1204can also be connected to the power management system1214. The PA module1206can include a plurality of PAs that can provide an amplified RF signal to the switch1210(e.g., via the duplexer1208). The PA module1206can also receive an unamplified RF signal from the transceiver1204. In examples, the duplexer1208can allow transmit and/or receive operations to be performed simultaneously using a common antenna. InFIG.12, received signals are shown to be routed to “Rx” paths that can include, for example, a low-noise amplifier (LNA). In some embodiments, any of the amplifiers discussed herein are implemented within an LNA, the PA module1206, or another component. The switch1210can route an RF signal to and/or from the one or more antennas1212. The switch1210can include any number of poles and/or throws. In examples, the switch1210is implemented on a module. The module can include a packaging substrate configured to receive a plurality of components. Although one switch1210is illustrated in the example ofFIG.12, any number of switches can be implemented on the radio-frequency device1200. The one or more antennas1212can include antennas for transmitting and/or receiving signals associated with a wide variety of frequencies and communications standards. In examples, the one or more antennas1212support Multiple-Input Multiple-output (MIMO) communications and/or switched diversity communications. For example, MIMO communications use multiple antennas for communicating multiple data streams over a single radio frequency channel. MIMO communications benefit from higher signal to noise ratio, improved coding, and/or reduced signal interference due to spatial multiplexing differences of the radio environment. Switched diversity can refer to communications in which a particular antenna is selected for operation at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on a variety of factors, such as an observed bit error rate and/or a signal strength indicator. In examples, the one or more antennas1212can include a diversity antenna. The power management system1214can be configured to manage power for operation of the radio-frequency device1200. The power management system1214can provide power to any number of components of the radio-frequency device1200. The power management system1214can receive a battery voltage from the battery1216. The battery1216can be any suitable battery for use in the radio-frequency device1200, including, for example, a lithium-ion battery. The radio-frequency device1200can communicate using a wide variety of communications technologies, including, but not limited to, 2G, 3G, 4G (including Long Term Evolution (LTE), LTE-Advanced, and LTE-Advanced Pro), 5G, Wireless Local Area Network (WLAN) (for instance, Wi-Fi), Wireless Personal Area Network (WPAN) (for instance, Bluetooth and ZigBee), Wireless Metropolitan Area Network (WMAN) (for instance, WiMax), and/or satellite-based radio navigation systems (for instance, Global Positioning System (GPS) technologies). The radio-frequency device1200can operate with beamforming in certain implementations. For example, the radio-frequency device1200can include phase shifters having variable phase controlled by the transceiver1204. Additionally, the phase shifters can be controlled to provide beam formation and directivity for transmission and/or reception of signals using the one or more antennas1212. For example, in the context of signal transmission, the phases of the transmit signals provided to the one or more antennas1212are controlled such that radiated signals from the one or more antennas1212combine using constructive and destructive interference to generate an aggregate transmit signal exhibiting beam-like qualities with more signal strength propagating in a given direction. In the context of signal reception, the phases are controlled such that more signal energy is received when the signal is arriving to the one or more antennas1212from a particular direction. In some embodiments, the one or more antennas1212include one or more arrays of antenna elements to enhance beamforming. In examples, the radio-frequency device1200supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD) and can be used to aggregate a plurality of carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous and can include carriers separated in frequency within a common band or in different bands. The radio-frequency device1200can include a wide variety of devices that are configured to communicate wirelessly. For example, the radio-frequency device1200can include a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a smart appliance, a smart vehicle, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, an automobile, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wearable device (e.g., a watch), a clock, etc. The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Components discussed herein can be coupled in a variety of manners, such as through a conductive material. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word can cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The above description of embodiments of the disclosure is not intended to be exhaustive or to limit the disclosure to the precise form disclosed above. While specific embodiments, and examples, are described above for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. For example, while processes or blocks can be presented in a given order, alternative embodiments can perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks can be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks can be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks can instead be performed in parallel or can be performed at different times. The features described herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. In some embodiments, the methods and/or systems discussed herein can be implemented at least in part by control circuitry and/or memory. For example, memory can store executable instructions that, when executed by control circuitry, cause the control circuitry to perform operations discussed herein. To illustrate, in some embodiments of the process ofFIG.9, a device can include memory and control circuitry, wherein the memory can store executable instructions that, when executed by the control circuitry, cause the control circuitry to perform, at least in part, any of the operations of the process ofFIG.9. Additionally, or alternatively, other methods and/or systems discussed herein can be implemented at least in part with control circuitry and memory storing executable instructions. Control circuitry can include one or more processors, such as one or more central processing units (CPUs), one or more microprocessors, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), and/or other processing circuitry. Alternatively, or additionally, control circuitry can include one or more application specific integrated circuits (ASIC), one or more field-programmable gate arrays (FPGAs), one or more program-specific standard products (ASSPs), one or more complex programmable logic devices (CPLDs), and/or the like. Control circuitry can be configured to execute one or more instructions stored in memory to thereby perform one or more operations to implement various functionality discussed herein. Memory can include any suitable or desirable type of computer-readable media. For example, computer-readable media can include one or more volatile data storage devices, non-volatile data storage devices, removable data storage devices, and/or nonremovable data storage devices implemented using any technology, layout, and/or data structure(s)/protocol, including any suitable or desirable computer-readable instructions, data structures, program modules, or other types of data. Computer-readable media that may be implemented in accordance with embodiments of the present disclosure includes, but is not limited to, phase change memory, static random-access memory (SRAM), dynamic random-access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information for access by a computing device. As used in certain contexts herein, computer-readable media may not generally include communication media, such as modulated data signals and carrier waves. As such, computer-readable media should generally be understood to refer to non-transitory media. While some embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the disclosure. Claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 52,271 |
11942913 | DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, before the description of the embodiments, a principle of embodiments of the present invention will be described. Principle of Embodiments of the Invention In embodiments of the present invention, in consideration of the problem described above, a gain adjustment unit and a power monitor unit capable of reducing power consumption to almost zero will be proposed and means constituting a high-output variable gain amplifier by combining the gain adjustment unit and the power monitor unit with a power amplifier will be provided. First, power consumption by the power monitor unit will be described. Conventionally, there is a power monitor circuit using a diode circuit.FIG.15shows an outline of a conventional power monitor circuit4. The power monitor circuit4is configured such that, by connecting one end of a coupler CP (in the present example, a high resistance R1) to an output line of an amplifier A1which is a monitoring target and connecting another end of the coupler CP to an anode of a diode D1, a part of output of the amplifier A1is taken out by the coupler CP and input to the diode D1. Since the diode D1has characteristics indicated by a solid line inFIG.16, by biasing the anode of the diode D1to threshold voltage (Vth), a half-wave rectified waveform indicated as a diode output signal inFIG.16appears at a cathode of the diode D1. An amplitude of the half-wave rectified waveform is proportional to power taken out by the coupler CP or, in other words, proportional to output of the amplifier A1and, consequently, monitoring of the output of the amplifier A1is realized. In order to obtain DC voltage (or a DC current) proportional to an amplitude of the diode output signal as monitor information from a monitor terminal PM, a cathode of the diode D1is provided with a low-pass filter LPF1. With this method, since the anode of the diode D1must be constantly biased to Vth and a currently flows through the diode D1upon diode detection, power consumption in the power monitor circuit4occurs. When the power monitor circuit4is applied as a power monitor unit to an amplifier circuit with large output power such as a power amplifier, since a detected current also increases, even larger power consumption occurs. Next, power consumption in the gain adjustment unit will be described. Each of the gain adjustment units described in NPL 1 and 2 uses an active element such as an operational amplifier. Therefore, the gain adjustment units generate power consumption. Embodiments of the present invention provide a variable gain amplifier which reduces power consumption at the power monitor unit and the gain adjustment unit to almost zero as described above. Embodiments of the present invention include a method that is particularly suitably applied to amplifiers with large output power such as a power amplifier. First, a power monitor circuit (a power monitor unit) that is proposed as a power monitor unit in embodiments of the present invention will be described.FIG.1shows an outline of the power monitor circuit. In a similar manner to the conventional power monitor circuit4(FIG.15), a power monitor circuit5is also configured such that, by connecting one end of a coupler CP (in the present example, a high resistance R1) to an output line of an amplifier A1and connecting another end of the coupler CP to an anode of a diode D1, a part of output of the amplifier A1is taken out by the coupler CP and input to the diode D1. In addition, the power monitor circuit5is configured such that a low-pass filter LPF1is connected to a cathode of the diode D1and a DC component of a signal detected by the diode D1is output to a monitor terminal PM. The power monitor circuit5differs from the conventional power monitor circuit4in that the anode of the diode D1is not biased to threshold voltage Vth but is unbiased (set to ground potential=0 volts). In other words, the power monitor circuit5is not provided by a bias circuit for the diode. In this case, although weak signals cannot be detected since sharp detection characteristics near the threshold voltage Vth are unavailable, output power of a circuit such as a power amplifier with large output can be monitored. In other words, with a circuit with large output power, voltage generated at the anode of the diode D1is large and, as shown inFIG.2, the voltage of the anode of the diode D1exceeds Vth. In this case, a portion with larger amplitude than Vth is to be detected in the diode D1as shown inFIG.2and power can be monitored. Specific minimum output power that enables such monitoring to be performed can be calculated as follows. As shown inFIG.3, let us assume that impedance (load resistance) of a load connected to output of the amplifier A1is Rload. Let us also assume that output power of the amplifier A1is Pout and voltage applied to the load is Vload. In this case, using Vload and Rload, Pout is represented by Formula (1) below. Formula1Pout=Vload22Rload(1) From Formula (1), Vload is represented by Formula (2) below. Formula 2 Vload=√{square root over (2RloadPout)} (2) Once Vload in Formula (2) exceeds the threshold voltage Vth, the output power of the amplifier A1can be monitored with the configuration shown inFIG.1. Usually, in power amplifiers using coaxial system components, load resistance is 50 Ω. In addition, in cases of differential output, 100 Ω may be used as load resistance. While a waveguide is used in frequency bands exceeding 100 GHz, in such a case, the load resistance (equivalent to characteristic impedance of the waveguide) is 350 Ω. FIG.4shows calculation results of Vload when using these load resistances. InFIG.4, an abscissa represents Pout.FIG.4reveals that, when using a diode constituted by a Si-based device, embodiments of the present invention can be used with amplifier output power in a range where the value of Vload exceeds 0.7 V, and when using a compound-based diode (albeit an example since threshold voltage varies among different compound semiconductors), embodiments of the present invention can be used with amplifier output power at which the value of Vload exceeds 0.5 V. For example, when the load resistance Rload is 50 Ω, the configuration shown inFIG.1can be realized using a Si-based diode with a power amplifier in which Pout exceeds 7 dBm. In addition, based on Formula 2 andFIG.4, since Vload characteristically increases as Rload increases, embodiments of the present invention are particularly effective with respect to power amplifiers constituted by a waveguide-system component with a large load resistance value. In other words, embodiments of the present invention are useful in frequency bands equal to or exceeding 100 GHz in which a waveguide is used. Next, a method of realizing a gain adjustment unit that does not generate power consumption will be described. A distribution switch (a switch made up of source-grounding FETs1to n)6as shown inFIG.5is predisposed to vary its pass characteristics depending on gate voltage of an FET. This is because the distribution switch6takes advantage of the fact that drain-source resistance of an FET varies depending on gate voltage. By connecting the distribution switch6shown inFIG.5to an input unit of a power amplifier or between circuit stages of the power amplifier, gain of the amplifier can be made variable. InFIG.5, since a current does not flow through the control terminal PC for adjusting voltage of a gate terminal, power consumption necessary for varying gain is not generated. First Embodiment As a first embodiment of the present invention, an example will be described in which the power monitor unit constituted by a power monitor circuit and the gain adjustment unit constituted by a distribution switch as described in [Principle of embodiments of the invention] above are applied to a 180 GHz-band amplifier. FIG.6shows an outline of the example.FIG.6represents an overall configuration. A variable gain amplifier according to the present embodiment includes an amplifier circuit (a 180 GHz-band amplifier)101, a gain adjustment unit102, and a power monitor unit103.FIG.7shows a unit configuration (a configuration of a unit amplifier) per one amplifier stage in the amplifier circuit101. As shown inFIG.6, the amplifier circuit101is configured such that the unit amplifier shown inFIG.7is arranged in six serial stages and four parallel stages. In addition, in order to consolidate the amplifiers arranged in four parallel stages to one port in an input/output unit of the amplifier, a 4-way distribution/combination circuit constituted by two-branch circuits in 2 stages is arranged in the input/output unit. An InP-HEMT with a gate width of 40 μm was adopted as the transistor used in the unit amplifier shown inFIG.7. In addition, element values of resistors, capacitors, and transmission lines shown inFIG.7were as follows. The resistor r1is 500 c, the capacitors C1, C2, and C3are respectively 50 fF, 400 fF, and 42 fF, and the transmission lines T1, T2, and T3all have characteristic impedance of 50 n and have electrical lengths at 180 GHz of, respectively, 10 degrees, 90 degrees, and 20 degrees. In the power monitor unit103used in the overall configuration shown inFIG.6, as the diode D1, an FET is used which equivalently acts as a diode by using a gate of an InP-HEMT with a gate width of 5 μm as an anode and short-circuiting a drain and a source to create a cathode. Vth of the present diode D1is approximately 0.25 V. In addition, a value of R1is set to 1000 Ω, a value of R2is set to 500 Ω, a value of C2is set to 450 fF, and a value of C3is set to 2000 fF. Furthermore, as described in [Principle of embodiments of the invention], the anode of the diode D1is unbiased. In other words, applied voltage to the anode of the diode D1is set to o volts (ground potential), and the anode and the cathode of the diode D1are set to a same potential. FIG.8shows a calculation result of voltage (monitor output voltage) which is generated at the monitor terminal PM in the configuration shown inFIG.6. In the calculation, by setting the value of the load resistance to 50 Ω for both input and output, monitor output voltage is plotted when output power (amplifier output power) of the amplifier circuit101is varied from −7 dBm to 12 dBm which is maximum output power. FIG.8reveals that monitor output voltage increases significantly as the amplifier output power increases from near 0 dBm and that the power monitor unit103is functioning as a monitor. It should be noted thatFIG.4in [Principle of embodiments of the invention] shows that, in a case of a load of 50 Ω, the monitor output voltage starts to exceed 0.25 V which is Vth in this case when the amplifier output power is near −2 dBm, which more or less corresponds to the result shown inFIG.8. This further corroborates effectiveness of the method proposed by embodiments of the present invention as described in [Principle of embodiments of the invention]. Next, a configuration shown inFIG.9will be described as a configuration for further improving sensitivity (a value of monitor output voltage relative to amplifier output power) of the power monitor unit103. InFIG.9, a transmission line of which one end is connected to ground potential is connected as a short stub Ts to the anode of the diode D1shown inFIG.6. Accordingly, the sensitivity of the power monitor unit103improves. A reason therefor is as follows. It should be noted that the short stub Ts may be an inductor. In the present specification, transmission lines and inductors will be collectively referred to as short stubs. An equivalent circuit in a vicinity of the anode of the diode D1in the configuration shown inFIG.6can be drawn as inFIG.10. In this case, since an input capacitance is inevitably present in the diode D1and the input capacitance lowers impedance of the anode of the diode D1, consequently, voltage that is generated at the anode of the diode D1drops. Therefore, the sensitivity of the power monitor unit103is inevitably lower than that shown inFIG.4in [Principle of embodiments of the invention}. In consideration thereof, an effective way to improve sensitivity is to cancel the input capacitance of the diode D1. As a method thereof, since adding the short stub Ts in parallel to the anode of the diode D1as shown inFIG.9causes the short stubs Ts to act as inductances as shown inFIG.11, the input capacitance of the diode D1and the inductances of the short stubs Ts act as a parallel resonator and the input capacitance of the diode D1can be canceled. FIG.12shows a calculation result of monitor output voltage in the configuration shown inFIG.9. The short stub Ts has a characteristic impedance of 50 Ω and an electrical length at 180 GHz of 20 degrees. It is revealed that the sensitivity of the power monitor unit103has improved as compared toFIG.8. In addition, whileFIG.4shows that, in a case of a load of 50 Ω, the monitor output voltage starts to exceed 0.25 V which is Vth in this case when the amplifier output power is near −2 dBm,FIG.12shows that the monitor output voltage actually starts to significantly rise from near −2 dBm, which reveals that characteristics close to a theoretical value are being produced. This is because the input capacitance of the diode D1has been canceled by the short stub Ts. In this case, since a parallel resonance frequency fr inFIG.11is calculated as Formula3fr=12πLC(3) L which sets frequency of the amplifier to fr is uniquely determined, and when designing the circuit shown inFIG.9, parameters of the short stub Ts may be determined so as to include such L. In both of the configurations shown inFIGS.6and9described above, since the voltage applied to the anode of the diode D1of the power monitor unit103is zero, power consumption at the power monitor unit103is approximately zero. As is apparent fromFIGS.8and12, while embodiments of the present invention are unsuitable for monitoring lower power unlike a conventional power monitor circuit (FIG.15), embodiments of the present invention are suitable as a power monitor circuit of amplifiers of which output power exceeds 0 dBm such as an ordinary power amplifier. Next, the gain adjustment unit102constituted by the distribution switch6arranged in the input unit of the amplifier circuit101in the configurations shown inFIGS.6and9will be described. The distribution switch6is configured by serially connecting a basic switch in five stages, the basic switch being constituted by an InP-HEMT with a gate width of 10 μm and a transmission line with a characteristic impedance of 65 Ω and an electrical length at 180 GHz of 35 degrees. FIG.13is a diagram showing a calculation result when input to the control terminal PC of the distribution switch6is adjusted and the gain of the amplifier circuit101is changed from maximum gain to minimum gain. It is shown that the present switch realizes a gain adjustment of 10 dB. Since a current does not flow through the control terminal PC of the present switch, power consumption is almost zero. As described above, in the present configuration, power consumption is almost zero in both the power monitor unit103and the gain adjustment unit102which are necessary for a variable gain amplifier. In other words, a system designer can allocate all power consumption to be originally allocated to these circuits to the power amplifier and, as described in [Principle of embodiments of the invention], a variable gain amplifier with higher output power than conventional variable gain amplifiers can be realized. Second Embodiment As a second embodiment, means for improving accuracy of the power monitor unit103will be described. In this case, accuracy refers to an amount of fluctuation of monitor output voltage when output power of an amplifier is a given value. As shown inFIG.2, since embodiments of the present invention uses sharp diode characteristics near the threshold voltage of a diode, when slight voltage is generated between an anode and a cathode, monitor output voltage varies. In consideration thereof, in the second embodiment, a configuration will be described in which a grounded waveguide coupler is used as the coupler CP in order to set a potential of the anode of the diode D1of the power monitor unit103of an output stage to a stable ground potential. An example of a grounded coupler is a waveguide ridge coupler such as that described as a high frequency connection structure in PTL 1. A signal line of the present coupler is directly connected to a wall surface of the waveguide via a metal ridge. Accordingly, the anode potential of the diode D1arranged in the output stage can be set to stable ground potential of the waveguide wall surface. As a result, the power monitor unit103can be realized in a stable and highly accurate manner. Expansion of Embodiments While embodiments of the present invention have been described with reference to embodiments, it is to be understood that the present invention is not limited to the embodiments described above. Various modifications to the configurations and details of the present invention will occur to and can be made by those skilled in the art within the technical scope of the present invention. REFERENCE SIGNS LIST 5Power monitor circuitD1DiodeCP CouplerLPF1Low-pass filterA1AmplifierPM Monitor terminalPC Control terminal6Distribution switch101Amplifier circuit (180 GHz-band amplifier)102Gain adjustment unit103Power monitor unitTs Short stub | 17,691 |
11942914 | MODE FOR CARRYING OUT THE INVENTION In the following, an embodiment of a noise filter and wire harness is described with reference to the drawings. An X axis of XYZ axes in the drawings indicates a width direction of a noise filter14(housing21), a Y axis is orthogonal to the X axis and indicates an inward direction of the noise filter14, and a Z axis is orthogonal to an XY plane and indicates a height direction of the noise filter14. In the drawings, portions of the configuration may be exaggerated or simplified for ease of illustration. Also, the dimensional ratios of the various components may differ from reality. As illustrated inFIG.1, a vehicle wire harness10according to the present embodiment includes a wire13that links a power source11and a load12, and the noise filter14that is connected to the wire13. The wire13is a coated wire in which a core wire configured by a conductor is covered by an insulating coating, and electricity from the power source11is supplied to the load12via the wire13. The wire13is routed in the vehicle on a predetermined path. The wire harness10is configured by forming a plurality of wires that include the wire13into a bundle, but wires other than the wire13are omitted from the drawings. The power source11is a generator (alternator) in an automobile and supplies power to various loads, including the load12, by generating electricity having a three-phase current and using a diode inside a regulator to rectify the current. However, since the current is not completely rectified, the power source11supplies the load12with electricity that contains noise. An example of the load may include a defogger circuit for a rear windshield of a vehicle, for example. Generally, a defogger circuit is often provided near an AM radio antenna, and because the defogger circuit converts electricity into heat, the circuit uses a large amount of power and generates significant noise. Therefore, the noise generated by the defogger circuit is likely to affect the AM radio antenna. The noise filter14includes a resin housing21, a capacitor22serving as a noise prevention element that is housed inside the housing21, a ground terminal23that is connected to one electrode of the capacitor22, and a noise filter wire24(also referred to simply as a wire24below) that is connected to the other electrode of the capacitor22. The interior of the housing21is filled with a potting material25composed of epoxy resin, for example. The noise filter wire24is a coated wire in which a core wire configured by a conductor is covered by an insulating coating. A first end24aof the noise filter wire24is connected to the capacitor22, and a second end24bside of the noise filter wire24is connected by splicing to a middle portion of the wire13. Specifically, an exposed portion13a,where the core wire is exposed by middle stripping the insulating coating, is formed at the middle portion of the wire13. In addition, an exposed portion24c,where the core wire is exposed by end stripping the insulating coating, is formed on the second end24bof the noise filter24. Then, the exposed portion13aof the wire13and the exposed portion24cof the noise filter wire24are lined up so as to be substantially parallel to each other, and the exposed portions13aand24care crimped by a splice terminal S. As illustrated inFIGS.2and3, the housing21has a cylindrical outer circumferential wall31that opens in the height direction Z and a bottom32(seeFIG.3) that closes off one end of the outer circumferential wall31in the height direction Z. In the following description, the bottom32side is described as downward in the height direction Z of the housing21, and an opening33side on the opposite side from the bottom32is described as upward in the height direction Z. The housing21has a rectangular parallelepiped shape that only opens upward. In other words, the outer circumferential wall31has a substantially rectangular shape in plan view (view in the height direction Z). A wire lead-out portion34is formed on a top end of the outer circumferential wall31on a first end side of the width direction X of the outer circumferential wall31, the wire lead-out portion34guiding a lead-out portion of the wire24that is led outside the housing21through the opening33. The outer circumferential wall31is configured to include a pair of walls (first wall31aand second wall31b) that face each other in the inward direction Y of the housing21. The first wall31aand second wall31beach form a flat plate shape perpendicular to the inward direction Y of the housing21. The first wall31aand second wall31bare parallel to each other. As illustrated inFIG.4, a fixation portion35that is fixed to a vehicle body panel P is integrally molded on an outer surface of the first wall31a.Overall, the fixation portion35projects along the inward direction Y of the housing21. In other words, the overall projection direction of the fixation portion35runs from the outer surface of the first wall31aand is perpendicular to the opening direction of the opening33(direction that follows the height direction Z). In addition, the fixation portion35according to the present embodiment includes a pair of engagement portions35athat extend toward the first wall31afrom a forefront end portion that is inserted through to a back side of the vehicle body panel P (seeFIG.2). As illustrated inFIGS.4and6, the ground terminal23is formed by a press-worked metal plate, and is accommodated in the housing21such that a portion of the ground terminal23projects out through the opening33. The ground terminal23is a metal terminal that integrally includes a connection portion41connected inside the housing21to the capacitor22, a grounding portion42that is led outside the housing21and is grounded on the vehicle body panel P, and a linking portion43that joins the connection portion41and the grounding portion42. The portion of the linking portion43that is arranged inside the housing21is provided along an inner surface of the first wall31aand, in the present embodiment, the linking portion43is in contact with the inner surface of the first wall31a.In other words, the linking portion43corresponds to a contact portion that makes contact with the first wall31a. A bent portion44that bends at substantially a right angle along the bottom32is formed at a lower end of the linking portion43in the height direction Z (end on the bottom32side). The connection portion41that is connected to the capacitor22is formed so as to extend upward in the height direction Z from one width direction X end of the bent portion44. As illustrated inFIG.6, the linking portion43of the ground terminal23has a slit43athat is formed in a straight line shape that follows the height direction Z. On the other hand, a regulating portion36that projects into the housing21is formed on the inner surface of the first wall31aof the housing21. The regulating portion36extends in a straight line shape that follows the height direction Z. Also, the regulating portion36is fitted to the slit43aon the ground terminal23side. Thus, displacement of the ground terminal23in the width direction X is regulated in a state prior to filling in the potting material25. As illustrated inFIG.4, the grounding portion42of the ground terminal23that is led out of the housing21extends upward in the height direction Z. The grounding portion42has a plate shape that is perpendicular to the inward direction Y. A bolt insertion hole42afor fixing the grounding portion42to the vehicle body panel P using a bolt that is not shown in the drawings is formed in the grounding portion42by perforation. By fixing the grounding portion42to the vehicle body panel P, the capacitor22is body grounded. A step portion45is formed at a position running from the linking portion43to the grounding portion42on the ground terminal23. Through the step portion45, the grounding portion42displaces in the opposite direction from the opening side in the inward direction Y. In other words, the grounding portion42is formed to be offset from the linking portion43in the inward direction Y. The grounding portion42is thereby configured so as to be located above the first wall31ain the height direction Z. In addition, in the present embodiment, the plate thickness of the grounding portion42and the plate thickness of the first wall31aare defined to be equal in the inward direction Y. Accordingly, a first surface42bof the grounding portion42that makes contact with the vehicle body panel P and the outer surface of the first wall31aare flush to each other and a second surface42c(reverse face of the first surface42b) of the grounding portion42and the inner surface of the first wall31aare flush to each other. As illustrated inFIGS.4and6, a retainer portion37is formed on a top end portion of the regulating portion36, the retainer portion37extending upward in the height direction Z (toward the exterior of the housing21) through the opening33of the housing21. The retainer portion37extends further upward than a top end of the slit43aof the ground terminal23and also is in contact with the second surface42cof the grounding portion42. In other words, the retainer portion37holds a reverse face side of a surface of the ground terminal23that faces the first wall31a. As illustrated inFIGS.3,4, and5, the capacitor22is a wound film capacitor and is provided such that the width direction (winding axis direction) of the capacitor22is substantially parallel to the width direction X of the housing21. Each end face22aand22bon both sides of the width direction (X axis direction) of the capacitor22is configured as an electrode surface. In addition, the capacitor22is arranged above the bent portion44of the ground terminal23in the height direction Z, and faces the linking portion43of the ground terminal23in the inward direction Y. The first end24aof the wire24is directly connected, by welding or soldering, to one of the end faces,22a,that serves as an electrode surface. The wire24extends upward in the height direction Z from the first end24athat is connected to the end face22aof the capacitor22, and is bent near the opening33and led in the width direction X out through the wire lead-out portion34(seeFIG.3). In addition, the connecting portion41of the ground terminal23is directly connected, by welding or soldering, to the other of the end faces,22b,that serves as an electrode surface of the capacitor22. As illustrated inFIG.5, two ribs31care formed on the second wall31bof the outer circumferential wall31, projecting in the inward direction Y from the inner surface of the second wall31b.Each of the ribs31cextends in a straight line shape that follows the height direction Z. In addition, each of the ribs31cis formed to project an equal amount as the other. A forefront end of each rib31cin the inward direction Y is capable of making contact with the capacitor22housed in the housing21. In other words, with respect to the second wall31b,the capacitor22only makes contact with the ribs31cand does not make contact with the inner surface of the second wall31bitself, and so a gap equal to or greater than the projection amount of the ribs31cis ensured between the capacitor22and the inner surface of the second wall31bitself. This allows the potting material25to be filled readily in a state where the capacitor22is housed in the housing21. As illustrated inFIG.6, a pair of ribs31dthat extend in a straight line shape that follows the height direction Z are formed projecting on the inner surface of the first wall31a.Each of the ribs31dof the first wall31aare formed at the same positions in the width direction X as each of the ribs31cof the second wall31b,described above. In addition, in the present embodiment, each of the ribs31dand31care defined so as to project an equal amount with respect to one another in the inward direction Y. The potting material25that is filled into the housing21covers the entire capacitor22, the connecting portion41of the ground terminal23that is connected to the capacitor22, and the site of connection between the capacitor22and the first end24aof the wire24. Accordingly, infiltration of water and the like into the housing21is prevented and corrosion at the sites where the ground terminal23and the wire24are connected to the capacitor22can be prevented. FIG.7is a graph explaining the relationship between the length of the noise filter wire24and frequency characteristics of the noise filter14. The solid line graph, the one-dash line graph, and the two-dash line graph inFIG.7respectively show the frequency characteristics (noise elimination characteristics) of the noise filter14when the length of the noise filter wire24is changed. The length of the noise filter wire24has a shorter setting in the order of the solid line graph, the one-dash line graph, and the two-dash line graph. As illustrated inFIG.7, the shorter the noise filter wire24becomes, the greater a self-resonant frequency f (frequency where elimination is easy for the noise filter14) becomes. In other words, with the noise filter14according to the present embodiment, the frequency characteristics (noise elimination characteristics) can be adjusted by changing the length of the wire24. A function of the present embodiment is described. When power is supplied from the power source11to the load12, noise carried in the electric current is dampened by an effect of the capacitor22. Accordingly, noise transmitted from the power source11to the load12is decreased. Effects of the present embodiment are described. (1) The noise filter14includes the capacitor22that is housed inside the housing21, the ground terminal23that is connected to the capacitor22, and the noise filter wire24in which the first end24ais directly connected to the capacitor22and the second end24bis connected by splicing to a middle portion of the wire13of the wire harness10. According to this aspect, the wire13of the wire harness10linking the power source11and the load12is connected to the capacitor22via the noise filter wire24. Therefore, even when an installation location of the noise filter wire24has to be set to a location far from a desired path of the wire13, the noise filter14and the wire13can be connected without changing the path of the wire13. That is, regardless of the installation location of the noise filter14, the wire13can be provided along a desired path. In addition, due to the configuration that directly connects the first end24aof the noise filter wire24to the capacitor22that is housed within the housing21, there is no need to provide components such as a terminal to connect the capacitor22and the noise filter wire24inside the housing21. Thus, the noise filter14(housing21) can be made more compact and, as a result, an installation location for the noise filter14can be readily ensured. (2) Both of the end faces22aand22bof the capacitor22in the width direction, which each have a flat shape, are configured as electrode surfaces of the capacitor22, and the first end24aof the noise filter wire24is directly connected to one end face of the capacitor22in the width direction (X axis direction) by welding or soldering. This aspect yields a configuration where the noise filter14can be made even more compact. (3) The housing21includes the cylindrical outer circumferential wall31that encompasses four sides, the bottom32that seals one end of the outer circumferential wall31, and the opening33that is formed on the end of the outer circumferential wall31that is on the opposite side from the bottom32. The outer circumferential wall31is configured to include the first wall31aand the second wall31b,which are parallel to each other. In addition, the ground terminal23has the linking portion43that is provided inside the outer circumferential wall31and makes contact with the first wall31a,and the connecting portion41extending from the linking portion43extends outside the housing21along the opening direction of the opening33(height direction Z). According to this aspect, the ground terminal23can be connected to the capacitor22inside the housing21, and can also be grounded by the grounding portion42that is outside the housing21. In addition, the linking portion43of the ground terminal23makes contact with the first wall31aof the housing21, and therefore an installation posture of the ground terminal23relative to the housing21is stable. (4) The first wall31aincludes the retainer portion37that holds a reverse face side (second surface42cside) of the surface of the ground terminal23that faces the first wall31a.According to this aspect, the installation posture of the ground terminal23relative to the housing21is even more stable. As a result, when filling the potting material25, the ground terminal23can be prevented from falling inward (away from the first wall31a). (5) The fixation portion35that is fixed to the vehicle body panel P is integrally molded on the first wall31aso as to project from the outer surface of the first wall31ain a direction (inward direction Y) perpendicular to the opening direction of the opening33(height direction Z). According to this aspect, when injection molding the housing21, the fixation portion35can be integrally molded without using a slide die. In other words, the housing21with the integral fixation portion35can be molded with a die configuration having fewer components. (6) Two ribs31cthat project toward the interior of the housing21and make contact with the capacitor22are provided on the second wall31b.According to this aspect, a gap equal to or greater than a projection amount of the ribs31ccan be ensured between the capacitor22and the second wall31b.This allows the potting material25to be filled readily in a state where the capacitor22is housed in the housing21. (7) The noise filter14is provided with the potting material25that is filled into the housing21so as to cover the capacitor22, the connecting portion41of the ground terminal23, and the site of connection between the capacitor22and the first end24aof the wire24. According to this aspect, infiltration of water and the like into the housing21can be prevented and corrosion at the sites where the ground terminal23and the wire24are connected to the capacitor22can be prevented. In addition, the noise filter14according to the present embodiment is a coverless structure that has no cover member engaged and fixed on the housing21that is intended to cover the opening33, and therefore the issue of a cover member detaching when handling the wire24, for example, does not arise. (8) The housing21is provided with the regulating portion36that regulates the displacement of the ground terminal23in the width direction X. According to this aspect, in a state prior to filling in the potting material25, displacement of the ground terminal23in the width direction X can be regulated, and also positional deviation of the ground terminal23in the width direction X when filling in the potting material25can be inhibited. In addition, in the present embodiment, when the ground terminal23is installed inside the housing21through the opening33, the regulating portion36is inserted into the slit43aof the ground terminal23and thereby serves as a guide for installing the ground terminal23. Also, the regulating portion36allows width direction X positioning of the ground terminal23and the capacitor22with respect to the housing21. (9) The bent portion44that is positioned on the lower side of the height direction Z is formed on the ground terminal23. In assembling the noise filter14, the ground terminal23and the capacitor22are connected by welding or soldering prior to being housed in the housing21. At this point, the capacitor22can be held by the bent portion44of the ground terminal23and assembly workability can be improved. (10) A base end (lower end) of the regulating portion36is continuous with the bottom32. In addition, a projection length of the regulating portion36in the inward direction Y, including the retainer portion37at a forefront end, is formed to be uniform across the entire height direction Z. This allows the regulating portion36and the retainer portion37to be integrally molded without using a slide die when injection molding the housing21. (11) The linking portion43of the ground terminal23, which serves as a portion inside the housing, makes contact with the inner surface of the first wall31athat configures a portion of the outer circumferential wall31. In addition, the retainer portion37holds the ground terminal23so as to maintain the state of contact of the linking portion43with the inner surface of the first wall31a.Accordingly, the retainer portion37can inhibit the ground terminal23from separating from the first wall31a.Also, by arranging the ground terminal23so as to make contact with the first wall31a,space for arranging the capacitor22inside the housing21is more readily ensured. (12) The housing21has, on the outer surface of the first wall31a,the fixation portion35that is fixed to the vehicle body panel P. Accordingly, in a state where the housing21is fixed to the vehicle body panel P by the fixation portion35, the ground terminal23that makes contact with the inner surface of the first wall31acan be brought closer to the vehicle body panel P. (13) The linking portion43and the grounding portion42that extends from the linking portion43to outside the housing21are both plate shaped. The grounding portion42displaces toward the first wall31a,relative to the linking portion43that is in contact with the inner surface of the first wall31a.In addition, the grounding portion42is arranged so as to align with the first wall31ain the height direction Z, which is parallel to the opening direction of the opening33. Accordingly, the grounding portion42of the ground terminal23can be brought closer to the vehicle body panel P. Also, in the present embodiment, the first surface42bof the grounding portion42, which is in contact with the vehicle body panel P, and the outer surface of the first wall31aare flush to each other, and therefore the noise filter14can be brought into contact with the vehicle body panel P without rattling. Therefore, ease of installing the noise filter14on the vehicle body panel P is improved. (14) The grounding portion42includes the first surface42bthat is continuous with the surface of the linking portion43that is in contact with the inner surface of the first wall31a,and the second surface42c,which is the reverse face of the first surface42b.In addition, the retainer portion37is provided so as to extend out of the housing21past the opening33and also touches the second surface42cof the grounding portion42. According to this configuration, the retainer portion37touches the second surface42cof the grounding portion42that projects out of the housing21, and therefore the ground terminal23falling in a direction away from the first wall31acan be favorably inhibited. (15) The ground terminal23has a slit43aprovided to the linking portion43, the slit43aextending in the opening direction of the opening33. In addition, the regulating portion36that extends in the opening direction of the opening33is provided convex on the inner surface of the first wall31a,and the regulating portion36is inserted into the slit43a.According to this configuration, displacement of the ground terminal23in the width direction X, which is orthogonal to the opening direction of the opening33, can be regulated by the engagement of the regulating portion36with the slit43a.This allows positional deviation of the ground terminal23in the width direction X to be inhibited when filling in the potting material25, as described above. (16) The slit43ais formed spanning from the linking portion43to the step portion45that is between the linking portion43and the grounding portion42. In addition, the retainer portion37extends in the opening direction from one end of the regulating portion36in the opening direction of the opening33. Also, the retainer portion37extends through the slit43ato a position that touches the second surface42cof the grounding portion42. According to this configuration, the retainer portion37that touches the second surface42cof the grounding portion42can be formed in a way that elongates the regulating potion36, yielding a favorable configuration for molding the housing21. The present embodiment can be modified as follows. The present embodiment and the following modifications can be combined with each other to the extent that the combination is not technically incompatible.Each of the ribs31dof the first wall31amay be configured to be capable of making contact with the capacitor22. By doing so, a larger gap from the capacitor22can be formed on the first wall31aside, as well, and filling in the potting material25becomes easier.A retainer portion that holds the reverse face side of the surface of the ground terminal23that faces the first wall31ais not limited to the configuration of the retainer portion37in the embodiment described above, and may be modified as appropriate in response to the configuration of the ground terminal23or the housing21. For example, the retainer portion may be configured to hold, on both width direction X edges of the ground terminal23(linking portion43), the reverse face side of the surface of the ground terminal23(linking portion43) that faces the first wall31a.In such a configuration, the entire retainer portion37can be configured to be positioned within the housing21, rather than the retainer portion37being configured to project upward through the opening33and outside the housing21, as in the embodiment described above. Also, in such a configuration, the slit43aof the ground terminal23and the regulating portion36that is inserted into the slit43acan be omitted.The embodiment described above has a configuration where the potting material25is filled into the interior of the housing21. However, regardless of whether there is any potting material25, when the potting material25is omitted, a configuration is also possible where the opening33of the housing21is covered by a cover member or the like made of the same material as the housing21, for example.In the embodiment described above, the noise filter14is not limited to eliminating noise (the load12) from the defogger circuit for the rear windshield, and can be applied to vehicle devices other than the defogger circuit.In the embodiment described above, the noise filter wire24of the noise filter14is connected by splicing to the wire13of the wire harness10, but the invention is not particularly limited to this. That is, so long as the noise filter wire24is electrically connected to the wire13of the wire harness10, the invention can be modified to a configuration where the noise filter wire24is not directly connected to the wire13of the wire harness10. DESCRIPTION OF REFERENCE NUMERALS 10. . . Wire harness11. . . Power source12. . . Load13. . . Wire13a. . . Exposed portion14. . . Noise filter21. . . Housing22. . . Capacitor22a,22b. . . End face23. . . Ground terminal24. . . Noise filter wire24a. . . First end24b. . . Second end24c. . . Exposed portion25. . . Potting material31. . . Outer circumferential wall31a. . . First wall31b. . . Second wall31c,31d. . . Rib32. . . Bottom33. . . Opening34. . . Wire lead-out portion35. . . Fixation portion35a. . . Engagement portion36. . . Regulating portion37. . . Retainer portion41. . . Connecting portion42. . . Grounding portion42a. . . Bolt insertion hole42b. . . First surface42c. . . Second surface43. . . Linking portion (contact portion, portion inside housing)43a. . . Slit45. . . Step portionP . . . Vehicle body panelS . . . Splice terminalf . . . Self-resonant frequencyX . . . Width directionY . . . Inward directionZ . . . Height direction | 27,821 |
11942915 | DETAILED DESCRIPTION OF EMBODIMENTS The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings showing embodiments of the disclosure. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will fully convey the scope of the disclosure to those skilled in the art. The drawings are not necessarily drawn to scale but are configured to clearly illustrate the disclosure. The same elements in different figures of the drawings are denoted by the same reference signs. Turning now toFIGS.1A through1E, several consecutive process steps concerning the preparation of a monocrystalline piezoelectric wafer110are shown. These processing steps are the same for the fabrication of a BAW device according to the SMR and the FBAR type. The piezoelectric wafer is denoted by “A”. The wafer110is made of a monocrystalline piezoelectric material such as LiNbO3, LiTaO3or quartz. In case of a LiNbO3piezoelectric wafer the piezoelectric material may be cut along a preference direction to achieve the desired piezoelectric properties. It is possible that the the monocrystalline piezoelectric material of the piezoelectric wafer has a cut angle selected from (0°, 90°, 0°), (0°, 300°, 0°), and (0°, 120°, 0°). In this case, the Euler angles (λ, μ, θ) are defined as follows: a set of axes x, y, z, which are the crystallographic axes of the substrate, are firstly taken as a basis. The first angle, λ, specifies the amount by which the x-axis and the y-axis are rotated about the z-axis, the x-axis being rotated in the direction of the y-axis. A new set of axes x′, y′, z′ accordingly arises, where z=z′. In a further rotation, the z′-axis and the y′-axis are rotated about the x′-axis by the angle μ. In this case, the y′-axis is rotated in the direction of the z′-axis. A new set of axes x″, y″, z″ accordingly arises, where x′=x″. In a third rotation, the x″-axis and the y″-axis are rotated about the z″-axis by the angle θ. In this case, the x″-axis is rotated in the direction of the y″-axis. A third set of axes x′″, y′″, z′″ thus arises, where z″=z′″. In this case, the x′″-axis and the y′″-axis are parallel to the surface of the substrate. The z′″-axis is the normal to the surface of the substrate. The x′″-axis specifies the propagation direction of the acoustic waves. The definition is in accordance with the international standard IEC 62276, 2005-05, Annex A1. The given angles λ, μ, and θ can have tolerances of ±5° or ±10°: (0°±5°, 90°±5°, 0°±5°), (0°±10°, 90°±10°, 0°±10°), (0°±10°, 300°±10°, 0°±10°), and (0°±10°, 120°±10°, 0°±10°). According toFIG.1B, a metal electrode120is formed on the surface of the piezoelectric material110. That surface is flat where the electrode is formed and in the vicinity of the electrode. A metal layer of preferably molybdenum is deposited on the surface of wafer110. The metal electrode is structured by forming a photoresist mask and removing the excess metal by etching. A seed layer of aluminum nitride may be disposed between wafer110and electrode layer120. Electrodes of alternative metals may also be possible such as a sandwich layer of tungsten and aluminum or a layer of ruthenium, iridium or platinum or a sandwich layer of one or more of the above-mentioned metals. Turning now toFIG.1C, a layer121of an insulating material is deposited such as silicon dioxide. Silicon dioxide may be deposited by chemical vapor deposition (CVD) or a physical process such as sputtering. In the area above the metal electrode, the surface of the silicon dioxide protrudes slightly because the deposition process is conformable. Another seed layer may be deposited on the metal electrode to facilitate the forming of the insulating layer thereon. This seed layer may be aluminum nitride. Turning now toFIG.1D, the surface of the silicon dioxide layer is planarized to achieve a uniform, flat surface130of the silicon dioxide layer. Planarization may be made by a chemical mechanical polishing (CMP) process. Turning now toFIG.1E, ions are implanted into the processed wafer as shown with arrows140. Suitable ions for the implantation may be hydrogen ions (H+), helium ions (He+) or deuterium ions (D+). Other ions of low molecular range may be also be possible. The ions penetrate the silicon dioxide121and reach a certain depth as shown at dashed line141within the monocrystalline piezoelectric layer110. The penetration depth of the ions comprises substantially three portions142,143,144. In the area covered by the metal bottom electrode120, the ions penetrate at reduced depth144into the piezoelectric wafer as the metal electrode120absorbs a certain amount of kinetic energy from the ions. In the area surrounding the metal electrode120, the penetration depth142is larger than in the area covered by the electrode. Between penetration portions142,144is the transitional portion143where the penetration depth is between the levels142and144and increases from level144to level142. The depth of penetration can be determined by the acceleration voltage of the ions and the thickness of the metal electrode. The type of metal material for the bottom electrode120determines also the penetration depth so that the depth is different for electrodes of different metal material. The presence of implanted ions at the levels142,143,144damages the crystalline structure of the piezoelectric wafer to a certain extent so that a weakness is inserted in the piezoelectric material. Although the penetration depth level141is depicted with a dotted line, the depth is not exact but it can be relatively well-controlled having a defined maximum concentration as depicted by dotted line141. Turning now toFIG.2, a carrier wafer210depicted with “B” is provided. Carrier wafer210may be a substrate suitable for carrying a Bragg mirror arrangement220. Wafer210may be a monocrystalline silicon wafer. Bragg mirror220comprises an alternate sequence or stack of layers having acoustically softer and acoustically harder characteristics. For example, Bragg mirror220comprises a lowermost silicon dioxide layer223, thereon disposed a metal layer such as a tungsten layer222, thereon disposed another silicon dioxide224and thereon disposed another tungsten layer221. The top surface of the Bragg mirror220is formed of silicon dioxide layer225which has a planarized surface230. The silicon dioxide layers have low acoustic impedance or are acoustically soft. The tungsten layers have high acoustic impedance or are acoustically hard. A suitable distance between the layers or layer thickness is related to the wavelength of the resonance frequency of the resonating acoustical wave and ensures that the acoustic wave entering through the silicon dioxide surface230is reflected and does not propagate deep into the material. Between a silicon dioxide layer and a tungsten layer, a thin layer of titanium may be provided as an adhesion layer to facilitate the deposition of tungsten. Alternative materials for the layers of high acoustic impedance are also useful such as other metals or aluminum nitride. FIGS.3A through3Cshow consecutive process steps in connection with and after the bonding of prefabricated wafers A and B. As shown inFIG.3A, wafer A is flipped so that the planarized surface130of the topmost silicon dioxide layer121is opposite the planarized surface230of the silicon dioxide layer of the Bragg mirror. Both surfaces130,230are brought in contact with each other and thereby bond together. Bonding of two silicon dioxide surfaces is a known and understood process. The silicon dioxide surfaces may be cleaned before bonding. The bonding may be performed with a defined amount of pressure, preferably at elevated temperature such as in the range from 150° C. to 300° C. Turning now toFIG.3B, portion350of the monocrystalline piezoelectric wafer that is distant from the other layers of the device is removed. The splitting of portion350from the portion355is achieved by a mechanical impact. For example, a mechanical impact can be caused by the insertion of a blade to mechanically delaminate layer350from layer355. As an alternative or additionally, the wafer can be heated to generate thermal stress to enhance delamination. The delamination of portions350from355occurs along level144of the implanted ions. This process is also called ion-cut. As the penetration depth of the ions is different over the wafer, the thickness of the monocrystalline piezoelectric layer355bonded to the device is smaller or thinner in the area352of the bottom electrode120and is larger or thicker in the area353surrounding the bottom electrode120. As can be gathered fromFIG.3B, the thickness of the monocrystalline piezoelectric layer in the active area above bottom electrode120is smaller than the thickness outside the active area. The portion355of the piezoelectric layer remaining at the device remains connected to the silicon dioxide material356and carries the bottom electrode120at its bottom surface. Turning now toFIG.3C, a metal top electrode360is formed on the surface of the active area352that is in the area352where the monocrystalline piezoelectric material is recessed having reduced thickness. The top metal electrode360may include the same metal or metals as the bottom electrode120. The electrode is deposited on the surface of the piezoelectric layer and is structured to the desired shape and size. The bottom surface of the piezoelectric layer is flat and is in contact with the silicon dioxide layer356and the bottom electrode120. As is shown by the dashed rectangles370,371, there is a transitional portion of the monocrystalline piezoelectric layer355between the thin active area and the thicker surrounding area. The transitional portions370,371forming the step feature are disposed on that surface of the piezoelectric layer355that is remote from the Bragg mirror arrangement270. The increase in depth in the transitional area370has the function of a lateral energy confinement feature for the acoustic resonating wave that is established during the operation of the device between the top and bottom electrodes360,120. Such a discontinuity in the form of a rapid increase in thickness in the piezoelectric layer in the vicinity of the edge of the electrodes prevents the escape of the acoustic wave from the active area. The lateral energy confinement structures are defined by a single process step such as the implanting of ions with different depth across the piezoelectric wafer. The surface of the piezoelectric layer355in contact with the Bragg mirror is flat, whereas the opposite surface of the piezoelectric layer remote from the Bragg mirror includes the energy confinement step feature. With the use of a monocrystalline piezoelectric material high piezoelectric coupling is achieved together with low losses in the material. The strong confinement of the acoustic wave in the active area ensures that the acoustic energy remains in the active area. As a consequence, the BAW resonator device has a high quality factor and low losses. These advantages are achieved with the use of a monocrystalline piezoelectric material in combination with the above-described ion-cut technology. It is to be noted that other lateral confinement structures such as notches and protrusions at the edge of the active area are often used for BAW resonators. Such other lateral energy confinement features may also be implemented in a BAW resonator according of the present embodiment (not shown) by means of, e.g. mass layers having defined size, shape, thickness, mass and overlap/underlap areas to provide enhanced matching between the resonator area and outside thereof. These mass layers may be made of a metal, an oxide such as silicon oxide or a nitride. They require structuring including etching at the active area and the top electrode. However, such additional lateral energy confinement features become obsolete or may have smaller size and complexity than in conventional devices, because the present device already exhibits an efficient lateral energy confinement structure in the form of the step of increasing thickness of the piezoelectric layer, as shown at370,371. In this case, the additional critical steps for forming and structuring the additional energy confinement structures are few and less complex so that the surfaces of the resonator area and the top electrode are less or almost not impacted. FIGS.4and5show an embodiment for a BAW-FBAR device. Turning now toFIG.4, a carrier substrate wafer410labelled with “B” is shown that has a thin silicon dioxide layer421at its surface. Silicon dioxide421is generated by CVD or sputtering to achieve a defined thickness and surface quality. Turning now toFIG.5A, substrate wafer410is bonded to the flipped ion implanted monocrystalline piezoelectric wafer “A” fabricated along the process described in connection withFIGS.1A through1E. Turning now toFIG.5B, the topmost portion550of the ion implanted piezoelectric wafer is removed and split from the remaining bonded piezoelectric wafer portion555according to the above-described ion-cut process. The piezoelectric layer portion555exhibits a thin, recessed piezoelectric portion552at the bottom electrode120and a protruding, thicker portion551surrounding the recessed portion552and the bottom electrode portion120. Turning now toFIG.5C, the top electrode560is formed by deposition and structuring so that the top electrode560is positioned within the recessed area of the piezoelectric layer. Turning now toFIG.5D, a cavity580is formed underneath the active area and underneath the bottom electrode120. The cavity can be formed by several etching steps performed from the bottom side of the device. The etching steps remove the monocrystalline silicon wafer410and the dielectric layer121in the region of the acoustically active area to reach the surface of the bottom electrode120. The bottom electrode120is exposed to air so that no additional mirror elements are necessary. The silicon wafer410may be etched in a reactive ion etching process involving sulphur hexafluorine (SF6). The silicon dioxide layer121may be etched in a hydrogen fluoride (HF) vapor etching process. The etch process stops at the surface of the metal bottom electrode120. If a seed layer of, e.g. aluminum nitride, is provided on the bottom electrode, the etch process stops at this seed layer rather than direct on the metal electrode. The resulting BAW-FBAR device includes the lateral energy confinement structures570,571that exhibit a step in the thickness of the monocrystalline piezoelectric layer. Optionally and additionally, additional matching features (not shown) can be formed in the areas570,571, as already described in connection withFIG.3C. In another embodiment (not shown in the drawings), the penetration depth of the ions into the piezoelectric substrate material can be less in the region surrounding the active area than in the region of the active area. To achieve this effect a mask layer is formed on the piezoelectric wafer covering the region surrounding the region intended for the active area so that this mask absorbs kinetic energy from the implanted ions so that the penetration depth is smaller than in the region intended for the active area that was not covered by the mask. The mask material may be a material that retards the ions. In one embodiment the mask may be a metal. The metal may be the same metal as the material for the electrode to be formed after the mask step. For example, the mask material may be Molybdenum. Then, the mask is removed and the bottom electrode is formed in the area that was not covered by the mask. Thereafter the wafer is provided with an insulating layer such as silicon dioxide to prepare it for bonding. The process proceeds in the same way as explained in connection withFIGS.2to5D. After splitting the piezoelectric wafer material, the piezoelectric material in the region surrounding the electrode or surrounding the active area is thinner than in the active area region. In conclusion, improved BAW resonators with a high quality factor employ low loss monocrystalline piezoelectric materials that have low intrinsic losses. The transfer of thin layers of the monocrystalline piezoelectric material onto wafers forming a BAW resonator is achieved by an ion-cut technique using ion implantation. This process allows to define lateral energy confinement structures within the same single process step taking advantage of the different penetration depths of the ions into the monocrystalline piezoelectric material in the area structured with a metal electrode and in the surrounding area. The ion-cut technique employs H+/D+/He+ ions implanted into the monocrystalline piezoelectric wafer prestructured with a metal electrode and embedded in silicon dioxide. The metal electrode serves as a mask leading to lower penetration depth of the ions into the piezoelectric material when compared to areas outside the metal electrode covered with silicon dioxide only. After the splitting of the piezoelectric wafer, the piezoelectric layer is thicker outside the resonator area compared to the areas covered with the metal electrode which is the resonator area. The different piezoelectric film thicknesses in the resonator area and outside serve as a lateral barrier resulting in a lateral energy confinement of the acoustic energy within the resonator. The film thickness difference between the resonator area and outside can be adjusted by the thickness of the electrode, the electrode material and the acceleration voltage of the ions implanted in the piezoelectric material. Additional lateral energy confinement features can be optionally added by means of overlap/underlap areas to provide optimal matching between the resonator area and outside. These additional confinement features, however, need to be less complex than in conventional devices. It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the disclosure as laid down in the appended claims. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirt and substance of the disclosure may occur to the persons skilled in the art, the disclosure should be construed to include everything within the scope of the appended claims. | 18,569 |
11942916 | DETAILED DESCRIPTION OF THE EMBODIMENTS In view of the defects in the prior art, the inventor puts forward the technical solution of the present application through long-term researches and lots of practices. Next, the technical solution, an implementation process, a principle and the like will be further explained and illustrated. Embodiments of the present application provides a fabricating method of a film bulk acoustic resonator, comprising:fabricating a lower electrode on a first surface of an SOI substrate;forming piezoelectric layers on the first surface of the SOI substrate and the lower electrode;forming top electrodes on the piezoelectric layers; andprocessing an air cavity on a second surface of the SOI substrate, wherein the second surface and the first surface are oppositely arranged. In some specific embodiments, the fabricating method comprises: treating top silicon on the SOI substrate by using ion implantation so that the top silicon in a selected region is at least formed into a highly doped conductive silicon layer, and then patterning the highly doped conductive silicon layer to form the lower electrode. In some specific embodiments, the fabricating method comprises: directly fabricating a conductive film layer in the selected region of the first surface of the SOI substrate, and then patterning the conductive film layer to form the lower electrode. Preferably, the material of the conductive film layer comprises any one of graphene, molybdenum and tungsten, but is not limited thereto. In some specific embodiments, the fabricating method comprises: forming the piezoelectric layer by using vapor phase epitaxy growth or magnetron sputtering growth. Preferably, the material of the piezoelectric layer comprises AlN. Preferably, the piezoelectric layer is a AlN piezoelectric film with C-axis orientation. In some specific embodiments, the fabricating method comprises: patterning the piezoelectric layer after the piezoelectric films on the first surface of the SOI substrate and the lower electrode are fabricated. Further, a through hole communicated with the outside is formed in the partial region of the piezoelectric layer corresponding to the lower electrode. Preferably, the through hole is processed on the piezoelectric layer by using an inductive coupling plasma etching technology. Preferably, the top electrode comprises a Pt electrode. Further, the orientation of the SOI substrate is (111) or (100). Further, the air cavity is formed in the back substrate of the SOI substrate. Preferably, the depth of the air cavity is 50-1000 μm, and the area of the air cavity is 10 μm×10 μm-1 mm×1 mm. Embodiments of the present application also provide a film bulk acoustic resonator fabricated by using the fabricating method of the film bulk acoustic resonator. The air cavity type film bulk acoustic resonator provided by the present application includes the SOI (silicon-on-insulator) substrate, the piezoelectric layer and the top electrode. The resonator uses silicon (namely top silicon on the insulating layer in the SOI, the highly doped conductive silicon layer is formed through ion implantation as the lower electrode of the resonator; or a conductive layer is fabricated on the silicon on the insulating layer as the lower electrode. Meanwhile, the AlN piezoelectric film layer in C-axis orientation is grown on the lower electrode through deposition or sputtering, and the upper electrode layer is arranged on the piezoelectric layer. The structure innovation of the new FBAR (film bulk acoustic resonator) is used, so as to simplify the fabricating process of FBAR, the quality of the AlN film crystal grown through this method is high, the improvement of the device performance is facilitated, and meanwhile the frequency of the resonator is regulated by controlling the thickness of the top silicon through the position of silicon implanted oxygen isolation. The present application integrates the characteristics of low power consumption, high integration density, low cost, good radiation resistance and the like of the SOI material, which reduces the process complexity of device preparation and brings a new direction for fabrication of a future 5G communication system radio-frequency front end such as a filter, a duplexer and a multiplexer. Next, the technical solution, the implementation process, the principle and the like will be further explained and illustrated. Example 1 Referring toFIG.7andFIG.8, a film bulk acoustic resonator includes a SOI substrate7as well as a lower electrode3, a piezoelectric layer6and a top electrode1which are arranged on the first surface (front side) of the SOI substrate7in turn. An air cavity5is formed on the second surface (back side) of the SOI substrate7, the depth of the air cavity is about 200 μm and the area of the air cavity is about 150 μm×150 μm; wherein, the lower electrode3is a highly doped conductive silicon layer formed from the top silicon71of the SOI substrate7in the selected region via ion implantation, and through holes2connected with the outside are also formed in the corresponding regions of the piezoelectric layer6and the lower electrode3; the air cavity5is formed in the back substrate73of the SOI substrate7; wherein, the SOI substrate7includes the top silicon71, the back substrate73and an oxidation layer arranged between the top silicon71and the back substrate73, and the top electrode1adopts the Pt electrode. In practical application, two test G electrodes4are arranged at both sides of the film bulk acoustic resonator. Specifically, a fabricating method of a film bulk acoustic resonator can include the following steps:1) the SOI substrate is provided and ultrasonically washed with acetone and isopropanol. The substrate structure is shown inFIG.2, and the thickness of the substrate is 50 nm-1 μm;2) photoetching patterning: on the top silicon of the SOI substrate, a part of the top silicon is formed into the highly doped conductive silicon via ion implantation, and the patterned highly doped conductive silicon is used as the lower electrode; the structure of the formed device is shown inFIG.3;3) the AlN piezoelectric film with high C-axis orientation is formed on the top silicon and the lower electrode of the SOI substrate by using vapor phase epitaxy (MOVCD) or magnetron sputtering. The structure of the formed device is shown inFIG.4;4) the through hole is etched on the piezoelectric layer via ICP; the structure of the formed device is shown inFIG.5;5) the top electrode is fabricated on the piezoelectric layer by using electron beam evaporation and patterned; the top electrode is the Pt electrode, and the structure of the formed device is shown inFIG.6;6) the substrate is back etched to form the air cavity, and the structure of the formed film bulk acoustic resonator is shown inFIG.7. The fabricating method provided by embodiments of the present application adopts a Si material on the insulating layer in the SOI to epitaxially deposit the AlN film. Such the AlN film crystal fabricated on Si (111) has good crystal quality, which is greatly improved compared with that of the AlN film formed by sputtering and other methods. The FWHM of the AlN film formed by sputtering is about 3° and the AlN epitaxially formed based on the fabricating method provided by the present application is generally less than 0.5°. It should be understood that the above-mentioned example only illustrates the technical conception and characteristics of the present application, and its purpose is to enable those skilled in the art to understand the content of the present application and accordingly implement it, and can not limit the protective scope of the present application. Any equivalent changes or modifications made according to the spirit of the present application shall be covered within the protective scope of the present application. | 7,930 |
11942917 | DETAILED DESCRIPTION A film bulk acoustic resonator and a fabrication method of film bulk acoustic resonator in the present disclosure may be further described in detail with reference to the accompanying drawings and specific embodiments hereinafter. The advantages and features of the present disclosure may be more apparent according to the following description and the accompanying drawings. However, it should be noted that the concept of the technical solution of the present disclosure may be implemented in various different forms and may not be limited to specific embodiments set forth herein. The accompanying drawings may be all in simplified forms and non-precise scales and may be merely for convenience and clarity of the purpose of the embodiments of the present disclosure. The terms “first”, “second” and the like in the specification and the claims may be used to distinguish similar elements and may be not necessarily used to describe a particular order or chronological order. It should be understood that the used terms may be substituted, as appropriate. For example, the embodiments described herein of the present disclosure may be enabled to operate in other sequences than sequences described or illustrated herein. Similarly, if the method described herein comprise a series of steps, the order of the steps presented herein may not be necessarily the only order in which the steps may be performed, and some of the steps may be omitted and/or other steps, which are not described herein, may be added to the method. If components in one of the drawings are same as components in other drawings, although the components may be easily recognized in all drawings, in order to make the description of the drawings clearer, labels of all the same components may not be marked in each figure in the present specification. Various embodiments of the present disclosure provide a fabrication method of a film bulk acoustic resonator. For example, as shown inFIG.2, an exemplary fabrication method of a film bulk acoustic resonator may include the following:S01, providing a first substrate and sequentially forming a first electrode layer, a piezoelectric material layer, and a second electrode layer on the first substrate;S02, forming a support layer on the second electrode layer and forming a cavity with a top opening in the support layer, where the cavity passes through the support layer;S03, providing a second substrate and bonding the second substrate with the support layer;S04, removing the first substrate; andS05, patterning the first electrode layer, the piezoelectric material layer, and the second electrode layer to form a first electrode, a piezoelectric layer, and a second electrode. FIGS.3A-3Killustrate structural schematics corresponding to certain stages of the fabrication method of the film bulk acoustic resonator according to various embodiments of the present disclosure. The fabrication method of the film bulk acoustic resonator provided in one embodiment is described in detail with reference toFIG.2andFIGS.3A-3Khereinafter. As shown inFIG.3A, a first substrate200may first be provided. The first substrate200may be any suitable substrate known to those skilled in the art. For example, the first substrate200may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors. The first substrate may also be a multilayer structure composed of above-mentioned semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S—SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or double side polished wafers (DSP), a ceramic substrate such as alumina, a quartz or glass substrate, and the like. Optionally, as shown inFIG.3B, a release layer201may be formed on the first substrate200. The release layer201may prevent the piezoelectric stacked layer structure of the film bulk acoustic resonator formed subsequently from affecting the first substrate200; meanwhile, in the subsequent removal process of the first substrate200, the first substrate200may be separated from the piezoelectric stacked layer structure formed subsequently by the manner of etching the release layer201, which is beneficial for rapid removing the first substrate200and improving the manufacturing efficiency of the process. The release layer is made of a material including a dielectric material, a light solidification adhesive, a thermally melt adhesive, a laser release material, or a combination thereof. For example, the material of the release layer201may include silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and aluminum nitride (AlN). The release layer201may be formed by a process including chemical vapor deposition, magnetron sputtering, evaporation, and the like. In one embodiment, the first substrate200may be a silicon wafer; and the material of the release layer201may be silicon dioxide (SiO2). Next, as shown inFIG.3C, a piezoelectric stacked layer structure may be formed on the release layer201; and the piezoelectric stacked layer structure may include a first electrode layer202′, a piezoelectric material layer203′, and a second electrode layer204′, where the piezoelectric material layer203′ may be located between the first electrode layer202′ and the second electrode layer204′; and the first electrode layer202′ and the second electrode layer204′ may be disposed oppositely. The first electrode layer202′ may be used as an input electrode or an output electrode which receives or provides electrical signals such as radio frequency (RF) signals. For example, when the second electrode layer204′ is used as the input electrode, the first electrode layer202′ may be used as the output electrode; when the second electrode layer204′ is used as the output electrode, the first electrode layer202′ may be used as the input electrode; and the piezoelectric material layer203′ may convert the electrical signal inputted through the first electrode layer202′ or the second electrode layer204′ into the bulk acoustic wave. For example, the piezoelectric material layer203′ may convert the electrical signal into bulk acoustic wave through physical vibration. The first electrode layer202′ and the second electrode layer204′ may be made of any suitable conductive materials or semiconductor materials known in the existing technology, where the conductive material may be a metal material with conductive properties, such as one metal or a stacked layer of the following metals including molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd), and the like; and the semiconductor material may be, for example, Si, Ge, SiGe, SiC, SiGeC, and the like. The first electrode layer202′ and the second electrode layer204′ may be formed by a physical vapor deposition process or a chemical vapor deposition process such as magnetron sputtering, evaporation, and the like. The piezoelectric material layer203′ may also be called a piezoelectric resonance layer or a piezoelectric resonance part. The material of the piezoelectric material layer203′ may be one or a combination of piezoelectric materials with wurtzite crystal structure, including aluminum nitride (AlN), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium niobate (LiNbO3), quartz (Quartz), potassium niobate (KNbO3), lithium tantalate (LiTaO3), and the like. When the piezoelectric material layer203′ includes aluminum nitride (AlN), the piezoelectric material layer203′ may also include rare earth metals, such as at least one of scandium (Sc), erbium (Er), yttrium (Y), and lanthanum (La). Moreover, when the piezoelectric material layer203′ includes aluminum nitride (AlN), the piezoelectric material layer203′ may also include transition metals, such as at least one of zirconium (Zr), titanium (Ti), manganese (Mn), and hafnium (Hf). The piezoelectric material layer203′ may be deposited by any suitable process known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Preferably, in one embodiment, the first electrode layer202′ and the second electrode layer204′ may be made of metallic molybdenum (Mo); and the piezoelectric material layer203′ may be made of aluminum nitride (AlN). The shapes of the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ may be same or different, and the areas of the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ may be same or different. In one embodiment, the shapes and areas of the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ are same, where the shapes may all be polygonal, such as square. Before forming the first electrode layer202′, a seed layer (not shown inFIG.3C) may be formed on the release layer201. The seed layer may be formed between the release layer201and the first electrode layer202′. The seed layer may guide the crystal orientation of the first electrode layer202′ (the piezoelectric material layer203′ and the second electrode layer204′) subsequently formed, which is convenient for the piezoelectric stacked layer structure formed subsequently to grow along a specific crystal orientation, thereby ensuring the uniformity of the piezoelectric layer. The material of the seed layer may be aluminum nitride (AlN). In addition to AlN, the seed layer may also be formed by a metal or a dielectric material having a hexagonal close packed (HCP) structure. For example, the seed layer may also be formed by metal titanium (Ti). Next, as shown inFIG.3D, step S02may be performed to form a support layer206over the second electrode layer204′ and to form a cavity210with a top opening in the support layer206, where the cavity210passes through the support layer206. For example, the support layer206may be first formed by a chemical deposition process. The material of the support layer206may be, for example, one or a combination of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and aluminum nitride (AlN). The material of the support layer206in one embodiment may be silicon dioxide (SiO2). Then, the support layer206may be etched by an etching process to form an opening210′ to expose a portion of the second electrode layer204′. The etching process may be a wet etching process or a dry etching process; and the dry etching process may be preferably used. The dry etching processes may include, but may not be limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser cutting. The depth and shape of the opening210′ may depend on the depth and shape of the cavity required by the bulk acoustic resonator to be fabricated; and the thickness of the cavity in the film bulk acoustic resonator is related to the resonance frequency. Therefore, the depth of the opening210′, that is, the thickness of the support layer206, may be set according to the required resonance frequency of the film bulk acoustic resonator. Exemplarily, the depth of the opening210′ may be about 0.5 micrometer to about 3 micrometers, for example, 1 micrometer or 2 micrometers or 3 micrometers. The shape of the bottom surface of the opening210′ may be a rectangle or a polygon other than a rectangle, such as a pentagon, a hexagon, an octagon, and the like, and may also be a circle or an ellipse. The sidewall of the opening210′ may be inclined or vertical. In one embodiment, the bottom surface of the opening210′ may be a rectangle, and an obtuse angle may be formed between the side wall and the bottom surface (the shape of the longitudinal section of the opening210′ (the section along the thickness direction of the substrate) is an inverted trapezoid). In other embodiments of the present disclosure, the longitudinal cross-sectional shape of the opening210′ may also be a spherical crown with a wide top and a narrow bottom, that is, the longitudinal cross-section may be U-shaped. In one embodiment, before forming the support layer206, an etch stop layer205may be further formed on the second electrode layer204′. The material of the etch stop layer205may include, but may not be limited to, silicon nitride (Si3N4) and silicon oxynitride (SiON). The etch stop layer205has a lower etch rate compared with the support layer206formed subsequently, which may prevent over-etching when the support layer206is subsequently etched to form the opening, thereby protecting the surface of the second electrode layer204′ under the etch stop layer205from being damaged. Next, as shown inFIG.3F, step S03may be performed to provide a second substrate300and to bond the second substrate300with the support layer206. The second substrate300and the second electrode204may form the cavity210at the opening210′ of the support layer206. The second substrate300may be any suitable substrate known to those skilled in the art. For example, the second substrate300may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors. The second substrate300may also be a multilayer structure composed of such semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S—SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or double side polished wafers (DSP), a ceramic substrate such as alumina, a quartz or glass substrate, and the like. The bonding of the second substrate300and the support layer206may be implemented by thermocompression bonding. In order to increase the bonding capability between the support layer206and the second substrate300, a bonding layer may be disposed on the side of the support layer206for the thermocompression bonding. The bonding layer may be, for example, a silicon dioxide layer. In other embodiments of the present disclosure, other bonding manners may also be used for bonding. The second substrate300and the support layer206may be bonded into a single piece by dry film bonding. For example, a dry film layer may be disposed on the side of the second substrate300for bonding the dry film, and the second substrate300may be bonded to the support layer206through the dry film. After the bonding process is completed, the above-mentioned film bulk acoustic resonator after bonding may be turned over to obtain the structure shown inFIG.3G. Next, as shown inFIG.3H, step S04may be performed to remove the first substrate200. The first substrate200may be removed through a thinning process, a thermal release process, and a peeling process. For example, the release layer201may be made of a material including a dielectric material; and the release layer201and the first substrate200may be removed by the thinning process, such as mechanical polishing; the release layer201may be a light solidification adhesive, and the light solidification adhesive may be removed by a chemical agent to remove the first substrate200; the release layer may be a thermally melt adhesive, and the thermally melt adhesive may lose its viscosity through a thermal release process to remove the first substrate200. In other embodiments of the present disclosure, the first substrate200may also be removed by other manners, which are not listed in detail herein. Next, as shown inFIG.3I, step S05may be performed to pattern the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ to form a first electrode202, a piezoelectric layer203and the second electrode204. The overlapped region of the first electrode202, the piezoelectric layer203and the second electrode204along the vertical direction (i.e., the thickness direction) may be at least partially located above the cavity210. After the patterning step, the second electrode204may not only cover the opening of the cavity210but also extend and cover a portion of the support layer206around the opening210′ (for example, directly cover the surface of the etch stop layer205above the support layer206). That is, the second electrode204may not only completely enclose the cavity210but also adjoin the support layer206. The portion of the second electrode204that adjoins the support layer206may be a closed loop structure formed by surrounding the opening of the cavity210for one turn. In other embodiments of the present disclosure, the second electrode204may be coplanar with the edge of the support layer206. After patterning the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′, the shapes of the first electrode202and the piezoelectric layer203formed may be same as or different from the shape of the second electrode204; and the top-view shape may be pentagons or other polygons, such as quadrangles, hexagons, heptagons, or octagons. In one embodiment, after the patterning step, the first electrode202and the piezoelectric layer203may be completely overlapped with a same area, and the area of the second electrode204may be greater than the area of the opening of the cavity210. For example, the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ may be patterned through photolithography and etching processes. Exemplarily, the electrode pattern of the first electrode202may be defined by a photolithography process, and the shape of the first electrode202may be formed by a dry etching process or a wet etching process. Then, using the first electrode202as a mask, the piezoelectric material layer203′ may be etched using a dry etching process or a wet etching process, as shown inFIG.3I. Next, the electrode pattern of the second electrode204may be defined by a photolithography process, and the shape of the second electrode204may be formed by a dry etching process or a wet etching process, as shown inFIG.3J. The patterned first electrode202, the piezoelectric layer203, and the second electrode204may have an overlapped region along the vertical direction. Therefore, after the first electrode202and the second electrode204are applied with a voltage, an electric field may be formed between such two electrodes, and the electric field may facilitate the piezoelectric layer203to generate mechanical vibrations. Moreover, the overlapped region may be at least partially located above the cavity210, and a portion of the second electrode204above the cavity210may be exposed. That is, the overlapped region, along the thickness direction, of the first electrode202, the piezoelectric layer203, and the second electrode204located above the cavity210may be an active working region (effective working region) of the bulk acoustic resonator. Such arrangement may relatively reduce the dissipation of acoustic wave energy and improve the quality factor of the bulk acoustic resonator. Moreover, after patterning the first electrode layer202′, the piezoelectric material layer203′, and the second electrode layer204′ to form the first electrode202, the piezoelectric layer203, and the second electrode204, the method for fabricating the film bulk acoustic resonator provided by the present disclosure may further include forming a passivation layer207. The passivation layer207may cover the first electrode202, the piezoelectric layer203, and the second electrode204, and further cover the support layer206. Passivation layer openings may be formed in the passivation layer207above the support layer206and in the passivation layer207above the second electrode204, respectively, where a part of the passivation layer openings may expose the second electrode204, and another part of the passivation layer openings may expose the second electrode202. A first soldering pad208aand a second soldering pad208b,which are electrically connected to the first electrode202and the second electrode204, may be respectively formed at the passivation layer openings, as shown inFIG.3K. For example, the passivation layer207may be formed by chemical deposition or thermal oxidation. The material of the passivation layer207may be silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), and the like. Then, the passivation layer207may be etched to form the passivation layer openings on the first electrode202and the second electrode204as electrode lead-out windows. Finally, a conductive material such as metal may be filled in the passivation layer openings to form the first soldering pad208aand the second soldering pad208bwhich are electrically connected to the first electrode202and the second electrode204, respectively, thereby further realizing the connection between the electrodes of the film bulk acoustic resonator and an external power supply device. The material of each of the first soldering pad208aand the second soldering pad208bmay be a composite structure formed by one or a combination of aluminum (Al), copper (Cu), gold (Au), titanium (Ti), nickel (Ni), silver (Ag), tungsten (W) and the like. Preferably, in one embodiment, the first soldering pad208aand the second soldering pad208bmay be aluminum soldering pads; and the first soldering pad208aand the second soldering pad208bmay be located on two sides of the cavity210, respectively. In the above-mentioned etching steps, the etching manners may include, but may not be limited to, a wet etching technology, an inductively coupled plasma (ICP) etching process, a reactive ion etching (RIE) process, and the like. The deposition manners may include, but may not be limited to, a chemical vapor deposition process, a magnetron sputtering process, an electrochemical deposition process, an atomic layer deposition (ALD) process, a molecular beam epitaxy (MBE) process, and the like. The embodiments of the present disclosure also provide a film bulk acoustic resonator, which is fabricated by using the above-mentioned fabrication method of the film bulk acoustic resonator. As shown inFIG.3K, the film bulk acoustic resonator may include:the second substrate300;the support layer206disposed on the second substrate300, where the support layer206may be bonded to the second substrate300, and the cavity210, passing through the support layer206, may be disposed in the support layer206; andthe second electrode204, the piezoelectric layer203, and the first electrode202sequentially disposed on the support layer206. The cavity210may be disposed in the support layer206below the overlapped region, along the thickness direction, of the first electrode202, the piezoelectric layer203, and the second electrode204. The second electrode204may cover the opening of the cavity210and a portion of the support layer206around the opening. The portion of the second electrode204that adjoins the support layer206may a closed loop structure formed by surrounding the opening of the cavity210for one turn. In other embodiments of the present disclosure, the second electrode204may be coplanar with the edge of the support layer206. The second substrate300may be any suitable substrate known to those skilled in the art. For example, the second substrate300may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium (SiGeC), indium arsenide (InAs), Gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors. The second substrate300may be a multilayer structure composed of such semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S—SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or double side polished wafers (DSP), a ceramic substrate such as alumina, a quartz or glass substrate, and the like. In one embodiment, the first electrode202and the second electrode204may be made of metal molybdenum (Mo), and the piezoelectric layer203may be made of aluminum nitride (AlN). The material of the support layer206may be, for example, one or a combination of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) and aluminum nitride (AlN). Preferably, the material of the support layer206may be silicon dioxide (SiO2). Optionally, the areas of the first electrode202and the piezoelectric layer203may be equal and completely overlapped, and the area of the second electrode204may be greater than the area of the opening of the cavity210. The overlapped region, along the thickness direction, of the first electrode202, the piezoelectric layer203, and the second electrode204located above the cavity210may be an active working region (effective working region) of the bulk acoustic resonator. Such arrangement may relatively reduce the dissipation of acoustic wave energy and improve the quality factor of the bulk acoustic resonator. The support layer206may be bonded to the second substrate300by a thermocompression bonding manner or a dry film bonding manner. Using the thermocompression bonding manner, a bonding layer may be disposed on a side of the support layer for bonding with the second substrate by the thermocompression bonding. Using the dry film bonding manner, a dry film layer may be disposed on a side of the second substrate for bonding with the support layer by the dry film bonding. Optionally, the etch stop layer205may be disposed between the second electrode204and the support layer206. Furthermore, the etch stop layer205and the second electrode204, having a same shape and a same area, may be completely overlapped with each other. The material of the etch stop layer205may include, but may not be limited to, silicon nitride (Si3N4) and silicon oxynitride (SiON). Optionally, the film bulk acoustic resonator may further include the passivation layer207. The passivation layer207may cover the first electrode202, the piezoelectric layer203, the second electrode204, and the support layer206. Optionally, passivation layer openings, different from the cavity210, may be respectively formed in the passivation layer207above the support layer206and in the passivation layer207above the second electrode204. The film bulk acoustic resonator may further include at least two soldering pads. The soldering pads, disposed at the passivation layer207, may be electrically connected to the first electrode202and the second electrode204respectively through the openings of the passivation layer207. For example, the first soldering pad208amay be electrically connected to the first electrode202, and the second soldering pad208bmay be electrically connected to the second electrode204. Preferably, the first soldering pad208aand the second soldering pad208bmay be located on two sides of the cavity210, respectively. From the above-mentioned embodiments, it can be seen that the technical solutions provided by the present disclosure may achieve at least the following beneficial effects. The present disclosure provides the film bulk acoustic resonator and its fabrication method. The first electrode layer, the piezoelectric material layer, and the second electrode layer may be sequentially formed on the first substrate. Then, the support layer may be formed on the second electrode layer and the cavity with the top opening may be formed in the support layer, where the cavity passes through the support layer. Next, the second substrate may be bonded with the support layer, and the first substrate may be removed; and the first electrode layer, the piezoelectric material layer, and the second electrode layer may be patterned to form the first electrode, the piezoelectric layer, and the second electrode, such that the overlapped region of the first electrode, the piezoelectric layer, and the second electrode along the thickness direction may be directly above the cavity. The cavity structure of the film bulk acoustic filter may be realized through the etching support layer and the bonding process, which avoids the influence of slight fluctuations between different media caused by the CMP process on the uniformity of the piezoelectric layer and avoids the influence on the performance of the film bulk acoustic wave filter due to incompletely dissolving the sacrificial layer. It should be noted that each embodiment in present specification may be described in a related manner, and the same or similar parts between the various embodiments may be referred to each other. Each embodiment may focus on the differences from other embodiments. Particularly, as for the structural embodiments, since it is basically similar to the method embodiments, the description may be relatively simple, and related parts may refer to the partial description of the method embodiments. The above-mentioned description may merely the description of preferred embodiments of the present disclosure and may not limit the scope of the present disclosure in any way. Any changes or modifications made by those skilled in the art in the field of the present disclosure according to the above-mentioned description shall fall within the protection scope of the claims. | 29,639 |
11942918 | DETAILED DESCRIPTION The text below provides a detailed description of the present disclosure in conjunction with specific embodiments illustrated in the attached drawings. However, these embodiments do not limit the present disclosure. The scope of protection for the present disclosure covers changes made to the structure, method, or function by persons having ordinary skill in the art on the basis of these embodiments. To facilitate the presentation of the drawings in the present disclosure, the sizes of certain structures or portions may be enlarged relative to other structures or portions. Therefore, the drawings in the present disclosure are only for the purpose of illustrating the basic structure of the subject matter of the present disclosure. The same numbers in different drawings represent the same or similar elements unless otherwise represented. Additionally, terms in the text indicating relative spatial position, such as “top,” “bottom,” “upper,” “lower,” “above,” “below,” and so forth, are used for explanatory purposes in describing the relationship between a unit or feature depicted in a drawing and another unit or feature therein. Terms indicating relative spatial position may refer to positions other than those depicted in the drawings when a device is being used or operated. For example, if a device shown in a drawing is flipped over, a unit which is described as being positioned “below” or “under” another unit or feature will be located “above” the other unit or feature. Therefore, the illustrative term “below” may include positions both above and below. A device may be oriented in other ways (e.g., rotated degrees or facing another direction), and descriptive terms that appear in the text and are related to space should be interpreted accordingly. When a component or layer is said to be “above” another member or layer or “connected to” another member or layer, it may be directly above the other member or layer or directly connected to the other member or layer, or there may be an intermediate component or layer. FIG.1is a top view of a temperature compensated-surface acoustic wave (TC-SAW) device. As illustrated inFIG.1, the TC-SAW device may include an interdigital transducer (IDT)130having a plurality of interdigital electrodes131and small pieces of metal blocks300(also referred to as “Hammer Head”) are superimposed on both ends of each interdigital electrode131to form protruding structures to suppress clutter and ensure excellent filter performance. Clutter suppression works best when the edges of metal blocks300and the edges of interdigital electrodes131are perfectly aligned. Conventionally, protruding metal blocks300are formed on the ends of interdigital electrodes131through a lift-off process. During the lift-off process, a photolithography process (coating photoresist, exposure, and development) is performed on a substrate formed with interdigital electrodes131to obtain openings in the photoresist that expose the ends of interdigital electrodes131. Then, a metal layer is plated on substrate by metal evaporation, and the photoresist and the metal attached to the photoresist are stripped, leaving only the metal plated on the ends of interdigital electrodes131, thereby obtaining protruding metal blocks300at the ends of interdigital electrodes131. Therefore, protruding metal blocks300and interdigital electrodes131are not formed from the same integral material, but from two independent material layers. The photolithography process might cause a deviation in the alignment of metal blocks300with interdigital electrodes131, or a deviation in the line widths of metal blocks300. As a result, protruding metal blocks300may not be completely vertically aligned with the edges of interdigital electrodes131. FIGS.2A-2Dare sectional views of the TC-SAW device ofFIG.1, along line a-a′ ofFIG.1, in different alignment situations. As illustrated inFIG.2A, in an ideal situation, protruding metal blocks300and interdigital electrodes131are completely vertically aligned. As illustrated inFIG.2B, protruding metal block300and interdigital electrodes131are not aligned in the vertical direction, and protruding metal blocks300are off to one side of the corresponding interdigital electrodes131. As illustrated inFIG.2C, the width of protruding metal blocks300is narrower than the width of interdigital electrodes131. As illustrated inFIG.2D, the width of protruding metal blocks300are wider than the width of interdigital electrodes131. FIGS.3A and3Bare sectional views of the TC-SAW device ofFIG.1, along line b-b′ ofFIG.1, in different alignment situations. As illustrated inFIG.3A, in an ideal situation, protruding metal blocks300and interdigital electrodes131are completely vertically aligned. As illustrated inFIG.3B, protruding metal blocks300and interdigital electrodes131are not aligned in the vertical direction, and protruding metal blocks300are off to one side of the corresponding interdigital electrodes131. The misalignment between the metal blocks and the interdigital electrodes may bring about differences in the effect of clutter suppression, which affects performance and individual consistency of the filter of the TC-SAW device. Embodiments of the present disclosure provide a fabrication method for a TC-SAW. The fabrication process uses a precise etching back method to partially etch central portions of the interdigital electrodes, so that end portions of the interdigital electrodes are thicker than the central portions, thereby forming protruding structures at the end portions of the interdigital electrodes. As a result, the protruding structures and the interdigital electrodes are formed from an integral material layer without mutual interfaces, and the protruding structures and the interdigital electrodes may be completely vertically aligned. In order to ensure accuracy and efficiency of the etching back process, a protective layer (also referred to as a “SiO2 etch stop layer”) is deposited on the surface of the interdigital electrodes, so that a temperature compensation layer (SiO2) on the central portions of interdigital electrodes are first etched to expose the protective layer on the central portions of interdigital electrodes of the interdigital electrodes, and then precise ion beam etching (IBE) or a similar process is performed to accurately etch away the protective layer on the central portions of the interdigital electrodes and a part of the central portions of the interdigital electrodes using self-alignment. In this way, the interdigital electrodes with uniform thickness that meet a target thickness requirement are preserved. FIG.4Ais a top view of a TC-SAW device1000, according to an embodiment of the present disclosure.FIG.4Bis a sectional view of TC-SAW device1000, along line A-A′ ofFIG.4A.FIG.4Cis a sectional view of TC-SAW device1000, along line B-B′ ofFIG.4A. As illustrated inFIGS.4A-4C, TC-SAW device1000may include a substrate100, an interdigital transducer (IDT)130, a protective layer140, a first temperature compensation layer150, a second temperature compensation layer160, and a passivation layer190. TC-SAW device1000may further include a first IDT via170A, a second IDT via170B, a first pad metal layer180A, a second pad metal layer180B, a first pad contact window200A, and a second pad contact window200B. Substrate100may be formed of a piezoelectric material, for example, lithium niobate or lithium tantalate. IDT130includes lead-out portions and arrays of interdigital electrodes, such as an array of first interdigital electrodes131A, an array of second interdigital electrodes131B, a first lead-out portion132A connected to the array of first interdigital electrodes131A, and a second lead-out portion132B connected to the array of second interdigital electrodes131B. First interdigital electrodes131A are interleaved with, and parallel to, second interdigital electrodes131B. In the descriptions below, first interdigital electrodes131A and second interdigital electrodes131B are also collectively referred to as “interdigital electrodes131,” and first lead-out portion132A and second lead-out portion132B are also collectively referred to as “lead-out portions132.” Interdigital electrodes131include end portions136disposed at opposite end regions of interdigital electrodes131, central portions137disposed between end portions136, and intermediate portions138each disposed between one of end portions136and a corresponding one of lead-out portions132. For example, as illustrated inFIG.4A, each first interdigital electrode131A includes, from right (a tip of first interdigital electrode131A) to left (the portion connected to first lead-out portion132A), a first end portion136A-1, a central portion137A, a second end portion136A-2, and an intermediate portion138A; and each second interdigital electrode131B includes, from left (a tip of second interdigital electrode131B) to right (the portion connected to second lead-out portion132B), a first end portion136B-1, a central portion137B, a second end portion136B-2, and an intermediate portion138B. First end portions136A-1of first interdigital electrodes131A are aligned with second end portions136B-2of second interdigital electrodes131B to form a first row extending in a direction perpendicular to an extending direction of interdigital electrodes131; first end portions136B-1of second interdigital electrodes131B are aligned with second end portions136A-2of first interdigital electrodes131A to form a second row extending in the direction perpendicular to the extending direction of interdigital electrodes131. A thickness of each interdigital electrode131at end portions136is greater than a thickness of interdigital electrodes131at central portion137, thereby forming protruding structures133at end portions136of interdigital electrodes131. Protruding structures133and interdigital electrodes131may be formed from the same material without mutual interfaces, and protruding structures133and interdigital electrodes131are vertically aligned. Although protruding structures133and interdigital electrodes131illustrated inFIG.4Ahave different patterns, protruding structures133and interdigital electrodes131are formed from the same material and are illustrate inFIGS.4B and4Cto have the same patterns. First lead-out portion132A and second lead-out portion132B are located outside of terminal parts of first interdigital electrodes131A and second interdigital electrodes131B, respectively. First lead-out portion132A and second lead-out portion132B serve as external electrical connection parts for the corresponding of first interdigital electrodes131A and second interdigital electrodes131B. Protective layer140covers end portions136of interdigital electrodes131, including top and side surfaces of protruding structures133formed at end portions136of interdigital electrodes131. Protective layer140also covers portions of first lead-out portion132A and second lead-out portion1328. As will be described in more details later, the portions of the protective layer140covering central portions137and intermediate portions138of interdigital electrodes131are removed during the fabrication process of TC-SAW device1000, and therefore central portions137and intermediate portions138of interdigital electrodes131are not covered with protective layer140. First temperature compensation layer150covers the surface of protective layer140that covers end portions136of interdigital electrodes131and covers portions of first lead-out portion132A and second lead-out portion1328. As will be described in more details later, the portions of first temperature compensation layer150covering central portions137and intermediate portions138of interdigital electrodes131are removed during the fabrication process of TC-SAW device1000, and therefore central portions137and intermediate portions138of interdigital electrodes131are not covered with first temperature compensation layer150. Second temperature compensation layer160covering the surface of central portions137and intermediate portions138of interdigital electrodes131, and the surface of first temperature compensation layer150. First IDT via170A and second IDT via1708are formed by etching selected portions of second temperature compensation layer160, first temperature compensation layer150, and protective layer140, to expose surfaces of first and second interdigital lead-out portions132A and132B at the bottom. First pad metal layer180A and second pad metal layer180B are respectively in first IDT via170A and second IDT via170B, respectively, and are electrically connected to first and second interdigital lead-out portions132A and132B through first IDT via170A and second IDT via170B, respectively. Passivation layer190covers the surface of second temperature compensation layer160and first and second pad metal layers180A and180B. As illustrated inFIGS.4B and4C, protective layer140, first temperature compensation layer150, second temperature compensation layer160are formed between passivation layer190and end portions136of interdigital electrodes131, while only second temperature compensation layer160is formed between passivation layer190and central portions137and intermediate portions138of interdigital electrodes131. First pad contact window200A and second pad contact window200B are formed by etching passivation layer190to expose first and second pad metal layers180A and180B at the bottom, respectively. First and second pad contact windows200A and200B serve as windows for external electrical connection. FIG.5is a flow chart of a process1100of fabricating TC-SAW device1000ofFIGS.4A-4C, according to an embodiment of the present disclosure.FIGS.6A-6Kare cross-sectional views of structures formed in process1100, along line A-A′ ofFIG.4A, according to an embodiment of the present disclosure. As illustrated inFIG.6A, in step S0, substrate100is obtained. Substrate100may be formed of a piezoelectric material, for example, lithium niobate or lithium tantalate. As illustrated inFIG.6B, in step S1, IDT130is formed on substrate100. IDT130may by formed by using a lift-off process. IDT130may be formed of a metal, for example, Ti, Cr, Ag, Cu, Mo, Pt, W, Al, or a stacked combination of two or more of those metal materials. As described above with reference toFIG.4A, IDT130includes an array of first interdigital electrodes131A, an array of second interdigital electrodes131B, a first lead-out portion132A connected to the array of first interdigital electrodes131A, and a second lead-out portion132B connected to the array of second interdigital electrodes131B. Interdigital electrodes131include end portions136disposed at opposite end regions of interdigital electrodes131, central portions137disposed between end portions136, and intermediate portions138each disposed between one of end portions136and a corresponding one of lead-out portions132. As illustrated inFIG.6C, in step S2, protective layer140is deposited on the structure ofFIG.6B. Protective layer140covers all sides and surfaces of interdigital electrode131. Protective layer140may be formed of silicon nitride (SiN), aluminum nitride (AlN), gallium nitride (GaN), or amorphous silicon (α-Si). As illustrated inFIG.6D, in step S3, first temperature compensation layer150is deposited on the structure ofFIG.6C, and a top surface of the deposited first temperature compensation layer150is planarized by, for example, chemical mechanical polishing (CMP) planarization. First temperature compensation layer150covers all of the surfaces of protective layer140. First temperature compensation layer150may be formed of SiO2. As illustrated inFIG.6E, in step S4, first temperature compensation layer150is patterned by a photolithography processing and etching to form openings151that expose portions of protective layer140that are disposed above central portions137and intermediate portions138of interdigital electrodes131. After etching first temperature compensation layer150, a photoresist layer used for the photolithography process is removed. Protective layer140functions as an etching stop layer when etching first temperature compensation layer150. When protective layer140is formed of SiN, AlN, GaN, α-Si, or a similar material, and first temperature compensation layer150is formed from SiO2, a high etching selectivity ratio may be achieved. Therefore, protective layer140may be made relatively thin while still functions properly as the etching stop layer for first temperature compensation layer150. As illustrated inFIG.6F, in step S5, using first temperature compensation layer150as a hard mask, the portions of protective layer140exposed by openings151of first temperature compensation layer150, and top layers of central portions137and intermediate portions138of interdigital electrodes131disposed under the portions of protective layer140exposed by openings151of first temperature compensation layer150, are removed by using a precise etching process, for example, ion beam etching (IBE). As a result, a thickness of central portions137of interdigital electrodes131is accurately controlled to be at a target thickness. There is still a sufficiently thick first temperature compensation layer150remaining on the surface of end portions136of interdigital electrodes131after etching, so as to prevent end portions136of interdigital electrodes131from being damaged by etching. In some embodiments, the thickness of multiple points at central portions137of interdigital electrodes131may be measured to generate a wafer map in terms of thickness. According to the wafer map in terms of thickness, a thickness trimming process such as the IBE process may be performed to realize fine etching, so as to obtain a uniform and consistent target thickness on central portions137of interdigital electrodes131. After the etching process, central portion137of interdigital electrodes131is thinner than end portions136of interdigital electrodes131. In other words, end portions136of interdigital electrodes131protrude upwards compared to central portions137of interdigital electrodes131, thereby forming protruding structures133at end portions136of interdigital electrodes131. Protruding structures133at end portions136of interdigital electrodes131are formed of the same material as the other portions (i.e., central portions137and intermediate portions138) of interdigital electrodes131. There is no interface between protruding structures133and interdigital electrodes131. Protruding structures133are completely vertically aligned with interdigital electrodes131. As illustrated inFIG.6G, in step S6, second temperature compensation layer160is deposited on the structure ofFIG.6F, and a top surface of the deposited second temperature compensation layer160is planarized by, for example, CMP planarization. Second temperature compensation layer160covers the surface of first temperature compensation layer150and the surface of the portions of interdigital electrodes131exposed by openings151of first temperature compensation layer150, i.e., central portions137and intermediate portions138of interdigital electrodes131. Second temperature compensation layer160may be a single layer of SiO2, or a stacked combination of a thin layer of SiN, AlN, amorphous silicon, or GaN, and a thick layer of SiO2. The thin layer of SiN, AlN, amorphous silicon, or GaN may function as a protective layer to prevent the exposed portions of interdigital electrodes131, i.e., central portions137and intermediate portions138of interdigital electrodes131, from being oxidized when the thick layer of SiO2is deposited. As illustrated inFIG.6H, in step S7, second temperature compensation layer160, first temperature compensation layer150, and protective layer140are selectively etched to form first IDT via170A and second IDT via1708that expose a surface of first lead-out portion132A and a surface of second lead-out portion1328, respectively. As illustrated inFIG.6I, in step S8, first pad metal layer180A and second pad metal layer1808are formed in first IDT via170A and second IDT via1708, respectively, to electrically connect to first lead-out portion132A and second lead-out portion1328, respectively. First pad metal layer180A and second pad metal layer1808may be formed by a lift-off process, and may be formed of a metal material such as Ti, Cr, Al, Cu, Ni, Ag, Au, or another metal material, or a stacked combination of two or more of those materials. As illustrated inFIG.6J, in step S9, passivation layer190is deposited on the structure ofFIG.6Ito protect first and second pad metal layers180A and1808, and to function as a frequency adjustment layer for the filter. Passivation layer190may be formed of SiN, AlN, amorphous silicon, GaN, or another insulating material, or a stacked combination of two of more of those materials. As illustrated inFIG.6K, in step S10, passivation layer190is selectively etched to form first pad contact window200A and second pad contact window200B for external electrical connection. After step S10, the entire fabrication process is completed. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims | 21,490 |
11942919 | DETAILED DESCRIPTION Referring now toFIG.3, there is illustrated a stack10including a substrate12having a first layer14formed on a substrate surface16. The substrate12can possess material characteristics, such as a particular lattice constant aSiC. The substrate12can include a silicon carbide (SiC) material, silicon, sapphire, GaN, or other suitable epitaxial template substrate upon which the first layer14can be nucleated. The substrate12can be single crystal material. The first layer14can possess material characteristics different from the substrate12, such as a lattice constant aAlN, or a coefficient of thermal expansion CTE αAlN. The first layer14can be an aluminum nitride (AlN) material. The first layer14can be an epitaxial single-crystal film. The first layer14can be a nucleation layer. A second layer18can be formed on the first layer14opposite the substrate12. The second layer18can possess material characteristics that are different from the substrate12and the first layer14, such as a lattice constant of aScAlNand/or CTE αScAlN. The second layer18can be an epitaxial single-crystal film. The second layer18can be a scandium aluminum nitride (ScAlN) material. A third layer20can be formed on the second layer18opposite the first layer14. The third layer20can possess the same material characteristics of the first layer14, such as a lattice constant aAlNand/or CTE αAlN. The third layer20can be an epitaxial single-crystal film. The third layer20can be an aluminum nitride (AlN) material. In an exemplary embodiment, the third layer20can be a scandium aluminum nitride (ScAlN) composition that includes a composition with a lower scandium concentration than the second layer. For example, the second layer18can include a composition of Sc0.30Al0.70N and the third layer20can be a composition of Sc0.05Al0.95N. The third layer20can include a layer that is a thicker Sc0.05A10.95N layer than if AlN was used as it has a closer lattice match to Sc0.30Al0.70N than AlN. The goal is to balance the stress on either side of the second layer18that comprises Sc0.30Al0.70N. The compositions and thicknesses in the layers14,18and20can be configured to also correct for the CTE differences based on thermal growth from process temperatures. After the first layer14and the second layer18are formed on the substrate12, a resultant compressive force will act on the stack10. As explained above, the mismatch of the material characteristics of the substrate12, the first layer14and the second layer18will impart compressive forces on the stack10. Particularly, when growing epitaxial single-crystal films, large interfacial strains can occur due to the difference in lattice parameter and coefficient of thermal expansion between the heteroepitaxial materials. If the difference is small enough and if the films are below the relaxation critical thickness, a coherent (or semi-coherent) interface22can form where the crystal structure is distorted at the interface22to allow for bond matching. The first layer14comprising AlN has a smaller lattice parameter than the second layer18comprising ScAlN. When the substrate12is released from the first layer14, the AlN/ScAlN bilayer24bows or distorts in an attempt to relieve the interfacial strain25. When the bilayer24is bowed, the second layer18upper surface26becomes strained in tension and the lower surface28of the first layer14AlN becomes strained in compression. The third layer20, after being formed on the second layer18, having the same material properties as the first layer14, will impart counter bowing forces on the second layer18opposite to the forces imparted by the first layer14on the second layer18. If the third layer20includes a similar material but has a different thickness or a different concentration of materials in the composition, the third layer20can impart counter forces on the second layer18opposite to the forces imparted by the first layer14on the second layer18. When the substrate12is released from the membrane30, the bowing forces imparted by the first layer12will equal the bowing forces imparted by the third layer20, resulting in a strain/stress balance on the membrane30. The unique layering disclosed leverages the epitaxial nature of the growth of the materials in the layers14,18,20, and by mirroring the strain on either side of the second layer18of ScAlN, the impact of the difference between lattice parameter (aAlNand aScAlN) as well as CTE (αAlNand αScAlN) can be eliminated. An equal but opposite strain gradient on the surface32is imparted by the third layer20in order to match the lower ScAlN/AlN interface22. Therefore, when the substrate12is removed, the suspended membrane30remains neutrally stressed and does not crack, enabling further processing and device fabrication. With the improvement of the additional third layer20on the stack10to counterbalance the first layer14, upon release, the resonator membrane30will not crack or deform. It is contemplated that a range of net stress values can be obtained, where the residual stress will not cause sufficient deformation to crack the membrane30. Referring also toFIG.4a process map is shown. The process100generally describes the steps used to prevent the resonator membrane30from deforming during production. The process100includes the step110of providing a substrate. The next step112includes forming a first layer on the substrate. The first layer can be epitaxially grown. In an exemplary embodiment, the first layer can be AlN material. The next step114includes forming a second layer on the first layer. The second layer can be epitaxial. The second layer can be a ScAlN material. The next step116includes forming a third layer on the second layer. The third layer can be epitaxial. The third layer can be the same material as the first layer. The third layer can be AlN. The resultant stack results in the first layer and the third layer having equal but opposite strain gradient with respect to the second layer in the stack. The next step includes removing the substrate from the first layer. The substrate can be etched to allow for electrical contact with electrodes. With the substrate removed, the membrane in the stack is suspended, however the stack will not deform due to strain gradient built up from the epitaxial growth of the first and second layers in the substrate. The third layer provides a balancing force to match the first and second layer forces formed during layer formation. Referring also toFIG.5, a schematic diagram illustrates the net stress state relationship between the layers14,18,20. The net stress state can be understood as a set of force balances between the layers14,18,20. The forces on the layers14,18,20can be balanced such that there is no cracking in the membrane30. The diagram atFIG.5illustrates that there is a region of force balancing on either side of a value of zero. The diagram shows a region near zero which is less than the critical strain level for cracking (in either the compressive or tensile direction). Membranes with force balances within this region near zero are termed neutrally stressed. The closer to zero the forces can be balanced, the more processing tolerance and resonator durability will result. The forces do not have to balance at exactly zero net force, instead there are some forces that can exist on either side of the zero balanced value. There will be a value beyond the balance that results in cracking. The absolute numbers in the balance will depend on the combination of material compositions and thicknesses in the layers14,18,20. The disclosed process includes the concept of manipulating the stain/stress formed during production to avoid the deformation of the membrane after removal of the substrate. It is contemplated that a variety of materials can be utilized as substrates. However utilizing different substrate materials, may change the initial stress conditions between the layers14,16,18and the substrate12. For instance for SiC substrate, there will be an initial compressive force on the epi-layers (as SiC has a smaller lattice parameter). The opposite would happen for Silicon (as it has a larger lattice parameter). However, in either case, the membrane stress balance problem and solution described herein remains unchanged. The membrane stack can be utilized with a resonator, such as a bulk acoustic wave (BAW) resonator. A technical advantage of the exemplary disclosure includes a neutrally stressed released membrane for use as a resonator. Another technical advantage of the exemplary epitaxial single crystal AlN/ScAlN/AlN membrane includes inhibition of the released membrane from bowing and subsequently prevents cracking. Another technical advantage of the exemplary epitaxial single crystal AlN/ScAlN/AlN membrane includes introduction of a strain matching surface layer (third layer) to compensate for the strain present at the interface between the nucleation layer (first layer) and the second layer. Another technical advantage of the exemplary process includes applying the disclosed process to other combinations of materials with respect to Rare-Earth III-Nitride (IIIA, IIIB, Lanthanides, for example: AlGaN, InGaN, ScAlN, YAlN, and the like) multilayer membrane structures. Another technical advantage of the exemplary process includes a suspended membrane free of deformation allowing a free standing device. Another technical advantage of the exemplary process includes mirroring an interface between the first epitaxial layer and the second epitaxial layer and an interface between the third epitaxial layer and the second epitaxial layer. Another technical advantage of the exemplary process results in the first interfacial strain equaling the second interfacial strain in magnitude on opposite sides of the second epitaxial layer. Another technical advantage of the exemplary process results in the multilayer membrane structure comprising a neutrally stressed membrane responsive to release of the substrate. There has been provided a strain compensated heterostructures and process. While the strain compensated heterostructures and process has been described in the context of specific embodiments thereof, other unforeseen alternatives, modifications, and variations may become apparent to those skilled in the art having read the foregoing description. Accordingly, it is intended to embrace those alternatives, modifications, and variations which fall within the broad scope of the appended claims. | 10,512 |
11942920 | DETAILED DESCRIPTION By way of introduction, the present disclosure relates to acoustic delay lines (ADLs) with interdigital transducers (IDTs) on a piezoelectric thin film, an apparatus, and a full-duplex radio that include disclosed ADLs. Lithium niobate (LiNbO3) thin films can be excellent platforms for implementing low-loss ADLs based on unidirectional transducers. The reason lies in the high acoustic reflections caused by a mechanical loading of electrodes on the LiNbO3thin film. Low-loss ADLs can be based on shear-horizontal waves in thin-film LiNbO3. These propagation modes are known for their high electromechanical coupling, thus producing devices (e.g., ADLs) with large bandwidths. Such ADLs can be based on their acoustic vibration modes. Lamb modes (S0, A0, S1, A1, . . . ) and shear modes (SH0, SH1, SH2 . . . ) can both be used. The expansion of wireless interconnectivity among autonomous sensors or mobile devices seeks analog signal processing functions with low loss, small form factors, and low or zero power consumption at radio frequencies (RF). In this context, acoustic devices may constitute an excellent chip-scale and low-loss platform, in which electromagnetic (EM) waves can be converted into the acoustic domain for processing, and can subsequently be converted back to the EM domain for interfacing with the rest of the system. In the RF domain, the propagation of acoustic waves in some piezoelectric thin films can exhibit much lower loss than the propagation of EM waves in planar waveguide structures (e.g., microstrips). Moreover, given the low phase velocities, typically below 10000 m/s, and the low propagation loss of acoustic waves, high-performance waveguide structures can be designed with sizes comparable to the acoustic wavelengths (e.g., on the order of tens of micrometers) for RF applications. As a result of the above-mentioned benefits in the acoustic domain, wave phenomena can be exploited for signal processing functions (e.g., time delay or transversal filtering) in a very small form factor that otherwise may not be accessible in the EM domain at RF. The study of signal processing functions in the acoustic domain could be motivated by radar system implementations. Surface acoustic waveguide structures, namely ADLs can be built on piezoelectric bulk substrates, with which the electromechanical transduction from the electrical domain to the acoustic domain is provided by piezoelectricity of the material. By storing a received pulse in an ADL for comparison with a subsequent pulse, the scattering from static objects can be canceled, thus diminishing clutter in the radar displays. Following the advances made for radars, other applications for ADL, such as frequency discriminators and modulators/demodulators for frequency shift keying (FSK), also emerged. These applications can all leverage the large time-delay structure accessible only in ADLs to introduce delays over a broad bandwidth for signal processing. For instance, an FSK-based spread spectrum communication scheme can represent each data symbol with a code formed by a sequence of frequencies at RF. An ADL can then be used to impose delays to the incoming signal as a function of its frequency to perform matched filtering for demodulation of the signal. Similarly, such a function of ADLs can be also dual-purposed as a modulator on the transmitter side. In addition to various flavors of matched filtering, perhaps the most pervasive application of ADLs is transversal filtering. Transversal filters based on ADLs can offer flexibility in designing both the amplitude and phase responses while achieving high out-of-band (OOB) rejection. The operating principle of transversal filtering relies on tapping a delay line at different points. By connecting these taps situated at different sections of the ADL, the output signals can be combined in the electrical domain to form a finite Fourier series. With properly designed electrode pitch, polarity, and electrode sections in the ADL, the frequencies, phases, and relative amplitudes of the terms in the Fourier series can be varied to obtain a quasi-arbitrarily configurable filter response. Because of such addressability in their response, transversal filters understandably may be favored over filters based on coupled resonators, such as those based on surface acoustic waves (SAW), lamb waves, or thickness modes, for certain applications. Some ADLs have applications in enabling compact and low-power non-reciprocal networks using time-varying circuit structures. In these approaches, a pair of an array of ADLs can be controlled and accessed by switches on both ends so that signals can be routed between ports on opposite sides of delay lines only in certain allowed paths. Such an ability to engineer chip-scale non-reciprocal response without resorting to magnetic materials can provide for implementing front-ends with the simultaneous transmit and receive capability. The ADLs formed by piezoelectric interdigital transducers of the simplest type may suffer from high bi-directionality losses and may entail a minimum insertion loss (IL) of 6 dB. Transducers with a predominant radiation direction, known as unidirectional transducers (UDTs), can enable lower IL ADLs. Single-phase unidirectional transducers (SPUDTs) can be used to overcome the complexity in impedance matching. These designs can be based on embedding acoustic reflectors formed by grounded or floating electrodes in an asymmetrical arrangement with respect to the signal electrodes. The performance of ADLs formed by SPUDTs may be limited by the imperfect unidirectionality of the transducers that is caused by the finite reflectivity achievable with the electrodes. Some ADLs are based on SAWs excited on a piezoelectric substrate, which may be made of lithium niobate (LiNbO3), lithium tantalate (LiTaO3), or quartz. LiNbO3devices can additionally or alternatively be based on plate modes, like Lamb and shear-horizontal waves. Because of the high electro-mechanical coupling (kt2) of these vibrational modes, resonators can be demonstrated with fractional bandwidths (FBWs) that can outperform SAW ADLs. The advantage of this high coupling can also be demonstrated in dispersive delay lines. A mechanical loading produced by the metal electrodes on the thin-film structure can be expected to be more pronounced than in SAW devices, in which the wave propagates on the surface of a thick substrate. The higher reflectivity of the electrodes provided by the mechanical loading can be exploited to reduce the bi-directionality losses of SPUDTs. In some embodiments, ADLs based on the fundamental shear-horizontal waves (SH0) in LiNbO3can be used to implement delays with low loss and large bandwidth. For example, in some embodiments, an ADL can produce a delay of 75 ns with an IL below 2 dB over a 3 dB bandwidth of 16 MHz, centered at 160 MHz. Aspects of the present disclosure address the above challenges among others by using low-loss and wide-band acoustic delay lines (ADLs). The ADLs include a piezoelectric thin film located above a carrier substrate. A first interdigitated transducer (IDT) may be disposed at a first end of the thin film and a second IDT may be disposed at a second end of the piezoelectric thin film. The first IDT is to convert an input electromagnetic signal (e.g., an RF signal traveling along a longitudinal direction along a length of the piezoelectric thin film) into an acoustic wave. The second IDT is to convert the acoustic wave into an output electromagnetic signal, which can be delayed in time compared to the first electromagnetic signal. In some embodiments, the IDTs are unidirectional. In other embodiments, the IDTs are bi-directional. In some embodiments, the piezoelectric thin film is suspended above the carrier substrate. In other embodiments, the piezoelectric thin film is disposed on a high acoustic impedance layer interposed between the piezoelectric thin film and the carrier substrate. In still further embodiments, the high acoustic impedance layer includes at least one of silicon (Si), sapphire, fused silica, quartz, silicon carbide (SiC), diamond, aluminum nitride (AlN), aluminum oxide (Al2O3), tungsten, molybdenus, platinum, or combindations thereof. In some embodiments, the piezoelectric thin film is disposed on a Bragg reflector interposed between the piezoelectric thin film and the carrier substrate. In some embodiments the Bragg reflector includes a set of alternating high acoustic impedance layers and low acoustic impedance layers. The low acoustic impedance carrier may be at least one of silicon nitride (Si3N4) or silicon dioxide (SiO2). In some embodiments, interfaces between the high acoustic impedance layers and low acoustic impedance layers can reflect the acoustic waves, and can lead to multiple reflections from the alternating layers. In further embodiments, acoustic energy can be confined in a layer (e.g., the piezoelectric thin film) above the Bragg reflector, which may prevent or minimize energy leakage into the carrier substrate via the multiple reflections. In various embodiments, the acoustic wave travels within the piezoelectric thin film in at least one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, a second-order symmetrical (S2) mode, a fundamental shear-horizontal (SH0) mode, a first-order shear-horizontal (SH1) mode, a first-order antisymmetric (A1), or a third-order antisymmetric (A3) mode. In some embodiments, the modes are excited by at least one of a longitudinal-direction (e.g., along a length of the piezoelectric thin film) component of an electric field or a thickness-direction component of the electric field. In some embodiments, the electric fields are induced by incoming electromagnetic signal(s) (e.g., RF signal(s)). In some embodiments, the orientation of the induced electric field is determined by the configuration of electrodes of the IDTs in relation to a particular cut of the piezoelectric thin film. In some embodiments, the electric field is generated by a voltage potential that is applied between a signal bus line and a ground bus line. In various embodiments, the piezoelectric thin film includes one of an X-cut, Y-cut, Z-cut, 128Y-, 54Y-, or 36Y-cut lithium niobate (LiNbO3) thin film. For example, the 128Y-cut, 54Y-cut, or 36Y-cut can be considered as rotated cut variations of the Y-cut LiNbO3thin film. In some embodiments, the piezoelectric thin film includes one of a reactively sputtered c-axis aluminum nitride (AlN) or scandium aluminum nitride (ScAlN). In some embodiments, the piezoelectric thin film includes one of an X-cut LiNbO3thin film or a Y-cut LiNbO3thin film that is rotated with respect to the longitudinal direction by an angle, such as between −30° to +30°. In other words, a y-axis of the LiNbO3thin film can be rotated by the angle, either in a clockwise or counterclockwise direction, with respect to the longitudinal direction. In some embodiments, the longitudinal direction can be oriented between 10 degrees clockwise and 30 degrees counterclockwise to a Y-direction of the LiNbO3thin film. In other embodiments, the longitudinal direction can be oriented between 10 degrees counterclockwise and 30 degrees clockwise to a Y-direction of the LiNbO3thin film. FIGS.1A-1Care schematic illustrations of a cross-sectional view of an ADL device100, according to one embodiment.FIG.1Ais a schematic illustration of an ADL110with an air gap106according to one embodiment. The ADL device110includes a piezoelectric thin film102suspended above a carrier substrate104. An air gap106is located between the carrier substrate104(e.g., carrier wafer) and the piezoelectric thin film102(e.g., piezoelectric layer). Electrodes and/or reflectors are located above the piezoelectric thin film102, and are represented generally by108. The electrodes and/or reflectors108can be physically and electrically coupled to the piezoelectric thin film102. FIG.1Bis a schematic illustration of an ADL device120with a high-acoustic impedance layer112according to one embodiment. The ADL device120is similar to the ADL device110except that the air gap is replaced by a high-acoustic impedance layer112. In other words, the piezoelectric thin film102is located on the high-acoustic impedance layer112. Illustrated is an ADL mock-up including single-phased unidirectional transducers (SPUDTs) disposed on top of a suspended LiNbO3thin film The high-acoustic impedance layer is located between the piezoelectric thin film102and the carrier substrate104. In various embodiments, the high-acoustic impedance layer can be composed of one of silicon (Si), sapphire, fused silica, quartz, silicon carbide (SiC), diamond, aluminum nitride (AlN), aluminum oxide (Al2O3), tungsten, molybdenus, platinum, combindations thereof, or the like. Electrodes and/or reflectors108are located on top of the piezoelectric thin film102. Electrodes and/or reflectors are located above the piezoelectric thin film102, and are represented generally by108. The electrodes and/or reflectors108can be physically and electrically coupled to the piezoelectric thin film102. FIG.1Cis a schematic illustration of an ADL device130with a set of high-acoustic impedance layers112and a set of low-acoustic impedance layers114according to one embodiment. The ADL device130is similar to the ADL device110except that the air gap is replaced by the set of high-acoustic impedance layers112and set of low-acoustic impedance layers114. The piezoelectric thin film102is located on a combination of high acoustic impedance layers112and a combination of low acoustic impedance layers114. In some embodiments, the high acoustic impedance layers112and the low acoustic impedance layers114form a stack in an alternating pattern and that stack is interposed between the piezoelectric thin film102and the carrier substrate104. For example, respective ones of the low acoustic impedance layers114can be alternately disposed on respective ones of the high acoustic impedance layers112. The ADL device130illustrates a further embodiment in which the piezoelectric thin film102is disposed on a Bragg reflector which is composed of multiple alternating layers of high acoustic impedance layers112and low acoustic impedance layers114. In some embodiments, each of the high acoustic impedance layers112and the low acoustic impedance layers114have the same thickness. In other embodiments, the high acoustic impedance layers112can have a different thickness than the low acoustic impedance layers114. The low acoustic impedance carrier of the low acoustic impedance layers can be at least one of silicon nitride (Si3N4), silicon dioxide (SiO2), benzocyclobutene (BCB), or other suitable polymers. The Bragg reflector can be disposed between the carrier substrate104(e.g., carrier wafer) and the piezoelectric thin film102(e.g., piezoelectric layer). Electrodes and/or reflectors108can be located on top of or above the piezoelectric layer. In some embodiments, interfaces between the high acoustic impedance layers112and the low acoustic impedance layers114can reflect the acoustic waves, and can lead to multiple reflections from the alternating layers. In further embodiments, acoustic energy can be confined in a layer above the Bragg reflector, and can prevent energy leakage into the carrier substrate. In some embodiments, high impedance devices, such as ADL120) can provide better power handling. Further, air gap devices, such as the ADL110, can provide higher quadrature (Q) values compared to devices that have no air gap. FIG.2Ais a top view of an ADL200according to one embodiment. Illustrated is a mock-up of the ADL200including SPUDTs disposed on top of a suspended LiNbO3thin film. In one embodiment, the ADL200includes a suspended thin film202made of LiNbO3. The suspended thin film202may constitute a propagation medium for the SH0 acoustic waves. In other embodiments, the suspended thin film may be AlN, ScAlN, or other suitable piezoelectric thin film. For the following discussion, X-cut LiNbO3is used as an illustrative example, although, in other embodiments, the LiNbO3thin film can have a Y cut. The choice of cuts may affect the propagation of acoustic wave modes. These modes may be excited by electric fields oriented in a longitudinal direction, e.g., along a direction of propagation of the acoustic wave, or in other words along the x-axis inFIG.2A, or in the thickness direction, e.g., normal to a direction of propagation of the acoustic wave, or in other words along the y-axis inFIG.2A. In some embodiments the X-cut or the Y-cut LiNbO3thin film can be adapted to propagate an acoustic wave in at least one of a first mode excited by an electric field oriented in the longitudinal direction along a length of the piezoelectric thin film or in a second mode excited by the electric field oriented at least partially in the thickness direction of the piezoelectric thin film. The first mode can include at least one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, a fundamental shear-horizontal (SH0) mode, or a first-order antisymmetric (A1) mode. The second mode can include at least a first-order antisymmetric (A1) mode or a first-order shear-horizontal (SH1) mode. In some further embodiments, the Y-cut LiNbO3thin film includes one of a 128Y-cut, 54Y-cut, or 36Y-cut (also referred to as rotated Y cuts herein) LiNbO3thin film and the second mode includes one of a first-order symmetric (S1) mode. In some cases, the rotated Y cuts can also additionally propagate the acoustic wave in at least one of the first modes (S0, S1, SH0, and A1) excited by the electric field oriented in the longitudinal direction or one of the second modes (A1 and SH1) excited by the electric field oriented at least partially in the thickness direction. A thickness of the LiNbO3thin film can be taken to be between 30 nm and 100 μm. For illustrative purposes herein, the thickness of the LiNbO3thin film can be chosen to be 800 nm. As such, by way of example, the thickness of the LiNbO3thin film will be understood to be approximately 800 nm unless otherwise mentioned herein. With continued reference toFIG.2A, two sets of interdigital transducers (IDTs)216aand216bmay include metal electrodes interconnected by bus lines218and may be disposed on top of the LiNbO3thin film202. The IDTs216aand216bmay be composed of at least one of gold (Au), aluminum (Al), molybdenum (Mo), platinum (Pt), or any other suitable conductive material. In one embodiment, the IDTs216aand216bmay be unidirectional. In other embodiments, the IDTs216aand216bmay be bi-directional. Either set of IDTs216aand216bcan serve as the transmitting transducer (input port), while the other IDT serves as the receiving transducer (output port). In the depicted embodiment, the IDTs216aand216bare separated by a gap length201LGthat may set the time delay experienced by an electrical signal traversing from an input port220to an output port222. In some cases, the gap length201can be between 0 μm and several centimeters. In some cases, the gap length201may be larger. Each IDT216aand216bcan be formed by cascading N identical transducer unit cells (which are described in more detail in reference toFIGS.2B-2C). In some embodiments, the number N of transducer unit cells may range from 1 to 20. The number N of identical transducer cells may be as large as required for a given application. In some embodiments, the transducer unit cell may be a distributed acoustic reflector transducer (DART) unit cell (such as transducer unit cell230bofFIG.2B). In other embodiments, the transducer unit cell may be an electrode width controlled (EWC) unit cell (such as transducer unit cell230cofFIG.2C). FIG.2Bis a top view of a DART unit cell230baccording to one embodiment. The DART unit cell230bis one example of a SPUDT. The DART unit cell230bincludes a signal electrode226bcoupled to an upper bus line228band a ground electrode224bcoupled to a ground bus line218b. The signal electrode226band the ground electrode224bcan be collectively referred to as transduction electrodes herein. The transduction electrodes have a width of λ0/8. The DART unit cell230balso includes wider electrodes that are reflectors232aand232b(e.g., acoustic reflectors). A width of the reflectors232aand232bof the DART unit cell230bis 3λ0/8. While an ADL, such as the ADL200, itself can be treated as an electrical device with two ports, the individual IDTs, as well as each included transducer unit cell (such as the DART unit cell230b), can be analyzed as a three-port network that effectively has one electrical port234band two acoustic ports, including a forward (FWD) acoustic port236band a backward (BWD) acoustic port238b. The two acoustic ports236band238beffectively represent the two propagation directions (e.g., +x axis and −x-axis) into the acoustic medium. In some cases, a transducer unit cell, and thus the corresponding IDT, can be a bi-directional transducer with no directionality. Such a transducer can emit the same amount of power towards both acoustic ports. Thus, in an ADL formed by bi-directional transducers and an acoustic media, only half of the acoustic power available at the input transducer is sent towards the output transducer, while the other half may get lost. By reciprocity, the bi-directional output transducer may only convert half of the incident acoustic power to the electric domain. Consequently, ADLs formed by bi-directional transducers may suffer from an intrinsic minimum IL of 6 dB. In order to mitigate the acoustic power loss due to bi-directionality, unidirectional transducers, such as single-phased unidirectional transducers (SPUDTs), such as the DART unit cell230bcan be employed, although this may come at the cost of reduced bandwidth. The operation principle of SPUDTs can be explained from the analysis of the transduction and reflection centers founded in their electrode layouts. A transduction center (TC) is a reference plane at which the acoustic waves launched towards both longitudinal directions (e.g., the +x and −x directions) have the same amplitude and phase. Similarly, a reflection center (RC) is a reference plane at which the wave reflections from both longitudinal directions (e.g., the +x and −x directions) are equal. In some IDTs, such as bi-directional IDTs, the TCs and RCs can be evenly distributed along the transducer. Alternatively, in SPUDTs, TC240bcan be arranged asymmetrically with respect to the RCs242aand242b, in a way such that the launched acoustic waves, through both transduction and reflection, interfere constructively (illustrated by acoustic wave203b) towards one of the acoustic ports, while the waves launched towards the opposite acoustic port interfere destructively (illustrated by acoustic wave205b), thus leading to the unidirectionality. For simplicity, and by way of example, the former port will be referred to as the FWD acoustic port236band the latter port will be referred to as the BWD acoustic port238bin the present disclosure. However, it should be noted that in other embodiments, the former port can be referred to as the BWD acoustic port and the latter port can be referred to as the FWD acoustic port. In some cases, the TC can be placed closer to the nearest RC towards the BWD acoustic port than to the nearest RC towards the FWD acoustic port. The difference between these distances may be λ0/4 to produce the mentioned constructive (destructive) interaction at the FWD (BWD) port. FIG.2Cis a top view of an EWC unit cell230c, according to one embodiment. The EWC unit cell230cis another example of a SPUDT. The EWC unit cell230cincludes a signal electrode226ccoupled to an upper bus line228cand a ground electrode224ccoupled to a ground bus line218c. The signal electrode226cand the ground electrode224ccan be collectively referred to as transduction electrodes herein. The transduction electrodes have a width of λ0/8. The EWC unit cell230calso includes wider electrodes that are reflectors232cand232d(e.g., acoustic reflectors). A width of the reflectors232cand232dof the EWC unit cell230cis λ0/4. The EWC unit cell230ccan also be analyzed as a three-port network that effectively has one electrical port234band two acoustic ports, including an FWD acoustic port236cand a BWD acoustic port238c. The two acoustic ports236cand238ceffectively represent the two propagation directions (e.g., +x axis and −x axis) into the acoustic medium. Similar to the DART unit cell230b, in the case of the EWC unit cell230c, the TC240ccan be arranged asymmetrically with respect to the RCs242cand242c, in a way such that the launched acoustic waves, through both transduction and reflection, interfere constructively (illustrated by acoustic wave203c) towards one of the acoustic ports, while the waves launched towards the opposite acoustic port interfere destructively (illustrated by acoustic wave205c), thus leading to the unidirectionality. For simplicity, and by way of example, the former port will be referred to as the FWD acoustic port236cand the latter port will be referred to as the BWD acoustic port238cin the present disclosure. However, it should be noted that in other embodiments, the former port can be referred to as the BWD acoustic port and the latter port can be referred to as the FWD acoustic port. In some cases, the TC can be placed closer to the nearest RC towards the BWD acoustic port than to the nearest RC towards the FWD acoustic port. The difference between these distances may be λ0/4 to produce the mentioned constructive (destructive) interaction at the FWD (BWD) port. With reference toFIGS.2A-2C, each transducer unit cell can contain two types of electrodes: ground electrodes232and224that are connected to a lower bus line218and signal electrodes226that are connected to an upper bus line228. In some cases, the thickness of the electrodes (including the ground electrodes224and232as well as the signal electrodes226) may be between 5 nm and 10 μm. In some cases, the thickness of the electrodes may be larger. When a voltage is applied between the lower bus line218and the upper bus line228(e.g., from an electromagnetic signal, for example, an RF signal), electric fields (e.g., E-fields) may be generated between the signal electrodes226and the ground electrodes224along the propagation direction (e.g., the x-axis). In some embodiments, the electric fields may be induced by one or more incoming electromagnetic signals. Further, the orientation of the induced electric fields may be determined by the configuration of the electrodes224and226. Through the inverse piezoelectric effect, the E-fields can subsequently launch fundamental shear-horizontal strain and stress waves (SH0) in the xy-plane towards both the +x and −x directions. By reciprocity, the shear stress and/or strain in the xy-plane associated with an acoustic wave propagating through the receiving IDT216can generate a voltage difference across the corresponding input electrical port220. The efficiency of the conversion between electrical and acoustic energy can be maximum at a center frequency, f0, at which an acoustic wave is phase-delayed by 360° after traveling through a transducer unit cell. The value of f0can be determined by the length of the unit cells λ0as f0=vtλ0,(1) where vtis the average phase velocity of the acoustic wave in the transducer unit cell. In some cases, the length of the transducer unit cell can range between 0.1 μm to 100 μm. An average phase velocity of the acoustic wave can be calculated as a weighted average between a phase velocity v∞of the un-metallized LiNbO3film and a phase velocity vm, of the metallized film which can be expressed as vt=ηvm+(1−η)v∞, (2) where η is the metallization ratio of the transducer unit cell. The dependence of f0on the thickness of the piezoelectric thin film can be neglected, due to the weak dispersive nature of SH0 waves. FIG.3Ais a side-view of a SPUDT330with an effective electric field307and a corresponding strain 309 curve and displacement311curve according to one embodiment. Although not all components of the SPUDT330are shown, the SPUDT330is similar to the DART unit cell230band/or the EWC unit cell230cas noted by similar reference numbers. To locate the TCs240band240cof the transduction unit cells230band230cofFIGS.2B-2C, respectively it should first be noted that shear-horizontal waves can be generated through piezoelectricity in the areas with x-polarized electric fields, such as the electric field307. These areas may be the gaps between the signal electrode326and the adjacent ground electrodes324and332on either side. In adjacent gap areas, the x-polarized electric fields induced by the electrodes may have opposite signs, as seen inFIG.3A. Therefore, in a transduction unit cell (such as the DART unit cell230b), a center of the signal electrode326may be approximately an axis of anti-symmetry for a generated xy-plane strain ϵxy309. Since ϵxy309is the derivative of a y-axis displacement uy311with respect to x, uy311is symmetric with respect to the center of the signal electrode326. Thus, this point can be considered the TC for the displacement wave uy(x, t)311. The same approximation can be adopted for EWC unit cells.FIG.3Ashows that the induced strain 309 and displacement311may be respectively antisymmetric and symmetric with respect to the center of the signal electrode326. FIG.3Bis a side-view of the SPUDT330to illustrate an RC according to one embodiment. Following the same symmetry rationale as for the TC, the center of a reflection electrode332can be regarded as a reflection center. Due to the symmetry of the electrodes and the law of conservation of power, the reflection coefficients of metal electrodes referred to their centers may be purely imaginary.FIG.3Bshows equal reflection coefficients with respect to to the center of the electrode for incidences from both sides. FIG.3Cis a side-view of the SPUDT330to illustrate unidirectionality according to one embodiment. As seen inFIG.3C, in either a DART unit cell or an EWC unit cell, there can be a pair of electrodes324and325which have a width of λ0/8 and are connected to ground and signal, respectively, with a center-to-center distance of λ0/4. The acoustic waves respectively reflected by these electrodes can have a phase difference of 180° at the center frequency f0and interfere destructively. Assuming small reflections, their amplitudes can be considered equal, resulting in a perfect theoretical cancellation. In other words, acoustic waves reflected by the two adjacent λ0/8 electrodes324and326can produce an overall substantially zero reflection coefficient. As a result, the λ0/8-wide electrodes324and326with a center-to-center distance of λ0/8 can be omitted from the analysis for reflections within the SPUDTs. Different from λ0/8-wide electrodes, the wider electrodes (such as the acoustic reflectors, or the wider electrodes332) may be intended to produce pronounced reflections. In other words, FIG.3C shows a reflection-less nature of two identical electrodes324and326separated by a distance of λ0/4 at f0. FIG.3Dis a side-view of the SPUDT330to illustrate multiple reflections of acoustic waves according to one embodiment. As seenFIGS.2B-2C, the acoustic emission towards the FWD acoustic port236can be a combination of the waves generated at the TC240towards the FWD acoustic port236and the acoustic waves towards the BWD acoustic port238that are reflected from the closest RC on the left. For both DART and EWC designs, the RCs242aand242dcan be separated from TCs240band240c, respectively, by a distance of 3λ0/8. Assuming a negative imaginary reflection coefficient F (with a phase angle of 90 degrees), the reflected acoustic waves can be in phase with the acoustic waves generated at the TC towards the FWD acoustic port236at f0. Note that the acoustic waves sent by the further transduction unit cells on the left may also interfere constructively given the λ0periodicity. The acoustic emission towards BWD acoustic port238may be the result of the interference of the waves generated at the TC and their reflection from the closest RC on the right. Due to the 5λ0/8 separation between the TCs240band240and RCs242band242d, respectively, on the right, the directly transduced waves towards the BWD acoustic port238and their reflection from RCs may be out of phase. Hence, the BWD acoustic port238may receive less acoustic power than the FWD acoustic port236due to the partial cancellation of the directly transduced acoustic waves by the reflection. In some cases, a single reflection may not be sufficient to achieve the elimination of transduction towards the BWD acoustic port238and unidirectionality towards the FWD acoustic port236. More transduction unit cells may be required for this purpose. In a multi-cell ∞configuration (e.g., with N transduction unit cells), the RC in each cell can all serve to produce reflection for every TC. Therefore, the interference in both directions combines all the directly transduced waves from all TCs and all the reflections generated by all the RCs. The dynamics in a multi-cell configuration can be analyzed, and it can be shown that a near-perfect unidirectionality is thus possible with multiple cells and multi-reflections. The total reflection illustrated byFIG.3Dis induced by a metal electrode as a combination of two contributions, one electrical (Γe) and one mechanical (Γm). As discussed above, the directionality of the SPUDT330may be based on the reflectivity of the wide electrodes332in each unit cell. The reflectivity of each reflector can be quantitatively modeled. The reflection coefficient F of an electrode can be considered as the result of two phenomena. First, it can have a mechanical component, Γm, caused by the edges of the electrode on the film, along with the change in the acoustic impedance in sections with metal coverage. The change in acoustic impedance can arise from unequal mass density and stiffness of the electrode metal and LiNbO3. Second, F can have an electrical contribution, Γe, caused by a constant potential boundary condition created on the top surface of the LiNbO3film by the metallization. In other words, Γeis the reflection coefficient created by a strip of perfect electric conductor (PEC) of zero thickness. To calculate the total reflection coefficient, the mechanical and electrical reflections can be treated as if they were produced at different locations separated by a distance Xo, as seen inFIG.3D. By solving the multiple reflections between these two locations and taking a limit χ0→0, the total reflection coefficient can be obtained as Γ=Γe+Γm1+ΓeΓm(3) for small reflections, e.g., ΓeΓm<<1, Γ≈Γe+Γm. For the reflections that are mechanically-induced by metal electrodes, analytical expressions can be found for SAW devices. For wave propagation in plates, the methods to predict the reflections from mechanical discontinuities can rely on finite element method (FEM) simulations. For an electrode on a thin film, acoustic waves can be reflected as they travel from an un-metalized section to a metalized portion of the LiNbO3film (e.g., step-up). Further, acoustic waves can be reflected as they travel from a metalized portion to an un-metalized section (e.g., step-down). As a result of both reflections, an equivalent overall mechanical reflection coefficient Γmcan be defined for a single electrode. FIG.4Aillustrates a COMSOL model400for calculating the mechanical reflection coefficient from a step-up discontinuity402caused by metallization, according to one embodiment. The model400shown inFIG.4Acan be built in COMSOL to evaluate the mechanical reflection from the step-up discontinuity402created by an electrode. The model may be composed of sections of the delay medium, including a non-metallized region404in one end and metallized region406in the other. Perfectly matched layer (PML) conditions can be set at both ends of the model to emulate an infinitely long mechanical medium along −x and +x. The faces (e.g., surfaces) at −y and +y can be modeled as periodic boundaries. Acoustic waves can be excited by a harmonic force applied at the cross-section at x=0 and s1inFIG.4A, separated from the discontinuity by a distance Ld. With an excitation force along the y-axis, a first SH0 wave can be propagated in a first direction (e.g., along −x) and a second SH0 wave with the same amplitude as the first SH0 wave can be propagated in a second direction opposite to the first direction (e.g., along +x). The first SH0 wave and the second SH0 wave can have opposite phases if the strain ϵxyis considered as the wave variable. Alternatively, the first SH0 wave and the second SH0 wave can have the same phase if the displacement, uyis considered as the wave variable. FIG.4Bshows a magnitude of y-axis displacement uyat 160 MHz, according to one embodiment. In particular,FIG.4Bshows the solution for the magnitude of uy. A standing wave can be created between s1and the metallization edge as a result of the interference of a(x, t) with the reflected wave b(x, t). A constant amplitude can be observed between s1and the PML in the −x region, and between the discontinuity and the PML in the +x region. This can indicate a perfect absorption of the acoustic power by the PMLs. The strain field ϵxyassociated with the wave a can be written as ϵxya(x,t)=Ae−jβ∞xejωtforx>0 ϵxya(x,t)=−Ae−jβ∞xejωtforx>0, (4) where ω is the angular frequency and β∞=ω/v∞is the wave-number in the un-metallized LiNbO3film. The strain field associated with the reflected wave b can then be obtained as ϵxyb(x,t)=Aejβ∞xe-jβ∞x2LdΓsuejωtforx<Ld,(5) where the subscript su denotes the mechanical reflection coefficient associated with the step-up discontinuity. The stress at the cross-sections s2and s3, separated from s1by a distance Δx (e.g., seeFIG.4A), can be obtained as the superposition of a and b waves at x=−Δx and x=Δx respectively: ϵxys2(t)=A(−ejβ∞Δx+ejβ∞Δxe−β∞x2LdΓsu)ejωt(6) ϵxys3(t)=A(ejβ∞Δx+ejβ∞Δxe−β∞x2LdΓsu)ejωt(7) By taking a limit Δx→0, the expression below can be obtained: Γsu=uyb(x,t)uya(x,t)=-ϵxyb(x,t)ϵxya(x,t)=e-iβ∞2Ldϵxys3+ϵxys2ϵxys3-ϵxys2(8) where uyaand uybare the displacements associated with the incident and reflected waves, respectively. Using this expression, the reflection coefficient Γsucan then be obtained by evaluating ϵχs2and ϵχs3in the COMSOL simulation. As an illustrative example, the procedure described above can be performed for an 800 nm-thick LiNbO3film and four metals that are commonly used as electrodes in microsystems: gold (Au), aluminum (Al), molybdenum (Mo) and platinum (Pt). In all cases, it can be found that Γsuis substantially constant as a function of frequency up to 500 MHz. FIG.4Cis a graph illustrating an amplitude of the mechanical reflection coefficient Γmsuas a function of metal thickness for different metals at 160 MHz, according to one embodiment. The magnitude of Γsucan be found to be nearly linearly dependent on the metal thickness. FIG.4Dshows a phase of the mechanical reflection coefficient Γmsuas a function of metal thickness for different metals at 160 MHz, according to one embodiment. The phase of Γsuis close to 180° for the simulated thickness range. The reflection coefficient of the electrode step-down, Γsd, can be found to have the same magnitude but opposite phase as the reflection coefficient of the electrode step-up, (e.g., Γsd=−Γsu). The overall mechanical reflection coefficient of an electrode can be found by summing the multiple reflections produced by the step-up and step-down discontinuities. Referencing the reflections to the center of the electrode, the following expression can be obtained Γm=Γsuejα(1-e-j2αTsu∑n=0∞(Γsue-jα)2n)(9) where α is the phase retardation for traversing half of the width of a reflector. α is be 3π/4 for DART and π/2 for EWC reflectors. Tsuis the transmission coefficient of the step-up discontinuity, given by Tsu=1+Γsu. (10) Introducing Tsuto Eq. (9) and simplifying the geometric series, the following result can be obtained Γm=Γsuejα1-e-j2α(1-Γsu2)1-Γsu2e-j2α.(11) The electrical reflection can be calculated in a similar way by considering the change in phase velocity produced by the ground condition set by the reflector electrodes on top of the piezoelectric film. Similar to the approach with the mechanical reflection, a reflection coefficient can be defined as the wave passes from an un-metalized to a metalized section, Γ∞0=v0-v∞v0+v∞,(12) where v0and v∞are the phase velocities for a piezoelectric medium with the free and electrically shorted top surfaces, respectively. The reflection coefficient as the wave passes from a metallized to an un-metallized section is Γ0∞=−Γ∞0. The phase velocities of the SH0 mode can be determined using the finite element method (FEM) in COMSOL. For an 800 nm-thick LiNbO3film, the phase velocity v∞for a piezoelectric medium with an electrically shorted top surface can be calculated to be 4507 m/s. For the same film with the ground as the electrical boundary condition on the top surface, a phase velocity v0for a piezoelectric medium with a free top surface can be found to be 3550 m/s. The overall electrical reflection coefficient of an electrode can be obtained following the same procedure as for Eq. (11), as follows: Γe=Γ0∞ejα1-e-j2α(1-Γ0∞2)1-Γ0∞2e-j2α.(13) It should be noted that Eq. (13) may not account for non-uniform electric fields created by the uneven charge distribution in an electrode when surrounded by other electrodes in an array or multi-cell configuration. An analytical method to calculate the electrical reflection accounting for this phenomenon can be used. Such a method can assume an array of electrodes with constant width and separation. Since this condition may not be met by the reflectors in SPUDTs, the method may have to be revised before being applied. Based onFIGS.4A-4D, as an illustrative example, 100 nm-thick Au can be chosen to implement the electrodes for simultaneously enabling sufficient reflections and avoiding fabrication complications. In other embodiments, electrodes can be composed of at least one of gold (Au), aluminum (Al), molybdenum (Mo), platinum (Pt), or other suitable conductive material. In some embodiments, the thickness of the electrode can be between 5 nm and 10 μm. For such a configuration, Γs=−0.116 can be obtained in the case where the imaginary part is neglected. Using Eq. (11), the mechanical reflection coefficients can be obtained for the wide electrodes in DART unit cells (such as the DART unit cell230bofFIG.2B) and EWC unit cells (such as the EWC unit cell230cofFIG.2C): ΓmDART=−0.164 j, ΓmEWC=−0.229 j. For the electrical reflection, Eq. (12) can result in Γ∞0=−0.119, which, from Eq. (3), yields: ΓeDART=−0.168 j, ΓeEWC=−0.235 j. The total reflection coefficients, arising from both mechanical and electrical reflection phenomena, can be obtained through Eq. (3) as ΓDART=−0.323 j, ΓEWC=−0.440 j. These values can be negative and imaginary as assumed in the analysis for RCs with respect toFIGS.3A-3D. In various embodiments, with electrodes of the same material and thickness, the reflection coefficients of reflectors in a SAW device on a YZ-LiNBO3substrate may be at least one order of magnitude smaller. As shown in the following description, a higher reflectivity per reflector can permit a higher unidirectionality in a multi-cell configuration (e.g., in a multi-cell ADL). Considering that the bandwidth (BW) of unidirectionality scales down as the number of unit cells increases, a higher reflectivity can also imply a better tradeoff between delay line insertion loss (IL) and BW. As previously described, multiple unit cells that are spaced by λ0disposed in a cascaded configuration may be required to attain highly unidirectional transduction. In order to be consistent with the framework used for analyzing a single cell, a multi-cell transducer can also be considered with three ports (as described with respect toFIGS.2B-2C): one electric port that is connected to all the cells for excitation, and two acoustic ports that can be situated at the opposite ends of the multi-cell transducer. To quantitatively measure the directionality of multiple cells, a figure of merit (FoM) dubbed as directionality of transduction can be defined as D=PFWDPBWD,(14) where PFWDis the power emitted towards the FWD acoustic port and PBWDis the power emitted towards the BWD acoustic port. When a time-harmonic voltage is applied at the electrical port, a transducer (e.g., with N transducer unit cells) can emit acoustic power towards both acoustic ports. The total emission to each port can be calculated as the superposition of the waves emitted by each TC in the transducer. To determine the power emitted by a single TC in a multi-cell configuration, a voltage source can connected to one TC at a time, while all other TCs are grounded.Γ′1 FIG.5shows a schematic of a SPUDT516formed by N transducer unit cells530, according to one embodiment. Although not all components of the SPUDT516are shown, the SPUDT516is similar to the IDT216ofFIG.2A. The number of transducer unit cells Nis an integer number that can range from 1 to as many as is necessary for a given application. Increasing the number of transducer unit cells (also referred to simply as “unit cells” herein) can increase the unidirectionality of the SPUDT and can result in a narrower bandwidth. In some embodiments, increasing the unidirectionality can be preferable. InFIG.5, each rectangle corresponds to a unit cell with marked RC and TC. For the ithunit cell, the directionality can be calculated by considering its TC and all the RCs at both sides. As seen, the transduction center540at the unit cell i can have i−1 reflectors on its right (FWD) and (N−i+1) reflectors on its left (BWD), with all reflectors being characterized by the same reflection coefficient, F. Each RC in the transducer can be denoted by an index k. At the (i−1)thRC which is on the immediate right of the ithTC (i.e., k=i−1), an equivalent reflection coefficient Γ′kcan be defined, that accounts for all the reflections produced by the unit cells from 1 to k. For k=1, this may simply be Γ′1=Γ. For k=2, the equivalent reflection coefficient must account for the multiple reflections between the RCs of unit cells 1 and 2. At f0, there may be a 2π phase separation between the RCs, giving: Γ2′=Γ+T2Γ1′∑n=0∞(Γ1′Γ)n(15) where T is the transmission coefficient of the RCs, and can be obtained as: T=1-Γ∞m21-Γ∞m2e-j2α,(16) where Γ∞=(Γsu+Γ∞0)/(1+ΓsuΓ∞0) is the total reflection experienced by a wave traveling from a non-metallized to a metallized section. By substituting Eq. (16) into Eq. (15) and simplifying the geometric series, Eq. (15) can be reduced to Γ2′=Γ+TΓ1-Γ2.(17) This method can be applied to the successive RCs, leading to the recursive definition of Γ′k: Γk′=Γ+TΓk-1′1-ΓΓk-1′.(18) The equivalent reflection coefficients of the RCs on the left of the ithTC540can be obtained in the same way from the right to the left as Γ′N−k+1(seeFIG.5). Associated to the Γ′k, the equivalent transmission coefficients to each RC can be defined as: T′k=ejϕk√{square root over (1−|Γ′k|2)}, (19) where ϕkis the phase of the transmission coefficient. Then, the calculation of the directionality of unit cell i can be reduced to attending the ithTC540with two overall reflections at the locations of the two most adjacent RCs on the left and right, with reflection coefficients ΓN−+1and Γ′i−1respectively. By solving the multiple reflections for the two waves generated at the TC in the opposite directions, the wave amplitude emitted to the FWD port can be found to be: αiFWD=ψe-j(3π/4-ϕi-1)1-Γi-1′2(e-jπ/2+ΓN-i+1′)1-Γi-1′ΓN-i+1′,(20) where ψ is the transduction coefficient. For the wave radiated to the BWD port, the wave amplitude emitted to the BWD port can be found to be: αiBWD=ψe-j(3π/4-ϕN-i+1)1-ΓN-i+1′2(1+e-jπ/2+Γi-1′)1-Γi-1′ΓN-i+1′(21) Imposing that, from Eq. (18), all the Γ′kmay be negative and imaginary, the directionality of the unit cell i can be obtained as Di=aiFWD2aiBWD2=(1+Γi-1′)(1+ΓN-i+1′)(1-Γi-1′)(1-ΓN-i+1′).(22) By evaluating Eq. (18) into Eq. (22), it can be shown that the directionality of each unit cell in a multi-cell configuration has the same value Di=(1+Γ1-Γ)N(23) which, by linear superposition, may also be the overall directionality of the whole transducer, D. The transducer directionality calculated in this way is plotted inFIG.6as a function of the number of cells, for different values of the reflection coefficient. The specific values calculated above for the DART and EWC, ΓDART=−0.204 j and ΓEWC=−0.359 j, are represented by solid lines. If (3) is introduced in (23), the directionality is obtained as a composition of two factors, the directionality due to the electrical reflection, De, and the directionality due to the mechanical reflection, Dm: D=DeDm=(1+Γe1-Γe)N(1+Γm1-Γm)N(24) FIG.6illustrates the transducer directionality as a function of the number unit cells (N) for different values of the overall reflection coefficient (Γ), according to one embodiment. The solid lines correspond to the reflection coefficients derived for DART and EWC reflectors with 100 nm thick Au. The group delay of an ADL (also referred to simply as a delay line herein) employing the abovementioned transducers can be challenging to precisely predict with a closed-form expression. This can be due to the complexity introduced by the multiple reflections between the different cells in each transducer. A simplified analysis can be done by disregarding these internal reflections. This can be achieved by considering the transfer function F(ω) from the input port to the center of the ADL. It can be expressed as the superposition of N phase-retarded acoustic waves generated by the transducer unit cells. Assuming lossless propagation, each term in F(ω) can have three-phased delays: the one due to the propagation over a distance from the TC to the right edge of each unit cell, the phase delay from the right edge of each unit cell to the right edge of the entire input transducer, and the phase delay from the right edge of the input transducer to the center of the delay line, over a distance LG/2. This can be expressed as: F(ω)=∑n=1Ne-j(βtdc+βtλ0(n-1)+β∞LG/2)(25) where βt=ω/vtis the average wave number within the unit cell. The phase of F(ω) can be calculated at least by using Euler's identity as ∠F(ω)=-ωLG2v∞-ωdcvt-arctan(sin(Nλ0ω/vt)cos(Nλ0ω/vt)-1)+arctan(sin(λ0ω/vt)cos(λ0ω/vt)-1).(26) By reciprocity and symmetry of the transducers, this can also be equal to the phase shift experienced by a signal from the center of the ADL to the output port. Thus, the total group delay at f0can be obtained as τg(f0)=-2d∠F(ω)dω|ω=ω0=LGv∞+2dcf0λ0+N-1f0.(27) The first term is the delay introduced by the gap LGbetween transducers. The second and third terms correspond to the wave propagation within the transducers. FIG.7illustrates FEM simulated overall directionality per unit cell (D/N), and calculated directionality per unit cell due to electrical (De/N) and mechanical (Dm/N) reflections, according to one embodiment. A COMSOL-based FEM model of a unidirectional transducer can be built to more precisely predict the directionality as a function of the number of transducer unit cells. The directionality per transducer unit cell can be simulated for an EWC transducer formed by 100 nm of Au for different values of N. The results are shown inFIG.7. Theoretically, this value can be predicted from Eq. (23) as D/N(dB)=(1+|Γ|1-|Γ|).(28) It should be noted that, contrary to Eq. (28), the simulated D/N can show a dependence on N for low values of N. This can be explained by fringe effects in the transducer, which can make the transducer unit cells close to the edges present a smaller directionality than those cells located in the middle of the transducer. To gain insight into this phenomenon, additional simulations can be performed. In the first simulation, zero thickness electrodes can be used to obtain the directionality, Dedue to electrical reflections. In the other embodiments, inFIG.7, a pure solid mechanical simulation can be performed, disregarding the piezoelectricity, in order to obtain the directionality, Dmdue to the mechanical reflections. In such an embodiment, the excitation can be performed by harmonic y-axis forces on the signal electrodes. From these results, it can be seen that, first, the mechanical reflections can be dominant for high values of N. Second, the fringe effects can primarily pertain to the electrical part of the reflections due to the distorted electric field distribution near the transducer edges. Third, the electrical reflection coefficient approximated by Eq. (13) may be overestimated. A directionality of 2.1 dB per transducer unit cell can be deduced for EWC transducers with many cells. The total reflection coefficient can be indirectly obtained from Eq. (28) as |ΓEWC|=0.24. With the same method, the reflectors in DART transducers show |ΓDART|=0.17.j Z∞tan(θm/2) FIG.8illustrates a sectional Mason's model800for a single unit cell, according to one embodiment. Each uniform portion of the unit cell is represented by an acoustic transmission-line section. The acoustic impedance, phase velocity, and length of each section are labeled with symbols. In order to predict the response of the described ADLs with intricacies that may have been omitted in the closed-form analysis, an equivalent circuit model can be used. This method, based on Mason's model, can employ a 1D discretization of the ADL by representing each transducer unit cell of the transducers with a sectional equivalent circuit. The schematic of the implemented model for a single transducer unit cell can be found inFIG.8. Each section with uniform properties can be modeled by a transmission line. The phase velocities for the un-metalized and metalized sections can be calculated in COMSOL as v∞=4507 m/s and vm=2958 m/s. The reflections due to the discontinuities can be modeled by the different characteristic impedances of the sections representing metallized and un-metallized LiNbO3, respectively Zmand Z∞. The ratio can be calculated as ZmZ∞=1+Γ∞m1-Γ∞m,(29) where Γ∞mis the reflection coefficient for an acoustic wave passing from un-metallized to metallized LiNbO3. The reflection coefficient of an electrode can be approximated as a sum of two reflections at the step-up and step-down discontinuities, assuming small reflections. Given the width of the reflectors, these reflections may be in quadrature for DART and in-phase for EWC. Thus, it can be deduced that Γ∞mDART=12|ΓDART|,(30)Γ∞mEWC=12|ΓEWC|,(31) The lengths of the transmission line sections are labeled inFIG.8for both the DART and EWC designs. The transduction section, which may include the signal electrode826, can be modeled as a T-shaped network with an ideal transformer844connecting to the electrical port. The transformation ratio can be determined by the electromechanical coupling and is given by r=√{square root over (2πf0Csk2Zm)}, (32) where Csrepresents the static capacitance per transduction unit cell. From an electrostatic simulation in COMSOL, CS/WA=250 aF/μm can be calculated for an 800 nm-thick LiNbO3film, where WAis the acoustic aperture (e.g., seeFIG.2A). The value for the electromechanical coupling k2can be assumed to be 40%. Note the ratio Zm/Z∞defines the reflections, but the value of Z∞(or Zm) may be irrelevant for the electric response. Hence, Z∞=1 can be taken. The angle θmcan be obtained as θm=π4fλ0vm(33) for both DART and EWC transducers. FIG.9Aillustrates an FEM model900built in COMSOL to simulate the response of the ADLs to validate the circuit model800ofFIG.8according to one embodiment. A 3D model900for an ADL with EWC transducers that has N=10, λ0=20 μm, WA=200 μm, and LG=120 μm is shown inFIG.9A. FIG.9Billustrates a magnitude of a displacement along the y-axis at the center frequency according to one embodiment. With all the parameters defined, a model for a complete transducer can be built by concatenating the models of its unit cells. The unit cells can be connected in series in the acoustic domain, and in parallel in the electrical domain to form the electrical port of the transducer. A complete ADL can be simulated by connecting the models of two transducers in the acoustic domain with their FWD ports facing each other. The gap between the transducers can be modeled by an acoustic transmission line with characteristic impedance Z∞, phase velocity v∞and length LG. To ensure no reflection at the BWD acoustic ports of both transducers, these can be terminated by an impedance Z∞. FIG.10illustrates simulated Y-parameters using the FEM model900ofFIG.9and Mason's model800ofFIG.8, assuming zero propagation loss in the ADL according to one embodiment. An excellent match can be achieved between the two models. It should be noted that these models may not incorporate considerations for dissipative loss in the ADL structure. FIG.11is a flow chart of a fabrication process1100of the ADL according to one embodiment. Guided by the reflectivity analysis presented above, as an illustrative example, Au can be chosen as the material for the electrodes, with a thickness of 100 nm. Further, an X-cut LiNbO3thin film with a thickness of 800 nm can be chosen as the propagation medium since this platform may demonstrate high coupling and low loss for SH0 waves. The propagation direction, e.g., the longitudinal direction can be chosen as −10° with respect to the +Y crystallographic axis of LiNbO3to maximize k2. Table 1 below lists the parameters of the implemented ADL designs. TABLE 1DESIGN PARAMETERS OF THE FABRICATEDACOUSTIC DELAY LINESType ofLGλ0WAτgIDTransducersN(μm)(μm)(μm)(ns)1DART1012020200792DART10500202001643DART101000202002744DART15120202001065DART15500202001906DART20120202001327DART20500202002178EWC1012020200799EWC1010002020027410EWC151202020010611EWC201202020013212EWC2015002020043913DART/Bid (FWD)101202020014DART/Bid (BWD)101202020015EWC/Bid (FWD)101202020016EWC/Bid (BWD)1012020200 ADLs 1-12 can be designed in order to sweep the main design parameters as a way to characterize the propagation loss in the LiNbO3film, as well as the loss associated with the transducers, for a constant center frequency, f0, and acoustic aperture, WA. The expected group delays according to Eq. (27) are also listed in Table 1. ADLs 13-16 are example test structures to characterize the directionality of DART and EWC transducers formed by 10 cells. These ADLs can be formed by a SPUDT transducer and a bi-directional transducer with regular-width electrodes. In the bi-directional transducer, each period of λ0contain 54 electrodes of width λ0/8 to minimize reflections. The electrodes can be connected in the sequence of ‘ground-ground-signal-signal’ to have the same center frequency as the SPUDT. In addition, both transducers may be of the same length in order to similar bandwidths. In ADLs 13 and 15, the FWD acoustic ports of the SPUDTs are facing the bi-directional transducers. In ADLs 14 and 16, the BWD acoustic ports of the SPUDTs are facing the bi-directional transducers. The sixteen ADLs listed in Table 1 can be fabricated on a single chip with the fabrication process1100. The film transfer process can involve two steps. In the first step, an X-cut LiNbO3wafer can be bonded to a Si carrier wafer (1101). Second, the bonded LiNbO3layer can be thinned down to a thickness of 800 nm or other appropriate thickness (1103). Next, the 100 nm-thick Au electrodes can be defined with sputter-deposition and lift-off (1105). Then, the release windows can be defined, e.g., through etching (1107). For this purpose, a 1 μm-thick hard mask of SiO2can be created by plasma-enhanced chemical vapor deposition (PECVD) and can be patterned with fluorine-based reactive ion etching (RIE). The release windows in the LiNbO3film can then be etched by chlorine-based inductive coupled plasma (ICP)-RIE before the SiO2is removed with a buffered oxide etch (BOE). To prevent the Au electrodes from being exposed to XeF2and etched in the device release step, a photoresist (PR) can be spun and patterned to protect the electrodes and leave the release windows exposed (1109). The ADLs can then be released by isotropic XeF2etching, and the PR removed with acetone (1111). FIG.12shows optical top-view images1201and1203of ADLs 1 and 8 according to one embodiment. The ADLs 1 and 8 can be fabricated using the fabrication method1100as described with respect toFIG.11. FIG.13shows optical images1301and1303of SPUDT ADLs 13 and 14 (Table 1) according to one embodiment. Both ADLs 13 and 14 are designed to test the directionality of the DART SPUDT for SH0 waves in LiNbO3. The S-parameters of all the fabricated devices can be characterized using a network analyzer (e.g., such as a Keysight performance network analyzer PNA-XN5249A or the like) at room temperature. The measured data can then be normalized to a matching complex port impedance in an advanced design software (ADS) to extract the IL over the transmission bands. In implementation, the impedance matching to 50Ω can be done with an inductor-capacitor (LC) matching network with sufficient bandwidth. The ADLs can present bandwidths under 15%. Matching networks with LC circuits can be implemented to cover such bandwidths, given the high k2of the SH0 waves in LiNbO3thin films. FIGS.14A-14Fare graphs illustrating the measured and simulated S21 for ADLs 13, 14, 15, and 16 (Table 1) as well as the simulated directionality of the DART and EWC transducers with 10 unit cells according to some embodiments. For both the measured and simulated S21, the directionality is defined as the difference in S21 between FWD ADLs and BWD ADLs. The measured S21 with normalization to matched port impedances is shown for ADLs 13 and 14 with the DART design (e.g.,FIGS.14A and14B, respectively), and for ADLs 15 and 16 (e.g.,FIGS.14C and14D, respectively) with the SPUDT design. In both cases, the directionality of the SPUDT can be obtained by subtracting the S21 of the BWD devices from the S21 of the FWD devices. For the DART transducer with 10 unit cells, the measurements show a maximum directionality of about 15 dB. For the EWC transducer, the directionality can reach more than 20 dB at the center frequency, f0. Both values are in reasonable agreement with the analytical model (FIG.7) and FEM simulation. FIGS.15A-15Hare graphs illustrating measured and simulated S-parameters according to some embodiments.FIG.15AandFIG.15Bshow S11 for ADLs 1 and 8, respectively.FIG.15CandFIG.15Dshow S21 for ADLs 1 and 8.FIG.15EandFIG.15Fshow zoomed-in views of S21, showing a comparison between the measurements and the fitting curves for ADLs 1 and 8.FIG.15GandFIG.15Hshow measured and simulated group delays for ADLs 1 and 8. The analytically calculated delay based on Eq. (27) is also shown inFIG.15GandFIG.15Hfor comparison. Among the fabricated devices, ADLs 1 and 8, that use DART and EWC transducers respectively, present the lowest IL. Their S-parameters are plotted inFIGS.15A-15F, along with their group delays inFIGS.15G-15H. The simulated S-parameters and calculated group delays according to Eq. (27) are also plotted. Both ADLs can show a minimum IL around 2 dB. In spite of the low reflectivity of SPUDT transducers when their electrical ports are matched, ripples with amplitudes of about 1 dB can be observed in the passbands of both ADLs. The ripples can potentially create challenges for comparing the IL of different ADLs and evaluating the loss contributions from different loss mechanisms. In order to overcome this issue, the measured S21 results can be fitted by the following expression: S21=a1sinc2(a2f-a3a3)(34) which describes the transmission band of a piezoelectric delay line (e.g., and ADL) with no reflections between the transducers. FIG.16is a graph illustrating an average minimum IL as a function of the gap length, LG, for various DART and EWC transducers according to one embodiment. The average minimum IL can be obtained by fitting the measured response of each ADL with Eq. (34). Two general trends can be observed inFIG.16. First, IL tends to be larger for a longer ADL with the same number of unit cells. Second, IL tends to increase as more transducer unit cells are used for an ADL of the same length. In other words,FIG.16can indicate that the IL obtained for each ADL can be attributed to two distinctive causes. First, there can be loss due to the propagation through the separation introduced by the gap (LG) between the input and output transducers, which can be denoted as ILp. The second loss component IL can be caused by the transducers which corresponds to the interception points of the lines with the y-axis inFIG.16. The ILpcan be extracted as the slope of the lines inFIG.16. An average value of ILpof 1.19 dB/mm can be extracted from all the lines. From Eq. (27), it can be seen that the separation introduced by the gap may be responsible for a delay of 222 ns/mm. Therefore, the ILpper unit delay can be found to be: ILp=5.8 dB/μs. On the other hand, ILtmay be more complex to analyze. The transducer directionality can be predicted to grow with the number of cells in the transducers, which may enable ADLs with decreasing ILtas N increases. However, the trend seen in measurements, which shows that ILtincreases with N, can indicate a contradiction with the theoretical prediction. This can suggest a second transducer loss component that also scales with the number N of unit cells, and which may be more dominant than the loss due to imperfect unidirectionality. The second transducer loss can result from dissipation at the electrode and piezoelectric interface, thermos-elastic damping (TED), acoustic attenuation in the metal, or a combination of the above. It should be noted that it can be challenging to separate the dissipative loss component caused from the loss given by the imperfect unidirectionality in measurements due to the ripples. However, the latter can be indirectly estimated from FEM simulation. FIG.17is a graph illustrating the total loss in the transducers, ILtfor ADLs formed by DART transducers according to one embodiment. Illustrated is a loss break-down in the transducers (including both the input transducers and the output transducers), including the total loss due to the transducers (extracted from the measurements) and the loss due to imperfect unidirectionality (calculated from simulation) for ADLs 1, 4, and 6. The difference between these loses allows for obtaining the dissipation due to metal. Also shown is the total loss in the transducers, ILtfor ADLs formed by DART transducers of 10, 15, and 20 unit cells with the same LGand WA. The loss from imperfect unidirectionality, which can be derived from a simulation (such as in COMSOL), is also plotted. The remainder of the IL can then be attributed to the dissipative effects associated with the metal electrodes. From the analysis shown inFIG.17, it can be concluded that the IL of a device formed by either DART or EWC transducers of 10 cells can be expressed as IL (dB)=1.29+5.8τg(μs). (35) In summary, a type of ADL can be demonstrated based on shear-horizontal waves propagating in a thin film of LiNbO3. An analysis of the acoustic reflections can be done, showing the promising prospects of this platform for building transducers with large unidirectionality. The results show that time delays of tens of ns can be achieved with a low IL of 2 dB and an FBW in excess of 10%. These ADLs may open possibilities for RF signal processing in compact low-power applications. The remainder of this disclosure will illustrate some specific examples of ADLs, in particular for ADLs using X-cut or Y-cut LiNbO3. It should be noted, however, that the embodiments presented herein are for illustrative purposes only and do not limit the scope of the present disclosure. S0-Mode Lithium Niobate Acoustic Delay Lines FIG.18is a schematic diagram of a full-duplex transceiver1800with an acoustic delay synthesizer1802to attain self-interference cancellation (SIC) according to one embodiment. In some embodiments, the full-duplex transceiver1800may include an antenna1804, a circulator1806, a directional coupler1808, a power amplifier (PA)1810, a low noise amplifier (LNA)1812, a receiver1814, a transmitter1816, a tunable attenuator1818, and the acoustic delay synthesizer1802. In some embodiments, the acoustic delay synthesizer1705may include at least one acoustic delay line (ADL), as disclosed in the various embodiments herein. ADLs can be useful in implementing full-duplex radios, such as the full-duplex transceiver1800. One potential challenge for implementing full-duplex radios can include self-interference (SI). Due to the absence of frequency- or time-domain multiplexing, SI can occur when high-power transmitted signals are reflected from antenna packaging or obstacles in the ambiance, and inadvertently received by a highly sensitive receiver, typically after a 0.01-1 μs delay. To reduce the SI, e.g., attain SI cancellation (SIC), one approach can be to provide wideband time-domain equalization using true-time delays. In such a method, a fraction of the transmitted signal is sent into a time-domain equalizer that emulates the channel transfer function of the SI before it is combined with the SI to render cancellation through destructive interference. To accommodate the dynamic in-field conditions, such a system is typically required to provide reconfigurable delays and tunable attenuations. The challenge with such a method is that, although chip-scale tunable attenuation is attainable, miniature delay synthesis over a sufficiently wide bandwidth (BW) and a necessary delay range remains inaccessible. The unavailability of wide-range delay synthesis originates from the fact that the electromagnetic (EM) delay lines in the existing prototypes can hardly provide delays of more than 1 ns on chip-scale due to the fast group velocities of EM waves in state-of-the-art slow-wave waveguide-related structures. Therefore, EM-based delay synthesis is inadequate for enabling full-duplex in urban environments with dense reflectors (e.g., moving vehicles and buildings). Moreover, the dynamic range of EM-based SIC is also limited. The minimum insertion loss (IL) in the cancellation path is required to be no larger than that in the free space. However, the intrinsically high propagation loss (PL) in the EM delay lines leads to high IL. Moreover, the additional IL from the directional coupler strengthens the requirement of IL, which is challenging for the EM delay lines. In some embodiments, the full-duplex transceiver1800can also be referred to as a full-duplex radio. A full-duplex radio can transmit and receive signals in the same frequency band simultaneously. The full-duplex transceiver1800includes transmit (TX) chain circuitry and receive (RX) chain circuitry. The TX chain circuitry includes at least the directional coupler1808, the PA1810, and the transmitter1816. The RX chain circuitry includes at least the LNA1812and the receiver1814. The TX chain circuitry transmits a first RF signal in a first frequency range via the antenna1804. The RX chain circuitry receives a second RF signal in the first frequency range via the antenna1804. The TX chain circuitry can further include the directional coupler1808, which directs a portion of the first RF signal (e.g., that is transmitted) to the RX chain circuitry. The acoustic delay synthesizer1802includes a set of ADLs and is coupled between the TX chain circuitry and the RX chain circuitry in order to provide a signal delay. In other words, the acoustic delay synthesizer1802provides a delay to the portion of the first RF signal to the RX chain circuitry such that the first RF signal experiences the signal delay and destructively interferes with a reflected portion of the first RF signal. As described above, in an ADL, radio frequency (RF) signals are first converted into the acoustic domain by transducers on one end of the ADL via piezoelectricity. The signals can then propagate as acoustic waves and experience the designed delay before they are turned back into electrical signals by transducers on the other end. In some embodiments, RF ADLs may be realized using surface acoustic waves (SAW) technologies due to their compact sizes and easy fabrication processes. ADLs can be used to enable time delays, filtering, and correlation for improving the signal-to-noise ratios in radar front ends. ADLs can also be used for various sensing applications and the construction of nonreciprocal networks. SAW ADLs may not provide sufficiently low IL and wide BW simultaneously for self-interference cancelation (SIC) applications even when custom-designed unidirectional transducers are adopted. Such a performance limit can arise from the intrinsic tradeoff between the IL and fractional BW (FBW), which can be fundamentally imposed by the attainable reflectivity of the distributed reflectors and the maximum electromechanical coupling (k2) of the SAW modes. In addition, the transducer-induced SAW scattering into the substrate may further exacerbate the PL of the SAW and the tradeoff between IL and delay. To work toward an acoustic delay synthesizer, the fundamental performance bounds may be considerably lifted by resorting to a new piezoelectric platform with higher coupling, larger available reflectivity, and better-confined waveguiding at the same time, as will be described in the following embodiments and in more detail with reference to the various figures. In some embodiments, longitudinally vibrating modes in thin-film lithium niobate (LiNbO3), namely, the fundamental shear-horizontal (SH0) mode and fundamental symmetrical (S0) mode, can be utilized in ADL structures for their simultaneously large k2and low loss. The large coupling can be harnessed to widen the BW of ADLs, while the confined waveguide within a suspended LiNbO3thin film can lower PL and thus also lower IL. Moreover, reflectors on a suspended thin film can provide more substantial reflections in comparison to the same type of reflectors on a SAW structure, which can further improve the tradeoff between IL and BW. Such longitudinally vibrating modes can be used for the acoustic delay synthesizer1802of the full-duplex transceiver1800. The acoustic delay synthesizer includes a set of ADLs. Each of the ADLs includes an X-cut or Y-cut LiNbO3piezoelectric thin film, a first IDT, and a second IDT. The piezoelectric thin film is located above a carrier substrate. The piezoelectric thin film is adapted to propagate an acoustic wave in at least one of a first mode excited by an electric field oriented in a longitudinal direction along a length of the piezoelectric thin film or a second mode excited by the electric field oriented at least partially in a thickness direction of the piezoelectric thin film. In such embodiments, the first mode is one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, a fundamental shear-horizontal (SH0) mode, or a first-order antisymmetric (A1) mode and the second mode is one of a first-order antisymmetric (A1) mode or a first-order shear-horizontal (SH1) mode. In some further embodiments, the Y-cut LiNbO3thin film includes one of a 128Y-cut, 54Y-cut, or 36Y-cut (also referred to as rotated Y cuts herein) LiNbO3thin film and the second mode includes one of a first-order symmetric (S1) mode. In some cases, the rotated Y cuts can also additionally propagate the acoustic wave in at least one of the first modes (S0, S1, SH0, and A1) excited by the electric field oriented in the longitudinal direction or one of the second modes (A1 and SH1) excited by the electric field oriented at least partially in the thickness direction. The first IDT is disposed on a first end of the piezoelectric thin film and converts a first electromagnetic signal, which is traveling in the longitudinal direction, into the acoustic wave. The second IDT is disposed on a second end of the piezoelectric thin film. There is a gap between the second IDT and the first IDT. The second IDT converts the acoustic wave into a second electromagnetic signal. In some embodiments, the first mode can be one of an S0 mode, an S1 mode, or an SH0 mode and the second mode can be one of an A1 mode or an SH1 mode. FIG.19Ais a schematic diagram of an S0 mode ADL1900with a pair of IDTs1916aand1916baccording to one embodiment. The ADL1900includes a piezoelectric thin film1902located above a carrier substrate. The piezoelectric thin film1902is an X-cut or Y-cut LiNbO3thin film adapted to propagate an acoustic wave in at least one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, a fundamental shear-horizontal (SH0) mode, or a first-order antisymmetric (A1) mode excited by an electric field oriented in a longitudinal direction along a length of the piezoelectric thin film. The piezoelectric thin film1902can further be adapted to propagate an acoustic wave in at least one of an antisymmetric (A1) mode or a first-order shear-horizontal (SH1) mode excited by the electric field oriented at least partially in a thickness direction (e.g., mutually perpendicular to the longitudinal and transverse directions indicated) of the piezoelectric thin film1902. In some further embodiments, the Y-cut LiNbO3thin film includes one of a 128Y-cut, 54Y-cut, or 36Y-cut LiNbO3thin film and the second mode includes one of a first-order symmetric (S1) mode. In some cases, the rotated Y cuts can also additionally propagate the acoustic wave in at least one of the first modes (S0, S1, SH0, and A1) excited by the electric field oriented in the longitudinal direction or one of the second modes (A1 and SH1) excited by the electric field oriented at least partially in the thickness direction. A first IDT1916acan be disposed on a first end of the piezoelectric thin film1902. The first IDT1916acan convert a first electromagnetic signal, traveling in the longitudinal direction, into the acoustic wave. A second IDT1916bcan be disposed on a second end of the piezoelectric thin film, opposite the first end of the piezoelectric thin film, with a gap1901Lgbetween the second IDT1916band the first IDT1916a. The second IDT1916bcan convert the acoustic wave (that has traveled across the gap1901) into a second electromagnetic signal. In some embodiments, the ADL1900can support at least one of an S0, S1, S2, SH0, SH1, A0, A1, or A3 mode. In the present disclosure, as an illustrative example, the ADL1900includes 135 nm aluminum IDTs1916aand1916bon top of a suspended 800 nm X-cut or Y-cut LiNbO3thin film1902. In some embodiments, the piezoelectric thin film1902can be suspended above a carrier substrate. In other embodiments, the piezoelectric thin film1904may be disposed on a high acoustic impedance layer interposed between the piezoelectric thin film1902and the carrier substrate. The high acoustic impedance layer can be composed of at least one silicon (Si), sapphire, fused silica, quartz, silicon carbide (SiC), diamond, aluminum nitride (AlN), or aluminum oxide (Al2O3). In other embodiments, the piezoelectric thin film1902may be disposed on a Bragg reflector interposed between the piezoelectric thin film1902. The carrier substrate and the Bragg reflector can be composed of multiple alternating layers including a first layer with a first acoustic impedance (e.g., a high acoustic impedance layer or a high velocity layer) and a second layer with a second acoustic impedance (e.g., a low acoustic impedance layer or a low velocity layer). The second acoustic impedance may be lower than the first acoustic impedance. In some embodiments, the ADL1900further includes a waveguide1960inside of which is disposed the piezoelectric thin film1902, the first IDT1916a, the second IDT1916b, a first port1920coupled to the first IDT1916a, and a second port1922coupled to the second IDT1916b. The first port1920is to receive the first electromagnetic signal and the second port1922is to output the second electromagnetic signal. In some embodiments, the first IDT1916ais an input transducer in order to convert an RF signal into an acoustic signal. The first IDT1916acan include an input ground line1918a, and an input signal line1928a. The input ground line1918acan be coupled to an input ground transduction electrode1924aand an input acoustic reflector1932a. In some embodiments, the input ground line1918acan be coupled to more than one input ground transduction electrode and more than one input acoustic reflector. The input signal line1928acan be coupled to an input signal electrode1926a. In some embodiments, the input signal line1928acan be coupled to more than one input signal electrode. The first IDT1916acan serve as an input port (e.g., PORT 1) for an input signal (e.g., an RF signal). In some embodiments, the second IDT1916bis an output transducer in order to convert an acoustic signal into an RF signal. The second IDT1916bcan include an output ground line1918b, and an output signal line1928b. The output ground line1918bcan be coupled to an output ground transduction electrode1924band an output acoustic reflector1932b. In some embodiments, the output ground line1918bcan be coupled to more than one output ground transduction electrode and more than one output acoustic reflector. The output signal line1928bcan be coupled to an output signal electrode1926b. The second IDT1916bcan serve as an output port (e.g., PORT 2) for an output signal (e.g., an RF signal). The ADL1900can include IDTs1916aand1916bdisposed on top of a suspended piezoelectric thin film1902. In operation, the RF signals can be sent to an input port1920and converted into acoustic waves through input piezoelectric transducers. The launched acoustic waves propagate toward an output port1922. After traversing through the waveguide1960, the acoustic wave can be picked up by output piezoelectric transducers and converted back into the EM domain. Various acoustic signal processing functions can be passively implemented through designing the IDTs1916aand1916band the waveguide1960. ADLs can be sorted into different types from the following aspects, transducer types, electrical excitation direction, acoustic vibration modes, and thin-film material. The high-performance ADLs may require a combination of the proper electrical excitation direction for a certain acoustic mode in a specific material. In some embodiments, ADLs can be bi-directional or unidirectional based on the transducer shapes (e.g., IDT configurations). Bi-directional devices have a minimum 6 dB IL because bi-directional transducers lose half of the energy due to wave attenuation at both ports. Unidirectional devices can eliminate or significantly reduce the bi-directional loss, but the structures tend to be more complex and may require smaller feature sizes. ADLs can be sorted by which modes are excited by one or more of a longitudinal direction electric field or a thickness direction electric field. When the ADL includes electrodes with different polarizations on the top and bottom of the piezoelectric thin film, then the electric field is in the thickness direction. The longitudinal directional field devices have electrodes on the top, bottom, or both sides, but the polarizations of the electrodes facing towards each other in the thickness direction are the same (or the ADL only has electrodes on one side). In some embodiments, ADLs can be sorted based on their acoustic vibration modes (e.g., Lamb modes and shear modes). Lamb modes (e.g., S0, A0, S1, A1, and the like) and shear modes (e.g., SH0, SH1, SH2, and the like) can be both be used. In some embodiments, ADLs can be sorted based on the material, e.g., ADLs may be present on LiNbO3thin films, AlN thin films, or the like. In various embodiments, a gap length (LG) may be defined as the distance (e.g., gap1901) between the first IDT1916a(input transducer) and the second IDT1916b(output transducer). In some cases, the length of the gap1901can range between 0.1 mm and 6.4 mm. In other cases, the length of the gap1901can range between 0 mm to several centimeters. In alternate embodiments, the first IDT1916acan be the output transducer and the second IDT1916bcan be the input transducer. In some embodiments, electric fields can be induced by the electromagnetic signal(s) (e.g., RF signal(s)) received by the first IDT1916a. Further, the orientation of the induced electric fields can be determined by the configuration of electrodes of the first IDT1916a. The ADL1900can be oriented between −10° to 30° with respect to the +y-axis of the X-cut or Y-cut LiNbO3for harnessing the high phase velocity and large coupling of the S0 mode. In some other embodiments, the first IDT1916aand the second IDT1916bcan be oriented at an angle between −10° to 30° with respect to the positive y-axis of the piezoelectric thin film. The S0 mode can be chosen to create gigahertz ADLs for two primary reasons. First, a high electromechanical coupling, k2, up to 40% may be accessible in X-cut or Y-cut LiNbO3, thus allowing a better BW-IL tradeoff for ADLs. Second, in contrast to the SH0 mode, the high phase velocity (over 7000 m/s) of the S0 mode can permit the scaling to higher frequencies with larger feature sizes. FIG.19Bis a schematic diagram of a SPUDT unit cell1930of an S0 mode ADL according to one embodiment. The S0 mode ADL can be the same or similar to the ADL1900. In some embodiments, the first IDT1916acan include at least a transducer unit cell1930. The transducer unit cell1930includes a ground line1918coupled to the first port (e.g., first port1920), acoustic reflectors1932aand1932bcoupled to the ground line1918, a first transduction electrode1924coupled to the acoustic reflectors1932aand1932band to the ground line1918of the first port1920, a signal line1928coupled to the first port1920, and a second transduction electrode1926coupled to the signal line1928and disposed between the acoustic reflector1932aand the first transduction electrode1924. A center of the second transduction electrode1926can be defined as a transduction center1940. A first half of the acoustic reflector1932ais positioned at a first end of the transducer unit cell1930at a first distance away from the transduction center1940, and a second half of the acoustic reflector1932bis positioned at a second end of the transducer unit cell1930at a second distance away from the transduction center1940. The second distance is different from the first distance. In some embodiments, the second distance is 5λ/8 and the first distance is 3λ/8. In other embodiments, the second distance is between 40% and 95% greater than the first distance. The second transduction electrode1926is disposed between the first half of the acoustic reflector1932aand the first transduction electrode1924. The transducer unit cell1930may be a transducer unit cell of the S0 mode ADL1900ofFIG.19A. The first and second IDTs1916aand1916bon the opposite ends of the ADL1900may be SPUDTs. The SPUDTs can be composed of cascaded transducer unit cells1930that each include a pair of transduction electrodes1924and1926(that are λ/8 wide) and one (total effective) distributed acoustic reflector composed of half of acoustic reflector1932aand half of acoustic reflector1932b. In the depicted embodiment, each acoustic reflector1932aand1932bis 3λ/8 wide and shorted to the ground bus line1918(such as for the DART unit cells ofFIG.2B). In other embodiments, each acoustic reflectors can be λ/4 wide (such as for the EWC unit cells ofFIG.2C). In each transducer unit cell1930, the two acoustic reflectors1932aand1932bcan be arranged on opposite sides of transduction center1840nonsymmetrically with different spacings of 3λ/8 and 5λ/8 respectively. The transduction center1940referred to herein is defined as the center of the second electrode1926(e.g., the non-grounded electrode or the signal electrode). After launching from the transduction center1840, the acoustic wave propagating toward the left (e.g., the backward direction (BWD)1905) can get partially reflected from the left-side acoustic reflector1932aand can start traversing in the forward direction (FWD)1903, e.g., towards the right. As the reflected acoustic wave returns to the transduction center1940, it may experience a total of −2π phase delay that results from a −1.5π phase delay from the propagation and a −0.5π phase delay from the reflection, which can cause the reflected acoustic wave to constructively interfere with the acoustic wave that is directly launched toward the FWD direction1903. On the other hand, the acoustic wave propagating toward the FWD direction1903can be partially reflected from the right-side acoustic reflector1932band can start traversing in the backward direction (BWD)1905, e.g., towards the left. As the reflected acoustic wave returns to the transduction center1940, it can experience a −2.5π phase delay from the propagation and a −0.5π phase delay from the reflection. The acoustic wave may see a total delay of −3π upon its arrival back to the transducer center1940and can destructively interfere with the acoustic wave directly launched toward the BWD direction1905. With a sufficient amount of cascading reflections distributed in the unit cells, near perfect cancellation of the BWD wave propagation can be achieved, which can result in the removal of the bi-directionality in the transducers and a 6-dB reduction in the IL of the ADL. FIG.20Ais a graph that illustrates the tradeoff between the minimum insertion loss and fractional bandwidth for unidirectional ADLs with SAW modes showing piezoelectric and reflectivity limits according to one embodiment. The performance of S0-mode ADLs (shown inFIG.19B) can be compared with the SAW technology regarding their fundamental limits. As mentioned earlier, two factors, namely, k2and the reflectivity in SPUDTs, can fundamentally limit the performance of SPUDT-based ADLs. Their impact on ADL performance is shown inFIGS.20A-20Bfor SAW ADLs and S0-mode ADLs respectively. k2may be intrinsically bounded by the piezoelectric properties of the material and effective coupling efficiency of the transducer for a given mode. It can set the limit on the maximum FBW over which impedance matching can be attained without imposing a significant IL. For ADLs working beyond the maximum FBW, the IL can be expressed as IL=FBW2·QT/cpiezo,whenFBW>cpiezo/QT(36)wherecpiezo=vf-vmv·[1+3(vf-vm)2v].(37) and QTis the normalized quality factor of the transducer and may be only determined by the transduction structure. The parameter cpiezois the material piezoelectric constant determined by the material coupling coefficient and can be calculated through the phase velocities of the acoustic wave in the thin film sections with free surface vfand metalized surface vm. FIG.20Bis a graph that illustrates the tradeoff between the minimum insertion loss and fractional bandwidth for unidirectional ADLs in S0-mode LiNbO3, showing piezoelectric and reflectivity limits according to some embodiments. For one design, with QTof 0.6594, vfof 7018 m/s, and vmof 6047 m/s, the maximum electromechanical coupling coefficient k2is 35%. Based on Eq. (36), a k2of 35% translates to a maximum FBW of 50%, beyond which a larger FBW comes at the cost of a higher IL. In other words, the black region shown inFIG.20Bmay be forbidden and may not be accessible. FIG.21Ais a graph that illustrates the mechanical reflection coefficients caused by the thin film interface, with and without electrodes according to some embodiments. The graph ofFIG.21Ashows the attainable reflections in the embedded reflectors may limit the unidirectionality of the transducer pairs and thereby the IL of the ADL. Curve2102corresponds to Au, curve2104corresponds to A1, curve2106corresponds to Mo, and curve2108corresponds to Pt. The dependence of IL on reflectivity can be expressed as IL=1−e−Γλ/FBW, (38) where Γλis the reflection per wavelength. Eq. (38) quantitatively explains that a platform with a lower Γλmay require more cells e.g., acoustic reflectors, to achieve the same unidirectionality and IL and intrinsically leads to a smaller FBW due to the dependence of transducer frequency-domain response on the number of cells (FBWtransducer˜1/N). Γλcan be calculated based on a model that separates the reflection into the mechanically and electrically induced reflections. The mechanical reflection may be caused by different effective acoustic impedances in the sections of LiNbO3with and without electrodes, while the electrical reflection (described in further detail with respect toFIG.21B) can be induced by the constant potential boundary condition in the metalized LiNbO3sections. The mechanical reflection per unit cell can be calculated as Γm=Γsuejα1-e-j2α(1-Γsu2)1-Γsu2e-j2α,(39) where Γmis the mechanical reflection coefficient at the reflection center, Γsuis the step-up reflection coefficient, and α is the electrical width of the reflector, which is 3π/4 for some embodiments of a SPUDT design. Γsucan be obtained from COMSOL frequency-domain FEA. In the FEA, the mechanical reflection coefficient of a single reflector can be obtained. Γsumay then be extracted through the multi-reflection theory. In some embodiments, for a stack of 135 nm aluminum electrodes on 800 nm LiNbO3, Γsuis −0.045 as shown inFIG.20A. Thus, Γmis calculated to be −0.057. FIG.21Bis a graph that illustrates the electrical reflection coefficients caused by the thin film interface, with and without electrodes according to some embodiments. The electrical reflection can be calculated as Γe=Γ0∞ejα1-e-j2α(1-Γ0∞2)1-Γ0∞2e-j2α,(40) where Γeis the electrical reflection coefficient at the reflection center and Γ0∞is the reflection coefficient due to the phase velocity difference in the metalized and free piezoelectric surfaces. Γ0∞can be obtained from COMSOL FEA eigenmode simulation of a piezoelectric slab with electrically open or short surface boundary conditions. It should be noted that the electrodes are assumed to be massless. The relationship of the reflectivity to metal electrode thickness and metal type of the SPUDT is shown inFIG.20B. For the S0 mode with a wavelength, λ, of 6.4 μm in an 800 nm in LiNbO3film, Γ0∞is −0.0743, and thus Γeis calculated to be −0.105 j. The comprehensive reflection coefficient Fλ, which includes the effects of mechanical and electrical reflections, can be calculated through the multireflection theory and expressed as Γλ=Γm+Γe1+Γm·Γe.(41) The total reflection coefficient per reflector is calculated to be −0.16 j, which may be significantly larger than those obtained in SAW devices with a similar electrode thickness. The large reflectivity is collectively caused by a higher Γefrom a larger k2and a higher Γmfrom the more substantial electrode mass loading on a suspended thin film (e.g., Γeand Γmcan be approximately two to five times larger in the ADLs described herein as compared with SAW-based ADLs, and can be approximately on the order of 0.2). Based on Eq. (38), the forbidden region caused by the limit on reflectivity is illustrated inFIG.20B. Upon comparing the graphs ofFIG.20AandFIG.20B, it is evident that the S0-mode ADL may allow access to a more favorable FBW-IL trade space and overcomes the fundamental performance limits of the SAW ADL. Combined with their better energy confinement in the suspended structure and consequently lower PL, S0 ADLs can potentially enable wider BW and lower loss performance in the gigahertz frequency range. FIGS.22A-22Eare a set of graphs that illustrate a simulated performance of the gigahertz S0 ADLs with a 6.4-μm cell length, the same gap length of 0.2 mm, but different numbers of SPUDT cells (5-20) according to some embodiments. FIG.22Ais a cross-sectional mode shape depicting the unidirectionality of the SPUDT transducers for an ADL with 20 cells and a gap length of 0.1 mm according to one embodiment. It should be noted that as depicted, the thickness of the cross-section is exaggerated as illustrated. To better capture the intricacies and understand the frequency-domain responses of the S0-mode ADL, COMSOL FEA can be used for validating the S0-mode ADL prototype designs. To demonstrate the design fundamentals of the S0-mode ADLs, simplified 2D simulations can be used, assuming that the acoustic waves are plane waves and the fringe effects near the release windows can be neglected. The 3D simulation can also be analyzed, emphasizing the propagation characteristics of the S0 mode acoustic waves in our proposed structure. The 2D simulation is set up as follows. A slab of the proposed S0-mode ADL structure can be modeled in COMSOL, with the IDTs but not the bus line parts, as shown inFIG.22A. Periodic boundary conditions may be applied to the transverse edges for both the mechanical and electrical domains. The 2D simulation may also assume the whole structure, including the acoustic waveguide, to be lossless, given that PL may remain unknown for S0-mode waves at these frequencies. PL can be experimentally derived by making a series of measurements. Perfectly matched layers can be applied to both ends of the S0-mode ADL. First, the S0-mode ADL designs with different numbers of transducer unit cells, but the same gap length (0.2 mm), can be investigated to determine the number of cells in one design for an acceptable SIC application. In the simulation, without loss of generality, the transducer unit cell length can be chosen to be 6.4 μm. Considering potential in-house fabrication capabilities, the film stack is set as 135 nm-thick aluminum IDTs on the top of a suspended 800 nm LiNbO3thin film. As shown in the simulated cross-sectional mode shape (FIG.22A), the SPUDTs on both ends significantly reduce the energy leakage to the BWD direction. FIGS.22B-22Cshow the IL and the RL of the S0-mode ADL, respectively, with the ports conjugately matched according to some embodiments. For a device with 20 cells, an IL of 1.3 dB and a 3 dB FBW of 4.2% can be expected, while an IL of 3.9 dB and an FBW of 16% can be obtained for a device with five cells. FIG.22Dis a graph illustrating the group delay according to one embodiment. Simulated group delays are shown inFIG.2D. Delays from 25 to 45 ns can be obtained with longer delays which may be induced by longer acoustic wave propagation distances in devices with more cells. The ripples in delay may likely be caused by the multi-reflection between the transducers. The absolute delay value and the origin of the ripples will be discussed below. FIG.22Eshows the extracted IL and FBW, illustrating their tradeoff according to one embodiment. The tradeoff between IL and FBW for an ADL platform is shown inFIG.22E. The simulation results indicate a substantially improved trade space that can lead to low IL over a broad BW. For providing delays for SIC, a priority should be placed on providing low IL for adequately wide FBW. Based on the one demonstration of SIC, 4% FBW (20 cells) may be selected as an exemplary design prototype. FIGS.23A-23Dare a set of graphs illustrating simulated performances of the gigahertz S0 ADLs with 6.4-μm cell length, the same number of SPUDT cells of 20, but different gap lengths varying from 0.1 to 0.8 mm according to some embodiments. The effects of the gap length can be studied by simulating designs with the same number of cells (N=20) but different gap lengths varying from 0.1 to 0.8 mm. The study can allow insights towards an accurate prediction of the delays of different ADL designs. The other parameters of the simulated structure may be left the same as the previous group of ADLs. FIGS.23A-23Bare graphs illustrating the simulated IL and the RL of the ADLs with conjugately matched ports and various gap lengths according to some embodiments. It can be seen inFIG.23Athat an IL around 1.1 dB and an FBW of approximately 4.2% are obtained for different devices with various gap lengths, which may be due to the lossless nature of the simulation setup. FIG.23Cis a graph that illustrates the simulated group delay of the ADLs with various gap lengths according to one embodiment. ADLs with more considerable delay lengths may lead to longer delays, as summarized inFIG.23D. FIG.23Dis a graph illustrating the extracted group delay and the frequency spacing between the ripples, showing that the multi-reflections due to finite directionality may be the source of the ripples in the group delay according to one embodiment. The group delay τ can be approximated as τ≈(Lg+N·λ)/vo(42) where Lgis the gap length, N is the cell number, λ is the cell length, and vois the phase velocity of S0 mode in LiNbO3thin film with the electrically open-surface boundary condition. As shown in2210, an extracted vocan be 7238 m/s, which may be equivalent to providing 0.14 μs/mmin S0 ADLs. Another observation is that the frequency spacing between ripples may be smaller for more extended devices. Upon analyzing the frequency spacing quantitatively, e.g., see2210, the relation between the ripple spacing Δfspand the delay τ can be summarized as Δfsp≈12τ.(43) Such a conclusion indicates that the ripples can be caused by highly partial standing waves (with low standing wave ratio) formed between the two sets of IDTs on opposite ends. However, such effects may be less severe in an SH0 ADLs on the suspended LiNbO3thin films. The more subdued ripples may largely be a result of the higher damping of SH0 acoustic waves, which can significantly lower the quality factor Q of such a mode and mitigate the local group delay fluctuations. The simulations show the target performance of S0 ADLs for SIC applications, and may validate the enhanced design space of the new platform. However, scaling S0 ADLs toward the gigahertz range may not merely reduce the cell length, which is the same as the S0 mode wavelength. The presence of other spurious modes may create new challenges for attaining high-performance gigahertz ADLs. FIGS.24A-24Care a set of graphs that illustrate simulated performance of gigahertz S0 ADLs with different center frequencies according to some embodiments. Different ADLs can include the same number of SPUDT cells of 20, the same gap length of 0.1 mm, but different cell length varying from 6.8 to 3.2 μm.FIG.24Dis a graph that illustrates main passbands and mode shape of each mode, according to one embodiment. Main passbands can also be identified for each embodiment and the mode shape of each mode is shown inFIG.24D. To illustrate some challenges of scaling S0 ADLs toward higher frequencies, a group of devices with the same gap length (0.1 mm) and number of cells (20), but different cell lengths (6.4 to 3.2 μm) can be simulated using FEA for an 800-nm film. The simulation results are shown in the graph ofFIG.23Dwith port impedance conjugately matched for the S0 mode. Six significant modes can exist in a frequency range from 500 to 3000 MHz, and a passband can be created from each mode. As presented inFIG.23D, different modes may be identified with the displacement mode shapes obtained from FEA. The center frequencies of different bands can scale up with shorter cell lengths. However, as highlighted inFIG.24C, the spacing between the S0 and A0 modes may be significantly reduced for higher frequency ADLs. In the case of a 3.2-μm cell length on the 800-nm thin film, e.g., seeFIG.24C, the S0 and A0 passbands can merge. In the overlapped passband, both the IL and RL may degrade because part of the signal can be coupled into the low k2A0 mode and may travel at a different group velocity. It thus may not be adequately reflected by the embedded acoustic reflectors designed for S0 to achieve unidirectionality in the SPUDT transducers, which may result in more loss that may be absent in non-overlapping cases. Such a mode overlapping phenomenon can limit the available BW of the S0 ADL. FIGS.25A-25Bare a set of graphs that illustrate dispersion curves of an S0 mode and an A0 mode with different wavelengths in LiNbO3thin films with various thicknesses according to some embodiments. The A0 mode may be influenced more by the film thickness than the S0 mode. When the A0 dispersion curves become close to the S0 mode, the available FBW of the S0 mode may be reduced. The dispersion curves of S0 and A0 mode in a transducer cell are presented inFIG.25AandFIG.25B, respectively, for LiNbO3films with different thicknesses. The curves can be obtained using eigenmode FEA on a single cell with periodic boundary conditions in both the electrical and mechanical domains. As shown inFIG.25A, reducing the wavelength from 6.4 to 3.2 μm can result in the increase of the center frequency of the S0 mode from 1 to 2 GHz. Moreover, the dispersion curves of the S0 mode show a weak dependence on the thickness-to-wavelength ratio. For the ADLs described herein, a thicker film can lead to a higher compound phase velocity in the transducer. The dispersion curves of the A0 mode also show a similar trend, e.g., a shorter wavelength and a thinner film may lead to a lower center frequency as shown inFIG.25B. The S0-mode dispersion curves are plotted on the same figure, and show an overlapping of both modes for certain film thickness. It can be seen that a thinner film can provide a much larger space for scaling up the operating frequency. However, it may be nontrivial to micro-fabricate the long ADLs (lengths up to several millimeters may be required for adequate delays) on thin films. Therefore, it may require some consideration of the attainable operating frequency and the in-house fabrication capabilities. An 800 nm thin film can be used for demonstrating S0-mode ADL prototypes between 1 and 2 GHz. Note that it may be feasible to scale the S0-mode ADLs to even higher frequencies. FIGS.26A-26Dare a set of graphs that illustrate S0-mode propagation characteristics in an X-cut or Y-cut LiNbO3film around 1 GHz according to some embodiments.FIG.26Ashows phase velocities of the S0 waves in an electrically open LiNbO3thin film (vo) and an electrically short LiNbO3thin film (v5).FIG.26Bshows slowness curves of the S0 mode in electrically open and short LiNbO3thin films.FIG.26Cshows calculated power flow angle.FIG.26Dshows calculated coupling coefficient k2of the S0 mode. The description thus far has been based on a plane wave simplification. Such an assumption may only be valid when the launched acoustic waves propagate perfectly perpendicular to IDTs in the cut plane and do not have a wave vector component along the transverse direction. In other words, it requires the wave-front to propagate in alignment with the energy transportation direction. Therefore, it may be necessary to examine these two wave propagation directions in an actual ADL structure. The wavefront propagation direction can be shown to be the same as that of the phase velocity vp, which can be described as vp={circumflex over (k)}ω/|k|(44) where ω is the angular frequency, k is the wave vector, and {circumflex over (k)} is the unit vector of k. The energy transportation direction can be generally proved to be in the same direction as the group velocity vgof acoustic waves, which is described as vg={right arrow over (∇)}ω (45) which means the gradient of the angular frequency co as a function of the wave vector k. The angle between vpand vgcan be defined as the power flow angle (PFA), pointing from vgto vp. PFAs of acoustic waves may not always be zero for anisotropic materials, such as LiNbO3. If the PFA is non-zero, the launched acoustic waves may propagate into the bus line regions (e.g., seeFIGS.19A-19B) when reaching the other end, and may be missed by the receiving IDTs. As a result, having a non-zero PFA may introduce more IL to the actual devices than predicted by the 2D simulation (e.g., seeFIGS.22and23). Therefore, the PFA should be examined for the S0-mode in X-cut or Y-cut LiNbO3to identify an in-plane orientation at which large k2and adequately small PFA can be accessed simultaneously. A slowness curve method developed for various acoustic applications may for calculating PFA for Lamb waves in thin piezoelectric films. The slowness curve is traced by the locus of the vector that is defined as the inverse of the phase velocity over the in-plane orientations, e.g., seeFIG.26A. The phase velocity direction of the S0 mode propagating along a given in-plane orientation can coincide with the radial vector pointing along the in-plane Euler angle. The direction of the group velocity can be normal to the slowness curve for all in-plane orientations, as shown inFIG.25A. In the depicted embodiment, the phase velocities vpof the S0 mode in X-cut or Y-cut LiNbO3at different in-plane orientations can be calculated. The S0 mode with a 6.4-μm wavelength in an 800-nm-thin film may be used as an example. In other embodiments, the wavelength can be chosen to be between 3.2 μm and 6.8 μm. COMSOL eigenmode FEA can be used for obtaining the phase velocities of the electrically open LiNbO3thin film (vo) and electrically short LiNbO3thin film (vs) at different in-plane orientations, e.g., seeFIG.26A. A phase velocity of approximately 6500 m/s can be obtained for the S0 mode in this film stack. vsmay be slower than vodue to a piezoelectric softening effect. The slowness curves for different boundary conditions are plotted inFIG.26Awith an example of PFA presented. Using the aforementioned method, PFA curves at different in-plane orientations for both boundary conditions are plotted inFIG.26B. Targeting the high k2of the S0 mode in X-cut or Y-cut LiNbO3, the PFA zero points near 30° to the +y-axis can be investigated, seeFIG.26D. In the electrically open case, the PFA reaches zero when the propagation direction is approximately 29.5° to the +y-axis. For the electrically short case, the PFA reaches zero at a propagation direction of approximately 33.2° to the +y-axis. Deviation from these angles can cause a non-zero PFA and a misalignment between the propagating acoustic wave and the receiving transducer direction, which may degrade the device performance. Moreover, the suspended structure itself can introduce more multi-reflections within the IDTs and between the etched transverse edges. FEA can be used to analyze the effects. FIGS.27A-27Care a set of graphs that illustrate simulated effects of a nonzero PFA on ADL performance according to some embodiments. The transmission coefficients (conjugately matched) for two groups of S0-mode ADLs with different in-plane device orientations at 30° to +y-axis with a PFA of −0.27° and 35° to +y-axis with a PFA of −2.88 are shown (e.g.,FIG.27AandFIG.27Brespectively).FIG.27Cshows displacement mode shapes for devices at different orientations and PFAs. A larger deviation from the zero PFA can lead to larger ILs for certain gap widths as the guided acoustic waves may miss the output transducers in their zig-zag paths. To better illustrate the effects of a non-zero PFA, two groups of S0 ADLs with different in-plane orientations can be simulated with COMSOL FEA. In the 3D model, the total width of the ADL can be 86 μm. The aperture width, defined as the overlap length between the electrodes (e.g., seeFIGS.19A-19B), can be 50 μm. The other dimensions can be the same as those for the 2D simulation in reference toFIG.23. The mechanical boundary conditions in the transverse direction are set to be free, while perfectly matched layers are used at the two ends in the longitudinal direction. For ADLs orientated 30 to the +y axis (e.g.,FIG.27A), the displacement mode shape shows that most of the power can still propagate toward the receiving transducer (e.g., seeFIG.27C) due to a small PFA of −0.27° at this orientation. In comparison to the results obtained from the 2D simulation (e.g., in reference toFIG.23), the slight degradation of IL for longer ADLs can be due to the minor wave scattering into the bus line area where IDTs may not be present to effectively collect the power carried by the waves. In contrast to devices orientated 30° to the +y-axis, devices orientated 35° to the +y-axis (e.g., seeFIG.27B) may show a significant directional deviation in energy transportation as seen from the displacement mode shape (e.g., seeFIG.27C) to a larger PFA of −2.88°. The launched acoustic waves may therefore impinge upon the transverse free boundaries of the suspended thin film and follow a reflection-induced zig-zag path down the waveguide. Due to the existence of the transverse free boundaries, a longer ADL can potentially perform better than a shorter ADL, e.g., the 1.8-mm device inFIG.27B, if the reflected waves coincidentally get collected by the output IDTs. Nonetheless, to avoid complications and attain low IL for different lengths, the ADLs should be aligned to the zero PFA orientation as close as possible. It is also noteworthy that the PFA issue can be potentially mitigated using slanted transducers. In summary, the significantly improved FBW-IL trade space is theoretically shown in the new platform, and may promise superior gigahertz ADLs for SIC applications. Next, the design of S0 SPUDT is presented, with the two relevant parameters, namely, the number of cells and gap length, explored for determining the center frequency, IL, FBW, and delay of the ADLs. Potential challenges in scaling S0-mode ADLs to higher frequencies have been identified, and an approach considering both the targeting frequencies and fabrication process has been developed. FIG.28is a flowchart of a method2800of fabricating a gigahertz S0-mode ADL according to one embodiment. The ADL can be fabricated with the method2800. An X-cut or Y-cut LiNbO3thin film of 800 nm on a 4 inch Si wafer can be provided by NGK Insulators, Ltd., for this fabrication process. First, the electrodes can be defined with e-beam lithography to create feature sizes as small as 400 nm (step2801). Then, 135 nm-thick aluminum electrodes can be patterned using sputtering and lift off (step2803). Aluminum can be chosen for its good conductivity for lowering the electrical loss and also its compatibility with the following steps. The thickness of the electrodes can be chosen within the limit of an e-beam photoresist-based lift-off process. Next, a 2-μm SiO2layer can be deposited using plasma-enhanced chemical vapor deposition (PECVD) and patterned with fluorine-based reactive ion etching (RIE) (step2805). The release windows in the LiNbO3film can be subsequently etched using chlorine-based inductive coupled plasma (ICP-RIE) (step2807). The remaining SiO2can then be removed with low-power ICP (step2809). Finally, the ADLs can be released with isotropic XeF2etching (step2811). In this process, the diced sample can have a side aligned with the +y-axis of the LiNbO3material. The ADL orientation is preset in the lithography mask with each ADL tilted 30° with respect to the reference +y-axis on the mask. In the implementation, the reference axis on the mask may be aligned to the side of the sample that was aligned with the +y-axis of the LiNbO3crystal. FIGS.29A-29Fare optical microscope images of fabricated ADLs according to some embodiments.FIG.29Ashows zoomed-out view,FIG.29Bshows the transducer, andFIG.29Cshows zoomed-in views of the longest fabricated device with a 6.4 mm gap.FIG.29Dshows a shorter device with a 0.2-mm gap.FIG.29Eshows a five-cell SPUDT test device for validating the effects of cell numbers.FIG.29Fshows a test structure for identifying the PL in a metalized LiNbO3thin film. Some relevant parameters are shown in Table 2 below. TABLE 2SymbolParameterValueSymbolParameterValueλCell length (μm)3.2-6.8LgGap length (mm)0.1-6.4ReElectrode ratio0.125WaAperture width (μm)50RrReflector ratio0.375WdDevice width (μm)86NNumber of cells5-20TAlAluminum thickness (nm)130LtTransducer length (μm)64-136TLNLiNbO3 thickness (nm)800 The optical images of the fabricated ADLs are shown inFIGS.29A-29Fwith the parameters marked in the figures. The longest fabricated ADL has a high aspect ratio (e.g., total length/aperture width) of 128 and shows no visible warping under a microscope, e.g.,FIG.29A, demonstrating adequate stress management in the fabrication. The SPUDT electrodes can be also defined with high fidelity in width and are highly uniform across cells e.g., seeFIG.29BandFIG.29C. Three relevant parameters of the ADL designs (number of cells, gap length, and cell length) can be investigated individually. The number of cells can vary from 5 to 20, e.g., seeFIG.29E. The gap length can vary between 0.1 and 6.4 mm, e.g., seeFIG.29D, which can provide delays ranging from 20 to 900 ns. The cell length can vary from 6.8 to 3.2 μm, covering center frequencies from 900 MHz to 2 GHz. Some test ADLs can also be fabricated to investigate the PL of the metalized LiNbO3thin film. Most of the fabricated ADLs exhibit flat surfaces and well-defined electrodes from optical inspection and perform as anticipated. The orientation of the fabricated ADLs can be optically identified to be 30.8° to the +y-axis. A slight deviation from 30° to the +y-axis may be caused by a slight misalignment in the fabrication. To fully break down the IL, attain empirical data on the PL of S0, and ultimately validate the simulated performance limits of ADLs as described above, different groups of devices can be fabricated. A summary of the fabricated ADLs is shown in groups from A to F in Table 2. For easy references and comparisons, the figures showing the simulation and measurement results of these groups are also listed in Table 2. Groups A and B are used for validating the relevant design parameters (number of cells and gap length) for determining the IL, FBW, and group delay. Group C is used to demonstrate scaling of lower frequency ADLs to the gigahertz frequency range. Groups D, E, and F are used to identify the PL of S0 mode at different conditions, which cannot be directly obtained by FEA. FIGS.30A-30Dare a set of graphs that illustrate the measured performance of the gigahertz S0 ADLs with the same 64-μm cell length, the same gap length of 0.2 mm, but different numbers of SPUDT cells (5-20) according to some embodiments. The fabricated ADLs can be measured with a vector network analyzer (VNA) at a power level of −10 dBm in dry air, and then conjugately matched in a Keysight Advanced Design System. The ADLs in Group A are designed to investigate the impact of the number of cells on the IL-FBW tradeoff. ADLs with the same cell length of 6.4 μm and the same gap length of 0.2 mm, but different numbers of SPUDT cells of 5, 10, and 20 can be fabricated. The measured IL and RL are shown inFIG.30AandFIG.30B, respectively, with the ports conjugately matched. For an ADL with 20 cells, an IL of 3.2 dB and a 3 dB FBW of 3.8% can be obtained, while for an ADL with five cells, an IL of 5.0 dB and an FBW of 17.4% are shown. The tradeoff between IL and FBW for S0-mode ADLs is shown inFIG.30D. Compared to the simulated results inFIG.22E, a slight degradation in IL can be observed. The IL-FBW may still be dramatically improved from SAW ADLs, allowing access to the previously forbidden design space for low-loss wideband ADLs and the SIC applications. The measured group delays are shown inFIG.30C. Delays from 25 to 45 ns are obtained, with longer delays which are induced by longer transducers with a larger number of cells. The frequency spacing between adjacent ripples may be inversely proportional to the group delay, as expected inFIG.22. The larger ripples in both the amplitude and the group delay of the ADLs with fewer cells may be caused by insufficient suppression of triple travel signals (TTSs) from the lower unidirectionality in the transducers. FIGS.31A-31Dare a set of graphs that illustrate measured S-parameters of the fabricated ADLs (N=20, λ=6.4 μm) with identical transducers but different Lg(0.2-6.4 mm) according to some embodiments. The ADLs in Group B are designed to investigate the effects of longer gap lengths. The ADLs in group B can include ADLs with identical transducers (λ=6.4 μm) but different gap lengths (0.2-6.4 mm). The performance shows an FBW of 4% and a minimum IL of 3.2 dB, e.g., seeFIG.31AandFIG.31B. Group delays between 40 and 900 ns can be obtained for different gaps, e.g., seeFIG.31C. The small ripples in the IL and the group delays may be caused by the finite directionality of the IDTs and the slight resonant nature of the SPUDT. The finite directionality can be improved by enhancing the reflectivity per transducer unit cell and achieving a further reduced TTS between the transducers. The slight resonant nature of the SPUDT can be mitigated using the optimization approaches developed for SAW SPUDT devices namely, optimizing the reflection and transduction functions simultaneously across the transducer. The IL of ADLs with different lengths can be further analyzed. Naturally, the IL can increase for longer delays, which is commensurate with the more damped signals reflected from a further distance in the SIC scheme.FIG.31Dshows the extracted PL in the dry air ambiance and phase velocity is 6.08 dB/μs and 7097 m/s. It should be noted that the PL extracted here may be a conservative estimation, because longer devices with a high aspect ratio over 128 may suffer from the non-zero PFA issue (even for a small PFA). The etched transverse free boundaries can help to confine the energy in the propagation path. FIGS.32A-32Care a set of graphs that illustrate measured performance of the gigahertz S0 ADLs with different center frequencies according to some embodiments. The ADLs have the same number of SPUDT cells of 20, the same gap length of 0.1 mm, but different cell lengths, corresponding to 6.8 μm inFIG.32A, 4.4 μm inFIG.32B, and 3.2 μm inFIG.32C. FIGS.33A-33Care a set of graphs that illustrate measured S-parameters of the ADLs (N=20, Lg=0.1 mm) with identical gap lengths but different λ (3.2-6.8 μm) or center frequencies according to some embodiments. The Group C ADLs can have the same gap length of 0.1 mm but different transducers (λ=3.2-6.8 μm). The wideband measurement results are shown in the graph ofFIGS.32A-32C. The transmission at higher frequencies has the same or similar trend regarding S0 and A0 modes as predicted by the simulation (e.g., seeFIG.24). For an 800 nm-thick 20-cell LiNbO3ADL, the S0 passband can show good performance up to 2 GHz. Various transducer wavelengths can result in passbands ranging from 0.8 to 2 GHz with FBWs around 4% (e.g.,FIG.33AandFIG.33B). An IL of 3.0 dB can be achieved for the 900 MHz ADL, while an IL of 5.2 dB can be attained for the 2 GHz ADL. The slightly larger IL for higher frequency ADLs can be caused by the larger electrical length for a given Lgat a higher frequency and the constant PL/A can be empirically observed over the said frequency range. As shown inFIG.33C, a delay as low as 20 ns can be demonstrated over the 0.8-2 GHz range. The slight ripples in the group delay may be caused by the multi-reflections in SPUDTs. FIGS.34A-34Dare a set of graphs that illustrate extracted propagation parameters of the gigahertz S0 mode acoustic waves according to some embodiments. The propagation characteristics of SO waves in LiNbO3thin film can be further investigated. The devices with different cell lengths can be fabricated and measured (Group D in Table 3), shown below. TABLE 3KEY PARAMETERS OF THE FABRICATED DEVICESCellGapNo.LengthLengthofSim.Meas.Index(μm)(mm)Cells(FIG.)(FIG.)CommentsGroup A6.40.25-2513No. of cellsGroup B6.40.2-6.420614Gap lengthGroup C3.2-6.80.120715-16Cell lengthGroup D3.2-6.40.1-6.420—17PL at differentfrequenciesGroup E5.20.1-1.620—18PL in metalizedthin filmGroup F6.40.2-6.420—19TCF, PL invacuum The phase velocity voand PL can be extracted from devices with different gap lengths. The extracted vois shown inFIG.34Awith a constant value of approximately 7000 m/s over the 1-2 GHz range in the 800 nm thin film. The PL at different frequencies is shown inFIG.34BandFIG.34Cusing three metrics, including PL per unit distance, PL per wavelength, and PL per unit time. Due to the non-zero PFA, the PL extracted here may be a conservative estimation. The longer ADLs in this group may suffer additional IL due to the transverse propagation of S0 waves (e.g., seeFIG.27). Therefore, the PL extracted here may be worse than the real cases. An increase of PL can be observed at higher frequencies. FIGS.35A-35Dare a set of graphs that illustrate measured S-parameters of the ADLs (N=20, λ=5.2 μm) with identical transducers but different gap lengths Lg(0.1-1.6 mm) covered with 135 nm of A1 according to some embodiments. The propagation characteristics of S0 waves in LiNbO3thin film ADLs with the metalized surface can be extracted for understanding the PL in the transducer cells where the metalized thin film might be the main damping contributor. The S-parameters for a group of ADLs (Group E) centered at 1185 MHz can measured, e.g., seeFIG.35A,FIG.35B, andFIG.35C. The extracted relevant parameters are shown inFIG.35D. Due to the piezoelectric softening effect, the phase velocity may be lower than that measured in an electrically open piezoelectric thin film. The measured vsis 6336 m/s. The extracted PL is 0.0017 dB/A, or 21.2 dB/μs, which may be much larger than the values in the electrically open thin film. Such a result implies that the metalized area may be a main contributor of the IL in the transducer sections of the ADLs. FIGS.36A-36Bare a set of graphs that illustrate a comparison of the measured IL and group delays of the S0-mode ADLs in vacuum and in air according to some embodiments.FIG.35Ashows the IL and group delay of an ADL (N=20, λ=6.4 μm Lg=0.2 mm) measured in vacuum and air.FIG.36Bshows the PL in vacuum and air extracted from a group of (N=20, λ=6.4 μm Lg=0.2-6.4 mm, Group F in Table 3). The devices in Group F can be measured in vacuum for testing the effects of vacuum ambiance on the ADL performance. The results are presentedFIG.36Afor an ADL and compared to the (N=20, λ=6.4 μm Lg=0.2 mm, ofFIG.29D). The different measurement environment brings little difference to the performance. The PL of these ADLs measured in air and vacuum is then compared inFIG.36B. The PL may slightly drop from 6.08 to 5.96 dB/μs. Therefore, it can be found that the air damping may not be the main loss in ADLs. FIGS.37A-37Dare a set of graphs that illustrate measured temperature dependence of an ADL (N=20, λ=6.4 μm Lg=0.2 mm) in vacuum according to some embodiments. Temperature dependence may be another factor in SIC applications for covering the entire operating temperature range of the front-end modules. Therefore, one ADL in Group F can be measured at different temperatures, ranging from 295 to 355 K. The conjugately matched results are shown inFIG.37A,FIG.37B, andFIG.37C, with both the transmission, reflection, and group delay plotted. The passband can drift to lower frequencies due to the negative temperature coefficient of stiffness of the LiNbO3film. The temperature coefficient of the center frequency (TCF) is plotted inFIG.37D, showing a TCF around-59.69 ppm/K. The result shows good linearity over the measured frequency range. The TCF is close to the previously reported TCF in S0-mode X-cut or Y-cut LiNbO3. The temperature coefficient of delay may be challenging to extract accurately due to the existence of ripples in the group delay measurements. Based on the FEA simulation that has been validated by measurements and the experimental extracted results, the IL of the gigahertz S0 ADLs can be broken down for identifying the space for future improvement (Table 4). TABLE 4EXAMPLES OF IL BREAKDOWNDamping Source0.2 mm ADL IL6.4 mm ADL ILFinite Uni-directionality1.3dB1.3dBPL in Transducers0.25dB0.25dBPL in Waveguide0.17dB5.5dBOthers (Including Electrical1.4dB1.85dBLoading & Non-zero PFA)Total3.2dB8.9dB A pair of ADLs in Group A can be studied as examples, one with a 0.2 mm gap length (e.g.,FIG.29D) and the other one with a 6.4 mm gap length (e.g.,FIG.29A). For the 0.2 mm ADL, the first damping contributor may be the finite unidirectionality in the transducers. Based on the FEA of a lossless structure (e.g.,FIG.22), 1.3 dB may be from such an effect. The second damping source may be the PL in the transducers, which can be calculated from the extrapolated delay in the transducers and the PL in LiNbO3thin-film sections with and without electrodes. A total of 0.25 dB may be due to the PL in the transducers. The third damping term may be the PL in the waveguide between the transducers. For the 0.2 mm ADL, the loss is 0.17 dB. Finally, the last 1.4 dB IL may be collectively caused by the electrical loading of the IDTs and the non-zero PFA. Similarly, the IL breakdown of the 6.4 mm ADL is shown in the Table 4, with the PL in the waveguide which may be the main loss contributor. In summary, low-loss wideband gigahertz S0-mode ADLs may offer a significantly improved FBW-IL tradeoff for an S0-mode ADL. The design parameters of S0-mode ADLs, including cell number, gap length, and cell length, have been investigated through simulation. The fabricated miniature ADLs show an FBW of 4% and a minimum IL of 3.2 dB at a center frequency of 0.96 GHz. Various delays ranging from 20 to 900 ns can be obtained for digitally addressable delay synthesis. Multiple ADLs with center frequencies from 0.9 to 2 GHz can be fabricated. The PL of the S0 mode in the gigahertz frequency range can also be experimentally measured, showing a PL of 6.08 db/μs at 0.96 GHz or 0.0055 db/). (dB per wavelength). The PL at different frequencies, measured conditions, and electrical boundary conditions can be experimentally extracted. The demonstrated ADLs can provide wide-range and high-resolution reconfigurable delays for future SIC applications. SH0-Mode Lithium Niobate Acoustic Delay Lines The emerging enhanced mobile broadband (eMBB) applications for fifth-generation (5G) communication may require unprecedented signal processing capabilities. Acoustic devices, in which RF signals may be converted into and processed in the acoustic domain before the conversion back to the electromagnetic (EM) domain, can be great candidates for providing low-loss wideband signal processing capabilities for at least three potential advantages. First, acoustic devices are small because of their significantly shorter wavelength (λ) compared to their EM counterparts, and therefore may be suitable for handheld and mobile applications. Second, various signal processing functions can be passively implemented by designing a transfer function of transducers and waveguides. Thus, acoustic devices do not compete with the power-hungry analog-to-digital converters (ADC) and digital signal processors (DSP) in the follow-on stages for the power budget. Third, recent demonstrations of low-loss and high electromechanical coupling (k2) piezoelectric platforms can allow for low loss over a wide bandwidth (BW), thus potentially overcoming the high loss and narrow bandwidth bottleneck that has currently precluded acoustic signal processing from eMBB applications. For some RF acoustic devices, acoustic delay lines (ADLs) can be used for a wide range of applications, including transversal filters, correlators, time-domain equalizers, oscillators, sensors, and time-varying non-reciprocal systems. In some embodiments, ADLs can be built based on surface acoustic wave (SAW) platforms. The performance of SAW ADLs, namely the substantial insertion loss (IL) and the narrow fractional bandwidth (FBW), may be fundamentally curbed by the moderate k2and achievable reflectivity of the transducers, even in designs targeting low loss such as single-phase unidirectional transducers (SPUDTs). In other embodiments, ADLs can be based on longitudinal modes in lithium niobate (LiNbO3) thin films. Such ADLs can be implemented to support fundamental shear-horizontal (SH0) modes or fundamental symmetrical (S0) modes, and may show a significantly improved IL-FBW design space. The enhanced performance may be collectively enabled by large k2(e.g., up to 40%), the notable reflectivity in the embedded reflectors, and the low propagation loss (PL) in single-crystal quality LiNbO3thin films. It can be challenging to achieve broadband performance with some ADLs for at least two reasons. First, although a large FBW can be obtained, the absolute BW of the demonstrations may be limited because of their low center frequencies below 500 MHz. Second, the FBW of the high-frequency S0 mode demonstrations may also be limited by their adjacent modes that can cause the overlap of passbands. Therefore, to achieve broadband ADLs, it may be necessary to first identify a suitable acoustic mode with large k2, low loss, sufficient spectral clearance to adjacent modes, and scale to the GHz frequency range. Among various candidates, the SH0 mode in X-cut LiNbO3is promising. Some SH0 ADLs can have high k2and low loss at lower frequencies. Moreover, high-frequency SH0-mode acoustic devices can have a sparse mode-space. However, due to the highly dispersive characteristics of the mechanical modes in thin-film LiNbO3, it can be non-trivial to scale up the operating frequency. In some embodiments, the SH0-mode ADLs show 3 dB FBW may range from 4% to 34.3%, and IL between 3.4 dB and 11.3 dB. Multiple ADLs can have center frequencies from 0.7 GHz to 1.2 GHz. The PL of an SH0-mode ADL at 1.08 GHz can be extracted as 0.0182 dB per wavelength (dB/λ), and the phase velocity is 4255 m/s. The SH0-mode ADLs can potentially facilitate broadband applications at the GHz range. FIG.38Ais a schematic of an SH0 mode ADL3800according to one embodiment. The SH0-mode ADL can have a pair of single-phase unidirectional transducers (SPUDTs)3816aand3816baccording to one embodiment. The SH0-ADL can include a piezoelectric thin film3802located above a carrier substrate. The piezoelectric thin film3802can be an X-cut or Y-cut LiNbO3thin film adapted to propagate an acoustic wave within the piezoelectric thin film in at least one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, a fundamental shear-horizontal (SH0) mode, or a first-order antisymmetric (A1) mode excited by an electric field oriented in a longitudinal direction along a length of the piezoelectric thin film; or a first-order antisymmetric (A1) mode or a first-order shear-horizontal (SH1) mode excited by the electric field oriented at least partially in a thickness direction (e.g., mutually perpendicular to the longitudinal and transverse directions indicated in3800) of the piezoelectric thin film3802. In some further embodiments, the Y-cut LiNbO3thin film includes one of a 128Y-cut, 54Y-cut, or 36Y-cut LiNbO3thin film and the second mode includes one of a first-order symmetric (S1) mode. In some cases, the rotated Y cuts can also additionally propagate the acoustic wave in at least one of the first modes (S0, S1, SH0, and A1) excited by the electric field oriented in the longitudinal direction or one of the second modes (A1 and SH1) excited by the electric field oriented at least partially in the thickness direction. In various embodiments, a first interdigitated transducer (IDT)3816abe disposed on a first end of the piezoelectric thin film3802. The first IDT3816acan convert a first electromagnetic signal, traveling in the longitudinal direction, into the acoustic wave. A second IDT3816bcan be disposed on a second end of the piezoelectric thin film with a gap3810(Lg) between the second IDT3816band the first IDT3816a. The second IDT3816bcan convert the acoustic wave into a second electromagnetic signal. In some embodiments, the ADL3800can support at least one of an S0, S1, S2, SH0, SH1, A0, A1, or A3 mode. In the present disclosure, as an illustrative example, the ADL includes 135 nm aluminum IDTs on top of a suspended 800 nm X-cut or Y-cut LiNbO3thin film (e.g, the piezoelectric thin film3802). In some embodiments, the piezoelectric thin film3802can be suspended above a carrier substrate. In other embodiments, the piezoelectric thin film3802can be disposed on a high acoustic impedance layer interposed between the piezoelectric thin film3802and the carrier substrate. The high acoustic impedance layer can be composed of at least one of silicon (Si), sapphire, fused silica, quartz, silicon carbide (SiC), diamond, aluminum nitride (AlN), aluminum oxide (Al2O3), tungsten, molybdenus, platinum, or combindations thereof. In other embodiments, the piezoelectric thin film3802can be disposed on a Bragg reflector interposed between the piezoelectric thin film3802and the carrier substrate. The Bragg reflector can be composed of a set of alternating layers including a first layer with a first acoustic impedance (e.g., a high acoustic impedance layer) and a second layer with a second acoustic impedance (e.g., a low acoustic impedance layer). The second acoustic impedance may be lower than the first acoustic impedance. In some embodiments, the SH0 ADL3800further includes a waveguide3860inside of which is disposed of the piezoelectric thin film3802, the first IDT3816a, the second IDT3816b, a first port3820coupled to the first IDT3816a, and a second port3822coupled to the second IDT3816b. The first port3820is to receive the first electromagnetic signal and the second port3822is to output the second electromagnetic signal. The first IDT3816acan be an input transducer in order to convert an RF signal into an acoustic signal. The first IDT3816acan include an input ground line3818a, and an input signal line3828a. The input ground line3818acan be coupled to an input ground transduction electrode3824aand an input acoustic reflector3832a. In some embodiments, the input ground line3818acan be coupled to more than one input ground transduction electrode3824aand more than one input acoustic reflector3832a. The input signal line3828acan be coupled to an input signal electrode3826a. In some embodiments, the input signal line3828acan be coupled to more than one input signal electrode3826a. The first IDT3816a(e.g., the input transductor) can serve as an input port3820(e.g., PORT 1) for an input signal (e.g., an RF signal). The second IDT3816bcan be an output transducer in order to convert the acoustic signal into an EM signal. The second IDT3816bcan include an output ground line3818band an output signal line3828b. The output ground line3818bcan be coupled to an output ground transduction electrode3824band an output acoustic reflector3832b. In some embodiments, the output ground line3818bcan be coupled to more than one output ground transduction electrode3824band more than one output acoustic reflector3826b. The output signal line3828bcan be coupled to an output signal electrode3826b. In some embodiments, the output signal line3828bcan be coupled to more than one output signal electrode3826b. The second IDT3816bcan be an output port3822(e.g., PORT 2) for an output signal (e.g., an EM signal). A gap length3801(Lg) can be defined as the distance between the first IDT3816aand the second IDT3816b. In some cases, the gap length3801can range between 0.1 mm and 6.4 mm. In other cases, the gap length3801can range between 0 mm to several centimeters. In other embodiments, the first IDT3816acan be the output transducer and the second IDT3816bcan be the input transducer. The ADL3800can be oriented at 10° with respect to the +y-axis of the X-cut or Y-cut LiNbO3in order to take advantage of the high phase velocity and large coupling of the SH0 mode. In some other embodiments, the device may be oriented at an angle between −10° to 30° with respect to the positive y-axis of the thin film. FIG.38Bis a schematic diagram of a transduction unit cell3830of an SH0 mode ADL according to one embodiment. In some embodiments, the transduction unit cell3830is a SPUDT. In some embodiments, the first IDT3816acan be composed of at least one transducer unit cell3830. The transducer unit cell3830can include a ground line3818coupled to the first port3820, acoustic reflectors3832aand3832bcoupled to the ground line3818, a first transduction electrode3824coupled to the acoustic reflectors3832aand3832b, and to the ground line3818of the first port3820, a signal line3828coupled to the first port3820, and a second transduction electrode3826coupled to the signal line3828and disposed between the acoustic reflector3832aand the first transduction electrode3824c. A center of the second transduction electrode3826can be defined as a transduction center3840. A back part (e.g., back half in one example) of the acoustic reflector3832ais positioned at a first end of the transducer unit cell3830at a first distance away from the transduction center3840, and a front part (e.g., front half in one example) of the acoustic reflector3832bis positioned at a second end of the transducer unit cell3830at a second distance away from the transduction center3840. The second distance is different from the first distance. In other embodiments, the second distance is between 40% and 95% greater than the first distance. The second transduction electrode3826is disposed between the front part of the acoustic reflector3832aand the first transduction electrode3824. As such, the transduction unit cell3830is between the reflection center3842aand the reflection center3842b. In some embodiments, the transducer unit cell3830is a transducer unit cell of the SH0-mode ADL3800ofFIG.38A. In some embodiments, the first IDT3816aand the second IDT3816bon opposite ends of the ADL3800are SPUDTs. The first IDT3816aand the second IDT3816bcan be composed of cascaded transducer unit cells3830that each includes a pair of transduction electrodes3824and3826(that are both λ/8 wide) and a distributed acoustic reflector composed of a back part (e.g., a back half in one example) of the acoustic reflector3832aand a front part (e.g., a front half in one example) of the of acoustic reflector3832b. Each acoustic reflector3832aand3832bis (3λ/8 wide) and shorted to the ground line3818. In each transducer unit cell3830, the two acoustic reflectors3832aand3832bcan be arranged on opposite sides of transduction center3840non-symmetrically with different spacings of 3λ/8 and 5λ/8 respectively. The transduction center3840referred to herein is defined as the center of the second transduction electrode3826(e.g., the non-grounded electrode or the signal electrode). In some embodiments, a width of the back half of the acoustic reflector3832aand a width of the front half of the acoustic reflector3832bare less than four times greater than a width of the transduction electrodes3824and3826. In various embodiments with continued reference toFIG.38B, after launching from the transduction center3840, the acoustic wave propagating toward the left (e.g., the backward direction (BWD)3805) can get partially reflected from the acoustic reflector3832aand can start traversing in the forward (FWD) direction3803, e.g., towards the right. As the reflected acoustic wave returns to the transduction center3840, it may experience a total of −2π phase delay that results from a −1.5π phase delay from the propagation and a −0.5π phase delay from the reflection. In this way, the reflected acoustic wave can constructively interfere with the acoustic wave launched directly toward the FWD direction3803. On the other hand, the acoustic wave propagating toward the FWD direction3803can get partially reflected from the acoustic reflector3832aand can start traversing in the BWD direction3805, e.g., towards the left. As the reflected acoustic wave returns to the transduction center3840, it can experience a −2.5π phase delay from the propagation and a −0.5π phase delay from the reflection. The signal (e.g., the reflected acoustic wave) can experience a total delay of −3π upon its arrival back to the transduction center3840and can destructively interfere with the acoustic wave launched directly toward the BWD direction3805. With a sufficient number of cascading reflections distributed in the unit cells, a near (e.g., approximately) perfect cancellation of the BWD wave propagation can be achieved, which can result in an effective removal of the bi-directionality in the transducers and a 6-dB reduction in the IL of the ADL. For illustrative purposes, the SH0 mode ADL3800can include 135 nm aluminum IDTs on top of a suspended 80-nm LiNbO3thin film. In other embodiments the IDTs be composed of at least one of Au, Mo, Al, Pt, or other suitable conductive material. In other embodiments, the thickness of the IDTs may be between 5 nm to 10 μm and the thickness of the thin film can be between 30 nm to 100 μm. A pair of free boundaries can exist in the transverse direction for defining the acoustic waveguide. A pair of IDTs3816aand3816bcan be located on opposite ends of the ADL3800. The IDTs3816aand3816bcan be composed of cascaded transducer unit cells (e.g.,3830), and each transducer unit cell includes a pair of transduction electrodes3824and3826that are each λ/8 wide and one grounded distributed acoustic reflector composed of half of acoustic reflector3832aand half of acoustic reflector3832b. Each acoustic reflector3832aand3832bis 3λ/8 wide. A transduction center3840is located at the center of the transduction electrode3826because the gap3801between two grounded electrodes causes no transduction. The reflection centers3842aand3842bare located at a center of the acoustic reflectors3832aand3832b, respectively, because the pair of λ/8 electrodes3824and3826causes no reflection based on the multi-reflection theory. In each transducer unit cell3830, the transduction center3840can be located non-symmetrically from the acoustic reflectors3832aand3832bon both sides. The non-symmetry can cause a difference in the phase delay of the acoustic wave reflected from the acoustic reflectors3832aand3832bon both sides. It can be shown that the reflected acoustic wave propagating towards the FWD direction3803can constructively interfere with the acoustic wave launched directly towards FWD direction3803, while the reflected acoustic wave propagating towards the BWD direction3805can destructively interfere with the acoustic wave launched directly towards BWD direction3805. Thus, with a sufficient number of cascaded acoustic reflectors, substantial cancelation of the BWD wave propagation can be achieved, which can result in an effective removal of the bi-directionality in the transducers and an IL reduction of the ADL. FIGS.39A-39Dare a set of graphs that illustrate the simulated characteristics of SH0-mode ADLs at different in-plane orientations in a 0.8 μm-thick X-cut LiNbO3thin film according to some embodiments.FIG.39Aillustrates the phase velocity with electrically open and short boundary conditions,FIG.39Billustrates k2,FIG.39Cis the slowness curve, andFIG.39Dillustrates a power flow angle of SH0-mode ADLs at different longitudinal wavelengths. In the depicted embodiment, the GHz SH0-mode ADLs are oriented at −10° with respect to the +Y-axis in X-cut or Y-cut LiNbO3for two reasons. First, the SH0 mode in such orientation can take advantage of a large k2. The dependence of k2on the in-plane orientation can be analyzed via finite element analysis (FEA) in COMSOL as shown inFIG.39A, starting from the phase velocities of SH0 acoustic waves under electrically open and short boundary conditions. The phase velocity of the thin film with electrically short boundary conditions (vm) may be smaller than that of the electrically open boundary condition (vf), which can be caused by the piezoelectric softening effect. The dispersion of the SH0 acoustic wave near 1 GHz is also plotted inFIG.39A. SH0 modes at a larger wavelength A may have a slower phase velocity in an electrically shorted LiNbO3film (3684-3853 m/s) while SH0 modes in an electrically open film may be barely dispersive (4504 m/s). The k2can then be calculated with the obtained phase velocities. The maximum k2can be obtained at an angle of −10° with respect to the +Y-axis as shown inFIG.39B. Consistent with the dispersion of vp, lower frequency SH0-mode acoustic waves (e.g., with larger λ) can have a slightly larger k2(40% at 1 GHz). The second reason for the selected orientation can be to attain a small power flow angle (PFA) for the SH0-mode acoustic waves, consequently enabling ADLs with longer delays. The PFA is defined as the angle between the phase velocity and the group velocity (pointing to the phase velocity). PFAs for acoustic waves in anisotropic materials (e.g., LiNbO3) may not always be zero. If the PFA is significant, the acoustic waves launched in an ADL can bounce between free boundaries in the transverse direction (e.g., seeFIG.38). For ADLs with longer delays, the acoustic energy might leak out from the bus line area (without SPUDTs for collecting the energy). The PFA can be derived from the slope of the slowness curve shown inFIG.39Cof GHz SH0 waves as and presented inFIG.39D. The PFA of SH0 in the film with electrically open and short conditions can have different signs near the orientation with the highest k2. The PFA of SH0 in a LiNbO3film with the electrically open condition can reach zero at −11° to +Y, while PFA for that with the electrically short condition can reach zero at −6° to the +Y-axis. The dispersion phenomena can also be observed, but the crossover points are similar. To summarize, due to the large k2and small PFA, GHz SH0 ADLs can be oriented at −10° to the +Y-axis in X-cut LiNbO3. FIGS.40A-40Bare a set of graphs that illustrate the performance trade-off between minimum IL and FBW of SPUDT in various platforms according to some embodiments. The design space below each curve represents a forbidden region for a platform with such characteristics. The graph ofFIG.40Ashows the performance trade-off between minimum IL and FBW of SPUDT in various platforms with different coupling coefficients.FIG.39Bshows illustrate the performance trade-off between minimum IL and FBW of SPUDT in various platforms with different reflectivity per wavelength. Based on the structure introduced inFIG.37, the performance limitations of GHz SH0 ADLs can be evaluated. As stated in the introduction, both the performance limitations of the SH0 ADL and the frequency spacing of SH0 to the adjacent modes at GHz may be a factor for broadband applications. This subsection will investigate both aspects. Two performance bounds, namely the piezoelectric limitation and the reflectivity limitation, can define the performance of SPUDT-based ADL. The piezoelectric limitation can set the maximum 3 dB-FBW that a device can achieve without trading off IL. The maximum FBW can be directly related to k2of the intended mode and the effective coupling efficiency of the transducer in the chosen platform. The limitation can be presented as: IL=FBW2·QT/cpiezo,whenFBW>cpiezo/QT(46)wherecpiezo=vf-vmv·[1+3(vf-vm)2v].(47) And where QTis the normalized quality factor of the transducer and can be determined by the transduction structure. cpiezois the material piezoelectric constant and can be determined by the material coupling coefficient. Especially for a design with a λ of 3.6 μm, a QTof 0.659, vfof 4502 m/s, and vmof 3807 m/s, e.g., seeFIG.38A, the maximum coupling coefficient can be 40%. Therefore, the piezoelectric limit of GHz SH0 ADLs on the IL-FBW trade space can be plotted, with the forbidden region marked in grey, as shown inFIG.39A. It shows a significantly enlarged design space (up to 65%) when compared with a conventional piezoelectric platforms with lower k2(<10%). The second performance limitation may be caused by the finite attainable unidirectionality provided by the embedded reflectors. To achieve a certain IL, more reflectors (thus more cells) may be needed for a platform with less reflectivity per cell. An increased number of cells can lead to narrower bandwidth of the transfer functions (FBW−1/N). Such a performance bound can be expressed as: lL=1−e−Γλ/FBW, (48) where Γλis the reflection per wavelength and can be calculated based on the mechanically induced refection (Γm) and electrically induced reflection (Γe) as: Γλ=Γm+Γe1+Γm·Γe(49)Γm=Γsuejα1-e-j2α(1-Γsu2)1-Γsu2e-j2α(50)Γe=Γ0∞ejα1-e-j2α(1-Γ0∞2)1-Γ0∞2e-j2α,(51) where Γsuand Γ0∞are the step-up mechanical and electrical reflection coefficient in the interface between the metalized and un-metallized sections respectively. α is the electrical width of the reflector, which can be 3π/4 for a SPUDT according to one embodiment. Γsucan be extracted from the COMSOL FEA simulation, using a mechanical scattering parameter approach explained in. For one specific design with 135 nm Al on 800 nm LiNbO3, Γsuis −0.047. Thus, Γmcan be calculated as −0.066 j. The imaginary part may refer to a −90° phase difference for the reflected wave. Γ0∞can be extracted from vm, and vf. For vfof 4502 m/s, and vm, of 3807 m/s (e.g., seeFIG.38A), Γ0∞is −0.084. Thus, Γeis calculated to be −0.118 j. Using Eq. (49), Γλis −0.183 j. Such Γλmay be considerably larger than that of the incumbent SAW technology (−0.06 j), which may be collectively contributed to by the larger Γmfrom the larger k2and larger Γmfrom the suspended thin film structure. The design space is shown byFIG.39Bon the IL-FBW tradeoff figure with the forbidden region marked in grey. It can be seen that for GHz SH0 mode ADLs, the achievable reflectivity may be the limiting factor, and the minimum IL for ADLs with FBW of 4%, 8%, 16%, and 32% are 0.1 dB, 0.9 dB, 3.2 dB, and 7.2 dB, respectively, which have surpassed the theoretical limits of some SAW ADLs, according to some embodiments. It is noteworthy that these performance limits are first-order estimations based on the continuity approximation, and more accurate IL-FBW trade-off will be presented in the next subsection using FEA. FIGS.41A-41Care a set of graphs that illustrate dispersion curves of different modes in an 800 nm-thick X-cut or Y-cut LiNbO3thin film, sorted into symmetrical, shear, and asymmetric modes according to some embodiments. The achievable BW (SH0 mode) is highlighted inFIG.41A.FIG.41Bshows displacement mode shapes of different modes as labeled in the dispersion curve according to one embodiment.FIG.41Cshows extracted achievable FBW and BW with different λ according to one embodiment. An additional factor for enabling broadband ADLs may be the frequency spectral spacing between the mode of interest and the adjacent modes. If the passbands of the primary mode and the spurious modes partially overlap, the ADL performance degradation may occur for two causes. First, over the overlapped frequency range, the spurious modes may distort the transmission and reflection as part of the energy may be coupled into the undesired mode, introducing ripples in the scattering parameters. Second, the spurious modes may cause notable ripples in the group delay due to the fact that different modes can have different phase velocities and thus produce various group delays. FEA can be used to identify the dispersion curves of various modes in a single SPUDT cell with λ between 1.6 μm and 6.4 μm (SH0 eigenfrequency 0.6-2 GHz). Periodic boundary conditions can be applied to the longitudinal edges. The dispersion curves of asymmetric modes, shear modes, and symmetric modes are plotted inFIG.40Awith their displacement mode shapes presented inFIG.40B. Due to the dispersion of the modes in thin film LiNbO3, the spectral spacing between the SH0 and the first-order A0 modes may set the maximum FBW at shorter wavelengths, while the spectral spacing between the SH0 and second-order A0 modes may set the maximum FBW at longer wavelengths. The maximum achievable FBW can be quantitatively calculated based on the admittance transfer function of a pair of IDTs with the cell number N(>1), approximated as: |H(ω)|=ωh0e−jβL·sinc2(NtβWp), (52) where ω is the angular frequency, h0is a coupling constant related to the material properties and acoustic wave mode, L is the distance between the center of the transducers, Ntis the number of the transducer pitches, Wpis the pitch width, β is the wave vector (2π/λ), and sinc is the sampling function. Such an admittance transfer function follows the sinc-squared function, and the bandwidth is inversely proportional to N and independent of the k2of the mode. In other words, for an ADL with a specific topology, different modes can have the same bandwidth. Based on the above analysis, the maximum achievable FBW of GHz SH0-mode ADLs can be approximated as: FBWmax=2·min(fSH0-fA0fSH0+fA0′f2nd_A0-fSH0f2nd_A0+fSH0)(53) where fSH0, fA0, and f2nd_A0are the eigenfrequencies of the SH0, the A0, and the second-order A0 modes respectively. The calculated FBW is plotted inFIG.41C, reaching a maximum of 46.7% at λ=3.2 μm. The FBW can be above 30% for devices between 0.6 to 2 GHz, demonstrating a vast design space across different frequencies from 1 to 2 GHz as highlighted inFIG.41A. The absolute BW is also presented inFIG.4C, showing its increase towards the GHz frequency range and saturation at approximately 2 GHz which may be due to the decrease in FBW. The frequency at which the BW begins to saturate may be determined by the film thickness. Wider FBW and BW can be expected for higher frequency SH0 ADLs built on thinner LiNbO3films. For a first demonstration of broadband GHz SH0 ADLs, 800 nm LiNbO3may be selected based on fabrication capabilities. FIGS.42A-42Eare a set of graphs that illustrate the simulated performance of the GHz SH0 ADLs with a 36 μm cell length, the same gap length of 0.4 mm, but different numbers of SPUDT cells (3, 5, 10, and 20) according to some embodiments.FIG.42Ais the cross-sectional mode shape depicting the unidirectionality of the SPUDT transducers for an ADL with 20 cells and a gap length of 0.4 mm. It should be noted that as depicted, the thickness of the cross-section may be exaggerated.FIG.42Bshows the IL,FIG.42Cshows the RL,FIG.42Dshows the group delay, andFIG.42Eshows the extracted IL and FBW, illustrating their trade-off according to one embodiment. After theoretically investigating the design space of broad-band SH0 ADLs in LiNbO3, COMSOL FEA can be used to capture the intricacies and understand the frequency domain responses. Two-dimensional (2D) simulations can be set up with periodic boundary conditions applied to the transverse edges for both the mechanical and electrical domains. Perfectly matched layers can applied to the longitudinal ends of the ADL. The simulation assumes lossless conditions in both the electrical and mechanical domains. In the simulation, the film stack can be set as 135 nm-thick aluminum electrodes on an 800 nm-thick single crystal X-cut or Y-cut LiNbO3according to an embodiment. A can be set to be 3.6 μm, the gap length (Lg) can be 0.4 mm, while the cell number (N) can vary from 3 to 20.FIG.42Ashows the displacement mode shape of the ADL at the center frequency, demonstrating minimum power flow towards the BWD and thus validating the unidirectionality of the SPUDT.FIG.42BandFIG.42Cshow the simulated IL and RL with the ports conjugately matched, respectively. The IL-FBW trade-off can be clearly observed and is summarized inFIG.42E. For a 3-cell ADL, the IL can be 4 dB, and the 3 dB FBW can be 32.7%, while for 20 cell ADL, the IL can be 0.4 dB and the 3 dB FBW can be 4.6%. These results show an improved IL-FBW design space in comparison to state of the art (SOA) in one embodiment.FIG.42Dshows the group delays, exhibiting around 100 ns for the miniature ADLs shorter than 0.6 mm. The ripples in the passband may be caused by a combination of the internal reflections in the SPUDT and the lack of adequate unidirectionality in the SPUDT with fewer cell numbers. The group delay flatness can be further improved by weighting the transduction centers and reflection centers within a transducer and also by increased the reflectivity per reflector. To summarize, the SPUDT ADL design is first presented based on the analysis of k2, velocity, and PFA of SH0 at GHz. A maximum achievable FBW is then presented based on both the IL-FBW tradeoff of SPUDT designs (coupling and reflectivity limitations) and the analysis of the mode space. Finally, FEA can be used to investigate the design intricacies and to obtain the frequency response. FIGS.43A-43Fare optical microscope images of the fabricated SH0-mode ADLs according to some embodiments.FIG.43Ais a zoomed-out image of an ADL with a 20-cell SPUDT with a wavelength A of 36 μm, and a gap length Lgof 0.1 mm.FIG.43Bis a zoomed-out image of an ADL with a 3-cell SPUDT with A of 36 μm, and Lgof 0.4 mm.FIG.43C,FIG.43D,FIG.43E, andFIG.43Fare zoomed-in images of a SPUDT with N between 3 to 20 cells with A of 36 μm. The relevant parameters are shown in Table 5 below. TABLE 5SymbolParameterValueSymbolParameterValueλCell length (μm)3.2-5.2WaAperture width (μm)50NNumber of cells3-20WdDevice width (μm)86LgGap length (mm)0.1-1.6LTTransducer length (μm)10.8-104TLNLiNbO3 thickness (nm)800TAlAluminum thickness (nm)135 The devices may be in-house fabricated, according to one embodiment. An 800 nm X-cut LiNbO3thin film on a 4-inch Si wafer can be provided by NGK Insulators, Ltd. for the fabrication, according to one embodiment. The optical images of fabricated ADLs are shown inFIGS.43A-43F. The ADLs show no visible warping under a microscope, as shown inFIG.43AandFIG.43B. The SPUDT transducers may be well defined with high fidelity as shown inFIG.43CandFIG.43D. The relevant design parameters, in particular, the cell length (λ), the gap length (Lg), and the number of cells (N) are labeled, and their typical values are presented in Table 5. Five groups of SH0 ADLs, as shown in Table 5, are designed to provide an understanding of broadband performance space. ADLs in Group A have the same transducer design (λ and N) but different Lg, for identifying the propagation parameters of SH0 at gigahertz frequencies. Group B includes ADLs with the same N of 20 and Lgof 0.1 mm, but different), for exploring the frequency scalability and also validating the dispersion presented inFIG.41. The minimum A may be limited to 3.2 μm due to present fabrication capabilities. Groups C and D are similar to Group B, but with a different number of transducer unit cells N, in particular, of 10 and 5 respectively, demonstrating the dependence of IL and FBW on N. A set of ADLs with a maximum FBW of 34.3% and a group delay of 100 ns can be demonstrated by the ADLs of Group E. Measured results and discussions will be presented in the next section. TABLE 6CellGapLengthLengthNo. ofMeas.Index(μm)(mm)CellsFig.CommentsGroup A3.60.1-1.6207Gap LengthGroup B3.2-5.20.1208-9Cell No. & WavelengthGroup C3.2-5.20.11010Cell No. & WavelengthGroup D3.2-5.20.1511Cell No. & WavelengthGroup E3.60.43-2012-13Broadband ADL FIGS.44A-44Dare a set of graphs that show the measured S-parameters of SH0-mode ADLs (Group A, N=20, λ=36 μm) with identical transducers but different gap lengths, Lg(0.1-16 mm) according to some embodiments.FIG.44Ashows the IL,FIG.44Bshows the RL, andFIG.44Cshows group delay responses.FIG.44Dshows the extracted propagation loss (242 dB/μs), and phase velocity (4255 m/s) of the SH0 mode for an ADL with 800 nm X-cut or Y-cut LiNbO3at 1.1 GHz. The fabricated ADLs can be measured with a vector network analyzer (VNA) at the −10 dBm power level in air, and then conjugately matched using Keysight Advanced Design System. The ADLs in Group A (N=20, λ=3.6 Lg=0.1-1.6 mm) can be designed for investigating the propagation characteristics of SH0-mode acoustic waves at gigahertz frequencies and demonstrating longer delays. The measured IL and RL are shown inFIG.44AandFIG.44Bwith the ports conjugately matched, in one embodiment. The ADLs show a passband centered at 1.09 GHz. A minimum IL of 4.2 dB and a 3 dB FBW of 4% can be achieved for an ADL with a 0.1 mm gap length. An increase in the IL can be observed for longer ADLs, which can be caused by the PL of SH0 in the LiNbO3waveguide and the additional power loss due to a slight PFA caused by an angular misalignment. Group delays between 42 ns and 391 ns can be obtained, as shown inFIG.44C. The in-band ripples observed for group delays inFIG.44Cmay have the same source as the ripples in the IL ofFIG.44A. The propagation characteristics can be experimentally extracted, as shown inFIG.44D, which shows a PL of 24.2 dB/μs and phase velocity of 4255 m/s for the SH0 mode in 800 nm X-cut or Y-cut in LiNbO3at 1.1 GHz, in one embodiment. The PL may be higher than that of S0 mode at the same frequency, which is in agreement with the comparison in PL between S0 and SH0 at lower frequencies. The phase velocity of SH0 may be slower than that of S0 mode, which can lead to a shorter ADL for the same desired delay. It is worth noting that the current PL may be exacerbated by a non-zero PFA. For example, the increased IL for the device with 0.4 mm Lgmay likely be caused by the non-zero PFA, leading to an additional energy loss of no less than 1.9 dB. The effects can be mitigated by implementing a wider aperture or slanted electrodes. FIGS.45A-45Care a set of graphs that show the measured performance of the ADLs (Group B, N=20, Lg=0.1 mm) with different λ (32-52 μm) or center frequencies according to some embodiments.FIG.45Ashows the IL.FIG.45Bshows the RL.FIG.45Cshows the measured group delays of different ADLs in their passbands. The ADLs in Group B (N=20, Lg=0.1 mm, λ=3.2-5.2 μm) are designed for investigating the frequency scalability and also to validate the dispersion curves. The fabricated 20-cell ADLs can exhibit passbands ranging from 0.7 GHz to 1.2 GHz, with a 3 dB-FBW of 4%. An IL of 3.5 dB can be achieved for the 0.7 GHz ADL, while an IL of 4.4 dB can be attained for the 1.2 GHz ADL. The increasing IL at higher frequencies can be caused by an increasing loss in both the electrical domain (larger series resistance in the IDTs and dielectric loss in LiNbO3) and the mechanical domain (larger PL). Delays of approximately 40 ns can be obtained, with in-band ripples that may be caused by a finite directionality and the internal reflections of a SPUDT. FIGS.46A-46Fare a set of graphs that illustrate the measured wideband performance of different ADLs in Group B according to some embodiments.FIG.46A,FIG.46B, andFIG.46Cshow the IL.FIG.46D,FIG.46E, andFIG.46Fshow the RL. Adjacent modes can exist as predicted inFIGS.41A-41C. The wideband performance of the SH0-mode ADLs is presented inFIGS.46A-46F. A highly dispersive nature of different modes in the thin-film LiNbO3can be observed, since the first-order A0 mode is closer to the SH0 mode for shorter), while the second-order A0 mode is closer to the SH0 mode for longer A. A clean spectrum without spurious modes in the adjacent spectrum can be observed, which can enable wider FBW ADLs. ADLs in Group C (N=10, Lg=0.1 mm, λ=3.2-5.2 μm) and Group D (N=5, Lg=0.1 mm, λ=3.2-5.2 μm) can be designed for investigating the impact of cell numbers (N) on the fractional bandwidth, when compared with ADLs in Group B (presented in the description ofFIGS.45A-45C). The fabricated 10-cell ADLs (e.g., those of Group C,FIGS.46C and46D) have a 3 dB-FBW of 8%, a minimum IL of 5.1 dB at 0.7 GHz, and a maximum IL of 5.6 dB at 1.1 GHz, with group delays of approximately 30 ns. FIGS.47A-47Care a set of graphs that illustrate the measured performance of the ADLs (Group C, N=10, Lg=0.1 mm) with different λ (3.2-5.2 μm) or center frequencies according to some embodiments.FIG.47Ais the IL.FIG.47Bis the RL.FIG.47Cis the measured group delays of different ADLs in their corresponding passbands. The fabricated 5-cell ADLs (e.g., Group D,FIGS.47A-47C) have a 3 dB-FBW of 18%, a minimum IL of 4.8 dB at 0.7 GHz, and a maximum IL of 5.5 dB at 1.2 GHz, with group delays around 25 ns. FIGS.48A-48Care a set of graphs that illustrate the measured performance of the ADLs (Group C, N=5, Lg=0.1 mm) with different λ (32-52 μm) or center frequencies according to some embodiments.FIG.48Ais the IL.FIG.48Bis the RL.FIG.48Cis the measured group delays of different ADLs in their corresponding passbands. When comparing ADLs in Groups B, C, and D, four differences can be observed. First, the IL of ADLs with more cells tend to be smaller, which may be due to a greater amount of energy propagating towards the FWD direction caused by more reflectors (e.g., larger N). Second, the FBW of ADLs with more cells tends to be smaller, which may be a direct result of a narrower band transfer function (e.g., see Eq. 52). The above two results agree with the IL-FBW trade-off. Third, group delays tend to be longer for devices with more cells, due to longer transducers in those devices. Finally, ADLs with fewer cells tend to have larger ripples in the IL and group delay, because the triple travel signal (TTS) may not be effectively suppressed due to a lack of directionality in the SPUDT. These results demonstrate the large design space of gigahertz SH0 ADLs for various applications with different specifications. FIGS.49A-49Dare a set of graphs that illustrate the measured performance of the ADLs (Group E, λ=36 μm, Lg=04 mm) with different N(3-20) or FBW according to some embodiments.FIG.49Ais the IL.FIG.49Bis the RL.FIG.49Cis the measured group delays of different ADLs in their passbands.FIG.49Dis the extracted IL and FBW illustrating the trade-off on their respective use. Due to the existence of PL, the TTS can experience approximately three times larger PL when compared to the main signal. Therefore, for ADLs with larger PL due to longer delays, the in-band ripples in IL and group delay can still be relatively small for devices with even broader FBW (e.g., fewer cells). The ADLs in Group E (Lg=0.4 mm, λ=3.6 μm, N=3-20) can be designed to investigate the performance of ADLs with even broader FBW when a significant delay exists. The measured IL and RL are presented inFIG.49AandFIG.49Bwith ports conjugately matched, in one embodiment. For the ADL with 20 cells, an IL of 9.0 dB and a 3-dB FBW of 3.9% can be obtained, while for the device with 3 cells, an IL of 11.3 dB and an FBW of 34.3% are shown. The extracted IL-FBW tradeoff is presented inFIG.49D, showing the same trend as simulated, e.g., in reference toFIG.42. The group delay is presented inFIG.49C, showing that due to PL, the wider band ADLs may not have significantly increased ripples in the passbands. The IL break down is presented in Table 7. It can be observed that the finite directionality may not be the only main contributor to SH0 ADLs at gigahertz frequencies. Additional main contributors may be the PL, additional IL due to non-zero PFA, and other loss including electrical loading from the resistance of IDTs and the dielectric loss in LiNbO3. TABLE 7Damping Source3 Cell5 Cell10 Cell20 CellFinite Uni-directionality4.0dB3.0dB1.9 dB0.4 dBPL in Waveguide2.0dB2.1dB2.2 dB2.4 dBIL due to Non-zero PFA1.9dB1.9dB1.9 dB1.9 dBOthers3.4dB3.9dB3.6 dB4.3 dB(e.g., Electrical Loading)Total11.3dB10.9dB9.6 dB9.0 dB FIGS.50A-50Fare a series of graphs illustrating the measured wideband performance of different devices in Group E according to some embodiments.FIG.50A,FIG.50B, andFIG.50Cshow the IL.FIG.50D,FIG.50E, andFIG.50Fshow the RL. Large FBW can be achieved due to a large spectral spacing between the SH0 and adjacent modes. The wideband performance presented inFIG.50shows a clean spectrum without spurious modes in the passband, even for the device with 34.3% FBW, in one embodiment. In one embodiment, the ADL described herein is close to the calculated maximum achievable FBW at this frequency (e.g., 45%,FIG.41). The demonstrated broadband ADLs can be enabled due to the enhanced IL-FBW design space of the SH0 mode and the clean spectrum collectively. FIGS.51A-51Bare a set of graphs that illustrate a design space validation for gigahertz SH0 ADLs according to some embodiments. The demonstrated ADLs are labeled and sorted based on the gap length and cell number respectively. To better study the design space of broadband ADLs using SH0 at gigahertz frequencies, the extracted relevant parameters are plotted on the IL-FBW trade-off. The data points can be sorted based on the gap length inFIG.51A, showing that the propagation related losses (PL and additional IL from non-zero PFA) may be the main source of the IL. The impact of cell number on the performance is presented inFIG.51B, showing that different design specifications can be met using various applications. The demonstrated performance may surpass a SAW SOA ADL, and may open up new design space for eMBB applications. Broadband SH0 ADLs in lithium niobate operating in the gigahertz range have been demonstrated herein. The design space of the gigahertz SH0 ADLs is fully investigated based on both the IL-FBW trade-off and the spectral spacing between the SH0 and adjacent modes, showing that the large k2, large reflectivity from the thin film structure, and the clean spectrum near the SH0 mode collectively enable broadband performance. The adjacent modes can be considered modes that are adjacent to the intended mode on the frequency spectrum. In other words, adjacent modes are modes at a slightly higher or a slightly lower frequency to the intended mode. The implemented ADLs may show 3 dB fractional bandwidths ranging from 4% to 34.3%, insertion loss between 3.4 dB and 11.3 dB over the frequency range from 0.7 to 1.2 GHz. The PL and phase velocity of SH0 at 1.08 GHz are extracted as 0.0182 dB/A, and 4255 m/s, respectively. The demonstrated SH0 delay platform could potentially provide broadband passive signal processing capabilities for future eMBB applications. FIG.52is a flow diagram of a method5200of the operation of an ADL according to one embodiment. In one embodiment, the method5200is performed by any of the processing devices described herein. In one embodiment, the method5200is performed by processing logic coupled to or located within an ADL, such as the ADL200described herein. In one embodiment, the ADL includes at least one of an X-cut or Y-cut lithium niobate thin film. Referring toFIG.52, at operation5202, the method5200includes converting, by a first interdigitated transducer (IDT) disposed on a first end of a piezoelectric thin film, a first electromagnetic signal traveling in a longitudinal direction along a length of the piezoelectric thin film into an acoustic wave. The piezoelectric thin film is one of an X-cut or Y-cut lithium niobate (LiNbO3) thin film located above a carrier substrate. At operation5204, the method5200includes propagating the acoustic wave in at least one of: a first mode excited by an electric field oriented in the longitudinal direction; or a second mode excited by the electric field oriented at least partially in a thickness direction of the piezoelectric thin film. At operation5206, the method5200includes converting, by a second IDT disposed on a second end of the piezoelectric thin film, the acoustic wave into a second electromagnetic signal after a delay determined by a gap between the first IDT and the second IDT. At operation5208, the method5200includes outputting the second electromagnetic signal. In further embodiments, the first mode is one of a fundamental symmetrical (S0) mode, a first-order symmetrical (S1) mode, or a fundamental shear-horizontal (SH0) mode and the second mode is one of a first-order antisymmetric (A1) mode or a first-order shear-horizontal (SH1) mode. In still further embodiments, a voltage potential can be applied across a signal line coupled to the first IDT to generate the electric field. The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example’ or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims may generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an implementation” or “one implementation” or “an embodiment” or “one embodiment” or the like throughout is not intended to mean the same implementation or implementation unless described as such. One or more implementations or embodiments described herein may be combined in a particular implementation or embodiment. The terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation. In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. | 178,370 |
11942921 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Acoustic wave devices according to preferred embodiments of the present invention are described below with reference to the drawings.FIG.1andFIG.3, which are referred to in the description of preferred embodiments and so forth, are both schematic drawings, and ratios in size and thickness of components in the drawings do not necessarily reflect actual dimensional ratios. First Preferred Embodiment (1) Overall Structure of Acoustic Wave Device First, the overall structure of an acoustic wave device1according to a preferred embodiment of the present invention is described with reference toFIG.1. The acoustic wave device1according to the present preferred embodiment includes, as depicted inFIG.1, a high-acoustic-velocity member2, a low-acoustic-velocity film3, a piezoelectric layer4, an interdigital transducer (IDT) electrode5, and a dielectric film6. The high-acoustic-velocity member2, the low-acoustic-velocity film3, the piezoelectric layer4, the IDT electrode5, and the dielectric film6are stacked in this sequence in a first direction D1. (2) Each Component of Acoustic Wave Device Next, each component of the acoustic wave device1according to the present preferred embodiment is described with reference toFIG.1. (2.1) High-Acoustic-Velocity Member The high-acoustic-velocity member2is positioned on the opposite side of the piezoelectric layer4from the IDT electrode5as depicted inFIG.1. The high-acoustic-velocity member2is a high-acoustic-velocity support substrate21which supports the low-acoustic-velocity film3, the piezoelectric layer4, the IDT electrode5, and the dielectric film6. The acoustic velocity of a bulk wave propagating through the high-acoustic-velocity support substrate21is higher than the acoustic velocity of an acoustic wave propagating through the piezoelectric layer4. The shape of the high-acoustic-velocity support substrate21(high-acoustic-velocity member2) in plan view (peripheral shape when the high-acoustic-velocity support substrate21is viewed in the first direction D1) is a rectangular shape, but is not limited to a rectangular shape but may be, for example, a square shape. The material of the high-acoustic-velocity support substrate21is, for example, silicon. The thickness of the high-acoustic-velocity support substrate21is, for example, about 120 μm. Note that the material of the high-acoustic-velocity support substrate21is not limited to silicon and may be a piezoelectric material such as silicon carbide, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, sapphire, lithium tantalate (LiTaO3), lithium niobate (LiNbO3), or quartz; any of various ceramics such as alumina, zirconia, cordierite, mullite, steatite, and forsterite; magnesia; diamond; a material containing any of the above materials as a main component; or a material containing a mixture of the above materials as a main component. (2.2) Low-Acoustic-Velocity Film The low-acoustic-velocity film3is provided, as depicted inFIG.1, between the high-acoustic-velocity member2and the piezoelectric layer4. The acoustic velocity of a bulk wave propagating through the low-acoustic-velocity film3is lower than the acoustic velocity of a bulk wave propagating through the piezoelectric layer4. Because the low-acoustic-velocity film3is provided between the high-acoustic-velocity member2and the piezoelectric layer4, the acoustic velocity of the acoustic wave is decreased. The energy of the acoustic wave essentially concentrates on a medium with low acoustic velocity. Therefore, the effect of trapping acoustic wave energy into the piezoelectric layer4and into the IDT electrode5where the acoustic wave is excited can be enhanced. As a result, compared with a case in which the low-acoustic-velocity film3is not provided, loss can be reduced and the Q factor can be increased. The material of the low-acoustic-velocity film3is, for example, silicon oxide. The thickness of the low-acoustic-velocity film3is, for example, about 2.0λ or smaller, where λ is the wavelength of the acoustic wave defined by the electrode finger period of the IDT electrode5. Note that the material of the low-acoustic-velocity film3is not limited to silicon oxide but may be glass, silicon oxynitride, tantalum oxide, a compound with fluorine, carbon, or boron added to silicon oxide, or a material containing any of the above materials as a main component. When the material of the low-acoustic-velocity film3is silicon oxide, frequency-temperature characteristics can be improved, compared with a case in which the low-acoustic-velocity film3is not included. The elastic constant of lithium tantalate has negative temperature characteristics, and the elastic constant of silicon oxide has positive temperature characteristics. Therefore, in the acoustic wave device1, the absolute value of temperature coefficient of frequency (TCF) can be decreased. Note that an adhesion layer may be provided between the low-acoustic-velocity film3and the piezoelectric layer4. This can prevent the occurrence of peeling between the low-acoustic-velocity film3and the piezoelectric layer4. The material of the adhesion layer is, for example, a resin (epoxy resin, polyimide resin, or the like), a metal, or the like. Also, besides the adhesion layer, a dielectric film may be provided between the low-acoustic-velocity film3and the piezoelectric layer4or below the low-acoustic-velocity film3. (2.3) Piezoelectric Layer The piezoelectric layer4is located on the low-acoustic-velocity film3. Herein, “located on the low-acoustic-velocity film3” includes a case in which it is located directly on the low-acoustic-velocity film3and a case in which it is located indirectly on the low-acoustic-velocity film3. The material of the piezoelectric layer4is, for example, lithium tantalate. Note that the material of the piezoelectric layer4is not limited to lithium tantalate but may be lithium niobate, zinc oxide (ZnO), aluminum nitride (AlN), or lead zirconate titanate (PZT). The thickness (film thickness) of the piezoelectric layer4is preferably about 3.5λ or smaller, for example, where λ is the wavelength of the acoustic wave defined by the electrode finger period of the IDT electrode5. When the thickness of the piezoelectric layer4is about 3.5λ or smaller, the Q factor is increased. Also, when the thickness of the piezoelectric layer4is about 2.5λ or smaller, the frequency-temperature characteristics are improved. Furthermore, when the thickness of the piezoelectric layer4is about 1.5λ or smaller, the acoustic velocity is easily adjusted. (2.4) IDT Electrode The IDT electrode5is located on the piezoelectric layer4. Herein, “located on the piezoelectric layer4” includes a case in which it is located directly on the piezoelectric layer4and a case in which it is located indirectly on the piezoelectric layer4. The IDT electrode5includes a plurality of electrode fingers and two busbars. The plurality of electrode fingers are aligned in a second direction D2crossing (orthogonal to) the first direction D1. The two busbars are each preferably have an elongated shape, with the second direction D2being the longitudinal direction, and are electrically connected to the plurality of electrode fingers. More specifically, the plurality of electrode fingers include a plurality of first electrode fingers and a plurality of second electrode fingers. The plurality of first electrode fingers are electrically connected to a first busbar of the two busbars. The plurality of second electrode fingers are electrically connected to a second busbar of the two busbars. The material of the IDT electrode5is, for example, aluminum (Al). Note that the material of the IDT electrode5is not limited to aluminum but may be copper (Cu), platinum (Pt), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), magnesium (Mg), iron (Fe), an alloy containing any of these metals as a main component, or the like. Also, the IDT electrode5may have a structure in which a plurality of metal films made of any of these metals or alloys are stacked. In the present preferred embodiment, an adhesion layer is provided between the piezoelectric layer4and the IDT electrode5. The material of the adhesion layer is, for example, titanium. This can prevent occurrence of peeling between the piezoelectric layer4and the IDT electrode5. Note that the material of the adhesion layer is not limited to titanium but may be a resin (epoxy resin, polyimide resin, or the like), a metal other than titanium, or the like. (2.5) Dielectric Film The dielectric film6is located on the piezoelectric layer4so as to cover the IDT electrode5. Herein, “located on the piezoelectric layer4” includes a case in which it is located directly on the piezoelectric layer4and a case in which it is located indirectly on the piezoelectric layer4. In the present preferred embodiment, the dielectric film6is a protective film which protects the IDT electrode5, and preferably has a constant or substantially constant thickness (film thickness) along the shape of the IDT electrode5. The dielectric film6has electrical insulation properties. The material of the dielectric film6is, for example, silicon oxide. That is, in the present preferred embodiment, the material of the dielectric film6and the material of the low-acoustic-velocity film3are identical, for example. Note that the material of the dielectric film6is not limited to silicon oxide but may be, for example, silicon nitride or an appropriate insulating material other than silicon oxide and silicon nitride. (3) Characteristics of Acoustic Wave Device Next, the characteristics of the acoustic wave device1according to the present preferred embodiment is described with reference toFIG.2. FIG.2is a graph depicting a relation between frequency and the Q factor in the acoustic wave device1according to the present preferred embodiment. InFIG.2, the horizontal axis represents frequency, and the vertical axis represents the Q factor. Also inFIG.2, characteristics obtained when the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3are represented by a solid line al, and characteristics obtained when the Young's modulus of the dielectric film6and the Young's modulus of the low-acoustic-velocity film3are similar are represented by a solid line b1. Furthermore inFIG.2, characteristics obtained when the Young's modulus of the dielectric film6is smaller than the Young's modulus of the low-acoustic-velocity film3are represented by a one-dot-chain line c1. FromFIG.2, it can be seen that the Q factor is the worst when the Young's modulus of the dielectric film6is smaller than the Young's modulus of the low-acoustic-velocity film3(one-dot-chain line c1) and the Q factor is the best when the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3(solid line al). That is, when the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3, the Q factor of the acoustic wave device1can be improved. As in the acoustic wave device1according to the present preferred embodiment, when the dielectric film6which covers the IDT electrode5is included, as described above, the Q factor varies with the Young's modulus of the dielectric film6. In this acoustic wave device1, acoustic wave energy concentrates not only on the piezoelectric layer4but also on the dielectric film6. Viscosity loss of the dielectric film6greatly contributes to loss of acoustic wave energy. Therefore, to decrease loss of acoustic wave energy, viscosity loss of the dielectric film6is preferably decreased as much as possible. Here, as the Young's modulus is increased, viscosity loss is decreased. Thus, to decrease loss of acoustic wave energy, the Young's modulus of the dielectric film6is preferably increased as much as possible. Meanwhile, as described above, the acoustic velocity of the bulk wave propagating through the low-acoustic-velocity film3is lower than the acoustic velocity of the bulk wave propagating through the piezoelectric layer4, and the acoustic velocity is required to be smaller than that in the piezoelectric layer4. Thus, the Young's modulus of the low-acoustic-velocity film3is preferably smaller than the Young's modulus of the piezoelectric layer4. Thus, in this case, when the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3, loss of acoustic wave energy can be reduced (improved). (4) Film Formation Conditions Film formation conditions of the low-acoustic-velocity film3and the dielectric film6of the acoustic wave device1according to the present preferred embodiment are described below. In the acoustic wave device1according to the present preferred embodiment, the low-acoustic-velocity film3and the dielectric film6are formed by, for example, sputtering. In this case, by changing the degree of vacuum in a chamber of a sputter device, the Young's moduli of the low-acoustic-velocity film3and the dielectric film6can be controlled. For example, when the low-acoustic-velocity film3is formed, if the degree of vacuum in the chamber is set to about 0.5 Pa or larger and about 1.0 Pa or smaller, a low-acoustic-velocity film3with a small Young's modulus compared with that of the dielectric film6can be formed. Also, when the dielectric film6is formed, if the degree of vacuum in the chamber is set to about 0.04 Pa or larger and about 0.1 Pa or smaller, a dielectric film6with a large Young's modulus compared with that of the low-acoustic-velocity film3can be provided. That is, if the degree of vacuum is increased (the ultimate pressure of residual gas in the chamber is decreased), impurities in the formed film are decreased, and a film with high purity and density of atoms can be acquired. Thus, the film has large Young's modulus and small viscosity loss. That is, in the acoustic wave device1according to the present preferred embodiment, by adjusting the degree of vacuum in the chamber, the Young's modulus of the dielectric film6can be made larger than the Young's modulus of the low-acoustic-velocity film3. (5) Effects As described above, the acoustic wave device1according to the present preferred embodiment includes the piezoelectric layer4, the IDT electrode5, the high-acoustic-velocity member2, the low-acoustic-velocity film3, and the dielectric film6. The IDT electrode5is located on the piezoelectric layer4. The high-acoustic-velocity member2is positioned on an opposite side of the piezoelectric layer4from the IDT electrode5. An acoustic velocity of a bulk wave propagating through the high-acoustic-velocity member2is higher than an acoustic velocity of an acoustic wave propagating through the piezoelectric layer4. The low-acoustic-velocity film3is provided between the high-acoustic-velocity member2and the piezoelectric layer4. An acoustic velocity of a bulk wave propagating through the low-acoustic-velocity film3is lower than the acoustic velocity of the bulk wave propagating through the piezoelectric layer4. The dielectric film6is located on the piezoelectric layer4so as to cover the IDT electrode5. In this acoustic wave device1, a Young's modulus of the dielectric film6is larger than a Young's modulus of the low-acoustic-velocity film3. In the structure in which the IDT electrode5is covered with the dielectric film6, acoustic wave energy concentrates not only on the piezoelectric layer4but also on the dielectric film6. Thus, when the Young's modulus of the dielectric film6is increased as much as possible, viscosity loss of the dielectric film6can be decreased, thereby allowing loss of acoustic wave energy to be reduced. Here, as the Young's modulus of the low-acoustic-velocity film3becomes smaller, loss can be further reduced or prevented. Therefore, when the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3, loss can be further reduced or prevented. In the acoustic wave device1according to the present preferred embodiment, the material of the dielectric film6is silicon oxide. This can improve frequency-temperature characteristics compared with a case in which the material of the dielectric film6is not silicon oxide. In the acoustic wave device1according to the present preferred embodiment, the material of the low-acoustic-velocity film3is silicon oxide. This can improve frequency-temperature characteristics compared with a case in which the material of the low-acoustic-velocity film3is not silicon oxide. In the acoustic wave device1according to the present preferred embodiment, the material of the dielectric film6and the material of the low-acoustic-velocity film3are identical. This provides the advantage that the Young's modulus of the dielectric film6is easily adjusted, compared with a case in which the material of the dielectric film6and the material of the low-acoustic-velocity film3are different. In the acoustic wave device1according to the preferred embodiment, the high-acoustic-velocity member2is the high-acoustic-velocity support substrate21, and the acoustic velocity of the bulk wave propagating therethrough is higher than the acoustic velocity of the acoustic wave propagating through the piezoelectric layer4. This can increase the Q factor of the acoustic wave device1. (6) Modifications The above-described preferred embodiments are merely examples of various preferred embodiments of the present invention. The above-described preferred embodiments can be variously changed in accordance with design and so forth as desired or needed. Example modifications of the above-described preferred embodiments are listed below. The modifications described below can be applied in any suitable combination. (6.1) Modification 1 While the acoustic wave device1according to a preferred embodiment of the present invention has a three-layer structure having the high-acoustic-velocity support substrate21, the low-acoustic-velocity film3, and the piezoelectric layer4, an acoustic wave device1A according to Modification 1 has a four-layer structure and in this point, they are different. The structure of the acoustic wave device1A having the four-layer structure is described below with reference toFIG.3. Note that in the acoustic wave device1A according to Modification 1, components similar to those of the acoustic wave device1according to the preferred embodiments are provided with the same reference characters and their description is omitted. The acoustic wave device1A according to Modification 1 includes, as depicted inFIG.3, a high-acoustic-velocity member2A, the low-acoustic-velocity film3, the piezoelectric layer4, the IDT electrode5, and the dielectric film6. The high-acoustic-velocity member2A includes a support substrate22and a high-acoustic-velocity film23. That is, the acoustic wave device1A further includes the support substrate22. The high-acoustic-velocity film23is located on the support substrate22. Herein, “located on the support substrate22” includes a case in which it is located directly on the support substrate22and a case in which it is located indirectly on the support substrate22. The acoustic velocity of a bulk wave propagating through the high-acoustic-velocity film23is higher than the acoustic velocity of an acoustic wave propagating through the piezoelectric layer4. Note that the acoustic wave device1A may have an adhesion layer, a dielectric film, and so forth, in addition to the high-acoustic-velocity film23, the low-acoustic-velocity film3, the piezoelectric layer4, and the dielectric film6. The material of the support substrate22is, for example, silicon. Note that the material of the support substrate22is not limited to silicon but may be a piezoelectric material such as sapphire, lithium tantalate, lithium niobate, or quartz; any of various ceramics such as alumina, magnesia, silicon nitride, aluminum nitride, silicon carbide, zirconia, cordierite, mullite, steatite, and forsterite; a dielectric such as glass; a semiconductor such as gallium nitride; a resin; or the like. The high-acoustic-velocity film23is located on the support substrate22. The high-acoustic-velocity film23functions to trap the acoustic wave into a portion where the piezoelectric layer4and the low-acoustic-velocity film3are stacked and prevent the acoustic wave from leaking to the structure below the high-acoustic-velocity film23. As for the thickness of the high-acoustic-velocity film23, a thicker film is desirable in view of the function of trapping the acoustic wave into the piezoelectric layer4and the low-acoustic-velocity film3. When the thickness of the high-acoustic-velocity film23is sufficiently thick, acoustic wave energy in a specific example for use to acquire characteristics of a filter or a resonator is distributed over the entire piezoelectric layer4and low-acoustic-velocity film3and is also distributed to a portion of the high-acoustic-velocity film23on the low-acoustic-velocity film3side, but is not distributed to the support substrate22. A mechanism of trapping the acoustic wave by the high-acoustic-velocity film23is a mechanism similar to that for a Love-wave-type surface acoustic wave, which is a non-leaky SH wave, and is described in, for example, “Introduction to Simulation Technologies for Surface Acoustic Wave Devices”, Kenya Hashimoto, REALIZE Science & Engineering, pp. 26-28. The above-described mechanism is different from a mechanism of trapping an acoustic wave by using a Bragg reflector with an acoustic multilayer film. The material of the high-acoustic-velocity film23is, for example, at least one material selected from the group consisting of diamond-like carbon, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon, sapphire, lithium tantalate, lithium niobate, quartz, alumina, zirconia, cordierite, mullite, steatite, forsterite, magnesia, and diamond. According to the acoustic wave device1A of Modification 1, as with the acoustic wave device1according to the above-described preferred embodiments, the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3, thereby allowing a decrease in viscosity loss of the dielectric film6. This can reduce loss of acoustic wave energy. Also, according to the acoustic wave device1A of Modification 1, the Q factor can also be increased. (6.2) Other Modifications Other modifications are listed below. While the material of the dielectric film6and the material of the low-acoustic-velocity film3are identical in the preferred embodiments and Modification 1, the material of the dielectric film6and the material of the low-acoustic-velocity film3may be different if the Young's modulus of the dielectric film6is larger than the Young's modulus of the low-acoustic-velocity film3. However, if the material of the dielectric film6and the material of the low-acoustic-velocity film3are identical, there is the advantage that the Young's modulus of the dielectric film6can be adjusted only by, for example, changing pressure, temperature, or the like, and the Young's modulus is easily adjusted. In the preferred embodiments and Modification 1, the dielectric film6is provided to correspond to the shape of the IDT electrode5, and the thickness (film thickness) of the dielectric film6is constant or substantially constant over the entire surface of the piezoelectric layer4. However, it is not necessary that the thickness of the dielectric film6be constant, and the dielectric film6may be formed so that, for example, the thickness of the dielectric film6from a principal surface of the piezoelectric layer4on the IDT electrode5side is constant or substantially constant. In the preferred embodiments, by changing the degree of vacuum in the chamber, the Young's moduli of the low-acoustic-velocity film3and the dielectric film6are controlled. However, for example, the Young's moduli of the low-acoustic-velocity film3and the dielectric film6may be controlled by changing temperature in the chamber, or the Young's moduli of the low-acoustic-velocity film3and the dielectric film6may be controlled by changing both of the degree of vacuum and temperature in the chamber. Furthermore, the Young's moduli of the low-acoustic-velocity film3and the dielectric film6may be controlled by changing a condition other than the degree of vacuum and temperature in the chamber. SUMMARY From the preferred embodiments and others described above, the following non-limiting examples are disclosed. An acoustic wave device (1;1A) according to a first example includes a piezoelectric layer (4), an IDT electrode (5), a high-acoustic-velocity member (2;2A), a low-acoustic-velocity film (3), and a dielectric film (6). The IDT electrode (5) is located on the piezoelectric layer (4). The high-acoustic-velocity member (2;2A) is positioned on an opposite side of the piezoelectric layer (4) from the IDT electrode (5). An acoustic velocity of a bulk wave propagating through the high-acoustic-velocity member (2;2A) is higher than an acoustic velocity of an acoustic wave propagating through the piezoelectric layer (4). The low-acoustic-velocity film (3) is provided between the high-acoustic-velocity member (2;2A) and the piezoelectric layer (4). An acoustic velocity of a bulk wave propagating through the low-acoustic-velocity film (3) is lower than the acoustic velocity of the bulk wave propagating through the piezoelectric layer (4). The dielectric film (6) is located on the piezoelectric layer (4) so as to cover the IDT electrode (5). In the acoustic wave device (1;1A), a Young's modulus of the dielectric film (6) is larger than a Young's modulus of the low-acoustic-velocity film (3). According to this example, loss of acoustic wave energy can be reduced compared with a case in which the Young's modulus of the dielectric film (6) is smaller than or equal to the Young's modulus of the low-acoustic-velocity film (3). In the acoustic wave device (1;1A) according to a second example, in the first example, the material of the dielectric film (6) is silicon oxide. According to this example, frequency-temperature characteristics can be improved compared with a case in which the material of the dielectric film (6) is not silicon oxide. In the acoustic wave device (1;1A) according to a third example, in the first or second example, the material of the low-acoustic-velocity film (3) is silicon oxide. According to this example, frequency-temperature characteristics can be improved compared with a case in which the material of the low-acoustic-velocity film (3) is not silicon oxide. In the acoustic wave device (1;1A) according to a fourth example, in the first example, the material of the dielectric film (6) and the material of the low-acoustic-velocity film (3) are identical. According to this example, there is the advantage that the Young's modulus of the dielectric film (6) is easily adjusted, compared with a case in which the material of the dielectric film (6) and the material of the low-acoustic-velocity film (3) are different. In the acoustic wave device (1) according to a fifth example, in any one of the first to fourth examples, the high-acoustic-velocity member (2) is a high-acoustic-velocity support substrate (21), and an acoustic velocity of a bulk wave propagating through the high-acoustic-velocity support substrate (21) is higher than the acoustic velocity of the acoustic wave propagating through the piezoelectric layer (4). According to this example, the Q factor of the acoustic wave device (1) can be increased. The acoustic wave device (1A) according to a sixth example further includes a support substrate (22) in any one of the first to fourth examples. The high-acoustic-velocity member (2A) is located on the support substrate (22) and includes a high-acoustic-velocity film (23), and an acoustic velocity of a bulk wave propagating through the high-acoustic-velocity film (23) is higher than the acoustic velocity of the acoustic wave propagating through the piezoelectric layer (4). According to this example, the Q factor of the acoustic wave device (1A) can be increased. While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims. | 28,777 |
11942922 | Throughout this description, elements appearing in figures are assigned three-digit or four-digit reference designators, where the two least significant digits are specific to the element and the one or two most significant digit is the figure number where the element is first introduced. An element that is not described in conjunction with a figure may be presumed to have the same characteristics and function as a previously-described element having the same reference designator. DETAILED DESCRIPTION Description of Apparatus FIG.1shows a simplified schematic top view, orthogonal cross-sectional views, and a detailed cross-sectional view of a transversely-excited film bulk acoustic resonator (XBAR)100. XBAR resonators such as the resonator100may be used in a variety of RF filters including band-reject filters, band-pass filters, duplexers, and multiplexers. XBARs are particularly suited for use in filters for communications bands with frequencies above 3 GHz. The XBAR100is made up of a thin film conductor pattern formed on a surface of a piezoelectric plate110having parallel front and back surfaces112,114, respectively. The piezoelectric plate is a thin single-crystal layer of a piezoelectric material such as lithium niobate, lithium tantalate, lanthanum gallium silicate, gallium nitride, or aluminum nitride. The piezoelectric plate is cut such that the orientation of the X, Y, and Z crystalline axes with respect to the front and back surfaces is known and consistent. In the examples presented in this patent, the piezoelectric plates are Z-cut, which is to say the Z axis is normal to the front and back surfaces112,114. However, XBARs may be fabricated on piezoelectric plates with other crystallographic orientations. A thickness between the front and back surfaces112,114of the piezoelectric plate can be greater than or equal to 200 nm and less than or equal to 1000 nm. The back surface114of the piezoelectric plate110is attached to a surface of the substrate120except for a portion of the piezoelectric plate110that forms a diaphragm115spanning a cavity140formed in the substrate. The portion of the piezoelectric plate that spans the cavity is referred to herein as the “diaphragm”115due to its physical resemblance to the diaphragm of a microphone. As shown inFIG.1, the diaphragm115is contiguous with the rest of the piezoelectric plate110around all of a perimeter145of the cavity140. In this context, “contiguous” means “continuously connected without any intervening item”. In other configurations, the diaphragm115may be contiguous with the piezoelectric plate around at least 50% of the perimeter145of the cavity140. The substrate120provides mechanical support to the piezoelectric plate110. The substrate120may be, for example, silicon, sapphire, quartz, or some other material or combination of materials. The back surface114of the piezoelectric plate110may be bonded to the substrate120using a wafer bonding process. Alternatively, the piezoelectric plate110may be grown on the substrate120or attached to the substrate in some other manner. The piezoelectric plate110may be attached directly to the substrate or may be attached to the substrate120via one or more intermediate material layers (not shown inFIG.1). “Cavity” has its conventional meaning of “an empty space within a solid body.” The cavity140may be a hole completely through the substrate120(as shown in Section A-A and Section B-B) or a recess in the substrate120under the diaphragm115. The cavity140may be formed, for example, by selective etching of the substrate120before or after the piezoelectric plate110and the substrate120are attached. The conductor pattern of the XBAR100includes an interdigital transducer (IDT)130. The IDT130includes a first plurality of parallel fingers, such as finger136, extending from a first busbar132and a second plurality of fingers extending from a second busbar134. The first and second pluralities of parallel fingers are interleaved. The interleaved fingers overlap for a distance AP, commonly referred to as the “aperture” of the IDT. The center-to-center distance L between the outermost fingers of the IDT130is the “length” of the IDT. The first and second busbars132,134serve as the terminals of the XBAR100. A radio frequency or microwave signal applied between the two busbars132,134of the IDT130excites a primary acoustic mode (e.g., a shear primary acoustic mode) within the piezoelectric plate110. As will be discussed in further detail, the primary acoustic mode is a bulk shear mode where acoustic energy propagates along a direction substantially orthogonal to the surface of the piezoelectric plate110, which is also normal, or transverse, to the direction of the electric field created by the IDT fingers. Thus, the XBAR is considered a transversely-excited film bulk wave resonator. The IDT130is positioned on the piezoelectric plate110such that at least the fingers of the IDT130are disposed on the diaphragm115of the piezoelectric plate which spans, or is suspended over, the cavity140. As shown inFIG.1, the cavity140has a rectangular shape with an extent greater than the aperture AP and length L of the IDT130. A cavity of an XBAR may have a different shape, such as a regular or irregular polygon. The cavity of an XBAR may have more or fewer than four sides, which may be straight or curved. For ease of presentation inFIG.1, the geometric pitch and width of the IDT fingers is greatly exaggerated with respect to the length (dimension L) and aperture (dimension AP) of the XBAR. A typical XBAR has more than ten parallel fingers in the IDT110. An XBAR may have hundreds of parallel fingers in the IDT110. Similarly, the thickness of the fingers in the cross-sectional views is greatly exaggerated. Referring to the detailed cross-sectional view, a front-side dielectric layer150may optionally be formed on the front side of the piezoelectric plate110. The “front side” of the XBAR is, by definition, the surface facing away from the substrate. The front-side dielectric layer150may be formed only between the IDT fingers (e.g., IDT finger138b) or may be deposited as a blanket layer such that the dielectric layer is formed both between and over the IDT fingers (e.g., IDT finger138a). The front-side dielectric layer150may be a non-piezoelectric dielectric material, such as silicon dioxide or silicon nitride. The thickness of the front side dielectric layer is typically less than or equal to the thickness of the piezoelectric plate. The front-side dielectric layer150may be formed of multiple layers of two or more materials. A resonant frequency of the XBAR may be determined in part by a thickness of the front-side dielectric layer. The IDT fingers138aand138bmay be aluminum, an aluminum alloy, copper, a copper alloy, beryllium, gold, tungsten, molybdenum or some other conductive material. The IDT fingers are considered to be “substantially aluminum” if they are formed from aluminum or an alloy comprising at least 50% aluminum. The IDT fingers are considered to be “substantially copper” if they are formed from copper or an alloy comprising at least 50% copper. Thin (relative to the total thickness of the conductors) layers of other metals, such as chromium or titanium, may be formed under and/or over and/or as layers within the fingers to improve adhesion between the fingers and the piezoelectric plate110and/or to passivate or encapsulate the fingers and/or to improve power handling. The busbars132,134of the IDT may be made of the same or different materials as the fingers. Dimension p is the center-to-center spacing or “pitch” of the IDT fingers, which may be referred to as the pitch of the IDT and/or the pitch of the XBAR. Dimension w is the width or “mark” of the IDT fingers. FIG.2AandFIG.2Bshow two alternative cross-sectional views along the section plane A-A defined inFIG.1. InFIG.2A, a piezoelectric plate210is attached to a substrate220. A portion of the piezoelectric plate210forms a diaphragm215spanning a cavity240in the substrate. The cavity240does not fully penetrate the substrate220. Fingers of an IDT are disposed on the diaphragm215. The cavity240may be formed, for example, by etching the substrate220before attaching the piezoelectric plate210. Alternatively, the cavity240may be formed by etching the substrate220with a selective etchant that reaches the substrate through one or more openings (not shown) provided in the piezoelectric plate210. In this case, the diaphragm215may be contiguous with the rest of the piezoelectric plate210around a large portion of a perimeter245of the cavity240. For example, the diaphragm215may be contiguous with the rest of the piezoelectric plate210around at least 50% of the perimeter245of the cavity240. An intermediate layer (not shown), such as a dielectric bonding layer, may be present between the piezo electric plate240and the substrate220. InFIG.2B, the substrate220includes a base222and an intermediate layer224disposed between the piezoelectric plate210and the base222. For example, the base222may be silicon and the intermediate layer224may be silicon dioxide or silicon nitride or some other material. A portion of the piezoelectric plate210forms a diaphragm215spanning a cavity240in the intermediate layer224. Fingers of an IDT are disposed on the diaphragm215. The cavity240may be formed, for example, by etching the intermediate layer224before attaching the piezoelectric plate210. Alternatively, the cavity240may be formed by etching the intermediate layer224with a selective etchant that reaches the substrate through one or more openings provided in the piezoelectric plate210. In this case, the diaphragm215may be contiguous with the rest of the piezoelectric plate210around a large portion of a perimeter245of the cavity240. For example, the diaphragm215may be contiguous with the rest of the piezoelectric plate210around at least 50% of the perimeter245of the cavity240as shown inFIG.2C. Although not shown inFIG.2B, a cavity formed in the intermediate layer224may extend into the base222. FIG.2Cis a schematic plan view of another XBAR250. The XBAR250includes an IDT formed on a piezoelectric plate210. A portion of the piezoelectric plate210forms a diaphragm spanning a cavity in a substrate. In this example, the perimeter245of the cavity has an irregular polygon shape such that none of the edges of the cavity are parallel, nor are they parallel to the conductors of the IDT. A cavity may have a different shape with straight or curved edges. FIG.3is a graphical illustration of the primary acoustic mode of interest in an XBAR.FIG.3shows a small portion of an XBAR300including a piezoelectric plate310and three interleaved IDT fingers330which alternate in electrical polarity from finger to finger. An RF voltage is applied to the interleaved fingers330. This voltage creates a time-varying electric field between the fingers. The direction of the electric field is predominantly lateral, or parallel to the surface of the piezoelectric plate310, as indicated by the arrows labeled “electric field”. Due to the high dielectric constant of the piezoelectric plate, the RF electric energy is highly concentrated inside the plate relative to the air. The lateral electric field introduces shear deformation which couples strongly to a shear primary acoustic mode (at a resonance frequency defined by the acoustic cavity formed by the volume between the two surfaces of the piezoelectric plate) in the piezoelectric plate310. In this context, “shear deformation” is defined as deformation in which parallel planes in a material remain predominantly parallel and maintain constant separation while translating (within their respective planes) relative to each other. A “shear acoustic mode” is defined as an acoustic vibration mode in a medium that results in shear deformation of the medium. The shear deformations in the XBAR300are represented by the curves360, with the adjacent small arrows providing a schematic indication of the direction and relative magnitude of atomic motion at the resonance frequency. The degree of atomic motion, as well as the thickness of the piezoelectric plate310, have been greatly exaggerated for ease of visualization. While the atomic motions are predominantly lateral (i.e., horizontal as shown inFIG.3), the direction of acoustic energy flow of the excited primary acoustic mode is substantially orthogonal to the surface of the piezoelectric plate, as indicated by the arrow365. An acoustic resonator based on shear acoustic wave resonances can achieve better performance than current state-of-the art film-bulk-acoustic-resonators (FBAR) and solidly-mounted-resonator bulk-acoustic-wave (SMR BAW) devices where the electric field is applied in the thickness direction. In such devices, the acoustic mode is compressive with atomic motions and the direction of acoustic energy flow in the thickness direction. In addition, the piezoelectric coupling for shear wave XBAR resonances can be high (>20%) compared to other acoustic resonators. High piezoelectric coupling enables the design and implementation of microwave and millimeter-wave filters with appreciable bandwidth. FIG.4is a schematic circuit diagram of a band-pass filter400using five XBARs X1-X5. The filter400may be, for example, a band n79 band-pass filter for use in a communication device. The filter400has a conventional ladder filter architecture including three series resonators X1, X3, X5and two shunt resonators X2, X4. The three series resonators X1, X3, X5are connected in series between a first port and a second port. InFIG.4, the first and second ports are labeled “In” and “Out”, respectively. However, the filter400is symmetrical and either port may serve as the input or output of the filter. The two shunt resonators X2, X4are connected from nodes between the series resonators to ground. All the shunt resonators and series resonators are XBARs. The three series resonators X1, X3, X5and the two shunt resonators X2, X4of the filter400maybe formed on a single plate430of piezoelectric material bonded to a silicon substrate (not visible). Each resonator includes a respective IDT (not shown), with at least the fingers of the IDT disposed over a cavity in the substrate. In this and similar contexts, the term “respective” means “relating things each to each”, which is to say with a one-to-one correspondence. InFIG.4, the cavities are illustrated schematically as the dashed rectangles (such as the rectangle435). In this example, an IDT of each resonator is disposed over a respective cavity. In other filters, the IDTs of two or more resonators may be disposed over a common cavity. Resonators may also be cascaded into multiple IDTs which may be formed on multiple cavities. Each of the resonators X1to X5has a resonance frequency and an anti-resonance frequency. In over-simplified terms, each resonator is effectively a short circuit at its resonance frequency and effectively an open circuit at its anti-resonance frequency. Each resonator X1to X5creates a “transmission zero”, where the transmission between the in and out ports of the filter is very low. Note that the transmission at a “transmission zero” is not actually zero due to energy leakage through parasitic components and other effects. The three series resonators X1, X3, X5create transmission zeros at their respective anti-resonance frequencies (where each resonator is effectively an open circuit). The two shunt resonators X2, X4create transmission zeros at their respective resonance frequencies (where each resonator is effectively a short circuit). In a typical band-pass filter using acoustic resonators, the anti-resonance frequencies of the series resonators are above the passband, and the resonance frequencies of the shunt resonators are below the passband. A band-pass filter for use in a communications device, such as a cellular telephone, must meet a variety of requirements. First, a band-pass filter, by definition, must pass, or transmit with acceptable loss, a defined pass-band. Typically, a band-pass filter for use in a communications device must also stop, or substantially attenuate, one or more stop band(s). For example, a band n79 band-pass filter is typically required to pass the n79 frequency band from 4400 MHz to 5000 MHz and to stop the 5 GHz WiFi™ band and/or the n77 band from 3300 MHz to 4200 MHz. To meet these requirements, a filter using a ladder circuit would require series resonators with anti-resonance frequencies about or above 5100 MHz, and shunt resonators with resonance frequencies about or below 4300 MHz. The resonance and anti-resonance frequencies of an XBAR are strongly dependent on the thickness ts of the piezoelectric membrane (115inFIG.1).FIG.5is a graph500of resonance frequency of an XBAR versus piezoelectric diaphragm thickness. In this example, the piezoelectric diaphragm is z-cut lithium niobate. The solid curve510is plot of resonance frequency as function of the inverse of the piezoelectric plate thickness for XBARs with IDT pitch equal to 3 microns. This plot is based on results of simulations of XBARs using finite element methods. The resonance frequency is roughly proportional to the inverse of the piezoelectric plate thickness. The resonance and anti-resonance frequencies of an XBAR are also dependent on the pitch (dimension p inFIG.1) of the IDT. Further, the electromechanical coupling of an XBAR, which determines the separation between the resonance and anti-resonance frequencies, is dependent on the pitch.FIG.6is a graph of gamma (Γ) as a function of normalized pitch, which is to say IDT pitch p divided by diaphragm thickness ts. Gamma is a metric defined by the equation: Γ=1(Fa/Fr)2-1 where Fa is the antiresonance frequency and Fr is the resonance frequency. Large values for gamma correspond to smaller separation between the resonance and anti-resonance frequencies. Low values of gamma indicate strong coupling which is good for wideband ladder filters. In this example, the piezoelectric diaphragm is z-cut lithium niobate, and data is presented for diaphragm thicknesses of 300 nm, 400 nm, and 500 nm. In all cases the IDT is aluminum with a thickness of 25% of the diaphragm thickness, the duty factor (i.e., the ratio of the width w to the pitch p) of the IDT fingers is 0.14, and there are no dielectric layers. The “+” symbols, circles, and “×” symbols represent diaphragm thicknesses of 300 nm, 400 nm, and 500 nm, respectively. Outlier data points, such as those for relative IDT pitch about 4.5 and about 8, are caused by spurious modes interacting with the primary acoustic mode and altering the apparent gamma. The relationship between gamma and IDT pitch is relatively independent of diaphragm thickness, and roughly asymptotic to Γ=3.5 as the relative pitch is increased. Another typical requirement on a band-pass filter for use in a communications device is the input and output impedances of the filter have to match, at least over the pass-band of the filter, the impedances of other elements of the communications device to which the filter is connected (e.g., a transmitter, receiver, and/or antenna) for maximum power transfer. Commonly, the input and output impedances of a band-pass filter are required to match a 50-ohm impedance within a tolerance that may be expressed, for example, as a maximum return loss or a maximum voltage standing wave ratio. When necessary, an impedance matching network comprising one or more reactive components can be used at the input and/or output of a band-pass filter. Such impedance matching networks add to the complexity, cost, and insertion loss of the filter and are thus undesirable. To match, without additional impedance matching components, a 50-Ohm impedance at a frequency of 5 GHz, the capacitances of at least the shunt resonators in the band-pass filter need to be in a range of about 0.5 picofarads (pF) to about 1.5 picofarads. FIG.7is a graph showing the area and dimensions of XBAR resonators with capacitance equal to one picofarad. The solid line710is a plot of the IDT length required provide a capacitance of 1 pF as a function of the inverse of the IDT aperture when the IDT pitch is 3 microns. The dashed line720is a plot of the IDT length required provide a capacitance of 1 pF as a function of the inverse of the IDT aperture when the IDT pitch is 5 microns. The data plotted inFIG.7is specific to XBAR devices with lithium niobate diaphragm thickness of 400 nm. For any aperture, the IDT length required to provide a desired capacitance is greater for an IDT pitch of 5 microns than for an IDT pitch of 3 microns. The required IDT length is roughly proportional to the change in IDT pitch. The design of a filter using XBARs is a compromise between somewhat conflicting objectives. As shown inFIG.6, a larger IDT pitch may be preferred to reduce gamma and maximize the separation between the anti-resonance and resonance frequencies. As can be understood fromFIG.7, smaller IDT pitch is preferred to minimize IDT area. A reasonable compromise between these objectives is 6≤p/ts≤12.5. Setting the IDT pitch p equal to or greater than six times the diaphragm thickness ts provides Fa/Fr greater than 1.1. Setting the maximum IDT pitch p to 12.5 times the diaphragm thickness ts is reasonable since Fa/Fr does not increase appreciably for higher values of relative pitch. As will be discussed is greater detail subsequently, the metal fingers of the IDTs provide the primary mechanism for removing heat from an XBAR resonator. Increasing the aperture of a resonator increases the length and the electrical and thermal resistance of each IDT finger. Further, for a given IDT capacitance, increasing the aperture reduces the number of fingers required in the IDT, which, in turn, proportionally increases the RF current flowing in each finger. All of these effects argue for using the smallest possible aperture in resonators for high-power filters. Conversely, several factors argue for using a large aperture. First, the total area of an XBAR resonator includes the area of the IDT and the area of the bus bars. The area of the bus bars is generally proportional to the length of the IDT. For very small apertures, the area of the IDT bus bars may be larger than the area occupied by the interleaved IDT fingers. Further, some electrical and acoustic energy may be lost at the ends of the IDT fingers. These loss effects become more significant as IDT aperture is reduced and the total number of fingers is increased. These losses may be evident as a reduction in resonator Q-factor, particularly at the anti-resonance frequency, as IDT aperture is reduced. As a compromise between conflicting objectives, resonators apertures will typically fall in the range from 20 μm and 60 μm. The resonance and anti-resonance frequencies of an XBAR are also dependent on the thickness (dimension tfd inFIG.2) of the front-side dielectric layer applied between (and optionally over) the fingers of the IDT.FIG.8is a graph800of anti-resonant frequency and resonant frequency as a function of IDT finger pitch p for XBAR resonators with z-cut lithium niobate piezoelectric plate thickness ts=400 nm, with front-side dielectric layer thickness tfd as a parameter. The solid lines810and820are plots of the anti-resonance and resonance frequencies, respectively, as functions of IDT pitch for tfd=0. The dashed lines812and822are plots of the anti-resonance and resonance frequencies, respectively, as functions of IDT pitch for tfd=30 nm. The dash-dot lines814and824are plots of the anti-resonance and resonance frequencies, respectively, as functions of IDT pitch for tfd=60 nm. The dash-dot-dot lines816and826are plots of the anti-resonance and resonance frequencies, respectively, as functions of IDT pitch for tfd=90 nm. The frequency shifts are approximately linear functions of tfd. InFIG.8, the difference between the resonance and anti-resonance frequencies is 600 to 650 MHz for any particular values for front-side dielectric layer thickness and IDT pitch. This difference is large compared to that of older acoustic filter technologies, such as surface acoustic wave filters. However, 650 MHz is not sufficient for very wide band filters such as band-pass filters needed for bands n77 and n79. As described in application Ser. No. 16/230,443, the front-side dielectric layer over shunt resonators may be thicker than the front-side dielectric layer over series resonators to increase the frequency difference between the resonant frequencies of the shunt resonators and the anti-resonance frequencies of the series resonators. Communications devices operating in time-domain duplex (TDD) bands transmit and receive in the same frequency band. Both the transmit and receive signal paths pass through a common bandpass filter connected between an antenna and a transceiver. Communications devices operating in frequency-domain duplex (FDD) bands transmit and receive in different frequency bands. The transmit and receive signal paths pass through separate transmit and receive bandpass filters connected between an antenna and the transceiver. Filters for use in TDD bands or filters for use as transmit filters in FDD bands can be subjected to radio frequency input power levels of 30 dBm or greater and must avoid damage under power. The insertions loss of acoustic wave bandpass filters is usually not more than a few dB. Some portion of this lost power is return loss reflected back to the power source; the rest of the lost power is dissipated in the filter. Typical band-pass filters for LTE bands have surface areas of 1.0 to 2.0 square millimeters. Although the total power dissipation in a filter may be small, the power density can be high given the small surface area. Further, the primary loss mechanisms in an acoustic filter are resistive losses in the conductor patterns and acoustic losses in the IDT fingers and piezoelectric material. Thus, the power dissipation in an acoustic filter is concentrated in the acoustic resonators. To prevent excessive temperature increase in the acoustic resonators, the heat due to the power dissipation must be conducted away from the resonators through the filter package to the environment external to the filter. In traditional acoustic filters, such as surface acoustic wave (SAW) filters and bulk acoustic wave (BAW) filters, the heat generated by power dissipation in the acoustic resonators is efficiently conducted through the filter substrate and the metal electrode patterns to the package. In an XBAR device, the resonators are disposed on thin piezoelectric membranes that are inefficient heat conductors. The large majority of the heat generated in an XBAR device must be removed from the resonator via the IDT fingers and associated conductor patterns. To minimize power dissipation and maximize heat removal, the IDT fingers and associated conductors should be formed from a material that has low electrical resistivity and high thermal conductivity. Metals having both low resistivity and high thermal conductivity are listed in the following table: Electrical resistivityThermal conductivityMetal(10−6Ω-cm)(W/m-K)Silver1.55419Copper1.70385Gold2.2301Aluminium2.7210 Silver offers the lowest resistivity and highest thermal conductivity but is not a viable candidate for IDT conductors due to the lack of processes for deposition and patterning of silver thin films. Appropriate processes are available for copper, gold, and aluminum. Aluminum offers the most mature processes for use in acoustic resonator devices and potentially the lowest cost, but with higher resistivity and reduced thermal conductivity compared to copper and gold. For comparison, the thermal conductivity of lithium niobate is about 4 W/m-K, or about 2% of the thermal conductivity of aluminum. Aluminum also has good acoustic attenuation properties which helps minimize dissipation. The electric resistance of the IDT fingers can be reduced, and the thermal conductivity of the IDT fingers can be increased, by increasing the cross-sectional area of the fingers to the extent possible. As described in conjunction withFIG.3, unlike SAW or AlN BAW, for XBAR there is little coupling of the primary acoustic mode to the IDT fingers. Changing the width and/or thickness of the IDT fingers has minimal effect on the primary acoustic mode in an XBAR device. This is a very uncommon situation for an acoustic wave resonator. However, the IDT finger geometry does have a substantial effect on coupling to spurious acoustic modes, such as higher order shear modes and plate modes that travel laterally in the piezoelectric diaphragm. Given the complex dependence of spurious mode frequency and amplitude on diaphragm thickness ts, IDT metal thickness tm, IDT pitch p and IDT finger width w, the inventors undertook an empirical evaluation, using two-dimensional finite element modeling, of a large number of hypothetical XBAR resonators. For each combination of diaphragm thickness ts, IDT finger thickness tm, and IDT pitch p, the XBAR resonator was simulated for a sequence of IDT finger width w values. A figure of merit (FOM) was calculated for each value if w to estimate the negative impact of spurious modes. The FOM is calculated by integrating the negative impact of spurious modes across a defined frequency range. The FOM and the frequency range depend on the requirements of a particular filter. The frequency range typically includes the passband of the filter and may include one or more stop bands. Spurious modes occurring between the resonance and anti-resonance frequencies of each hypothetical resonator were given a heavier weight in the FOM than spurious modes at frequencies below resonance or above anti-resonance. Hypothetical resonators having a minimized FOM below a threshold value were considered potentially “useable”, which is to say probably having sufficiently low spurious modes for use in a filter. Hypothetical resonators having a minimized cost function above the threshold value were considered not useable. FIG.9is a chart900showing combinations of IDT pitch and IDT finger thickness that may provide useable resonators. This chart is based on two-dimensional simulations of XBARs with lithium niobate diaphragm thickness ts=400 nm, aluminum conductors, and front-side dielectric thickness tfd=0. XBARs with IDT pitch and thickness within shaded regions910,915,920,930are likely to have sufficiently low spurious effects for use in filters. For each combination of IDT pitch and IDT finger thickness, the width of the IDT fingers was selected to minimize the FOM. Usable resonators exist for IDT finger thickness greater than or equal to 340 nm and less than or equal to 1000 nm. As previously discussed, wide bandwidth filters using XBARs may use a thicker front-side dielectric layer on shunt resonators than on series resonators to lower the resonance frequencies of the shunt resonators with respect to the resonance frequencies of the series resonators. The front-side dielectric layer on shunt resonators may be as much as 150 nm thicker than the front side dielectric on series resonators. For ease of manufacturing, it may be preferable that the same IDT finger thickness be used on both shunt and series resonators. FIG.10is another chart1000showing combinations of IDT pitch and IDT finger thickness that may provide useable resonators. This chart is based on simulations of XBARs with lithium niobate diaphragm thickness=400 nm, aluminum conductors, and tfd=100 nm. XBARs having IDT pitch and thickness within shaded regions1010,1020,1030are likely to have sufficiently low spurious effects for use in filters. For each combination of IDT pitch and IDT finger thickness, the width of the IDT fingers was selected to minimize the FOM. Usable resonators exist for IDT finger thickness greater than or equal to 350 nm and less than or equal to 900 nm. Assuming that a filter is designed with no front-side dielectric layer on series resonators and 100 nm of front-side dielectric on shunt resonators,FIG.9andFIG.10jointly define the combinations of metal thickness and IDT pitch that result in useable resonators. Specifically,FIG.9defines useable combinations of metal thickness and IDT pitch for series resonators andFIG.10defines useable combinations of metal thickness and IDT for shunt resonators. Since only a single metal thickness is desirable for ease of manufacturing, the overlap between the ranges defined inFIG.9andFIG.10defines the range of metal thicknesses for filter using a front-side dielectric to shift the resonance frequency of shunt resonator. ComparingFIG.9andFIG.10, IDT aluminum thickness between 350 nm and 900 nm (350 nm≤tm≤900 nm) provides at least one useable value of pitch for both series and shunt resonators. FIG.11is another chart1100showing combinations of IDT pitch and IDT finger thickness that may provide useable resonators. The chart is comparable toFIG.9with copper, rather than aluminum, conductors.FIG.11is based on simulations of XBARs with lithium niobate diaphragm thickness=400 nm, copper conductors, and tfd=0. XBARs having IDT pitch and finger width within shaded regions1110,1120,1130,1140are likely to have sufficiently low spurious effects for use in filters. For each combination of IDT pitch and IDT finger thickness, the width of the IDT fingers is selected to minimize the FOM. Usable resonators exist for IDT finger thickness greater than or equal to 340 nm and less than or equal to 570 nm, and for IDT finger thickness greater than or equal to 780 nm and less than or equal to 930 nm. FIG.12is another chart1200showing combinations of IDT pitch and IDT finger thickness that may provide usable resonators. This chart is based on simulations of XBARs with lithium niobate diaphragm thickness=400 nm, copper conductors, and tfd=100 nm. XBARs having IDT pitch and finger thickness within shaded regions1210,1220are likely to have sufficiently low spurious effects for use in filters. For each combination of IDT pitch and IDT finger thickness, the width of the IDT fingers is selected to minimize the cost function. IDT finger thickness greater than or equal to 340 nm and less than or equal to 770 nm Assuming that a filter is designed with no front-side dielectric layer on series resonators and 100 nm of front-side dielectric on shunt resonators,FIG.11andFIG.12jointly define the combinations of metal thickness and IDT pitch that result in useable resonators. Specifically,FIG.11defines useful combinations of metal thickness and IDT pitch for series resonators andFIG.12defines useful combinations of metal thickness and IDT pitch for shunt resonators. Since only a single metal thickness is desirable for ease of manufacturing, the overlap between the ranges defined inFIG.11andFIG.12defines the range of metal thicknesses for filter using a front-side dielectric to shift the resonance frequency of shunt resonator. ComparingFIG.11andFIG.12, IDT copper thickness between 340 nm and 570 nm provides at least one useable value of pitch for series and shunt resonators. Charts similar toFIG.9,FIG.10,FIG.11, andFIG.12, can be prepared for other values of front-side dielectric thickness, and other conductor materials such as Gold. FIG.13is a chart1300showing combinations of IDT pitch and IDT finger thickness that may provide useable resonators on different thickness diaphragms. The shaded regions1310,1315,1320define useable combinations of IDT pitch and aluminum IDT thickness for a diaphragm thickness of 500 nm. The areas enclosed by solid lines, such as line1330, define useable combinations of IDT pitch and aluminum IDT thickness for a diaphragm thickness of 400 nm. The solid lines are the boundaries of the shaded areas910,915, and920ofFIG.9. The areas enclosed by dashed lines, such as line1340, define useable combinations of IDT pitch and aluminum IDT thickness for a diaphragm thickness of 300 nm. Although the combinations of IDT thickness and pitch that result in useable resonators on 500 nm diaphragms (shaded regions1310,1315,1320), 400 nm diaphragms (regions enclosed by solid lines), and 300 nm diaphragms (regions enclosed by dashed lines) are not identical, the same general trends are evident. For diaphragm thicknesses of 300, 400, and 500 nm, useable resonators may be made with IDT metal thickness less than about 0.375 times the diaphragm thickness. Further, for diaphragm thicknesses of 300, 400, and 500 nm, useable resonators may be made with IDT aluminum thickness greater than about 0.85 times the diaphragm thickness and up to at least 1.5 times the diaphragm thickness. Although not shown inFIG.13, it is believed that the conclusions drawn fromFIG.9toFIG.12can be scaled with diaphragm thickness. For aluminum IDT conductors, the range of IDT thickness that will provide useful resonators is given by the formula 0.85≤tm/ts≤2.5. For filters using a front-side dielectric to shift the resonance frequency of shunt resonators, the range of aluminum IDT thickness that will provide useful resonators is given by the formula 0.875≤tm/ts≤2.25. For copper IDT conductors, the range of IDT thickness that will provide useful resonators is given by the formula 0.85≤tm/ts≤1.42 or the formula 1.95≤tm/ts≤2.325. For filters using a front-side dielectric to shift the resonance frequency of shunt resonators, the range of aluminum IDT thickness that will provide useful resonators is given by the formula 0.85≤tm/ts≤1.42. Experimental results indicate that thin IDT fingers (i.e., tm/ts<0.375) cannot adequately transport heat out of the resonator area and IDTs with such thin IDT fingers are unsuitable for high power applications. Thick IDT conductors (i.e., tm/ts>0.85) provide greatly improved heat transport. Experimental results indicate that filters using XBAR resonators with 500 nm aluminum IDT fingers and 400 nm diaphragm thickness (tm/ts=1.25) can tolerate 31 dBm CW (continuous wave) RF power input at the upper edge of the filter passband (commonly the frequency with the highest power dissipation within a filter passband). FIG.14is a graph1400of relationships between XBAR performance and IDT pitch. The solid curve1410is a plot of the resonance frequency of the XBAR shear primary mode as a function of IDT pitch for an XBAR with a z-cut lithium niobate diaphragm 400 nm thick and aluminum conductors 100 nm thick. The solid curve1410is read against the left vertical axis of the graph. The diaphragm thickness is the dominant parameter that determines resonance frequency of an XBAR. The resonance frequency has a smaller dependence on IDT pitch. As shown inFIG.14, varying the IDT pitch from 1 μm to 6 μm results in reduction in resonance frequency by about 25%. The dashed curve1420is a plot of the resonance frequency of the A1-3 spurious mode of the same XBAR as a function of IDT pitch. The dashed curve1420is read against the left vertical axis of the graph. Diaphragm thickness is also the dominant parameter that determines resonance frequency of A1-3 mode. However, the resonance frequency of the A1-3 mode has a much larger dependence on IDT pitch compared to the shear primary mode. Varying the IDT pitch from 1 μm to 6 μm results in reduction in resonance frequency of the A1-4 mode by about 85%. The frequencies of other spurious modes (i.e., spurious modes640inFIG.6) are also very dependent on IDT pitch. The dot-dash curve1430is a plot of electromechanical coupling of the shear primary mode as a function of IDT pitch. The dot-dash curve1430is read against the right vertical axis of the graph. The relationship between coupling and pitch is nonlinear. Larger IDT pitch results in higher coupling and coupling decreases rapidly for pitch values less than 3 μm. However, 17% coupling is available at pitch value of 1 μm, which is still sufficient for many filter applications. FIG.15is a graph1500of relationships between XBAR performance and IDT mark-to-pitch ratio (mark/pitch). The solid curve1510is a plot of the resonance frequency of the XBAR shear primary mode as a function of IDT mark/pitch for an XBAR with a z-cut lithium niobate diaphragm 400 nm thick. The solid curve1510is read against the left vertical axis of the graph. The IDT conductors are aluminum 100 nm thick and the IDT pitch is 3 μm. The diaphragm thickness is the dominant parameter that determines resonance frequency of an XBAR. The resonance frequency has a smaller dependence on IDT mark/pitch. As shown inFIG.15, varying the IDT mark/pitch from 0.15 to 0.45 μm results in reduction in resonance frequency by about 6%. The dashed curve1520is a plot of electromechanical coupling of the shear primary mode as a function of IDT mark/pitch. The dashed curve1520is read against the right vertical axis of the graph. The relationship between coupling and mark/pitch is nonlinear. Maximum coupling occurs for IDT mark/pitch between 0.40 and 0.45. Coupling decreases with decreasing mark/pitch. However, 27% coupling is available at mark/pitch value of about 0.12, which is sufficient for most filter applications. FIG.14andFIG.15illustrate the complexity of selecting the pitch and mark of XBAR IDTs within a filter to provide a desired resonance frequency and electromechanical coupling of each XBAR while trying to place spurious modes at frequencies that do not degrade the filter performance. In particular, since the resonance frequency of the shear primary acoustic mode varies with both IDT pitch and IDT mark, the pitch and mark must be selected in combination to set the resonance frequency of an XBAR to a predetermined target frequency. Since the same resonance frequency may be achieved with different IDT pitch and mark combinations, a filter designer has some freedom to select the pitch and mark to control the frequencies of spurious modes. FIG.16is a graph1600of relationships between the A1-3 spurious mode and IDT mark-to-pitch ratio (mark/pitch). The solid curve1610is a plot of the resonance frequency of the A1-3 mode as a function of IDT mark/pitch for an XBAR with a z-cut lithium niobate diaphragm 400 nm thick. The solid curve1610is read against the left vertical axis of the graph. The IDT conductors are aluminum 100 nm thick and the IDT pitch is 3 μm. The A1-3 mode resonance frequency depends on IDT mark/pitch. As shown inFIG.9, varying the IDT mark/pitch from 0.15 to 0.45 μm results in reduction in resonance frequency by about 10%. The dashed curve1620is a plot of the absolute admittance of the A1-3 mode as a function of IDT mark/pitch. The dashed curve1620is read against the right vertical axis of the graph. The relationship between admittance and mark/pitch is nonlinear. Minimum admittance occurs for IDT mark/pitch from 0.235 to 0.265. The admittance increases for mark/pitch values outside of this range but is still small for a mark/pitch range from 0.2 to 0.3. The resonance and anti-resonance frequencies of the primary acoustic mode of an XBAR is determined by multiple factors including the type, crystallographic orientation, and thickness of the piezoelectric slab and the pitch and mark of the IDT fingers. In particular, different combinations of mark and pitch on the same piezoelectric diaphragm can excite the same primary acoustic mode. In this context, two acoustic modes are considered to be the same if the two acoustic modes have the same direction of acoustic energy flow and the same resonance and/or anti-resonance frequencies. A radio frequency or microwave signal applied across the IDT of an XBAR may also excite undesired spurious acoustics modes. The frequency and strength of such spurious acoustic modes also depend on multiple factors including the pitch and mark of the IDT fingers. However, two or more mark/pitch combinations that excite the same primary acoustic mode do not necessarily excite the same spurious modes. When the pitch and mark within an IDT is changed between two or more mark/pitch combinations that produce the same primary acoustic mode but different spurious modes, the different spurious modes will not add constructively over the area of the IDT. The XBAR primary acoustic mode is mostly bulk in nature, which can result in weak frequency dependence on mark and pitch. Thus, chirping (or variance) of mark, or mark and pitch, in the IDT of the XBAR can potentially suppress undesirable spurious modes that depend upon mark and/or pitch, such as metal and propagating modes, with only slight broadening of the primary mode resonance. FIG.17is an expanded schematic plan view of a unit cell1700for an IDT where the pitch and mark vary along the length of the IDT. The scale of the plan view has been stretched or expanded horizontally for ease of presentation of the various dimensions. In the unit cell1700, P1is a first pitch value, P2is a second pitch value, M1is a first mark value and M2is a second mark value. The differences between P1and P2and between M1and M2are exaggerated for ease of visualization. An IDT having a pitch P1and a mark M1would excite a primary acoustic mode with particular resonance and antiresonance frequencies. An IDT having a pitch P2and a mark M2would excite the same primary acoustic mode, which is to say a primary acoustic mode with the same resonance and/or antiresonance frequencies. The unit cell1700includes a first set of IDT fingers1712,1714,1716extending from an upper busbar1710, and a second set of IDT fingers1722,1724extending from a lower busbar1720. In this patent, directional terms such as upper, lower, left, right, vertical, horizontal, etc. refer to direction or position within the drawing being discussed and do not imply any physical position or orientation. The unit cell1700is intended to be cascaded in the horizontal direction (as will be described in conjunction withFIG.18) to form an IDT. The unit cell1700only includes portions of the end fingers1712and1716. Other portions of those fingers exist within adjacent unit cells (not shown inFIG.17). The unit cell1700is divided into a first pitch/mark zone1730and a second pitch/mark zone1740. Within the first pitch/mark zone1730, the pitch between adjacent fingers is P1and the mark of the fingers is M1. Within the second pitch/mark zone1740, the pitch between adjacent fingers is P2and the mark of the fingers is M2. The mark/pitch combination of the IDT changes between M1/P1and M2/P2every two fingers. To this end, each finger1712,1714,1716of first set of IDT fingers extending from the upper busbar1710has a uniform width of (M1+M2)/2, including portions of fingers1712and1716within adjacent unit cells. Note that the pitch is not measured to the respective centers of the first set of IDT fingers, but to a dashed line that divides each finger in a ratio of M1/M2. For example, finger1714is divided such that the portion of the finger extending left into the 1stpitch/mark zone1730has a width of M1/2, and the portion of this finger extending right into the 2ndpitch/mark zone1740has a width of M2/2. The second set of IDT fingers1722,1724extending from the lower busbar1720has a center-to-center distance between adjacent fingers equal to P1+P2. The mark of the second set of IDT fingers1722,1724alternates between M1(e.g., finger1722) and M2(e.g., finger1724). The net effect is that the unit cell1700has two periods of pitch P1and mark M1followed by two periods of pitch P2and mark M2. The unit cell1700may be cascaded to provide an IDT with any desired length with a corresponding number of fingers.FIG.18is a schematic plan view of an IDT1800composed of eight copies1700A to1700H of the unit cell1700juxtaposed along the length of the IDT1800resulting in a total of 33 fingers. The IDT1800is shown reasonably to scale (approximately 1600:1), with the exception that the differences between P1and P2and between M1and M2are still exaggerated for ease of visualization. The IDT1800has eight first pitch/mark zones1830A to1830H in which the pitch and mark are P1and M1, respectively. The eight first pitch/mark zones1830A to1830H are interleaved with eight second pitch/mark zones1840A to1840H, in which the pitch and mark are P2and M2, respectively. A pattern of two periods of pitch P1and mark M1alternating with two periods of pitch P2and mark M2is continued along the length of the IDT. Using eight copies of the unit cell1700is exemplary and an IDT may use more or fewer than 8 unit cells and have more or fewer than 33 fingers. FIG.19is a plan view of an exemplary multi-mark IDT1900. A “multi-mark IDT” is an IDT where the mark of the IDT fingers varies along the length of the IDT. At any given point along the length, the mark may not vary across the aperture of the IDT. Further, the pitch, can be constant over the entire IDT. The multi-mark IDT1900may be a portion of an XBAR such as the XBAR100ofFIG.1. The multi-mark IDT1900includes a first busbar1932, and a second busbar1934, and a plurality of interleaved fingers such as finger1936. The interleaved fingers extend alternately from the first and second busbars1932,1934. The multi-mark IDT1900is divided into three sections, identified as Section A, Section B, and Section C, along the length L of the IDT. Each of Sections A, B, and C includes 20 fingers, for a total of 60 fingers in the multi-mark IDT1900. The use of three sections and 60 fingers is exemplary. An IDT may have more than or fewer than 60 total fingers. An IDT may be divided along its length into two or more sections, each of which includes a plurality of adjacent fingers. The total number of fingers may be divided essentially equally between the two or more sections. In this context, “essentially” means “as close as possible.” For example, an IDT with 100 fingers divided into three sections with 33, 34, and 33 fingers is considered to be divided essentially equally. The total number of fingers may be divided unequally between the two or more sections. In this example, the fingers in Section B have mark m, which is the nominal mark of the IDT. The finger of Section A have a mark of m(1−δm), and the fingers of Section C have a mark of m(1+δm). δmis greater than 0 and less than or equal to 0.05. δmmay typically be less than 0.01. δmmay be selected during a filter design to achieve the most effective reduction of spurious modes. At any point along the length L of the IDT1900, the mark is constant across the aperture A. The pitch of the IDT fingers is constant and the same in all sections. When an IDT is divided into two sections or more than three sections, the maximum mark may be m(1+δm) and the minimum mark may be m(1−δm). In the example multi-mark IDT1900, the mark increases monotonically from left (as seen in the figure) to right. This is not necessarily the case in all multi-mark IDTs. The sections of a multi-mark IDT may be arranged in some other order. Further, in the multi-mark IDT1900, the change in mark between adjacent sections is constant. This is also not necessarily the case in all multi-mark IDTs. The change in mark between adjacent sections may be the same or different. FIG.20is a plan view of another multi-mark IDT2000with continuously varying mark. The IDT2000includes a first busbar2032, and second busbar2034, and a plurality of interleaved fingers such as finger2036. The interleaved fingers extend alternately from the first and second busbars2032,2034. The IDT2000is not divided into sections, but rather has a continuous change in mark for the fingers2036along its length L. The IDT2000has 60 fingers, which is exemplary. An IDT may have more than or fewer than 60 total fingers. The multi-mark IDT2000may be a portion of an XBAR such as the XBAR100ofFIG.1. As shown inFIG.20, the mark at the left edge of the IDT500is m(1−δm), and the mark at the right edge of the IDT500is m(1+δm). The mark varies continuously between these two extremes. The variation in mark may typically, but not necessarily, be a linear function of position along the length L of the IDT. δmis greater than 0, less than or equal to 0.05, and typically less than 0.01. δmmay be selected during a filter design to achieve the most effective reduction of spurious modes. At any point along the length of the IDT2000, the mark is constant across the aperture A. The pitch of the IDT fingers is constant over the entire IDT. Slight variations in the mark of the IDT in an XBAR can result in disruption or destructive interference of spurious modes with negligible effect on the shear primary mode. Multi-mark IDTs may be divided into two sections or more than three sections, or may be continuous. The number of sections may not be the same for all resonators in a filter, and a filter may include both sectioned and continuous multi-mark IDTs. The value of δmmay be different for some or all of the resonators. A filter may contain a combination of resonators with uniform mark and multi-mark resonators. In other examples, the pitch of the IDT can vary continuously, similar to the continuous variation of mark shown inFIG.20. The pitch may vary as the mark varies, or may vary at a different rate. The pitch and mark may both vary continuously. The pitch and/or the mark may vary between multiple maxima and minima along the length of the IDT. The mark may vary by section while the pitch varies continuously, or pitch may vary by section while the mark varies continuously. The mark may increase in one direction along the length of the IDT (either continuously or by section), while the pitch decreases in the same direction (either continuously or by section). Variation of mark and pitch can be optimized with respect to one another, and variation of mark and pitch can be different from one resonator to another, such that greatest suppression of spurious modes is achieved for best performance of the filter. FIG.21is a graphical illustration of Euler angles2100. Euler angles are a system, introduced by Swiss mathematician Leonhard Euler, to define the orientation of a body with respect to a fixed coordinate system. The orientation is defined by three successive rotations about angles α, β, and γ. As applied to acoustic wave devices, xyz is a three-dimensional coordinate system aligned with the crystalline axes of the piezoelectric material. XYZ is a three-dimensional coordinate system aligned with the acoustic wave device, where Z is normal to the surface of the piezoelectric material. XY is the plane of the surface of the piezoelectric material. X is the direction of the electric field and acoustic wave propagation for SAW and most plate-mode devices, and Y is typically parallel to the fingers on an IDT. In XBAR devices, X is the direction of the electric field, but acoustic wave propagation is dominantly along the Z direction. All of the XBAR devices described in application Ser. No. 16/230,443 and application Ser. No. 16/381,141 use piezoelectric plates with the z axis normal to the plate surface and the y axis orthogonal to the IDT fingers. Such piezoelectric plates have Euler angles of 0, 0, 90°. For historical reasons, lithium niobate plates having Euler angles [0°, β, 0°] are commonly referred to as “Y-cut”, where the “cut angle” is the angle between the y axis and the normal to the plate. The “cut angle” is equal to β+90°. For example, a plate with Euler angles [0°, 30°, 0°] is commonly referred to as “120° rotated Y-cut”. FIG.22is a graph2200of two piezoelectric coefficients e15 and e16 for lithium niobate plates having Euler angles [0°, β, 0°]. The solid line2210is a plot of piezoelectric coefficient e15 relating electric field along the x axis to shear stress or torque εxz axis as a function of β. This shear stress excites the shear primary acoustic mode shown inFIG.3. The dashed line2220is a plot of piezoelectric coefficient e16 relating electric field along the x axis to shear stress or torque εxy as a function of β. This shear stress excites horizontal shear modes (e.g., the SH0 plate mode) with atomic displacements normal to the plane ofFIG.3, which are undesired parasitic modes in an XBAR. Note that these two curves are identical and shifted by 90°, (as y-axis shifted from x-axis). Inspection ofFIG.22shows that the first piezoelectric stress coefficient is highest for Euler angle β about 30°. The first piezoelectric stress coefficient is higher than about 3.8 (the highest piezoelectric stress coefficient for an unrotated Z-cut lithium niobate) for 0°≤β≤60°. The second piezoelectric stress coefficient is zero for Euler angle β about 30°, where the first piezoelectric stress coefficient is maximum. In this context “about 30°” means “within a reasonable manufacturing tolerance of 30°”. The second piezoelectric stress coefficient is less than about 10% of the first piezoelectric stress coefficient for 26°≤β≤34°. Shear wave velocity and diaphragm thickness are both temperature dependent, with the temperature coefficient of shear wave velocity (TCV) being the dominant factor in the temperature dependence of resonance frequency. The difference between the resonance and anti-resonance frequencies of an XBAR is determined, in part, by the electro-mechanical coupling between the electric field and the primary shear wave. This coupling depends on piezoelectric coupling coefficient e15. e15is an element of a 3×6 matrix of piezoelectric coupling coefficients that describe the physical response of a piezoelectric material to an applied electric field. A larger value of e15results in more efficient coupling to the primary shear acoustic mode, which results in wider spacing between the resonance and anti-resonance frequencies of an XBAR. FIG.23is a chart2300of piezoelectric coupling coefficient e15and temperature coefficient of velocity TCV as functions of Euler angle β for lithium niobate with Euler angles (0°, β, 0°). Specifically, the solid curve2310is a plot of TCV versus β. The solid curve2310is read against the left-hand axis. TCV is expressed in part per million per degree Celsius (ppm/° C.). The dashed curve2320is a plot of e15versus β. The dashed curve2320is read against the right-hand axis. Lithium niobate crystal orientations previously used for XBARs include Z-cut and rotated Y-cut. Z-cut has Euler angles=(0°, 0°, 90°). Rotated Y-cut has Euler angles=(0°, β, 0°), with β between 30 and 38 degrees. Z-cut lithium niobate has a TCV of about −102 ppm/° C. and e15of about 3.7. Rotated Y-cut lithium niobate has e15about 4.4 and TCV between about −86 ppm/° C. and −92 ppm/° C. Inspection ofFIG.23shows that rotated Y-cut lithium niobate with β about 67 degrees (broken line432) has a value of e15of about 3.7 (broken line434) which is equivalent to the e15for Z-cut lithium niobate. Rotated Y-cut lithium niobate with β about 67 degrees has a TCV of about −73 ppm/° C., which is 30% smaller (in magnitude) than the TCV of Z-cut lithium niobate. Filters comprised of XBARs using lithium niobate piezoelectric plates with β substantially equal to 67° may have performance comparable to filters using Z-cut lithium niobate with significantly less frequency dependence on temperature. In this and similar contexts, “substantially equal” means equal with defined manufacturing tolerances. The range from β=38° to β=67° offers a continuous trade-off between piezoelectric coupling and TCV. For example, a rotated Y-cut lithium niobate plate with β=60° offers 5% higher piezoelectric coupling than a plate with β=67° with only a small increase in the magnitude of TCV. The bandwidth and other requirements of a particular filter may dictate a minimum value for e15. The Euler angles (0°, β, 0°) of the piezoelectric plate may be selected with β set to the highest value in the range from 40° to 67° that provides the required minimum value of e15, while minimizing, to the extent possible, the TCF of the filter. FIG.24is a chart2400of the electromechanical coupling coefficient of representative XBAR devices using piezoelectric plates with Euler angles 0, β, 90°, where β is in the range from −15° to +5°. The chart inFIG.24is based on simulation of XBAR devices using finite element methods. The line2410is a plot of electromechanical coupling coefficient as a function of β. Inspection of the chart2400shows that the electromechanical coupling coefficient is greater than 0.26 for β greater than or equal to −11° and less than or equal to −5°, as compared to a value of about 0.243 for β=0. The Q-factor of an acoustic resonator is commonly defined as the peak energy stored during a cycle of the applied RF signal divided by the total energy dissipated or lost during the cycle. The Q-factor of an XBAR is a complex function of numerous parameters including the length, or number of fingers, in the IDT of the XBAR. Possible loss mechanisms in an acoustic resonator include resistive losses in the IDT and other conductors; viscous or acoustic losses in the piezoelectric plate, IDT fingers, and other materials; and leakage of acoustic energy out of the resonator structure. The peak energy stored in a resonator is proportional the capacitance of the resonator. In an XBAR resonator, the capacitance is proportional to the number of IDT fingers. Resistive losses and viscose losses are also proportional to the number of IDT fingers. Acoustic energy that leaks from the resonator in the transverse direction (i.e., the direction parallel to the IDT fingers) is proportional to the length of the resonator and thus also proportional to the number of IDT fingers. In contrast, energy lost from the ends of the IDT in the longitudinal direction (i.e., the direction normal to the IDT fingers) is roughly constant, independent of the number of IDT fingers. As the number of IDT fingers and the peak energy stored in an XBAR is reduced, the acoustic energy lost in the longitudinal direction becomes an ever-increasing fraction of the peak energy stored. FIG.25is a plan view of an exemplary conductor pattern2500that reduces the acoustic energy leakage in the longitudinal direction at the ends of an XBAR. The conductor pattern2500includes an IDT2530and four reflector elements2562,2564,2566,2568. The IDT2530includes a first busbar2532, a second busbar2534, and a plurality of n interleaved IDT fingers extending alternately from the first and second busbars. In this example, n, the number of IDT fingers, is equal to 24. In other XBARs, n may be in a range from 20 to 100 or more IDT fingers. IDT finger2536is the 1stfinger and IDT finger2538is the n'th finger. Numbering the IDT fingers from left to right (as shown inFIG.25) is arbitrary and the designations of the 1stand n'th fingers could be reversed. As shown inFIG.25, the odd numbered IDT fingers extend from the first busbar432and the even numbered IDT fingers extend from the second busbar2534. The IDT2530has an even number of IDT fingers such that the 1stand n'th IDT fingers2536,2538extend from different busbars. In some cases, an IDT may have an odd number of IDT fingers such that the 1stand n'th IDT fingers and all of the reflector elements extend from the same busbar. A total of four reflector elements are provided outside of periphery of the IDT2530. A first reflector element2562is proximate and parallel to 1st IDT finger2536at the left end of the IDT2530. A second reflector element2566is proximate and parallel to n'th IDT finger2538at the right end of the IDT2530. An optional third reflector element2564is parallel to the first reflector element2562. An optional fourth reflector element2568is parallel to the second reflector element2566. First and third reflector elements2562,2564extend from the first busbar2532and thus are at the same electrical potential as the 1st IDT finger2536. Similarly, second and fourth reflector elements2566and2568extend from the second busbar2530and thus are at the same electrical potential as the n'th IDT finger2538. The reflector elements2562,2564,2566,2568are configured to confine acoustic energy to the area of the IDT2530and thus reduce acoustic energy losses in the longitudinal direction. To this end, the pitch pr between adjacent reflector elements and between reflector elements2562and2566and the adjacent first and n'th IDT fingers, respectively, is typically greater than the pitch p of the IDT fingers. The width or mark mr of the reflector elements2562,2564,2566,2568is not necessarily equal to the mark m of the IDT fingers. As will be described subsequently, the mark mr of the reflector elements may be selected to optimize Q-factor at a specific frequency or range of frequencies. In other embodiments, reflector elements (e.g., four reflector elements are provided outside of periphery of the IDT. First and third reflector elements are proximate and parallel to 1st IDT finger at the left end of the IDT that are connected to each other but are not connected to either busbar. First and third reflector elements are capacitively coupled to 1st IDT finger and thus are at substantially the same electrical potential as the 1st IDT finger. The reflector elements are considered to be at substantially the same potential if, when an RF signal is applied between the busbars, the potential between the reflector elements and the 1stIDT finger is small compared to the potential between adjacent IDT fingers. Similarly, second and fourth reflector elements are proximate and parallel to n'th IDT finger at the right end of the IDT. Second and fourth reflector elements are connected to each other and not connected to either busbar. Second and fourth reflector elements are capacitively coupled to the n'th IDT finger and thus are at nearly the same electrical potential as the n'th IDT finger. FIG.26Ais a schematic cross-sectional view of an XBAR device2600A with an etch-stop layer and back-side etched cavities. The XBAR device2600A includes two XBARs, each of which is similar to the XBAR100ofFIG.1. A back surface2614of a piezoelectric plate2610is attached to a substrate2620. An electrode pattern is formed on a front surface2612of the piezoelectric plate2610. The electrode pattern includes interleaved fingers2630of respective IDTs for the two XBARs. The IDT fingers2630are disposed over respective cavities2640A formed in the substrate2620. The materials of the piezoelectric plate, substrate, and electrode pattern are as previously described. The primary difference between the XBAR device2600A and the XBAR100ofFIG.1is the presence of an etch-stop layer2650sandwiched between the piezoelectric plate2610and the substrate2620. The term “sandwiched” means the etch-stop layer2650is both disposed between and physically connected to a surface of the substrate2620and the back surface2614of the piezoelectric plate2610. In some embodiments, as will be described subsequently, layers of additional materials may be disposed between the etch-stop layer2650and the surface of the substrate2620and/or between the etch-stop layer2650and the back surface2614of the piezoelectric plate2610. In XBAR device2600A, the piezoelectric plate2610is not bonded directly to the substrate2620but is attached to the substrate2620via the etch-stop layer2650. The cavities2640A are formed by using an etch process to remove material from the substrate. The etch process may be a “wet” process using a liquid etchant, or a “dry” process such as reactive ion etching or sputter etching that use a gaseous etchant. As represented by the dashed arrow2660A, the etch process proceeds from the back surface of the substrate and progressively removes material from the substrate until the cavities2640A are formed. In the absence of the etch-stop layer2650, at least a portion of the back surface2614of the piezoelectric plate2610would be exposed to the etch process2660. The performance of the XBAR2600A is sensitive to the thickness of the piezoelectric and, to at least some extent, to the smoothness of the back surface2614. Any erosion of the back surface2614by the etch process2660may have a deleterious effect on the performance of the XBAR2600A. The etch-stop layer2650protects the back surface2614from the etch process. To this end, the etch-stop layer2650is impervious to the etch process represented by the dashed arrow2660A. The word “impervious” has several definitions including “not affected by” and “not allowing fluid to pass though”. Both of these definitions apply to the etch-stop layer2650. The etch-stop layer is not materially affected by the etch process and does not allow the liquid or gaseous etchant used in the etch process to penetrate to the piezoelectric layer2610. The etch-stop layer need not be inert with respect to the etchant but must be highly resistant to the etchant such that a substantial portion of the etch stop layer remains after completion of the cavity etch. The remaining etch stop layer2650is not removed after the cavities2640A are formed and becomes a portion of the diaphragms of the XBAR devices. The etch-stop layer2650is formed from an etch-stop material. The etch-stop material must be a dielectric with very low conductivity and low acoustic loss. The etch-stop material must have high adhesion to the surface(s) on which it is formed. Further, the etch-stop material must be compatible with attaching the piezoelectric plate to the substrate with a wafer bonding process. Most importantly, the etch-stop material must be impervious, as previously defined, to the processes and chemicals used to etch the substrate material. Suitable etch-stop materials may include oxides such as aluminum oxide and silicon dioxide, sapphire, nitrides including silicon nitride, aluminum nitride, and boron nitride, silicon carbide, and diamond. When the etch-stop material is a high thermal conductivity dielectric, such as aluminum nitride, boron nitride, or diamond, the etch-stop layer will help conduct heat away from the diaphragm of the XBAR. As described in U.S. Pat. No. 10,491,192, a dielectric layer2670may be selectively formed on the front side of the piezoelectric plate2610over the IDTs2630of some XBARs. For example, a frequency setting dielectric layer may be formed over the IDTs of shunt resonators to lower their resonant frequencies with respect to the resonant frequencies of series resonators in a filter. The electromechanical coupling efficiency of an XBAR may be reduced and spurious modes may be enhanced if the total thickness of dielectric layers on the front and back surfaces of the piezoelectric plate exceeds about 35% of the piezoelectric plate thickness. Further, filters designed for broad communications bands such as band n77 and band n79 may require a frequency setting layer with a thickness of 20% to 30% of the piezoelectric plate thickness. To allow flexibility in selection of the frequency setting layer thickness, the thickness tesof the etch-stop layer2650may be less than or equal to 10% of the piezoelectric plate thickness, and preferably about 4% to 6% of the piezoelectric plate thickness. When a frequency setting dielectric layer is not used, the thickness tesmay be less than about 20% of the piezoelectric plate thickness. FIG.26Bis a schematic cross-sectional view of an XBAR device2600B with an etch-stop layer and front-side etched cavities. The XBAR device2600B includes two XBARs, each of which is similar to the XBAR100ofFIG.1. A back surface of a piezoelectric plate2610is attached to a substrate2620. An etch-stop layer2650is sandwiched between the piezoelectric plate2610and the substrate2620. An electrode pattern is formed on a front surface of the piezoelectric plate2610. The electrode pattern includes interleaved fingers2630of respective IDTs for the two XBARs. The IDT fingers2630are disposed over respective cavities2640B formed in the substrate2620. The materials and characteristics of the piezoelectric plate2610, substrate2620, etch-stop layer2650, and electrode pattern2630are as previously described. The primary difference between the XBAR device2600B and the XBAR device2600A ofFIG.26Ais the etch process used to form the cavities2640B. The cavities2640B are formed with an etch process, represented by the dashed arrow2660B, using an etchant introduced though openings2642in the piezoelectric plate2610and the underlying etch-stop layer2650. FIG.27shows a schematic cross-sectional view and two detailed cross-sectional views of a filter2700using XBARs. A piezoelectric plate2710is attached to a substrate2720. An optional dielectric layer2725may be between the piezoelectric plate2710and the substrate2720. A portion of the piezoelectric plate2710forms a diaphragm2715spanning a cavity2740in the substrate. As shown, the cavity2740does not fully penetrate the substrate2720. Alternatively, the cavity2740may penetrate the substrate as shown inFIG.1. Fingers of an IDT are disposed on the diaphragm2715. Two conductors2750and2755are formed on the surface of the piezoelectric plate2710at a location removed from the cavity2740. The two conductors2750,2755may be signal conductors interconnecting XBARs and/or other components of the filter2700. The conductors2750and2755may be a signal conductor and a ground conductor. WhileFIG.27only shows a single XBAR and two conductors, a filter may include multiple XBARs and more than two signal and ground conductors. A preferred material for the substrate2720is silicon. Silicon wafers are readily available and inexpensive. Further, processes and equipment for handling silicon wafers are well developed. However, silicon is a semiconductor material. Silicon wafers may be doped, or loaded with impurities, to have a desired bulk resistivity. Undoped, or intrinsic, silicon wafers can form a conductive inversion layer along the boundary between the silicon and some other material, such as along the boundary of the silicon wafer2720and the dielectric layer2725of the filter device2700. If the dielectric layer2725is not present, the inversion layer may form along the boundary between the silicon wafer2720and the piezoelectric plate2710. As shown in Detail A ofFIG.27, conductors2750and2755are capacitively coupled to the substrate2720through the piezoelectric plate2710and the dielectric layer2725, if present. If the substrate2720is conductive, or if a conductive inversion layer is formed in the substrate2720, the conductors2750,2755will be effectively connected, at RF frequencies, by a parasitic resistance2760. Power dissipated in the resistance2760will contribute to the insertion loss of the filter2700. Detail B ofFIG.27, shows a cross-sectional view of a portion of a filter formed on a substrate2720including a high resistivity silicon wafer2722and a trap-rich region2724. The trap rich region2724may be a region within the high resistivity silicon wafer2722or a layer formed on a surface of the high resistivity silicon wafer2722. In either case, the trap-rich region is immediately adjacent the dielectric layer2725or the piezoelectric plate2710if the dielectric layer2725is not present. The trap-rich region2722has an abundance of traps that capture free carriers and reduce carrier lifetime to an extent that the conductivity of the trap-rich region approaches zero. A trap-rich region may be formed within a silicon substrate by irradiating the surface of the substrate with neutrons, protons, or various ions (silicon, argon, nitrogen, neon, oxygen, etc.) to create defects in the crystalline structure of the substrate. Alternatively, a trap-rich region may be formed within a silicon substrate by introducing deep trap impurities such as gold, copper, or other metal ions. Such impurities may be introduced by ion implantation, diffusion, or some other method. The trap-rich region may be formed by a combination of these techniques. When the dielectric layer2725is included in the filter2700, the trap-rich region2724may be formed before the dielectric layer is formed on the substrate2720. Alternatively, the trap-rich region2724may be form by ion implantation through the dielectric layer2725. A trap-region layer may be formed on a silicon substrate by depositing a layer of trap-rich material such as amorphous silicon or polysilicon (polycrystalline silicon). When the trap-rich region is polysilicon, the average grain size of the polysilicon should be substantially smaller than the minimum spacing between electrodes2750,2755. The thickness of the trap rich region formed on or within a high resistivity silicon substrate should be greater than the thickness of an inversion layer that may form in the absence of the trap-rich layer. FIG.28is a plan view of an XBAR2800with periodic etched holes. The XBAR2800includes a piezoelectric plate2810having parallel front and back surfaces2812,2814, respectively. The piezoelectric plate is a thin single-crystal layer of a piezoelectric material such as lithium niobate, lithium tantalate, lanthanum gallium silicate, gallium nitride, or aluminum nitride. The piezoelectric plate is cut such that the orientation of the X, Y, and Z crystalline axes with respect to the front and back surfaces is known and consistent. The back surface2814of the piezoelectric plate is attached to surface of a substrate2820. A portion of the piezoelectric plate forms a diaphragm spanning a cavity2840in the substrate2820. As shown inFIG.28, the cavity2840extends completely through the substrate2820. The cavity may only extend part way through the substrate, as shown inFIG.2AandFIG.2B. An IDT2830is formed on the surface of the piezoelectric plate2810. The IDT2830includes a first busbar2832and a second busbar2834. A first set of parallel fingers, such as finger2836extends from the first busbar2832. A second set of parallel fingers extends from the second busbar2834. The first and second sets of fingers are parallel and interleaved. At least the interleaved fingers of the IDT are disposed on the diaphragm. A periodic array of holes2880are formed in the diaphragm. As shown inFIG.28, the periodic array includes one hole at the end of each IDT finger. Specifically, a hole is disposed between the end of each of the first set of fingers and the second busbar and a hole is disposed between the end of each of the second set of fingers and the first busbar. Other periodic arrangements of the holes, such as at the ends of alternate IDT fingers may be used. The periodic array of holes2880has two effects on the performance of the XBAR2800. First, the holes scatter, and thus inhibit resonance of, spurious acoustic waves traveling parallel to the IDT fingers. Such spurious acoustic waves can introduce ripple in the input/output transfer function of XBAR filters. Second, the array of holes2880appears to increase the Q-factor of XBAR devices, possibly by helping to confine the primary shear acoustic mode to the aperture of the XBAR. As shown inFIG.28, the holes2880are right circular cylinders with a diameter approximately equal to the width of the IDT fingers. The size and shape of the holes inFIG.28is exemplary. The holes may be larger or smaller than the width of the IDT fingers and may have a cross-sectional shape other than circular. For example, the cross-sectional shape of the holes may be oval, square, rectangular, or some other shape. The holes need not necessarily pass through the piezoelectric plate. The holes may be blind holes that only extend part way though the thickness of the piezoelectric plate. The size and depth of the holes must be sufficient to create a domain with significantly reduced acoustic impedance. An additional benefit of holes at the ends of the IDT fingers is reduction of parasitic capacitance between the IDT finger tips and the adjacent busbar. To produce improved XBAR resonators and filters that efficiently conduct heat from the IDT or busbars to the substrate, predetermined areas of the bonding oxide layer (e.g., BOX) and/or piezoelectric layer can be removed from selected locations of the surface of the substrate of the device to provide a predetermined amount in reduction of thermal resistance between the conductor pattern and the substrate. The predetermined areas removed from the selected locations may be described as excess BOX and piezoelectric material that is removed because their removal does not affect or change the filtering performance (e.g., frequency range passed) by the filter. In some cases, the removal may change the performance by less than 5 percent of the frequency range and/or wave pass amplitude. In some cases, it is by less than 10 percent. It may be by less than 3 percent. In some cases, to produce improved XBAR resonators and filters with excess BOX and piezoelectric material removed, the portions or areas of the BOX and piezoelectric material of a plate or layer that extend a certain distance past the cavity perimeter of the cavities of filter may be removed. This removing may include removing the BOX and piezoelectric material: a) that extends in the length direction past the perimeter of the cavity by between 2 and 25 percent more the length of the cavity; and b) that extends in the width direction past the perimeter of the cavity by between 2 and 25 percent more the width of the cavity. This removing may include removing the excess BOX and piezoelectric material to provide a predetermined amount in reduction of thermal resistance between the conductor pattern and the substrate. This removing may include removing the excess BOX and piezoelectric material from locations immediately adjacent to (e.g., touching) contact layers and/or under contact bumps. It may include removing the BOX and piezoelectric material from outside of the XBAR resonators or diaphragms of an RF filter, such as from locations beside a cavity over which the resonator or diaphragm spans (e.g., is suspended or extends). FIG.29Ais a schematic cross-sectional view of XBAR device2900having predetermined areas of the bonding oxide layer2922(e.g., BOX layer) and piezoelectric layer2910removed from selected locations over the surface of the substrate of the device to provide a predetermined amount in reduction of thermal resistance between the IDT pattern2936and the substrate2920.FIG.29Amay be a view of the filter device at the section A-A ofFIG.1, section B-B ofFIG.1, and/or of plane A-A ofFIG.2A.FIG.29Ashows filter device2900comprising substrate2920having cavity2940. BOX layer2922is formed on the substrate and spans over the cavity2940. Piezoelectric plate2910is bonded to the bonding layer2922and spans the cavity2940. In some cases, bonding layer2922does not exist over the cavity2940and is only between where the plate is attached to the substrate. An interdigital transducer (IDT)2930formed on a front surface of the piezoelectric plate2910has busbars2932and2934; and interleaved fingers2936. Each of the busbars is attached to a set of fingers that form interleaved fingers2936. Fingers2936may span or be over cavity2940. In some cases, part of the busbars of the IDT are also over the cavity. In other cases, all of the busbars are over the substrate2920but not over the cavity. At least portions of the busbars are over the substrate (e.g., not over the cavity) to better conduct heat generated in the IDT to the substrate. Device2900has width WC of cavity2940; width WP of layers2922and2910; width WIDT of IDT2930. It also has lengths of the cavity, layers and IDT that are related to the widths, such as noted inFIG.1. The widths and corresponding length may define a perimeter of the cavity, layers (e.g., diaphragm) and IDT. Second metal layers2970and2971of M2 material are attached to the top of the substrate2920; to the side surfaces of bonding layer2922; to the side surfaces and part of the top surface of the piezoelectric layer2910; and to the side surfaces and part of the top surface of the IDT2936, such as to the top of the busbars and not to the top of the fingers2936. In some cases, the second metal layers2970and2971are a single metal layer extending around a perimeter of and form an island of the bonding layer2922, plate2910and IDT2930. The materials that can be used for the substrate, bonding layer, piezoelectric plate/layer, IDT, fingers, busbars, conductor pattern ofFIGS.5A and5Bmay be the same as those described forFIG.1. The material of layer M1 and layer M2 ofFIGS.5A-5Bmay be the same as those described forFIG.1. The bonding layer2922may be BOX such as silicon dioxide, Al2O3, silicon nitride, silicon carbide, SiOC, aluminum nitride, a metal oxide, another oxide or another proper bonding material. It can be multiple layers of one or more of such materials. The heat generated in or by the diaphragm2910during filtering may be conducted through the fingers2936to busbars2932and2934of the IDT2930; and then to the substrate2920. However, the busbars and other parts of the IDT are separated from the substrate by the piezoelectric layer and a layer of bonding oxide (BOX). Thus, an improved XBAR resonator2900that efficiently conducts heat from the fingers2936and busbars2932and2934to the substrate2920is formed by removing predetermined areas (e.g., excess amounts) WR1and WR2of the bonding layer2922and piezoelectric layer2910from selected locations of the surface of the substrate of the device2900to provide a predetermined amount in reduction of thermal resistance between the conductor pattern and the substrate. Removing may be done by an island etch concept that removes layers2922and2910around a perimeter of the resonator to leave an island of the layers2922,2910and IDT2930over cavity2940. In this case, areas WR1and WR2are a single area extending around a perimeter of and form an island of the bonding layer2922, plate2910and IDT2930. It is considered that multiple devices2900may exist as islands on substrate2920with areas WR1and WR2separating each island. Here, layer2970may extend partially between each island. In other cases, it may extend completely between all of the islands. Removing the predetermined areas WR1and WR2causes the predetermined amount of reduction in ‘contact thermal resistance’. The predetermined amount in reduction of thermal resistance between the conductor pattern and the substrate may be a reduction of 2×, 3×, 5× or 10× the thermal resistance. In some cases, it is a 3× reduction. In other cases, it is a 10× reduction. The area sizes of areas WR1and WR2can be selected or predetermined based on the predetermined amount of reduction desired. WR1and WR2may range from 1 um to 200 um, with maximum extent determined by resonator to resonator or resonator to bump offsets. WR1and WR2need not be identical to each other, but are not excluded from being identical. The selected locations are predetermined areas WR1and WR2where removal of bonding layer2922and piezoelectric layer2910take place. For example, the bonding layer2922and piezoelectric layer2910span the cavity and have excess portions that extend a certain length past the perimeter of the cavity. The excess portions may extend a certain length and width distance (WR1and WR2) past the length and width (WC) perimeter of the cavity. The excess portions may be a perimeter of the bonding layer and piezoelectric layer that extend in the length and width past the perimeter of the cavity by: a) more than 5, 10 or 20 percent; or b) between 2 and 25 percent of the length distance and width distance of the cavity. The removal regions WR1and WR2correspond to some or all of the area covered by metal routing between resonators or between a resonators and bumps. The IDT and second metal conductors may be metal or another proper conductive material. The substrate may be silicon or another proper substrate semiconductor material. The bonding layer may be BOX such as silicon dioxide or another proper bonding material. The piezoelectric layer2910may be etched away from over layer2910at areas WR1and WR2using a selective etching technique or chemistry that removes layer2910but does not remove any of the layer2922. Here, layer2922may be an etch stop layer for etching layer2910. The bonding layer2922may be etched away from over substrate2920at areas WR1and WR2using a selective etching technique or chemistry that removes layer2922but does not remove any or a functionally relevant thickness of the substrate120. Here, substrate2920may be an etch stop layer for etching layer2922. In some cases, both the bonding layer2922and piezoelectric layer2910are etched away from over substrate2920at areas WR1and WR2using a selective etching technique or chemistry that removes both layers but does not remove any or a functionally relevant thickness of the substrate120. Here, substrate2920may be an etch stop layer for etching both layers. Removing the areas of BOX and LN layers2910and2922may not impact the electrical isolation path of the IDT because there is no capacitance between M2 layers and the Si substrate layer2920if the BOX+LN is removed from the areas WR1and WR2. For example, a trap-rich layer with high electrical resistance formed over the surface of substrate2920at the areas WR1and WR2will likely be sufficient to ensure the electrical isolation path. In some cases, it will be desirable to maintain high resistance with a barrier layer formed over the surface of substrate2920at the areas WR1and WR2, such as an oxidized Ti layer. Such a layer would be of thickness between 0 nm and 20 nm to minimize parasitic thermal resistance contributions. FIG.29Bis a schematic cross-sectional view of XBAR device2902having three predetermined areas of the bonding layer2922and piezoelectric layer2910removed from selected locations over the surface of the substrate of the device to provide a predetermined amount in reduction of thermal resistance between the IDT pattern2936and the substrate2920. Device2902may represent an alternative configuration of device2900that includes width WP1and another width WP2of layers2922and2910; and width WR3of a third area of the layers2922and2910that is removed for reasons similar to removal of area WR1and WR2. Device2902also has bump2972attached to layer2971as shown. Widths WP2and WR3may have lengths that are related to the widths, such as noted inFIGS.1and5. The widths and corresponding length may define a perimeter of the layers and area. For device2902, second metal layer2973of M2 material is attached to the side surfaces of bonding layer2922at WP2; to the side surfaces and the top surface of the piezoelectric layer2910at WP2; and to a top surface layer2971. It also has second metal layer2974of M2 material attached to the top of the substrate2920at WR3; to a side surface of layer2973; and with bump2972attached to its top surface. In some cases, the second metal layers2973and2974are separate metal layers extending through trenches formed in the bonding layer2922and plate2910beside the resonator or layer2971. The BOX2922and LN2910over length WP2may remain in order to provide additional electrical isolation, in regions where trap-rich Si or high resistance metal films do not provide sufficient electrical isolation. However, WP2may also be zero, such that WR2and WR3are directly adjacent. Thus, an improved XBAR resonator2902that efficiently conducts heat from the fingers2936and busbars2932and2934to the substrate2920is formed by removing predetermined areas (e.g., excess amounts) WR1, WR2and WR3of the bonding layer2922and piezoelectric layer2910from selected locations of the surface of the substrate of the device2902to provide a predetermined amount in reduction of thermal resistance between the conductor pattern and the substrate. Removing may be done by a trench etch concept that removes layers2922and2910in trenches beside a perimeter of the resonator separately from or in addition to the island of the layers2922,2910and IDT2930described forFIG.29A. The minimum size of WR3is the diameter of the bump2972, which typically ranges from 50 um to 100 um. WR3may also extend as far as WR2, up to 200 um. The selected locations and predetermined amounts for device2902can be the same as for device2900. Etching the bonding layer2922and piezoelectric layer2910away from over substrate2920at the WR areas can be the same in device2902as for device2900. Description of Methods FIG.30is a simplified flow chart summarizing a process3000for fabricating an XBAR or a filter device incorporating XBARs. The process3000could be for fabricating a filter device including multiple XBARs, some of which may include a frequency setting dielectric or coating layer. The process3000starts at3005with a device substrate and a thin plate of piezoelectric material disposed on a sacrificial substrate. The process3000ends at3095with a completed filter device. The flow chart ofFIG.30includes only major process steps. Various conventional process steps (e.g., surface preparation, cleaning, inspection, baking, annealing, monitoring, testing, etc.) may be performed before, between, after, and during the steps shown inFIG.30. WhileFIG.30generally describes a process for fabricating a single filter device, multiple filter devices may be fabricated simultaneously on a common wafer (consisting of a piezoelectric plate bonded to a substrate). In this case, each step of the process3000may be performed concurrently on all of the filter devices on the wafer. XBARs or XBAR filter devices constructed according to this method can include any of the features described above. Thus, the method would include any steps necessary to include these features including modifications to the structure and the dimensions of the structure, orienting of the crystal structure of the piezoelectric plate, shaping of the electrodes and other structures related to the electrodes, etc. The flow chart ofFIG.30captures three variations of the process3000for making an XBAR which differ in when and how cavities are formed in the device substrate. The cavities may be formed at steps3010A,3010B, or3010C. Only one of these steps is performed in each of the three variations of the process3000. The piezoelectric plate may typically be lithium niobate, including lithium niobite with a suitable crystal orientation. The piezoelectric plate may be some other material and/or some other cut. The device substrate may preferably be silicon. The device substrate may be some other material that allows formation of deep cavities by etching or other processing. In one variation of the process3000, one or more cavities are formed in the device substrate at3010A, before the piezoelectric plate is bonded to the substrate at3015. A separate cavity may be formed for each resonator in a filter device. Also, the cavities can be shaped and formed such that two or more resonators can be on one diaphragm over one cavity. The one or more cavities may be formed using conventional photolithographic and etching techniques. Typically, the cavities formed at3010A will not penetrate through the device substrate. At3015, the piezoelectric plate is bonded to the device substrate. The piezoelectric plate and the device substrate may be bonded by a wafer bonding process. Typically, the mating surfaces of the device substrate and the piezoelectric plate are highly polished. One or more layers of intermediate materials, such as an oxide or metal, may be formed or deposited on the mating surface of one or both of the piezoelectric plate and the device substrate. One or both mating surfaces may be activated using, for example, a plasma process. The mating surfaces may then be pressed together with considerable force to establish molecular bonds between the piezoelectric plate and the device substrate or intermediate material layers. At3020, the sacrificial substrate may be removed. For example, the piezoelectric plate and the sacrificial substrate may be a wafer of piezoelectric material that has been ion implanted to create defects in the crystal structure along a plane that defines a boundary between what will become the piezoelectric plate and the sacrificial substrate. At3020, the wafer may be split along the defect plane, for example by thermal shock, detaching the sacrificial substrate and leaving the piezoelectric plate bonded to the device substrate. The exposed surface of the piezoelectric plate may be polished or processed in some manner after the sacrificial substrate is detached. A first conductor pattern, including IDTs and reflector elements of each XBAR, is formed at3045by depositing and patterning one or more conductor layers on the front side of the piezoelectric plate. All or portions of the first conductor pattern may be over the coating layer formed at3025. The conductor layer may be, for example, aluminum, an aluminum alloy, copper, a copper alloy, or some other conductive metal. Optionally, one or more layers of other materials may be disposed below (i.e., between the conductor layer and the piezoelectric plate) and/or on top of the conductor layer. For example, a thin film of titanium, chrome, or other metal may be used to improve the adhesion between the conductor layer and the piezoelectric plate. A second conductor pattern of gold, aluminum, copper or other higher conductivity metal may be formed over portions of the first conductor pattern (for example the IDT bus bars and interconnections between the IDTs). Each conductor pattern may be formed at3045by depositing the conductor layer and, optionally, one or more other metal layers in sequence over the surface of the piezoelectric plate. The excess metal may then be removed by etching through patterned photoresist. The conductor layer can be etched, for example, by plasma etching, reactive ion etching, wet chemical etching, or other etching techniques. Alternatively, each conductor pattern may be formed at3045using a lift-off process. Photoresist may be deposited over the piezoelectric plate. and patterned to define the conductor pattern. The conductor layer and, optionally, one or more other layers may be deposited in sequence over the surface of the piezoelectric plate. The photoresist may then be removed, which removes the excess material, leaving the conductor pattern. At3050, one or more frequency setting dielectric layer(s) may be formed by depositing one or more layers of dielectric material on the front side of the piezoelectric plate. For example, a dielectric layer may be formed over the shunt resonators to lower the frequencies of the shunt resonators relative to the frequencies of the series resonators. The one or more dielectric layers may be deposited using a conventional deposition technique such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or some other method. One or more lithography processes (using photomasks) may be used to limit the deposition of the dielectric layers to selected areas of the piezoelectric plate. For example, a mask may be used to limit a dielectric layer to cover only the shunt resonators. At3055, a passivation/tuning dielectric layer is deposited over the piezoelectric plate and conductor patterns. The passivation/tuning dielectric layer may cover the entire surface of the filter except for pads for electrical connections to circuitry external to the filter. In some instantiations of the process3000, the passivation/tuning dielectric layer may be formed after the cavities in the device substrate are etched at either3010B or3010C. In a second variation of the process3000, one or more cavities are formed in the back side of the device substrate at3010B. A separate cavity may be formed for each resonator in a filter device. Also, the cavities can be shaped and formed such that two or more resonators can be on one diaphragm over one cavity. These resonators sharing a diaphragm are acoustically coupled on an acoustic track. The one or more cavities may be formed using an anisotropic or orientation-dependent dry or wet etch to open holes through the back side of the device substrate to the piezoelectric plate. In this case, the resulting resonator devices will have a cross-section as shown inFIG.1. In a third variation of the process3000, one or more cavities in the form of recesses in the device substrate may be formed at3010C by etching the substrate using an etchant introduced through openings in the piezoelectric plate. A separate cavity may be formed for each resonator in a filter device. Also, the cavities can be shaped and formed such that two or more resonators can be on one diaphragm over one cavity. The one or more cavities formed at3010C will not penetrate through the device substrate. For all cavity forming steps3010A,3010B, and3010C, the dimensions of the cavity will be formed with respect to the dimensions of the IDTs of the conductor pattern, as described above with respect toFIGS.1,2A and2B. Ideally, after the cavities are formed at3010B or3010C, most or all of the filter devices on a wafer will meet a set of performance requirements. However, normal process tolerances will result in variations in parameters such as the thicknesses of dielectric layer formed at3050and3055, variations in the thickness and line widths of conductors and IDT fingers formed at3045, and variations in the thickness of the piezoelectric plate. These variations contribute to deviations of the filter device performance from the set of performance requirements. To improve the yield of filter devices meeting the performance requirements, frequency tuning may be performed by selectively adjusting the thickness of the passivation/tuning layer deposited over the resonators at3055. The frequency of a filter device passband can be lowered by adding material to the passivation/tuning layer, and the frequency of the filter device passband can be increased by removing material to the passivation/tuning layer. Typically, the process3000is biased to produce filter devices with passbands that are initially lower than a required frequency range but can be tuned to the desired frequency range by removing material from the surface of the passivation/tuning layer. At3060, a probe card or other means may be used to make electrical connections with the filter to allow radio frequency (RF) tests and measurements of filter characteristics such as input-output transfer function. Typically, RF measurements are made on all, or a large portion, of the filter devices fabricated simultaneously on a common piezoelectric plate and substrate. At3065, global frequency tuning may be performed by removing material from the surface of the passivation/tuning layer using a selective material removal tool such as, for example, a scanning ion mill as previously described. “Global” tuning is performed with a spatial resolution equal to or larger than an individual filter device. The objective of global tuning is to move the passband of each filter device towards a desired frequency range. The test results from 3060 may be processed to generate a global contour map indicating the amount of material to be removed as a function of two-dimensional position on the wafer. The material is then removed in accordance with the contour map using the selective material removal tool. At3070, local frequency tuning may be performed in addition to, or instead of, the global frequency tuning performed at3065. “Local” frequency tuning is performed with a spatial resolution smaller than an individual filter device. The test results from 3060 may be processed to generate a map indicating the amount of material to be removed at each filter device. Local frequency tuning may require the use of a mask to restrict the size of the areas from which material is removed. For example, a first mask may be used to restrict tuning to only shunt resonators, and a second mask may be subsequently used to restrict tuning to only series resonators (or vice versa). This would allow independent tuning of the lower band edge (by tuning shunt resonators) and upper band edge (by tuning series resonators) of the filter devices. After frequency tuning at3065and/or3070, the filter device is completed at3075. Actions that may occur at3075include forming bonding pads or solder bumps or other means for making connection between the device and external circuitry (if such pads were not formed at3045); excising individual filter devices from a wafer containing multiple filter devices; other packaging steps; and additional testing. After each filter device is completed, the process ends at3095. Closing Comments Throughout this description, the embodiments and examples shown should be considered as exemplars, rather than limitations on the apparatus and procedures disclosed or claimed. Although many of the examples presented herein involve specific combinations of method acts or system elements, it should be understood that those acts and those elements may be combined in other ways to accomplish the same objectives. With regard to flowcharts, additional and fewer steps may be taken, and the steps as shown may be combined or further refined to achieve the methods described herein. Acts, elements and features discussed only in connection with one embodiment are not intended to be excluded from a similar role in other embodiments. As used herein, “plurality” means two or more. As used herein, a “set” of items may include one or more of such items. As used herein, whether in the written description or the claims, the terms “comprising”, “including”, “carrying”, “having”, “containing”, “involving”, and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of”, respectively, are closed or semi-closed transitional phrases with respect to claims. Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements. As used herein, “and/or” means that the listed items are alternatives, but the alternatives also include any combination of the listed items. | 106,281 |
11942923 | FIG.1shows basic circuit elements of a bandpass filter BPF. The bandpass filter BPF comprises a first port P1and a second port P2. It is possible but not necessary that the first port P1is an input port while the second port P2is an output port o the bandpass filter BPF. The direction of propagation of RF signals can go from the first port P1to the second port P2or from the second port P2to the first port P1. The signal path SP is arranged between the first port P1and the second port P2. The signal path comprises a first segment S1. The first segment S1is arranged between a first node N1and a second node N2. Further, a parallel branch PB is electrically connected in parallel to the first segment S1between the first node N1and the second node N2. In the first segment S1a first electro acoustic resonator EAR1is electrically connected between the first port P1and the second port P2. In the parallel branch PB a series connection of an impedance element IE and a phase shifter PS is electrically connected. It is possible that the impedance element IE is electrically connected between the first node N1and the phase shifter PS while the phase shifter PS is electrically connected between the impedance element IE and the second port P2or the second node N2. FIG.2illustrates a basic embodiment of the phase shifter PS. The phase shifter PS has a first terminal T1and a second terminal T2and a connection to ground. The first terminal T1can be an input terminal and the second terminal T2can be an output terminal or vice versa. The phase shifter PS comprises a first inductance element INE1and a second inductance element INE2. The first and the inductance elements establish inductively coupled inductance elements as indicated by the arrow. The first inductance element INE1electrically connects the first terminal T1to ground. The second inductance element INE2electrically connects the second terminal T2to ground. The coupling between the inductance elements can be a direct coupling (k=1) or an opposite coupling (k)−1). With the first terminal T1the phase shifter PS can be electrically connected to or coupled to the impedance element shown inFIG.1. With the second terminal T2the phase shifter PS shown inFIG.2can be electrically connected to the second node N2shown inFIG.1. The configuration comprising the topology shown inFIG.1with the embodiment of the phase shifter PS shown inFIG.2provides a substantially increased bandwidth while maintaining excellent other filter properties. FIG.3illustrates the possibility of using a second electro acoustic resonator EAR2in the bandpass filter BPF as the impedance element IE. FIG.4illustrates an alternative approach where the impedance element IE is realized by a capacitance element CE. The difference between the topologies shown inFIGS.3and4is that the impedance element IE shown inFIG.3is acoustically active while the impedance element IE shown inFIG.4is acoustically inactive. However, the basic construction of the two impedance elements can be essentially similar except for the acoustic activity. FIG.5shows a further possibility of providing the phase shifter PS. In addition to the inductively coupled inductance elements INE1, INE2a first capacitance element CE1is electrically connected between the first terminal and ground. A second capacitance element CE2is electrically connected between the second terminal T2and ground. FIG.6shows a possibility of a phase shifter PS where in addition to the first and second coupled inductance elements INE1, INE2a first capacitance element CE1is connected between the first terminal T1and the second terminal T2. The two capacitance elements electrically connected in parallel to the inductance elements can be optionally present in the phase shifter shown inFIG.6. FIG.7shows the possibility of shunting the corresponding terminals of the coupled inductance elements INE1, INE2via a specifically dedicated node N and via a third capacitance element CE3to ground. The capacitance element shown inFIG.6and the two capacitance elements shown inFIG.5can be optionally present in the phase shifter PS ofFIG.7. FIG.8shows a possible combination of the circuit elements of the phase shifter in combination with the other circuit elements of the bandpass filter BPF. In addition, impedance matching circuits can also be present. The topology of the bandpass filter BPF shown inFIG.8comprises an additional, second electro acoustic resonator EAR2between the second node and the second port P2. A first impedance matching circuit IMC1is electrically arranged between the first port P1and the first node. A second impedance matching circuit IMC2is electrically configured between the second electro acoustic resonator EAR2and the second port P2. In the parallel branch the impedance element IE is realized as a first capacitance element CE1. An additional, second capacitance element CE2is arranged between the first capacitance element CE1and the second node. A further, third capacitance element CE3is electrically connected between the second capacitance element CE2and the second node. Thus, the three capacitance elements CE1, CE2and CE3establish a series connection in the parallel branch PB. One terminal of the first coupled inductance elements INE1is connected to a node between the first capacitance element CE1and the second capacitance element CE2. The respective other terminal of the inductance element INE1is connected to ground. Correspondingly, a first terminal of the second coupled inductance element INE2is electrically connected to a node between the second capacitance element CE2and the third capacitance element CE3. The respective other terminal of the inductance element is connected to ground. The two electro acoustic resonators EAR1, EAR2together with the three capacitance elements CE1, CE2, CE3are realized in the acoustic package AP. The respective other circuit elements, e.g. of the first and of the second impedance matching circuit IMC1, IMC2and the inductance elements are established outside the acoustic package, e.g. within a multilayer construction of the carrier substrate. The first and the second impedance matching circuits IMC1, IMC2can comprise LC elements electrically configured in Pi and Tee configurations to match an external circuit environment of the bandpass filter BPF at the corresponding ports P1, P2. The matching impedance can be 50 ohm, 100 ohm or 200 ohm. FIG.9illustrates a configuration where the parallel branch PB is electrically connected to ground at the place of the second node via a fourth capacitance element CE4. A second electro acoustic resonator EAR2is electrically connected between the second node N2and the second port P2. Further, a first impedance matching circuit IMC1and a second impedance matching circuit IMC2are electrically connected between the first port P1and the first node and between the second electro acoustic resonator EAR2and the second port P2, respectively. While the inductively coupled inductance elements electrically shunt the parallel branch PB to ground in the topology shown inFIG.8, the inductance elements INE1, INE2are electrically connected in series in the parallel branch PB and the node between the two inductance elements INE1, INE2is electrically connected to ground. The two electro acoustic resonators EAR1, EAR2and the impedance element IE are realized as a first capacitance element CE1and the fourth capacitance element CE4are realized in the acoustic package AP while the respective other circuit elements are realized outside the acoustic package AP, e.g. in a multilayer construction of the carrier substrate. FIG.10illustrates a cross-section through a possible multilayer filter component MLFC. The multilayer filter component comprises a multilayer carrier substrate with a plurality of layers L. The layers L comprise or consist of a dielectric material. Conductive structures realized as metallized patterns between the layers L realize passive circuit elements such as impedance elements like inductance elements IN and capacitance elements CE. The acoustic package AP is arranged at the top side of the multilayer carrier substrate and electrically connected to the impedance elements in the substrate. A connection can take place via a bump connection or via wire bonding connections. The sensitive MEMS structures (MEMS=micro electro mechanical system) are protected in a hermetically sealed environment HS. FIG.11shows a comparison of three different phase shifter topologies. Curve1shows a three-stages high pass phase shifter. Curve3shows a three-stages low pass phase shifter. In contrast, curve2shows a phase shifter comprising two coupled parallel coils as suggested above. The phase error (slope of the phase curve) for frequencies around 4.2 GHz is much smaller in curve2, i.e., a phase shift around 180° degrees is achieved for a much wider frequency range. In this context it is to be noted that a phase difference of 180° is equal to a phase difference of −180°. The vertical boundaries of −180° and 180° are choosen arbitrarily. Thus, a relatively stable phase in a wide frequency range, e.g. from 3 GHz to 6 GHz is obtained. FIG.12shows the corresponding insertion loss of the phase shifters described in the context ofFIG.11. Curve2denotes the insertion loss of the phase shifter with the two coupled inductance elements. A wide frequency range with a low insertion loss and a phase shift around 180° are simultaneously obtained. FIG.13shows the passband performance of the bandpass filter shown inFIG.8without a coupling of the inductance elements (curve1) and the corresponding passband performance of the bandpass filter according toFIG.9with coupled inductance elements (curve3). The bandwidth specification is fulfilled in both filters, the important point as mentioned in the following paragraph, is that both passband bandwidth specification and isolation level above the passband can be simultaneously achieved. FIG.14illustrates the corresponding performances shown inFIG.13in a wider frequency range FIG.15shows the right skirt performance of a topology indicated byFIG.8without the coupling of the inductance coils (curve1) and the right skirt performance of the filter shown inFIG.9including the coupling between the inductance elements (curve3) showing that the isolation levels above the passband are significantly improved fulfilling now the specified parameters. The above-described bandpass filters provide a substantially better close-in suppression above the passband while other important filter parameters are essentially maintained. The filter or the filter component are not limited to the specific details shown in the figures or described above. Filters or filter components can comprise further circuit elements, e.g. for impedance matching, and further structural elements, e.g. for embedding impedance elements in a multilayer substrate or protecting sensitive MEMS structures like resonators from detrimental influences. LIST OF REFERENCE SIGNS AP: acoustic packageBPF: bandpass filterCE: capacitance elementCE1, CE2, CE3CE4: capacitance elementEAR1, EAR2: first, second electro acoustic resonatorHS: hermetical sealIE: impedance elementIMC1, IMC2: first, second impedance matching circuitIN: inductance elementINE1, INE2: first, second inductively coupled inductance elementL: layerMLFC: multilayer filter componentN: nodeN1, N2: first, second node in the signal pathP1, P2: first, second port of the filterPB: parallel branchPS: phase shifterS1: first segment of signal pathSP: signal pathT1, T2: first, second terminal of the phase shifterW: wire connection through one or more layers | 11,707 |
11942924 | DETAILED DESCRIPTION The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Cellular communication systems use various governmental-licensed frequency bands or carriers to transmit downlink (DL) data to wireless communication devices, such as smart phones, desktop computers, laptop computers, Internet of Things (IoT), and other devices. Depending on the governmental agency that assigns frequency bands or carriers for transmission of data to wireless communication devices, some of these bands, that are exemplified herein, are referred to as B25, B66, B34, and B39. However, it shall be understood that the filtering concepts described herein are applicable to other frequency bands. Frequency band B25 extends from 1930 to 1995 megahertz (MHz). Frequency band B66 extends from 2110 to 2200 MHz. Frequency band B34 extends from 2010 to 2025 MHz. And, frequency band B39 extends from 1880 to 1920 MHz. A wireless communication device, capable of receiving DL signals transmitted via these frequency bands, includes a receiver with appropriate bandpass filters (BPFs) for substantially passing through these DL signals in these frequency bands, while substantially rejecting signals outside of the frequency bands, respectively. This is better explained with reference to an example receiver front-end described further herein. FIG.1Aillustrates a schematic/block diagram of an example receiver front-end100in accordance with an aspect of the disclosure. The receiver front-end100includes at least one antenna110, an antenna switching network120, a set of shunt inductors LI1, LI2, and LI3, a set of band select filters130,132,134, and136, a set of series inductors LO1, LO2, LO3, and LO4, a low noise amplifier (LNA) switching network140, and a controller150. The antenna switching network120includes a set of switching devices SWI1, SWI2, and SWI3including respective first terminals coupled to the at least one antenna110. The open/closed states of the set of switching devices SWI1, SWI2, and SWI3are responsive to a band select signal BAND_SEL generated by the controller150. The BAND_SEL signal may be a single signal, a combination of multiple signals, a mobile industry processor interface (MIPI) protocol signal, etc. The set of switching devices SWI1, SWI2, and SWI3include respective second terminals coupled to inputs of filters130/132,134, and136, respectively. The set of shunt inductors LI1, LI2, and LI3are coupled between the inputs of the filters130/132,134, and136and ground, respectively. The set of shunt inductors LI1, LI2, and LI3, one or more of which may be optional, function to improve the impedance match between the input of the filters130/132,134, and136and the at least one antenna110, respectively; as well as provide input phase shifting to reduce loading of one filter by another filter when the filters are used simultaneously (i.e., the inputs of the filters are coupled together). The set of filters130,132,134, and136are configured to substantially pass through the DL signals within corresponding frequency bands, and substantially reject signals that are outside of the corresponding frequency bands. The filter130is for the B25 frequency band; the filter132is for B66 frequency band; the filter134is for B34 frequency band; and the filter136is for the B39 frequency band. Each of the filters130,132,134, and136may be configured as a micro-acoustic filter (e.g., surface acoustic wave (SAW) filter or bulk acoustic wave (BAW) filter). The LNA switching network140includes a first set of switching devices SWO1, SWO2, SWO3, and SWO4, a set of LNAs142,144,146, and148, and a second set of switching devices SWO5, SWO6, SWO7, and SWO8. The set of series inductors LO1, LO2, LO3, and LO4, one or more of which may be optional, are coupled between the outputs of the set of filters130,132,134, and136and respective first terminals of the first set of switching devices SWO1, SWO2, SWO3, and SWO4. The set of series inductors LO1, LO2, LO3, and LO4function to improve the impedance match between the outputs of the set of filters130,132,134, and136and the inputs of the set of LNAs142,144,146, and148, respectively. The set of LNAs142,144,146, and148are coupled between respective second terminals of the first set of switching device SWO1, SWO2, SWO3, and SWO4and respective first terminals of the second set of switching devices SWO5, SWO6, SWO7, and SWO8. The second set of switching devices SWO5, SWO6, SWO7, and SWO8include respective second terminals coupled together, and to additional processing circuitry further downstream (e.g., mixer with local oscillator (LO), baseband filter, etc.). Similarly, the open/closed states of the first and second sets of switching devices SWO1-SWO4and SWO5-SWO8are responsive to the band select signal BAND_SEL generated by the controller150. In operation, if the DL signals-of-interest are within frequency bands B25 and B66, which may be multiplexed together, the band select signal BAND_SEL controls the switching devices SWI1, SWO1, SWO2, SWO5, and SWO6to close, and the switching devices SWI2, SWI3, SWO3, SWO4, SWO7, and SWO8to open. In this configuration, the at least one antenna110is coupled to the inputs of the filters130and132including the shunt inductor LI1, the outputs of the filters130and132are coupled to the inputs of the LNAs142and144via the series inductors LO1and LO2, and the outputs of the LNAs142and144are coupled to the additional processing circuitry, respectively. The filter130substantially passes through the DL signal within the B25 frequency band, and substantially rejects signals outside of the B25 frequency band in accordance with a first filter frequency response. Similarly, the filter132substantially passes through the DL signal within the B66 frequency band, and substantially rejects signals outside of the B66 frequency band in accordance with a second filter frequency response. Thus, the receiver front-end100may process the DL signals within the frequency bands B25 and B66 (e.g., filter and low noise amplify) and provide them to the additional processing circuitry to obtain data embedded in these signals. In this configuration, the remaining filters134and136and LNAs146and148are not used because the corresponding switching devices SWI2, SWI3, SWO3, SWO4, SWO7, and SWO8are open. Similarly, if the DL signal-of-interest is within frequency band B34, the band select signal BAND_SEL controls the switching devices SWI2, SWO3, and SWO7to close, and the switching devices SWI1, SWI3, SWO1, SWO2, SWO4, SWO5, SWO6, and SWO8to open. In this configuration, the at least one antenna110is coupled to the input of the filter134including the shunt inductor LI2, the output of the filter134is coupled to the input of the LNA146via the series inductor LO3, and the output of the LNA146is coupled to the additional processing circuitry. The filter134substantially passes through the DL signal within the B34 frequency band, and substantially rejects signals outside of the B34 frequency band in accordance with a particular filter frequency response. Thus, the receiver front-end100may process the DL signal within the frequency band B34 (e.g., filter and low noise amplify) and provide them to the additional processing circuitry to obtain the data embedded in the signal. In this configuration, the remaining filters130,132and136and LNAs142,144, and148are not used because the corresponding switching devices SWI1, SWI3, SWO1, SWO2, SWO4, SWO5, SWO6, and SWO8are open. Similarly, if the DL signals-of-interest are within frequency bands B34 and B39 in a carrier aggregation (CA) mode of operation, the band select signal BAND_SEL controls the switching devices SWI2, SWI3, SWO3, SWO4, SWO7, and SWO8to close, and the switching devices SWI1, SWO1, SWO2, SWO5, and SWO6to open. In this configuration, the at least one antenna110is coupled to the input of the filters134and136including the shunt inductors LI2and LI3, the outputs of the filter134and136are coupled to the inputs of the LNAs146and148via the series inductors LO3and LO4, and the outputs of the LNAs146and148are coupled to the additional processing circuitry. The filter134substantially passes through the DL signal within the B34 frequency band, and substantially rejects signals outside of the B34 frequency band in accordance with a first filter frequency response. Also, the filter136substantially passes through the DL signal within the B39 frequency band, and substantially rejects signals outside of the B39 frequency band in accordance with a second filter frequency response. Thus, the receiver front-end100may process the DL signals within the frequency bands B34 and B39 (e.g., filter and low noise amplify) in CA mode, and provide them to the additional processing circuitry to obtain the data embedded in the signals. In this configuration, the remaining filters130and132and LNAs142and144are not used because the corresponding switching devices SWI1, SWO1, SWO2, SWO5and SWO6are open. To reduce costs, circuit area, and improve performance (e.g., less signal loss and improved noise figure), it would be desirable to reduce the number of components in the receiver front-end100. With reference toFIG.1B, which illustrates frequency spectrum of the frequency bands B39, B25, B34, and B66, it is noted that the frequency band B25 is close to the frequency band B34 (e.g., 15 MHz away). Accordingly, as discussed further herein, the B25 filter130may have enough bandwidth to also cover the B34 frequency band. However, the B34 frequency band has a rejection requirement (identified as R34) that is at least −20 decibels (dB) at 1925 MHz, which is 5 MHz below the passband of the frequency band B25. As discussed herein, the filter B25 may be reconfigured to have multiple- or dual-outputs to produce the filter outputs for the frequency bands B25 and B34, respectively. In addition, the reconfigured filter B25 may have a notch near the lower frequency end of the B25 frequency band that can be tuned to provide the required rejection R34 for frequency band R34, without substantially affecting the rejection requirement (identified as R25) for the frequency band R25. The R25 rejection requirement is at least −45 dB rejection at 1915 MHz. FIG.2Aillustrates a schematic/block diagram of another example receiver front-end200in accordance with another aspect of the disclosure. The receiver front-end200includes at least one antenna210, an antenna switching network220, a set of shunt inductors LI1and LI2, a set of band select filters230,232, and234, a set of series inductors LO1, LO2, LO3, and LO4, a low noise amplifier (LNA) switching network240, and a controller250. As discussed further herein, the band select filter230is configured with a single input, and multiple- or dual-outputs to produce different frequency responses suitable for different frequency bands, such as the B25 and B34 frequency bands, respectively. The antenna switching network220includes a set of switching devices SWI1and SWI2including respective first terminals coupled to the at least one antenna210. The open/closed states of the set of switching devices SWI1and SWI2are responsive to a band select signal BAND_SEL generated by the controller250. Similarly, the BAND_SEL signal may be a single signal, a combination of multiple signals, a mobile industry processor interface (MIPI) protocol signal, etc. The set of switching devices SWI1and SWI2include respective second terminals coupled to inputs of filters230/232and234, respectively. The set of shunt inductors LI1and LI2are coupled between the inputs of the filters230/232and234and ground, respectively. The set of shunt inductors LI1and LI2, one or more of which may be optional, function to improve the impedance match between the input of the filters230/232and234and the at least one antenna210, respectively; as well as provide phase shifting to reduce loading of one filter by another filter when the filters are used simultaneously (i.e., when the inputs of the filters are coupled together). The set of filters230,232, and234are configured to substantially pass through the DL signals within corresponding frequency bands, and substantially reject signals that are outside of the corresponding frequency bands. As previously discussed, the filter230includes dual-outputs to provide two different filter frequency responses suitable for frequency bands B25 and B34; the filter232provides a filter frequency response suitable for frequency band B66; and the filter234provides a filter frequency response suitable for frequency band B39. Each of the filters230,232, and234may be configured as a micro-acoustic filter (e.g., surface acoustic wave (SAW) filter or bulk acoustic wave (BAW) filter). The LNA switching network240includes a first set of switching devices SWO1, SWO2, SWO3, and SWO4, a set of LNAs242,244,246, and248, and a second set of switching devices SWO5, SWO6, SWO7, and SWO8. The set of series inductors LO1, LO2, LO3, and LO4are coupled between the dual-outputs of filter230and the outputs of filters232and234, and first terminals of the first set of switching devices SWO1, SWO2, SWO3, and SWO4, respectively. The set of series inductors LO1, LO2, LO3, and LO4, one or more of which may be optional, function improve the impedance match between the dual outputs of filter230and outputs of filters232and234and the inputs of the set of LNAs242,244,246, and248, respectively. The set of LNAs242,244,246, and248are coupled between second terminals of the first set of switching devices SWO1, SWO2, SWO3, and SWO4and first terminals of the second set of switching devices SWO5, SWO6, SWO7, and SWO8, respectively. The second set of switching devices SWO5, SWO6, SWO7, and SWO8include respective second terminals coupled together, and to additional processing circuitry further downstream (e.g., mixer with local oscillator (LO), baseband filter, etc.). Similarly, the open/closed states the first and second sets of switching devices SWO1-SWO4and SWO5-SWO8are responsive to the band select signal BAND_SEL generated by the controller250. In operation, if the DL signals-of-interest are within frequency bands B25 and B66, which may be multiplexed together, the band select signal BAND_SEL controls the switching devices SWI1, SWO1, SWO3, SWO5, and SWO7to close, and the switching devices SWI2, SWO2, SWO4, SWO6, and SWO8to open. In this configuration, the at least one antenna210is coupled to the inputs of the filters230and232including the shunt inductor LI1, the B25 output of filter230and the output of filter232are coupled to the inputs of the LNAs242and246via the series inductors LO1and LO3, and the outputs of the LNAs242and246are coupled to the additional processing circuitry, respectively. The filter230substantially passes through the DL signal within the B25 frequency band to the B25 output, and substantially rejects signals outside of the B25 frequency band in accordance with a first filter frequency response. Similarly, the filter232substantially passes through the DL signal within the B66 frequency band, and substantially rejects signals outside of the B66 frequency band in accordance with a second filter frequency response. Thus, the receiver front-end200may process the DL signals within the frequency bands B25 and B66 (e.g., filter and low noise amplify) and provide them to the additional processing circuitry to obtain data embedded in these signals. In this configuration, the B34 filter frequency response of filter230is not used as switching device SWO2coupled to the B34 output of the filter230is open, and consequently, LNA244is not in operation (e.g., it has no input signal, and not coupled to the additional processing circuitry as switching device SWO6is open). Also, the remaining filter234and LNA248are not used because the corresponding switching devices SWI2, SWO4, and SWO8are open. Similarly, if the DL signal-of-interest is within frequency band B34, the band select signal BAND_SEL controls the switching devices SWI1, SWO2, and SWO6to close, and the switching devices SWI2, SWO1, SWO3, SWO4, SWO5, SWO7, and SWO8to open. In this configuration, the at least one antenna210is coupled to the input of the filter230including the shunt inductor LI1, the B34 output of the filter230is coupled to the input of the LNA244via the series inductor LO2, and the output of the LNA244is coupled to the additional processing circuitry. The filter230substantially passes through the DL signal within the B34 frequency band to the B34 output, and substantially rejects signals outside of the B34 frequency band in accordance with a particular filter frequency response. Thus, the receiver front-end200may process the DL signal within the frequency band B34 (e.g., filter and low noise amplify) and provide them to the additional processing circuitry to obtain the data embedded in the signal. In this configuration, the B25 filter frequency response of filter230is not used as switching devices SWO1coupled to the B25 output of the filter230is open; and consequently, LNA242is not in operational (e.g., it has no input signal, and not coupled to the additional processing circuitry as switching device SWO5is open). Also, the remaining filters232and236and LNAs246and248are not used because the corresponding switching devices SWI2, SWO3, SWO4, SWO7, and SWO8are open. Similarly, if the DL signals-of-interest are within frequency bands B34 and B39 in a carrier aggregation (CA) mode of operation, the band select signal BAND_SEL controls the switching devices SWI1, SWI2, SWO2, SWO4, SWO6, and SWO8, to close, and the switching devices SWO1, SWO3, SWO5, and SWO7to open. In this configuration, the at least one antenna210is coupled to the inputs of the filters230,232, and234including the shunt inductors LI1and LI2, the B34 output of filter230and the output of filter234are coupled to the inputs of the LNAs244and248via the series inductors LO2and LO4, and the outputs of the LNAs244and248coupled to the additional processing circuitry. The filter230substantially passes through the DL signal within the B34 frequency band to the B34 output, and substantially rejects signals outside of the B34 frequency band in accordance with a second filter frequency response. Also, the filter234substantially passes through the DL signal within the B39 frequency band, and substantially rejects signals outside of the B39 frequency band in accordance with another filter frequency response. Thus, the receiver front-end200may process the DL signals within the frequency bands B34 and B39 (e.g., filter and low noise amplify) in CA mode, and provide them to the additional processing circuitry to obtain the data embedded in the signals. In this configuration, the B25 filter frequency response of filter230is not used as switching device SWO1is open; and therefore, the LNA242is not in operational (e.g., it has no input signal, and not coupled to the additional processing circuitry as switching device SWO5is open). Also, the remaining filter232and LNA246are not used because the corresponding switching devices SWO3and SWO7are open. Comparing the receiver front-end200with receiver front-end100, the receiver front-end200includes one less switching device within the antenna switching network220, one less shunt inductor, and one less filter. This translates to significant cost savings, significant IC footprint savings, and improved receiver performance as there are less components adversely affecting each other. FIG.2Billustrates a graph of an example B34 filter frequency response of the filter230in accordance with another aspect of the disclosure. The x- or horizontal axis represents frequency f in MHz. The y- or vertical axis represents insertion loss associated with the frequency response of filter134(represented as a dotted line) and the B34 frequency response of the dual-output filter230(represented as a solid line). Also superimposed on the graph is a shaded rectangle representing the B34 frequency band, which extends from 2010 to 2025 MHz. As illustrated, the frequency response of the filter134has a passband (e.g., insertion loss of 3 dB or less) that extends from about 1992 to 2094 MHz, which may be suitable for the B34 frequency band, which extends from 2010 to 2025 MHz. As discussed, the B34 frequency band has a rejection requirement R34 of at least −20 dB at 1925 MHz. Thus, as illustrated, the frequency response of the filter134has a rejection of greater than −20 dB at 1925 MHz. Similarly, the B34 frequency response of the filter230has a passband (e.g., insertion loss of 3 dB or less) that extends from about 1956 to 2032 MHz, which may be suitable for B34 frequency band. The B34 frequency response of the filter230also meets the R34 rejection requirement of frequency band B34, which includes a notch that has been tuned to provide a rejection greater than −20 dB at 1925 MHz. FIG.2Cillustrates a graph of an example B25 filter frequency response of the filter230in accordance with another aspect of the disclosure. Similarly, the x- or horizontal axis represents frequency ƒ in MHz, and the y- or vertical axis represents insertion loss associated with the frequency response of filter130(represented as a dotted line) and the B25 frequency response of the dual-output filter230(represented as a solid line). Also superimposed in the graph is a shaded rectangle representing the B25 frequency band, which extends from 1930 to 1995 MHz. As illustrated, the frequency response of the filter130has a passband (e.g., insertion loss of 3 dB or less) that extends from about 1925 to 2000 MHz, which is suitable for the B25 frequency band, which extends from 1930 to 1995 MHz. As discussed, the B25 frequency band as a rejection requirement R25 of −45 dB at 1915 MHz. Thus, as illustrated, the frequency response of the filter130has a rejection of greater than −45 dB at 1915 MHz. As illustrated, the B25 frequency response of the filter230is substantially the same as the frequency response of the filter130. This is because, as discussed further herein, reconfiguring the filter130into the dual-output filter230does not significantly affect the frequency response of the filter130. Thus, the B25 frequency response of the filter230also has a passband (e.g., insertion loss of 3 dB or less) that extends from about 1925 to 2000 MHz and rejection of greater than −45 dB at 1915 MHz, which are suitable for the B25 frequency band. FIG.3illustrates a schematic diagram of an example filter300with multiple outputs to produce multiple filter frequency responses in accordance with another aspect of the disclosure. The filter300may be an example detailed implementation of the filter230previously discussed. The filter300includes a filter input (IN), a set of two or more cascaded resonator stages310-1to310-N, a first filter output (OUT1), and a second filter output (OUT2). Another way to characterize the filter300is that it includes a first set of one or more cascaded resonator stages (e.g.,310-1to310-N−1) between the filter input (IN) and the second filter output (OUT2), and a second set of one or more cascaded resonator stages (e.g.,310-N) between the second filter output (OUT2) and the first filter output (OUT1). Although, in this example, each of the set of two or more cascaded resonators are described as being a surface acoustic wave (SAW) resonator, it shall be understood that each resonator may be a bulk acoustic wave (BAW) resonator or other type of micro-acoustic resonator. With reference to filter230shown inFIG.2A, the filter input IN is coupled to the shunt inductor LI1and the second terminal of switching device SWI1. The first filter output OUT1, serves as the B25 output, and is coupled to the series inductor LO1. The second filter output OUT2, serves as the B34 output, and is coupled to the series inductor LO2. The set of two or more cascaded resonator stages is coupled between the filter input IN and the first filter output OUT1. In this example, each of the cascaded resonator stages includes a parallel resonator (e.g., a micro-acoustic resonator) and a series resonator (e.g., a micro-acoustic resonator), with the exception that the last or Nth resonator stage310-N may include two parallel resonators. For example, the first resonator stage310-1includes a first parallel resonator P1coupled between a first node n1and ground, and a first series resonator S1coupled between the first node n1and a second node n2. The first node n1may be the positive terminal of the filter input IN. However, it shall be understood that the filter300may include other filter elements preceding the first resonator stage310-1, such as a double mode SAW (DMS) filter element. The second resonator stage310-2includes a second parallel resonator P2coupled between the second node n2and ground, and a second series resonator S2coupled between the second node n2and a second node n3. The third resonator stage310-3includes a third parallel resonator P3coupled between the third node n3and ground, and a third series resonator S3coupled between the third node n3and a fourth node n4. Depending on the number of stages N (which as discussed could be two or more), the cascaded resonator stages continues in a similar manner, including, as illustrated the last resonator stage310-N, which includes an Nth parallel resonator PN coupled between an nN node and ground, an Nth series resonator SN coupled between the nN node and an nN+1 node, and an N+1 parallel resonator coupled between the nN+1 node and ground. The node nN+1 may be the positive terminal of the first filter input output OUT1. However, it shall be understood that the filter300may include other filter elements following the resonator stage310-N, such as a DMS filter element. The filter300may also include such DMS filter element between any two of the cascaded resonator stages310-1and310-N. As discussed, the filter300includes the second filter output OUT2taken across one of an output of the first one or an intermediate one of the cascaded resonator stages (e.g.,310-1to310-N−1) and ground. In this example, the second filter output OUT2is taken across the output of the cascaded resonator stage310-N−1 (immediately preceding the last cascaded resonator stage310-N) and ground. However, it shall be understood that the second filter output OUT2may be taken across any other cascaded resonator stage output (e.g., anyone of node n2to node nN−1) and ground. As depicted, the second filter output OUT2bypasses the last cascaded resonator stage310-N. As discussed, the node nN may be the positive terminal of the second filter input output OUT2. However, it shall be understood that the filter300may include other filter elements between the output of the resonator stage310-N−1 and the second filter output OUT2, such as a DMS filter element. The filter300has a first filter frequency response for a first signal applied to the filter input IN that propagates to the first filter output OUT1via the set of cascaded resonator stages310-1to310-N. The filter300has a second filter frequency response for a second signal applied to the filter input IN and propagates to the second filter output OUT2via the subset of cascaded resonator stages310-1to310-N−1, although both filter frequency responses are affected by one or more common cascaded resonator stages (e.g., by stages310-1to310-N−1). With reference to filter230shown inFIG.2A, the filter300may be configured to apply the first filter frequency response to the first signal that meets the passband and rejection requirements of the B25 frequency band, and apply the second filter frequency response to the second signal that meets the passband and rejection requirements of the B34 frequency band. As discussed, in this example, each of the cascaded resonator stages includes at least one parallel resonator and a series resonator. It shall be understood that each of the cascaded resonator stages may include a series resonator, but not a parallel resonator (e.g., in the case of a one-port SAW resonator). Also, it shall be understood that each of the cascaded resonator stages need not be configured the same, but one or more may be configured differently, such as the case where the last stage310-N includes two parallel resonators and the other stages include one parallel resonator. Each of the resonators of the filter300may be a SAW type resonator, a BAW type, or other type of resonator, such as a inductor-capacitor resonator, coaxial resonator, dielectric resonator, crystal resonator, ceramic resonator, Yttrium iron garnet (YIG) resonator, or other. FIG.4illustrates a top view diagram of an example filter400with multiple outputs to produce multiple filter frequency responses in accordance with another aspect of the disclosure. The filter400may be an example SAW implementation of the filter300previously discussed. The filter400includes a filter input (IN), a set of two or more cascaded resonator stages420-1to420-N, a first filter output (OUT1), and a second filter output (OUT2). The set of cascaded resonators420-1to420-N are coupled between the filter input In and the first filter output OUT1. The set of two or more cascaded resonator stages420-1to420-N are formed on a piezoelectric substrate410, such as a single crystal quartz, lithium niobite, lithium tantalite, and others. In this example, each of the cascaded resonator stages420-1to420-N is configured as a two-port SAW resonator. That is, each resonator stage includes an input inter digital transducer (IDT)422(which is a comb-like electrode or metallization structure disposed on the substrate410), and output IDT424, an input grating426(e.g., reflector), and an output grating428(e.g., reflector). The input IDT422includes a grounded terminal and an input terminal, which may serve as the input IN of the filter400if it is part of the first resonator stage420-1, or a signal from a previous stage if it is part of another resonator stage (e.g., anyone of resonator stages420-2to420-N). The output IDT424includes a grounded terminal and an output terminal, which may serve as the first output OUT1of the filter400if it is part of the last resonator stage420-N, or an output of another resonator stage (e.g., anyone of resonator stages420-1to420-N−1). The input and output IDTs422and424are juxtaposed next to each other along the interior center of the resonator. The input grating426is on the exterior side of the input IDT422, and the output grating428is on the exterior side of the output IDT424. To form the cascaded arrangement, the output IDT424of a preceding resonator stage is coupled to the input IDT422of following resonator stage (in other words, the electrode or metallization forming the input and output terminals may be common). In this example, the first filter output OUT1of the filter400is at the output of the last resonator stage420-N. The second filter output OUT2of the filter400is at the output of the stage420-N−1 immediately preceding the last resonator stage420-N (or the input of the last resonator stage420-N). However, it shall be understood that the second filter output OUT2may be at the output of a resonator stage preceding the resonator stage420-N−1. As in filter300, there may be other filter elements preceding the filter input IN of filter400, following the first or second filter outputs OUT1and OUT2of the filter400, or in between two of the cascaded resonator stages, wherein such filter element may include a DMS. The filter400applies a first filter frequency response to a first signal applied to the filter input IN that propagates to the first filter output OUT1via the set of cascaded resonator stages420-1to420-N. The filter400applies a second filter frequency response to a second signal applied to the filter input IN that propagates to the second filter output OUT2via a subset of the cascaded resonator stages e.g.,420-1to420-N−1, although both filter frequency responses are affected by one or more common cascaded resonator stages. With reference to filter230shown inFIG.2A, the filter400may be configured to produce the first filter frequency response that meets the passband and rejection requirements of the B25 frequency band, and produce the second filter frequency response that meets the passband and rejection requirements of the B34 frequency band. Although the frequency bands B25 and B34 are used as examples, it shall be understood that the filters described herein are applicable to passbands that are similarly close in frequency or have similar relationship/properties as bands B25 and B34. FIG.5illustrates a schematic/block diagram of another example receiver front-end500in accordance with another aspect of the disclosure. The receiver front-end500includes at least one antenna510, an antenna switching network520, a set of inductors LI1, LI2, and LI3, a set of band select filters530,532, and534, a set of series inductors LO1, LO2, and LO3, and a low noise amplifier (LNA) switching network540. As discussed further herein, the band select filter530is configured with multiple- or dual-inputs to produce different frequency responses suitable for different frequency bands, such as the B25 and B34 frequency bands, respectively. The antenna switching network520includes a set of switching devices SWI1, SWI2, and SWI3including respective first terminals coupled to the at least one antenna510. The open/closed states of the set of switching devices SWI1, SWI2, and SWI3are responsive to a band select signal BAND_SEL. The series inductor Lu is coupled between a second terminal of the switching device SWI1and the B34 input of filter530. The series inductor LI2is coupled between the second terminal of the switching device SWI2and the B25 input of filter530and the input of filter532. The series inductors LI1and LI2function to improve the impedance match between the inputs of the filters530and532and the at least one antenna510. The shunt inductor LI3is coupled between a second terminal of the switching device SWI3(and the input of filter534) and ground. The shunt inductor LI3functions to improve the impedance match between the input of the filter534and the at least one antenna510, as well as to provide phase shifting to reduce loading of filter530by filter534or vice-versa, when the filters530and534are used simultaneously (i.e., when the inputs of the filters530and534are coupled together). The set of filters530,532, and534are configured to substantially pass through the DL signals within corresponding frequency bands, and substantially reject signals that are outside of the corresponding frequency bands. As previously discussed, the filter530includes dual-inputs to provide two different filter frequency responses suitable for frequency bands B25 and B34, respectively; the filter532provides a filter frequency response suitable for frequency band B66; and the filter534provides a filter frequency response suitable for frequency band B39. Each of the filters530,532, and534may be configured as a SAW filter. The LNA switching network540includes a first set of switching devices SWO1, SWO2, and SWO3, a set of LNAs542,544, and546, and a second set of switching devices SWO5, SWO6, and SWO7. The set of series inductors LO1, LO2, and LO3are coupled between the outputs of filters530,532and534and first terminals of the first set of switching devices SWO1, SWO2, and SWO3, respectively. The set of series inductors LO1, LO2, and LO3function to improve the impedance match between the outputs of filters530,532and534and the inputs of the set of LNAs542,544, and546, respectively. The set of LNAs542,544, and548are coupled between second terminals of the first set of switching devices SWO1, SWO2, and SWO3and first terminals of the second set of switching devices SWO5, SWO6, and SWO7, respectively. The second set of switching devices SWO5, SWO6, and SWO7include respective second terminals coupled together, and to additional processing circuitry further downstream (e.g., mixer with local oscillator (LO), baseband filter, etc.). Similarly, the open/closed states the first and second sets of switching devices SWO1-SWO3and SWO5-SWO7are responsive to the band select signal BAND_SEL. In operation, if the DL signal-of-interest is within frequency band B34, the band select signal BAND_SEL controls the switching devices SWI1, SWO1, and SWO5to close, and the switching devices SWI2, SWI3, SWO2, SWO3, SWO6, and SWO7to open. In this configuration, the at least one antenna510is coupled to the B34 input of the filter530via the series inductor LI1, the output of the filter530is coupled to the input of the LNA542via the series inductor LO1, and the output of the LNA542is coupled to the additional processing circuitry. The filter530substantially passes through the DL signal within the B34 frequency band, and substantially rejects signals outside of the B34 frequency band in accordance with a particular filter frequency response. Thus, the receiver front-end500may process the DL signal within the frequency band B34 (e.g., filter and low noise amplify) and provide it to the additional processing circuitry to obtain the data embedded in the signal. Also, in this configuration, the B25 input to filter530is not used as switching devices SWI2is open. Further, the remaining filters532and534and LNAs544and546are not used because the corresponding switching devices SWI2, SWI3, SWO2, SWO3, SWO6, and SWO7are open. If the DL signals-of-interest are within frequency bands B25 and B66, which may be multiplexed together, the band select signal BAND_SEL controls the switching devices SWI2, SWO1, SWO2, SWO5, and SWO6to close, and the switching devices SWI1, SWI3, SWO3, and SWO7to open. In this configuration, the at least one antenna510is coupled to the B25 input of the filter530and the input of filter532, both via the series inductor LI2, the output of filter530is coupled to the input of the LNA542via the series inductor LO1, the output of filter532is coupled to the input of the LNAs544via the series inductor LO2, and the outputs of the LNAs542and544are coupled to the additional processing circuitry. The filter530substantially passes through the DL signal within the B25 frequency band, and substantially rejects signals outside of the B25 frequency band in accordance with a particular filter frequency response. Similarly, the filter532substantially passes through the DL signal within the B66 frequency band, and substantially rejects signals outside of the B66 frequency band in accordance with another particular filter frequency response. Thus, the receiver front-end500may process the DL signals within the frequency bands B25 and B66 (e.g., filter and low noise amplify) and provide them to the additional processing circuitry to obtain the data embedded in these signals. In this configuration, the B34 input to the filter530is not used as switching device SWI1is open. Also, the remaining filter534and LNA546are not used because the corresponding switching devices SWI3, SWO3, and SWO7are open. Similarly, if the DL signals-of-interest are within frequency bands B34 and B39 in a carrier aggregation (CA) mode of operation, the band select signal BAND_SEL controls the switching devices SWI1, SWI3, SWO1, SWO3, SWO5, and SWO7to close, and the switching devices SWI2, SWO2, and SWO6to open. In this configuration, the at least one antenna510is coupled to the B34 input of the filters530via the series inductor LI1, and the input of filter534, the outputs of filters530and534are coupled to the inputs of the LNAs542and546via the series inductors LO1and LO3, and the outputs of the LNAs542and546are coupled to the additional processing circuitry. The filter530substantially passes through the DL signal within the B34 frequency band, and substantially rejects signals outside of the B34 frequency band in accordance with a particular filter frequency response. Also, the filter534substantially passes through the DL signal within the B39 frequency band, and substantially rejects signals outside of the B39 frequency band in accordance with another particular filter frequency response. Thus, the receiver front-end500may process the DL signals within the frequency bands B34 and B39 (e.g., filter and low noise amplify) in CA mode, and provide them to the additional processing circuitry to obtain the data embedded in these signals. In this configuration, the B25 input of the filter530is not used as switching device SWI2is open. Also, the remaining filter532and LNA544are not used because the corresponding switching devices SWI2, SWO2and SWO6are open. Comparing the receiver front-end500with receiver front-end100, the receiver front-end500has less filters, less switching devices, and less LNAs. This translates to significant cost savings, significant IC footprint savings, and improved receiver performance as there are less components to adversely interact with each other. FIG.6illustrates a schematic diagram of an example filter600with multiple inputs to produce multiple filter frequency responses in accordance with another aspect of the disclosure. The filter600may be an example detailed implementation of the filter530previously discussed. The filter600includes a first filter input (IN1), a second filter input (IN2), a set of two or more cascaded resonator stages610-1to610-N, and an output (OUT). The set of two or more cascaded resonator stages610-1to610-N is coupled between the first filter input IN and the filter output OUT. Another way to characterize the filter600is that it includes a first set of one or more cascaded resonator stages (e.g.,610-1) between the first filter input (IN1) and the second filter input (IN2), and a second set of one or more cascaded resonator stages (e.g.,610-2to610-N) between the second filter input (IN2) and the filter output (OUT). With reference to filter530shown inFIG.5, the first filter input IN1, which may serve as the B25 input, is coupled to the series inductor LI2. The second filter input IN2, which may serve as the B34 input, is coupled to the series inductor LI1. The filter output OUT is coupled to the series inductor LO1. In this example, each of the cascaded resonator stages includes a parallel resonator (e.g., a micro-acoustic resonator) and a series resonator (e.g., a micro-acoustic resonator), with the exception that the last or Nth resonator stage610-N may include two parallel resonators. For example, the first resonator stage610-1includes a first parallel resonator P1coupled between a first node n1and ground, and a first series resonator S1coupled between the first node n1and a second node n2. The first node n1may be the positive terminal of the first filter input IN1. However, it shall be understood that the filter600may include other filter elements preceding the first resonator stage610-1, such as a DMS filter element. The second resonator stage610-2includes a second parallel resonator P2coupled between the second node n2and ground, and a second series resonator S2coupled between the second node n2and a third node n3. Depending on the number of stages N (which, as discussed, could be two or more), the cascaded resonator stages continues in a similar manner, including, as illustrated the second-to-last resonator stage610-N−1, which includes a parallel resonator PN−1 coupled between a node nN−1 and ground, and a series resonator SN−1 coupled between the node nN−1 to node nN; and the last resonator stage610-N, which includes an Nth parallel resonator PN coupled between the nN node and ground, an Nth series resonator SN coupled between the nN node and an nN+1 node, and an N+1 parallel resonator coupled between the nN+1 node and ground. The node nN+1 may serve as the positive terminal of the filter output OUT. However, it shall be understood that the filter600may include other filter elements following the resonator stage610-N, such as a DMS filter element. The filter600may also include such DMS filter element between any two of the cascaded resonator stages610-1and610-N. As discussed, the filter600includes the second filter input IN2coupled to the input (node n2) of the second cascaded resonator stage610-2and ground. Thus, the second filter input IN2bypasses the first cascaded resonator stage610-1. However, it shall be understood that the second filter input IN2may be coupled to the input of another cascaded resonator stage, such as anyone of stages610-3to610-N and ground. As discussed, the node n2may serve as the positive terminal of the second filter input IN2. However, it shall be understood that the filter600may include other filter elements between the second filter input IN2and the input n2of the second cascaded resonator stage610-2, such as a DMS filter element. The filter600has a first filter frequency response for a first signal applied to the first filter input IN1that propagates to the filter output OUT via the set of cascaded resonator stages610-1to610-N. The filter600has a second filter frequency response for a second signal applied to the second filter input IN2and propagates to the filter output OUT via the subset of cascaded resonator stages610-2to610-N, although both filter frequency responses are affected by one or more common cascaded resonator stages. With reference to filter530shown inFIG.5, the filter600may be configured to produce the first filter frequency response that meets the passband and rejection requirements of the B25 frequency band, and produce the second filter frequency response that meets the passband and rejection requirements of the B34 frequency band. As discussed, in this example, each of the cascaded resonator stages includes at least one parallel resonator and a series resonator. It shall be understood that each of the cascaded resonator stages may include a series resonator, but not a parallel resonator (e.g., in the case of a one-port SAW resonator). Also, it shall be understood that each of the cascaded resonator stages need not be configured the same, but one or more may be configured differently, such as the case where the last stage610-N includes two parallel resonators and the other stages include one parallel resonator. Each of the resonators of the filter600may be a SAW or BAW type resonator, or other type of resonator, such as a inductor-capacitor resonator, coaxial resonator, dielectric resonator, crystal resonator, ceramic resonator, Yttrium iron garnet (YIG) resonator, or other. FIG.7illustrates a top view diagram of an example filter700with multiple inputs to produce multiple filter frequency responses in accordance with another aspect of the disclosure. The filter700may be an example SAW implementation of the filter600previously discussed. The filter700includes a first filter input (IN1), a second filter input (IN2), a set of two or more cascaded resonator stages720-1to720-N, and an output OUT. The set of cascaded resonator stages720-1to720-N are coupled between the first filter input (IN1) and the output OUT. The set of two or more cascaded resonator stages720-1to720-N are formed on a piezoelectric substrate710, such as single crystal quartz, lithium niobite, lithium tantalite, and others. In this example, each of the cascaded resonator stages720-1to720-N is configured as a two-port SAW resonator. That is, each resonator stage includes an input IDT722(which is a comb-like electrode or metallization structure disposed on the substrate710), and output IDT724, an input grating726, and an output grating728. The input IDT722includes a grounded terminal and an input terminal, which may serve as the first input (IN1) of the filter700if it is part of the first resonator stage720-1, or coupled to an output of a previous stage if it is part of another resonator stage (e.g., anyone of resonator stages720-2to720-N). The output IDT724includes a grounded terminal and an output terminal, which may serve as the output (OUT) of the filter700if it is part of the last resonator stage720-N, or produces a signal for a following stage if it is part of another resonator stage (e.g., anyone of resonator stages720-1to720-N−1). The input and output IDTs722and724are juxtaposed next to each other along the interior center of the resonator. The input grating726is on the exterior side of the input IDT722, and the output grating728is on the exterior side of the output IDT724. To form the cascaded arrangement, the output IDT724of a preceding resonator is coupled to the input IDT722of following resonator (in other words, the electrode or metallization forming the input and output terminals may be common). In this example, the first filter input IN1of the filter700is at the input of the first resonator stage720-1. The second filter input IN2of the filter700is at an input of the second resonator stage720-2. In this example, the terminal reserved for grounding the output IDT724of the second resonator stage720-2may be used for the second filter input IN2. However, it shall be understood that the second filter input IN2may be coupled to the input of a resonator stage following the second resonator stage720-2. As in filter300, there may be other filter elements preceding the first and second filter inputs IN1and IN2of filter700, following the output OUT of the filter700, or in between two cascaded resonator stages, such filter element may include a DMS. The filter700has a first filter frequency response for a first signal applied to the first filter input IN1that propagates to the filter output OUT via the set of cascaded resonator stages720-1to720-N. The filter700has a second filter frequency response for a second signal applied to the second filter input IN2that propagates to the filter output OUT via the subset of cascaded resonator stages720-2to720-N, although both filter frequency responses are affected by one or more common cascaded resonator stages. With reference to filter530shown inFIG.5, the filter700may be configured to produce the first filter frequency response that meets the passband and rejection requirements of the B25 frequency band, and produce the second filter frequency response that meets the passband and rejection requirements of the B34 frequency band. FIG.8illustrates a flow diagram of an example method800of filtering multiple signals in accordance with another aspect of the disclosure. The method800includes receiving first and second signals at a filter input (block810). The method800further includes filtering the first signal via a set of cascaded resonator stages to generate a first filtered signal at a first filter output (block820). Additionally, the method800includes filtering the second signal via a subset of one or more of the set of cascaded resonator stages to generate a second filtered signal at a second filter output (block830). FIG.9illustrates a flow diagram of another example method900of filtering multiple signals in accordance with another aspect of the disclosure. The method900includes receiving first and second signals at first and second filter inputs, respectively (block910). The method900further includes filtering the first signal via a set of cascaded resonator stages to generate a first filtered signal at a filter output (block920). Additionally, the method900includes filtering the second signal via a subset of one or more of the set of cascaded resonator stages to generate a second filtered signal at the filter output (block930). FIG.10illustrates a block diagram of an example wireless communication device1000in accordance with another aspect of the disclosure. The wireless communication device1000may take the form of a smart phone, personal computer, laptop computer, computing pad, Internet of Things (IoT) devices, vehicle traffic control devices, sensors, and others. In this example, the wireless communication device1000is configured to at least wirelessly receive a signal from a remote device, such as a base station. The wireless communication device1000includes a baseband integrated circuit (IC)1010, which may be configured as a system on chip (SOC). The SOC1010may be configured to process data in accordance with any number of applications. The wireless communication device1000further includes a transceiver1020and at least one antenna1030. The transceiver1020may include any of the receiver front-ends described herein. The at least one antenna1030may correspond to any of the at least one antenna described herein. The at least one antenna1030wirelessly receives a radio frequency (RF) signal within one or more frequency bands from a remote device, such as a base station. As discussed, the receiver front-end in the transceiver1020selects the appropriate dual-input or dual-output filter and LNA to filter and amplify the received RF signal. The transceiver1020may process the filtered and amplified RF signal to generate a baseband signal, and process the baseband signal to generate data. The data may be provided to the SOC1010for processing in accordance with any number of applications. Although the wireless communication device1000is described as receiving signals, it shall be understood that the wireless communication device1000(such as the transceiver1020) may be configured to also generate and transmit RF signals to one or more other devices, such as a base station. Implementation examples are in the following numbered clauses: 1. An apparatus, comprising a filter including:a first set of one or more cascaded resonator stages coupled between a filter input and a first filter output, each cascaded resonator stage of the first set comprising a first series micro-acoustic resonator and a first parallel micro-acoustic resonator; anda second set of one or more cascaded resonator stages coupled between the first filter output and a second filter output, each cascaded resonator stage of the second set comprising a second series micro-acoustic resonator and a second parallel micro-acoustic resonator. 2. The apparatus of clause 1, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a one-port surface acoustic wave (SAW) resonator. 3. The apparatus of clause 1 or 2, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a two-port surface acoustic wave (SAW) resonator. 4. The apparatus of any of clauses 1-3, wherein the filter further comprises a double mode surface acoustic wave (DMS) filter element. 5. The apparatus of any of clauses 1-4, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a bulk acoustic wave (BAW) resonator. 6. The apparatus of any of clauses 1-5, wherein the filter is configured to:apply a first filter frequency response to a first signal propagating from the filter input to the first filter output via the first set of one or more cascaded resonator stages; andapply a second filter frequency response to a second signal propagating from the filter input to the second filter output via the first and second sets of cascaded resonator stages. 7. The apparatus of clause 6, wherein the second filter frequency response includes a passband that extends from 1930 megaHertz (MHz) to 1995 MHz. 8. The apparatus of clause 6, wherein the first filter frequency response includes a passband that extends from 2010 MHz to 2025 MHz. 9. The apparatus of any of clauses 1-8, further comprising at least one antenna coupled to the filter input. 10. The apparatus of clause 9, wherein the at least one antenna is coupled to the filter input via a switching device responsive to a band select signal. 11. The apparatus of any of clauses 1-10, further comprising a shunt inductor coupled between the filter input and ground. 12. The apparatus of any of clauses 1-11, further comprising:a first low noise amplifier (LNA);a first series inductor coupled between the first filter output of the filter and an input of the first LNA;a second LNA; anda second series inductor coupled between the second filter output and an input of the second LNA. 13. The apparatus of clause 12, further comprising:a first switching device coupled in series with the first series inductor between the first filter output of the filter and the input of the first LNA; anda second switching device coupled in series with the second series inductor between the second filter output of the filter and the input of the second LNA, wherein the first and second switching devices are responsive to a band select signal. 14. The apparatus of clause 13, further comprising:additional processing circuitry;a third switching device coupled between an output of the first LNA and the additional processing circuitry; anda fourth switching device coupled between an output of the second LNA and the additional processing circuitry, wherein the first and second switching devices are responsive to a band select signal. 15. The apparatus of clause 14, further comprising:a second filter;a third LNA;a third series inductor coupled between an output of the second filter and an input of the third LNA;a fifth switching device coupled in series with the third series inductor between the output of the second filter and the input of the third LNA; anda sixth switching device coupled between an output of the third LNA and the additional processing circuitry. 16. The apparatus of clause 15, wherein an input of the second filter is coupled to the filter input of the filter. 17. A method, comprising:receiving first and second signals at a filter input;filtering the first signal via a set of cascaded resonator stages to generate a first filtered signal at a first filter output; andfiltering the second signal via a subset of one or more of the set of cascaded resonator stages to generate a second filtered signal at a second filter output. 18. The method of clause 17, wherein:the set of cascaded resonator stages apply a first filter frequency response to the first signal to generate the first filtered signal; andthe subset of one or more of the set of cascaded resonator stages apply a second filter frequency response to the second signal to generate the second filtered signal, wherein the first filter frequency response is different than the second filter frequency response. 19. The method of clause 17 or 18, wherein at least one of the set of cascaded resonator stages includes a one-port surface acoustic wave (SAW) resonator. 20. The method of any of clauses 17-19, wherein at least one of the set of cascaded resonator stages includes a two-port surface acoustic wave (SAW) resonator. 21. The method of any of clauses 17-20, wherein at least one of the set of cascaded resonator stages includes a micro-acoustic resonator. 22. An apparatus, comprising a filter including:a first set of one or more cascaded resonator stages coupled between a first filter input and a second filter input, each cascaded resonator stage of the first set comprising a first series micro-acoustic resonator and a first parallel micro-acoustic resonator; anda second set of one or more cascaded resonator stages coupled between the second filter input and a filter output, each cascaded resonator stage of the second set comprising a second series micro-acoustic resonator and a second parallel micro-acoustic resonator. 23. The apparatus of clause 22, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a one-port surface acoustic wave (SAW) resonator. 24. The apparatus of clause 22 or 23, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a two-port surface acoustic wave (SAW) resonator. 25. The apparatus of any of clauses 22-24, wherein at least one of the first or second series micro-acoustic resonator, or first or second parallel micro-acoustic resonator includes a bulk acoustic wave (BAW) resonator. 26. The apparatus of any of clauses 22-25, wherein the filter is configured to:apply a first filter frequency response to a first signal propagating from the first filter input to the filter output via the first and second sets of cascaded resonator stages; andapply a second filter frequency response to a second signal propagating from the second filter input to the filter output via the second set of one or more cascaded resonator stages. 27. The apparatus of clause 26, wherein the first filter frequency response includes a passband that extends from 1930 megaHertz (MHz) to 1995 MHz. 28. The apparatus of clause 26, wherein the second filter frequency response includes a passband that extends from 2010 MHz to 2025 MHz. 29. An apparatus, comprising a filter including a set of cascaded resonator stages coupled between a filter input and a first filter output, wherein the filter includes a second filter output coupled to an output of a first or an intermediate one of the set of cascaded resonator stages. 30. The apparatus of clause 29, wherein at least one of the set of cascaded resonator stages includes a parallel resonator and a series resonator. 31. A method, comprising:receiving first and second signals at first and second filter inputs, respectively;filtering the first signal via a set of cascaded resonator stages to generate a first filtered signal at a filter output; andfiltering the second signal via a subset of one or more of the set of cascaded resonator stages to generate a second filtered signal at the filter output. 32. The method of clause 29, wherein at least one of the set of cascaded resonator stages includes a micro-acoustic resonator. The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. | 62,949 |
11942925 | The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION A measurement management technique utilizes a higher-priority measurement, referred to as a Measure-First measurement, followed by a Round-Robin measurement sequence to provide independent selection and management of measurements that are synchronized to an On-State of a switching signal (e.g., a state of a switching control signal corresponding to an enabled state of a high-power drive device) having a variable duty cycle or an Off-State of the switching signal (e.g., a state of a switching control signal corresponding to a disabled state of a high-power drive device). This approach has several advantages when compared to conventional single-measurement or Round-Robin measurement approaches. In at least one embodiment, the measurement management technique prioritizes an input (i.e., one parameter) while providing statistically distributed spacing of lower priority inputs (i.e., lower priority parameters) and adapts to the varying duty-cycle of the synchronizing switching signal. The parameters being measured will vary with the target application. In a gate driver application, exemplary parameters measured include a sensed current through a high-power drive device, a sensed battery voltage, a sensed temperature of the high-power drive device, a voltage on a control node of the high-power drive device, or other parameter. In at least one embodiment, the measurement management technique allows measurement near the beginning or near the end of a single On-State or Off-State of the switching signal. In at least one embodiment, the Measure-First measurement technique allows multiple measurements of the same input to be captured with various timing parameters for system characterization purposes. Referring toFIGS.1and2, in an exemplary motor control application, system controller100receives a voltage (e.g., VDD1, e.g., 3V) based on a first voltage domain and provides one or more signals for a high-power load system operating in a second domain (i.e., VDD3, e.g., hundreds of volts). Gate driver products102each include an isolation barrier and a communication channel for safely communicating control signals from system controller100across isolation barrier130to drive high-power drive device108and high-power drive device109of a traction inverter used to deliver three-phase power to motor120. In at least some embodiments, gate driver products102include integrated voltage regulation and control for an external transformer of a voltage converter. Referring toFIG.2, by integrating the voltage regulation and DC-to-DC controller functions into driver product200, which interacts with an external transformer202, a high-Q inductor may be used in the voltage conversion, yet fewer other additional elements are required externally to the motor control system. By integrating voltage regulation into gate driver products102, less printed circuit board routing is used. Accordingly, the system can achieve improved performance with reduced printed circuit board routing and system cost as compared to a system using an integrated circuit or chip-scale transformer and/or other voltage conversion techniques. Referring toFIG.2, in the exemplary motor control application, driver product200outputs at least one signal used to provide a pulse-width modulated signal having a variable duty-cycle to the gate of high-power drive device108. In an exemplary embodiment, driver product200includes multiple integrated circuits configured as a multi-chip module in a single package. For example, driver product200includes primary-side integrated circuit201and secondary-side integrated circuit203. Primary-side integrated circuit201, receives control signal IN from system controller100and communicates the signal across isolation barrier130to secondary-side integrated circuit203. In such embodiments, terminals244,246,248, . . . ,274are pins of a package of the multi-chip module and are coupled to system controller100and other external elements, e.g., discrete resistors and capacitors. Driver product200includes an isolation communications channel that facilitates communication between primary-side integrated circuit201and secondary-side integrated circuit203. Any suitable communications technique that does not use a conductive path between the two sides may be used, e.g., optical, capacitive, inductive, or electromagnetic techniques. The isolation communications channel facilitates communication of signals between secondary-side integrated circuit203and system controller100using primary-side integrated circuit201. An exemplary isolation communications channel uses digital modulation (e.g., on-off keying modulation) to communicate one or more digital signals between primary-side integrated circuit201and secondary-side integrated circuit203, although other communication protocols may be used. In general, on-off keying modulation is a form of amplitude-shift keying modulation that represents digital data as the presence or absence of a carrier wave or oscillating signal having a carrier frequency fc (e.g., 500 MHz-1 GHz). The presence of the carrier for a specified duration represents a binary one, while its absence for the same duration represents a binary zero. This type of signaling is robust for isolation applications because a logic ‘0’ state sends the same signal (e.g., nothing) as when the primary side loses power and the device gracefully assumes its default state. That behavior is advantageous in driver applications because it will not accidentally turn on a load device being driven, even when the primary side loses power. However, the isolation communications channel may use other types of signals (e.g., pulse width modulated signals or other types of amplitude shift keying modulated signals). The digital modulation scheme used may be determined according to performance specifications (e.g., signal resolution) and environment (e.g., probability of transient events) of the target application. DC-to-DC controller205and DC-to-DC regulator210of gate driver product102and external transformer202form a flyback converter, which is a buck-boost converter. DC-to-DC regulator210senses feedback voltage VFB (e.g., approximately 1.25V) provided by the secondary side of the transformer on terminal272and compares the sensed feedback voltage to a voltage reference. The comparison is compensated based on a voltage on terminal274and fed back to DC-to-DC controller205. DC-to-DC controller205provides switch control signals (e.g., on terminal244) to adjust a pulse-width modulated signal that drives the primary side of external transformer202to achieve a target voltage on the secondary side of external transformer202based on the feedback from DC-to-DC regulator210and voltage sensed on terminals246and248. The voltage converter converts VDD3to VDD2so that gate driver product102can generate one or more control signals, i.e., a control signal (e.g., a control signal having voltage levels in the tens of volts) sufficient to drive a high-power drive device108without damaging gate driver product102. In other embodiments of motor drive circuit200, other power converter architectures and other reference voltage levels may be used. An embodiment of secondary-side integrated circuit203includes driver221, which generates one or more output control signals based on received control signal CTL received from primary-side integrated circuit201, which receives control signal IN on terminal254from system controller100. Driver221provides corresponding signals to terminals264and266. Buffer219generates control signals CTLH and CTLL at appropriate signal levels for controlling pull-up and pull-down devices of driver221, respectively. Buffer219may generate one control signal or two separate control signals for the pull-up device and the pull-down device based on received control signal CTL. External resistance RHadjusts the pull-up strength by 1/RHindependently from external resistance RLthat adjusts the pull-down strength by 1/RL. Although received control signal CTL is illustrated as a single-ended signal based on input control signal CTL received from system controller100on terminal254, note that in other embodiments, input control signal IN and received control signal CTL are differential signals. In general, signals illustrated herein as single-ended signals may be implemented as differential signals in other embodiments and signals illustrated herein as differential signals may be implemented as single-ended signals in other embodiments. The pull-up strength and the pull-down strength of the output control signal provided to the control terminal of high-power drive device108can be independently adjusted from on-resistance RDS(ON)of the integrated pull-up output device coupled to terminal264using one or more passive elements. For example, resistance RHadjusts the pull-up strength. Resistor RLadjusts the pull-down strength of the signal provided to the gate of high-power drive device108via terminal266to have a strength different from the pull-up strength of the signal provided to the gate of high-power drive device108. In a typical configuration, the pull-up time is slower than the pull-down time and resistances RHand RLwill vary with specifications of the device (e.g., power MOSFET, IGBT, GaN MOSFET, Si-Carbide power MOSFET, etc.) used as high-power drive device108. In at least one embodiment, the isolation communications channel feeds back voltage information or fault information from secondary-side integrated circuit203to primary-side integrated circuit201. Primary-side integrated circuit201or system controller100uses that information to adjust operating parameters or to generate one or more fault indicators that may be used for automatically handling faults by controlling output driver221accordingly. For example, secondary-side integrated circuit203includes modules that detect fault conditions associated with high-power drive devices, e.g., desaturation detector214, and may also detect fault conditions associated with signaling from system controller100. Fault indicator(s) may be used by secondary-side integrated circuit203to prevent damage to the high-power drive devices, load system, or user of the load system. In addition, secondary-side integrated circuit203may send an indication of a fault or associated diagnostic information to primary-side integrated circuit201and/or system controller100. In at least one embodiment, secondary-side integrated circuit203includes desaturation fault protection for high-power semiconductor devices, which protects against short-circuit current events that may destroy high-power drive device108. This fault may result from an insufficient gate drive signal caused by inverter gate driver misbehavior, drive supply voltage issues, a short circuit in a power stage, or other excessive current or power dissipation of the high-power drive devices. Those events can substantially increase power consumption that quickly overheats and damages the corresponding high-power drive device. For example, when a short circuit current condition occurs in the exemplary motor drive application ofFIGS.1and2(e.g., both devices of an individual inverter phase of a three-phase inverter are on), high current flows through high-power drive devices108and109and may destroy high-power drive devices108and109. Accordingly, a fault detection technique detects this desaturation condition. Driver product200may send an indication thereof to system controller100. In at least one embodiment of gate driver product102, desaturation fault protection turns off high-power drive device108following detection of the fault condition. In a typical application, terminal262is coupled to an external resistor and diode that are coupled to a terminal of high-power drive device108(e.g., the collector terminal of an IGBT or drain terminal of a MOSFET). In at least one embodiment of gate driver product102, desaturation detection circuit214is enabled only while high-power drive device108is turned on. Desaturation detection circuit214senses when the collector-emitter voltage (or drain-to-source voltage, as the case may be) of high-power drive device108exceeds a predetermined threshold level (e.g., 7V). Note that the predetermined threshold level of desaturation detection circuit214may be externally adjusted based on the forward voltage of one or more diodes coupled to the desaturation resistor coupled to terminal262or based on the resistance of the desaturation resistor. In addition, a delay time may be introduced by coupling a capacitor between terminal262and an external power supply node. In general, undervoltage lockout detector212prevents application of insufficient voltage to the control terminal of high-power drive device108by forcing the output on terminal264to be low during power-up of gate driver product102. Undervoltage lockout detector212detects when the power supply voltage (e.g., VDD2sensed using terminal260) falls below a first predetermined undervoltage lockout threshold voltage and generates an indication thereof, which may be used to disable the lockout condition. Undervoltage lockout detector212also detects when the power supply voltage falls below a second predetermined undervoltage lockout threshold, which may be different from the first undervoltage lockout threshold voltage, to provide noise margin for the undervoltage lockout voltage detection. The indicator generated by undervoltage lockout detector212may be provided to system controller100using terminal252. In at least one embodiment, driver product200includes a similar mechanism for an overvoltage condition. Miller clamp220reduces effects of parasitic turn-on of high-power drive device108due to charging of the Miller capacitor (e.g., the collector-to-gate parasitic capacitor of an IGBT device or the drain-to-gate parasitic capacitor of a MOSFET in other embodiments of high-power device108). That gate-to-collector coupling can cause a parasitic turn on of device108in response to a high transient voltage (e.g., a gate voltage spike) generated while high-power drive device108is turned off. A gate voltage spike is created when turning on another high-power drive device coupled to high-power drive device108. For example, when turning on upper high-power drive device109, a corresponding lower high-power drive device108coupled to upper high-power drive device109experiences a voltage change dVCE/dt causing current flow into the gate drive terminal coupled to lower high-power drive device108. In the absence of Miller clamp220, this current would create a voltage drop across external resistance RLand would increase the gate-to-emitter voltage of a corresponding lower high-power drive device108. If the gate-to-emitter voltage exceeds the device threshold voltage (e.g., 2 V), then high-power drive device108turns on. A similar parasitic turn-on event occurs when turning on high-power drive device108and the corresponding upper high-power drive device109is in an off state. Miller clamp220prevents parasitic turn-on by coupling terminal268to ground via a low-resistance switch that hinders or prevents the Miller capacitor current from developing a voltage sufficient to turn on the high-power drive device. In some embodiments of driver product200, Miller clamp220is not needed because a sufficiently sized gate capacitor coupled between the gate and emitter of each high-power drive device108shunts any Miller current and raises the level of the transient needed to parasitically turn on the device. However, such embodiments increase the gate charge voltage required to reach the threshold voltage of high-power drive device108, increase the driver power, and increase switching losses of high-power drive device108. In other embodiments of driver product200that do not use a Miller clamp circuit, the lower supply voltage is coupled to a negative voltage (e.g., −5 V) rather than ground. This configuration provides additional voltage margin to increase the likelihood that the parasitic turn-on transient does not raise the control terminal of high-power drive device108above its threshold voltage. However, this configuration increases cost by requiring an additional pin on the package and requiring generation of the negative voltage. Upon detection of a fault condition by modules on secondary-side integrated circuit203, fault logic216generates control signal FAULT, which may initiate shutdown of high-power drive device108. Fault logic216reports the fault condition to system controller100via primary-side integrated circuit201. Alternatively, fault logic216only reports the fault condition to primary-side integrated circuit201and high-power drive device108continues operation. Then, primary-side integrated circuit201reports the fault condition to system controller100. Since a system may include multiple high-power drive devices (e.g., six high-power drive devices in the exemplary motor control application described herein), shutting down only one of these devices may harm the high-power drive devices or the load. Therefore, in response to detection of a fault, system controller100may initiate a shutdown of high-power drive device108only after detecting a predetermined number of faults over a particular period or other condition is satisfied. In at least one embodiment, system controller100initiates shutdown of high-power drive device108independently from any fault detection of driver product200(e.g., based on fault detection from another driver product200associated with another high-power drive device108or109). An abrupt shutoff of high-power drive device108may result in large di/dt induced voltages. Such voltage spikes could be damaging to high-power drive circuit108or the load. Accordingly, in response to a fault condition, system controller100or driver product200initiates a soft shutdown of high-power drive device108that slowly discharges the control terminal of high-power drive device108at a rate having a turn-off time longer than the regular turn-off time of the output control signal. For example, fault logic216receives an indicator from desaturation detection circuit214and generates control signal FAULT based thereon that initiates a soft shutdown. In other embodiments, fault logic216receives an indicator from one or more other fault detection circuits. Typical implementations of a soft-shutdown function in a driver product may use an additional terminal or at least one additional external resistor coupled to terminal264or terminal266. Referring toFIG.3, in at least one embodiment, a driver product includes a primary-side integrated circuit, isolation barrier, and isolation communications channel, as described above, and secondary-side integrated circuit303including gate driver features describe above. In at least one embodiment, secondary-side integrated circuit303of driver product300includes driver321coupled to terminal VO, which in some embodiments is the only terminal of driver product300that is coupled to the gate terminal of high-power drive device108. In at least one embodiment, driver321is a variable strength driver that integrates the Miller clamp function or other fault detection circuits described above, and eliminates external resistors coupled to high power drive device108described above. Embodiments of variable strength driver321are described in U.S. patent application Ser. No. 17/138,091, entitled “VARIABLE CURRENT DRIVE FOR ISOLATED GATE DRIVERS,” naming Ion C. Tesu, James E. Heckroth, Stefan N. Mastovich, John N. Wilson, Krishna Pentakota, Michael Ireland, Greg Ridsdale, and Lyric Jackson as inventors, filed on Dec. 30, 2020, which application is incorporated herein by reference now U.S. Pat. No. 11,362,646. In at least one embodiment of secondary-side integrated circuit303, controller304configures driver321to source current according to a normal turn-on profile in response to a switching control signal transitioning from a first value to a second value, configures driver321to sink current according to a normal turn-off profile in response to the switching control signal transitioning from the second value to the first value, or configures driver321to implement a soft-shutdown turn-off profile in response to the switching control signal having the second value and in response to a fault condition (e.g., a desaturation fault condition indicated by control signal FAULT). In at least one embodiment, controller304receives the switching control signal from receiver306, which receives the control signal across isolation barrier130from system controller302using controller322, memory324, and transmitter318. Controller304provides digital signals to transmitter308for transmission across isolation barrier130to system controller302using receiver320, controller322, and memory324. In at least one embodiment, one or more digital signals DIG1, DIG2, . . . , DIGn are digital values (i.e., measurements) received from corresponding analog-to-digital converter circuits for storage in memory314and used by controller304or transmission across the isolation barrier by transmitter308. In at least one embodiment, digital signal DIG1is a digital value corresponding to a measurement received from analog-to-digital converter310and indicates a level of the output voltage on the control terminal of high-power drive device108. In at least one embodiment, digital signal DIG2is a digital value corresponding to a feedback signal generated by sensor316, digitized by analog-to-digital converter312, and indicates a sensed temperature level or battery voltage received from an external sensor coupled to gate driver product300. In other embodiments, an analog-to-digital converter digitizes a level of a signal on terminal VO and digital comparison logic or controller304generates a measurement that is indicative of the comparison of gate-to-source voltage VGSof high-power drive device108to a predetermined threshold voltage. In an embodiment, controller304receives other digital signals corresponding to other signals sensed by secondary-side integrated circuit303(e.g., indicators of collector-emitter current of high-power drive device108, indicator of battery voltage, indication of temperature of high-power drive device108, or other system parameter). Controller304provides at least one measurement to transmitter308, which communicates the measurement across the isolation barrier using a digital modulation scheme (e.g., on-off keying described above). Referring toFIG.3, in an embodiment, secondary-side integrated circuit303includes controller304, which includes state machine305, and memory314that are used to implement a flexible and adaptive measurement management technique that selects, prioritizes, and sequences measurements of different inputs that are synchronized to the switching control signal. In an embodiment, the switching control signal controls a corresponding high-power drive device108. This technique utilizes a selectable high priority Measure-First measurement followed by a flexible Round-Robin measurement sequence described further below. In an embodiment, system controller302configures measurements for a target application by writing to on-state registers328and off-state registers330on the low-voltage side of the system, information for configuring measurements made by the secondary-side integrated circuit303on the high-voltage side of the system. A replica of that information is stored in on-state registers313and off-state registers315on the high-voltage side of the system. For example, an On-State measurement configuration is stored in ON CONFIG of on-state registers313and Off-State measurement configuration is stored in OFF CONFIG of off-state registers315. Secondary-side integrated circuit303communicates information sensed by the high-voltage side of the system, to system controller302via the primary-side integrated circuit201for storage in memory326. On-state registers313and328include register ON_MF, which stores the identity of a prioritized, Measure-First measurement to be made in the On-State and registers ON_RR1, ON_RR2, ON_RR3, and ON_RR4, which store the identities of Round-Robin prioritized inputs to be measured in the On-State. Similarly, off-state registers315and330include register OFF_MF, which stores the identity of a Measure-First prioritized measurement to be made in the Off-State and registers OFF_RR1, OFF_RR2, OFF_RR3, and OFF_RR4, which store the identities of Round-Robin prioritized inputs to be measured in the Off-State. Referring toFIGS.3and4, in at least one embodiment, system controller302specifies separate Measure-First and Round-Robin sequences for On-State and for Off-State measurements and this configuration is communicated to secondary-side integrated circuit303. State machine305controls execution of the measurements made using one or more analog-to-digital converters or sensors coupled to DIG1, DIG2, . . . , DIGN. Controller304stores those measurements in registers (e.g., ON_MF, ON_RR1, ON_RR2, ON_RR3, ON_RR4, OFF_RR1, OFF_RR2, OFF_RR3, and OFF_RR4) and transfers the data to primary-side integrated circuit201for storage in corresponding locations in memory324, which are readable by system controller302. In at least one embodiment, controller304independently configures characteristics of On-State measurements and Off-State measurements with regard to Measurement Sequence Settling Time, Measure-First input selection, Post-Measure-First Delay time, Round-Robin Sequence Input Selection, Inter-Round-Robin Delay time, Round-Robin Sequence Resume location, and Round-Robin Repeat and Overwrite mode, as described further below. Measurement Sequence Settling Time (ON_Settling, OFF_Settling) In at least one embodiment, Measurement Sequence Settling Time specifies the time delay after a leading edge (e.g., a first edge of a pulse having an active level) of a corresponding On-State or Off-State, after which the first measurement of the associated measurement sequence should begin. The settling time is used to delay measurement until switching transients have died out. In at least one embodiment, ON_Settling specifies Measurement Sequence Settling Time for the On-State measurement sequence and OFF_Settling specifies the Measurement Sequence Settling Time for the Off-State measurement sequence. Two settling time modes are available: Fixed and Automatically Centered. In at least one embodiment, when Fixed mode is selected for either the On-State measurement sequence or the Off-State measurement sequence, a predetermined fixed settling time, i.e., tON_fixed or tOFF_fixed, respectively, is used. In at least one embodiment, if the Automatically Centered mode is selected for either the On-State measurement sequence or the Off-State measurement sequence, then controller304uses an automatically generated settling time, e.g., tON_center or tOFF_center, respectively. If the duty-cycle of the synchronizing switching signal varies relatively slowly, then the duration of the current On-State or Off-State will be approximately the same as that of the preceding On-State or Off-State, respectively. In at least one embodiment, controller304measures the time of each On-State and Off-State and dynamically adjusts the tON_center and tOFF_center times to equal one-half of the measured time of the preceding On-State and Off-State, respectively. Measure-First Measurement Selection (ON_MF, OFF_MF) In at least one embodiment, Measure-First Measurement Selection specifies the input signal assigned to a high-priority Measure-First Measurement Slot. If system controller302does not select an input for the Measure-First Measurement Slot, controller304skips any Measure-First Measurement and begins the measurement sequence with the Round-Robin Sequence. As referred to herein, a “Round-Robin Sequence” provides a time slot to each measurement in a circular order and “Measure-First Measurement” prioritizes measurement of a parameter with respect to the Round-Robin Sequence or other measurements of other parameters. Each of the On-State and Off-State measurement examples described below include a single Measure-First Measurement Slot, although multiple high-priority Measure-First measurement slots could be used. Round-Robin Measurement Queue (ON_RR1, ON_RR2, ON_RRn, OFF_RR1, OFF_RR2, . . . , OFF_RRn) In at least one embodiment, a Round-Robin Measurement Queue includes a number of Measurement Slots. Any, or none, of the input signals can be assigned to any of the Measurement Slots. The On-State and Off-State Round-Robin examples described herein each include four measurement Slots, labelled ON_RR1, ON_RR2, ON_RR3, and ON_RR4, and OFF_RR1, OFF_RR2, OFF_RR3, and OFF_RR4, respectively, although a different number of Round-Robin measurement slots is used in other embodiments. Round-Robin Pick-Up Point (ON_RR_PU, OFF_RR_PU) In at least one embodiment, controller304may interrupt a measurement in response to an occurrence of a trailing edge (i.e., a second edge of a pulse having an active level) of a corresponding On-State or Off-State. These interruptions may be unavoidable in applications where the synchronizing switching signal has a variable duty-cycle. During a subsequent On-State or Off-State, respectively, the measurement sequence will begin with the designated Measure-First measurement, and then return to the specified measurement of the Round-Robin Sequence. The point in the Round-Robin Sequence at which measurement resumes depends on the Round-Robin Pick-Up Point setting. In at least one embodiment, if the Round-Robin Pick-Up Point for the On-State or Off-State (i.e., ON_RR_PU or OFF_RR_PU, respectively) is set to Where Left Off, then the Round-Robin Sequence resumes with the measurement that follows the last measurement that was completed during the preceding On-State or Off-State, respectively. In at least one embodiment, if the Round-Robin Pick-Up Point for the On-State or Off-State is set to Top of List, then the Round-Robin measurement sequence will resume with the measurement specified for the ON_RR1or OFF_RR1measurement slot, respectively, regardless of which measurement was completed last during the preceding On-State or Off-State, respectively. Round-Robin Repeat and Overwrite Mode (ON_RR_Repeat, OFF_RR_Repeat) In at least one embodiment, whether the Round-Robin Repeat and Overwrite Mode settings are enabled or disabled determines whether the Round-Robin Sequence continues if time remains in the ongoing On-State or Off-State after completion of one full cycle of the Round-Robin Sequence. In at least one embodiment, if the Repeat and Overwrite Mode for the On-State or Off-State (ON_RR_Repeat or OFF_RR_Repeat, respectively) is disabled, the measurement process stops after completion of one full cycle through the Round-Robin Sequence, even if time for additional measurements is available in the ongoing On-State or Off-State, respectively. In at least one embodiment, if the Repeat and Overwrite Mode for the On-State or Off-State is enabled, then the measurement process continues after completion of one full cycle through the Round-Robin Sequence, with new measurements overwriting (i.e., replacing) previous measurements made for the corresponding measurement slot. In at least one embodiment, the Repeat and Overwrite process continues until interrupted by the end (i.e., a trailing edge) of the ongoing On-State or Off-State. Measurement Result Time Stamping and Storage In an embodiment of a control system that uses a variable-duty-cycle switching signal, the time available to make measurements during the On-State or the Off-State is variable. Thus, any specific measurement that is scheduled in the measurement sequence for that On-State or Off-State may or may not be made during a given On-State or Off-State depending on the available time. Further, the nature of the Round-Robin Sequence makes determination of the time-order in which the measurements were taken ambiguous without some method of recording measurement times. In at least one embodiment, in order to allow identification of which measurements have been updated, controller304stores all measurement results in their corresponding result registers along with an accompanying timestamp. The time stamp represents the value of a running counter at the time the measurement was made. The time stamp allows identification of which measurements have been updated during the current On-State or Off-State. For example, system controller302determines updated measurements by comparing the timestamp for a specific measurement slot to a corresponding time stamp value from the previous On-State or Off-State. In at least one embodiment, the timestamp is implemented using a rolling counter that is incremented with every rising edge of the switching signal. Parameter Usage Examples FIGS.5A and5Bprovide a graphical representation of exemplary measurement sequences for various parameter settings. Exemplary On-State measurement settings include Input 1 being selected for the Measure First slot for the On-State (i.e., ON_MF: mill). Input 1 is also included in the Round-Robin Sequence for the On-State, along with Input 2, Input 3, and Input 4. The On-State Round-Robin Sequence uses a fixed settling time (i.e., ON Settling: Fixed), a Round-Robin Pick-Up point setting of Where Left Off (i.e., ON_RR_PU: Where Left Off), and has the Round-Robin Repeat and Overwrite Mode Enabled (i.e., ON_RR Repeat: Enabled). The Off-State Measurement Sequence in this example has no Measure First measurement (OFF_MF: (None)). The Off-State Round-Robin Sequence includes Input 2, Input 3, and Input 4. The Off State Settling Time in this case is set to Centered mode (i.e., OFF Settling: Centered), the Round-Robin Pick-Up Point is set to Top of List (i.e., OFF_RR_PU: Top of List), and Repeat and Overwrite is disabled for the Off-State measurements (i.e., OFF_RR Repeat: Disabled). FIGS.3,5A and5Bprovide examples of measurement sequences that would result from these settings for a synchronizing switching cycle with low duty cycle (e.g., less than 50%), medium duty cycle (e.g., 50%), and high duty cycle (e.g., greater than 50%), illustrated in the left column, center column, and right column, respectively. The low-duty-cycle sequence begins with low-to-high transition502of the synchronizing switching signal, which represents the leading edge of the On-State, triggering the On-State Measurement Sequence as follows:after the settling time specified for tON_fixed, controller304measures Input 1 and stores the value in the On-State Measure First register location (In1→ON_MF),after measuring Input 1 and after the delay specified for tON_MF, controller304measures Input 1 and stores the value in the On-State Round-Robin Measurement 1 slot (In1→ON_RR1), andafter measuring Input 1 again and after the delay specified for tON_RR, controller304initiates measurement of Input 2, but that measurement is interrupted by the trailing edge of the On-State (i.e., the high-to-low transition of the synchronizing switching control signal), as illustrated by hatching. High-to-low transition504of the synchronizing switching control signal represents the leading edge of the Off-State and triggers the Off-State Measurement Sequence. The Off-State sequence differs from that of the On-State since the Off-State sequence is configured to have no Measure First measurement and uses a settling time setting of Automatically Centered:after the settling time specified for tOFF_center, controller304measures Input 2 and stores the value in the Off-State Round Robin Measurement 1 slot (In2→OFF_RR1),after measuring Input 2 and the delay specified for tOFF_RR, controller304measures Input 3 and stores the value in the Off-State Round-Robin Measurement 2 slot (In3→OFF_RR2),after measuring Input 3, and the delay specified for tOFF_RR, controller304measures Input 4 and stores the value in the Off-State Round-Robin Measurement 3 slot (In4→OFF_RR3).Since the Off-State Round Robin sequence includes only these three measurements, this measurement completes a full cycle of the sequence.Since the Repeat and Overwrite mode is Disabled for the Off-State Round-Robin Sequence, this measurement completes the Off-State measurement sequence. Low-to-high transition506signals a return to the On-State, and the measurement sequence continues in response to high-to-low transition508, low-to-high transition510. The center column of represents the measurement sequence when the duty-cycle of the synchronizing switching signal is 50%. Controller304begins the On-State measurement sequence as described above for the low-duty-cycle case. However, the 50% duty-cycle provides ample time in the On-State to complete the On-State Round-Robin Sequence, which includes Inputs 1 through 4. Since Repeat and Overwrite is enabled for the On-State, after measurement of Input 4 completes, the measurements begin to repeat, starting with Input 1. The remeasured values, along with their associated timestamps, replace (i.e., overwrite) the measurements or digital values recorded earlier. The measurement sequence continues until the end of the On-State (e.g., high-to-low transition514). In this example, only the original values for the timeslots ON_RR1 and ON_RR2 are rewritten before the end of the On-State. The Off-State measurement sequence for the 50% duty-cycle case is the same as for the low-duty-cycle example, since there is enough time prior to the low-to-high transition506or516, respectively, to complete the non-repeating Off-State sequence in each case. The following On-State sequence between low-to-high transition516and high-to-low transition518is the same as the earlier On-State sequence between low-to-high transition512and high-to-low transition514, with the prioritized measurement of Input 1 followed by resumption of the Round-Robin sequence. However, since the On-State Round-Robin Pick-Up Point is set to Where Left Off, the first measurement of the Round-Robin Sequence for the On-State after low-to-high transition516is the measurement of Input 3 for the ON_RR3measurement slot. The right column illustrates an exemplary measurement sequence for a high duty-cycle (e.g., greater than 50%) synchronizing switching signal. The On-State sequences between low-to-high transition522and high-to-low transition524and between low-to-high transition526and high-to-low transition528include more than one cycle of the Round-Robin Sequence and the Off-State sequences between high-to-low transition524and low-to-high transition526and between high-to-low transition528and low-to-high transition530include less than one cycle of the Round-Robin Sequence. Shaded measurements indicate that those measurements are not final measurements (e.g., measurements that are overwritten or measurements that are incomplete and therefore not saved). FIGS.6A and6Billustrate an exemplary configuration of the measurement technique to facilitate characterization of system performance. The goal of this configuration is to make multiple sequential measurements of a signal to characterize how the signal changes over time. Such measurements can be used, for example, to determine the time required for a voltage to stabilize after a switching edge, or to characterize the effect of a gate driver turn-on or turn-off strength adjustment on the gate voltage or switching current of a high-power drive device. In an embodiment, this configuration assigns the same input signal (e.g, Input 1) to the Measure-First measurement and all of the Round-Robin measurement of the On-State and/or Off-State in order to secure as many measurements of the signal as possible. The Settling time is set to Fixed, which determines when the measurements should begin and is programmed to control the time after the leading edge of the On-State and/or Off-State. The tON_MF and tON_RR timing parameters (and/or tOFF_MF and tOFF_RR for the Off-State) are set to small values to focus the sequence of measurements into the specific time frame of interest. The Round-Robin Pick-Up Point is set to “Top of List”, and Repeat and Overwrite is disabled, to achieve a single, sequential set of measurements. The three columns ofFIGS.6A and6Bshow how the cluster of measurements used for characterization can be located at different times within the On-State and Off-State by changing the settling time settings tON_fixed and tOFF_fixed. Although configurations ofFIGS.6A and6Bshow the duty-cycle being a constant 50% for a characterization involving Input 1, this is not a requirement, and other duty cycles may be used. In some cases, it is desirable to obtain measurements both near the beginning of an On-State (or Off-State) and near the end of the On-State (or Off-State), but is not easily achievable using conventional measurement techniques involving single measurements or Round-Robin measurements alone. However, this is easily done using the measurement management method described herein. Further, the leading edge measurement and the trailing edge measurement may be made on the same input source or on different input sources, as illustrated inFIGS.7A and7Bfor low duty cycle, 50% duty cycle, and high duty cycle synchronizing switching signals.FIGS.7A and7Billustrate measurements at the beginning and at the end of the On-State or Off-State. In this example the Measure First measurements obtain measurements near the beginning of the On-State or Off-State. Fixed settling times tON_fixed and tOFF_fixed determine how close those measurements are to the beginning of the corresponding states. Measurements near the end of the On-State and Off-State are obtained using a Round-Robin measurement sequence with Repeat and Overwrite enabled. In the examples illustrated here, only one measurement is specified for the On-State Round-Robin sequence, so the same measurement is repeated until the end of the On-State. The result from each new measurement, along with the associated timestamp, overwrite the previously captured result (illustrated by shading inFIGS.7A and7B), leaving a final value that was measured as near the end of the On-State as possible. The same technique is used with the Off-State Round-Robin sequence to obtain a measured value that was captured as near to the end of the Off-State as possible. For the On-State, the input source for the Measure-First and for the Round-Robin measurement is Input 1, resulting in measurement of Input 1 being captured at the beginning and at the end of the On-State. For the Off-State case Input 2 is selected for the Measure First, and Input 3 is selected for the Round-Robin input, resulting in a measurement of Input 2 from the beginning of the Off-State and a measurement of Input 3 from the end of the Off-State. FIGS.8A and8Billustrate a Center-Only example that illustrates how the measurement management system can be used to capture a single measurement in the estimated center of the On-State and/or Off-State for low duty cycle, 50% duty cycle, and high duty cycle synchronizing switching signals. This type of centered measurement is useful in applications such as three-phase motor control where the center of the On-State and Off-States represent quiet times where minimal switching transients typically occur. The measurement management system achieves centered measurements, as illustrated inFIGS.8A and8B, using a configuration that makes a single measurement in the On-State or Off-State and has a Settling Time set to Automatically Centered. The On-State measurement uses the Measure First measurement slot as the single measurement; no measurement slots are enabled for the On-State Round-Robin sequence. The Off-State measurement sequence uses a different configuration to achieve the same result. In the Off-State case, the Measure First measurement is not used, and only one of the Round-Robin measurement slots is configured to make the measurement. Thus, techniques for managing switching synchronized measurements using a combination of prioritized measurement and round-robin sequence measurements are disclosed. Structures described herein may be implemented using software executing on a processor (which includes firmware) or by a combination of software and hardware. Software, as described herein, may be encoded in at least one tangible (i.e., non-transitory) computer readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which a gate driver product is configured for power conversion and motor control, one of skill in the art will appreciate that the teachings herein can be utilized with other applications. In addition, while the invention has been described in an embodiment in which a gate driver product includes a DC-to-DC controller, one of skill in the art will appreciate that the teachings herein can be utilized with a gate driver without an integrated DC-to-DC controller. Although signals and responses are described regarding specific edge polarities (e.g., rising edge or positive edge for a transition from a low logic level to a high logic level and falling edge or negative edge for a transition from a high logic level to a low logic level) other combinations of edge polarities may be used. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location, or quality. For example, “a first signal” or “a second signal” does not indicate or imply that the first received network signal occurs in time before the second received network signal. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims. | 46,391 |
11942926 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Parts which correspond to one another are provided with the same reference characters in the figures. FIG.1shows a block circuit diagram of a first exemplary embodiment of a circuit arrangement1according to the invention, The circuit arrangement1comprises a semiconductor switch3with a gate5, a gate driver7for controlling the gate5and a first exemplary embodiment of a protection circuit9according to the invention. The semiconductor switch3of this exemplary embodiment is an IGBT. The gate driver7has an electronic switch unit11with a push-pull output stage having output stage bipolar transistors Q1, Q2and a control input13. The protection circuit9comprises an integrator15, a timer element17and a comparator unit19. According to a first variant of the method according to the invention, a gate charge of the gate5is detected by the integrator15, with the timer element17, a minimum duration to the switching-off of the semiconductor switch3after a switching-on of the semiconductor switch3is set and with the comparator unit19, the semiconductor switch3is switched off when, after the elapse of the minimum duration following a switching-on of the semiconductor switch, the gate charge falls below the reference charge. The reference charge is therein time-independent. The minimum duration is selected such that, during the minimum duration, a gate capacitance and a Miller capacitance of the semiconductor switch after switching into a normal operation of the semiconductor switch are recharged at least approximately completely, for example to at least 90%. The semiconductor switch3is switched off by the comparator unit19in a lasting manner or only for one clock cycle of the gate driver7. FIG.2shows a circuit diagram of a circuit arrangement1according to the first exemplary embodiment. With the electronic switching unit11of the gate driver7, to switch on the semiconductor switch3, the gate5is connected to a switch-on potential and to switch off the semiconductor switch, the gate is connected to a switch-off potential. The switch-on potential is generated by a switch-on voltage source V1. The switch-off potential is generated by a switch-off voltage source V2. The electronic switching unit11is controlled by a driver voltage. The driver voltage is applied by a driver voltage source V3via a driver resistor R3to the control input13of the electronic switching unit11. The voltage sources V1, V2, V3are each DC sources. The integrator15of the protection circuit9has an integrator operational amplifier O1, an integrator capacitor C1and an integrator resistor R4. The integrator capacitor C1and the integrator resistor R4set the time constant of the integrator15. The integrator15detects the gate charge via a voltage drop across a measuring resistor R5. The measuring resistor R5is connected to the emitter of the semiconductor switch3and is also used in this exemplary embodiment as a gate resistor. Alternatively, the measuring resistor R5can be arranged in the gate line of the semiconductor switch3, although this places greater demands on the integrator15, since the measuring resistor R5then lies alternatingly at the switch-on potential and the switch-off potential. Furthermore, in addition to the measuring resistor R5as arranged inFIG.2, a separate gate resistor R2(seeFIG.5) can be connected into the gate line of the semiconductor switch3. The timer element17has a timer element resistor R1, a timer element capacitor C2and a timer element diode D2. The anode of the timer element diode D2is connected to a first terminal R1_1of the timer element resistor R1and a first electrode C2_1of the timer element capacitor C2. The output of the integrator15is connected to the cathode of an output diode D3, the anode of which is connected to the anode of the timer element diode D2, the first terminal R1_1of the timer element resistor R1and the first electrode C2_1of the timer element capacitor C2. The comparator unit19has an npn-bipolar transistor Q3, a pnp-bipolar transistor Q4, a first comparator diode D1, a second comparator diode D4, a comparator capacitor C3, a first comparator resistor R8, a second comparator resistor R6and an optional third comparator resistor R7. The collector of the npn-bipolar transistor Q3is connected to the base of the pnp-bipolar transistor Q4. The collector of the pnp-bipolar transistor Q4is connected to the base of the npn-bipolar transistor Q3and the anode of the first comparator diode D1. The comparator capacitor C3and the first comparator resistor R8are each connected in parallel with the base-emitter path of the pnp-bipolar transistor Q4. The second comparator resistor R6is connected in parallel with the base-emitter path of the npn-bipolar transistor Q3. The cathode of the first comparator diode D1is connected to the anode of the output diode D3. The emitter of the npn-bipolar transistor Q3is connected to the second electrode C2_2of the timer element capacitor C2. The emitter of the pnp-bipolar transistor Q4is connected via the third comparator resistor R7to the second terminal R1_2of the timer element resistor R1. The base of the pnp-bipolar transistor Q4is connected to the cathode of the second comparator diode D4. The emitter of the npn-bipolar transistor Q3is connected to the switch-off potential, that is, the negative terminal of the switch-off voltage source V2. The second terminal R1_2of the timer element resistor R1is connected to the switch-on potential, that is, the positive terminal of the switch-on voltage source V1. The anode of the second comparator diode D4is connected to the control input13of the electronic switching unit11. FIG.3shows variations of currents I1, I2and voltages U1to U4of the circuit arrangement1shown inFIG.2, dependent upon a time t in the case that the semiconductor switch3reaches its desaturation limit after the switch-on. The variations were generated with a simulation in which the semiconductor switch3is connected, as shown inFIG.2, to a second semiconductor switch4to form a half-bridge and a load connected to the half-bridge has been simulated by a load inductance L1, a leakage inductance L2and a load voltage source V4. The load voltage source V4is a DC voltage source. The leakage inductance L2is connected in series with the second semiconductor switch4. The load inductance L1is connected in parallel with the series connection of the leakage inductance L2and the second semiconductor switch4. The simulation was carried out for a measuring resistor R5of 10Ω, a driver resistor R3of 1.5 kΩ, an integrator capacitor C1with a capacitance of 500 pF, an integrator resistor R4of 220Ω, a timer element resistor R1of 2.2 kΩ, a timer element capacitor C2with a capacitance of 10 nF, a comparator capacitor C3with a capacitance of 2 nF, a first comparator resistance R8of 470Ω, a second comparator resistance R6of 470Ω, a third comparator resistor R7of 2.2 kΩ, a load inductance L1of 15 μH, a leakage inductance L2of 150 nH, a switch-on voltage source V1von 15 V, a switch-off voltage source V2of 8 V, a load voltage source V4of 600 V, diodes D2, D3, D4designed as Schottky diodes and a diode D1designed as a Z-diode. Approximately 100 μs after the start of the simulation, the semiconductor switch3is switched on. Thereupon, a gate-emitter voltage U1, a gate current I1and a collector current I2of the semiconductor switch3all rise and a collector voltage U2of the semiconductor switch3falls rapidly to approximately 0 V. At the same time, an integrator output voltage U3at the output of the negating integrator operational amplifier O1falls and a control signal U4which is a voltage between the electrodes C2_1, C_2of the timer element capacitor C2rises. Shortly after the switching-on of the semiconductor switch3, the gate current I1falls again to 0 A. After the gate current I1has fallen again to 0 A, the integrator output voltage U3and the control signal U4initially remain constant. However, the gate-emitter voltage U1and the collector current I2rise further. Approximately 104.5 μs after the start of the simulation, the semiconductor switch3again reaches its desaturation limit and the collector voltage U2rises again (initially only slowly). Thereupon, the Miller capacitance of the semiconductor switch3begins to charge up and the gate current I1begins to flow in the opposite direction (it flows back into the gate5). The reverse-flowing gate current I1causes the integrator output voltage U3to rise. Approximately 106 μs after the start of the simulation, the Miller capacitance of the semiconductor switch3is fully charged, the gate current I1is 0 A again and the integrator output voltage U3and the collector voltage U2each assume constant values. However, the control signal U4rises further. Approximately 110 μs after the start of the simulation, the first electrode C2_1of the timer element capacitor C2reaches a voltage at which the first comparator diode D1and the base-emitter path of the npn-bipolar transistor Q3become conductive. Finally, the thyristor structure formed by the npn-bipolar transistor Q3and the pnp-bipolar transistor Q4is switched off via the first comparator diode D1and the semiconductor switch3. Here, the Zener voltage of the first comparator diode D1defines the reference charge. The third comparator resistor R7of the circuit arrangement1shown inFIG.2causes the semiconductor switch3to be switched off in a lasting manner. If the third comparator resistor R7is removed, the semiconductor switch3is switched off for only one clock cycle of the gate driver7. FIG.4shows a block circuit diagram of a second exemplary embodiment of a circuit arrangement1according to the invention. The circuit arrangement1of this exemplary embodiment differs from the circuit arrangement1shown inFIG.1in that it has no timer element17, but rather has a reference charge circuit18. According to a second variant of the method according to the invention, a gate charge of the gate5is detected by the integrator15, with the reference charge circuit18, a reference charge is increased after a switching-on of the semiconductor switch3during a rise time from zero to an end value and the semiconductor switch3is switched off with the comparator unit19when the gate charge falls below the reference charge. The rise time is selected such that, during the minimum duration, a gate capacitance and a Miller capacitance of the semiconductor switch are recharged at least approximately completely, for example to at least 90%, after the elapse of the rise time after a switching of the semiconductor switch3into a normal operating mode. The semiconductor switch3is switched off by the comparator unit19for one clock cycle of the gate driver7. FIG.5shows a circuit diagram of a circuit arrangement1according to the second exemplary embodiment. The gate driver7and the integrator15are configured as in the circuit arrangement1shown inFIG.2. The integrator15detects the gate charge via a voltage drop across a measuring resistor R5. The measuring resistor R5is connected to the emitter of the semiconductor switch3. The gate driver7is connected to the gate5of the semiconductor switch3via a gate resistor R2. In an alternative embodiment of the circuit arrangement1, the measuring resistor R5can be dispensed with and the voltage for the integrator15can be tapped off at the gate resistor R2(see also the comments in the description regardingFIG.2). The comparator unit19has a comparator operational amplifier O2and a comparator diode D4. The reference charge circuit18has a reference charge capacitor C4, a reference charge resistor R9, and a first reference charge diode D5and a second reference charge diode D6, which is a Z-diode. The positive input of the comparator operational amplifier O2is connected to the output of the integrator15. The negative input of the comparator operational amplifier O2is connected to a first terminal R9_1of the reference charge resistor R9, a first electrode C4_1of the reference charge capacitor C4and the anode of the first reference charge diode D5. The output of the comparator operational amplifier O2is connected to the cathode of the comparator diode D4. The cathode of the first reference charge diode D5is connected to the cathode of the second reference charge diode D6. The anode of the second reference charge diode D6is connected to the input of the integrator15. Furthermore, the anode of the first reference charge diode D5is connected via a series connection from the resetting diodes D7, D8, D9to the positive terminal of the driver voltage source V3. The second terminal R9_2of the reference charge resistor R9is connected to the switch-on potential, that is, the positive terminal of the switch-on voltage source V1. The second electrode C4_2of the reference charge capacitor C4is connected to the switch-off potential, that is, to the negative terminal of the switch-off voltage source V2. The anode of the comparator diode D4is connected to a control input13of the electronic switching unit11. In the circuit arrangement1shown inFIG.5, in contrast to the exemplary embodiment shown inFIG.2, the integrator15does not function in a negating manner. The reference charge resistor R9and the reference charge capacitor C4set the rise time within which the reference charge rises after the switching-on of the semiconductor switch3to its final value. The final value is reached when the voltage on the reference charge capacitor C4reaches the sum of the forward voltage of the first reference charge diode D5and the Zener voltage of the second reference charge diode D6. After reaching the final value, the voltage on the reference charge capacitor C4remains constant. After the switching-on of the semiconductor switch3, the gate charge of the gate5, which is measured with the integrator15and is compared with the reference charge by means of the comparator operational amplifier O2, rises. In fault-free operation of the semiconductor switch3, the gate charge is always higher than the reference charge. In the event of a fault, the gate charge falls below the reference charge and the semiconductor switch3is switched off by the comparator unit19. The reset diodes D7, D8, D9serve for rapid resetting of the reference charge after a switching-off of the semiconductor switch3. FIG.6shows temporal variations of currents I1, I2and voltages U1to U3, U5, U6of the circuit arrangement1shown inFIG.5, in the case that the semiconductor switch3reaches its desaturation limit after the switching-on. The variations were generated with a simulation in which the semiconductor switch3is connected, as shown inFIG.2, to a second semiconductor switch4to form a half-bridge and a load connected to the half-bridge was simulated by inductances L1, L2and a load voltage source V4. The simulation was carried out for a measuring resistor R5of 6.8Ω, a driver resistor R3of 1 kΩ, a gate resistor R2of 6.8Ω an integrator capacitor C1with a capacitance of 100 pF, an integrator resistor R4of 1.5 kΩ, a reference charge capacitor C4with a capacitance of 620 pF, a reference charge resistor R9of 4.7 kΩ, a load inductance L1of 15 μH, a leakage inductance L2of 150 nH, a switch-on voltage source V1von 15 V, a switch-off voltage source V2of 8 V, and a load voltage source V4of 600 V. Approximately 100 μs after the start of the simulation, the semiconductor switch3is switched on. Thereupon, the gate-emitter voltage U1rises, the gate current I1rises briefly, a collector current I2of the semiconductor switch3rises and the collector voltage U2of the semiconductor switch3falls rapidly to approximately 0 V. At the same time, the integrator output voltage U3at the output of the non-negating integrator operational amplifier O1and a reference voltage U5applied to the negative input of the comparator operational amplifier O2, which is a measure for the reference charge, rise, wherein the integrator output voltage U3is greater than the reference voltage U5since the gate charge is greater than the reference charge. Approximately 104.5 μs after the start of the simulation, the semiconductor switch3again reaches its desaturation limit and the collector voltage U2rises again (initially only slowly). Thereupon, the Miller capacitance of the semiconductor switch3begins to charge up and the gate current I1begins to flow in the opposite direction (it flows back into the gate5). The reverse-flowing gate current I1causes the integrator output voltage U3to fall. Approximately 105 μs after the beginning of the simulation, the integrator output voltage U3falls below the reference voltage U5, since the gate charge falls below the reference charge. This is detected by the comparator operational amplifier O2and a comparator output voltage U6at the output of the comparator operational amplifier O2falls to the switch-off voltage of −8 V, whereby the semiconductor switch3is switched off. As distinct from the simulation shown inFIG.3, in this case a desaturation of the semiconductor switch3does not take place since no minimum duration is waited before the switching-off of the semiconductor switch3, so that the semiconductor switch3is switched off faster. FIG.7shows temporal variations of the currents I1, I2and the voltages U1to U3, U5, U6of the circuit arrangement1shown inFIG.5, whereby these variations have been carried out with a simulation for a load inductance L1of 0.5 μH, whereas all further parameters of the simulation have been selected as in the simulation shown inFIG.6. As distinct from the simulation shown inFIG.6, in this case, the collector voltage U2does not reach the saturation level and the Miller capacitance of the semiconductor switch3is barely charged. The gate charge and the integrator output voltage U3therefore rise after the switching-on of the semiconductor switch3to less high values than in the simulation shown inFIG.6, so that the integrator output voltage U3falls below the reference voltage U5sooner and the comparator19then switches off the semiconductor switch3. The collector current I2lasts less than 2 μs (approximately 1.7 μs). This shows that the second exemplary embodiment shown inFIG.5of a protection circuit9according to the invention can bring about a very rapid switching-off of a semiconductor switch3with a small load inductance L1. FIG.8shows a block circuit diagram of a third exemplary embodiment of a circuit arrangement1according to the invention. This exemplary embodiment differs from the exemplary embodiment shown inFIG.4only in that the protection circuit9has two P-elements21,23for compensation of an input offset voltage of the integrator15. A first P-element21is connected between the output and the negative input of the integrator15. The second P-element23is connected between the positive input of the integrator15and the control input13of the electronic switching unit11of the gate driver7. The P-elements21,23prevent an input offset voltage at an input of the integrator operational amplifier O1leading to an undesirable drifting of the output voltage of the integrator operational amplifier O1. The P-elements21,23are dimensioned so that the input offset voltage is compensated for and the drift of the output voltage maintains a sufficient margin from a supply voltage of the integrator operational amplifier O1to ensure its reliable functioning. The first P-element21provides, with an inverted feedback of the integrator output signal to the input of the integrator15, that the integrator15cannot enter into the boundary. The amplification of the integrator output signal by the first P-element21is kept so low by a high-ohmic resistor that an error is slowly balanced out. This feedback alone would cause the integrator15to return slowly back to zero. In order to prevent this, the driver signal is provided at the control input13of the electronic switching unit11of the gate driver7also with a low amplification of the second P-element23in a non-inverting manner to the input of the integrator15. The integrator15is thus forced to pause for the switching-on and switching-off to predefined values with a long integration constant in each case. An input-offset voltage of the integrator operational amplifier O1displaces these values to a certain level provided the first P-element21permits this. The integration constant of the integrator15is selected so that each complete recharging of the gate5causes the output of the integrator15to “jump” alternatingly exactly to these two predefined values. Rapid processes such as the desaturation of the semiconductor switch3are not compensated for by the P-elements21,23and are processed faithfully. Summarizing, an input-offset voltage of the integrator operational amplifier O1is compensated for by the P-elements21,23with a tolerable residual deviation, while rapid processes such as the recharging of the gate5or the desaturation of the semiconductor switch3are not affected by the compensation. FIG.9shows a circuit diagram of a circuit arrangement1according to the third exemplary embodiment. The circuit arrangement1differs from the circuit arrangement1shown inFIG.5only by three P-element resistors R10, R11, R12. A first P-element resistor R10is connected between the output and the negative input of the integrator operational amplifier O1. A second P-element resistor R11is connected between the positive input of the integrator operational amplifier O1and the control input13of the electronic switching unit11of the gate driver7. The third P-element resistor R12is connected between the emitter of the semiconductor switch3and the positive input of the integrator operational amplifier O1. The first P-element resistor R10has, for example, a resistance value of approximately 2000 kΩ, the second P-element resistor R11has, for example, a resistance value of approximately 300 kΩ, the third P-element resistor R12has, for example, a resistance value of approximately 100Ω. The first P-element resistor R10and the integrator resistor R4form the first P-element21, the second P-element resistor R11and the third P-element resistor R12form the second P-element23(seeFIG.8). All the exemplary embodiments shown inFIGS.1to9of a circuit arrangement1according to the invention can similarly also be configured with a MOSFET rather than an IGBT as the semiconductor switch3and/or with a differently configured gate driver7, for example, a gate driver7the electronic switching unit11of which has an output stage with a complementary output stage MOSFET rather than a push-pull output stage with output stage bipolar transistors Q1, Q2. Although the invention has been illustrated and described in detail on the basis of preferred exemplary embodiments, the invention is not restricted by the examples given and other variations can be derived therefrom by a person skilled in the art without departing from the protective scope of the invention. | 22,945 |
11942927 | DETAILED DESCRIPTION FIG.1shows, schematically, the method for short-circuit detection by saturation detection in power semiconductor switches. The method comprises the step of providing1a reference voltage Uref, generating2a differential voltage Udiff, comparing3the generated differential voltage Udiffwith a predetermined limit voltage Ulim, opening4the power semiconductor switch and optionally preventing5charging of an input filter. The steps of the method can take place in any desired sequence and/or at least partially at the same time. In the step of providing1the reference voltage Uref, the reference voltage is provided depending on the supply voltage UVDDof the power semiconductor switch. The reference voltage Urefin this case follows changes in the supply voltage UVDD. For this purpose, the reference voltage Urefis provided or tapped off between a Zener diode and a parallel circuit comprising a first resistor and a first capacitor. The Zener diode is electrically connected to the supply current source for the power semiconductor switch. The parallel circuit comprising the first resistor and the first capacitor is electrically connected to ground GND. The supply current source provides current with a supply voltage UVDDof 18 V. Uref˜UVDD In the step of generating2the differential voltage Udiff, the differential voltage Udiffcorresponds to a difference between a voltage drop UΔacross a load path of the power semiconductor switch and the provided reference voltage Uref. Udiff=U66−Uref The voltage drop UΔacross the load path of the power semiconductor switch is tapped off at an anode of at least one decoupling diode, which is electrically connected to a drain terminal or a collector terminal of the power semiconductor switch. The at least one decoupling diode is in this case fed the auxiliary current from a current source by means of a pull-up resistor. In the step of comparing3the generated differential voltage Udiffwith the predetermined limit voltage Ulim, the differential voltage Udiffis compared with the predetermined limit voltage Ulim. The limit voltage Ulimis in this case 10 V to 20 V. In this case, a short-circuit current is detected in the load path of the power semiconductor switch when the differential voltage Udiffreaches or exceeds the limit voltage Ulim. Udiff≥Ulim In the step of opening4the power semiconductor switch, the power semiconductor switch is opened when a short-circuit current has been detected in the load path of the power semiconductor switch. In addition, in the optional step of preventing5charging of the input filter, charging of the input filter by means of the pull-up resistor is prevented in the switched-off state. The input filter is connected electrically in parallel with the power semiconductor switch. By means of the pull-up resistor, the input filter could be charged in a switched-off state. This is prevented by a clamping transistor, which is connected electrically in parallel with the input filter. FIG.2shows, schematically, the device10for short-circuit detection (short-circuit detection circuit) by saturation detection in power semiconductor switches. The device10can implement the method fromFIG.1. The device10comprises the following components:a decoupling diode11to a drain terminal21(or alternatively to a collector terminal (not illustrated)) of the power semiconductor20;a current source12(in the form of a pull-up resistor, not illustrated);a reference voltage source13with dependence on a supply voltage UVDDof the power semiconductor20;a comparator circuit14;evaluation electronics15;a clamping transistor16; andoutput circuitry17. The decoupling diode11is electrically connected (with its anode) to the current source12and is also electrically connected, in the direction of flow, (with its cathode) to the drain terminal21of the power semiconductor switch20. The voltage drop UΔacross the load path of the power semiconductor switch20is tapped off at the anode of the decoupling diode11. The current source12in this case provides the auxiliary current from the supply voltage UVDDfor the decoupling diode11in order that the voltage drop UΔcan be measured or tapped off at the anode of the decoupling diode11. The reference voltage source13provides the reference voltage Uref. The reference voltage Ureffollows a supply voltage UVDDof the supply current source of the power semiconductor switch20. The decoupling diode11(with its anode) and the reference voltage source13are electrically connected to the comparator circuit14in such a way that the output of the comparator circuit14has the differential voltage Udiff, wherein the differential voltage Udiffcorresponds to the difference between the voltage drop UΔacross the load path of the power semiconductor switch20and the reference voltage Uref. The comparator circuit14is electrically connected with its output to the evaluation electronics15. The evaluation electronics15are in this case an integrated circuit (IC), which can implement the Desat method. In this case, the power semiconductor switch20is opened by the evaluation electronics/IC15when the differential voltage Udiffis equal to or greater than a predetermined limit voltage Ulim. In this case, the predetermined limit voltage Ulimis selected in such a way that there is a short circuit in the power semiconductor switch20when the differential voltage Udiffreaches or exceeds the predetermined limit voltage Ulim. The clamping transistor16is electrically connected to the output of the comparator circuit14and the current source12. In this case, the clamping transistor16prevents charging of an input filter of the device10by means of a pull-up resistor of the current source12in a switched-off state. In addition, output circuitry17is electrically connected to the output of the comparator circuit14. The output circuitry is connected to ground (GND). The functionality illustrated in the basic circuit diagram of the device10can also be implemented in a (single) integrated circuit (IC) or completely in a discrete (analog) circuit. FIG.3schematically illustrates a special embodiment of the device10fromFIG.2. Only differences or special configurations of the device10inFIG.3in relation to the device fromFIG.2will be explained. The decoupling diode11is electrically connected with its anode via a pull-up resistor19to the current source12(more precisely to a collector terminal of a first PNP transistor12.4of the current source12). The current source12comprises a second resistor12.1and a fourth resistor12.3, which are electrically connected to the supply current source of the power semiconductor20which provides the supply voltage UVDD. In addition, the current source comprises a third resistor12.2, which is connected electrically in series with the first resistor12.1. In addition, the current source12comprises the first PNP transistor12.4, wherein a bulk terminal of the first PNP transistor12.4is electrically connected between the first resistor12.1and the second resistor12.2, an emitter terminal of the first PNP transistor12.4is electrically connected to the third resistor12.3, and the collector terminal of the first PNP transistor12.4is electrically connected, via the pull-up resistor19, to the anode of the decoupling diode11. The collector terminal of the first PNP transistor12.4is additionally electrically connected to a third capacitor18, wherein the third capacitor18is additionally connected to ground (GND). The reference voltage source13comprises a Zener diode13.1and a parallel circuit comprising a first resistor13.2and a first capacitor13.3. The Zener diode is electrically connected (with its cathode) to the supply current source of the power semiconductor switch20. In addition, the Zener diode is electrically connected (with its anode) to the parallel circuit. The first resistor13.2and the first capacitor13.3of the parallel circuit are additionally connected to ground (GND). The Zener diode13.1is electrically connected with its anode additionally to the comparator circuit14(more precisely to an emitter terminal of an NPN transistor14.5and to an anode of a first diode14.6of the comparator circuit14). The comparator circuit14comprises a second PNP transistor14.1, which is electrically connected with its emitter terminal to the supply current source of the power semiconductor switch20, with its collector terminal to a fifth resistor14.2of the comparator circuit14and with its bulk terminal to a sixth resistor14.3of the comparator circuit14. In addition, the comparator circuit14comprises the first NPN transistor14.5, which is electrically connected with its collector terminal, via the sixth resistor14.3, to the bulk terminal of the second PNP transistor. In addition, the collector terminal of the first NPN transistor14.5is electrically connected, via a seventh resistor14.4of the comparator circuit14, to the supply current source of the power semiconductor switch20. The emitter terminal of the first NPN transistor14.5is electrically connected to the anode of the Zener diode13.1of the reference voltage source13, the anode of the first diode14.6of the comparator circuit14and the third resistor12.2of the current source12. A bulk terminal of the first NPN transistor14.5and a cathode of the first diode14.6are electrically connected to a cathode of a second diode14.8of the comparator circuit14and, via an eighth resistor14.7of the comparator circuit, to the collector terminal of the first PNP transistor12.4of the current source or additionally, via the pull-up resistor19, to the anode of the decoupling diode11. The collector terminal of the second PNP transistor is electrically connected, via the fifth resistor14.2, to the evaluation electronics15. The clamping transistor16is an n-channel insulated-gate field-effect transistor which is connected with its gate terminal to ground (GND), and which is electrically connected, on one side, with its source terminal and its gate terminal to the collector terminal of the second PNP transistor14.1of the comparator circuit14and the evaluation electronics15and, on the other side, with its drain terminal to the collector terminal of the first PNP transistor12.4of the current source12and, via the pull-up resistor19, to the anode of the decoupling diode11. The output circuitry17in this case comprises a parallel circuit comprising a ninth resistor17.1and a second capacitor17.2. The ninth resistor17.1and the capacitor are electrically connected on one side to ground (GND) and on the other side to the collector terminal of the second PNP transistor14.1via the fifth resistor14.2, the evaluation electronics15and the source terminal and gate terminal of the n-channel insulated-gate field-effect transistor16. Although specific embodiments have been illustrated and described here, it is clear to a person skilled in the art that there is a multiplicity of alternatives and/or equivalent implementations. It should be appreciated that the exemplary configurations or embodiments are merely examples and are not intended to restrict the scope, the applicability or the configuration in any way. Rather, the above summary and detailed description will provide a person skilled in the art with sufficient instructions for implementing at least one preferred embodiment, wherein it goes without saying that various changes to the function and arrangement of the elements which are described in an exemplary configuration do not result from the application field set forth in the attached claims and their legal equivalents. In general, this application is intended to cover all adaptations and variations of the specific embodiments discussed here. In the detailed description above, various features have been summarized in one or more examples in order to keep the disclosure concise. It goes without saying that the above description is intended to be illustrative and not restrictive. It is intended to cover all alternatives, amendments and equivalents which can be contained within the scope of the invention. Many other examples will become obvious to a person skilled in the art when studying the above disclosure. In order to enable comprehensive understanding of the invention, a specific nomenclature is used which has been used in the above disclosure. However, it will become apparent to a person skilled in the art in the light of the specification contained therein that the specific details are not required in order to apply the invention. Thus, the above descriptions of specific embodiments of the present invention are illustrated for illustrative and descriptive purposes. They are not intended to be exhaustive or to restrict the invention to the above-disclosed precise embodiments; many modifications and variations in respect of the abovementioned teachings are obviously possible. The embodiments have been selected and described in order to best clarify the principles of the invention and their practical applications and in order to therefore give others skilled in the art the possibility of best applying the invention and various embodiments with various modifications as appears suitable for the respective application. Throughout the specification, the terms “including” and “in the case of which” are used as equivalents of the respective terms “comprising” and “in which”. Furthermore, the terms “first”, “second”, “third” etc. are merely used as a designation and are not intended to place numerical demands on the objects or prescribe a specific sequence. In connection with the above description and the claims, the conjunction “or” should be understood to be inclusive (“and/or”) and not exclusive (“either . . . or”). | 13,725 |
11942928 | DETAILED DESCRIPTION Hereinafter, a semiconductor device, a power-on reset circuit, and a control method of a semiconductor device according to the present disclosure will be described in detail with reference to the drawings. In the following description, a mode in which a semiconductor device10according to the present embodiment is applied to the power-on reset circuit will be described as an example. First Embodiment The semiconductor device10according to the present embodiment will be described with reference toFIGS.1and2.FIG.1is a circuit diagram illustrating a circuit of the semiconductor device10together with peripheral circuits. As illustrated inFIG.1, the semiconductor device10includes a bias mirror circuit11, a first power supply voltage monitoring circuit12, a second power supply voltage monitoring circuit13, and an output circuit14. The bias mirror circuit11, the first power supply voltage monitoring circuit12, the second power supply voltage monitoring circuit13, and the output circuit14configure the power-on reset circuit. The semiconductor device10is connected between a power supply VDD having a predetermined power supply voltage and a power supply VSS having a power supply voltage lower than the power supply VDD.FIG.1illustrates a bias circuit20, a regulator21, and a reset target circuit22as the peripheral circuits. The bias circuit20is connected to a power supply VDD′ having a higher power supply voltage than the power supply VDD, and supplies a bias voltage to the semiconductor device10with a bias terminal15interposed therebetween. The regulator21generates a stabilized voltage <VDD> of the power supply VDD from a voltage <VDD′> of the power supply VDD′. The reset target circuit22is a circuit that is connected to the power supply VDD and is a target of a reset operation by a reset signal RESET output from the power-on reset circuit. The reset target circuit22may be included in the semiconductor device10. The “first power supply voltage monitoring circuit12” is an example of a “first power supply voltage monitoring circuit” according to the present disclosure, the “second power supply voltage monitoring circuit13” is an example of a “second power supply voltage monitoring circuit” according to the present disclosure, and a combination of the “first power supply voltage monitoring circuit12” and the “second power supply voltage monitoring circuit13” is an example of a “power supply voltage monitoring circuit” according to the present disclosure. The bias mirror circuit11includes a PMOS P1and an NMOS N1. A gate of the NMOS N1is connected to the bias circuit20with the bias terminal15interposed therebetween, the source is connected to the power supply VSS, and the drain is connected to the drain of the PMOS P1. The NMOS N1generates a constant current by mirroring the current by the bias voltage supplied from the bias circuit20with the bias terminal15interposed therebetween. Here, mirroring refers to, for example, causing a current having a current amount corresponding to a current amount of a current generated in a circuit or an element that supplies a current or a voltage to flow in a circuit or an element thereof such that the NMOS N1causes a current having a current amount corresponding to the current amount generated in the bias circuit20to flow. The PMOS P1transmits the current flowing through the NMOS N1to a PMOS P3and a PMOS P4at a subsequent stage. The “bias mirror circuit11” is an example of a “current mirror circuit” according to the present disclosure. The first power supply voltage monitoring circuit12includes an NMOS N2and a PMOS P2. A gate of the NMOS N2is connected to a bias terminal15, a source is connected to the power supply VSS, and a drain is connected to a node node1. The NMOS N2generates a constant current by mirroring the current by the bias voltage supplied from the bias circuit20. A source of the PMOS P2is connected to the power supply VDD, and a gate and a drain are connected to the node node1. That is, the PMOS P2is diode-connected. The first power supply voltage monitoring circuit12is a circuit that monitors the voltage of the power supply VDD. Here, monitoring the voltage of the power supply VDD means operating in accordance with a rise of the voltage of the power supply VDD. The second power supply voltage monitoring circuit13includes an NMOS N3and a PMOS P3. A gate of the NMOS N3is connected to the node node1, a source is connected to the power supply VSS, and a drain is connected to a node node2. A gate of the PMOS P3is connected to the gate of the PMOS P1, a source is connected to the power supply VDD, and a drain is connected to the node node2. The PMOS P3mirrors the current flowing through the NMOS N1with the PMOS P1interposed therebetween to generate a constant current. The second power supply voltage monitoring circuit13is a circuit that monitors the voltage of the power supply VDD. Here, monitoring the voltage of the power supply VDD means operating in accordance with a rise of the voltage of the power supply VDD. The output circuit14includes an NMOS N4, a PMOS P4, and an inverter INV. A gate of the NMOS N4is connected to the node node2, a source is connected to the power supply VSS, and a drain is connected to a node node3. A gate of the PMOS P4is connected to the gate of the PMOS P1, a source is connected to the power supply VDD, and a drain is connected to the node node3. The PMOS P4mirrors the current flowing through the NMOS N1with the PMOS P1interposed therebetween to generate a constant current. An input of the inverter INV is connected to the node node3, and an output is connected to an output terminal16. The output terminal16is connected to the reset target circuit22. The inverter INV forms a waveform of a voltage generated in the node node3and functions as an output buffer when the reset signal RESET is output to the output terminal16. Here, in the semiconductor device10according to the present embodiment, the NMOS N4, the PMOS P4, and the inverter INV are provided for waveform forming and the output buffer. Accordingly, the configuration is not essential, and can be omitted as long as the waveform or the like are decent. Next, an operation of the semiconductor device10will be described with reference toFIG.2.FIG.2is a diagram illustrating a time chart according to the operation of the semiconductor device10. InFIG.2, changes in waveforms of the power supply VDD, the node node1, the node node2, the node node3, and the reset signal RESET when the power supply VDD is turned on are illustrated along the passage of time t. Here, a time when the voltage is applied to the power supply VDD of the semiconductor device10is defined as time t0. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, while the voltage <VDD> is less than a threshold voltage Vtp2of the PMOS P2, a gate voltage Vgs of the PMOS P2is still low, and the PMOS P2is turned off. At this time, since the NMOS N2is turned on, a potential of the node node1is identical to a potential of the power supply VSS. At time t1when the voltage <VDD> reaches the threshold voltage Vtp2of the PMOS P2, the gate voltage Vgs of the PMOS P2becomes higher than the threshold voltage Vtp2of the PMOS P2, and the PMOS P2is turned on. As a result, when the time reaches time t1, the potential of the node node1becomes <VDD−Vtp2>. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, the NMOS N3is turned off until the power supply VDD gives a gate voltage Vgs sufficient to turn on the NMOS N3. During this time, since the PMOS P3is turned on, a potential of the node node2is a potential of the power supply VDD. At time t1, since the voltage <VDD> of the power supply VDD is higher than the threshold voltage Vtp2of the PMOS P2but the potential of the node node1is <VDD−Vtp2>, the NMOS N3remains off. When the voltage <VDD> further increases and a threshold voltage of the NMOS N3is Vtn3, a gate voltage Vgs of the NMOS N3becomes higher than the threshold voltage Vtn3of the NMOS N3at time t2when the voltage <VDD> reaches (Vtp2+Vtn3), and the NMOS N3is turned on. Accordingly, when the time reaches time t2, the potential of the node node2becomes identical to the potential of the power supply VSS. As a result, a pulsed waveform as illustrated inFIG.2is generated in the node node2. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, a gate voltage Vgs of the NMOS N4is still low and the NMOS N4is turned off and the PMOS P4is turned on until time t1. Thus, a potential of the node node3is identical to the potential of the power supply VDD. When the gate voltage Vgs of the NMOS N4becomes higher than a threshold voltage Vtn4and the NMOS N4is turned on at a point in time when the voltage <VDD> reaches the threshold voltage Vtn4of the NMOS N4, the potential of the node node3becomes identical to the potential of the power supply VSS. At time t2when the voltage <VDD> reaches (Vtp2+Vtn3), since the NMOS N4is turned on, the node node3is disconnected from the power supply VSS, and the potential of the node node3becomes identical to the potential of the power supply VDD. Here, for ease of understanding, the threshold voltages of the PMOSs P1to P4and the threshold voltages of the NMOSs N1to N4are equal to each other. The reset signal RESET has a waveform obtained by inverting the waveform generated in the node node3by the inverter INV. By a threshold of the inverter INV, the reset signal RESET configures a reset pulse that rises from time t1and falls at time t2. The reset target circuit22receives the reset pulse and executes a reset operation. That is, the reset signal RESET is a reset execution signal that causes the reset operation of the reset target circuit22to be executed in a period from time t1to time t2, and is a reset cancellation signal that causes the reset operation of the reset target circuit22to be canceled after time t2. That is, the reset signal RESET is a reset execution signal when the voltage <VDD> of the power supply VDD is less than the sum of the threshold voltage Vtp2of the PMOS P2and the threshold voltage Vtn3of the NMOS N3, and is a reset cancellation signal when the voltage <VDD> of the power supply VDD is equal to or greater than the sum of the threshold voltage Vtp2of the PMOS P2and the threshold voltage Vtn3of the NMOS N3. Here, as described above, in order for the reset target circuit to reliably execute the reset operation by the power-on reset circuit, the voltage <VDD> of the power supply VDD needs to be a voltage at which the reset operation can be reliably performed in the reset target circuit in a period in which the reset execution signal is output. In this regard, in the semiconductor device10according to the present embodiment, the reset signal is switched not at time t1when the voltage <VDD> reaches the threshold voltage Vtp2of the PMOS P2but at time t2when the increase in the voltage <VDD> further reaches the threshold voltage Vtn3of the NMOS N3from time t1, that is, the reset execution signal is switched to the reset cancellation signal. That is, in the semiconductor device10, a cancellation execution voltage is determined not only by the threshold voltage Vtp2of the PMOS P2but also by (Vtp2+Vtn3) that is the sum of the threshold voltage Vtp2of the PMOS P2and the threshold voltage Vtn3of the NMOS N3. Thus, the cancellation execution voltage of the semiconductor device10according to the present embodiment can be set to be higher than a cancellation execution voltage of the power-on reset circuit50according to a comparative example, and when the reset cancellation signal is output, it is possible to prevent the reset target circuit22from not yet executing a sufficient reset operation. As described above, in accordance with the semiconductor device10according to the present embodiment, the reset signal is switched, that is, the reset execution signal is switched to the reset cancellation signal at a point in time when the voltage of the power supply VDD becomes (Vptp2+Vtn3), that is, at a point in time when the voltage becomes (threshold voltage of NMOS+threshold voltage of PMOS). In a semiconductor device50, the reset cancellation signal is output when the voltage of the power supply VDD reaches the threshold voltage of the PMOS P1. Meanwhile, in the semiconductor device10, the voltage <VDD> of the power supply VDD at the time of power-on reset, that is, the cancellation execution voltage can be raised to a voltage at which the reset operation can be executed more reliably in the reset target circuit22. As a result, in accordance with the semiconductor device10according to the present embodiment, it is possible to provide a semiconductor device that realizes a power-on reset circuit that more reliably exhibits a function, and a control method of a semiconductor device. When the power-on reset circuit and the reset target circuit are mounted in the same semiconductor device, the semiconductor device10according to the present embodiment can obtain the following effects. That is, as described above, in accordance with the semiconductor device10of the present embodiment, a timing, when a signal for canceling the reset operation is output, is determined not only by the threshold voltage Vtp of the PMOS but also by the threshold voltage Vtp of the PMOS and the threshold voltage Vtn of the NMOS. Even when, for example, the threshold voltage Vtn of the NMOS fluctuates due to manufacturing variation in manufacturing of the semiconductor device and a cancellation specified voltage of the reset target circuit becomes high, since the cancellation execution voltage of the semiconductor device10according to the present embodiment also includes the threshold voltage Vtn of the NMOS, it is possible to follow the fluctuation of the cancellation specified voltage of the reset target circuit. As a result, the semiconductor device10, a power-on reset circuit and a control method of a semiconductor device of the present embodiment may more reliably exhibit the power-on reset function. Second Embodiment A semiconductor device30according to the present embodiment will be described with reference toFIGS.3and4.FIG.3is a circuit diagram illustrating a circuit of the semiconductor device30together with peripheral circuits. As illustrated inFIG.3, the semiconductor device30includes a bias mirror circuit31, a first power supply voltage monitoring circuit32, a second power supply voltage monitoring circuit33, and an output circuit34. The bias mirror circuit31, the first power supply voltage monitoring circuit32, the second power supply voltage monitoring circuit33, and the output circuit34configure a power-on reset circuit. The semiconductor device30is connected between a power supply VDD having a predetermined power supply voltage and a power supply VSS having a power supply voltage lower than the power supply VDD. Similarly to the semiconductor device10according to the first embodiment, the semiconductor device30according to the present embodiment also includes a bias circuit20, a regulator21, and a reset target circuit22as the peripheral circuits, but the illustration and description thereof are omitted inFIG.3. As in the first embodiment, the “first power supply voltage monitoring circuit32” is an example of a “first power supply voltage monitoring circuit” according to the present disclosure, the “second power supply voltage monitoring circuit33” is an example of a “second power supply voltage monitoring circuit” according to the present disclosure, and a combination of the “first power supply voltage monitoring circuit32” and the “second power supply voltage monitoring circuit33” is an example of a “power supply voltage monitoring circuit” according to the present disclosure. The bias mirror circuit31includes a PMOS P1and an NMOS N1. A gate of the PMOS P1is connected to a bias circuit20(not illustrated) with a bias terminal15interposed therebetween, a source thereof is connected to the power supply VDD, and a drain thereof is connected to a drain of the NMOS N1. The PMOS P1mirrors a current by a bias voltage supplied from the bias circuit20(not illustrated) with the bias terminal15interposed therebetween to generate a constant current. Here, mirroring refers to, for example, causing a current having a current amount corresponding to a current amount of a current generated in a circuit or an element that supplies a current or a voltage to flow in a circuit or an element thereof, such that the PMOS P1causes a current having a current amount corresponding to the current amount generated in the bias circuit20, to flow. The NMOS N1transmits the current flowing through the PMOS P1to an NMOS N3at a subsequent stage. The “bias mirror circuit31” is an example of a “current mirror circuit” according to the present disclosure. The first power supply voltage monitoring circuit32includes an NMOS N2and a PMOS P2. A gate of the PMOS P2is connected to the gate of the PMOS P1, a source is connected to the power supply VDD, and a drain is connected to a node node1. The PMOS P2mirrors the current flowing through the PMOS P1to generate a constant current. A source of the NMOS N2is connected to the power supply VSS, and a gate and a drain are connected to the node node1. That is, the NMOS N2is diode-connected. The first power supply voltage monitoring circuit32is a circuit that monitors a voltage of the power supply VDD. Here, monitoring the voltage of the power supply VDD means operating in accordance with a rise of the voltage of the power supply VDD. The second power supply voltage monitoring circuit33includes an NMOS N3and a PMOS P3. A gate of the PMOS P3is connected to the node node1, a source is connected to the power supply VDD, and a drain is connected to a node node2. A gate of the NMOS N3is connected to a gate of the NMOS N1, a source is connected to the power supply VSS, and a drain is connected to the node node2. The NMOS N3mirrors the current flowing through the NMOS N1to generate a constant current. The second power supply voltage monitoring circuit33is a circuit that monitors the voltage of the power supply VDD. Here, monitoring the voltage of the power supply VDD means operating in accordance with a rise of the voltage of the power supply VDD. The output circuit14includes an NMOS N4, a PMOS P4, and a buffer BUFF. A gate of the NMOS N4is connected to the node node2, a source is connected to the power supply VSS, and a drain is connected to a node node3. A gate of the PMOS P4is connected to the gate of the PMOS P1, a source is connected to the power supply VDD, and a drain is connected to the node node3. The PMOS P4mirrors the current flowing through the PMOS P1to generate a constant current. An input of the buffer BUFF is connected to a node node3, and an output is connected to an output terminal16. The output terminal16is connected to the reset target circuit22(not illustrated). The buffer BUFF forms a waveform of a voltage generated in the node node3and functions as an output buffer when a reset signal RESET is output to the output terminal16. Here, similarly to the semiconductor device10, in the semiconductor device30according to the present embodiment, the NMOS N4, the PMOS P4, and the buffer BUFF are provided for waveform forming and the output buffer. Accordingly, the configuration is not essential, and may be omitted as long as the waveform or the like are decent. Next, an operation of the semiconductor device30will be described with reference toFIG.4.FIG.4is a diagram illustrating a time chart according to the operation of the semiconductor device30. InFIG.4, changes in the waveforms of the power supply VDD, the node node1, the node node2, the node node3, and the reset signal RESET when the power supply VDD is turned on are illustrated along the passage of time t. A time when the voltage is applied to the power supply VDD of the semiconductor device30is defined as time t0. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, while the voltage <VDD> is less than a threshold voltage Vtn2of the NMOS N2, a gate voltage Vgs of the NMOS N2is still low, and the NMOS N2is turned off. At this time, since the PMOS P2is turned on, a potential of the node node1is identical to a potential of the power supply VDD. At time t1when the voltage <VDD> reaches the threshold voltage Vtn2of the NMOS N2, the gate voltage Vgs of the NMOS N2becomes higher than the threshold voltage Vtn2of the NMOS N2, and the NMOS N2is turned on. As a result, when the time reaches time t1, the potential of the node node1becomes <Vtn2>. Since the NMOS N2is diode-connected, the potential of the node node1becomes constant at <Vtn2> after time t1. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, the PMOS P3is turned off until the power supply VDD gives a gate voltage Vgs sufficient to turn on the PMOS P3. During this time, since the NMOS N3is turned on, a potential of the node node2is the potential of the power supply VSS. When the voltage <VDD> further increases and a threshold voltage of the PMOS P3is Vtp3, a gate voltage Vgs of the PMOS P3becomes higher than the threshold voltage Vtp3of the PMOS P3at time t2when the voltage <VDD> reaches (Vtn2+Vtp3), and the PMOS P3is turned on. Accordingly, when the time reaches time t2, the potential of the node node2becomes identical to the potential of the power supply VDD. As a result, a stepwise waveform illustrated inFIG.4is generated in the node node2. In a procedure in which the voltage <VDD> of the power supply VDD increases from time t0, a gate voltage Vgs of the NMOS N4is still low and the NMOS N4is turned off and the PMOS P4is turned on until time t2. Thus, a potential of the node node3is identical to the potential of the power supply VDD. The voltage <VDD> further increases, the PMOS P3is turned on, and the NMOS N4is turned on at time t2when the potential of the node node2becomes identical to the potential of the power supply VDD. As a result, the potential of the node node3becomes identical to the potential of the power supply VSS. Here, for ease of understanding, the threshold voltages of the PMOSs P1to P4and the threshold voltages of the NMOSs N1to N4are equal to each other. The reset signal RESET configures a reset pulse that rises from time t0and is canceled at time t2. The reset target circuit22(not illustrated) receives the reset pulse and performs a reset operation. Note that the reset signal RESET is a reset execution signal that causes the reset operation of the reset target circuit22to be executed in a period from time t0to time t2, and is a reset cancellation signal that causes the reset operation of the reset target circuit22to be canceled after time t2. That is, the reset signal RESET is a reset execution signal when the voltage <VDD> of the power supply VDD is less than the sum of the threshold voltage Vtn2of the NMOS N2and the threshold voltage Vtp3of the PMOS P3, and is a reset cancellation signal when the voltage <VDD> of the power supply VDD is equal to or greater than the sum of the threshold voltage Vtn2of the NMOS N2and the threshold voltage Vtp3of the PMOS P3. Here, as described above, in order for the reset target circuit to reliably execute the reset operation by the power-on reset circuit, the voltage <VDD> of the power supply VDD needs to be a voltage at which the reset operation can be reliably performed in the reset target circuit in a period in which the reset execution signal is output. In this regard, in the semiconductor device30according to the present embodiment, the reset signal is switched not at time t1when the voltage <VDD> reaches the threshold voltage Vtn2of the NMOS N2but at time t2when the voltage <VDD> reaches the threshold voltage Vtp3of the PMOS P3in addition to Vtn2, that is, the reset execution signal is switched to the reset cancellation signal. That is, in the semiconductor device30, a cancellation execution voltage is determined not only by the threshold voltage Vtn2of the NMOS N2but also by (Vtn2+Vtp3) that is the sum of the threshold voltage Vtn2of the NMOS N2and the threshold voltage Vtp3of the PMOS P3. Thus, the cancellation execution voltage of the semiconductor device30according to the present embodiment can be made higher than the cancellation execution voltage of the power-on reset circuit50according to the comparative example, and when the reset cancellation signal is output, it is possible to prevent the reset target circuit22from not yet executing a sufficient reset operation. As described above, in accordance with the semiconductor device30according to the present embodiment, the reset execution signal is switched to the reset cancellation signal at a point in time when the voltage of the power supply VDD becomes (Vptn2+Vtp3), that is, at a point in time when the voltage becomes (threshold voltage of NMOS+threshold voltage of PMOS). In the semiconductor device50, the reset cancellation signal is output when the voltage of the power supply VDD reaches the threshold voltage of the PMOS P1, Meanwhile, in the semiconductor device30, the voltage <VDD> of the power supply VDD at the time of power-on reset, that is, the cancellation execution voltage can be raised to a voltage at which the reset operation can be executed more reliably in the reset target circuit22. As a result, in accordance with the semiconductor device30according to the present embodiment, it is possible to provide a semiconductor device that realizes a power-on reset circuit that more reliably exhibits a function, and a control method of a semiconductor device. When the power-on reset circuit and the reset target circuit22are mounted in the same semiconductor device, the semiconductor device30according to the present embodiment can obtain the following effects. In accordance with the semiconductor device30according to the present embodiment, a timing when a signal for canceling the reset operation is output is determined not only by the threshold voltage Vtn of the NMOS but also by the threshold voltage Vtn of the NMOS and the threshold voltage Vtp of the PMOS. Even when, for example, the threshold voltage Vtp of the PMOS fluctuates due to manufacturing variation in manufacturing of the semiconductor device and a cancellation specified voltage of the reset target circuit becomes high, since the cancellation execution voltage of the semiconductor device30according to the present embodiment also includes the threshold voltage Vtp of the PMOS, it is possible to follow the fluctuation of the cancellation specified voltage of the reset target circuit. As a result, the semiconductor device30, a power-on reset circuit, and a control method of a semiconductor device according to the present embodiment, may more reliably exhibit the power-on reset function. In each of the embodiments, although the operation at the time of power-on has been described, the semiconductor device according to each of the above embodiments can perform the reset operation even at the time of power-off. Accordingly, even when an instantaneous interruption occurs in the power supply VDD, it is possible to temporarily reset the reset target circuit. | 27,372 |
11942929 | Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION FIG.1Bshows two different electrical pulse profiles, in accordance with the present disclosure, for switching the resistivity states of the PCM (102) ofFIG.1A. Such electrical pulse profiles are applied to the heater (101) ofFIG.1Ato generate different thermal profiles that result either in amorphizing the PCM (102) ofFIG.1Ainto a high resistance state (OFF or open) using a higher-power, short-period pulse (110), or crystalizing the PCM (102) into a low resistance state (ON or closed) using a lower-power, long-period pulse (120). Pulses (110,120) may typically have pulse widths of 100 nsec and 1 usec respectively. FIG.2shows an exemplary driving arrangement for a PCM switch (200) according to an embodiment of the present disclosure. The driving arrangement comprises a volume of PCM (202) a heater (201), a first driver (230), a second driver (230′), a logic and timing circuit (220), serial interface (240), and power supply module (210). For the purposes of the present disclosure, elements (201) and (202) will be collectively defined as PCM switch. As mentioned previously, different power profiles are implemented to drive a PCM switch. A pulse with a higher power and shorter pulse-width is implemented to put the PCM switch into the OFF state, while a different pulse with a lower power and longer pulse-width is implemented to turn the PCM switch into the ON state. Drivers (230,230′) are used to drive heater (201) to turn PCM switch (201,202) into the OFF/ON states respectively. As such, a higher bias voltage (VH) is provided to driver (230) by power supply module (210), while a lower bias voltage (VL) is provided to driver (230′) by power supply module (210). In an embodiment, a single driver, instead of two, may be implemented to generate the pulse waveforms for both the ON and OFF state of the PCM switch (201,202). According to the teachings of the present disclosure, the widths of the pulses at the output of drives (230,230′) to drive heater (201) can be programmable. In an embodiment all the constituents of the driving arrangement (200) are integrated on the same chip, as shown by the exemplary dotted box (250). With further reference toFIG.2, the logic and timing circuit (220) provides logic level pulses in correspondence with the state of the PCM switch (201,202). Logic and timing circuit (220) receives digital reference clock input (REF_CLK) and digital control input (SW_IN), which are used to control the ON or OFF state of PCM switch (201,202). In other words, based on the state of control input (SW_IN) and using digital reference clock input (REF_CLK), power profiles with proper amplitudes and widths in correspondence with the desired state of the PCM (202) are generated and fed to heater (201). As a result, PCM switch (021,202) is transitioned between the ON and OFF states based on digital control input (SW_IN). With continued reference toFIG.2, power supply module (210) provides also the bias voltage (VDD) for logic and timing circuit (220). Switching arrangement (200) further comprises serial interface (240) connected to logic and timing circuit (220). Serial interface (240) includes an input (S_IN) and may be implemented using a serial peripheral interface (SPI) standard, a mobile industry processor interface (MIPI) standard or alike. The input control signal may also come from the serial interface. FIG.3Ashows an exemplary PCM switch driver (300A) representing an implementation of any of drivers (230,230′) ofFIG.2according to an embodiment of the present disclosure. Driver (300A) comprises a first driver switch stack (303) including transistors (T3, T5), and a second driver switch stack (304) including transistors (T4, T6). Driver switch stacks (303,304) are each arranged in series with corresponding load device transistors (T1, T2), respectively. Also shown, is an output transistor (T7) delivering the voltage and current required by a downstream heater (e.g., heater (201) ofFIG.2) at output terminal (OUT). Driver (300A) further includes a serial arrangement of logic inverters (301,302) receiving the control input (SW_IN). The logic inverters (301,302) operate with bias voltage (VDD) and drive transistors (T5, T6) respectively. Bias voltage (VH) is also provided to the driver similarly to what was described with regards to the embodiment ofFIG.2. According to the teachings of the present disclosure, the stacked arrangement shown in the figure allows for improved voltage handling. If desired, the transistor stacking can be increased or reduced according to transistor voltage handling capability and output drive required. The voltage values shown inFIG.3Arepresent the case where the PCM switch driver (300A) is in an OFF state. No current is being sent to the heater. Exemplary values for bias voltages (VDD, VH) may be 2.5V, 5V respectively. Voltage levels at various points of the driver (300A) are shown based on such exemplary bias values. On the other hand,FIG.3Bshows the same driver as inFIG.3A, but this time with voltage values where the PCM switch driver is in the ON state. This is used to transition the PCM material to either the ON or OFF state depending on output amplitude and timing, as previously described. With reference toFIGS.3A-3B, transistors (T3, T4, T5, T6T7) may be NFETs and transistors (T1, T2) may be PFETs. Based on the exemplary bias voltages of (2.5V, 5V) for bias voltages (VDD, VH), the NFETs and PFETs may be each designed to handle a voltage of at least (2.5V, 5V) respectively. FIG.4represents exemplary timing diagrams related to the embodiment ofFIG.2. Signals (410,420,430) represent control input, heater current, and heater voltage vs. time respectively. Pulses (401,402,403) corresponds to the case where the PCM switch is driven or programmed to an OFF state while pulses (401′,402′,403′) represent the case where such switch is driven or programmed to an ON state. With reference toFIG.2, operation of the logic and timing module (220) may be described as a state machine.FIG.5shows an exemplary state diagram (500) according to an embodiment of the present disclosure. Referring to bothFIG.2andFIG.5, the PCM switch (201,202) ofFIG.2may be programmed (501) to be in an ON or OFF state based on the state (503) of digital control input (SW_IN). When the PCM switch (201,202) is transitioning to the ON state, first counter (502) will generate an ON pulse with a desired width to the driver (230) ofFIG.1, see alsoFIG.3A. The desired width may be implemented by counting the number of periods in a reference clock (clk) which is an input to the first counter (502). Similarly, when the PCM switch (201,202) is transitioning into the OFF state, second counter (502′) will generate an OFF pulse with a desired width to the driver (230′) ofFIG.1, see alsoFIG.3B. Also in this case, the width of the OFF pulse may be achieved by counting the number of clock periods in the reference clock (clk) which is an input to the second counter (502′). The control inputs to the first and second counters may have different values. As mentioned previously, pulses are needed to be applied to the heater to transition the PCM switch between one state and another. More in particular, higher power profiles need to be implemented when transitioning to the OFF state. This may be problematic when designing PCM switches arranged in a stack configuration for an improved voltage handling. In such stacks, each PCM requires its own separate heater to be programmed and changing the state of all the stacked PCMs at the same time may be taxing on the power supply. This imposes power supply design challenges for the applications using PCM switch stacks. According to the teachings of the present disclosure, changing the state of the PCM switches within the stack may be performed in a staggered fashion, so that not all the PCM switches are changing state at the same time. As an example, this can be performed one PCM device at a time or several PCM devices at a time. As a result, the peak current drawn from the power supply can be reduced. In order to further clarify this teaching, reference is made toFIG.6Ashowing the timing diagram presenting the control input pulses vs. time, when a staggered control of a PCM switch stack is adopted. Control pulses (601,601′) are issued sequentially and they correspond to programming the OFF state of two of the PCM switches within the stack. Similarly, control pulses (602,602′) are issued sequentially and they correspond to programming the ON state of two of the PCM devices within the stack. The timing diagram ofFIG.6Ais an example illustrating the staggered control and it is understood that such concept can be extended to control sequentially all of the PCM switches within the stack, one or more at a time, until all the PCM switches within the stack have changed state in accordance with the control input. The above teachings can be extended to an RF switch with a plurality of inputs and PCM devices and having at least two switch arms to transition OFF or ON. In this embodiment, the control signals may be staggered such that only one PCM device is being programmed at a given instant in time. If the switch arms include stacked PCM devices, each switch stack can be programmed at a given time interval, each PCM switch of the stack being programmed at a given instant. By way of example,FIG.6Bshows an exemplary driving arrangement for a PCM switch stack (600B) representing an exemplary implementation of the above-disclosed teachings related to the embodiment ofFIG.6A. The driving arrangement comprises PCM switch stack (650), drivers (D1, . . . , Dn), control and logic circuit (620), power supply (610), and serial interface (640). PCM switch stack (600B) includes a plurality of PCM switches (PS1, . . . , PSn) arranged in a stacked configuration, wherein in each PCM switch comprises a heater and volume of PCM. Logic and timing circuit (620) provides control input to each of drivers (D1, . . . , Dn) in accordance with the teachings disclosed with regards to the embodiment ofFIG.6A, i.e., in a staggered fashion. As a result, each of the drivers (D1, . . . , Dn) provides driving pulses to a corresponding PCM switch (PS1, . . . , PSn), in correspondence with the state of each power switch (PS1, . . . , PSn). Power supply (610) provides high and low bias voltages (VH, VL) to each driver (D1, . . . , Dn). Bias voltages (VH, VL) correspond to the ON/OFF state of the PCM switches within the PCM switch stack (6500), respectively. With reference to bothFIGS.6A-6B, the states of PCM switches (PS1, . . . , PSn) may be changed, one or more PCM switch at a time, and in separate/staggered time intervals. This means that less instantaneous current is drawn from the power supply to transition switching stack (650) from one state to another, resulting in a simpler power supply design. FIG.7shows an exemplary PCM switch driver (700) including a driver first stage (710) and a driver second stage (750) wherein the driver first stage (710) represents an implementation of any of drivers (230,230′) ofFIG.2according to an embodiment of the present disclosure. Terminal (OUTPUT) provides the input signal to the PCM (not shown). The embodiment ofFIG.7is similar to the one shown inFIG.3A, where the teachings of the disclosure are extended in order to handle larger supply voltages and output voltages. The embodiment ofFIG.7could be beneficial in case of larger heater resistance values or in case a same driver drives a stack of heaters. Driver first stage (710) comprises a first driver switch stack (701) including transistors (T10, . . . , T40), and a second driver switch stack (701′) including transistors (T10′, . . . , T40′). Driver switch stacks (701,701′) are each arranged in series with corresponding transistors (T50, T50′), respectively. Driver first stage (710) further comprises quasi-latch (703) including transistors (T60, T60′). In particular, transistors T60and T60′ are arranged to have positive feedback such that the resulting output signals transition quickly from one state to the other (i.e., driver OFF to ON), and the output voltage swing has the required amplitude to drive the next stage. Also shown are resistive ladders (702,702′) providing biasing to the gate terminal of the transistors within driver switch stacks (701,701′), respectively. Control input (SW_IN) is directly applied to transistor (T1) while the inverted version of the control input (SW_IN) is applied to transistor (T10′) via inverter (704). With further reference toFIG.7, according to an embodiment of the present disclosure, transistors (T10, . . . , T40, T10′, . . . , T40′) may be NFETs and transistors (T50, T50′, T60, T60′) may be PFETs. As an example, such embodiment may be implemented using a bias voltage (VH) of 10V, in which case NFETs would have a breakdown voltage handling of 2.5V or better, and PFETs would have a breakdown voltage handling of 5V or better. The output of the circuit is at the drains of transistors (T50, T50′), in order to drive a stack of transistors similar to transistor (T7) shown inFIG.3A. FIG.8Ashows an exemplary PCM switching arrangement (800A) according to an embodiment of the present disclosure, where a feedback mechanism is provided upstream of the PCM driver. In particular, PCM switching arrangement (800A) comprises PCM driver (801), PCM (802), feedback circuit (805), and transistors (T2, T2′) arranged as a current mirror (804). Feedback circuit (805) comprises operational amplifier (OP-amp) (803), reference resistor (Rref), reference voltage (Vref) and transistor (T1). Rref is intended to be identical to the heater resistor to be controlled. Such feedback circuit generates a desired current (Iref) through reference resistor (Rref) due to the voltages at both input terminals of the OP-amp (803) remaining the same at the desired reference voltage (Vref). Current mirror (804) essentially mirrors current (Iref) and feeds such current to PCM driver (801) to ensure the desired voltage and current are generated in the heater in correspondence with the desired state in which PCM (802) should be programmed. By virtue of implementing such feedback mechanism, variations from process, temperature, and supply voltage can be mitigated. Implementation of the feedback mechanism ofFIG.8Awill imply some design changes to the driver (801) with respect to the architectures shown inFIGS.3A,3B and7.FIG.8Bshows an exemplary PCM driver (800B) according to an embodiment of the present disclosure. PCM driver (800B) represents an exemplary implementation of PCM driver (801) ofFIG.8Aand includes switch stacks (813,813′) that are driven by circuits (810,810′) respectively, each provided to program the PCM switch (802) ofFIG.8A. When the PCM switch (802) is to be programmed in the ON state, the output of circuit (810) is HIGH and current Ion flows in switch stack (813), as indicated by arrow (820), while in the case when the PCM switch (802) is to be programmed in the OFF state, the output of circuit (810′) is HIGH and current Ioff flows in switch stack (813′), as indicated by arrow (820′). FIG.8Balso shows current Iref as an additional input, in accordance with the teachings ofFIG.8A. Such current is fed to switch stacks (813) and (813′) through current mirror (M5, M3) to generate current Ion and current mirror (M5, M2) to generate current Ioff. Reference current (Iref) is fixed by the feedback circuit. The values of currents Ion and Ioff are generated by the current mirror ratio generated by the ratio of M3and M2to M5. PCM driver (800B) further comprises current mirror (812) that is used to generate the current required by the heater through terminal (OUT), and in correspondence with the ON and OFF states of the PCM switch. The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material. As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit. With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions. Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design. Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits. Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication. A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence). | 22,008 |
11942930 | DETAILED DESCRIPTION OF THE INVENTION The following description is of preferred embodiments by way of example only and without limitation to the combination of features necessary for carrying the invention into effect. Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. The present invention relates to a field-effect transistor (FET), and particularly, but not exclusively, to a metal-oxide-semiconductor field-effect transistor (MOSFET) based synchronous rectifier in the form of a fully-integrated, single chip device for emulating the function of a diode. Particularly, the present invention provides a structurally simple, on-chip device by integrating in a single chip all the required, active and passive, electronic components generally associated with a synchronous rectifier diode. In one embodiment, the fully integrated single-chip device may comprise equal to or less than 15 discrete electronic devices or components integrated in said chip. The fully-integrated chip device of the present invention can be applied to and/or assembled in any standard or non-standard electronic packages and/or applications so as to function as a diode chip with a significantly lower forward voltage (Vf) drop achievable when compared to the available diode products in the market. Referring toFIG.4, shown is a circuit diagram of an embodied metal-oxide-semiconductor field-effect transistor (MOSFET) based synchronous rectifier provided in the form of a fully-integrated, single chip device10for emulating the function of a diode in accordance with the present invention. In this embodiment, the fully-integrated chip device10comprises two terminals20,30comprising a first terminal which comprises an anode20, and a second terminal which comprises a cathode30. The chip10further comprises a first FET such as a first MOSFET (M1) and a second FET such as a second MOSFET (M2). Specifically, the second MOSFET (M2) is adapted to control operation of the first MOSFET (M1) to thereby allow unidirectional current flow when the two terminals20,30are connected with an external circuit for emulating a diode. Preferably, the first terminal, i.e. the anode20, is provided on a first or top metal surface of the fully integrated single-chip device10, and the second terminal, i.e. the cathode30, is provided on a second or bottom metal surface of the fully integrated single-chip device10. More preferably, the single-chip device10has only two terminals20,30, i.e. the anode20at the top surface and the cathode30at the bottom surface for the integrated, single-chip device10to function as a diode. In this embodiment, the first MOSFET (M1) and the second MOSFET (M2) are integrated in the single-chip device10such that the second MOSFET (M2) comprises a driver for the first MOSFET (M1) to enable said first MOSFET (M1) to operate as a synchronous rectifier. Detailed structure and functionalities of the embodied on-chip device10as shown inFIG.4will be discussed further in the following description. Like most MOSFETs, the first MOSFET (M1) of the present invention has at least a first gate electrode, a first source electrode and a first drain electrode; and the second MOSFET (M2) has at least a second gate electrode, a second source electrode and a second drain electrode. In the embodiment as shown inFIG.4, the second drain electrode of the second MOSFET (M2) is connected in series with the first gate electrode of the first MOSFET (M1). To allow the integrated chip device10to function as a diode, the second MOSFET (M2) is configured to stay on when a voltage at the first drain electrode of the first MOSFET (M1) is positive, and the second MOSFET (M2) is configured to keep off when a voltage at the first drain electrode of the first FET (M1) is negative. This provides a clear difference in terms of operating principle from the prior art MOSFET based diode structures: the fully-integrated chip device10utilizes M2to control M1to operate as a synchronous rectifier MOSFET, while the other MOSFET solutions in the prior art require control of the synchronous rectifier MOSFET with at least one separate, operational integrated circuit that comprises a very large number of other, discrete electronic components electrically connected thereto which has considerable assembly and cost implications. Preferably, the circuit of the chip device10of the present invention can be configured by having the second source electrode of the second MOSFET (M2) and the first source electrode of the first MOSFET (M1) connected with the anode20; and the first drain electrode of the first MOSFET (M1) connected with the cathode30. More preferably, the chip device10may further comprise a first diode (D1) and a first resistor (R1) connected in series between the second drain electrode of the second MOSFET (M2) and the cathode30; a first capacitor (C1) connected in series between the first diode (D1) and the second source electrode of the second MOSFET (M2); and a second resistor (R2) and a second diode (D2) connected in parallel with the first capacitor (C1) and the first diode (D1) in between the anode20and the cathode30. More preferably, the second resistor (R2) is connected in series with the second gate electrode of the second MOSFET (M2); and the circuit may further comprise a third diode (D3) connected in parallel with the first MOSFET (M1), as shown inFIG.4. In one embodiment, the integrated capacitor (C1) is adapted to serve as a voltage or a current pump, such that the capacitor (C1) will be charged in the beginning of the input sinusoidal waveforms, and that the voltage charged will be used by the second MOSFET (M2) to drive operation of the first MOSFET (M1). FIG.5afurther illustrates a schematic diagram of a cross-section of the fully-integrated, on-chip device10; withFIG.5bshowing, in dashed lines, the components as shown in the cross-sectional view, and their interconnections in the form of a circuit diagram. The fully integrated single-chip device10, when operated to emulate a diode, does not require connection with any one or more of an external power FET and/or a control integrated circuit (IC) having one or more active and/or passive electronic components to control the MOSFETs. This is in contrast to the MOSFET synchronous rectifiers in the prior art, which generally require at least one or more of an external power MOSFET, a control integrated circuit and/or a number of other discrete components to enable controlling of the MOSFET by the integrated circuit, for example. The single-chip device10of the present invention has integrated therein all of the required active and/or passive components, which may comprise equal to or less than 15 discrete electronic devices or components integrated in said chip, for example, to enable said device to be provided in a simple and compact, on-chip structure to emulate a diode. As further shown inFIG.5a, the first MOSFET (M1) is preferably integrated in the single-chip device10for vertical operation, whilst all the other components are integrated in the single-chip device10to have horizontal operation. As discussed, the single-chip device10is capable of emulating the function of a diode, based on its MOSFET synchronous rectification configuration, which allows the first MOSFET (M1) to go into a conduction phase when its drain electrode is negatively polarized; and to go into a blocking phase, when the polarization of its drain electrode is switched from negative to positive. Specifically, during the conduction phase, the drain-source resistance can be very low which allows the voltage between drain electrode and source electrode of M1to become very low. In one embodiment, this low voltage, which equals to the forward voltages (Vf) of the emulated diode, can be equal to or lower than about 0.3 volt (V) for more than 90% during the on-state period, and preferably less than or equal to about 0.1 volt (V) for more than 90% during the on-state period, and more preferably, in the range of about 80 mV to about 90 mV for more than 90% during the on-state period, for example. To verify functionality of the single-chip device10as an emulator of a diode having a low Vf, a series of simulations have been conducted. For example,FIGS.6and7display the waveforms demonstrated by the emulated diode during the switching periods from on to off when the circuit of the chip device10is biased by a sinusoidal waveform generator.FIG.8further shows the comparison between the power dissipation waves form of the first MOSFET (M1) of the chip device10of the present invention and that of the Schottky diode as shown inFIG.2. The results clearly demonstrate a significant reduction in power loss achievable by the emulated diode of the present invention. Based on the Ohm's law, the diode-emulating chip device10dissipates a peak power loss of approximately about 9.5 W; while an equivalent Schottky diode typically dissipates a power loss of about 52.5 W, which is equivalent to about 5.5 times of the power loss of emulated diode of the present invention. The present invention is therefore advantageous in that it provides a structurally simple, MOSFET based synchronous rectifier for emulating the function of a diode, of which, when compared to known alternative diode devices, achieves a significantly lower forward voltage drop (Vf). Particularly, the present invention makes use of a second MOSFET (M2) to control operation of a first MOSFET (M1) configured in a synchronous rectification setting, which differs to the MOSFET synchronous rectifier of the prior art in which a MOSFET is controlled by at least one separate, operational integrated circuit having a large number of discrete electronic components connected thereto. It has been demonstrated that, for example, for a chip size of smaller than or about 30 mm2, a low Vfvalue of about 0.3V to 1 V may at best be achievable by a traditional silicon diode and/or a Schottky diode at a high current of above 3A. With the present invention, it is possible to achieve a much lower Vfof lower than or equal to about 0.1V for more than 90% of the on-state period duration under the same conditions, and therefore, a significant reduction in power loss is achieved. The Vfof the present invention is found to be about 5.5 times lower than the traditional Schottky diode, or in other words, a smaller chip size of about 1/5.5 or less would be required by the present invention to provide the same power during operation. The present invention also demonstrates superior performance in having a much lower reverse leakage at high temperature, which prevents thermal runaway when the emulated diode is operated at high temperature. Furthermore, the present invention also allows relatively simple fabrication and/or assembling processes when compared to the processing steps of the Schottky diodes and/or the MOSFET diodes in the prior art, which provides reduction in the associated manufacturing costs. The present description illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only exemplary embodiments have been shown and described and do not limit the scope of the invention in any manner. It can be appreciated that any of the features described herein may be used with any embodiment. The illustrative embodiments are not exclusive of each other or of other embodiments not recited herein. Accordingly, the invention also provides embodiments that comprise combinations of one or more of the illustrative embodiments described above. Modifications and variations of the invention as herein set forth can be made without departing from the spirit and scope thereof, and, therefore, only such limitations should be imposed as are indicated by the appended claims. In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function. The invention as defined by such claims resides in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein. In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word “comprise” or variations such as “comprises” or “comprising” is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. It is to be understood that, if any prior art publication is referred to herein, such reference does not constitute an admission that the publication forms a part of the common general knowledge in the art. | 14,378 |
11942931 | DESCRIPTION The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. Radio frequency (RF) switch applications can benefit from and/or require fast switching time. A gate capacitance and/or resistance of an RF Switch can create large resistor-capacitor (RC) time constant delays and/or can result in a relatively long switching time. Some switches (e.g., double pole double throw (DPDT) switches) can utilize relatively large RF switches (e.g., W=34×16 mm). However, the gate capacitance and/or gate resistance for such designs can be relatively high and/or can cause high delays. For example, a time constant associated with an RF switch may be proportional to the gate resistance multiplied by the gate capacitance of the RF switch. Some methods of reducing switching time can involve using transmission gate switches to short out the gate resistance of the RF switch application during switching. However, voltage swings can cause breakdown of the transmission gate switches in such cases. For example, a breakdown voltage for a transmission gate switch may be in the range of 4.5V. Generally, RF switch gate voltage swings from a range of a negative first voltage (e.g., −V1) to a positive second voltage (e.g., V2). In some switch applications, the negative first voltage can be approximately −2.5V and/or the positive second voltage may be approximately 3.5V, resulting in a voltage swing of 6 volts, which can exceed the breakdown voltage (e.g., 3.5V) of the transmission gate switch. Thus, use of a simple switch to short out the gate resistance may not be effective in cases in which voltage swing exceeds the breakdown voltage of the transmission gate switch. FIG.1illustrates an example switching circuit100in accordance with one or more embodiments. The circuit100can comprise an RF switch110(e.g., a transistor and/or field-effect transistor) including a gate, a source, and a drain. The gate of the RF switch110may be coupled (e.g., via coupling circuitry) to a gate resistor104. The drain of the RF switch110may be coupled to an RF output pad106and/or the source of the RF switch110may be coupled to an RF input pad108. The gate resistor104may be coupled in series with and/or may experience a voltage drop from a voltage source102, which may be configured to deliver a variable internal gate bias voltage from a range of −V1 to V2. The gate resistor104may be shorted by a transmission gate switch to speed up RF switching time. FIG.2illustrates gate capacitance for an example switching circuit (e.g., the circuit100ofFIG.1) in accordance with one or more embodiments. The circuit200can comprise an RF switch210(e.g., a transistor and/or field-effect transistor) including a gate, a source, and a drain. The gate of the RF switch210may be coupled (e.g., via coupling circuitry) to a gate resistor204. The drain of the RF switch210may be coupled to an RF output pad206and/or the source of the RF switch210may be coupled to an RF input pad208. The gate resistor204may be coupled in series with and/or may experience a voltage drop from a voltage source202, which may be configured to deliver a variable internal gate bias voltage from a range of −V1 to V2. The RF switch210may experience an internal gate capacitance, as illustrated by a gate capacitor212coupled between the gate of the RF switch210and the source of the RF switch210. The gate capacitance of the RF switch210may increase proportionately with the size of the RF switch210. A product of the gate capacitance and the gate resistance of the RF switch210may be indicative of a switching time of the RF switch210. In some embodiments, the circuit200may comprise a transmission gate switch214(e.g., a CMOS gate switch) coupled in parallel with the gate resistor204. The transmission gate switch214may be configured to experience the same gate voltage control circuit as the RF switch210. FIG.3illustrates another example switching circuit300configured to provide dynamic complementary pulsing to reduce switching time and/or startup time (e.g., turn-on time) of an RF switch310. The circuit comprises a first level shifter316associated with and/or coupled to a first voltage pulse source314receiving a supply voltage (Vlogic). The circuit300further comprises a second level shifter322associated with and/or coupled to a second voltage pulse source320receiving Vlogic. The first level shifter316may be directly coupled to a gate of a p-channel metal-oxide-semiconductor (PMOS)318and/or the second level shifter322may be directly coupled to a gate of an n-channel metal-oxide-semiconductor (NMOS)324. The first level shifter316and/or second level shifter322may be configured to shift a voltage range of a supply voltage. The NMOS324and/or PMOS318may form a transmission gate configured to short out the gate resistor304. The first level shifter316and the second level shifter322may be configured to apply complementary dynamic pulses to the PMOS318and/or NMOS324to short the gate resistor304when the RF switch310is switching or first turned on. Shorting the gate resistor304may be configured to cause a reduction in RC time constant of the circuit300and/or a reduction in switching time and/or turn-on time of the RF switch310. Pulses from the first level shifter316and the second level shifter322may last for a few (e.g., six or seven) microseconds each and/or may depend on the size of the RF switch310. A drain of the RF switch310may be coupled to an output pad306and/or a source of the RF switch310may be coupled to an input pad308. The first level shifter316and/or second level shifter322may be configured to be turned on when the RF switch is switching and/or turned on. Pulse widths of the first level shifter316and/or second level shifter322may be set according to the size of the RF switch310and/or based on a product of the gate resistance and gate capacitance (e.g., Rgate*Cgate) of the RF switch310. The first level shifter316and/or second level shifter322may be configured to dynamically follow voltage levels of a first voltage source302(e.g., a bias voltage) configured to supply a gate voltage to the RF switch310. By dynamically following the voltage levels of the first voltage source302, the first level shifter316and/or second level shifter322may be configured to ensure that the PMOS318and/or NMOS324do not break down. A supply voltage (Vlogic) may be supplied by control circuits and/or provide voltage inputs to the first pulse module314and/or the second pulse module320. When the RF switch gate voltage (Vgate) is between a negative voltage value (e.g., −V1) and 0V, the NMOS324may be in an on-state and/or the PMOS318may be in an off-state. A gate-to-source voltage (e.g., Vgs) of the NMOS324may be approximately equivalent to a sum of V1 and Vlogic when the RF switch gate voltage (Vgate) is −V1. The gate-to-source voltage of the NMOS324may then be gradually reduced to 0V when the gate voltage rises towards Vlogic. When the voltage experienced at the RF Switch (Vgate) is between 0V and V2=3.5V, the PMOS318may be in an on-state and/or the NMOS324may move gradually to an off-state when the gate voltage (e.g., Vgate) approaches Vlogic and then may move completely to the off-state when Vgate reaches V2. A gate-to-source voltage (e.g., Vgs) of the PMOS318may be approximately equal to (−V2) when Vgate is at 0V. The gate-to source voltage of the PMOS318may then gradually approach 0V and/or PMOS318may be turned off when Vgate rises toward V2. The PMOS318and/or NMOS324, together with the level shifters and/or pulse sources, may be configured to speed up switching time of the RF switch310, particularly in cases where the RF switch310is relatively large and/or where the bias voltage range is from −V1 to V2 and/or V1+V2>4.5V. In some embodiments, degradation of performance of the RF switch310may be greatly reduced as a result of the components of the circuit300. When the RF switch gate voltage is at a minimum value (e.g., −V1), the NMOS324and/or the PMOS318may be turned off so that the gate resistor304may not be shorted out. When the gate voltage is at a maximum value (e.g., V2), the NMOS324and/or the PMOS318may be turned off so that the gate resistor304may not be shorted out. The gate resistor304may only be shorted out when Vgate of the RF switch310is in a transition between −V1 to V2 and/or V2 to −V1. During this transition period, either NMOS324may be on or PMOS318may be on so that the gate resistor304may be shorted. The gate resistor304may not be shorted out when Vgate of the RF switch310is out of the transition period and/or is constant at V2 or −V1. In such cases, both PMOS318and NMOS324may be turned off. The PMOS318and/or NMOS324may advantageously be configured to short out the gate resistor304only when the RF switch310is turned on. After a turn-on period and/or when the RF switch310is operating normally, the PMOS318and/or NMOS324may not short out the gate resistor304such that the gate resistor304advantageously supplies resistance to the RF switch during operation to improve performance. FIG.4provides a graph400illustrating voltage values associated with various components of the circuit300ofFIG.3. A first plot402represents a gate voltage, a second plot404represents a first pulse voltage (e.g., into the PMOS318of the circuit300ofFIG.3), a third plot406represents a second pulse voltage (e.g., into the NMOS324of the circuit300ofFIG.3), and/or a fourth plot408represents a voltage source (Vlogic). For example, a voltage source (e.g., the first voltage source302ofFIG.3) may begin increasing in voltage at a 0s point of the graph400and/or may increase gradually until it reaches a determined voltage value (e.g., 1.8V, “Vlogic”) at approximately a 10 us mark. A gate voltage of the RF switch310may remain at approximately 0V for a period of time (e.g., approximately 20 us) after the voltage source turns on and/or may increase to a maximum value (e.g., approximately 3.5V, “V2”) for period of time (e.g., approximately 20 us) and/or may decrease to a minimum value (e.g., −2.5V, “−V1”) for a period of time (e.g., approximately 20 us) and/or may oscillate periodically between the maximum value and the minimum value. The gate voltage may transition from the maximum voltage to the minimum voltage at a gate voltage transition period. During the transition period, the gate resistor may be shorted. The gate voltage may increase from the minimum voltage to the maximum voltage at a gate voltage transmission period. During the transmission period, the gate resistor may be shorted. While the gate voltage maintains the minimum value, a transmission gate switch may be off, the gate resistor of the RF switch may not be shorted out. The first pulse voltage may have a delayed ramp-up and/or may increase from 0V to the maximum value at approximately the 30 us mark and/or may decrease back to 0V at approximately the 50 us mark. The first pulse voltage may dip down to a negative value (e.g., approximately −0.5V) but may periodically increase back to the maximum value. Thus, the voltage swing of the first pulse voltage may be approximately 4V. The second pulse voltage may increase to the Vlogic value (e.g., approximately 1.8V) simultaneously or near-simultaneously with the voltage source and/or may increase slightly above Vlogic (e.g., to approximately 2.1V) and/or may periodically oscillate between Vlogic and the minimum value (e.g., approximately −2.5V). Thus, the voltage swing of the second pulse voltage may be approximately 4.6V. The voltage swings of Vgs of the PMOS318(e.g., a difference between the first plot402and the second plot404may be less than V2 (e.g., 3.5V). The voltage swing of Vgs of NMOS324(e.g., a difference between the third plot406and the first plot402) may each be less than a sum of Vlogic and V1 (e.g., 4.3V) and/or may be less than a breakdown voltage of the transmission gate switches PMOS318and NMOS324. FIG.5shows a die505implemented in a packaged module500. Such a packaged module can include a packaging substrate502configured to receive a plurality of components. In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc. FIG.6depicts an example wireless device600having one or more advantageous features described herein. In some embodiments, a module that includes one or more power amplifiers can also include one or more clamps having one or more features as described herein. In the example ofFIG.6, power amplifiers (PAs) are depicted in a PA module612; however, it will be understood that such power amplifiers can be implemented in one or more functional blocks, one or more devices such as die or modules, etc. Such power amplifiers can receive their respective RF signals from a transceiver610that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver610is shown to interact with a baseband sub-system608that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver610. The transceiver610is also shown to be connected to a power management component606that is configured to manage power for the operation of the wireless device600. Such power management can also control operations of the baseband sub-system608and other components of the wireless device600. The baseband sub-system608is shown to be connected to a user interface602to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system608can also be connected to a memory604that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user. In the example ofFIG.6, a diversity receive (DRx) module631can be implemented between one or more diversity antennas (e.g., diversity antenna630) and the front-end module. Such a configuration can allow an RF signal received through the diversity antenna630to be processed (in some embodiments, including amplification by an LNA) with little or no loss of and/or little or no addition of noise to the RF signal from the diversity antenna630. Such processed signal from the DRx module640can then be routed to the front-end module through one or more signal paths. In some embodiments, the wireless device600may or may not include the foregoing DRx functionality. In the example ofFIG.6, a plurality of antennas (e.g.,620a,620b) can be configured to, for example, facilitate transmission of RF signals from the PA module612. In some embodiments, receive operations can also be achieved through some or all of the antennas620a,620b. Some implementations of the present disclosure relate to a switching circuit including: an RF switch; a gate resistor; a voltage source; a transmission gate; and coupling circuitry configured to couple a gate of the RF switch, a first side of the gate resistor, and the transmission gate at a first node and the voltage source, a second side of the gate resistor, and the transmission gate at a second node. In some aspects, the techniques described herein relate to a switching circuit wherein the transmission gate includes a PMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the transmission gate includes an NMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the coupling circuitry is further configured to couple a source of the PMOS to a drain of the NMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the coupling circuitry is further configured to couple a drain of the PMOS to a source of the NMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the coupling circuitry is further configured to couple the gate of the RF switch, the first side of the gate resistor, a drain of the PMOS, and a source of the NMOS at the first node. In some aspects, the techniques described herein relate to a switching circuit wherein the coupling circuitry is further configured to couple the voltage source, the second side of the gate resistor, a source of the PMOS, and a drain of the NMOS at the second node. In some aspects, the techniques described herein relate to a switching circuit further including a first level shifter configured to supply voltage pulses to the PMOS. In some aspects, the techniques described herein relate to a switching circuit further including a second level shifter configured to supply voltage pulses to the NMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the first level shifter and the second level shifter are configured to apply complementary dynamic pulses to the PMOS and NMOS. In some aspects, the techniques described herein relate to a switching circuit wherein the first level shifter and the second level shifter are configured to turn on when the RF switch is turned on. In some aspects, the techniques described herein relate to a switching circuit further including a first voltage pulse source coupled to the first level shifter. In some aspects, the techniques described herein relate to a switching circuit further including a second voltage pulse source coupled to the second level shifter. In some aspects, the techniques described herein relate to a switching circuit wherein the coupling circuitry is further configured to couple the gate resistor in parallel with the transmission gate. In some aspects, the techniques described herein relate to a switching circuit wherein the transmission gate is configured to short out the gate resistor. In some aspects, the techniques described herein relate to a circuit including: an RF switch; a transmission gate including a PMOS and an NMOS, wherein the transmission gate is configured to provide dynamic complementary pulsing voltages to the RF switch; and coupling circuitry configured to couple a gate of the RF switch to the transmission gate. In some aspects, the techniques described herein relate to a circuit further including a gate resistor, wherein the coupling circuitry is further configured to couple the gate of the RF switch, the gate resistor, and the transmission gate at a first node. In some aspects, the techniques described herein relate to a circuit wherein the transmission gate is configured to short out the gate resistor in response to the RF switch turning on. In some aspects, the techniques described herein relate to a circuit further including a first level shifter coupled to a gate of the PMOS. In some aspects, the techniques described herein relate to a circuit further including a second level shifter coupled to a gate of the NMOS. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed. Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general-purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers. Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices. Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general-purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means. Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s). Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include multiple distinct computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the described functions. Each such computing device typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. Where the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid-state memory chips and/or magnetic disks, into a different state. | 28,276 |
11942932 | DESCRIPTION OF REFERENCE SIGNS IN THE DRAWINGS 1—first pin;2—second pin;3—core module;31—first voltage regulating unit;32—enabling control unit;33—second voltage regulating unit;34—first short-circuit pull-up unit;35—second short-circuit pull-up unit; and4—target pin. DETAILED DESCRIPTION OF EMBODIMENTS The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are merely some but not all of embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the protection scope of the present invention. In the specification, claims and accompanying drawings of the present invention, the terms “first”, “second”, “third”, “fourth” and so on (if any) are intended to distinguish between similar objects but do not necessarily indicate a specific order or sequence. It should be understood that the terms so used may be interchanged where appropriate, so that the embodiments described herein can be implemented in a sequence other than what is illustrated or described herein. Furthermore, the terms “comprise” and “include” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, system, product or apparatus that comprises a list of steps or units does not include only those steps or units, but may include other steps or units not explicitly listed or inherent to such process, method, product or apparatus. The technical solutions of the present invention will be described in detail with reference to specific embodiments below. The following specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Referring toFIG.1toFIG.5, an embodiment of the present invention provides a level conversion circuit, and the level conversion circuit can be arranged on the same chip that may have a ground pin. In the embodiment of the present invention, the level conversion circuit includes a first pin1, a second pin2, a target pin4, a core module3and a switch5. A first terminal of the switch5is connected to the first pin1, a second terminal of the switch5is connected to the second pin2, and the core module3is connected to the target pin4, the second pin2and a control terminal of the switch5respectively. The switch5may be any device that can be controlled to turn on or off, such as a transistor, specifically a triode or a field-effect transistor. Therefore, the control terminal of the switch5may be, for example, a base or a gate. In the solution shown inFIG.5, the switch5is an NMOS transistor. In a further example, the switch5may have a threshold voltage Vth, which can be specifically understood as a gate-to-source threshold voltage that enables the switch to turn on. The first pin1and the second pin2can be any pins for digital signal transmission. In the level conversion circuit, a high level voltage transmitted by the second pin is lower than a high level transmitted by the first pin. In an example shown inFIG.5, the first pin1is a high voltage side pin (i.e., an IOVH pin) and the second pin2is a low voltage side pin (i.e., an IOVL pin). The target pin4can be any pin capable of transmitting an electrical signal. In the example shown inFIG.5, the target pin4can be characterized as a VCCEN pin because the target pin enables and provides a reference high level. In the embodiment of the present invention, the core module3is configured to:when a voltage connected to the target pin4is at a first reference high level, control the switch5to turn on to transmit a signal with a specified voltage amplitude, and pull the first pin to the first reference high level and the second pin to a second reference high level based on the first reference high level;the first reference high level is higher than the second reference high level; and at the specified voltage amplitude, a voltage of the signal transmitted through the switch is not higher than the first reference high level and the second reference high level. The core module3provides two voltages (i.e., the first reference high level and the second reference high level) respectively based on the same voltage (i.e., the first reference high level), and thus, no matter how the pin is pulled to a reference high level, the voltages are not out of the scope of the embodiment of the present invention. Because the first reference high level is higher than the second reference high level, step-down voltage regulation will be implemented in the core module3. In the above solution, based on access of the target pin to the first reference high level and cooperation of the core module, the target pin can implement both functions of an enabling pin and reference high level pins in the prior art, that is, the switch is enabled and two reference high levels are provided. It is thus clear that the number of pins used by the level conversion circuit is reduced by two and a circuit structure is simplified in the embodiment of the present invention, thereby reducing area and costs of the circuit and the chip, and saving internal space of the electronic device. Furthermore, the core module3may be further configured to:control the first pin and the second pin at the ground level when a voltage of the target pin is at the ground level. The ground level can also be understood as a ground voltage, specifically a ground potential of a chip of a logic conversion circuit (e.g., 0 V), but is not limited thereto. In one of the implementations, to achieve step-down regulation, the core module3may include a first voltage regulating unit31and an enabling control unit32. A first side of the first voltage regulating unit31is connected to the target pin4, a second side of the first voltage regulating unit31is connected to a first side of the enabling control unit32, a second side of the enabling control unit32is connected to the control terminal of the switch5, and the target pin4is also connected to the first pin1and the second pin2directly or indirectly. In an example shown inFIG.2, the target pin4is connected to the first pin1and the second pin2directly, and in examples shown inFIG.3toFIG.5, the target pin4is connected to a corresponding pin (i.e., the first pin1and/or the second pin2) indirectly (for example, through a corresponding voltage regulating unit and/or short-circuit pull-up unit). When the voltage connected to the target pin is at the first reference high level, a voltage at the first side of the first voltage regulating unit is at the first reference high level, and a voltage at the second side of the first voltage regulating unit is not lower than the second reference high level and not higher than the sum of the second reference high level and a threshold voltage of the switch. The enabling control unit32is configured to:when the voltage connected to the target pin is at the first reference high level, control the switch5to turn on in response to the voltage at the second side of the first voltage regulating unit to transmit the signal with the specified voltage amplitude; andcontrol the switch to turn off when the voltage connected to the target pin is at the ground level. For example, when the voltage connected to the target pin is at the first reference high level, then:if the voltage at the second side of the first voltage regulating unit is at the second reference high level, the first pin is pulled to the second reference high level and the switch is on (i.e., turned on), and pins (i.e., the first pin and the second pin) at both sides of the switch are pulled to the corresponding first reference high level and second reference high level respectively;if the voltage at the second side of the first voltage regulating unit is the sum of the second reference high level and the threshold voltage, the first pin is pulled to the second reference high level, and the switch is on, so that all transmitted signals lower than the second reference high level can pass through directly through the switch. The enabling control unit32can be understood as a circuit unit capable of controlling on-off of the switch based on received external signals. In a further solution, the enabling control unit32may also have a function of automatically turning off the switch in case of overtemperature. The first voltage regulating unit may be capable of regulating voltages, which can be achieved by linear voltage regulation, or achieved by switching a power supply or combining with a voltage divider resistor. In a specific solution, the first voltage regulating unit31may be a low dropout regulator (LDO). A voltage at the first side, a voltage at the second side, and the dropout between the voltage at the first side and the voltage at the second side can be preset as required. Furthermore, the voltage at the second side of the first voltage regulating unit31can be preset to match circuits shown inFIG.2toFIG.5. Specifically, in the circuit shown inFIG.2(i.e., the second voltage regulating unit33, the first short-circuit pull-up unit34and the second short-circuit pull-up unit35mentioned below are not used):for example, when the first voltage regulating unit is an LDO, the first reference high level at the first side of the first voltage regulating unit31can be described as VH_Ref, the voltage at the second side of the first voltage regulating unit31can be described as VLDO1, the second reference high level can be described as VL_Ref, and the threshold voltage can be described as Vth, then:in an example shown inFIG.2, VLDO=VL_Ref+Vth; andin another example shown inFIG.2, VLDO is slightly less than VL_Ref+Vth, for example: VLDO=0.9*VL_Ref+Vth. It can also be understood that the value of VL_Ref+Vth−VLDO is less than a preset difference threshold. The selection of the above values can also be applied to the circuits shown inFIG.3toFIG.5. In the circuits shown inFIG.3toFIG.5, the core module3further includes a second voltage regulating unit33, a first side of the second voltage regulating unit33is connected to the target pin4, and a second side of the second voltage regulating unit33is connected to the second pin2directly or indirectly. Specifically, the second voltage regulating unit33can be, for example, connected to the second pin2directly as shown inFIG.3, or connected to the second pin2through a second short-circuit pull-up unit mentioned below. When the voltage connected to the target pin is at the first reference high level, a voltage at the first side of the second voltage regulating unit is at the first reference high level, and a voltage at the second side of the second voltage regulating unit is at the second reference high level. The second voltage regulating unit33may be capable of regulating voltages, which can be achieved by linear voltage regulation, or achieved by switching a power supply or combining with a voltage divider resistor. In a specific solution, the second voltage regulating unit33may be a low dropout regulator (LDO). A voltage at the first side, a voltage at the second side, and the dropout between the voltage at the first side and the voltage at the second side can be preset as required. Specifically, in the circuits shown inFIG.3toFIG.5, for example, when the second voltage regulating unit is an LDO, the second reference high level at the first side of the second voltage regulating unit33can be described as VH_Ref, the voltage at the second side of the second voltage regulating unit33can be described as VLDO2, the second reference high level can be described as VL_Ref, and the threshold voltage can be described as Vth, then:in an example shown inFIG.3toFIG.5, VLDO=VL_Ref; andin an example shown inFIG.3toFIG.5, VLDO=VL_Ref+Vth; in this case, all transmitted signals in a range from GND to VL_Ref can pass through, thereby accelerating the establishment of higher logic high levels. In one of the implementations, referring toFIG.4andFIG.5, the core module3further includes a first short-circuit pull-up unit34disposed between the target pin4and the first pin1, and a second short-circuit pull-up unit35disposed between the second side of the second voltage regulating unit33and the second pin2. The short-circuit pull-up unit can be understood as any circuit unit capable of pulling a pin to a corresponding potential by short-circuiting a corresponding circuit position, for example, the first short-circuit pull-up unit can pull up the first pin to a voltage (e.g., the first reference high level) of the target pin, and the second short-circuit pull-up unit can pull up the second pin to a voltage at an output side of the second voltage regulating unit. In a further solution, a short-circuit pull-up unit can achieve instantaneous short-circuit, and thus, the short-circuit pull-up unit can also be understood as an instantaneous short-circuit pull-up unit. During pull-up, the pull-up can be achieved based on a pull-up resistor, for example, pull-up can be achieved by a 10 kΩ pull-up resistor. An instantaneous short-circuit pull-up unit may include an instantaneous short-circuit part (which can be understood as a one-shoot circuit part) and a pull-up part (which can be understood as a pull-up circuit part). The instantaneous short-circuit part can be understood as a circuit part that implements instantaneous short-circuit, the pull-up part can achieve a pull-up circuit part, and these parts can be connected in parallel and then connected to corresponding pins. For example, an instantaneous short-circuit part and a pull-up part in the first short-circuit pull-up unit can be connected in parallel, with both ends connected between the target pin and the first pin respectively; and an instantaneous short-circuit part and a pull-up part in the second short-circuit pull-up unit can be connected in parallel, and then connected between the second side of the second voltage regulating unit33and the second pin respectively. Therefore, instantaneous short-circuit between the target pin and the first pin, and instantaneous short-circuit between the second voltage regulating unit and the second pin can be achieved by the instantaneous short-circuit pull-up units. In a circuit, when transmission at a logic high level is detected on one side, the other side pulls up the level quickly through an instantaneous short-circuit circuit part in an instantaneous short-circuit pull-up unit to support signal transmission at a higher speed, and maintain a logic high level state after instantaneous short-circuit through a pull-up part connected in parallel with the instantaneous short-circuit pull-up unit (unless in a logic low level transmission stage). The pull-up part may be a pull-up resistor circuit that is fixed or can be controlled to turn on and off in the circuit, and if controllable, the pull-up part can be controlled by an enabling control unit or other circuits. Referring toFIG.5, the above-mentioned first pin is an IOVH pin, the second pin is an IOVL pin, the target pin is a VCCEN pin, and the ground pin is a GND pin, in which the switch5can be a switch SW, and a threshold voltage of the switch SW is characterized as VTH, the first voltage regulating unit is LDO1, and the second voltage regulating unit is LDO2. Therefore, when a voltage of the VCCEN pin is a normal working voltage for the first reference high level VH_Ref, power is supplied to a level conversion circuit chip therein, the first reference high level VH_Ref of the VCCEN pin is input to the LDO1, and an output of the LDO1 is a normal working voltage of the second reference high level VL_Ref. In this case, a voltage at the second reference high level VL_Ref generated inside the chip through the LDO1 assumes the duties of an external second reference high level VL_Ref in the prior art;the VCCEN pin also generates an output voltage through the LDO2, and controls on-off of the switch SW through the enabling control module32. In this case, an output of the LDO2 can be the second reference high level VL_Ref or VL_Ref+VTH. If VLDO2 (i.e., the voltage at the second side of the LDO2)=VL_Ref+VTH, signals in a range from GND to the second reference high level VL_Ref transmitted by the level conversion circuit can pass through, thereby accelerating the establishment of higher logic high levels. Finally, VH_Ref=GND, LDO1=VL_Ref=GND and LDO2=GND when VCCEN=GND, that is, a gate control voltage of the SW is GND, and thus, the whole level conversion circuit is completely turned off. It is thus learned that in the solution, a function of level conversion is well implemented, and two pins are reduced, so that die area is reduced and it is easier to select a suitable smaller package, thereby reducing the area of a finished chip. In this way, space is saved and costs are reduced for some space-constrained electronic devices such as mobile phones and wireless Bluetooth headsets. In actual application, considering that signal logic high levels of a receiver and a transmitter in a circuit system with level conversion are fixed, a voltage at the second reference high level VL_Ref can be stabilized in the level conversion circuit by the LDO1 and a control voltage of the SW can be stabilized by the LDO2 in advance. Therefore, voltages that would otherwise be input are now generated internally, so that pins of a chip are simplified. An embodiment of the present invention further provides an electronic device, including the above-mentioned level conversion circuit. Finally, it should be noted that the foregoing embodiments are merely intended for describing the technical solutions of the present invention rather than limiting the present invention. Although the present invention is described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they may still make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some or all technical features thereof, without departing from the scope of the technical solutions of the embodiments of the present invention. | 18,420 |
11942933 | DETAILED DESCRIPTION The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Voltage level shifting is used in many applications. Voltage level shifting entails shifting an input signal that varies in accordance with a first voltage domain, to generate an output signal that varies in accordance with a second voltage domain; the first voltage domain being different from the second voltage domain. A voltage domain is defined by the voltage levels of the high and low logic states of a signal. Voltage level shifting may be upwards, where the second voltage domain of the output signal has at least one logic voltage higher than at least one corresponding logic voltage of the first voltage domain of the input signal. Voltage level shifting may also be downwards, where the second voltage domain of the output signal has at least one logic voltage lower than at least one corresponding logic voltage of the first voltage domain of the input signal. As an example of an upwards voltage level shifting, the first voltage domain of the input signal may vary between a low logic voltage of zero (0) Volt (V) and a high logic voltage of 0.9V, and the second voltage domain of the output signal may vary between a low logic voltage of 0V and a high logic voltage of 1.8V. Thus, the high logic voltage 1.8V of the second voltage domain is higher than the high logic voltage 0.9V of the first voltage domain. This example may be the case where the input signal is processed by high-speed digital circuits pertaining to an integrated circuit (IC) or a system on chip (SOC), where the high speed nature of the signal processing favors using relatively small transistors or field effect transistors (FETs) in the digital circuits. Because of the small nature of the transistors, the transistors may have a reliability limit as to the voltage that may be applied across the transistors. With regard to this example, the high logic voltage of 0.9V of the first voltage domain may be within the reliability limit of the transistors, but the high logic voltage of the second voltage domain may be outside of the reliability limit of the transistors. The second voltage domain of the output signal may be more appropriate for transmission of signals outside of the IC or SOC, such as via transmission lines of a printed circuit board (PCB). Continuing the previous example, pursuant to a downward voltage level shifting, the second voltage domain of the input signal in this case may vary between a low logic voltage of 0V and a high logic voltage of 1.8V, and the first voltage domain of the output signal may vary between a low logic voltage of 0V and a high logic voltage of 0.9V. Thus, the high logic voltage 0.9V of the second voltage domain is lower than the high logic voltage 1.8V of the first voltage domain. This example may be the case where the input signal is received by an IC or SOC from a transmission line of a PCB, and the down voltage conversion is performed so that the high-speed digital circuits may process the output signal in the lower voltage domain so that the reliability of the transistors is not compromised. Voltage level shifters that perform the aforementioned upwards and downwards voltage level shifting may be employed by input/output (I/O) circuits or drivers of an IC or SOC to send and receive signals to and from outside of the IC or SOC. More discussion and examples of voltage level shifting is provided further herein. FIG.1Aillustrates a block diagram of an example signal processing system100in accordance with an aspect of the disclosure. The signal processing system100is configured to receive an input signal VINPXin a first voltage domain, which may be referred to herein as the “PX” voltage domain. Pursuant to the PX voltage domain, the input signal VINPXmay vary between a low logic voltage VSSX (e.g., 0V) and a high logic voltage VDDPX (e.g., 1.8V). As discussed further herein, the signal processing system100is configured to generate signals in different voltage domains for processing based on the input signal VINPX. In particular, the signal processing system100includes a voltage domain splitter110, buffers115,125,130, and135, and voltage level shifters120and140. Additionally, the signal processing system100includes a low voltage (LV) domain signal processing circuit150and a high voltage (HV) domain processing circuit160. The voltage domain splitter110is configured to receive the input signal VINPX, and generate first and second signals V1HVand V2LVbased on the input signal VINPXPer the example previously discussed, the input signal VINPXmay be in the higher PX voltage domain because the signal processing system100may have received the signal from outside of an IC or SOC via a transmission line of a PCB. The voltage domain splitter110may be part of an I/O circuit or driver of an IC or SOC, and may include transistors (e.g., FETs) or circuitry (e.g., stacking of FETs) configured to reliably process signals in the PX voltage domain (e.g., 0V to 1.8V). The first signal V1HVmay be in the HV voltage domain, where the first signal V1HVvaries between a low logic voltage VSSIX (e.g., 0.9V) and the high logic voltage VDDPX (e.g., 1.8V). Similarly, the second signal V2LVmay be in the LV voltage domain, where the second signal V2LVvaries between the low logic voltage VSSX (e.g., 0V) and a high logic voltage VDDIX (e.g., 0.9V). Thus, the voltage domain splitter110effectively splits the voltage domain PX (e.g., 0V to 1.8V) of the input signal VINPXinto an upper half voltage domain HV (e.g., 0.9V to 1.8V) and a lower half voltage domain LV (e.g., 0V to 0.9V). Note that, in this example, the low logic voltage of the HV voltage domain is substantially the same as the high logic voltage of the LV voltage domain. Since the voltage difference (e.g., ΔV=0.9V) between the low and high logic voltages in the HV and LV voltage domains is half of the PX voltage domain, the circuits (e.g., buffers115,125,130,135, voltage level shifters120and140, and signal processing circuits150and160) that process these signals may be implemented using smaller transistors or FETs that may reliably process signals in the HV and LV voltage domains. The buffer115is configured to buffer the first signal V1HVto generate a buffered first signal V1BHV. The buffer125is configured to buffer the second signal V2LVto generate a buffered second signal V2BLV. The buffer135is configured to buffer the first signal V1HVto generate another buffered first signal V1BHV. The buffer130is configured to buffer the second signal V2LVto generate another buffered second signal V2BLV. The voltage level shifter120is configured to downward voltage level shift the buffered first signal V1BHVto generate a signal V1LVbased on the first signal V1HV, but in the LV voltage domain. Similarly, the voltage level shifter140is configured to upward voltage level shift the buffered second signal V2BLVto generate a signal V2HVbased on the second signal V2LV, but in the HV voltage domain. The LV domain signal processing circuit150is configured to process the V1LVand V2BLVsignals, as these signals are in the LV voltage domain. Similarly, the HV domain signal processing circuit160is configured to process the V1BHVand V2HVsignals, as these signals are in the HV voltage domain. FIG.1Billustrates a timing diagram of an example operation of the signal processing system100in accordance with another aspect of the disclosure. The horizontal axis of the timing diagram represents time. The vertical axis of the timing diagram represents logic levels, from top to bottom, of the signals V1HV, V2LV, V1BHV, V1LV, V2BLV, and V2HV. As previously discussed, the first and second signals V1HVand V2LVare generated by the voltage domain splitter110based on the input signal VINPX. As both signals V1HVand V2LVare derived from the same signal VINPX, both signals should be logically identical, but for being in different voltage domains HV and LV. However, in some cases, the first and second signals V1HVand V2LVpropagate through different data paths; and, as a result, the V1HVand V2LVare no longer identical. For instance, in the example timing diagram, the second signal V2LVhas a pulse width or duty cycle larger than the pulse width or duty cycle of the first signal V1HV. That is, the pulse width of the second signal V2LVextends from time t1to time t10; whereas the pulse width of the first signal V1HVextends from time t3to time is (e.g., t10−t1>t8−t3). As a result of this initial timing degradation, the signals derived from these signals V1HVand V2LVmay experience additional timing degradation. For instance, the first and second buffered signals V1BHVand V2BLVgenerated by buffers115/135and130/135based on the first and second signals V1HVand V2LVhave significantly disparate pulse widths or duty cycles, respectively. For example, the second buffered signal V2BLVhas a pulse width extending from time t2to time t9, and the first buffered signal V1BHVhas a pulse width extending from time t4to time t7, where t9−t2is significantly greater than t7−t4. This is sometimes referred to as duty cycle distortion. Further, in accordance with this example, the voltage level shifted signals V1LVand V2HVgenerated by voltage level shifters120and140based on the buffered signals V1BHVand V2BLVmay have further timing degradation and uncertainties, respectively. For example, in addition to duty cycle distortion, there may be timing uncertainties ΔT5and ΔT6in the rising edges of the voltage level shifted signals V1LVand V2HV, and timing uncertainties ΔT11and ΔT12in the falling edges of the voltage level shifted signals V1LVand V2HV, respectively. This may be because the voltage level shifters120and140typically have many devices (e.g.,18FETs or more), and there may be significant process-voltage-temperature (PVT) operational variations due to the many devices. Due to all of the aforementioned timing degradations, the timing of the signals V1LV/V2BLVand V1BHV/V2HVprovided to the LV domain signal processing circuit150and HV domain signal processing circuit160may be completely destroyed, respectively. As such, the LV and HV signal processing circuits150and160may not be able to perform its intended operations based on the timing-degraded signals V1LV/V2BLVand V1BHV/V2HV, respectively. Other drawbacks of the voltage level shifters120and140include occupying substantial IC footprint due to the many devices. Further, the delay between the input signal and the output signal of the voltage level shifters120and140could be quite large; for example, on the order of nanoseconds. FIG.2illustrates a block diagram of another example signal processing system200in accordance with another aspect of the disclosure. The signal processing system200may perform the same or similar operations as that of signal processing system100previously discussed. However, instead of using voltage level shifters120and140, the signal processing system200uses edge alignment circuits to reduce or substantially eliminate any timing degradation in the signals provided to LV and HV signal processing circuits. In particular, the signal processing system200includes a voltage domain splitter210, inverters220and230, edge alignment circuits215and240, and buffers225and235. The voltage domain splitter210may be implemented similar as voltage domain splitter110previously discussed in detail. That is, the voltage domain splitter210is configured to receive an input signal VINPXin the PX voltage domain (e.g., 0V to 1.8V), and generate first and second signals V1HVand V2LVin HV (e.g., 0.9V to 1.8V) and LV (e.g., 0V to 0.9V) voltage domains based on the input signal VINPX, respectively. Similarly, the buffers235and225are configured to generate buffered first and second signals V1BHVand V2BLVbased on the first and second signals V1HVand V2LV, respectively. The inverters230and220are configured to invert the first and second signals V1HVand V2LVto generate complementary first and second signalsV1HVandV2LV, respectively. The edge alignment circuit215is configured to receive the first signal V1HVand the complementary second signalV2LV, and generate a voltage-level shifted signal V1LVbased on these signals V1HVandV2LV. Similarly, the edge alignment circuit240is configured to receive the second signal V2LVand the complementary first signalV1HV, and generate a voltage-level shifted signal V2HVbased on these signalsV1HVand V2LV. As discussed further herein, the signals V1LVand V2HVgenerated by the edge alignment circuits215and240are substantially time aligned; preserving the timing information of the original input signal VINPX; and allowing the LV and HV processing circuits250and260to process them adequately pursuant to their intended operations. FIG.3illustrates a schematic diagram of an example edge alignment circuit300in accordance with another aspect of the disclosure. The edge alignment circuit300may be an example detailed implementation of the edge alignment circuit215previously discussed. In particular, the edge alignment circuit300includes a first field effect transistor (FET) M1, which may be implemented as an n-channel metal oxide semiconductor (NMOS) FET. The edge alignment circuit300further includes an inverter310including a second FET M2and a third FET M3. The second FET M2may be implemented as a p-channel metal oxide semiconductor (PMOS) FET, and the third FET M3may be implemented as an NMOS FET. The FET M1and the inverter310are coupled in series between an upper voltage rail VDDIX and a lower voltage rail VSSX. The NMOS FET M1includes a gate configured to receive the first signal V1HV, for example, generated by the voltage domain splitter210based on the input signal VINPX. As previously discussed, the first signal V1HVis in the HV voltage domain (e.g., 0.9V to 1.8V). The PMOS FET M2and the NMOS FET M3include respective gates coupled together to form an input of the inverter310, and configured to receive the complementary second signalV2LV, for example, generated by the inverter220based on the second signal V2LV; which, in turn, is generated by the voltage domain splitter210based on the input signal VINPX. The complementary second signalV2LVis in the LV voltage domain (e.g., 0V to 0.9V), and is substantially logically complementary to the first signal V1LV. The PMOS FET M2and the NMOS FET M3include respective drains coupled together to form an output of the inverter310, and configured to generate the output signal V1LV. As previously discussed, the output signal V1LVis in the LV voltage domain (e.g., 0V to 0.9V), and may be provided to the LV voltage domain signal processing circuit250as previously discussed. The edge alignment circuit300may optionally include a latch320coupled to the output of the inverter310to latch the output signal V1LV. This may improve the latching of the correct logic state of the output signal V1LVif there is significant time delay between the first signal V1HVand the complementary second signal V2LV. The upper and lower voltage rails VDDIX and VSSX are configured to receive supply voltages in accordance with the LV voltage domain (e.g., 0.9V and 0V, respectively). FIG.4illustrates a schematic diagram of another example edge alignment circuit400in accordance with another aspect of the disclosure. The edge alignment circuit400may be an example detailed implementation of the edge alignment circuit240previously discussed. In particular, the edge alignment circuit400includes an inverter410including a first FET M4and a second FET M5. The first FET M4may be implemented as a PMOS FET, and the second FET M5may be implemented as an NMOS FET. The edge alignment circuit400includes a third FET M6, which may be implemented as a PMOS FET. The inverter410and the PMOS FET M6are coupled in series between an upper voltage rail VDDPX and a lower voltage rail VSSIX. The PMOS FET M6includes a gate configured to receive the second signal V2LV, for example, generated by the voltage domain splitter210based on the input signal VINPX. As previously discussed, the second signal V2LVis in the LV voltage domain (e.g., 0V to 0.9V). The PMOS FET M4and the NMOS FET M5include respective gates coupled together to form an input of the inverter410, and configured to receive the complementary first signalV1HV, for example, generated by the inverter230based on the first signal V1HV; which, in turn, is generated by the voltage domain splitter210based on the input signal VINPX. The complementary first signalV1HVis in the HV voltage domain (e.g., 0.9V to 1.8V), and is substantially logically complementary to the second signal V2LV. The PMOS FET M4and the NMOS FET M5include respective drains coupled together to form an output of the inverter410, and configured to generate the output signal V2HV. As previously discussed, the output signal V2HVis in the HV voltage domain (e.g., 0.9V to 1.8V), and may be provided to the HV voltage domain signal processing circuit260as previously discussed. The edge alignment circuit400may optionally include a latch420coupled to the output of the inverter410to latch the output signal V2HV. This may improve the latching of the correct logic state of the output signal V2HVif there is significant time delay between the second signal V2LVand the complementary first signalV1HV. The upper and lower voltage rails VDDPX and VSSIX are configured to receive supply voltages in accordance with the HV voltage domain (e.g., 1.8V and 0.9V, respectively). FIG.5illustrates a timing diagram of an example operation of the edge alignment circuits300and400in accordance with another aspect of the disclosure. The timing diagram is similar to the timing diagram ofFIG.1B, where the horizontal axis represents time, and the vertical axis represents the logic levels, from top to bottom, of the signals V1HV, V2LV, V1LV, and V2HV. As previously discussed, there may be some timing degradation in the first and second signals V1HVand V2LVwhen, for example, generated by the voltage domain splitter210based on the input signal VINPXAs an example, the second signal V2LVmay have a pulse width or duty cycle greater that the pulse width or duty cycle of the first voltage signal V1HV. For instance, in this particular example, the pulse width of the second signal V2LVextends from time t1to time t8, and the pulse width of the first signal V1HVextends from t2to time t8, where t8−t1is greater than t5−t2. Further, in accordance with this example, the complementary first and second signalsV1HVandV2LVare substantially the inverted versions of the first and second signals V1HVand V2LV, respectively. With further reference toFIG.3, considering the operation of the edge alignment circuit300, at time t1, the second signal V2LVtransitions from a low logic level to a high logic level in the LV domain. Substantially simultaneously, the complementary second signalV2LVtransitions from a high logic level to a low logic level in the LV domain. As the complementary second signalV2LVis applied to the gate of the inverter310, the PMOS FET M2turns on and the NMOS FET M3turns off. Then, at time t2, the first signal V1HVtransitions from a low logic level to a high logic level in the HV domain. As the first signal V1HVis applied to the gate of NMOS FET M1, the NMOS FET M1turns on. As both FETs M1and M2are turned on, and FET M3is turned off, the output signal V1LVtransitions from a low logic level to a high logic level in the LV domain at time t3, as the supply voltage provided to the upper voltage rail VDDIX is substantially the same as the high logic level in the LV domain, as previously discussed. Then, at time t4, the first signal V1HVtransitions from a high logic signal to a low logic signal in the HV domain. As the first signal V1HVis applied to the gate of the NMOS FET M1, the FET M1turns off. Then, at time t6, the second signal V2LVtransitions from a high logic level to a low logic level in the LV domain. Substantially simultaneously, the complementary second signalV2LVtransitions from a low logic level to a high logic level in the LV domain. As the complementary second signalV2LVis applied to the input of the inverter310, the PMOS FET M2turns off and the NMOS FET M3turns on. As both FETs M1and M2are turned off, and FET M3is turned on, the output signal V1LVtransitions from a high logic level to a low logic level in the LV domain at time t7, as the supply voltage provided to the lower voltage rail VSSX is substantially the same as the low logic level in the LV domain, as previously discussed. With further reference toFIG.4, considering the operation of the edge alignment circuit400, similarly at time t1, the second signal V2LVtransitions from a low logic level to a high logic level in the LV domain. As the second signal V2LVis applied to the gate of PMOS FET M6, the PMOS FET M6turns off. Then, at time t2, the first signal V1HVtransitions from a low logic level to a high logic level in the HV domain. Substantially simultaneously, the complementary first signalV1HVtransitions from a high logic level to a low logic level in the HV domain. As the complementary first signalV1HVis applied to the input of the inverter410, the PMOS FET M4turns on and the NMOS FET M5turns off. As both FETs M5and M6are turned off, and FET M4is turned on, the output signal V2HVtransitions from a low logic level to a high logic level in the HV domain at time t3, as the supply voltage provided to the upper voltage rail VDDPX is substantially the same as the high logic level in the HV domain, as previously discussed. Then, at time t4, the first signal V1HVtransitions from a high logic level to a low logic level in the HV domain. Substantially simultaneously, the complementary first signalV1HVtransitions from a low logic level to a high logic level in the HV domain. As the complementary first signalV1HVis applied to the input of the inverter410, the PMOS FET M4turns off and the NMOS FET M5turns on. Then, at time t6, the second signal V2LVtransitions from a high logic level to a low logic level in the LV domain. As both FETs M5and M6are turned on, and FET M4is turned off, the output signal V2HVtransitions from a high logic level to a low logic level in the HV domain at time t7, as the supply voltage provided to the lower voltage rail VSSIX is substantially the same as the low logic level in the HV domain, as previously discussed. Note that the output signals V1LVand V2HVof the edge alignment circuits300and400have substantially time aligned rising edges at time t3and falling edges at time t7. This is because the rising edge of the output signals V1LVand V2HVoccurs in response to the rising edge of the first signal V1HV, and the falling edge of the output signals V1LVand V2HVoccur in response to the falling edge of the second signal V2LVThus, the edge alignment circuit300and400may be used as a voltage level shifter for the input signals at the gates of FETs M1and M6, respectively. In the case of edge alignment circuit300, it operates as a downwards voltage level shifter to level shift the first signal V1HVfrom the HV voltage domain to the LV voltage domain In the case of edge alignment circuit400, it operates as an upwards voltage level shifter to level shift the second signal V2LVfrom the LV voltage domain to the HV voltage domain. Additional advantages of the edge alignment circuits300and400follow from the fact that they include a small number of devices. For example, without the optional latches320and420, each of the edge alignment circuits300and400includes three (3) devices, compared to at least 18 devices for an example voltage level shifter, as previously discussed. With the optional latches320and420, each of the edge alignment circuits300and400may have nine (9) devices, as each latch may include cross-coupled inverters. Additionally, due to the small number of devices, each of the edge alignment circuits300and400may occupy a relatively small IC footprint. Further, the delay associated with each of the edge alignment circuits300and400may be on the order of picoseconds (ps), whereas the delay associated with an example voltage level shifter may be on the order of nanoseconds (ns), as previously discussed. FIG.6illustrates a block diagram of another example signal processing system600in accordance with another aspect of the disclosure. In the signal processing system200, a voltage domain splitter210is used to generate signals in an upper half voltage domain HV and a lower half voltage domain LV from an input signal VINPXin a PX voltage domain, which extends from the low logic voltage of the LV voltage domain to the high logic voltage of the HV voltage domain. In signal processing system600, an input signal VINCXin a CX voltage domain (e.g., a voltage domain (e.g., 0.5V to 1.1V) used by high-speed signal processing circuits in an IC or SOC) is provided to a voltage level shifter610. In this case, the voltage level shifter610generates a first signal V1HVand a complementary first signalV1HVin the HV voltage domain (e.g., 0.9V to 1.8V) based on the input signal VINCX. Additionally, the voltage level shifter610generates a second signal V2LVand a complementary second signalV2LVin the LV voltage domain (e.g., 0V to 0.9V) based on the input signal VINCXHowever, due to different data paths, the first and second signals V1HVand V2LVand their respective complementary signalsV1HVandV2LVmay have timing degradation, as previously discussed. FIG.7illustrates a block diagram of another example signal processing system700in accordance with another aspect of the disclosure. To address the timing degradation discussed with respect to signal processing system600, the signal processing system700includes edge alignment circuits to retime or substantially time-align the signals for further processing by HV and LV voltage domain signal processing circuits, as previously discussed. In particular, the signal processing system700includes a voltage level shifter710configured to receive an input signal VINCXin the CX voltage domain (e.g., 0.5V to 1.1V), and generate a first signal V1HVand a complementary first signalV1HVin the HV voltage domain (e.g., 0.9V to 1.8V), and a second signal V2LVand a complementary second signalV2LVin the LV voltage domain (e.g., 0V to 0.9V); both sets of signals being based on the input signal VINCX. The signal processing system700further includes a set of edge alignment circuits720,730,740, and740. The edge alignment circuit720is configured to receive the first signal V1HVand the complementary second signalV2LV, and generate a third signal V3LVin the LV domain. The edge alignment circuit720may be implemented per edge alignment circuit300. The edge alignment circuit730is configured to receive the first signal V1HVand the complementary second signalV2LV, and generate a complementary fourth signalV4LVin the HV domain. The edge alignment circuit730may be implemented per edge alignment circuit400. The edge alignment circuit740is configured to receive the complementary first signalV1HVand the second signal V2LV, and generate a fourth signal V4HVin the HV domain. The edge alignment circuit740may be implemented per edge alignment circuit400. The edge alignment circuit750is configured to receive the complementary first signalV1HVand the second signal V2LV, and generate a complementary third signalV3LVin the LV domain. The edge alignment circuit750may be implemented per edge alignment circuit300. As these signals V3LV,V4HV, V4HV, andV3LVare generated by edge alignment circuits720,730,740, and750, respectively, the rising and falling edges of the signals may be substantially time-aligned for improved processing by LV and HV voltage domain signal processing circuits. FIG.8illustrates a schematic diagram of an example multi-mode edge alignment circuit800in accordance with another aspect of the disclosure. In a first mode of operation, the edge alignment circuit800operates per edge alignment circuit300previously discussed. In a second mode of operation, the edge alignment circuit300operates as a two-input inverter. In particular, the edge alignment circuit800includes a first FET M7, which may be implemented as a PMOS FET. The edge alignment circuit800further includes a first inverter815including an input coupled to a gate of the PMOS FET M7. The first inverter815may be coupled to first and second programmable voltage rails VDDPX/VDD_1P2and VSSIX/VSSX configured to receive supply voltages in accordance with an HV voltage domain (e.g., 1.8V and 0.9V, respectively) in the first mode of operation, and supply voltages in the VDD_1P2voltage domain (e.g., 1.2V and 0V, respectively) in the second mode of operation. The edge alignment circuit800additionally includes a second FET M8, which may be implemented as an NMOS FET. The edge alignment circuit800also includes a second inverter810including a third FET M9and a fourth FET M10. The third FET M9may be implemented as a PMOS FET, and the fourth FET M10may be implemented as an NMOS FET. The second FET M8and the second inverter810are coupled in series between an upper voltage rail VDD_1P2and a lower voltage rail VSSX, which are configured to receive supply voltages in accordance with the VDD_1P2voltage domain (e.g., 1.2V and 0V, respectively). The PMOS FET M7is coupled between the upper voltage rail VDD_1P2and the second inverter810. The PMOS FET M7includes a gate configured to receive a first input signal V1. In accordance with the first mode of operation, the first input signal V1varies in accordance with the HV voltage domain (e.g., 0.9V to 1.8V). In accordance with the second mode of operation, the first input signal V1varies in accordance with the VDD_1P2voltage domain (e.g., 0V to 1.2V). The PMOS FET M9and the NMOS FET M10include respective gates coupled together to form an input of the inverter810, and configured to receive a second input signal V2. In accordance with the first mode of operation, the second input signal V2varies in accordance with the LV voltage domain (e.g., 0V to 0.9V). In accordance with the second mode of operation, the second input signal V2varies in accordance with the VDD_1P2voltage domain (e.g., 0V to 1.2V). The PMOS FET M9and the NMOS FET M10include respective drains coupled together to form an output of the inverter810, and configured to generate an output signal V3. In the first mode of operation, the output signal V3varies in accordance with the LV voltage domain (e.g., 0V to 0.9V). In the second mode of operation, the output signal V3varies in accordance with the VDD_1P2voltage domain (e.g., 0V to 1.2V). The edge alignment circuit800may optionally include a latch820coupled to the output of the inverter810to latch the output signal V3. This may improve the latching of the correct logic state of the output signal V3if there is significant time delay between the first signal V1and the second signal V2. The mode of operation is set by the voltage domain of the first and second input signals V1and V2. For instance, if the first and second input signals V1and V2vary in accordance with the HV and LV voltage domains, respectively, the edge alignment circuit800operates in accordance with the first mode of operation. In this mode, the PMOS FET M7is effectively disabled, and the inverter815and the NMOS FET M8are enabled. The inverter815generates the complementary first voltage V1at the gate of NMOS FET M8, which, in this example, is substantially complementary to the logic level of the second voltage V2. As such, the operation of the edge alignment circuit800is effectively the same as the operation of the edge alignment circuit300previously discussed. As discussed, in accordance with the first mode of operation, the PMOS FET M7is effectively disabled because the first signal V1is unable to turn on the PMOS FET M7with the low logic level (e.g., 0.9V) in accordance with the HV voltage domain. If, for example, the threshold voltage of the PMOS FET M7is 0.4V, the low logic level of 0.9V produces a gate-to-source voltage of 0.3V, which is less than the threshold voltage of 0.4V. As such, the PMOS FET M7does not turn on. If the first and second input signals V1and V2vary in accordance with the VDD_1P2voltage domain, the edge alignment circuit800operates in accordance with the second mode of operation. In this mode, the PMOS FET M7, the inverter815and the NMOS FET M8are enabled. As such, the edge alignment circuit800operates as a two-input inverter. That is, when the first and second input signals V1and V2are at a low logic level in accordance with the VDD_1P2voltage domain (e.g., 0V), FETs M7, M8, and M9turn on, and FET M10turns off. Thus, the output signal V3is at a high logic level (e.g., 1.2V) in accordance with the VDD_1P2voltage domain. Conversely, when the first and second input signals V1and V2are at a high logic level in accordance with the VDD_1P2voltage domain (e.g., 1.2V), FETs M7, M8, and M9turn off, and FET M10turns on. Thus, the output signal V3is at a low logic level (e.g., 0V) in accordance with the VDD_1P2voltage domain. FIG.9illustrates a flow diagram of an example method900of voltage level shifting an input signal to generate an output signal in accordance with another aspect of the disclosure. The method900includes receiving, at a first input, a first input signal that varies in accordance with a first voltage domain in accordance with a first mode of operation (block910). Examples of means for receiving, at a first input, a first input signal that varies in accordance with a first voltage domain in accordance with a first mode of operation include the gate of FET M1in edge alignment circuit300, the gate of FET M6in edge alignment circuit400, and the gate of FET M8of edge alignment circuit800, as well as respective first inputs of edge alignment circuits215,240,720,730,740, and735. The method900further includes receiving, at a second input, a second input signal that varies in accordance with a second voltage domain in accordance with the first mode of operation, wherein the first voltage domain is different than the second voltage domain (block920). Examples of means for receiving, at a second input, a second input signal that varies in accordance with a second voltage domain in accordance with the first mode of operation, wherein the first voltage domain is different than the second voltage domain include the input to inverter310in edge alignment circuit300, the input to inverter410in edge alignment circuit400, and the input to the inverter810of edge alignment circuit800, as well as respective second inputs of edge alignment circuits215,240,720,730,740, and735. Additionally, the method900includes generating, at an output, a first output signal that varies in accordance with the second voltage domain in accordance with the first mode of operation, wherein the first output signal is based on the first and second input signals (block930). Examples of means for generating, at an output, a first output signal that varies in accordance with the second voltage domain in accordance with the first mode of operation, wherein the first output signal is based on the first and second input signals include inverter310of edge alignment circuit300, inverter410of edge alignment circuit400, and inverter810of edge alignment circuit800, as well as the edge alignment circuits215,240,720,730,740, and735. FIG.10illustrates a block diagram of an example wireless communication device1000in accordance with another aspect of the disclosure. The wireless communication device1000includes at least one antenna1060(e.g., an antenna array), a transceiver1050coupled to the at least one antenna1060, and an integrated circuit (IC) or system on chip (SOC)1010. The IC or SOC1010, in turn, includes one or more signal processing cores1020, and one or more input/output (I/O) drivers or circuits1030coupled to the transceiver. The one or more I/O circuits1030may include one or more edge alignment circuits implemented as previously discussed herein. Pursuant to a signal transmission application, the one or more signal processing cores1020may be configured to process a transmit baseband (BB) signal in a first voltage domain (e.g., a CX voltage domain). The one or more I/O circuits1030may be configured to upwards voltage level shift the transmit (BB) baseband signal to a second voltage domain (e.g., a PX voltage domain). The one or more I/O circuits1030may include one or more edge alignment circuits, for example, each implemented per edge alignment circuit400to perform the upwards voltage level shifting. The transmit baseband (BB) signal in the second voltage domain is provided to the transceiver1050, which is configured to generate a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to the at least one antenna1060for wireless transmission to one or more remote wireless devices. Pursuant to a signal reception application, the at least one antenna1060is configured to wirelessly receive a received RF signal from one or more remote wireless devices. The transceiver1050is configured to generate a received baseband (BB) signal in the second voltage domain based on the received RF signal. The one or more I/O circuits1030is configured to downwards voltage level shift the received baseband (BB) signal to generate the received baseband (BB) signal in the first voltage domain. The one or more I/O circuits1030may include one or more edge alignment circuits, for example, each implemented per edge alignment circuit300or800to perform the downwards voltage level shifting. The one or more signal processing cores1020may be configured to process the received baseband (BB) signal in the first voltage domain. The following provides an overview of aspects of the present disclosure: Aspect 1: An apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Aspect 2: The apparatus of aspect 1, wherein the first and second voltage rails are configured to receive first and second supply voltages in accordance with the second voltage domain, respectively. Aspect 3: The apparatus of aspect 1 or 2, wherein the first FET includes an n-channel metal oxide semiconductor (NMOS) FET. Aspect 4: The apparatus of aspect 3, wherein the NMOS FET and the first inverter are coupled in series in that order between the first voltage rail and the second voltage rail. Aspect 5: The apparatus of any one of aspects 1-4, wherein the second input signal varies between a first low logic voltage and a first high logic voltage in accordance with the second voltage domain, wherein the first supply voltage is substantially the same as the first high logic voltage, and wherein the second supply voltage is substantially the same as the first low logic voltage. Aspect 6: The apparatus of aspect 5, wherein the first input signal varies between a second low logic voltage and a second high logic voltage in accordance with the first voltage domain, wherein the second low logic voltage is substantially the same as the first high logic voltage. Aspect 7: The apparatus of aspect 1 or 2, wherein the first FET includes a p-channel metal oxide semiconductor (PMOS) FET. Aspect 8: The apparatus of aspect 7, wherein the first inverter and the PMOS FET are coupled in series in that order between the first voltage rail and the second voltage rail. Aspect 9: The apparatus of aspect 7 or 8, wherein the second input signal varies between a first low logic voltage and a first high logic voltage in accordance with the second voltage domain, wherein the first supply voltage is substantially the same as the first high logic voltage, and wherein the second supply voltage is substantially the same as the first low logic voltage. Aspect 10: The apparatus of aspect 9, wherein the first input signal varies between a second low logic voltage and a second high logic voltage in accordance with the first voltage domain, wherein the second high logic voltage is substantially the same as the first low logic voltage. Aspect 11: The apparatus of any one of aspects 1-10, wherein the first input signal is logically complementary to the second input signal. Aspect 12: The apparatus of any one of aspects 1-11, further including a latch coupled to the first output of the first inverter. Aspect 13: The apparatus of aspect 1, wherein the first gate of the first FET is configured to receive the first input signal, and the first inverter is configured to receive the second input signal and generate the first output signal in accordance with a first mode of operation. Aspect 14: The apparatus of aspect 13, wherein the first and second voltage rails are configured to receive first and second supply voltages in accordance with a third voltage domain, respectively. Aspect 15: The apparatus of aspect 13 or 14, further including: a second FET including a second gate configured to receive the first input signal in accordance with the first mode of operation, and a third input signal in accordance with the second mode of operation; and a second inverter including a second input coupled to the second gate of the second FET, and a second output coupled to first gate of the first FET. Aspect 16: The apparatus of aspect 15, wherein the second inverter is coupled to programmable third and fourth voltage rails configured to receive third and fourth supply voltages in accordance with the first voltage domain and the first mode of operation, and receive the first and second supply voltages in accordance with the second mode of operation. Aspect 17: The apparatus of aspect 15 or 16, wherein the first FET includes an n-channel metal oxide semiconductor (NMOS) FET, and wherein the second FET includes a p-channel metal oxide semiconductor (PMOS) FET. Aspect 18: The apparatus of any one of aspects 15-17, wherein the second FET is coupled between the first voltage rail and the first inverter. Aspect 19: The apparatus of any one of aspect 15-18, in accordance with the second mode of operation, the second gate of the second FET is configured to receive a third input signal that varies in accordance with the third voltage domain, and the first inverter is configured to receive a fourth input signal that varies in accordance with the third voltage domain and generate a second output signal that varies in accordance with the third voltage domain. Aspect 20: The apparatus of any one of aspects 15-19, wherein: the second FET is effectively disabled, and the second inverter and the first FET are enabled in accordance with the first mode of operation; and the second FET, the second inverter and the first FET are enabled in accordance with the second mode of operation. Aspect 21: A method, including: receiving a first input signal that varies in accordance with a first voltage domain in accordance with a first mode of operation; receiving a second input signal that varies in accordance with a second voltage domain in accordance with the first mode of operation, wherein the first voltage domain is different than the second voltage domain; and generating a first output signal that varies in accordance with the second voltage domain in accordance with the first mode of operation, wherein the first output signal is based on the first and second input signals. Aspect 22: The method of aspect 21, wherein the first input signal is logically complementary to the second input signal. Aspect 23: The method of aspect 21 or 22, wherein the first input signal varies between a first low logic voltage and a first high logic voltage in accordance with the first voltage domain, wherein the second input signal varies between a second low logic voltage and second high logic voltage in accordance with the second voltage domain, and wherein the second high logic voltage is substantially the same as the first low logic voltage. Aspect 24: The method of aspect 21 or 22, wherein the first input signal varies between a first low logic voltage and a first high logic voltage in accordance with the first voltage domain, wherein the second input signal varies between a second low logic voltage and second high logic voltage in accordance with the second voltage domain, and wherein the first high logic voltage is substantially the same as the second low logic voltage. Aspect 25: The method of any one of aspects 21-23, further including: receiving, at the first input, a third input signal that varies in accordance with a third voltage domain in accordance with a second mode of operation; receiving, at the second input, a fourth input signal that varies in accordance with the third voltage domain in accordance with the second mode of operation; and generating, at the output, a second output signal that varies in accordance with the third voltage domain in accordance with the second mode of operation, wherein the second output signal is based on the third and fourth input signals. Aspect 26: An apparatus, including: a voltage domain splitter including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, wherein the second and third signals are based on the first signal; a first edge alignment circuit configured to generate a fourth signal in the third voltage domain based on the second signal and a complementary of the third signal; and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on a complementary of the second signal and the third signal. Aspect 27: The apparatus of aspect 26, wherein the first edge alignment circuit includes: an n-channel metal oxide semiconductor field effect transistor (NMOS FET) including a gate configured to receive the second signal; and an inverter including an input configured to receive the complementary third signal, and an output configured to generate the fourth signal, wherein the NMOS FET and the inverter are coupled in series between first and second voltage rails associated with the third voltage domain. Aspect 28: The apparatus of aspect 26 or 27, wherein the second edge alignment circuit includes: an inverter including an input configured to receive the complementary second signal, and an output configured to generate the fifth signal; and a p-channel metal oxide semiconductor field effect transistor (PMOS FET) including a gate configured to receive the third signal, wherein the inverter and the PMOS FET are coupled in series between first and second voltage rails associated with the second voltage domain. Aspect 29: An apparatus, including: a voltage level shifter including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, wherein the second and third signals are based on the first signal; a first edge alignment circuit configured to generate a fourth signal in the third voltage domain based on the second signal and a complementary of the third signal; and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on a complementary of the second signal and the third signal. Aspect 30: The apparatus of aspect 29, wherein at least one of the first or second edge alignment circuit, includes: a field effect transistor (FET) including a gate configured to receive the second or third signal; and an inverter including an input configured to receive the third or second signal, and an output configured to generate the fourth or fifth signal, wherein the FET and the inverter are coupled in series between first and second voltage rails. The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. | 49,591 |
11942934 | DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS FIG.1is a circuit diagram of a specific example embodiment of a level converter according to the present invention. The level converter here comprises a p-channel MOSFET10(abbreviated below to “PMOS10”), the source terminal12of which is bypassed with a bulk terminal18of the PMOS10, as a result of which a source-gate voltage USGof the PMOS10is kept substantially constant. A gate terminal16of the PMOS10is connected to an input voltage connection30by way of which an input voltage UErelated to a ground potential M of the level converter is fed in, the level of which input voltage is raised by 2 V here using the level converter. An output voltage connection40of the level converter is connected to the source terminal12of the PMOS10and to a power supply connection50, and is equipped to provide the input voltage UEraised by 2 V by the level converter as output voltage UA. The power supply connection50is connected to a first connection of a constant current source60that provides a constant current I. For this, the constant current source60is connected to a second connection with a positive supply voltage VDD. The source terminal12is furthermore connected to a first connection of a reference voltage source80that provides a predefined constant reference voltage. A second connection of the reference voltage source80is connected to a first input terminal22of an impedance converter20. An output terminal26of the impedance converter20is connected to a drain terminal14of the PMOS10. The impedance converter20is equipped to keep a source-drain voltage USDof the PMOS10at a predefined value using the reference voltage. FIG.2shows a circuit diagram of a further specific embodiment of a level converter according to the present invention. It should be pointed out that, owing to the similarities between the specific embodiments of the level converter according to the present invention inFIGS.1and2, in order to avoid repetition only the differences between the two figures will be described below. The impedance converter20in the specific embodiment shown inFIG.2is implemented on the basis of a differential amplifier. The first input terminal of the impedance converter20thus corresponds here to a positive input terminal22of the differential amplifier. A second input terminal of the impedance converter corresponds to a negative input terminal24of the differential amplifier. The negative input terminal24of the differential amplifier is connected to a drain terminal14of the PMOS10. FIG.3shows a circuit diagram of an exemplary circuit arrangement for a differential voltage measurement on the basis of the level converter according to the present invention. The circuit arrangement is marked using the broken line inFIG.2and comprises a first level converter70and a second level converter75that are constructed identically and are arranged here in the immediate vicinity of each other in an integrated circuit. A positive input signal UEP, which is related to a negative input signal UEN, is fed into an input voltage connection30of the first level converter70. A negative input signal UEN, which is related to the positive input signal UEP, is fed into an input voltage connection30of the second level converter75. Both level converters70,75raise the input signals UEPand UENeach by the same value. By way of an output voltage connection40of the first level converter70, a correspondingly level-shifted positive output signal UAPis emitted which corresponds to a negative output signal UANof an output voltage connection40of the second level converter75. | 3,616 |
11942935 | DETAILED DESCRIPTION In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuitry associated with integrated circuits have not been shown or described in detail, to avoid unnecessarily obscuring descriptions of the embodiments. Unless the context requires otherwise, throughout the specification and claims which follow, the word “comprise” and variations thereof, such as, “comprises” and “comprising” are to be construed in an open, inclusive sense, that is as “including, but not limited to.” Further, the terms “first,” “second,” and similar indicators of sequence are to be construed as interchangeable unless the context clearly dictates otherwise. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its broadest sense, that is as meaning “and/or” unless the content clearly dictates otherwise. FIG.1is a block diagram of an integrated circuit100, according to one embodiment. The integrated circuit100includes a PLA102. As will be set forth in more detail below, the components of the PLA102cooperate to enable a high degree of flexibility in selecting clock signals for the PLA102. This high degree of flexibility enables programmers of the PLA102greater freedom in selecting how to program the PLA102. In a broad sense, the PLA102receives PLA input signals PLA IN and outputs PLA output signals PLA OUT. The PLA102includes an array of programmable logic cells110that can be programmed to process the PLA input signals PLA IN in order to generate PLA output signals PLA OUT. Accordingly, the PLA102receives input signals PLA IN and outputs PLA output signals PLA OUT based on the input signals PLA IN and the logical expressions corresponding to the programming of the logic cells110. Further details regarding the logic cells110are provided below. The integrated circuit100includes one or more input terminals106. The input terminals106are terminals by which input signals are received at the integrated circuit100from sources external to the integrated circuit100. The input terminals can include input pads or other types of terminals. The input signals can be digital signals or analog signals. The integrated circuit includes one or more subsystems108. The one or more subsystems108can correspond to other functional blocks of the integrated circuit100. The subsystems can include analog-to-digital converters, memory arrays, serial interfaces, or other types of subsystems that can generate output signals. The integrated circuit100includes one or more signal conditioners104. The signal conditioners104provide the PLA inputs PLA IN to the PLA102. Each signal conditioner104is coupled to either an input pad106or a subsystem108. The signal conditioner104receives an input signal and conditions the input signal for processing by the PLA102. The outputs of the signal conditioners104correspond to the PLA inputs PLA IN provided to the PLA102. Further details regarding the signal conditioners104are provided below. The integrated circuit100includes a PLA clock generator114. The PLA clock generator generates a PLA clock signal PCLK. The PLA clock signal PCLK may correspond to a global or default clock signal for the PLA102. The global clock signal PCLK may also be provided to the signal conditioners104. The shape of the data pulses received from the subsystems108may be unknown. If the input data signals from the subsystems108are not conditioned in some way, the programmable logic array102may not properly process the input data signals and, thus, may generate faulty or erroneous output data. Additionally, signals or data received at the input pads106may have characteristics that are unknown to the integrated circuit. For example, data signals may be passed to the input pads106in conjunction with clocks having frequencies and phases that are not known ahead of time to the integrated circuit100. Some of these data may be passed to the programmable logic array102. If the input data signals are not conditioned in some way, it may be difficult for the programmable logic array102to process the data and generate outputs that are error-free. The signal conditioners104may include circuitry for synchronizing the signals provided from the input terminals106and the subsystems108with the PLA clock signal PCLK. The signal conditioners104may also include filtering circuits. The filtering circuits can be programmed to filter out undesirable features in the signals received from the input terminals106and the subsystems108. Accordingly, the signal conditioners104prepare the signals received from the input terminals106and subsystems108for effective and efficient processing by the PLA102. The PLA102includes a plurality of logic cells110. Each logic cell110includes a plurality of inputs111, a plurality of direct outputs107, and a plurality of synchronized outputs109. The logic cells110may be arranged in rows and columns. Each input111may receive an input signal from the input of the PLA102, the direct outputs signals from the direct outputs107of the logic cells110of the PLA102, and the synchronized output signals from the synchronized outputs109of the logic cells110of the PLA102. The PLA102may include synchronized interconnects corresponding to signal lines that electrically connect the synchronized outputs109of the logic cells110to the inputs111of the logic cells110. In one embodiment, the synchronized interconnects may enable connecting the synchronized output of a logic cell to an input111of any of the logic cells110. The PLA may include direct interconnects corresponding to signal lines that electrically connect the direct outputs107of the logic cells110to the inputs111of the logic cells110. The direct and synchronized interconnects may include conductive vias, metal lines, and other metal interconnects formed in various layers of the integrated circuit100. In some cases, the direct and synchronized interconnects may include one or more switches that can selectively connect and disconnect the direct and synchronized interconnects. Each logic cell110receives a clock signal CLK. The clock signal CLK is utilized by a logic cell110to generate the synchronized output109of that logic cell110. In one embodiment, each logic cell110includes a flip-flop. The synchronized output109is generated by passing the direct output107to the data input terminal of the flip-flop. The data output terminal of the flip-flop outputs the synchronized output109. The clock input terminal of the flip-flop receives the clock signal CLK. Because the rising or falling edge of the synchronized output109is controlled by the rising or falling edge of the clock signal CLK, the synchronized output109is synchronized with the clock signal CLK. Other synchronization circuits and schemes can be utilized without departing from the scope of the present disclosure. In some cases, it may be beneficial to enable the logic cells110to utilize a clock signal CLK other than the global PLA clock signal PCLK. For this reason, the PLA102includes a plurality of clock selectors112. In one embodiment, there is a respective clock selector112for each logic cell110. Each clock selector112receives the global PLA clock signal PCLK. Each clock selector112also receives one or more of the signals provided to the inputs111of the logic cell110. As described previously, each logic cell receives a plurality of inputs including the PLA inputs PLA IN, direct outputs from other logic cells110, and synchronized outputs from the logic cells110. One or more of these inputs are provided to the clock selector112. The clock selector112selects one of the available signals to provide to the corresponding logic cell110. When a user programs the PLA102, the user can program the clock selector112to select a desired clock signal from the available clock signals. The clock signal CLK provided to a logic cell110corresponds to the selected clock signal for that logic cell110. Accordingly, it is possible that different logic cells110will select different signals for the clock signal CLK. In one embodiment, each clock selector112includes a multiplexer. The multiplexer receives a plurality of the signals received at the inputs111. The multiplexer also receives a control signal that determines which of the input signals will be provided at the output of the multiplexer. The output of the multiplexer may correspond to the selected clock signal CLK. Alternatively, the clock selector may utilize the output of the multiplexer to assist in generating the selected clock signal CLK. In one embodiment, each clock selector112includes both a multiplexer as described above, and a logic gate. The logic gate receives the output of the multiplexer and the global PLA clock signal PCLK. The logic gate outputs a clock signal CLK based on the output of the multiplexer and a global clock signal PCLK. Accordingly, the output of the clock selector112may be a clock signal CLK that is based on both the global clock signal PCLK and the signal output by the multiplexer. Various other schemes for generating the clock signal CLK can be utilized without departing from the scope of the present disclosure. FIG.2is a schematic diagram of a portion of a PLA102, according to one embodiment. WhileFIG.2illustrates a single row of three logic cells110, in practice, the PLA102may include a large number of logic cells110arranged in rows and columns. Each of the logic cells110has a plurality of inputs111. Each logic cell110provides a direct output107and a synchronized output109. The direct outputs107and the synchronized outputs109of each logic cell110are utilized as input signals of the logic cells110. The PLA102also receives PLA inputs PLA IN. The PLA inputs PLA IN are utilized as inputs111of the logic cells110. For simplicity, the direct outputs107are shown as connecting to a single interconnect line115. In practice, the interconnect line115represents each of the individual interconnects that connect the direct outputs107to the inputs of the logic cells110. Likewise, the synchronized outputs109are also shown as connecting to a single interconnect line117. However, the interconnect line117represents the individual distinct synchronized outputs109of each of the logic cells110. All of the direct outputs107and all of the synchronized outputs109can be utilized as PLA output signals PLA OUT. FIG.2illustrates that some of the input signals111are provided to the clock selectors112. In particular, one or more of the PLA inputs PLA IN and one or more of the synchronized outputs109are provided to the clock selectors112. The clock selector112also receives the global PLA clock signal PCLK. The direct outputs107are not provided to the clock selectors112. As described previously, each clock selector112outputs a clock signal CLK to the corresponding logic element110. The clock signal CLK can be generated based on one or more of the input signals provided to the clock selector112. The clock signal CLK may correspond to the global PLA clock signal PCLK, to one of the input signals111, or may be a signal based on the PLA clock signal PCLK and one of the inputs111. FIG.3is a schematic diagram of a logic cell110of a PLA102, according to one embodiment. The logic cell110ofFIG.3is one embodiment of a logic cell110that can be utilized for the logic cells110ofFIGS.1-2, and for subsequent figures. WhileFIG.3illustrates a specific embodiment of a logic cell110, other configurations of logic cells110can be utilized without departing from the scope of the present disclosure. The logic cells110includes a multiplexer122, a memory124, and a flip-flop126. The input side of the multiplexer122correspond to the input side of a logic cell110. In particular, the multiplexer122may have a plurality of inputs111. The inputs111can include synchronous outputs109of all of the logic cells110of a block. The inputs111can include the direct outputs107of all of the logic cells110. The inputs111can include one or more inputs of the PLA102. In practice there may be a large number of inputs. The multiplexer122provides a plurality of outputs. In the example ofFIG.3, the multiplexer122has four outputs. In this case, a control signal (not illustrated) is provided to the multiplexer122to determine which of the inputs111will be provided at the outputs of the multiplexer122. The multiplexer122can receive other numbers of inputs and can provide other numbers of outputs that are shown inFIG.3without departing from the scope of the present disclosure. In one embodiment, the memory124is a register with 16 data values d1-d16. Each data value may be a binary value of 0 or 1. The register outputs one of the data values d1-d16 depending on the combination of data values received from the multiplexer122. The outputs of the multiplexer122effectively correspond to an address for the memory124. If the multiplexer provides, on the four outputs, a value of 0000, then the memory124will output the value stored in d1. If the multiplexer provides, on the four outputs a value of 1111, then the memory124will output the value stored in d16. Accordingly, each four bit value received from the multiplexer122corresponds to one of the 16 data storage locations of the memory124. WhileFIG.3illustrates that the memory124is a register, other types of memories can be utilized for logic cell110without departing from the scope of the present disclosure. Programming the logic cells110includes selecting a value for each of the data values d1-d16 and writing the selected data values to the memory124. Programming of the logic cells110can also include selecting a value for the control signal provided to the multiplexer122. The value of the control signal determines which of the inputs111will be provided at the outputs of the multiplexer122. The logic cells110includes a flip-flop126. The flip-flop126receives, on a data input terminal, the output of the memory124. The data output terminal of the flip-flop126corresponds to the synchronized output109of the logic cell110. The logic cell110also includes a clock selector112. The clock selector112includes a multiplexer128and an AND gate130. The output of the multiplexer128is coupled to a first input of the AND gate130. A second input of the AND gate130receives the global PLA clock signal PCLK. The output of the AND gate130is coupled to the input of the clock terminal of the flip-flop126. The output of the AND gate130corresponds to the output of the clock selector112. The multiplexer128receives one or more of the inputs111of the flip-flop122. Accordingly, some of the signals that are provided to the inputs of the multiplexer122are provided to the inputs of the multiplexer128. In one embodiment, one or more of the PLA inputs PLA IN are provided to the multiplexer128. In one embodiment, one or more of the synchronized outputs109that are provided to the inputs of the multiplexer122are also provided to the inputs of the multiplexer128. In one embodiment, the direct outputs107are not provided to the inputs of the multiplexers128. The multiplexer128also receives an enable signal EN. Programming the logic cell110includes selecting the input of the multiplexer128that will be utilized as the output of the multiplexer128. The output of the multiplexer128helps determine the clock signal CLK. Accordingly, a programmer of the PLA102is able to select from various input signals to be utilized in shaping the clock signal CLK. The clock signal CLK is only high when the global PLA clock signal PCLK is high and when the output of the multiplexer128is high. Accordingly, the shape of CLK is based on both the global clock signal PCLK and the selected output of the multiplexer128. This provides great flexibility to programmers of the PLA102in selecting how the synchronized output109of a logic cell110will be generated. In one embodiment, the multiplexer128outputs the enable signal EN when it is desired to utilize the clock signal PCLK as the clock signal CLK. In this case, the enable signal EN is constantly in a high state such that the output of the AND gate130corresponds directly to the global PLA clock signal PCLK. The clock selector112can utilize logic gates other than AND gates without departing from the scope of the present disclosure. AlthoughFIG.3illustrates that the clock signal CLK is based on both the clock signal PCLK and a selected input signal, in practice, the clock signal CLK can be generated in other manners without departing from the scope of the present disclosure. For example, PCLK may be provided as an input to the multiplexer128. In this case, the output of the multiplexer128is connected to the clock input terminal of the flip-flop126. FIG.4is a block diagram of an integrated circuit100, according to one embodiment. The integrated circuit100includes a programmable logic block140, a controller142, and subsystems108. The programmable logic block140, the controller142, and the subsystems108are coupled together by a bus146. As will be set forth in more detail below, the programmable logic block140enables selection of either or both of the complex logic array and a simple logic array. The programmable logic block140includes a PLA102and the FPGA152. The PLA102corresponds to a simple programmable logic. The FPGA152corresponds to a complex programmable logic. Traditionally, an integrated circuit may include either PLA or an FPGA. However, the integrated circuit102includes a programmable logic block140that includes both a PLA102and an FPGA152. This enables programmers of the programmable logic block140great flexibility in programming the programmable logic block140. Programmers may utilize either or both of the PLA102and the FPGA152. The subsystems108can provide inputs to the programmable logic block140. The inputs may be provided to the programmable logic block140via the bus146or via other connections. The programmable logic block140may also receive inputs from the controller142. The programmable logic block140may also receive inputs from terminals of the integrated circuit100. Furthermore, the programmable logic block140may also utilize signal conditioners104as described in relation toFIG.1. The PLA102of the programmable logic block140may correspond substantially to a PLA102as described in relation toFIGS.1-3. Accordingly, the PLA102may include a plurality of logic cells110. Each logic cell110may include a multiplexer122, a programmable memory124, and a flip-flop126. Each logic cell110may generate a direct output107and the synchronized output109, as described previously. Other types of simple logic cells and arrays of logic cells110can be utilized for the PLA without departing from the scope of the present disclosure. The FPGA152may include an array of logic cells that is much more complex than the PLA102. In particular, each individual logic cell may include a plurality of programmable memories coupled together by switches. The switches may also be coupled to a large number of interconnection lines. The switches of the FPGA logic cell can determine which inputs are provided to each of the programmable memories and which outputs of the programmable memories are provided from the FPGA logic cells. The FPGA may also include switching nodes coupled to the FPGA logic cells. The switching nodes control which signals are passed through a large number of interconnections between the FPGA programmable memories. Programming the FPGA can include programming the switching nodes, programming the switches of the FPGA logic cells, and writing data to the programmable memories of the FPGA logic cells. The programmable logic block140includes an interface148. The interface148is coupled to both the PLA102and the FPGA152. The interface is coupled to the bus146. The interface can receive signals from the bus146and can pass the signals to the PLA102and the FPGA152. The interface can provide signals from the PLA102and the FPGA152to the bus146. The controller142can control the interface148. In particular, the controller142can be utilized to program the PLA102and the FPGA152via the interface148. Programming control signals are provided from the controller142to the interface148for programming the PLA102and the FPGA152. The interface140may also include registers150. The registers may store the program data for one or both of the PLA102and the FPGA152. In particular, programming the PLA102and FPGA152can include writing data to the registers150. The data in the registers150controls the programming of the FPGA152and the PLA102. The data written to the registers150can indicate when data is written to the logic cells110of the PLA102and which signals are utilized by the multiplexers of the logic cells110of the PLA102. Though not shown inFIG.4, input terminals106may also be coupled to the bus146via registers for providing input signals to the programmable logic block140. FIG.5is a schematic diagram of a programmable logic block140, according to one embodiment. The programmable logic block140ofFIG.5is one example of a programmable logic block140ofFIG.4. The programmable logic block140includes a PLA102and an FPGA152. The PLA102includes a plurality of logic cells110. Each logic cell110includes a multiplexer122, a programmable memory124, and a flip-flop126. Each logic cell110can operate substantially as described in relation toFIGS.1-3. The FPGA152includes a plurality of logic cells156. The logic cells156are connected to each other by interconnections160. The interconnections160extends between switches158. Each switch158may correspond to a group of switches. Signals are passed between the logic cells156through the interconnections160. The switches158control the connections between logic cells156. Interconnections160pass output signals from one logic cell156as input signals to other logic cells156. Programming of the FPGA152can include which switches158will be open and which switches158will be closed. Each logic cell156includes multiple programmable memories162. Each programmable memory162may be substantially similar to the programmable memories124of the logic cells110. In one example, each programmable memory162is a lookup table including a selected number of data values. Input signals are provided to the programmable memories162. The programmable memories162output data values based on the values of the input signals provided to them. Though not shown inFIG.5, each logic cell may also include a respective multiplexer upstream from each lookup table156. Each logic cell156includes a switch164. In practice, the switch164of each logic cell156represents a plurality of switches. The switches164determine which input signals are provided to the programmable memories156and which output signals are passed from the programmable memories156. Various other configurations of FPGA logic cells156, interconnections160and switches158and164can be utilized without departing from the scope of the present disclosure. The architecture of the FPGA152is substantially more complex than the architecture of the PLA102. As one example, each logic cell156of the FPGA includes multiple programmable memories162and multiple switches164that can be programmed to provide complex interconnections schemes to the programmable memories162and to the other logic cells156. In contrast, each logic cell110of the PLA102includes only a single programmable memory124and multiplexer122that provides input signals to the programmable memory124. The PLA input signals PLA IN can include signals provided from the bus146to the PLA102. In particular, input signals PLA IN can be passed via the bus146to the interface148of the programmable logic block140(seeFIG.4). The input signals PLA IN are then passed through signal conditioners104and on to the PLA102. The PLA102outputs PLA output signals PLA OUT. The PLA output signals PLA OUT can be passed to the bus146via the interface148. The FPGA152receives FPGA input signals FPGA IN. The FPGA input signals FPGA IN can include signals provided from the bus146to the FPGA152via the interface148. Though not shown inFIG.5, there may be additional signal conditioners that process the FPGA input signals FPGA IN before passing into the FPGA152. The FPGA input signals FPGA IN can include signals from input terminals of the integrated circuit100and from other subsystems108of the integrated circuit100. The FPGA152outputs FPGA output signals FPGA OUT after processing the FPGA input signals FPGA IN in accordance with the programmed logic of the FPGA152. The PLA102and the FPGA152can be programmed via the controller142. The controller142can pass programming signals or data to the interface148. The interface148programs the PLA102and the FPGA152in accordance with the programming signals. Programming the PLA102can include configuring registers150of the interface148. The values written to the registers150determine the program logic of the PLA102. The FPGA152may be programmed in a similar manner or in a different manner. In one embodiment, the FPGA152is programmed by passing the single bit stream of programming data to the FPGA to configure the data values in the programmable memories162and to configure the switches158and164. In one embodiment, the FPGA152can be programmed by configuring registers150. The interface148may include first registers dedicated to the PLA102and second registers dedicated to the FPGA152. Beneficially, a single interface148can be utilized to access and program both the PLA102and the FPGA152. The FPGA152may receive the global PLA clock signal PCLK. Alternatively, the FPGA152may receive different clock signals. The PLA102can include clock selectors112as described in relation toFIGS.1-3. The FPGA152may also include circuitry for enabling flexible selection of clock signals. FIG.6is a flow diagram of a method600for operating an integrated circuit. The method600can utilize processes, systems, and components described in relation toFIGS.1-5. At602, the method600includes receiving a plurality of input signals at a first logic cell of a programmable logic array. At604, the method600includes receiving a global clock signal at a first input of a logic gate. At606, the method600includes receiving a selected input signal of the plurality of input signals at a second input of the logic gate. At608, the method600includes supplying a clock signal from the logic gate to a clock input terminal of a flip-flop of the first logic cell. FIG.7is a flow diagram of a method700for operating an integrated circuit. The method700can utilize processes, systems, and components described in relation toFIGS.1-5. At702, the method700receiving a plurality of input signals at a logic cell of a programmable logic array. At704, the method700includes generating, with the logic cell, a direct output signal based on the plurality of input signals. At706, the method700includes generating, with the logic cell, a synchronized output signal by passing the direct output signal through a flip-flop of the logic cell. At708, the method includes passing, to a clock-input terminal of the flip-flop, a first clock signal based on a selected input signal from the plurality of input signals. FIG.8is a flow diagram of a method800for operating an integrated circuit. The method800can utilize processes, systems, and components described in relation toFIGS.1-5. At802, the method800includes providing first input signals to a programmable logic array of a programmable logic block of an integrated circuit. At804, the method800includes generating first output signals with the programmable logic array based on the first input signals. At806, the method800includes providing second input signals to a field programmable gate array of the programmable logic block. At808, the method800includes generating second output signal with the field programmable gate array based on the second input signals. FIG.9is a flow diagram of a method900for operating an integrated circuit. The method900can utilize processes, systems, and components described in relation toFIGS.1-5. At902, the method900providing first programming signals to an interface of a programmable logic block. At904, the method900includes providing second programming signals to the interface. At906, the method900includes configuring, with the interface, a programmable logic array of the programmable logic block based on first programming signals. At908, the method900includes configuring, with the interface, a field programmable gate array of the programmable logic block based on the second programming signals. In one embodiment, a method includes receiving a plurality of input signals at a first logic cell of a PLA and receiving a global clock signal at a first input of a logic gate. The method includes receiving a selected input signal of the plurality of input signals at a second input of the logic gate and supplying a clock signal from the logic gate to a clock input terminal of a flip-flop of the first logic cell. In one embodiment, a method includes receiving a plurality of input signals at a logic cell of a PLA and generating, with the logic cell, a direct output signal based on the plurality of input signals. The method includes generating, with the logic cell, a synchronized output signal by passing the direct output signal through a flip-flop of the logic cell and passing, to a clock-input terminal of the flip-flop, a first clock signal based on a selected input signal from the plurality of input signals. In one embodiment, an integrated circuit includes a PLA. The PLA includes an array of logic cells. A first logic cell of the array of logic cells include a first multiplexer configured to receive a plurality of input signals and a programmable memory coupled to the first multiplexer and configured to provide a direct output based on the plurality of input signals. The first logic cell includes a flip-flop configured to provide a synchronized output signal and a logic gate having an output coupled to a clock input terminal of the flip-flop, a first input that receives a global clock signal, and a second input that receives a selected input signal from the plurality of input signals. In one embodiment, an integrated circuit includes a programmable logic block including a PLA, an FPGA, and an interface coupled to the array of programmable logic cells. In one embodiment, a method includes providing first input signals to a programmable logic array of a programmable logic block of an integrated circuit and generating first output signals with the programmable logic array based on the first input signals. The method includes providing second input signals to a FPGA of the programmable logic block and generating second output signal with the FPGA based on the second input signals. In one embodiment, a method includes providing first programming signals to an interface of a programmable logic block and providing second programming signals to the interface. The method includes configuring, with the interface, a PLA of the programmable logic block based on first programming signals and configuring, with the interface, a FPGA of the programmable logic block based on the second programming signals. The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. | 32,776 |
11942936 | In the drawings, reference signs can be omitted as is consistent with accepted engineering practice; however, a skilled person will understand that the illustrated components are readily understood when viewed in the context of the illustration as a whole and the accompanying disclosure describing such various figures. DETAILED DESCRIPTION The Figures and Detailed Description signify, only to provide knowledge and understanding, the claimed inventions. To minimize the length of the Detailed Description, while various features, structures, or characteristics can be described together in a single embodiment, they also can be used in other embodiments without being written about. The Figures and Detailed Description also can signify, implicitly or explicitly, advantages and improvements of the claimed inventions and their embodiments. In the Figures and Detailed Description, numerous specific details can be described to enable at least one embodiment of the claimed inventions. Any embodiment disclosed herein signifies a tangible form of a claim invention. To not obscure the significance of the embodiments and/or examples in this Detailed Description, some elements that are known to a skilled person can be combined together for presentation and for illustration purposes and not be described in detail. To not obscure the significance of these embodiments and/or examples, some well-known processes, machines, systems, manufactures, or compositions are not written about in detail. Thus, the Detailed Description focuses on enabling the distinctive elements of the claimed inventions and exemplary embodiments. Where this Detailed Description refers to some elements in the singular tense, more than one element can be depicted in the Figures, and like elements are labeled with like numerals. In this disclosure, various embodiments based on the ERSFQ (Energy Efficient RSFQ) approach are detailed as a lower-power SFQ derivative. This has approximately an order of magnitude less power consumption than is possible with standard RSFQ. DETAILED DESCRIPTION—RSFQ BIASING CIRCUITRY FIG.1illustrates a method of powering rapid single flux quantum (RSFQ) circuitry.FIG.1illustrates an RSFQ circuit100with a dropping resistor102and a bias voltage source106. Due to the dropping resistor102, the RSFQ circuit100has a high power dissipation. The bias voltage source106, as shown inFIG.1, is connected to the dropping resistor102, which is connected to a Josephson junction104. Even though, only one instance of the dropping resistor102and the Josephson junction104are shown inFIG.1, the RSFQ circuit may have a plurality of similar Josephson junction104, each connected with a dropping resistor similar to the dropping resistor102. By way of non-limiting example, for the RSFQ circuit100, the bias voltage source106may be provided off-chip. The time-averaged voltage across Josephson junction104may range from 0 volts, when the Josephson junction is not switching at all, to a voltage proportional to the system clock frequency when the Josephson junction pulses on every clock cycle. The average voltage across a Josephson junction depends on the frequency of pulsing with a proportionality constant that is twice the electron charge divided by Planck's constant, or about 500 MHz per microvolt. Accordingly, the bias current is obtained from the voltage source106through use of a dropping resistor102. The values of the voltage source106and the dropping resistor102specify the biasing current. For the RSFQ circuit100, the average voltage across the dropping resistor102may vary according to the switching probability of the Josephson junction104and may cause the bias current supplied to the Josephson junction104to change correspondingly. The change of the bias current through the Josephson junction104may cause spurious triggering or lack of an expected triggering. Accordingly, to prevent the spurious triggering or lack of the expected triggering, the bias source voltage106may be required to be at least ten times higher than the voltage corresponding to the system clock frequency. Accordingly, the dropping resistor104may dissipate at least 90 percent of chip power as heat in a very low-temperature environment. DETAILED DESCRIPTION—JOSEPHSON JUNCTION AS A CURRENT SOURCE In some embodiments, by way of non-limiting example, a Josephson junction as a current source may be used as a constant current bias to the circuit junction. In this case, when the on-chip voltage is kept low, the total power dissipation may be lower compared to using the dropping resistor102. By way of non-limiting example, the total power dissipation may be about ten times lower than the total power dissipation with the dropping resistor. FIG.2illustrates current-voltage (I-V) characteristics of a shunted Josephson junction as a current source, in accordance with some embodiments. The current source is evident from the I-V characteristic of the shunted Josephson junction that shows average current changes are very small compared to voltage changes, as shown inFIG.2by202. In other words, a ratio of a difference in current to a difference in voltage (di/dv) is almost zero when the voltage across the Josephson junction as the current source is kept low. Accordingly, the power dissipation is kept low, while the current flowing through the Josephson junction may be controlled to be the same as the critical current required for the Josephson junction. In addition to the constant DC current, there will be a large AC current, which may be filtered out to prevent interfering of the circuit being biased. The AC current may be filtered out by inductance placed in series with the Josephson junction. FIG.3illustrates a simulation of a Josephson current source element, in accordance with some embodiments. The simulation of the Josephson current source element may be performed using a circuit simulator. One example of such a circuit simulator may be WRspice Circuit Simulator from Whiteley Research Inc. The circuit simulator may accept as an input circuit description using Simulation Program with Integrated Circuit Emphasis (SPICE) specification language. As shown inFIG.3, the Josephson junction302being biased is connected to a constant voltage source304. Another voltage source (308), which may be time-varying, is used to model the Josephson junction anticipated as the load. The voltage across the voltage source308may be changing so that an effect of the voltage change across the junction may be simulated. By way of non-limiting example, the voltage of the other voltage source308may change from 0 volt to 18 microvolts and back, and the voltage of the voltage source304may be 20 microvolts. Accordingly, an average voltage across the Josephson current source may change by a factor of 10, in this case. FIG.4shows a current graph402that indicates the current through the current source at point306and a voltage graph404that indicates the voltage measured at point308. As shown inFIG.4, long ramp-up406is due to a filter inductor310, for example, of value 1 nanoHenry, charging up from the voltage source304. As shown inFIG.4, the bias current may contain ripple408of about 1 percent, which is shown as zoomed-in ripple410. However, the bias current ripple408,410may be reduced by using a large inductance filter. FIG.5illustrates an example of feeding JTL regulating voltage on bias line.FIG.5shows a feeding JTL502, a bias line504, a ground plane506, a JTL clock508, and logic circuitry510. The feeding JTL502is driven by the JTL clock508. The JTL clock508may be in addition to a system clock, and the frequency of the JTL clock508may set the voltage across the feeding JTL and bias voltage for the bias line504. However, any benefit of precise voltage regulation by the feeding JTL502using conventional techniques may be outweighed by the complexity and additional power dissipation of the feeding JTL502. The feeding JTL is used to establish a known reference voltage from which to power the SFQ circuitry, however as shown below this can be replaced by a more efficient approach. DETAILED DESCRIPTION—JOSEPHSON JUNCTION AS A CURRENT SOURCE WITH A RESISTOR TO GROUND InFIG.6, the feeding JTL502may be removed and replaced by a resistor602, according to some embodiments. Such replacement of the feeding JTL502by the resistor602may free substantial circuit area, since none of the JTL clock508and associated inductors502athrough502hare needed. By way of non-limiting example, each bias feed point may have an added resistor to ground, and approximately 10 percent of the overall chip bias current may flow through a plurality of resistors to ground. The plurality of resistors to the ground may provide a well-defined bias voltage when the chip is biased by a relatively high impedance source. Further, the on-chip voltage may not be clamped as it generally occurs in the feeding JTL, rather the on-chip voltage may vary with the changing bias current. The voltage across the resistor602is the “excess” current not consumed by a Josephson junction current source608times the value of the resistance. Since the resistor602is in parallel to the Josephson junction and the bias line, the on-chip voltage may be provided according to the expectations by adjusting the bias current. Even though the feeding JTL and the embodiments described herein, both may use resistors as part of the biasing network, the embodiments described herein differ from the feeding JTL. For example, the feeding JTL may use dropping resistors102, which appear in series with the Josephson junction104. The values of the dropping resistors may be high and may cause the dropping resistors to appear as a current source to the load. On the other hand, in biasing circuitry described herein with reference to various embodiments, an actual current source may be provided, and resistors with small resistance to the ground may be used to control the voltage at the feed point. Because only a small amount of current may be needed to flow through these resistors to ground, the power dissipation is small. By way of non-limiting example, the power dissipation through the resistors to the ground may be approximately 10 percent of the total power dissipation. Further, the resistor to ground602used in the embodiments is of very small value compared to the dropping resistor104. Therefore, the resistor to the ground used in the embodiments may require substantially less circuit area. Thus, the resistor to ground to drain the excess current may allow using the Josephson junction current source to replace the functionality of dropping resistor. In some embodiments, when the feeding JTL502is replaced by a resistor to ground602, about 25 percent of the Josephson junctions required by an ERSFQ logic chip may be eliminated. Along with the elimination of the Josephson junctions, associated inductors may also be eliminated, which may free up substantial chip area for additional circuitry and functionality, or a small die size may be used for the chip minimizing the overall circuit. FIG.7illustrates current and voltage characteristics for the electrical structure ofFIG.6, according to an exemplary embodiment of the present disclosure. As described above, the feeding JTL502may provide precise regulated voltage, but requires more circuit area. In comparison to the feeding JTL502, the voltage measured at points504and506shows that the voltage at points604and606may not be as precise as available using the feeding JTL502. However, a lack of precise voltage control is not known to be associated with any adverse effect during testing. This is because the system power supply regulator may provide and control the power needed to accommodate the system clock frequency. Also, current flow measured at points612and614for each bias feed branch, and voltage measured at points604and604are shown as graphs702,704,706, and708, respectively, inFIG.7. A zoomed-in version of graphs702,704,706, and708are also shown as710,712,714, and716, respectively. As described above, the current ripple shown in710and712remains less than 1 percentage. In other words, the current flow remains constant across the Josephson junctions616and618. The current flow remains constant even in the presence of excess inductance, for example, inductors620and622placed to simulate a bias line, which may be a narrow and meandering strip in the chip layout. Further, as seen from voltage graphs706and708, or714and716, the time required to charge the inductors up to their quiescent currents is significantly reduced. Based on the above disclosure, in some embodiments, a parameterized power distribution point cell may be designed for use in Electronic Design Automation (EDA) systems. FIG.8illustrates four power distribution point cells, in accordance with some embodiments. As shown inFIG.8, four power distribution point cells802,804,806, and808simulate the circuit load. Each power distribution point cell802,804,806, and808may include a current source Josephson junction, for example,802a,804a,806a, and808a, the filter inductor for example,802b,804b,806b, and808b), and a resistor to the ground, for example,802c,804c,806c, and808c. The value of resistor to the ground and the junction critical current are set by the cell parameter, which is the current delivered by the power distribution cell. There is no additional circuitry required for the power distribution system, and the actual inductance of the power supply lines on-chip810,812, and814can be incorporated into the schematic. FIG.9illustrates characteristics of voltage over time for the electrical structure ofFIG.8, according to an exemplary embodiment of the present disclosure. Simulation and measurement of current at points816,818,820, and822, and voltage at points824,826,828, and830shown inFIG.9as902,904,906,908,910,912,914, and916, respectively, which may be consistent with similar current and voltage characteristics, for example, shown inFIG.7. Finally, a logic circuit based on the embodiments disclosed herein may require much less circuit area since it requires much fewer components and circuitry in comparison to a logic circuit with the feeding JTL. Further, since at least 25 percentage of Josephson junctions may be eliminated, and the overall cost of the logic circuit may be reduced while increasing yield. Data and Information. While ‘data’ and ‘information’ often are used interchangeably (e.g., ‘data processing’ and ‘information processing’), the term ‘datum’ (plural ‘data’) typically signifies a representation of the value of a measurement of a physical quantity (e.g., the current in a wire), or the answer to a question (e.g., “yes” or “no”), while the term ‘information’ typically signifies a structured set of data (often times signified by ‘data structure’). A specified data structure is used to structure an electronic device to be used as a specific machine as an article of manufacture. Data and information are physical, for example, binary data (a ‘bit,’ usually signified with ‘0’ and ‘1’) enabled with two different levels of voltage in a circuit. For example, data can be enabled as an electrical, magnetic, optical, or acoustical signal; a quantum state such as spin that enables a ‘qubit’; or a physical state of an atom or molecule. All such data and information, when enabled, are stored, accessed, transferred, combined, compared, or otherwise acted upon, actions that require energy. As used herein, the term ‘process’ signifies an unnatural sequence of physical actions and/or transformations (both also referred to as ‘operations’ or ‘steps’) to produce at least one result. The actions and transformations are technical applications of one or more natural laws of science or unnatural laws of technology. The actions and transformations often change the physical state of a machine, of structures of data and information, or of a composition of matter. Two or more actions can occur at about the same time, or one action can occur before or after another action if they produce the same result. A description of the physical actions and/or transformations that comprise a process are often signified with a set of gerund phrases (or their semantic equivalents) that are typically preceded with the signifier ‘the steps of’ (e.g., “a process comprising the steps of measuring, transforming, partitioning and then distributing . . . ”). As used herein, the term ‘component’ (also signified by ‘part,’ and typically signified by ‘element’ when described in a patent text or diagram) signifies a physical object that is used to enable a process in combination with other components. For example, electronic components are used in processes that affect the physical state of one or more electromagnetic or quantum particles/waves (e.g., electrons, photons) or quasiparticles (e.g., electron holes, phonons, magnetic domains) and their associated fields or signals. Electronic components have at least two connection points to which are attached ‘leads,’ typically a conductive wire or an optical fiber, with one end attached to the component and the other end attached to another component, typically as part of a circuit with current flows. There are at least three types of electrical components: passive, active, and electromechanical. Passive electronic components typically do not introduce energy into a circuit—such components include resistors, memristors, capacitors, magnetic inductors, crystals, Josephson junctions, transducers, sensors, antennas, waveguides, etc. Active electronic components require a source of energy and can inject energy into a circuit—such components include semiconductors (e.g., diodes, transistors, optoelectronic devices), vacuum tubes, batteries, power supplies, displays (e.g., LEDs, LCDs, lamps, CRTs, plasma displays). Electromechanical components affect current flow using mechanical forces and structures—such components include switches, relays, protection devices (e.g., fuses, circuit breakers), heat sinks, fans, cables, wires, terminals, connectors, and printed circuit boards. As used herein, the term ‘netlist’ is a specification of the components comprising an electric circuit, and electrical connections between the components. The programming language for the SPICE circuit simulation program is often used to specify a netlist. In the context of circuit design, the term ‘instance’ signifies each time a component is specified in a netlist. As used herein, the term ‘integrated circuit’ signifies a set of connected electronic components on a small substrate (thus the use of the signifier ‘chip’) of semiconductor material, such as silicon or gallium arsenide, with components fabricated on one or more layers. Other signifiers for ‘integrated circuit’ include ‘monolithic integrated circuit,’ ‘IC,’ ‘chip,’ ‘microchip,’ and ‘System on Chip’ (‘SoC’). Examples of types of integrated circuits include gate/logic arrays, processors, memories, interface chips, power controllers, and operational amplifiers. The term ‘cell’ as used in electronic circuit design signifies a specification of one or more components, for example, a set of transistors that are connected to function as a logic gate. Cells are usually stored in a database, to be accessed by circuit designers and design processes. As used herein, the term ‘module’ signifies a tangible structure for acting on data and information. For example, the term ‘module’ can signify a process that transforms data and information, for example, a process comprising a computer program. The term ‘module’ also can signify one or more interconnected electronic components, such as digital logic devices. A process comprising a module, if specified in a programming language, such as SystemC or Verilog, also can be transformed into a specification for a structure of electronic components that transform data and information that produce the same result as the process.” A module is permanently structured (e.g., circuits with unalterable connections), temporarily structured (e.g., circuits or processes that are alterable with sets of data), or a combination of the two forms of structuring. Permanently structured modules can be manufactured, for example, using Application-Specific Integrated Circuits (‘ASICs’) such as Arithmetic Logic Units (‘ALUs’), Programmable Logic Arrays (‘PLAs’), or Read Only Memories (‘ROMs’), all of which are typically structured during manufacturing. For example, a permanently structured module can comprise an integrated circuit. Temporarily structured modules can be manufactured, for example, using Field Programmable Gate Arrays (FPGAs—for example, sold by Xilinx or Intel's Altera), Random Access Memories (RAMs) or microprocessors. For example, data and information are transformed using data as an address in RAM or ROM memory that stores output data and information. One can embed temporarily structured modules in permanently structured modules (for example, an FPGA embedded into an ASIC). Modules that are temporarily structured can be structured during multiple time periods. For example, a processor comprising one or more modules has its modules first structured by a manufacturer at a factory and then further structured by a user. The processor can comprise a set of one or more modules during a first time period, and then be restructured to comprise a different set of one or modules during a second time period. The decision to manufacture or implement a module in a permanently structured form, in a temporarily structured form, or in a combination of the two forms, depends on issues such as cost, time considerations, resource constraints, tariffs, maintenance needs, national intellectual property laws, and/or specific design goals. How a module is used is mostly independent of the physical form in which it is manufactured or enabled. This last sentence also follows from the modified Church-Turing thesis. As used herein, the term ‘processor’ signifies a tangible data and information processing machine that physically transforms, transfers, and/or transmits data and information, using at least one process. A processor consists of one or more modules (e.g., a central processing unit, ‘CPU,’ an input/output (′I/O′) controller, a memory controller, a network controller, and other modules). The term ‘processor’ can signify one or more processors, or one or more processors with multiple computational cores/CPUs, specialized processors (for example, graphics processors or signal processors), and their combinations. Where two or more processors interact, one or more of the processors can be remotely located. Where the term ‘processor’ is used in another context, such as a ‘chemical processor,’ it will be signified and defined in that context. The processor can comprise, for example, digital logic circuitry (for example, a binary logic gate), and/or analog circuitry (for example, an operational amplifier). The processor also can use optical signal processing, DNA transformations or quantum operations, microfluidic logic processing, or a combination of technologies, such as an optoelectronic processor. For data and information structured with binary data, any processor that can transform data and information using the AND, OR, and NOT logical operations (and their derivatives, such as the NAND, NOR, and XOR operations) also can transform data and information using any function of Boolean logic. A processor such as an analog processor, such as an artificial neural network, also can transform data and information. No scientific evidence exists that any of these technological processors are processing, storing, and retrieving data and information, using any process or structure equivalent to the bioelectric structures and processes of the human brain. The one or more processors also can use a process in a ‘cloud computing’ environment, where time and resources of multiple remote computers are shared by multiple users or processors communicating with the computers. For example, a group of processors can use at least one process available at a distributed or remote system, these processors using a communications network (e.g., the Internet, or an Ethernet) and using one or more specified interfaces (e.g., an application program interface (API′) that signifies functions and data structures to communicate with the remote process). As used herein, the term ‘computer’ and ‘computer system’ (further defined below) includes at least one processor that, for example, performs operations on data and information such as (but not limited to) the AND, OR and NOT logical operations using electronic gates that can comprise transistors, with the addition of memory (for example, memory structured with flip-flops using the NOT-AND or NOT-OR operation). Such a processor is Turing-complete and computationally universal. A computer can comprise a simple structure, for example, comprising an I/O module, a CPU, and a memory that performs, for example, the process of inputting a signal, transforming the signal, and outputting the signal with no human intervention. As used herein, the term ‘programming language’ signifies a structured grammar for specifying sets of operations and data for use by modules, processors, and computers. Programming languages include assembler instructions, instruction-set-architecture instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more higher-level languages, for example, the C programming language and similar general programming languages (such as Fortran, Basic, Javascript, PHP, Python, C++), knowledge programming languages (such as Lisp, Smalltalk, Prolog, or CycL), electronic structure programming languages (such as VHDL, Verilog, SPICE or SystemC), text programming languages (such as SGML, HTML, or XML), or audiovisual programming languages (such as SVG, MathML, X3D/VRML, or MIDI), and any future equivalent programming languages. As used herein, the term ‘source code’ signifies a set of instructions and data specified in text form using a programming language. A large amount of source code for use in enabling any of the claimed inventions is available on the Internet, such as from a source code library such as GitHub. As used herein, the term ‘program’ (also referred to as an ‘application program’) signifies one or more processes and data structures that structure a module, processor or computer to be used as a “specific machine.”. One use of a program is to structure one or more computers, for example, standalone, client or server computers, or one or more modules, or systems of one or more such computers or modules. As used herein, the term ‘computer application’ signifies a program that enables a specific use, for example, to enable text processing operations, or to encrypt a set of data. As used herein, the term ‘firmware’ signifies a type of program that typically structures a processor or a computer, where the firmware is smaller in size than a typical application program and is typically not very accessible to or modifiable by the user of a computer. Computer programs and firmware are often specified using source code written in a programming language, such as C. Modules, circuits, processors, programs, and computers can be specified at multiple levels of abstraction, for example, using the SystemC programming language. A program is transferred into one or more memories of the computer or computer system from a data and information device or storage system. A computer system typically has a device for reading storage media that is used to transfer the program and/or has an interface device that receives the program over a network. FIGS.11A and11Bare diagrams of example computer systems suitable for enabling embodiments of the claimed inventions. InFIG.11A, the structure of a computer system1110typically includes at least one computer1114, which communicates with peripheral devices via bus subsystem1112. Typically, the computer includes a processor (e.g., a microprocessor, graphics processing unit, or digital signal processor), or its electronic processing equivalents, such as an Application Specific Integrated Circuit (‘ASIC’) or Field Programmable Gate Array (‘FPGA’). Typically, peripheral devices include a storage subsystem1124, comprising a memory subsystem1126and a file storage subsystem1128, user interface input devices1122, user interface output devices1120, and/or a network interface subsystem1116. The input and output devices enable direct and remote user interaction with the computer system1110. The computer system enables significant post-process activity using at least one output device and/or the network interface subsystem. The computer system can be structured as a server, a client, a workstation, a mainframe, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a web appliance, a rack-mounted ‘blade,’ a kiosk, a television, a game station, a network router, switch or bridge, or any data processing machine with instructions that specify actions to be taken by that machine. The term ‘server,’ as used herein, refers to a computer or processor that typically performs processes for, and sends data and information to, another computer or processor. A computer system typically is structured, in part, with at least one operating system program, such as Microsoft's Windows, Sun Microsystems's Solaris, Apple Computer's macOS and iOS, Google's Android, Linux and/or Unix. The computer system typically includes a Basic Input/Output System (BIOS) and processor firmware. The operating system, BIOS, and firmware are used by the processor to structure and control any subsystems and interfaces connected to the processor. Typical processors that enable these operating systems include the Pentium, Itanium, and Xeon processors from Intel; the Opteron and Athlon processors from Advanced Micro Devices; the Graviton processor from Amazon; the POWER processor from IBM; the SPARC processor from Oracle; and the ARM processor from ARM Holdings. The claimed inventions and their embodiments are limited neither to the electronic digital logic computer structured with programs nor to an electronically programmable device. For example, the claimed inventions can use an optical computer, a quantum computer, an analog computer, or the like. Further, where only a single computer system or a single machine is signified, the use of a singular form of such terms also can signify any structure of computer systems or machines that individually or jointly use processes. Due to the ever-changing nature of computers and networks, the description of computer system1110depicted inFIG.11Ais intended only as an example. Many other structures of computer system1110have more or fewer components than the computer system depicted inFIG.11A. Network interface subsystem1116provides an interface to outside networks, including an interface to a communication network1118, and is coupled via communication network1118to corresponding interface devices in other computer systems or machines. Communication network1118can comprise many interconnected computer systems, machines, and physical communication connections (signified by ‘links’). These communication links can be wireline links, optical links, wireless links (e.g., using the Wi-Fi or Bluetooth protocols), or any other physical devices for communication of information. Communication network1118can be any suitable computer network, for example, a wide area network such as the Internet and/or a local-to-wide area network such as Ethernet. The communication network is wired and/or wireless, and many communication networks use encryption and decryption processes, such as is available with a virtual private network. The communication network uses one or more communications interfaces, which receive data from and transmit data to other systems. Embodiments of communications interfaces typically include an Ethernet card, a modem (e.g., telephone, satellite, cable, or ISDN), (asynchronous) digital subscriber line (DSL) unit, Firewire interface, USB interface, and the like. Communication algorithms (‘protocols’) can be specified using one or communication languages, such as HTTP, TCP/IP, RTP/RTSP, IPX, and/or UDP. User interface input devices1122can include an alphanumeric keyboard, a keypad, pointing devices such as a mouse, trackball, toggle switch, touchpad, stylus, a graphics tablet, an optical scanner such as a bar code reader, touchscreen electronics for a display device, audio input devices such as voice recognition systems or microphones, eye-gaze recognition, brainwave pattern recognition, optical character recognition systems, and other types of input devices. Such devices are connected by wire or wirelessly to a computer system. Typically, the term ‘input device’ signifies all possible types of devices and processes to transfer data and information into the computer system1110or onto communication network1118. User interface input devices typically enable a user to select objects, icons, text, and the like that appear on some types of user interface output devices, for example, a display subsystem. User interface output devices1120can include a display subsystem, a printer, a fax machine, or a non-visual communication device such as audio and haptic devices. The display subsystem can include a cathode ray tube (CRT), a flat-panel device such as a liquid crystal display (LCD), an image projection device, or some other device for creating visible stimuli such as a virtual reality system. The display subsystem also can provide non-visual stimuli such as via audio output, aroma generation, or tactile/haptic output (e.g., vibrations and forces) devices. Typically, the term ‘output device’ signifies all possible types of devices and processes to transfer data and information out of computer system1110to the user or to another machine or computer system. Such devices are connected by wire or wirelessly to a computer system. Note: some devices transfer data and information both into and out of the computer, for example, haptic devices that generate vibrations and forces on the hand of a user while also incorporating sensors to measure the location and movement of the hand. Technical applications of the sciences of ergonomics and semiotics are used to improve the efficiency of user interactions with any processes and computers disclosed herein, such as any interactions with regards to the design and manufacture of circuits that use any of the above input or output devices. Memory subsystem1126typically includes a number of memories including a main random-access memory (‘RAM’)1130(or other volatile storage devices) for storage of instructions and data during program execution and a read-only memory (ROM′)1132in which fixed instructions are stored. File storage subsystem1128provides persistent storage for program and data files and can include a hard disk drive, a floppy disk drive along with associated removable media, a CD-ROM drive, an optical drive, a flash memory such as a USB drive, or removable media cartridges. If computer system1110includes an input device that performs optical character recognition, then text and symbols printed on paper can be used as a device for storage of program and data files. The databases and modules used by some embodiments can be stored by file storage subsystem1128. Bus subsystem1112provides a device for transmitting data and information between the various components and subsystems of computer system1110. Although bus subsystem1112is depicted as a single bus, alternative embodiments of the bus subsystem can use multiple busses. For example, a main memory using RAM can communicate directly with file storage systems using Direct Memory Access (DMA′) systems. FIG.11Bdepicts a memory1140such as a non-transitory, processor-readable data and information storage medium associated with file storage subsystem1128, and/or with network interface subsystem1116, and can include a data structure specifying a circuit design. The memory1140can be a hard disk, a floppy disk, a CD-ROM, an optical medium, removable media cartridge, or any other medium that stores computer-readable data in a volatile or non-volatile form, such as text and symbols on paper that can be processed by an optical character recognition system. In some examples, the memory1140may include a plurality of cells1180to store data. A program transferred in to and out of a processor from such a memory can be transformed into a physical signal that is propagated through a medium (such as a network, connector, wire, or circuit trace as an electrical pulse); or through a medium such as space or an atmosphere as an acoustic signal, or as electromagnetic radiation with wavelengths in the electromagnetic spectrum longer than infrared light). FIG.10depicts a set of processes1000used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. Each of these processes can be structured and enabled as multiple modules. The term ‘EDA’ signifies the term ‘Electronic Design Automation.’ These processes start with the creation of a product idea1010with information supplied by a designer, information that is transformed to create an article of manufacture that uses a set of EDA processes1012. When the design is finalized, it is taped-out1034, which typically is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is manufactured1036, and packaging and assembly processes1038are performed to produce the finished integrated circuit. Specifications for a circuit or electronic structure are as used in multiple levels of useful abstraction ranging from low-level transistor material layouts to high-level description languages. Most designers start with a description using one or more modules with less detail at a high-level of abstraction to design their circuits and systems, using a hardware description language (‘HDL’) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The high-level description is easier for designers to understand, especially for a vast system, and can describe very complex systems that are difficult to understand using a lower level of abstraction that is a more detailed description. The HDL description can be transformed into other levels of abstraction that are used by the developers. For example, a high-level description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower abstraction level that is a less abstract description adds more useful detail into the design description, for example, more details for the modules that comprise the description. The lower-levels of abstraction that are less abstract descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction language for specifying more detailed descriptions is SPICE, which is much used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction are enabled for use by the corresponding tools of that layer (for example, a formal verification tool), and some of the modules of the abstractions need not be novel or unobvious. A design process that uses EDA processes1012includes processes1014to1032, which are described below. This design flow description is used only to illustrate, not to limit. For example, a designer of an integrated circuit can use the design processes in a different sequence than the sequence depicted inFIG.10. For the embodiments disclosed herein, products from Synopsys, Inc. of Mountain View, California (hereinafter signified by ‘Synopsys’), are used to enable these processes, and/or similar products from other companies. During system design1014, a designer specifies the functionality to be manufactured. The designer also can optimize the power, performance, and area (physical and/or lines of code) and minimize costs, etc. Partitioning of the design into different types of modules can occur at this stage. Exemplary EDA products from Synopsys that enable system design1014include the Model Architect, Saber, System Studio, and DesignWare products. During the logic design and functional verification1016, modules in the circuit are specified in one or more description languages, and the specification is checked for functional accuracy, that is, that the modules produce outputs that match the requirements of the specification of the circuit or system being designed. Exemplary HDL languages are Verilog, VHDL, and SystemC. Functional verification typically uses simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some situations, special systems of modules referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification. Exemplary EDA products from Synopsys that can be used at this stage include VCS, Vera, DesignWare, Magellan, Formality, ESP, and Leda products. Exemplary emulator and prototyping products available from Synopsys that enable logic design and functional verification1016include ZeBu® and Protolink® (® signifies ‘Registered Trademark’). During synthesis and design for test1018, HDL code is transformed to a netlist (which typically is a graph structure where the edges represent components of a circuit and where the nodes represent how the components are interconnected). Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to its design. This netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit is tested to verify that it satisfies the requirements of the specification. Exemplary EDA products from Synopsys that enable synthesis and design for the test include the Design Compiler, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, TetraMAX, and DesignWare products. During netlist verification1020, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. Exemplary EDA products from Synopsys that enable netlist verification1020include the Formality, Primetime, and VCS products. During design planning1022, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing. Exemplary EDA products from Synopsys that enable design-planning1022include the Astro and IC Compiler products. During layout implementation1024, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions. As used herein, the term ‘cell’ signifies a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit ‘block’ comprises two or more cells. Both a cell and a circuit block can be referred to as a module, and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products. Examples of databases that can be used for accessing cells include MySQL and PostgreSQL. Exemplary EDA products from Synopsys that enable layout implementation include the Astro and IC Compiler products. During analysis and extraction1026, the circuit function is verified at the layout level, which permits refinement of the layout design. Exemplary EDA products from Synopsys that enable analysis and extraction include the Astrorail, Primerail, Primetime, and Star RC/XT products. During physical verification1028, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification. Exemplary EDA products from Synopsys that enable physical verification1028include the Hercules product. During resolution enhancement1030, the geometry of the layout is transformed to improve how the design is manufactured. Exemplary EDA products from Synopsys that enable resolution enhancement1030include theProteusproduct. During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for the production of lithography masks. Example EDA products from Synopsys that enable tape-out include the IC Compiler and Custom Designer products. During mask-data preparation1032, the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits. Exemplary EDA products from Synopsys that enable mask-data preparation1032include the CATS family of products. For all of the abovementioned EDA products, similar products from other EDA vendors, such as Cadence, Siemens, other corporate entities, or various non-commercial products from universities, or open-source repositories, can be used as an alternative. A storage subsystem of a computer system (such as computer system1110ofFIG.11A) is preferably used to store the programs and data structures that are used by some or all of the EDA products described herein, and products used for development of cells for the library and for physical and logical design that use the library. Based on the teachings contained in this disclosure, it may be apparent to persons skilled in the relevant art(s) how to make and use embodiments of this disclosure using data processing devices, computer systems and/or computer architectures other than that shown inFIG.11A. In particular, embodiments may operate with software, hardware, and/or operating system implementations other than those described herein. It is to be appreciated that the Detailed Description section, and not any other section, is intended to be used to interpret the claims. Other sections may set forth one or more but not all exemplary embodiments as contemplated by the inventor(s), and thus, are not intended to limit this disclosure or the appended claims in any way. The Detailed Description and any corresponding figures may signify, only to provide knowledge and understanding. To minimize the length of the Detailed Description, while various features, structures or characteristics may be described together in a single embodiment, they also can be used in other embodiments without being written about. While this disclosure describes exemplary embodiments for exemplary fields and applications, it should be understood that the disclosure is not limited thereto. Other embodiments and modifications thereto are possible, and are within the scope and spirit of this disclosure. For example, and without limiting the generality of this paragraph, embodiments are not limited to the software, hardware, firmware, and/or entities illustrated in the figures and/or described herein. Further, embodiments (whether or not explicitly described herein) have significant utility to fields and applications beyond the examples described herein. Embodiments have been described herein with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined as long as the specified functions and relationships (or equivalents thereof) are appropriately performed. Also, alternative embodiments may perform functional blocks, steps, operations, methods, etc. using orderings different from those described herein. References herein to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” or similar phrases, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of persons skilled in the relevant art(s) to incorporate such feature, structure, or characteristic into other embodiments whether or not explicitly mentioned or described herein. Additionally, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. | 50,109 |
11942937 | DETAILED DESCRIPTION The computational functions of an RQL system can be at least in part performed by operative digital circuitry that can include logic gates and JTLs. This operative circuitry includes JJs that are biased by the one or more biasing signals of the RQL system, which can include both AC and DC bias signals, the AC signals of which can function as one or more clocks for the RQL system to synchronize data and/or provide a time-based flow of the logic functions of the RQL system. The AC biasing signals can provide clocks of different phases, such as a 0° clock or a 180° clock, sourced from an I clock resonator, or a 90° clock or a 270° clock, sourced from a Q clock resonator. The operative circuitry may operate correctly only within certain margins of various operating parameters. Some of these operating parameters are related to the biasing signals (e.g., clocks) provided to the RQL system. For example, if the DC bias level of a clock is too high or too low, and is thus outside of the DC bias operating margins of a gate or JTL within the RQL system, the RQL system may malfunction. As another example, if the AC bias signal of a clock is of an amplitude that is too large or too small, and is thus outside the AC bias operating margins of a gate or JTL within the RQL system, this can be another cause of RQL malfunction. As yet another example, if the relative phase difference of different clocks, such as an I clock and a Q clock, is too large or too small and falls outside the clock phase difference operating margins of a gate or JTL within the RQL system, this can be another cause of RQL malfunction. Flux, the time integral of voltage, be it applied to conventional inductor or a JJ, is the primary operating parameter governing the function of RQL logic circuits. Due to fabrication process variations, among other factors, there can be considerable variation in the AC and DC flux produced by resonators and the tap transformers that couple to them, which transformers, in turn, supply bias signals to RQL logic circuits. Variations in inductors, dielectrics, and JJs that make up operational RQL circuits cause variations in the amount of AC and DC flux needed by those circuits. Variations in temperature can affect performance of RQL circuits, as can aging. Considering these changes and variations, the ideal values of bias parameters such as AC amplitude, DC value, and gate flux bias currents may not be the same for every RQL logic gate in a system. Whereas the one or more clock signals provided to the RQL system may be generated by function generator circuitry operating at about room temperature (approximately 300 K), the RQL operative circuitry of the system may reside inside of a cryogenic cold space that operates much colder, e.g., at around 4 K or below, and may be meters away from the function generator circuitry. Because of the low operating temperature and thermal sequestration requirements of the RQL system, it may not be possible to directly probe an integrated circuit (IC) on which an RQL system is implemented to ascertain the biasing signal parameters (DC level, AC amplitude, relative phase difference of AC clock signals, etc.) at various points on the IC in order to check that the bias signal parameters actually supplied to the RQL operative circuitry are those intended to be supplied, or otherwise are within the operating margins of the operative circuitry. Measurement of provided bias levels, e.g., the AC voltage and DC currents, and other bias parameters, such as relative phase difference between different bias signals, as provided on an RQL integrated circuit, can provide insight necessary to adjust bias levels, as generated at a bias source outside of the cold space, to assure that the delivered bias levels and other parameters as delivered to the operational RQL circuitry inside the cold space align with optimum values that are within the operating margins of the operational RQL circuitry, e.g., at the center of the operating margins of the operational RQL circuitry. Results of measurements for each RQL IC, or portions of each IC, can be used to adjust bias levels to improved, optimal, or near-optimal values, thus providing more reliable performance of the operational RQL circuitry. Bias-level sensors can thus be provided as sensing circuitry fabricated on an RQL IC along with the operative circuitry of the RQL system. The bias-level sensors can sense the signal parameters of the bias signals provided to the operative circuitry at various locations on the IC. The sensed signal parameters can be used in a manual or automatic feedback loop to inform adjustment of the bias signals provided to the RQL system, so that the operative circuitry of the RQL system is provided with biasing that stays within the operative circuitry's operating margins. In some examples, a number of bias-level sensors can be embedded within a logic circuit, referred to herein as a wrapper, that activates the bias-level sensors, e.g., by interrogating them with a sampling signal, and reads out their results. As examples, the sensors can be embedded in an RQL scan register or JTL testbed register. In some examples, bias-level-sensing circuit architectures and related methods described in this application enable the determination of improved, near-optimal, or optimal bias levels by observing pulses created by an ensemble of bias-level sensing circuits. Example bias-level sensing circuits, which can be referred to as samplers, act as surrogates for the operational RQL circuitry. The samplers can be configured in ensemble such that when elements of the operational RQL circuitry are at their optimal bias points, a certain fraction of the samplers are operational, or certain individual one(s) of the samplers are operational to transmit or produce bias-level-sensing output pulses in an expected manner, and others of the samplers are not operational to transmit or produce bias-level-sensing output pulses in the expected manner. Which and how many samplers generate bias-level-sensing output pulses reveals information relating to the present biasing of the operational RQL circuitry, e.g., the present bias point of the operational RQL circuitry. Digital logic can be utilized to count, reorder, and/or categorize the bias-level-sensing output pulses, and search and optimization algorithms can be used to adjust the bias signal generation parameters (e.g., bias levels), to improve the delivered bias levels and/or to bring the operating point nearer to its optimum. Operating-margin offsets of the bias-level sensors, from nominal operating margins of operational RQL circuitry, can in some examples permit bias-level measurements to be made without stopping the operational RQL circuitry. As one example, bias transformer flux can be altered from its normal level to ensure that the bias sensing circuits provide a useful output without having to move bias levels beyond the range over which the operational RQL circuitry is functional. One way of altering bias transformer flux is to provide bias-level sensors with transformers configured to produce greater-than-normal or less-than-normal flux by altering their mutual inductance to a clock resonator. Another way of altering bias transformer flux is to insert more or less than the nominal amount of inductance between the transformer and the bias-level sensor. As another example, specialized bias sensing circuits can be configured to go in and out of operation at levels within the operating range of the logic circuits. This can be done by increasing or decreasing the sizes of JJs and inductors in the circuit. If the performance of the bias transformers and the clock resonator to which they are coupled is of greatest interest, directly driving a JJ from a standard transformer may be preferred, because only the variability of the JJ adds to the variability of the resonator and transformers. If the needs of the logic circuits vis-à-vis the outputs of the clock resonator and the bias transformers is of interest, it may be convenient to utilize sensing circuits that differ minimally from the operational circuits. This latter objective can be achieved by adding extra inductance in series with the transformers, while keeping the transformers and the rest of the logic sensing circuits in standard configuration. The operating-margin offsets can differ from one bias-level sensor to another in an ensemble of such sensors that can be collected within wrapper circuitry configured to provide bias level measurement sampling inputs and outputs. Inter-sensor variations of operating-margin offsets can be intentionally induced by design (staged), for example, to cover a range centered about the nominal operating point of the operational RQL circuitry. In such a case, the ensemble of bias-level sensors can be configured that a certain proportion of the bias-level sensors (e.g., about half of the bias-level sensors) produce pulses when the operational logic is optimally biased in terms of AC amplitude. Thus, the AC amplitude bias level, relative to the needs of the operational RQL circuitry, can be determined by counting the pulses generated by the ensemble. In other examples, element spread in the operating levels of the bias-level sensors caused by fabrication process variation can be used to provide pulse-count sensing output effectively equivalent to that using the staged sensors described above, without intentional staging of bias-level sensor operating-margin offsets. This is because when bias to the sensors is such that they are on the edge of functionality when the operational circuits are optimally biased, even without designing for intentional staging of the sensors' margins, the operational RQL circuitry is near its optimal bias condition when around half of the bias-level sensors are biased within their own operating margins and thus produce sensing pulses when interrogated with a sample signal via the wrapper circuitry. FIG.1shows an example RQL bias level sensing and adjustment system100. Operational RQL circuitry102, such as may include JTLs and logic gates, can be fabricated along with associated one or more clock resonators104on an IC106as a chip that can be enclosed in a cryogenic cold space configured to be brought down to RQL operating temperatures, e.g., in the low single-digit kelvins or below. The term “operational RQL circuitry” as used herein means logic circuits and associated infrastructure circuitry used to perform the useful computational action for which the RQL IC106or system is designed, as distinct from circuitry118on the RQL IC106used to perform sensing of parameters associated with bias signals provided to the RQL IC106. The bias-level sensors and wrapper118can be provided as spatially distributed on the IC106(e.g., throughout the space on the IC also occupied by the operational RQL circuitry) to improve accuracy of bias-level measurement. The operational circuitry102is coupled (e.g., inductively coupled) to the one or more clock resonators104via a number of taps108to provide AC biasing to the operational circuitry102. The operational circuitry can also be coupled to a number of DC bias lines124to provide DC biasing to the operational circuitry102. In some examples, DC bias lines124can be configured to circulate about through the clock resonators104to control the amount of DC bias that is applied to the operational RQL circuitry102and/or bias-level sensors118. In some examples, each bias tap108or120can have an AC transformer coupled to a rib or ribs of a clock resonator104in series with another transformer coupled to a DC bias line124. Outside of the cold space, a bias signal generator110(or multiple such bias signal generators, e.g., different signal generators to provide I clock bias, Q clock bias, and various DC bias signals) can generate one or more clock signals, such as I clock112and Q clock114, for provision to the operational circuitry102via the clock resonators104and associated taps108in the cold space. The one or more bias signal generators110can also generate DC bias signals for provision to the operational circuitry102on the IC106over DC bias lines124. The one or more clock signals and/or DC bias signals generated by the clock signal generator110can be based on different bias parameters116, which can be of the form of adjustable or variable settings provided to or stored in the bias signal generator110. Such bias parameters can include, as examples, a clock frequency, AC amplitudes for any AC clocks generated (e.g., I and Q clocks), or one or more DC values for DC biases generated, and a phase difference between the Q clock and an I clock at the point of clock generation (which can nominally be about 90°, but in some cases are not exactly 90°). Bias-level sensors118can also be fabricated on the same IC106as the operational RQL circuitry102and can be configured to sample the one or more biasing signals (AC clocks and/or DC bias signals) provided by the one or more resonators104via a number (N) of sampling taps120, and/or via the DC bias lines124. The bias-level sensors can be configured within a wrapper that can be used to introduce a sampling signal to the bias-level sensors118and to output a signal based on the sampling signal that is indicative of the measurements of the various clock parameters taken by the bias-level sensors. Such parameters can include any or all of those listed above (parameters116) as used to generate the clock signals outside of the cold space by the clock signal generator110. The output of the bias-level sensors and/or an associated sensor wrapper118can be used to adjust, via feedback loop122, the parameters provided to the clock signal generator110, such that the AC clocks and/or DC bias signals as provided at the operational RQL circuitry102can be assured to provide biasing that meets the margin requirements of the operational RQL circuitry102. In some examples, RQL bias level sensing and adjustment system100can provide the bias feedback and adjustment without necessitating the deactivation or otherwise the rendering inoperative of the operational RQL circuitry102. FIG.2Ashows an example arrangement200of RQL bias-level sensors202-212wrapped in a JTL-based RQL scan register bias-level sensor wrapper used to provide as a serial output what otherwise might be a parallel output of a possibly very large number of bias-level sensors. The bias-level sensors202-212, also referred to herein as samplers, can be considered as residing on rungs of a ladder formed by the sensor wrapper. One such rung is labeled214inFIG.2A. The rails of the ladder can be formed by JTLs216-238, illustrated inFIG.2Aas triangles, or other circuitry configured to propagate SFQ pulses through the wrapper structure with an inter-rung propagation delay. Although the example ofFIG.2Ais illustrated as having one rail JTL between each ladder rung, each JTL216-238can be configured with one or as many repeating RQL JTL circuit structures as may be desired to produce one or a number of AC clock cycles of SFQ signal propagation delay. The bias-level sensors202-212can take a number of different forms, and can be configured to measure any of a number of different parameters, including AC bias signal amplitude, DC bias value, and inter-clock phase. Depending on the form of the bias-level sensors202-212, the rungs can also include suppression logic (SL)240-250configured to prevent multiple output pulse assertions from being propagated out of a rung, should an associated sampler be in a state of flipping spontaneously due to a fabrication defect or over-bias. Some examples may omit suppression logic240-250on any or all rungs of the wrapper. The wrapper can also include an input transformer252configured to provide to the wrapper a sample signal consisting of at least one input SFQ pulse supplied from positive and negative input nodes INP and INN. The wrapper can also include an output amplifier254configured to output a voltage signal between positive and negative output nodes OUTP and OUTN. Output amplifier254can, for example, take the form of a binary vine tree of JTLs (not shown) configured to split an incoming SFQ signal for provision into a number of stacked DC SQUIDs (e.g., four DC SQUIDs) arranged as a voltage summer. In the example arrangement200ofFIG.2A, a sample signal provided as an SFQ pulse via input transformer252propagates along the upper rail from the proximal end toward the distal end of the wrapper ladder and splits along the rungs of the ladder to produce multiple time-separated output voltage pulses at the ladder output between output nodes OUTP, OUTN. Because each rail JTL216-238produces an inter-rung propagation delay of at least one AC clock cycle, the output pulses are spaced apart in time, with the earlier-arriving output pulses being those that have propagated through the more proximal rungs of the wrapper ladder (those closer to the input/output end of the wrapper ladder) and the later-arriving output pulses being those that have propagated through the more distal rungs of the wrapper ladder (those further away from the input/output end of the wrapper ladder). Precisely how many output pulses are produced for a given sample input pulse depends on the number of the samplers202-212that are functional by virtue of the provided bias signal(s) being within the operating margins of the individual samplers202-212. As described in greater detail below, in some examples, the samplers202-212can be fabricated to have margins that are intentionally staged in, for example, AC bias amplitude XAC, DC bias value XDC, or inter-clock phase difference Xphase. The “X” in this nomenclature refers to a multiplier of a nominal bias level. For example, if a nominal bias level is 0.2 V, an actual applied bias level of 0.22 V has an X of 1.1 (110%). In other examples, the sensing system can rely on fabrication process variations to provide samplers202-212that have margins that are spread (vary over a range) without having intentionally designed staging. In some examples, such as the example200illustrated inFIG.2A, the first and final rungs of the wrapper ladder (the most proximal and most distal rungs) can be JTLs256,258fed with standard biases (that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6), such that the first and final pulses provided at the output of the wrapper are indicative of the margins of standard devices, for comparison with margins of samplers202-212. Pulses generated by standard-bias JTLs256,258provide pulses that serve to mark the beginning and the end of the pulse train that is generated when an input pulse is provided at INP/INN. Other examples, not shown, can have additional standard-JTL rungs at other rung locations interspersed along the wrapper ladder. Logic, e.g., room-temperature semiconductor logic (not shown), can evaluate the output of each sampler202-212individually, or can use the total number of functional samplers (each represented by its pulse) as a measurement of the global bias for the sensing system. As described in greater detail below, introducing a gradation in the bias level sensed by the bias-level sensors202-212that are included in the rungs of the RQL scan register200results in an output that quantifies or digitizes the sensed bias parameter either by producing a number of output pulses in the output pulse stream that is proportional to the bias parameter being sensed, or by producing output pulses the output timing of which is indicative of the bias parameter being sensed. FIG.2Bshows an example arrangement260of RQL bias-level sensors262-272arranged with parallel output. Arrangement260is similar to the RQL scan register arrangement200ofFIG.2A, except that output is provided in parallel rather than in serial. Parallel-output arrangement260can also include suppression logic (SL)280-290configured to prevent multiple output pulse assertions from being propagated out of each output, should an associated sampler be in a state of flipping spontaneously due to a fabrication defect or over-bias. Each bias-level sensor262-272can be situated at different locations on RQL IC106and can tap one or more bias resonators104at a different point along the resonator(s)104via bias coupling transformers (not shown inFIG.2C). An advantage of the serial-output arrangement ofFIG.2Aover the parallel-output arrangement ofFIG.2Bis that the arrangement ofFIG.2Acan in some examples conserve I/O on the RQL IC106. In some examples, the parallel outputs OUTA-OUTZ ofFIG.2Bcan be provided to a built-in self-test (BIST) readable register implemented on RQL IC106for storage and later readout in serial or parallel fashion. FIG.2Cshows an example arrangement290of bias-level sensors (each labeled BLS) arranged as a ring oscillator. The number of bias-level in the ring oscillator can be arbitrarily large. The output of one bias-level sensor serves as the sample signal input for the next bias-level sensor in the ring. Each bias-level sensor can be situated at different locations on RQL IC106and can tap one or more bias resonators104at a different point along the resonator(s)104via bias coupling transformers (not shown inFIG.2C). Although not shown inFIG.2C, bias-level sensors in the ring290can be interspersed with conventional JTLs on the ring to facilitate propagation of SFQ pulses between bias-level sensors in the ring. In ring arrangement290ofFIG.2C, an initial sampling assertion signal (an SFQ pulse or reciprocal pulse pair) can be provided on input RINGIN. The sampling pulse or pulse pair can propagate around the ring indefinitely so long as all of the bias-level sensors are operational (so long as the provided bias point is within the operating region of all of the bias-level sensors in the ring)290. When the bias parameters are adjusted such that the provided bias parameters are outside of the operating region of any one bias-level sensor in the ring, the entire ring “breaks” in that the sampling signal no longer propagates around the ring but instead stops at the first inoperative bias-level sensor it reaches. The continued operationality of the ring can be checked via output RINGOUT, which, under conditions of full ring operation, generates an SFQ pulse stream (or stream of reciprocal pulse pairs) at a rate that is related to the size of the ring (one output pulse or pulse pair per revolution of the sample pulse around the ring), and ceases output when the ring breaks due to a bias parameter adjustment. As described in greater detail below, XAC, XDC, and Xphaseparameters can be scanned (iteratively adjusted) in an optimization procedure. The minimum XAClevel at which the ring oscillator still functions to produce the output at RINGOUT results in optimal bias for operational RQL circuitry102. In some examples, more than one input sample pulse at a time can be provided to an operational ring, e.g., by multiple pulses separated in time, resulting in an increased output pulse frequency. In each of the above examples ofFIGS.2A-2C, the bias-level sensors can be JTL-based bias-level sensors as described with regard toFIGS.6,8A,9A,10A,11A,12,13,16, and18, PML flip-flop-based bias-level sensors as described with regard toFIG.25, pulse-generator-based bias-level sensors as described with regard toFIG.25, or other types of bias-level sensor suitable for arrangement in serial, parallel, or ring output configurations. Different bias-level sensors in the same arrangement can be configured to sense any or all of XAC, XDC, Xphase, or other bias parameters. Combinations of operating margins of RQL circuitry can be described by a shmoo plot. For example, the AC and DC operating margins can be described by a two-dimensional shmoo plot. The graph300ofFIG.3shows a first example shmoo plot302representing nominal AC and DC bias level operating margins for operational RQL circuitry102and a second example shmoo plot304representing the average of AC and DC bias level operating margins304for RQL bias-level sensors (e.g., samplers202-212). The operating margins302of operational RQL circuitry, when represented in the XDC, XACspace, have a well-defined corner308, referred to herein as a lower limit or as XACmin, where the AC clock amplitude is minimized in the respective margin shmoo plot302. Because the lower limit (XACmin) of a sampler is a unique point in the XDC, XACspace of a sampler's margin shmoo plot, it can be used to provide an unambiguous measurement of both XACand XDCfor the sampler. Within the center of the nominal margin shmoo plot302(e.g., at the centroid or geometric center of the nominal margin shmoo plot302) resides an optimal bias point306for the operational RQL circuitry, a unique point in the XDC, XACspace of the margin shmoo plot302. Samplers (e.g., samplers202-212) can be designed and staged such that the lower limit (XACmin) of an average of the margin shmoo plots304of the samplers is in the middle of the margin shmoo plot of nominal operational RQL circuitry102, at the optimal bias point306, as shown inFIG.3. One or more parameters of the biasing signals (e.g., clocks, DC biases) provided (e.g., via one of input lines112,114,124inFIG.1) to the operational RQL circuitry102, such as a DC value or AC amplitude, can be adjusted until outputs of the bias-level sensor wrapper are consistent with a desired, improved, or ideal biasing condition. For example, the operational RQL circuitry102can be said to be ideally biased in terms of the AC and DC parameters of the provided clock when the AC amplitude and DC level parameters are set such that only the proximal half of the XACsamplers of a linearly staged set of XACsamplers return output pulses (as shown inFIG.4C) and such that only one or several of the middle XDCsamplers of a linearly staged set of XDCsamplers return output pulses (as shown inFIG.5C). Setting the lower-limit point of the samplers' shmoo304to be at about the optimal bias point306of the operational circuitry shmoo302can be accomplished, by way of example, by setting of the self inductance and/or DC mutual inductance (for XACor XDCsamplers, respectively) by which the sampler JTLs are provided the corresponding bias signal to be measured. Setting the lower-limit point of the samplers' shmoo304to be at about the optimal bias point306of the operational circuitry shmoo302can be accomplished, by way of another example, by setting of one or more of the AC mutual inductances by which the sampler JTLs are provided one or more AC bias signals or, as another example, by inserting self-inductance between the JTL and the transformers (tap). An optimization procedure such as the procedure2800illustrated inFIG.28can be used to calibrate a bias signal, e.g., to an ideal calibration or close to an ideal calibration. When the samplers are configured with their lower limits at about the optimal bias point306, the optimization procedure2800can be carried out such that the adjusted parameters of the clock(s) and/or DC bias signals remain within the operating margins of the operational RQL circuitry102, meaning that the bias signal calibration can be performed while the operational RQL circuitry remains continuously in operation even while its bias parameters are being adjusted, improved, or optimized. The graph400ofFIG.4Ashows example shmoo plots302,404of nominal AC and DC bias level operating margins for operative RQL circuitry102and for AC bias-level sensors (XACsamplers), respectively. Graph400includes margins404for eight XACsamplers, but the number of XACsamplers can, in some examples, be less than or greater than eight. The graph400, viewed along with the one-dimensional time plots ofFIGS.4B-4D, illustrates the performance of an example XACoptimization method that can be carried out without interruption of the operation of operational RQL circuitry102having nominal operating margins302. The AC amplitude of a provided bias signal can be varied, in effect shifting a bias point vertically up and down on the graph400, until the optimal AC bias point4C is determined. The XACsamplers can, for example, have bias transformers with varying values of self-inductance to produce varying offsets in AC response and nominal DC mutual inductance. Increased self-inductance between a JTL of an XACsampler and its respective sampler tap of bias lines can have a further beneficial effect of preventing the XACsampler from flipping spontaneously, as clock amplitude is raised, before the operational RQL circuitry102does. An ensemble of XACsamplers can be configured such that the lower limits of their respective margin shmoo plots are centered about the bias point306initially deemed or assumed optimal for operation of the operational RQL circuitry102. As shown inFIG.4A, the lower limits of the XACsampler margin shmoo plots are centered near the middle of the nominal operational RQL circuitry margin shmoo plot302. FIGS.4B-4Dshow output pulse receipts, or non-receipts, for an example bias-level sensor wrapper like the one ofFIG.2Awhen it is provided with XACsamplers as its bias-level sensors202-212. In the illustrated example, the XACsamplers are arranged in the wrapper in order of the level by which their shmoo plots have been shifted upward in the XDC-XACspace. Samplers having shmoo plots least elevated in the XDC-XACspace are placed near the proximal end of the bias-level sensor wrapper and those having shmoo plots most elevated in the XDC-XACspace are placed near the distal end of the bias-level sensor wrapper. The broken-line patterns of the output pulses inFIGS.4B-4Dcorrespond to the same broken-line patterns of the margin shmoo plots404ofFIG.4A, in that a pulse of a certain broken-line pattern inFIGS.4B-4Dis one created by an XACsampler having margins drawn with the same broken-line pattern inFIG.4A.FIGS.4B-4Dthus show the wrapper output effect of change in AC amplitude of provided bias signals as illustrated inFIG.4A. When the provided AC bias is too low, the AC bias point4B is too low to be within the operating margins of most of the XACsamplers. Accordingly, the number of returned output pulses are comparatively few, as shown inFIG.4B. For example, as illustrated inFIG.4B, the output pulses returned can be limited to the earlier pulse returns, provided the XACsamplers are staged in order (e.g., linearly), with those configured to have the lowest AC operating margins placed most proximally to the input/output end of the wrapper shown inFIG.2A. By contrast, when the provided AC bias is too high, the AC bias point4D is too high to be within the operating margins of most of the XACsamplers. Accordingly, the number of returned output pulses are comparatively many, as shown inFIG.4D. For example, as illustrated inFIG.4B, the output pulses returned, can include the earlier pulse returns as well as some later pulse returns, again provided the XACsamplers are staged linearly, with those configured to have the highest AC operating margins placed most distally to the input/output end of the wrapper shown inFIG.2A. The provided AC bias4C can, for example, be deemed optimal when the number of returned output pulses is at a mid-range number, an example of which is shown inFIG.4C, e.g., such that about half of the XACsamplers are operational and therefore return output pulses, and about half of the XACsamplers are non-operational and therefore do not return output pulses. AlthoughFIGS.4B-4Dillustrate an example in which XACsamplers are distributed in XAC-dimension ascending order of their AC lower limits along the length of an RQL scan register wrapper like that ofFIG.2A, in other examples, an RQL scan register wrapper like that ofFIG.2Acan be configured with XACsamplers arranged in other orders, including descending order or a known arrangement of no particular order, and the order can be accounted for accordingly when analyzing outputs of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples in which wrapper output analysis involves counting the number of samplers active under a given bias condition, as when spreading of the sampler margins is accomplished by process variation alone, the order is unimportant and need not be accounted for in analysis of wrapper outputs to determine improved or optimized bias levels. The graph500ofFIG.5Ashows example shmoo plots302,504of nominal AC and DC bias level operating margins for operative RQL circuitry102and for DC bias-level sensors (XDCsamplers). Graph500includes margins504for eight XDCsamplers, but the number of XDCsamplers can, in some examples, be less than or greater than eight. The graph500, viewed along with the one-dimensional time plots ofFIGS.5B-5D, illustrates the performance of an example XDCoptimization method that can be carried out without interruption of the operation of operational RQL circuitry102having nominal operating margins302. The DC value of a provided bias signal can be varied, in effect shifting a bias point horizontally left and right on the graph500, until the optimal DC bias point5C is determined. The XDCsamplers can, for example, have bias transformers with varying DC mutual inductance (MDC) and nominal AC mutual inductance. As an example, if the DC bias point of nominal operating margins302is such that the ideal current in the DC bias lines is 2.0 mA, DC mutual inductance for the XDCsamplers can be staged to have mutual inductances in each of the samplers' respective transformer(s) to the DC bias line so that the XDCsamplers are optimally biased when the DC bias line current varies between 1.5 mA and 2.5 mA. Such variation in DC mutual inductance can be provided for a given XDCsampler, for example, by varying distance over which a DC transformer in a bias tap of the given XDCsampler couples to a respective DC bias line, thus making such coupling distance shorter or longer. As with XACsamplers in the example illustrated inFIG.4A, the XDCsamplers can be configured in ensemble such that the lower limits of their margin shmoo plots are centered about the bias point306initially deemed or assumed optimal for operation of the operational RQL circuitry102. As shown inFIG.5A, the lower limits of the XDCsampler margin shmoo plots are centered near the middle of the nominal operational RQL circuitry margin shmoo plot302. FIGS.5B-5Dshow output pulse receipts, or non-receipts, for an example bias-level sensor wrapper like the one ofFIG.2Awhen it is provided with XDCsamplers as its bias-level sensors202-212. The broken-line patterns of the output pulses inFIGS.5B-5Dcorrespond to the same broken-line patterns of the margin shmoo plots504ofFIG.5A, in that a pulse of a certain broken-line pattern inFIGS.5B-5Dis one created by an XDCsampler having margins drawn with the same broken-line pattern inFIG.5A.FIGS.5B-5Dthus show the wrapper output effect of change in DC value of provided bias signals as illustrated inFIG.5A. The bias signal DC value optimization can be carried out with the bias signal AC amplitude set at or just slightly higher than its optimal level. When the provided DC bias is too low, the returned output pulses are limited to the earlier one or several pulse returns, as shown inFIG.5B, provided the XDCsamplers are staged in order (e.g., linearly), with those configured to have the lowest DC operating margins placed most proximally to the input/output end of the wrapper shown inFIG.2A. By contrast, when the provided DC bias is too high5D, the returned output pulses are only the last one or the last several in time, indicating that only the one or several XDCsamplers most distal to the input/output end of the wrapper shown inFIG.2Aare operational, as shown inFIG.5D. The provided DC bias5C can be said to be optimal when the returned output pulses are only the temporally middle one or several, as shown inFIG.5C, indicating that only the one or several middle XDCsamplers are operational and therefore return output pulses, while the others do not. AlthoughFIGS.5B-5Dillustrate an example in which XDCsamplers are distributed in XDCdimension ascending order of their AC lower limits along the length of an RQL scan register wrapper like that ofFIG.2A, in other examples, an RQL scan register wrapper like that ofFIG.2Acan be configured with XDCsamplers arranged in other orders, including descending order or a known arrangement of no particular order, and the order can be accounted for accordingly when analyzing outputs of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples in which wrapper output analysis involves counting the number of samplers active under a given bias condition, as when spreading of the sampler margins is accomplished by process variation alone, the order is unimportant and need not be accounted for in analysis of wrapper outputs to determine improved or optimized bias levels. In various examples, a wrapper can be configured to include only XACsamplers, only XDCsamplers, or some mix of different types of samplers. In some examples, the XACor XDCmargin offset staging can be reversed from the ascending order described above, such that high-margin samplers are located proximally on the wrapper ladder and low-margin samplers are located distally on the wrapper ladder, or the staging can take on some pattern other than ordered staging, with an accompanying change in the expected pulse output. The linear ordered low-to-high staging described above is provided only as one example for purposes of illustration. In any example, the location of a sampler as distal or proximal to the input/output end of a bias-level sensor wrapper is not the factor determinative of the bias-level adjustment/optimization significance of its corresponding output pulse; rather, the margin offset for which the sampler is configured is the factor that is determinative of the bias-level adjustment/optimization significance of the sampler's corresponding output pulse. The one-dimensional scan procedure illustrated inFIGS.5B-5D, varying only applied DC bias, leads to a more accurate assessment or calibration of an applied DC bias level after the one-dimensional scan procedure illustrated inFIGS.4B-4D, varying only applied AC bias, is performed to first find an improved or optimal applied AC bias level Similarly, the one-dimensional scan procedure illustrated inFIGS.4B-4D, varying only applied AC bias, leads to a more accurate assessment or calibration of an applied AC bias level after the one-dimensional scan procedure illustrated inFIGS.5B-5D, varying only applied DC bias, is performed to first find an improved or optimal applied DC bias level. Thus, these two one-dimensional scan procedures can be performed iteratively and repeatedly to home in on improved or optimal values of both XACand XDC. The RQL scan registers200,260,290ofFIGS.2A-2Ccan be used, for example, with either or both of XACsamplers and XDCsamplers as bias-level sensors202-212(or262-272or BLS) to provide an output indicative of the AC or DC bias level. When used to measure XAC, any of the scan registers200,260,290produces a specific number of pulses when an optimal level has been reached. When used to measure XDC, the result output by any of the scan registers200,260,290is indicative of the average position of the operationally-biased XDCsamplers along the scan register. Each of the RQL scan registers200,260,290can provide a numerical result in some example modes of operation, or in other example modes of operation, the output can be indicative of bias levels in other ways. For example, the RQL scan registers200,260,290can permit examination of the output of a single bias level sensor arranged in the scan register, in order to find its improved or optimum bias point by varying applied AC and DC bias. In some examples, this procedure can be performed individually for a plurality, or for all, of the bias-level sensors arranged in the scan register. In some examples, this procedure can be performed for individual bias-level sensors located at various positions throughout a chip, which are not necessarily all elements of a single scan register, or of any scan register. In such examples, the average values of the individually measured improved or optimal applied AC and DC bias levels can then be computed and used as setpoints for the bias sources. Different methods can be used to scan the XDC-XACspace to find improved or optimum AC and DC applied bias levels. A first example scan method can include sampling at every XDC-XACpoint within a range to create a complete two-dimensional map of the XDC-XACspace. A second example scan method can include limiting a scan to a discovered boundary of an operating region, in effect “walking” in and out of a perimeter of a margin shmoo plot in a zig-zag fashion, to determine the contours of the boundary or perimeter. This second example scan method can have time efficiency advantages over the complete XDC-XACspace sampling of the first example scan method. A third example scan method can involve traversing the XDC—XACspace in a spiral or conical scan. A fourth example scan method can implement a successive approximation method, such as is found in an analog-to-digital converter (ADC). A fifth example scan method can implement a delta-sigma algorithm. Other example scan methods can implement variations or combinations of the above methods to home in on improved or optimal applied AC and/or DC bias levels. In any of these examples, the chosen scan method can use a closed loop to find and stabilize the bias levels, irrespective of the type of scan(s) employed and configuration or placement on the chip of the bias-level sensors used in the scan method. Samplers, such as bias-level sensors202-212inFIG.2A, can have any of a number of different forms. In some examples, samplers are made of one or more JTLs or logic gates configured in series with each other, e.g., as a shift register, with at least one of the JTLs or logic gates in the shift register being specially configured so that it is sensitive to bias in different ways than other JTLs or logic gates in operational RQL circuitry102.FIG.6shows an example sampler stage600having sampler JTL602coupled to sampler bias tap604, configured for use in a bias-level sensor, such as any of bias-level sensors202-212inFIG.2A. An SFQ-based sample signal provided at sampler JTL input terminal ai may transmit (i.e., propagate) to sampler JTL output terminal qo when sampler JTL602is operational. The operability of sampler JTL602depends at least upon sampler JTL602being biased within its operating margins. Biasing is provided to sampler JTL602via bias lines606, which in the illustrated example include bias lines614,616,618. Sampler JTL602is inductively coupled to bias lines606via sampler tap604. In the example illustrated inFIG.6, sampler tap604includes DC coupling transformer608for inductively coupling the sampler JTL602to a DC bias line614, I-clock coupling transformer610for inductively coupling the sampler JTL602to an I-clock bias line616, and Q-clock coupling transformer612for inductively coupling the sampler JTL602to a Q-clock bias line618. The following table relates normalized mutual inductance to tap phase in the sampler tap204, thus showing how the normalized AC mutual inductances MI, MQcan be modified to provide a sampler JTL602with biasing of different clock phases. The normalized MDCcan vary (from 1) for XDCsamplers. TABLE 1Normalized mutual inductance versus tap phase.Tap phase0º45º90º135º180º225º270º315ºMutualMI11/√20−1/√2−1−1/√201/√2inductorMQ01/√211/√20−1/√2−1−1/√2MDC11111111 In contrast to JTLs or gates that may be found in operational RQL circuitry102, sampler JTL602is fed by sampler bias tap604through a larger self-inductance, which in some examples can be provided by an enlargement of bias inductor L2, or in other examples can equivalently be provided by inclusion of AC offset inductor LoffsetACbetween sampler JTL602and tap604, as shown inFIG.6. In this latter example, sampler JTL602, which is defined to exclude AC offset inductor LoffsetAC, can otherwise be identical to standard-bias JTLs used in operational RQL circuitry102. As compared to JTLs that may be found in operational RQL circuitry102, the DC bias transformer608of the bias tap604can in some examples also be configured with a larger or smaller mutual inductance MDCby which the sampler JTL602is coupled to DC bias line614. The enlargement of bias inductor L2or the inclusion of AC offset inductor LoffsetACto provide greater self-inductance of sampler stage600can provide the offsets illustrated inFIG.4A, in which the margin shmoo plot is vertically shifted upward in the XDC-XACspace with respect to the nominal margins302. In some examples, AC offset inductor LoffsetACcan be omitted and bias inductor L2can be made smaller than normal (smaller than in a JTL in operational RQL circuitry102) to achieve opposite-direction offsets (not illustrated), in which the operating margin shmoo plot of a bias-level sensor is effectively shifted down (in the XACdimension) from the nominal operating margins302. Bias inductor L2and, where present, AC offset inductor LoffsetACcan, for example, be provided by an inductive network. In example bias-level sensors having a reduced AC response, AC offset inductor LoffsetACin sampler stage600can, for example, be about 1.5 times the self-inductance of the sampler tap604. This self-inductance value of AC offset inductor LoffsetACcan have the effect of placing the bottom corner of the corresponding sampler's schmoo plot at about the XAC-dimension midpoint of the schmoo plot302of operational RQL circuitry102. As an example, AC offset inductor LoffsetACin sampler stage600can be about 29.25 pH, or can provide about 1.5 times the self-inductance of sampler tap604, which can be, for example, about 19.3 pH. In an example in which instances of bias-level sensors having sampler stage600are implemented as bias-level sensors202-212in the context of the wrapper shown inFIG.2A, such that the bias-level sensors are functional for relatively low values of XAC, the bias-level sensors may respond to high AC bias levels by outputting a steady stream of RQL-encoded logical “1”s (positive SFQ pulses followed by negative SFQ pulses), flipping every AC clock cycle. The corresponding suppression logic240-250prevents this steady stream of RQL-encoded logical “1”s by generating a stream of RQL-encoded logical “0”s (no SFQ pulses) in response. The sensing of the lower limit of the bias-level sensor margin shmoo plot can be used to calibrate AC bias amplitude parameters, and thus to stabilize an RQL clock, in an operating RQL system, as described above with regard toFIGS.4A-4D. In example bias-level sensors having margin shmoo plots shifted to higher XACvalues, AC offset inductor LoffsetACin a bias-level sensor sampler stage600can, for example, be between about 0.5 and 10 times the nominal tap self-inductance value, e.g., the tap self-inductance value for JTLs or gates used in operational RQL circuitry102. For example, AC offset inductor LoffsetACin a bias-level sensor sampler stage600can be about 1.5 times the size of the tap self-inductance for JTLs and gates used in operational RQL circuitry102. As an example, if the nominal self-inductance value for a bias tap supplying a JTL or gate used in operational RQL circuitry102is about 19.3 pH, the inductance value for the AC offset inductor LoffsetACin bias level sensor sampler stage600inFIG.6can be between about 9.65 pH and about 193 pH, e.g., between about 40 pH and about 50 pH, e.g., about 29.0 pH. In an example in which bias-level sensors that include instances of sampler stage600are implemented as bias-level sensors202-212in the context of the wrapper shown inFIG.2A, such that the bias-level sensors are function for relatively high values of XAC, the bias-level sensors may respond to low AC bias levels by outputting a steady stream of RQL-encoded logical “1”s (positive SFQ pulses followed by negative SFQ pulses), flipping every AC clock cycle. The corresponding suppression logic240-250prevents this steady stream of RQL-encoded logical “1”s by generating a stream of RQL-encoded logical “0”s (no SFQ pulses) in response. Thus the upper edge of the bias-level sensor margin shmoo plot can be sensed without filling the RQL shift register wrapper output with a steady stream of “F”s. The sensing of the upper edge of the bias-level sensor margin shmoo plot may not be needed to calibrate AC bias amplitude parameters in an operating RQL system; it can, in some examples, be used as a diagnostic tool. FIG.6provides an example in which a JTL602is used as the sample signal transmission device. Other example sampler stages, not illustrated, can be like sampler stage600ofFIG.6but with an RQL gate as the sample signal transmission device in place of the sampler JTL602. The RQL gate, biased with the modified biasing of a sampler tap like sampler tap604with desired mutual inductances MQ, MIto AC bias lines to provide a desired clock phase, and mutual inductance to DC bias lines to provide an XDCoffset where desired. The RQL gate can, in some examples, further be provided with an AC offset inductor like LoffsetACinFIG.6to raise the shmoo plot (operating region) to higher level of XAC. The RQL gate would, like the sampler JTL602, operate within its modified operating margins and fail (would produce unexpected output or no output) outside of its modified operating margins. FIG.7shows example suppression logic700such as may be used to implement any instance of suppression logic240-250inFIG.2A. Suppression logic700includes a first superconducting path to a noninverting input of an RQL A-NOT-B gate704(a two-input AND gate with a single inverting input) and a second path through a number (e.g., four) JTLs702to create a one-cycle delay to the inverting input of the A-NOT-B gate. When bias to a sampler is too high, the sampler can be caused to “spin” (generate a steady stream of logical “1” outputs) that can disable the RQL scan register wrapper ofFIG.2A. Suppression logic700prevents such spinning (repeat triggering). The A-NOT-B gate704passes the first logical “1” out of the sampler, but not subsequent “1”s from a sampler producing a stream of reciprocal SFQ pulses due to a defect or over-bias. In some examples, suppression logic700can be omitted. Excess AC bias amplitude will spin standard logic in the read-out register approximately 2 dB before it spins samplers whose lower limit (XACmin) has been elevated to a higher-than-standard XAClevel. Moreover, a suppression logic circuit may itself be defective and start spinning, for example, because of use of an RQL A-NOT-B gate704that has narrow operating margins. Some examples can use multiple instances of sampler stage600arranged in series, as a shift register, to provide a bias-level sensor. Because a single JTL receives a substantial portion of its operating flux from the cell driving it and from the cell it drives, it can be necessary to place several sensing JTLs600(having similarly shifted bias margins) in series before the true effect of the bias shift is manifest in the output of the shift register that constitutes the bias-level sensor. As an example, four or more sensing JTLs in series can be sufficient to make the sensing elements operate independently of the JTLs that precede and follow them. FIG.8shows an example shift register800configured as a bias-level sensor, including four instances804,806,808,810of the example sampler stage600ofFIG.6. Shift register800can further include input stage802and output stage812, each of which can be implemented as one or more JTLs and/or logic gates provided with standard biases (e.g., that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6).FIG.9shows an example shift register900, including three instances904,906,908of the example sampler stage600ofFIG.6. Shift register900can further include input stage902and output stage912, each of which can be implemented as one or more JTLs and/or logic gates provided with standard biases (e.g., that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6).FIG.10shows an example shift register1000, including one instance1004of the example sampler stage600ofFIG.6. Shift register1000can further include input stage1002and output stage1012, each of which can be implemented as one or more JTLs and/or logic gates provided with standard biases (e.g., that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6).FIG.11shows an example shift register1100, including one instance1104of the example sampler stage600ofFIG.6. Shift register1100can further include input stage1102, which can be implemented as one or more JTLs and/or logic gates provided with standard biases (e.g., that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6). As examples, any of shift registers800,900,1000, or1100can be implemented as any of the bias-level sensors202,204,206,208,210,212inFIG.2A, as any of the bias-level sensors262,264,266,268,270,272inFIG.2B, or as any of the bias-level sensors BLS inFIG.2C. FIG.12shows an example phase-specific bias-level sensor1200for a Q clock. Phase-specific Q sampler1200ofFIG.12thus provides a sampler that responds to variations in Q clock amplitude while not responding to variations in I clock amplitude.FIG.13shows an example phase-specific bias-level sampler1300for an I clock. Phase-specific I sampler1300ofFIG.13thus provides a sampler that responds to variations in I clock amplitude while not responding to variations in Q clock amplitude. Samplers1200,1300thus allow for independent adjustment of I and Q clock AC amplitudes.FIGS.14and15explain sensing symbols used inFIGS.12,13,16, and18. In the phase-specific Q sampler1200ofFIG.12, four quad (“x4”) sampler stages1202,1204,1206,1208are placed in series with each other and each of the four quad sampler stages1202,1204,1206,1208is biased by a different-phase RQL clock signal. The first quad sampler stage1202comprises an arrangement of four JTLs and/or logic gates provided with standard biases that do not have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6. An expansion of such a standard-bias quad sampler stage is shown as standard-bias JTL and/or gate series1400inFIG.14. First quad sampler stage1202is biased by a 0° clock. The second quad sampler stage1204comprises an arrangement of four JTLs and/or logic gates provided with modified AC biases that do have the self-inductance and/or mutual inductance modifications of the sampler stage600ofFIG.6. An expansion of such a modified-bias quad sampler stage is shown as modified-bias JTL and/or gate series1500inFIG.15. Second quad sampler stage1204is biased by a 90° clock (a clock for which the AC waveform is shifted by 90° with respect to the AC waveform of the 0° clock). The third quad sampler stage1206is a quad standard-bias sampler stage1400biased by a 180° clock. The fourth quad sampler stage1208is a quad standard-bias sampler stage1400biased by a 270° clock. The 0° and 180° clocks can be sourced from an I clock resonator, and the 90° and 270° clocks can be sourced from a Q clock resonator, as described in Table 1, above. Although sampler stages1202,1204,1206,1208are shown in the illustrated example arrangement1200as quad sampler stages, having four series JTLs and/or logic gates each, the number of JTLs and/or logic gates in each sampler stage can be larger or smaller in other examples. The number of JTLs and/or logic gates in each sampler stage can be determined as a design parameter. In an example (not shown), sampler stage1204has four or more series JTLs and/or logic gates to prevent current-sharing influence from sampler stages1202,1206, and sampler stages1202,1206,1208are composed of fewer than four series JTLs and/or logic gates. In the phase-specific I sampler1300ofFIG.13, four quad sampler stages1302,1304,1306,1308are placed in series with each other, and each of the four quad sampler stages1302,1304,1306,1308is biased by a different phase RQL clock signal. The first quad sampler stage1302is a quad standard-bias sampler stage1400biased by a 0° clock. The second quad sampler stage arrangement1304is a quad standard-bias sampler stage1400biased by a 90° clock. The third quad sampler stage1306is a quad modified-bias sampler stage1500biased by a 180° clock. The fourth quad sampler stage1308is a quad standard-bias sampler stage1400biased by a 270° clock. Although sampler stages1302,1304,1306,1308are shown in the illustrated example arrangement1300as quad sampler stages, having four series JTLs and/or logic gates each, the number of JTLs and/or logic gates in each sampler stage can be larger or smaller in other examples. The number of JTLs and/or logic gates in each sampler stage can be determined as a design parameter. In an example (not shown), sampler stage1306has four or more series JTLs and/or logic gates to prevent current-sharing influence from sampler stages1304,1308, and sampler stages1302,1304,1308are each composed of fewer than four series JTLs and/or logic gates. In the expansion1400of the quad standard-bias sampler stage shown inFIG.14, each individual component stage1402,1404,1406,1408of each sampler stage1202,1206,1208,1302,1304,1308includes a JTL or gate with a bias-tap self-inductance of a standard value, that is, of the same value used to supply JTLs and gates in operational RQL circuitry102(e.g., with no AC offset inductances LoffsetAC). The JTL or gate of each individual component stage1402,1404,1406,1408is biased with an AC clock signal of the same phase (“PHASE°”). In the expansion1500of the quad modified-bias sampler stage shown inFIG.15, each individual component stage1502,1504,1506,1508of each sampler stage1204,1306includes a JTL or gate that is supplied bias via an AC offset inductor LoffsetACinserted between the JTL or gate and its respective bias tap (or, equivalently, an enlarged bias tap inductor L2) that provides bias self-inductance larger than that in JTLs and gates in operational RQL circuitry102. Thus, each individual component stage1502,1504,1506,1508has a raised margin shmoo plot in the XDC-XACspace as compared to JTLs or gates in operational RQL circuitry102. The JTL or gate of each individual component stage1502,1504,1506,1508is biased with an AC clock signal of the same phase (“PHASE°”). Because of the tendency of flux to be shared between driven and driving JTLs or logic gates, a single JTL or logic gate operating at 90° clock phase behind the one driving it and 90° clock phase ahead of the JTL or logic gate that it drives may not provide an accurate measurement of the amplitude of the clock of a particular phase that is biasing it. However, with four or more individual component stages biased by a clock signal of the phase to be sampled (e.g., sampler stages1502,1504,1506,1508, or1402,1404,1406,1408), flux sharing can be effectively confined to the first and last JTL or logic gate, leaving remaining JTLs and/or logic gates largely uninfluenced by flux sharing. The phase to be sensed can thus be accurately measured. In phase-specific samplers1200,1300shown inFIGS.12and13, series arrangements1204,1306of individual component stages1502,1504,1506,1506are biased through weakened bias taps, e.g., with AC offset inductor LoffsetACpresent to provide an elevated XAClower limit, while series arrangements1202,1206,1208,1302,1304,1308of individual component stages1402,1404,1406,1408have standard bias taps to form supporting infrastructure. The individual component stages1502,1504,1506,1508of sensing sampler stages1204or1306respond independently to either I or Q clock bias. For I/Q phase angles near the nominal 90°, phase sensitivities of I and Q weak-tapped JTLs or gates have opposite slopes. FIG.16shows an example I clock-specific (Q clock-independent) bias-level sensor1600. The standard-bias quad sampler stages1602,1606, and1610are as expanded inFIG.14and the modified-bias quad sampler stages1604and1608are as expanded inFIG.15. Example sampler1600thus contains twenty JTLs and/or gates in series with each other. In the example I clock-specific (Q clock-independent) bias-level sensor1600, the XACoperating margins of the sensing sampler stages provided with 0° and 180° clocks (the sensing JTLs and/or gates in quad arrangements1604,1608) are shifted up in the XDC-XACspace, e.g., by inserting AC offset inductors LoffsetACof 1.5 times the nominal tap self-inductance (e.g., 1.5×19.3 pH). Only in these sensing JTLs or gates is the I clock AC amplitude varied during the margin-sweep optimization procedure by which an optimum AC bias level is determined for I clock signals. By contrast, AC offset inductance LoffsetACequals 0 (AC offset inductor LoffsetACis absent) in the sampler stages1602,1606, and1610, such that the XACmargins of the sampler stage JTLs and/or gates in sampler stages1602,1606,1610are the same as of JTLs and gates in the operating circuitry102. The Q clock amplitude supplied to quad sampler stages1602,1606, and1610remains fixed during the margin-sweep optimization procedure (while sweeping the AC amplitude of the I clock supplied to sampling JTLs or gates in quad sampler stages1604and1608). The graph ofFIG.17shows example AC and DC bias margin shmoo plots for the I-clock-specific (Q-clock-independent) bias-level sensor1600ofFIG.16. When operated with various XACbias levels (nominal, 1 dB below nominal, 2 dB below nominal) for the JTLs running on the Q clock, the effect on the margin shmoo plot of the I-specific sampler1600can be observed as the different plotted curves ofFIG.17. The lower limit1702of the margin shmoo plots of the I sampler1600remains constant over variations in Q bias (is unaffected by the strength of a clock signal applied to Q wrappers), verifying that the I bias level can be measured independent of variations in Q bias levels. FIG.18shows another example I clock-specific (Q clock-independent) bias-level sensor. The standard-bias quad sampler stages1802,1806are as expanded inFIG.14and the modified-bias quad sampler stage1804is as expanded inFIG.15. In the example I clock-specific (Q clock-independent) bias-level sensor1800, the margin shmoo plots of the sampler stages provided with the 180° clock (the sampler stages in quad arrangement1804) are shifted up in the XDC-XACspace, e.g., by inserting AC offset inductor LoffsetAChaving a value of 1.5 times nominal tap self-inductance (e.g., 1.5×19.3 pH). No AC offset inductor is used in the standard-bias sampler stages1802and1806(as with JTLs and gates in the operating circuitry102). Sampler1800represents a structural simplification of sampler1600that does not incur loss of performance. Sampler1800has a margin shmoo plot similar to sampler1600, as shown inFIG.17. In contrast to sampler1600, sampler1800uses only the 180° phase clock, and not the 0° phase clock, to define the XAClower limit1702shown inFIG.17. The lower limit1702of the margin shmoo plots of the I sampler1800remains constant over variations in Q bias, verifying that the I bias level can be measured independent of variations in Q bias levels. A challenge of RQL circuitry is that I and Q clock signals112,114generated to be in quadrature at 90° apart as measured at the signal generator110in the warm space may not be 90° apart from each other at the level of the RQL IC106in the cold space due to components in clock resonator networks104that introduce unwanted phase shifts. Offsets, from 90°, in phase difference between I and Q clock signals at the level of the RQL IC106can cause operational issues, including reduced operating margins, in operational RQL circuitry102. Circuitry described herein can provide an indirect measurement of phase error through measurement of the effects on the operation of samplers for different clock phase differences by effectively turning a phase variation into an amplitude variation. As well as being sensitive to the I and Q clock amplitudes, the phase-specific samplers1200,1300,1600and1800ofFIGS.12,13,16, and18are also sensitive to the difference in phase between I and Q clocks. The minimum XACfor I and Q phase-specific samplers is equal when the difference in phase between the I and Q clocks, within the RQL IC106, is 90°. Thus, the I and Q phase-specific samplers1200,1300,1600and1800can be used to determine the optimal phase difference between the I and Q clocks, as generated at the source110, needed to obtain an exactly 90° phase difference between the I and Q clocks within the RQL IC106. The graph ofFIG.19shows example minimum operative AC bias for I clock-specific and Q clock-specific bias-level sensors as a function of deviation of Q clock phase from 90° (XACat the margin shmoo plot lower limit for I-specific and Q-specific samplers). For the samplers used to produce the graph ofFIG.19, the AC offset inductance LoffsetACof the I and Q sensing JTLs or gates is 1.5 times the nominal tap self-inductance (the tap self-inductance used for JTLs or gates in operational RQL circuitry102). The phase difference between the I and Q clocks is varied ±45° about a nominal value of 90°. The horizontal axis of the graph ofFIG.19is the deviation from 90° of the interclock phase difference. XACminis equal 1902 for both I and Q sensing JTLs or gates when the I/Q phase difference is 90°. FIG.20shows a 45° shift register2000, comprising JTLs or logic gates supplied with clocks at 45°, 135°, 225°, 315°, that can be used as a phase sampler, also referred to herein as an Xphasesampler. The Xphasesampler is capable of indirectly detecting phase difference between two AC clocks (e.g., between I and Q clocks). In the phase sampler2000ofFIG.20, four hex sampler stages2002,2004,2006,2008are placed in series with each other and each of the four hex sampler stages2002,2004,2006,2008is biased by a different-phase clock signal that can be produced, for example, as a combination of other clock signals (e.g., as shown above in Table 1).FIG.21shows the expansion of the hex sampler stage symbol used for each of the hex sampler stages2002,2004,2006,2008inFIG.20. The first hex sampler stage2002is biased by a 45° clock. The second hex sampler stage2004is biased by a 135° clock. The third hex sampler stage2006is biased by a 225° clock. The fourth hex sampler stage2008is biased by a 315° clock. Combination clock waveforms providing clocks of 45°, 135°, 225°, or 315° phase can be provided by transformer-coupling to both I (0° or 180°) and Q (90° or 270°) clock resonators (as shown above in Table 1). Use of the Xphasesampler2000ofFIG.20to directly measure phase error between I and Q clock signals can include first equalizing I clock and Q clock signal amplitudes with separate sensors, for example, an I-independent clock amplitude sensor, such as the phase-specific I sampler1300ofFIG.13, and a Q-independent clock amplitude sensor, such as the phase-specific Q sampler1200ofFIG.12. In the expansion2100of each of the hex sampler stages2002,2004,2006,2008inFIG.21, each individual component stage2102,2104,2106,2108,2110,2112of each sampler stage2002,2004,2006,2008includes a JTL or gate that is supplied bias via an AC offset inductor LoffsetACinserted between the JTL or gate and its respective bias tap (or, equivalently, an enlarged bias tap inductor L2) that provides bias self-inductance larger than that in JTLs and gates in operational RQL circuitry102. Thus, each sampler stage2102,2104,2106,2108,2110,2112has a raised margin shmoo plot in the XDC-XACspace as compared to JTLs or gates in operational RQL circuitry102. The JTL or gate of each sampler stage2102,2104,2106,2108,2110,2112is biased with an AC clock signal of the same phase (“PHASE°”). As described above, concatenating several sampler stages all biased with the same AC clock phase mitigates the effect of current (or, alternatively, flux) shared between adjacent JTLs biased by clock signals of different clock phases. The specific number of sensing JTLs needed to provide this insensitivity depends upon details of the JTLs and/or gates and their respective bias taps. In some examples, concatenating between four and six sampler stages can be adequate to provide the desired flux sharing mitigation. AlthoughFIG.20illustrates an example of a phase sampler2000having six same-clock-phase-driven sampler stages per set2002,2004,2006,2008, that is, in which each sampler stage2002,2004,2006,2008includes a set of six same-clock-phase-driven sampler stages coupled directly to each other in series, other examples can have more or fewer same-clock-phase-driven samplers stages coupled directly to each other in series, e.g., four, five, or seven same-clock-phase-driven JTLs or gates coupled directly to each other in series in each set, or varying numbers of same-clock-phase-driven JTLs or gates coupled directly to each other in series in the different sets. The minimum XACclock amplitudes, that is the amplitudes of AC flux provided by the transformers of the 45° and the 135° combination clocks, as a function of phase error (phase difference between the I and Q clocks) is plotted inFIG.22. The sampler stages respond to these differences in clock amplitudes. Thus, phase error can be calibrated based on information about the operating margins observed in sampler stages while varying I/Q phase. In the 45° shift register2000ofFIG.20, clock amplitudes of 45° and 225° transformers decrease as the interclock phase difference (phase error) increases relative to 90°, while clock amplitudes of 135° and 315° transformers increase. The clock amplitude versus phase error graph ofFIG.22shows this relationship for the example phase sampler2000ofFIG.20. The minimum operative bias signal AC amplitude graph ofFIG.23shows how this property is applied to form an Xphasesampler that is sensitive to phase, in the form of phase sampler2000ofFIG.20. As shown inFIG.23, the operating margin shmoo plot lower limit (XACmin) of a shift register consisting of 45°, 135°, 225°, and 315° sampler stages is at the lowest XAClevel2302when the phase difference between the I and Q clocks (phase error), as measured on the RQL IC106, is 90°. AlthoughFIG.20illustrates an example with six sampler stages per phase-specific sampler stage2002,2004,2006,2008, other example shift registers configured as Xphasesamplers may have more or fewer sampler stages per arrangement2102,2104,2106,2108. A method3000for clock signal phase calibration using a phase-sensitive sampler like the phase sampler2000shown inFIG.20is shown inFIG.30, and is described in greater detail below. FIG.24shows a representative portion of a phase mode logic (PML) bias-level sensing arrangement2400that can use flip-flops (e.g., flip-flops2402,2404,2406) and phase-mode shift registers (e.g., shift registers2408,2410,2412,2414,2416,2418,2420,2422,2424) to sense and read out bias amplitudes. PML bias-level sensing arrangement2400ofFIG.24can thus provide a similar function as the ladder wrapper arrangement ofFIG.2A, in that it provides sensors that are individually testable for their operating range under variable RQL bias conditions and that can be located in multiple places on an RQL IC106, but with a different structure and method of use than the arrangement ofFIG.2A. Bias-level testing and adjustment using the arrangement2400ofFIG.24involves changing the AC level in the resonator under test, which in different examples can be the I resonator (as illustrated) or the Q resonator (not illustrated). As with an RQL scan register or JTL testbed ofFIG.2A, multiple sensors are activated and their responses are read out using a shift register circuit structure. The structure2400inFIG.24forms a shift register wherein each time a logical clock assertion signal (provided, for example, as a reciprocal pair of SFQ pulses, or, in some instances, as a first positive SFQ pulse of such a pulse pair) is advanced in through logical clock path2426(from right to left in the orientation ofFIG.24) and thus provided to clocking inputs of D flip-flops (e.g., D. flip-flops2402,2404,2406), a pattern signal provided on data path2428is advanced by one shift-register element through the shift register2400(from left to right in the orientation ofFIG.24). A single element of the shift register2400is encompassed by broken-line box2430, having one D flip-flop2416and JTL-based shift registers2410,2416,2422. The register2400can include as many elements like element2430as desired, arranged in series with each other, each element being placed in a location on the RQL IC106so as to tap the clock resonators in that portion of the IC106. Each element thus observes a different physical connection (tap)120to the AC clock network104in RQL IC106. InFIG.24, each small triangle represents a buffer, e.g., a JTL-based buffer. The flip-flops of shift register2400(e.g., flip-flops2402,2404,2406) can be implemented, for example, as a PML flip-flop, examples of which are described in U.S. Pat. No. 10,615,783 B2, entitled “RQL D Flip-Flops”, and U.S. Pat. No. 10,756,712 B2, entitled “RQL Phase-Mode Flip-Flop”, both of which are incorporated by reference. The number above each flip-flop or buffer (in degrees) represents the phase of the clock provided to the flip-flop or buffer below it. Different phase clocks can be provided by tapping, via different transformers, different clock resonators104on the RQL IC106, or in some cases by tapping different combinations of transformers. In some examples of shift register2400, the elements of the shift register can be designed and fabricated to each have different operating-margin offsets from each other, which offsets can be staged, linearly or in some other fashion, similarly to how the bias-level sensors202-212of the ladder wrapper configuration200ofFIG.2Acan be intentionally configured with staged operating-margin offsets, as described above. In some examples, the bias transformers that connect the AC clock network to the D flip-flops in shift register2400can be modified from their typical values, so that the D flip-flops of shift register2400are underbiased or overbiased, either all with the same amount of underbiasing or overbiasing or with differing degrees of underbiasing or overbiasing. The D flip-flops can thus be expected to fail (to stop functioning due to the AC bias point being outside of the AC operating margins of the D flip-flops) with varying AC bias at an AC bias amplitude that is larger (at an AC bias point that is higher) than the AC amplitude at which the JTL-based buffers fail from the same amplitude-varying AC bias. Even absent intentional underbiasing of the D flip-flops, the D flip-flops may fail at a higher AC bias point than the AC bias point at which the JTL-based buffers fail from the same amplitude-varying AC bias, because the D flip-flops are not as robust as JTLs in terms of their operating margins. The PML flip-flop-based bias samplers in the shift register arrangement2400ofFIG.24are responsive to variations in clock resonator, bias coupling transformer, and all other circuit parameters. Use of the PML flip-flop-based bias samplers in the shift register arrangement2400ofFIG.24can thus help identify the bias levels needed by operational RQL circuitry102, which can be expected to be influenced by variations in all process parameters. Specifically, PML flip-flop-based bias samplers are sensitive to the self-inductance of bias coupling transformer, the mutual inductance between the bias coupling transformer and the corresponding clock resonator, the magnitude of current in clock lines, the inductance of the coupling transformer, the inductances in JTLs and gates, and the Josephson junction (JJ) critical current. In the illustrated example2400ofFIG.24, the Q clock resonator can be driven at nominal biasing levels, so that the logical clock signal is reliably provided to all of the flip-flops in the shift register2400(e.g., flip-flops2402,2404,2406), while the I resonator can be driven with varying AC amplitude to test whether or not the shift operation is successful across the range of different AC amplitudes. For example, the operating range of each of the flip-flops can be independently determined for each flip-flop by performing the method2900shown in the flow diagram ofFIG.29. With the AC amplitudes of the Q and I clocks set2902to nominal, and the logical clock running, a test data bit pattern can be shifted2904into the data path2428. The logical clock can be run by inputting a continuous stream of reciprocal pulse pairs into the logical clock path2426. Thus, the initial data shift-in2904is performed while driving the I resonator at nominal AC bias amplitude levels. With the logical clock subsequently stopped2906after the test data bit pattern is shifted into the PML shift register2400, the I resonator AC bias amplitude can be varied2908to a test an AC bias amplitude level that is greater or less than nominal. Then, a single logical clock assertion (e.g., a single positive SFQ pulse or a reciprocal pulse pair) can input2910into the logical clock path2426. The I resonator AC bias amplitude can then be returned2912to nominal, and the logical clock restarted, to shift out2914an output data bit pattern on the data path2428. The output data bit pattern can be observed2916, e.g., following output of the data bit pattern through input/output circuitry of the RQL IC106. The observation can be done, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) outside the cold space of the RQL IC106. If the output data bit pattern does not match the input data bit pattern, it can be determined that at least one of the elements2430of the PML shift register2400is outside of its operating margins under the conditions of the varied I resonator AC bias amplitude, and precisely which element2430is outside of its operating margins may be identifiable by the point in the output data bit pattern at which the output data bit pattern no longer matches the input data bit pattern (e.g., by a single-bit error found in the output data bitstream). In some examples, multiple shift errors in the data bit pattern (e.g., multiple single-bit errors between the input data bitstream and the output data bitstream) can be used to identify multiple shift register elements that are operating outside of their respective margins. Observation of the data output under the condition that one of the elements of the shift register2400fails (e.g., due to the provided2908bias point being outside of that element's operating margins), e.g., comparison of the output data bit pattern with the input data bit pattern, can reveal that at a certain point in the output bit data stream, a bit failed to advance through the shift register2400in the bit data stream. If, for example, the input data bit pattern consists of alternating pairs of “0”s and “1”s, the output data bit pattern might include somewhere in its bitstream three “0”s in a row followed by one “1” (“0001”), or three “1”s in a row followed by one “0” (“1110”). The location of the extra bit can be indicative of the identity of the element of the shift register2400that was outside of its operating margins during the single-clock advance. An example input data bit pattern could consist of a series of alternating pairs, triplets, etc., of logical “1”s and “0s” having the length of the PML shift register2400, such as “0011001100110011” for a 16-bit shift register. Method2900, or portions thereof, can, in some examples, be repeated with the bit pattern offset so that transitions could be guaranteed to land on different flip-flops of the shift register2400, so as to provide a thorough data probing of the shift register2400. For example, a “0011001100110011” or “1100110011001100” bit pattern may only be able to detect errors caused by odd-numbered elements of the shift register2400whereas a “1001100110011001” or “0110011001100110” bit pattern may only be able to detect errors caused by even-numbered elements of the shift register2400. Other input data bit patterns may also be used. Conventional semiconductor circuitry (e.g., CMOS circuitry) outside of the cold space of the RQL IC106can perform comparisons of the input data bit pattern with the output data bit pattern, or can otherwise detect anomalies in the output data bit pattern indicative of flip-flop failure with varying bias parameters. Still with reference toFIG.29, after the output data bit pattern provided on the data path2428of the shift register2400ofFIG.24is observed2916for differences from the input data bit pattern, it can be assessed2918whether the AC bias amplitude parameter has been optimized. For example, if a number of different AC bias amplitudes have been provided to the shift register2400, data can be compiled showing which AC bias amplitudes are furthest in value from those that produce errors in the output data bit pattern, from which conclusions can be drawn about which AC bias amplitude is optimal. As one example, an AC bias amplitude that is between (e.g., the mean of) two extreme-value within-operating-margin AC bias amplitudes can be selected as an optimal AC bias amplitude. As another example, in which bias tap values of the D flip-flops are staged to be provided varying amounts of AC bias from flip-flop to flip-flop, the output data bitstream can be analyzed to determine which D flip-flops failed with the AC bias adjustment and which did not, and the optimal AC bias can be determined based on the respective operating margins of the working and failed flip-flops during the test. If insufficient data has been collected to draw a bias parameter optimality conclusion, the test can be repeated by resetting2902the AC bias amplitudes to nominal, restarting2904the logical clock and shifting2904either the same or a different input data bit pattern to repeat the test process portion2902-2918. This test process portion can be iteratively repeated as many times as is necessary to provide confidence that the AC bias amplitude has been optimized2920for the AC clock resonator under test (e.g., the I resonator in the example as illustrated inFIG.24). In some examples, the AC bias amplitude is not optimized, but is improved, e.g., from a starting or nominal value. Although the method ofFIG.29has been outlined with respect to AC bias adjustment or optimization, a similar method can be used for DC bias adjustment or optimization or for phase error adjustment or optimization. For DC bias adjustment or optimization, a DC bias value of a bias signal provided to the D flip-flops can be varied2908rather than an AC amplitude value, and in some examples, the transformer-coupling strengths to the DC bias line under test of the D flip-flops the phase-mode shift register can be staged, such that each has a different strength DC bias coupling and thus the flip-flops present different operating-margin shmoo plots that are shifted in the XDCdimension with respect to each other, as illustrated inFIG.5A. For phase error adjustment or optimization, a phase differential between I and Q clock signals provided to the D flip-flops can be varied2908in addition to an AC amplitude value so as to carry out a two-dimensional XAC—Xphasesearch as shown inFIG.22, with each D flip-flop being biased by an AC bias signal that is a mix of the I and Q clock signals. In some examples, the transformer-coupling strengths to the AC bias line under test of the D flip-flops of the phase-mode shift register can be staged, such that each D flip-flop has a different strength AC bias coupling to the mixed-resonator clock signal and thus the flip-flops present different operating-margin shmoo plots that are shifted in the XACdimension with respect to each other, as illustrated inFIG.5A. Whereas a conventional RQL shift register may progress through at least four phases in every path (e.g., 0°, 90°, 180°, 270°), PML shift register2400is configured such that the logical clock path2426is coupled to the clock resonators104to receive only two phases (in the illustrated example, 90° and 270°) in its logical clock path trunk2420,2422,2424and the data path2428is coupled to the clock resonators104to receive only the other two phases (in the illustrated example, 0° and 180°). Accordingly, the trunk of the logical clock path2426is powered only by one clock resonator (in the illustrated example, the Q resonator), and the data path2428is powered only by the other clock resonator (in the illustrated example, the I resonator). By this arrangement, the logical clock path2426remains functional even when the data path2428is stressed to fail, by varying a bias parameter outside of the operating margins of the data path, for one or more shift register elements, thus ensuring that logical clock signals reach all flip-flops in the shift register2400, even those that are rendered nonfunctional by bias parameter adjustments. The phase assignments thus isolate the operation of the flip-flops onto one AC clock resonator and isolate the logical clock that excites the flip-flops onto a different AC clock resonator. The 0° buffers in the logical clock path branches2414,2416,2418can be considered as part of the corresponding flip-flop circuits2406,2404,2402for the purposes of the above explanation. The buffers driving the clock pins of the respective flip-flops in the illustrated example2400may be required to be on the same clock phase as the flip-flop. Buffers illustrated with broken lines inFIG.24, such as buffers2432,2434in the logical clock path2426and buffer2436in the data path2428, can be of a different design than the buffers illustrated with solid lines inFIG.24. The buffers illustrated in broken lines inFIG.24can each include an extra Josephson junction to ground at the input of their respective JTLs, allowing them to work reliably with a 180° phase delta from the previous cell. Absent this extra Josephson junction, it can be ambiguous which direction an SFQ pulse waiting at the boundary will propagate—forward or backward—when the AC bias signal provided to the respective buffer ramps up. In another example PML shift register similar to shift register2400, but which is not illustrated, 90° of AC clock phase can be added to all the phase values listed inFIG.24to provide a bias-level sensing arrangement that tests the Q clock resonator instead of the instead of I clock resonator. In such an example, the logical clock path trunk is driven by the I resonator and the data path is driven by the Q resonator. In such an example, the “resonator under test” in the method2900ofFIG.29, and the resonator in which the AC amplitude is varied2908as part of the method2900, becomes the Q resonator, rather than the I resonator. In another example modification of PML shift register2400, the JTL-based buffers in the logical clock path can be provided with offset bias transformers as illustrated in, and described above with respect to,FIG.6. Such a modification can effectively shift the operating margins of the clock feed and thus can permit taking of samples when operational logic is at near nominal AC bias. In other example PML shift registers similar to shift register2400, but which are not illustrated, 45° or 135° of AC clock phase can be added to all the phase values listed inFIG.24to provide a bias-level sensing arrangement in which the data path and the logical clock path trunk receive bias signals that are mixes of the 0° I clock and the 90° Q clock. For example, the data path can be driven by 45° and 225° phase AC signals, and the logical clock path trunk can be driven by 135° and 315° signals. As another example, the data path can be driven by 135° and 315° phase AC signals, and the logical clock path trunk can be driven by 45° and 225° signals. Such examples can be useful for determining phase error between the I and Q clock signals and to improve or optimize the phases of the I and Q clocks for true quadrature. In another example modification of PML shift register2400, the JTL-based buffers in the logical clock path can be provided with offset bias transformers as illustrated in, and described above with respect to,FIG.6. Such a modification can effectively shift the operating margins of the clock feed and thus can permit taking of samples when operational logic is at near nominal AC bias. FIG.25illustrates an example proximal portion of an arrangement2500in which pulse generators2502,2508coupled to RQL gates (AND gates2504,2510in the illustrated example) to form bias-level sensors (samplers). A wrapper for the pulse-generator-based bias-level sensors, of which a portion is illustrated inFIG.25, is similar to the ladder structure shown inFIG.2Ain that it has a repeating circuit pattern of rungs (e.g., first two rungs2512,2514) and rails (2516,2518) between a proximal input/output end (illustrated at the bottom ofFIG.25) and a distal end (not shown inFIG.25), the rungs being arranged between an input rail2516and an output rail2518of the wrapper ladder. The rails2516,2518can, for example, extend the full length of the clock resonator tapped by the wrapper. As one example, wrapper can have about 2,000 rungs each having a pulse-generator-based sampler that individually samples the clock resonator at a different location along the clock resonator. JTLs, represented as triangles inFIG.25, providing timing delays. A sample signal input2506provides an SFQ pulse as a sample signal to the wrapper ladder, which SFQ pulse propagates along input rail2516(upward, in the orientation ofFIG.25), is branched and duplicated along each rung, and either returns or not along output rail2518(downward, in the orientation ofFIG.25) to output OUT, depending on whether individual samplers embedded in the rungs of the wrapper ladder are within their operating margins. Accordingly, in the wrapper illustrated inFIG.25, a single sample SFQ pulse provided at the input2506results in a train of time-separated output SFQ pulses at the output OUT. The pulse generators in the arrangement2500(e.g., pulse generators2502,2508) each comprise a Josephson junction having a first end that is grounded through an inductor and a second end that is inductively coupled to an AC bias transformer (e.g., through a coupling transformer). The second end effectively provides the output of the pulse generator. Each pulse generator outputs an SFQ pulse to its corresponding ladder rung with each cycle of the AC clock by which the pulse generator is driven, provided that the pulse generator is driven within its operating range, e.g., provided that the amplitude of the AC clock that drives the pulse generator is within the AC operating margins of the pulse generator. The Josephson junctions of the pulse generators can be sized to be larger than, and thus can have a larger critical current than, Josephson junctions used withing the JTLs and gates of the operational RQL circuitry102, in order to help reduce variability of the pulse generator Josephson junctions. Each pulse generator output is gated by the sample signal via a corresponding gate (e.g., gates2504,2510inFIG.25). Thus, although each pulse generator operates continuously to provide repeated SFQ outputs to its corresponding rung so long as the provided AC bias is within the operating margins of the pulse generator, only the SFQ outputs generated substantially contemporaneously with the arrival of the sample signal pulse on the same rung (e.g., within the same AC clock cycle or half clock cycle) propagate down output rail2518to the output OUT. The operating range of each pulse generator in the sensing system ofFIG.25can be individually set, for example, by configuring each pulse generator with a stronger or weaker coupling to one or more AC clock resonators and/or DC bias lines that provide biasing to (drive) the pulse generator. For example, the XACmargins of the pulse-generator-based samplers in the sensing system ofFIG.25can be shifted (offset) such that the pulse generators can go into and out of operation with varying provided levels of AC bias (with varying amplitudes of the driving AC clock) and their operating level can be determined even while the bias point variation that enables the sensing allows operational RQL circuitry102to remain within its operating margins. An XACmargin shift can in some examples be implemented by increasing the critical current of the JJs in the pulse generators. An increase in the critical current of the JJ of a pulse generator in a pulse-generator-based sampler has the effect of moving the corresponding sampler's margin shmoo plot up and to the right in an XDC-XACplot like that ofFIG.3, because higher-than-usual DC and AC bias amplitudes are needed to flip the pulse generator JJ due to its increased critical current. The JJ critical current can be chosen such that AC and DC bias produced by the pulse generator bias coupling transformer is at the threshold of causing the pulse generator JJ to trigger with every AC clock cycle at an XDC-XACbias point that lies within the margin shmoo plot (operating region) of operational JTL circuitry102. For example, the margin shmoo plot (operating region) of a pulse-generator-based sampler can be positioned within that of operational JTL circuitry102so that the pulse-generator-based sampler can be driven into and out of the operating region in which it produces pulses by varying the bias delivered to both the pulse-generator-based sampler and the operational RQL circuitry102even while delivered bias remains within the operating region of the operational RQL circuitry102and the operational RQL circuitry102therefore remains functional. As with the example ofFIG.2A, the pulse-generator-based samplers inFIG.25can have their XACand/or XDCoperating margin offsets staged, and such staging can be linear along the ladder, e.g., from lowest to highest AC margins, or highest to lowest, or in any other arrangement that can be considered when evaluating the output. XDCstaging can be provided in the pulse-generator-based samplers ofFIG.25by, for example, varying the length of the DC portion of the coupling transformer, in effect shifting the respective margin shmoo plots of the pulse-generator-based samplers left and right in the XDC-XACspace as shown inFIG.5A. The pulse-generator-based samplers inFIG.25can be arranged on the RQL IC106to tap a clock resonator104at various points along the resonator. Although not illustrated inFIG.25, input sample SFQ pulses can be provided to input2506using an input transformer coupled to input2506in a similar fashion to input transformer252shown inFIG.2A, and output SFQ pulses can be converted to voltage pulses using an output amplifier coupled to output OUT in a similar fashion to output amplifier254shown inFIG.2A. The pulse generators in the arrangement2500(e.g., pulse generators2502,2508) are sensitive to fabrication variations in the JJs that make them up and to clock resonator and coupling transformer variations, with a comparatively smaller sensitivity to other circuit parameters relative to samplers based on JTLs or gates with large self-inductances as described above with regard toFIGS.6,8A,9A,10A,11A,12,13,16, and18. For example, the pulse-generator-based samplers ofFIG.25are not especially sensitive to variations in inductances on the circuit side of the ground plane in an RQL IC106. The arrangement2500is therefore especially well-suited for evaluating the performance of clock resonators and coupling transformers, e.g., when assessing the self-inductance of coupling transformers, the mutual inductance between coupling transformers and the clock resonators to which they are coupled, and the magnitude of current in clock resonators. The pulse generators in the arrangement2500can be configured to measure I-specific (Q-independent) or Q-specific (I-independent) readings by coupling the samplers to appropriate clock bias resonators, as described above with regard toFIGS.12,13,16, and18, and as set out in Table 1. Pulse generators in the arrangement2500can also be configured to measure the phase difference between the I and Q clocks (in some examples, with AC bias amplitudes first having been calibrated for both I and Q clock bias signals) by driving pairs of pulse generators in a single wrapper, or by driving pluralities of pulse generators in different wrappers, with mixed clock signals separated by 90°, e.g., by driving a first pulse generator (or a first set of pulse generators in a first wrapper of pulse-generator-based bias-level sensors) with a 45° clock and a second pulse generator (or a second set of pulse generators in a second wrapper of pulse-generator-based bias-level sensors) with a 135° clock, or driving a first pulse generator (or a first set of pulse generators in a first wrapper of pulse-generator-based bias-level sensors) with a 225° clock and the a second pulse generator (or a second set of pulse generators in a second wrapper of pulse-generator-based bias-level sensors) with a 315° clock. The outputs of 45° and 135° driven pulse generators (or 225° and 315° driven pulse generators, etc.) are equal only at a 90° phase difference between the two driving clocks and when AC amplitudes of AC signals provided by the I and Q clock resonators are equal. This mixed-clock setup can therefore be used to determine true quadrature between the I and Q clock signals and can be used to inform or command adjustments to the I and Q clock phases, or adjustments to a difference in phase between the I and Q clock phases, so as to improve or optimize the quadrature to 90° of phase difference between the I and Q clocks. As an example, a process as described with reference toFIG.30can be used with the arrangement2500to determine the optimum phase difference between the I and Q clocks at which the I and Q clocks should be driven in the warm space to achieve true quadrature (90° phase separation) between the clocks at the operational RQL circuitry102on the RQL IC106in the cold space. FIG.26Ashows an example arrangement of samplers2602-2610arranged in a DC SQUID-based bias-level sensor2600. The samplers2602-2610can be based on JTLs or RQL gates, as described above with regard toFIG.6, and can comprise one or more sampler stages in series with each other, as described above with regard toFIGS.15and21. The samplers2602-2610act as triggers for DC SQUIDs2612-2620. Each sampler2602-2610has one of its parameters, such as XACor XDC, staged such that the number of DC SQUIDs2612-2620in a stack that are activated when an input pulse is applied to the sample signal input on the left ofFIG.26Avaries according to a bias level provided to the samplers2602-2610. The voltage level of an output pulse generated by the stack of DC SQUIDs2612-2620therefore varies according to the provided bias level. The arrangement2600can thus be considered as a single bias-level sensor having a voltage output that varies with the number of individual samplers2602-2610biased within their operating regions at the time a sample signal pulse is provided to the sample signal input. The output voltage can in turn be indicative of the sensed bias parameter (AC bias amplitude or DC bias value) that the sensor2600is configured to measure, given appropriate staging of the bias coupling strengths of the sensors2602-2610, as has been discussed above with respect toFIGS.4A and5A, for example. Because sensor2600can measure the outputs of individual sensors2602-2610in parallel and simultaneously, sensor2600can have higher output throughput than the arrangements ofFIGS.2A-2C. Sensor2600generates an output voltage pulse each time an input SFQ pulse is applied at the sample signal input, which can be as often as once every AC clock cycle. Each DC SQUID2612-2620of the DC SQUID stack of sensor2600receives its input from a respective sampler2602-2610via a respective transformer coupling to the DC SQUID, each respective transformer coupling being illustrated inFIG.26Aas a broken line between each sampler2602-2610and the respective DC SQUID2612-2620to which the sampler is transformer-coupled. Each sampler can, for example, be a JTL with its respective AC offset inductor LoffsetACsize-adjusted to provide both the desired XACoffset from the nominal (as shown inFIG.3) and the desired staging (inter-sampler variation). In the example ofFIG.26A, the DC SQUID stack is illustrated as including stages (five samplers2602-2610and five corresponding DC SQUIDs2612-2620), but in other examples, the stack can include more or fewer stages (more or fewer samplers and corresponding DC SQUIDs), with more stages providing finer output voltage signal resolution, or permitting for sensing multiple bias parameters. For example, some of the samplers2602-2610can be configured to sense AC bias amplitude while others can be configured to sense DC bias value, or some of the samplers2602-2610can be configured to sense AC bias amplitude of one clock resonator, I or Q, or some combination of clock signals, while others can be configured to sense AC bias amplitude of a different clock resonator, or some different combination of clock signals. In different examples, the structure of sensor2600ofFIG.26Acan have between five and ten stages. A sample signal input can be provided to each of the samplers2602-2610, e.g., via a binary vine tree of JTLs (not shown) such that, in some examples, the sample signal arrives at each of the samplers2602-2610substantially simultaneously. As in the examples described above (e.g., the examples ofFIGS.2A and25), the samplers can be XACshifted and/or can be XACstaged and/or XDCstaged with variation in mutual inductance to the respective AC resonator or DC bias line measured by the individual sampler. A DC bias current IBIASOUT, which by itself is insufficient to trigger any of the SQUIDs2612-2620, is driven between OUTP and OUTN to bias the SQUID stack such that any current provided by an input sample pulse distributed to SQUIDs2612-2620via samplers2602-2610is sufficient to trigger the respective SQUID. Because IBIASOUTcan be provided externally to the RQL IC106on which the sensor2600is implemented, and because the voltage signal across OUTP and OUTN can be made available at the pads of the RQL IC106, the signal from the sensor ofFIG.26Acan be available for direct measurement, e.g., by external test equipment, and need not require logic to process or interpret its output. In the example illustrated inFIG.26A, five samplers2602-2610are XACstaged with the AC amplitude margin variation given by the values XAC1-XACNshown in the boxes representing samplers2602-2610. For example, a resonator clock network can be fabricated on an RQL IC106to run underneath the samplers2602-2610, and a different AC offset inductor LoffsetACcan be provided to each sampler2602-2610to mutually couple power to the respective sampler based on the I and Q bias signal required for the clock phase desired to be provided to the sampler. InFIG.26A, an XACvalue of 100% signifies the bias level that the sampler is rated for, and variations of the XACvalue signify greater or lesser AC bias levels coupled into the samplers. XACvalues of 75%, 87.5%, 100%, 112.5%, and 125% are given inFIG.26Aas examples for linear staging of a five-sampler arrangement as shown inFIG.26A. In operation, the strength of a bias level provided to all the samplers2602-2610can be externally varied as sample signal input pulses are provided to sensor2600, and the different strengths of bias into each of the samplers2602-2610can result in a different number of the SQUIDs2612-2620contributing to the potential difference between output voltage terminals OUTP and OUTN, depending upon how many of the samplers are operative under the provided bias condition. For example, a sampler2610having an XACvalue of 125%, due to sampler2610having been configured to be biased via an AC offset inductor LoffsetACof an appropriate inductance value, requires a higher AC bias level to transfer an input sampler pulse to its respective DC SQUID2620, whereas sampler2602, having an XACvalue of 75%, due to sampler2602having been configured to be biased via a smaller AC offset inductor LoffsetAC, requires a relatively lower AC bias level to operate. By contrast, the sampler2602with an XACvalue of 75% can continue to operate with a higher bias current (because the higher provided bias current is inside of its operating region) even when the sampler2610with an XACvalue of 125% will not continue to operate (because the AC bias level is below, and thus is outside of, its operating region). For example, in the arrangement2600ofFIG.26A, if each SQUID2612-2620, when activated by an operational corresponding sampler2602-2610, generates a potential difference of about 0.5 mV, then the voltage output between OUTP and OUTN is about 2.5 mV when the provided bias level is within the respective operating regions of all samplers2602-2610. This output voltage is reduced when fewer than all of the samplers2602-2610are provided bias within their respective operating regions. For example, the output voltage of arrangement2600may be about 2 mV when the provided bias level is such that only four samplers2602-2610are operational, about 1.5 mV when the provided bias level is such that only three samplers2602-2610are operational, about 1 mV when the provided bias level is such that only two samplers2602-2610are operational, about 0.5 mV when the provided bias level is such that only one of the samplers2602-2610is operational, and about 0 mV when the provided bias level is such that none of the samplers2602-2610is operational. In the five-stage example ofFIG.26A, the AC bias amplitude can be considered to be calibrated when the amplitude is varied to obtain about three-fifths of the maximum output voltage pulse height. In the five-stage example ofFIG.26A, the AC bias amplitude can be considered to be calibrated when samplers2602and2604are within their operating ranges and therefore provide the split input sample signal to their respective SQUIDs2612,2614, when samplers2608and2610are outside of their operating ranges and therefore do not provide the split input sample signal to their respective SQUIDs2618,2620, and when sampler2606is just within its operating range and therefore just provides the split input sample signal to its corresponding SQUID2616. Operational RQL circuitry102inFIG.1can include output amplifiers similar in structure to the sensor ofFIG.26Athat can be required to be biased with an output bias current IBIASOUTof an appropriate current level, which can vary with variations in circuit fabrication process and/or system setup.FIG.26Bshows an example DC SQUID-based output amplifier2650configured as an output bias current IBIASOUTlevel sensor capable of sensing, for example, how well the applied level of output bias current IBIASOUTmeets the needs of an output amplifier to which the output bias current IBIASOUTis applied. The arrangement2650ofFIG.26Bis similar to arrangement2600ofFIG.26A, except that rather than the AC offset inductors LoffsetACof corresponding samplers2602-2610being staged in their inductance values, the standard-bias samplers2652-2660have no difference in self-inductance with respect to each other (e.g., no AC offset inductors LoffsetAC), and instead the critical currents Icof JJs in corresponding DC SQUIDs2662-2670are staged in their respective offsets with respect to a nominal value. In the example arrangement2650illustrated inFIG.26B, the JJs of SQUID2666have the nominal value (IC3=100%), whereas other SQUIDs in the stack have JJs fabricated to have lower critical currents (e.g., SQUIDs2662,2664, having JJs with critical currents Ic1=75% and Ic2=87.5%, respectively) or higher critical currents (e.g., SQUIDs2668,2670, having JJs with critical currents Ic4=112.5% and IcN=125%, respectively). As with the example shown inFIG.26A, the example ofFIG.26Bcan have more or fewer DC SQUIDs in its DC SQUID stack, with more stages providing finer output voltage signal resolution. In the example2650ofFIG.26B, the output bias current IBIASOUT, provided between the output terminals OUTP and OUTN, can be varied to determine the optimum DC bias on an output amplifier bias line, i.e., the optimum bias current for the SQUIDs2662,2664,2666,2668, and2670. For example, when a five-SQUID stack is used as shown inFIG.26B, the output amplifier output bias current IBIASOUTcan be varied to obtain about three-fifths the full output voltage pulse height with each sample SFQ pulse provided to the sample signal input. The example arrangement2650ofFIG.26Bdoes not de-couple the respective effects of AC and DC bias on the samplers2652-2660that trigger the SQUIDs2662-2670, or any other JTLs in the circuit. The example arrangement2650can be used, for example, to calibrate an output bias current IBIASOUTprovided to output amplifiers on RQL IC106, XACand XDChaving first been independently adjusted, improved, or optimized, the output amplifier output bias current IBIASOUTcan subsequently be adjusted, improved, or optimized. Because the output-amplifier-based arrangements2600,2650ofFIGS.26A and26Bprovide an instantaneous indication of the number of operational samplers in the arrangement for each provided sample signal, these arrangements improve throughput of the bias-level sensing output as compared to an RQL scan register arrangement like that ofFIG.2A or25, a ring oscillator arrangement like that ofFIG.2C, or a PML shift register arrangement like that ofFIG.24, each of which may take a longer time than an output-amplifier-based arrangement to provide a complete output indicative of the bias parameter being sensed. In some examples (not illustrated), a different amount of time delay can be added to each branch of the output-amplifier-based arrangements2600,2650ofFIGS.26A,26B(e.g., by adding a different number of additional standard-bias JTLs to samplers of each branch of the output-amplifier-based arrangements2600,2650ofFIGS.26A,26B) to enable time-division multiplexing. For example, a phase shift can be added at 90° increments or 45° increments. In one example, each branch of the output amplifier structure2600or2650ofFIGS.26A,26Bhas (from top to bottom, e.g.) time delay to assign a phase of 0°, 45°, 90°, 135°, 180°, etc. This example arrangement provides a time-based step function signal at the output, with the output signal stepping up in 0.5 mV increments at each time step, or not stepping up, depending on whether the SQUID of the corresponding stage of the output amplifier arrangement was induced to fire, which, in the example ofFIG.26A, would in turn depend on whether the corresponding JTL-based sampler2602-2610was within its operating range. The time-staggered output could then be used to identify which of the samplers2602-2610delivered a signal to their corresponding SQUIDs2612-2620, triggering the corresponding SQUID2612-2620or not. A serial-output ladder wrapper (RQL scan register) structure like that ofFIG.2Acan also be used to calibrate output amplifier output bias current, by implementing its bias-level sensors202-212as output amplifier emulators. JTL-based bias-level sensors configured as output amplifier emulators can have the following distinctive characteristics. First, each bias-level sensor configured as an output amplifier emulator can have the AC bias transformer(s) of its respective JTL(s) coupled to a clock resonator via a lower than standard mutual inductance. Second, each bias-level sensor configured as an output amplifier emulator can have the DC bias transformer(s) of its respective JTL(s) coupled to the output amplifier output bias current (IBIASOUTinFIG.26B), rather than to a different DC bias line. Each output amplifier emulator thus derives its DC bias from an output amplifier output bias line of RQL IC106. Third, the sensitivity of the JTLs in each output amplifier emulator to output amplifier output bias current can be configured to be similar to that of the SQUIDs in the output amplifiers that the output amplifier emulators are configured to emulate. For example, JJs in the JTLs of the output amplifier emulators can be sized to have critical currents that approximate the critical currents of the JJs in the DC SQUIDs of the output amplifier that the output amplifier emulators are configured to emulate. When the bias-level sensors202-212of the serial-output ladder arrangement200ofFIG.2Aare configured as output amplifier emulators having the above three characteristics, the pulse count provided at the output of the ladder structure200configured with output amplifier emulators as bias-level sensors202-212is representative of how well the output amplifier output bias current is adjusted for the SQUIDs in the output amplifier that the output amplifier emulators are configured to emulate. As described above with regard to bias-level sensing arrangements configured for calibrating AC bias amplitude or DC bias value, the mutual inductance to the output amplifier output bias line of each bias-level sensor configured as an output amplifier emulator can be varied in stages so that each output amplifier emulator provides the desired XOA. For example, with regard to the example arrangement200ofFIG.2A, and implementing each bias-level sensor202-212as an output amplifier emulator, output amplifier emulator202could have a smaller mutual inductance to the output amplifier output bias line than output amplifier emulator204, output amplifier emulator204could have a smaller mutual inductance to the output amplifier output bias line than output amplifier emulator206, and so on for each rung of the wrapper ladder structure200. Thus, as the output amplifier output bias is varied, more or fewer of the output amplifier emulators202-212produce pulses, and the pulse count of the serial output of the wrapper is varied. With respect to the above-described output amplifier emulator example, the output amplifier output bias current can be adjusted, improved, or optimized by direct observation of the output amplifier outputs, without using the output amplifier emulator. Such variance of the output amplifier output bias current during direct observation of the output amplifier outputs can require varying the output amplifier output bias current over a range that includes disabling the output amplifier being observed. Once the optimal bias has been determined by such a method, the pulse count from a serial-output wrapper ladder sensor having its bias-level sensors202-212configured as output amplifier emulators can be noted and used to maintain the optimum output amplifier output bias current even while the output amplifier continuously remains in operation, because the output amplifier output bias current can then be kept within the operating range of the output amplifier being emulated. In such a case, it is not necessary for the output amplifier emulators to emulate the JJ critical current characteristics of the SQUIDs of the output amplifier being emulated, that is, the output amplifier emulators need not be configured to fulfill the third characteristic described above. FIGS.27A and27Bshow example feedback systems2700,2750that can be used for sensing and tuning I clock and Q clock AC amplitudes (FIG.27A) and phase (FIG.27B). In each ofFIGS.27A and27B, two RQL bias-level sensors2702,2704,2708,2710can be implemented as shown inFIG.26AorFIG.26B. The sensors2702,2704,2708,2710can be implemented as all or part of the sensors118on the RQL IC106in the cold space. In the example illustrated inFIG.27A, the first sensor2702is powered on the 90° clock (the Q clock). The second sensor2704is powered on the 0° clock (the I clock). AC bias amplitudes provided to the I and Q clocks can be sensed contemporaneously by the two sensors2702,2704. The outputs OUTPQ, OUTPI of the sensors2702,2704have the form of voltage pulse trains of time-varying voltage height. The pulses in the pulse trains can be configured to be produced, for example, at a rate of once every AC clock cycle. The respective output signals OUTPQ, OUTPI provided by the sensors2702,2704are each of a large enough voltage amplitude that they can be analyzed by AC amplitude adjustment logic2706that can, for example, be provided as part feedback loop122to bias signals generator(s)110outside of the cold space. AC amplitude adjustment logic2706can, for example, be implemented in conventional semiconductor circuitry (e.g., CMOS circuitry). A third input to AC amplitude adjustment logic2706, labeled AMPREF, provides an AC or DC signal representative of an ideal nominal level desired to be provided out of the two sensors2702,2704. The output QOUT at the top of logic2706commands a change in the output of the clock source for Q clock (the 90° clock source), the output IOUT at the bottom of logic2706commands a change in the output of the clock source for the I clock (the 0° clock source), and amplitude reference signal AMPREF is descriptive or representative of the level at which the clock sources should be regulated. The reference signal AMPREF could, for example, be representative of the height of the pulses produced by sensors2702and2704. AC amplitude adjustment logic2706can be configured to perform a voltage comparison of the provided bias sensing signals OUTPQ, OUTPI and to generate one or more control signals based on the comparison of the OUTPQ and OUTPI signals. For example, if the AC amplitudes of the 0° I clock and 90° Q clock, as sensed on the RQL IC106by sensors2704,2702, are near or consistent with the optimal AC bias point306, then the outputs OUTPQ, OUTPI of sensors2702,2704are equal, and the outputs QOUT, IOUT of the logic2706does not command a change in AC amplitudes of either clock112,114. If, however, the AC amplitudes of the 0° I clock and the 90° Q clock, as sensed on the RQL IC106by sensors2704,2702, differ, or if either of them is inconsistent with an optimal AC bias setting for its respective clock, then the outputs OUTPQ, OUTPI of sensors2702,2704are not equal, and one or both of the outputs QOUT, IOUT of the logic2706then commands a change in AC amplitudes of either clock112,114. Following the AC amplitude calibration of the I and Q clocks performed by the arrangement ofFIG.27A, the arrangement ofFIG.27Bcan be used to sense and calibrate relative phase of the I and Q clocks to ensure that the phase difference between the I and Q clocks, as provided to the operational RQL circuitry102on the RQL IC106in the cold space, is 90°. The bias-level sensor arrangement ofFIG.27Bis structurally identical to the arrangement ofFIG.27A, except that first sensor2708inFIG.27Bis provided a 45° clock formed by tapping both the I and Q resonators, rather than a 90° formed by tapping the Q resonator only, as in sensor2702ofFIG.27A, and second sensor2710inFIG.27Bis provided a)−45° (315° clock formed by tapping both the Q and I resonators, rather than a 0° clock formed by tapping the I resonator only. Clock signals produced by a 45° transformer or a 135° transformer on the RQL IC106are dependent on both the phase difference and the amplitudes of the I clock and Q clock. A phase mismatch between the I clock and the Q clock at the level of the RQL IC106in the cold space can cause the 45° and 135° signals to have AC amplitude variation. By powering the samplers in sensor2708with a 45° clock as inFIG.27B, a mismatch in output voltage between 45° sensor2708output OUTPIQ and −45° sensor2710output OUTPQI is indicative of a phase difference that differs from 90° between the I clock and the Q clock, because the only thing that can cause such a sensor output voltage difference is inter-clock phase error, once the AC amplitudes of the I clock and Q clock have been equalized. AC phase adjustment logic2712can therefore be configured to perform a voltage comparison of the provided bias sensing signals OUTPIQ, OUTPQI and to generate one or more control signals based on the comparison of the OUTPIQ and OUTPQI signals. For example, if the phase error between the 0° I clock and 90° Q clock, as sensed on the RQL IC106by sensors2708,2704, shows true quadrature (exactly 90° phase difference), then the outputs OUTPIQ, OUTPQI of sensors2708,2710are equal, and the outputs QOUT, IOUT of the logic2712does not command a change in AC phase of either clock112,114. If, however, the phase error between the 0° I clock and 90° Q clock, as sensed on the RQL IC106by sensors2708,2702, differ, then the outputs OUTPIQ, OUTPQI of sensors2708,2710are not equal, and one or both of the outputs QOUT, IOUT of the AC phase adjustment logic2712then commands a change in phase of either clock112,114. The output-amplifier-based structures ofFIGS.26A and26Bhave advantages of being able to generate a relatively large output voltages with relatively high throughput. They can be used, as shown inFIGS.27A and27B, to adjust AC amplitude and phase to tune a resonator clock. FIG.28shows an example optimization method2800that can be used to calibrate a bias signal, e.g., to an ideal calibration or close to an ideal calibration, using one or more arrangements of bias-level sensors. A sample signal, e.g., an SFQ pulse or reciprocal pulse pair, is input2802to a sampler wrapper having XACsamplers. As examples, the wrapper can be a serial-output RQL scan register like that shown inFIG.2A or25, a parallel-output arrangement like that shown inFIG.2B, a ring oscillator like that shown inFIG.2C, an DC SQUID-based arrangement like that shown inFIG.26A or26B, or a PML shift register arrangement like that shown inFIG.24. The XACsamplers can be, as examples, a JTL-based or RQL-gate-based sampler like that shown inFIG.6, a shift-register-based sampler as shown in any ofFIG.8,9,10,11,12,13,16, or18, a PML-flip-flop-based sampler as shown inFIG.24, or a pulse-generator-based sampler as shown inFIG.25. The XACsampler output can be observed2804, e.g., by circuitry that counts pulses in an output pulse train produced by a sampler wrapper like the pulses shown inFIGS.4A-4D, in the case of a serial pulse output by a wrapper like that shown inFIG.2A, by circuitry that compares an input pulse stream to an output pulse stream, in the case of a PML shift register arrangement like that shown inFIG.24, or by voltage comparison circuitry, in the case of a DC SQUID-based arrangement like that shown inFIG.26A or26Bthat outputs a voltage pulse having a value on the order of millivolts. The circuitry that observes the bias-level sensor output can be conventional semiconductor circuitry (e.g., CMOS circuitry) that operates in the warm space of the system100and need not be implemented on the RQL IC106or otherwise in the cold space. Observation2804can, in some examples, be performed by a human user, using a human-in-the-loop feedback methodology, wherein the human user observes2804the XACsampler output, makes the determination2806of optimization, and manually varies2808the AC clock amplitude. As one example, more than one of the XACsamplers (AC bias samplers) includes at least one JTL or pulse generator having a weakened AC clock resonator bias tap to an AC clock resonator of the RQL IC, as compared to an AC clock resonator bias tap of a JTL in the operational RQL circuitry102. A weakened AC clock resonator bias tap means that a larger amplitude AC bias signal is required to drive the JTL or pulse generator within its respective AC operating margins, and thus that the XDC-XACmargin shmoo plot of the AC bias sampler is shifted up with respect to the margin shmoo plot of the operational RQL circuitry102, as shown, for example, inFIG.3. As another example, more than one of the XACsamplers includes a pulse generator having a Josephson junction with a larger critical current than a Josephson junction in the operational RQL circuitry. Based on the observation2804of the XACsampler output, it can be assessed2806whether the AC bias amplitude parameter has been optimized. For example, if a number of different AC bias amplitudes have been provided to the sampler wrapper, data can be compiled showing which AC bias amplitudes produce optimal or near-optimal output results. In the case of the serial-output wrapper ofFIG.2Ahaving XACbias-level sensors having linearly staged AC operating margin offsets, for example, optimal results are produced when a medium number of XACsamplers are operational, as shown inFIG.4C. If insufficient data has been collected to draw such a conclusion, the AC clock amplitude of the AC clock resonator under test can be varied2808to a different value and a new sample signal can be input2802. This process portion2802-2808can be iteratively repeated as many times as is necessary to provide confidence that the AC bias amplitude has been optimized2810for the AC clock resonator under test (e.g., an I resonator or a Q resonator). In some example methods similar to those of method2800, the AC bias amplitude is not optimized2810, but is improved. Improvement of the AC bias amplitude can be determined by observation2804of the XACsampler output showing results that are consistent with the provided2808AC clock amplitude moving nearer to the optimal bias point306of the operational RQL circuitry102. The AC bias signal having been calibrated2098, the process2800can continue to calibrate the DC bias. A sample signal is input2812to a sampler wrapper having XDCsamplers. The wrapper can be the same wrapper or a different wrapper from that used to calibrate the AC bias amplitude in the AC bias calibration portion of method2800. The XDCsamplers can similarly be of the forms listed and described above. The XDCsampler output can be observed2814, e.g., by circuitry that counts pulses in an output pulse train produced by a sampler wrapper like the pulses shown inFIGS.4A-4D, in the case of a serial pulse output by a wrapper like that shown inFIG.2A, or by circuitry that compares an input pulse stream to an output pulse stream, in the case of a PML shift register arrangement like that shown inFIG.24, or by voltage comparison circuitry, in the case of a DC SQUID-based arrangement like that shown inFIG.26A or26Bthat outputs a voltage pulse having a value on the order of millivolts. The circuitry that observes the bias-level sensor output can be conventional semiconductor circuitry (e.g., CMOS circuitry) that operates in the warm space of the system100and need not be implemented on the RQL IC106or otherwise in the cold space. Observation2814can also be performed by a human user, using a human-in-the-loop feedback methodology, wherein the human user observes2814the XDCsampler output, makes the determination2816of optimization, and manually varies2818the DC bias value. Based on the observation2814of the XDCsampler output, it can be assessed2816whether the DC bias value parameter has been optimized. For example, if a number of different DC bias values have been provided to the sampler wrapper, data can be compiled showing which DC bias values produce optimal or near-optimal output results. In the case of the serial-output wrapper ofFIG.2Ahaving XDCbias-level sensors having linearly staged DC operating margin offsets, for example, optimal results are produced when only mid-offset-range XDCsamplers are operational, as shown inFIG.5C. If insufficient data has been collected to draw such a conclusion, the DC bias value provided to the DC bias line under test can be varied2818to a different value and a new sample signal can be input2812. This process portion2812-2818can be iteratively repeated as many times as is necessary to provide confidence that the DC bias value has been optimized2820for the DC bias line under test. Thus, both AC and DC bias signals are calibrated2820. Calibration method2800, or any portion thereof, can in some examples be performed while the operational RQL circuitry102remains continuously in operation even while its bias parameters are being adjusted, improved, or optimized. In some example methods similar to those of method2800, the DC bias value is not optimized2820, but is improved. Improvement of the DC bias value can be determined by observation2814of the XDCsampler output showing results that are consistent with the provided2818DC bias value moving nearer to the optimal bias point306of the operational RQL circuitry102. The PML-based optimization method2900ofFIG.29is described above with relation to the description of the PML shift register structure of which a portion is shown inFIG.24. Although method2900as illustrated and described relates to AC bias amplitude calibration, method2900can be modified to provide DC bias value calibration, by using flip-flops in various of the PML shift register elements staged in their respective DC bias operating margin offsets (e.g., by fabricating the flip-flop bias transformers to have different, e.g., graduated, DC bias line coupling transformer lengths), varying the DC bias value rather than the AC amplitude2908with the logical clock stopped2906and advanced2910a single clock cycle (or half-cycle), and checking for XDCoptimization rather than for XACoptimization2918following restarting2914of the logical clock and observation2916of the output data bit pattern. FIG.30shows an example optimization method3000that can be used to calibrate phase difference between different AC clock bias signals, e.g., between I and Q clocks. In some examples, AC amplitudes of the I and Q clocks are first calibrated independently of each other3002,3004, which can be done, for example, using either of methods2900or2900by using bias-level sensors that are I-clock independent or Q-clock independent, such as those shown inFIG.12,13,16,18, or24. In method3000, a sample signal, e.g., an SFQ pulse or reciprocal pulse pair, is input3002to an Xphasesampler or to a sampler wrapper having multiple Xphasesamplers. The wrapper can be a serial-output RQL scan register like that shown inFIG.2A or25, a parallel-output arrangement like that shown inFIG.2B, a ring oscillator like that shown inFIG.2C, or an output-amplifier-based arrangement like that shown inFIG.26A or26B(e.g., arranged as shown inFIG.27B). The Xphasesampler(s) can be, for example, a JTL-based sampler like that shown inFIG.21, having mixed-resonator clock inputs at four different phases each 90° from each other. The most weakly biased JTLs or gates in the Xphasesampler(s) define the minimum AC operating point (XACmin) at which the Xphasesamplers operate. The Xphasesampler output can be observed3004, e.g., by circuitry that counts pulses in an output pulse train produced by the sampler wrapper. Such circuitry can be conventional semiconductor circuitry (e.g., CMOS circuitry) that operates in the warm space of the system100and need not be implemented on the RQL IC106or otherwise in the cold space. Based on the observation3004of the Xphasesampler output, it can be assessed3006whether the clock phase difference parameter has been optimized. For example, if a number of clock phase difference values have been provided to the one or more Xphasesamplers in the sampler wrapper over a number of AC bias amplitudes in a two-dimensional search, data can be compiled showing which clock phase difference values produce optimal or near-optimal output results. Where Xphasesampler2000is used, for example, optimal results are produced when the phase error is such that XACmin, the lower limit of the operating margin of the Xphasesampler2000(the lowest AC bias amplitude at which the Xphasesampler2000remains operational) is at its lowest over a phase-error-dependent range of such XACminpoints, as shown at point2402inFIG.24. As another example, where I-specific or Q-specific XACsamplers are used, such as those shown inFIG.12,13,16, or18, optimal results are produced when the phase error is such that the phase-error-dependent plot of the XACminof an I-specific sampler crosses the phase-error-dependent plot of the XACminof a Q-specific sampler, as shown at point1902inFIG.19. As another example, where XACsamplers having mixed-resonator clocks that are 90° apart are used, such as a 45° clock sampler and a 135° sampler, are used, optimal results are produced when the phase error is such that the phase-error-dependent plot of the XACminof a first mixed-resonator sampler crosses the phase-error-dependent plot of the XACminof a second mixed-resonator sampler that is provided an AC bias signal that is 90° apart from the phase of the AC bias signal provided to the first mixed-resonator sampler, as shown at point2302inFIG.23. If insufficient data has been collected to draw a conclusion that the Xphasevalue has been optimized, more data can be collected by performing a two-dimensional search of the values of XACand Xphase. For each Xphasevalue, XACcan be varied to find XACminof the phase sampler(s). If the XACsweep has not been completed for the current Xphasevalue3008, the AC amplitude of the provided bias (whether on an I clock resonator, a Q clock resonator, or both) can be varied3010to provide a different XACinput value to the phase sampler(s), and a new input sample signal can be provided3002to the sampler wrapper. The AC sweep portion3002-3010of the process can be repeated until XACminhas been identified for the phase sampler(s) for a given Xphasevalue. Once XACminhas been found for the phase sampler for the current phase difference between the I and Q clocks, the phase difference between the I clock and the Q clock can be varied3012to a different value and a new sample signal can be input3002. This Xphasesweep process portion3002-3012can be iteratively repeated as many times as is necessary to find the XACminof the phase sampler(s) for as many values of Xphaseas is necessary provide confidence that the clock phase difference has been optimized3014for the AC clock resonators under test. The XACsweep and the Xphasesweep need not be linear sweeps; a binary search process can be used, for example, to more rapidly home in on both the XACminat each Xphasevalue, and on the Xphasevalue at which the XACminis minimum as a function of Xphase. The phase offset at which XACminis minimum (e.g., using the phase sampler2000ofFIG.20, as at point2302inFIG.23) or at which XACplots of 90°-separated samplers cross (e.g., at points1902or2202inFIGS.19and22, respectively) indicates the optimum phase offset between I and Q clocks in the warm space at which the clocks should be driven so as to obtain true quadrature (90° separation) at the operational RQL circuitry102on the RQL IC106in the cold space. The optimal XDClevel is at the XACmin. Thus, once the minimum value of XAChas been found by any method that searches values of XDCas well as XAC, the optimal value of XDCwill also be known. FIG.31shows an example optimization method3100that can be used to calibrate I and Q clock AC amplitude parameters and I and Q clock phase parameters to optimize clock bias signals delivered to an RQL IC106, using, for example, the output-amplifier-based sensors2600or2650shown inFIGS.26A and26Band the two-sensor feedback systems shown inFIGS.27A and27B. First and second sensors are driven3102with I and Q clock signals, respectively. The sensors can each be provided a sample signal, e.g., an SFQ pulse, at their respective inputs and can each provide an output voltage signal at their respective outputs. The outputs of the first and second sensors can be compared3104. The comparison3104can be done, for example, outside the cold space in which the RQL IC106resides, and can be done, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) configured to receive the output voltage signals of the first and second sensors and to perform the comparison3104. Based on the comparison3104of the outputs of the first and second sensors, and in some examples, further based on a reference signal, it can be assessed3106whether the AC clock amplitude parameters of the I and Q clocks have been optimized. For example, if the comparison3104shows no difference between the sensor outputs of the first and second sensors (e.g., OUTPQ and OUTPI inFIG.27A), and both outputs are within a tolerance range of a value indicated by the reference signal, then it can be determined that the AC amplitude parameters have been calibrated3110, and method3100can proceed to calibrate phase error between the I and Q clocks. If, however, the comparison3104shows a difference between the sensor outputs, then one or both of the AC clock amplitudes for the I and Q clocks can be varied3108, e.g., based on outputs of the comparison circuitry in the warm space, and the outputs of the first and second sensors can be re-compared3104. This process portion3102-3108can be iteratively repeated as many times as is necessary to provide confidence that the AC clock amplitudes of the I and Q clock signals have been optimized3110. The AC clock amplitudes of the I and Q clock signals having been optimized3110, first and second sensors can be biased with 90° phase-separated clock signals formed from a mix of I and Q resonator signals. For example, the first sensor can be driven with a 45° AC clock signal and the second sensor can be driven with a −45° (315°) AC clock signal. The mixed-resonator AC clock signals can be formed in accordance with Table 1, above. The first and second sensors driven3112with 90° phase-separated mixed-resonator clock signals can be the same sensors as those driven3102with the I and Q clock signals, provided a mechanism for switchable coupling of those sensors to different resonators or combinations of resonators, or one or both of them can be different than the sensors driven3102with the I and Q clock signals. As one example, a first sensor (e.g., sensor2710inFIG.27B) can be driven3112with a nominally −45° clock signal (e.g., by transformer-coupling the first sensor to both the Q and I clock resonators) and a second sensor (e.g., sensor2708inFIG.27B) can be driven3112with a nominally 45° clock signal (e.g., by transformer-coupling the second sensor to both the I and Q clock resonators). In another example, the 90° phase-separated clock signals biasing the first and second sensors can each be pure I clock and Q clock signals (e.g., 0° and 90°, 90° and 180°, or 180° and 270°). Methods for sensing phase that compare outputs of a pair of bias parameter sensors whose clock signals are formed from combinations of I and Q clock signals (e.g., at ±45°, or 45° and 135°, 135° and 225°, etc.) have the advantage of being more sensitive to phase alignment than an arrangement consisting of a pair of bias parameter sensors operating with pure I and Q clock signals, for example, at 0° and 90°, 90° and 180°, or 180° and 270°. The outputs of the first and second sensors can be compared3114. The comparison3114can be done, for example, outside the cold space in which the RQL IC106resides, and can be done, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) configured to receive the output voltage signals of the first and second sensors and to perform the comparison3114. The comparison circuitry can be the same or different circuitry from the circuitry used to perform the comparison3104of the AC-amplitude-indicative outputs in the first part of method3100. Based on the comparison3114of the outputs of the first and second sensors, and in some examples, further based on a reference signal, it can be assessed3116whether the AC clock phase error is optimized to provide true quadrature between the I and Q clock phases, that is, whether there is 90° of separation of the Q clock phase from the I clock phase as observed on the RQL IC106. For example, if the comparison3114shows no difference between the sensor outputs of the first and second sensors (e.g., OUTPIQ and OUTPI inFIG.27B), then it can be determined that the AC phase error parameter has been calibrated3120. If, however, the comparison3114shows a difference between the sensor outputs of the first and second sensors, then one or both of the AC clock phases for the I and Q clocks can be varied3118, e.g., based on outputs of the comparison circuitry in the warm space, and the outputs of the first and second sensors can be re-compared3114. This process portion3112-3118can be iteratively repeated as many times as is necessary to provide confidence that the AC clock phase error of the I and Q clock signals has been optimized3120. In the above-described example circuit structures and methods, operating regimes for test circuits can be established by electronic tests in which bias levels are varied to determine the test circuits' respective ranges of operation. The ranges of operation for the test circuits can be made different from the ranges of operation of operational RQL circuitry by fabrication differences such as differences in AC clock resonator or DC bias line coupling transformer mutual inductance values, and by the addition of self-inductance between taps and the respective JTLs or gates driven by the taps. In each different example described, the electronic tests involve applying a stimulus in the form of a logic signal and observing the presence or absence of expected logical outputs indicative of operation of the test circuits. The bounds of the operational regime can be determined by ascertaining the applied varied bias levels at which each test circuit operates correctly or fails. In some examples, the bias-level sensors and associated methods of the present application can advantageously determine how close an operational RQL circuit's operating point is to its optimal operating point while the operational RQL circuit remains operational, i.e., without causing a bias-related failure in the operational RQL circuit. By populating an RQL IC106with samplers each of which has an operating range that is constructed to be varied in a systematic way with respect to the operating ranges of the other samplers, it is possible to numerically ascertain a presently applied bias level of the RQL IC106as observed on the RQL IC106. When the samplers are provided in a wrapper having a ladder arrangement as illustrated inFIG.2A or25, the numerical determination of the present bias level can be made, for example, by counting the number of pulses provided at the output of the sampler wrapper each time a sampler pulse is provided to the input of the sampler wrapper. The bias-level sensors and associated methods of the present application can thus assess bias conditions on an RQL IC106without interfering with operation of the operational RQL circuitry102on the IC106. The bias-level sensors and associated methods of the present application are especially useful in calibrating the bias operating points of RQL systems having multiple RQL ICs. The bias-level sensors and associated methods of the present application can serve as process control monitors, i.e., on-chip instruments for assessing the performance of circuits as affected by variations in circuit (wafer) processing. The bias-level sensors and associated methods of the present application can be implemented in human-in-the-loop feedback controls or in fully automated feedback controls that can use a combination of RQL circuitry inside the cold space and non-RQL circuitry (e.g., CMOS or other semiconductor circuitry) outside the cold space to continuously or periodically make measurements of, and command adjustments to, bias signal parameters. What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements. As used herein, the term “includes” means includes but not limited to, and the term “including” means including but not limited to. The term “based on” means based at least in part on. | 144,819 |
11942938 | PRIOR ART Standard 1/D Divider Implementation—FIG.1 This simple divider will divide the clock by the 1/D ratio with a duty cycle of 50% when D is even, and with one input-clock cycle width difference when D is odd. The divider uses a counter which counts from 1 to D (box101inFIG.1) and two comparators which compare the counter to D (box102inFIG.1) and D/2 when D is even or D/2+1 when D is odd (box103inFIG.1). When one of these two comparators finds an equal result, a toggle Flip-Flop (T-FF) (box104inFIG.1) changes its state to generate the output clock. Because this T-FF is working only on the rising edge of the clock, we get a 50% duty cycle when D is even and one input-clock cycle difference between the high and the low of the output clock when D is odd. 1/D Divider Implementation with 50% Duty Cycle—FIG.2 This divider will divide the clock by the 1/D ratio with a duty cycle of 50% even when the D is odd by working on both rising and falling edges of the input clock. The divider uses a counter which counts from 1 to D (box201inFIG.2) and two comparators which compare the counter to D (box202inFIG.2) and D/2 when D is even or D/2+1 when D is odd (box203inFIG.2). When one of these two comparators finds an equal result, a T-FF which works at the rising edge of the input clock (box204inFIG.2) changes its state to generate the output clock in case D is even. Another T-FF which works at falling edge of the input clock (box205inFIG.2) changes its state when the counter is equal D/2+1 when D is odd. A XOR (box206inFIG.2) between the first T-FF which samples at the rising edge and the second T-FF which samples at the falling edge generates the output clock when D is odd. A multiplexer (box207inFIG.2) selects the output of the first T-FF which samples at the rising edge or the output of the XOR depending if D is even or odd. Because the two T-FFs are working one on the rising edge of the input clock and the other on the falling edge of the input clock, we get a 50% duty cycle even when D is odd and not like the 1/D implementation inFIG.1. The disadvantage of the 1/D divider is that it can't give an accurate frequency on the output as it can support only division by D of the input clock frequency and not by N/D as the RRM implementation does. RRM Implementation Using Clock Qualifier Approach—FIG.3 This RRM implementation creates a qualified clock pulse of the input clock at the multiplication ratio of N/D. The high pulse width of this RRM remains always one cycle of the input clock and if any logic in the design is working with the falling edge of the output clock it will be required to meet the timing constraints of the input clock which is faster than the timing constraint of the output clock. The RRM is programmed by receiving the value of N (box300inFIG.3) and D (box301inFIG.3). An adder (box303inFIG.3) adds at each rising edge of the input clock the value of N to the previous output of the adder which comes from the multiplexer (box302inFIG.3). The multiplexer chooses between passing a zero at the beginning of the count or the stored value of a register otherwise (box304inFIG.3). The register value is set according to the previous cycle's result—when the previous cycle's output of the adder is greater than D, then the register will sample the result of the adder modulo (box304inFIG.3). When the previous cycle's output of the adder is less than D, the register will sample the adder output. Whenever the adder result is greater than D, the clock qualifier (box308inFIG.3) will receive an enable signal and pass one cycle of the input clock to the output clock. Using this method, we receive for every D cycles of the input clock, N cycles on the output clock. DESCRIPTION OF THE INVENTION To get an RRM which can work on any fractional ratio and give close to 50% duty cycle, a new implementation is proposed which performs this accurate clock multiplication. This invention may be used by any system which requires an accurate clock multiplication using a rational fraction ratio and requires an output clock with close to 50% duty cycle so any negative edge logic which uses this clock can work with timing constraint of the output clock. This invention has been described as including various operations. Many of the processes are described in their most basic form, but operations can be added to or deleted from any of the processes without departing from the scope of the invention. RRM Implementation with Optimized Duty Cycle—FIG.4 The RRM implementation under this invention generates an output clock with cycle time which is the multiplication of the input clock by the fraction rational ratio of N/D while D>N. The duty cycle of the resulted output clock is close to 50% with a difference of only one half a cycle of the input-clock between the high period and the low period of output clock. The implementation under this invention is programmed by receiving the value of N (box400inFIG.4) and D (box401inFIG.4). The RRM implementation calculates the low period (box403inFIG.4) which is the number of rising and falling edges of the input clock pulses that the output clock should be at zero and the high period (box406inFIG.4) which is the number of rising and falling edges of the input clock pulses that the output clock should be at one. The low period is calculated according to the result of the D DIV N calculation (box402inFIG.4). The high period equals to the low period if N==1 (this is the same as the implementation of a 1/D divider) or equals to the low period plus one (as shown with box404inFIG.4). In addition to the above, this invention includes a counter which counts from 1 to the sum of low period+high period (box407inFIG.4) using the rising edge of the input clock. Connected to this counter are 4 T-FF's which 2 of them are sampling on the rising edge of input clock and the other two on the falling edge of input clock. These FF's are toggling when the counter equals to the following values:The first T-FF (box408inFIG.4) which samples at the rising edge of input clock toggles when the counter equals the high period or the sum of both the high and low periods.The second T-FF (box409inFIG.4) which samples at the rising edge of input clock toggles when the counter equals to half of the high period or the half of the sum of both the high and low periods.The third T-FF (box410inFIG.4) which samples at the falling edge of input clock toggles when the counter equals to the high period or the sum of both the high and low periods.The fourth T-FF (box411inFIG.4) which samples at the falling edge of input clock toggles when the counter equals to the half of the high period+1 or the half of the sum of both the high and low periods+1 When N isn't equal to 1 (this means that the implementation isn't a 1/D implementation) then the output clock is generated by a XOR (box414inFIG.4) with one AND function between the first T-FF and the third T-FF (box413inFIG.4) with another AND function between the second T-FF and the fourth T-FF (box412inFIG.4). When N is equal to 1 (this means that the implementation is a 1/D implementation), the output clock is generated either by a XOR of the first T-FF with the fourth T-FF (box416inFIG.4) when the high period is odd, or by a XOR of the first T-FF with the second T-FF (box415inFIG.4) when the high period is even. The selection between these two XOR's is done by a multiplexer (box417inFIG.4) which generates the output clock if N is equal to 1. The last multiplexer on the output (box418inFIG.4) is selecting the correct clock between the above two implementations depending on whether N is equal to 1 or not. | 7,675 |
11942939 | DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS The advantages and features of the present invention and methods for accomplishing the same will be more clearly understood from embodiments to be described in detail below with reference to the accompanying drawing. However, the present invention is not limited to the following embodiments but may be implemented in various different forms. Rather, these embodiments are provided only to complete the disclosure of the present invention and to allow those skilled in the art to understand the category of the present invention. The present invention is defined by the category of the claims. Meanwhile, terms used in this specification are to describe the embodiments and are not intended to limit the present invention. As used herein, singular expressions, unless defined otherwise in context, include plural expressions. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated elements, steps, operations, and/or components but do not preclude the presence or addition of one or more other elements, steps, operations, and/or components. FIG.2is a block diagram of an apparatus for reducing a temperature influence in measuring a switching current based on stray inductance according to the present invention. As described inFIG.1, a current detector20detects a switching current iswflowing between a Kelvin pin and a source pin, having therebetween stray inductance Lsand stray resistance Rs, through which the switching current iswof a power module10flows. the current detector20outputs the voltage vdidtderived from a differential component of the current isw. The apparatus of the present invention includes: a filter30which filters a voltage vdidtby being connected in parallel to the current detector20; an integrator40which integrates a voltage of output from the filter30; an analog-to-digital converter (ADC)50which converts an analog voltage vintgoutput from the integrator40into a digital voltage, and performs sampling of the converted digital voltage; a scaler60which converts a sampled integrator output value vintg_sampoutput from the ADC50into a current value isw_samp; and a compensator70which removes a temperature dependent dc resistance (DCR) effect from the scaled current isw_samp. Each component ofFIG.2will be described in detail. FIGS.3A and3Bare exemplary circuit diagrams of the current detector20, the filter30, and the integrator40ofFIG.2. Specifically,FIG.3Aillustrates an embodiment in which a high pass filter (HPF) is used as the filter30, andFIG.3Billustrates an embodiment in which a low pass filter (LPF) is used as the filter30. InFIG.3A, a Kelvin-to-source voltage V_KS derived from the switching current iswflowing in the power module10is Vdidt=Lsdiswdt+Rsisw. The Kelvin-to-source voltage V_KS(=vdidt) is indicated by VstrayinFIGS.3A and3B. The Vstraypasses through the filter30and is input to the integrator40. The filter30may be implemented as a resistor-capacitor (RC) filter as shown in the drawing and may be implemented as the HPF ofFIG.3Aor the LPF ofFIG.3B. Filter parameters of the filter30may be set to Rf*Cf=Ls/Rs. (Rfand Cfwill be described later) The integrator40may be implemented using an OP AMP. The integrator40operates by receiving a PWM switching signal from a controller (for example, a microcomputer). An integrator output vintgand the switching current iswhave a relationship of vintg=(1sRiCi)·sRfCfRs·(sLsRs+1)sRfCf+1isw. (wherein s denotes a constant, and Riand Ciwill be described later) Meanwhile, a reset circuit may be required to perform resetting for every switching period such that an integral value should not be accumulated when the integrator performs an integration operation. The reset circuit may be included in the integrator40. Alternatively, the reset circuit may not be included in the integrator40and may be provided as a separate circuit. The integrator40and the reset circuit will be described in detail later. Returning toFIG.2, the scaler60applies a scaling constant Kscale=RiCiRfCfRs to Vintg_sampprovided from the ADC50to output a sampled switching current isw_samp. The compensator70performs a compensation process on the sampled switching current isw_sampusing a software algorithm, and thereby outputs a current is_hatfrom which a temperature dependent DCR (stray resistance) component is removed. An integrator40will be described in detail with reference toFIGS.4to7. FIG.4illustrates an embodiment when a filter30is provided as an HPF. The HPF is an RC filter based HPF in which a filter capacitor Cfis connected to a source pin of a current detector20and a filter resistor Rfis connected to a Kelvin pin of the current detector20, and the filter capacitor Cfand the filter resistor Rfare connected in series. An output voltage V_HPF of the filter30is applied to a negative input terminal of an integrator OP AMP through an integrator resistor Ri. A positive input terminal of the OP AMP is connected to the Kelvin pin and is grounded. An integrating capacitor Ciis connected between the negative input terminal and an output terminal of the OP AMP. A reset circuit has been described above. The reset circuit is illustrated inFIG.4. The reset circuit is formed such that a switch1configured to connect both ends the integrating capacitor Ciinterworks with a switch2configured to connect both ends the filter capacitor Cf. The switch1and the switch2operate in response to a PWM switching signal S (=1 or =0) applied to a switching device(s) of a power module10. As an example, a separate circuit may be provided to generate a reset signal Vreset(seeFIG.4) for opening or short-circuiting the switch1and the switch2when the PWM switching signal is 1 or 0. That is to say, during a switching device's PWM-ON sequence in which the PWM switching signal S=1 is applied to the switching device, the reset signal Vreset=0 opens both the switch1and the switch2, and thus, the OP AMP operates as an integrator to measure a current. On the other hand, during a switching device's PWM-OFF sequence in which the PWM switching signal S=0 is applied to the switching device, the reset signal Vreset=1 short-circuits both the switch1and the switch2, and thus, energy (voltage) having been charged in the integrating capacitor Ciand the filter capacitor Cfis discharged to reset the OP AMP. FIGS.5A-5Cshow waveforms of an A-phase switching current Ia_sw, an output voltage of an integrator (Vintg*Kscale), PWM ON/OFF signal S, and a capacitor voltage Vcf of an RC filter30, for describing operations of the integration mode and the reset mode. FIG.6illustrates an embodiment when a filter30′ is provided as an LPF. Unlike that shown inFIG.4, the LPF is an RC filter based LPF in which a filter resistor Rfis connected to a source pin of a current detector20, a filter capacitor Cfis connected to a Kelvin pin of the current detector20, and the filter resistor Rfand the filter capacitor Cfare connected together. An output voltage V_LPF of the filter30′ is applied to a positive input terminal of an integrator, i.e., OP AMP. A negative input terminal of the OP AMP is connected to the source pin through an integrator resistor Ri. An integrating capacitor Ciis connected between the negative input terminal and an output terminal of the OP AMP. In addition, similar to the case ofFIG.4, a reset circuit is formed such that a switch1configured to connect both ends the integrating capacitor Ciinterworks with a switch2configured to connect both ends of the filter capacitor Cf. As described above, the switch1and the switch2operate in response to a PWM switching signal S (=1 or 0). A reset operation is the same as that ofFIG.4. In addition,FIG.7illustrates another embodiment of the HPF, that is, the filter30shown inFIG.4. While as a reset circuit there remains only the switch1connecting both ends of an integrating capacitor Ci, the switch2connecting both ends of a capacitor Cfis omitted. During a PWM-OFF sequence, the integrating capacitor Ciis reset using the switch1, and during a PWM-OFF sequence, the capacitor Cfof an HPF is reset through a path42for connecting the switch2and the capacitor Cf. Therefore, the separate switch2is not used. Next, the compensator70will be described in detail. The compensator70is implemented through a compensation algorithm using response characteristics of a three-phase inverter circuit (resistor-inductor (RL) circuit) and an RC filter. Since a power module has a temperature sensor (e.g., NTC), the compensator70may calculate a variation of a stray resistance value using the temperature sensor. The compensator70provides a current value is_hatby removing a DCR component from a current value isw(to be exact, isw_sampshown inFIG.2) using Equation below. The current value is_hatis a measured value of a switching current from which a stray resistance component is removed. That is, is-hat(t)=Isw,meas(t)-Δisw(t)-Δisw_filt(t)kRs(t)+Δisw(t)=isw,meas(t)kRs(t)+(1-1kRs(t))Δisw(t)-Δisw_filt(t)kRs(t) In Equation above, a current variation, which flows in an inverter RL circuit (i.e., stray inductance and stray resistance present between a Kelvin pin K and a source pin S of a power module), may be calculated as in Equation below. Δisw(t)=(1-e-RmLmt)·(Vs*-Es)Rm·u(t)≅tLm(Vs*-Es)·u(t) In addition, in Equation above, a filtered current variation of an Rs error (or variation) component and the inverter RL circuit may be calculated as in Equation below. Δisw_filt(t)=k2(t)·(Vs*-Es)·u(t)=ΔRsRs,25·1Rm(1-Lme-RmLmt-RfCfRme-1RfCft(Lm-RfCfRm))·(Vs*-Es)·u(t) In addition, in Equation above, a parameter for compensating for the Rserror (or variation) component may be calculated as in Equation below. kRs(t)=1+f(Rf,Cf)=1+ΔRsRs,25(1-e-tRfCf) In Equations above, 0<t<D*Ts, wherein D refers to a duty cycle having a value between 0 and 1, Rsand Lsrefer to stray resistance and stray inductance, Rfand Cfrefer to RC filter parameters (of an HPF or an LPF), Rmand Lmrefer to RL circuit parameters (for a three-phase inverter), Rs,25refers to an original Rsvalue at temperature 25° C., and ΔRsrefers to an error or variation of Rs. FIGS.8A-8Dshow simulation results showing a result of compensating for a stray resistance component according to the present invention. It shows a comparison between results before and after a compensational operation of the compensator70. Simulation conditions are as follows. A stray resistance Rs=1.5×Rs,25(at power module temperature Tc=125° C.) When a filter is applied, a sensing error is 22.5% (45 A) When a filter and a compensation algorithm are applied, a sensing error is 2% (4 A) The meanings of variables and parameters shown inFIG.8are as follows. Ias, Ibs, and Ics: A-phase, B-phase, and C-phase currents [A] Ias_hat: sampled switching current [A] of A-phase Ias_hat_f1: compensated current [A] Ia_sw: switching current [A] of A-phase Ia_sw_meas: output of the integrator multiplied by Ri×Ci/Ls[A] Ias_samp: sampled switching current [A] of A-phase Delta_IL: current variation Δisw(t) Delta_IL_filt: filtered current variation Δisw_filt(t) Krs: parameter for compensation d_calc: duty ratio According to the present invention, it is possible to increase current measurement accuracy by minimizing the influence of dc resistance (DCR) that is changed as a temperature. It is possible to reduce costs required for a switching current measuring sensor. That is, a current transducer or a Hall effect sensor is used in the existing products, but according to the present invention, costs are reduced because a magnetic core required to constitute such sensors does not need to be used. In addition, since the magnetic core is not used, a size of an inverter product including a power module can be thereby effectively reduced. Ultimately, accurate switching current can be measured by the present invention, thereby quickly and accurately detecting sensing an arm short circuit or an overcurrent phenomenon to protect a power semiconductor. While configurations of the present invention have been described above with reference to the accompanying drawings, it is by way of example only. Those skilled in the art can make various modifications and changes within the technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments but should be determined by the appended claims. | 12,564 |
11942940 | DETAILED DESCRIPTION FIG.1is a diagram showing an example system100that can implement boot capacitor charge during low power states in one embodiment. The system100can include a controller102and one or more devices including at least a device110and a device120. In an example, the system100can be implemented as a power regulator that provides an output voltage VOUT for a load104, where the power regulator can include a plurality of power stages (e.g., devices110and120). The controller102can be a master device configured to control the devices110and120. The devices110and120can be slave devices that can be current-sourced, voltage-sourced or devices implementing both current and voltage-sourced control. In an example, the devices110and120can be smart power stage (SPS) devices configured to perform voltage regulation on an input voltage VIN, with additional features such as temperature and current feedback control. In an example, the controller102may control additional devices in addition to the slave devices110and120. It will be apparent to a person of ordinary skill in the art that the system100can include additional controllers and/or power stage devices. The device110and the device120can include identical components and configured to perform the same functions. It will be apparent to a person of ordinary skill in the art that the descriptions of the device110herein are also applicable to the device120. In an example, each device among the devices110and120can include its own power converter (e.g., DC-DC converter or buck converter). Using the device110as an example, the device110can include a power converter112, where the power converter112can include a set of switching elements such as high side switching element M1and a low side switching element M2. The switching elements M1and M2can be metal-oxide-semiconductor field-effect transistors (MOSFETs). In an example, switching elements M1and M2can be n-type MOSFETs. Each one of the devices110and120can further include a controller configured to receive signals from the controller102and operate its respective power converter. For example, the device110can include a controller114that can be configured to control various components within the device110. The device110can also include a bootstrap circuit116, and the bootstrap circuit116can include a bootstrap capacitor CBOOT connected between a power supply PVCC and a driver111of the device110. It will be apparent to a person of ordinary skill in the art that the bootstrap circuit116can include additional components. The bootstrap circuit116can be a step-up circuit in response to switching element M1being a n-type MOSFET. The bootstrap circuit116can be configured to output a bootstrap voltage VBST, where VBST can be used for turning on the switching element M1. For example, when switching element M1is turned off and switching element M2is turned on, the bootstrap capacitor CBOOT in the bootstrap circuit116can be charged by the power supply PVCC, and when switching element M1is turned on and switching element M2is turned off, the bootstrap capacitor CBOOT in the bootstrap circuit116can be discharged causing an output of the bootstrap voltage VBST. The power converters in the devices110and120can be controlled or driven by a control signal being transmitted by the controller102via a pulse width modulation (PWM) line132. The control signal can be a PWM signal having at least two levels. In an example, the PWM signal can be a three level, or tri-level, PWM signal having three signal levels, such as low, mid, and high. The three levels of the PWM signal can be represented as, for example, +1, 0, and −1. It will be apparent to a person of ordinary skill in the art that the levels of a PWM signal can be represented by arbitrary values and/or signal amplitudes. The controller114can include PWM level detection circuits configured to detect a level of the PWM control signal being transmitted via the PWM line132. Based on the detected level of the PWM control signal, the controller114can determine whether to turn on switching element M1, turn on switching element M2, or turn off both switching elements M1and M2. In an example, the low-level PWM signal turn on (e.g., activate or close) switching element M2while keeping switching element M1off, the high-level PWM signal can turn on (e.g., activate or close) switching element M1while keeping switching element M2off, and the mid-level PWM signal can turn off (e.g., deactivate or open) both switching elements M1and M2. In another example, the low-level PWM signal can turn on switching element M1while keeping switching element M2off, the high-level PWM signal can turn on switching element M2while keeping switching element M1off, and the mid-level PWM signal can turn off both switching elements M1and M2. It will be apparent to a person of ordinary skill in the art that the three levels of PWM signal can be assigned to turn on or turn off different switching elements in the power converter112. In response to turning on switching element M2and turning off switching element M1, the bootstrap capacitor CBOOT in the bootstrap circuit116can be charged by a power rail or supply, labeled as PVCC, connected to the bootstrap capacitor CBOOT in the bootstrap circuit116. In response to turning on switching element M1and turning off switching element M2, the bootstrap capacitor CBOOT in the bootstrap circuit116can discharge its energy to drive the gate of switching element M1. To turn on switching element M1, the energy being discharged by the bootstrap capacitor CBOOT in the bootstrap circuit116needs to be at a level sufficient to provide a gate-source voltage VGS greater than a threshold voltage of switching element M1. The controller102can be configured to activate or enable, and deactivate or disable, a low power state of the devices110and120via a low power (LP) line134. In an example, the controller102can send an enable signal (e.g., a logic 1 signal) to the device110and the device120via the LP line134for enabling the low power state of the device110. In another example, the controller102can send a disable signal (e.g., a logic 0 signal) to the device110via the LP line134for disabling the low power state of the device110. When the low power state of the devices110and120is enabled, the devices110and120can operate under a low power state to preserve energy and power. During the low power state, various connection paths among components in the devices110and120can be shut down or disconnected, and/or various functions can be disabled, to minimize current flow within the devices110and120, thus preserving energy and power. For example, if a particular component is not needed, the particular component can be shut down to preserve power during the low power state. In an example, different levels of low power states can be enabled for the device110. For example, the device110can operate under more than one level of low power state, such as a nap mode and a sleep mode. In an example, the nap mode can cause the device110to partially shut down and the sleep mode can cause the device110to shut down relatively more components when compared to the nap mode. In an example, the nap mode can reduce power dissipation of the device110to less than a first amount of power and may recover to normal operation within a first amount of time. The sleep mode can reduce power dissipation of the device110to less than a second amount of power, where the second amount of power is less than the first amount of power, but may require a second amount of time to recover from the sleep mode, where the second amount of time is more than the first amount of time. It will be apparent to a person of ordinary skill in the art that the methods and apparatus being described herein can be applicable to different modes of low power state of a power stage and/or other types of electronic devices, providing that the components necessary for performing the methods described herein are not shut down. Further, different low power states can be enabled or disabled using different LP lines. For example, the nap mode of the devices110and120can be enabled or disabled using signals being sent on the LP line134, while the sleep mode of the device110and120can be enabled or disabled using another LP line that can be different from the LP line134. To transition from the low power state back to normal operation state, the disconnected paths can be reconnected, and the device110may need to go through a start-up process. In an example, the start-up process of the device110may include biasing various components, turning on switching element M1, etc. Thus, the bootstrap voltage being provided by the bootstrap circuit116may need to be at a level sufficient for turning on switching element M1to allow the device110to resume operation in the normal operation state. The transition time from the low power state to the normal operation state can be referred to as wake-up time (or in some other instances, recovery time). The wake-up time can include the time to ensure the bootstrap capacitor CBOOT in the bootstrap circuit116is sufficiently charged in order for the bootstrap circuit116to provide a sufficient level of VBST to turn on switching element M1. Therefore, if the bootstrap capacitor CBOOT in the bootstrap circuit116is not charged sufficiently, the wake-up time may increase causing a delay in the transition from the low power state to the normal operating state. The system100shown inFIG.1can allow the bootstrap capacitor CBOOT in the bootstrap circuit116to be charged when the device110is in a specific low power state where certain components in the device110can remain active (e.g., a nap mode). For example, under the nap mode, the controller114can be programmed to turn on and turn off switching element M2, but not turn on switching element M1, based on the control signal being sent on the PWM line132. For example, under the nap mode, the controller114can be programmed to maintain switching element M1in a deactivated state, and maintain a current state of switching element M2(e.g., not interrupting operations of switching element M2) in response to receiving a mid-level PWM signal or other levels of PWM indicating to turn off both switching elements M1and M2. In other words, the controller114can still receive a PWM control signal from the controller102, but may not react to all levels of the PWM control signal. By allowing the controller114to turn on switching element M2during the nap mode, while not reacting to other levels of the PWM control signal, the bootstrap capacitor CBOOT in the bootstrap circuit116can be charged while allowing the device110to remain in a low power state that preserves power. For example, the controller114may not need to consume additional power to pull an output voltage of the driver111to a mid-level voltage in response to receiving a mid-level PWM control signal. FIG.2is a diagram showing a timing diagram200of an example implementation of boot capacitor charge during low power states, that can be performed by the system100shown inFIG.1, in one embodiment. The timing diagram200shows a “Status” that indicates whether the device110is in a low power state (e.g., nap mode) or an operational mode (e.g., a normal operation mode). The “EN_NAP” signal can represent an enable signal being transmitted from the controller102to the device110via the LP line134. In the timing diagram200, the EN_NAP signal can be a logic low signal to activate the nap mode of the device110. It will be apparent to a person of ordinary skill in the art that some systems may activate the nap mode based on the EN_NAP signal being a logic high signal, or other levels, as well. The PWM signal shown in the timing diagram200can be the control signal being transmitted from the controller102to the device110via the PWM line132. In the example shown inFIG.2, the PWM signal is a three level PWM signal that can have a low-level, a mid-level, and a high-level. The switching elements M1and M2can be activated or deactivated based on the levels of the PWM signal. In the timing diagram shown inFIG.2, during the operational mode, a low-level PWM signal can activate switching element M2and deactivate switching element M1, a high-level PWM signal can activate switching element M1and deactivate switching element M2, and a mid-level PWM signal can deactivate both switching elements M1and M2. The controller114can be configured to selectively react to different levels of the PWM signal during nap mode. For example, the controller114can be configured to disable current that is required for high impedance sensing on the PWM input of the device110. Thus, during nap mode, the controller114of the device110can continue to operate switching element M2during nap mode, but may ignore the high-level PWM signal in order to avoid using power to operate switching element M1. The timing diagram200can be a result of an implementation of the system100where default states of switching elements M1and M2are logic high. As shown in the timing diagram200, during nap mode, the device110can continue to activate switching element M2(M2signal driven to logic high) in response to the PWM signal being a low-level PWM signal. Also, during nap mode, in response to receiving a high-level PWM signal, the controller114of the device110can maintain switching element M1in a deactivated or off state. The device110can also deactivate switching element M2(M2signal driven to logic low) in response to the PWM signal being a high-level PWM signal during nap mode. In other words, during nap mode, the device110can operate switching element M2as if the status is under the operational mode. By being able to operate switching element M2during nap mode, the bootstrap capacitor CBOOT of the device110can be charged during nap mode, and the bootstrap voltage of the device110can also be refreshed. Further, by configuring the controller114to operate switching element M2under normal operation mode, and configuring the controller114to not operate switching element M1based on the PWM signal, the bootstrap capacitor CBOOT of the device110can be charged during nap mode as the nap mode preserves power for the device110. In an example, the controller102can be also configured to implement the charging of the bootstrap capacitor CBOOT during nap mode. For example, as shown in the timing diagram200, the controller102can be configured to send a mid-level PWM signal in response to sending the EN_NAP signal. The controller102can send the mid-level PWM signal to the device110prior to the nap mode being enabled by the device110. The controller102can send the mid-level PWM signal to allow the device110to stabilize the voltages being outputted by the driver111and to ensure that switching elements M1and M2are deactivated or turned off as the nap mode begins, and to avoid creating unwanted signals being outputted by the driver111to switching elements M1and M2. The controller102can send the mid-level PWM signal having a pulse width equivalent to a transmission time from the controller102to the device110and a hand off time of, for example, j microseconds (μs) to ensure that there is sufficient time to turn off switching elements M1and M2. After a lapse of the hand off time of j μs, the controller102can send high-level and low-level PWM signals alternatively for the device110to operate switching element M2to charge the bootstrap capacitor. Therefore, the controller102can be configured to output two-level PWM signal having high level and low level, without the mid-level, during the nap mode. To transition from the nap mode to the operational mode, the controller102can send a disable signal (e.g., logic high for the EN_NAP signal) to the device110. In response to sending the disable signal, the controller102can send the mid-level PWM signal to allow the device110to stabilize the voltages being outputted by the driver111and to ensure that switching elements M1and M2are deactivated or turned off before resuming the operational mode. The controller102can send the mid-level PWM signal having a pulse width equivalent to a transmission time from the controller102to the device110and a hand off time of, for example, k μs, to ensure that there is sufficient time to turn off switching elements M1and M2and to avoid creating unwanted signals being outputted by the driver111to switching elements M1and M2. The values of the hand off time j and k can be arbitrary, can be the same, or can be different from one another, depending on a desired implementation of the system100. After a lapse of the hand off time of k μs, the controller102can control the device110according to the operational model of the device110. FIG.3is a diagram showing another timing diagram300of another example implementation of boot capacitor charge during low power states, that can be performed by the system100shown inFIG.1, in one embodiment. The timing diagram300shows a “Status” that indicates whether the device110is in a low power state (e.g., nap mode) or an operational mode (e.g., a normal operation mode). The “EN_NAP” signal can represent an enable signal being transmitted from the controller102to the device110via the LP line134. In the timing diagram300, the EN_NAP signal can be a logic low signal to activate the nap mode of the device110. It will be apparent to a person of ordinary skill in the art that some systems may activate the nap mode based on the EN_NAP signal being a logic high signal, or other levels, as well. The PWM signal shown in the timing diagram300can be the control signal being transmitted from the controller102to the device110via the PWM line132. In the example shown inFIG.2, the PWM signal is a three level PWM signal that can have a low-level, a mid-level, and a high-level. The switching elements M1and M2can be activated or deactivated based on the levels of the PWM signal. In the timing diagram shown inFIG.2, during the operational mode, a high-level PWM signal can activate switching element M2and deactivate switching element M1, a low-level PWM signal can activate switching element M1and deactivate switching element M2, and a mid-level PWM signal can deactivate both switching elements M1and M2. The controller114can be configured to selectively react to different levels of the PWM signal during nap mode. Thus, during nap mode, the controller114of the device110can continue to operate switching element M2during nap mode, but may ignore the high-level PWM signal in order to avoid using power to operate switching element M1. The timing diagram300can be a result of an implementation of the system100where default states of switching elements M1and M2are logic low, and where the device110can include pull down resistors incorporated with floating PWM outputs during the nap mode. As shown in the timing diagram300, during nap mode, the device110can continue to activate switching element M2(M2signal driven to logic high) in response to the PWM signal being a high-level PWM signal. Also, during nap mode, in response to receiving a low-level PWM signal, the controller114of the device110can maintain switching element M1in a deactivated or off state. The device110can also deactivate switching element M2(M2signal driven to logic low) in response to the PWM signal being a low-level PWM signal during nap mode. In other words, during nap mode, the device110can operate switching element M2as if the status is under the operational mode. By being able to operate switching element M2during nap mode, the bootstrap capacitor CBOOT of the device110can be charged during nap mode, and the bootstrap voltage of the device110can also be refreshed. Further, by configuring the controller114to operate switching element M2under normal operation mode, and configuring the controller114to not operate switching element M1based on the PWM signal, the bootstrap capacitor CBOOT of the device110can be charged during nap mode as the nap mode preserves power for the device110. In an example, the controller102can be also configured to implement the charging of the bootstrap capacitor CBOOT during nap mode. For example, as shown in the timing diagram300, the controller102can be configured to send a mid-level PWM signal in response to sending the EN_NAP signal. The controller102can send the mid-level PWM signal to the device110prior to the nap mode being enabled by the device110. The controller102can send the mid-level PWM signal to allow the device110to stabilize the voltages being outputted by the driver111and to ensure that switching elements M1and M2are deactivated or turned off as the nap mode begins, and to avoid creating unwanted signals being outputted by the driver111to M1and M2. The controller102can send the mid-level PWM signal having a pulse width equivalent to a transmission time from the controller102to the device110and a hand off time of, for example, j microseconds (μs) to ensure that there is sufficient time to turn off switching elements M1and M2. After a lapse of the hand off time of j μs, the controller102can send high-level and low-level PWM signals alternatively for the device110to operate switching element M2to charge the bootstrap capacitor. Therefore, the controller102can be configured to output two-level PWM signal having high level and low level, without the mid-level, during the nap mode. To transition from the nap mode to the operational mode, the controller102can send a disable signal (e.g., logic high for the EN_NAP signal) to the device110. In response to sending the disable signal, the controller102can send the mid-level PWM signal to allow the device110to stabilize the voltages being outputted by the driver111and to ensure that switching elements M1and M2are deactivated or turned off before resuming the operational mode. The controller102can send the mid-level PWM signal having a pulse width equivalent to a transmission time from the controller102to the device110and a hand off time of, for example, k μs, to ensure that there is sufficient time to turn off switching elements M1and M2and to avoid creating unwanted signals being outputted by the driver111to switching elements M1and M2. The values of the hand off time j and k can be arbitrary, can be the same, or can be different from one another, depending on a desired implementation of the system100. After a lapse of the hand off time of k μs, the controller102can control the device110according to the operational model of the device110. FIG.4is a diagram showing another timing diagram400of another example implementation of boot capacitor charge during low power states, that can be performed by the system100shown inFIG.1, in one embodiment. The timing diagram400shows a “Status” that indicates whether the device110is in a low power state (e.g., nap mode) or an operational mode (e.g., a normal operation mode). An enable signal for controlling the activation and deactivation of the nap mode can be transmitted from the controller102to the device110via the LP line134. In the timing diagram400, the enable signal can be a logic low signal to activate the nap mode of the device110. It will be apparent to a person of ordinary skill in the art that some systems may activate the nap mode based on the enable signal being a logic high signal, or other levels, as well. The PWM signal shown in the timing diagram400can be the control signal being transmitted from the controller102to the device110via the PWM line132. In the example shown inFIG.2, the PWM signal is a three level PWM signal that can have a low-level, a mid-level, and a high-level. The switching elements M1and M2can be activated or deactivated based on the levels of the PWM signal. In the timing diagram400shown inFIG.4, during the operational mode, a low-level PWM signal can activate M2and deactivate switching element M1, a high-level PWM signal can activate switching element M1and deactivate switching element M2, and a mid-level PWM signal can deactivate both switching elements M1and M2. In an example, the nap mode of the device110may be a low power state where circuits configured to detect and interpret PWN signals are disabled or shut down. Therefore, the controller102can be configured to control charging of the bootstrap capacitor CBOOT of the device110in response to the nap mode of the device110being enabled. In an example, as shown in the timing diagram400, the controller102may not be able to send any PWM signal to the device110during the nap mode. For example, the connections between the PWM input pin of the device110and other components of the device110can be disconnected. Therefore, during nap mode of the device110, the controller102can be configured to periodically disable the nap mode of the device110by periodically sending a disable signal to the device110. In response to sending the disable signal, the controller102can send a mid-level PWM signal to turn off switching elements M1and M2, then a low-level PWM signal (or high-level PWM signal, depending on whether switching element M2activates by logic high or logic low) to turn on switching element M2. Thus, the bootstrap capacitor CBOOT of the device110can be charged periodically. In an example, the bootstrap capacitor CBOOT of the device110can be charged for a predetermined amount of time (labeled as t) that can be defined by a pulse width of, for example, the low-level PWM signal shown in the timing diagram400. The controller102can send the mid-level PWM signal to the device110once again to turn off switching elements M1and M2before sending another enable signal to put the device110into nap mode once again. By allowing the controller102to exit the nap mode periodically, devices that goes into a low power state (nap mode or sleep mode) where PWM detection and interpretation circuits are shut off can charge their bootstrap capacitors during low power state. FIG.5is a flow diagram illustrating a process500to implement boot capacitor charge during low power states in one embodiment. The process can include one or more operations, actions, or functions as illustrated by one or more of blocks502,504A,504B,504C,506A,506B, and/or506C. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, or performed in parallel, depending on the desired implementation. The process500can begin at block502. At block502, a device (e.g., device110or device120shown inFIG.1) can enable a low power state. The device can include a high side switching element and a low side switching element. In an example, the device can deactivate the high side switching element and the low side switching element prior to enabling the low power state of the device. The process500can proceed from block502to one of block504A,504B, and504C. At block504A, the device can receive a PWM control signal of a first level. The process500can proceed from block504A to block506A. At block506A, in response to receiving the PWM control signal of the first level, the device can operate the low side switching element to charge a bootstrap capacitor of the device. At block504B, the device can receive a PWM control signal of a second level. The process500can proceed from block504B to block506B. At block506B, in response to receiving the PWM control signal of the second level, the device can maintain the high side switching element in deactivated state. At block504C, the device can receive a PWM control signal of a third level. The process500can proceed from block504C to block506C. At block506C, in response to receiving the PWM control signal of the third level, the device can maintain the high side switching element in deactivated state and maintain the low side switching element in a current state. In an example, the device can disable the low power state of the device. In response to the low power state of the device being disabled, the device can deactivate the high side switching element and the low side switching element. The device can resume a normal operation state of the device in response to the deactivation of the high side switching element and the low side switching element. In an example, the device can periodically disable the low power state of the device. In response to the low power state of the device being disabled, the device can operate the low side switching element of the device to charge the bootstrap capacitor of the device for a predetermined amount of time. In response to the bootstrap capacitor of the device being charged for the predetermined amount of time, the device can enable the low power state of the device to resume the low power state of the device. The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. | 31,508 |
11942941 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As integrated circuits evolve to include low and ultra-low voltage circuits, the circuits evolve to include lower supply voltages that reduce power consumption. However, lowering supply voltages increases circuit variations, such as timing variations. In standard cells, lowering the supply voltage exponentially increases timing delays through the standard cells and increases timing delay variations, such that the timing delay variations dominate the total delay time through the standard cells. In these standard cell circuits, the timing delay variation, i.e., the sigma of the timing delay, is much greater than the mean value of the timing delay. Timing variations can be improved by lowering threshold voltages Vt and/or increasing the size of the standard cells. However, lowering threshold voltages Vt and/or increasing the size of the standard cells increases the dynamic and leakage power consumption of the standard cells and the area used by the standard cells on the integrated circuit, leaving the circuit designer with power and area issues. Thus, with lower supply voltages it is difficult to achieve timing convergence while still satisfying power consumption and area constraints. This trade-off between timing delays and variations versus power consumption and area constraints creates a challenge for improving PPA in the low and ultra-low voltage circuits. Disclosed embodiments thus provide a semiconductor device, such as an integrated circuit, that includes multiple supply voltage tracks, where each of the multiple supply voltage tracks is configured to provide at least one different supply voltage. The disclosed embodiments further provide standard cells configured to be electrically connected to a supply voltage track to receive at least one supply voltage and to a reference track to receive a reference voltage, such as ground. In some embodiments, one or more of the multiple supply voltage tracks is configured to provide two or more different supply voltages. In some embodiments, the standard cells are electrically connected to a supply voltage track to receive one supply voltage. In some embodiments, the standard cells are electrically connected to a supply voltage track to receive two or more supply voltages. Advantages of the disclosed embodiments include providing multiple different supply voltages to the standard cells for optimizing the trade-off between timing delays/variations versus power consumption and area constraints. Standard cells, including devices in the standard cells, that receive higher supply voltages provide decreased timing delays and decreased timing variations, but increased power consumption and/or leakage. Standard cells, including devices in the standard cells, that receive lower supply voltages provide increased timing delays and increased timing variations, but reduced power consumption and/or leakage. Disclosed embodiments also include multiple standard cell libraries, where each of the multiple standard cell libraries is for a different supply voltage. The standard cells in one of the multiple standard cell libraries are identified for use with the supply voltage corresponding to the standard cell library. Also, standard cells that perform the same function that are in different standard cell libraries are labeled for use with the supply voltage that corresponds to their standard cell library. Disclosed embodiments further include devices that include a plurality of tiles, where each of the tiles includes multiple different supply voltage tracks. In some embodiments, a first tile includes a first combination of supply voltage tracks, and a second tile includes a second combination of supply voltage tracks that is different from the first combination of supply voltage tracks. In some embodiments, a device includes a higher speed tile that includes two or more first supply voltage tracks that each provide a first voltage and at least one second supply voltage track that provides a second voltage that is less than the first voltage, wherein the higher speed tile includes more first supply voltage tracks than second supply voltage tracks. In some embodiments, a device includes a lower power tile that includes at least one first supply voltage track that provides a first voltage and two or more second supply voltage tracks that provide a second voltage that is less than the first voltage, wherein the lower power tile includes fewer first supply voltage tracks than second supply voltage tracks. Disclosed embodiments further include a method of manufacturing an integrated circuit that includes generating multiple versions of standard cell libraries that are each for a different supply voltage; generating a supply voltage floorplan that includes a plurality of tiles that each include multiple supply voltage tracks; placing the standard cells from the multiple versions of standard cell libraries on the tiles; routing conductive nets between the standard cells; and providing a routed result of the integrated circuit. FIG.1is a diagram schematically illustrating a semiconductor device30that includes multiple supply voltage tracks32,34, and36and multiple standard cells38,40,42, and44, in accordance with some embodiments. In some embodiments, the standard cells38,40,42, and44are logic gates that perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. In some embodiments, the semiconductor device30is an integrated circuit. The semiconductor device30includes the multiple supply voltage tracks32,34, and36and two reference voltage tracks46and48. Each of the multiple supply voltage tracks32,34, and36is configured to provide one different supply voltage. Supply voltage track32is configured to provide supply voltage VDD1, supply voltage track34is configured to provide supply voltage VDD2, and supply voltage track36is configured to provide supply voltage VDD3. Each of the reference voltage tracks46and48provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, each of the multiple supply voltage tracks32,34, and36is configured to provide one or more other or different supply voltages than those depicted inFIG.1. The standard cells38,40,42, and44are configured to be electrically connected to the supply voltage tracks32,34, and36. Each of the standard cells38,40,42, and44is electrically connected to one of the supply voltage tracks32,34, and36and to one of the reference voltage tracks46and48. The standard cell Cell138is electrically connected to the supply voltage track32to receive supply voltage VDD1and to the first reference voltage track46. The standard cell Cell240is electrically connected to the supply voltage track34to receive supply voltage VDD2and to the first reference voltage track46. The standard cell Cell342is electrically connected to the supply voltage track34to receive supply voltage VDD2and to the second reference voltage track48. The standard cell Cell444is electrically connected to the supply voltage track36to receive supply voltage VDD3and to the second reference voltage track48. The standard cells38,40,42, and44are electrically connected to different supply voltage tracks32,34, and36to receive different supply voltages VDD1, VDD2, and VDD3to optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device30. Standard cells, including devices in the standard cells, that receive higher supply voltages provide decreased timing delays and decreased timing variations, but increased power consumption and/or leakage. Standard cells, including devices in the standard cells, that receive lower supply voltages provide increased timing delays and increased timing variations, but reduced power consumption and/or leakage. FIG.2is a diagram schematically illustrating a semiconductor device60that includes multiple supply voltage tracks62,64, and66including supply voltage tracks62and64that provide more than one supply voltage, in accordance with some embodiments. The semiconductor device60further includes multiple standard cells68,70,72, and74that perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. The multiple standard cells68,70,72, and74include the standard cells68,70, and72that are configured to receive more than one supply voltage. In some embodiments, the semiconductor device60is an integrated circuit. The semiconductor device60includes the multiple supply voltage tracks62,64, and66and two reference voltage tracks76and78. Each of the multiple supply voltage tracks62,64, and66is configured to provide one or more supply voltages. Supply voltage track62is configured to provide supply voltage VDD180and supply voltage VDD282. Supply voltage track64is configured to provide supply voltage VDD284, supply voltage VDD186, and supply voltage VDD388. Supply voltage track66is configured to provide supply voltage VDD3. Each of the reference voltage tracks76and78provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, each of the multiple supply voltage tracks62,64, and66is configured to provide one or more other or different supply voltages than those depicted inFIG.2. The standard cells68,70,72, and74are configured to be electrically connected to the supply voltage tracks62,64, and66. The standard cells68,70, and72are electrically connected to supply voltage tracks62and64to receive two or more supply voltages. The standard cell Cell968is electrically connected to the supply voltage track62to receive supply voltage VDD180and supply voltage VDD282and to the first reference voltage track76. The standard cell Cell1070is electrically connected to the supply voltage track64to receive supply voltage VDD284and supply voltage VDD186and to the first reference voltage track76. The standard cell Cell1172is electrically connected to the supply voltage track64to receive supply voltage VDD284, supply voltage VDD186, and supply voltage VDD388and to the second reference voltage track78. The standard cell Cell1274is electrically connected to the supply voltage track66to receive supply voltage VDD3and to the second reference voltage track78. In other embodiments, each of the standard cells68,70,72, and74is electrically connected to receive one or more other or different supply voltages than those depicted inFIG.2. The standard cells68,70,72, and74are electrically connected to different supply voltage tracks62,64, and66to receive the different supply voltages VDD1, VDD2, and VDD3to optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device60. Standard cells, including devices in the standard cells, that receive higher supply voltages provide decreased timing delays and decreased timing variations, but increased power consumption and/or leakage. Standard cells, including devices in the standard cells, that receive lower supply voltages provide increased timing delays and increased timing variations, but reduced power consumption and/or leakage. FIG.3is a block diagram illustrating an example of a computer system100configured to provide the semiconductor devices and methods of the current disclosure, including the semiconductors devices30and60ofFIGS.1and2, respectively, in accordance with some embodiments. Some or all the design and manufacture of the semiconductor devices can be performed by or with the computer system100. In some embodiments, the computer system100includes an EDA system. In some embodiments, the semiconductor devices are ICs. In some embodiments, the system100is a general-purpose computing device including a processor102and a non-transitory, computer-readable storage medium104. The computer-readable storage medium104may be encoded with, e.g., store, computer program code such as executable instructions106. Execution of the instructions106by the processor102provides (at least in part) a design tool that implements a portion or all the functions of the system100, such as the pre-layout simulations, post-layout simulations, routing, rerouting, and final layout for manufacturing. Further, fabrication tools108are included to further layout and physically implement the design and manufacture of the semiconductor devices. In some embodiments, the system100includes a commercial router. In some embodiments, the system100includes an APR system. The processor102is electrically coupled to the computer-readable storage medium104by a bus110and to an I/O interface112by the bus110. A network interface114is also electrically connected to the processor102by the bus110. The network interface114is connected to a network116, so that the processor102and the computer-readable storage medium104can connect to external elements using the network116. The processor102is configured to execute the computer program code or instructions106encoded in the computer-readable storage medium104to cause the system100to perform a portion or all the functions of the system100, such as providing the semiconductor devices and methods of the current disclosure and other functions of the system100. In some embodiments, the processor102is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In some embodiments, the computer-readable storage medium104is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system or apparatus or device. For example, the computer-readable storage medium104can include a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random-access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In some embodiments using optical disks, the computer-readable storage medium104can include a compact disk, read only memory (CD-ROM), a compact disk read/write memory (CD-R/W), and/or a digital video disc (DVD). In some embodiments, the computer-readable storage medium104stores computer program code or instructions106configured to cause the system100to perform a portion or all the functions of the system100. In some embodiments, the computer-readable storage medium104also stores information which facilitates performing a portion or all the functions of the system100. In some embodiments, the computer-readable storage medium104stores a database118that includes one or more of component libraries, digital circuit cell libraries, and databases. The EDA system100includes the I/O interface112, which is coupled to external circuitry. In some embodiments, the I/O interface112includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to the processor102. The network interface114is coupled to the processor102and allows the system100to communicate with the network116, to which one or more other computer systems are connected. The network interface114can include: wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In some embodiments, a portion or all the functions of the system100can be performed in two or more systems that are like system100. The system100is configured to receive information through the I/O interface112. The information received through the I/O interface112includes one or more of instructions, data, design rules, libraries of components and cells, and/or other parameters for processing by processor102. The information is transferred to the processor102by the bus110. Also, the system100is configured to receive information related to a user interface (UI) through the I/O interface112. This UI information can be stored in the computer-readable storage medium104as a UI120. In some embodiments, a portion or all the functions of the system100are implemented via a standalone software application for execution by a processor. In some embodiments, a portion or all the functions of the system100are implemented in a software application that is a part of an additional software application. In some embodiments, a portion or all the functions of the system100are implemented as a plug-in to a software application. In some embodiments, at least one of the functions of the system100is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all the functions of the system100are implemented as a software application that is used by the system100. In some embodiments, a layout diagram is generated using a tool such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the variable track based NDR routing, layouts, and other processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory units, e.g., one or more optical disks such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM and RAM, and a memory card, and the like. As noted above, embodiments of the system100include fabrication tools108for implementing the manufacturing processes of the system100. For example, based on the final layout, photolithographic masks may be generated, which are used to fabricate the semiconductor device by the fabrication tools108. Further aspects of device fabrication are disclosed in conjunction withFIG.4, which is a block diagram of a semiconductor device manufacturing system122and a semiconductor device manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, one or more semiconductor masks and/or at least one component in a layer of a semiconductor device is fabricated using the manufacturing system122. InFIG.4, the semiconductor device manufacturing system122includes entities, such as a design house124, a mask house126, and a semiconductor device manufacturer/fabricator (“Fab”)128, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing a semiconductor device, such as the semiconductor devices described herein. The entities in the system122are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house124, the mask house126, and the semiconductor device fab128are owned by a single larger company. In some embodiments, two or more of the design house124, the mask house126, and the semiconductor device fab128coexist in a common facility and use common resources. The design house (or design team)124generates a semiconductor device design layout diagram130. The semiconductor device design layout diagram130includes various geometrical patterns, or semiconductor device layout diagrams designed for a semiconductor device. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the semiconductor structures to be fabricated. The various layers combine to form various semiconductor device features. For example, a portion of the semiconductor device design layout diagram130includes various semiconductor device features, such as diagonal vias, active areas or regions, gate electrodes, sources, drains, metal lines, local vias, and openings for bond pads, to be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design house124implements a design procedure to form a semiconductor device design layout diagram130. The semiconductor device design layout diagram130is presented in one or more data files having information of the geometrical patterns. For example, semiconductor device design layout diagram130can be expressed in a GDSII file format or DFII file format. In some embodiments, the design procedure includes one or more of analog circuit design, digital logic circuit design, standard cell circuit design, supply voltage track design, reference voltage track design, place and route routines, and physical layout designs. The mask house126includes data preparation132and mask fabrication134. The mask house126uses the semiconductor device design layout diagram130to manufacture one or more masks136to be used for fabricating the various layers of the semiconductor device or semiconductor structure. The mask house126performs mask data preparation132, where the semiconductor device design layout diagram130is translated into a representative data file (RDF). The mask data preparation132provides the RDF to the mask fabrication134. The mask fabrication134includes a mask writer that converts the RDF to an image on a substrate, such as a mask (reticle)136or a semiconductor wafer138. The design layout diagram130is manipulated by the mask data preparation132to comply with characteristics of the mask writer and/or criteria of the semiconductor device fab128. InFIG.4, the mask data preparation132and the mask fabrication134are illustrated as separate elements. In some embodiments, the mask data preparation132and the mask fabrication134can be collectively referred to as mask data preparation. In some embodiments, the mask data preparation132includes an optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. The OPC adjusts the semiconductor device design layout diagram130. In some embodiments, the mask data preparation132includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, the mask data preparation132includes a mask rule checker (MRC) that checks the semiconductor device design layout diagram130that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the semiconductor device design layout diagram130to compensate for limitations during the mask fabrication134, which may undo part of the modifications performed by OPC to meet mask creation rules. In some embodiments, the mask data preparation132includes lithography process checking (LPC) that simulates processing that will be implemented by the semiconductor device fab128. LPC simulates this processing based on the semiconductor device design layout diagram130to create a simulated manufactured device. The processing parameters in LPC simulation can include parameters associated with various processes of the semiconductor device manufacturing cycle, parameters associated with tools used for manufacturing the semiconductor device, and/or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine the semiconductor device design layout diagram130. The above description of mask data preparation132has been simplified for the purposes of clarity. In some embodiments, data preparation132includes additional features such as a logic operation (LOP) to modify the semiconductor device design layout diagram130according to manufacturing rules. Additionally, the processes applied to the semiconductor device design layout diagram130during data preparation132may be executed in a variety of different orders. After the mask data preparation132and during the mask fabrication134, a mask136or a group of masks136are fabricated based on the modified semiconductor device design layout diagram130. In some embodiments, the mask fabrication134includes performing one or more lithographic exposures based on the semiconductor device design layout diagram130. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)136based on the modified semiconductor device design layout diagram130. The mask136can be formed in various technologies. In some embodiments, the mask136is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region, and transmits through the transparent regions. In one example, a binary mask version of the mask136includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask136is formed using a phase shift technology. In a phase shift mask (PSM) version of the mask136, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by the mask fabrication134is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer138, in an etching process to form various etching regions in the semiconductor wafer138, and/or in other suitable processes. The semiconductor device fab128includes wafer fabrication140. The semiconductor device fab128is a semiconductor device fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different semiconductor device products. In some embodiments, the semiconductor device fab128is a semiconductor foundry. For example, there may be a manufacturing facility for the front end of line (FEOL) fabrication of a plurality of semiconductor device products, while a second manufacturing facility may provide the back end of line (BEOL) fabrication for the interconnection and packaging of the semiconductor device products, and a third manufacturing facility may provide other services for the foundry business. The semiconductor device fab128uses the mask(s)136fabricated by the mask house126to fabricate the semiconductor structures or semiconductor devices142of the current disclosure. Thus, the semiconductor device fab128at least indirectly uses the semiconductor device design layout diagram130to fabricate the semiconductor structures or semiconductor devices142of the current disclosure. Also, the semiconductor wafer138includes a silicon substrate or other proper substrate having material layers formed thereon, and the semiconductor wafer138further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). In some embodiments, the semiconductor wafer138is fabricated by the semiconductor device fab128using the mask(s)136to form the semiconductor structures or semiconductor devices142of the current disclosure. In some embodiments, the semiconductor device fabrication includes performing one or more lithographic exposures based at least indirectly on the semiconductor device design layout diagram130. As described above, the semiconductor device30ofFIG.1includes multiple supply voltage tracks32,34, and36, two reference voltage tracks46and48, and multiple standard cells38,40,42, and44, where each of the multiple supply voltage tracks32,34, and36is configured to provide a different supply voltage. FIG.5is a diagram schematically illustrating a semiconductor device200that includes multiple supply voltage tracks202,204, and206including supply voltage tracks202and206that provide the same supply voltage VDD1, in accordance with some embodiments. Also, the semiconductor device200includes multiple standard cells208,210,212, and214where, in some embodiments, the standard cells208,210,212, and214are like the standard cells38,40,42, and44(shown inFIG.1), respectively, except standard cell214is configured to receive supply voltage VDD1instead of supply voltage VDD3. In some embodiments, the multiple standard cells208,210,212, and214are logic gates that perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. In some embodiments, the semiconductor device200is an integrated circuit. The semiconductor device200includes the multiple supply voltage tracks202,204, and206and two reference voltage tracks216and218. Supply voltage track202is configured to provide supply voltage VDD1, supply voltage track204is configured to provide supply voltage VDD2, and supply voltage track206is configured to provide supply voltage VDD1. Each of the reference voltage tracks216and218provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2by 10 millivolts (mV). In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2by 10 millivolts (mV). In other embodiments, at least one of the multiple supply voltage tracks202,204, and206is configured to provide one or more other or different supply voltages than those depicted inFIG.5. The standard cells208,210,212, and214are configured to be electrically connected to the supply voltage tracks202,204, and206. Each of the standard cells208,210,212, and214is electrically connected to one of the supply voltage tracks202,204, and206and to one of the reference voltage tracks216and218. The standard cell Cell1 208 is electrically connected to the supply voltage track202to receive supply voltage VDD1and to the first reference voltage track216. The standard cell Cell2210is electrically connected to the supply voltage track204to receive supply voltage VDD2and to the first reference voltage track216. The standard cell Cell3212is electrically connected to the supply voltage track204to receive supply voltage VDD2and to the second reference voltage track218. The standard cell Cell4214is electrically connected to the supply voltage track206to receive supply voltage VDD1and to the second reference voltage track218. In some embodiments, the standard cell Cell4214is a different version of the standard cell Cell444(shown inFIG.1), where the standard cell Cell4214is configured to receive the supply voltage VDD1and the standard cell Cell444is configured to receive the supply voltage VDD3. In other embodiments, one or more of the standard cells208,210,212, and214is configured to receive a different supply voltage. The standard cells208,210,212, and214are electrically connected to different supply voltage tracks202,204, and206to receive the different supply voltages VDD1and VDD2to optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device200. In some embodiments, a standard cell, such as one of the standard cells208,210,212, and214, has multiple versions for trading-off between timing delays, timing variations, and power consumption. In some embodiments, a standard cell, such as one of the standard cells208,210,212, and214, has multiple versions of the standard cell where each version of the standard cell is configured to receive a different supply voltage. For example, in some embodiments VDD2is greater than VDD1by 10 mV, such that a version of the standard cell that receives VDD2instead of VDD1has much smaller timing variations and only a small increase in power consumption. Such as in ultra-low voltage range devices. FIG.6is a diagram schematically illustrating a semiconductor device230that includes standard cells232,234,236, and238from different versions of a standard cell library, in accordance with some embodiments. Each of the different versions of the standard cell library provides standard cells configured to receive power from a selected power supply voltage. Each of the standard cells in one version of the standard cell library has a name that includes the power supply voltage of the version of the standard cell library. In some embodiments, the multiple standard cells232,234,236, and238are logic gates that perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. In some embodiments, the semiconductor device230is an integrated circuit. Each of the standard cells232,234,236, and238is configured to perform the standard cell function that is indicated in its name and to receive the supply voltage that is indicated in its name. The standard cell232is standard cell Cell1_VDD1that performs a Cell1 function and is configured to receive the supply voltage VDD1, and the standard cell234is standard cell Cell1_VDD2that performs the Cell1 function and is configured to receive the supply voltage VDD2. Thus, the standard cells232and234perform the same Cell1 function, but the standard cell232is from a standard cell library version configured to be powered by supply voltage VDD1and the standard cell234is from a standard cell library version configured to be powered by supply voltage VDD2. The standard cell236is standard cell Cell2_VDD2that performs a Cell2 function and is configured to receive the supply voltage VDD2, and the standard cell238is standard cell Cell2_VDD3that performs the Cell2 function and is configured to receive the supply voltage VDD3. Thus, the standard cells236and238perform the same Cell2 function, but the standard cell236is from the standard cell library version configured to be powered by supply voltage VDD2and the standard cell238is from a standard cell library version configured to be powered by supply voltage VDD3. The standard cells234and236are from the same standard cell library version that is configured to be powered by the supply voltage VDD2. The semiconductor device230includes multiple supply voltage tracks240,242, and244and reference voltage tracks246and248. Supply voltage track240is configured to provide supply voltage VDD1, supply voltage track242is configured to provide supply voltage VDD2, and supply voltage track244is configured to provide supply voltage VDD3. Each of the reference voltage tracks246and248provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, at least one of the multiple supply voltage tracks240,242, and244is configured to provide one or more other or different supply voltages than those depicted inFIG.6. The standard cells232,234,236, and238are configured to be electrically connected to the supply voltage tracks240,242, and244. Each of the standard cells232,234,236, and238is electrically connected to one of the supply voltage tracks240,242, and244and to one of the reference voltage tracks246and248. The standard cell232is electrically connected to the supply voltage track240to receive supply voltage VDD1and to the first reference voltage track246. The standard cell234is electrically connected to the supply voltage track242to receive supply voltage VDD2and to the first reference voltage track246. The standard cell236is electrically connected to the supply voltage track242to receive supply voltage VDD2and to the second reference voltage track248. The standard cell238is electrically connected to the supply voltage track244to receive supply voltage VDD3and to the second reference voltage track248. The standard cells232,234,236, and238are provided from selected versions of the standard cell library and electrically connected to different supply voltage tracks240,242, and244to receive the different supply voltages VDD1, VDD2, and VDD3and optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device230. The standard cells232and234are different supply voltage versions of a standard cell that performs the Cell1 function and the standard cells236and238are different supply voltage versions of a standard cell that performs the Cell2 function. The different supply voltage versions of these cell functions can be used for trade-offs between timing delays, timing variations, and power consumption. FIG.7is a diagram schematically illustrating a semiconductor device260that includes supply voltage tracks262,264, and266including supply voltage tracks262and264that provide more than one supply voltage and multiple standard cells268,270,272, and274including standard cells268,270, and272that receive more than one supply voltage, in accordance with some embodiments. In some embodiments, the multiple standard cells268,270,272, and274perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. In some embodiments, the semiconductor device260is an integrated circuit. The semiconductor device260includes the multiple supply voltage tracks262,264, and266and two reference voltage tracks276and278. Each of the multiple supply voltage tracks262,264, and266is configured to provide one or more supply voltages. Supply voltage track262is configured to provide supply voltage VDD1280and supply voltage VDD2282. Supply voltage track264is configured to provide supply voltage VDD2284, supply voltage VDD1286, and supply voltage VDD3288. Supply voltage track266is configured to provide supply voltage VDD3. Each of the reference voltage tracks276and278provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, the multiple supply voltage tracks262,264, and266can be configured to provide one or more other or different supply voltages than those depicted inFIG.7. The standard cells268,270,272, and274are configured to be electrically connected to the supply voltage tracks262,264, and266. The standard cell Cell9268is electrically connected to the supply voltage track262to receive supply voltage VDD1280and supply voltage VDD2282and to the first reference voltage track276. The standard cell Cell10270is electrically connected to the supply voltage track264to receive supply voltage VDD2284and supply voltage VDD1286and to the first reference voltage track276. The standard cell Cell11272is electrically connected to the supply voltage track264to receive supply voltage VDD2284, supply voltage VDD1286, and supply voltage VDD3288and to the supply voltage track266to receive supply voltage VDD3and to the second reference voltage track278. The standard cell Cell12274is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the second reference voltage track278. In other embodiments, the standard cells268,270,272, and274can be electrically connected to receive one or more other or different supply voltages than those depicted inFIG.7. In some embodiments, a standard cell, such as one of the standard cells268,270, and272, includes multiple devices, such as multiple transistors, that are configured to be electrically connected to different supply voltages. By connecting different devices in a standard cell to different voltage supplies, the performance of the devices and the standard cell can be improved. For example, by connecting one or more devices in a standard cell to a higher voltage, timing delays and variations can be reduced, with a small increase in power consumption. The standard cells268,270,272, and274are electrically connected to different supply voltage tracks262,264, and266to receive the different supply voltages VDD1, VDD2, and VDD3and optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device260. FIG.8is a diagram schematically illustrating the standard cell Cell9268electrically connected to the supply voltage track262and the reference voltage track276, in accordance with some embodiments. The standard cell Cell9268includes four devices290,292,294, and296. In some embodiments, a device, such as one of the devices290,292,294, and296is a transistor. In some embodiments, a device, such as one of the devices290,292,294, and296is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. The devices290,292,294, and296are electrically connected to the supply voltage track262. The device Device1290is electrically connected to the supply voltage track262to receive supply voltage VDD1280and to the reference voltage track276. The device Device2292is electrically connected to the supply voltage track262to receive supply voltage VDD2282and to the reference voltage track276. The device Device3294is electrically connected to the supply voltage track262to receive supply voltage VDD2282and to the reference voltage track276. The device Device4296is electrically connected to the supply voltage track262to receive supply voltage VDD2282and to the reference voltage track276. By electrically connecting different devices290,292,294, and296in the standard cell268to different supply voltages, the performance of the devices290,292,294, and296and the standard cell268can be improved and/or optimized. For example, if supply voltage VDD2is greater than supply voltage VDD1, then by connecting the devices292,294, and296to receive supply voltage VDD2the timing delays and variations are reduced, with a likely increase in power consumption. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device260. FIG.9is a diagram schematically illustrating the standard cell Cell11272electrically connected to the supply voltage tracks264and266and to the reference voltage track278, in accordance with some embodiments. The standard cell Cell11272includes ten devices300,302,304,306,308,310,312,314,316, and318. The standard cell Cell11272includes five devices300,302,304,306, and308on one side of the reference voltage track278and five devices310,312,314,316, and318on the other side of the reference voltage track278. In some embodiments, a device, such as one of the devices300,302,304,306,308,310,312,314,316, and318is a transistor. In some embodiments, a device, such as one of the devices300,302,304,306,308,310,312,314,316, and318is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. The devices300,302,304,306, and308are electrically connected to the supply voltage track264. The device Device1300is electrically connected to the supply voltage track264to receive supply voltage VDD2284and to the reference voltage track278. The device Device2302is electrically connected to the supply voltage track264to receive supply voltage VDD2284and to the reference voltage track278. The device Device3304is electrically connected to the supply voltage track264to receive supply voltage VDD1286and to the reference voltage track278. The device Device4306is electrically connected to the supply voltage track264to receive supply voltage VDD1286and to the reference voltage track278. The device Device5308is electrically connected to the supply voltage track264to receive supply voltage VDD3288and to the reference voltage track278. The devices310,312,314,316, and318are electrically connected to the supply voltage track266. The device Device6310is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device7312is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device8314is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device9316is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device10318is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. By electrically connecting different devices300,302,304,306,308,310,312,314,316, and318in the standard cell272to different supply voltages, the performance of the devices300,302,304,306,308,310,312,314,316, and318and the standard cell272can be improved and/or optimized. For example, if supply voltage VDD2is greater than supply voltage VDD1, then by connecting the devices300and302to receive supply voltage VDD2, instead of supply voltage VDD1, the timing delays and variations are reduced in the devices300and302, with a likely increase in power consumption. Also, if supply voltage VDD3is greater than supply voltage VDD2and supply voltage VDD1, then by connecting the devices308,310,312,314,316, and318to receive supply voltage VDD3, instead of supply voltage VDD2or supply voltage VDD1, the timing delays and variations are reduced in the devices308,310,312,314,316, and318, with a likely increase in power consumption. In addition, if supply voltage VDD1is less than supply voltage VDD2and supply voltage VDD3, then by connecting the devices304and306to receive supply voltage VDD1, instead of supply voltage VDD2or supply voltage VDD3, the power consumption is reduced in the semiconductor device260. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device260. FIG.10is a diagram schematically illustrating the standard cell Cell12274electrically connected to the supply voltage track266and to the reference voltage track278, in accordance with some embodiments. The standard cell Cell12274includes four devices320,322,324, and326. In some embodiments, a device, such as one of the devices320,322,324, and326is a transistor. In some embodiments, a device, such as one of the devices320,322,324, and326is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. The devices320,322,324, and326are electrically connected to the supply voltage track266. The device Device1320is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device2322is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device3324is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. The device Device4326is electrically connected to the supply voltage track266to receive supply voltage VDD3and to the reference voltage track278. By electrically connecting devices320,322,324, and326in the standard cell274to supply voltages, the performance of the devices320,322,324, and326and the standard cell274can be improved and/or optimized. For example, if supply voltage VDD3is greater than supply voltage VDD2and supply voltage VDD1, then by connecting the devices320,322,324, and326to receive supply voltage VDD3the timing delays and variations are reduced in the devices320,322,324, and326, with a likely increase in power consumption. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device260. FIG.11is a diagram schematically illustrating a semiconductor device400that includes supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422in different rows of the semiconductor device400, in accordance with some embodiments. Each of the supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422is in a different row, i.e., at a different vertical height, in the semiconductor device400to provide a power delivery network (PDN) of the semiconductor device400. The semiconductor device400further includes two reference voltage tracks424and426and four standard cells428,430,432, and434. In some embodiments, the standard cells428,430,432, and434perform logic functions, such as AND, OR, NOT, NAND, and NOR logic functions. In some embodiments, the semiconductor device400is an integrated circuit. Each of the supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422is configured to provide one supply voltage. Supply voltage tracks402,412, and422are each configured to provide supply voltage VDD1. Supply voltage tracks404,410,414, and420are each configured to provide supply voltage VDD2. Supply voltage tracks406,408,416, and418are each configured to provide supply voltage VDD3. Also, each of the reference voltage tracks424and426provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, the supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422can be configured to provide one or more other or different supply voltages than those depicted inFIG.11. The standard cells428,430,432, and434are configured to be electrically connected to the supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422. The standard cell Cell9428is electrically connected to the supply voltage track402to receive supply voltage VDD1, to the supply voltage track404to receive supply voltage VDD2, and to the reference voltage track424. The standard cell Cell10430is electrically connected to the supply voltage track410to receive supply voltage VDD2, to the supply voltage track412to receive supply voltage VDD1, and to the reference voltage track424. The standard cell Cell11432is electrically connected to the supply voltage track414to receive supply voltage VDD2, to the supply voltage track412to receive supply voltage VDD1, and to supply voltage track416to receive supply voltage VDD3. The standard cell Cell11432is further electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The standard cell Cell12 434 is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. In other embodiments, the standard cells428,430,432, and434can be electrically connected to receive one or more other or different supply voltages. In some embodiments, each of the standard cells428,430,432, and434includes multiple devices, such as transistors, that are configured to be electrically connected to receive supply voltages. Each of the devices is configured to be electrically connected to one of the supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422at the vertical height of the row of the selected supply voltage track. By connecting different devices in a standard cell to different supply voltages, the performance of the devices and the standard cell can be improved and/or optimized. For example, by connecting one or more devices in a standard cell to a higher voltage, timing delays and variations can be reduced with a small increase in power consumption. The standard cells428,430,432, and434are electrically connected to different supply voltage tracks402,404,406,408,410,412,414,416,418,420, and422to receive the different supply voltages VDD1, VDD2, and VDD3and optimize the trade-offs between timing delays/variations versus power consumption and area constraints in the semiconductor device400. FIG.12is a diagram schematically illustrating the standard cell Cell9428electrically connected to the supply voltage tracks402and404and the reference voltage track424, in accordance with some embodiments. The standard cell Cell9428includes four devices440,442,444, and446. In some embodiments, a device, such as one of the devices440,442,444, and446, is a transistor. In some embodiments, a device, such as one of the devices440,442,444, and446, is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. Each of the devices440,442,444, and446is configured to be electrically connected to one of the supply voltage tracks402and404at the vertical height of the row of the supply voltage track402and404in the semiconductor device400. The device440is electrically connected to the supply voltage track402and the devices442,444, and446are electrically connected to the supply voltage track404. The device Device1440is electrically connected to the supply voltage track402to receive supply voltage VDD1and to the reference voltage track424. The device Device2442is electrically connected to the supply voltage track404to receive supply voltage VDD2and to the reference voltage track424. The device Device3444is electrically connected to the supply voltage track404to receive supply voltage VDD2and to the reference voltage track424. The device Device4446is electrically connected to the supply voltage track404to receive supply voltage VDD2and to the reference voltage track424. By electrically connecting different devices440,442,444, and446in the standard cell428to different supply voltages, the performance of the devices440,442,444, and446and the standard cell428can be improved and/or optimized. For example, if supply voltage VDD2is greater than supply voltage VDD1, then by connecting the devices442,444, and446to receive supply voltage VDD2the timing delays and variations are reduced, with a likely increase in power consumption. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device400. FIG.13is a diagram schematically illustrating the standard cell Cell11432electrically connected to the supply voltage tracks412,414,416and418and the reference voltage track426, in accordance with some embodiments. The standard cell Cell11432includes ten devices450,452,454,456,458,460,462,464,466, and468. The standard cell Cell11432includes five devices450,452,454,456, and458on one side of the reference voltage track426and five devices460,462,464,466, and468on the other side of the reference voltage track426. In some embodiments, a device, such as one of the devices450,452,454,456,458,460,462,464,466, and468is a transistor. In some embodiments, a device, such as one of the devices450,452,454,456,458,460,462,464,466, and468is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. Each of the devices450,452,454,456,458,460,462,464,466, and468is configured to be electrically connected to one of the supply voltage tracks412,414,416and418at the vertical height of the row of the supply voltage track412,414,416and418in the semiconductor device400. The devices450and452are each electrically connected to the supply voltage track414, the devices454and456are each electrically connected to the supply voltage track412, the device458is electrically connected to the supply voltage track416, and the devices460,462,464,466, and468are each electrically connected to the supply voltage track418. The devices450,452,454,456, and458are electrically connected to the supply voltage tracks412,414, and416. The device Device1450is electrically connected to the supply voltage track414to receive supply voltage VDD2and to the reference voltage track426. The device Device2452is electrically connected to the supply voltage track414to receive supply voltage VDD2and to the reference voltage track426. The device Device3454is electrically connected to the supply voltage track412to receive supply voltage VDD1and to the reference voltage track426. The device Device4456is electrically connected to the supply voltage track412to receive supply voltage VDD1and to the reference voltage track426. The device Device5458is electrically connected to the supply voltage track416to receive supply voltage VDD3and to the reference voltage track426. The devices460,462,464,466, and468are electrically connected to the supply voltage track418. The device Device6460is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device7462is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device8464is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device9466is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device10468is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. By electrically connecting different devices450,452,454,456,458,460,462,464,466, and468in the standard cell432to different supply voltages, the performance of the devices450,452,454,456,458,460,462,464,466, and468and the standard cell432can be improved and/or optimized. For example, if supply voltage VDD2is greater than supply voltage VDD1, then by connecting the devices450and452to receive supply voltage VDD2, instead of supply voltage VDD1, the timing delays and variations are reduced in the devices450and452, with a likely increase in power consumption. Also, if supply voltage VDD3is greater than supply voltage VDD2and supply voltage VDD1, then by connecting the devices458,460,462,464,466, and468to receive supply voltage VDD3, instead of supply voltage VDD2or supply voltage VDD1, the timing delays and variations are reduced in the devices458,460,462,464,466, and468, with a likely increase in power consumption. In addition, if supply voltage VDD1is less than supply voltage VDD2and supply voltage VDD3, then by connecting the devices454and456to receive supply voltage VDD1, instead of supply voltage VDD2or supply voltage VDD3, the power consumption is reduced in the semiconductor device400. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device400. FIG.14is a diagram schematically illustrating the standard cell Cell12434electrically connected to the supply voltage track418and the reference voltage track426, in accordance with some embodiments. The standard cell Cell12434includes four devices480,482,484, and486. In some embodiments, a device, such as one of the devices480,482,484, and486is a transistor. In some embodiments, a device, such as one of the devices480,482,484, and486is a combination of transistors and/or other elements, such as resistors, that are configured to perform a function. Each of the devices480,482,484, and486is electrically connected to the supply voltage track418at the vertical height of the row of the supply voltage track418in the semiconductor device400. The device Device1480is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device2482is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device3484is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. The device Device4486is electrically connected to the supply voltage track418to receive supply voltage VDD3and to the reference voltage track426. By electrically connecting devices480,482,484, and486in the standard cell434to supply voltages, the performance of the devices480,482,484, and486and the standard cell434can be improved and/or optimized. For example, if supply voltage VDD3is greater than supply voltage VDD2and supply voltage VDD1, then by connecting the devices480,482,484, and486to receive supply voltage VDD3, instead of the supply voltage VDD2or the supply voltage VDD1, the timing delays and variations are reduced in the devices480,482,484, and486, with a likely increase in power consumption. Thus, the trade-offs between timing delays and variations versus power consumption and area constraints can be optimized in the semiconductor device400. FIG.15is a diagram schematically illustrating a method of manufacturing a semiconductor device, in accordance with some embodiments. The manufacturing of the semiconductor device includes design, layout, and fabrication of the semiconductor device such as by a computer system like the computer system100ofFIG.3and the semiconductor device manufacturing system122ofFIG.4. The semiconductor device can be any of the semiconductor devices described in this disclosure, or another semiconductor device. In some embodiments, the semiconductor device is one of: the semiconductor device30ofFIG.1; the semiconductor device60ofFIG.2; the semiconductor device200ofFIG.5; the semiconductor device230ofFIG.6; the semiconductor device260ofFIG.7; and the semiconductor device400ofFIG.11. In some embodiments, the semiconductor device is an integrated circuit. At step500, the method includes preparing multiple supply voltage libraries. In this step, multiple versions of standard cell libraries are constructed, where different versions of a standard cell library are made for different supply voltages. Each of the different versions of a standard cell library is characterized for providing accurate timing delays, timing variations, and power consumption information. In some embodiments, one or more standard cell layouts are changed in different versions of a standard cell library. In some embodiments, the standard cell layouts are not changed for different versions of a standard cell library, which reduces the library preparation effort. At step502, the method includes storing the different versions of the standard cell libraires in a system's memory, such as the computer system100ofFIG.3. In some embodiments, the method includes storing the different versions of the standard cell libraires in the database118of the computer-readable storage medium104in the computer system100ofFIG.3. At step504, the method includes performing an automated place and route (APR) flow. The APR flow can be performed by a computer system, such as the computer system100ofFIG.1. At step506, the method includes generating a floorplan of the semiconductor device, which includes providing multiple supply voltage tracks in the semiconductor device. In some embodiments, generating the floorplan includes providing supply voltage tracks that provide a single supply voltage, such as the supply voltage tracks shown inFIGS.1,5, and6. In some embodiments, generating the floorplan includes providing supply voltage tracks that provide one or more supply voltages per supply voltage track, such as the supply voltage tracks shown inFIGS.2and7. In some embodiments, generating the floorplan includes providing supply voltage tracks at different vertical heights in rows of the semiconductor device, such as the supply voltage tracks shown inFIG.11. In some embodiments, generating the floorplan includes providing supply voltage track tiles, where each tile has a pre-designed supply voltage track pattern. At step508, the method includes synthesis of the functions of the semiconductor device into standard cells from the multiple standard cell libraries. In some embodiments, synthesis creates a netlist of the standard cells that perform the functions of the semiconductor device. In some embodiments, synthesis is the process of transforming hardware design language (HDL) into a gate-level netlist, given all the specified constraints and optimization settings. In some embodiments, synthesis is the process of translating and mapping register transfer level (RTL) code written in HDL into technology specific gate-level representations. At step510, the method includes placement of the standard cells that perform the functions of the semiconductor device into the floorplan of the semiconductor device. The standard cells are placed in cell rows of the floorplan and electrically connected to the supply voltage tracks and supply voltages. During optimization of the timing delays, timing variations, and power consumption, the standard cells are selected from different versions of the standard cell libraries to meet the constraints of the semiconductor device. In some embodiments, each of the cell rows in the floorplan has a supply voltage track that provides one supply voltage or set of supply voltages, such that the standard cells placed in the cell row belong to a library for the supply voltage or set of supply voltages of the cell row. During optimization, information such as timing delays, timing variations, and power consumption data are taken from this library of standard cells for the cell row. Also, during optimization, the APR tool can change the supply voltage or set of supply voltages of a cell row by splitting or merging the supply voltages of the cell row to optimize timing delays, timing variations, and power consumption and meet the constraints of the semiconductor device. This provides flexibility for the APR tool to optimize the design with different supply voltages, such as for reducing timing delay, timing variation, and/or power consumption of the semiconductor device. At step512, the method includes clock tree synthesis (CTS), which is the process of connecting clocks to the clock pins of sequential circuits by using inverters and/or buffers to balance clock signal skew and minimize inverter and/or buffer insertion delay. Clock balancing is very important for meeting design constraints. CTS includes both clock tree construction and clock tree balancing. At step514, the method includes routing conductive paths between inputs and outputs of the standard cells to provide the functions of the semiconductor device. At step516, the method includes a static timing analysis (STA) and signoff of the layout. After signoff of the layout, the semiconductor device is fabricated, such as with the computer system100ofFIG.3and the semiconductor device manufacturing system122ofFIG.4. In some embodiments, one or more of the steps in the APR flow504is repeated, with or without manual manipulation, to meet the design constraints of the semiconductor device. FIGS.16and17are diagrams schematically illustrating standard cells constructed in step500of the method of manufacturing a semiconductor device ofFIG.15. At step500, the method includes preparing multiple supply voltage libraries, such as multiple versions of standard cell libraries where different versions of the standard cell libraries are made for different supply voltages. Also, in some embodiments, one or more standard cell layouts are changed in different versions of the standard cell libraries. FIG.16is a diagram schematically illustrating an inverter (INV) standard cell group520, in accordance with some embodiments. The INV standard cell group520includes four INV standard cells522,524,526, and528. In some embodiments, each of the INV standard cells522,524,526, and528is from or belongs to a different standard cell library. In some embodiments, each of the INV standard cells522,524,526, and528is from or belongs to a different version of one or more of the standard cell libraries. In some embodiments, each of the INV standard cells522,524,526, and528is from or belongs to a different version of one or more of the standard cell libraries that is for a different supply voltage. The INV standard cells522,524,526, and528have names or indexes that indicate the standard cell library or version of the standard cell libraires to which they belong. The INV standard cell Cell1522is named INV_v1, which indicates that INV standard cell Cell1522is an INV standard cell that belongs to version v1 of the standard cell libraries that is configured for use with a first supply voltage or set of supply voltages. The INV standard cell Cell2524is named INV_v2, which indicates that INV standard cell Cell2524is an INV standard cell that belongs to version v2 of the standard cell libraries that is configured for use with a second supply voltage or set of supply voltages that are different than the first supply voltage or set of supply voltages. The INV standard cells522and524have the same structure but are configured for use with different supply voltages. The INV standard cell Cell3526is named INV_m3, which indicates that INV standard cell Cell3526is an INV standard cell that belongs to version m3 of the standard cell libraries, such that the INV standard cell Cell3526has a different standard cell structure than other INV standard cells and is configured for use with one supply voltage or set of supply voltages. The INV standard cell Cell4528is named INV_m4, which indicates that INV standard cell Cell4528is an INV standard cell that belongs to version m4 of the standard cell libraries, such that the INV standard cell Cell4528has a different standard cell structure and is configured for use with another supply voltage or set of supply voltages. The INV standard cells526and528are configured for use with different supply voltages and have different standard cell structures than one another and different standard cell structures than the INV standard cells522and524. FIG.17is a diagram schematically illustrating a buffer (BUF) standard cell group540, in accordance with some embodiments. The BUF standard cell group540includes four BUF standard cells542,544,546, and548. In some embodiments, each of the BUF standard cells542,544,546, and548is from or belongs to a different standard cell library. In some embodiments, each of the BUF standard cells542,544,546, and548is from or belongs to a different version of one or more of the standard cell libraries. In some embodiments, each of the BUF standard cells542,544,546, and548is from or belongs to a different version of one or more of the standard cell libraries that is for a different supply voltage. The BUF standard cells542,544,546, and548have names or indexes that indicate the standard cell library or version of the standard cell libraires to which they belong. The BUF standard cell Cell5542is named BUF_v1, which indicates that BUF standard cell Cell5542is a BUF standard cell that belongs to version v1 of the standard cell libraries that is configured for use with a first supply voltage or set of supply voltages. The BUF standard cell Cell6 544 is named BUF_v2, which indicates that BUF standard cell Cell6 544 is a BUF standard cell that belongs to version v2 of the standard cell libraries that is configured for use with a second supply voltage or set of supply voltages that are different than the first supply voltage or set of supply voltages. The BUF standard cells542and544have the same standard cell structure but are configured for use with different supply voltages. The BUF standard cell Cell7546is named BUF_m3, which indicates that BUF standard cell Cell7546is a BUF standard cell that belongs to version m3 of the standard cell libraries, such that the BUF standard cell Cell7546has a different standard cell structure than other BUF standard cells and is configured for use with one supply voltage or set of supply voltages. The BUF standard cell Cell8548is named BUF_m4, which indicates that BUF standard cell Cell8548is a BUF standard cell that belongs to version m4 of the standard cell libraries, such that the BUF standard cell Cell8548has a different standard cell structure and is configured for use with another supply voltage or set of supply voltages. The BUF standard cells546and548are configured for use with different supply voltages and have different standard cell structures than one another and different standard cell structures than the BUF standard cells542and544. FIGS.18-23are diagrams schematically illustrating floorplans of a semiconductor device, which are generated during step506of the APR flow. At step506, the method includes generating a floorplan of the semiconductor device, which includes providing multiple supply voltage tracks in the semiconductor device. In some embodiments, the floorplan includes floorplan tiles, where each tile includes a pre-defined supply voltage track pattern. In some embodiments, the floorplan includes at least three different floorplan tiles including: a first floorplan tile that is a high-speed floorplan tile; a second floorplan tile that is a normal floorplan tile; and a third floorplan tile that is a low power floorplan tile. The floorplan tiles can have different dimensions, such as different height and length dimensions. In some embodiments, different floorplans have a different composition of floorplan tiles, such as a different relative number of each of the at least three different floorplan tiles, based on the semiconductor devices PPA goals. Higher speed designs have more high-speed floorplan tiles to accommodate more standard cells at higher supply voltages, and low power designs (power intensive designs) have more low power floorplan tiles to accommodate more standard cells at lower supply voltages. In some embodiments, the PDN of the semiconductor device includes electrically connecting different floorplan tiles of the semiconductor device. FIG.18is a diagram schematically illustrating a high-speed floorplan tile600that is at least part of a semiconductor device, in accordance with some embodiments. The high-speed floorplan tile600includes multiple supply voltage tracks602,604,606, and608and multiple reference voltage tracks610,612,614, and616. Each of the reference voltage tracks610,612,614, and616provides a reference voltage VSS, such as ground. In some embodiments, the semiconductor device is an integrated circuit. The high-speed floorplan tile600includes two supply voltage tracks602and608that provide supply voltage VDD1, one supply voltage track604that provides supply voltage VDD2, and one supply voltage track606that provides supply voltage VDD3. In this example, supply voltage VDD1is greater than supply voltage VDD2, and supply voltage VDD2is greater than supply voltage VDD3. Thus, the high-speed floorplan tile600includes 50% supply voltage tracks providing the highest supply voltage VDD1, 25% supply voltage tracks providing the supply voltage VDD2, and 25% supply voltage tracks providing the lowest supply voltage VDD3. With this composition of supply voltage tracks, the high-speed floorplan tile600can accommodate more standard cells at higher supply voltages. Standard cells are electrically connected to the supply voltage tracks602,604,606, and608to receive the supply voltages VDD1, VDD2, and VDD3and to at least one of the reference voltage tracks610,612,614, and616to receive the reference voltage VSS. Also, the floorplan tiles can have different dimensions, such as different height and length dimensions. The high-speed floorplan tile600has a height H and a length L1. In other embodiments, the high-speed floorplan tile600, as with any other tile, can have different height and/or length dimensions. FIG.19is a diagram schematically illustrating a high-speed floorplan tile620that has the same height H as the high-speed floorplan tile600ofFIG.18but a different length, in accordance with some embodiments. The length L2of the high-speed floorplan tile620is greater than the length L1of the high-speed floorplan tile600, such that the high-speed floorplan tile620can hold or accommodate more standard cells than the high-speed floorplan tile600. The high-speed floorplan tile620is at least part of a semiconductor device and includes multiple supply voltage tracks622,624,626, and628and multiple reference voltage tracks630,632,634, and636. Each of the reference voltage tracks630,632,634, and636provides a reference voltage VSS, such as ground. In some embodiments, the semiconductor device is an integrated circuit. The high-speed floorplan tile620includes two supply voltage tracks622and628that provide supply voltage VDD1, one supply voltage track624that provides supply voltage VDD2, and one supply voltage track626that provides supply voltage VDD3. In this example, supply voltage VDD1is greater than supply voltage VDD2, and supply voltage VDD2is greater than supply voltage VDD3. Thus, the high-speed floorplan tile620includes 50% supply voltage tracks providing the highest supply voltage VDD1, 25% supply voltage tracks providing the supply voltage VDD2, and 25% supply voltage tracks providing the lowest supply voltage VDD3. With this composition of supply voltage tracks, the high-speed floorplan tile620can accommodate more standard cells at higher supply voltages. Standard cells are electrically connected to the supply voltage tracks622,624,626, and628to receive the supply voltages VDD1, VDD2, and VDD3and to at least one of the reference voltage tracks630,632,634, and636to receive the reference voltage VSS. Also, in contrast to the high-speed floorplan tile600and the high-speed floorplan tile620, a normal floorplan tile (not shown) may include 33.33 . . . % supply voltage tracks providing the highest supply voltage VDD1, 33.33 . . . % supply voltage tracks providing the supply voltage VDD2, and 33.33 . . . % supply voltage tracks providing the lowest supply voltage VDD3. FIG.20is a diagram schematically illustrating a low power floorplan tile640that is at least part of a semiconductor device, in accordance with some embodiments. The low power floorplan tile640includes multiple supply voltage tracks642,644,646, and648and multiple reference voltage tracks650,652,654, and656. Each of the reference voltage tracks650,652,654, and656provides a reference voltage VSS, such as ground. In some embodiments, the semiconductor device is an integrated circuit. The low power floorplan tile640includes two supply voltage tracks642and648that provide supply voltage VDD3, one supply voltage track644that provides supply voltage VDD2, and one supply voltage track646that provides supply voltage VDD1. In this example, supply voltage VDD1is greater than supply voltage VDD2, and supply voltage VDD2is greater than supply voltage VDD3. Thus, the low power floorplan tile640includes 50% supply voltage tracks providing the lowest supply voltage VDD3, 25% supply voltage tracks providing the supply voltage VDD2, and 25% supply voltage tracks providing the highest supply voltage VDD1. With this composition of supply voltage tracks, the low power floorplan tile640can accommodate more standard cells at lower supply voltages. Standard cells are electrically connected to the supply voltage tracks642,644,646, and648to receive the supply voltages VDD1, VDD2, and VDD3and to at least one of the reference voltage tracks650,652,654, and656to receive the reference voltage VSS. Also, the floorplan tiles can have different dimensions, such as different height and length dimensions. The low power floorplan tile640has a height H and a length L1like the high-speed floorplan tile600. In other embodiments, the low power floorplan tile640, as with any other tile, can have different height and/or length dimensions. FIG.21is a diagram schematically illustrating a semiconductor device660that includes high-speed floorplan tiles662, normal floorplan tiles664, and low power floorplan tiles666, in accordance with some embodiments. Semiconductor devices, such as the semiconductor device660, can have different compositions, i.e., a different number and/or size of each of the floorplan tiles662,664, and666, based on the semiconductor device's PPA. In some embodiments, a semiconductor device includes more high-speed floorplan tile area, such that the semiconductor device is configured to accommodate more standard cells at higher supply voltages. In some embodiments, the semiconductor device includes more low power floorplan tile area, such that the semiconductor device is configured to accommodate more standard cells at lower supply voltages. The semiconductor device660includes six high-speed floorplan tiles662of different shapes and sizes, 5 normal tiles664of different shapes and sizes, and 7 low power floorplan tiles666of different shapes and sizes. The semiconductor device600includes more low power floorplan tile area than high-speed floorplan tile area, and more high-speed floorplan tile area than normal tile area. Thus, the semiconductor device600can accommodate more standard cells at lower supply voltages than standard cells at higher supply voltages. FIG.22is a diagram schematically illustrating a high-speed floorplan tile700that includes a PDN that includes supply voltage tracks configured to be electrically connected to other tiles, in accordance with some embodiments. The high-speed floorplan tile700includes horizontal supply voltage tracks702,704,706, and708, horizontal reference voltage tracks710,712,714, and716, vertical supply voltage tracks718,720,722, and724, and a vertical reference voltage track726. Each of the reference voltage tracks710,712,714,716, and726provides a reference voltage VSS, such as ground. The high-speed floorplan tile700is part of a semiconductor device. In some embodiments, the semiconductor device is an integrated circuit. The PDN of the high-speed floorplan tile700can be connected among or to different tiles, including different high-speed floorplan tiles, normal tiles, and low power floorplan tiles. The horizontal supply voltage tracks702,704,706, and708and the horizontal reference voltage tracks710,712,714, and716are on lower conductive layers of the semiconductor device and staggered for minimizing the utilized resources, such as row and layer resources. The vertical supply voltage tracks718,720,722, and724and the vertical reference voltage track726are on upper conductive layers of the semiconductor device and staggered for minimizing the utilized resources, such as the row and layer resources. In some embodiments, the vertical supply voltage tracks718,720,722, and724are on a common layer of the semiconductor device for connecting supply voltages from lower layers to other tiles. In some embodiments, the vertical supply voltage tracks718,720,722, and724and the vertical reference voltage track726are on a common layer of the semiconductor device for connecting power supply voltages and references from lower layers to other tiles. The high-speed floorplan tile700includes two supply voltage tracks702and708that provide supply voltage VDD1, one supply voltage track704that provides supply voltage VDD2, and one supply voltage track706that provides supply voltage VDD3. In this example, supply voltage VDD1is greater than supply voltage VDD2, and supply voltage VDD2is greater than supply voltage VDD3. Thus, the high-speed floorplan tile700includes 50% supply voltage tracks providing the highest supply voltage VDD1, 25% supply voltage tracks providing the supply voltage VDD2, and 25% supply voltage tracks providing the lowest supply voltage VDD3. With this composition of supply voltage tracks, the high-speed floorplan tile700can accommodate more standard cells at higher supply voltages. Each of the vertical supply voltage tracks718,720,722, and724is electrically connected to one of the horizontal supply voltage tracks702,704,706, and708. The vertical supply voltage track718is electrically connected to the horizontal supply voltage track702, the vertical supply voltage track720is electrically connected to the horizontal supply voltage track704, the vertical supply voltage track722is electrically connected to the horizontal supply voltage track706, and the vertical supply voltage track724is electrically connected to the horizontal supply voltage track708. Also, the vertical reference voltage track726is electrically connected to each of the horizontal reference voltage tracks710,712,714, and716. The vertical supply voltage tracks718,720,722, and724and the vertical reference voltage track726can be electrically connected among or to different tiles, including different high-speed floorplan tiles, normal tiles, and low power floorplan tiles. Standard cells are electrically connected to the supply voltage tracks702,704,706, and708to receive the supply voltages VDD1, VDD2, and VDD3and to at least one of the reference voltage tracks710,712,714, and716to receive the reference voltage VSS. FIG.23is a diagram schematically illustrating a low power floorplan tile730that includes a PDN that includes supply voltage tracks configured to be electrically connected to other tiles, in accordance with some embodiments. The low power floorplan tile730includes horizontal supply voltage tracks732,734,736, and738, horizontal reference voltage tracks740,742,744, and746, vertical supply voltage tracks748,750,752, and754, and a vertical reference voltage track756. Each of the reference voltage tracks740,742,744,746, and756provides a reference voltage VSS, such as ground. The low power floorplan tile730is part of a semiconductor device. In some embodiments, the semiconductor device is an integrated circuit. The PDN of the low power floorplan tile730can be connected among or to different tiles, including different high-speed floorplan tiles, normal tiles, and low power floorplan tiles. The horizontal supply voltage tracks732,734,736, and738and the horizontal reference voltage tracks740,742,744, and746are on lower conductive layers of the semiconductor device and staggered for minimizing the utilized resources, such as row and layer resources. The vertical supply voltage tracks748,750,752, and754and the vertical reference voltage track756are on upper conductive layers of the semiconductor device and staggered for minimizing the utilized resources, such as the row and layer resources. In some embodiments, the vertical supply voltage tracks748,750,752, and754are on a common layer of the semiconductor device for connecting supply voltages from lower layers to other tiles. In some embodiments, the vertical supply voltage tracks748,750,752, and754and the vertical reference voltage track756are on a common layer of the semiconductor device for connecting power supply voltages and references from lower layers to other tiles. The low power floorplan tile730includes two supply voltage tracks732and738that provide supply voltage VDD3, one supply voltage track734that provides supply voltage VDD2, and one supply voltage track736that provides supply voltage VDD1. In this example, supply voltage VDD1is greater than supply voltage VDD2, and supply voltage VDD2is greater than supply voltage VDD3. Thus, the low power floorplan tile730includes 50% supply voltage tracks providing the lowest supply voltage VDD3, 25% supply voltage tracks providing the supply voltage VDD2, and 25% supply voltage tracks providing the highest supply voltage VDD1. With this composition of supply voltage tracks, the low power floorplan tile730can accommodate more standard cells at lower supply voltages. Each of the vertical supply voltage tracks748,750,752, and754is electrically connected to at least one of the horizontal supply voltage tracks732,734,736, and738. The vertical supply voltage track748is electrically connected to the horizontal supply voltage track736, the vertical supply voltage track750is electrically connected to the horizontal supply voltage track734, the vertical supply voltage track752is electrically connected to the horizontal supply voltage track732, and the vertical supply voltage track754is electrically connected to the horizontal supply voltage track738. Also, the vertical reference voltage track756is electrically connected to each of the horizontal reference voltage tracks740,742,744, and746. The vertical supply voltage tracks748,750,752, and754and the vertical reference voltage track746can be electrically connected among or to different tiles, including different high-speed floorplan tiles, normal tiles, and low power floorplan tiles. In some embodiments, the vertical supply voltage tracks752and754are electrically connected. Standard cells are electrically connected to the supply voltage tracks732,734,736, and738to receive the supply voltages VDD1, VDD2, and VDD3and to at least one of the reference voltage tracks740,742,744, and746to receive the reference voltage VS S. Also, as with the high-speed floorplan tile700ofFIG.22and the low power floorplan tile730ofFIG.23, normal tiles can include vertical supply voltage tracks configured to be electrically connected to other tiles. FIGS.24and25are diagrams schematically illustrating placement of standard cells into a floorplan, which is performed during step510of the APR flow. At step510, the method includes placement of the standard cells that perform the functions of the semiconductor device into a floorplan of the semiconductor device. The standard cells are placed in cell rows of the floorplan and, eventually, electrically connected to the supply voltage tracks and supply voltages for the cell tow. Each of the cell rows in the floorplan has a supply voltage track that provides one supply voltage or set of supply voltages, such that the standard cells placed in the cell row belong to a library for the supply voltage or set of supply voltages of that cell row. During optimization, information such as timing delays, timing variations, and power consumption are taken from the library of standard cells for the supply voltage or set of supply voltages of the cell row. Also, during optimization, the APR tool can change the supply voltage or set of supply voltages of a cell row by splitting or merging the supply voltages of the cell row to optimize timing delays, timing variations, and power consumption and meet the constraints of the semiconductor device. This provides flexibility for the APR tool to optimize the design with different supply voltages, such as for reducing timing delay, timing variation, and/or power consumption of the semiconductor device. FIG.24is a diagram schematically illustrating a semiconductor device800that includes placement of a standard cell Cell1 in each of four cell rows802,804,806, and808, in accordance with some embodiments. The standard cell Cell1 that is placed in a cell row belongs to a standard cell library for the supply voltage or set of supply voltages in that cell row. The semiconductor device800includes three supply voltage tracks810,812, and814and two reference voltage tracks816and818. Also, the semiconductor device800includes four standard cells820,822,824, and826that perform the same logic function, such as an AND, OR, NOT, NAND, or NOR logic function. In some embodiments, the semiconductor device800is an integrated circuit. Each of the cell rows802,804,806, and808includes one of the supply voltage tracks810,812, and814that is configured to provide one or more supply voltages. Cell row802includes supply voltage track810that is configured to provide supply voltage VDD1. Cell rows804and806include supply voltage track812that is configured to provide supply voltage VDD2828and supply voltage VDD3830. Cell row808includes supply voltage track814that is configured to provide supply voltage VDD3. Also, each of the reference voltage tracks816and818provides a reference voltage VSS, such as ground. In some embodiments, the supply voltage VDD1is greater than the supply voltage VDD2, and the supply voltage VDD2is greater than the supply voltage VDD3. In some embodiments, the supply voltage VDD1is less than the supply voltage VDD2, and the supply voltage VDD2is less than the supply voltage VDD3. In other embodiments, the supply voltages VDD1, VDD2, and VDD3can compare to one another differently, such as the supply voltage VDD2being greater than the supply voltage VDD1, and the supply voltage VDD1being greater than the supply voltage VDD3, or the supply voltage VDD2being less than the supply voltage VDD1, and the supply voltage VDD1being less than the supply voltage VDD3. In other embodiments, each of the supply voltage tracks810,812, and814is configured to provide one or more other or different supply voltages than those depicted inFIG.24. Each of the standard cells820,822,824, and826is placed in one of the cell rows802,804,806, and808, respectively, and configured to be electrically connected to the supply voltage track810,812, or814that is included in the cell row802,804,806, or808. Also, the standard cells820,822,824, and826belong to standard cell libraries832,834,836, and838, respectively, that are for the supply voltage or set of supply voltages of the supply voltage track810,812, or814that is included in the cell row802,804,806, or808. The standard cell Cell1820is placed in cell row802and configured to be electrically connected to the supply voltage track810to receive supply voltage VDD1. The standard cell Cell1820belongs to standard cell library832that is for supply voltage VDD1. The standard cell Cell1822is placed in cell row804and configured to be electrically connected to the supply voltage track812to receive supply voltages VDD2and VDD3. The standard cell Cell1822belongs to standard cell library834that is for supply voltages VDD2and VDD3. The standard cell Cell1824is placed in cell row806and configured to be electrically connected to the supply voltage track812to receive supply voltages VDD2and VDD3. The standard cell Cell1824belongs to standard cell library836that is for supply voltages VDD2and VDD3. The standard cell Cell1826is placed in cell row808and configured to be electrically connected to the supply voltage track814to receive supply voltage VDD3. The standard cell Cell1826belongs to standard cell library838that is for supply voltage VDD3. In some embodiments, standard cell library834is the same as standard cell library836. In other embodiments, each of the standard cells820,822,824, and826is electrically connected to receive one or more other or different supply voltages than those depicted inFIG.24. FIG.25is a diagram schematically illustrating a semiconductor device850that is the result of optimizing the semiconductor device800for timing delays, timing variations, and power consumption to meet design constraints for the semiconductor device, in accordance with some embodiments. The semiconductor device850includes the four cell rows802,804,806, and808, the three supply voltage tracks810,812, and814, and the two reference voltage tracks816and818. Also, the standard cells in the semiconductor device850perform the same logic function, such as an AND, OR, NOT, NAND, or NOR logic function and, in some embodiments, the semiconductor device850is an integrated circuit. The optimization was performed by an APR tool that is part of a computer system, such as the computer system100ofFIG.3. During optimization, the APR tool changed each of the supply voltage tracks810and812and placed different standard cells852,854, and856in the cell rows802,804, and806, respectively, to correspond with the changes in the supply voltage tracks810and812. The APR tool split supply voltage track810to provide supply voltages VDD1858and VDD2860. Also, the APR tool merged or changed supply voltage track812to provide only supply voltage VDD2862. The supply voltage track814was not changed. In the semiconductor device850, standard cell Cell1852is placed in cell row802and configured to be electrically connected to the supply voltage track810to receive supply voltages VDD1858and VDD2860. The standard cell Cell1852belongs to standard cell library864that is for supply voltages VDD1and VDD2. The standard cell Cell1854is placed in cell row804and configured to be electrically connected to the supply voltage track812to receive supply voltage VDD2862. The standard cell Cell1854belongs to standard cell library866that is for supply voltage VDD2. The standard cell Cell1856is placed in cell row806and configured to be electrically connected to the supply voltage track812to receive supply voltage VDD2862. The standard cell Cell1856belongs to standard cell library868that is for supply voltage VDD2862. The standard cell Cell1826remains placed in cell row808and configured to be electrically connected to the supply voltage track814to receive supply voltage VDD3, and the standard cell Cell1826belongs to standard cell library838that is for supply voltage VDD3. In some embodiments, standard cell library866is the same as standard cell library868. Thus, during optimization, information such as timing delays, timing variations, and power consumption are taken from the standard cell libraries and the APR tool changes supply voltages for the cell rows to meet the constraints of the semiconductor device. This provides flexibility for the APR tool to optimize the design with different supply voltages and standard cells, such as for reducing timing delay, timing variation, and/or power consumption of the semiconductor device. FIG.26is a diagram schematically illustrating a method of manufacturing a semiconductor device, in accordance with some embodiments. The manufacturing of the semiconductor device includes design, layout, and fabrication of the semiconductor device such as by a computer system like the computer system100ofFIG.3and the semiconductor device manufacturing system122ofFIG.4. The semiconductor device can be any of the semiconductor devices described in this disclosure, or another semiconductor device. In some embodiments, the semiconductor device is one of: the semiconductor device30ofFIG.1; the semiconductor device60ofFIG.2; the semiconductor device200ofFIG.5; the semiconductor device230ofFIG.6; the semiconductor device260ofFIG.7; and the semiconductor device400ofFIG.11. In some embodiments, the semiconductor device is an integrated circuit. At step900, the method includes generating multiple versions of standard cell libraries, wherein each version of the standard cell libraries is for a different supply voltage or set of supply voltages. In some embodiments, generating multiple versions of standard cell libraries includes generating versions of a standard cell, where each version of the standard cell has an index that identifies one of the multiple versions of standard cell libraries to which it belongs. In some embodiments, generating multiple versions of standard cell libraries includes generating versions of a standard cell that perform the same function at different voltages and with different layouts and/or structures. At step902, the method includes generating a supply voltage floorplan that includes a plurality of tiles, wherein each of the plurality of tiles includes multiple supply voltage tracks. In some embodiments, generating a supply voltage floorplan that includes a plurality of tiles includes generating tiles that have a different number of at least one supply voltage track. In some embodiments, generating a supply voltage floorplan that includes a plurality of tiles includes generating at least one higher speed tile and at least one lower power tile in the plurality of tiles. At step904, the method includes placing standard cells from the multiple versions of standard cell libraries on the tiles of the plurality of tiles. In some embodiments, the method includes placing standard cells that perform the functions of the semiconductor device into the floorplan of the semiconductor device. The standard cells are placed in cell rows of the floorplan and electrically connected to the supply voltage tracks and supply voltages. During optimization of the timing delays, timing variations, and power consumption, the standard cells are selected from different versions of the standard cell libraries to meet the constraints of the semiconductor device. At step906, the method includes routing conductive nets between the standard cells of the integrated circuit and, at step908, the method includes providing a routed integrated circuit. Disclosed embodiments thus provide semiconductor devices that include multiple supply voltage tracks that provide multiple supply voltages, where each of the multiple supply voltage tracks is configured to provide one or more supply voltages. The disclosed embodiments further provide standard cells configured to be electrically connected to the supply voltage tracks to receive the one or more supply voltages and to a reference track to receive a reference voltage, such as ground. Disclosed embodiments also include multiple standard cell libraries, where each of the multiple standard cell libraries is for a different supply voltage or set of supply voltages. The standard cells in one of the multiple standard cell libraries are identified for use with the supply voltage or set of supply voltages corresponding to the standard cell library. Also, standard cells that perform the same function that are in different standard cell libraries are labeled for use with the supply voltage or set of supply voltages that correspond to their standard cell library. Disclosed embodiments further include devices that include a plurality of tiles, where each of the tiles includes multiple different supply voltage tracks. In some embodiments, a first tile includes a first combination of supply voltage tracks, and a second tile includes a second combination of supply voltage tracks that is different from the first combination of supply voltage tracks. In some embodiments, a device includes a higher speed tile that includes two or more first supply voltage tracks that each provide a first voltage and at least one second supply voltage track that provides a second voltage that is less than the first voltage, wherein the higher speed tile includes more first supply voltage tracks than second supply voltage tracks. In some embodiments, a device includes a lower power tile that includes at least one first supply voltage track that provides a first voltage and two or more second supply voltage tracks that provide a second voltage that is less than the first voltage, wherein the lower power tile includes fewer first supply voltage tracks than second supply voltage tracks. In some embodiments, semiconductor devices include different compositions, i.e., different relative numbers, of high-speed tiles and low power tiles. Disclosed embodiments further include methods of manufacturing a semiconductor device, such as an integrated circuit. In some embodiments, the method includes generating multiple versions of standard cell libraries that are each for a different supply voltage or set of supply voltages; generating a supply voltage floorplan that includes a plurality of tiles that each include multiple supply voltage tracks; placing the standard cells from the multiple versions of standard cell libraries on the tiles; routing conductive nets between the standard cells; and providing a routed semiconductor device. Advantages of the disclosed embodiments include providing multiple different supply voltages to the standard cells for optimizing timing delays, timing variations, and power consumption constraints, reducing the impact of timing variations with minimal APR design flow changes, allowing increased usage of higher Vt cells for saving power without layout changes, and reducing power consumption in ultra-low voltage semiconductor devices. In accordance with some embodiments, a device includes a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track. In accordance with further embodiments, a device includes a plurality of tiles that include a speed tile and a power tile. The speed tile includes two or more first supply voltage tracks that each provide a first voltage and at least one second supply voltage track that provides a second voltage that is less than the first voltage, where the speed tile includes more first supply voltage tracks than second supply voltage tracks. The power tile includes at least one first supply voltage track that provides the first voltage and two or more second supply voltage tracks that provide the second voltage, where the power tile includes fewer first supply voltage tracks than second supply voltage tracks. In accordance with still further disclosed aspects, a method of manufacturing an integrated circuit includes: generating multiple versions of standard cell libraries, where each version of the standard cell libraries is for a different supply voltage; generating a supply voltage floorplan that includes a plurality of tiles, where each of the plurality of tiles includes multiple supply voltage tracks; placing standard cells from the multiple versions of standard cell libraries on the tiles of the plurality of tiles; routing conductive nets between the standard cells of the integrated circuit; and providing a routed result of the integrated circuit. This disclosure outlines various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 111,739 |
11942942 | DETAILED DESCRIPTION The present invention relates to an improvement in level-shifter circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. FIG.3is a block diagram of an edge-triggered level shifter with LDMOS clamp transistors. An input IN in the low-voltage domain is level shifted to generate output OUT in the high voltage domain. For example, the low-voltage domain may have a high logic level of 3 volts and ground for the low logic level, while the high-voltage domain may have 15 volts as the logical high level and 12 volts as the logical low level. Oneshots110are edge-triggered pulse generators that generate a pulse when IN changes state. These pulses are applied to gates of differential transistors106to shift current among two circuit legs. Current limiter108limits the tail current through differential transistors106. Differential transistors106shift current among the two circuit legs to generate a voltage difference among two nodes that are clamped by LDMOS clamp104. LDMOS clamp104uses n-channel transistors that have a lateral diffusion to provide a higher drain-to-source breakdown voltage, so LDMOS clamp104can support a larger voltage difference across its transistor channels than can ordinary n-channel transistors used in differential transistors106. Current-mirror amplifier102uses standard p-channel transistors that have low drain-to-source breakdown voltages. However, LDMOS clamp104reduces the voltages applied to these p-channel transistors in current-mirror amplifier102. Thus the only specialized high-voltage transistors used by the level shifter are the LDMOS n-channel transistors in LDMOS clamp104. Standard p-channel transistors are used in current-mirror amplifier102, while standard n-channel transistors are used in differential transistors106. Oneshots110and output latch116may use standard p-channel and standard n-channel transistors. Output latch116is a bistable that latches the output generated from current-mirror amplifier102after oneshots110trigger the pulse. Output latch116holds the output state after the pulse generated by oneshots110ends. Bias generator114generates a bias for the two circuit-leg nodes between differential transistors106and LDMOS clamp104. Differential transistors106generate a large current than this bias when triggered by the pulse from oneshots110, but after the pulse ends, differential transistors106turn off to save power and bias generator114drives a smaller transistor to hold the voltage difference across the two circuit-leg nodes. Power-on reset generator112allows the level shifter circuit to power up to a stable state. The bias current from bias generator114may require time during power initialization to become stable, so power-on reset generator112initializes an internal node while the bias generator is ramping up current. Power-on reset generator112and bias generator114can used standard low-voltage n-channel transistors. High-voltage transistors are not needed. FIG.4is a schematic of an edge-triggered level shifter with LDMOS clamp transistors. When IN transitions from low to high, oneshot62generates a high-going pulse of short duration that turns on transient differential transistor72to allow current to flow through resistor46to ground from node N6. IN is applied to the gate of holding differential transistor52which allows current to flow from node N6through bias transistor86to ground to keep node N6low after the pulse ends and transient differential transistor72turns off. Holding differential transistor50and transient differential transistor70remain off when IN is high, allowing node N5to float high through LDMOS transistor40. When IN transitions high to low, inverter68activates oneshot64to generate a high pulse of short duration to transient differential transistor70, allowing node N5to be pulled lower by current that is limited by resistor44. Inverter66drives a high to the gate of holding differential transistor50to hold node N5low after the pulse ends. Holding differential transistors50,52can be smaller than transient differential transistors70,72so that a larger current is provided initially by transient differential transistor70or72, and then a smaller holding current is provided by holding differential transistor50or52. LDMOS transistors40,42act as a clamp to prevent the upper high-voltage supply, boosted voltage VBST, from applying a high voltage onto the low-voltage n-channel transistors such as transient differential transistors70,72, holding differential transistors50,52, and bias transistor86. LDMOS transistors40,42have a higher breakdown voltage that is provided by the lateral diffusion under the gate that has a lower doping concentration than the N+ source. The gates of LDMOS transistors40,42are driven by the low-voltage upper supply VDD. When IN goes high, transient differential transistor72turns on driving node N6lower than node N5. LDMOS transistor42pulls more current than LDMOS transistor40due to its lower source voltage N6, so node N2on the drain of LDMOS transistor42is pulled lower than node N1on the drain of LDMOS transistor40, and this lower N2voltage on the gate and drain of p-channel sensing transistor30increases its current flow to compensate. The lower N2voltage is also applied to the gates of p-channel mirror transistors32,34, which draw more current, pulling their drains OUT and node N4, respectively, higher. The higher current through p-channel mirror transistor34causes node N4to go higher, which is the gate and drain of n-channel mirror transistor38. This higher N4voltage is applied to the gate of n-channel output transistor28, increasing its current drive and pulling node OB lower. The lower OB and the higher OUT are applied to opposite sides of output latch60, which is bistable and pulls OUT closer to the upper high supply, VBST and pulls OB closer to the lower high supply SW. When IN goes low and node N5is pulled lower by transient differential transistor70, LDMOS transistor40drives node N1lower than node N2. This lower N1voltage on the gate and drain of p-channel sensing transistor20increases its current flow to compensate. The lower N1voltage is also applied to the gates of p-channel mirror transistors22,24, which draw more current, pulling their drains, node N3and OB, respectively, higher. The higher current through p-channel mirror transistor22causes node N3to go higher, which is the gate and drain of n-channel mirror transistor26. This higher N3voltage is applied to the gate of n-channel output transistor36, increasing its current drive and pulling output node OUT lower. The lower OUT and the higher OB are applied to opposite sides of output latch60, which is bistable and pulls OB closer to the upper high supply, VBST and pulls OUT closer to the lower high supply SW. Rather than be a constant voltage, SW can have a varying voltage that still acts as the lower high-voltage supply terminal. For example, VBST can be a constant 15 volts, while SW switches above 10 volts so that VBST-SW is less than 5 volts to protect low-voltage transistors. A bias current is set by the gate voltage to bias transistor86. This gate voltage on node N9is generated by the gate and drain of n-channel transistor82. When enable EN is high and applied to the gate of n-channel transistor80, bias current IBAS flows through n-channel transistors80,82, generating a bias voltage on node N9. When EN is low, inverter88drives a high to the gate of disable transistor84to drive node N9to ground, which turns off bias transistor86. During initialization, IBIAS may not yet be stable. Power-On-Reset POR is high during power initialization, turning on n-channel transistor56, which holds node N8low through resistor54. Once POR goes low, transistor56turns off and bias transistor86pulls a steady bias current from node N8. FIG.5is an alternative of the transient level shifter. In this alternative, oneshot62drives the gate of LDMOS transistor42directly. The gate of LDMOS transistor40is driven by oneshot64which generates a pulse when IN goes low and inverter68drives a high to the input of oneshot64. The sources of LDMOS transistors40,42are grounded. Advantages of this alternative include a simpler circuit to implement and no DC power consumption. However, the transition current depends on the ON-resistance of LDMOS transistors40,42which are sensitive to process variation. Since LDMOS transistors40,42are turned off after the one-shot pulse period, only output latch60holds the data. Output latch60can be noise sensitive without an additional biasing circuit to hold the data. Without POR, OUT is not well-defined before IN settles during power up. FIG.6is another alternative of the transient level shifter. In this alternative the current mirror is simplified. P-channel sensing transistor20has its gate and drain connected together at node N1which is mirrored to the gate of p-channel mirror transistor24which drives node OB at its drain. P-channel sensing transistor30has its gate and drain connected together at node N2which is mirrored to the gate of p-channel mirror transistor34which drives node OUT at its drain. Output latch60helps to more rapidly drive a small voltage difference on OUT, OB to the upper rails VBST and SW. Node N1is the drain of LDMOS transistor40, while the source of LDMOS transistor40is node N5, which is driven to ground by transient differential transistor70when oneshot64is triggered by IN going low through inverter68. The current limiting resistors44,46have been eliminated as well as holding differential transistors50,52, and the bias and reset circuits. In this alternative output latch60will hold the state after the pulses from oneshots62,64end. The circuit may be less stable during power on reset and a longer pulse duration may be required. Advantages of this alternative include a simpler circuit to implement and no DC power consumption. However, the transition current depends on the ON-resistance of LDMOS transistors40,42and differential transistors70,72which are sensitive to process variation. Since differential transistors70,72are turned off after the one-shot pulse period, only output latch60holds the data. Output latch60can be noise sensitive without an additional biasing circuit to hold the data. Without POR, OUT is not well-defined before IN settles during power up. Also without sink current paths of n-channel mirror transistor26, n-channel output transistors28,36, and n-channel mirror transistor38, the transition speed of output latch60may be slower. FIG.7is another alternative of the transient level shifter. In this alternative oneshots62,64turn on current sink71for the short period of time of the generated pulse. When IN goes high, oneshot62is activated to turn on current sink71and IN is applied to the gate of transient differential transistor72to turn it on to connect LDMOS transistor42to current sink71. When IN goes low, inverter68triggers oneshot64to turn on current sink71. Inverter68drives high the gate of transient differential transistor70to turn it on to connect LDMOS transistor40to current sink71. This alternative circuit has better control of the transition current and no DC power consumption. Since differential transistors70,72are turned off after the one-shot pulse period, only output latch60holds the data. Output latch60can be noise sensitive without an additional biasing circuit to hold the data. Without POR, OUT is not well-defined before IN settles during power up. FIG.8is still another alternative of the transient level shifter. In this alternative p-channel sensing transistor20has its gate and drain connected together at node N1which is applied to the non-inverting (+) input of comparator232, while the non-inverting (−) input of comparator232is node N2from the gate and drain of p-channel sensing transistor30. The output of comparator232is output OUT, which is applied to output latch60to rapidly settle the output. Inverter234inverts comparator232output OUT to drive OB into output latch60 Node N1is the drain of LDMOS transistor40, while the source of LDMOS transistor40is node N5, which is driven to ground by transient differential transistor70when oneshot64is triggered by IN going low through inverter68. The current limiting resistors44,46have been eliminated as well as holding differential transistors50,52, and the bias and reset circuits. In this alternative output latch60will hold the state after the pulses from oneshots62,64end. The circuit may be less stable during power on reset and a longer pulse duration may be required. Advantages of this alternative include a simpler circuit to implement and no DC power consumption. However, the transition current depends on the ON-resistance of LDMOS transistors40,42and differential transistors70,72which are sensitive to process variation. Since differential transistors70,72are turned off after the one-shot pulse period, only output latch60holds the data. Output latch60can be noise sensitive without an additional biasing circuit to hold the data. Without POR, OUT is not well-defined before IN settles during power up. FIG.9is an alternative of the transient level shifter with bipolar compensating transistors. In this alternative PNP transistor90has its emitter connected to the lower terminal of current limiting resistor44while PNP transistor92has its emitter connected to the lower terminal of current limiting resistor46. The bases of PNP transistors90,92are connected together and to ground. PNP transistors90,92allow for temperature, voltage, and process compensation that may be superior to using limiting resistors44,46(FIG.3). Compensation for different frequency bands of operation may also be provided. Temperature compensation is provided by the positive temperature coefficient of a polysilicon resistor. The negative temperature coefficient of the base-emitter junction can cancel out the temperature drift of the polysilicon resistor. However the die area may increase due to addition of the Bipolar Junction Transistors (BJT) and reduction of the driving strength of LDMOS transistors40,42and differential transistors70,72. FIG.10shows a level-shifter within a Buck converter. Level shifter702can be any of the level shifters ofFIGS.3-9or other variants. The switch-control input IN_L drives the gate of pull-down driver transistor706through buffer704, which is powered by the low-voltage power supply VDD and connects to ground. Switch-control input IN_H is shifted by level-shifter702to drive the input of buffer714which drives the gate of pull-up driver transistor716. IN_H and IN_L can be non-overlapping to prevent power spikes and their timing adjusted to obtain a desired output POUT, such as when PIN is an AC signal. Level-shifter702and buffer714are powered by the boosted power-supply voltage VBST. Level-shifter702and buffer714have their lower supply terminals connected to node SW, which is the node between pull-up driver transistor716and pull-down driver transistor706, which can be filtered by inductor720and capacitor722to generate the switched-power output POUT from the Buck converter. The Buck converter input PIN is applied to the drain of pull-up driver transistor716while the source of pull-down driver transistor706is ground. Boost capacitor730can be connected between node SW and VBST. The internal node of the Buck converter between the driver transistors, node SW, can be used as the lower supply terminal SW to level-shifter702and buffer714. This node SW acts as a floating ground to level-shifter702and buffer714. Pull-down driver transistor706and pull-up driver transistor716can be large n-channel transistors. For a buck converter, VBST and SW can both have varying voltages such that VBST-SW<5V by using a bootstrap circuit. Although output OUT from current-mirror amplifier102(FIG.3) in level-shifter702has a high voltage, node SW acts as a floating ground that rises above ground when OUT goes high to turn on pull-up driver transistor716, which drives SW higher. Thus a lower voltage is applied across transistors in current-mirror amplifier102that if SW were replaced with a fixed ground. This allows for standard p-channel and n-channel transistors to be used in current-mirror amplifier102despite the high OUT voltage. Using standard low-voltage n-channel and p-channel transistors and only having two high-voltage transistors, LDMOS transistors40,42, can reduce cost and complexity and improve circuit speed. Oneshots provide for an edge-triggered or transient response that can lower power consumption. The bias circuit prevents noise disturbance once the pulse from the oneshot ends. Tail resistors or transistors provide current limitation for safety and to prevent circuit damage. The current mirror amplifier prevent undershoot on falling edges of the output signals, improves circuit speed, and limit voltage swings. Alternate Embodiments Several other embodiments are contemplated by the inventors. For example many combinations and variations of the level-shifter circuit alternatives inFIGS.4-9may be substituted. Some embodiments may not use power-on reset generator112or bias generator114. Other biasing or holding mechanisms may be used in place of bias transistor86and holding differential transistors50,52, such as leaker resistors. Transistors may be used as resistors to limit current in some embodiments. Capacitors may be transistors with source and drains connected together as one terminal of the capacitor, and the gate as the other terminal. The level shifter provides a good propagation delay and reduced standby current due to its transient triggering using the oneshots. A oneshot may be constructed from a logic gate such as a NAND, NOR, AND, OR, XOR gate that has one input delayed by a string of inverters while the other gate input is direct with no delay. The delay through the string of inverters determines the pulse width. Other circuits for oneshots may be substituted. While a Buck converter has been shown, other kinds of circuits for high-voltage applications could be substituted, such as source-followers, common-source amplifiers, class-B amplifiers, class AB amplifiers, etc. The technique can apply to all high-voltage circuits (analog or logic) that use LDMOS and can't withstand full high-voltage swing signals. LDMOS transistors40,42can be n-channel transistors with a higher source-drain breakdown voltage than other n-channel transistors, such as transient differential transistors70,72, holding differential transistors50,52, bias transistor86, and other n-channel transistors in the Power-on-reset and bias circuits. LDMOS transistors40,42have a higher breakdown voltage due to the added lateral diffusion that creates N-drift region304between N+ drain diffusion316and conduction channel302(FIG.2). This added lateral diffusion adds one or more processing steps and is not used for standard n-channel transistors that have the lower breakdown voltage, making these standard n-channel transistors low-voltage transistors while LDMOS transistors40,42can be considered high-voltage transistors. The p-channel transistors in conduction channel current-mirror amplifier102can be standard p-channel transistors that do not have an added lateral diffusion to create a P-drift region under the gates. Thus these standard p-channel transistors can be considered to be low-voltage transistors. The n-channel transistors in current-mirror amplifier102also can be standard n-channel transistors without N-drift region304and with a small drain-source breakdown voltage. Thus current-mirror amplifier102uses low-voltage p-channel and n-channel transistors. Although output OUT from current-mirror amplifier102has a high voltage, node SW acts as a floating ground that rises above ground when OUT goes high to turn on pull-up driver transistor716, which drives SW higher. Thus a lower voltage is applied across transistors in current-mirror amplifier102that if SW were replaced with a fixed ground. Additional process steps may be added, such as to provide a thicker gate oxide for LDMOS transistors40,42, or to other transistors, for better gate-to-source breakdown voltages. Long-term reliability may be enhanced by the process steps. Various physical layouts may be used to enhance resistance to high voltage, such as using doughnut transistor layouts, increased spacings, longer gate lengths, etc. Gates may be polysilicon or other materials. Some process enhancements may be added to all standard transistors, such as adjusting drain doping profiles to reduce the sharpness of the source-to-well junctions. These process enhancements may be needed for the standard transistors just to have sufficient breakdown voltages for the low-voltage VDD supply, especially for smaller device sizes, but these enhancements are insufficient for higher voltages such as VBST. The boosted power supply VBST could be an externally-generated voltage, or could be generated by a voltage booster circuit, a charge pump, or by other circuits. Different values of VBST, VDD, and SW could be substituted. Using a boosted voltage from the level shifter allows for a smaller pull-up transistor to be used in the Buck converter. While VDD has been shown as the bias voltage to the gates of LDMOS transistors40,42, a different fixed voltage may be substituted, or a variable voltage used. More complex buffers, level shifters, or other components could be substituted or added. Inversions could be added at various locations. Hysteresis of other delays and output wave shaping could be added. Rather than use CMOS inverters, other kinds of buffer circuits, selectors, or muxes may be used. Different transistor, capacitor, resistor, and other device sizes can be used, and various layout arrangements can be used, such as multi-leg, ring, doughnut or irregular-shape transistors. Currents can be positive or negative currents and flow in either direction. Many second and third order circuit effects may be present and may be significant, especially for smaller device sizes. A circuit simulation may be used to account for these secondary factors during design. Devices may be implemented using n-channel, p-channel, or bipolar transistors, or junctions within these transistors. The gate lengths and spacings can be increased to provide better protection from damage. Many variations of IC semiconductor manufacturing processes are possible. Various materials may be used. Additional process steps may be added, such as for additional metal layers or for other transistor types or modification of standard complementary metal-oxide-semiconductor (CMOS) transistors when the transistors are integrated onto a larger device. While complementary metal-oxide-semiconductor (CMOS) transistors have been described, other kinds of transistors could be substituted for some embodiments, such as n-channel only, p-channel only when the output swing can be limited, or various alternate transistor technologies such as Bipolar or BiCMOS. The CMOS process may be a Fin Field-Effect Transistor (FinFET) process. Terms such as up, down, above, under, horizontal, vertical, inside, outside, are relative and depend on the viewpoint and are not meant to limit the invention to a particular perspective. Devices may be rotated so that vertical is horizontal and horizontal is vertical, so these terms are viewer dependent. The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant. Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result. Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. | 26,239 |
11942943 | DETAILED DESCRIPTION OF THIS DISCLOSURE The present disclosure is directed to duty cycle adjustment. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure. Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “power supply,” “ground,” “CMOS (complementary metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “inverter,” “multiplexer,” and “NAND gate.” Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail here. Those of ordinary skill in the art can recognize a resistor symbol and can recognize a MOS (metal-oxide semiconductor) transistor symbol, for both PMOS transistor and NMOS transistor. Those of ordinary skill in the art can read schematics of a circuit comprising resistors, NMOS transistors, and PMOS transistors, and do not need a verbose description about how one transistor or resistor connects with another in the schematics. This present disclosure is disclosed in terms of an engineering sense. For instance, regarding two variables X and Y, when it is said that “X is equal to Y,” it means that “X is approximately equal to Y,” i.e. “a difference between X and Y is smaller than a specified engineering tolerance.” When it is said that “X is zero,” it means that “X is approximately zero,” i.e. “X is smaller than a specified engineering tolerance.” When it is said that “X is substantially smaller than Y,” it means that “X is negligible with respect to Y,” i.e. “a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.” Throughout this disclosure, “VDD” denotes a power supply node, and “VSS” denotes a ground node. Note that a ground node is a node at which a voltage level is substantially zero, and a power supply node is a node at which a voltage level is substantially stationary and higher than zero. In this present disclosure, a signal is a voltage of a variable level that can vary with time. A (voltage) level of a signal at a moment represents a state of the signal at that moment. A logical signal is a signal of two states: a low state and a high state. The low state is also referred to as a “0” state, while the high stage is also referred to as a “1” state. Regarding a logical signal Q, “Q is high” or “Q is low,” means “Q is in the high state” or “Q is in the low state.” Likewise, “Q is 1” or “Q is 0,” means “Q is in the 1 state” or “Q is in the 0 state.” When a logical signal toggles from low to high, it undergoes a low-to-high transition. When a logical signal toggles from high to low, it undergoes a high-to-low transition. A first logical signal is said to be a logical inversion of a second logical signal, if the first logical signal and the second logical signal are always in opposite states. That is, when the first logical signal is 0 (or low), the second logical signal is 1 (or high); when the first logical signal is 1 (or high), the second logical signal is 0 (high). A clock is a logical signal that cyclically toggles back and forth between a low state and a high state. A duty cycle of the clock is a percentage of time that the clock stays in the high state. In this disclosure, “duty cycle” may sometimes be simply referred to as “duty” for short. If a first clock is a logical inversion of a second clock, a sum of a duty cycle of the first clock and a duty cycle of the second clock will be equal to 100%. If the duty cycle of the first clock is above (below) 50%, the duty cycle of the second clock must be below (above) 50%; an enlargement of the duty cycle of the first clock is accompanied by a reduction of the duty cycle of the second clock, and vice versa. A rising edge refers to an event where the clock toggles from the low state to the high stage. A falling edge refers to an event that the clock toggles from the high state to the low state. A circuit is a collection of a transistor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function. An inverter is a circuit configured to receive a first logical signal and output a second logical signal that is a logical inversion of the first logical signal. An inverter comprises a pull-up circuit that usually comprises a PMOS transistor and a pull-down circuit that usually comprises a NMOS transistor. A high-to-low transition of the first logical signal activates the pull-up circuit to pull up the second logical signal to a voltage level of a power supply node, resulting in a low-to-high transition of the second logical signal. A low-to-high transition of the first logical signal activates the pull-down circuit to pull down the second logical signal to a voltage level of a ground node, resulting in a high-to-low transition of the second logical signal. A resistance of the pull-up circuit is referred to as a pull-up resistance. A resistance of the pull-down circuit is referred to as a pull-down resistance. A time that the second logical signal takes to complete a low-to-high transition depends on the pull-up resistance, while a time that the second logical signal takes to complete a high-to-low transition depends on the pull-down resistance. Consider a case where the first logical signal is a first clock and the second logical signal is a second clock. When the pull-up resistance is larger (smaller) than the pull-down resistance, it is said that a pull-up is weaker (stronger) than a pull-down, an incidentally it has an effect of reducing (enlarging) a duty cycle of the second clock. Since the second clock is an inversion of the first clock, the effect of reducing (enlarging) the duty cycle of the second clock is functionally equivalent to enlarging (reducing) the duty cycle of the first clock. A multiplexer receives a first input signal and a second input signal and outputs an output signal in accordance with a control signal, which is a logical signal; the output signal is equal to the first input signal if the control signal is 0, and equal to the second input signal if the control signal is 1. When the control signal is 0, the second input signal is irrelevant; when the control signal is 1, the first input signal is irrelevant. A NAND gate receives a first input signal and a second input signal and outputs an output signal, wherein the first input signal, the second input signal, and the output signal are all logical signals. The output signal is 0 if both the first input signal and the second input signal are 1, otherwise, the output signal is 1. If one of the first input signal and the second input signal is always 1 for a long duration of time of interest, the NAND gate effectively becomes an inverter that inverts the other input signal into the output signal. If one of the first input signal and the second input signal is always 0 for a very long duration of time of interest, then the output signal is always 1 (or is 1 for a long duration of time of interest) and does not respond to a change of the other input signal, which becomes irrelevant. A schematic diagram of a duty-cycle adjustment circuit200in accordance with an embodiment of the present disclosure is depicted inFIG.2. Duty-cycle adjustment circuit200comprises: a conditional inversion circuit210configured to receive an input clock C0and output a conditionally inverted clock Cxin accordance with an inversion enable signal IEN; and a one-directional duty adjustment circuit230configured to receive the conditionally inverted clock Cxand output an output clock Coutin accordance with a N-bit control code A[N−1:0], where Nis an integer greater than 1. In a first embodiment, the one-directional duty adjustment circuit230is a duty enlarging circuit; in this case, a duty cycle of Coutis always larger than a duty cycle of Cxregardless of a value of A[N−1:0]. In a second embodiment, the one-directional duty adjustment circuit230is a duty reducing circuit; in this case, the duty cycle of Coutis always smaller than the duty cycle of Cxregardless of a value of A[N−1:0]. In an embodiment, the duty-cycle adjustment circuit200further comprises an encoder220configured to encode an integer D into A[N−1:0], wherein D represents an amount of duty cycle adjustment and is not smaller than 0 but not greater than N. By way of example but not limitation, N is 4 and encoder220is a thermometer code encoder that encodes D into A[3:0] in accordance with the table below: DA[0]A[1]A[2]A[3]0000011000211003111041111 Conditional inversion circuit210comprises an inverter211configured to receive C0and output and inverted clock C1, and a multiplexer212configured to select one of C0and C1to be Cxin accordance with IEN. When IENis 0, C0is selected; when IENis 1, C1is selected. C1is a logical inversion of C0, therefore a sum of a duty cycle of C0and a duty cycle of C1is 100%. If the duty cycle of C0is above (below) 50%, the duty cycle of C1must be below (above) 50%; an enlargement of the duty cycle of C0is functionally equivalent to a reduction of the duty cycle of C1, and vice versa. When IENis 0 (1), C0(C1) is selected as Cx, enlarging the duty cycle of Cxis functionally equivalent to enlarging the duty cycle of C0(C1) and reducing the duty cycle of C1(C0). In the first embodiment where the one-directional duty adjustment circuit230is a duty enlarging circuit, the duty cycle of Coutwill always be greater than the duty cycle of Cxand thus greater (smaller) than the duty cycle C0if IENis 0 (1). In the second embodiment where the duty adjustment circuit is a duty reducing circuit, the duty cycle of Coutwill always be smaller than the duty cycle of Cxand thus greater (smaller) than the duty cycle of C0if IENis 1 (0). Therefore, in both the first embodiment and the second embodiment, the duty cycle of Coutcan be made either larger or smaller than the duty cycle of C0, albert using a one-directional duty adjustment circuit230that can adjust duty cycle only in one direction, be it larger or smaller. A one-directional duty adjustment circuit just needs to adjust the duty in one direction, enlarging or reducing, can eliminate the overhead in incorporating the circuitry needed to adjust the duty in the opposite direction, and thus can have a superior design efficiency and figure of merit. In case an adjustment in the opposite direction is needed, it can be accomplished by enabling the clock inversion function of the conditional inversion circuit210, i.e., setting IENto 1. The one-directional duty adjustment circuit230is based on instantiating an uneven clock multiplexer (UCM)300that, as shown inFIG.3A, receives a first input clock from a first input pin “I1” and a second input clock from a second input pin “I2” and outputs a first output clock via a first output pin “O1” and a second output clock via a second output pin “O2” in accordance with a control signal provided at a control pin “C”; when the control signal is 0 and incidentally the second input clock is irrelevant (and will be explained later), as shown inFIG.3B, the first output clock is irrelevant (and will be explained later), and the first input clock propagates into the second output clock with a change of duty cycle of δ1; and when the control signal is 1, as shown inFIG.3C, the first input clock propagates into the first output clock with a change of duty cycle of δ2, and the second input clock propagates into the second output clock with a change of duty cycle of δ3. The uneven clock multiplexer300is said to be uneven, because for the first output clock and/or the second output clock, a pull-up and a pull-down are of different strengths, resulting in a change of duty cycle of the first output clock and/or the second output clock. A schematic of a one-directional duty adjustment circuit400that can be used to embody the one-directional duty adjustment circuit230ofFIG.2is shown inFIG.4. One-directional duty adjustment circuit400comprises: an uneven clock multiplexer (UCM) chain comprising four UCMs410,411,412, and413, that are cascaded; and an uneven clock buffer420. UCM410(411,412,413) receives Cx(X0, X1, X2) and Y0(Y1, Y2, Y3) via its “I1” pin and “I2” pin, respectively, outputs X0(X1, X2, X3) and Cout(Y0, Y1, Y2) via its “O1” pin and “O2” pin, respectively, in accordance with a control of A[0] (A[1], A[2], A[3]) provided at its “C” pin. When A[0] (A[1], A[2], A[3]) is 0, Cx(X0, X1, X2) propagates into Cout(Y0, Y1, Y2) with a duty cycle change of δ1,0(δ1,1, δ1,2, δ1,3). When A[0] (A[1], A[2], A[3]) is 1, Cx(X0, X1, X2) propagates into X0(X1, X2, X3) with a duty cycle change of δ2,0(δ2,1, δ2,2, δ2,3) while Y0(Y1, Y2, Y3) propagates into Cout(Y0, Y1, Y2) with a duty cycle change of δ3,0(δ3,1, δ3,2, δ3,3). The uneven clock buffer420receives X3and output Y3so that X3propagates into Y3with a duty cycle change of δ4. When D=0 and A[3:0]=0000, Cxpropagates into Coutthrough UCM410with a duty cycle change of δ1,0. In this case, X0and Y0are irrelevant (because they do not react to a toggle of Cxand do not affect Cout), and UCM411, UCM412, UCM413, and the uneven clock buffer420are de facto deactivated. When D=1 and A [3:0]=0001, Cxpropagates into Coutthrough UCM410and UCM411with a duty cycle change of δ2,0+δ1,1+δ3,0. In this case, X1and Y1are irrelevant (because they do not react to a toggle of Cxand do not affect Cout), and UCM412, UCM413, and the uneven clock buffer420are de facto deactivated. When D=2 and A [3:0]=0011, Cxpropagates into Coutthrough UCM410, UCM411, and UCM412with a duty cycle change of δ2,0+δ2,1+δ1,2+δ3,1+δ3,0. In this case, X2and Y2are irrelevant (because they do not react to a toggle of Cxand do not affect Cout), and UCM413and the uneven clock buffer420are de facto deactivated. When D=3 and A[3:0]=0111, Cxpropagates into Coutthrough UCM410, UCM411, UCM412, and UCM413with a duty cycle change of δ2,0+δ2,1+δ2,2+δ1,3+δ3,2+δ3,1+δ3,0. In this case, X3and Y3are irrelevant (because they do not react to a toggle of Cxand do not affect Cout), and the uneven clock buffer420is de facto deactivated. When D=4 and A [3:0]=1111, Cxpropagates into Coutthrough UCM410, UCM411, UCM412, UCM413, and the uneven clock buffer420with a duty cycle change of δ2,0+δ2,1+δ2,2+δ2,3+δ4+δ3,3+δ3,2+δ3,1+δ3,0. As the value of integer D increments by 1, an additional UCM or the uneven clock buffer420is activated, causing the output clock Coutto have an additional change in duty cycle. A schematic diagram of an UCM500that can be used to embody UCM410,411,412, and413ofFIG.4is shown inFIG.5. The UCM500comprises an inverter511and three NAND gates521,522, and523. For brevity, hereafter the first input clock at the first input pin “I1” is simply referred to as I1, the second input clock at the second input pin “I2” is simply referred to as12, the first output clock at the first output pin “O1” is simply referred to as O1, the second output clock at the second output pin “O2” is simply referred to as O2, and the control signal at the control pin “C” is simply referred to as C. Inverter511receives C and outputs an inverted control signal CinvNAND gate521receives C and 1 and outputs O1. NAND gate522receives I1and Cinvand outputs an inverted input clock Iinv. NAND gate523receives Iinvand I2and outputs O2. When C pin is 1, Cinvis 0, Iinvis 1, O1is an inversion of h, and O2is an inversion of I2. However, a duty cycle of O1can be different from a duty cycle of I1and it depends on the circuit implementation of NAND gate521. Likewise, a duty cycle of O2can be different from a duty cycle of I2and it depends on the circuit implementation of NAND gate523. When C is 0, O1and Cinvare both 1, and Iinvis an inversion of h. In a case where UCM500is instantiated to embody UCM413, O1will propagate into I2through the uneven clock buffer420, and thus I2will be 1. In a case where UCM500to embody UCM412, O1will propagate into I2through UCM413and the uneven clock buffer420and thus I2will be 1. In a case where UCM500is instantiated to embody UCM411, O1will propagate into I2through UCM412, UCM413, and the uneven clock buffer420and thus I2will be 1. In a case where UCM500is instantiated to embody UCM410, O1will propagate into I2through UCM411, UCM412, UCM413, and the uneven clock buffer420and thus I2will be 1. Therefore, in any case, O1will always propagate into I2and thus I2will always be 1, and O2will always be an inversion of Iinv, and thus the same as I1. That's why, earlier in this disclosure, it is said that when C is 0, I1will propagate into O2, while O1and I2become irrelevant (seeFIG.3B). However, a duty cycle of O2can be different from a duty cycle of I1and it depends on the circuit implementation of NAND gates522and523. A schematic diagram of a NAND gate600that can be instantiated to embody NAND gates521(522,523) is shown inFIG.6. NAND gate comprises two PMOS transistors631and632, two NMOS transistors633and634, and three optional resistors641,642, and643. Except for the three optional resistors, NAND gate600is a circuit well known in the prior art and thus not be described in detailed. A purpose of using the three optional resistors will be explained shortly. Consider the case where the NAND gate600is used to embody NAND gate521. If a desired duty cycle change requires O1to have a pull-up weaker than a pull-down in response to a toggle of I1: resistor641is useful and can be incorporated; resistor643is detrimental and should be avoided (i.e., should be replaced by a short circuit); and resistor642is unnecessary. If a desired duty cycle change requires O1to have a pull-down weaker than a pull-up in response to a toggle of I1: resistor643is useful and can be incorporated; resistor641is detrimental and should be avoided (i.e., should be replaced by a short circuit); and resistor642is unnecessary. Consider the case where the NAND gate600is used to embody NAND gate522. If a desired duty cycle change requires Iinvto have a pull-up weaker than a pull-down in response to a toggle of I1: resistor641is useful and can be incorporated; resistor643is detrimental and should be avoided (i.e., should be replaced by a short circuit); and resistor642is unnecessary. If a desired duty cycle change requires Iinvto have a pull-down weaker than a pull-up in response to a toggle of I1: resistor643is useful and can be incorporated; resistor641is detrimental and should be avoided (i.e., should be replaced by a short circuit); and resistor642is unnecessary. Consider the case where the NAND gate600is used to embody NAND gate523. If a desired duty cycle change requires O2to have a pull-up weaker than a pull-down in response to either a toggle of I2or a toggle of Iinv: resistors641and642are useful and can be incorporated; and resistor643is detrimental and should be avoided (i.e., should be replaced by a short circuit). If a desired duty cycle change requires O2to have a pull-down weaker than a pull-up in response to either a toggle of I2or a toggle of Iinv: resistor643is useful and can be incorporated, while resistors641and642are detrimental (and should be replaced by a short circuit). For NAND gate600, however, one can choose not to incorporate resistors641,642, or643, but instead resort to using proper width/length ratios to make PMOS transistors631and/or632intentionally have a pull-up strength that is either greater than or smaller than a pull-down strength of NMOS transistors633and/or634. This approach, however, leads to a higher flicker noise, and thus may not be favorable. Note that, for a clock, once inverted, the roles of pull-up and pull-down are swapped. So, although an original clock needs a weaker pull-down than a pull-up to have a larger duty cycle, an inversion of the original clock will need a weaker pull-up than a pull-down to have a larger duty cycle, if we refer to the equivalent duty cycle of the original clock. In the one-directional duty adjustment circuit400, if UCM500ofFIG.5is used to embody UCM410,411,412, and413, an objective of effectively having a larger duty cycle of Cxwill demand a pull-up weaker than a pull-down for X0, X2, Y0and Y2, but a pull-down weaker than a pull-up for X1, X3, Y1and Y3, due to an inverting nature of a propagation from I1to O1and from I2to O2of UCM500. Since there are numerous modifications and alterations that are possible, it'll be futile to exhaustively list all possibilities, as simply adding an extra inverter would swap the roles of pull-up and pull-down, and thus the appended claims will focus on an underlying principle without attempting to specify whether a pull-up is stronger than a pull-down. An uneven clock buffer700that can be used to embody the uneven clock buffer420ofFIG.4is shown inFIG.7. The uneven clock buffer700comprises two PMOS transistors731and732, two NMOS transistors733and734, and four optional resistors741,742,743, and744. If a desired duty cycle change requires Y3to have a pull-up weaker than a pull-down in response to a toggle of X3, resistors742and743are helpful and can be incorporated, while resistors741and742are detrimental and should be avoided (i.e., replaced by a short circuit). If a desired duty cycle change requires Y3to have a pull-down weaker than a pull-up in response to a toggle of X3, resistors741and744are helpful and can be incorporated, while resistors742and743are detrimental and should be avoided (i.e., replaced by a short circuit). Now refer toFIG.4. In the appended claims, UCM411(412,413) is said to be a succeeding UCM of UCM410(411,412), while UCM410(411,412) is said to be a preceding UCM of UCM411(412,413). Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims. | 22,447 |
11942944 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) The exemplary embodiments of this invention will be described in relation to oscillator systems, and in particular to an oscillator comprising at least two operably coupled signal delay circuits having inversely correlated voltage response characteristics. However, it is understood by a person skilled in the art that any number and type of suitable signal delay stages may be used provided that the sum of all voltage characteristics cancels out, or at least minimises, any frequency variation for variations in the supply voltage. As is known in the field, an RC oscillator's frequency is (approximately) inversely proportional to the supply voltage. On the other hand, a ring oscillator's frequency is proportional to supply voltage. The improved oscillator of the present invention is a hybrid oscillator that combines the characteristics of a ring oscillator stage with the characteristics of an RC oscillator stage. In particular, the oscillator of the present invention is a combination of a ring oscillator stage in series with an RC oscillator stage. FIG.4shows a simplified circuit diagram of an example embodiment of an oscillator of the present invention. Here, the ring oscillator stage102features a number of inverters104a,104b,104c,104dand104ein series. The RC oscillator stage106features one inverter104e, with a resistance108and a capacitance110connected in series between the output112and the input114of inverter104e. The junction116between the resistor108and the capacitance110is also connected to the input118of the ring oscillator stage102. Although, capacitor110is shown connected to the input of the inverter104eand the resistor108is connected to the output of the inverter104e, their positions may also be reversed without deviating from the inventive concept of the hybrid oscillator. Another inverter104fmay be coupled to the output112to provide an optional output buffer stage. In embodiments of the present invention the frequency of the ring oscillator stage102is approximately matched to the frequency of the RC oscillator stage106. FIG.5shows simulated results (dashed line) from the hybrid oscillator100of the present invention, as well as, those from an RC oscillator (continuous line) and a ring oscillator (dash-dot line) for comparison. The plot shows the variation in oscillator frequency (vertical axis) over a range of supply voltage (horizontal axis). In this particular simulation, all three oscillators were specified for the same nominal frequency of 450 kHz at a supply voltage Vdd−Vssof 4.5 V. The comparison clearly shows that the hybrid oscillator frequency variation is significantly less over the range of supply voltage than either one of the ring oscillator or the RC oscillator. FIG.6is an alternative embodiment 200 to embodiment 100 shown inFIG.4, containing the same components as the circuit diagram shown inFIG.4, but without the buffer stage104f. An inverter delay circuit is formed from five inverters in series, i.e. inverters122and124, these five inverters being arranged around resistor108and capacitor110so as to make the RC delay circuit126oscillate. It is instructive to consider the operation of this circuit in the time domain, rather than in the frequency domain. The cycle delay through all five inverters124and122of the inverter delay circuit needs to be approximately matched to the time constant of the RC delay circuit126. The number of inverter stages and the inverter specifications/characteristics (i.e. load resistances, transistor impedances, etc.) in the ring oscillator102or inverter delay circuit122and124, and the resistor108and capacitor110components and inverter specifications/characteristics in the RC oscillator106or RC delay circuit126may be chosen so as to optimise oscillator performance (i.e. frequency stability, oscillating accuracy) over a desired range of the supply voltage (i.e. Vdd−Vss) and a desired frequency range. Alternatively, the ring oscillator stage102and the RC oscillator stage106may each be separately optimised for a frequency range that is centred on a frequency that is double the desired centre frequency of the hybrid oscillator100. In another alternative embodiment, the inverter delay circuit122and124and the RC delay circuit126may each be separately optimised for a delay range that is centred on a delay that is one half (i.e. ½) of the desired overall cycle delay of the hybrid oscillator200. FIGS.7(a) and (b)illustrate the simplified RC oscillator operation within the hybrid oscillator, (a) showing logic states at each one of the components of the hybrid oscillator are shown as logic ‘1’ or logic ‘0’ at a first time, and (b) showing the logic states at a subsequent clock cycle. The delay time depends on the charging/discharging of the RC element108,110, and, as is known in the art, is dominated by the discharge time. Therefore, the overall RC stage delay time increases as the supply voltage is increased. FIG.8illustrates the ring oscillator operation within the hybrid oscillator, represented by a unipolar inverter stage comprising transistors202(of the same type) and resistors204. Here, the delay time depends on the charging/discharging of the gate capacitance of the transistor202, and, as is known in the art, decreases in both charge and discharge cycles with increases in supply voltage. Hence the overall ring oscillator stage delay time decreases as the supply voltage increases. When the ring oscillator stage delay time is approximately matched to that of the RC oscillator stage, this has the effect of substantially cancelling out the supply voltage-dependence characteristics of the RC oscillator shown above. It will be appreciated by persons skilled in the art that the above embodiment(s) have been described by way of example only and not in any limitative sense, and that various alterations and modifications are possible without departing from the scope of the invention as defined by the appended claims. | 6,027 |
11942945 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A master-slave flip-flop includes a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch. The master latch is coupled between the gated input circuit and the transmission gate. In some embodiments, a modified timing circuit for controlling the master-slave flip-flop improves the reliability of the operation sequences that the transmission gate is opened before the gated input circuit is changed to the connected state. In some embodiments, the modified timing circuit includes a first time delay circuit and a second time delay circuit. The first time delay circuit has an output coupled to an input of the second time delay circuit. A clock signal at the output of the first time delay circuit is coupled to the transmission gate, and a clock signal at the output of the second time delay circuit is coupled to the gated input circuit. In some embodiments, at least a portion of a first gate-conductor in a time delay circuit is atop a structure having active regions. FIGS.1A-1Bare circuit diagrams of a master-slave flip-flop100and a timing circuit180for generating the clock signals for the master-slave flip-flop100, in accordance with some embodiments. InFIG.1B, the timing circuit180includes time delay circuits182,184,186,185, and187. The timing circuit180receives a base clock signal CP, and generates various time delayed clock signals clkb, clkbb, clkbbb, clkb_m, and clkbb_m which are coupled to the master-slave flip-flop100to control the operation of various components in the master-slave flip-flop100.FIG.2is a timing diagram of various clock signals in the timing circuit180and various data signals in the master-slave flip-flop100, in accordance with some embodiments. InFIG.1B, the base clock signal CP is received at the input of the time delay circuit182, and the inversion of the base clock signal CP with some time delay is generated as the first clock signal clkb at the output of the time delay circuit182. Because the first clock signal clkb is the inverse of the base clock signal CP, as shown inFIG.2, when the base clock signal CP changes from the logic LOW to the logic HIGH, the first clock signal clkb correspondingly changes from the logic HIGH to the logic LOW. The falling edge of the first clock signal clkb follows the rising edge of the base clock signal CP with some time delay. Similarly, as shown inFIG.2, when the base clock signal CP changes from the logic HIGH to the logic LOW, the first clock signal clkb correspondingly changes from the logic LOW to the logic HIGH. The rising edge of the first clock signal clkb follows the falling edge of the base clock signal CP also with some time delay. InFIG.1B, the first clock signal clkb at the output of the time delay circuit182is received at the input of the time delay circuit184, and the inverse of the first clock signal clkb with some time delay is generated as the second clock signal clkbb at the output of the time delay circuit184. The time delay circuit185receives the second clock signal clkbb at one input and receives the scan enabling signal SE at another input. If the scan enabling signal SE is set as the logic LOW, the inverse of the second clock signal clkbb with some time delay is generated as the third clock signal clkb_m at the output of the time delay circuit185. The output signal of the time delay circuit185is coupled to the input of the time delay circuit187, and the inverse of the third clock signal clkb_m is generated as clock signal clkbb_m at the output of the time delay circuit187. Additionally, inFIG.1B, the second clock signal clkbb is also received by the time delay circuit186, and the inverse of the second clock signal clkbb is generated as clock signal clkbbb at the output of the time delay circuit186. In the timing diagram ofFIG.2, the base clock signal CP has a time period T with 50% duty cycle, and one of the falling edges of the base clock signal CP is at time t0as identified in the figure. The first clock signal clkb is delayed from the base clock signal CP by a time delay τa and has a rising edge at time t0+τa. In addition, the second clock signal clkbb is delayed from the first clock signal clkb by a time delay τb, and the clock signal clkbbb is delayed from the second clock signal clkbb by a time delay τd. One of the falling edges of the second clock signal clkbb is at time t0+τa+τb, and one of the rising edges of the clock signal clkbbb is at time t0+τa+τb+τd. Furthermore, the third clock signal clkb_m is delayed from the second clock signal clkbb by a time delay τc, and the clock signal clkbb_m is delayed from the third clock signal clkb_m by a time delay τe. One of the rising edges of the third clock signal clkb_m is at time t0+τa+τb+τc, and one of the falling edges of the clock signal clkbb_m is at time t0+τa+τb+τc+τe. In some embodiments, each of the time delay circuits182,184,186, and187is implemented as an inverter gate, and the time delay circuit185is implemented as a NOR gate. Other implementations of the time delay circuits are within the contemplated scope of the present disclosure. For example, in some alternative embodiments, one or more of the time delay circuits182,184,186, and187are implemented as three serially connected inverter gates. In some alternative embodiments, the time delay circuit185is implemented as one NOR gate coupled with two serially connected inverter gates. InFIG.1A, the master-slave flip-flop100includes a gated input circuit110, a master latch120, a transmission gate130, a slave latch140, and an inverter150. The gated input circuit110receives an input data D at the input terminal of the master-slave flip-flop100and receives the clock signals clkb_m and clkbb_m from the timing circuit180. The master latch120, which is coupled between the gated input circuit110and the transmission gate130, receives the clock signals clkbb and clkbbb from the timing circuit180. The transmission gate130, which is coupled between the master latch120and the slave latch140, receives the clock signals clkbb and clkb from the timing circuit180. The slave latch140, which is coupled between the transmission gate130and the inverter150, receives the clock signals clkb and clkbb from the timing circuit180. InFIG.1A, the gated input circuit110is implemented as a clocked inverter. The input transmission state of the gated input circuit110is controlled by the clock signals clkb_m and clkbb_m received from the timing circuit180. When the third clock signal clkb_m is at the logic HIGH and/or the clock signal clkbb_m is at the logic LOW, the input transmission state of the gated input circuit110is set to the connected state, and the inverse of the input data D is generated at the output of the gated input circuit110which is coupled to the input node ml_ax of the master latch120. In the timing diagram ofFIG.2, the input transmission state of the gated input circuit110is driven to the connected state during one time interval from time t1=t0+τa+τb+τc to time t0+τa+τb+τc+τe+T/2 and during another time interval from time t4=t0+τa+τb+τc+T to time t0+τa+τb+τc+τe+3T/2. InFIG.1A, the master latch120includes an inverter122and a clocked inverter124driven by the clock signals clkbb and clkbbb. When the second clock signal clkbb is at the logic LOW and the clock signal clkbbb is at the logic HIGH, the master latch120is at the unlatched state, the output signal of the clocked inverter124is the inverse of the input signal of the clocked inverter124. When the second clock signal clkbb is at the logic HIGH and/or the clock signal clkbbb is at the logic LOW, the master latch120is at the latched state, and the signal at the output node ml_b is latched in the master latch120. In the timing diagram ofFIG.2, the master latch120is latched during one time interval from time t2=t0+τa+τb+T/2 to time t0+τa+τb+τd+T and during another time interval from time t5=t0+τa+τb+3T/2 to time t0+τa+τb+τd+2T. InFIG.1A, the transmission gate130is controlled by the second clock signal clkbb and the first clock signal clkb received from the timing circuit180. When the second clock signal clkbb is at the logic HIGH and/or the first clock signal clkb is at the logic LOW, the transmission state of the transmission gate130is set to the connected state, and the input node sl_a of the slave latch140is conductively connected to the output node ml_b of the master latch120. In the timing diagram ofFIG.2, the transmission state of the transmission gate130is driven to the connected state during one time interval from time t0+τa+T/2 to time t0+τca+τb+T and during another time interval from time t0+τa+3T/2 to time t0+τa+τb+2T. InFIG.1A, the slave latch140includes an inverter142and a clocked inverter144driven by the clock signals clkb and clkbb. When the first clock signal clkb is at the logic LOW and the second clock signal clkbb is at the logic HIGH, the slave latch140is at the unlatched state, and the output signal of the clocked inverter144is the inverse of the input signal of the clocked inverter144. When the first clock signal clkb is at the logic HIGH and/or the second clock signal clkbb is at the logic LOW, the slave latch140is at the latched state, and the signal at the output node sl_bx is latched in the slave latch140. In the timing diagram ofFIG.2, the slave latch140is latched during one time interval from time t0+τa to time t0+τa+τb+T/2 and during another time interval from time t3=t0+τca+T to time t5=t0+τa+τb+3T/2. In addition to the wave forms of various clock signals generated by the timing circuit180,FIG.2also depicts the input signal D(t), the output signal Q(t), and the signals at the circuit nodes ml_ax, ml_b, sl_a, and sl_bx. InFIG.2, as a non-limiting example, if the input signal D(t) has the logic value D1from time t0to time t0+T and has the logic value D2from time t0+T to time t0+2T, then the output signal Q(t) has the logic value D1from time t2to time t2+T and has the logic value D2from time t2+T to time t2+2T. Here, the time t2=t0+τa+τb+T/2. The process of generating the output signal Q(t) from the input signal D(t) is explained in the following, with reference to the signals at the circuit nodes ml_ax, ml_b, sl_a, and sl_bx. InFIG.2, beginning from time t1=t0+τa+τb+τc and ending at time t1+τe+T/2, the gated input circuit110is set to the connected state, and the signal at the input node ml_ax of the master latch120is ˜D(t), which is the inverse of the input data D(t). At time t1, the master latch120is not latched, and the signal at the output node ml_b of the master latch120is ˜ml_ax(t), which is the inverse of the signal ml_ax(t) at the input node ml_ax of the master latch120. At time t1, the transmission gate130is at the open state, and the input node sl_a of the slave latch140is isolated from the output node ml_b of the master latch120. At time t1, the slave latch140is at the latched state, and the signal at the output node sl_bx of the slave latch140is latched to a previous value ˜D0, which is the inverse of the signal of the logic value D0. At time t1, the output signal Q(t) of the master-slave flip-flop100is maintained at the logic value D0. InFIG.2, from time t1to time t2, the signal ml_b(t) at the output node ml_b is equal to the inverse of the signal ml_ax(t), and the signal ml_ax(t) at the input node ml_ax is equal to the inverse of the input signal D(t). That is, ml_b(t)=˜ml_ax(t) and ml_ax(t)=˜D(t). Consequently, the signal at the output node ml_b is equal to the input data D(t), which is ml_b(t)=D(t). At time t2, the signal at the output node ml_b of the master latch120is equal to the logic value D_1. The logic value D1at the output node ml_b is latched from time t2to time t2+τd+T/2. Additionally, at time t2, the transmission gate130is at the connected state, and the signal sl_a(t) at the input node sl_a of the slave latch140is identical to the signal ml_b(t) at the output node ml_b of the master latch120, which has the logic value D1. Beginning from time t2, the slave latch140is unlatched, and the signal at the output node sl_bx is the inverse of the signal at the input node sl_a. At least during the time period from time t2to time t3, the signal at the input node sl_a of the slave latch140is identical to the logic value D_1. Consequently, from time t2to time t3, the signal at the output node sl_bx of the slave latch140is identical to ˜D1(the inverse of the logic signal D1). The logic value ˜D1at the output node sl_bx of the slave latch140is latched from time t3to time t5=τ3+τb+T/2. Therefore, the output node sl_bx is at the logic value ˜D1from time t2to time t5, and the output signal Q(t) of the master-slave flip-flop100is the logic value D1from time t2to time t5=τ2+T. Similarly, in the example ofFIG.2, when the input signal D(t) has the logic value D2from time t0+T to time t0+2T, the output signal Q(t) of the master-slave flip-flop100in response generates the logic value D2from time t5to time t5+T. Specifically, inFIG.2, at least during the time period from t4to time t5, the gated input circuit110is at the connected state, the master latch120is at the unlatched state, and the signal at the output node ml_b of the master latch120is at the logic value D2. Beginning at time t5, the logic value D2at the output node ml_b is latched. At least during the time period from t5to time t6, the output node ml_b of the master latch120is maintained with the logic value D2, the transmission gate130is at the connected state, the slave latch140is at the unlatched state, and the signal at the output node sl_bx of the slave latch140is at the logic value ˜D2. From time t6to time t5+T (not shown in the figure), the output node sl_bx of the slave latch140is latched at the logic value ˜D2. Consequently, from time t5to time t5+T, the output signal Q(t) of the master-slave flip-flop100is D2, which is the inverse of the logic value ˜D2at the output node sl_bx from time t5to time t5+T. FIGS.3A-3Bare circuit diagrams of one specific implementation of the master-slave flip-flop100and the timing circuit180inFIGS.1A-1B, in accordance with some embodiments. InFIG.3A, each of the inverters122,142, and150ofFIG.1Aincludes a p-type transistor and an n-type transistor serially connected between two power supplies. Also inFIG.3A, the transmission gate130includes a p-type transistor and an n-type transistor parallelly connected between the input terminal and output terminal of the transmission gate130, and the gate terminals of the p-type transistor and the n-type transistor are correspondingly configured to receive the two clock signals clkbb and clkb for controlling the transmission state of the transmission gate130. When the clock signal clkbb is at the logic HIGH and/or the first clock signal clkb is at the logic LOW, the transmission state of the transmission gate130is at the connected state, and the output terminal of the transmission gate130is conductively connected to the input terminal of the transmission gate130. When the clock signal clkbb is at the logic LOW and the first clock signal clkb is at the logic HIGH, the transmission state of the transmission gate130is at the open state, and the signal at the output terminal of the transmission gate130is not responsive to signal changes at the input terminal of the transmission gate130. InFIG.3A, each of the clocked inverters112,124, and144ofFIG.1Aincludes two p-type transistors and two n-type transistors all serially connected between two power supplies. In each of the clocked inverters112,124, and144, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as the inverter input terminal, while the gate terminals of the second p-type transistor and the second n-type transistor are correspondingly configured to receive the two clock signals for controlling the inverter transmission state. For example, in the clocked inverter124, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as the inverter input terminal (which is connected to the output of the inverter122), the gate terminal of the second p-type transistor is configured to receive the clock signal clkbbb, and the gate terminal of the second n-type transistor is configured to receive the clock signal clkbb. When the clock signal clkbbb is at the logic LOW and/or the clock signal clkbb is at the logic HIGH, the clocked inverter124functions as an inverter which latches the signal at the output node ml_b of the master latch120. When the clock signal clkbbb is at the logic HIGH and the clock signal clkbb is at the logic LOW, the clocked inverter124is in the open state, and the output signal of the clocked inverter124is not responsive to signal changes at the input terminal of the clocked inverter124. When the clocked inverter124is in the open state, the master latch120is unlatched. Similarly, in the clocked inverter144, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as the inverter input terminal (which is connected to the output of the inverter142), the gate terminal of the second p-type transistor is configured to receive the clock signal clkbb, and the gate terminal of the second n-type transistor is configured to receive the clock signal clkb. When the clock signal clkbb is at the logic LOW and/or the clock signal clkb is at the logic HIGH, the clocked inverter144functions as an inverter which latches the signal at the output node sl_bx of the slave latch140. When the clock signal clkbb is at the logic HIGH and the clock signal clkb is at the logic LOW, the clocked inverter144is in the open state, and the output signal of the clocked inverter144is not responsive to signal changes at the input terminal of the clocked inverter144. When the clocked inverter144is in the open state, the slave latch140is unlatched. InFIG.3B, each of the inverters INV1, INV2, INV3, and INV4ofFIG.1Bincludes a p-type transistor and an n-type transistor serially connected between two power supplies. The NOR gate ofFIG.1Bincludes two p-type transistors and two n-type transistors. The two p-type transistors are serially connected between the power supply VDD and the output node Z. The two n-type transistors are parallelly connected between the output node Z and the power supply VSS. The gate terminals of the first p-type transistor and the first n-type transistor in the NOR gate are connected together as a first input terminal which is connected to the output of the inverter INV2, while the gate terminals of the second p-type transistor and the second n-type transistor in the NOR gate constitute a second input terminal which is configured to receive the scan enable signal SE. InFIG.3A, the gated input circuit110is implemented as a clocked inverter112. The gate terminals of the first p-type transistor and the first n-type transistor in the clocked inverter112are connected together as the input terminal of the gated input circuit110. The gate terminal of the second p-type transistor in the clocked inverter112is configured to receive the clock signal clkbb_m, and the gate terminal of the second n-type transistor in the clocked inverter112is configured to receive the clock signal clkb_m. When the clock signal clkbb_m is at the logic LOW and/or the clock signal clkb_m is at the logic HIGH, the clocked inverter112functions as an inverter which generates an output signal that is the inverse of the input data signal. When the clock signal clkbb_m is at the logic HIGH and the clock signal clkb_m is at the logic LOW, the clocked inverter112is in the open state, and the output signal of the clocked inverter112is not responsive to signal changes at the input terminal of the clocked inverter112. When the clocked inverter112is in the open state, the input node ml_ax of the master latch120is isolated from the input terminal D of the gated input circuit110. In the timing diagram ofFIG.2, because the clock signal clkb_m is delayed from the second clock signal clkbb with the delay time τc, the transmission gate130is opened (at the falling edge of the clock signal clkbb inFIG.2) before the gated input circuit110is changed to the connected state (at the rising edge of the clock signal clkb_m inFIG.2). Consequently, signal changes at the input of the gated input circuit110during the time interval from the falling edge of the base clock signal CP to the falling edge of the clock signal clkbb do not get propagated to the input node sl_a of the slave latch140. The timing circuit180provides improved reliability for the operation sequence that the transmission gate130is opened before the gated input circuit110is changed to the connected state. With the timing circuit180, the above mentioned operation sequence is ensured even if the falling edge of the clock signal clkbb has large variations. In some other designs of the timing circuit; however, as the supply voltage difference between VDD and VSS is lowered and approaches a threshold, the variations in the falling edge of the clock signal clkbb may become too large and the variations may have negative impact to the reliability for the above mentioned operation sequence. In some embodiments, because of the improved reliability for the above mentioned operation sequence, the supply voltage difference between VDD and VSS in the timing circuit180is lower than that supply voltage difference in some other designs of the timing circuit. FIGS.4A-4Bare circuit diagrams of one specific implementation of the master-slave flip-flop100and the timing circuit180inFIGS.1A-1B, in accordance with some embodiments. For the timing circuit180, the implementation inFIG.4Bis identical to the implementation inFIG.3B. For the master-slave flip-flop100, the implementation inFIG.4Ais modified based on the implementation inFIG.3A. While the gated input circuit110inFIG.3Ais implemented as a single clocked inverter112, the gated input circuit110inFIG.4Aincludes two clocked inverters112A and112B and another scan input circuit116. The input terminals of the clocked inverters112A and112B are connected together to receive the input data D for the gated input circuit110. The output terminals of the clocked inverters112A and112B and the output terminal of the scan input circuit116are all connected together as the output terminal of the gated input circuit110. Each of the two clocked inverters112A and112B is controlled by the two clock signals clkbb_m and clkb_m. The scan input circuit116includes three p-type transistors and three n-type transistors all serially connected between two power supplies. The three p-type transistors are serially connected between the power supply VDD and the output terminal of the scan input circuit116(which is directly connected to the input node ml_ax of the master latch120). The three n-type transistors are serially connected between the output terminal of the scan input circuit116and the power supply VSS. The gate terminals of the first p-type transistor and the first n-type transistor in the scan input circuit116are configured to receive the scan input signal SI. The gate terminal of the second p-type transistor in the scan input circuit116is configured to receive the clock signal clkbb, and the gate terminal of the second n-type transistor in the scan input circuit116is configured to receive the clock signal clkb. The gate terminals of the third p-type transistor in the scan input circuit116is configured to receive from the inverter105the signal seb, and the third n-type transistor in the scan input circuit116is configured to receive the scan enable signal SE. The input of the inverter105is also configured to receive the scan enable signal SE, and the signal seb at the output of the inverter105is an inverse of the scan enable signal SE. In operation, when the scan enable signal SE is at logic HIGH, both the third p-type transistor and the third n-type transistor in the scan input circuit116are in the conducting state, and the scan input circuit116is enabled. When the scan input circuit116is enabled, the scan input circuit116is equivalent to a clocked inverter that is controlled by the clock signals clkbb and clkb and also receives the scan input signal SI as the input signal. Additionally, when the scan enable signal SE is kept at logic HIGH, one of the inputs of the NOR gate is kept at the logic HIGH. As a consequence, the clock signals clkb_m is kept at the logic LOW and the clock signals clkbb_m is kept at the logic HIGH. As the clock signals clkb_m and clkbb_m are correspondingly applied to the gate terminals of the n-type transistors and the second p-type transistors in each of the clocked inverters112A and112B, the logic LOW (i.e., the clock signal clkb_m) at the gate terminals of the n-type transistors and the logic HIGH (i.e., the clock signal clkbb_m) at the gate terminal of the p-type transistors set each of the clocked inverters112A and112B into the open state, which isolates the signal at the input node ml_ax of the master latch129from the data input signal D at the input of the gated input circuit110during the time period when the scan enable signal SE is kept at the logic HIGH. In the gated input circuit110, when the scan enable signal SE is at the logic HIGH, the data input signal D is disabled and the scan input signal SI is enabled, for generating the output signal at output terminal of the gated input circuit110. Conversely, when the scan enable signal SE is at the logic LOW, the data input signal D is enabled and the scan input signal SI is disabled, for generating the output signal at output terminal of the gated input circuit110. FIG.5Ais a layout diagram of parts of the timing circuit180inFIG.3BandFIG.4B, in accordance with some embodiments.FIGS.5B-5Dare cross-sectional views of the timing circuit180as specified by the layout diagram inFIG.5A, in accordance with some embodiments.FIG.5Eis an equivalent circuit for a part of the layout diagram inFIG.5A, in accordance with some embodiments. InFIG.3BandFIG.4B, the timing circuit180includes four inverters INV1-INV4and a NOR gate. In the timing circuit180as specified by the layout diagram ofFIG.5A, the inverters INV1, INV2, and INV3are fabricated in a first area501in the integrated circuit, and the NOR gate is fabricated in a second area502. The location of the inverter INV4is not specifically identified in the layout diagram. As specified by the layout diagram ofFIG.5A, each of the inverters INV1, INV2, and INV3includes a corresponding gate-conductor intersecting a p-type active region structure82pand an n-type active region structure82nin the first area501. In some embodiments, the p-type active region structure82pand the n-type active region structure82nare fin structures, and the transistors in the inverters INV1, INV2, and INV3are fin transistors. In some embodiments, the p-type active region structure82pand the n-type active region structure82nare nano-sheet structures, and the transistors in the inverters INV1, INV2, and INV3are nano-sheet transistors. In some embodiments, the p-type active region structure82pand the n-type active region structure82nare nano-wire structures, and the transistors in the inverters INV1, INV2, and INV3are nano-wire transistors. The gate-conductor551intersects the p-type active region structure82pand the n-type active region structure82nand forms correspondingly the channel regions for the p-type transistor T2pand the n-type transistor T2nin the INV2. The gate-conductor553intersects the p-type active region structure82pand the n-type active region structure82nand forms correspondingly the channel regions for the p-type transistor T1pand the n-type transistor T1nin the INV1. The gate-conductor555intersects the p-type active region structure82pand the n-type active region structure82nand forms correspondingly the channel regions for the p-type transistor T3pand the n-type transistor T3nin the INV3. While each of the dummy gate-conductors552p,554p,556p,552n,554n,556nintersects the active region structures, each intersection does not correspond to the channel of a working transistor in the timing circuit180. The equivalent circuit formed by the three p-type transistors (T1p, T2p, and T3p) and the three n-type transistors (Tin, T2n, and T3n) in the three inverters (INV1, INV2, and INV3) inFIG.5Aare depicted inFIG.5E. In the layout diagram ofFIG.5Aand as shown inFIG.5E, each of the terminal-conductors531p,533p, and535pintersects the p-type active region structure82pat a corresponding source region of one of the p-type transistors T2p, T1p, and T3p. Each of the terminal-conductors531n,533n, and535nintersects the n-type active region structure82nat a corresponding source region of one of the n-type transistors T2n, T1n, and T3n. Each of the terminal-conductors531p,533p, and535pis connected to a power rail (not shown inFIG.5A) configured to provide the power supply VDD. Each of the terminal-conductors531n,533n, and535nis connected to a power rail (not shown inFIG.5A) configured to provide the power supply VSS. In the layout diagram ofFIG.5Aand as shown inFIG.5E, the terminal-conductor534intersects the p-type active region structure82pat the drain region for the p-type transistor T1pand intersects the n-type active region structure82nat the drain region for the n-type transistor T1n. The terminal-conductor534forms the output terminal of the inverter INV1. The terminal-conductor534is conductively connected to the horizontal conducting line540through the terminal via-connector VD1. The horizontal conducting line540is conductively connected to the gate-conductor551through the gate via-connector VG2. The gate-conductor551functions as the input terminal of the inverter INV2. The terminal-conductor532intersects the p-type active region structure82pat the drain region for the p-type transistor T2pand intersects the n-type active region structure82nat the drain region for the n-type transistor T2n. The terminal-conductor532forms the output terminal of the inverter INV2. The terminal-conductor532is conductively connected to the horizontal conducting line520through the terminal via-connector VD2. The horizontal conducting line520is conductively connected to the gate-conductor555through the gate via-connector VG3. The gate-conductor555functions as the input terminal of the inverter INV3. In addition toFIG.5AandFIG.5E, the connection from the output terminal of the inverter INV1to the input terminal of the inverter INV2is also shown in the cross-sectional view ofFIG.5D, and the connection from the output terminal of the inverter INV2to the input terminal of the inverter INV3is also shown in cross-sectional view ofFIG.5C. FIG.5Cis a cross-sectional view of the circuit inFIG.5Ain a cutting plane P-P″, in accordance with some embodiments. InFIG.5C, each of the gate-conductors551,552n,553,554n,555, and556nintersects the n-type active region structure82non the substrate510. The terminal-conductor532is conductively connected to the horizontal conducting line520through the terminal via-connector VD2. The horizontal conducting line520is conductively connected to the gate-conductor555through the gate via-connector VG3. The horizontal conducting line520is in the first connection layer M0overlying the isolation materials covering the gate-conductors and the terminal-conductors. FIG.5Dis a cross-sectional view of the circuit inFIG.5Ain a cutting plane Q-Q′, in accordance with some embodiments. InFIG.5D, each of the gate-conductors551,552p,553,554p,555, and556pintersects the p-type active region structure82pon the substrate510. The terminal-conductor534is conductively connected to the horizontal conducting line540through the terminal via-connector VD1. The horizontal conducting line540is conductively connected to the gate-conductor551through the gate via-connector VG2. The horizontal conducting line540is in the first connection layer M0overlying the isolation materials covering the gate-conductors and the terminal-conductors. As shown inFIG.5D, the gate via-connector VG2for connecting the gate-conductor551with the horizontal conducting line540is at least partially positioned atop the p-type active region structure82p. The position of the gate via-connector VG2relative to the p-type active region structure82pis also depicted inFIG.5B. FIG.5Bis a cross-sectional view of the circuit inFIG.5Ain a cutting plane S-S′, in accordance with some embodiments. As shown inFIG.5B, the gate-conductor551intersects both the p-type active region structure82pand the n-type active region structure82non the substrate510. The horizontal conducting lines520and540are in the first connection layer M0above the gate-conductor551. The horizontal conducting line540is conductively connected to the gate-conductor551through the gate via-connector VG2. The combination of the cross-sectional views inFIG.5BandFIG.5Dindicates that all of the gate via-connector VG2is positioned atop the p-type active region structure82p. In some alternative embodiments, only a portion of the gate via-connector VG2is positioned atop the p-type active region structure82p. A non-limiting example of the integrated circuits as implemented in the alternative embodiments is shown inFIGS.6A-6D. FIG.6Ais a layout diagram of parts of the timing circuit180inFIG.3BandFIG.4B, in accordance with some embodiments.FIG.6Bis a cross-sectional view of the circuit inFIG.6Ain a cutting plane S-S′, in accordance with some embodiments.FIG.6Cis a cross-sectional view of the circuit inFIG.6Ain a cutting plane P-P′, in accordance with some embodiments.FIG.6Dis a cross-sectional view of the circuit inFIG.6Ain a cutting plane Q-Q′, in accordance with some embodiments. The layout diagram inFIG.6Ais modified from the layout diagram inFIG.5Aby shifting the gate via-connector VG2, the terminal via-connector VD1, and the horizontal conducting line540along the Y-direction such that only a portion of the gate via-connector VG2is positioned directly atop the p-type active region structure82p. The equivalent circuit for the layout diagram inFIG.5Ais identical to the equivalent circuit for the layout diagram inFIG.6A; therefore,FIG.5Eis also an equivalent circuit for parts of the layout diagram inFIG.6A, in accordance with some embodiments. Furthermore, because the layout diagram inFIG.6Ais a modification of the layout diagram inFIG.5A, the cross-sectional views inFIG.6BandFIG.6Dare modified from the cross-sectional views inFIG.5BandFIG.5Daccordingly, while the cross-sectional view inFIG.6Cis the same as the cross-sectional view inFIG.5C. InFIG.6D, the terminal-conductor534is conductively connected to the horizontal conducting line540through the terminal via-connector VD1. The horizontal conducting line540is conductively connected to the gate-conductor551through the gate via-connector VG2. The horizontal conducting line540is in the first connection layer M0overlying the isolation materials covering the gate-conductors and the terminal-conductors. While the p-type active region structure82pon the substrate510is in the cross-sectional view inFIG.5D, the p-type active region structure82pon the substrate510does not appear in the cross-sectional view inFIG.6D, because the cutting plane Q-Q′ inFIG.6Adoes not pass through the p-type active region structure82p. InFIG.6B, the gate-conductor551intersects both the p-type active region structure82pand the n-type active region structure82non the substrate510. The horizontal conducting lines520and540are in the first connection layer M0above the gate-conductor551. The horizontal conducting line540is conductively connected to the gate-conductor551through the gate via-connector VG2. The combination of the cross-sectional views inFIG.6BandFIG.6Dindicates that only a portion of the gate via-connector VG2is positioned directly atop the p-type active region structure82p. Another modification of the layout diagram inFIG.5Ais the layout diagram inFIG.7A.FIG.7Ais a layout diagram of parts of the timing circuit180inFIG.3BandFIG.4B, in accordance with some embodiments.FIG.7Bis a cross-sectional view of the circuit inFIG.7Ain a cutting plane S-S′, in accordance with some embodiments.FIG.7Cis a cross-sectional view of the circuit inFIG.7Ain a cutting plane P-P′, in accordance with some embodiments.FIG.7Dis a cross-sectional view of the circuit inFIG.7Ain a cutting plane Q-Q′, in accordance with some embodiments.FIG.7Eis an equivalent circuit for a part of the layout diagram inFIG.7A, in accordance with some embodiments. The layout diagram inFIG.7Ais modified from the layout diagram inFIG.5Aby replacing the dummy gate-conductors552nand552pwith the gate-conductor552. The gate-conductor552intersects the p-type active region structure82pand the n-type active region structure82nand forms correspondingly the channel regions for the p-type transistor T2Bp and the n-type transistor T2Bn in the inverter INV2. The gate-conductor552is conductively connected to the horizontal conducting line540through the gate via-connector VG2b. InFIG.7AandFIG.7E, the inverter INV2formed by the transistors T2p, T2n, T2Bp, and T2Bn has improved driving strength as compared with the inverter INV2(which is formed by the transistors T2pand T2n) inFIG.5AandFIG.5E. That is, the driving strength of the inverter INV2inFIG.7Ais larger than the driving strength of the inverter INV2inFIG.5A. Furthermore, because the layout diagram inFIG.7Ais a modification of the layout diagram inFIG.5A, the cross-sectional views inFIG.7CandFIG.7Dare modified from the cross-sectional views inFIG.5CandFIG.5Daccordingly, while the cross-sectional views inFIG.7Bis the same as the cross-sectional view inFIG.5B. InFIG.7C, the gate-conductor552replaces the dummy gate-conductors552ninFIG.5C, and the gate-conductors552intersects the n-type active region structure82nat the channel region of the n-type transitory T2Bn. InFIG.7D, the gate-conductor552replaces the dummy gate-conductors552pinFIG.5D, and the gate-conductors552intersects the p-type active region structure82pat the channel region of the p-type transitory T2Bp. The gate-conductor552inFIG.7Dis conductively connected to the horizontal conducting line540through the gate via-connector VG2b. InFIG.7D, the terminal-conductor534in the inverter INV1is conductively connected to the gate-conductors551and552in the inverter INV2. In the layout diagrams ofFIG.5A,FIG.6A, andFIG.7A, the inverters INV1, INV2, and INV3in the timing circuit180are implemented in the first area501, the NOR gate in the timing circuit180is implemented in the second area502. The NOR gate includes two p-type transistors and two n-type transistors. InFIG.5A,FIG.6A, andFIG.7A, the gate-conductor558intersects the p-type active region structure84pand the n-type active region structure84ncorrespondingly at the channel regions of the first one of the p-type transistors and the first one of the n-type transistors. The gate-conductor559intersects the p-type active region structure84pand the n-type active region structure84ncorrespondingly at the channel regions of the second one of the p-type transistors and the second one of the n-type transistors. The gate via-connector VG8conductively connects the gate-conductor558to a first corresponding horizontal conducting line (not shown in the figure) in the first metal layer M0. In some embodiments, all of the gate-conductor558is atop the n-type active region structure84nin the second area502. In some embodiments, only a portion of the gate-conductor558is atop the n-type active region structure84nin the second area502. Similarly, the gate via-connector VG9conductively connects the gate-conductor559to a second corresponding horizontal conducting line (not shown in the figure). In some embodiments, all of the gate-conductor559is atop the n-type active region structure84nin the second area502. In some embodiments, only a portion of the gate-conductor559is atop the n-type active region structure84nin the second area502. In some embodiments, the driving strength of the inverter INV2in the timing circuit180is larger than the driving strength of the NOR gate in the timing circuit180. In some embodiments, when the inverter INV2(e.g., the inverter INV2inFIG.7A) is formed by the transistors T2p, T2n, T2Bp, and T2Bn and includes two gate-conductors551and552, the ratio of the driving strength of the inverter INV2to the driving strength of the NOR gate is larger than 1.0. In some embodiments, the ratio of the driving strength of the inverter INV2to the driving strength of the NOR gate is reversely proportional to the ratio of the output impedance of the inverter INV2to the output impedance of the NOR gate. In some embodiments, the clock signals for driving the master-slave flip-flop100is provided by the timing circuit180inFIG.1B. In some alternative embodiments, the clock signals for driving the master-slave flip-flop100is provided by a timing circuit that is different from the timing circuit180inFIG.1B. FIGS.8A-8Bare circuit diagrams of the master-slave flip-flop100and the timing circuit880for providing the clock signals to drive the master-slave flip-flop100, in accordance with some embodiments. The timing circuit880still includes the inverters INV1, INV2, and INV3in the first area501as specified by one of the layout diagrams inFIG.5A,FIG.6A, orFIG.7A. The master-slave flip-flop100inFIG.8Ais identical to the master-slave flip-flop100inFIG.4A. The timing circuit880inFIG.8B, however, is a modification of the timing circuit180inFIG.1B. InFIG.8B, the time delay circuit183replaces the time delay circuit185ofFIG.1B, and the input terminal of the time delay circuit183is directly connected to the output terminal of the time delay circuit182. In some embodiments, the time delay circuit183is implemented as a NAND gate in the second area502. FIG.8Cis a timing diagram of various clock signals in the timing circuit880and various data signals in the master-slave flip-flop100, in accordance with some embodiments. While the wave forms of the clock signals clkb_m and clkbb_m inFIG.8Care different from the wave forms of the clock signals clkb_m and clkbb_m inFIG.2, the wave forms for other clock signals inFIG.8Care identical to the corresponding wave forms inFIG.2. The wave forms for the various data signals inFIG.8Care also identical to the corresponding wave forms inFIG.2. InFIG.8C, the clock signal clkbb_m is delayed from the first clock signal clkb by a time delay τf, and the clock signal clkb_m is delayed from the clock signal clkbb_m by a time delay τe. As a comparison, inFIG.2, the clock signal clkb_m is delayed from the second clock signal clkbb by a time delay τc, and the clock signal clkbb_m is delayed from the clock signal clkb_m by a time delay τe. In the timing diagram ofFIG.8C, because the clock signal clkbb and the clock signal clkbb_m are both delayed from the same clock signal clkb, in some embodiments, the delay time τf introduced by the NAND gate is made larger than the delay time τb introduced by of the inverter INV2to improve the reliability of the master-slave flip-flop100. For example, in some embodiments, when the gate via-connector VG2is atop the p-type active region structure82pin the first area501(as shown inFIG.5A,FIG.6A,FIG.7A), the delay time of the inverter INV2in the first area501is decreased. In some embodiments, when the gate via-connector VG8and/or the gate via-connector VG9is atop the n-type active region structure84n, the delay time of the NAND gate in the second area502is increased. InFIG.8C, when the delay time τf introduced by the NAND gate is made larger than the delay time τb introduced by the inverter INV2, the clock signal clkbb_m is delayed from the clock signal clkbb, and the transmission gate130is opened (at the falling edge of the clock signal clkbb inFIG.8C) before the gated input circuit110is changed to the connected state (at the falling edge of the clock signal clkbb_m inFIG.8C). Consequently, signal changes at the input of the gated input circuit110during the time interval from the falling edge of the base clock signal CP to the falling edge of the clock signal clkbb do not get propagated to the input node sl_a of the slave latch140. The master-slave flip-flop100inFIG.1A,FIG.3A,FIG.4A, andFIG.8Aare provided as non-limiting examples. The timing circuit180(inFIG.1B,FIG.3B, andFIG.4B) and the timing circuit880(inFIG.8B) are also provided as non-limiting examples. Other implementations of the master-slave flip-flop and/or the timing circuit are within the contemplated scope of present disclosure. Examples of the master-slave flip-flop for use with the timing circuit180or880include the asynchronous reset D flip-flop, the asynchronous set D flip-flop, and the asynchronous set/reset D flip-flop. FIGS.9A-9Bare circuit diagrams of the master-slave flip-flop900A and the timing circuit180for providing the clock signals to drive the master-slave flip-flop900A, in accordance with some embodiments. The circuit diagram of the timing circuit180inFIG.9Bis identical to the timing circuit180inFIG.4B. InFIG.9A, the master-slave flip-flop900A is an asynchronous reset D flip-flop. Each of the master latch120A and the slave latch140A is configured to receive a reset signal CD. During operation, when the reset signal CD is at the logic LOW, each p-type transistor that has the gate terminal receiving the reset signal CD is at the channel conductive state, and each n-type transistor that has the gate terminal receiving the reset signal CD is at the channel opened state. As a consequence, when the reset signal CD is at the logic LOW, the circuit of the master latch120A inFIG.9Ais equivalent to the circuit of the master latch120inFIG.4A, and the circuit of the slave latch140A inFIG.9Ais equivalent to the circuit of the slave latch140inFIG.4A. When the reset signal CD is at the logic LOW, the master-slave flip-flop900A inFIG.9Aoperates like the master-slave flip-flop100inFIG.4A. During operation, when the reset signal CD is at the logic HIGH, each p-type transistor that has the gate terminal receiving the reset signal CD is at the channel opened state, and each n-type transistor that has the gate terminal receiving the reset signal CD is at the channel conductive state. As a consequence, when the reset signal CD is at the logic HIGH, the signal at the output node ml_b of the master latch120A becomes the logic LOW, the signal at the output node sl_bx of the slave latch140A becomes the logic HIGH. When the reset signal CD is at the logic HIGH, the signal at the output of the master-slave flip-flop900A is reset to the logic LOW. FIGS.10A-10Bare circuit diagrams of the master-slave flip-flop900B and the timing circuit180for providing the clock signals to drive the master-slave flip-flop900B, in accordance with some embodiments. The circuit diagram of the timing circuit180in ofFIG.10Bis identical to the timing circuit180inFIG.4B. InFIG.10A, the master-slave flip-flop900B is an asynchronous set D flip-flop. Each of the master latch120B and the slave latch140B is configured to receive a set signal SDN. During operation, when the set signal SDN is at the logic HIGH, each p-type transistor that has the gate terminal receiving the set signal SDN is at the channel opened state, and each n-type transistor that has the gate terminal receiving the set signal SDN is at the channel conductive state. As a consequence, when the set signal SDN is at the logic HIGH, the circuit of the master latch120B inFIG.10Ais equivalent to the circuit of the master latch120inFIG.4A, and the circuit of the slave latch140B inFIG.10Ais equivalent to the circuit of the slave latch140inFIG.4A. When the set signal SDN is at the logic HIGH, the master-slave flip-flop900B inFIG.10Aoperates like the master-slave flip-flop100inFIG.4A. During operation, when the set signal SDN is at the logic LOW, each p-type transistor that has the gate terminal receiving the set signal SDN is at the channel conductive state, and each n-type transistor that has the gate terminal receiving the set signal SDN is at the channel opened state. As a consequence, when the set signal SDN is at the logic LOW, the signal at the output node ml_b of the master latch120B becomes the logic HIGH, the signal at the output node sl_bx of the slave latch140B becomes the logic LOW. When the set signal SDN is at the logic LOW, the signal at the output of the master-slave flip-flop900B is set to the logic HIGH. FIGS.11A-11Bare circuit diagrams of the master-slave flip-flop900C and the timing circuit180for providing the clock signals to drive the master-slave flip-flop900C, in accordance with some embodiments. The circuit diagram of the timing circuit180in ofFIG.11Bis identical to the timing circuit180inFIG.4B. InFIG.11A, the master-slave flip-flop900C is an asynchronous set/reset D flip-flop. Each of the master latch120C and the slave latch140C is configured to receive a reset signal CD and a set signal SDN. During operation, when the reset signal CD is at the logic HIGH, each p-type transistor that has the gate terminal receiving the reset signal CD is at the channel opened state, and each n-type transistor that has the gate terminal receiving the reset signal CD is at the channel conductive state. As a consequence, when the reset signal CD is at the logic HIGH, the signal at the output node ml_b of the master latch120C becomes the logic LOW, the signal at the output node sl_bx of the slave latch140C becomes the logic HIGH. When the reset signal CD is at the logic HIGH, regardless the logic level of the set signal SDN, the signal at the output of the master-slave flip-flop900C is reset to the logic LOW. During operation, when the reset signal CD is at the logic LOW, each p-type transistor that has the gate terminal receiving the reset signal CD is at the channel conductive state, and each n-type transistor that has the gate terminal receiving the reset signal CD is at the channel opened state. As a consequence, when the reset signal CD is at the logic LOW, the operation of the master-slave flip-flop900C depends upon the logic level of the set signal SDN. During operation, when the set signal SDN is at the logic LOW, each p-type transistor that has the gate terminal receiving the set signal SDN is at the channel conductive state, and each n-type transistor that has the gate terminal receiving the set signal SDN is at the channel opened state. As a consequence, when the set signal SDN is at the logic LOW while the reset signal CD is at the logic LOW, the signal at the output node ml_b of the master latch120C becomes the logic HIGH, the signal at the output node sl_bx of the slave latch140C becomes the logic LOW. When the set signal SDN is at the logic LOW while the reset signal CD is at the logic LOW, the signal at the output of the master-slave flip-flop900C is set to the logic HIGH. During operation, when the set signal SDN is at the logic HIGH, each p-type transistor that has the gate terminal receiving the set signal SDN is at the channel opened state, and each n-type transistor that has the gate terminal receiving the set signal SDN is at the channel conductive state. As a consequence, when the set signal SDN is at the logic HIGH while the reset signal CD is at the logic LOW, the circuit of the master latch120C inFIG.11Ais equivalent to the circuit of the master latch120inFIG.4A, and the circuit of the slave latch140C inFIG.11Ais equivalent to the circuit of the slave latch140inFIG.4A. When the set signal SDN is at the logic HIGH while the reset signal CD is at the logic LOW, the master-slave flip-flop900C inFIG.11Aoperates like the master-slave flip-flop100inFIG.4A. FIG.12is a flow chart of a method1200of operating a master-slave flip-flop, in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method1200depicted inFIG.12, and that some other processes may only be briefly described herein. In some embodiments, the circuit diagram of the master-slave flip-flop is shown inFIG.4A. The master-slave flip-flop100inFIG.4Aincludes a gated input circuit110, a master latch120, a slave latch140, and a transmission gate130coupled between the master latch120and the slave latch140. The master latch120is coupled between the gated input circuit110and the transmission gate130. In operation1210of method1200, a second clock signal delayed from the first clock signal is generated. In the embodiments as shown inFIG.4B, the first clock signal clkb at the output of the time delay circuit182is coupled to the input of the time delay circuit184, and the second clock signal clkbb is generated at the output of the time delay circuit184. In some embodiments, as shown inFIG.2, the second clock signal clkbb is the inverse of the first clock signal clkb and delayed from the first clock signal clkb by a time delay τb. In operation1220of method1200, a third clock signal is generated from the second clock signal, and the third clock signal is delayed from the second clock signal. In the embodiments as shown inFIG.4B, the time delay circuit185receives the second clock signal clkbb at one input and receives the scan enabling signal SE at another input, and the third clock signal clkb_m is generated at the output of the time delay circuit185. In some embodiments, as shown inFIG.2, the third clock signal clkb_m is the inverse of the second clock signal clkbb and delayed from the second clock signal clkbb by a time delay τc. In operation1230of method1200, the first clock signal and the second clock signal are transmitted to the transmission gate to change a transmission state of the transmission gate. In the embodiments as shown inFIG.4A, the second clock signal clkbb is coupled to the gate of the n-type transistor in the transmission gate130, and the first clock signal clkb is coupled to the gate of the p-type transistor in the transmission gate130. When the clock signal clkbb is at the logic HIGH and/or the first clock signal clkb is at the logic LOW, the transmission state of the transmission gate130is at the connected state. When the clock signal clkbb is at the logic LOW and the first clock signal clkb is at the logic HIGH, the transmission state of the transmission gate130is at the open state. In operation1240of method1200, an input transmission state of the gated input circuit is controlled with the third clock signal. In the embodiments as shown inFIG.4B, the output signal of the time delay circuit185is coupled to the input of the time delay circuit187, and a fourth clock signal clkbb_m is generated from the third clock signal clkb_m. InFIG.4A, the input transmission state of the gated input circuit110is controlled by the clock signals clkb_m and clkbb_m received from the timing circuit180. When the third clock signal clkb_m is at the logic HIGH and/or the fourth clock signal clkbb_m is at the logic LOW, the input transmission state of the gated input circuit110is set to the connected state. When the third clock signal clkb_m is at the logic LOW and the fourth clock signal clkbb_m is at the logic HIGH, the input transmission state of the gated input circuit110is set to the open state. FIG.13is a block diagram of an electronic design automation (EDA) system1300in accordance with some embodiments. In some embodiments, EDA system1300includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system1300, in accordance with some embodiments. In some embodiments, EDA system1300is a general purpose computing device including a hardware processor1302and a non-transitory, computer-readable storage medium1304. Storage medium1304, amongst other things, is encoded with, i.e., stores, computer program code1306, i.e., a set of executable instructions. Execution of instructions1306by hardware processor1302represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Processor1302is electrically coupled to computer-readable storage medium1304via a bus1308. Processor1302is also electrically coupled to an I/O interface1310by bus1308. A network interface1312is also electrically connected to processor1302via bus1308. Network interface1312is connected to a network1314, so that processor1302and computer-readable storage medium1304are capable of connecting to external elements via network1314. Processor1302is configured to execute computer program code1306encoded in computer-readable storage medium1304in order to cause system1300to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1302is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium1304is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium1304includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium1304includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium1304stores computer program code1306configured to cause system1300(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1304also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1304stores library1307of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium1304stores one or more layout diagrams1309corresponding to one or more layouts disclosed herein. EDA system1300includes I/O interface1310. I/O interface1310is coupled to external circuitry. In one or more embodiments, I/O interface1310includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor1302. EDA system1300also includes network interface1312coupled to processor1302. Network interface1312allows system1300to communicate with network1314, to which one or more other computer systems are connected. Network interface1312includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems1300. System1300is configured to receive information through I/O interface1310. The information received through I/O interface1310includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor1302. The information is transferred to processor1302via bus1308. EDA system1300is configured to receive information related to a UI through I/O interface1310. The information is stored in computer-readable medium1304as user interface (UI)1342. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system1300. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.13is a block diagram of an integrated circuit (IC) manufacturing system1300, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1300. InFIG.14, IC manufacturing system1400includes entities, such as a design house1420, a mask house1430, and an IC manufacturer/fabricator (“fab”)1450, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1460. The entities in system1400are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1420, mask house1430, and IC fab1450is owned by a single larger company. In some embodiments, two or more of design house1420, mask house1430, and IC fab1450coexist in a common facility and use common resources. Design house (or design team)1420generates an IC design layout diagram1422. IC design layout diagram1422includes various geometrical patterns designed for an IC device1460. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1460to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1422includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1420implements a proper design procedure to form IC design layout diagram1422. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1422is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1422can be expressed in a GDSII file format or DFII file format. Mask house1430includes data preparation1432and mask fabrication1444. Mask house1430uses IC design layout diagram1422to manufacture one or more masks1445to be used for fabricating the various layers of IC device1460according to IC design layout diagram1422. Mask house1430performs mask data preparation1432, where IC design layout diagram1422is translated into a representative data file (“RDF”). Mask data preparation1432provides the RDF to mask fabrication1444. Mask fabrication1444includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1445or a semiconductor wafer1453. The design layout diagram1422is manipulated by mask data preparation1432to comply with particular characteristics of the mask writer and/or requirements of IC fab1450. InFIG.14, mask data preparation1432and mask fabrication1444are illustrated as separate elements. In some embodiments, mask data preparation1432and mask fabrication1444can be collectively referred to as mask data preparation. In some embodiments, mask data preparation1432includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1422. In some embodiments, mask data preparation1432includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, mask data preparation1432includes a mask rule checker (MRC) that checks the IC design layout diagram1422that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1422to compensate for limitations during mask fabrication1444, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, mask data preparation1432includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1450to fabricate IC device1460. LPC simulates this processing based on IC design layout diagram1422to create a simulated manufactured device, such as IC device1460. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1422. It should be understood that the above description of mask data preparation1432has been simplified for the purposes of clarity. In some embodiments, data preparation1432includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1422according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1422during data preparation1432may be executed in a variety of different orders. After mask data preparation1432and during mask fabrication1444, a mask1445or a group of masks1445are fabricated based on the modified IC design layout diagram1422. In some embodiments, mask fabrication1444includes performing one or more lithographic exposures based on IC design layout diagram1422. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1445based on the modified IC design layout diagram1422. Mask1445can be formed in various technologies. In some embodiments, mask1445is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1445includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1445is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1445, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1444is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1453, in an etching process to form various etching regions in semiconductor wafer1453, and/or in other suitable processes. IC fab1450is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1450is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. IC fab1450includes fabrication tools1452configured to execute various manufacturing operations on semiconductor wafer1453such that IC device1460is fabricated in accordance with the mask(s), e.g., mask1445. In various embodiments, fabrication tools1452include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein. IC fab1450uses mask(s)1445fabricated by mask house1430to fabricate IC device1460. Thus, IC fab1450at least indirectly uses IC design layout diagram1422to fabricate IC device1460. In some embodiments, semiconductor wafer1453is fabricated by IC fab1450using mask(s)1445to form IC device1460. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1422. Semiconductor wafer1453includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1453further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Details regarding an integrated circuit (IC) manufacturing system (e.g., system1400ofFIG.14), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. In some embodiments, a method of forming a semiconductor device includes forming active regions including doping areas of a substrate; forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components; forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; and the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines resulting in: a first set of the first to fourth transistor-components connected as corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal, wherein the first time delay circuit further includes a first gate line intersecting a first-type active region and a second-type active region in a first area; and a second set of the first to fourth transistor-components connected as corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal, wherein the second time delay circuit further includes a second gate line intersecting the first-type active region and the second-type active region in a second area; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area. In some embodiments, the forming the active regions includes forming the first-type active region in the first area and the first-type active region in the second area between the second-type active region in the first area and the second-type active region in the second area. In some embodiments, the forming the gate lines includes forming all first gate lines in the first time delay circuit atop the first-type active region in the first area. In some embodiments, the forming the gate lines includes forming all the second gate line in the second time delay circuit atop the second-type active region in the second area. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in a third set of the first to fourth transistor-components connected as corresponding transistors that define a master-slave flip-flop having a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch and configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in a fourth set of the first to fourth transistor-components connected as corresponding transistors that define a third time delay circuit having a third input configured to receive the third clock signal and having a third output configured to generate a fourth clock signal from the third clock signal; and a fifth set of the first to fourth transistor-components connected as corresponding transistors that define a gated input circuit in the master-slave flip-flop configured to receive the third clock signal and the fourth clock signal to control an input transmission state of the gated input circuit. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in a third set of the first to fourth transistor-components connected as corresponding transistors that define a third gate line intersecting the first-type active region and the second-type active region in the first area, and wherein each of the first gate line and the third gate line is configured to receive the first clock signal. In some embodiments, a method of forming a semiconductor device includes forming active regions including doping areas of a substrate; forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components; forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; and the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines resulting in a first set of the first to fourth transistor-components connected as corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; a second set of the first to fourth transistor-components connected as corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the second clock signal; a third set of the first to fourth transistor-components connected as corresponding transistors that define a master-slave flip-flop that includes a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch, wherein the master latch is coupled between the gated input circuit and the transmission gate and configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. In some embodiments, the method of forming the semiconductor device further includes forming a first gate via-connector in direct contact with a first gate line included with the first time delay circuit, wherein the first gate line intersects a first-type active region and a second-type active region in a first area, and wherein at least a portion of the first gate via-connector is atop the first-type active region. In some embodiments, the method of forming the semiconductor device further includes forming a second gate via-connector in direct contact with a second gate line included with the second time delay circuit, wherein the second gate line intersects the first-type active region and the second-type active region in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in the first time delay circuit includes two gate lines, each of the two gate lines intersects the first-type active region and the second-type active region, and each of the two gate lines is configured to receive the first clock signal. In some embodiments, a method of forming a semiconductor device, including forming active regions including doping areas of a substrate; forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components; forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; and the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines resulting in a first set of the first to fourth transistor-components connected as corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal, wherein the first time delay circuit further includes a first gate line intersecting a first-type active region and a second-type active region in a first area; and a second set of the first to fourth transistor-components connected as corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal, wherein the second time delay circuit further includes a second gate line intersecting the first-type active region and the second-type active region in a second area. In some embodiments, the method of forming the semiconductor device further includes forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area. In some embodiments, the method of forming the semiconductor device further includes forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area. In some embodiments, the forming the active regions includes forming the first-type active region in the first area and the first-type active region in the second area between the second-type active region in the first area and the second-type active region in the second area. In some embodiments, the forming the gate lines includes forming a portion of the first gate line in the first time delay circuit atop the first-type active region in the first area. In some embodiments, the forming the gate lines includes forming all first gate lines in the first time delay circuit atop the first-type active region in the first area. In some embodiments, the forming the gate lines includes forming a portion of the second gate line in the second time delay circuit atop the second-type active region in the second area. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in a third set of the first to fourth transistor-components connected as corresponding transistors that define a master-slave flip-flop having a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch and configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. In some embodiments, the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in a fourth set of the first to fourth transistor-components connected as corresponding transistors that define a third time delay circuit having a third input configured to receive the third clock signal and having a third output configured to generate a fourth clock signal from the third clock signal; and a fifth set of the first to fourth transistor-components connected as corresponding transistors that define a gated input circuit in the master-slave flip-flop configured to receive the third clock signal and the fourth clock signal to control an input transmission state of the gated input circuit. It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof. | 86,380 |
11942946 | DETAILED DESCRIPTION Classical computers operate by storing information in the form of binary digits (“bits”) and processing those bits via binary logic gates. At any given time, each bit takes on only one of two discrete values: 0 (or “off”) and 1 (or “on”). The logical operations performed by the binary logic gates are defined by Boolean algebra and circuit behavior is governed by classical physics. In a modern classical system, the circuits for storing the bits and realizing the logical operations are usually made from electrical wires that can carry two different voltages, representing the 0 and 1 of the bit, and transistor-based logic gates that perform the Boolean logic operations. Shown inFIG.1Ais a simple example of a classical computer configured to a bit102and apply a single logic operation104to the bit102. At time t0the bit102is in a first state, at time t1the logic operation104is applied to the bit102, and at time t2the bit102is in a second state determined by the state at time t0and the logic operation. So, for example, the bit102may typically be stored as a voltage (e.g., 1 Vdc for a “1” or 0 Vdc for a “0”) which is applied to an input of the logic operation104(comprised of one or more transistors). The output of the logic gate is then either 1 Vdc or 0 Vdc, depending on the logic operation performed. Obviously, a classical computer with a single bit and single logic gate is of limited use, which is why modern classical computers with even modest computation power contain billions of bits and transistors. That is to say, classical computers that can solve increasingly complex problems inevitably require increasingly large numbers of bits and transistors and/or increasingly long amounts of time for carrying out the algorithms. There are, however, some problems which would require an infeasibly large number of transistors and/or infeasibly long amount of time to arrive at a solution. Such problems are referred to as intractable. Quantum computers operate by storing information in the form of quantum bits (“qubits”) and processing those qubits via quantum gates. Unlike a bit which can only be in one state (either 0 or 1) at any given time, a qubit can be in a superposition of the two states at the same time. More precisely, a quantum bit is a system whose state lives in a two dimensional Hilbert space and is therefore described as a linear combination α|0+β|1, where |0and |1are two basis states, and α and β are complex numbers, usually called probability amplitudes, which satisfy |α|2+|β|2=1. Using this notation, when the qubit is measured, it will be 0 with probability |α|2and will be 1 with probability |β|2. |0and |1can also be represented by two-dimensional basis vectors [1 0] and [0 1], respectively, and then the qubit state is represented by [α β]. The operations performed by the quantum gates are defined by linear algebra over Hilbert space and circuit behavior is governed by quantum physics. This extra richness in the mathematical behavior of qubits and the operations on them, enables quantum computers to solve some problems much faster than classical computers (in fact some problems that are intractable for classical computers may become trivial for quantum computers). Shown inFIG.1Bis a simple example of a quantum computer configured to store a qubit122and apply a single quantum gate operation124to the qubit122. At time t0the qubit122is described by α1|0)+β1|1, at time t1the logic operation124is applied to the qubit122, and at time t2the qubits122is described by α2|0+β2|1. Unlike a classical bit, a qubit cannot be stored as a single voltage value on a wire. Instead, a qubit is physically realized using a two-level quantum mechanical system. Many physical implementations of qubits have been proposed and developed over the years with some being more promising than others. Some examples of leading qubits implementations include superconducting circuits, spin qubits, and trapped ions. It is the job of the quantum controller to generate the precise series of external signals, usually pulses of electromagnetic waves and pulses of base band voltage, to perform the desired logic operations (and thus carry out the desired quantum algorithm). Example implementations of a quantum controller are described in further detail below. FIGS.2A-2Cillustrate example configurations of a quantum orchestration platform (QOP). The QOP comprises a quantum programming subsystem202, a quantum controller210, front-end circuitry254, multi-LO tone generator222, connectivity circuitry224, and a quantum processor218. The quantum programming subsystem202comprises circuitry operable to generate a pulse generation program and quantum machine specification206which configures the quantum controller210and includes instructions the quantum controller210can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control pulse(s)) with little or no human intervention during runtime. In an example implementation, the quantum programming system202is a personal computer comprising a processor, memory, and other associated circuitry (e.g., an x86 or x64 chipset) having installed on it a quantum orchestration software development kit (SDK) that enables creation (e.g., by a user via a text editor and/or by automated pulse program generation circuitry) of a high-level (as opposed to binary or “machine code”) pulse generation program. In an example implementation, the high-level pulse generation program and quantum machine specification use a high-level programming language (e.g., Python, R, Java, Matlab, etc.) simply as a “host” programming language in which are embedded the QOP programming constructs. The quantum machine specification and pulse generation program may be part of one or more larger databases and/or contained in one or more files (e.g., each may take the form of a plain-text file recognizable by an operating system such as Windows, Linux, Mac, or another OS) on which quantum programming subsystem runs. The quantum programming subsystem202then compiles the high-level pulse generation program and machine specification to machine code (i.e., series of binary vectors that represent instructions that the quantum controller's hardware can interpret and execute directly). The quantum programming subsystem202is coupled to the quantum controller210via any suitable wired, wireless, and/or optical link(s). The quantum controller210comprises circuitry operable to load the machine code from the programming subsystem202, and then execute the machine code to generate the necessary outbound quantum control pulse(s) that correspond to the desired operations to be performed on the quantum processor218(e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.) and/or process inbound pulses returning from the quantum processor218via front-end circuitry254. Depending on the pulse program being executed, whether to transmit one or more outbound pulse and/or characteristics of one or more outbound pulse to be transmitted may be predetermined at design time and/or may be determined during runtime. The runtime determination of the pulses may comprise performance of classical calculations and processing in the quantum controller210and/or the quantum programing subsystem202during runtime of the algorithm (e.g., runtime analysis of inbound pulses received from the quantum processor218via front-end circuitry254). During runtime of a pulse program and/or upon completion of a pulse program, the quantum controller210may output data/results to the quantum programming subsystem202. In an example implementation these results may be used to update the source and/or machine code of the pulse program and/or specification. The quantum controller210is coupled to front-end circuitry254via any suitable wired, wireless, and/or optical link(s). As shown inFIG.2B, the quantum controller210may comprise a plurality of interconnected, but physically separate quantum control modules250(e.g., each module being a separate IC, PCB, or desktop or rack mounted device) such that quantum control systems requiring relatively fewer resources can be realized with relatively fewer quantum control modules and quantum control systems requiring relatively more resources can be realized with relatively more quantum control modules. The number of quantum control modules250needed for a particular quantum system may be determined based on the number of qubits of the quantum processor218and their architecture (tunability, connectivity, coupling elements and readout architecture). In general, the quantum processor218comprises K (an integer) quantum elements122, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element(s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling outbound quantum control pulses from front-end circuitry254and inbound quantum control pulses to the front-end circuitry254. In the example shown, inFIG.2A, K=8 and the quantum processor218comprises 4 readout elements226and 4 qubits228. InFIG.2B, port(s)262represent RF output ports via which pulses are sent to qubits of the quantum processor (in the example ofFIG.2A,262corresponds to2251-2254). InFIG.2B, port(s)264represent RF output ports via which pulses are sent to readout elements of the quantum processor (in the example ofFIG.2A,266corresponds to227). InFIG.2B, port(s)266represent RF input ports via which pulses are received from the readout elements of the quantum processor (in the example ofFIG.2A,264corresponds to227). InFIG.2B, port(s)268represent IF input ports via which pulses to be sent to qubits of the quantum processor218are received from a controller module250(in the example ofFIG.2A,268corresponds to one or more of2210-2214). InFIG.2B, port(s)270represent IF input ports via which pulses to be sent to readout elements of the quantum processor218are received from a controller module250(in the example ofFIG.2A,268corresponds to one or more of2210-2214). InFIG.2B, port(s)272represent IF output ports via which pulses from readout elements are sent to controller module250(in the example ofFIG.2A,272corresponds to223). The front-end circuitry254is operable to receive outbound intermediate frequency (IF) pulses from quantum controller210via one or more ports221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports229, and output the RF pulses to quantum processor218via one or more output ports225. Each IF input port221is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse). In the latter case, the front-end circuitry254is operable to perform IQ upconversion. In the example shown, Five IF input ports2210-2214, five RF output ports2250-2254, one RF input port227, one IF output port217, and six LO input ports2290-2295were chosen merely as an example. Other implementations may have any number of RF, IF, and LO input ports and any number of RF and IF output ports. As shown inFIG.2B, the front-end circuitry254may comprise a plurality of interconnected, but physically separate front-end circuitry modules (e.g., each module being a separate IC, PCB, or desktop or rack mounted device) such that quantum control systems requiring relatively fewer resources can be realized with relatively fewer front-end circuitry modules and quantum control systems requiring relatively more resources can be realized with relatively more front-end circuitry modules. The number of front-end circuitry modules needed for a particular quantum system may be determined based on the number of qubits of the quantum processor218and their architecture (tunability, connectivity, preparation, trapping, coupling elements and readout architecture). In the example implementation shown inFIG.2D, the circuitry254comprises 6 IQ mixers270. Each of mixers2700-2704receives an IQ pair of IF signals via a respective one of ports2210-2214, and uses an LO signal received via a respective one of ports2290-2294to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports2250-2254. The mixer2705uses the LO received via port2295to downconvert the RF signal received via port227to generate the IF IQ pair output via port217. In an example implementation, the front-end circuitry254is configured manually and/or programmatically via digital control signals. For example, a signal259from the quantum programming subsystem202and/or a signal257from the quantum controller module250may open and close switching elements of the circuitry254, adjust gains within the circuitry254, adjust coefficients of filters within the circuitry254, and/or otherwise configure the RF, IF, and/or LO signal paths of circuitry254. The multi-tone generator222is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor218(e.g., based on the resonant frequencies of quantum elements of the quantum processor218). In an example implementation, two types of outputs are provided by quantum multi-tone generator222: (1) one or more fixed frequency continuous wave (CW) tones223; and (2) one or more synthesized frequency signals231. Each of the tone(s)223may be a single, fixed frequency tone with a power fixed at, for example, +23 dBm. Assuming a tolerable LO power of +14 to +20 dBm, this allows splitting a tone223into up to six LO signals using a suitable power splitting circuit, without any additional active RF components. For an implementation generating multiple tones223, the tones may be multiples of a single base tone fi. For example, in the implementation shown, there are eight tones with f0=500 MHz and thus the tones223range from 2.5 GHz to 6 GHz in steps of 500 MHz. This, together with the ability of the quantum controller210to accurately and dynamically control the frequencies of IF pulses it generates (see e.g.,FIGS.6A and6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations. Of course, different and/or other frequencies can be used to accommodate different qubit implementations. The synthesized signal or signals231output an adjustable frequency RF tone within a band of frequencies that contains, for example, the band 4 GHz to 8 GHz. This, together with the ability of the quantum controller210to accurately and dynamically control the frequencies of IF pulses it generates (see e.g.,FIGS.6A and6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies. Of course, different and/or other frequencies can be used to accommodate different qubit implementations. FIG.2Aprovides an illustrative example in which quantum processor218comprises four qubits228with no tunability, and four readout elements226(e.g., superconducting resonators) addressed by the same control line from port2250. In this case, the QOP requires only a single quantum controller module250, only a single front-end circuitry module with six mixers, and a single multi-tone generator222.FIG.2Bshows a more generalized QOP comprising multiple front-end modules254and multiple controller modules250. This illustrates the ability of a single instance of the multi-tone generator222to generate N (an integer) LO signals for driving a large number (e.g., 10 s or 100 s) of quantum elements with the use of appropriate RF signal distribution circuitry252and front-end circuitry254. The distribution circuitry252may comprise suitable transmission lines, amplifiers, filters, etc. The connectivity circuitry224is operable to couple the outputs of the multi-tone generator222to the inputs of the front-end circuitry254. The connectivity circuitry224can connect any one or more of the signals2230-2237and231to any one or more of the input ports2290-2295of front-end circuitry254. Because the desired connections between multi-tone generator222and quantum processor218depends on the architecture and operating frequencies of the quantum processor218, the connectivity circuitry224is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor218. The configuration may be controlled manually and/or programmatically. For example, the signal253from the quantum programming subsystem202and/or a signal255from the quantum controller module250may configure signal paths within circuitry224(e.g., by opening and closing switches, adjusting gains, adjusting filter coefficients, and/or the like).FIG.2Cshows an example of four such connectivity options. Examples 1, 2 and 3 are directly compatible with the setup inFIG.2A. In example 1, the 4.5 GHz signal is connected to LO input ports2293and2294, the 5 GHz signal is connected to LO input ports2291and2292, and the synthesized 4-8 GHz tone is connected to2290and2295. The 4.5 GHz signal received via ports2293and2294may be used to upconvert pulses to be sent to two qubits228having resonant frequencies in, for example, the 4.1 GHz to 4.9 GHz band. The 5 GHz signal received via ports2291and2292may be used to upconvert the pulses to be sent to two qubits228having resonant frequencies in the 4.6 GHz to 5.4 GHz band, for example. In example 2, the 4.5 GHz signal is connected to LO input ports2291-2294, and the synthesized 4-8 GHz tone is connected to2290and2295. The 4.5 GHz signal received via ports2291-2294may be used to upconvert pulses to be sent to four qubits having resonant frequencies in the 4.1 GHz to 4.9 GHz band. Example 3 shows using an attenuator to keep LO signal power below an upper limit when an LO drives only a single port229. In each of examples 1, 2, and 3, the 4-8 GHz synthesized signal may be used for upconversion of the readout element control signal that is output via port2250, and for downconversion of the readout element return signal received via port227. Example 4 shows driving all 6 LO ports229of the front end circuit220with a single fixed frequency source. The reference generator circuit219provides a reference signal that the multi-tone generator222splits, frequency multiplies, amplifies and filters to generate signals2230-2237and231. In an example implementation, the low-phase-noise reference generator219is an oven-controlled crystal oscillator (OCXO) or other low-phase-noise reference generator219. In general, the spacing of frequency-adjacent ones of the signals223(e.g., assuming increasing frequency from223to2237, the spacing between2230and2231, between2231and2232, and so on) is based on the tuning range of the quantum controller module250. In the example above, the quantum controller module250is assumed capable of tuning the IF pulses over a bandwidth of 500 MHz, thus spacing of 500 MHz or less between frequency adjacent ones of the signals2230-2237enables outputting a pulse at any frequency 500 MHz below the frequency of2230to the frequency of2237plus 500 MHz. As another example, where the quantum controller module250is operable to tune the IF over 1 GHz then frequency adjacent ones of the signals2230-2237may be separated by up to 1 GHz. FIG.3shows an example implementation of the quantum controller210. The example quantum controller shown comprises pullers3021-302L-1(L an integer ≥1), receive analog frontend350, input manager352, digital manager354, pulse operations manager356, pulse operations358, output manager360, transmit analog frontend362, data exchange364, synchronization manager366, and input/output (“I/O”) manager368. The receive analog frontend350comprises circuitry operable to concurrently process up to M (an integer ≥1) analog inbound signals (RP′0-RP′M-1) from one or more outputs of front end circuitry220to generate up to M concurrent inbound signals (RP0-RPM-1) to be output to input manager352via one or more signal paths. Although there is shown to be M signals RP and M signals RP′, this need not be the case. Such processing may comprise, for example, analog-to-digital conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing, and/or the like. In various implementations, M may be less than, equal to, or greater than L and M may be less than, equal to, or greater than K. The input manager352comprises circuitry operable to route any one or more of signals (RP0-RPM-1) to any one or more of pulsers3020-302L-1(as signal(s) Al0-AlL-1) and/or to other circuits (e.g. as signal io_mgr to I/O manager368). In an example implementation, the input manager352comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which signals RP0-RPM-1are routed to which pulsers3020-302L-1. This may enable time division multiplexing multiple of the signals RP0-RPM-1onto a single signal Alland/or time division demultiplexing components (e.g., time slices) of a signal RPmonto multiple of the signals Al0-AlL-1. In an example implementation, the input manager352comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals RP0-RPM-1onto a single signal Alland/or frequency division demultiplexing components (e.g., frequency bands) of a signal RPm, onto multiple of the signals Al0-AlL-1. The signal routing and multiplexing/demultiplexing functions performed by the input manager352enables: a particular pulser302lto process different inbound pulses from different quantum elements at different times; a particular pulser302lto process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers3020-302L-1to processes the same inbound pulse at the same time. In the example implementation shown, routing of the signals RP0-RPM-1among the inputs of the pulsers3020-302L-1is controlled by digital control signals in_slct0-in_slctL-1from the pulsers3020-302L-1. In another implementation, the input manager may be operable to autonomously determine the appropriate routing (e.g., where the pulse generation program and quantum machine specification206includes instructions to be loaded into memory of, and executed by, the input manager352). In the example implementation, the input manager352is operable to route input signals RP0-RPM-1to the I/O manager368(as signal(s) io_mgr), to be sent to the quantum programming subsystem202. This routing may, for example, be controlled by signals from the digital manager354. In an example implementation, for each input signal RPmthere is a digital signal, streamm, from the digital manager354to the input manager352that controls whether RPmwill be sent from the input manager352to the I/O manager368and from there to the quantum programing subsystem202. Each pulser circuit302l(l between 0 and L−1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor218. This involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses. The outbound pulses may be, for example, control pulses sent to the quantum processor218to manipulate one or more properties of one or more quantum elements—e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements. The characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor218via frontend circuitry220at a prior time. In an example implementation, the time required to close the feedback loop (i.e., time from receiving a first pulse on an output217of front-end circuitry254to sending a second pulse (e.g., at an input221of front-end circuitry254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor218. For example, the time to close the feedback loop may be on the order of 100 nanoseconds. In the example implementation shown, each pulser302lis operable to generate raw outbound pulses CP′l(“raw” is used simply to denote that the pulse has not yet been processed by pulse operations circuitry358) and digital control signals in_slctl, D_portl, Dl, out_slctl, ops_ctrll, ops_slctl, IFl, Fl, and dmod_scltlfor carrying out quantum algorithms on the quantum processor218, and results' for carrying intermediate and/or final results generated by the pulser302lto the quantum programming subsystem202. One or more of the pulsers3020-302L-1may receive and/or generate additional signals which are not shown inFIG.3for clarity of illustration. Each of the pulsers302lis operable to receive inbound pulse signal Alland signal f_dmodl. Pulser302lmay process the inbound signal Allto determine the state of certain quantum element(s) in the quantum processor218and use this state information for making decisions such as, for example, which raw outbound pulse CP′lto generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately. Pulser302lmay use the signal f_dmodlfor determining how to process inbound pulse signal All. As an example, when pulser3021needs to process an inbound signal Al1from quantum element1223, it can send a dmod_sclt1signal that directs pulse operations manager356to send, on f_dmod1, settings to be used for demodulation of an inbound signal Al1from quantum element1223(e.g., the pulse operations manager356may send the value cos(ω3*TS*Tclk1+ϕ3), where ω3is the frequency of quantum element1223, TS is amount of time passed since the reference point, for instance the time at which a pulse program started running, and ϕ3is the phase of the total frame rotation of quantum element1223, i.e. the accumulated phase of all frame rotations since the reference point). The pulse operations circuitry358is operable to process the raw outbound pulses CP′0-CP′L-1to generate corresponding output outbound pulses CP0-CPL-1. This may comprise, for example, manipulating the amplitude, phase, and/or frequency of the raw pulse CP′l. The pulse operations circuitry358receives raw outbound pulses CP′0-CP′L-1from pulsers3020-302L-1, control signals ops_cnfgo-ops_cnfgL-1from pulse operations manager356, and ops_ctrl0-ops_ctrlL-1from pulsers3020-302L-1. The control signal ops_cnfglconfigures, at least in part, the pulse operations circuitry358such that each raw outbound pulse CP′lthat passes through the pulse operations circuitry358has performed on it one or more operation(s) tailored for that particular pulse. To illustrate, denoting a raw outbound pulse from pulser3023at time T1as CP′3,T1, then, at time T1(or sometime before T1to allow for latency, circuit setup, etc.), the digital control signal ops_cnfg3(denoted ops_cnfg3,T1for purposes of this example) provides the information (e.g., in the form of one or more matrix, as described below) as to what specific operations are to be performed on pulse CP′3,T1. Similarly, ops_cnfg4,T1provides the information as to what specific operations are to be performed on pulse CP′4,T1, and ops_cnfg3,T2provides the information as to what specific operations are to be performed on pulse CP′3,T2. The control signal ops_ctrllprovides another way for the pulser302lto configure how any particular pulse is processed in the pulse operations circuitry358. This may enable the pulser302lto, for example, provide information to the pulse operation circuitry358that does not need to pass through the pulse operation manager356. For example, the pulser302lmay send matrix values calculated in real-time by the pulser302lto be used by the pulse operation circuitry358to modify pulse CP′l. These matrix values arrive to the pulse operation circuitry358directly from the pulser302land do not need to be sent to the pulse operation manager first. Another example may be that the pulser302lprovides information to the pulse operation circuitry358to affect the operations themselves (e.g. the signal ops_ctrllcan choose among several different mathematical operations that can be performed on the pulse). The pulse operations manager356comprises circuitry operable to configure the pulse operations circuitry358such that the pulse operations applied to each raw outbound pulse CP′lare tailored to that particular raw outbound pulse. To illustrate, denoting a first raw outbound pulse to be output during a first time interval T1as CP′l,T1, and a second raw outbound pulse to be output during a second time interval T2as CP′l,T2, then pulse operations circuitry358is operable to perform a first one or more operations on CP′l,T1and a second one or more operations on CP′1,T2. The first one or more operations may be determined, at least in part, based on to which quantum element the pulse CP1,T1is to be sent, and the second one or more operations may be determined, at least in part, based on to which quantum element the pulse CP1,T2is to be sent. The determination of the first one or more operations and second one or more operations may be performed dynamically during runtime. The transmit analog frontend362comprises circuitry operable to concurrently process up to K digital signals DOkto generate up to K concurrent analog signals AOkto be output to inputs221of the front-end circuitry254. Such processing may comprise, for example, digital-to-analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like. Although there is one-to-one correspondence between the number of DO signals and the number of AO signals in the example implementation described here, such does not need to be the case. In another example implementation, the analog frontend362is operable to map more (or fewer) signals DO to fewer (or more) signals AO. In an example implementation the transmit analog frontend362is operable to process digital signals DO0-DOK-1as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1as independent outbound pulses and some signals DO0-DOK-1as two-pulse pairs (at different times and/or concurrently. The output manager360comprises circuitry operable to route any one or more of signals CP0-CPL-1to any one or more input ports221of the front-end circuitry254. In an example implementation, the output manager360comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which one or more signals CP0-CPL-1are routed to which input port(s)221of the front-end220. This may enable time division multiplexing multiple of the signals CP0-CPL-1onto a single input port221of the front-end circuit220and/or time division demultiplexing components (e.g., time slices) of a signal CPmonto multiple of the input ports221of the front-end circuitry254. In an example implementation, the output manager360comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM-1onto a single input port221of front-end circuitry254and/or frequency division demultiplexing components (e.g., frequency bands) of a signal CPmonto multiple of the input ports221of the front-end circuitry254. The signal routing and multiplexing/demultiplexing functions performed by the output manager360enables: routing outbound pulses from a particular pulser302lto different ones input ports221at different times; routing outbound pulses from a particular pulser302lto multiple of the input ports221at the same time; and multiple of the pulsers3020-302L-1generating pulses for the same input port221at the same time. In the example implementation shown, routing of the signals CP0-CPL-1among the input ports221is controlled by digital control signals out_slct0-out_slctL-1from the pulsers3020-302L-1. In another implementation, the output manager360may be operable to autonomously determine the appropriate routing (e.g., where the pulse generation program and quantum machine specification206includes instructions to be loaded into memory of, and executed by, the output manager360). In an example implementation, at any given time, the output manager360is operable to concurrently route K of the digital signals CP0-CPL-1as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1as two-pulse pairs, or route some of signals CP0-CPL-1as independent outbound pulses and some others of the signals CP0-CPL-1as multi-pulse sets (at different times and/or concurrently). The digital manager354comprises circuitry operable to process and/or route digital control signals (DigCtrl0-DigCtrlJ-1) to various circuits of the quantum controller210and/or external circuits coupled to the quantum controller210. In the example implementation shown, the digital manager receives, from each pulser302l, a digital signal Dlthat is to be processed and routed by the digital manager354, and a control signal D_portlthat indicates to which output port(s) of the digital manager354the signal Dlshould be routed. The digital control signals may be routed to, for example: any one or more of circuits shown inFIG.3; switches/gates which connect and disconnect the outputs AO0-AOK-1from the front-end circuitry254and/or connect and disconnect output ports225of the front-end circuitry254from the quantum processor218; and/or any other circuitry which can benefit from real-time information from the pulser circuits3020-302L-1. Each such destination of the digital signals may require different operations to be performed on the digital signal (such as delay, broadening, or digital convolution with a given digital pattern). These operations may be performed by the digital manager354and may be specified by control signals from the pulsers3020-302L-1. This allows each pulser302lto generate digital signals to different destinations and allows different ones of pulsers3020-302L-1to generate digital signals to the same destination while saving resources. The synchronization manager366comprises circuitry operable to manage synchronization of the various circuits shown inFIG.3. Such synchronization is advantageous in a modular and dynamic system, such as quantum controller210, where different ones of pulsers3020-302L-1generate, receive, and process pulses to and from different quantum elements at different times. For example, a pulse generation program may require that a first pulser circuit3021and a second pulser circuit3022sometimes need to transmit pulses at precisely the same time, and at other times transmit pulses independently of one another. In the example implementation shown, the synchronization manager366reduces the overhead involved in performing such synchronization. The data exchange circuitry364is operable to manage exchange of data among the various circuits shown inFIG.3. For example, a pulse generation program may require a first pulser circuit3021and a second pulser circuit3022to sometimes exchange information. As just one example, pulser3021may need to share, with pulser3022, the characteristics of an inbound signal Al1that it just processed so that pulser3022can generate a raw outbound pulse CP′2based on the characteristics of Al1. The data exchange circuitry364may enable such information exchange. In an example implementation, the data exchange circuitry364may comprise one or more registers to and from which the pulsers3020-302L-1can read and write. The I/O manager368is operable to route information between the quantum controller210and the quantum programming subsystem202. Machine code quantum pulse program descriptions may be received via the I/O manager368. Accordingly, the I/O manager368may comprise circuitry for loading the machine code into the necessary registers/memory (including any SRAM, DRAM, FPGA BRAM, flash memory, programmable read only memory, etc.) of the quantum controller210as well as for reading contents of the registers/memory of the quantum controller210and conveying the contents to the quantum programming subsystem202. The I/O manager368may, for example, include a PCIe controller, AXI controller/interconnect, and/or the like. In an example implementation, the I/O manager368comprises one or more registers380which can be written to and read from via a quantum machine API and via reserved variables in the language used to create pulse generation program and quantum machine specification206. FIG.4shows an example implementation of the pulser ofFIG.3. The example pulser302lshown comprises instruction memory402, pulse template memory404, digital pattern memory406, control circuitry408, and compute and/or signal processing circuitry (CSP)410. The memories402,404,406may comprise one or more be any type of suitable storage elements (e.g., DRAM, SRAM, Flash, etc.). The instructions stored in memory402are instructions to be executed out by the pulser302lfor carrying out a pulse generation program. Because different pulsers3020-302L-1have different roles to play in any particular pulse generation program (e.g., generating different pulses at different times), the instructions memory402for each pulser302lmay be specific to that pulser. For example, the pulse generation program from the quantum programming subsystem202may comprise a first set of instructions to be loaded (via I/O manager368) into pulser3020, a second set of instructions to be loaded into pulser3021, and so on. Each pulse template stored in memory404comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sinc, impulse, etc.) representing the pulses to be sent to pulse operation circuitry358. Each digital pattern stored in memory406comprises a sequence of one or more binary values which may represent the digital pulses to be sent to the digital manager354for generating digital control signals DigCtrl0-DigCtrlJ-1. The control circuitry408is operable to execute the instructions stored in memory402to process inbound signal All, generate raw outbound pulses CP′l, and generate digital control signals in_slctl, out_slctl, D_portl, Dl, IFl, Fl, ops_slctl, ops_ctrll, resultsl, dmod_slctland pairl. In the example implementation shown, the processing of the inbound signal Allis performed by the CSP circuitry410and based (at least in part) on the signal f_dmodl. The compute and/or signal processing circuitry (CSP)410is operable to perform computational and/or signal processing functions, which may comprise, for example Boolean-algebra based logic and arithmetic functions and demodulation (e.g., of inbound signals All). The CSP410may comprise memory in which are stored instructions for performing the functions and demodulation. The instructions may be specific to a particular pulse generation program and be generated during compilation of the program. In operation of an example implementation, generation of a raw outbound pulse CP′lcomprises the control circuitry408: (1) determining a pulse template to retrieve from memory404(e.g., based on a result of computations and/or signal processing performed by the CSP410); (2) retrieving the pulse template; (3) performing some preliminary processing on the pulse template; (4) determining the values of F, IF, painl, ops_slctl, and dmod_slctlto be sent to the pulse operation manager356(as predetermined in pulse generation program and quantum machine specification206and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (5) determining the value of ops_ctrllto be sent to the pulse operation circuitry358; (6) determining the value of in_slctlto be sent to the input manager352; (7) determining a digital pattern to retrieve from memory406(as predetermined in the pulse generation program and quantum machine specification206and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (8) outputting the digital pattern as Dlto the digital manager along with control signal D_portl(as predetermined in the pulse program description and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (9) outputting the raw outbound pulse CP′lto the pulse operations circuitry358; (10) outputting resultslto the I/O manager. FIG.5shows an example implementation of the pulse operations manager and pulse operations circuitry ofFIG.3. The pulse operations circuitry358comprises a plurality of pulse modification circuits5080-508R-1(R is an integer ≥1 in general, and R=L/2 in the example shown). The pulse operations manager356comprises control circuitry502, routing circuitry506, and a plurality of modification settings circuits5040-504K-1. Although the example implementation has a 1-to-2 correspondence between pulse modification circuits5080-508R-1and pulser circuits3020-302L-1, such does not need to be the case. In other implementations there may be fewer pulse modification circuits508than pulser circuits302. Similarly, other implementations may comprise more pulse modification circuits508than pulser circuits302. As an example, in some instances, two of the pullers3020-302L-1may generate two raw outbound pulses which are a phase-quadrature pulse pair. For example, assuming CP1and CP2are a phase-quadrature pulse pair to be output. In this example, pulse operations circuitry358may process CP1and CP2by multiplying a vector representation of CP′1and CP′2by one or more 2 by 2 matrices to: (1) perform single-sideband-modulation, as given by (CP1CP2)=(cos(ω*TS*Tclck1)−sin(ω*TS*Tclck1)sin(ω*TS*Tclck1) cos(ω*TS*Tclck1))(CP′1CP′2), where co is the frequency of the single sideband modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (2) keep track of frame-of-reference rotations, as given by (CP1CP2)=(cos(ϕ)−sin(ϕ) sin(ϕ) cos(ϕ))(CP′1CP′2), where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (3) perform an IQ-mixer correction (CP1CP2)=(C00C01C10C11)(CP′1CP′2), where C00, C01, C10, and C11are the elements of a matrix that corrects for IQ-mixer imperfections. In an example implementation, each modification settings circuit,504k, contains registers that contain the matrix elements of three matrices: Ck=(Ck00Ck01Ck10Ck11), an IQ-mixer correction matrix; Sk=(cos(ωk*TS*Tclck1)−sin(ωk*TS)*Tclck1sin(ωk*TS*Tclck1) cos(ωk*TS*Tclck1)), a single sideband frequency modulation matrix; and Fk=(cos(ϕk)−sin(ϕk) sin(ϕk) cos(ϕk)), a frame rotation matrix, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis). In an example implementation, each modification settings circuit504kalso contains registers that contain the elements of the matrix products CkSkFkand SkFk. In the example shown, each pulse modification circuit508ris operable to process two raw outbound pulses CP′2rand CP′2r+1according to: the modification settings ops_cnfg2rand ops_cnfg2r+1; the signals ops_ctrl2rand ops_ctrl2r+1; and the signals pair2rand pair2r+1. In an example implementation pair2rand pair2r+1may be communicated as ops_ctrl2rand ops_ctrl2r+1. The result of the processing is outbound pulses CP2rand CP2r+1. Such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP′2rand CP′2r+1. In an example implementation, ops_cnfg2rand ops_cnfg2r+1are in the form of a matrix comprising real and/or complex numbers and the processing comprises matrix multiplication involving a matrix representation of the raw outbound pulses CP2rand CP2r+1and the ops_cnfg2rand ops_cnfg2r+1matrix. The control circuitry502is operable to exchange information with the puller circuits3020-302L-1to generate values of ops_confg0-ops_confgL-1and f_demod0-f_demodL-1, to control routing circuitry506based on signals ops_slct0-ops_slctL-1and dmod_slct0-dmod_slctL-1, and to update pulse modification settings5040-504K-1based on IF0-IFL-1and F0-FL-1such that pulse modification settings output to pulse operations circuitry358are specifically tailored to each raw outbound pulse (e.g., to which quantum element226or228the pulse is destined, to which input port221of front-end circuitry254the pulse is destined, etc.) to be processed by pulse operations circuitry358. Each modification settings circuit504kcomprises circuitry operable to store modification settings for later retrieval and communication to the pulse operations circuitry358. The modification settings stored in each modification settings circuit504kmay be in the form of one or more two-dimensional complex-valued matrices. Each path a pulse may travel to the quantum processor218via front-end circuitry254may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations. Similarly, each quantum element1220-122kmay have a particular characteristics (e.g. resonance frequency, frame of reference, etc.). In an example implementation, the number of pulse modification settings, K, stored in the circuits504corresponds to the number of signal paths, such that each of the modification settings circuits5040-504K-1stores modification settings for a respective one of the paths. In other implementations, there may be more or fewer pulse modification circuits504than signal paths and more or fewer pulse modification circuits504than quantum elements122and more or fewer signal paths than quantum elements122. The control circuitry502may load values into the modification settings circuit5040-504K-1via signal503. The routing circuitry506is operable to route modification settings from the modification settings circuits5040-504L-1to the pulse operations circuit358(as ops_confg0-ops_confgL-1) and to the pulsers3020-302L-1(as f_dmod0-f_dmodL-1). In the example implementation shown, which of the modification settings circuits5040-504K-1has its/their contents sent to which of the pulse modification circuits5080-508R-1and to which of the pulsers3020-302L-1is controlled by the signal505from the control circuitry502. The signal ops_slctlinforms the pulse operations manager356as to which modification settings504kto send to the pulse modification circuit508l. The pulser302lmay determine ops_slctlbased on the particular quantum element122kand/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction). The determination of which quantum element and/or signal path to which a particular pulser302lis to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification206or may be determined based on calculations performed by the pulser302land/or others of the pulsers3020-302L-1during runtime. The control circuitry502may then use this information to configure the routing block506such that the correct modification settings are routed to the correct one or more of the pulse modification circuits5080-508L-1. In an example implementation, the digital signal IFlinstructs the pulse operations manager356to update a frequency setting of the modification settings circuit504kindicated by ops_slctl. In an example implementation, the frequency setting is the matrix Sk(described above) and the signal IFlcarries new values indicating the new ωkto be used in the elements of the matrix Sk. The new values may, for example, be determined during a calibration routine (e.g., performed as an initial portion of the pulse generation program) in which one or more of the pulsers3020-302L-1sends a series of outbound pulses CP, each at a different carrier frequency, and then measures the corresponding inbound signals Al. In an example implementation, the signal Flinstructs the pulse operations manager356to update a frame setting of the modification settings circuit504kindicated by ops_slctl. In an example implementation, the frame setting is the matrix Fk(described above) and the signal Flcarries a rotation matrix Fi which multiplies with Fkto rotate Fk. This can be written as Fk=FlFk=(cos(Δϕ)−sin(Δϕ) sin(Δϕ) cos(Δϕ))(cos(ϕk)−sin(ϕk) sin(ϕk) cos(ϕk))=(cos(ϕk+Δϕ)−sin(ϕk+Δϕ)sin(ϕk+Δϕ)cos(ϕk+Δϕ)), where ϕkis the frame of reference before the rotation and Δϕ is the amount by which to rotate the frame of reference. The pulser302lmay determine Δϕ based on a predetermined algorithm or based on calculations performed by the pulsers302land/or others of the pulsers3020-302L-1during runtime. In an example implementation, the signal dmod_scltlinforms the pulse operations manager356from which of the modification settings circuits504kto retrieve values to be sent to pulser302las f_dmodl. The pulser302lmay determine dmod_slctlbased on the particular quantum element122kand/or signal path from which the pulse to be processed arrived. The determination of from which quantum element and/or signal path a particular pulser302lis to process an inbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification206or may be determined based on calculations performed by the pulser302land/or others of the pulsers3020-302L-1during runtime. The control circuitry502may then use this information to configure the routing block506such that the correct modification settings are routed to the correct one of the pulsers3020-302L-1. For example, when pulse generation circuit302lneeds to demodulate a pulse signal Allfrom quantum element122k, it will send a dmod_scltlsignal instructing the pulse operation manager356to rout the element SFk00=cos(ωk*time_stamp+ϕk) from modification settings circuit504kto puller302l(as f_dmodl). In the example implementation shown, the digital signals C0-CK-1provide information about signal-path-specific modification settings to be used for each of the signal paths to the quantum processor218. For example, each signal Ckmay comprise a matrix to be multiplied by a matrix representation of a raw outbound pulse CP′lsuch that the resulting output outbound pulse is pre-compensated for errors (e.g., resulting from imperfections in mixers, amplifiers, wiring, etc.) introduced as the outbound pulse propagates along the signal path. The result of the pre-compensation is that output outbound pulse CPlwill have the proper characteristics upon arriving at the quantum processor218. The signals C0-CK-1may, for example, be calculated by the quantum controller210itself, by the programming subsystem202, and/or by external calibration equipment and provided via I/O manager368. The calculation of signals may be done as part of a calibration routine which may be performed before execution of a pulse generation program and/or may be determined/adapted in real-time as part of a pulse generation program (e.g., to compensate for temperature changes during runtime of the pulse generation program). FIG.6Ashows frequency generation circuitry of the quantum controller ofFIG.3. In the example implementation shown, the frequency generation circuitry is part of control circuitry502of pulse operations manager circuitry356. The frequency generation circuitry comprises K coordinate rotation digital computer (CORDIC) circuits6020-604K-1, phase generation circuitry604, timestamp register606, and S-Matrix generation circuitry608. Each CORDIC circuit602kis operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk). The phase generation circuitry604is operable to generate the CORDIC input parameters θ0-θk-1based on: (1) the frequency setting signals IF0-IFL-1from the pullers3020-302L-1; and (2) the contents, TS, of the timestamp register606. The timestamp register606comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1since a reference point in time (e.g., power up of the quantum controller210, start of execution of set of instructions of a pulse generation program by the quantum controller210, etc.). In the example shown, the phase generation circuitry604sets θ0=2πf0(TS)(dtclk1), where f0is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1is the duration of a single clock cycle of clk1. This leads to the CORDIC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0rotation matrix that rotates at a frequency f0. As shown inFIG.6B, the signal IFlmay comprise an update component and an flcomponent. In an example implementation, when updatelis asserted then the phase generation circuitry updates one of more of f0-fK-1to be the value of fl. The S-matrix generation circuitry608is operable to build the matrices S0-SK-1from the outputs of the CORDIC circuits6020-602K-1. In an example implementation, the S-matrix generation circuit608is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1(which may be determined by the control information IF0-IFL-1). With K CORDIC circuits602k, the frequency generation circuitry is operable to concurrently generate K S-matrices. In instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit604is operable to change the input parameter θkof one or more of the CORDIC circuits6020-602K-1to stop generating one frequency and start generating the K+1thfrequency. In some instances, it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point). In some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in. The phase generation circuit604and timestamp register606enable both of these possibilities. FIG.7shows an example implementation of the digital manager ofFIG.3. Shown inFIG.7are the digital manager376, controlled circuits7100-710J-1, and input manager372. The example implementation of the digital manager376comprises input routing circuit702, configuration circuit704, output routing circuit706, processing paths7080-708Z-1(where Z is an integer), and routing control circuit712. The configuration circuit704is operable to store configuration settings and use those settings to configure the processing paths7080-708Z-1and/or the routing control circuit712. The settings may, for example, be loaded via the signal DM_config as part of the pulse generation program and quantum machine specification206provided by quantum programming subsystem202. The settings may comprise, for example, one or more of: a bitmap on which may be based a determination of which of signals D0-DL-1to route to which of signals P′0-P′Z-1for one or more instructions of a pulse program; a bitmap on which may be based a determination of which processing path outputs P0-PZ-1to route to which of DigOut0-DigOutJ+M-1for one or more instructions of a pulse program; and one or more bit patterns which processing paths7080-708Z-1may convolve with one or more of the signals P′0-P′Z-lfor one or more instructions of a pulse program. The input routing circuit702is operable to route each of the digital signals D0-DL-1to one or more of the processing paths7080-708Z-1. At any given time (e.g., for any particular instruction of every puller302lof pullers3020-302L), the input routing circuit702may determine to which of the processing paths7080-708Z-1to rout the signal Dlof signals D0-DL-1based on the signal faninlof signals fanin0-faninL-1. That is, for a particular instruction, the digital signal Dlmay be routed to any one or more of paths7080-708Z-1based on the value of faninlfor that instruction. For example, faninlmay be a Z-bit signal and a state of each bit of faninlduring a particular instruction may indicate whether Dlis to be routed to a corresponding one of the Z processing paths7080-708Z-1during that instruction. An example implementation of the input routing circuit702is described below with reference toFIG.8. The output routing circuit706is operable to route each of the digital signals P0-PZ-1to one or more of DigOut0-DigOutJ+M-1(In the example shown DigOut0-DigOutJ+M-1connect to stream0-streamM-1, respectively, and DigOutM-DigOutJ+M-1connect to DigCtrl0-DigCtrlJ-1, respectively). At any given time (e.g., for any particular instruction of every puller302lof pulsers3020-302L), the output routing circuit706may determine to which of DigOut0-DigOutJ+M-1to rout the signal Pi of the signals P0-PL-1based on the signal fanoutlof signals fanout0-fanoutZ-1. That is, for a particular instruction, the digital signal Pz(z an integer between 0 and Z) may be routed to any one or more of DigOut0-DigOutJ+M-1based on the value of fanoutzfor that instruction. For example, values of fanoutzmay be (J+M-1) bits and a state of each bit of fanoutzduring a particular instruction may indicate whether Pzis to be routed to a corresponding one of the J+M-1 signals DigOut during that instruction. An example implementation of the output routing circuit706is described below with reference toFIG.8. Each of the processing path circuits7080-708Z-1is operable to manipulate a respective one of signals P′0-P′Z-1to generate a corresponding manipulated signal P0-PZ-1. The manipulation may comprise, for example, introducing a delay to the signal such that the resulting one or more of DigOut0-DigOutJ+M-1reach(es) its/their destination (a controlled circuit710and/or input manager372) at the proper time with respect to the time of arrival of a corresponding quantum control pulse at the corresponding destination. Each of the controlled circuits7100-710J-1and input manager372is a circuit which, at least some of the time, needs to operate synchronously with quantum control pulses generated by one or more of pulsers3020-302L-1(possibly a reflection/return pulse from a quantum processor in the case of input manager372). Accordingly, each of the control circuits7100-710J-1receives a respective one of control signals DigOut0-DigCtrlJ-1that is synchronized with a respective quantum control pulse. Similarly, input manager372receives a plurality of the DigOut signals (one for each stream input). The routing controller712comprises circuitry operable to generate signals fanin0-faninL-1and fanout0-fanoutZ-1based on D_path0-D_pathL-1, D_port0-D_portL-1, and/or information stored in configuration circuit704. FIG.8shows an example implementation of the digital manager ofFIG.3. The example input routing circuit702comprises routing circuits8020-802L-1and combining circuits8040-804L-1. The example output routing circuitry506comprises circuits routing circuits8080-808Z-1and combining circuits8100-810J-1. The example processing path circuits are convolution circuits8060-806Z-1. Each of the routing circuits8020-802Lis operable to route a respective one of signals D0-DL-1to one or more of the combining circuits8040-804Z-1. To which of combining circuit(s)8040-804Z-1the signal Dlis routed is determined based on the signal faninl. In an example implementation, each signal faninlis a Z-bits signal and, for a pulserlinstruction, the value of bit z of the signal faninldetermines whether the signal Dlis to be routed to combining circuit804zfor that instruction. The value of faninlmay be updated on a per-instruction basis. Each of combining circuits8040-804L-1is operable to combine up to L of the signals D0-DL−1 to generate a corresponding one of signals P0-PZ-1. In an example implementation, the combining comprises OR-ing together the values of the up to L signals. Each of the routing circuits8080-808Z-1is operable to route a respective one of signals P′0-P′Z-1to one or more of the combining circuits8100-810J-1. To which of combining circuit(s)8100-810J-1the signal P′Zis routed is determined based on the signal fanoutz. In an example implementation, each signal fanoutzis a (J+M-1)-bit signal and the value of bit j+m−1 of the signal fanoutzdetermines whether the signal P′Zis to be routed to combining circuit804j+m-1. In an example implementation the value of fanoutzis preconfigured before the runtime of the pulse program, however, in another implementation it may be updated dynamically (e.g., on a per-instruction basis). Each combining circuit of combining circuits8100-810J-1is operable to combine up to Z of the signals P′0-P′Z-1(received via inputs8030to803Z-1) to generate a corresponding one of signals DigOut0-DigOutJ+M-1. In an example implementation, the combining comprises OR-ing together the values of the up to Z signals. Each convolution circuit806zis operable to convolve signal Pzwith patternzto generate signal P′z. In an example implementation, patternzis preconfigured before runtime of the pulse program, however, in another implementation it may be updated dynamically. patternzmay be determined based on: the destination(s) of signal Pz(e.g., to which of controlled circuits510and/or input of input manager352Pz is intended); characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations. FIG.9Aillustrates configuration and control of the quantum controller via the quantum programming subsystem. InFIG.9A, the quantum controller210comprises one or more instances of various circuits (such as the puller, input manager, output manager, digital manager, pulse operations manager, and analog front end circuits described above). Connected to the inputs and outputs of the quantum controller210may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements. As described in further detail below, these physical circuits can be allocated and deallocated independently of one another such that the physical resources of the quantum controller210, and the quantum elements and external devices connected to the quantum controller210via the analog and digital inputs and outputs, can be organized into one or more “quantum machines.” Also shown inFIG.9Aare a compiler906and quantum machines manager908of the quantum programming subsystem202. The compiler906comprises circuitry operable to generate quantum controller machine code based on: (1) a specification902; (2) a pulse generation program904; and (3) a resources management data structure from the quantum machines manager908. Referring toFIG.9B, an example implementation of the compiler906comprises analyzer circuitry952and synthesizer circuitry954. The analyzer circuitry952is operable to parse the specification902and program904to generate an intermediate code representation (e.g., a parse tree). The synthesizer circuitry954is operable to generate machine code based on the intermediate code representation and the available resources indicated by the quantum machines manager908. The specification902identifies resources of a quantum machine some of which are mapped to physical circuits during an instantiation of a quantum machines (e.g. input and output ports of the quantum controller210), and some of which the compiler attaches to physical circuits of the quantum controller210during compilation of a Pulse generation Program904. The compiler906may allocate resources for executing the program904based on the specification902, the program904, and/or the available resources indicated by the quantum machines manager908. As an example, assume a scenario in which there are five quantum elements in the specification902and the program904uses only two of the quantum elements; the number of the pulsers3020-302Lallocated may depend on the available resources and the specifics of the program904. In one case the compiler906may allocate a first number (e.g., two) of the pulsers3020-302Lfor interfacing with the two quantum elements and in another case the compiler may allocate a second number (e.g., four) for sending pulses to the two quantum elements. In an example implementation, Python is used as a “host” language for the specification and the specification is a Python dictionary. In this example implementation the Python syntax/constructs can thus be leveraged to create the specification (Python variables, functions, etc.). The pulse generation program904comprises statements that define a sequence of operations to be performed by the quantum machine defined in the specification902. Such operations typically include the generation of one or more analog pulses to be sent to a controlled element, such as a quantum element. Such operations typically include measuring one or more return pulses from an element. The pulse generation program is also referred to herein as a QUA program. Functions, syntax, etc. of the QUA programming language are described below. In an example implementation, Python is used as a “host” language for the QUA program. This allows leveraging Python syntax/constructs (Python variables, functions, etc.) to generate the QUA program, but it is still a QUA—not Python—program to be compiled by the compiler906to generate QOP machine code, and to be executed on the quantum controller/s210. In an example implementation, a QUA program defines the sequence of statements for: (1) Generating, shaping and sending pulses to the quantum device; (2) Measuring of pulses returning from the quantum device; (3) Performing real-time classical calculations on the measured data and storing results in classical variables; (4) Performing real-time classical calculations on classical variables; (5) Controlling the flow of the program, including branching statements; and (6) Streaming of data from the quantum controller210to the quantum programing system202and processing and saving it in the quantum programing system202. In addition to the specification of which pulses are played, a QUA program can also specify when they should be played through both explicit and implicit statements and dependency constructs. Thus, a QUA program can define exactly the timing in which pulses are played, down to the single sample level and single clock cycles of the quantum controller210. Compilation may include allocating specific resources of the quantum controller210to that quantum machine and then generating machine code that, when executed by quantum controller210, will use those allocated resources. The quantum machines manager908comprises circuitry operable to determine resources present in the quantum controller210and the availability of those resources at any given time. To determine the resources, the quantum machines manager908may be operable to read one or more configuration registers of the quantum controller210, inspect a netlist of one or more circuits of the quantum controller210, and/or parse hardware description language (HDL) source code used to define circuits of the quantum controller210and/or other files used to describe various configurations of the hardware and software components. Once the resources are determined, the quantum machines manager908may keep track of which resources are in use and which are available based on which quantum machines are “open” (i.e., in a state where some resources are reserved for that machine regardless of which, if any, pulse program that quantum machine is executing at that time), and/or which pulse programs are loaded into and/or being executed by the quantum controller210at that time. For each element defined in a specification902, the controller output and/or input ports to which it is connected are defined. During compilation, pulse modification settings for manipulating pulses intended for an element may be generated (for loading into pulse modification settings circuits504) and the pulse modification setting circuit(s)504to which they will be loaded before execution may be chosen and may be allocated to the quantum machine on which the program is to be executed. Similarly, parameters and configurations of operations that will be performed on input signals related to an element (e.g. readout/measurement pulses) may be generated during compilation (for loading into compute and signal processing circuits410). Likewise, the compute and signal processing circuit410in which they will be used may be chosen during compilation and may be allocated to the quantum machine on which the program is to be executed during compilation. One example of an element that a quantum machine may contain is a mixer of front-end circuitry254. To correct for mixer imbalances, the in-phase/quadrature (IQ) waveforms of the pulse can be multiplied by a 2×2 mixer correction matrix before being sent to the output ports. This mixer correction matrix, determined via a calibration routine, may be frequency dependent. Thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency. In one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation. Similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated. When generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times. For example, for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz. Also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed. Some systems and/or algorithms can tolerate higher phase noise. Laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator222. Other quantum systems and/or algorithms can benefit from lower phase noise, and for those systems and/or algorithms the added cost of a lower-phase-noise implementation of the multi-tone generator222may be justified. FIG.10shows an example implementation of a quantum control multi-tone generator. Shown is an example implementation of multi-tone generator222comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry1002. The signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals1003from the OCXO output1001. The signal1001is at frequency fi, f0 is a multiple of fi, each of the signals223is at a multiple of f0, and each of k and M are integers. In one example implementation, fi=100 MHz, f0=500 MHz, k=5, M=12, and signals2230-223Mrange from 500 MHz to 7 GHz in step of 500 MHz. Other implementations may use any other values of fi, f0, k, and M. Unlike the example implementations ofFIGS.11A and11B, the implementation ofFIG.10does not use any dielectric resonators (DROs) or feedback loops. This lowers the cost of the implementation ofFIG.10relative to the implementations ofFIGS.11A and11Bwith the tradeoff that phase noise saturates to a noise floor above a certain carrier offset frequency (e.g., the phase noise may be higher at offsets between ˜10 MHz and 100 MHz from the carrier frequency). The use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry222(in general VCOs introduce additional phase noise as compared to OCXOs). In an example implementation, the quantum control multi-tone generator222also comprises a variable frequency signal generator1004operable to output a signal231having a variable (i.e., tunable) frequency. The variable frequency generator1004may be driven by the same reference signal that is input to the OCXO1000(e.g., a 10 MHz signal) and/or may be driven by the signal1001output by OXCO1000(e.g., a 1000 MHz signal). For quantum computing applications, it is not only the individual phase noise fluctuations that affect the gate operation fidelity, but also the correlation between separate reference sources. In the implementations ofFIG.10, the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs. This generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations. In an example implementation, the signal processing circuit1002performs fanout, frequency multiplication, amplification, and filtration functions. In one such implementation, the multiplication is done by injecting the frequency reference fi (1001) into a nonlinear transmission line (NLTL). The NLTL creates, at its output, a comb of frequencies with spacing fi. The output of the NLTL is then fanned out to become signals2230-223M, wherein each individual signal223mis composed of the sum of multiples of fi. Each fanout output223m(0<=m<=M) is amplified and filtered with a bandpass filter with a passband which includes the frequency (k+m)*fi (0<=m<=M) and having stopbands which include the tones present at f<=(f+m−1)*fi and f>=(k+m+1)*fi so as to filter all adjacent tones, leaving a monotone output at frequency (k+m)*fi. This is just one example and other type of filtering configurations are possible. For example, in another implementation, the pass bands and stop bands of the filtering stages may be chosen in such a way as to allow multiple tones on the same channel. The fanout frequency multiplication, amplification, and filtration circuit1002can be composed of one or more NLTL, amplifier, square wave amplifier, power divider, attenuator, filter, diplexer, bias-T, inductor, resistor, and capacitor. FIG.11Ashows an example implementation of a quantum control multi-tone generator. Again shown are the OCXO1000and the circuit1002which outputs M multiples of the fi. Each of the outputs of circuit1002is then input to circuitry comprising a PLL and DRO1120in a feedback arrangement to generate a signal223. The DROs have the effect of lowering phase noise in the signals223at frequencies far from the carrier frequency. This is illustrated inFIG.12for an example signal223mhaving carrier frequency of 5 GHz. Specifically, the phase noise of signal223m(m an integer between 0 and M-1) is the minimum of the line1201—the phase noise of the circuit1002, and line1203—the phase noise of the DRO. The cut-over from the line1201to the line1203around 5.E+5 is achieved by tuning the PLL bandwidth (e.g., via a variable resistor). The implementation ofFIG.11Aprovides improved phase noise performance over the implementation ofFIG.10, at the expense of higher component cost (DROs are very expensive). FIG.11Bshows an example implementation of a quantum control multi-tone generator. In contrast to the implementation ofFIG.11A, the implementation ofFIG.11Buses only a single DRO1120and PLL1104. InFIG.11B, the outputs of circuit1002and the DRO1120feed a signal processing circuit1122which mixes the signals11060-1106N-1(N an integer) to generate signals2230-223M-1. Which of the N+1 signals11060-1106N-1is selected as signal1106q(q an integer where 0≤q≤N−1) to be input to the PLL1104may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s)253,255,257, and/or259) based on the desired frequencies of the signals2230-223M. In an example implementation, fi=100 MHz, f0=500 MHz, k=5, N=4, M=12, q=5, and signals2230-223Mrange from 500 MHz to 7 GHz in step of 500 MHz generated as follows:11060and2230are at 500 MHz,11061and2231are at 1 GHz,11062and2232are at 1.5 GHz,11063and2233are at 2 GHz,11064and2234are at 2.5 GHz,11065(=1106q) and2235are at 3 GHz2236at 3.5 GHz is generated by mixing11060and1106qin circuit11222237at 4 GHz is generated by mixing11061and1106qin circuit11222238at 4.5 GHz is generated by mixing11062and1106qin circuit11222238at 5 GHz is generated by mixing11063and1106qin circuit11222239at 5.5 GHz is generated by mixing11064and1106qin circuit112222310at 6 GHz is generated by doubling1106qin circuit112222311at 6.5 GHz is generated by mixing11060and the doubled1106qin circuit112222312at 7 GHz is generated by mixing11061and the doubled1106qin circuit1122. In an example implementation, the number of signals223and/or the frequency spacing of the signals223may be determined based on the range of frequencies that the control circuitry502of quantum controller210is configured to generate. As an example, referring toFIG.6A, if the control circuit502is configured to output signals503that span a range of 800 MHz. Then, as long as the spacing between the tones223is less than 800 MHz (ignoring margin for simplicity of example), then the quantum orchestration platform is able to generate quantum control signals across the range of frequencies from F2230minus 800 MHz (Frequency of signal2230minus 800 MHz) to F223Mplus 800 MHz (Frequency of signal2230plus 800 MHz). This, combined with programmatic control (via signal(s)253,255,257, and/or259) of the which of the tones2230-223Mis routed to which mixer of circuit254enables, for example, programmatically sweeping over a 1 GHz+ range of frequencies sent to a particular quantum element. FIG.11Cshows example implementation details of circuitry of the multi-tone generator. As shown inFIG.11C, the circuit1002may comprise one or more frequency multiplier circuits1052. In the example shown, there are three circuits1150, with one or more outputs of one or more of the circuits1150driving output ports of the multi-tone generator222, one or more outputs of one or more of the circuits1150driving inputs of one or more others of the circuits1150(i.e., one or more signal paths go through a cascade of circuits1150), and one or more outputs of one or more of the circuits1150driving one or more mixers of one or more circuits1152ofFIG.11D(i.e., one or more signal paths go through a cascade of one or more circuits1150and one or more circuits1152). In the example shown, each circuit1150comprises M, an integer, multiplier circuits1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit1052may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit1052, a PLL such as1104, mixer(s) of the circuit1122, and/or one or more inputs of the circuit224. FIG.11Dshows example implementation details of circuitry of the multi-tone generator. As shown inFIG.11C, the circuit1122may comprise one or more mixer circuits1152. In the example shown, there are three circuits1152, each generating six output signals, each of which drives an output port of the multi-tone generator222. In one example implementation. Through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier1052, the number of circuits1150, the number of circuits1152, and/or the interconnection of the circuits1150and1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers. In one example implementation, the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows:circuit11500outputs:fi, which drives an output port of the multi-tone generator2224fi, which drives the input of circuit11501, and is the basis for the frequency spacing.10fi, which drives an output port of the multi-tone generator222circuit11501outputs:4fi, which drives an input of each of circuits11520,11521, and115228fi, which drives an input of each of circuits11520,11521, and1152212fi, which drives an input of each of circuits11520,11521, and1152216fi, which drives an input of circuit11502circuit11502outputs:16fi, which drives an output port of the multi-tone generator22232fi, which drives an input of circuit1152048fi, which drives an input of circuit1152164fi which drives an input of circuit1152280fi, which drives an output port of the multi-tone generator222circuit11520receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20ficircuit11521receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36ficircuit11522receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi. In accordance with an example implementation of this disclosure, a system comprises quantum control pulse generation circuitry (e.g.,250) and a multi-tone generator circuit (e.g.,222). The multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g.,2230-2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of222). Each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz). The frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals. The system may comprise quantum control interconnect circuitry (e.g.,224and/or254) that comprises: a plurality of first input ports (e.g.,2210-2214) for reception of quantum control pulses to be sent to one or more qubits; one or more second input ports (e.g.,2290-2294) for reception of one or more fixed-frequency signals from the multi-tone generator; one or more first mixers (e.g., one or more of2700-2705) for upconversion of the quantum control pulses received via the first input ports using one or more of the fixed-frequency signals; and one or more first output ports configured to convey upconverted quantum control pulses from the first mixer to the one or more qubits. The quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing. The quantum control interconnect circuitry may comprise signal routing circuitry (e.g.,224) that couples the one or more output ports of the multi-tone generator to the plurality of third input ports of the quantum control interconnect circuitry, wherein which one or more of the plurality of output ports of the multi-tone generator is connected to which one or more of the plurality of third input ports of the quantum control interconnect circuitry is different for different configurations of the signal routing circuitry. Which of the different configurations of the quantum control interconnect circuitry is used at any given time may be controllable via one or more digital control signals from the quantum control pulse generation circuit. The quantum control interconnect circuitry may comprise a third input port (e.g.,227) for reception of quantum element readout pulses to be sent to one or more quantum element readout circuits. The quantum control interconnect circuitry may comprise a fourth input port (e.g.,2295) for reception of a variable-frequency signal (e.g.,231). The quantum control interconnect circuitry may comprise a second mixer (e.g.,2700) for upconversion of the readout pulses received via the second input port using the variable-frequency signal. The quantum control interconnect circuitry may comprise a second output port (e.g.,2250) configured to convey upconverted readout pulses from the second mixer to the one or more quantum element readout circuits. The quantum control interconnect circuitry may comprise a fifth input port (e.g.,227) for receiving return pulses from the one or more quantum element readout circuits. The quantum control interconnect circuitry may comprises a third mixer (e.g.,2705) configured to downconvert the return pulses using the variable-frequency reference signal received. The quantum control interconnect circuitry may comprise a third output (e.g.,223) configured to convey downconverted return pulses from the third mixer to the quantum control pulse generation circuitry. The multi-tone generator may comprise a crystal oscillator (e.g.,1000), and a first signal processing circuit (e.g.,1002), wherein the crystal oscillator may be configured to generate the fixed-frequency reference signal; the first signal processing circuit may be configured to process the first fixed-frequency reference signal to generate the plurality of fixed-frequency intermediary signals; a frequency of each of the plurality of fixed-frequency signals may be an integer multiple of a frequency of the first fixed-frequency reference signal. The multi-tone generator may comprise a plurality of phase locked loops (e.g.,11040-1104M-1), and a plurality of resonators (e.g.,11200-1120M-1). Each of the phase locked loops may be configured to receive an output of a respective one of the resonators. Each of the resonators may be configured to receive an output of a respective one of the phase locked loops. The plurality of fixed frequency-signals may comprise one or more of the outputs of the resonators and/or one or more signals generated from mixing together two or more outputs of the resonators (e.g., a processing circuit1122coupled to outputs of the resonators). A bandwidth of the phase locked loop may be set such that phase noise of the plurality of fixed-frequency signals at frequencies below a first frequency (e.g., fco) is a phase noise of the first signal processing circuit (e.g., represented by line1201) and phase noise of the plurality of fixed-frequency signals at frequencies above a second frequency, equal to or higher than the first frequency, is a phase noise of the resonator circuit (e.g., represented by line1203). One or more of the fixed-frequency intermediary signals (e.g., via a pass-through path of circuit1122), the output of the resonator (e.g., via a pass-through path of circuit1122), and/or one or more of the fixed-frequency signals may be coupled to a respective one or more of the plurality of output ports of the quantum control interconnect circuitry. The system may comprise a quantum control pulse generation circuit (e.g.,250) operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing. The system may comprise signal routing circuitry (e.g.,224) that couples the plurality of output ports of the multi-tone generator the plurality of third input ports of the quantum control interconnect circuitry, wherein which one or more of the plurality of output ports of the multi-tone generator is connected to which one or more of the plurality of third input ports of the quantum control interconnect circuitry is different for different configurations of the signal routing circuitry. Which of the different configurations of the signal routing circuitry is used may be controllable via one or more digital control signals (e.g.,253and/or255) from the quantum control pulse generation circuit and/or a quantum programming subsystem. In an example implementations, a signal is considered “fixed frequency” if its frequency does not vary and/or is not tunable by more than 100 parts per million (ppm). In an example implementations, a signal is considered “fixed frequency” if its frequency does not vary and/or is not tunable by more than 10 parts per million (ppm). In an example implementations, a signal is considered “fixed frequency” if its frequency does not vary and/or is not tunable by more than 5 parts per million (ppm). The present method and/or system may be realized in hardware, software, or a combination of hardware and software. The present methods and/or systems may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical implementation may comprise one or more application specific integrated circuit (ASIC), one or more field programmable gate array (FPGA), and/or one or more processor (e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture) and associated supporting circuitry (e.g., storage, DRAM, FLASH, bus interface circuits, etc.). Each discrete ASIC, FPGA, Processor, or other circuit may be referred to as “chip,” and multiple such circuits may be referred to as a “chipset.” Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to perform processes as described in this disclosure. Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to be configured (e.g., to load software and/or firmware into its circuits) to operate as a system described in this disclosure. As used herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As used herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As used herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As used herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.). As used herein, the term “based on” means “based at least in part on.” For example, “x based on y” means that “x” is based at least in part on “y” (and may also be based on z, for example). While the present method and/or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims. | 93,709 |
11942947 | DETAILED DESCRIPTION Classical computers operate by storing information in the form of binary digits (“bits”) and processing those bits via binary logic gates. At any given time, each bit takes on only one of two discrete values: 0 (or “off”) and 1 (or “on”). The logical operations performed by the binary logic gates are defined by Boolean algebra and circuit behavior is governed by classical physics. In a modern classical system, the circuits for storing the bits and realizing the logical operations are usually made from electrical wires that can carry two different voltages, representing the 0 and 1 of the bit, and transistor-based logic gates that perform the Boolean logic operations. Shown inFIG.1Ais a simple example of a classical computer configured to a bit102and apply a single logic operation104to the bit102. At time t0the bit102is in a first state, at time t1the logic operation104is applied to the bit102, and at time t2the bit102is in a second state determined by the state at time t0and the logic operation. So, for example, the bit102may typically be stored as a voltage (e.g., 1 Vdc for a “1” or 0 Vdc for a “0”) which is applied to an input of the logic operation104(comprised of one or more transistors). The output of the logic gate is then either 1Vdc or 0Vdc, depending on the logic operation performed. Obviously, a classical computer with a single bit and single logic gate is of limited use, which is why modern classical computers with even modest computation power contain billions of bits and transistors. That is to say, classical computers that can solve increasingly complex problems inevitably require increasingly large numbers of bits and transistors and/or increasingly long amounts of time for carrying out the algorithms. There are, however, some problems which would require an infeasibly large number of transistors and/or infeasibly long amount of time to arrive at a solution. Such problems are referred to as intractable. Quantum computers operate by storing information in the form of quantum bits (“qubits”) and processing those qubits via quantum gates. Unlike a bit which can only be in one state (either 0 or 1) at any given time, a qubit can be in a superposition of the two states at the same time. More precisely, a quantum bit is a system whose state lives in a two dimensional Hilbert space and is therefore described as a linear combination α|0+β|1, where |0and |1are two basis states, and a and β are complex numbers, usually called probability amplitudes, which satisfy |α|2+|β|2=1. Using this notation, when the qubit is measured, it will be 0 with probability |α|2and will be 1 with probability |β|2. |0and |1can also be represented by two-dimensional basis vectors [10] and [01], respectively, and then the qubit state is represented by [αβ]. The operations performed by the quantum gates are defined by linear algebra over Hilbert space and circuit behavior is governed by quantum physics. This extra richness in the mathematical behavior of qubits and the operations on them, enables quantum computers to solve some problems much faster than classical computers (in fact some problems that are intractable for classical computers may become trivial for quantum computers). Shown inFIG.1Bis a simple example of a quantum computer configured to store a qubit122and apply a single quantum gate operation124to the qubit122. At time t0the qubit122is described by α1|0+β1|1, at time t1the logic operation104is applied to the qubit122, and at time t2the qubits122is described by α2|0+β2|1. Unlike a classical bit, a qubit cannot be stored as a single voltage value on a wire. Instead, a qubit is physically realized using a two-level quantum mechanical system. Many physical implementations of qubits have been proposed and developed over the years with some being more promising than others. Some examples of leading qubits implementations include superconducting circuits, spin qubits, and trapped ions. It is the job of the quantum controller to generate the precise series of external signals, usually pulses of electromagnetic waves and pulses of base band voltage, to perform the desired logic operations (and thus carry out the desired quantum algorithm). Example implementations of a quantum controller are described in further detail below. FIG.2shows an example quantum orchestration platform (QOP). The system comprises a quantum programming subsystem202, a quantum controller210, and a quantum processor218. The quantum programming subsystem202comprises circuitry operable to generate a quantum algorithm description206which configures the quantum controller210and includes instructions the quantum controller210can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control pulse(s)213) with little or no human intervention during runtime. In an example implementation, the quantum programming system202is a personal computer comprising a processor, memory, and other associated circuitry (e.g., an x86 or x64 chipset) having installed on it a quantum orchestration software development kit (SDK) that enables creation (e.g., by a user via a text editor, integrated development environment (IDE), and/or by automated quantum algorithm description generation circuitry) of a high-level (as opposed to binary or “machine code”) quantum algorithm description206. In an example implementation, the high-level quantum algorithm description uses a high-level programming language (e.g., Python, R, Java, Matlab, etc.) simply as a “host” programming language in which are embedded the QOP programming constructs. The high-level quantum algorithm description may comprise a specification (an example of which is shown inFIGS.10A-10C) and a program (an example program for a Power Rabi calibration is discussed below). Although the specification and program may be part of one or more larger databases and/or contained in one or more files, and one or more formats, the remainder of this disclosure will, for simplicity of description, assume the configuration data structure and the program data structure each takes the form of a plain-text file recognizable by an operating system (e.g., windows, Linux, Mac, or another OS) on which quantum programming subsystem runs. The quantum programming subsystem202then compiles the high-level quantum algorithm description206to a machine code version of the quantum algorithm description206(i.e., series of binary vectors that represent instructions that the quantum controller's hardware can interpret and execute directly). An example implementation of the data structures/vectors used for realizing the machine code version of the quantum algorithm description are described below. The quantum programming subsystem202is coupled to the quantum controller210via interconnect204which may, for example, utilize universal serial bus (USB), peripheral component interconnect (PCIe) bus, wired or wireless Ethernet, or any other suitable communication protocol. The quantum controller210comprises circuitry operable to load the machine code quantum algorithm description206from the programming subsystem202via interconnect204. Then, execution of the machine code by the quantum controller210causes the quantum controller210to generate the necessary outbound quantum control pulse(s)213that correspond to the desired operations to be performed on the quantum processor218(e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.). Depending on the quantum algorithm to be performed, outbound pulse(s)213for carrying out the algorithm may be predetermined at design time and/or may need to be determined during runtime. The runtime determination of the pulses may comprise performance of classical calculations and processing in the quantum controller210and/or the quantum programing subsystem202during runtime of the algorithm (e.g., runtime analysis of inbound pulses215received from the quantum processor218). During runtime and/or upon completion of a quantum algorithm performed by the quantum controller210, the quantum controller210may output data/results208to the quantum programming subsystem202. In an example implementation these results may be used to generate a new quantum algorithm description206for a subsequent run of the quantum algorithm and/or update the quantum algorithm description during runtime. The quantum controller210is coupled to the quantum processor218via interconnect212which may comprise, for example, one or more conductors and/or optical fibers. The quantum controller210may comprise a plurality of interconnected, but physically distinct quantum control modules (e.g., each module being a desktop or rack mounted device) such that quantum control systems requiring relatively fewer resources can be realized with relatively fewer quantum control modules and quantum control systems requiring relatively more resources can be realized with relatively more quantum control modules. The quantum processor218comprises K (an integer) quantum elements122, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element(s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling the outbound quantum control pulses213and inbound quantum control pulses215between interconnect212and the quantum element(s)122(e.g., readout resonator(s)). In an example implementation in which the quantum processor comprises readout resonators (or other readout circuitry), K may be equal to the total number of qubits plus the number of readout circuits. That is, if each of Q (an integer) qubits of the quantum processor218is associated with a dedicated readout circuit, then K may be equal to 2Q. For ease of description, the remainder of this disclosure will assume such an implementation, but it need not be the case in all implementations. Other elements of the quantum processor218may include, for example, flux lines (electronic lines for carrying current), gate electrodes (electrodes for voltage gating), current/voltage lines, amplifiers, classical logic circuits residing on-chip in the quantum processor218, and/or the like. FIG.3Ashows an example quantum controller architecture in accordance with various example implementations of this disclosure. The quantum controller210comprises L (an integer ≥1) pulser circuits3020-302L−1and shared circuitry310. In the example implementation shown, each pulser circuit302l(l an integer between 0 and L−1) comprises circuitry for exchanging information over signal paths304l,306l, and308l, where the signal path308lcarries outbound pulses (e.g.,213ofFIG.2) generated by the pulser circuit302, (which may be, for example, control pulses sent to the quantum processor218to manipulate one or more properties of one or more quantum elements—e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements), the signal path306lcarries inbound quantum element readout pulses (e.g.,215ofFIG.2) to be processed by the pulser circuit302l, and signal path304, carries control information. Each signal path may comprise one or more conductors, optical channels, and/or wireless channels. Each pulser circuit302, comprises circuitry operable to generate outbound pulses on signal path308, according to quantum control operations to be performed on the quantum processor218. This involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses. The characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor218(via shared circuitry310and signal path306l) at a prior time. In an example implementation, the time required to close the feedback loop (i.e., time from receiving a first pulse on one or more of paths3151-315L(e.g., at an analog to digital converter of the path) to sending a second pulse on one or more of paths3130-313L−1(e.g., at an output of a digital-to-analog converter of the path), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor218. For example, the time to close the feedback loop may be on the order of 100 nanoseconds. It should be noted that each signal path inFIG.3Amay in practice be a set of signal paths for supporting generation of multi-pulse sets (e.g., two signal paths for two-pulse pairs, three signal paths for three-pulse sets, and so on). In the example implementation shown, the shared circuitry310comprises circuitry for exchanging information with the pulser circuits3020-302L−1over signal paths3040-304L−1,3060-306L−1, and3080-308L−1, where each signal path308, carries outbound pulses generated by the pulser circuit302l, each signal path306, carries inbound pulses to be processed by pulser circuit302l, and each signal path304lcarries control information such as flag/status signals, data read from memory, data to be stored in memory, data streamed to/from the quantum programming subsystem202, and data to be exchanged between two or more pulsers3020-302L. Similarly, in the example shown the shared circuitry310comprises circuitry for exchanging information with the quantum processor218over signal paths3150-315M−1and3131-313K−1, where each signal path315m(m an integer between 0 and M−1) carries inbound pulses from the quantum processor218, and each signal path313k(k an integer between 0 and K−1) carries outbound pulses to the quantum processor218. Additionally, in the example shown the shared circuitry310comprises circuitry for exchanging information with the quantum programming subsystem over signal path311. The shared circuitry310may be: integrated with the quantum controller210(e.g., residing on one or more of the same field programmable gate arrays or application specific integrated circuits or printed circuit boards); external to the quantum controller (e.g., on a separate FPGA, ASIC, or PCB connected to the quantum controller via one or more cables, backplanes, or other devices connected to the quantum processor218, etc.); or partially integrated with the quantum controller210and partially external to the quantum controller210. In various implementations, M may be less than, equal to, or greater than L, K may be less than, equal to, or greater than L, and M may be less than, equal to, or greater than K. For example, the nature of some quantum algorithms is such that not all K quantum elements need to be driven at the same time. For such algorithms, L may be less than K and one or more of the L pulsers302lmay be shared among multiple of the K quantum elements circuits. That is, any pulser302lmay generate pulses for different quantum elements at different times. This ability of a pulser302lto generate pulses for different quantum elements at different times can reduce the number of pulsers3020-302L−1(i.e., reduce L) required to support a given number of quantum elements (thus saving significant resources, cost, size, overhead when scaling to larger numbers of qubits, etc.). The ability of a pulser302lto generate pulses for different quantum elements at different times also enables reduced latency. As just one example, assume a quantum algorithm which needs to send a pulse to quantum element1220at time T1, but whether the pulse is to be of a first type or second type (e.g., either an X pulse or a Hadamard pulse) cannot be determined until after processing an inbound readout pulse at time T1-DT (i.e., DT time intervals before the pulse is to be output). If there were a fixed assignment of pulsers3020-302L−1to quantum elements of the quantum processor218(i.e., if3020could only send pulses to quantum element1220, and pulser302lcould only send pulses to quantum element1221, and so on), then pulser3020might not be able to start generating the pulse until it determined what the type was to be. In the depicted example implementation, on the other hand, pulser3020can start generating the first type pulse and pulser302lcan start generating the second type pulse and then either of the two pulses can be released as soon as the necessary type is determined. Thus, if the time to generate the pulse is Tlat, in this example the example quantum controller210may reduce latency of outputting the pulse by Tlat. The shared circuitry310is thus operable to receive pulses via any one or more of the signals paths3080-308L−1and/or3150-315M−1, process the received pulses as necessary for carrying out a quantum algorithm, and then output the resulting processed pulses via any one or more of the signal paths3060-306L−1and/or3130-313K−1. The processing of the pulses may take place in the digital domain and/or the analog domain. The processing may comprise, for example: frequency translation/modulation, phase translation/modulation, frequency and/or time division multiplexing, time and/or frequency division demultiplexing, amplification, attenuation, filtering in the frequency domain and/or time domain, time-to-frequency-domain or frequency-to-time-domain conversion, upsampling, downsampling, and/or any other signal processing operation. At any given time, the decision as to from which signal path(s) to receive one or more pulse(s), and the decision as to onto which signal path(s) to output the pulse(s) may be: predetermined (at least in part) in the quantum algorithm description; and/or dynamically determined (at least in part) during runtime of the quantum algorithm based on classical programs/computations performed during runtime, which may involve processing of inbound pulses. As an example of predetermined pulse generation and routing, a quantum algorithm description may simply specify that a particular pulse with predetermined characteristics is to be sent to signal path3131at a predetermined time. As an example of dynamic pulse determination and routing, a quantum algorithm description may specify that an inbound readout pulse at time T−DT should be analyzed and its characteristics (e.g., phase, frequency, and/or amplitude) used to determine, for example, whether at time T pulser302lshould output a pulse to a first quantum element or to a second quantum element or to determine, for example, whether at time T pulser302lshould output a first pulse to a first quantum element or a second pulse to the first quantum element. In various implementations of the quantum controller210, the shared circuitry310may perform various other functions instead of and/or in addition to those described above. In general, the shared circuitry310may perform functions that are desired to be performed outside of the individual pulser circuits3020-302L−1. For example, a function may be desirable to implement in the shared circuitry310where the same function is needed by a number of pulser circuits from3020-302L−1and thus may be shared among these pulser circuits instead of redundantly being implemented inside each pulser circuit. As another example, a function may be desirable to implement in the shared circuitry310where the function is not needed by all pulser circuits3020-302L−1at the same time and/or on the same frequency and thus fewer than L circuits for implementing the function may be shared among the L pulser circuits3020-302L−1through time and/or frequency division multiplexing. As another example, a function may be desirable to implement in the shared circuitry310where the function involves making decisions based on inputs, outputs, and/or state of multiple of the L pulser circuits3020-302L−1, or other circuits. Utilizing a centralized coordinator/decision maker in the shared circuitry310may have the benefit(s) of: (1) reducing pinout and complexity of the pulser circuits3020-302L−1; and/or (2) reducing decision-making latency. Nevertheless, in some implementations, decisions affecting multiple pulser circuits3020-302L−1may be made by one or more of the pulser circuits3020-302L−1where the information necessary for making the decision can be communicated among pulser circuits within a suitable time frame (e.g., still allowing the feedback loop to be closed within the qubit coherence time) over a tolerable number of pins/traces. FIG.3Bshows an example implementation of the quantum controller ofFIG.2. The example quantum controller shown comprises pulsers3021-302L−1, receive analog frontend350, input manager352, digital manager354, pulse operations manager356, pulse operations358, output manager360, transmit analog frontend362, data exchange364, synchronization manager366, and input/output (“I/O”) manager368. Circuitry depicted inFIG.3Bother than pulser circuits3020-302L−1corresponds to an example implementation of the shared circuitry310ofFIG.3A. The receive analog frontend350comprises circuitry operable to concurrently process up to M (an integer ≥1) analog inbound signals (RP′0-RP′M−1) received via signal paths3150-315M−1to generate up to M concurrent inbound signals (RP0-RPM−1) to be output to input manager352via one or more signal paths. Although there is shown to be M signals RP and M signals RP′, this need not be the case. Such processing may comprise, for example, analog-to-digital conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing, and/or the like. In various implementations, M may be less than, equal to, or greater than L and M may be less than, equal to, or greater than K. The input manager352comprises circuitry operable to route any one or more of signals (RP0-RPM−1) to any one or more of pulsers3020-302L−1(as signal(s) Al0-AlL−1) and/or to other circuits (e.g. as signal io_mgr to I/O manager368). In an example implementation, the input manager352comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which signals RP0-RPM−1are routed to which pulsers3020-302L−1. This may enable time division multiplexing multiple of the signals RP0-RPM−1onto a single signal Aliand/or time division demultiplexing components (e.g., time slices) of a signal RPmonto multiple of the signals AI0-AlL−1. In an example implementation, the input manager352comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals RP0-RPM−1onto a single signal Alland/or frequency division demultiplexing components (e.g., frequency bands) of a signal RPmonto multiple of the signals AI0-AlL−1. The signal routing and multiplexing/demultiplexing functions performed by the input manager352enables: a particular pulser302lto process different inbound pulses from different quantum elements at different times; a particular pulser302lto process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers3020-302L−1to processes the same inbound pulse at the same time. In the example implementation shown, routing of the signals RP0-RPM−1among the inputs of the pulsers3020-302L−1is controlled by digital control signals in_slct0-in_slctL−1from the pulsers3020-302L−1. In another implementation, the input manager may be operable to autonomously determine the appropriate routing (e.g., where the quantum algorithm description includes instructions to be loaded into memory of, and executed by, the input manager352). In the example implementation, the input manager352is operable to rout input signals RP0-RPM−1to the I/O manager368(as signal(s) io_mgr), to be sent to the quantum programing subsystem202. This routing may, for example, be controlled by signals from the digital manager354. In an example implementation, for each input signal RPmthere is a digital signal, streamm, from the digital manager354to the input manager352that controls whether RPmwill be sent from the input manager352to the I/O manager368and from there to the quantum programing subsystem202. Each of the pulsers3020-302L−1is as described above with reference toFIG.3A. In the example implementation shown, each pulser302lis operable to generate raw outbound pulses CP′l(“raw” is used simply to denote that the pulse has not yet been processed by pulse operations circuitry358) and digital control signals in_slctl, D_portl, Dl, out_slctl, ops_ctrll, ops_slctl, IFl, Fl, and dmod_scltlfor carrying out quantum algorithms on the quantum processor218, and resultslfor carrying intermediate and/or final results generated by the pulser302, to the quantum programming subsystem202. One or more of the pulsers3020-302L−1may receive and/or generate additional signals which are not shown inFIG.3Afor clarity of illustration. The raw outbound pulses CP′0-CP′L−1are conveyed via signal paths3080-308L−1and the digital control signals are conveyed via signal paths3040-304L−1. Each of the pulsers302Iis operable to receive inbound pulse signal Aliand signal f_dmodl. Pulser302, may process the inbound signal Allto determine the state of certain quantum element(s) in the quantum processor218and use this state information for making decisions such as, for example, which raw outbound pulse CP′lto generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately. Pulser302lmay use the signal f_dmodlfor determining how to process inbound pulse signal Ali. As an example, when pulser302lneeds to process an inbound signal Alifrom quantum element1223, it can send a dmod_sclt1signal that directs pulse operations manager356to send, on f_dmod1, settings to be used for demodulation of an inbound signal Al1from quantum element1223(e.g., the pulse operations manager356may send the value cos(ω3*TS*Tclk1+ϕ3), where ω3is the frequency of quantum element1223, TS is amount of time passed since the reference point, for instance the time at which quantum algorithm started running, and ϕ3is the phase of the total frame rotation of quantum element1223, i.e. the accumulated phase of all frame rotations since the reference point). The pulse operations circuitry358is operable to process the raw outbound pulses CP′0-CP′L−1to generate corresponding output outbound pulses CP0-CPL−1. This may comprise, for example, manipulating the amplitude, phase, and/or frequency of the raw pulse CP′I. The pulse operations circuitry358receives raw outbound pulses CP′0-CP′L−1from pulsers3020-302L−1, control signals ops_cnfg0-ops_cnfgL−1from pulse operations manager356, and ops_ctrl0-ops_ctrlL−1from pulsers3020-302L−1. The control signal ops_cnfgIconfigures, at least in part, the pulse operations circuitry358such that each raw outbound pulse CP′Ithat passes through the pulse operations circuitry358has performed on it one or more operation(s) tailored for that particular pulse. To illustrate, denoting a raw outbound pulse from pulser3023at time T1as CP′3,T1, then, at time T1(or sometime before T1to allow for latency, circuit setup, etc.), the digital control signal ops_cnfg3(denoted ops_cnfg3,T1for purposes of this example) provides the information (e.g., in the form of one or more matrix, as described below) as to what specific operations are to be performed on pulse CP′3,T1. Similarly, ops_cnfg4,T1provides the information as to what specific operations are to be performed on pulse CP′4,T1, and ops_cnfg3,T2provides the information as to what specific operations are to be performed on pulse CP′4,T1. The control signal ops_ctrlIprovides another way for the pulser302Ito configure how any particular pulse is processed in the pulse operations circuitry358. This may enable the pulser302Ito, for example, provide information to the pulse operation circuitry358that does not need to pass through the pulse operation manager356. For example, the pulser302Imay send matrix values calculated in real-time by the pulser302, to be used by the pulse operation circuitry358to modify pulse CP′I. These matrix values arrive to the pulse operation circuitry358directly from the pulser302Iand do not need to be sent to the pulse operation manager first. Another example may be that the pulser302Iprovides information to the pulse operation circuitry358to affect the operations themselves (e.g. the signal ops_ctrlIcan choose among several different mathematical operations that can be performed on the pulse). The pulse operations manager356comprises circuitry operable to configure the pulse operations circuitry358such that the pulse operations applied to each raw outbound pulse CP′Iare tailored to that particular raw outbound pulse. To illustrate, denoting a first raw outbound pulse to be output during a first time interval T1as CP′I,T1, and a second raw outbound pulse to be output during a second time interval T2as CP′I,T2, then pulse operations circuitry358is operable to perform a first one or more operations on CP′I,T1and a second one or more operations on CP′1,T2. The first one or more operations may be determined, at least in part, based on to which quantum element the pulse CP1,T1is to be sent, and the second one or more operations may be determined, at least in part, based on to which quantum element the pulse CP1,T2is to be sent. The determination of the first one or more operations and second one or more operations may be performed dynamically during runtime. The transmit analog frontend362comprises circuitry operable to concurrently process up to K digital signals DOkto generate up to K concurrent analog signals AOkto be output to the quantum processor218. Such processing may comprise, for example, digital-to-analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like. In an example implementation, each of the one or more of signal paths3130-313K−1(FIG.3A) represents a respective portion of Tx analog frontend circuit362as well as a respective portion of interconnect212(FIG.2) between the Tx analog frontend circuit362and the quantum processor218. Although there is one-to-one correspondence between the number of DO signals and the number of AO signals in the example implementation described here, such does not need to be the case. In another example implementation, the analog frontend362is operable to map more (or fewer) signals DO to fewer (or more) signals AO. In an example implementation the transmit analog frontend362is operable to process digital signals DO0-DOK−1as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK−1as independent outbound pulses and some signals DO0-DOK−1as two-pulse pairs (at different times and/or concurrently. The output manager360comprises circuitry operable to route any one or more of signals CP0-CPL−1to any one or more of signal paths3130-313K−1. As just one possible example, signal path3130may comprise a first path through the analog frontend362(e.g., a first mixer and DAC) that outputs AO0and traces/wires of interconnect212that carry signal AO0; signal path3131may comprise a second path through the analog frontend362(e.g., a second mixer and DAC) that outputs AO1and traces/wires of interconnect212that carry signal AO1, and so on. In an example implementation, the output manager360comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which one or more signals CP0-CPL−1are routed to which signal paths3130-313K−1. This may enable time division multiplexing multiple of the signals CP0-CPL−1onto a single signal path313kand/or time division demultiplexing components (e.g., time slices) of a signal CPmonto multiple of the signal paths3130-313K−1. In an example implementation, the output manager360comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM−1onto a single signal path313kand/or frequency division demultiplexing components (e.g., frequency bands) of a signal CPmonto multiple of the signal paths3130-313K−1. The signal routing and multiplexing/demultiplexing functions performed by the output manager360enables: routing outbound pulses from a particular pulser302Ito different ones of the signal paths3130-313K−1at different times; routing outbound pulses from a particular pulser302Ito multiple of the signal paths3130-313K−1at the same time; and multiple of the pulsers3020-302L−1generating pulses for the same signal path313kat the same time. In the example implementation shown, routing of the signals CP0-CPL−1among the signal paths3130-313K−1is controlled by digital control signals out_slct0-out_slctL−1from the pulsers3020-302L−1. In another implementation, the output manager360may be operable to autonomously determine the appropriate routing (e.g., where the quantum algorithm description includes instructions to be loaded into memory of, and executed by, the output manager360). In an example implementation, at any given time, the output manager360is operable to concurrently route K of the digital signals CP0-CPL−1as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL−1as two-pulse pairs, or route some of signals CP0-CPL−1as independent outbound pulses and some others of the signals CP0-CPL−1as multi-pulse sets (at different times and/or concurrently). The digital manager354comprises circuitry operable to process and/or route digital control signals (DigCtrl0-DigCtrlJ−1) to various circuits of the quantum controller210and/or external circuits coupled to the quantum controller210. In the example implementation shown, the digital manager receives, from each pulser302l, (e.g., via one or more of signal paths3040-304N−1) a digital signal Di that is to be processed and routed by the digital manager354, and a control signal D_portIthat indicates to which output port(s) of the digital manager354the signal DIshould be routed. The digital control signals may be routed to, for example, any one or more of circuits shown inFIG.3B, switches/gates which connect and disconnect the outputs AO0-AOK−1from the quantum processor218, external circuits coupled to the quantum controller210such as microwave mixers and amplifiers, and/or any other circuitry which can benefit from on real-time information from the pulser circuits3020-302L−1. Each such destination of the digital signals may require different operations to be performed on the digital signal (such as delay, broadening, or digital convolution with a given digital pattern). These operations may be performed by the digital manager354and may be specified by control signals from the pulsers3020-302L−1. This allows each pulser302, to generate digital signals to different destinations and allows different ones of pulsers3020-302L−1to generate digital signals to the same destination while saving resources. The synchronization manager366comprises circuitry operable to manage synchronization of the various circuits shown inFIG.3B. Such synchronization is advantageous in a modular and dynamic system, such as quantum controller210, where different ones of pulsers3020-302L−1generate, receive, and process pulses to and from different quantum elements at different times. For example, while carrying out a quantum algorithm, a first pulser circuit302land a second pulser circuit3022may sometimes need to transmit pulses at precisely the same time and at other times transmit pulses independently of one another. In the example implementation shown, the synchronization manager366reduces the overhead involved in performing such synchronization. The data exchange circuitry364is operable to manage exchange of data among the various circuits shown inFIG.3B. For example, while carrying out a quantum algorithm, a first pulser circuit3021and a second pulser circuit3022may sometimes need to exchange information. As just one example, pulser302lmay need to share, with pulser3022, the characteristics of an inbound signal Al1that it just processed so that pulser3022can generate a raw outbound pulse CP′2based on the characteristics of Al1. The data exchange circuitry364may enable such information exchange. In an example implementation, the data exchange circuitry364may comprise one or more registers to and from which the pulsers3020-302L−1can read and write. The I/O manager368is operable to route information between the quantum controller210and the quantum programming subsystem202. Machine code quantum algorithm descriptions may be received via the I/O manager368. Accordingly, the I/O manager368may comprise circuitry for loading the machine code into the necessary registers/memory (including any SRAM, DRAM, FPGA BRAM, flash memory, programmable read only memory, etc.) of the quantum controller210as well as for reading contents of the registers/memory of the quantum controller210and conveying the contents to the quantum programming subsystem202. The I/O manager368may, for example, include a PCIe controller, AXI controller/interconnect, and/or the like. FIG.4shows an example implementation of the pulser ofFIG.3B. The example pulser302Ishown comprises instruction memory402, pulse template memory404, digital pattern memory406, control circuitry408, and compute and/or signal processing circuitry (CSP)410. The memories402,404,406may comprise one or more be any type of suitable storage elements (e.g., DRAM, SRAM, Flash, etc.). The instructions stored in memory402are instructions to be executed out by the pulser302Ifor carrying out its role in a quantum algorithm. Because different pulsers3020-302L−1have different roles to play in any particular quantum algorithm (e.g., generating different pulses at different times), the instructions memory402for each pulser302Imay be specific to that pulser. For example, the quantum algorithm description206from the quantum programming subsystem202may comprise a first set of instructions to be loaded (via I/O manager368) into pulser3020, a second set of instructions to be loaded into pulser302l, and so on. Each pulse template stored in memory404comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sinc, impulse, etc.) representing the pulses to be sent to pulse operation circuitry358. Each digital pattern stored in memory406comprises a sequence of one or more binary values which may represent the digital pulses to be sent to the digital manager354for generating digital control signals DigCtrl0-DigCtrlJ−1. The control circuitry408is operable to execute the instructions stored in memory402to process inbound signal Ali, generate raw outbound pulses CP′I, and generate digital control signals in_slctI, out_slctI, D_portI, DI, IFI, FI, ops_slctI, ops_ctrlI, resultsI, dmod_slctIand pair. In the example implementation shown, the processing of the inbound signal Aliis performed by the CSP circuitry410and based (at least in part) on the signal f_dmodI. The compute and/or signal processing circuitry (CSP)410is operable to perform computational and/or signal processing functions, which may comprise, for example Boolean-algebra based logic and arithmetic functions and demodulation (e.g., of inbound signals AII). The CSP410may comprise memory in which are stored instructions for performing the functions and demodulation. The instructions may be specific to a quantum algorithm to be performed and be generated during compilation of a quantum machine specification and QUA program. In operation of an example implementation, generation of a raw outbound pulse CP′Icomprises the control circuitry408: (1) determining a pulse template to retrieve from memory404(e.g., based on a result of computations and/or signal processing performed by the CSP410); (2) retrieving the pulse template; (3) performing some preliminary processing on the pulse template; (4) determining the values of F, IF, pair, ops_slctI, and dmod_slctIto be sent to the pulse operation manager356(as predetermined in the quantum algorithm description and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (5) determining the value of ops_ctrlIto be sent to the pulse operation circuitry358; (6) determining the value of in_slctIto be sent to the input manager352; (7) determining a digital pattern to retrieve from memory406(as predetermined in the quantum algorithm description and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (8) outputting the digital pattern as Di to the digital manager along with control signal D_portI(as predetermined in the quantum algorithm description and/or determined dynamically based on results of computations and/or signal processing performed by the CSP410); (9) outputting the raw outbound pulse CP′Ito the pulse operations circuitry358; (10) outputting resultsIto the I/O manager. FIG.5shows an example implementation of the pulse operations manager and pulse operations circuitry ofFIG.3B. The pulse operations circuitry358comprises a plurality of pulse modification circuits5080-508R−1(R is an integer ≥1 in general, and R=L/2 in the example shown). The pulse operations manager356comprises control circuitry502, routing circuitry506, and a plurality of modification settings circuits5040-504K−1. Although the example implementation has a 1-to-2 correspondence between pulse modification circuits5080-508R−1and pulser circuits3020-302L−1, such does not need to be the case. In other implementations there may be fewer pulse modification circuits508than pulser circuits302. Similarly, other implementations may comprise more pulse modification circuits508than pulser circuits302. As an example, in some instances, two of the pulsers3020-302L−1may generate two raw outbound pulses which are a phase-quadrature pulse pair. For example, assuming CP1and CP2are a phase-quadrature pulse pair to be output on path3133. In this example, pulse operations circuitry358may process CP1and CP2by multiplying a vector representation of CP′1and CP′2by one or more 2 by 2 matrices to: (1) perform single-sideband-modulation, as given by (CP1CP2)=(cos(ω*TS*Tclck1)-sin(ω*TS*Tclck1)sin(ω*TS*Tclck1)cos(ω*TS*Tclck1))(CP1′CP2′), where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (2) keep track of frame-of-reference rotations, as given by (CP1CP2)=(cos(ϕ)-sin(ϕ)sin(ϕ)cos(ϕ))(CP1′CP2′), where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (3) perform an IQ-mixer correction (CP1CP2)=(C00C01C10C11)(CP1′CP2′) where C00, C01, C10, and C11are the elements of a matrix that corrects for IQ-mixer imperfections. In an example implementation, each modification settings circuit,504k, contains registers that contain the matrix elements of three matrices: Ck=(Ck00Ck01Ck10Ck11), an IQ-mixer correction matrix; Sk=(cos(ω*TS*Tclck1)-sin(ω*TS*Tclck1)sin(ω*TS*Tclck1)cos(ω*TS*Tclck1)), a single side band frequency modulation matrix; and Fk=(cos(ϕk)-sin(ϕk)sin(ϕk)cos(ϕk)), a frame rotation matrix, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis). In an example implementation, each modification settings circuit504kalso contains registers that contain the elements of the matrix products CkSkFkand SkFk. In the example shown, each pulse modification circuit508ris operable to process two raw outbound pulses CP′2rand CP′2r+1according to: the modification settings ops_cnfg2r and ops_cnfg2r+1; the signals ops_ctrl2rand ops_ctrl2r+1; and the signals pair2rand pair2r+1. In an example implementation pair2rand pair2r+1may be communicated as ops_ctrl2rand ops_ctrl2r+1. The result of the processing is outbound pulses CP2rand CP2r+1. Such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP′2rand CP′2r+1. In an example implementation, ops_cnfg2rand ops_cnfg2r+1are in the form of a matrix comprising real and/or complex numbers and the processing comprises matrix multiplication involving a matrix representation of the raw outbound pulses CP2rand CP2r+1and the ops_cnfg2rand ops_cnfg2r+1matrix. The control circuitry502is operable to exchange information with the pulser circuits3020-302L−1to generate values of ops_confg0-ops_confgL−1and f_demod0-f_demodL−1, to control routing circuitry506based on signals ops_slct0-ops_slctL−1and dmod_slct0-dmod_slctL−1, and to update pulse modification settings5040-504K−1based on IF0-IFL−1and F0-FL−1such that pulse modification settings output to pulse operations circuitry358are specifically tailored to each raw outbound pulse (e.g., to which quantum element222the pulse is destined, to which signal path313the pulse is destined, etc.) to be processed by pulse operations circuitry358. Each modification settings circuit504kcomprises circuitry operable to store modification settings for later retrieval and communication to the pulse operations circuitry358. The modification settings stored in each modification settings circuit504kmay be in the form of one or more two-dimensional complex-valued matrices. Each signal path3130-313K−1may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations. Similarly, each quantum element1220-122kmay have a particular characteristics (e.g. resonance frequency, frame of reference, etc.). In an example implementation, the number of pulse modification settings, K, stored in the circuits504corresponds to the number of quantum element1220-122K−1and of signal paths3130-313K−1such that each of the modification settings circuits5040-504K−1stores modification settings for a respective one of the quantum elements1220-122K−1and/or paths3130-313K−1. In other implementations, there may be more or fewer pulse modification circuits504than signal paths313and more or fewer pulse modification circuits504than quantum elements122and more or fewer signal paths313than quantum elements122. The control circuitry502may load values into the modification settings circuit5040-504K−1via signal503. The routing circuitry506is operable to route modification settings from the modification settings circuits5040-504L−1to the pulse operations circuit358(as ops_confg0-ops_confgL−1) and to the pulsers3020-302L−1(as f_dmod0-f_dmodL−1). In the example implementation shown, which of the modification settings circuits5040-504K−1has its/their contents sent to which of the pulse modification circuits5080-508R−1and to which of the pulsers3020-302L−1is controlled by the signal505from the control circuitry502. The signal ops_slctIinforms the pulse operations manager356as to which modification settings504kto send to the pulse modification circuit5081. The pulser302Imay determine ops_slctIbased on the particular quantum element122kand/or signal path313kto which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction). The determination of which quantum element and/or signal path to which a particular pulser302Iis to send an outbound pulse at a particular time may be predetermined in the quantum algorithm description or may be determined based on calculations performed by the pulser302Iand/or others of the pulsers3020-302L−1during runtime. The control circuitry502may then use this information to configure the routing block506such that the correct modification settings are routed to the correct one or more of the pulse modification circuits5080-508L−1. In an example implementation, the digital signal IF1instructs the pulse operations manager356to update a frequency setting of the modification settings circuit504kindicated by ops_slctI. In an example implementation, the frequency setting is the matrix Sk(described above) and the signal IF1carries new values indicating the new ωkto be used in the elements of the matrix Sk. The new values may, for example, be determined during a calibration routine (e.g., performed as an initial portion of the quantum algorithm) in which one or more of the pulsers3020-302L−1sends a series of outbound pulses CP, each at a different carrier frequency, and then measures the corresponding inbound signals AI. In an example implementation, the signal FIinstructs the pulse operations manager356to update a frame setting of the modification settings circuit504kindicated by ops_slctI. In an example implementation, the frame setting is the matrix Fk(described above) and the signal FIcarries a rotation matrix FIwhich multiplies with Fkto rotate Fk. This can be written as Fk=FIFk=(cos(Δϕ)-sin(Δϕ)sin(Δϕ)cos(Δϕ))(cos(ϕk)-sin(ϕk)sin(ϕk)cos(ϕk))=(cos(ϕk+Δϕ)-sin(ϕk+Δϕ)sin(ϕk+Δϕ)cos(ϕk+Δϕ)), where ϕkis the frame of reference before the rotation and Δϕ is the amount by which to rotate the frame of reference. The pulser302Imay determine Δϕ based on a predetermined algorithm or based on calculations performed by the pulsers302Iand/or others of the pulsers3020-302L−1during runtime. In an example implementation, the signal dmod_scltiinforms the pulse operations manager356from which of the modification settings circuits504kto retrieve values to be sent to pulser302Ias f_dmodI. The pulser302, may determine dmod_slctIbased on the particular quantum element122kand/or signal path315kfrom which the pulse to be processed arrived. The determination of from which quantum element and/or signal path a particular pulser302Iis to process an inbound pulse at a particular time may be predetermined in the quantum algorithm description or may be determined based on calculations performed by the pulser302Iand/or others of the pulsers3020-302L−1during runtime. The control circuitry502may then use this information to configure the routing block506such that the correct modification settings are routed to the correct one of the pulsers3020-302L−1. For example, when pulse generation circuit302Ineeds to demodulate a pulse signal AIIfrom quantum element122k, it will send a dmod_scltIsignal instructing the pulse operation manager356to rout the element SFk00=cos(ωk*time_stamp+ϕk) from modification settings circuit504kto pulser302I(as f_dmodI). In the example implementation shown, the digital signals C0-CK−1provide information about signal-path-specific modification settings to be used for each of the signal paths3130-313K−1. For example, each signal Ckmay comprise a matrix to be multiplied by a matrix representation of a raw outbound pulse CP′Isuch that the resulting output outbound pulse is pre-compensated for errors (e.g., resulting from imperfections in mixers, amplifiers, wiring, etc.) introduced as the outbound pulse propagates along signal path313k. The result of the pre-compensation is that output outbound pulse CPIwill have the proper characteristics upon arriving at the quantum processor218. The signals C0-CK−1may, for example, be calculated by the quantum controller210itself, by the programming subsystem202, and/or by external calibration equipment and provided via I/O manager368. The calculation of signals may be done as part of a calibration routine which may be performed before a quantum algorithm and/or may be determined/adapted in real-time as part of a quantum algorithm (e.g., to compensate for temperature changes during the quantum algorithm). FIG.6Ashows frequency generation circuitry of the quantum controller ofFIG.3B. In the example implementation shown, the frequency generation circuitry is part of control circuitry502of pulse operations manager circuitry356. The frequency generation circuitry comprises K coordinate rotation digital computer (CORDIC) circuits6020-602K−1, phase generation circuitry604, timestamp register606, and S-Matrix generation circuitry608. Each CORDIC circuit602kis operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk). The phase generation circuitry604is operable to generate the CORDIC input parameters θ0-θk−1based on: (1) the frequency setting signals IF0-IFL−1from the pulsers3020-302L−1; and (2) the contents, TS, of the timestamp register606. The timestamp register606comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1since a reference point in time (e.g., power up of the quantum controller210, start of execution of set of instructions of a quantum algorithm by the quantum controller210, etc.). In the example shown, the phase generation circuitry604sets θ0=2πf0(TS)(dtclk1), where f0is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1is the duration of a single clock cycle of clk1. This leads to the CORDIC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0rotation matrix that rotates at a frequency f0. As shown inFIG.6B, the signal IF1may comprise an update component and an fIcomponent. In an example implementation, when updateIis asserted then the phase generation circuitry updates one of more of f0-fK−1to be the value of fI. The S-matrix generation circuitry608is operable to build the matrices S0-SK−1from the outputs of the CORDIC circuits6020-602K−1. In an example implementation, the S-matrix generation circuit606is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1(which may be determined by the control information IF0-IFL−1). With K CORDIC circuits602k, the frequency generation circuitry is operable to concurrently generate K S-matrices. In instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit604is operable to change the input parameter θkof one or more of the CORDIC circuits6020-602K−1to stop generating one frequency and start generating the K+1thfrequency. In some instances, it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point). In some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in. The phase generation circuit604and timestamp register606enable both of these possibilities. FIG.7shows an example implementation of the digital manager ofFIG.3B. Shown inFIG.7are the digital manager376, controlled circuits7100-710J−1, and input manager372. The example implementation of the digital manager376comprises input routing circuit702, configuration circuit704, output routing circuit706, processing paths7080-708Z−1(where Z is an integer), and routing control circuit712. The configuration circuit704is operable to store configuration settings and use those settings to configure the processing paths7080-708Z−1and/or the routing control circuit712. The settings may, for example, be loaded via the signal DM_config as part of the quantum algorithm description provided by quantum programming subsystem202. The settings may comprise, for example, one or more of: a bitmap on which may be based a determination of which of signals D0-DL−1to route to which of signals P′0-P′Z−1for one or more instructions of a quantum algorithm; a bitmap on which may be based a determination of which processing path outputs P0-PZ−1to route to which of DigOut0-DigOutJ+M−1for one or more instructions of a quantum algorithm; and one or more bit patterns which processing paths7080-708Z−1may convolve with one or more of the signals P′0-P′Z−1for one or more instructions of a quantum algorithm. The input routing circuit702is operable to route each of the digital signals D0-DL−1to one or more of the processing paths7080-708Z−1. At any given time (e.g., for any particular instruction of every pulser302Iof pulsers3020-302L), the input routing circuit702may determine to which of the processing paths7080-708Z−1to rout the signal DIof signals D0-DL−1based on the signal faninIof signals fanin0-faninL−1. That is, for a particular instruction, the digital signal DImay be routed to any one or more of paths7080-708Z−1based on the value of faninifor that instruction. For example, faninimay be a Z-bit signal and a state of each bit of faninIduring a particular instruction may indicate whether DIis to be routed to a corresponding one of the Z processing paths7080-708Z−1during that instruction. An example implementation of the input routing circuit702is described below with reference toFIG.8. The output routing circuit706is operable to route each of the digital signals P0-PZ−1to one or more of DigOut0-DigOutJ+M−1(in the example shown DigOut0-DigOutJ+M−1connect to stream0-streamM−1, respectively, and DigOutM-DigOutJ+M−1connect to DigCtrl0-DigCtrlJ−1, respectively). At any given time (e.g., for any particular instruction of every pulser302Iof pulsers3020-302L), the output routing circuit706may determine to which of DigOut0-DigOutJ+M−1to rout the signal Pi of the signals P0-PL−1based on the signal fanoutIof signals fanout0-fanoutZ−1. That is, for a particular instruction, the digital signal Pz(z an integer between 0 and Z) may be routed to any one or more of DigOut0-DigOutJ+M−1based on the value of fanoutzfor that instruction. For example, values of fanoutzmay be (J+M−1) bits and a state of each bit of fanoutzduring a particular instruction may indicate whether Pzis to be routed to a corresponding one of the J+M−1 signals DigOut during that instruction. An example implementation of the output routing circuit704is described below with reference toFIG.8. Each of the processing path circuits7080-708Z−1is operable to manipulate a respective one of signals P′0-P′Z−1to generate a corresponding manipulated signal P0-PZ−1. The manipulation may comprise, for example, introducing a delay to the signal such that the resulting one or more of DigOut0-DigOutJ+M−1reach(es) its/their destination (a controlled circuit710and/or input manager372) at the proper time with respect to the time of arrival of a corresponding quantum control pulse at the corresponding destination. Each of the controlled circuits7100-710J−1and input manager372is a circuit which, at least some of the time, needs to operate synchronously with quantum control pulses generated by one or more of pulsers3020-302L−1(possibly a reflection/return pulse from a quantum processor in the case of input manager372). Accordingly, each of the control circuits7100-710J−1receives a respective one of control signals DigOut0-DigCtrlJ−1that is synchronized with a respective quantum control pulse. Similarly, input manager372receives a plurality of the DigOut signals (one for each stream input). The routing controller712comprises circuitry operable to generate signals fanin0-faninL−1and fanout0-fanoutZ−1based on D_path0-D_pathL−1, D_port0-D_portL−1, and/or information stored in configuration circuit704. FIG.8shows an example implementation of the digital manager ofFIG.3B. The example input routing circuit502comprises routing circuits8020-802L−1and combining circuits8040-804L−1. The example output routing circuitry506comprises circuits routing circuits8080-808Z−1and combining circuits8100-810J−1. The example processing path circuits are convolution circuits8060-806Z−1. Each of the routing circuits8020-802Lis operable to route a respective one of signals D0-DL−1to one or more of the combining circuits8040-804Z−1. To which of combining circuit(s)8040-804Z−1the signal DIis routed is determined based on the signal faninI. In an example implementation, each signal faninIis a Z-bits signal and, for a pulserIinstruction, the value of bit z of the signal faninIdetermines whether the signal DIis to be routed to combining circuit804zfor that instruction. The value of faninImay be updated on a per-instruction basis. Each of combining circuits8040-804L−1is operable to combine up to L of the signals DO-DL−1to generate a corresponding one of signals P0-PZ−1. In an example implementation, the combining comprises OR-ing together the values of the up to L signals. Each of the routing circuits8080-808Z−1is operable to route a respective one of signals P′0-P′Z−1to one or more of the combining circuits8100-810J−1. To which of combining circuit(s)8100-810J−1the signal P′zis routed is determined based on the signal fanoutz. In an example implementation, each signal fanoutzis a (J+M−1)-bit signal and the value of bit j+m−1 of the signal fanoutzdetermines whether the signal P′zis to be routed to combining circuit804j+m−1. In an example implementation the value of fanoutzis preconfigured before the runtime of the quantum algorithm, however, in another implementation it may be updated dynamically (e.g., on a per-instruction basis). Each combining circuit of combining circuits8100-810J−1is operable to combine up to Z of the signals P′0-P′Z−1(received via inputs8030to803Z−1) to generate a corresponding one of signals DigOut0-DigOutJ+M−1. In an example implementation, the combining comprises OR-ing together the values of the up to Z signals. Each convolution circuit806zis operable to convolve signal Pzwith patternzto generate signal P′z. In an example implementation, patternzis preconfigured before runtime of the quantum algorithm, however, in another implementation it may be updated dynamically. patternzmay be determined based on: the destination(s) of signal Pz(e.g., to which of controlled circuits510and/or input of input manager352Pz is intended); characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations. FIG.9illustrates configuration and control of the quantum controller via the quantum programming subsystem. InFIG.9, the quantum controller210comprises one or more instances of various circuits (such as the pulser, input manager, output manager, digital manager, pulse operations manager, and analog front end circuits described above). Connected to the inputs and outputs of the quantum controller210may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements. As described in further detail below, these physical circuits can be allocated and deallocated independently of one another such that the physical resources of the quantum controller210, and the quantum elements and external devices connected to the quantum controller210via the analog and digital inputs and outputs, can be organized into one or more “quantum machines.” Also shown inFIG.9are a compiler906and quantum machines manager908of the quantum programming subsystem202. The compiler906comprises circuitry operable to generate a machine code quantum algorithm description based on: (1) a specification902; (2) a pulse generation program904; and (3) a resources management data structure from the quantum machines manager908. The specification902identifies resources of a quantum machine some of which are mapped to physical circuits during an instantiation of a quantum machines (e.g. input and output ports of the quantum controller210), and some of which the compiler attaches to physical circuits of the quantum controller210during compilation of a Pulse generation Program904. The compiler906may allocate resources for executing the program904based on the specification902, the program904, and/or the available resources indicated by the quantum machines manager908. As an example, assume a scenario in which there are five quantum elements in the specification902and the program904uses only two of the quantum elements; the number of the pulsers3020-302Lallocated may depend on the available resources and the specifics of the program904. In one case the compiler906may allocate a first number (e.g., two) of the pulsers3020-302Lfor interfacing with the two quantum elements and in another case the compiler may allocate a second number (e.g., four) for sending pulses to the two quantum elements. Examples of resource definitions which may be present in specification902are described below with reference toFIGS.10A-C. In an example implementation, Python is used as a “host” language for the specification and the specification is a Python dictionary. In this example implementation the Python syntax/constructs can thus be leveraged to create the specification (Python variables, functions, etc.). The pulse generation program904comprises statements that define a sequence of operations to be performed by the quantum machine defined in the specification902. Such operations typically include the generation of one or more analog pulses to be sent to a controlled element, such as a quantum element. Such operations typically include measuring one or more return pulses from an element. The pulse generation program is also referred to herein as a QUA program. Functions, syntax, etc. of the QUA programming language are described below. In an example implementation, Python is used as a “host” language for the QUA program. This allows leveraging Python syntax/constructs (Python variables, functions, etc.) to generate the QUA program, but it is still a QUA—not Python—program to be compiled by the compiler906to generate QOP machine code, and to be executed on the quantum controller/s210. In an example implementation, a QUA program defines the sequence of statements for: (1) Generating, shaping and sending pulses to the quantum device; (2) Measuring of pulses returning from the quantum device; (3) Performing real-time classical calculations on the measured data and storing results in classical variables; (4) Performing real-time classical calculations on classical variables; (5) Controlling the flow of the program, including branching statements; and (6) Streaming of data from the quantum controller210to the quantum programing system202and processing and saving it in the quantum programing system202. In addition to the specification of which pulses are played, a QUA program can also specify when they should be played through both explicit and implicit statements and dependency constructs. Thus, a QUA program can define exactly the timing in which pulses are played, down to the single sample level and single clock cycles of the quantum controller210. In an example implementation, the pulses syntax defines an implicit pulse dependency, which determines the order of pulse execution. The dependency can be summarized as follows: (1) Each pulse is played immediately, unless dependent on a previous pulse yet to be played; (2) Pulses applied to the same quantum element are dependent on each other according to the order in which they are written in the program In another implementation, timing and ordering or pulses may be set forth explicitly in the QUA program. Example QUA programming constructs are described below in Table 1. TABLE 1QUA programming constructsplay(pulse * amp(g00, g01, g10, g11), qe, duration=None, condition=None, break_condition=None )Play a pulse to an element.The pulse will be modified according to the properties of the element defined in the specification, andthen played to the analog output(s) defined in the specification.Parameters:pulse - name of the pulse, as defined in the quantum machine specification.qe - name of the quantum element, as defined in the quantum machine specification.duration - duration of the pulse (″=None″ means default is no explicit duration)gij- an expression;amp( ) - matrix definition;condition - if present, the pulse will be played with the condition evaluates to true (″=None″means default is no condition);break_condition - if present, the pulser will be stopped when the condition evaluates to true(″=None″ means default is no break_condition);It is possible to scale the pulse′s amplitude dynamically by using the following syntax:play(′pulse_name′ * amp(v), ′element′), where amp(v) = mat(v, 0, 0, v)where v is a variable.Moreover, if the pulse is intended for an element that receives a pulse pair and thus is defined withtwo waveforms, the two waveforms, described as a column vector, can be multiplied by a matrix:play(′pulse_name′ * amp([v_00, v_01, v_10, v_11]), ′element′),where v_ij, i,j={0,1}, are variables.Example:>>> with program( ) as prog:>>> v1 = declare(fixed)>>> assign(v1, 0.3)>>> play(′pulse1′, ′qe1′)>>> play(′pulse1′ * amp(0.5), ′qe1′)>>> play(′pulse1′ * amp(v1), ′qe1′)>>> play(′pulse1′ * amp([0.9, v1, −v1, 0.9]), ′qe_iq_pair′)wait(duration, *qes)Wait for the given duration on all provided elements.During the wait command the quantum controller 210 will output 0.0 to the elements.Parameters:duration (int | QUA variable of type int) - time to wait (e.g., in multiples of 4nsecwith Range: [4, 224] in steps of 1).*qes (str | sequence of str) - elements to wait on (the Asterix denotes there can be0 or more)measure(pulse, qe, Rvar, *outputs)The measure statement allows operating on a quantum element (which has outputs), bysending a pulse to it, after some time acquiring the returning signal and processing it invarious waysAn element for which a measurement is applied must have outputs defined in the quatum machinespecification.A measurement may comprise:playing a pulse to the element (identical to a play statement)waiting for a duration of time defined as the time_of_flight in the definition of the element,and then sampling the returning pulse. The analog input to be sampled is defined in thedefinition of the element.processing the returned samples using the listed process(es) (if any). The processing could be,for example, demodulation and integration with specified integration weights, whichproduces a scalar, accumulated demodulation and integration that produces a vector,a sequence of demodulation and integrations that produces a vector, FIR filter, neuralnetwork.Parameterspulse - name of the pulse, as defined in the quantum machine specification. Pulse must havea measurement operation.qe - name of the element, as defined in the quantum machine specification. The element musthave outputs.Rvar - a result variable reference, a string, or ‘None’. If Rvar is a result variable reference, theraw ADC data will be sent to the quantum programing subsystem 202 and processed thereaccording to the result processing section of the QUA program. If Rvar is a string, the raw ADCdata will be sent to the quantum programming subsystem 202 and saved as it is with the defaultminimal processing. If Rvar is set to None, raw results will not be sent to quantum programmingsubsystem 202 and will not be saved. In one implementation, the raw results will be saved as longas the digital pulse that is played with pulse is high.outputs - a tuple with the form (processing identifier, params, variable name), where:processing identifierdefined in the top-level specification and/or in reserved words of the QUA languageand referred to in the pulse definition. A processing identifier may, for example, referto a set of integration weights, or neural network parameters, or the like.Paramsparameters passed to the processing referencevariable namethe name of a QUA variable to which the processing result is assigned.zero or more output tuples may be defined.Example:>>> with program( ) as prog:>>> I = declare(fixed)>>> Q = declare(fixed)>>>>>> # measure by playing ′meas_pulse1′ to QE ′rr1′, do not save raw results.>>> # demodulate and integrate using ′cos_weights′ and store result in I, and also>>> # demodulate and integrate using ′sin_weights′ and store result in Q>>> measure(′meas_pulse1′, ′rr1′, None, (‘int’, ′cos_weights′, I), (‘int’ ′sin_weights′, Q))>>>>>> # measure by playing ′meas_pulse2′ to QE ′rr1′, save raw results to tag ′samples′.>>> # demodulate and integrate data from ′out1′ port of ′rr1′ using ′optimized_weights′ asintegration weights>>> # store result in I>>> measure(′meas_pulse2′, ′rr1′, ′samples′, (‘int’, ′optimized_weights′, ′out1′, I))align(*qes)Align several quantum elements together.All of the quantum elements referenced in *qes will wait for all the others to finish theircurrently running statement.Parameters*qes (str | sequence of str) - a single quantum element, or list of quantum elementspause( )Pause the execution of the job until QmJob.resume( ) is called.The quantum machines freezes on its current output state.declare(t)Declare a QUA variable to be used in subsequent expressions and assignments.Declaration is performed by declaring a python variable with the return value of this function.Parameterst - The type of QUA variable. Possible values: int, fixed, bool, where:inta signed 32-bit numberfixeda signed 4.28 fixed point numberbooleither True or FalseReturnsThe variableExample:>>> a = declare(fixed)>>> play(′pulse′ * amp(a), ′qe′)assign(var,_exp)Set the value of a given QUA variable.Parametersvar (QUA variable) - The variable to set (defined by the declare function)_exp (QUA expression) - An expression to set the variable toExample:>>> with program( ) as prog:>>> v1 = declare(fixed)>>> assign(v1, 1.3)>>> play(′pulse1′ * amp(v1), ′qe1′)save(var, tag)Save a QUA variable with a given tag.The tag will appear later as a field in the saved results object returned by QmJob.get_results( ).The type of the variable determines the python type, according to the following rule:int −> intfixed −> floatbool −> boolParametersvar (QUA variable) - A QUA variable to savetag (str) - A name to save the value underupdate_frequency(qe, new_frequency)Dynamically update the frequency of the NCO associated with a given quantum element.This changes the frequency from the value defined in the quantum machine specification.Parametersqe (str) - The quantum element associated with the NCO whose frequency will bechangednew_frequency (int) - The new frequency value to set in units of Hz. Range: (0 to5000000) in steps of 1.Example:>>> with program( ) as prog:>>> update_frequency(″q1″, 4000000)z_rotation(angle, *qes)Shift the phase of the NCO associated with a quantum element by the given angle.This is typically used for virtual z-rotations. Equivalent to z_rot( )Parametersangle (float) - The angle to add to the current phase (in radians)*qes (str | sequence of str) - A quantum element, or sequence of quantum elements,associated with the NCO whose phase will be shiftedz_rot(angle, *qes)Shift the phase of the NCO associated with a quantum element by the given angle.This is typically used for virtual z-rotations. Equivalent to z_rotation( )Parametersangle (float) - The angle to add to the current phase (in radians)*qes (str | sequence of str) - A quantum element, or sequence of quantum elements,associated with the NCO whose phase will be shiftedset_frame(qes, angle)Set the phase of the frame matrix associated with a quantum element to the given angle.reset_phase(qes, angle)Set the total phase of the frequency modulation of a quantum element to zero (both thefrequency modulation matrix and the frame matrix).infinite_loop_( )Infinite loop flow control statement in QUA.To be used with a context manager.Optimized for zero latency between iterations, provided that no more than a single quantumelement appears in the loop.NoteIn case multiple quantum elements need to be used in an infinite loop, it is possible to addseveral loops in parallel (see example).Example:>>> with infinite_loop_( ):>>> play(′pulse1′, ′qe1′)>>> with infinite_loop_( ):>>> play(′pulse2′, ′qe2′)for(var=None, init=None, cond=None, update=None)For loop flow control statement in QUA.To be used with a context manager.Parametersvar (QUA variable) - QUA variable used as iteration variableinit (QUA expression) - an expression which sets the initial value of the iteration variablecond (QUA expression) - an expression which evaluates to a boolean variable, determinesif to continue to next loop iterationupdate (QUA expression) - an expression to add to var with each loop iterationExample:>>> x = declare(fixed)>>> with for(var=x, init=0, cond=x<=1, update=x+0.1):>>> play(′pulse′, ′qe′)if(condition)If flow control statement in QUA.To be used with a context manager.The QUA code block following the statement will be executed only if condition evaluates totrue.Parameterscondition - A boolean expression to evaluateExample:>>> x=declare(int)>>> with if_(x>0):>>> play(′pulse′, ′qe′)elseElse flow control statement in QUA.To be used with a context manager.Must appear after an if( ) statement.The QUA code block following the statement will be executed only if expression inpreceding if( ) statement evaluates to false.Example:>>> x=declare(int)>>> with if(x>0):>>> play(′pulse′, ′qe′)>>> with else( ):>>> play(′other_pulse′, ′qe′) The Play statement in QUA instructs the quantum controller210to send the indicated pulse to the indicated element. The quantum controller210will modify or manipulate the pulse according to the element's properties defined in the quantum machine specification (i.e., the compiler will generate the required pulse modification settings which will then be stored to the appropriate one or more of pulse modification settings circuit(s)5040-504K−1), so the user is relieved of the burden of having to specify the modifications/manipulations in each individual Play statement. If the element has a single input, the pulse sent to it may be defined with a single waveform. For example: ‘elements’: { ‘qubit’: {‘SingleInput’: {‘port’: (‘con1’, 1),},‘intermediate_frequency’: 70e6,‘operations’: {‘pulse1’: ‘pulse1’},}, } ‘pulses’: {‘gauss_pulse_in’: {‘operation’: ‘control’,‘length’: 12,‘waveforms’: {‘single’: ‘wf1’,}},},‘waveforms’: {‘wf1’: {‘type’: ‘arbitrary’,‘samples’:[0.49, 0.47, 0.44, 0.41, 0.37, 0.32, 0.32, 0.37, 0.41, 0.44, 0.47, 0.49] } Denoting the samples of the waveform as si, the play statement instructs the quantum controller210to modulate the waveform samples with the intermediate frequency of the element: {tilde over (s)}i=sicos(ωIFt+ϕF) ωIF, is the intermediate frequency defined in the quantum machine specification of the element and ϕFis the frame phase, initially set to zero (see z_rot statement specifications for information on ϕF). The quantum controller210then plays sito the analog output port defined in the definition of the element (in the above example, port 1). If the element has two mixed inputs (i.e. two output ports of the quantum controller210are connected to the element via an IQ mixer), in addition to the intermediate frequency, a mixer and a lo_frequency may be defined in the quantum machine specification. For example: ‘elements’: { ‘qubit’: {‘mixedInputs’: {‘I’: (‘con1’, 1),‘Q’: (‘con1’, 2),‘mixer’: ‘mixer1’,‘lo_frequency’: 5.1e9,},‘intermediate_frequency’: 70e6,‘operations’: {‘pulse1’: ‘pulse1’},}, }, A pulse that is sent to such element may be defined with two waveforms. For example: ‘pulses’: { ‘pulse1’: {‘operation’: ‘control’,‘length’: 12,‘waveforms’: {‘I’: ‘wf_I’,‘Q’: ‘wf_Q’,},},}, ‘waveforms’: {‘wf_I’: {‘type’: ‘arbitrary’,‘samples’:[0.49, 0.47, 0.44, 0.41, 0.37, 0.32, 0.32, 0.37, 0.41, 0.44, 0.47, 0.49]},‘wf_Q’: {‘type’: ‘arbitrary’,‘samples’: [0.02, 0.03, 0.03, 0.04, 0.05, 0.00, 0.05, 0.04, 0.03, 0.03, 0.02, 0.02]}, } In addition, a mixer can be defined with a mixer correction matrix that corresponds to the intermediate_frequency and the lo_frequency. For example: ‘mixers’: { ‘mixer1’: [{‘intermediate_frequency’: 70e6,‘lo_frequency’: 5.1e9,‘correction’: [0.9, 0.003, 0.0, 1.05]}], Denoting the samples of the waveforms by Iiand Qi, the play statement instructs the quantum controller210to modulate the waveform samples with the intermediate frequency of the element and to apply the mixer correction matrix in the following way: (I~ιQ~ι)=(C00C01C10C11)(cos(ωIFt+ϕF)-sin(ωIFt+ϕF)sin(ωIFt+ϕF)cos(ωIFt+ϕF))(IiQi) ωIFωIF, is the intermediate and the Cij's are the matrix elements of the correction matrix defined in the mixer for the relevant intermediate_frequency and lo_frequency. As mentioned above, ϕFis the frame phase, initially set to zero (see z_rot statement specifications for information on ϕF). The quantum controller210then plays Iiand Qito the analog output ports defined in the definition of the element (in the above example, port 1 and port 2, respectively). An element could have digital inputs as well as analog inputs. Each digital input of an element may be defined with three properties: port, delay, and buffer. For example: ‘elements’: { ‘qubit’: {‘mixedInputs’: {‘I’: (‘con1’, 1),‘Q’: (‘con1’, 2),‘mixer’: ‘mixer1’,‘lo_frequency’: 5.1e9,},‘intermediate_frequency’: 70e6,‘digital_inputs’:‘digital_input1’:‘port’: (cont1, 1)‘delay’: 144‘buffer’: 8‘digital_input2’:‘port’: (cont1, 2)‘delay’: 88‘buffer’: 20‘operations’: {‘pulse1’: ‘pulse1’},}, }, For a simple example, a pulse that is played to such quantum element could include a single digital marker which points to a single digital waveform. For example: ‘pulses’: { ‘pulse1’: {‘operation’: ‘control’,‘length’: 40,‘waveforms’: {‘I’: ‘wf_I’,‘Q’: ‘wf_Q’,},‘digital_marker’: ‘digital_waveform_high’},}, ‘digital_waveforms’: {‘digital_waveform_high’: {‘samples’: [(1, 0)]} } The coding of the digital waveform may be a list of the form: [(value, length), (value, length), . . . , (value, length)], where each value is either 0 or 1 indicating the digital value to be played (digital high or low). Each length may be an integer (e.g., divisible by 4 in one example implementation) indicating for how many nanoseconds the value should be played. A length 0 indicates that the corresponding value is to be played for the remaining duration of the pulse. In the example above, the digital waveform is a digital high. When such pulse is played to the element, via the play or the measurement command, the digital waveform may be sent to all the digital inputs of the element. For each digital input, however, the quantum controller210may: (1) Delay the digital waveform by the delay that is defined in the definition of the digital input (e.g., given in ns); (2) Convolve the digital waveform with a digital pattern that is high for a duration which is, for example, twice the buffer that is defined in the definition of the digital input (e.g., given in ns in a “buffer”); and (3) Play the digital waveform to the digital output of the quantum controller210that is indicated in the quantum machine specification to be connected to the digital input. In other implementations, the digital pattern with which the digital waveform to be convolved may be more complex than a simple high value. In one such example, the “buffer” object may comprise “duration” and “pattern” properties. In the example above a play(pulse1, qubit) command would play: (1) A digital waveform to digital output 1, which starts 144 ns after the analog waveforms and which is high for 56 ns (the length of the pulse plus 2×8 ns); and (2) A digital waveform to digital output 2, which starts 88 ns after the analog waveforms and which is high for 80 ns (the length of the pulse plus 2×20 ns). A measurement can be done for an element that has outputs defined in the quantum machine specification. For example: ‘elements’: { ‘resonator’: {‘mixedInputs’: {‘I’: (‘con1’, 3),‘Q’: (‘con1’, 4),‘mixer’: ‘mixer1’,‘lo_frequency’: 7.3e9,},‘intermediate_frequency’: 50e6,‘outputs’: {‘out’:: (‘con1’, 1),},‘time_of_flight’: 196,‘smearing’: 20,} }, As seen in the above example, when a quantum element has outputs, two additional properties may be defined: time_of_flight and smearing. The pulse used in a measurement statement may also be defined as a measurement pulse and may have integration_weights defined. For example: ‘pulses’: { ‘pulse1’: {‘operation’: ‘measurement’,‘length’: 400,‘waveforms’: {‘I’: ‘meas_wf_I’,‘Q’: ‘meas_wf_Q’,},‘integration_weights’: {‘integ1’: ‘integW1’,‘integ2’: ‘integW2’,} ‘integration_weights’: {‘integW1’: {‘cosine’: [0.0, 0.5, 1.0, 1.0, . . . , 1.0, 0.5, 0.0]‘sine’: [0.0, 0.0, . . . , 0.0]},‘integW2’: {‘cosine’: [0.0, 0.0, . . . , 0.0]‘sine’: [0.0, 0.5, 1.0, 1.0, . . . , 1.0, 0.5, 0.0]}, } A measurement statement, such as the one shown above, instructs the quantum controller210to: (1) Send the indicated pulse to the indicated element, manipulating the waveforms in the same manner that is described in the play statement section above; (2) After a time period time_of_flight (e.g., given in ns), samples the returning pulse at the quantum controller210input port/s that is/are connected to the output/s of the element. It saves the sampled data under stream_name (unless stream_name=None, in which case the sampled data will not be saved). The sampling time window will be of a duration that is the duration of the pulse plus twice the smearing (e.g., given in ns). This accounts for the returning pulse that is longer than the sent pulse due to the response of the quantum device, as well as for the cables and other elements in the pulse's path; and (3) Demodulate the sampled data with a frequency intermediate_frequency, defined in the definition of the element, perform weighted integration on the demodulated data with integration_weights that are defined in the quantum machine specification, and put the result in the indicated variable. The quantum controller210can perform multiple (e.g., 10 or more) demodulations and integrations at any given point in time, which may or may not be a part of the same measurement statement. The precise mathematical operation on the sampled data is: variable=∑isi[wcicos(ωIFti+ϕF)+wsisin(ωIFti+ϕF)] where siis the sampled data, ωIFis the intermediate_frequency, ϕFis the frame phase discussed in the z_rot statement below, and wciand wsiare the cosine and sine integration_weights. In an example implementation, the integration_weights are defined in a time resolution of 4 ns, while the sampling is done with time resolution of 1 ns (1 GSa/Sec sampling rate): wc/s4i+wc/s4i+1+wc/s4i+2+wc/s4i+3 Compilation may include allocating specific resources of the quantum controller210to that quantum machine and then generating machine code that, when executed by quantum controller210, will use those allocated resources. The quantum machines manager908comprises circuitry operable to determine resources present in the quantum controller210and the availability of those resources at any given time. To determine the resources, the quantum machines manager908may be operable to read one or more configuration registers of the quantum controller210, inspect a netlist of one or more circuits of the quantum controller210, and/or parse hardware description language (HDL) source code used to define circuits of the quantum controller210and/or other files used to describe various configurations of the hardware and software components. Once the resources are determined, the quantum machines manager908may keep track of which resources are in use and which are available based on which quantum machines are “open” (i.e., in a state where some resources are reserved for that machine regardless of which, if any, quantum algorithm description that quantum machine is executing at that time), and/or which quantum algorithm descriptions are loaded into and/or being executed by the quantum controller210at that time. For example, referring briefly toFIG.13A, during a time period where two quantum machines are open, each executing one of a first two quantum algorithms descriptions (QAD) (“Program 1” and “Program 2”), the system may be configured as shown inFIG.13Aand a data structure managed by the quantum machines manager908may reflect the situation as shown in Table 2. TABLE 2Example data structure maintained byquantum machines managerResourceStatusPulser 1Allocated to program 2Pulser 2Allocated to program 2Pulser 3Allocated to program 1Pulser 4AvailablePort 1Allocated to QM2Port 2AvailablePort 3Allocated to QM2Port 4Allocated to QM1Port 5Allocated to QM1Port 6Allocated to QM2Port 7Allocated to QM1Port 8Allocated to QM1 During another time period where a single quantum machine is open and executing a third algorithm description (“Program 3”), the system may be configured as shown inFIG.13B. The data structure managed by the quantum machines manager908may reflect the situation as shown in Table 3. TABLE 3Example data structure maintained byquantum machines managerResourceStatusPulser 1Allocated toprogram 3Pulser 2Allocated toprogram 3Pulser 3Allocated toprogram 3Pulser 4Allocated toprogram 3Port 1Allocated to QM3Port 2Allocated to QM3Port 3Allocated to QM3Port 4Allocated to QM3Port 5Allocated to QM3Port 6Allocated to QM3Port 7Allocated to QM3Port 8Allocated to QM3 Table 4 below shows an example schema which uses Python as a host language the quantum machine specification is one or more Python dictionaries. TABLE 4Example quantum machine specification schemaversioninteger <int32>schema version.controllersobjectA collection of controllers. Each controller represents a controland computation resource on the quantum controller 210hardware.property name*object (controller)specification of a single quantum control module. Here wedefine its static properties.analog_outputsobjecta collection of analog output ports and the propertiesassociated with themproperty name*object (quantum control module analog output port)specification of the properties of a physical analog output portof the quantum control module.offsetnumberDC offset to output, range: (−0.5, 0.5). Will be applied onlywhen program runs.digital_outputsobjectproperty name*object (quantum control module digital port)specification of the properties of a physical digital output portof the quantum control module.offsetnumberanalogobjecta collection of analog output ports and the propertiesassociated with them.Property name*object (quantum control module analog output port)specification of the properties of a physical analog output portof the quantum control module.offsetnumberDC offset to output, range: (−0.5, 0.5). Will be applied onlywhen program runs.typestringDefault: “opx1”analog_inputsobjectProperty name*object (quantum control module analog input port)specification of the properties of a physical digital input port ofthe quantum control module.OffsetnumberelementsobjectA collection of quantum elements and/or external devices.Each quantum element represents and describes a controlledentity which is connected to the ports (analog input, analogoutput and digital outputs) of the quantum control module.property_name*object (quantum element (QE))specification of a single element. Here we define to which portof the quantum control module the element is connected,what is the RF frequency of the pulses sent and/or receivedfrom this elementfrequencyinteger <int32>resonance frequency [Hz]. Actual carrier frequency output bythe quantum control module to the input of this QE isfrequency - lo_frequency.mixInputsobject (mixer input)specification of the input of a QE which is driven by an IQ mixerIstring(tuple) of the form ((string) controller name, (int) controlleroutput/input port)Qstring(tuple) of the form ((string) controller name, (int) controlleroutput/input port)mixerstringthe mixer used to drive the input of the QE, taken from thenames in mixers entry in the main quantum machinespecificationlo_frequencyinteger <int32>the frequency of the local oscillator which drives the mixeroutputsobjectcollection of up to two output ports of QE. Keys: “out1” and“out2”.property_name*string(tuple) of the form ((string) controller name, (int) controlleroutput/input port)intermediate_frequencyinteger <int32>intermediate frequency [Hz]. The actual frequency to beoutput by the quantum control module to the input of thiselementmeasurement_qeStringA reference to an element that has outputs (and thus can bemeasured using the measurement command). This can bespecified for any element that does not have outputs so thatwhenever a measurement command is used to measure thiselements, the actual measurement will be of the referencedelement.smearinginteger <int32>padding time, in nsec, to add to both the start and end of theraw data streaming window during a measure command.time_of_flightinteger <int32>delay time [nsec] from start of pulse until output of QE reachesquantum control module. Minimal value: 180. Used in measurecommand, to determine the delay between the start of ameasurement pulse and the beginning of the demodulationand/or raw data streaming window.singleInputobject (single input)specification of the input of a QE which has a single input portportstring(tuple) of the form ((string) controller name, (int) controlleroutput/input port)operationsobjectA collection of all pulse names to be used in play and measurecommandsproperty_name*stringthe name of the pulse as it appears under the “pulses” entry inthe quantum machine specificationdigitalInputsobjectproperty_name*object (digital input)specification of the digital input of a QEportstring(tuple) of the form ((string) controller name, (int) controlleroutput/input port)delayinteger <int32>the digital pulses played to this QE will be delayed by thisamount [nsec] relative to the analog pulses.An intinsic negative delay of 143 +− 2nsec exists by defaultoutputstring(tuple) of the form ((string) controller name, (int) controlleroutput/input port)bufferinteger <int32>all digital pulses played to this QE will be convolved with adigital pulse of value 1 with this length [nsec]pulsesobjectA collection of pulses to be played to the quantum elements.In the case of a measurement pulse, the properties related tothe measurement are specified as well.property_name*object (pulse)specification of a single pulse. Here we define its analog anddigital components, as well as properties related tomeasurement associated with it.integration_weightsobjectif measurement pulse, a collection of integration weightsassociated with this pulse,to be applied to the data output from the QE and sent to thecontroller.Keys: name of integration weights to be used in themeasurement command.property_name*stringthe name of the integration weights as it appears under the“integration_weigths” entry in the quantum machinespecificationwaveformsobjecta specification of the analog waveform to be played with thispulse.If associated element has singleInput, key is “single”.If associated element has “mixInputs”, keys are “I” and “Q”.property_name*stringname of waveform to be played at the input port given inassociated keysdigital_markerstringname of the digital marker to be played with this pulseoperationstringtype of operation. Possible values: control, measurementlengthinteger <int32>length of pulse [nsec]. Possible values: 16 to 4194304 in stepsof 4waveformsobjectA collection of analog waveforms to be output when a pulse isplayed. Here we specify their defining type (constant, arbitraryor compressed) and their actual datapoints.property_name*arbitrary waveform (object) or constant waveform (object) orcompressed waveform (object)type‘arbitrary’ | ‘constant’ | ‘compressed’samplesIf type = ‘arbitrary’:Array of numbers <float>list of values of arbitrary waveforms, range: (−0.5, 0.5)If type = ‘constant’:number <float>value of constant, range: (−0.5, 0.5)If type = ‘compressed’:Array of numbers <float>Integer <int32>digital_waveformsobjectA collection of digital waveforms to be output when a pulse isplayed. Here we specify their actual datapoints.property_name*object (digital waveform)raw data samples of a digital waveformsamplesArray of strings(list of tuples) specifying the analog data according to followingcode:The first entry of each tuple is 0 or 1 and corresponds to thedigital value, and the second entry is the length in nsec to playthe value, in steps of 1. If value is 0, the value will be played toend of pulse.integration_weightsobjectA collection of integration weight vectors used in thedemodulation of pulses returned from a quantum element.property_name*object (integration weights)specification of a set of measurement integration weights.Result of integration will be:sum over i of (W_cosine[i]cos[wt[i]] +W_sine[i]sin[wt[i]])analog[i].Here:w is the angular frequency of the quantum element, andanalog[i] is the analog data acquired by the controller.W_cosine, W_sine are the vectors associated with the ‘cosine’and ‘sine’ keys, respectively.Note: the entries in the vector are specified in 4 nsec intervals,and each entry is repeated four times during thedemodulation.Example:W_cosine = [2.0], W_sine = [0.0] will lead to the followingdemodulation operation:2.0(cos[wt[0]]analog[0] + cos[wt[1]]analog[1] +cos[wt[2]]analog[2] + cos[wt[3]]analog[3])sineArray of numbers <float>W_sine, a fixed-point vector of integration weights,range: [−2048, 2048] in steps of 2**-15cosineArray of numbers <float>W_cosine, a fixed-point vector of integration weights,range: [−2048, 2048] in steps of 2**-15mixersobjectA collection of IQ mixer calibration properties, used to post-shape the pulse to compensate for imperfections in the mixersused for upconverting the analog waveforms.property_name*Array of objects (mixer)intermediate_frequencyinteger <int32>intermediate frequency associated with correction matrixlo_freqinteger <int32>local oscillator (LO) frequency associated with correctionmatrixcorrectionstring(tuple) a 2 × 2 matrix entered as a four-element tuple specifyingthe correction matrix Elements of the quantum processor, (e.g. qubits, resonators, flux lines, gates, etc.), external devices (e.g., oscilloscopes, spectrum analyzers, waveform generators, etc.), and/or any other element which is a part of a quantum machine and is connected to output and/or input ports of the controller210, are defined using one or more of the other properties described in Table 4 and/or other similar properties which may be used in other implementations. An example of other properties which may be used to specify an element are properties of a neural network that processes pulses sent to the element. For example, an element specification may specify that pulses sent to it are to be generates and/or processed by a neural network and the element definition may include one or more parameters specifying the number of layers of the neural network, the number of neurons of the neural network, the weights and biases for each neuron of the neural network, and/or other parameters familiar to those working with neural networks. The neural network having the specified parameters may then be trained during a calibration routine (e.g., at the beginning of execution of a QUA program). For each element defined in a specification902, the controller output and/or input ports to which it is connected are defined. During compilation, pulse modification settings for manipulating pulses intended for an element may be generated (for loading into pulse modification settings circuits504) and the pulse modification setting circuit(s)504to which they will be loaded before execution may be chosen and may be allocated to the quantum machine on which the program is to be executed. Similarly, parameters and configurations of operations that will be performed on input signals related to an element (e.g. readout/measurement pulses) may be generated during compilation (for loading into compute and signal processing circuits410). Likewise, the compute and signal processing circuit410in which they will be used may be chosen during compilation and may be allocated to the quantum machine on which the program is to be executed during compilation. One example of an element that a quantum machine may contain is an IQ mixer that is connected to two output ports of the controller210. To correct for mixer imbalances, the in-phase/quadrature (IQ) waveforms of the pulse can be multiplied by a 2λ2 mixer correction matrix before being sent to the output ports. This mixer correction matrix, determined via a calibration routine, may be frequency dependent. Thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency. In one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation. Similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated. An example quantum machine specification file is described below with reference toFIGS.10A-10C. While the example implementations we show here (including the one Table 4 refers to) show some possible properties that can be defined and specified in the quantum machine specification, it is not limited to these examples. For example, various filters and their parameters may be defined (e.g. FIR filter) to be performed on pulses to be played to certain elements and/or on input signals to the controller. Pulses available for transmission by a quantum machine may be defined using one or more of the properties described in Table 4 and/or other similar properties which may be used in other implementations. Each pulse has a length. Each pulse is made of one or more waveforms. In one implementation there are two types of pulses: control pulses that are pulses that are only sent to the quantum system and will not be measured, and measurement pulses that are sent to the quantum system and will be measured upon return. The definition of a measurement pulse may specify parameters to be used for processing the measurement pulse upon its return from the element to which it was sent. Such parameters may include, for example, integration weights, parameters (e.g., number of layers, number of neurons, weights and biases, and/or the like) of a neural network, parameters (e.g., number of taps and tap coefficients) of a FIR filter, and/or the like. During compilation, pulse definitions may be used to, for example: generate pulse templates to load into pulse template memory404; generate instructions to be loaded into instruction memory402and/or compute and signal processing circuit410for retrieving and manipulating the contents of pulse template memory404to achieve the defined pulses; and/or generate one or more classical processor programs to be executed by compute and signal processing circuit410for processing readout/measurement pulses. FIGS.10A-10Cshow an example quantum machine specification. The example shown uses Python as a host language. The example quantum machine specification is a Python dictionary with a key of “config” and a value that comprises a plurality of nested objects, some of which are key-value pairs and some of which are nested dictionaries. The “version” key-value pair which indicates the version of the quantum machine specification schema being used. The “controllers” object is used to specify the number of modules/units that make up the quantum controller210of the quantum machine. The example shown specifies just a single quantum control module named “con1”, which is of type “opx1” (different opx types may, for example, indicated different hardware and/or configuration of the hardware). For each controller210, the output and input ports that are used in the quantum machine are specified. For analog outputs and inputs, DC offset voltage is specified as well. The “elements” object is used to specify elements that are connected to output and input ports of the controller210. Such elements may include quantum elements (e.g., qubits, readout resonators, flux lines, etc.), external devices (e.g., test equipment such as oscilloscopes, spectrum analyzers, signal generators, etc.), and/or any other element connected to the output and/or input ports of the controller. The example shown inFIG.10Aspecifies a qubit named “qubit” and a readout resonator named “RR”. The “qubit” element comprises “mixinputs”, “operations”, and “frequency” objects. The “mixinputs” object comprises “I”, “Q”, “lo_frequency”, and “mixer” objects. The “I” and “Q” objects specify the corresponding output ports of “con1” to which the inputs of the element are connected. The “intermediate_frequency” object specifies the intermediate frequency with which pulses sent to the qubit are to be modulated (e.g., determined from a qubit calibration routine). The “mixer” object refers to mixer object “mixer_quibit,” which is defined later in the quantum machine specification. The “operations” object specifies a “gauss-pulse” which refers to the “gauss_pulse_in” object is defined later in the quantum machine specification. The “RR” element comprises “mixinputs”, “operations”, “outputs”, “frequency”, “time_of_flight”, and “smearing” objects. The “mixinputs” object comprises “I”, “Q”, “lo_frequency”, and “mixer” objects. The “I” and “Q” objects specify the corresponding ports of “con1”. The “frequency” object specifies the frequency of the readout_resonator (e.g., determined from a qubit calibration routine). The “mixer” object refers to mixer object “mixer_res,” which is defined later in the quantum machine specification. The “operations” object specifies a “meas_pulse” which refers to the “meas_pulse_in” object is defined later in the quantum machine specification. The “time_of_flight” and “smearing” objects specify those values for the readout resonator. The “outputs” object specifies an output on the element “out1” and the corresponding input port of “con1” to which it is connected. The “Pulses” object is used to specify pulses available for transmission by the quantum machine. The example shown specifies two pulses: “means_pulse_in” and “gauss_pulse_in.” The “means_pulse_in” object in turn comprises “operation”, “length”, “waveforms”, “integration_weights”, and “digital_marker” objects. The “operation” object specifies it as a “measurement” pulse. The “I” and “Q” objects of the “waveforms” object refer to the “exc_wf” and “zero_wf” objects which are defined later in the quantum machine specification. The “integration_weights” object refers to the integration weights objects “integW1” and “integW2” which are defined later in the specification. The “digital_marker” object refers to the “marker1” object defined later in the specification. The “gauss_pulse_in” object comprises “operation”, “length”, and “waveforms” objects. The “operation” object specifies it is a “control” pulse. The “I” and “Q” objects of the “waveforms” object refer to the “gauss_wf” and “zero_wf” objects which are defined later in the quantum machine specification. The “waveforms” object defines the “zero_wf”, “gauss_wf”, and “exc_wf” objects (“exc_wf” not shown) using “type” and “samples” objects. The “digital_waveforms” defines the “marker1” object using a “samples” object. The “integration_weights” object defines the objects “integW1” and “integW2” using “cosine” and “sine” objects. The “mixers” object defines the “mixer_res” and “mixer_qubit” objects using “freq”, “lo_freq”, and “correction” objects. FIG.11is a flow chart showing an example process for operation of the quantum orchestration platform. The process begins in block1102in which one or more quantum control modules are connected together to form quantum controller210and the quantum controller210is connected to a quantum system. In this regard, the quantum controller210is modular and extendable enabling use of as many units as desired/necessary for the quantum algorithm to be performed. Each of the modules may, for example, comprise one or more of each of the circuits shown inFIG.3B. In block1103, a quantum machine with a certain specification is instantiated by a user. This may be done via a Quantum Machines Manager API. In an example of such an API, shown in Table 5, this may include a call to the open_qm( ) function or the open_qm_from_file( ) function. TABLE 5Quantum Machines Manager APIClass QuantumMachinesManager (host=None, port=None, **kargs)close_all_quantum_machines( )Closes ALL open quantum machinesget_controllers( )Returns a list of all the quantum control modules that are availableget_qm(machine_id)Gets an open quantum machine object with the given machine idParametersmachine_id - The id of the open quantum machine to getReturnsA quantum machine obj that can be used to execute programslist_open_quantum_machines( )Return a list of open quantum machines. (Returns only the ids, use get_qm(...) to getthe machine object)ReturnsThe ids listopen_qm(config, close_other_machines=True) →qm.QuantumMachine.QuantumMachineOpens a new quantum machineParametersconfig - The config that will be used by the name machineclose_other_machines - Flag whether to close all other running machinesReturnsA quantum machine obj that can be used to execute programsopen_qm_from_file(filename, close_other_machines=True)Opens a new quantum machine with config taken from a file on the local file systemParametersfilename - The path to the file that contains the configclose_other_machines - Flag whether to close all other running machinesReturnsA quantum machine obj that can be used to execute programsperform_healthcheck(strict=True)Perform a health check against the QM programming subsystem.Parametersstrict - Will raise an exception if health check failedversion( )ReturnsThe QM programming subsystem version In block1104, the quantum machines manager908attempts to allocate machine resources (i.e., resources allocated to a particular quantum machine regardless of whether a quantum algorithm description is currently executing on that quantum machine) of the quantum controller210to the new quantum machine according to the specification. In block1105, the quantum machines manager908determines whether the allocation and instantiation is successful. If not, then in block1122an alert is generated for the user (e.g., to inform the user that there are currently insufficient resources available to instantiate the required quantum machine). If allocation is successful, then in block1106the allocated resources are stored in quantum machines manager908, which updates its data structure of available resources to reflect the allocation of resources to the quantum machine, the new quantum machine is instantiated, and the process advances to block1107. In block1107, a user requests to execute a QUA program on the quantum machine. This may be done via a Quantum Machine API. In an example of such an API, shown in Table 6, this may include a call to the execute( ) function. Prior to the request to execute the QUA program, and/or during the execution of the QUA program, the user can use a Quantum Machine API, such as the one shown below in table 6, to alter any parameter that was set in the specification902. This is advantageous where, for example, something (e.g., temperature, voltage, equipment in use, and/or any other factor that may impact a quantum experiment), has changed since the time the specification902was generated. TABLE 6Quantum Machine APIClass QuantumMachine (machine_id, pb_config, config, manager)close( )Closes the quantum machine.ReturnsTrue if the close request succeeded, Raises an exception otherwise.execute(pragram, duration_limit=1000, data_limit=20000, force_execution=False, dry_run=False, **kwargs) → qm.QmJob.QmJobExecutes a program and returns a job object to keep track of execution and get results.Parametersprogram - A program( ) object generated in QUA to executeduration_limit (int) - Maximal time (in msec) for which results will be collected.data_limit (int) -Maximal amount of data sends for which results will be collected.Here data sends is either:1.4 ADC samples, in case raw data is transferred2.a single save operationforce_execution (bool) - Execute program even if warnings occur (verify this)dry_run (bool) - compile program but do not run it (verify this)No new results will be available to the returned job object When duration_limit is reached,or when data_limit is reached, whichever occurs sooner.ReturnsA QmJob object that can be used to keep track of the execution and get resultsget_config( )Gives the current config of the qmReturnsA dictionary with the qm's configget_dc_offset_by_qe(qe, input)get the current DC offset of the quantum control module analog output channelassociated with a quantum element. ** remove ** note: not currently implemented.Parametersqe - the name of the element to get the correction forinput - the input name as appears in the element's config be more specific hereReturnsthe offset, in normalized output unitsget_digital_buffer(qe, digital_input)get the buffer for digital waveforms of the quantum elementParametersqe (str) - the name of the element to get the buffer fordigital_input (str) - the digital input name as appears in the element's configReturnsthe bufferget_digital_delay(qe, digital_input)Parametersqe - the name of the element to get the delay fordigital_input - the digital input name as appears in the element's configReturnsthe delayget_io1_value( )Gives the data stored in OI1No inference is made on type.ReturnsA dictionary with data stored in IO1. (Data is in all three format: int, float, bool)get_io2_value( )Gives the data stored in IO2No inference is made on type.ReturnsA dictionary with data from the second IO register. (Data is in all three format: int, float,and bool)get_io_values( )Gives the data stored In both IO1 and IO2No inference is made on type.ReturnsA list that contains dictionaries with data from the IO registers. (Data is in all threeformat: int, float, and bool)get_smearing(qe)get the smearing associated with a measurement quantum element.This is a broadening of the raw results acquisition window, to account for dispersivebroadening in the measurement elements (readout resonators etc.) The acquisitionwindow will be broadened by this amount on both sides.Parametersqe (str) - the name of the element to get smearing forReturnsthe smearing, in nsec.get_time_of_flight(qe)get the time of flight, associated with a measurement quantum element.This is the amount of time between the beginning of a measurement pulse applied toquantum element and the time that the data is available to the controller fordemodulation or streaming.Parametersqe (str) - the name of the element to get time of flight forReturnsthe time of flight, in nseclist_controllers( )Gives a list with the defined controllers in this qmReturnsThe names of the controllers configured in this qmsave_config_to_file(filename)Saves the qm current config to a fileParametersfilename: The name of the file where the config will be savedset_correction(qe, values)Sets the correction matrix for correcting gain and phase imbalances of an IQ mixer associatedwith a quantum element.Parametersqe (str) - the name of the element to update the correction forvalues (tuple) - 4 value tuple which represents the correction matrixset_dc_offset_by_qe(qe, input, offset)set the current DC offset of the quantum control module analog output channelassociated with a quantum element.Parametersqe (str) - the name of the element to update the correction forinput (str) - the input name as appears in the element config. Options:’single’for an element with single input’I’ or ‘Q’for an element with mixer inputsoffset (float) - the dc value to set to, in normalized output units. Ranges from −0.5to 0.5 - 2{circumflex over ( )}−16 in steps of 2{circumflex over ( )}−16.set_digital_buffer(qe, digital_input, buffer)set the buffer for digital waveforms of the quantum elementParametersqe (str) - the name of the element to update buffer fordigital_input (str) - the digital input name as appears in the element's configbuffer (int) - the buffer value to set to, in nsec. Range: 0 to (255 − delay) / 2, insteps of 1set_digital_delay(qe, digital_input, delay)Sets the delay of the digital waveform of the quantum elementParametersqe (str) - the name of the element to update delay fordigital_input (str) - the digital input name as appears in the element's configdelay (int) - the delay value to set to, in nsec. Range: 0 to 255 − 2 * buffer, insteps of 1set_frequency(qe, freq)Sets the frequency of an element, at the output of the mixer, taking LO frequency intoaccount.Parametersqe (str) - the name of the element to update the correction forfreq (float) - the frequency to set to the given elementset_intermediate_frequency(qe, freq)Sets the intermediate frequency of the quantum element:Parametersqe (str) - the name of the element to update the intermediate frequency forfreq (float) - the intermediate frequency to set to the given elementset_io1_value(value_1)Sets the value of IO1.This can be used later inside a QUA program as a QUA variable IO1 without declaration.The type of QUA variable is inferred from the python type passed to value_1, accordingto the following rule:int −> int float −> fixed bool −> boolParametersvalue_1 (float | bool | int) - the value to be placed in IO1set_io2_value(value_2)Sets the value of IO1This can be used later inside a QUA program as a QUA variable IO2 without declaration.The type of QUA variable is inferred from the python type passed to value_2, accordingto the following rule:int −> int float −> fixed bool −> boolParametersvalue_1 (float | bool | int) - the value to be placed in IO1set_io_values(value_1, value_2)Sets the value of IO1 and IO2This can be used later inside a QUA program as a QUA variable IO1, IO2 withoutdeclaration. The type of QUA variable is inferred from the python type passed tovalue_1, value_2 according to the following rule:int −> int float −> fixed bool −> boolParametersvalue_1 (float | bool | int) - the value to be placed in IO1value_2 (float | bool | int) - the value to be placed in IO2set_smearing(ge, smearing)set the smearing associated with a measurement quantum element.This is a broadening of the raw results acquisition window, to account for dispersivebroadening in the measurement elements (readout resonators etc.) The acquisitionwindow will be broadened by this amount on both sides.Parametersqe (str) - the name of the element to set smearing forsmearing (int) - the time, in nsec, to broaden the acquisition window. Range: 0 to(255 − time of flight)/2, in steps of 1.set_time_of_flight(qe, time_of_flight)set the time of flight, associated with a measurement quantum element.This is the amount of time between the beginning of a measurement pulse applied toquantum element and the time that the data is available to the controller fordemodulation or streaming.This time also accounts for processing delays, which are typically 176nsec.Parametersqe (str) - the name of the element to set time of flight fortime_of_flight (int) - the time of flight to set, in nsec. Range: 0 to 255 − 2 *smearing, in steps of 4. In block1108, compiler906receives the quantum machine specification and the QUA program (e.g., in the form of two plain text files). In block1109, compiler906attempts to compile the program using the quantum machine specification and the resources of the quantum controller210that the quantum machines manager908indicates are available for program execution. During compilation, the compiler determines and allocates the program resources of the quantum controller210that will be used in the program. In block1110, the compiler906determines whether compilation is successful. If not, then in block1122an alert is generated for the user (e.g., to inform the user that there are currently insufficient resources available to execute the program). If compilation is successful, then the process advances to block1112. If compilation is successful the compiler outputs the machine code to be loaded to the quantum controller for program execution. In block1112, the programming system202loads machine code generated by the compiler906based on the program, the quantum machine specification, and the available resources into quantum controller210(e.g., via I/O Manager368). In block1114, the programming subsystem202determines whether the machine code has been successfully loaded into the quantum controller210. If not, then in block1122an alert is generated for the user. If the machine code is successfully loaded, then the process advances to block1116. In block1116, the program is executed on the quantum controller and the quantum machines manager908updates its data structure of available resources to reflect the allocation of resources to the program. Either while the program is executing and/or after the program execution is over, the user may change the configuration/specification of the quantum machine. This may be done via a Quantum Machine API, an example implementation of which is shown in Table 6. An example of changing the configuration/specification of the quantum machine may be that the user uses the call to the set_frequency(qe, freq) function, which changes the frequency of the specified element to the specified frequency. In another example implementation such quantum machines API may include commands for changing any parameter defined in the specification (e.g. an API command may allow to change the definition of the samples of a specified waveform, change the parameters of a neural network associated with an element or a pulse, etc.) If the specification is changed while a program is running on the quantum machine, this may include writing to registers and/or memory of the quantum controller210while the program is executing as well as changing the specification in the quantum machines manager. If the specification is changed while no program is running on the quantum machine, this may include only changing the specification in the quantum machines manager. The ability to alter characteristics of the quantum machine without closing the quantum machine and even during execution of a QUA program on the quantum machine enables, for example, altering the quantum machine based on calculations performed on the quantum programming subsystem202. As an example, during execution of a QUA program, results may be streamed from the quantum controller210to the quantum programming subsystem202, the quantum programming subsystem202may perform some calculations using the results (e.g., resource-intensive calculations not possible or desirable to perform on the quantum controller210) and then update the quantum machine based on the calculations. The update may impact the currently running QUA program or a successive run of the same QUA program or a different QUA program without having to close the quantum machine for reconfiguration (which may be desirable to, for example, avoid having to repeat a calibration). In block1118, upon completing execution of the instructions, the program ends and the quantum machines manager908updates its data structure to deallocate the program resources that were allocated to that program and updates the available resources. In block1120, the process can advance either back to block1107again in which a user a user requests to execute a QUA program on the quantum machine, or to block1124in which a user closes the quantum machine. If the user closes the quantum machine the process advances to block1126. In block1126the quantum machines manager908deallocate the machine resources that were allocated to that quantum machine and updates the available resources. In an example implementation, the pulse generation program904is written using the QUA programming language. To aid understanding of the QOP's unique approach to quantum control, a use case example of Power Rabi Calibration will now be described, end-to-end. The use case begins by discussing the theoretical background of the experiment and its goals and showing a typical setup on which it is implemented. It is then shown, step by step, how to program the QOP to perform this experiment, how to execute it, and how to retrieve the results. The purpose of Power Rabi Calibration is to measure Rabi oscillations—oscillations of the qubit state that are driven by a control signal. Assume that the qubit is initially in the ground state (state 0), a drive pulse is applied to rotate the qubit on the Bloch sphere around a rotation axis in the x-y plane. The qubit is then measured by calculating the effect of the resonator (that is coupled to the qubit) on a measurement pulse. The rotation angle, and consequently the probability to find the qubit in the excited state (1), depends on the amplitude of the drive pulse. The protocol is repeated with varying amplitudes (a). For each amplitude, the protocol is repeated many times for averaging, which allows extracting the probability of the qubit to be in the excited state after the drive pulse is applied. This probability is then plotted as a function of the drive amplitude, from which the rotation angle, as a function of the amplitude, can be extracted. This experiment provides an important tool for calibrating quantum gates. For example, the amplitude at which the qubit reaches a rotation of 180 degrees gives us the required amplitude for performing an X-gate (the quantum NOT gate). Similarly, this program can be run to identify the amplitude required to perform a π/2-rotation. The example experiment setup is shown inFIG.12A. The quantum device is a superconducting circuit composed of a single, fixed frequency qubit and a readout resonator, with the following Hamiltonian: H=ℏ2ωQσZ+ℏωRa†a+ℏg(a†σ-+aσ+). Since the interaction between the qubit and resonator is dispersive (|ωR−ωQ|), an approximation can be made that leads to the following form of the Hamiltonian: H=ℏ2(ωQ+g2Δ)σZ+ℏ(ωR+g2ΔσZ)a†a Where Δ=ωQ−ωR. Finally, the qubit driving term can be explicitly included, which leads to the Hamiltonian: H=H0+ℏs(t)σx·+m(t)2[a†e-iωt+aeiωt] Here it is assumed that the frequencies of both the qubit and the resonator were calibrated in advance. A signal, at the resonance frequency of the qubit, of the form s(t)=Acos(ωQt+ϕ) rotates the Bloch vector of the qubit at a rate A around the axis which is on the x-y plane and is rotated by an angle φ from the x-axis. If the parameters A(t) and φ(t) are varied slowly compared to ωQ, then this still holds at each point in time. Thus, if a pulse is sent (i.e. a signal that is finite in time) to the qubit of the form s(t)=A(t)cos(ωQt+ϕ) where A(t) varies slowly compared to ωQ, the Bloch vector will be rotated around the above axis by a total angle which is given by the integral of A(t): θ=∫t0t0+τA(t)dt. Here t0is the time at which the pulse starts and τ is the duration of the pulse. In a typical Power Rabi Oscillations experiment, the shape and duration of the pulse A(t) are fixed (e.g. a 20-nanosecond gaussian pulse) and only its amplitude is varied in order to get different rotation angles θ. The experiment performed by repeating the following basic sequence:(1) Initialize the qubit to the ground state, 0.(2) Apply a pulse with amplitude a (e.g. A(t) is a Gaussian shaped pulse with peak amplitude a, which rotates the qubit by θ so that the qubit is in the state cos(θa)|0+eiϕsin(θa)|1.(3) Apply a resonant pulse to the readout resonator, and from the phase of the reflected pulse, deduce the state of the qubit. This basic sequence is repeated in the program for a series of amplitudes (i.e., many values of a), where for each amplitude, a, it is repeated N times (i.e. N identical basic sequences with the same a). N identical measurements are required because of state collapse. The measurement at the end of each basic sequence gives a binary result (0 or 1) for the state of the qubit, even if before the measurement the qubit was in a superposition state. However, when the results of the N identical basic sequences are averaged, the average will be ˜sin2(θ). Denote this average as P|1(a) since it reflects the probability of measuring the qubit in the |1state for a given amplitude, a. The results of the whole experiment can be summarized by plotting P|1(a) as a function of a (seeFIG.12B). This can be used to calibrate any single qubit rotation gate that rotates the qubit by an angle θ, around a rotation axis that is on the x-y plane and is rotated φ from the x-axis. Such a gate is denoted by Rϕ(θ). In fact, one of the typical goals of the Power Rabi Oscillations experiment is to calibrate the amplitude of a given pulse so that it performs n-rotation (X-gate) or π/2-rotation. φ, however, cannot be determined from the Rabi oscillations and must be determined by other means (e.g. tomography). An example implementation of the Power Rabi experiment in the QOP will now be described. The experiment is implemented on the QOP as follows: (1) Defining a quantum machine specification; (2) Opening an interface to the quantum machine; (3) Writing the program; (4) Running the program; (5) Saving the results As discussed above, the quantum machine specification is a description of the physical elements present in the experimental setup and their properties, as well as the connectivity between the elements and the quantum control module(s). The physical elements that are connected to the quantum control module(s) are denoted in the quantum machine specification as elements, which are discrete entities such as qubits, readout resonators, flux lines, gate electrodes, etc. Each of these has inputs and in some cases outputs, connected to the quantum control module(s). The properties of the elements and their connectivity to the quantum control module(s) are used by the QOP to interpret and execute QUA programs correctly (e.g. a pulse played to a certain qubit is modulated by the quantum control module with the intermediate frequency defined for this element). The quantum machine specification inFIGS.10A-10Cis used for this particular example. The pulses applied to the elements are also specified in the quantum machine specification, where each pulse is defined as a collection of temporal waveforms. For example, a pulse to an element with two analog inputs and one digital input will specify the two waveforms applied to the analog inputs of the element and the digital pulse applied to its digital input. Also defined in the quantum machine specification are the properties of any auxiliary components that affect the actual output of the controller, such as IQ mixers and local oscillators. After defining the quantum machine specification, an interface to a new quantum machine can be opened with the following command:my_qm=qmManager.open_qm(my_config) After having defined the quantum machine specification, write the QUA program. Below is the power Rabi program.with program( ) as powerRabiProg:I=declare(fixed)Q=declare(fixed)a=declare(fixed)Nrep=declare(int)with for_(Nrep, 0, Nrep<100, Nrep+1):with for_(a, 0.00, a<=1.0, a+0.01):play(‘gauss_pulse’*amp(a), ‘qubit’)align(“qubit”, “RR”)measure(‘meas_pulse’, ‘RR’, ‘samples’,(‘integW1’,I), (‘integW2’,Q))save(I, ‘I’)save(Q, ‘Q’)save(a, ‘a’) The program is very intuitive to someone who knows the theory of the Power Rabi calibration, which illustrates one of the benefits of the QOP: the ability for people (e.g., quantum physicists) to rapidly design and run quantum experiments without first having to become expert programmers or computer systems designers. This is in stark contrast to current systems which, for example, require quantum physicists to learn a hardware description language such as VHDL or Verilog to be able to run their quantum experiments/algorithms. This program: (1) Defines the variables a (amplitude) and Nrep (number of repetitions), as well as the variables i and Q, which store the demodulation result; and (2) Performs 100 repetitions (the loop over Nrep), where in each scan loops over 100 values of a, from 0-1 in increments of 0.01 and for each value of a performs the Rabi sequence: playing a pulse with amplitude a to the qubit, then measuring the resonator response and extracting from it the state of the qubit. This is done by sending a measurement pulse to the resonator and demodulating and integrating the returning pulse using the indicated integration weights. The raw data sampled at the quantum control module's input is also streamed and saved with the label ‘samples.’ Finally, the demodulation and integration results, I and Q, are saved as well as the corresponding amplitude. This Python code block creates an object named powerRabiProg, which is a QUA program that can be executed on an open quantum machine. The program is run on a quantum machine “my_qm” defined in the quantum machine specification using the following command which saves the results in the job object “my_job.”my_job=my_qm.execute(powerRabiProg) After the program is executed, the results can be pulled:my_powerRabi_results=job.get_results( ) This command pulls the results from “my_job” to the results object “my_powerRabi_results”. The data in “my_powerRabi_results” is a Python object which contains the variables saved during the program, as well as all the raw data sampled at the input of the quantum control module. Here, “my_powerRabi_results” will have: (1) my_powerRabi_results.variable_results, which will be a dictionary containing three keys: ‘I’, ‘Q’ and ‘a’. The value for each key will be a dictionary containing the saved data and the time stamp for each saved data point; (2) my_powerRabi_results.raw_results, which will be a dictionary containing a single key and its value will be a dictionary containing the sampled input data and the timestamp of each data point. In accordance with an example implementation of this disclosure, a system comprises pulse generation and measurement circuitry (e.g.,210) comprising a plurality of pulse generator circuits (e.g.,302) and a plurality of ports (e.g., ports of signal path(s)304,306, and/or308), and management circuitry (e.g.,202and part of210). The management circuitry is operable to analyze a specification of a control system and controlled elements (e.g., specification902) that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports. The configuration of the pulse generation and measurement circuitry may comprise generation of one or more pulse modification settings and storage of the one or more pulse modification settings to pulse modification circuitry (e.g.,5040-504K−1) of the pulse generation and measurement circuitry. The configuration of the pulse generation and measurement circuitry may comprise generation of pulse templates and storage of the pulse templates to pulse memory (404) of the pulse generation and measurement circuitry. The configuration of the pulse generation and measurement circuitry may comprise generation of instructions for a processor (e.g., 410) of the pulse generation and modification circuitry to perform classical computations and storage of the instructions to the processor. The configuration of the pulse generation and measurement circuitry may comprise generation of digital signal processing path configuration settings and storage of the digital signal processing path configuration settings to digital signal generation circuitry (e.g.,376) of the pulse generation and measurement circuitry. The definition of the controlled element may specify whether the controlled element is to be controlled with independent pulses or with two-pair pulses (e.g., via “singleInput” and “mixInputs” properties). The definition of the controlled element may specify a frequency with which pulses sent to the controlled element are to be modulated (e.g., via an “intermediate_frequency” property). The definition of the controlled element may specify which of the one or more pulses are to be available for transmission to the controlled element (e.g., via an “operations” property). The definition of the controlled element may specify which of the plurality of ports are connected to which of one or more inputs of the controlled element of the first control system (e.g., via “mixinputs” or “singleInput” properties). The definition of the controlled element may specify whether the controlled element has an output (e.g., via an “outputs” property), and, if the controlled element has an output, one or more timing parameters to be used for receiving signals from the controlled element (e.g., via “smearing” and/or “time-of-flight” property). The one or more timing parameters determine, at least in part, one or both of: a duration of an acquisition window; and a delay between when a pulse is transmitted to the controlled element and when measurement of a signal from the controlled element should begin. The definition of the controlled element may specify one or more digital inputs of the controlled element (e.g., via a “digital inputs” property). The definition of the controlled element may specify a delay between a send time of a pulse destined for the controlled element and a send time of a digital signal accompanying the pulse destined for the controlled element (e.g., via a “delay” property). The definition of the controlled element may specify convolution parameters and/or delay parameters for use with digital signals sent to the controlled element (e.g., via a “buffer”. The definition of the controlled element may specify a circuit element associated with the controlled element (e.g., in the signal path to the controlled element), The circuit element may be a of particular type (e.g., a mixer) specified by a property named after the type of circuit (e.g., “mixer”)). The control system specification comprises a definition of the circuit element, and the definition of the circuit element may comprise a parameter for compensating for nonidealities of the circuit element (e.g., a mixer correction matrix). The definition of the one or more pulses may specify one or more parameters to be used for processing signals from the controlled element (e.g., integration weights, a filter transfer function, etc.). The specification may comprise a definition of the one or more parameters, which may take the form of a plurality of vectors. The definition of the one or more pulses may specify one or more waveforms to be used for generation of the one or more pulses (e.g., via a “waveforms” property). The specification may comprise a definition of the one or more waveforms. The definition of the one or more waveforms which may take the form of a collection (e.g., list, string, array, etc.) of samples of the one or more waveforms. The definition of the one or more pulses may specify one or more digital signals that are to be output along with the one or more pulses. The specification may comprise a definition of the one or more digital signals. The definition of the one or more digital signals may specify the digital values of the one or more digital signals and how long each of the digital values is to be output. The management circuitry may be operable to receive commands via an application programming interface (e.g., a quantum machine API, an example of which is shown in Table 6), and the configuration may be based on the commands such that the commands supplement the specification and/or override one or more definitions in the specification. The present method and/or system may be realized in hardware, software, or a combination of hardware and software. The present methods and/or systems may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical implementation may comprise one or more application specific integrated circuit (ASIC), one or more field programmable gate array (FPGA), and/or one or more processor (e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture) and associated supporting circuitry (e.g., storage, DRAM, FLASH, bus interface circuits, etc.). Each discrete ASIC, FPGA, Processor, or other circuit may be referred to as “chip,” and multiple such circuits may be referred to as a “chipset.” Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to perform processes as described in this disclosure. Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to be configured (e.g., to load software and/or firmware into its circuits) to operate as a system described in this disclosure. As used herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As used herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As used herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As used herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.). As used herein, the term “based on” means “based at least in part on.” For example, “x based on y” means that “x” is based at least in part on “y” (and may also be based on z, for example). While the present method and/or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims. | 143,797 |
11942948 | DETAILED DESCRIPTION A Wideband Pseudo Random Noise Former (WPRN Former) is used to accomplish multiple tasks including: calibrating a Global Navigation Satellite System (“GNSS”) Radio Frequency (“RF”) front-end by a pseudo-satellite signal; generating composite signals for local positioning; transmitting signals from a near transmitter with its further subtraction from the received signal, which partially solves a near-far problem; and generating signals for truck-platooning, mm-range radars, prism direction finding of a total station, etc. In one embodiment, a basic WPRN former comprises:(a) a set of channels with code generators, each channel including a PRN code generator and an NCO with a controlled frequency and a phase, the output of the NCO generating a strobe sent to PRN code generator which generates a new element of +1 and −1 sequence according to the received strobe;(b) a modulator including:(1) a plurality of weight coefficients,(2) a plurality of multipliers multiplying one weight coefficient by the output of one of PRN code generator,(3) an adder outputting a sum of multipliers' outputs(4) a mixer with a quadrature output, the mixer multiplies the output of the adder by sines and cosines of intermediate frequency close to zero (low-IF)(c) a processor controlling the set of channels with code generators(d) a receiving-transmitting device to receive/transmit quadrature signals, the receiving-transmitting device including an RF front-end and antenna; and(e) an interface connecting the output of the quadrature mixer and receiving-transmitting device to receive/transmit quadrature signals. In one embodiment, the output of the mixer of the WPRN former transmits a broadcast quadrature signal converted to a radio frequency and/or adds the quadrature signal from the mixer output to a received broadcast signal which was converted by the quadrature signal to zero or near-zero frequency or replace the received and converted to zero or near-zero frequency quadrature signal. In one embodiment, the number of channels in the set of channels is in an integer times greater than the number of weight coefficients in the plurality of weight coefficients, the NCO clock rate is the same integer smaller than the bandwidth of the signal transmitted and/or received by the antenna in the transceiver module. FIG.1shows a schematic of a Wideband Pseudo Random Noise (“WPRN”) former10according to one embodiment.FIG.1shows WPRN former10comprising CPU100, channel with code generator101(1) . . .101(N), code rate numerically-controlled oscillator (“CRNCO”)102, code generator103, data buffer104, XOR105, PRN code S106, data synchronization signal S107, data S108, one bit pseudorandom sequence with data S109, modulator110, weight multiplexer112(1) . . .112(N), multiplier unit113(1) . . .113(N),115,116, weight coefficient114(1) . . .114(N), intermediate frequency NCO (“IFNCO”)117, cosine unit118, sine unit119, signal with cosine modulation S120, signal with sine modulation S121, interface122, RF path123, antenna124, adder unit125. In one embodiment, a digital quadrature mixer (i.e., a mixer with a quadrature output) includes unit115, unit116, IFNCO117, cosine unit118, and sine unit119. In one embodiment, before operation, CPU100initializes code rate and initial phase of CRNCO102, code generator103, data buffer104, weight coefficient114(1) . . .114(N), intermediate frequency of IFNCO117, and interface122. CRNCO102generates a strobe at a code rate. The strobe is input to code generator103. Code generator103generates PRN Code S106which is input to XOR105. Code generator103generates data synchronization signal S107which is input to data buffer104. Data buffer104outputs signal S108which is input to XOR105. Data in signal S108output from data buffer104are modified according to signal S107. If needed, CPU100writes new data to data buffer104. XOR105outputs one-bit pseudorandom sequence with data S109. S109(1) . . . S109(N) are output from channels with code generator101(1) . . .101(N) and are input to modulator110. In modulator110, signals S109(1) . . .109(N) are input to the control input of weight multiplexer112(1) . . .112(N). If S109is active, then the value −1 is input to output unit112, otherwise, the value +1 is input to output unit112. Output of output unit112(1) . . .112(N) is input to multiplier113(1) . . .113(N). The output of weight coefficient114(1) . . .114(N) is input to multiplier113(1) . . .113(N). Output of output unit112and output of output unit114are multiplied in multiplier113and are input to adder125where multiplication results113(1) . . .113(N) are added. The output of adder125is input to multiplier unit115and multiplier unit116. IFNCO117generates an intermediate frequency phase which is input to cosine unit118and sine unit119. The output of cosine unit118is input to multiplier unit115. The output of sine unit119is input to multiplier unit116. In multiplier unit115, the output of adder unit125is multiplied by the output of cosine unit118, i.e., the output of adder unit125is modulated by the output of cosine unit118. In multiplier unit116, the output of adder unit125is multiplied by the output of sine unit119, i.e., the output of adder unit125is modulated by the output of sine unit119. In one embodiment, multiplier unit115and multiplier unit116function as a quadrature mixer located in modulator110. The output of multiplier unit115is signal S120. The output of multiplier unit116is signal S121. Signal S120and signal S121from the output of modulator110are input to interface122. The output of interface122is input to RF unit123which outputs a signal to antenna124. During operation CPU100controls code frequency and phase in CRNCO102, data buffer104, weight coefficient114(1) . . .114(N), and frequency and phase in IFNCO117. Channels with code generator101(1) . . .101(N) generate signals S109(1) . . . S109(N) which are code signal S106with superimposed data S108, and S109can be shifted in time (phase) relative to each other. In modulator110, signals S109(1) . . . S109(N) are assigned a positive or negative sign and are scaled by weight coefficient114(1) . . .114(N) and added and modulated in cosine unit118and sine unit119. This arrangement makes it possible to generate complicated multi-level composite signals, as well as interpolate and smooth fronts without a classical interpolator with sophisticated control schematics and a great number of multiplying multi-bits data. Both of these functions are implemented using a few NCOs, wherein different code phases and weight coefficients are preset and the results are summed. Since weight coefficients are multiplied by +1 or −1, this multiplication operation can be implemented by compact multipliers taking smaller space than that of multi-bit multipliers. A signal at the output of adder unit125can be brought to intermediate frequency by multiplying by sine and cosine. In one embodiment, this operation is needed for most solved tasks. Depending on the problem being solved, different embodiments of interface122can be used in the apparatus. Such embodiments can be modified by reconfiguring of the interface, so that the same apparatus can be used for different applications.FIGS.2A,2B,2C, and2Dshow different embodiments of interface122. FIG.2Ashows interface122comprising: analog to digital convertor (“ADC”)205and adder unit130and adder unit131. From RF front-end123a signal is fed to ADC205and digitized, then the digitized quadrature signal is input to adder unit130and adder unit131where it is added to the signal of multiplier unit (also referred to as quadrature mixer)115and multiplier unit (also referred to as quadrature mixer)116. The output of adder unit130and adder unit131is input to signal processor126for further processing. This interface implementation can be used for local positioning to subtract a third party's interference signal from the received signal. FIG.2Bshows interface122, which includes: digital to analog convertor (“DAC”)202and ADC205. The output of quadrature mixer115and quadrature mixer116is input to DAC202, and then is converted to the intermediated radio frequency in the transmitting portion of RF front-end123. It is then moved to zero or near-zero frequency in the receiving portion of RF123, with either the signal is added to the received broadcasting radio signal from antenna124or replacing the received broadcasting signal from antenna124. Such an implementation can be applied for GNSS receiver calibration. In some embodiments, the RF front-end is calibrated before the GNSS receiver starts to search and track satellite signals. In such embodiments, during a calibration phase the signal from the antenna is replaced by the generated signal by means of an RF-switch. After the calibration phase the RF-switch is reconfigured to provide a path for satellite signals from the antenna. In other embodiments, the RF front-end is calibrated simultaneously with satellite signal reception. In this embodiment the generated signal with relatively weak power is added to the signal from antenna. A combiner, differential operational amplifier or other RF components can be used for summing the signals. In some embodiments the signal output by the transmitting portion of RF front-end123is a calibrating signal. The calibrating signal, in some embodiments, resembles GNSS navigation signals. In some embodiments, the calibrating signal is a particular signal with characteristics that do not resemble characteristics of GNSS navigation signals. In some embodiments, characteristics of the particular signal are periodically modified during calibration process. FIG.2Cshows interface122including DAC202. The output signal of quadrature mixer115and quadrature mixer116passes through DAC202, then is converted to the intermediate radio frequency in the transmitting portion of RF123. Such an implementation can be used for local positioning in transmitters. In some embodiments, code phase and/or carrier phase of the generated signal are adjusted according to corresponding code and/or carrier phase of a master transmitter or according to a GNSS reference signal. In other embodiments, the parameters are adjusted according to a reference signal being locally connected to the transmitter. FIG.2Dshows interface122comprising subtractor206, DAC202and ADC205. The output signal from modulator110(1) passes through DAC202, then is converted to the intermediate frequency in the transmitting portion of RF123. Another operation mode is also possible. In this other operation mode, when a broadcasting signal is input to the receiving portion of RF123where it is converted to zero or near-zero frequency, the signal is then digitized and, in subtractor206, it is added to or subtracted from the signal from modulator110(2). This implementation allows transmitting the signal to an antenna and subtracting the near-end echo of the implementation's own transmitter from the signal received from this or another antenna in millimeter-range radars. FIG.3shows a particular case in which the channel with code generator101(1),101(2),101(3),101(4), and101(5) generates signals S109(1), S109(2), S109(3), S109(4), and S109(5). At the same time, PRN codes S106(shown inFIG.1) are phase shifted relative to each other by Tdelta. Tdelta are used when specifying the phase offset of the code frequency in CRNCO102during initialization. Weight coefficients114(1),114(2),114(3),114(4), and114(5) are set equal to a value of +1, weight coefficient (6) . . . weight coefficient (N) equal to the value of 0. At the output of adder125, a multi-level PRN Code with tilted edges is generated. FIG.4shows an embodiment of a WPRN former that includes additional components. In one embodiment, WPRN former40can be implemented with two antennas (transmitting124(1), receiving124(2)) or with single receiving-transmitting antenna124(not shown). The following components are added to the embodiment shown inFIG.1to assemble a more complex embodiment of WPRN former40as shown inFIG.4: digital combiner201(1) . . .201(2), DAC202(1) . . .202(2), analog sum unit203, subtractor mux204, ADC205, subtractor unit206, navigation receiver207, and decimator208. In the complex embodiment shown inFIG.4, the number of the following units increases: Modulator110(1) . . .110(8), RF- path123(1) . . .123(2), antenna124(1) . . .124(2), channels with code generator101(1) . . .101(N*2). WPRN former40operates at synchronous clock speeds CLKsend and CLKch. In one embodiment, CLKsend and CLKch can have the same rate. CLKch can be also, for example, twice (or 2{circumflex over ( )}M times) as slow as CLKsend. The following components of WPRN former40operate at CLKsend clock speed: channel code generator101(1) . . .101(N*2), Modulator110(1) . . .110(8), digital combiner201(1) . . .201(2), DAC202(1) . . .202(2), subtractor mux204, and a portion of decimator208. The following components of WPRN former40operate at CLKch clock speed: a portion of decimator208, subtractor206, navigation receiver207, and ADC205. Before operation, CPU100adjusts: channel code generator101(1) . . .101(N*2), modulator110(1) . . .110(8), digital combiner201(1) . . .201(2), subtractor mux204, decimator208, subtractor206, navigation receiver207, and ratio of clocks CLKsend and CLKch. Channel with code generator101generates signal S109. From the output of channel with code generator101(1) . . .101(N) signals S109(1) . . . S109(N) are input to modulator110(1) . . .110(4) where they are scaled and down converted to the intermediate frequency. Signals S120and S121from the output of Modulator110(1) . . .110(4) are input to digital combiner201(1) with further conversion. From the output of Digital combiner201(1) they are fed to the input of DAC202(1) and Subtractor mux204. Returning toFIG.1, in various embodiments, interface122comprises:(1) a quadrature DAC202(1) and quadrature DAC202(2), DAC202(2) is subject to clocking with a half-period delay relative to DAC202(1);(2) a splitter circuit with two quadrature inputs and two quadrature outputs, converting the quadrature outputs of the mixers of modulators110(1) . . .110(8), the quadrature outputs of which are connected to inputs of DAC202(1) and DAC202(2);(3) an analog component wise addition module for two quadrature signals to obtain one quadrature signal, the splitter generating quadrature outputs of mixers such that after addition in the analog component wise addition module there is a signal shaped as a DAC double clock rate signal (signal with double clock rate of DAC), in this signal, even samples are output signals of the mixer of one modulator, odd samples are the mixer's output signals of the other modulator, the output of said analog component wise addition module is connected with RF front-end, and the output of RF front-end is connected with the transmitting antenna. The apparatus is part of a local positioning transmitter of signals. In one embodiment, the splitter is part of digital combiner201. Returning toFIG.4, signal S109(N+1) . . . S109(N*2) from the output of channels with code generator101(N+1) . . .101(N*2) are input to modulator110(5) . . .110(8) where they are modulated. From the output of modulator110(5) . . .110(8), signals S120and S121are input to digital combiner201(2) and are converted there. From the output of digital combiner201(2) the signals are input to DAC202(2) and subtractor mux204. Signals from the output of DAC202(1) . . . DAC(2) are added in analog Sum203and further are input to RF-path123(1). Operation amplifier can serve as analog sum203. After passing through RF-path123(1), the signal is transmitted to antenna124(1). The output of subtractor mux204is input to decimator208. In decimator208, the signal is decimated according to the preset ratio of clock speeds CLKsend and CLKch. The output signal from decimator208is input to subtractor206. The signal from antenna124(2) is input to RF-path123(2). Once RF-path123(2) is passed, the signal is input to ADC205. The digitized signal from the output of ADC205is input to subtractor206. In subtractor206, if needed (e.g., it is assigned by CPU100), a signal from the output of decimator208is subtracted from the sampled signal from the output of ADC205, and it is input to navigation receiver207. In navigation receiver207, the signal is processed. In one embodiment, in operation, CPU100controls: channels with code generator101(1) . . .101(N*2), modulator110(1) . . .110(8), digital combiner201(1) . . .201(2), subtractor mux204, decimator208, subtractor206, and navigation receiver207. FIG.5shows a block diagram of an embodiment including a digital combiner circuit. In one embodiment, the digital combiner comprises: Multiplexer310(1. . .4),311(1. . .4),306, adder320,321, subtraction unit330,331in digital combiner201, splitter signal S350, S351, S360, S361, and DAC input signal S340, S341. In one embodiment, CPU100initiates and controls: modulator110(1) . . .110(8) and subtractor mux204. Before operation, CPU100adjusts multiplexer310(1) . . . (310(4), multiplexer311(1) . . .311(4), and multiplexer306. Digital combiner201(1) and digital combiner201(2) are paired. Signals S120and S121from the output of Modulator110(1) . . .101(4) are input to digital combiner201(1). Signals S120and S121from the output of Modulator110(5) . . .110(8) are input to digital combiner201(2). Signal S120is input to multiplexer310(1) . . .310(4). If the signal at the control input of multiplexer310(1) . . .310(4) is active, then at the output there is signal S120, otherwise, at the output is value 0. The output signals of multiplexer310(1) . . .310(4) are input to adder unit320, and are added. The output signal of adder unit320is input to subtraction unit330and multiplexer306. Signal S121is input to multiplexer311(1) . . .311(4). If the signal at the control input of multiplexer311(1) . . .311(4) is active, then at the output there is signal S121, otherwise, at the output is value 0. The output signals of multiplexer311(1) . . .311(4) are input to adder unit321, and are added. The output signal of adder unit321is input to subtraction unit331and multiplexer306. Signal S350is signal S360from the paired digital combiner201. Signal S350is input to subtraction unit330and adder unit320. In subtraction unit330, signal S350is subtracted from the output signal of adder unit320. Output signal of subtraction unit330is signal S360. S360is fed to the input of multiplexer306and to the paired digital combiner201. In some embodiments, the digital combiner201(1) has a delay of signal S360. Signal S351is signal S361from the paired digital combiner201. Signal S351is input to subtraction unit331and adder unit321. In subtraction unit331, signal S351is subtracted from the output signal of adder unit321. Output signal of subtraction unit331is signal S361. Signal S361is input to multiplexer306and to the paired digital combiner201. In some embodiments, the digital combiner201(1) has a delay of signal S361. If the signal at the control input of multiplexer306is inactive, then signal S360is fed to the output, and signal S340becomes equal to S360. If the signal at the control input of multiplexer306is inactive, then signal S361is fed to the output, and signal S341becomes equal to S361. If the signal at the control input of multiplexer306is active, then the output signal of unit320is fed to the output, and signal S340becomes equal to the output signal of unit320. If the signal at the control input of multiplexer306is active, then the output signal of adder unit321is fed to the output, and signal S341takes the value of the output signal of adder unit321. Signals S340and S341from the output of digital combiner201(2) are input to DAC202(2) and subtractor mux204. From the output of modulator110(1) . . .110(4), signals S120and S121are input to digital combiner201(1). Digital combiner201(1) operates in a similar mode to digital combiner201(2). From the output of digital combiner201(1) signals S340and S341are input to DAC202(1) and subtractor mux204. FIG.6shows one embodiment using a complex embodiment of WPRN former60with a navigation receiver. In this embodiment, instead of channel with code generator101there is navigation channels400. This embodiment also includes time code mux401(1) . . .401(2). Also, in this embodiment clock CLKch is twice as slow as CLKsend. In this embodiment, navigation channel400(1) . . .400(N*4) are used to generate signals S109, the rest of navigation channels400(with numbers greater than N*4 to N*4+K. Where K is the limit amount of navigation signals which need to be received, it is a sufficient number of channels to receive needed signals) process the signal arriving from subtractor206. Time code mux401(1) . . .401(2) operates at clock speed CLKsend. In one embodiment, before operation, CPU100adjusts navigation channel400(1) . . .400(N*4), modulator110(1) . . .110(8), digital combiner201(1) . . .201(2), subtractor mux204, decimator208, subtractor206, navigation receiver207(for channel numbers are greater than N*4 to N*4+K), and the ratio of clock speeds for CLKsend and CLKch. In this embodiment, navigation Channel400(1) . . .400(N*4) generates signal S109(1) . . . S109(N*4). Signals S109(1) . . . S109(N*2) from outputs of navigation channels400(1) . . .400(N*2) are input to time code mux401(1) where signal S109is selected in time. The output of time code mux401(1) is input to modulator110(1) . . .110(4) where it is scaled and down converted to the intermediate frequency. From the output of Modulator110(1) . . .110(4), signals S120and S121are input to Digital combiner201(1) for further conversion. From the output of digital combiner201(1) they are input to DAC202(1) and subtractor mux204. Signals S109(N*2+1) . . . S109(N*4) from the outputs of navigation Channels400(N*2+1) . . .400(N*4) are input to Time code mux401(2), in this unit signal S109is selected in time. The output of time code mux401(2) is input to modulator110(5) . . .110(8) where it is scaled and down converted to the intermediate frequency. From the output of modulator110(5) . . .110(8) signals S120and S121are input to Digital combiner201(2) for further conversion. From the output of digital combiner201(2) they are input to DAC202(2) and subtractor mux204. DAC202(2) operates at a clock with a half-period delay relative to the clock of DAC202(1). Signals output from DAC202(1) . . . DAC(2) are added in analog sum203, and the obtained signal is close in value to a signal with double the clock rate of DAC is fed to the RF-path123(1). In one embodiment, operation amplifier can serve as analog sum203. RF123(1) path outputs the signals that are then input to antenna124(1). Signals from a selected digital combiner201(1) . . .201(2) pass through subtractor mux204. The output signal of subtractor mux204is input to decimator208. In decimator208, the signal is decimated according to the preset clock ratio of CLKsend and CLKch. The output signal of decimator208is input to Subtractor206. Antenna signal124(2) is input to RF-path123(2). After RF-path123(2) the signal is input to ADC205. Then, the sampled(digitized) signal from the output of ADC205is input to subtractor206. In subtractor206, if CPU100assigns it, the output signal of decimator208is subtracted from the sampled signal from the output of ADC205, and it is fed to the input of navigation receiver207wherein it is processed. In one embodiment, during operation, CPU100controls navigation channel400(1) . . .400(N*4), modulator110(1) . . .110(8), digital combiner201(1) . . .201(2), subtractor mux204, decimator208, subtractor206, and navigation receiver207(the number of Channel400is greater than N*4 to N*4+K). FIG.7shows a schematic of time code mux and navigation channels according to an embodiment. In this embodiment, navigation channel400is used instead of channel with code generator101. Clock CLKch is twice as slow as CLKsend. This embodiment comprises multiplexer500, time control mux501, CRNCO502, code generator503, secondary code buffer504, XOR505, PRN code signal S506, data synchronization signal S507, secondary code signal S508, one bit pseudorandom sequence with data S509, integration period counter510, navigation channel intermediate frequency NCO511, and correlator512. Secondary code buffer504is used to generate secondary code signal S508via which data is transferred. In one embodiment, secondary code buffer504is used as data buffer104. In one embodiment, CPU100initiates and controls modulator110(1) . . .100(4) and subtractor206. Before operation, CPU100initializes the following units in navigation channel400(1) . . .400(N*2): code frequency and initial phase in CRNCO502, code generator503, and secondary code buffer504. In one embodiment, the following units are not used in navigation channel400(1) . . .400(N*4) during operation: integration period counter510, navigation channel intermediate frequency NCO511, and correlator512. In one embodiment, before operation, CPU100initializes navigation channel (greater than N*4 to N*4+K) and, in operation, CPU100controls navigation channels400. CRNCO502generates code frequency which is input to code generator503. Code generator503forms PRN Code S506, which is input to XOR505. Code generator503generates data synchronization signal S507, which is then input to secondary code buffer504. Secondary code signal S508is output from secondary code buffer504and is input to XOR505. Secondary code signal S508at the output of secondary code buffer504is modified according to signal S507. CPU100may additionally write new data to secondary code buffer504. One bit pseudorandom sequence with data S509is output from XOR505. In one embodiment, signal S509is the same as signal S109. Signals S109from Navigation Channels400(1. . . N*4) are fed to Time code mux401(1) and at the input of multiplexer500. Signal S109(S509) is generated at clock CLKch. Time code mux401(1) operates at CLKsend which is twice as much as CLKch. Time control mux501generates at its output a meandering signal which is changed each clock pulse of clock CLKsend. The output signal of time control mux501is input to control input of multiplexer500. If the state at the control input of multiplexer500is inactive, then signals S109(1) . . . S109(N) are output, otherwise, signals S109(N+1) . . . S109(N*2) are output. A signal from the output of unit401(1) is input to modulator110(1) . . .110(4). Navigation Channels400(greater than N*4 to N*4+K) process signals from the output of subtractor206. In one embodiment, a method for forming pseudo-random wideband signals comprises the steps of controlling a frequency and a phase of a plurality of NCOs each associated with a respective one of a set of channels, generating, by one of the plurality of NCOs, a strobe that is output to a PRN code generator, forming, by the PRN code generator, a new sequence element of +1 or −1 in response to the strobe, multiplying, by one of a plurality of multipliers, one of a plurality of weight coefficients by an output of the PRN code generator, outputting, from an adder, a sum of the plurality of multiplier's output signals. multiplying, by a mixer with a quadrature output signal, the adder's output by sine and cosine of a low intermediate frequency, receiving quadrature signals by a transceiver module, and transmitting quadrature signals by the transceiver module, wherein the transceiver module transmits the quadrature signal output from the mixer converted to a radio frequency, and adds the quadrature signal to a quadrature signal received from the antenna and converted to a zero or a near-zero frequency, or replaces the quadrature signal received from the antenna and converted to the zero or the near-zero frequency signal. In one embodiment of the method, the steps of the method mitigate an unwanted signal from one of the transceiver module or a transmitter located within transmission distance of the transceiver module, the unwanted signal being received along with a navigation signal from the antenna. In one embodiment of the method, the steps of the method form a combined signal that comprises a signal received from the antenna and a locally generated signal, the combined signal processed by a GNSS receiver to obtain a position of the GNSS receiver, the combined signal processed as a calibrating signal to calibrate the receiver RF front-end simultaneously with satellite signal reception. The foregoing Detailed Description is to be understood as is in every respect illustrative and exemplary, but not restrictive, and the scope of the inventive concept disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the embodiments shown and described herein are only illustrative of the principles of the inventive concept and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the inventive concept. | 29,313 |
11942949 | DETAILED DESCRIPTION OF THE EMBODIMENTS To make those skilled in the art in the technical field to which the disclosure belongs understand the disclosure more clearly, technical solutions of the disclosure are described in detail below through specific embodiments in combination with accompanying drawings. The embodiments of the disclosure provide a signal correction circuit. As shown inFIG.1, the circuit includes a first signal processing component1, a second signal processing component2, and an output component3. The first signal processing component1is configured to receive an input signal and positive power supply voltages and negative power supply voltages, generate a first control voltage according to the input signal and the positive power supply voltages and negative power supply voltages, control the input signal according to the first control voltage, and output a first voltage. The first voltage is zero within a first time period, and the waveform of the first voltage in a second time period is the same as the waveform of the input signal in the second time period. The input signal is a signal to be corrected. The input signal may be a pulse signal. A rising edge of the pulse signal has a ringback, that is, a non-monotonic condition occurs during the rise of a signal level. The period of the pulse signal is T. The time t1 of a non-monotonic part is the first time period, and the time t2 of a normal part is the second time period. The highest threshold voltage of the ringback part is V1, that is, the waveform of the pulse signal is normal after V1. The first signal processing component1includes a first feedback amplification unit11, and a first NMOS tube Q1. The NMOS tube is a N-type Metal-Oxide-Semiconductor Field-Effect Transistor, that is, a MOSFET tube. The first feedback amplification unit11is configured to receive the input signal and the positive power supply voltages and negative power supply voltages, and generate the first control voltage according to the input signal and the positive power supply voltages and negative power supply voltages. A grid of the first NMOS tube Q1 is electrically connected to an output end of the first feedback amplification unit11, a drain of the first NMOS Q1 tube receives the input signal, and a source of the first NMOS tube Q1 is electrically connected to an input end of the output component3. The first feedback amplification unit11includes a first amplifier U1, a first resistor R1, and a second resistor R2. A negative-phase input end of the first amplifier U1 is connected to the ground GND, and two power supply ends of the first amplifier U1 are respectively connected to a positive supply voltage VCC and a negative positive supply voltage −VCC. A first end of a first resistor R1 receives the input signal, and a second end of the first resistor R1 is connected to a positive-phase input end of the first amplifier U1. A first end of a second resistor R2 is connected to a positive-phase input end of the first amplifier U1, and a second end of the second resistor R2 is connected to an output end of the first amplifier U1. The first amplifier U1 is in a positive and negative feedback amplification state. It can be known from a voltage superposition principle that the positive-phase input end voltage of the first amplifier U1 is that U1+=R2*u1/(R1+R2)+R1*Ua/(R1+R2), u1 is the input signal, Ua is the voltage at node a, and U1− is the negative-phase input end of the first amplifier U1. When U1+=U1−=0, the first amplifier U1 outputs an overturned critical voltage. It can be obtained from the above equation that, when the input signal is that u1=−R1*a/R2, that is, an overturned threshold voltage is output, the threshold voltage is recorded as V1. Since the first amplifier U1 is in an amplified state, when the output is positive, an output signal is VCC; and when the output is negative, an output signal is −VCC. Since the voltage of the node a before hopping is −VCC, it can be obtained that the threshold voltage is that V1=R1*VCC/R2. If R1=0.5*R2, that is, when u1 is greater than 0.5*VCC, Ua is VCC, and on the contrary, Ua is −VCC. For the first NMOS tube Q1, when u1 is less than V1, the first NMOS tube Q1 is turned off. When u1 is greater than V1, the first NMOS tube Q1 is turned on, during t1, the voltage Uc at the node c is 0. During t2, the voltage Uc at the node c is u1. At this moment, the voltage at the node c is equivalent to a waveform in which all ringback part of u1 is changed into 0 and the rest of the time is equal to u1. The first signal processing component1further includes a first capacitor C1, a second diode D1, and a third resistor R3. A first end of the diode D1 receives the input signal through the first capacitor C1, and a second end of the diode D1 is connected to a drain of the first NMOS tube Q1. A Direct Current (DC) offset voltage in the input signal may be filtered away through the first capacitor C1. The input signal is divided into two paths after passing through the first capacitor C1. The first path is input into the positive-phase input end of the first amplifier U1, and the second path is input into a positive electrode of the diode D1. A first end of the third resistor R3 is connected to the output end of the first amplifier U1, and a second end of the third resistor R3 is connected to the source of the first NMOS tube Q1. The second signal processing component2is electrically connected to the first signal processing component1, and is configured to generate a second control voltage according to the first control voltage, perform energy storage charging according to the second control voltage, control an energy storage charging voltage according to the second control voltage, and output a second voltage. The corresponding waveform of the second voltage in the first time period includes a smooth monotonic rising curve and a straight line connected to the smooth monotonic rising curve, and the second voltage is zero in the second time period. The second signal processing component2includes a second feedback amplification unit21, an energy storage unit22, and a second NMOS tube Q2. The second feedback amplification unit21is configured to receive the first control voltage, and generate the second control voltage according to the first control voltage. The energy storage unit22is electrically connected to an output end of the second feedback amplification unit21, and is configured to perform energy storage charging in the first time period. A drain of the second NMOS tube Q2 is connected to the ground GND through the energy storage unit22, a grid of the second NMOS tube Q2 is connected to an output end of the second feedback amplification unit21, and a source of the second NMOS tube Q2 is electrically connected to an input end of the output component3. The second feedback amplification unit21includes a fourth resistor R4, a fifth resistor R5, and a second amplifier U2. A negative-phase input end of the second amplifier U2 is connected to an output end of the first signal processing component1through the fourth resistor R4, a negative-phase input end and an output end of the second amplifier U2 are connected in parallel with the fifth resistor R5, and two power supply ends of the second amplifier U2 are respectively connected to a positive supply voltage VCC and connected to the ground GND. The second amplifier U2 is in a negative feedback state, and meets the characteristics of a virtual short circuit and a virtual open circuit of an operational amplifier. It can be obtained that the voltage of the second amplifier U2 at output node b is that Ub=−R5*a/R4. If R5=R4, it can be obtained that Ub=−Ua. That is, during a period t1, Ub=VCC. During time t2, Ub=−VCC. For the second NMOS tube Q2, during time t1, the second NMOS tube Q2 is turned on, and during time t2, the second NMOS tube Q2 is turned off. During t1, b performs energy storage charging on C2 through R8. This circuit needs to take R1/R2=R8/R7, so that the corresponding voltage value is equal to a threshold voltage V1 when the capacitor C2 reaches a stable state. At the beginning of t1, the voltage waveform at C2 is a linear growth smooth curve, and because the second NMOS tube Q2 is turned on in this time period, the voltage waveform at node d is a smooth monotonic rising curve in a time period t1 and remains stable until it reaches the threshold voltage V1. The effect of correcting the waveform can be achieved by adjusting parameters. Similarly, in a time period t2, the second NMOS tube Q2 is turned off, and the voltage Ud at node d is 0. The signal correction circuit further includes a sixth resistor R6. A first end of the sixth resistor R6 is connected to an output end of the second feedback amplification unit21, and a second end of the sixth resistor R6 is connected to a grid of the second NMOS tube Q2. The sixth resistor R6 is configured to limit the current of the output end of the second amplifier U2. The energy storage unit22includes a second capacitor C2, a seventh resistor R7, and an eighth resistor R8. A first end of the second capacitor C2 is connected to a drain of the second NMOS tube Q2, and a second end of the second capacitor C2 is connected to the ground. The seventh resistor R7 is connected in parallel with the second capacitor C2. A first end of the eighth resistor R8 is connected to an output end of the second feedback amplification unit21, and a second end of the eighth resistor R8 is connected to the ground through the seventh resistor R7. The output component3is electrically connected to each of the first signal processing component1and a second signal processing component2, and is configured to perform superposition processing on the first voltage and the second voltage to obtain an output signal. The output signal is a corrected voltage signal. The waveform of the output signal in the first time period is the same as the waveform of the second voltage in the first time period, and the waveform of the output signal in the second time period is the same as the waveform of the first voltage in the second time period. The output component3includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a third amplifier U3. The ninth resistor R9 is equal to the tenth resistor R10. A first end of the twelfth resistor R12 is connected to the ground GND through the eleventh resistor R11. A positive-phase input end of the third amplifier U3 is connected to each of the output ends of the first signal processing component1and the second signal processing component2through the ninth resistor R9 and the tenth resistor R10 respectively. A negative-phase input end of the third amplifier U3 is connected to the ground GND through the eleventh resistor R11, an output end of the third amplifier U3 is connected to a second end of the twelfth resistor R12, and two power supply ends of the third amplifier U3 are respectively connected to a positive supply voltage VCC and connected to the ground GND. The resistance of the eleventh resistor R 11 is the same as that of the twelfth resistor R12. The third amplifier U3 is in a negative feedback state, and has the characteristics of a virtual short circuit and a virtual open circuit. On the basis that the current at node c is equal to the current at node d, (U3+−Uc)/R9=(Ud−U3+)/R10, R9=R10, U3+ is a positive-phase input end voltage of the third NMOS tube Q3, and U3− is a negative-phase input end voltage of the third NMOS tube Q3, it can be obtained that U3+=0.5*(Uc+Ud). According to a voltage division principle, it is obtained that U3−=Vout*R11/(R11+R12). According to the virtual short circuit, it is obtained that U3+=U3−, and an output signal Vout=0.5*(Uc+Ud)*(R11+R12)/R11=0.5*(1+R12/R11)*(Uc+Ud) is obtained. At this moment, if R11=R12, the output signal is Vout=Uc+Ud. Therefore, the output signal Vout is a smooth rising curve during t1. The waveform during t2 is consistent with the waveform of the input signal u1. Therefore, an input rising edge ringback part is replaced with a smooth curve, and a ringback is corrected and eliminated. In another embodiment provided by the present disclosure, VCC is 5V, C1 is 0.01 uF, C2 is 4.7 Uf, R1 is 5K, R2, R4, R5, R8, R9, R10, R7, R11, and R12 are all 10 K, R3 and R6 are 100K, U1 and U2 are high slew rate optional amplifiers 351, U3 is an ordinary LM307 operational amplifier, D1 is a 1N4007 switching diode, and Q1 and Q2 are AO3402N type MOS tubes. Detailed description is made as follows.1) When there is an input signal u1 input into the circuit, according to the previous equivalent analysis, since R1=0.5*R2, the output a of the U1 is −5V in an interval t1 and the output is 5V in an interval t2. A threshold voltage V1=2.5 V, that is, the ringback in the circuit is located in an interval where the voltage value is less than 2.5 V. According to the actual position of the ringback, the resistance of R1 and R2 are adjusted appropriately to eliminate the ringback.2) At this moment, Q1 is turned off in the interval t1; and when Uc=0, Q2 is turned on, and U2 starts to charge C2 through R8. The voltage Ud at d is equal to the energy storage voltage on the capacitor C2. Since R1/R2=R8/R7=1, the voltage of the capacitor C2 is equal to V1 when it is stable. The corresponding waveform is a monotonically rising smooth curve, so that the output waveforms can be connected at V1. The shape of the curve can be adjusted by adjusting the values of R8 and C2 can be adjusted according to actual needs. Since R11=R12=10k, according to above analysis, it can be obtained that the output is the superposition of Uc and Ud in the interval t1. Therefore, the output is a smooth monotonic rising curve.3) Similarly, in the interval t2, D1 is turned on in one way, which prevents the circuit from backflow to damage a signal source end. The output of U1 is 5V, and Q1 is turned on; the output of U2 is −5V, and Q2 is turned off. At this moment, the output signal Vout is equal to an input signal u1, starts to change from V1, and is equal to u1. In conclusion, the output signal Vout eliminates the ringback in the input signal u1, and the ringback at the rising edge is corrected and eliminated by the circuit. The embodiments of the disclosure further provide a server, which includes the abovementioned signal correction circuit. In conclusion, according to the signal correction circuit and the server provided by the disclosure, a circuit structure is reset to divide the input signal into two paths, which are respectively output into the first signal processing component1and the second signal processing component2. The first signal processing component1eliminates a ringback-containing part in the waveform of the input signal. The second signal processing component2adjusts the ringback-containing part in the waveform of the input signal, and the waveform of an output signal is a smooth monotonic rising curve. Superposition processing is performed on the first voltage output by the first signal processing component1and the second voltage output by the second signal processing component2, and the ringback part in the obtained output signal is completely eliminated. The circuit is redesigned, and various components in the circuit do not need to be debugged and revised for the input signal, so that the cost of debugging, revision, and the like can be reduced, and the input signal is corrected conveniently, stably, and reliably. While preferred embodiments of the disclosure have been described, those skilled in the art can make additional changes and modifications to the embodiments once knowing a basic creativity concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all the changes and modifications falling within the scope of the disclosure. It is apparent that those skilled in the art can make various modifications and variations to the disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the disclosure fall within the scope of the appended claims and their equivalents of the disclosure, the disclosure is also intended to cover the modifications and variations. | 16,346 |
11942950 | DETAILED DESCRIPTION Several embodiments are provided in following descriptions to explain the concept of the present invention. Also, the method in following descriptions can be executed by programs stored in a non-transitory computer readable recording medium such as a hard disk, an optical disc or a memory. Additionally, the term “first”, “second”, “third” in following descriptions are only for the purpose of distinguishing different one elements, and do not mean the sequence of the elements. For example, a first device and a second device only mean these devices can have the same structure but are different devices. FIG.1is a block diagram illustrating an input clock buffer according to one embodiment of the present invention. As illustrated inFIG.1, the input clock buffer100comprises a first capacitor C1, a second capacitor C2, a first amplifier AP1, a second amplifier AP2, a frequency detection circuit103, and a switch SW. The first amplifier AP1is configured to generate a first output signal OS1, comprises a first input terminal coupled to the first capacitor C1and comprises a second input terminal coupled to the second capacitor C2. The first capacitor C1and the second capacitor C2receive a differential input signal DIN and form a first pair of signal paths for the differential input signal DIN. As illustrated inFIG.1, the differential input signal DIN is formed by a first input signal IN1and a second input signal IN2. The second amplifier AP2is configured to generate a second output signal OS2, and also comprises a first input terminal and a second input terminal. The first input terminal of the second amplifier AP2and the second input terminal of the second amplifier AP2form a second pair of signal paths for the differential input signal DIN. The frequency detection circuit103is configured to generate a frequency detection signal FD according to a frequency of the differential input signal DIN. The switch SW is located between an output of the first amplifier AP1and an output of the second amplifier AP2, configured to turn on (conducted) and turn off (non-conducted) according to the frequency detection signal FD. Details of the frequency detection will be described later. In the embodiment illustrated inFIG.1, the frequency detection circuit103generates the frequency detection signal FD according to the reference clock signal RCLK. The frequency of the reference clock signal RCLK corresponds to a frequency of the first output signal OS1, and the frequency of the first output signal OS1corresponds to a frequency of the differential input signal DIN. Therefore, the frequency detection circuit103can generate the frequency detection signal FD according to the frequency of the differential input signal DIN by generating the frequency detection signal FD according to the reference clock signal RCLK. However, please note the frequency detection circuit103can generate the frequency detection signal FD according to the frequency of the differential input signal DIN via any other mechanism rather than the mechanism illustrated inFIG.1. In one embodiment, the switch SW turns on if the frequency of the first output signal OS1is lower than a frequency threshold and turns off if the frequency of the first output signal OS1is higher than the frequency threshold. In other words, the switch SW turns on if the frequency of the first output signal OS1has a low frequency and turns off if the frequency of the first output signal OS1has a high frequency. By this way, since the first output signal OS1and the second output signal OS2are combined to generate the reference clock signal RCLK, the second output signal OS2can be combined to the reference clock signal RCLK if the switch SW turns on when the first output signal OS1has a low frequency. Thereby the non-ideal factors, such as current leakages, of the input terminal of the first amplifier AP1can be improved. In one embodiment, the first input signal IN1is a clock signal and the second input signal IN2is an inverted signal of the first input signal IN1. However, the first input signal IN1and the second input signal IN2can be other kinds of signals.FIG.2is a circuit diagram illustrating circuits for providing the differential input signal DIN illustrated inFIG.1, according to one embodiment of the present invention. In the embodiment ofFIG.2, a circuit200for providing the differential input signal DIN comprises a third capacitor C3, a four capacitor C4, a third amplifier AP3and a fourth amplifier AP4. The third amplifier AP3comprises a first input terminal and a second input terminal, wherein the first input terminal of the third amplifier AP3and the second input terminal of the third amplifier AP3form a third pair of signal paths for a differential clock signal DCLK. The differential clock signal DCLK is formed by a clock signal XCLK and a clock signal XCLKN which is an inverted signal of the clock signal XCLK. The fourth amplifier AP4comprises a first input terminal and a second input terminal, wherein the first input terminal of the fourth amplifier AP4and the second input terminal of the fourth amplifier AP4form a fourth pair of signal paths for the differential clock signal DCLK. The differential input signal DIN is generated according to outputs of the third amplifier AP3and an output of the fourth amplifier AP4. Specifically, the first input signal IN1which can be used to generate the differential input signal DIN is generated according to outputs of the third amplifier AP3and the fourth amplifier AP4. In one embodiment, if the clock signal XCLK and the clock signal XCLKN receive by the third amplifier AP3both have variations (i.e., have rising edges and falling edges), the first input signal IN1is generated according to the output of the third amplifier AP3and the output of the fourth amplifier AP4. However, if one of the clock signal XCLK and the clock signal XCLKN does not vary (i.e., does not have rising/falling edges), for example, the clock signal XCLK is a predetermined voltage level such as a ground level, the output of the third amplifier AP3does not respond the difference between the clock signal XCLK and the clock signal XCLKN but the output of the fourth amplifier AP4still responds the difference between the clock signal XCLK and the clock signal XCLKN due to the capacitors C3, C4. In such case, since the outputs of the third amplifier AP3and the fourth amplifier AP4are connected together, the output of the third amplifier AP3affects the value of the first input signal IN1. By this way, the duty ratio of the first input signal IN1is different from the duty ratio of the clock signal XCLKN. In the embodiment ofFIG.2, the circuit200comprises a fifth capacitor C5, a sixth capacitor C6, a fifth amplifier AP5and a sixth amplifier AP6, but not limited. The fifth capacitor C5, the sixth capacitor C6, the fifth amplifier AP5and the sixth amplifier AP6can be configured to generate the second input signal IN2, and have arrangements and operations the same as the circuit for generating the first input signal IN1. Accordingly, repeated descriptions are omitted for brevity here. In one embodiment, the input signals for generating the differential input signal DIN can be generated by only one kind of amplifier. For example, the first input signal IN1or the second input signal IN2can be generated only according to an amplifier having the structure of the third amplifier AP3. For another example, the first input signal IN1or the second input signal IN2can be generated only according to an amplifier having the structure of the fourth amplifier AP4. Such variation should also fall in the scope of the present invention. The frequency detection circuit103illustrated inFIG.1can be implemented by various circuits. Please refer toFIG.1again, in one embodiment, the input clock buffer100further comprises a delay circuit Xl, configured to generate a delay signal of the first output signal OS1. If the switch SW turns off, the delay signal is the reference clock signal RCLK, and if the switch SW turns on, the reference clock signal RCLK is a combination of the first output signal OS1and the second output signal OS2. The frequency detection circuit103generates the frequency detection signal FD according to edges of the delay signal FIG.3is a schematic diagram illustrating how to generate the frequency detection signal FD illustrated inFIG.1, according to one embodiment of the present invention. In such case, the frequency detection circuit103can comprise a plurality of logic gates (such as NAND gates and NOR gates) and a plurality of inverters to perform the operations illustrated inFIG.3. As shown inFIG.3, the switch SW turns on when the frequency detection signal FD has a high logic level, and turns off when the frequency detection signal FD has a low logic level. Also, the rising edges of the frequency detection signal FD correspond to a delay phase of the rising/falling edges of the reference clock signal RCLK. In one embodiment, a time difference td1exists between a rising edge of the frequency detection signal FD and a rising edge of the reference clock signal RCLK. Also, time difference td2exists between a next rising edge of the frequency detection signal FD and a falling edge of the reference clock signal RCLK. Therefore, the time interval of the high logic level of the frequency detection signal FD can be set via setting time differences td1and td2in the embodiment ofFIG.3. Also, the frequency threshold can be set via setting the time differences td1and td2in the embodiment ofFIG.3. If the frequency of the reference clock signal RCLK is larger than the frequency threshold, the signal period of the reference clock signal RCLK decreases, thus a time interval that the frequency detection signal FD has a high logic level also decreases. If the time interval of the high logic level of the frequency detection signal FD is smaller than td1, the frequency detection signal FD keeps at a low logic, thus the switch SW inFIG.2keeps turning off. In other words, if the time difference td1is a constant value and a frequency of the reference clock signal RCLK is larger than the frequency threshold, the switch SW inFIG.1keeps turns off. The frequency threshold can be set corresponding to different circuit requirements. In one embodiment, the frequency threshold is 200 MHz. FIG.4is a block diagram illustrating an input clock buffer400according to another embodiment of the present invention. Besides the components illustrated inFIG.1, the input clock buffer400further comprises a DC level providing circuit, which is coupled to the first capacitor C1, the second capacitor C2, the first input terminal of the first amplifier and the second input terminal of the first amplifier AP1. The DC level providing circuit is configured to provide a DC level to the differential input signal DIN after the DC component thereof is filtered. In the embodiment ofFIG.4, the DC level providing circuit comprises resistors R1, R2, R3, R4, which form a voltage divider. Also, in one embodiment, the resistors R1, R2, R3, R4provide a DC voltage level of VDD/2. FIG.5is a schematic diagram illustrating operations of the input clock buffer inFIG.4when the switch turns off, according to one embodiment of the present invention. That is, in the embodiment ofFIG.5, a frequency of the differential input signal DIN is higher than the frequency threshold. Please note, in order to simplify the drawing, only the first input signal IN1is illustrated, and the second input signal IN2which is an inverted signal of the first input signal IN1is not illustrated. Also, the signal IN1′ which is received by the first terminal of the first amplifier AP1means the DC component of the first input signal IN1is filtered by the first capacitor C1and then re-provided by the DC level providing circuit. As shown inFIG.5, the frequency detection signal FD keeps at a low logic level, thus the switch SW turns off. Therefore, the output of the second amplifier AP2is not coupled to the output of the first amplifier AP1, and the output clock signal of the input clock buffer400is only affected by the output of the first amplifier AP1. Thus, the duty ratio of the output clock signal RCLK (the reference clock signal) can approach the desired value as the duty ratio of IN1. FIG.6is a schematic diagram illustrating operations of the input clock buffer inFIG.4when the switch turns on, according to one embodiment of the present invention. That is, in the embodiment ofFIG.6, a frequency of the differential input signal DIN is lower than the frequency threshold. Please note, in order to simplify the drawing, only the first input signal IN1is illustrated, and the second input signal IN2which is an inverted signal of the first input signal IN1is not illustrated. Also, the signal IN1′ which is received by the first terminal of the first amplifier AP1means the DC component of the first input signal IN1is filtered by the first capacitor C1and then re-provided by the DC level providing circuit. In the embodiment ofFIG.6, since the frequency of the differential input signal DIN is low, some leakage currents may flow to the ground through the DC level providing circuit. Therefore, the DC level of the first input signal IN1decreases, and the DC level of the signal IN1′ correspondingly decreases. In such case, the switch SW turns on corresponding to the high logic level of the frequency detection signal FD. By this way, the DC level of the signal IN1′ can be compensated since the output of the first amplifier AP1is coupled to the output of the second amplifier AP2. FIG.7is a flow chart illustrating a clock signal buffering method according to one embodiment of the present invention, which comprises following steps: Step701 Filter a DC component of a differential input signal DIN. Step703 Form a first pair of signal paths for the differential input signal DIN by input terminals of a first amplifier AP1after filtering the DC component. Step705 Generate a first output signal OS1by the first amplifier AP1. Step707 Form a second pair of signal paths for the differential input signal DIN by input terminals of a second amplifier AP2. Step709 Generate a second output signal OS2by the second amplifier AP2. Step711 Generate a frequency detection signal FD according to a frequency of the differential input signal DIN. Step713 Selectively couple an output of the first amplifier AP1and an output of the second amplifier AP2according to the frequency detection signal FD. Other detail steps can be acquired based on above-mentioned embodiments, thus are omitted for brevity here. Please note, the clock signal buffering method is not limited to be performed by the input clock buffer shown inFIG.1andFIG.4. In view of above-mentioned embodiments, the duty ratio of the output clock signal can keep accurate even if the DC level of the differential input signal varies. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 15,300 |
11942951 | DETAILED DESCRIPTION An example of circuitry that may be used in some embodiments to detect signal transients is illustrated in the functional block diagram ofFIG.1. An input node of buffer amplifier102is coupled to a signal source104. In embodiments where the signal source104is a household alternating current (AC) power supply, the coupling may be performed using a plug configured to fit a conventional AC power socket. The configuration of the plug and the socket may vary in different countries, and different configurations may be used in different embodiments as appropriate. In general, the signal source104is not itself a portion of the embodiments described herein, rather, the circuitry is configured to be releasably couplable to the signal source (e.g. capable of being directly or indirectly attached to or detached from the signal source). A capacitor106is provided, which may be referred to as a hold capacitor. Capacitor106may be a single capacitor device, or, in some embodiments, it may include more than one capacitor device configured to perform cooperatively as a hold capacitor. The buffer amplifier102has an output node, and a first switchable unidirectional current path108is provided between the capacitor106and the first unidirectional current path108. The first unidirectional current path selectively allows current flow from the capacitor to the output node under conditions described in further detail below. Comparator circuitry110is further provided to operate in response to the voltage on the capacitor106. In some embodiments, in response to a voltage on the capacitor being above an upper threshold, the comparator circuitry110is operative to open the first switchable unidirectional current path to substantially prevent current flow therethrough. In some embodiments, the upper threshold is a predetermined upper voltage threshold VThU. In some embodiments, a second switchable unidirectional current path112is provided between the output node of the buffer amplifier102and the capacitor106. The second unidirectional current path112selectively allows current flow from the output node to the capacitor. In some embodiments, in response to a voltage on the capacitor below a lower threshold, the comparator circuitry110is operative to open the second switchable unidirectional current path112to substantially prevent current flow therethrough. In some embodiments, the lower threshold is a predetermined lower voltage threshold VThL. In some embodiments, an analog-to-digital converter (ADC)114is coupled directly or indirectly (e.g. through additional buffering and/or filtering circuitry) to the capacitor106to sample the voltage on the capacitor106. In some embodiments, the ADC may be configured to sample the voltage in response to the voltage exceeding the upper threshold and/or falling below the lower threshold, in which case the ADC may be triggered to perform a reading by the comparator circuitry. In some embodiments, the ADC may read the voltage periodically, e.g. with a sampling rate of 120 Hz or any other sampling rate as appropriate to the desired use. The sampling may be performed, for example, at or above the Nyquist rate of the nominal signal as appropriate to the desired use. In some embodiments, the ADC may provide a digital signal representative of the voltage to a microcontroller116. In some embodiments, the ADC114may be a component of the microcontroller116. In some embodiments, after the voltage on the capacitor106has been read using the ADC114, one or more signals from the microcontroller116are provided to the first unidirectional current path108and/or to the second unidirectional current path112to close those current paths to allow current to flow therethrough. In some embodiments, a filter118, such as a high-pass filter or other frequency-dependent filter, may be provided between the capacitor106and the comparator circuitry110. In other embodiments, the filter118is not included. Some embodiments further include a low-pass filter (not illustrated) between the hold capacitor and the analog-to-digital converter. An example of operation of a system as illustrated inFIG.1, is illustrated inFIG.2. A signal is provided (202) to the capacitor. The signal may be provided directly or indirectly through componentry such as a buffer amplifier and/or a voltage divider. A comparison is made (204) between the voltage on the capacitor and an upper threshold voltage. In response to a determination (206) that the voltage on the capacitor is greater than the upper threshold, the signal is at least temporarily prevented (208) from discharging the capacitor, e.g. by opening the first unidirectional current path108. A first voltage value is read (210) from the capacitor. Subsequently, the capacitor voltage may be reset (212), e.g. by closing the first unidirectional current path108. The reading of the voltage may take place between the time the signal is prevented from discharging the capacitor (208) and the time the capacitor voltage is reset (212). For example, this may be between the time the first unidirectional current path108is opened and the time the first unidirectional current path108is closed. In some embodiments, the reading of the voltage is performed in response to (e.g. triggered by) the voltage exceeding the upper threshold. In other embodiments, the voltage may be sampled periodically including at the time during which the first unidirectional current path108is closed. According to such a method, the voltage on the capacitor generally follows the voltage of the signal as long as the signal is permitted to both charge the capacitor (through the second unidirectional current path) and to discharge the capacitor (through the first unidirectional current path). However, in response to a determination that the signal exceeds the upper threshold, which may indicate a transient, the capacitor is prevented from discharging through the first unidirectional current path, allowing for a stable measurement of the transient to take place before the capacitor is discharged. In further aspects of a method performed in some embodiments, a comparison is made (214) between the voltage on the capacitor and a lower threshold voltage. In response to a determination (216) that the voltage on the capacitor is less than the lower threshold, the signal is at least temporarily prevented (218) from discharging the capacitor, e.g. by opening the second unidirectional current path112. A voltage value is read (210) from the capacitor. Subsequently, the capacitor voltage may be reset (212), e.g. by closing the second unidirectional current path112. The reading of the voltage may take place between the time the signal is prevented from discharging the capacitor (218) and the time the capacitor voltage is reset (212). For example, this may be between the time the second unidirectional current path112is opened and the time the second unidirectional current path112is closed. In some embodiments, the reading of the voltage is performed in response to (e.g. triggered by) the voltage falling below the lower threshold. In other embodiments, the voltage may be sampled periodically including at the time during which the first unidirectional current path112is closed. As described above, the voltage on the capacitor generally follows the voltage of the signal as long as the signal is permitted to both charge the capacitor (through the second unidirectional current path) and to discharge the capacitor (through the first unidirectional current path). However, in response to a determination that the signal falls below the lower threshold, which may indicate a transient, the capacitor is prevented from charging through the second unidirectional current path, allowing for a stable measurement of the transient to take place before the capacitor is again charged. In some embodiments, the signal that is provided (202) to the capacitor is a signal that represents the voltage of an alternating current (AC) power supply. The signal may be provided directly or indirectly through componentry such as a buffer amplifier and/or a voltage divider. In this way, the signal provided to the capacitor may be, for example, scaled down as compared to the relatively high voltage signal of the AC power supply itself. Similarly, the signal provided to the capacitor may be a signal to which a voltage offset has been applied. A voltage offset may be applied, for example, such that the voltage applied to the capacitor is always positive (relative to a ground voltage level) even when the AC power supply voltage (or other signal of interest) is negative. A schematic illustration of a circuit that can be used in some embodiments is provided inFIG.3. The circuit ofFIG.3includes a capacitor302, which may be a hold capacitor with capacitance CHold. The capacitor includes a first capacitor terminal303. A second terminal of the capacitor may be coupled (directly or indirectly) to ground. A buffer amplifier304is provided. In some embodiments, the buffer has an open-loop DC gain of at least 60 dB. In some embodiments, the buffer has a gain-bandwidth product of at least 8 MHz. In other embodiments, however, the buffer amplifier may have other gain values. The buffer amplifier has an output node306. The circuit includes a first current path between the output node306and the capacitor terminal303. The first current path includes, in series, a first switch308and a first diode310. The first diode is oriented to prevent current flow from the output node to the capacitor terminal. The circuit further includes a second current path between the output node306and the capacitor terminal303. The second current path has, in series, a second switch312and a second diode314, the second diode being oriented to prevent current flow from the capacitor terminal to the output. Comparator circuity is provided including a first comparator316and a second comparator318. One or more of the comparators may be implemented using an operational amplifier (op amp). The first comparator316is configured to open the first switch308in response to a determination that a voltage on the capacitor terminal303is above an upper threshold VThU. The second comparator318is configured to open the second switch312in response to a determination that a voltage on the capacitor terminal303is below a lower threshold VThL. In some embodiments, the comparator upper threshold voltage VThUand the lower threshold voltage VThLare provided to their respective comparators as reference voltages, which may be generated using, for example, voltage dividers or other techniques. In the example ofFIG.3, while the voltage on the capacitor terminal303is below the upper threshold voltage VThU, the comparator316outputs a HIGH (or “1”) value that closes the first switch308. If the voltage on the capacitor terminal303goes above the upper threshold voltage VThU, the comparator316outputs a LOW (or “0”) value that opens the first switch308(except under reset conditions, discussed below). Similarly, while the voltage on the capacitor terminal303is above the lower threshold voltage VThL, the comparator316outputs a HIGH (or “1”) value that closes the second switch312. If the voltage on the capacitor terminal303goes below the lower threshold voltage VThL, the comparator316outputs a LOW (or “0”) value that opens the second switch312(except under reset conditions, discussed below). A node320is provided through which the circuit may be coupled (directly or indirectly to an analog to digital converter, such as ADC114. In some embodiments, the coupling between node320and the ADC is accomplished through either or both of a buffer amplifier and a filter (such as a low-pass filter). In some embodiments, a node322is provided to supply an output (e.g.IRQ_1) that may be used to represent the output of the first comparator316. The output provided at node322may be used in some embodiments (e.g. by the microcontroller116) to trigger the reading by an ADC (e.g. ADC114) of the voltage at node320in response to the voltage exceeding the threshold VThU. The voltage read at node320represents a possibly filtered, scaled, offset, and/or buffered version of the voltage on the capacitor terminal303. In this way, the voltage read at the node320may be used characterize a positive transient voltage at an input node (e.g. node324) without requiring a high sampling rate from the ADC114and without imposing high processing requirements on the microcontroller116. In some embodiments, a node326is provided to supply an output (e.g.IRQ_2) that may be used to represent the output of the second comparator318. The output provided at node326may be used in some embodiments (e.g. by the microcontroller116) to trigger the reading by an ADC (e.g. ADC114) of the voltage at node320in response to the voltage falling below the threshold VThL. In this way, the voltage read at the node320may be used characterize a negative transient voltage at an input node (e.g. node324) without requiring a high sampling rate from the ADC114and without imposing high processing requirements on the microcontroller116. Some embodiments are configured as shown inFIG.3to detect and allow measurement of both positive and negative transient voltages. Other embodiments may be configured to detect and allow measurement only of positive transients or only of negative transients. In some embodiments, a first reset control node328(RESET_1) is provided. The first comparator316and the first reset control node328are coupled to the first switch308through a first OR gate331. In this way, the first switch308is closed not only in response to a HIGH signal from the comparator316but also in response to a HIGH signal from RESET_1. In some embodiments, the microcontroller116applies a HIGH signal to RESET_1after the voltage characterizing a positive transient has been read from node320. In some embodiments, a signal applied to RESET_1may be used to perform a reset operation212as described above. In some embodiments, a second reset control node330(RESET_2) is provided. The second comparator318and the second reset control node330are coupled to the second switch312through a second OR gate332. In this way, the second switch312is closed not only in response to a HIGH signal from the comparator318but also in response to a HIGH signal from RESET_2. In some embodiments, the microcontroller116applies a HIGH signal to RESET_2after the voltage characterizing a negative transient has been read from node320. In some embodiments, a signal applied to RESET_2may be used to perform a reset operation212as described above. In some embodiments, a filter334(e.g. a frequency-specific filter such as a band-pass filter) may be provided between the capacitor terminal303and the comparators316and/or318. In such embodiments, the comparators316and318may be most sensitive to detecting transients that correspond to the frequency characteristics defined by the filter334. In other embodiments, however, no filter is provided between the capacitor terminal303and the comparators316and/or318. In some embodiments, a resistive path is provided between capacitor terminal303and ground (or to another predetermined voltage level) to allows for a slow discharge of the capacitor regardless of the open or closed state of the first and second unidirectional current paths. WhileFIG.3shows an embodiment in which switches308and312are closed by a HIGH (or “1”) signal and opened by a LOW (or “0”) signal, and in which the comparator circuitry uses a LOW signal to indicate a voltage excursion outside the range of (VThL, VThU), it should be understood that other types of signaling may be used, for example with one or more switches being closed by a LOW parameter and the output of one or more of the comparators and other logical components (such as OR gates331,332) being adjusted accordingly. An example of one such embodiment is illustrated inFIG.4. FIG.4illustrates a circuit according to some embodiments in which the switches in the switchable unidirectional current paths are implemented using transistors. The circuit ofFIG.4includes a capacitor402, which may be a hold capacitor with capacitance CHold. The capacitor includes a first capacitor terminal403. A second terminal of the capacitor may be coupled (directly or indirectly) to ground or to another predetermined voltage level. A buffer amplifier404is provided. In some embodiments, the buffer has an open-loop DC gain of at least 60 dB. In some embodiments, the buffer has a gain-bandwidth product of at least 8 MHz. In other embodiments, however, the buffer amplifier may have other gain values. The buffer amplifier has an output node406. In some embodiments, an input node424of the buffer amplifier404is releasably coupled (e.g. through a two- or three-prong connector or other power plug) to a household AC power supply405. A voltage divider407is also provided between the AC power supply405and the buffer amplifier404to scale down the power supply voltage to a more manageable level for signal processing. In some embodiments, a direct current (DC) offset is also applied to the input voltage so that the signal at input node424is positive even when the power supply voltage is negative. The circuit includes a first current path between the output node406and the capacitor terminal403. The first current path includes, in series, a first transistor408and a first diode410. The first diode is oriented to prevent current flow from the output node to the capacitor terminal. In the circuit ofFIG.4, the first transistor408is an NPN bipolar junction transistor. The circuit further includes a second current path between the output node406and the capacitor terminal403. The second current path has, in series, a second transistor412and a second diode414, the second diode being oriented to prevent current flow from the capacitor terminal to the output. In the circuit ofFIG.4, the second transistor412is a PNP bipolar junction transistor. In some embodiments, the bipolar junction transistors408,412are selected to have a very low storage time, as a lower storage time may improve the maximum surge holding accuracy. In some embodiments, N and P channel MOSFETs are used in the circuit in place of the NPN and PNP bipolar junction transistors described above. In such embodiments, the buffer circuit may be configured to meet the Vgsturn-on threshold requirements of the MOSFETs. Because the voltage of the AC power source405may be quite high, with the voltage of any superimposed transients potentially being even higher, the downscaling of the input voltage for processing (e.g. by the voltage divider407) may be sufficiently great to result in a relatively low voltage difference between capacitor terminal403and buffer output node406during normal operation. In some embodiments, to allow for a sufficient voltage difference between terminal403and node406to permit operation of the transistors408,412, the diodes410,414may be Schottky diodes, which generate less of a voltage drop than PN junction diodes. Comparator circuity is provided including a first comparator416and a second comparator418. One or more of the comparators may be implemented using an operational amplifier (op amp). The first comparator416is configured to bias transistor408into cut-off mode in response to a determination that a voltage on the capacitor terminal403is above an upper threshold VThU. The second comparator418is configured to bias transistor412into cut-off mode in response to a determination that a voltage on the capacitor terminal403is below a lower threshold VThL. In some embodiments, the comparator the upper threshold voltage VThUand the lower threshold voltage VThLare provided to their respective comparators as reference voltages, which may be generated using, for example, voltage dividers or other techniques. In the example ofFIG.4, while the voltage on the capacitor terminal403is below the upper threshold voltage VThU, the comparator416outputs a HIGH (or “1”) value that drives the first transistor408into saturation mode, corresponding to a closed switch state. If the voltage on the capacitor terminal403goes above the upper threshold voltage VThU, the comparator416outputs a LOW (or “0”) value that drives the first transistor408into cut-off mode (except under reset conditions, discussed below), corresponding to an open switch state. Conversely, while the voltage on the capacitor terminal403is above the lower threshold voltage VThL, the comparator418outputs a LOW (or “0”) value that drives the second transistor412into saturation mode, corresponding to a closed switch state. If the voltage on the capacitor terminal403goes below the lower threshold voltage VThL, the comparator418outputs a HIGH (or “1”) value that drives the second transistor412into cut-off mode (except under reset conditions, discussed below), corresponding to an open switch state. A node420is provided through which the circuit may be coupled (directly or indirectly to an analog to digital converter, such as ADC114. In some embodiments, the coupling between node420and the ADC is accomplished through either or both of a buffer amplifier (such as op amp421) and a filter (such as a low-pass filter). In some embodiments, a node422is provided to signal an output (e.g.IRQ_1) that may be used to represent the output of the first comparator416. The output provided at node422may be used in some embodiments (e.g. by the microcontroller116) to trigger the reading by an ADC (e.g. ADC114) of the voltage at node420in response to the voltage exceeding the threshold VThU. The voltage read at node420represents a possibly filtered, scaled, offset, and/or buffered version of the voltage on the capacitor terminal403. In this way, the voltage read at the node420may be used characterize a positive transient voltage at the AC power supply405without requiring specialized high-speed, high-voltage, or high-frequency circuitry. In some embodiments, a node426is provided to signal an output (e.g. IRQ_2) that may be used to represent the output of the second comparator418. The output provided at node426may be used in some embodiments (e.g. by the microcontroller116) to trigger the reading by an ADC (e.g. ADC114) of the voltage at node420in response to the voltage falling below the threshold VThL. In this way, the voltage read at the node420may be used characterize a negative transient voltage at the AC power supply405without requiring specialized high-speed, high-voltage, or high-frequency circuitry. A circuit as shown inFIG.4thus allows for measurement and characterization of both positive and negative transients in the AC power supply voltage. Some embodiments are configured as shown inFIG.4to detect and allow measurement of both positive and negative transient voltages. Other embodiments may be configured to detect and allow measurement only of positive transients or only of negative transients. In some embodiments, a first reset control node428(RESET_1) is provided. The first reset control node428is coupled to the base of the first transistor408. In this way, the first transistor408is driven into saturation mode (corresponding to a closed state) not only in response to a HIGH signal from the comparator416but also in response to a HIGH signal from RESET_1. In some embodiments, the microcontroller116applies a HIGH signal to RESET_1after the voltage characterizing a positive transient has been read from node420. In some embodiments, a signal applied to RESET_1may be used to perform a reset operation212as described above. In some embodiments, a second reset control node430(RESET_2) is provided. The second reset control node430is coupled to the base of the second transistor412. In this way, the second transistor412is driven into saturation mode (corresponding to a closed state) not only in response to a LOW signal from the comparator418but also in response to a LOW signal fromRESET_2. In some embodiments, the microcontroller116applies a LOW signal toRESET_2after the voltage characterizing a negative transient has been read from node420. In some embodiments, a signal applied toRESET_2may be used to perform a reset operation212as described above. A circuit as shown inFIG.1,3, or4may be described as a conditional track and hold amplifier (CTHA). Such circuits may be used as a component of an analog-to-digital signal processing chain. The signal voltages may be scaled, level-shifted, and/or buffered appropriately to meet the goals of a given deployment. In some embodiments, additional circuitry may be provided to stabilize the op amp and comparators, depending on the component selection. While other implementations may be used, the implementation ofFIGS.3and4uses one buffer op amp, two comparators, two switches, two diodes, one capacitor, and two optional OR gates. In an example CTHA, the op amp (e.g.102,304,404) tracks the incoming signal as long as its amplitude is less than VThUand greater than VThL. When the signal amplitude is within this range, both switches are closed allowing both diodes to conduct in their respective direction and the voltage on CHoldtracks the voltage of the incoming signal. If the signal amplitude goes above VTHU, the first switch (e.g.308or408) opens, preventing the voltage on CHoldfrom being pulled in the negative direction, therefore holding the positive peak. Likewise, if the signal amplitude goes below VThL, the second switch (e.g.312or412) opens, preventing the voltage on CHoldfrom being pushed in the positive direction, therefore holding the negative peak. The outputs (e.g.322,326,422,426) of the comparators (e.g.316,318,416,418) may be provide to an input GPIO (general-purpose input/output) of a microcontroller (MCU) and can be used as indicators that a peak has been captured. Similarly, GPIO outputs from the MCU connected to the switches, e.g. through OR gates, may be used to temporarily force the switches closed to re-center the voltage on CHold. This may be done after a peak has been recognized by the data acquisition system. FIG.5is a schematic diagram of the circuit ofFIG.4with additional features one or more of which may be used in some embodiments to enhance the stability of the circuit. As the circuit ofFIG.4includes two high gain stages in series, namely the buffer amplifier404and the comparators416,418, it is susceptible to oscillation. Buffer amplifier404may be susceptible to oscillation at high frequencies. In some embodiments, a capacitor502is be provided to limit high-frequency gain and prevent high-frequency oscillation. However, the capacitor502may not be needed in all embodiments. In some embodiments, additional componentry is provided to reduce or eliminate the possibility of low-frequency oscillations. In some embodiments, a high impedance bias network504coupled to a voltage source505is provided to pull the voltage of the hold capacitor402back toward the tracking range (e.g. between VThLand VThU) regardless of the operation of the transistors408and412. The connection between the hold capacitor402and the bias network504may be an unswitched coupling that allows at least some current flow regardless of the states of transistors408,412, so long as there is a voltage difference between the hold capacitor and the output of the bias network. In normal operation, a (positive or negative) peak is held by opening up the feedback loop at transistor408or412by turning one of these transistors off, putting the circuit in “hold” mode, and capturing the peak voltage on capacitor402. When the surge goes away, the buffer amplifier404is working to generate an output to match the incoming signal at node424. As the amplitude of the regular signal is less than the peak, the buffer amplifier404is operating to pull the voltage of the hold capacitor402back into the tracking range. But the transistor that would allow the hold capacitor voltage to pulled into the tracking range was turned off by the last peak. As a result, there is a risk of the buffer amplifier404swinging all the way in the opposite direction, but it is prevented from doing so until transistor(s)408and/or412are reset by injecting current into their bases, or until the high-impedance bias network504slowly pulls capacitor402back into the tracking range (“track” mode). However, with buffer amplifier404providing its maximum output at a voltage opposite of the last peak, when the feedback loop is closed again, the hold capacitor402is quickly charged up to a new peak of the opposite polarity. There is a risk of that peak being mistakenly detected as a transient by the opposite comparator, and the loop is opened up again, placing the circuit back into “hold” mode, but with a peak of the opposite polarity. In this event, there is a risk of a low-frequency oscillation in which the circuit alternates between “detecting” peaks of opposite polarity each time it is reset. To address this type of potential low-frequency oscillation, some embodiments operate to shift the threshold voltages provided to the comparator. For example, in response to a voltage on the capacitor402exceeding the upper threshold, the lower threshold voltage may temporarily be lowered. Conversely, in response to a voltage on the capacitor402dropping below the lower threshold, the upper threshold voltage may temporarily be raised. This reduces or eliminates the likelihood that a reset operation, performed after detection of one peak, spuriously triggers detection of an opposite peak. In some embodiments the changes to the threshold voltages are performed using circuitry as shown inFIG.5. The upper threshold VThUis provided through upper threshold voltage supply circuitry508that includes a voltage divider having an output node510with a capacitive path512to ground. The voltage supply circuitry508is coupled to a voltage source511. The output node510is coupled through a diode514to the output of the second comparator418. In “track” mode, the output of comparator418is low, and the coupling through diode514has no substantial effect on the upper threshold voltage VThU. However, when the voltage on capacitor402falls below the lower threshold VThL, the resulting voltage at the output of the second comparator418, acting through diode514, drives the upper threshold voltage VThUhigher. The capacitor512temporarily keeps the threshold voltage VThUat an elevated level for a short period even after the second comparator returns to a low output voltage. This way, even if there is a voltage swing from low to high during a reset operation, the voltage swing is less likely to exceed the temporarily-elevated threshold voltage VThUand thus is less likely to trigger a spurious peak detection and possible oscillation. A similar arrangement is provided to temporarily lower the lower threshold. The lower threshold VThLis provided using lower threshold voltage supply circuitry516that includes a voltage divider having an output node518with a capacitive path520to ground. The voltage supply circuitry516is coupled to a voltage source517. The output node518is coupled through a diode522to the output of the first comparator416. In “track” mode, the output of comparator416is high, and the coupling through diode522has no substantial effect on the lower threshold voltage VThL. However, when the voltage on capacitor402rises above the upper threshold VThH, the resulting low voltage at the output of the first comparator416, acting through diode522, pulls the lower threshold voltage VThLeven lower. The capacitor520temporarily keeps the threshold voltage VThLat the lowered level for a short period even after the first comparator returns to a higher output voltage. This way, even if there is a voltage swing from high to low during a reset operation, the voltage swing is less likely to drop below the temporarily-lowered threshold voltage VThLand thus is less likely to trigger a spurious peak detection and possible oscillation. Thus, with the use of the cross-connected diodes514and522in conjunction with capacitors512and520, when one comparator detects a surge, its output shifts the threshold of the other comparator to a more extreme level, keeping it from detecting the opposite peak when corning out of “hold” mode, and then returning to the regular thresholds as capacitors512and520discharge to their normal levels. In a further feature used in some embodiments to address potential low-frequency oscillation, the “reset” signals are applied simultaneously by the microcontroller116during a reset operation to exit the “hold” mode. This forces the transistors408,412closed, completing the “track” mode feedback loop and overpowering the comparator outputs which drive the bases of those transistors with more than twice the impedance. Once the buffer amplifier404is back in tracking range, both resets are then released, and the circuit will track again until one of the comparators is tripped by a new surge on the incoming signal. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Other variations of the described embodiments are contemplated. The above-described embodiments are intended to be illustrative, rather than restrictive, of the present invention. The scope of the invention is thus not limited by the examples given above but rather is defined by the following claims. | 33,883 |
11942952 | DETAILED DESCRIPTION FIG.1shows a block diagram of a frequency generation circuit100according to one exemplary embodiment. For simplicity,FIG.1only shows the elements of the frequency generation circuit100necessary to facilitate the description provided herein. It will be appreciated by those skilled in the art that the frequency generation circuit100may include additional components and/or signal connections not shown inFIG.1. Frequency generation circuit100includes an oscillator110coupled to control circuitry115that controls the amplitude of the oscillator output. Oscillator110includes a first control input (CTRL1), a second control input (CTRL2), and an output (OUT). The oscillator110may comprise a crystal oscillator, or any other negative resistance-based oscillator that includes a resonant circuit112operatively connected to a negative resistance circuit114. In one exemplary embodiment, the resonant circuit112may comprise a crystal, and the negative resistance circuit114may comprise an amplifier (not shown). First and second control signals, S1and S2, applied to the respective first and second control inputs control the amplitude of the signal Soat the output of the oscillator110. In particular, the first control signal S1provides time-continuous control of the amplitude of So, while the second control signal S2provides time-discrete control of one or more amplitude regulating parameters of the oscillator110, as described further below. Exemplary amplitude regulating parameters include, but are not limited to, an oscillator bias current, a number of active oscillator gmcells, a bias point of one or more of the oscillator gmcells, and/or a variable resistance connected in parallel with a core of the oscillator110. Because the second control signal S2controls the configuration of the oscillator110, S2enables the relaxation of the requirements that would otherwise be placed on the time-continuous amplitude control provided by the first control signal S1. The control circuitry115generates the first and second control signals S1, S2responsive to the oscillator output signal Soaccording to the exemplary method200ofFIG.2. More particularly, the control circuitry115comprises a detector120, a first feedback path130, and a second feedback path140. The detector120, which is coupled between the oscillator output and the inputs of the first feedback path130and the second feedback path140, detects an amplitude A of the oscillator output signal So(block210). The first feedback path130provides time-continuous control of the amplitude of the oscillator output signal Soby continuously controlling the first control signal S1responsive to the detected amplitude A (block220). The second feedback path140provides time-discrete control of one or more amplitude regulating parameters of the oscillator110by controlling, in discrete time, the second control signal S2responsive to the detected amplitude A (block230). For example, the second control signal may provide time-discrete control of the parameter(s) controlling the operation of the negative resistance circuit114. By controlling the amplitude regulating parameter(s) of the oscillator110, the second feedback path140allows the first feedback path130to operate at a lower gain, and therefore at a lower power and with less noise. FIG.3shows a block diagram of the first feedback path130according to one exemplary embodiment. In this embodiment, the first feedback path130includes an amplifier132and a filter134. The detected amplitude A, as well as a reference amplitude Aref, are input to amplifier132. Amplifier132amplifies the amplitude error Aerrformed from the difference between the detected amplitude A and the reference amplitude Aref, and filter134helps reduce the noise input to the oscillator110by low-pass filtering the amplified signal to generate the first control signal S1. The first control signal S1controls the gain of the oscillator core by controlling the gain of the negative resistance circuit114. In so doing, the first control signal S1controls the amplitude of the oscillator output signal So. Amplifier132establishes the gain of the first feedback path130. Because various environmental conditions, oscillator properties, and/or the age of the oscillator110, may impact the ability of the first control signal S1to sufficiently control the amplitude of the oscillator output signal So, conventional systems tend to set the gain of amplifier132to account for a wide range of conditions, even if some of the more extreme conditions are very rare. For example, higher temperatures may reduce the gain of the oscillator core relative to what that gain would be with the same input control signal at regular operating temperatures. Conventional solutions address this problem by making sure the gain of amplifier132is high enough to enable the oscillator core to handle even extreme temperature conditions without dropping the amplitude of the oscillator output Sobelow a desired level. Such high gain conditions, however, cause amplifier132to consume more power and to insert more noise into the oscillator core than would otherwise be necessary for many operating conditions. The solution presented herein incorporates the second feedback path140into the control circuitry115to control the amplitude regulating parameter(s) of the oscillator110, which allows the first feedback path130to be designed and configured for a lower gain. Such gain reduction in the first feedback path130will enable the frequency generation circuit100to operate at a lower power and will reduce the noise level input to oscillator110. To that end, the second feedback path140controls one or more amplitude regulating parameters responsive to the detected amplitude A of the oscillator output signal So. For example, if the detected amplitude A drops too low, indicating that the first control signal is unable to sufficiently amplify the oscillator amplitude, the second feedback path140may adjust the amplitude regulating parameters, e.g., by increasing the bias current, increasing the number of active oscillator gm cells, and/or increasing a bias point of one or more of the active gmcells. Alternatively or additionally, the second feedback path140may adjust the amplitude regulating parameters by increasing the resistance of a variable resistance connected in parallel with the oscillator core, e.g., using a variable resistor116connected across differential outputs of the oscillator110. In another example, if the detected amplitude A rises too high, indicating the amplitude of the oscillator output signal So, is too high, the second feedback path140may decrease the bias current, decrease the number of active oscillator gmcells, decrease a bias point of one or more of the active gmcells, and/or decrease the resistance of the variable resistor116connected in parallel with the core of the oscillator110. In either case, the second feedback path140adjusts the amplitude regulating parameter(s) for the current operating conditions as indicated by the detected amplitude A to enable the oscillator110to maintain the desired amplitude at the output without requiring the first feedback path130to have a high gain. Because the gain of amplifier132is designed to handle most operating conditions, the control provided by the second feedback path140may be implemented in a time-discrete manner. For example, the second feedback path140may include a control circuit142, as shown inFIG.4. Control circuit142may control the amplitude regulating parameter(s) of the oscillator in a time-discrete manner by only controlling the amplitude regulating parameter(s) when the detected amplitude A satisfies one or more predetermined conditions, e.g., threshold conditions. For example, the control circuit142may control the second control signal S2to control the amplitude regulating parameter(s) only when the detected amplitude A exceeds an upper threshold TUor is lower than a lower threshold TL. In addition, the control circuit142may control the second control signal S2to control the amplitude regulating parameter(s) only under certain operating conditions and/or responsive to an event trigger. For example, control circuit142may control the second control signal S2to allow the amplitude regulating parameter(s) to change when the oscillator110powers on and/or when the oscillator110is acting in response to some communication event trigger. However, because changing the amplitude regulating parameters during, e.g., active communications, could disrupt the phase and/or frequency of the oscillator110, the control circuit142may control the second control signal S2to prevent the amplitude regulating parameter(s) from changing during such periods to prevent this disruption. The control circuit142may therefore use, in addition to the threshold conditions, power on/off events and/or communication event triggers to provide additional time-discrete control of the oscillator's amplitude regulating parameter(s). The exemplary method250ofFIG.5provides a more detailed approach for controlling the oscillator110at startup. In this exemplary method250, the oscillator110is powered on (block202), and the process waits until the oscillator110stabilizes (block204). Once the oscillator110stabilizes (block204), the detector120detects the amplitude A of the oscillator output signal So(block210). If the detected amplitude A exceeds an upper threshold TU(block232) or is less than a lower threshold TL(block234), the control circuit142in the second feedback path140determines the oscillator110is unable to maintain a desired amplitude with the current configuration. In response, the control circuit142therefore alters one or more amplitude regulating parameters of the oscillator110(block236). Blocks210,232, and234may be repeated once the oscillator110stabilizes again (block204). This repetition may be indefinite, or may terminate after some predetermined maximum number of iterations. FIGS.6-10show simulation results to demonstrate the advantages of the solution presented herein.FIGS.6and7first show the oscillation amplitude achievable when the control circuitry115does not include the second feedback path140. In this case, the amplitude regulating parameters of the oscillator110are fixed and the first feedback path130provides the only amplitude control.FIG.6provides results when amplifier132in the first feedback path130is configured to operate with a high gain that results in a relatively high loop gain, e.g., greater than 10, versus the results inFIG.7where the amplifier132operates with a lower gain that results in a relatively low loop gain, e.g., less than 5. As shown byFIG.6, the higher loop gain implementation provides a very low amplitude variation, e.g., 50-55% of the full swing. However, the high gain necessary to achieve this low amplitude variation results in high power consumption and high noise levels. The lower loop gain implementation enables lower power consumption and noise levels, but as shown inFIG.7, this lower loop gain implementation has a relatively high amplitude variation, e.g., 48-68% of the full swing. FIG.8shows the results when the second feedback path140is included with the control circuitry115to enable time-discrete adjustment of the amplitude regulating parameter(s) of the oscillator110. In this simulation, the first feedback path130has a low gain and the second feedback path140is used to control two extra amplitude regulating parameters, e.g., the bias tail current and/or the number of gmcells in the oscillator core, as shown by the three curves inFIG.8. As shown byFIG.8, the solution presented herein results in a lower amplitude variation (52-60%), which was previously not achievable when the first feedback path130had a lower loop gain. Thus, the solution presented herein provides the lower noise and power consumption benefits more typically associated with lower loop gain implementations while also providing the amplitude control benefits more typically associated with higher loop gain implementations. FIG.9shows simulation results demonstrating how the gain of amplifier132may be selected to achieve the desired trade-off between amplitude control and noise/power reduction. The results inFIG.9demonstrate the oscillator amplitude performance for six scenarios, which are qualitatively specified at each point, e.g., “high loop gain,” “low loop gain including second feedback path,” etc. The first four scenarios show the amplitude performance for high/low loop gain and high/low Q scenarios when the second feedback path140is not included. The last two scenarios show the amplitude performance for low loop gain and high/low Q scenarios when the second feedback path140is included. FIG.10shows simulation results demonstrating the noise performance for the same six scenarios as inFIG.9, and thus demonstrates the noise improvement provided by the solution presented herein. In particular, the top two plots show the operation of the frequency generation circuit100when the amplitude regulating parameters are fixed and the loop gain of the first feedback path130is high. The bottom plot shows the results when the second feedback path140is used to modify the bias current and the gmcells of the oscillator core when the loop gain of the first feedback path130is low. The solution presented herein therefore provides a frequency generation circuit having the amplitude control benefits associated with high gain negative feedback and the power and noise benefits associated with low gain negative feedback. The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein. | 13,992 |
11942953 | In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate implementations using suitable forms of indirect electrical connection as well. DETAILED DESCRIPTION An apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal. A method monitors a power supply. The method includes receiving a binary number and creating a pulse-density modulated signal scaled based on the binary number. The pulse-density modulated signal is converted to an analog signal, and compared to a monitored supply voltage. Responsive to detecting a droop in the monitored supply voltage below a designated value relative to the analog signal, a droop detection signal is produced. Responsive to the droop detection signal, the method causes a digital frequency-locked loop (DFLL) that provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage to slow the clock signal. A data processing system, includes an integrated circuit with at least two processor tiles. Each processor tile includes digital logic, a local DFLL providing a clock signal for synchronizing the digital logic, and a local power supply monitor for monitoring a respective monitored local supply voltage. Each power supply monitor includes a reference signal generator, a droop detection circuit, and a DFLL control circuit. The reference signal generator receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to the respective monitored local supply voltage, and responsive to detecting a droop of the respective monitored local supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL control circuit, responsive to receiving the droop detection signal, causes the local DFLL to slow the clock signal. FIG.1illustrates, in block diagram form, a system for regulating supply voltages to a plurality of processor cores according to the prior art. A supply voltage VDD12is connected to a plurality of supply adjustment blocks (SAB)14A-C. Each of the supply adjustment blocks14A-C is connected to produce an adjusted supply voltage to a processor core16A-C. Each of the processor cores16A-C includes a power supply monitor (PSM)30A-C, a fast droop detector (FDD)26A-C, and a digital low voltage regulator (DLVR)22A-C. Each DLVR22A-C is formed within the processor core16A-C, respectively. The processor cores and their associated circuitry may be referred to as a “processor tile”. In some versions, a supply adjustment block (SAB)60may be used either in addition to or in place of a supply adjustment block14. As may be seen, supply adjustment block60is a footer circuit rather than a header circuit meaning that the supply adjustment block is connected between the processor core and ground instead of being connected between the processor core and the supply. In versions of the system ofFIG.1where a supply of adjustment block60is included, the specific discrete logic is modified to support the desired operations and one of average skill in the art may readily make such transformations in design. The first regulators (22A-C) and FDD (26A-C) would remain the same. Thus, for example, a charge inject signal generated by FDD26A-C would serve to activate or select resistive elements within supply adjustment block60. While only one supply adjustment block60is shown in dashed lines, it should be understood that a plurality of supply adjustment blocks60could be included in the version ofFIG.1. As with a supply adjustment block14comprising a header circuit, a second regulator, namely FDD26A-C, generates a charge inject signal that causes selected resistive elements to be activated to adjust the voltage drop across the supply adjustment block14A-C and therefore to adjust voltage produced to the processor core16A-C. FIG.2illustrates, partially in block diagram form and partially in schematic form, further details of a regulator system that compensates for droop according to one implementation of the invention. A supply voltage VDD12is connected to supply adjustment block14that in turn produces the adjusted supply voltage to processor core16. The magnitude of the adjusted supply voltage is based upon the values of a control word, a charge control word and the charge inject signal generated by FDD26(illustrated as additional inputs to SAB14). In the described version, PSM30, DLVR22, and FDD26are all formed within processor core block16in the version ofFIG.2. The adjusted supply voltage is provided to PSM30that in turn produces the digital representation of the adjusted supply voltage magnitude to DLVR22. The adjusted supply voltage is also produced to FDD26. DLVR22is further connected to receive the target adjusted supply voltage, shown as “target”, and the droop threshold level from an external source. The external source may be a power management block in one implementation. DLVR22produces the droop threshold level to FDD26. DLVR22also produces the control word “ctrl [(n−1):0]” and the charge control word “chg_ctrl [(n−1):0]” to supply adjustment block14. FDD26includes a digital-to-analog converter (DAC)62that is connected to receive the droop threshold level from DLVR22and is configured to produce an analog signal whose magnitude corresponds to the received droop threshold level to a plus (+) input of a comparator64. In the depicted version, DAC62is a sigma-delta converter. A minus (−) of comparator64is connected to receive the adjusted supply voltage produced by supply adjustment block14. Comparator64generates the charge inject signal that activates the supply adjustment block14whenever the adjusted supply voltage falls below the analog droop threshold level or voltage. It should be noted, in the charge selection block utilizes NAND logic, a logic one for the charge injection signal triggers the charge injection or, more specifically, supply voltage adjustment for a selected MOSFET. A logic zero is only generated when the droop threshold is lower than the adjusted supply voltage. It should also be noted that the version ofFIG.2includes a first regulator (DLVR22) formed within processor core block16. In an alternative version, the first regulator, namely DLVR22, may be formed outside of processor core16. FDD26performs its processing very quickly by performing an analog comparison of the adjusted supply voltage and the droop threshold. Accordingly, the charge injection signal may be generated nearly instantly and may be generated much more quickly than processor-based digital logic that requires a number of clock cycles to obtain all necessary data and to process the data. As such, the second control loop that includes FDD26is a fast-acting control loop to immediately correct or regulate the adjusted supply voltage whenever the adjusted supply voltage falls below the droop threshold level. The first regulation loop, in contrast, that includes the first regulator (DLVR22), is a slower acting loop that compares the adjusted supply voltage to a target adjusted supply voltage value. By utilizing a fast acting second control loop with FDD26, a simpler and slower first regulation loop may be utilized to reduce IC real estate and associated power consumption. Moreover, because the decision-making in the second control loop is made in analog (real time), the first control loop may be clocked at a lower rate thereby saving power. FIG.3illustrates in block diagram form two implementations of a power supply monitor, labeled300(FIG.3A) and302(FIG.3B), according to some implementations. Power supply monitor300includes a reference signal generator320, a fast droop detector340, a DFLL control circuit350, a digital frequency-locked loop (DFLL)360, and a finite state machine (FSM)370. In this implementation, the droop detection performed by fast droop detector340is used to control DFLL360to increase or decrease its output clock signal frequency. Reference signal generator320has an input connected to a local power controller and receiving a digital number indicating a reference voltage, and an output providing a modulated digital signal indicating the reference voltage. The reference voltage is associated with the desired level of local supply voltage “VDD_CORE” to be monitored. Fast droop detector340has an input connected to the output of reference signal generator320, an input receiving the VDD_CORE supply voltage, a third input, and an output. DFLL control circuit350has an input connected to the output of fast droop detector340, and an output connected to DFLL360. DFLL360has a number of control and enable inputs (not shown) and an output providing a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. FSM370has an input connected to the output of fast droop detector340, an output connected to the second input of fast droop detector340, and may include a number of other control inputs (not shown). In operation, the local power controller for the voltage domain of the monitored supply voltage, in this case VDD_CORE, is operable to adjust the monitored supply voltage and provide a new value for the binary number to reference signal generator320corresponding to the adjusted monitored supply voltage. Reference signal generator320provides a digitally modulated signal carrying the provided value. Fast droop detector340compares the VDD_CORE supply voltage to an analog signal based on the digitally modulated signal to detect droops in the VDD_CORE supply voltage. Based on detecting such a droop, fast droop detector340sends a droop detected signal to DFLL control circuit350. Based on this signal, DFLL control circuit350commands DFLL360to slow the clock, or stop and then slow the clock, for a designated period. Power supply monitor302includes a reference signal generator320, a fast droop detector340, a DFLL control circuit350, a digital frequency-locked loop DFLL360, a clock gate380, and a finite state machine370. In this implementation, the DFLL control scheme ofFIG.3Bis used together with clock gate380to provide more rapid response to detected droops. Reference signal generator320inFIG.3Bhas an input connected to a local power controller and receiving a digital number indicating a reference voltage, and an output providing a modulated digital signal indicating the reference voltage. The reference voltage is associated with the desired level of local supply voltage “VDD_CORE” to be monitored. Fast droop detector340has an input connected to the output of reference signal generator320, an input receiving the VDDCORE supply voltage, a second input, and an output. DFLL control circuit350has an input connected to the output of fast droop detector340, and an output connected to DFLL360. DFLL360has a number of control and enable inputs (not shown) and an output providing a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. Clock gate380has a first input connected to the output of DFLL360, a second input connected to the output of fast droop detector340, and an output for selectively providing the clock signal from DFLL360. FSM370has an input connected to the output of fast droop detector340, an output connected to the second input of fast droop detector340, and may include a number of other control inputs (not shown). In operation of PSM302, the local power controller for the voltage domain of the monitored supply voltage is operable to adjust the monitored supply voltage and provide a new value for the binary number to the reference signal generator corresponding to the adjusted monitored supply voltage. Reference signal generator320provides a digitally modulated signal carrying the provided value. Fast droop detector340compares the VDD_CORE supply voltage to an analog signal based on the digitally modulated signal to detect droops in the VDD_CORE supply voltage. Based on detecting such a droop, fast droop detector340, sends a droop detected signal to clock gate380and DFLL control circuit350. Based on this signal, clock gate380gates the clock to immediately gate the clock while DFLL control circuit350commands DFLL360to slow the clock for a designated period. Because DFLL360is relatively slow in responding to commands to implement a change in clock frequency, fast droop detector340is also responsive to the droop detection signal to control clock gate380to gate the clock signal for a designated period to reduce the power consumed by the circuit and mitigate the drooping voltage on the VDD_CORE supply. FSM370controls the designated period by resetting the clock gate control signal, such as by controlling a latch. FIG.4shows in mixed block diagram and circuit diagram form a power supply monitor400according to further additional implementations. Power supply monitor400includes an extreme voltage minimum (XVMIN) detection circuit410, a digital frequency-locked loop DFLL460, a clock gate480, and a graphics DFLL FSM490(GDFLL FSM). Power supply monitor400is an exemplary implementation of the power supply monitor ofFIG.3B, which provides more rapid response to detected droops. While the depicted implementation performs power supply monitoring for a graphics processor, power supply monitor400is suitable for use with a wide variety of integrated circuits (ICs) that need power supply monitoring, such as, for example, central processing units (CPUs) or other data processors and application-specific ICs (ASICs). These processors and the associated power supply monitor can be implemented in devices such as laptops, desktops, smartphones, tablets, servers, game consoles and a multitude of other devices incorporating processors and requiring power supplying monitoring. XVMIN detection circuit410includes a first input receiving a graphics supply voltage labeled “VDDGFX” to be monitored, a second input receiving a system management network clock signal labelled “SMNCLK(VDDGFX)”, a first output providing a signal labelled “Xvmin_trig”, a second output labelled “Xvmin_clk_stop”, a fast droop detector420, an extreme voltage minimum trigger circuit470labelled “Xvmin_trigger”, an AND gate472, an OR gate474, and an AND gate476. Fast droop detector420, in this implementation, generally includes a reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value, and a droop detection circuit that converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. For example,FIG.5shows an implementation of a fast droop detector suitable for use as fast droop detector420. Fast droop detector420has an input receiving the voltage VDDGFX to be monitored, an input receiving the clock signal SMNCLK(VDDGFX), an input receiving a signal labelled “ResetDD_Xvmin”, and an output providing a signal labelled “DDlatched_sync”. Xvmin_trigger470is a control circuit, in this implementation of a FSM, and includes an input receiving the DDlatched_sync signal from fast droop detector420, an output providing the ResetDD_Xvmin signal to fast droop detector420, an input receiving the clock signal SMNCLK(VDDGFX), and an output providing a signal labelled “clk_gator”. OR gate474has a first input receiving the signal DDlatched_sync from fast droop detector420, a second input receiving the signal clk_gator from Xvmin_trigger470, and an output. AND gate472has a first input connected to the output of OR gate474, a second input receiving a clock stop enable signal labelled “Reg_Xvmin_clkstop_en” from a configuration register (not shown), and an output providing a signal labelled “Xvmin_clk_stop”. AND gate476has a first input receiving the signal DDlatched_sync from fast droop detector420, a second input receiving an enable signal labelled “Reg_Xvmin_en” from a configuration register (not shown), and an output providing the signal Xvmin_trig. DFLL460has a first input receiving a clock signal labelled “RefCLK”, a second input receiving signal labelled “DFLLConfigC[4:0]”, a third input receiving a signal labelled “FcsTrig”, and an output providing a clock signal for synchronizing circuitry within a domain of the monitored supply voltage VDDGFX, in this implementation a graphics processing core clock labelled “GFXCLK”. Clock gate480has a first input receiving the clock signal GFXCLK from DFLL460, a second input receiving the signal Xvmin_clk_stop from AND gate472of XVMIN detection circuit410, and an output providing a gated version of clock signal GFXCLK. GDFLL FSM490includes an input connected to receive the signal Xvmin_trig from XVMIN detection circuit410, a frequency control stretch trigger output providing the signal FcsTrig, a second output providing the signal DFLLConfigC[4:0] containing a frequency control word (FCW) for DFLL460, a control arbitration circuit495labelled “Arbitration”, a peak current control (PCC) client stretch control circuit491, a power brake client stretch control circuit492labelled “Power Brake”, an adaptive PCC client stretch control circuit493labelled “APCC”, and an XVMIN client stretch control circuit494labelled “Xvmin-stretch”. PCC client stretch control circuit491receives a signal (not shown) from the host IC's voltage regulator indicating whether an inductor current associated with the entire IC power supply is at risk of exceeding a maximum threshold. Based on this signal, PCC client stretch control circuit491produces an output indicating a requested amount of clock stretching (slowing), which is provided to control arbitration circuit495as a requested frequency control stretch (FCS) amount. Power brake client stretch control circuit492receives a signal (not shown) from a system state controller for throttling power consumption of a circuit based on workload, and produces an output provided to control arbitration circuit495indicating a requested FCS amount. APCC493has an input receiving a signal (not shown) from an adaptive peak current control circuit which is produced based on an amount of time a peak current control signal has been active. APCC493produces an output provided to control arbitration circuit495indicating a requested FCS amount. Xvmin-stretch494has an input receiving the signal Xvmin_trig, and an output connected to control arbitration circuit495. Xvmin-stretch494produces an output signal to control arbitration circuit495indicating a requested FCS amount based on the amount of time the signal Xvmin_trig has been active. Control arbitration circuit495has four inputs connected respectively to outputs of PCC491, Power Brake492, APCC493, and Xvmin-stretch494also have respective inputs (not shown) for receiving signals related to their functions. Control arbitration circuit495generally functions to select which stretch client of the four connected stretch clients will control the amount of clock stretch required of DFLL460, as further described below. In operation, fast droop detector420ofFIG.4monitors the supply voltage VDDGFX and will assert an internal signal “Droopdetected” if voltage crosses certain predefined threshold level. This internal signal, in normal operation, is latched at the output of fast droop detector420and is shown as the signal DDlatched_sync. Xvmin_Trig state-machine receives the signal DDlatched_sync as input and initiates gating of clock signal GFXCLK through the signal Xvmin_clk_stop. As the frequency of this clock drops to no-clock, the current drawn from supply voltage VDDGFX is reduced, causing the VDDGFX rail voltage to come out of droop. The signal internal Droopdetected that triggers this sequence is latched signal such that it stays high (irrespective of the voltage of VDDGFX) unless it gets reset by the ResetDD_Xvmin signal from Xvmin_trig470. This Droopdetected signal will also go out to GDFLL FSM490as a trigger signal (Xvmin_Trig). GDFLL FSM490has different clients491,492,493, and494requesting different amounts of stretch for different programmable durations. While these particular clients are shown, other clients employed in performance control and power control may be employed, and, of course, fewer clients may be used in various implementations. Xvmin-stretch494is one of the clients requesting stretch and is triggered by the signal Xvmin_Trig. In response, Xvmin_stretch494initiates a sequence of states to control how the clock frequency increased back to its earlier state. This sequence is performed through a force-stretch mode of the DFLL460in which a frequency control word that controls the DCO clock frequency in DFLL460is gradually increased to its initial operating state. Typically, when the power delivery network (PDN) providing supply voltage VDDGFX responds to a large current change event (known as a di/dt event), like the extreme stretch produced by the trigger described above, the supply voltage tends to oscillate between droops and overshoot for few cycles at PDN resonance frequencies before eventually getting dampened out. By increasing the clock frequency in this gradual manner, the depicted circuit ensures that frequency of power supply voltage changes is much lower than the natural resonance frequency of the PDN and prevent further oscillations. Different clients can request different stretch amount at different times, and control arbitration circuit495arbitrates among all these requests. Preferably, the client requesting the largest stretch amount will get the precedence and control DFLL460. Referring in more detail to the triggering process, in this implementation, the logic of GDFLL FSM490runs on the clock signal SMNCLK, which as shown is over 400 Mhz, rather than a system reference clock which is typically a lower speed of around 100 Mhz, to reduce latency for initiating stretching events. Xvmin_trigger470will be triggered as soon as the signal DDlatched_sync toggles high. For an extreme voltage minimum event, the goal of power supply monitor400is to drop the frequency of clock signal GFXCLK as fast as possible and stretch as deeply as allowed. However, any update of the FCW to DFLL460to change clock frequency will need to go through GDFLL FSM490, and the arbitration therein requires several clock cycles. So instead, Xvmin_trigger470generates the signal Xvmin_clock_gator that goes to clock gate480. However, even this fast path will take 2-3 cycles of the SMNCLK(VDDGFX) clock on which the power supply monitor400operates to synchronize following a droop event. To avoid this additional delay, the signal DDlatched_sync is OR-ed with clock_gator signal generated by Xvmin_Trig470to control clock gate480. DDlatched_sync will stay high once triggered, and therefore it should be free of glitches. Furthermore, clock gate480will internally synchronize its input (over 2-3 GFXCLK cycles and GFXCLK runs at a relatively high frequency), so that no glitch can pass through. In this way, within a delay of 2-3 GFXCLK cycles (plus the logic and propagation delay) following a droop event, GFXCLK will be stopped. In a preferred implementation, Xvmin_trigger470will first reset the latch of fast droop detector420with the ResetDD_Xvmin signal (FIG.6), causing the signal DDlatched_sync signal to go low after a programmable count, and then release clock gating after an additional programmable cycle count. This sequence ensures that the following restrictions are followed. First, DDlatched_sync will stay high and stable long enough to get synchronized properly and initiate Xvmin-stretch494inside GDFLL FSM490. Second, by resetting DDlatched_sync before releasing clock gating, the circuit ensures that if there is a new droop event (when GFXCLK is restored suddenly), mafdd is ready to react. Programmability for the signal Xvmin_clock_stop ensures that the circuit can stop the clock at least for a few cycles more than what it takes to propagate the FCS stretch amount through GDFLL FSM490(including arbitration and synchronization) and finally to DFLL460to update its FCW and change to stretched clock frequency. Because DFLL460supports external triggers to stretch the output CLK, different parts of the host system may use this stretching trigger to implement different features that are making use of DFLL stretch functionality. One of these different features is the peak Current Control (PCC) feature that limits the amount of current that the VDDGFX domain consumes for protection of an off-chip voltage regulator. A similar functionality exists regarding the power brake (PB) feature for throttling performance. The amount of stretch for these two features is the same and is programmable between 3% to 97.5% of the clock speed. GDFLL FSM490supports hysteresis counters for both inputs that can be used to filter the stretch input and make the stretch last longer. Adaptive PCC (or APCC) is a feature that dynamically changes the stretch amount according to how long the PCC signal has been asserted. The longer the PCC assertion, the higher the stretch amount is. Upon de-assertion of the PCC input, the stretch amount is decreased rather than abruptly being switched to zero. To implement this feature, APCC493is a programmable state machine within the GDFLL block to control the initial stretch, incremental stretch, max stretch, decremental stretch, final stretch and the time for each step. In prior clock stretch arbitration schemes, triggers from different features were OR-ed, i.e. a trigger from any feature will program DFLL stretch amount similarly. Since XVMIN410is there to protect any voltage excursion beyond a designated minimum voltage “Vmin”, Xvmin-stretch494will request a stretch amount more than other force stretch events. However, when XVMIN410is coming out of deep stretch, GDFLL FSM490will need to compare its own FCS request against other FCS requests from the other clients, and whichever client demands max stretch will be treated as the final FCWoffset. This will ensure that all clients get the protection they need. This arbitration process is implemented inside GDFLL FSM. Upon assertion of Xvmin_Trig, Xvmin-stretch494will generate the max FCS stretch amount. This stretch amount is preferably programmable. Upon de-assertion of the Xvmin_Trig input, the stretch amount will gradually decrease rather than abruptly being switched to zero. It will make use of a programmable state machine within the GDFLL block to control the initial stretch, incremental stretch, max stretch, decremental stretch, final stretch and the time for each step. All mentioned settings are preferably programmable and controlled through a register interface. FIG.5shows in mixed block diagram and circuit diagram form a portion of a power supply monitor500according to further additional implementations. The depicted portion of a power supply monitor500is suitable for use with the monitoring and control topologies shown inFIG.3,FIG.4, andFIG.5, as well as other circuits in which a power supply is monitored to detect fast droops of the power supply voltage. For example, the design of power supply monitor500is employed in some implementations to control a charge injection system such as the prior art system shown inFIG.1andFIG.2. Power supply monitor500generally includes a reference signal generator510and a fast droop detector circuit550. In this implementation, reference signal generator510has input labeled “fddConfigIn” receiving a binary number and an output labeled “LSIN” providing a pulse-density modulated signal. Generally, reference signal generator510operates to scale the pulse-density modulated signal based on the binary number. Reference signal generator510includes a control circuit512, an expander514, and a second order delta sigma modulator516. Control circuit512has a first input receiving a 10-bit binary number carried on the fddConfigIn input, a second input receiving a reset signal labelled “resetDD”, and an output labelled “ref” carrying the 10-bit binary number. Control circuit512generally operates to halt the passage of the 10-bit binary number when the resetDD indicates fast droop detector circuit550is disabled or reset, and pass the 10-bit binary number to the its output when the fast droop detector is operational. Expander514has an input connected to the output of control circuit512and an output. Expander514expands the 10-bit number to a 16-bit number. In this implementation, delta-sigma modulator516is a second-order delta-sigma modulator having an input connected to the output of expander514and an output providing a pulse-density modulated binary signal LSIN. While delta-sigma modulation is used in this implementation, other suitable modulation schemes may be employed to provide the pulse density modulated signal based on the binary number, which represents a desired voltage level for the monitored power supply. Reference signal generator510generates a bitstream whose average value (ideally) equals a supply voltage VDD on which reference signal generator510operates, scaled by the 10-bit binary number received as a reference at the fddConfigIn input. The long-term average output voltage of the bitstream LSIN will correspond to Equation 1 below, with “ref_value” being the value of the 10-bit number supplied the fddConfigIn input: <LSIN>avg=ref_value*VDD(1) While this particular modulator design is employed in this implementation, other implementations employ other suitable delta-sigma modulator designs, or other types of modulators for producing a pulse-density modulated signal. The pulse-density modulated signal LSIN is fed to the input of fast droop detector circuit550. Fast droop detector circuit550includes a power sniffer552, a level shifter554, a lowpass filter551, a comparator561, a second level shifter574, a latch580, a two-to-one multiplexor576, and an AND gate578. Fast droop detector circuit550is suitable for use in the power supply monitor circuits ofFIG.3,FIG.4, andFIG.5, as well as other power supply monitor circuits. Level shifter554has a first input receiving the pulse-density modulated signal LSIN, a second input receiving an enable signal from power sniffer552, and an output providing the pulse-density modulated signal referenced to a clean supply voltage labeled “VDDCR SOC” at the node labelled555(the voltage on this node is referred to as “voltage555”). Level shifter554may also include an inverting input553to provide an inverter version of signal LSIN for use in level shifting. Level shifter554is supplied with two voltages for the two domains across which it shifts voltage levels, from VDD to VDDCR_SOC. Power sniffer552has a first input receiving a power indication signal labeled “PwrOkVDD”, a second input receiving the clean supply voltage VDDCR_SOC, and an output connected to level shifter554. Power sniffer552enables level shifter554responsive to its two inputs when VDD is in a designated range. Lowpass filter551has an input coupled to the output of level shifter254and an output. Many lowpass filter designs and component values are suitable for use in various implementations. Comparator561has a first input coupled to the output of lowpass filter551, a second input receiving a monitored supply voltage VDDCORE, and an output. Generally, comparator561provides a droop detection signal at its output responsive to the monitored supply voltage VDDCORE dropping below a predetermined level relative to the first input. In this implementation, comparator561comprises a series of four inverters including a first complimentary-metal-oxide-semiconductor (CMOS) inverter562, a second CMOS inverter564, a third CMOS inverter566, and a fourth CMOS inverter568. Each inverter562,564,566, and568includes a positive supply terminal connected to the second input of the comparator to provide VDDCORE as the supply voltage for the inverters. CMOS inverter562has an input connected to first input of the comparator, and inverters564,566, and568are connected in series following inverter562. The output of inverter568provides a droop detection signal to level shifter574. In this implementation, inverters562,564,566, and568are biased such that they are configured to operate in a “crowbar” mode or crowbar region of operation in which both the p-type metal-oxide semiconductor (PMOS) and n-type metal-oxide semiconductor (NMOS) sides of the inverter are turned on when the monitored supply voltage is at approximately the predetermined level relative to the voltage on the respective inverter input. In this implementation, the predetermined level is twice the level of the voltage at the inverter input. Thus, as one-half of VDDCORE drops to the voltage at the output of lowpass filter551, the inverters562,564,566, and568enter crowbar mode and switch from a digital low to a digital high to signal a droop. Such operation provides a high gain and fast response for detecting droops below a designated level relative to the threshold voltage provided at the input of inverter562. Since the inverters are biased in a crowbar-state, they are highly sensitive to any noise on the input VDD rail. In some implementations, at least inverter562, or inverters562and564, are biased in such a crowbar state. Level shifter574has an input connected to the output of comparator561, and an output. Level shifter574is supplied with both the VDDCORE supply voltage (the monitored voltage), and the VDD supply voltage. Level shifter574may also include an inverting input573to provide an inverter version of the droop comparator output for use in level shifting. Level shifter574operates to shift the droop detection signal to be referenced to the VDD voltage. Multiplexor576has a first input connected to the output of level shifter574for receiving the droop detection signal, a second input, a selector input labeled “latchMode”, and an output coupled to the clock gate (i.e.,360,FIG.3,560,FIG.5) for gating a clock signal responsive to the droop detection signal. Latch580is a set-reset (SR) flip flop having an “S” input connected to the output of level shifter574, an “R” input receiving a reset signal labeled “resetDD_X”, a “Q” output connected to the second input of multiplexor576, and a “Q-NOT” output which is unused in this implementation. The latchMode input of multiplexor576is used to select whether the between the two inputs. AND gate578has a first input receiving an enable signal for the droop detection circuit labeled “FDDEN”, a second input receiving the droop detection signal from the output of multiplexor576, and an output providing the final output of fast droop detector circuit550labelled “droopDetected”. In operation, fast droop detector circuit550receives the LSIN pulse-density modulated signal. Due to the variability on VDD, this signal needs to be translated into a fixed voltage, which is accomplished through level shifter554supplied from VDDCR_SOC. This VDDCR_SOC voltage is a stable, regulated voltage providing a fixed amplitude for the level-shifted pulse-density modulated output of level shifter554. The new, fixed amplitude signal feeds lowpass filter551, which averages the value of the pulse-density modulated signal to produce a stable analog voltage to use with comparator561. This stable analog value provides a threshold, for detecting droops in the VDDCORE voltage supply. In this implementation, the threshold (“fdd threshold”,FIG.7) is twice the voltage of the stable analog value. Lowpass filter551is a double RC low pass filter operating with a cut-off frequency under 10 MHz. The output of low pass filter561feeds the series of inverters in comparator561supplied from VDDCORE that acts as an analog comparator. Because they are biased in the “crowbar” region, the series of inverters responds quickly to droops below the designated threshold. Preferably at least two inverters are used to provide stability for the droop detected signal, and more preferably at least three or four (as shown). The droop detected signal at the output of comparator561is level shifted back to VDD domain to be used for controlling various circuits to mitigate power supply droop, such as the clock gate and PLL circuits depicted inFIG.3,FIG.4, andFIG.5. Latch580is included to hold the droop detected signal at a digital HIGH for a designated period to provide proper timing for control of operations such as a one-time charge injection operation or a PLL adjustment. When latch580is enabled, the droop detected signal remains on once is triggered until is actively turned off by the local FSM. FIG.6shows a graph600depicting respective signals associated with power supply monitor circuit400ofFIG.4. The signals601,602,603, and604, and605show the digital level of the signal over time as two droops are detected in the monitored supply voltage VDDGFX, while signal606illustrates the normalized speed of the DFLL output clock GFXCLK. The depicted signals are aligned with respect to time. For signal601, the monitored supply voltage VDDCORE is shown relative to the Xvmin threshold on which fast droop detector420detects droops. VDDCORE droops below the threshold twice in the depicted scenario. Fast droop detector420detects the droop and produces the “Droopdetected” signal shown in graph602. XVmin_FSM440provides the signal “ResetDD_Xvmin” in graph603, which controls the latch holding the Droopdetected signal to reset it after a droop is detected. Signal604is the latched droop detected signal, DDlatched_sync, which is activated goes HIGH when the droop detected signal activates the latch output, and is held HIGH until it is reset. XVmin_FSM440has a programmable period which can be adjusted depending on the use of the DDlatched_sync signal. Signal605shows the signal Xvmin_clk_stop, which in the implementation ofFIG.4is produced by XVMIN detection circuit410to control clock gate480. Signal606shows the normalized clock speed of DFLL460relative to its highest operating speed before a droop detection event. As can be seen in the graph, the DDlatched_sync signal initially causes clock gate408to gate the clock, down to a no-clock or zero normalized level. Then as control arbitration circuit495responds to its inputs to start controlling the frequency of DFLL460, following three cycles of the RefClk, it causes DFLL460to gradually ramp up the speed of GFXCLK. Because in the depicted scenario, the second droop is detected before GFXCLK reaches its full normalized value, GFXCLK is again gated and then ramp up process is completed. FIG.7illustrates a block diagram of a power supply monitor700according to some additional implementations additional features for mitigating potential electrical design current (EDC) event. Power supply monitor700includes a reference signal generator320, a fast droop detector340, a digital frequency-locked loop (DFLL)360, a DFLL control circuit745, and a finite state machine370. Similarly to that ofFIG.3A, fast droop detector340performs droop detection which is used to control DFLL360to increase or decrease its output clock signal frequency. FSM370also functions similarly to that ofFIG.3A. In this implementation, DFLL control circuit745includes additional features for mitigating potential EDC events that may violate a peak current constraint of the power supply related to the socket over which power is supplied to the host IC, for example. Traditionally, EDC events are managed by PCC signals such as that provided to PCC client stretch control circuit491(FIG.4). Typically, such EDC events are not instantaneous and develop over a period of time such as 500 nanoseconds or 1 microsecond. However, because the PCC signals are typically generated off of the host IC, they take a relatively large amount of time to reach internal circuits to the IC to be used for throttling and power control functions. Power supply monitor700provides an alternative way to measure such events that occurs on-chip and therefore is able to respond more quickly to potential EDC events, and more effectively prevent them. DFLL control circuit745has an input connected to the output of fast droop detector340, an output connected to DFLL360, various digital control logic (not shown) which may be implemented as described above, and a counter747. The counter value increments while a droop is detected and decrements toward a zero value while a droop is not detected. Responsive to the counter value exceeding a designated threshold, DFLL control circuit745provides a signal indicating a potential EDC event exists that may violate the peak current constraint. FIG.8shows a flow diagram800showing the operation of an electrical design current mitigation process according to some implementations. The depicted process is suitable for use with power supply monitor700ofFIG.7, or other power supply monitor circuits. The process starts at block802, where it determines if a droop is detected below a defined load line level. The process then runs continuously. If a droop is detected at block802, the process goes to block804where it increments a counter such as counter747. If a droop is not detected, the process goes to block808, where it decrements the counter. (If the counter is already at zero, no action is taken.) At block810, if the counter is above a predetermined threshold for detecting a potential EDC event, the process goes to block812where it activates, or holds, an EDC event trigger signal. Such a signal may be used in various places on the host IC for triggering responses to potential EDC events. For example, the process may provide a signal to a stretch client such as those described with respect toFIG.4, thus activating stretches of a DFLL through an arbitration process including other clients. At block810, if the counter is not above the EDC event threshold, the process starts a separate hysteresis counter to deactivate the EDC event trigger signal. The hysteresis counter is reset when the EDC threshold is passed again if the other is above the threshold at block810. When the hysteresis counter reaches a designated value without being reset, the EDC event trigger signal from block812is deactivated. The process is continuous in response to droops being detected or not detected as shown by the arrows returning to block802. FIG.9shows a graph900depicting respective signals associated with power supply monitor circuit700ofFIG.7. The signals901,902,903, and904, and905depict the operation over time as three droops are detected in the monitored supply voltage VDDCORE. The depicted signals are aligned with respect to time. In signal901, the monitored supply voltage, in this example labeled “RVDD”, is shown relative to the Xvmin threshold on which fast droop detector420detects droops. In this implementation, the Xvmin threshold is set relative to the bottom of a Load Line (LL) region to enable detecting potential EDC events. RVDD droops below the threshold twice in the depicted scenario. Fast droop detector420detects the droop and produces the “Droopdetected” signal shown in graph902. In signal903, the value of a counter such as counter747(FIG.7) increments whenever the Droopdetected signal is active. The unlatched droop detected signal as described with respect toFIG.5is employed for this functionality to provide an accurate value for the counter. The counter decrements responsive to the droop no longer being detected. After the second depicted droop in signal901, a third droop begins before the counter is completely decremented, causing it to increment again. This droop lasts long enough to cause the counter to exceed a designated threshold labelled “Xvmin_count_threshold”. Signal904shows EDC event trigger signal “Xvmin_trig_filt” generated at block812in the process ofFIG.8to indicate an EDC event. Signal Xvmin_trig shows a programmable delay “Hysteresis_2” provided by DFLL control circuit745(FIG.7), as shown at block814ofFIG.8, to control the period for which the signal Xvmin_trig_filt is held HIGH after being triggered. Signal905shows a signal “Xvmin_trig”, which functions similarly to the signal DDlatched_sync shown inFIG.6, to provide a latched version of the Droopdetected signal for stabilizing the function of the droop detection circuit. Signal Xvmin_trig shows a programmable delay “Hysteresis_1” provided by FSM370(FIG.7) to control the latch of fast droop detect circuit340in this implementation. As can be seen comparing signals904and905, the process of using a counter acts a filter to Xvmin_trig events, such that only events that persist for a designated number of clock cycles cause potential EDC events to be recognized and the trigger, Xvmin_trig_filt, to the activated. FIG.10illustrates in block diagram form an accelerated processing unit (APU)1000according to some implementations. APU1000is implemented as a System-on-Chip (SoC) which may be part of a variety of host data processing platforms in various implementations. While an APU is shown in this implementation, other data processing platforms such as a central processing unit (CPU) or a graphics processing unit (GPU) may be used. For example, in some implementations, the fine-grained memory access techniques herein are embodied in a GPU chip employed in a graphics card or other graphics processing module. In other implementations, specialized processor cores such as intelligence processing units (IPUs) may be employed. In this implementation, APU1000includes generally a CPU core complex1010, a graphics core1020, a set of display engines1030, a memory management hub1040, a data fabric1050, a set of peripheral controllers1060, a set of peripheral bus controllers1070, a system management unit (SMU)1080, a flash memory205, and a set of FG_DRAM memory controllers1090. CPU core complex1010includes a processor tile1012and a processor tile1014, each processor tile including a CPU core, a power supply monitor (PSM), a fast droop detector (FDD), and a digital low voltage regulator (DLVR). In this example, CPU core complex1010includes two processor tiles, but in other implementations processor tile complex1010can include an arbitrary number of processor tiles. Each of processor tiles1012and1014is bidirectionally connected to a system management network (SMN)1045, which forms a control fabric, and to data fabric1050, and is capable of providing memory access requests to data fabric1050. Each of processor tiles1012and1014may be unitary cores, or may further be a core complex with two or more unitary cores sharing certain resources such as caches. The FDD implementations ofFIGS.3-5and7are all suitable for use in processor tiles1012and1014in various implementations. Each FDD controls a local PLL or DFLL for its local CPU core according to the techniques described above. Each of graphics cores1020is a high-performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, and the like in a highly integrated and parallel fashion. Power supply monitoring with an FDD such as those ofFIGS.3-5and7may also be implemented in each of graphics cores1020in various implementations. Each graphics core1020is bidirectionally connected to the SMN1045and to data fabric1050, and is capable of providing memory access requests to data fabric1050. In this regard, APU1000may either support a unified memory architecture in which CPU core complex1010and graphics cores1020share the same memory space, or a memory architecture in which CPU core complex1010and graphics cores1020share a portion of the memory space, while graphics cores1020also uses a private graphics memory not accessible by CPU core complex1010. Display engines1030render and rasterize objects generated by graphics core1020for display on a monitor. Graphics core1020and display engines1030are bidirectionally connected to a common memory management hub1040for uniform translation into appropriate addresses in memory, and memory management hub1040is bidirectionally connected to data fabric1050for generating such memory accesses and receiving read data returned from the memory system. Data fabric1050includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agent and memory controllers1090. It also includes a system memory map, defined by basic input/output system (BIOS), for determining destinations of memory accesses based on the system configuration, as well as buffers for each virtual connection. Peripheral controllers1060include a USB controller1062and a serial advanced technology attachment (SATA) interface controller1064, each of which is bidirectionally connected to a system hub1066and to SMN1045. These two controllers are merely exemplary of peripheral controllers that may be used in APU1000. Peripheral bus controllers1070include a system controller hub1072and a peripheral controller hub1074, each of which is bidirectionally connected to an input/output (I/O) hub1076and to SMN1045. System controller hub1072connects to Flash memory205over a suitable communications link. I/O hub1076is also bidirectionally connected to system hub1066and to data fabric1050. Thus, for example, a CPU core can program registers in USB controller1062, SATA interface controller1064, system controller hub1072, or peripheral controller hub1074through accesses that data fabric1050routes through I/O hub1076. SMU1080is a local controller that controls the operation of the resources on APU1000and synchronizes communication among them. SMU1080manages power-up sequencing of the various processors on APU1000and controls multiple off-chip devices via reset, enable and other signals. SMU1080also manages power for the various processors and other functional blocks. While a SoC implementation is shown, this is not limiting, and other computing platforms may also benefit from the techniques set forth herein. The circuits ofFIG.3A,FIG.3B,FIG.4,FIG.5,FIG.7, andFIG.10or any portions thereof may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data. While particular implementations have been described, various modifications to these implementations will be apparent to those skilled in the art. Accordingly, it is intended by the appended claims to cover all modifications of the disclosed implementations that fall within the scope of the disclosed implementations. | 52,686 |
11942954 | DETAILED DESCRIPTION The following description sets forth numerous specific details in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these specific details. In other instances, well-known technical features have not been described in order to avoid unnecessary obscuring of the invention. It is to be understood that the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure is thorough and conveys the scope of the invention to those skilled in the art. In the drawings, like reference numerals refer to like elements throughout. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly connected to” another element, there are no intervening elements. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term “including” specifies the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of the associated listed items. A DDR memory device is demanding on the accuracy of its two clocks, one of which is provided by an external bus (referred to hereinafter as the “external clock signal” denoted by VCLK), and the other is an internal clock generated by itself as required by its operation (“internal clock signal” by DQS). Referring toFIG.1, it receives a command cmd (e.g., a read command Read cmd) from an external source under the control of the external clock signal VCLK, and in response to the receipt of the read command Read cmd, generates the internal clock signal DQS (DQ strobe, data strobe pulse) that serves as a clock for sending a data DQ signal. In other words, the external clock signal VCLK controls the reception of the read command Read cmd by the memory device, and the internal clock signal DQS controls sampling of the data DQ by the DDR memory device. Theoretically, the two clock signals are synchronous. For many reasons, such as slight discrepancies between the internal circuit of the DDR memory device and the external circuit, the internal clock signal DQS (i.e., the data strobe pulse signal) may not be aligned (i.e., asynchronous) with the external clock signal VCLK. When data reading is directly conducted based on the unaligned internal clock signal DQS and external clock signal VCLK and on the read command Read cmd, an eye opening of data from the DDR memory device will be reduced. Therefore, it is necessary to add a DLL circuit to the DDR memory device to lock the internal clock signal DQS in phase with the external clock signal VCLK (i.e., control a phase difference between DQS and VCLK within a predetermined range where the two signals can be considered as being aligned or with a zero phase difference). As a result, the read command Read cmd can be aligned with the data DQ, avoiding a reduced eye opening. Once DQS and VCLK are locked to (aligned with) each other, transmission of the data DQ will occur at rising and falling edges of VCLK. FIG.2is a block diagram of such a DLL circuit. The DLL circuit is composed of a DLL delay line11, a clock buffer circuit12, a replica clock buffer circuit13, a DLL phase detector (PD) and a DLL controller15. The replica clock buffer circuit13is a replica of the clock buffer circuit and is able to generate a feedback clock signal DQS_fb from an output signal CLKout of the delay line11. The DLL delay line11is usually implemented as being controlled by a power supply voltage VDD. The DLL delay line11is included in the DLL circuit to reduce a phase difference between DQS and VCLK. Through adjusting the DLL delay line11, the phase difference between DQS and VCLK can be tuned into the aforementioned predetermined range. Once this is achieved, the DLL delay line11is locked so that the internal and external clocks remain synchronous (i.e., aligned) with each other throughout subsequent operation of the DDR memory device. For example, during a read operation, the external clock signal VCLK from the external circuit is delayed by the DLL delay line11, and the delayed clock signal CLKout from the DLL delay line11is fed to the replica clock buffer circuit13, which responsively generates the feedback clock signal DQS_fb. The DLL phase detector14samples and compares the external clock signal VCLK and the feedback clock signal DQS_fb from the replica clock buffer circuit13and feeds the comparison to the DLL controller15. Based on the comparison, the DLL controller15then adjusts the DLL delay line11until the internal clock signal DQS from the clock buffer circuit12is aligned with the external clock signal VCLK. The delay of the DLL delay line11is then locked. Considering the trend of such memory devices toward an increasingly high operating frequency, the DDR memory devices may switch to a low power consumption mode upon receiving a command instructing it to do so to avoid unnecessary power consumption. In the low power consumption mode, part of the DLL circuit including the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13may stay inactive. However, after the DDR memory device enters the low power consumption mode under the control of the power down signal (i.e., the command that instructs the DDR memory device to enter the low power consumption mode, referred to hereinafter as the “PWD signal” for short), a power supply voltage of the DLL circuit will rise (i.e., experience a significant change) due to a reduced load current in a circuit (e.g., an LDO circuit) providing the power supply voltage), which will lead to a change in the delay provided by the DLL delay line11in the DLL circuit and hence a shift of DQS. Consequently, DQS and VCLK are no longer aligned with each other (i.e., they are not locked to each other anymore), and therefore when it is necessary to read or write data immediately after the DDR memory device exits the power down mode, a read or write error may occur. In order to overcome this problem, according to a non-preferred embodiment of the present invention shown inFIG.3, an associated voltage detection circuit is employed to detect variation of the power supply voltage. When a significant change in the voltage (indicating a significant change in the delay of the DLL delay line) is detected, the DLL circuit is enabled to allow the DLL circuit to realign DQS with VCLK. The voltage detection circuit is generally composed of an oscillator VCO that is sensitive to the power supply voltage, a counter U1and a data storage and comparison circuit U2. FIG.4shows a timing diagram of operation of the voltage detection circuit. When the power down signal (i.e., the command that instructs the DDR memory device to enter the low power consumption mode, labeled as “PWD Signal” inFIG.4) is enabled, the DDR memory device will enter the low power consumption mode. In response, the voltage detection circuit ofFIG.3will be enabled, and the counter U1therein will be enabled by a clock signal CLKE. A change in the power supply voltage will cause a frequency change in an output frequency signal from the oscillator VCO, which will in turn lead to a change in a count of the counter U1. When this new count (Count Signal A) differs from a previous count registered in the data storage and comparison circuit U2(Stored Signal B), the data storage and comparison circuit U2will output a pulse as an enable signal for the DLL circuit. As a result, the DLL circuit resumes operation to realign DQS with VCLK, ensuring correct data reading or writing after the DDR memory device exits the low power consumption mode. The above non-preferred embodiment has at least the following disadvantages. First, it is complex in circuit structure and design and introduces a considerable increase in circuit area. Second, the voltage detection circuit operates as long as the DDR memory device is in the low power consumption mode and has a complex structure, introducing a substantial increase in power consumption. Third, the detection of the voltage detection circuit would take some time, and if the DDR memory device stays in the low power consumption mode for a very short period of time, the DLL circuit may not have sufficient time to accomplish the realignment of the internal and external clocks. In addition to DDR memory devices, other memory devices adopting DLL circuits also suffer from the above problems. In view of this, the present invention provides delay locked loop (DLL) circuitry system and a memory device. With a simple circuit structure, a DLL circuit can be enabled in a low power consumption mode of the memory device to align internal and external clocks (i.e., the above internal clock signal DQS and external clock signal VCLK) with each other. Even if it is necessary to read or write data immediately after the memory device exits the low power consumption mode, no read or write error will occur. Further, the undesirable addition of a large circuit area and a significant increase in power consumption can be avoided. The present invention will be described in greater detail below with reference to particular embodiments thereof and the accompanying drawings. From the following description, advantages and features of the invention will become more apparent. Note that the figures are provided in a very simplified form not necessarily drawn to exact scale and for the only purpose of facilitating easy and clear description of the embodiments. Referring toFIGS.5and6, in an embodiment of the present invention, there is provided DLL circuitry system including a timer unit21and a DLL circuit22coupled thereto. DLL circuit22is operable to receive an external clock signal VCLK and an internal clock signal DQS delayed in time with respect to the external clock signal VCLK and lock the internal clock signal in phase with the external clock signal (i.e., align edges of the internal clock signal DQS with those of the external clock signal VCLK). The timer unit21is coupled to an enable terminal of the DLL circuit22and configured to be enabled in response to a signal from outside of the DLL circuitry system, which instructs entry into a low power consumption mode (i.e., PWD signal), and generate, under the control of the signal, based on a predefined timer condition, a DLL enable signal for enabling the DLL circuit22to allow it to lock the internal clock signal in phase with the external clock signal (i.e., align them with each other). This embodiment differs from that shown inFIG.3in that, when the DLL circuitry system is used in a memory device (e.g., SDRAM, PSRAM or the like), the timer unit21is adapted to enable the DLL circuit22in the low power consumption mode of the memory device. According to this embodiment, in the low power consumption mode of the memory device in which the DLL circuitry system is disposed, the timer unit21enables the DLL circuit22at a predetermined time determined by the predefined timer condition. Instead of detecting whether there is a change in the power supply voltage VDD of the DLL circuit22, as long as the predefined timer condition is satisfied in in the low power consumption mode of the memory device, the DLL enable signal will be generated to enable the DLL circuit. FIG.15schematically illustrates a memory device incorporating the proposed DLL circuitry system according to an embodiment of the present invention. The DLL circuitry system51is incorporated in the memory device (e.g., DDR SDRAM, PSRAM or the like)500. In one embodiment, the DLL circuitry system51is implemented in an interface circuit50of the memory device500. The timer unit21is configured to enable the DLL circuit22in a low power consumption mode of the memory device500. Detailed description is set forth below regarding how the memory device500enters the low power consumption mode and how a signal instructing the entry (i.e., a power down (PWD) signal) is generated. As shown inFIG.15, the memory device500is controlled by an external memory controller600. The memory controller600may be a DDR controller or a system memory controller. In one embodiment, the memory controller600is configured to send the command cmd and external clock signal VCLK ofFIG.1to the memory device500, receive data read from the memory device500and write data to the memory device500. The memory device500further includes a mode register52, a control circuit53and a memory block54. The memory block54is configured for storage of data thereon and may be implemented as a dual-edge sampled memory array. In one embodiment, the mode register52and the control circuit53are disposed in the interface circuit50. The mode register52is configured to set a condition for entry of the memory device500into the low power consumption mode (which may be a specific value). When the control circuit53receives a command (cmd) instructing entry into the low power consumption mode, if a clock enable signal CKE is disabled (e.g., pulled low), the control circuit53enables, depending on the mode register52, a signal instructing entry into the low power consumption mode (i.e., the PWD signal). As a result, the memory device500enters the low power consumption mode under the control of the signal. In some other embodiments, the memory device500may directly enter the low power consumption mode upon the reception of the command (cmd), without the involvement of the clock enable signal CKE. More specifically, the low power consumption mode of the memory device500may include, for example, a self-refresh or power-down mode as specified in the JEDEC standards. Moreover, the low power consumption mode of the memory device500is controlled by the external memory controller600. For example, when the memory controller600issues the command instructing entry into the low power consumption mode and pulls the clock enable signal CKE low, the control circuit53reads a value of the mode register52. The mode register52may be implemented as a mode register set (MRS), and the value thereof represents a user-defined predetermined condition for entry into the self-refresh or power-down mode. If the control circuit53determines that the predetermined condition is satisfied, then it enables the signal instructing entry into the low power consumption mode (PWD signal) to cause the memory device500to enter the self-refresh or power-down mode. In the self-refresh mode, without refresh commands from the external memory controller600, the memory device500will regularly refresh itself (e.g., count values of address counters, etc.) based on an internal logic circuit such as an internal timer so that data in the memory block54is naturally maintained at a reduced level of power consumption. In contrast, in the power-down mode, power for the memory device500and the external memory controller600may be cut off or reduced. As another example, when the memory controller600pulls the clock enable signal CKE high or issues a command instructing exit from the low power consumption mode, the control circuit53will disable the signal instructing entry into the low power consumption mode (PWD signal) to cause the memory device500to exit the low power consumption mode. It is noted that, different from the automatic periodic powering down of the DLL circuit22after the alignment of DQS and VCLK, in the present invention, the DLL circuitry system51is enabled and powered down under the control of the control circuit53after the memory device500enters into the low power consumption mode. As a particular example, referring toFIG.6, in this embodiment, the DLL circuit22may include a DLL delay line11, a clock buffer circuit12, a replica clock buffer circuit13, a DLL phase detector14and a DLL controller15. The DLL delay line11delays the external clock signal VCLK and outputs the delayed signal. The clock buffer circuit12is coupled to the DLL delay line11. The DLL delay line outputs the clock signal CLKout, and the clock buffer circuit outputs the internal clock signal DQS. The DLL delay line11may be implemented as a voltage-controlled delay line controlled by the power supply voltage VDD. The replica clock buffer circuit13includes a replica of the clock buffer circuit12and is able to reproduce a delay of the external clock signal VCLK caused by its propagation through the clock buffer circuit12and other components. Moreover, it can generate a feedback clock signal DQS_fb from the clock signal CLKout output from the DLL delay line11. The DLL phase detector14compares the feedback clock signal DQS_fb with the external clock signal VCLK. Based on the comparison of the DLL phase detector14, the DLL controller15controls the DLL delay line11to adjust its delay. Through configuring the delay of the DLL delay line11, the DLL circuit22can reduce the phase difference between the incoming external clock signal VCLK and the output internal clock signal DQS. Moreover, the delay of the DLL delay line11can be incrementally adjusted so that the phase difference between the incoming external clock signal VCLK and the output internal clock signal DQS lies within a predetermined range (where the phase difference can be considered as zero). When this is achieved, the delay of the DLL delay line11is locked to allow the internal and external clocks to be kept synchronized (i.e., aligned) with each other through subsequent operation of the memory device500. An output terminal of the timer unit21is coupled to enable terminals of the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13in the DLL circuit22. In this way, when the PWD signal arrives, the timer unit21can output the DLL enable signal Nap_en based on the predefined timer condition. A high level or rising edge of the DLL enable signal Nap_en can wake up the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13(i.e., enable the DLL circuit22) to allow the DLL circuit22to lock the internal clock signal DQS in phase with the external clock signal VCLK again. In this embodiment, the alignment and locking of DQS in phase with VCLK by the DLL circuit22particularly involves delaying of the external clock signal VCLK by the DLL delay line11and outputting of the delayed clock signal CLKout therefrom. The delayed clock signal CLKout is passed through the clock buffer circuit12and output therefrom as the internal clock signal DQS. At the same time, it is passed through the replica clock buffer circuit13and output therefrom as the feedback clock signal DQS_fb. The DLL phase detector14receives and compares the external clock signal VCLK and the feedback clock signal DQS_fb to assess a phase difference between them. Based on the comparison of the DLL phase detector14(i.e., an output signal from the DLL phase detector14, which is not shown), the DLL controller15performs control to adjust the time delay provided by the DLL delay line11. The DLL delay line11, the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13form a closed control loop. The control is carried out until edges of the external clock signal VCLK are aligned with those of the internal clock signal DQS (e.g., with a phase difference between rising edges of the two lying within a predetermined range). The delay of the DLL delay line11is then locked. Increasing or decreasing of the delay of the DLL delay line11accomplished under the control of the DLL controller15generally involves coarse delay adjustment and fine delay adjustment. The coarse delay adjustment may employ a minimum step which may be multiple times (i.e., 16 times) a minimum step employed in the fine delay adjustment. In normal operation of the DLL controller15, the coarse delay adjustment usually precedes the fine delay adjustment, of the DLL delay line11, and the fine delay adjustment is performed until the phase difference between the rising edges of VCLK and DQS is tuned into the predetermined range, followed by locking of the DLL circuit22. The DLL controller15may include an internal DLL state machine15acarrying an internal state signal (not shown). The state signal may transition depending on a sampled voltage level of VCLK at the rising edge of DQS, and the state machine may switch between different states in response to the transitioning of the state signal. The DLL state machine15ain different states can control the delay of the DLL delay line11to be adjusted at different incremental steps. Referring toFIG.11, in the course of the fine delay adjustment of the DLL delay line11under the control of the DLL controller15at the minimum fine adjustment step, the DLL state machine15amay determine whether the number of times the rising edge of DQS cross the rising edge of VCLK forth and back reaches a predetermined threshold value (e.g., 2, 3 or greater). If so, it can be considered that the phase difference between the rising edges of DQS and VCLK falls within the predetermined range, and the two are aligned with each other, and the DLL circuit22is then locked. When the DLL controller15determines that the phase locking has been achieved, it will lock a DLL code value for subsequent use in the next phase locking operation when the DLL enable signal Nap_en is again enabled. The locking of the DLL code value corresponds to locking of the DLL delay line11and hence the time delay provided thereby. With continued reference toFIGS.6,10A and15, in this embodiment, in response to the signal instructing entry into the low power consumption mode (i.e., the power down (PWD) signal), the memory device500incorporating the DLL circuitry system51enters the low power consumption mode in which the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13in the DLL circuit22are inactive, with the delay of the DLL delay line11being locked. At the same time, the PWD signal enables the timer unit21. When a phase shift occurs in DQS due to jitter of the power supply voltage VDD, the timer unit21can output the DLL enable signal Nap_en (which is asserted at a high level, for instance) based on the predefined timer condition. For example, the DLL enable signal Nap_en may be asserted after a period of time t1, and its high level or rising edge can wake up the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13(i.e., enable the DLL circuit22) to allow the DLL circuit22to lock the internal clock signal DQS in phase with the external clock signal VCLK again. After another period of time t2(which may be longer than or equal to a minimum period of time required by the DLL circuit22to complete the relocking), the DLL enable signal Nap_en may be unasserted, again deactivating the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13, with the delay of the DLL delay line11being locked. In case of the enable signal Nap_en being implemented as a pulse modulation signal with a duty cycle of t2/(t1+t2), the above processes may alternate until the PWD signal is unasserted and the memory device500exits the low power consumption mode. In some other embodiments, once the locking is completed, the DLL controller15may again disable the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13to allow them to consume less power. For example, after the locking is completed, the DLL controller15may output a DLL lock signal DLLctrl which disables the DLL enable signal Nap_en. As shown inFIG.10B, the DLL circuit22may be woken up by the DLL enable signal Nap_en to lock the internal clock signal DQS in phase with the external clock signal VCLK again. When the DLL controller15determines that the phase locking has been achieved, it will lock a DLL code value for subsequent use in the next phase locking operation when the DLL enable signal Nap_en is again enabled. As shown inFIG.10B, in an example of another embodiment, the DLL controller15may additionally output a DLL control signal DLL ctrl, and a sampling logic circuit23may disable the DLL enable signal Nap_en based on both an output from the timer unit21and the DLL control signal DLL ctrl, thereby deactivating the DLL phase detector14, the DLL controller15and the replica clock buffer circuit13. The deactivation by the DLL controller15may be accomplished by a logic operation performed on a system clock clk and the DLL enable signal Nap_en by an AND logic circuit (e.g., an AND gate)24. With combined reference toFIGS.6,11and15, as any phase shift in DQS caused by variation of the power supply voltage VDD in the low power consumption mode is actually small (i.e., any phase difference between the rising edges of DQS and VCLK caused by variation of the power supply voltage VDD will exceed the predetermined range much), relocking would be attained with only a few delay adjustment steps of the DLL delay line11, and it would be not necessary for the DLL circuit22to start operation as soon as any such shift occurs. Therefore, during relocking, the DLL controller15may control the DLL delay line11so that it switches to fine delay adjustment after a few (e.g., one or two) coarse delay adjustment steps, or that it skips coarse delay adjustment and directly performs fine delay adjustment. Moreover, DQS and VCLK can be locked in phase with each other again only with a few fine delay adjustment steps. In this case, the number of times of crossing serving as a criterion for determining by the state machine15awhether relocking is achieved may be reduced compared to that for normal operation. For example, if the number of times of crossing reaches a first threshold value (e.g., 2 or 3, lower than the threshold value for normal operation), it can be considered that the phase difference between the rising edges of DQS and VCLK is within the predetermined range, i.e., relocking is achieved by the DLL circuit22. That is, in the low power consumption mode, the DLL state machine15ais allowed to roughly determine whether relocking is achieved by the DLL circuit, without having to undergo a standard process as in normal locking operation. Accordingly, in some other embodiments, the first threshold value may be smaller than the threshold value for determining whether the delay of the DLL delay line11is to be locked in normal operation of the DLL circuit. In this way, higher relocking efficiency can be achieved, and less power can be consumed during relocking. In a particular example, referring toFIGS.6and11, as a consequence of jitter of the power supply voltage VDD, DQS overall shifts to the left relative to VCLK that it was previously locked to and becomes DQS(0). Responsively, the DLL circuit22is woken up by the DLL enable signal Nap_en from the timer unit21and commences a relocking process, in which the DLL state machine15afirst outputs a DLL code value of “+1” for controlling the DLL delay line11to adjust its delay so that DQS overall shifts to the right until the rising edge of DQS crosses the rising edge of the VCLK for the first time and becomes DQS(1). Subsequently, the DLL state machine15aoutputs a DLL code value of “−1” for controlling the DLL delay line11to adjust its delay so that DQS overall shifts to the left until the rising edge of DQS crosses the rising edge of the VCLK for the second time and becomes DQS(2). At this point, the DLL state machine15adetermines that the number of times the rising edge of DQS crosses the rising edge of VCLK (i.e., 2) reaches the first threshold value, and it is therefore considered that the phase difference between the rising edges of DQS and VCLK lies within the predetermined range and the DQS and VCLK have been locked in phase with each other again. The DLL code value of the DLL state machine15ais then locked. Similarly, in case of DQS overall shifting to the right relative to VCLK due to jitter of the power supply voltage VDD, DQS may be first shifted to the left side of VCLK and then back to the right side thereof. In this way, the number of times the rising edge of DQS crosses the rising edge of VCLK is also 2, and DQS is again locked in phase with VCLK. In this embodiment, the timer unit21includes a counter, which is enabled in response to the reception of the signal instructing entry into the low power consumption mode (PWD) and is inverted or reset after it counts to a count threshold (e.g., corresponding to n cycles of the system clock clk). In an example of this embodiment, referring toFIG.7, the predefined timer condition that the timer unit21is based on may be the count threshold n, and n may rely mainly on a stabilization time for the power supply voltage VDD (i.e., a stabilization time for an output voltage of the LDO circuit that powers the DLL circuit22) and may be an empirical value greater than 0. The timer unit21may start counting as soon as it is enabled by the PWD signal and, upon its count reaching the count threshold n, assert the DLL enable signal Nap_en for enabling the DLL circuit22. Specifically, as soon as the timer unit21is enabled by the incoming PWD signal, the counter in the timer unit21starts counting the number of cycles of the system clock clk, and when the count reaches n (i.e., the count threshold, which satisfies t1=n*clk), the timer unit21will pull the DLL enable signal Nap_en high, thereby enabling (i.e., waking up) the DLL circuit22. As a result, the delay of the delay line11in the DLL circuit22is adjusted and relocked, and the internal clock signal DQS is locked in phase with the external clock signal VCLK again. In this example, a pulse width of the enable signal Nap_en from the timer unit21(i.e., t2) may be an empirical value, which may be determined by the stabilization time for the power supply voltage VDD and a length of time required by the DLL circuit to realign DQS with VCLK. Moreover, the count threshold n may determine the delay t1between the times when the DLL circuit22is enabled and when the PWD signal arrives (i.e., t1=n*clk). It may also determine a start point for the DLL state machine15ain the aforementioned standard locking process. N may be determined as an empirical value which ensures that the DLL circuit22is enabled to allow the delay of the delay line11to be adjusted only after the power supply voltage VDD of the DLL circuit22has become stable and that a reduced number of adjustment steps is allowed in the DLL delay line so that the relocking process can be completed faster within a shorter time. This example is suitable for use in cases where the memory device500stays in the low power consumption mode for a period of time that is sufficiently long to allow the delay of the delay line11in the DLL circuit22to be adjusted after the power supply voltage has experienced a change due to entry of the memory device500into the low power consumption mode and stabilized (possibly at a higher level). However, if the memory device500stays in the low power consumption mode for a very short period of time (e.g., shorter than n system clock cycles), then at the time when the memory device500exits the low power consumption mode, the timer unit21may not have been enabled yet, or although it has been enabled, the time left is not sufficient for it to adjust and update the delay of the delay line11. Consequently, the internal clock signal DQS remains unaligned with the external clock signal VCLK. In another example of this embodiment, referring toFIG.8, the predefined timer condition that the timer unit21is based on may be the count threshold n, and n may rely mainly on a stabilization time for the power supply voltage VDD (i.e., a stabilization time for the output voltage of the LDO circuit that powers the DLL circuit22) and may be an empirical value greater than 0. As soon as the timer unit21is enabled by the PWD signal, it may start counting and outputting the enable signal Nap_en that is asserted and enables the DLL circuit22. Upon the count reaching the count threshold n, it may stop enabling the DLL circuit22(by unasserting the enable signal Nap_en). That is, in this example, a rising edge of the enable pulse signal Nap_en from the timer unit21is aligned with a rising edge of the PWD signal, while a falling edge of the enable pulse signal Nap_en is determined by the count threshold n, as expressed by t1=0 and t2=n*clk. Specifically, as soon as the timer unit21is enabled by the incoming PWD signal, the counter in the timer unit21starts counting the number of cycles of the system clock clk, and the timer unit21starts outputting the DLL enable signal Nap_en to enable the DLL circuit22. Upon the count reaching n, it stops enabling the DLL circuit22. In this example, the count threshold n may be set to a relatively large value so that the time length of n cycles of the system clock clk (i.e., t2) is not shorter than the stabilization time for the power supply voltage VDD of the DLL circuit22(i.e., the stabilization time for the output voltage of the LDO circuit that powers the DLL circuit22). In this way, the DLL circuit22will operate across n cycles of the system clock clk after the PWD signal arrives and then stop operation as the count in the timer unit21reaches the count threshold n. This example is suitable for use in cases where the memory device500stays in the low power consumption mode for a relatively short period of time, because even if the memory device500stays in the low power consumption mode for a very short period of time (e.g., shorter than n system clock cycles), it can still ensure that, at the time when the memory device500exits the low power consumption mode, the timer unit21has been enabled in the low power consumption mode for a period of time that is sufficiently long to allow the DLL circuit to update its delay to align the internal clock signal DQS with the external clock signal VCLK. However, this example requires greater power consumption because the DLL circuit is enabled for a longer period of time in the low power consumption mode. In a further example of this embodiment, referring toFIG.9, the predefined timer condition that the timer unit21is based on may be a predetermined duty cycle of n/m, where n and m are both empirical values greater than 0. In this example, in the low power consumption mode of the memory device500, the DLL enable signal Nap_en output from the timer unit21has the predetermined duty cycle n/m and thus enables the DLL circuit22intermittently until the PWD signal is disabled. That is, t1=m*clk and t2=n*clk are satisfied. Specifically, as soon as the timer unit21is enabled by the incoming PWD signal, the counter in the timer unit21starts counting the number of cycles of the system clock clk and outputting the enable signal Nap_en that is asserted and enables the DLL circuit22. When the count reaches n, the enable signal Nap_en is unasserted to stop enabling the DLL circuit22, and the counter is reset and starts counting the number of cycles of the system clock clk again. When the new count reaches m, the DLL circuit22is enabled again, and the counter is reset and starts counting again. This is repeated until the PWD signal is disabled (e.g., by the control circuit53under the control of the clock enable signal CKE that instructs exit from the low power consumption mode). Each period of the DLL enable signal Nap_en from the timer unit21consists of n consecutive cycles of the system clock clk and m consecutive cycles of the system clock clk. The DLL enable signal Nap_en from the timer unit21may have an empirical number of periods, which correspond to a length of time that is not shorter than a stabilization time for the power supply voltage VDD of the DLL circuit22(i.e., a stabilization time for the output voltage of the LDO circuit that powers the DLL circuit22). Therefore, the predetermined duty cycle (n/m) is determined by at least one of: a change in the power supply voltage VDD of the DLL circuit22(i.e., the system power supply voltage); an offset of the internal clock signal from the external clock signal caused by entry of the memory device500incorporating the DLL circuitry system51into the low power consumption mode; the time taken by each calibration cycle of the DLL circuit22; the stabilization time for the power supply voltage VDD; a time length of each system clock cycle on which the timer unit21is based to enable the DLL circuit22; the number of cycles of the system clock clk taken by each calibration cycle of the DLL circuit22; and so forth. In this example, in the low power consumption mode of the memory device500, the DLL circuit22is intermittently enabled by the DLL enable signal Nap_en from the timer unit21. In this way, the delay of the DLL circuit22can be updated intermittently, avoiding any change in the delay of the DLL circuit22caused by variation of the power supply voltage VDD of the DLL circuit22upon entry into the low power consumption mode and maintaining the internal clock signal DQS in alignment with the external clock signal VCLK, while achieving a relatively low level of power consumption. Moreover, since the delay of the DLL circuit22is updated and adjusted multiple times, it is more accurate. In other words, the internal clock signal DQS can be more accurately aligned with the external clock signal VCLK. All in all, no matter which of the above examples is used, in this embodiment, upon receipt of the PWD signal, the timer unit21is enabled and then generates, based on the predefined timer condition, the DLL enable signal Nap_en for enabling the DLL circuit22. The enabled DLL circuit22then locks the internal clock signal DQS in phase with the external clock signal VCLK again. In this way, even when the memory device500is in the low power consumption mode, the DLL circuit22can relock the internal clock signal DQS to the external clock signal VCLK. Unlocking of the DLL circuit (i.e., the phase difference between the internal clock signal DQS and the external clock signal VCLK exceeds the predetermined range) that may be caused by a change in power supply voltage of the DLL circuit due to entry of the memory device into the low power consumption mode can be avoided. If this remains untreated when the memory device exits from the low power consumption mode, an error may occur when data is to be read or written immediately after the exit. It is to be understood that the timer unit21may have any suitable circuit architecture and design, as long as it enables the timer unit21to provide the functions described herein. The system clock clk that it requires may be generated by an oscillator OSC, a crystal oscillator, a pulse generator or any other suitable electronic element or special-purpose circuit. It may alternatively obtained by dividing the external clock signal VCLK using a frequency divider. Apart from the counter, the timer unit21may also be implemented by a timer circuit consisting of, sequentially connected, an oscillator, a frequency divider and a counter, or another timer circuit such as a DFF line. The circuit architecture of the proposed DLL circuitry system is not limited to the components discussed in the foregoing embodiments, as it may also include some circuit modules required for the implementation of functions necessary for some chip systems. For example, in DLL circuitry system according to another embodiment of the present invention, referring toFIG.12, the DLL circuit22further includes a duty cycle correction (DCC) circuit16, which is coupled to the DLL delay line11, the replica clock buffer circuit13and the timer unit21and is configured to adjust the duty cycle of the internal clock signal DQS based on the feedback clock signal DQS_fb output from the replica clock buffer circuit13until the duty cycle of the internal clock signal DQS reaches a predetermined value that is, for example, 50%. In this embodiment, the DLL circuit22can be locked only when the rising edge of DQS is aligned with the rising edge of VCLK and the duty cycle of DQS is reaches the predetermined value. It is to be noted that when the duty cycle of DQS reaches the predetermined value, it may be the same as a duty cycle of VCLK or not. As an example, the DCC circuit16may include a duty cycle detection circuit16a, a DCC controller16band a DCC adjustment circuit16c. The duty cycle detection circuit16ais coupled at an input terminal thereof to an output terminal of the replica clock buffer circuit13and is configured to measure a duty cycle of the feedback clock signal DQS_fb output from the replica clock buffer circuit13. The DCC controller16bis coupled to an output terminal of the duty cycle detection circuit16aand is configured to generate, based on a detection result of the duty cycle detection circuit16a, a DCC code which determines the duty cycle compensation provided by the DCC adjustment circuit16c. The DCC adjustment circuit16cis coupled to both the DCC controller16band the DLL delay line11and is configured to receive the external clock signal VCLK, generate an input clock signal CLK D cc with a corresponding duty cycle based on the DCC code output from the DCC controller16band provide it to the DLL delay line11. Under the control of the DCC code regarding the duty cycle, the DCC adjustment circuit16cadjusts the duty cycle of the generated input clock signal CLKDCCuntil the duty cycle of the internal clock signal DQS reaches the predetermined value (e.g., 50%). The input clock signal CLKDCCfrom the DCC circuit16is delayed by the DLL delay line11and then output by the clock buffer circuit12as the internal clock signal DQS. Further, referring toFIG.13, the DCC controller16bmay include a DCC state machine161carrying an internal state signal (not shown) which transitions depending on the detection result of the duty cycle detection circuit16a(indicating whether the duty cycle of DQS has reached the predetermined value), and the state machine may switch between different states in response to the transitioning of the state signal. The DCC state machine161in different states can output different DCC code values which control the DCC adjustment circuit16cto adjust the duty cycle of the input clock signal CLKDCCand hence that of DQS with different duty cycle adjustment steps. The duty cycle detection circuit16adetects the duty cycle of the feedback clock signal DQS_fb, determines whether it reaches the predetermined value for the duty cycle of DQS (e.g., 50%) and outputs a high or low level to the DCC controller16bdepending on the determination. The DCC state machine161in the DCC controller16bupdates the DCC code based on the output from the duty cycle detection circuit16aand controls the DCC adjustment circuit16cto adjust the duty cycle of the input clock signal CLKDCC. Moreover, it determines whether the number of times the duty cycle of DQS_fb crosses the predetermined value (e.g., 50%) reaches a second threshold value. If so, it is considered that the duty cycle of the internal clock signal DQS reaches the predetermined value, and the value of the DCC code output from the DCC state machine161is locked for subsequent use in the next phase locking operation when the DLL enable signal Nap_en is again enabled. With combined reference toFIGS.12,13and15, as any change in the duty cycle of DQS caused by variation of the power supply voltage VDD in the low power consumption mode is actually small, relocking would be attained with only a few duty cycle adjustment steps of the DCC adjustment circuit16c. Thus, in the low power consumption mode, the DLL state machine15ais allowed to roughly determine whether the duty cycle of the internal clock signal DQS reaches the predetermined value, without having to undergo a standard process in normal locking operation. Accordingly, in another embodiment, the second threshold value may be smaller than the threshold value for determining whether the duty cycle reaches the predetermined value in normal operation of the DLL circuit22. In this way, higher relocking efficiency can be achieved, and less power can be consumed during relocking. As an example, referring toFIGS.12and13, both the duty cycle of VCLK and the predetermined value for the duty cycle of DQS are equal to 50%. As a consequence of jitter of the power supply voltage VDD, DQS that was previously locked changes into DQS (0′), and its duty cycle drops below 50%. That is, when its rising edge is aligned with the rising edge of VCLK, its falling edge is on the left side of that of VCLK. Responsively, the DLL circuit22is woken up by the DLL enable signal Nap_en from the timer unit21and commences a relocking process, in which the DCC state machine161first outputs a DCC code value of “+1” for controlling the DCC adjustment circuit16cto increase the duty cycle of DQS above 50% so that when its rising edge is aligned with the rising edge of VCLK, its falling edge crosses the falling edge of VCLK for the first time. As a result, DQS (0′) turns into DQS (1′). Subsequently, the DCC state machine161outputs a DCC code value of “−1” for controlling the DCC adjustment circuit16cto decrease the duty cycle of DQS below 50% so that when its rising edge is aligned with the rising edge of VCLK, its falling edge crosses the falling edge of VCLK for the second time. As a result, DQS (1′) turns into DQS (2′). At this point, the DCC state machine16determines that the number of times the duty cycle of DQS crosses 50% (i.e.,2) reaches the second threshold value, and it is therefore considered that duty cycle of DQS reaches the predetermined value (50%). Similarly, in case of the duty cycle of DQS rising above 50% (i.e., when its rising edge is aligned with the rising edge of VCLK, its falling edge is on the right side of that of VCLK) due to jitter of the power supply voltage VDD, the duty cycle of DQS may be first reduced below 50% so that its falling edge moves to the left side of the falling edge of VCLK, and then raised above 50% so that its falling edge moves back to the right side of the falling edge of VCLK. In this way, the number of times the duty cycle of DQS crosses the predetermined value (50%) is also 2, and the duty cycle of DQS again reaches the predetermined value. In this embodiment, the DLL circuit22may determine that phase locking is achieved when both the locking conditions shown in11and13are satisfied. When this happens, the DLL controller15and the DCC controller16will lock the DLL code value and DCC code value, respectively, for subsequent use in the next phase locking operation. As another example, referring toFIG.14, DLL circuitry system according to further embodiment of the present invention additionally includes a low dropout regulator (LDO) circuit20coupled to power supply terminals of the DLL circuit22and the timer unit21. The LDO circuit20provides the power supply voltage VDD to both the DLL circuit22and the timer unit21. Upon entry into the low power consumption mode, the power supply voltage VDD of the DLL circuit22will experience a change due to a load change of the LDO circuit20. Based on the same inventive concept, referring toFIGS.5and15, in one embodiment of the present invention, there is also provided a memory device500including the proposed DLL circuitry system51discussed above. The internal clock signal DQS output from the DLL circuitry system51serves as a data strobe pulse signal for the memory device, and the DLL circuit22in the DLL circuitry system51synchronizes the external clock signal VCLK for the memory device500with the data strobe pulse signal (edge-to-edge alignment). Further, when the memory device500receives a read command cmd under the control of the external clock signal VCLK, it reads corresponding data under the control of the data strobe pulse signal DQS generated by the DLL circuit22and sends the data out. On the one hand, in normal operation of the memory device500, since the DLL circuitry system51can maintain edge-to-edge alignment of the internal clock signal DQS with the external clock signal VCLK, a reduced eye opening during data transmission can be avoided. On the other hand, when the memory device500enters the low power consumption mode, the power supply voltage VDD of the DLL circuit22will vary due to a load change of the LDO circuit20, leading to a change in the delay of the gate circuit in the DLL delay line11of the DLL circuit22(e.g., the DLL delay line11consists of a number of NAND gates). For example, as a consequence of the entry into the low power consumption mode, the power supply voltage VDD from the LDO circuit20may rise and shorten the unit delay of the gate circuit in the DLL delay line11, destroying the edge-to-edge alignment between the internal clock signal DQS and the external clock signal VCLK that is established in normal operation. In order to overcome this, the present invention can enable the timer unit21to wake up the DLL circuit22at a correct time to realign the internal clock signal DQS with the external clock signal VCLK to eliminate the adverse influence of the variation of the power supply voltage VDD from the LDO circuit20in the low power consumption mode and thereby ensure correct data reading or writing even when data is to be read or written immediately after the memory device500exits the low power consumption mode (at this time, the power supply voltage VDD output from the LDO circuit20has not yet recovered to the normal condition). The description presented above is merely that of a few preferred embodiments of the present invention and is not intended to limit the scope thereof in any sense. Any and all changes and modifications made by those of ordinary skill in the art based on the above teachings fall within the scope as defined in the appended claims. | 50,382 |
11942955 | DETAILED DESCRIPTION FIG.1is a diagram illustrating a configuration of a semiconductor apparatus100in accordance with an embodiment. Referring toFIG.1, the semiconductor apparatus100may receive a clock signal CLK to generate a plurality of internal clock signals. The clock signal CLK may be an external clock signal provided from an external apparatus coupled to the semiconductor apparatus100. In an embodiment, the clock signal CLK may be a periodic signal generated from a clock generator such as an oscillator. The semiconductor apparatus100may perform a delay-locking operation on the clock signal CLK to generate the plurality of internal clock signals. The semiconductor apparatus100may include a delay locked loop circuit including at least two delay locked loops, which have different characteristics from each other. The delay locked loop circuit may perform the delay-locking operation on the clock signal CLK through at least one between the two delay locked loops. The two delay locked loops may include a digital delay locked loop and an analog delay locked loop. The semiconductor apparatus100may include a clock receiver110and a delay locked loop circuit120. The clock receiver110may receive the clock signal CLK. The clock receiver110may receive the clock signal CLK to output a buffered clock signal CLKR. The clock signal CLK may be transmitted, together with a complementary signal CLKB, as a differential signal. The clock signal CLK may be transmitted as a single-ended signal. When the clock signal CLK is transmitted as a differential signal, the clock receiver110may differentially amplify the clock signal CLK and the complementary signal CLKB to output the buffered clock signal CLKR. When the clock signal CLK is transmitted as a single-ended signal, the clock receiver110may differentially amplify the clock signal CLK and a reference voltage VREF to output the buffered clock signal CLKR. The reference voltage VREF may have a voltage level corresponding to a middle of the amplitude of the clock signal CLK. The delay locked loop circuit120may receive a reference clock signal and may perform a delay-locking operation on the reference clock signal. The buffered clock signal CLKR generated from the clock receiver110may be provided as the reference clock signal. The semiconductor apparatus100may further include division circuit130. The division circuit130may receive the buffered clock signal CLKR and may divide the frequency of the buffered clock signal CLKR to provide the divided clock signal as the reference clock signal. When the semiconductor apparatus100operates at a relatively low frequency, the delay locked loop circuit120may receive the buffered clock signal CLKR as the reference clock signal to perform a delay-locking operation. When the semiconductor apparatus100operates at a relatively high frequency, the delay locked loop circuit120may receive the clock signal, which is divided by the division circuit130, as the reference clock signal to perform a delay-locking operation. The division circuit130may divide the buffered clock signal CLKR to generate a first divided clock signal ICLK, a second divided clock signal QCLK, a third divided clock signal IBCLK and a fourth divided clock signal QBCLK. The first to fourth divided clock signals ICLK, QCLK, IBCLK and QBCLK may have lower frequencies or longer periods than the buffered clock signal CLKR. The first divided clock signal ICLK may have the same phase as the buffered clock signal CLKR and may have a leading phase to the second divided clock signal QCLK by an amount of 90 degrees. The second divided clock signal QCLK may have a leading phase to the third divided clock signal IBCLK by an amount of 90 degrees. The third divided clock signal IBCLK may have a leading phase to the fourth divided clock signal QBCLK by an amount of 90 degrees. The fourth divided clock signal QBCLK may have a leading phase to the first divided clock signal ICLK by an amount of 90 degrees. The delay locked loop circuit120may receive the first divided clock signal ICLK as the reference clock signal and may perform a delay-locking operation on the first divided clock signal ICLK. In an embodiment, the delay locked loop circuit120may receive the second divided clock signal QCLK as the reference clock signal and may perform a delay-locking operation on the second divided clock signal QCLK. The delay locked loop circuit120may include a first delay locked loop121and a second delay locked loop122. The first delay locked loop121may be a digital delay locked loop. The second delay locked loop122may be an analog delay locked loop. The first delay locked loop121may receive the reference clock signal and an internal reference clock signal. The first delay locked loop121may perform a delay-locking operation on the reference clock signal based on the reference clock signal and the internal reference clock signal to generate a delay locked clock signal CLKDLL. The second delay locked loop122may receive the delay locked clock signal CLKDLL and the internal reference clock signal. The second delay locked loop122may receive the delay locked clock signal CLKDLL and the internal reference clock signal and may perform a delay-locking operation on the delay locked clock signal CLKDLL to generate the internal reference clock signal. For compensation for modelled delay time, the first delay locked loop121may delay the reference clock signal to generate the delay locked clock signal CLKDLL. The second delay locked loop122may adjust the phase of the delay locked clock signal CLKDLL and may generate, from the delay locked clock signal CLKDLL, a plurality of internal clock signals having different phases from one another. The plurality of internal clock signals may include a first internal clock signal ICLKD, a second internal clock signal QCLKD, a third internal clock signal IBCLKD and a fourth internal clock signal QBCLKD. The first internal clock signal ICLKD may be provided as the internal reference clock signal. The first internal clock signal ICLKD may have a leading phase to the second internal clock signal QCLKD by an amount of 90 degrees. The second internal clock signal QCLKD may have a leading phase to the third internal clock signal IBCLKD by an amount of 90 degrees. The third internal clock signal IBCLKD may have a leading phase to the fourth internal clock signal QBCLKD by an amount of 90 degrees. The fourth internal clock signal QBCLKD may have a leading phase to the first internal clock signal ICLKD by an amount of 90 degrees. The first to fourth internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD may be provided to internal circuits, which operate in synchronization with a clock signal among various internal circuits included in the semiconductor apparatus100. Hereinafter, the terms “internal reference clock signal” and “internal clock signal” may indicate the same clock signal unless explicitly stated otherwise. In general, a digital delay locked loop may be capable of performing a fast delay-locking operation and may perform a delay-locking operation on a clock signal having a broader frequency band than an analog delay locked loop. However, it may be difficult for a delay locked loop with one delay line to perform a delay-locking operation on a clock signal having a particular frequency or higher. A dual delay locked loop is designed to have two delay lines in order to settle the difficulty. However, there may easily occur a skew on phases of a plurality of internal clock signals generated from the dual delay locked loop due to process variation between the two delay lines. Therefore, in accordance with an embodiment, the semiconductor apparatus100adopts the delay locked loop circuit120having both of a digital delay locked loop and an analog delay locked loop, which makes it possible to perform a delay-locking operation on a clock signal having a high frequency and to generate a plurality of internal clock signals having precise phase difference. FIG.2is a diagram illustrating a configuration of a delay locked loop circuit200in accordance with an embodiment. The delay locked loop circuit200may be applied as the delay locked loop circuit120illustrated inFIG.1. Referring toFIG.2, the delay locked loop circuit200may include a first delay locked loop210and a second delay locked loop220. The first delay locked loop210may be a digital delay locked loop. The second delay locked loop220may be an analog delay locked loop. The first delay locked loop210may receive a reference clock signal REFCLK and an internal clock signal ICLKD. The first delay locked loop210may perform a delay-locking operation on the reference clock signal REFCLK based on the reference clock signal REFCLK and the internal clock signal ICLKD to generate a delay locked clock signal CLKDLL. The second delay locked loop220may receive the delay locked clock signal CLKDLL. The second delay locked loop220may perform a delay-locking operation on the delay locked clock signal CLKDLL to generate first to fourth internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. Any one among the first to fourth internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD may be provided as the internal reference clock signal. For example, the first internal clock signal ICLKD may be utilized as the internal reference clock signal. The first delay locked loop210may include a first delay line211, a replica212, a first phase detector213and a delay controller214. The first delay line211may receive the reference clock signal REFCLK and a delay control signal DC. The first delay line211may delay the reference clock signal REFCLK based on the delay control signal DC to generate the delay locked clock signal CLKDLL. The first delay line211may be a digitally controlled delay line. A delay amount of the first delay line211may be set on the basis of the delay control signal DC. The first delay line211may delay the reference clock signal REFCLK by the delay amount, which is set by the delay control signal DC, to generate the delay locked clock signal CLKDLL. The replica212may receive the internal clock signal ICLKD as the internal reference clock signal. The replica212may delay the internal clock signal ICLKD to generate a first feedback clock signal FBCLK1. The replica212may be designed by modelling a transmission path, through which the clock signal CLK is transferred within the semiconductor apparatus100illustrated inFIG.1. Therefore, the replica212may have a delay amount corresponding to delay time occurring due to the transmission path, through which the clock signal CLK is transferred. The replica212may delay the internal reference clock signal by an amount of the modelled delay time to generate the first feedback clock signal FBCLK1. The first phase detector213may receive the reference clock signal REFCLK and the first feedback clock signal FBCLK1. The first phase detector213may compare phases between the reference clock signal REFCLK and the first feedback clock signal FBCLK1 to generate a first phase detection signal PD1. The first phase detector213may change the logic level of the first phase detection signal PD1 depending on whether the reference clock signal REFCLK has a leading phase or a lagging phase to the first feedback clock signal FBCLK1. For example, the first phase detector213may generate, when the reference clock signal REFCLK has a leading phase to the first feedback clock signal FBCLK1, the first phase detection signal PD1 having a high logic level. For example, the first phase detector213may generate, when the reference clock signal REFCLK has a lagging phase to the first feedback clock signal FBCLK1, the first phase detection signal PD1 having a low logic level. The delay controller214may receive the first phase detection signal PD1 to generate the delay control signal DC. The delay control signal DC may be a digital code signal having a plurality of bits. The delay controller214may change a code value of the delay control signal DC based on the first phase detection signal PD1. A delay amount of the first delay line211may increase or decrease depending on the code value of the delay control signal DC. The first delay locked loop210may perform a delay-locking operation by changing the code value of the delay control signal DC until the reference clock signal REFCLK and the first feedback clock signal FBCLK1 have the same phase. The first delay locked loop210may be locked by fixing and/or maintaining the code value of the delay control signal DC when the reference clock signal REFCLK and the first feedback clock signal FBCLK1 have the same phase. In an embodiment, the first delay locked loop210may generate the delay locked clock signal CLKDLL by performing a delay-locking operation on the reference clock signal REFCLK to set a delay of the reference clock signal REFCLK when a first feedback clock signal FBCLK1 has the same phase as the reference clock signal REFCLK. The second delay locked loop220may include a second delay line221, a second phase detector222and a charge pump223. The second delay line221may receive the delay locked clock signal CLKDLL output from the first delay locked loop210. The second delay line221may receive a delay control voltage VC and may delay the delay locked clock signal CLKDLL based on the delay control voltage VC to generate a plurality of delayed clock signals. The second delay line221may be a voltage-controlled delay line. A delay amount of the second delay line221may be set on the basis of the delay control voltage VC, which is an analog signal. The second delay line221may delay the delay locked clock signal CLKDLL by the delay amount, which is set by the delay control voltage VC, to generate the plurality of delayed clock signals. The second delay line221may output, as the first to fourth internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD, four among the plurality of delayed clock signals and may output, as a second feedback clock signal FBCLK2, another one among the plurality of delayed clock signals. The second delay line221may include a plurality of delay cells. AlthoughFIG.2exemplifies the second delay line221having nine delay cells DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8 and DC9, an embodiment will not be limited thereto. The number of delay cells included in the second delay line221may be greater or less than nine. Referring toFIGS.1and2, one delay cell may be set to have delay time corresponding to a quarter of the period of the clock signal CLK. When any one between the first divided clock signal ICLK and the second divided clock signal QCLK output from the division circuit130provided as the reference clock signal REFCLK, the one delay cell may be set to have delay time corresponding to an eighth of the period of the reference clock signal REFCLK. The second delay line221may provide, as the first internal clock signal ICLKD, a delayed clock signal output from the first delay cell DC1. The first internal clock signal ICLKD may be provided as the internal reference clock signal. The second delay line221may provide, as the second internal clock signal QCLKD, a delayed clock signal output from the third delay cell DC3. The second delay line221may provide, as the third internal clock signal IBCLKD, a delayed clock signal output from the fifth delay cell DC5. The second delay line221may provide, as the fourth internal clock signal QBCLKD, a delayed clock signal output from the seventh delay cell DC7. The second delay line221may provide, as the second feedback clock signal FBCLK2, a delayed clock signal output from the last delay cell DC9. The second phase detector222may receive the internal reference clock signal and the second feedback clock signal FBCLK2. The second phase detector222may generate a second phase detection signal PD2 based on the phases of the internal clock signal ICLKD, which is provided as the internal reference clock signal, and the second feedback clock signal FBCLK2. For example, the second phase detection signal PD2 may include an up signal UP and a down signal DN. The second phase detector222may enable the up signal UP based on the phase of the internal clock signal ICLKD. The second phase detector222may enable the down signal DN based on the phase of the second feedback clock signal FBCLK2. The second phase detector222may enable the up signal UP when the phase of the internal clock signal ICLKD transitions from a low logic level to a high logic level. The second phase detector222may enable the down signal DN when the phase of the second feedback clock signal FBCLK2 transitions from a low logic level to a high logic level. The second phase detector222may reset the up signal UP and the down signal DN when a predetermined time elapses. The second phase detector222may disable both of the up signal UP and the down signal DN when the predetermined time elapses from a time point, at which any signal is enabled later than the other signal between the up signal UP and the down signal DN. The predetermined time may be less than a time corresponding to a half of the period of the reference clock signal REFCLK and/or the second feedback clock signal FBCLK2. The word “predetermined” as used herein with respect to a parameter, such as a predetermined time and predetermined amount, means that a value for the parameter is determined prior to the parameter being used in a process or algorithm. For some embodiments, the value for the parameter is determined before the process or algorithm begins. In other embodiments, the value for the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm. The charge pump223may receive the second phase detection signal PD2 and may generate the delay control voltage VC based on the second phase detection signal PD2. The charge pump223may raise the voltage level of the delay control voltage VC based on the up signal UP and may lower the voltage level of the delay control voltage VC based on the down signal DN. When the voltage level of the delay control voltage VC rises, the delay time of the delay cells DC1 to DC9 configuring the second phase detector222may decrease. When the voltage level of the delay control voltage VC lowers, the delay time of the delay cells DC1 to DC9 configuring the second phase detector222may increase. The second delay locked loop220may perform a delay-locking operation by changing the value of the delay control voltage VC until the internal reference clock signal and the second feedback clock signal FBCLK2 have the same phase. The second delay locked loop220may be locked by fixing and maintaining the voltage level of the delay control voltage VC when the internal reference clock signal and the second feedback clock signal FBCLK2 have the same phase. In an embodiment, the second delay locked loop220may generate the internal reference clock signal by performing a delay-locking operation on the delay locked clock signal CLKDLL to set a delay of the delay locked clock signal CLKDLL when a second feedback clock signal FBCLK2 has the same phase as the internal reference clock signal. FIG.3is a diagram schematically illustrating configurations of the second phase detector222and the charge pump223illustrated inFIG.2. The second phase detector222may include a first set of plural drivers311and a second set of plural drivers312. The first set of plural drivers311may receive the first internal clock signal ICLKD and may generate the up signal UP by driving the first internal clock signal ICLKD. The second set of plural drivers312may receive the second feedback clock signal FBCLK2 and may generate the down signal DN by driving the second feedback clock signal FBCLK2. The charge pump223may include a pull-up current source321, a pull-down current source322, a capacitor323, a first switch324and a second switch325. The pull-up current source321may be coupled between a node, from which a high voltage VH is provided, and an output node ON. The pull-up current source321may generate a pull-up current IUP. The delay control voltage VC may be generated from the output node ON. The pull-up current source321may be implemented by at least one P-channel MOS transistor configured to receive a bias voltage or a current control signal. The pull-down current source322may be coupled between the output node ON and a node, from which a low voltage VL is provided. The pull-down current source322may generate a pull-down current IDN. The low voltage VL may have a lower voltage level than the high voltage VH. The pull-down current source322may be implemented by at least one N-channel MOS transistor configured to a bias voltage or a current control signal. The capacitor323may be coupled to the output node ON at one end and may be coupled to the node, from which the low voltage VL is provided, at the other node. The voltage level of the output node ON and the delay control voltage VC may change depending on an amount of charge that is charged into the capacitor323. The first switch324may receive the up signal UP. The first switch324may couple the pull-up current source321to the output node ON based on the up signal UP. When the first switch324turned on according to the up signal UP, the pull-up current IUP may be provided to the output node ON and the capacitor323may be charged. Therefore, the voltage level of the output node ON and the delay control voltage VC may rise. The second switch325may receive the down signal DN. The second switch325may couple the pull-down current source322to the output node ON based on the down signal DN. When the second switch325is turned on according to the down signal DN, the pull-down current IDN may flow from the output node ON to the node, from which the low voltage VL is provided, and the capacitor323may be discharged. Therefore, the voltage level of the output node ON and the delay control voltage VC may lower. There may be delay mismatch in the second phase detector222due to local process variation between the first set of plural drivers311and the second set of plural drivers312. Therefore, there may occur an error between a time, at which the up signal UP is enabled according to a rising edge of the first internal clock signal ICLKD, and a time, at which the down signal DN is enabled according to a rising edge of the second feedback clock signal FBCLK2. Further, since the pull-up current source321is configured by a P-channel MOS transistor and the pull-down current source322is configured by a N-channel MOS transistor in the charge pump223, there may occur an error in sizes between the pull-up current IUP and the pull-down current IDN in spite of size adjustment of the transistors when designed. Therefore, there should occur a phase error between the first internal clock signal ICLKD and the second feedback clock signal FBCLK2 even when the second delay locked loop220illustrated inFIG.2completes a delay-locking operation. The phase error may be represented by a following equation. Δt2=ΔtMIS+tRESET*(1−IUP/IDN) In the above equation, “Δt2” may represent the phase error between the first internal clock signal ICLKD and the second feedback clock signal FBCLK2 when the second delay locked loop220is locked, “ΔtMIS” may represent the delay mismatch by the second phase detector222and “tRESET” may represent the predetermined time when the up signal UP and the down signal DN are reset. In general, in order to improve “Δt2”, the amount of the pull-up current IUP and the pull-down current IDN which are provided for the charge pump223to generate the delay control voltage VC may be adjusted. However, it may be difficult to implement high resolution by the scheme of adjusting the current amount of the charge pump223and the mismatch may occur again between the adjusted pull-up current IUP and pull-down current IDN. Therefore, it may be difficult to fundamentally resolve the phase error between the first internal clock signal ICLKD and the second feedback clock signal FBCLK2. FIG.4is a diagram illustrating a configuration of an analog delay locked loop400in accordance with an embodiment. The analog delay locked loop400may be applied as the second delay locked loop122illustrated inFIG.1. The analog delay locked loop400may replace the second delay locked loop220illustrated inFIG.2. The analog delay locked loop400may include a delay line410, a calibration circuit420, a phase detector430and a charge pump440. The delay line410receives the reference clock signal REFCLK and the delay control voltage VC. When the analog delay locked loop400replaces the second delay locked loop220illustrated inFIG.2, the reference clock signal REFCLK may correspond to the delay locked clock signal CLKDLL. The delay line410may delay the reference clock signal REFCLK based on the delay control voltage VC to generate the plurality of delayed clock signals. The delay line410may output one among the plurality of delayed clock signals as the internal reference clock signal and may output another one among the plurality of delayed clock signals as the feedback clock signal FBCLK. The delay line410may generate four among the plurality of delayed clock signals, as the first internal clock signal ICLKD, the second internal clock signal QCLKD, the third internal clock signal IBCLKD and the fourth internal clock signal QBCLKD. The delay line410may provide the first internal clock signal ICLKD as the internal reference clock signal. The delay line410may include a plurality of delay cells DC1 to DC9 respectively configured to output the plurality of delayed clock signals. The configurations of the delay line410may be the same as the configurations of the second delay line221and thus redundant description about the same elements will be omitted. The calibration circuit420may receive the first internal clock signal ICLKD and the feedback clock signal FBCLK. The calibration circuit420may generate a delayed reference clock signal REFD from the reference clock signal based on the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK. The calibration circuit420may generate a delayed feedback clock signal FEBD from the feedback clock signal FBCLK. The calibration circuit420may change the delay amount of the first internal clock signal ICLKD and the delay amount of the feedback clock signal FBCLK according to relative phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK. The calibration circuit420may delay, for a longer time, a clock signal having a lagging phase to the other clock signal between the first internal clock signal ICLKD and the feedback clock signal FBCLK. For example, when the first internal clock signal ICLKD has a leading phase to the feedback clock signal FBCLK, the calibration circuit420may delay the first internal clock signal ICLKD for a first time to generate the delayed reference clock signal REFD and may delay the feedback clock signal FBCLK for a second time to generate the delayed feedback clock signal FEBD. The second time may be longer than the first time. For example, when the first internal clock signal ICLKD has a lagging phase to the feedback clock signal FBCLK, the calibration circuit420may delay the first internal clock signal ICLKD for the second time to generate the delayed reference clock signal REFD and may delay the feedback clock signal FBCLK for the first time to generate the delayed feedback clock signal FEBD. The phase detector430may receive the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The phase detector430may detect the phases of the delayed reference clock signal REFD and the delayed feedback clock signal FEBD to generate a phase detection signal PD. The phase detection signal PD may include the up signal UP and the down signal DN. The charge pump440may generate the delay control voltage VC based on the phase detection signal PD. The phase detector430and the charge pump440may have the same configurations and may perform the same operations as the second phase detector222and the charge pump223illustrated inFIGS.2and3. Redundant description about the same configurations will be omitted. The calibration circuit420may include a timing skew detector421, a calibration signal generator422and a delay adjuster423. The timing skew detector421may detect phase difference between the first internal clock signal ICLKD and the feedback clock signal FBCLK. The timing skew detector421may detect the phase difference between the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate a first phase adjustment signal FEBINC and a second phase adjustment signal REFINC. The timing skew detector421may detect the phase difference between the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate a first skew detection signal and a second skew detection signal. The timing skew detector421may generate the first phase adjustment signal FEBINC and the second phase adjustment signal REFINC according to whether the logic levels of the first skew detection signal and the second skew detection signal stay kept for an time corresponding to at least double of a unit cycle. The time corresponding to at least double of the unit cycle may be a loop bandwidth of the calibration circuit420and may represent a period when the calibration circuit420is updated. The loop bandwidth of the calibration circuit420may be smaller than a loop bandwidth of the analog delay locked loop400. The period when the calibration circuit420is updated may be greater than a period when the analog delay locked loop400is updated. In an embodiment, the loop bandwidth of the calibration circuit420may be set as three times of the unit cycle or greater. The unit cycle may be determined on the basis of the plurality of delayed clock signals generated from the delay line410. The unit cycle will be described later. The calibration signal generator422may receive the first phase adjustment signal FEBINC and the second phase adjustment signal REFINC to generate a calibration signal CAL<1:2N>. The calibration signal CAL<1:2N> may be a digital code signal having a plurality of bits. The calibration signal generator422may change a value of a part of the calibration signal CAL<1:2N> based on the first phase adjustment signal FEBINC. The calibration signal generator422may change a value of a remaining part of the calibration signal CAL<1:2N> based on the second phase adjustment signal REFINC. For example, the calibration signal CAL<1:2N> may have 2N number of bits. Here, N is an integer equal to or greater than 2. The calibration signal generator422may change a value of first to Nthbits CAL<1:N> of the calibration signal CAL<1:2N> based on the first phase adjustment signal FEBINC. The calibration signal generator422may change a value of (N+1)thto 2Nthbits CAL<N+1:2N> of the calibration signal CAL<1:2N> based on the second phase adjustment signal REFINC. The calibration signal generator422may include configurations such as a decoding circuit, a shift register circuit and so forth such that the calibration signal generator422decodes the first phase adjustment signal FEBINC and the second phase adjustment signal REFINC and changes a value of the first to 2Nthbits CAL<1:2N> of the calibration signal CAL<1:2N> according to the result of the decoding. The delay adjuster423may receive the calibration signal CAL<1:2N>. The delay adjuster423may delay the first internal clock signal ICLKD based on a part of the calibration signal CAL<1:2N> to generate the delayed reference clock signal REFD. The delay adjuster423may delay the feedback clock signal FBCLK based on a remaining part of the calibration signal CAL<1:2N> to generate the delayed feedback clock signal FEBD. The delay adjuster423may delay the first internal clock signal ICLKD by a predetermined amount based on the first to Nthbits CAL<1:N> of the calibration signal CAL<1:2N> to generate the delayed reference clock signal REFD. The delay adjuster423may delay the feedback clock signal FBCLK by a predetermined amount based on the (N+1)th to 2Nthbits CAL<N+1:2N> of the calibration signal CAL<1:2N> to generate the delayed feedback clock signal FEBD. FIG.5is a diagram illustrating a configuration of timing skew detector421illustrated inFIG.4. Referring toFIG.5, the timing skew detector421may include a skew detector510, a filter520and a phase adjustment signal generator530. The skew detector510may detect the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate a first skew detection signal SKW1 and a second skew detection signal SKW2. The first skew detection signal SKW1 may include information on whether the first internal clock signal ICLKD has a leading phase or a lagging phase to the feedback clock signal FBCLK. The second skew detection signal SKW2 may include information on whether the feedback clock signal FBCLK has a leading phase or a lagging phase to the first internal clock signal ICLKD. The filter520may receive the first skew detection signal SKW1 and the second skew detection signal SKW2. The filter520may generate a first phase information signal SLOW and a second phase information signal FAST based on the first skew detection signal SKW1 and the second skew detection signal SKW2. The first phase information signal SLOW may be enabled when the feedback clock signal FBCLK has a lagging phase to the first internal clock signal ICLKD. The second phase information signal FAST may be enabled with the feedback clock signal FBCLK has a leading phase to the first internal clock signal ICLKD. The filter520may define the loop bandwidth of the calibration circuit420based on one among the plurality of delayed clock signals. The filter520may generate the first phase information signal SLOW and the second phase information signal FAST based on whether the logic levels of the first skew detection signal SKW1 and the second skew detection signal SKW2 stay kept at the same logic level, for a time corresponding to the loop bandwidth. The phase adjustment signal generator530may receive the first phase information signal SLOW and the second phase information signal FAST. The phase adjustment signal generator530may generate the first phase adjustment signal FEBINC based on the first phase information signal SLOW. The phase adjustment signal generator530may generate the second phase adjustment signal REFINC based on the second phase information signal FAST. The skew detector510may include a first flip-flop511and a second flip-flop512. Each of the first flip-flop511and the second flip-flop512may be a D flip-flop. The first flip-flop511may receive the first internal clock signal ICLKD at its input node D, may receive the feedback clock signal FBCLK at its clock node and may output the first skew detection signal SKW1 at its output node Q. The second flip-flop512may receive the feedback clock signal FBCLK at its input node D, may receive the first internal clock signal ICLKD at its clock node and may output the second skew detection signal SKW2 at its output node Q. In order to reduce a malfunction that can occur due to variation of setup times and hold times of the first flip-flop511and the second flip-flop512, the skew detector510may detect a skew between phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK in a dual mode. The filter520may include a first flip-flop521, a second flip-flop522, a third flip-flop523, a fourth flip-flop524, a first gating circuit525and a second gating circuit526. Each of the first to fourth flip-flops521,522,523and524may be a D flip-flop. The first flip-flop521may receive the first skew detection signal SKW1 at its input node D, may receive a first clock signal EVCLK at its clock node and may output a first even signal EV1 at its output node Q. The second flip-flop522may receive the second skew detection signal SKW2 at its input node D, may receive the first clock signal EVCLK at its clock node and may output a second even signal EV2 at its output node Q. The third flip-flop523may receive the first skew detection signal SKW1 at its input node D, may receive a second clock signal ODCLK at its clock node and may output a first odd signal OD1 at its output node Q. The second clock signal ODCLK may have a lagging phase to the first clock signal EVCLK. The fourth flip-flop524may receive the second skew detection signal SKW2 at its input node D, may receive the second clock signal ODCLK at its clock node and may output a second odd signal OD2 at its output node Q. The first gating circuit525may receive the first even signal EV1, the first odd signal OD1, the second even signal EV2 and the second odd signal OD2. The first gating circuit525may perform an AND operation on the received signals to generate the first phase information signal SLOW. The first gating circuit525may include an AND gate. The first gating circuit525may receive the first even signal EV1, the first odd signal OD1, an inverted signal of the second even signal EV2 and an inverted signal of the second odd signal OD2 to generate the first phase information signal SLOW. The second gating circuit526may receive the first even signal EV1, the first odd signal OD1, the second even signal EV2 and the second odd signal OD2. The second gating circuit526may perform an AND operation on the received signal to generate the second phase information signal FAST. The second gating circuit526may include an AND gate. The second gating circuit526may receive an inverted signal of the first even signal EV1, an inverted signal of the first odd signal OD1, the second even signal EV2 and the second odd signal OD2 to generate the second phase information signal FAST. In order to reduce the loop bandwidth of the calibration circuit420and increase the update period of the calibration circuit420, the filter520may further include an additional flip-flop. The additional flip-flop may receive a clock signal having a lagging phase to the second clock signal ODCLK. The gating circuits may be modified to further receive a signal output from the additional flip-flop. The first gating circuit525may output, when the first even signal EV1 and the first odd signal OD1 are of a high logic level and the second even signal EV2 and the second odd signal OD2 are of a low logic level, the first phase information signal SLOW of a high logic level. The second gating circuit526may output, when the first even signal EV1 and the first odd signal OD1 are of a low logic level and the second even signal EV2 and the second odd signal OD2 are of a high logic level, the second phase information signal FAST of a high logic level. The first even signal EV1 and the second even signal EV2 may be generated in synchronization with the first clock signal EVCLK. The first odd signal OD1 and the second odd signal OD2 may be generated in synchronization with the second clock signal ODCLK. Therefore, the filter520may enable the first phase information signal SLOW and the second phase information signal FAST to a high logic level only when the logic levels of the first skew detection signal SKW1 and the second skew detection signal SKW2 are kept at the high logic level until transitions of the first clock signal EVCLK and the second clock signal ODCLK are generated. In general, a delay locked loop may cause a bang-bang jitter and thus an incorrect calibration operation may be performed in a case of generating phase information signal directly from the first skew detection signal SKW1 and the second skew detection signal SKW2. In accordance with an embodiment, a value of a calibration signal may change according to a phase information signal only when the logic levels of the first skew detection signal SKW1 and the second skew detection signal SKW2 are kept at a same logic level for a predetermined time. Therefore, a precise calibration operation may be performed. The phase adjustment signal generator530may include a first gating circuit531, a second gating circuit532and a third gating circuit533. The first gating circuit531may receive the first phase information signal SLOW and the second phase information signal FAST to generate a calibration enable signal CALON. The first gating circuit531may perform an OR operation on the first phase information signal SLOW and the second phase information signal FAST to generate the calibration enable signal CALON. The first gating circuit531may include an OR gate. The first gating circuit531may enable, when at least one between the first phase information signal SLOW and the second phase information signal FAST is enabled to a high logic level, the calibration enable signal CALON to a high logic level. The second gating circuit532may receive the first phase information signal SLOW, the calibration enable signal CALON and a third clock signal ODCLKB. The third clock signal ODCLKB may have a lagging phase to the second clock signal ODCLK. The second gating circuit532may perform an AND operation on the first phase information signal SLOW, the calibration enable signal CALON and the third clock signal ODCLKB to generate the first phase adjustment signal FEBINC. The second gating circuit532may include an AND gate. The second gating circuit532may enable the first phase adjustment signal FEBINC to a high logic level when both of the first phase information signal SLOW and the calibration enable signal CALON are of a high logic level while the third clock signal ODCLKB is of a high logic level. The third gating circuit533may receive the second phase information signal FAST, the calibration enable signal CALON and the third clock signal ODCLKB. The third gating circuit533may perform an AND operation on the second phase information signal FAST, the calibration enable signal CALON and the third clock signal ODCLKB to generate the second phase adjustment signal REFINC. The third gating circuit533may include an AND gate. The third gating circuit533may enable the second phase adjustment signal REFINC to a high logic level when both of the second phase information signal FAST and the calibration enable signal CALON are of a high logic level while the third clock signal ODCLKB is of a high logic level. The timing skew detector421may further include a control clock generator540. The control clock generator540may receive one among the plurality of delayed clock signals generated from the voltage-controlled delay line410illustrated inFIG.4. For example, the control clock generator540may receive the delayed clock signal CLK4 output from the fourth delay cell DC4 of the voltage-controlled delay line410. The control clock generator540may generate the first clock signal EVCLK, the second clock signal ODCLK and the third clock signal ODCLKB from the delayed clock signal CLK4. The control clock generator540may include a first divider541, a first inverter542, a second divider543, a third divider544and a second inverter545. The first divider541may divide the delayed clock signal CLK4. The first inverter542may invert the output of the first divider541. The second divider543may divide the output of the first inverter542to generate the first clock signal EVCLK. The third divider544may divide the output of the first divider541to generate the second clock signal ODCLK. The second inverter545may invert the second clock signal ODCLK to generate the third clock signal ODCLKB. FIG.6is a diagram illustrating a configuration of the delay adjuster423illustrated inFIG.4. Referring toFIG.6, the delay adjuster423may include a first variable delayer610and a second variable delayer620. The first variable delayer610may receive the first internal clock signal ICLKD and the first to Nthbits CAL<1:N> of the calibration signal CAL<1:2N> to generate the delayed reference clock signal REFD. A delay amount of the first variable delayer610may be set on the basis of the first to Nthbits CAL<1:N> of the calibration signal CAL<1:2N>. The first variable delayer610may delay the first internal clock signal ICLKD by the set delay time to generate the delayed reference clock signal REFD. The second variable delayer620may receive the feedback clock signal FBCLK and the (N+1)thto 2Nthbits CAL<N+1:2N> of the calibration signal CAL<1:2N> to generate the delayed feedback clock signal FEBD. A delay amount of the second variable delayer620may be set on the basis of the (N+1)thto 2Nthbits CAL<N+1:2N> of the calibration signal CAL<1:2N>. The second variable delayer620may delay the feedback clock signal FBCLK by the set delay time to generate the delayed feedback clock signal FEBD. FIG.7is a timing diagram illustrating operations of the calibration circuit420and the analog delay locked loop400in accordance with an embodiment. Hereinafter, described with reference toFIGS.3to6will be the operations of the calibration circuit420and the analog delay locked loop400. In S1, the skew detector510of the timing skew detector421may detect the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate the first skew detection signal SKW1 and the second skew detection signal SKW2. As illustrated inFIG.7, when the first internal clock signal ICLKD has a lagging phase to the feedback clock signal FBCLK due to the phase error “Δt2” caused by the phase detector430and the charge pump440, the skew detector510may generate the first skew detection signal SKW1 having a low logic level and the second skew detection signal SKW2 having a high logic level. The calibration signal CAL<1:2N> may keep a default value before update. The delay adjuster423may delay the first internal clock signal ICLKD and the feedback clock signal FBCLK by the same time to generate the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The phase detector430may enable the down signal DN when the delayed feedback clock signal FEBD transitions from a low logic level to a high logic level. The phase detector430may enable the up signal UP when the first internal clock signal ICLKD transitions from a low logic level to a high logic level. The up signal UP and the down signal DN may stay enabled until reset. A pulse width of the down signal DN may be wider than a pulse width of the up signal UP. In an ideal case, the charge pump440should generate the delay control voltage VC having a lower level based on the up signal UP and the down signal DN. However, when the pull-up current IUP is greater than the pull-down current IDN due to the mismatch between the pull-up current IUP and the pull-down current IDN of the charge pump440, there may occur a malfunction that the voltage level of the delay control voltage VC cannot lower and stays to a previous voltage level. Therefore, it is impossible, only by the phase detector430and the charge pump440, to match the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK. When the logic levels of the first skew detection signal SKW1 and the second skew detection signal SKW2 are kept at a same logic level for a predetermined time, the filter520of the calibration circuit420may keep the first phase information signal SLOW disabled and may enable the second phase information signal FAST to a high logic level. In S2, the phase adjustment signal generator530may enable the second phase adjustment signal REFINC according to the second phase information signal FAST. The calibration signal generator422may increase the value of the (N+1)thto 2Nthbits CAL<N+1:2N> of the calibration signal CAL<1:2N>. The delay adjuster423may delay the feedback clock signal FBCLK by a relatively longer time to generate the delayed feedback clock signal FEBD. The delay adjuster423may delay the first internal clock signal ICLKD by a relatively shorter time to generate the delayed reference clock signal REFD. Therefore, the phase difference between the delayed reference clock signal REFD and the delayed feedback clock signal FEBD may become greater than the phase difference between the first internal clock signal ICLKD and the feedback clock signal FBCLK. The delayed reference clock signal REFD may be further delayed than the delayed feedback clock signal FEBD by a calibrated phase “Δt3”, which is set by a calibration operation. The phase detector430may enable the down signal DN when the delayed feedback clock signal FEBD transitions from a low logic level to a high logic level. The phase detector430may enable the up signal UP when the delayed reference clock signal REFD transitions from a low logic level to a high logic level. The up signal UP and the down signal DN may stay enabled until reset. The up signal UP may have the same pulse width as the up signal UP generated in S1. The down signal DN may have a greater pulse width than the down signal DN generated in S1. The charge pump440may pull-down the delay control voltage VC for a longer time according to the down signal DN. Therefore, the voltage level of the delay control voltage VC may lower even when the pull-up current IUP is greater than the pull-down current IDN. In S3, when the voltage level of the delay control voltage VC lowers, the phased of the first internal clock signal ICLKD and the feedback clock signal FBCLK, which are generated from the delay line410, may be matched. The delayed reference clock signal REFD and the delayed feedback clock signal FEBD may have lagging phases to the delayed reference clock signal REFD and the delayed feedback clock signal FEBD illustrated in S2. Therefore, the voltage level of the delay control voltage VC may become lower than the voltage level of the delay control voltage VC illustrated in S2. Since the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK are matched, the calibration circuit420may terminate the calibration operation and may keep the value of the calibration signal CAL<1:2N>. The delay adjuster423may further delay the first internal clock signal ICLKD with respect to the feedback clock signal FBCLK by the delay time, which is set by the calibration operation, to generate the delayed reference clock signal REFD. Therefore, the delayed reference clock signal REFD may have a lagging phase, by an amount of the calibrated phase “Δt3” that is set by the calibration operation, to the delayed feedback clock signal FEBD. The phase difference between the delayed reference clock signal REFD and the delayed feedback clock signal FEBD may compensate for the phase error “Δt2” caused by the local process variation of the phase detector430and the mismatch between pull-up current IUP and the pull-down current IDN of the charge pump440. The delay control voltage VC generated from the charge pump440may keep having a specific level. Therefore, the analog delay locked loop400may generate the first internal clock signal ICLKD and the feedback clock signal FBCLK, of which the phases are matched by the calibration circuit420. FIG.8Ais a diagram illustrating a configuration of a delay line800in accordance with an embodiment.FIG.8Bis a timing diagram illustrating an operation of the delay line800illustrated in FIG.8A. The delay line800may be applied as a part of each of the second delay line221and the delay line410respectively illustrated inFIGS.2and4. Referring toFIG.8A, the delay line800may include a first delay cell810and a second delay cell820. The first delay cell810may invert an input signal IN to generate a first output signal OUT1. The first delay cell810may inversion-drive the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell820may invert the first output signal OUT1 to generate a second output signal OUT2. The second delay cell820may inversion-drive the second output signal OUT2 to output a second delayed clock signal DCLK2. Pull-down driving force, with which the first delay cell810pulls down the first output signal OUT1 according to the input signal IN, may change based on the delay control voltage VC. When the pull-down driving force of the first delay cell810changes, a delay amount of the first delay cell810may change. Pull-down driving force, with which the second delay cell820pulls down the second output signal OUT2 according to the first output signal OUT1, may change based on the delay control voltage VC. When the pull-down driving force of the second delay cell820changes, a delay amount of the second delay cell820may change. In an embodiments, a voltage level outputted from the delay cell may be quickly changed and the delay amount of the delay cell may be decreased as the pull-down driving force of the delay cell is increased. The voltage level outputted from the delay cell may be slowly changed and the delay amount of the delay cell may be increased as the pull-down driving force of the delay cell is decreased. The first delay cell810may include a first inverter811and a first current source812. The first inverter811may receive the input signal IN and may invert the input signal IN to generate the first output signal OUT1. The first inverter811may be coupled between a node, from which the high voltage VH is provided, and a node, from which the low voltage VL is provided. The first inverter811may invert the input signal IN. The high voltage VH may have a higher voltage level than the low voltage VL. The first current source812may be coupled between the first inverter811and the node, from which the low voltage VL is provided. The first current source812may receive the delay control voltage VC. The first current source812may change the pull-down driving force of the first inverter811based on the delay control voltage VC to change the delay amount of the first delay cell810. The first delay cell810may further include a second inverter813. The second inverter813may inversion-drive the first output signal OUT1 to output the first delayed clock signal DCLK1. The second delay cell820may include a third inverter821and a second current source822. The third inverter821may receive the first output signal OUT1 and may invert the first output signal OUT1 to generate the second output signal OUT2. The third inverter821may be coupled between the node, from which the high voltage VH is provided, and the node, from which the low voltage VL is provided. The third inverter821may invert the first output signal OUT1. The second current source822may be coupled between the third inverter821and the node, from which the low voltage VL is provided. The second current source822may receive the delay control voltage VC. The second current source822may change the pull-down driving force of the third inverter821based on the delay control voltage VC to change the delay amount of the second delay cell820. The second delay cell820may further include a fourth inverter823. The fourth inverter823may inversion-drive the second output signal OUT2 to output the second delayed clock signal DCLK2. The first inverter811may include a first transistor M1 and a second transistor M2. The first transistor M1 may be a P-channel MOS transistor. The second transistor M2 may be a N-channel MOS transistor. The first current source812may include a third transistor M3. The third transistor M3 may be a N-channel MOS transistor. The first transistor M1 may receive the input signal IN at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a first output node ON1 at its drain. The first output signal OUT1 may be output through the first output node ON1. The second transistor M2 may receive the input signal IN at its gate and may be coupled to the first output node ON1 at its drain. The third transistor M3 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the second transistor M2 and may be coupled to the node, from which the low voltage VL is provided, at its source. The third transistor M3 may change an amount of current flowing from the source of the second transistor M2 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The third inverter821may include a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 may be a P-channel MOS transistor. The fifth transistor M5 may be a N-channel MOS transistor. The second current source822may include a sixth transistor M6. The sixth transistor M6 may be a N-channel MOS transistor. The fourth transistor M4 may receive the first output signal OUT1 at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a second output node ON2 at its drain. The second output signal OUT2 may be output through the second output node ON2. The fifth transistor M5 may receive the first output signal OUT1 at its gate and may be coupled to the second output node ON2 at its drain. The sixth transistor M6 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the fifth transistor M5 and may be coupled to the node, from which the low voltage VL is provided, at its source. The sixth transistor M6 may change an amount of current flowing from the source of the fifth transistor M5 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The delay line800has an advantage that the delay amounts of the first delay cell810and the second delay cell820can change based on the delay control voltage VC, which is an analog signal, and thus the delay variation is reduced and the phase skew is reduced in spite of a high frequency of the input signal IN input to the delay line800. However, due to the characteristic of the N-channel MOS transistor that loss occurs in a threshold voltage and the voltage level variation that high boundary of the voltage level is increased, there is a problem that the first output signal OUT1 and the second output signal OUT2 cannot fully swing to the voltage level of the low voltage VL, as illustrated inFIG.8B. When the first output signal OUT1 and the second output signal OUT2 cannot fully swing, a waveform of a final output signal becomes more distorted as a number of delay cells becomes greater and a precise output signal cannot be generated at a high-speed operation. FIG.9Ais a diagram illustrating a configuration of a delay line900in accordance with an embodiment.FIG.9Bis a timing diagram illustrating an operation of the delay line900illustrated inFIG.9A. The delay line900may be applied as a part of each of the second delay line221and the delay line410respectively illustrated inFIGS.2and4. Referring toFIG.9A, the delay line900may include a first delay cell910and a second delay cell920. The first delay cell910may invert an input signal IN to generate a first output signal OUT1. The first delay cell910may inversion-drive the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell920may invert the first output signal OUT1 to generate a second output signal OUT2. The second delay cell920may inversion-drive the second output signal OUT2 to output a second delayed clock signal DCLK2. Pull-down driving force, with which the first delay cell910pulls down the first output signal OUT1 according to the input signal IN, may change based on the delay control voltage VC and the second output signal OUT2. When the pull-down driving force of the first delay cell910changes, a delay amount of the first delay cell910may change. Pull-down driving force, with which the second delay cell920pulls down the second output signal OUT2 according to the first output signal OUT1, may change based on the delay control voltage VC. When the pull-down driving force of the second delay cell920changes, a delay amount of the second delay cell920may change. In an embodiment, the second delay cell920may further receive an output signal OUT3 output from a subsequent delay cell, which is disposed subsequently to the second delay cell920and configured to receive the second output signal OUT2. The pull-down driving force and the delay amount of the second delay cell920may change based on the delay control voltage VC and the output signal OUT3 output from the subsequent delay cell. The first delay cell910may include a first inverter911, a first current source912and a first feedback current source913. The first inverter911may receive the input signal IN and may invert the input signal IN to generate the first output signal OUT1. The first inverter911may be coupled between a node, from which the high voltage VH is provided, and a node, from which the low voltage VL is provided. The first inverter911may invert the input signal IN. The first current source912may be coupled between the first inverter911and the node, from which the low voltage VL is provided. The first current source912may receive the delay control voltage VC. The first current source912may change the pull-down driving force of the first inverter911based on the delay control voltage VC to change the delay amount of the first delay cell910. The first feedback current source913may be coupled between the first inverter911and the node, from which the low voltage VL is provided. The first feedback current source913may receive the second output signal OUT2. The first feedback current source913may further change the pull-down driving force of the first inverter911based on the second output signal OUT2. The first delay cell910may further include a second inverter914. The second inverter914may inversion-drive the first output signal OUT1 to output the first delayed clock signal DCLK1. The second delay cell920may include a third inverter921, a second current source922and a second feedback current source923. The third inverter921may receive the first output signal OUT1 and may invert the first output signal OUT1 to generate the second output signal OUT2. The third inverter921may be coupled between the node, from which the high voltage VH is provided, and the node, from which the low voltage VL is provided. The third inverter921may invert the first output signal OUT1. The second current source922may be coupled between the third inverter921and the node, from which the low voltage VL is provided. The second current source922may receive the delay control voltage VC. The second current source922may change the pull-down driving force of the third inverter921based on the delay control voltage VC to change the delay amount of the second delay cell920. The second feedback current source923may be coupled between the third inverter921and the node, from which the low voltage VL is provided. The second feedback current source923may receive the output signal OUT3 output from the subsequent delay cell. The second feedback current source923may further change the pull-down driving force of the third inverter921based on the output signal OUT3 output from the subsequent delay cell. The second delay cell920may further include a fourth inverter924. The fourth inverter924may inversion-drive the second output signal OUT2 to output the second delayed clock signal DCLK2. The first inverter911may include a first transistor T1 and a second transistor T2. The first transistor T1 may be a P-channel MOS transistor. The second transistor T2 may be a N-channel MOS transistor. The first current source912may include a third transistor T3. The third transistor T3 may be a N-channel MOS transistor. The first feedback current source913may include a fourth transistor T4. The fourth transistor T4 may be a N-channel MOS transistor. The first transistor T1 may receive the input signal IN at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a first output node ON1 at its drain. The first output signal OUT1 may be output through the first output node ON1. The second transistor T2 may receive the input signal IN at its gate and may be coupled to the first output node ON1 at its drain. The third transistor T3 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the second transistor T2 and may be coupled to the node, from which the low voltage VL is provided, at its source. The third transistor T3 may change an amount of current flowing from the source of the second transistor T2 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The fourth transistor T4 may receive the second output signal OUT2 at its gate, may be coupled at its drain to the source of the second transistor T2 and may be coupled to the node, from which the low voltage VL is provided, at its source. The fourth transistor T4 may further change the amount of current flowing from the source of the second transistor T2 to the node, from which the low voltage VL is provided, based on the second output signal OUT2. The third inverter921may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may be a P-channel MOS transistor. The sixth transistor T6 may be a N-channel MOS transistor. The second current source922may include a seventh transistor T7. The seventh transistor T7 may be a N-channel MOS transistor. The second feedback current source923may include an eighth transistor T8. The eighth transistor T8 may be a N-channel MOS transistor. The fifth transistor T5 may receive the first output signal OUT1 at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a second output node ON2 at its drain. The second output signal OUT2 may be output through the second output node ON2. The sixth transistor T6 may receive the first output signal OUT1 at its gate and may be coupled to the second output node ON2 at its drain. The seventh transistor T7 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the sixth transistor T6 and may be coupled to the node, from which the low voltage VL is provided, at its source. The seventh transistor T7 may change an amount of current flowing from the source of the sixth transistor T6 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The eighth transistor T8 may receive at its gate the output signal OUT3 output from the subsequent delay cell, may be coupled at its drain to the source of the sixth transistor T6 and may be coupled to the node, from which the low voltage VL is provided, at its source. The eighth transistor T8 may further change the amount of current flowing from the source of the sixth transistor T6 to the node, from which the low voltage VL is provided, based on the output signal OUT3 output from the subsequent delay cell. The delay line900may solve the problem, as illustrated inFIG.8B, that the first output signal OUT1 and the second output signal OUT2 cannot fully swing. The first feedback current source913and the second feedback current source923may further increase the amounts of current respectively flowing from the first inverter911and the third inverter921to the node, from which the low voltage VL is provided, to further change the pull-down driving force of the first delay cell910and the second delay cell920. As illustrated inFIG.9B, the first feedback current source913and the second feedback current source923may respectively receive the output signals fed-back from the delay cells disposed subsequently thereto and thus may further change the pull-down driving force of the first delay cell910and the second delay cell920. Therefore, the first feedback current source913and the second feedback current source923may allow the first output signal OUT1 and the second output signal OUT2 to fully swing to the level of the low voltage VL. The first feedback current source913and the second feedback current source923may operate after the logic level of the fed-back output signal transitions. Therefore, the first feedback current source913and the second feedback current source923may pull-down the first output signal OUT1 and the second output signal OUT2 to the level of the low voltage VL but the delay amounts of the delay cell910and the second delay cell920might not substantially change. FIGS.10A to10Care diagrams illustrating configurations of delay lines1000A,1000B and1000C in accordance with an embodiment. Each of the delay lines1000A,1000B and1000C may be applied as a part of each of the second delay line221and the delay line410respectively illustrated inFIGS.2and4. Referring toFIG.10A, the delay line1000A may include a first delay cell10A and a second delay cell20A. The first delay cell10A may invert an input signal IN to generate a first output signal OUT1. The first delay cell10A may inversion-drive the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell20A may invert the first output signal OUT1 to generate a second output signal OUT2. The second delay cell20A may inversion-drive the second output signal OUT2 to output a second delayed clock signal DCLK2. Pull-down driving force, with which the first delay cell10A pulls down the first output signal OUT1 according to the input signal IN, may change based on the delay control voltage VC and the second output signal OUT2. Pull-down driving force, with which the second delay cell20A pulls down the second output signal OUT2 according to the first output signal OUT1, may change based on the delay control voltage VC and an output signal OUT3 output from a subsequent delay cell, which is disposed subsequently to the second delay cell20A and configured to receive the second output signal OUT2. The first delay cell10A may include a first inverter11A, a first current source12A and a first feedback current source13A. The first inverter11A may receive the input signal IN and may invert the input signal IN to generate the first output signal OUT1. The first inverter11A may be coupled between a node, from which the high voltage VH is provided, and a node, from which the low voltage VL is provided. The first inverter11A may invert the input signal IN. The first current source12A may be coupled between the first inverter11A and the node, from which the low voltage VL is provided. The first current source12A may receive the delay control voltage VC. The first current source12A may change the pull-down driving force of the first inverter11A based on the delay control voltage VC to change the delay amount of the first delay cell10A. The first feedback current source13A may be coupled between the first inverter11A and the node, from which the low voltage VL is provided. The first feedback current source13A may receive the second output signal OUT2. The first feedback current source13A may further change the pull-down driving force of the first inverter11A based on the second output signal OUT2. In an embodiment, the first feedback current source13A may further receive a first switching signal SW1. The first feedback current source13A may be selectively coupled to the first inverter11A according to the first switching signal SW1. The first delay cell10A may further include a second inverter14A. The second inverter14A may inversion-drive the first output signal OUT1 to output the first delayed clock signal DCLK1. In an embodiment, the first delay cell10A may further include a first auxiliary current source15A. The first auxiliary current source15A may be coupled between the first inverter11A and the node, from which the low voltage VL is provided. The first auxiliary current source15A may receive the delay control voltage VC. The first auxiliary current source15A may further change the pull-down driving force of the first inverter11A based on the delay control voltage VC. In an embodiment, the first auxiliary current source15A may further receive a second switching signal SW2. The first auxiliary current source15A may be selectively coupled to the first inverter11A according to the second switching signal SW2. The second delay cell20A may include a third inverter21A, a second current source22A and a second feedback current source23A. The third inverter21A may receive the first output signal OUT1 and may invert the first output signal OUT1 to generate the second output signal OUT2. The third inverter21A may be coupled between the node, from which the high voltage VH is provided, and the node, from which the low voltage VL is provided. The third inverter21A may invert the first output signal OUT1. The second current source22A may be coupled between the third inverter21A and the node, from which the low voltage VL is provided. The second current source22A may receive the delay control voltage VC. The second current source22A may change the pull-down driving force of the third inverter21A based on the delay control voltage VC to change the delay amount of the second delay cell20A. The second feedback current source23A may be coupled between the third inverter21A and the node, from which the low voltage VL is provided. The second feedback current source23A may receive the output signal OUT3 output from the subsequent delay cell. The second feedback current source23A may further change the pull-down driving force of the third inverter21A based on the output signal OUT3 output from the subsequent delay cell. In an embodiment, the second feedback current source23A may further receive the first switching signal SW1. The second feedback current source23A may be selectively coupled to the third inverter21A according to the first switching signal SW1. The second delay cell20A may further include a fourth inverter24A. The fourth inverter24A may inversion-drive the second output signal OUT2 to output the second delayed clock signal DCLK2. In an embodiment, the second delay cell20A may further include a second auxiliary current source25A. The second auxiliary current source25A may be coupled between the third inverter21A and the node, from which the low voltage VL is provided. The second auxiliary current source25A may receive the delay control voltage VC. The second auxiliary current source25A may further change the pull-down driving force of the third inverter21A based on the delay control voltage VC. In an embodiment, the second auxiliary current source25A may further receive the second switching signal SW2. The second auxiliary current source25A may be selectively coupled to the third inverter21A according to the second switching signal SW2. The first inverter11A may include a first transistor T11 and a second transistor T12. The first transistor T11 may be a P-channel MOS transistor. The second transistor T12 may be a N-channel MOS transistor. The first current source12A may include a third transistor T13. The third transistor T13 may be a N-channel MOS transistor. The first feedback current source13A may include a fourth transistor T14 and a fifth transistor T15. Each of the fourth transistor T14 and the fifth transistor T15 may be a N-channel MOS transistor. The first auxiliary current source15A may include a sixth transistor T16 and a seventh transistor T17. Each of the sixth transistor T16 and the seventh transistor T17 may be a N-channel MOS transistor. The first transistor T11 may receive the input signal IN at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a first output node ON1 at its drain. The first output signal OUT1 may be output through the first output node ON1. The second transistor T12 may receive the input signal IN at its gate and may be coupled to the first output node ON1 at its drain. The third transistor T13 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the second transistor T12 and may be coupled to the node, from which the low voltage VL is provided, at its source. The third transistor T13 may change an amount of current flowing from the source of the second transistor T12 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The fourth transistor T14 may receive the second output signal OUT2 at its gate and may be coupled to the node, from which the low voltage VL is provided, at its source. The fifth transistor T15 may receive the first switching signal SW1 at its gate, may be coupled at its drain to the source of the second transistor T12 and may be coupled at its source to the drain of the fourth transistor T14. The fourth transistor T14 may further change the amount of current flowing from the source of the second transistor T12 to the node, from which the low voltage VL is provided, based on the second output signal OUT2. The fifth transistor T15 may selectively couple the fourth transistor T14 to the source of the second transistor T12 based on the first switching signal SW1. The sixth transistor T16 may receive the delay control voltage VC at its gate and may be coupled to the node, from which the low voltage VL is provided, at its source. The seventh transistor T17 may receive the second switching signal SW2 at its gate, may be coupled at its drain to the source of the second transistor T12 and may be coupled at its source to the drain of the sixth transistor T16. The sixth transistor T16 may further change the amount of current flowing from the source of the second transistor T12 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The seventh transistor T17 may selectively couple the sixth transistor T16 to the source of the second transistor T12 based on the second switching signal SW2. The third inverter21A may include a first transistor T21 and a second transistor T22. The first transistor T21 may be a P-channel MOS transistor. The second transistor T22 may be a N-channel MOS transistor. The second current source22A may include a third transistor T23. The third transistor T23 may be a N-channel MOS transistor. The second feedback current source23A may include a fourth transistor T24 and a fifth transistor T25. Each of the fourth transistor T24 and the fifth transistor T25 may be a N-channel MOS transistor. The second auxiliary current source25A may include a sixth transistor T26 and a seventh transistor T27. Each of the sixth transistor T26 and the seventh transistor T27 may be a N-channel MOS transistor. The first transistor T21 may receive the first output signal OUT1 at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a second output node ON2 at its drain. The second output signal OUT2 may be output through the second output node ON2. The second transistor T22 may receive the first output signal OUT1 at its gate and may be coupled to the second output node ON2 at its drain. The third transistor T23 may receive the delay control voltage VC at its gate, may be coupled at its drain to the source of the second transistor T22 and may be coupled to the node, from which the low voltage VL is provided, at its source. The third transistor T23 may change an amount of current flowing from the source of the second transistor T22 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The fourth transistor T24 may receive at its gate the output signal OUT3 output from the subsequent delay cell and may be coupled to the node, from which the low voltage VL is provided, at its source. The fifth transistor T25 may receive the first switching signal SW1 at its gate, may be coupled at its drain to the source of the second transistor T22 and may be coupled at its source to the drain of the fourth transistor T24. The fourth transistor T24 may further change the amount of current flowing from the source of the second transistor T22 to the node, from which the low voltage VL is provided, based on the output signal OUT3 output from the subsequent delay cell. The fifth transistor T25 may selectively couple the fourth transistor T24 to the source of the second transistor T22 based on the first switching signal SW1. The sixth transistor T26 may receive the delay control voltage VC at its gate and may be coupled to the node, from which the low voltage VL is provided, at its source. The seventh transistor T27 may receive the second switching signal SW2 at its gate, may be coupled at its drain to the source of the second transistor T22 and may be coupled at its source to the drain of the sixth transistor T26. The sixth transistor T26 may further change the amount of current flowing from the source of the second transistor T22 to the node, from which the low voltage VL is provided, based on the delay control voltage VC. The seventh transistor T27 may selectively couple the sixth transistor T26 to the source of the second transistor T22 based on the second switching signal SW2. Referring toFIG.10B, the delay line1000B may include a first delay cell10B and a second delay cell20B. The first delay cell10B may invert an input signal IN to generate a first output signal OUT1. The first delay cell10B may inversion-drive the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell20B may invert the first output signal OUT1 to generate a second output signal OUT2. The second delay cell20B may inversion-drive the second output signal OUT2 to output a second delayed clock signal DCLK2. Pull-up driving force, with which the first delay cell10B pulls up the first output signal OUT1 according to the input signal IN, may change based on the delay control voltage VC and the second output signal OUT2. Pull-up driving force, with which the second delay cell20B pulls up the second output signal OUT2 according to the first output signal OUT1, may change based on the delay control voltage VC and an output signal OUT3 output from a subsequent delay cell, which is disposed subsequently to the second delay cell20B and configured to receive the second output signal OUT2. In an embodiments, a voltage level outputted from the delay cell may be quickly changed and the delay amount of the delay cell may be decreased as the pull-up driving force of the delay cell is increased. The voltage level outputted from the delay cell may be slowly changed and the delay amount of the delay cell may be increased as the pull-up driving force of the delay cell is decreased. The first delay cell10B may include a first inverter11B, a first current source12B and a first feedback current source13B. The first inverter11B may receive the input signal IN and may invert the input signal IN to generate the first output signal OUT1. The first inverter11B may be coupled between a node, from which the high voltage VH is provided, and a node, from which the low voltage VL is provided. The first inverter11B may invert the input signal IN. The first current source12B may be coupled between the first inverter11B and the node, from which the high voltage VH is provided. The first current source12B may receive the delay control voltage VC. The first current source12B may change the pull-up driving force of the first inverter11B based on the delay control voltage VC to change the delay amount of the first delay cell10B. The first feedback current source13B may be coupled between the first inverter11B and the node, from which the high voltage VH is provided. The first feedback current source13B may receive the second output signal OUT2. The first feedback current source13B may further change the pull-up driving force of the first inverter11B based on the second output signal OUT2. In an embodiment, the first feedback current source13B may further receive a first switching signal SW1. The first feedback current source13B may be selectively coupled to the first inverter11B according to the first switching signal SW1. The first delay cell10B may further include a second inverter14B. The second inverter14B may inversion-drive the first output signal OUT1 to output the first delayed clock signal DCLK1. In an embodiment, the first delay cell10B may further include a first auxiliary current source15B. The first auxiliary current source15B may be coupled between the first inverter11B and the node, from which the high voltage VH is provided. The first auxiliary current source15B may receive the delay control voltage VC. The first auxiliary current source15B may further change the pull-up driving force of the first inverter11B based on the delay control voltage VC. In an embodiment, the first auxiliary current source15B may further receive a second switching signal SW2. The first auxiliary current source15B may be selectively coupled to the first inverter11B according to the second switching signal SW2. The second delay cell20B may include a third inverter21B, a second current source22B and a second feedback current source23B. The third inverter21B may receive the first output signal OUT1 and may invert the first output signal OUT1 to generate the second output signal OUT2. The third inverter21B may be coupled between the node, from which the high voltage VH is provided, and the node, from which the low voltage VL is provided. The third inverter21B may invert the first output signal OUT1. The second current source22B may be coupled between the third inverter21B and the node, from which the high voltage VH is provided. The second current source22B may receive the delay control voltage VC. The second current source22B may change the pull-up driving force of the third inverter21B based on the delay control voltage VC to change the delay amount of the second delay cell20B. The second feedback current source23B may be coupled between the third inverter21B and the node, from which the high voltage VH is provided. The second feedback current source23B may receive the output signal OUT3 output from the subsequent delay cell. The second feedback current source23B may further change the pull-up driving force of the third inverter21B based on the output signal OUT3 output from the subsequent delay cell. In an embodiment, the second feedback current source23B may further receive the first switching signal SW1. The second feedback current source23B may be selectively coupled to the third inverter21B according to the first switching signal SW1. The second delay cell20B may further include a fourth inverter24B. The fourth inverter24B may inversion-drive the second output signal OUT2 to output the second delayed clock signal DCLK2. In an embodiment, the second delay cell20B may further include a second auxiliary current source25B. The second auxiliary current source25B may be coupled between the third inverter21B and the node, from which the high voltage VH is provided. The second auxiliary current source25B may receive the delay control voltage VC. The second auxiliary current source25B may further change the pull-up driving force of the third inverter21B based on the delay control voltage VC. In an embodiment, the second auxiliary current source25B may further receive the second switching signal SW2. The second auxiliary current source25B may be selectively coupled to the third inverter21B according to the second switching signal SW2. The first inverter11B may include a first transistor T31 and a second transistor T32. The first transistor T31 may be a P-channel MOS transistor. The second transistor T32 may be a N-channel MOS transistor. The first current source12B may include a third transistor T33. The third transistor T33 may be a P-channel MOS transistor. The first feedback current source13B may include a fourth transistor T34 and a fifth transistor T35. Each of the fourth transistor T34 and the fifth transistor T35 may be a P-channel MOS transistor. The first auxiliary current source15B may include a sixth transistor T36 and a seventh transistor T37. Each of the sixth transistor T36 and the seventh transistor T37 may be a P-channel MOS transistor. The first transistor T31 may receive the input signal IN at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a first output node ON1 at its drain. The first output signal OUT1 may be output through the first output node ON1. The second transistor T32 may receive the input signal IN at its gate and may be coupled to the first output node ON1 at its drain. The third transistor T33 may receive the delay control voltage VC at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled at its drain to the source of the first transistor T31. The third transistor T33 may change an amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T31 based on the delay control voltage VC. The fourth transistor T34 may receive the second output signal OUT2 at its gate and may be coupled to the node, from which the high voltage VH is provided, at its source. The fifth transistor T35 may receive the first switching signal SW1 at its gate, may be coupled at its source to the drain of the fourth transistor T34 and may be coupled at its drain to the source of the first transistor T31. The fourth transistor T34 may further change the amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T31 based on the second output signal OUT2. The fifth transistor T35 may selectively couple the fourth transistor T34 to the source of the first transistor T31 based on the first switching signal SW1. The sixth transistor T36 may receive the delay control voltage VC at its gate and may be coupled to the node, from which the high voltage VH is provided, at its source. The seventh transistor T37 may receive the second switching signal SW2 at its gate, may be coupled at its source to the drain of the sixth transistor T36 and may be coupled at its drain to the source of the first transistor T31. The sixth transistor T36 may further change the amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T31 based on the delay control voltage VC. The seventh transistor T37 may selectively couple the sixth transistor T36 to the source of the first transistor T31 based on the second switching signal SW2. The third inverter21B may include a first transistor T41 and a second transistor T42. The first transistor T41 may be a P-channel MOS transistor. The second transistor T42 may be a N-channel MOS transistor. The second current source22B may include a third transistor T43. The third transistor T43 may be a P-channel MOS transistor. The second feedback current source23B may include a fourth transistor T44 and a fifth transistor T45. Each of the fourth transistor T44 and the fifth transistor T45 may be a P-channel MOS transistor. The second auxiliary current source25B may include a sixth transistor T46 and a seventh transistor T47. Each of the sixth transistor T46 and the seventh transistor T47 may be a P-channel MOS transistor. The first transistor T41 may receive the first output signal OUT1 at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled to a second output node ON2 at its drain. The second output signal OUT2 may be output through the second output node ON2. The second transistor T42 may receive the first output signal OUT1 at its gate and may be coupled to the second output node ON2 at its drain. The third transistor T43 may receive the delay control voltage VC at its gate, may be coupled to the node, from which the high voltage VH is provided, at its source and may be coupled at its drain to the source of the first transistor T41. The third transistor T43 may change an amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T41 based on the delay control voltage VC. The fourth transistor T44 may receive at its gate the output signal OUT3 output from the subsequent delay cell and may be coupled to the node, from which the high voltage VH is provided, at its source. The fifth transistor T45 may receive the first switching signal SW1 at its gate, may be coupled at its source to the drain of the fourth transistor T44 and may be coupled at its drain to the source of the first transistor T41. The fourth transistor T44 may further change the amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T41 based on the second output signal OUT2. The fifth transistor T45 may selectively couple the fourth transistor T44 to the source of the first transistor T41 based on the first switching signal SW1. The sixth transistor T46 may receive the delay control voltage VC at its gate and may be coupled to the node, from which the high voltage VH is provided, at its source. The seventh transistor T47 may receive the second switching signal SW2 at its gate, may be coupled at its source to the drain of the sixth transistor T46 and may be coupled at its drain to the source of the first transistor T41. The sixth transistor T46 may further change the amount of current flowing from the node, from which the high voltage VH is provided, to the source of the first transistor T41 based on the delay control voltage VC. The seventh transistor T47 may selectively couple the sixth transistor T46 to the source of the first transistor T41 based on the second switching signal SW2. Referring toFIG.10C, the delay line1000C may include a first delay cell10C and a second delay cell20C. The first delay cell10C may invert an input signal IN to generate a first output signal OUT1. The first delay cell10C may inversion-drive the first output signal OUT1 to output a first delayed clock signal DCLK1. The second delay cell20C may invert the first output signal OUT1 to generate a second output signal OUT2. The second delay cell20C may inversion-drive the second output signal OUT2 to output a second delayed clock signal DCLK2. Pull-up driving force, with which the first delay cell10C pulls up the first output signal OUT1 according to the input signal IN, may change based on a pull-up delay control voltage VCP and the second output signal OUT2. Pull-down driving force, with which the first delay cell10C pulls down the first output signal OUT1 according to the input signal IN, may change based on a pull-down delay control voltage VCN and the second output signal OUT2. Pull-up driving force, with which the second delay cell20C pulls up the second output signal OUT2 according to the first output signal OUT1, may change based on the pull-up delay control voltage VCP and an output signal OUT3 output from a subsequent delay cell, which is disposed subsequently to the second delay cell20C and configured to receive the second output signal OUT2. Pull-down driving force, with which the second delay cell20C pulls down the second output signal OUT2 according to the first output signal OUT1, may change based on the pull-down delay control voltage VCN and an output signal OUT3 output from the subsequent delay cell. The first delay cell10C may include a first inverter11C, a first current source12C, a second current source13C, a first feedback current source14C and a second feedback current source15C. The first delay cell10C may further include a second inverter16C, a first auxiliary current source17C and a second auxiliary current source18C. The second delay cell20C may include a third inverter22C, a third current source22C, a fourth current source23C, a third feedback current source24C and a fourth feedback current source25C. The second delay cell20C may further include a fourth inverter26C, a third auxiliary current source27C and a fourth auxiliary current source28C. The delay line1000C may be configured by consolidating the configurations of the delay lines1000A and1000B respectively illustrated inFIGS.10A and10B. The first inverter11C may receive the input signal IN and may invert the input signal IN to generate the first output signal OUT1. The first current source12C may be coupled between the first inverter11C and the node, from which the high voltage VH is provided. The first current source12C may receive the pull-up delay control voltage VCP. The first current source12C may change the pull-up driving force of the first inverter11C based on the pull-up delay control voltage VCP to change the delay amount of the first delay cell10C. The second current source13C may be coupled between the first inverter11C and the node, from which the low voltage VL is provided. The second current source13C may receive the pull-down delay control voltage VCN. The second current source13C may change the pull-down driving force of the first inverter11C based on the pull-down delay control voltage VCN to change the delay amount of the first delay cell10C. The first feedback current source14C may be coupled between the first inverter11C and the node, from which the high voltage VH is provided. The first feedback current source14C may receive the second output signal OUT2. The first feedback current source14C may further change the pull-up driving force of the first inverter11C based on the second output signal OUT2. In an embodiment, the first feedback current source14C may further receive a complementary signal SW1B of a first switching signal SW1. The first feedback current source14C may be selectively coupled to the first inverter11C according to the complementary signal SW1B. The second feedback current source15C may receive the second output signal OUT2. The second feedback current source15C may be coupled between the first inverter11C and the node, from which the low voltage VL is provided. The second feedback current source15C may further change the pull-down driving force of the first inverter11C based on the second output signal OUT2. In an embodiment, the second feedback current source15C may further receive the first switching signal SW1. The second feedback current source15C may be selectively coupled to the first inverter11C according to the first switching signal SW1. The second inverter16C may inversion-drive the first output signal OUT1 to output the first delayed clock signal DCLK1. The first auxiliary current source17C may be coupled between the first inverter11C and the node, from which the high voltage VH is provided. The first auxiliary current source17C may receive the pull-up delay control voltage VCP. The first auxiliary current source17C may further change the pull-up driving force of the first inverter11C based on the pull-up delay control voltage VCP. In an embodiment, the first auxiliary current source17C may further receive a complementary signal SW2B of a second switching signal SW2. The first auxiliary current source17C may be selectively coupled to the first inverter11C according to the complementary signal SW2B. The second auxiliary current source18C may be coupled between the first inverter11C and the node, from which the low voltage VL is provided. The second auxiliary current source18C may receive the pull-down delay control voltage VCN. The second auxiliary current source18C may further change the pull-down driving force of the first inverter11C based on the pull-down delay control voltage VCN. In an embodiment, the second auxiliary current source18C may further receive the second switching signal SW2. The second auxiliary current source18C may be selectively coupled to the first inverter11C according to the second switching signal SW2. The third inverter21C may receive the first output signal OUT1 and may invert the first output signal OUT1 to generate the second output signal OUT2. The third current source22C may be coupled between the second inverter21C and the node, from which the high voltage VH is provided. The third current source22C may receive the pull-up delay control voltage VCP. The third current source22C may change the pull-up driving force of the second inverter21C based on the pull-up delay control voltage VCP to change the delay amount of the second delay cell20C. The fourth current source23C may be coupled between the third inverter21C and the node, from which the low voltage VL is provided. The fourth current source23C may receive the pull-down delay control voltage VCN. The fourth current source23C may change the pull-down driving force of the third inverter21C based on the pull-down delay control voltage VCN to change the delay amount of the second delay cell20C. The third feedback current source24C may be coupled between the third inverter21C and the node, from which the high voltage VH is provided. The third feedback current source24C may receive the output signal OUT3 output from the subsequent delay cell. The third feedback current source24C may further change the pull-up driving force of the third inverter21C based on the output signal OUT3 output from the subsequent delay cell. In an embodiment, the third feedback current source24C may further receive the complementary signal SW1B of the first switching signal SW1. The third feedback current source24C may be selectively coupled to the third inverter21C according to the complementary signal SW1B. The fourth feedback current source25C may receive the output signal OUT3 output from the subsequent delay cell. The fourth feedback current source25C may be coupled between the third inverter21C and the node, from which the low voltage VL is provided. The fourth feedback current source25C may further change the pull-down driving force of the third inverter21C based on the output signal OUT3 output from the subsequent delay cell. In an embodiment, the fourth feedback current source25C may further receive the first switching signal SW1. The fourth feedback current source25C may be selectively coupled to the third inverter21C according to the first switching signal SW1. The fourth inverter26C may inversion-drive the second output signal OUT2 to output the second delayed clock signal DCLK2. The third auxiliary current source27C may be coupled between the third inverter21C and the node, from which the high voltage VH is provided. The third auxiliary current source27C may receive the pull-up delay control voltage VCP. The third auxiliary current source27C may further change the pull-up driving force of the third inverter21C based on the pull-up delay control voltage VCP. In an embodiment, the third auxiliary current source27C may further receive the complementary signal SW2B of the second switching signal SW2. The third auxiliary current source27C may be selectively coupled to the third inverter21C according to the complementary signal SW2B. The fourth auxiliary current source28C may be coupled between the third inverter21C and the node, from which the low voltage VL is provided. The fourth auxiliary current source28C may receive the pull-down delay control voltage VCN. The fourth auxiliary current source28C may further change the pull-down driving force of the third inverter21C based on the pull-down delay control voltage VCN. In an embodiment, the fourth auxiliary current source28C may further receive the second switching signal SW2. The fourth auxiliary current source28C may be selectively coupled to the third inverter21C according to the second switching signal SW2. FIG.11is a diagram illustrating a configuration of a semiconductor apparatus1100in accordance with an embodiment. Referring toFIG.11, the semiconductor apparatus1100may receive a clock signal CLK and may perform a delay-locking operation on the clock signal CLK to generate a plurality of internal clock signals. The semiconductor apparatus1100may include a delay locked loop circuit in order to generate the plurality of internal clock signals from the clock signal CLK. The semiconductor apparatus1100may include a clock receiver1110, a division circuit1120, a first delay locked loop1130, a second delay locked loop1140and a clock generation circuit1150. The clock receiver1110may receive the clock signal CLK provided from an external of the semiconductor apparatus1100. The clock receiver1110may buffer the clock signal CLK to output a buffered clock signal CLKR. The division circuit1120may receive the buffered clock signal CLKR and a frequency information signal EN. The frequency information signal EN may have information about whether the semiconductor apparatus1100operates with a relatively high frequency or with a relatively low frequency. For example, when the semiconductor apparatus1100operates with a high frequency, the frequency information signal EN may be enabled. For example, when the semiconductor apparatus1100operates with a low frequency lower than the high frequency, the frequency information signal EN may be disabled. The division circuit1120may receive the buffered clock signal CLKR and may divide the buffered clock signal CLKR to generate a divided clock signal ICLK. The division circuit1120may provide the divided clock signal ICLK as a reference clock signal. The division circuit1120may selectively output the buffered clock signal CLKR based on the frequency information signal EN. For example, the division circuit1120may output, when the frequency information signal EN is disabled, the first delay locked loop1130with the divided clock signal ICLK together with the buffered clock signal CLKR. The first delay locked loop1130may be a digital delay locked loop including at least one digitally controlled delay line. The first delay locked loop1130may receive the reference clock signal, the frequency information signal EN, a first output clock signal ICLKD1 and a second output clock signal ICLKD2. The first delay locked loop1130may perform a delay-locking operation based on the reference clock signal and one signal selected on the basis of the frequency information signal EN between the first output clock signal ICLKD1 and the second output clock signal ICLKD2. The first delay locked loop1130may receive, as the reference clock signal, the divided clock signal ICLK generated from the division circuit1120. The first delay locked loop1130may delay the reference clock signal to generate a first delay locked clock signal CLKDLL1. The first delay locked loop1130may delay the buffered clock signal CLKR to generate a second delay locked clock signal CLKDLL2. When the frequency information signal EN is enabled, the first delay locked loop1130may perform a delay-locking operation based on the first output clock signal ICLKD1 and the divided clock signal ICLK and may delay the divided clock signal ICLK to generate the first delay locked clock signal CLKDLL1. When the frequency information signal EN is disabled, the first delay locked loop1130may perform a delay-locking operation based on the second output clock signal ICLKD2 and the divided clock signal ICLK and may delay the buffered clock signal CLKR to generate the second delay locked clock signal CLKDLL2. The second delay locked loop1140may be an analog delay locked loop including a voltage-controlled delay line. The second delay locked loop1140may receive the first delay locked clock signal CLKDLL1 to generate the first output clock signal ICLKD1. The second delay locked loop1140may perform a delay-locking operation on the first delay locked clock signal CLKDLL1 based on the first delay locked clock signal CLKDLL1 and the first output clock signal ICLKD1 to generate the first output clock signal ICLKD1. The second delay locked loop1140may delay the first delay locked clock signal CLKDLL1 to generate a first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1. One among the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 may be provided as the first output clock signal ICLKD1. The clock generation circuit1150may receive the second delay locked clock signal CLKDLL2. The clock generation circuit1150may generate the second output clock signal ICLKD2 based on the second delay locked clock signal CLKDLL2. The clock generation circuit1150may generate, from the second delay locked clock signal CLKDLL2, a second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. One among the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 may be provided as the second output clock signal ICLKD2. The clock generation circuit1150may further receive the frequency information signal EN. Based on the frequency information signal EN, the clock generation circuit1150may output, as a plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD, one between the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 and the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. When the frequency information signal EN is enabled, the clock generation circuit1150may output the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. When the frequency information signal EN is disabled, the clock generation circuit1150may output the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. When the semiconductor apparatus1100operates with a high frequency, the frequency information signal EN may be enabled and a delay-locking operation may be performed through the first delay locked loop1130and the second delay locked loop1140. The division circuit1120may divide the buffered clock signal CLKR to output the divided clock signal ICLK as the reference clock signal. The first delay locked loop1130may perform a delay-locking operation based on the divided clock signal ICLK and the first output clock signal ICLKD1 to generate the first delay locked clock signal CLKDLL1. When the delay-locking operation of the first delay locked loop1130is completed, the second delay locked loop1140may perform a delay-locking operation on the first delay locked clock signal CLKDLL1 provided from the first delay locked loop1130. The second delay locked loop1140may perform a delay-locking operation on the first delay locked clock signal CLKDLL1 to generate the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1. The clock generation circuit1150may output, as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD, the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1, which are output from the second delay locked loop1140. When the semiconductor apparatus1100operates with a low frequency, the frequency information signal EN may be disabled and a delay-locking operation may be performed through the first delay locked loop1130. The division circuit1120may output the divided clock signal ICLK as the reference clock signal and may output the buffered clock signal CLKR together with the divided clock signal ICLK. The first delay locked loop1130may perform a delay-locking operation based on the divided clock signal ICLK and the second output clock signal ICLKD2 and may delay the buffered clock signal CLKR to generate the second delay locked clock signal CLKDLL2. When the delay-locking operation of the first delay locked loop1130is completed, the clock generation circuit1150may receive the second delay locked clock signal CLKDLL2 from the first delay locked loop1130. The clock generation circuit1150may generate the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 based on the second delay locked clock signal CLKDLL2. The clock generation circuit1150may output the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. The division circuit1120may include a clock divider1121and a gating circuit1122. The clock divider1121may receive the buffered clock signal CLKR and may divide the buffered clock signal CLKR. For example, the clock divider1121may divide the buffered clock signal CLKR by two to generate four divided clock signals. The clock divider1121may output, as the reference clock signal, one among the four divided clock signals. For example, the clock divider1121may output, as the reference clock signal, one divided clock signal ICLK, which has a phase corresponding to a phase of the buffered clock signal CLKR among the four divided clock signals. The gating circuit1122may selectively output the buffered clock signal CLKR based on the frequency information signal EN. The gating circuit1122may receive the buffered clock signal CLKR and a complementary signal ENB of the frequency information signal EN. The gating circuit1122may gate the buffered clock signal CLKR by the complementary signal ENB of the frequency information signal EN. The gating circuit1122may include an AND gate. When the frequency information signal EN is disabled or the complementary signal ENB of the frequency information signal EN is enabled, the gating circuit1122may output the buffered clock signal CLKR to the first delay locked loop1130. The first delay locked loop1130may include a high-frequency delay line1131, a low-frequency delay line1132, a replica1133, a first phase detector1134and a delay controller1135. Each of the high-frequency delay line1131and the low-frequency delay line1132may be a digitally controlled delay line. The high-frequency delay line1131may receive the divided clock signal ICLK, a delay control signal DC and the frequency information signal EN. When the frequency information signal EN is enabled, the high-frequency delay line1131may delay the divided clock signal ICLK based on the delay control signal DC to generate the first delay locked clock signal CLKDLL1. When the frequency information signal EN is disabled, the high-frequency delay line1131may be deactivated. The low-frequency delay line1132may receive the buffered clock signal CLKR and the delay control signal DC. The low-frequency delay line1132may delay the buffered clock signal CLKR based on the delay control signal DC to generate the second delay locked clock signal CLKDLL2. The high-frequency delay line1131may be a high-frequency digitally controlled delay line. The low-frequency delay line1132may be a low-frequency digitally controlled delay line. The replica1133may receive one between the first output clock signal ICLKD1 and the second output clock signal ICLKD2. When the frequency information signal EN is enabled, the replica1133may receive the first output clock signal ICLKD1 and may delay the first output clock signal ICLKD1 by an amount of modelled delay time to generate a first feedback clock signal FBCLK1. When the frequency information signal EN is disabled, the replica1133may receive the second output clock signal ICLKD2 and may delay the second output clock signal ICLKD2 by an amount of the modelled delay time to generate the first feedback clock signal FBCLK1. In an embodiment, the replica1133may be modified to receive one among the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD, which are output from the clock generation circuit1150, regardless of the frequency information signal EN. For example, the replica1133may be modified to receive the internal clock signal ICLKD, which has a phase corresponding to the first output clock signal ICLKD1 and the second output clock signal ICLKD2 among the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. The first phase detector1134may compare the phases between the divided clock signal ICLK, which is provided as the reference clock signal, and the first feedback clock signal FBCLK1 to generate the first phase detection signal PD1. The delay controller1135may generate the delay control signal DC based on the first phase detection signal PD1. The delay controller1135may increase or decrease the value of the delay control signal DC according to the logic level of the first phase detection signal PD1. The delay control signal DC may be provided commonly to the high-frequency delay line1131and the low-frequency delay line1132. The delay amounts of the high-frequency delay line1131and the low-frequency delay line1132may be set on the basis of the delay control signal DC. The first delay locked loop1130may further include a clock selector1136. The clock selector1136may receive the first output clock signal ICLKD1, the second output clock signal ICLKD2 and the frequency information signal EN. The clock selector1136may receive, based on the frequency information signal EN, one between the first output clock signal ICLKD1 and the second output clock signal ICLKD2. The clock selector1136may be coupled to the replica1133. The clock signal output from the clock selector1136may be input to the replica1133. When the frequency information signal EN is enabled, the clock selector1136may output the first output clock signal ICLKD1 to the replica1133. When the frequency information signal EN is disabled, the clock selector1136may output the second output clock signal ICLKD2 to the replica1133. The second delay locked loop1140may include a voltage-controlled delay line1141, a calibration circuit1142, a second phase detector1143and a charge pump1144. The voltage-controlled delay line1141may receive the first delay locked clock signal CLKDLL1 and a delay control voltage VC. The voltage-controlled delay line1141may delay the first delay locked clock signal CLKDLL1 based on the delay control voltage VC to generate the first output clock signal ICLKD1 and a second feedback clock signal FBCLK2. The voltage-controlled delay line1141may delay the first delay locked clock signal CLKDLL1 to generate the first set of plural output clock signals QCLKD1, IBCLKD1 and QBCLKD1 other than the first output clock signal ICLKD1. The calibration circuit1142may receive the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2. The calibration circuit1142may detect the phases of the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2. The calibration circuit1142may delay the first output clock signal ICLKD1 to generate a delayed reference clock signal REFD. The calibration circuit1142may delay the second feedback clock signal FBCLK2 to generate a delayed feedback clock signal FEBD. The calibration circuit1142may compensate for a phase error between the first output clock signal ICLKD1 and the second feedback clock signal FBCLK2, which may occur due to the configurations of the second delay locked loop1140. Accordingly, the second delay locked loop1140to perform a precise delay-locking operation. The calibration circuit420illustrated inFIG.4may be applied as the calibration circuit1142. The second phase detector1143may receive the delayed reference clock signal REFD and the delayed feedback clock signal FEBD. The second phase detector1143may detect the phases of the delayed reference clock signal REFD and the delayed feedback clock signal FEBD to generate a second phase detection signal PD2. The second phase detection signal PD2 may include an up signal UP and a down signal DN. The charge pump1144may receive the second phase detection signal PD2. The charge pump1144may generate the delay control voltage VC based on the second phase detection signal PD2. The charge pump1144may raise the voltage level of the delay control voltage VC based on the up signal UP and may lower the voltage level of the delay control voltage VC based on the down signal DN. The clock generation circuit1150may include a multi-phase clock generator1151and a clock selector1152. The multi-phase clock generator1151may receive the second delay locked clock signal CLKDLL2. The multi-phase clock generator1151may generate the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 from the second delay locked clock signal CLKDLL2. The multi-phase clock generator1151may divide the phase of the second delay locked clock signal CLKDLL2 and divide the frequency of the second delay locked clock signal CLKDLL2 to generate the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 having predetermined phase difference therebetween. Although not illustrated, the multi-phase clock generator1151may include configurations such as a phase splitter, a divider and so forth. The clock selector1152may receive the frequency information signal EN, the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 and the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. Based on the frequency information signal EN, the clock selector1152may output, as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD, one between the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 and the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. When the frequency information signal EN is enabled, the clock selector1152may output the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. When the frequency information signal EN is disabled, the clock selector1152may output the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 as the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. The semiconductor apparatus1100may include a command receiver1210, a command decoder1220, a command delay line1230, a clock generation replica1240, a delay cell replica1250, a command selector1260and a synchronization circuit1270. The command receiver1210may receive a command signal CMD provided from an external of the semiconductor apparatus1100. The command signal CMD may be a control signal for controlling the semiconductor apparatus1100to perform various operations. The command signal CMD may include a plurality of signals of different kinds. The command decoder1220may decode the command signal CMD, which is provided through the command receiver1210, to generate an internal command signal ICMD. The command decoder1220may generate the internal command signal ICMD of various kinds based on the command signal CMD. For example, the internal command signal ICMD may include but might not be limited to an active command signal, a precharge command signal, a read command signal, a write command signal, an on-die termination command signal, a refresh command signal and so forth. The command decoder1220may latch the command signal CMD, which is provided through the command receiver1210, based on the buffered clock signal CLKR. The command decoder1220may decode the latched command signal to generate the internal command signal ICMD. The command delay line1230may receive the internal command signal ICMD and the delay control signal DC. The command delay line1230may delay the internal command signal ICMD based on the delay control signal DC to generate a delayed command signal DCMD. The delay amount of the command delay line1230may be set on the basis of the delay control signal DC. The command delay line1230may have substantially the same configuration as the high-frequency delay line1131and/or the low-frequency delay line1132. Since the command delay line1230, the frequency delay line1131and the low-frequency delay line1132commonly receive the delay control signal DC, the delay amount of the command delay line1230may set to be substantially the same as the delay amount of the high-frequency delay line1131and/or the delay amount of the low-frequency delay line1132. The internal command signal ICMD may be delayed through the command delay line1230by an time as much as the divided clock signal ICLK or the buffered clock signal CLKR is delayed through the high-frequency delay line1131or the low-frequency delay line1132. The clock generation replica1240may delay the delayed command signal DCMD to generate an additionally delayed command signal. The clock generation replica1240may be a circuit, to which the clock generation circuit1150is modelled. The clock generation replica1240may further delay the delayed command signal DCMD by a time that is taken for the clock generation circuit1150to generate the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. The clock generation circuit1150may generate the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 from the second delay locked clock signal CLKDLL2 that is delayed through the low-frequency delay line1132. Therefore, the clock generation replica1240may delay the delayed command signal DCMD by an time that is taken for the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2 to be generated from the second delay locked clock signal CLKDLL2 thereby matching timing of the command signal output from the clock generation replica1240to the phases of the second set of plural output clock signals ICLKD2, QCLKD2, IBCLKD2 and QBCLKD2. The delay cell replica1250may be a circuit, to which at least one among a plurality of delay cells configuring the voltage-controlled delay line1141is modelled. A number of delay cells included in the delay cell replica1250may correspond to a number of delay cells utilized to generate the first output clock signal ICLKD1 from the first delay locked clock signal CLKDLL1. For example, when the first delay locked clock signal CLKDLL1 is delayed through one delay cell to be generated as the first output clock signal ICLKD1 within the voltage-controlled delay line1141, the delay cell replica1250may be configured to include one delay cell. The delay cell replica1250may receive the delayed command signal DCMD and the delay control signal DC and may delay the delayed command signal DCMD based on the delay control voltage VC to generate the additionally delayed command signal. The first delay locked clock signal CLKDLL1 delayed through the high-frequency delay line1131may be further delayed through the voltage-controlled delay line1141of the second delay locked loop1140. The delay cell replica1250may delay the delayed command signal DCMD by an time that is taken for the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1 to be generated from the first delay locked clock signal CLKDLL1 thereby matching timing of the command signal output from the delay cell replica1250to the phases of the first set of plural output clock signals ICLKD1, QCLKD1, IBCLKD1 and QBCLKD1. The command selector1260may receive the output signal from the clock generation replica1240, the output signal from the delay cell replica1250and the frequency information signal EN. Based on the frequency information signal EN, the command selector1260may output, as an asynchronized command signal ASCMD, one between the output signal from the clock generation replica1240and the output signal from the delay cell replica1250. When the frequency information signal EN is enabled, the command selector1260may output the output signal from the delay cell replica1250as the asynchronized command signal ASCMD. When the frequency information signal EN is disabled, the command selector1260may output the output signal from the clock generation replica1240as the asynchronized command signal ASCMD. The synchronization circuit1270may receive the asynchronized command signal ASCMD and one among the plurality of internal clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. For example, the synchronization circuit1270may receive the internal clock signal ICLKD. The synchronization circuit1270may change the domain of the asynchronized command signal ASCMD. The synchronization circuit1270may synchronize the asynchronized command signal ASCMD to the internal clock signal ICLKD to output a synchronized command signal SCMD. The synchronization circuit1270may transform the asynchronized command signal ASCMD into the synchronized command signal SCMD, which is synchronized with the internal clock signal ICLKD. Internal circuits of the semiconductor apparatus1100may utilize the synchronized command signal SCMD. In an embodiment, the synchronization circuit1270may be modified to generate the synchronized command signal SCMD, which is synchronized with the internal clock signal QCLKD. FIG.12is a diagram illustrating a configuration of an analogue delay locked loop circuit1300in accordance with an embodiment. The analogue delay locked loop circuit1300may be applied as the second delay locked loop122illustrated inFIG.1and may replace the second delay locked loop220illustrated inFIG.2. The analogue delay locked loop circuit1300may receive a reference clock signal REFCLK and may perform a delay-lock operation on the reference clock signal REFCLK to generate a plurality of internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. When the analogue delay locked loop circuit1300replaces the second delay locked loop220illustrated inFIG.2, the reference clock signal REFCLK may correspond to the delay locked clock signal CLKDLL. The analogue delay locked loop circuit1300may detect the frequency of the reference clock signal REFCLK to prevent uneven deterioration from occurring in the elements of the analogue delay locked loop circuit1300. When the frequency of the reference clock signal REFCLK provided to the analogue delay locked loop circuit1300goes beyond the operation frequency of the analogue delay locked loop circuit1300, there may occur asymmetrical deterioration in the analogue delay locked loop circuit1300. The asymmetrical deterioration may cause the static phase error of the analogue delay locked loop circuit1300. For example, while the analogue delay locked loop circuit1300may perform a normal delay-lock operation on the reference clock signal REFCLK having a higher frequency than a reference frequency, the analogue delay locked loop circuit1300may tend to be asymmetrically deteriorated when receiving the reference clock signal REFCLK having a lower frequency than the reference frequency. The reference frequency may be defined as a minimum frequency, at which the analogue delay locked loop circuit1300may perform a normal delay-lock operation. The analogue delay locked loop circuit1300may detect the frequency of the reference clock signal REFCLK. When the frequency of the reference clock signal REFCLK becomes lower than the reference frequency, the analogue delay locked loop circuit1300may control at least part of the elements of the analogue delay locked loop circuit1300by the reference clock signal REFCLK thereby preventing the asymmetrical deterioration from occurring in the elements within the analogue delay locked loop circuit1300. The analogue delay locked loop circuit1300may include a frequency detector1310, a delay line1320, a phase detector1330, a selection controller1340, and a charge pump1350. The frequency detector1310may receive the reference clock signal REFCLK and may detect the frequency of the reference clock signal REFCLK. The frequency detector1310may generate a frequency detection signal FD by detecting the frequency of the reference clock signal REFCLK. The frequency detector1310may enable the frequency detection signal FD when the frequency of the reference clock signal REFCLK is lower than the reference frequency and may disable the frequency detection signal FD when the frequency of the reference clock signal REFCLK is higher than the reference frequency. The reference frequency may be arbitrarily determined. The reference frequency may be low enough to cause the uneven deterioration in the frequency detector1310. The delay line1320may receive the reference clock signal REFCLK and a delay control voltage VC. Based on the delay control voltage VC, the delay line1320may delay the reference clock signal REFCLK to generate the plurality of delayed clock signals ICLKD, QCLKD, IBCLKD and QBCLKD. The delay line1320may be a voltage controlled delay line. A delay amount of the delay line1320may be set based on the delay control voltage VC that is an analogue voltage signal. The delay line1320may gradually delay the reference clock signal REFCLK by the delay amount, which is set based on the delay control voltage VC, to generate the plurality of delayed clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. The delay line1320may output four signals among a plurality of delayed clock signals as first to fourth internal clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD and may output another one signal among the plurality of delayed clock signals as a feedback clock signal FBCLK. The delay line1320may include a plurality of delay cells.FIG.12exemplifies the delay line1320having nine number of delay cells DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8, and DC9, which will not limit the present disclosure. The delay line1320may include less or more than nine number of delay cells. The delay line1320may output, as the first internal clock signal ICLKD, the delayed clock signal from the first delay cell DC1. The first internal clock signal ICLKD may be provided as an internal reference clock signal. The delay line1320may output, as the second internal clock signal QCLKD, the delayed clock signal from the third delay cell DC3. The delay line1320may output, as the third internal clock signal IBCLKD, the delayed clock signal from the fifth delay cell DC5. The delay line1320may output, as the fourth internal clock signal QBCLKD, the delayed clock signal from the seventh delay cell DC7. The delay line1320may output, as the feedback clock signal FBCLK, the delayed clock signal from the last delay cell DC9. The phase detector1330may receive the internal reference clock signal ICLKD and the feedback clock signal FBCLK. The phase detector1330may generate a phase detection signal based on phases of the feedback clock signal FBCLK and the first internal clock signal ICLKD provided as the internal reference clock signal. For example, the phase detection signal may include a first detection signal UPP and a second detection signal DNP. The phase detector1330may enable the first detection signal UPP based on the phase of the first internal clock signal ICLKD and may enable the second detection signal DNP based on the phase of the feedback clock signal FBCLK. The phase detector1330may enable the first detection signal UPP when the phase of the first internal clock signal ICLKD transitions from a low logic level to a high logic level. The phase detector1330may enable the second detection signal DNP when the phase of the feedback clock signal FBCLK transitions from a low logic level to a high logic level. The phase detector1330may reset the first detection signal UPP and the second detection signal DNP after a lapse of a predetermined amount of time. The phase detector1330may disable both the first detection signal UPP and the second detection signal DNP after the predetermined amount of time lapses from when any signal, which is enabled later between the first detection signal UPP and the second detection signal DNP, becomes enabled. The predetermined amount of time may be shorter than an amount of time corresponding to a half period of the reference clock signal REFCLK and/or the feedback clock signal FBCLK. The selection controller1340may receive the reference clock signal REFCLK, the first detection signal UPP, the second detection signal DNP and the frequency detection signal FD to generate an up-signal UP and a down-signal DN. Based on the frequency detection signal FD, the selection controller1340may selectively provide the reference clock signal REFCLK, the first detection signal UPP and the second detection signal DNP, as the up-signal UP and the down-signal DN. When the frequency detection signal FD stays disabled, the selection controller1340may provide the first detection signal UPP and the second detection signal DNP respectively as the up-signal UP and the down-signal DN. The selection controller1340may provide the first detection signal UPP as the up-signal UP and may provide the second detection signal DNP as the down-signal DN. When the frequency detection signal FD becomes enabled, the selection controller1340may provide the reference clock signal REFCLK as both the up-signal UP and the down-signal DN. The charge pump1350may receive the up-signal UP and the down-signal DN. The charge pump1350may generate the delay control voltage VC based on the up-signal UP and the down-signal DN. The charge pump1350may raise the voltage level of the delay control voltage VC based on the up-signal UP and may lower the voltage level of the delay control voltage VC based on the down-signal DN. For example, when the voltage level of the delay control voltage VC rises, the delay time of the delay cells DC1 to DC9 configuring the delay line1320may decrease. When the voltage level of the delay control voltage VC falls, the delay time of the delay cells DC1 to DC9 configuring the delay line1320may increase. The analogue delay locked loop circuit1300may perform the delay-lock operation by changing the voltage level of the delay control voltage VC until the internal reference signal ICLKD is in phase with the feedback clock signal FBCLK. When the internal reference signal ICLKD is in phase with the feedback clock signal FBCLK, the analogue delay locked loop circuit1300may fix the voltage level of the delay control voltage VC and may be locked. The charge pump1350may further receive the frequency detection signal FD. The charge pump1350may control the delay control voltage VC to have a logic level based on the frequency detection signal FD. When the frequency detection signal FD becomes enabled, the charge pump1350may raise or lower the voltage level of the delay control voltage VC in order for the delay cells DC1 to DC9 of the delay line1320to be turned on. For example, the charge pump1350may raise, based on the frequency detection signal FD, the voltage level of the delay control voltage VC to an enough level for the delay control voltage VC to be determined to have a high logic level. Alternatively, the charge pump1350may lower, based on the frequency detection signal FD, the voltage level of the delay control voltage VC to an enough level for the delay control voltage VC to be determined to have a low logic level. FIG.13is a diagram illustrating a configuration of the frequency detector1310illustrated inFIG.12. Referring toFIG.13, the frequency detector1310may include a pulse generator1311, a first transistor1312, a second transistor1313, a third transistor1314and an inverter1315. The pulse generator1311may receive the reference clock signal REFCLK and may generate a detection pulse signal DP based on the reference clock signal REFCLK. The pulse generator1311may include a delay unit1311-1and a NAND gate1311-2. The delay unit1311-1may include an odd number of inverters. The NAND gate1311-2may perform a NAND operation on the reference clock signal REFCLK and an output of the delay unit1311-1to generate the detection pulse signal DP. In synchronization with a rising edge of the reference clock signal REFCLK, the pulse generator1311may generate the detection pulse signal DP having a pulse width corresponding to the delay time of the delay unit1311-1and transitioning to a low logic level. The pulse generator1311may generate the detection pulse signal DP having a greater number of pulses as the frequency of the reference clock signal REFCLK becomes higher and may generate the detection pulse signal DP having a smaller number of pulses as the frequency of the reference clock signal REFCLK becomes lower. Each of the first to third transistors1312,1313and1314may be a P-channel MOS transistor. The first transistor1312may receive a power voltage VDD at its source and may receive a ground voltage VSS at its gate. The second transistor1313may receive the ground voltage VSS at its gate and drain. The third transistor1314may be coupled, at its source, to a drain of the first transistor1312. The third transistor1314may be coupled, at its drain, to a source of the second transistor1313. The third transistor1314may receive the detection pulse signal DP at its gate. Because the first transistor1312and the second transistor1313receive the ground voltage VSS at their respective gates, the first transistor1312and the second transistor1313may be always turned on. The first transistor1312may transfer the power voltage VDD to the source of the third transistor1314and the second transistor1313may transfer the ground voltage VSS to the drain of the third transistor1314. Whenever the detection pulse signal DP transitions to a low logic level, the third transistor1314may drive a detection node ND to the voltage level of the power voltage VDD. The inverter1315may invert the voltage level of the detection node ND to generate the frequency detection signal FD. When the voltage level of the detection node ND is a low logic level, the frequency detection signal FD may be enabled to a high logic level. When the voltage level of the detection node ND is a high logic level, the frequency detection signal FD may be disabled to a low logic level. The frequency detector1310may further include a capacitor1316. The capacitor1316may be coupled to the detection node ND at one end and may be coupled to the ground voltage VSS at the other end. The capacitor1316may stabilize the voltage level of the detection node ND. As the frequency of the reference clock signal REFCLK becomes higher, the detection pulse signal DP may frequently transition to a low logic level. The third transistor1314may be frequently turned on according to the detection pulse signal DP and the voltage level of the detection node ND may rise to the voltage level of the power voltage VDD. Therefore, the detection node ND may have the voltage level corresponding to a high logic level and the frequency detection signal FD may be disabled to a low logic level. As the frequency of the reference clock signal REFCLK becomes lower, the detection pulse signal DP may rarely transition to a low logic level. The third transistor1314may also be rarely turned on according to the detection pulse signal DP and the voltage level of the detection node ND may fail to rise to the voltage level corresponding to a high logic level. Therefore, the frequency detection signal FD may be enabled to a high logic level. FIG.14is a diagram illustrating a configuration of the selection controller1340illustrated inFIG.12. Referring toFIG.14, the selection controller1340may include a first multiplexer1341and a second multiplexer1342. The first multiplexer1341may receive the first detection signal UPP, the reference clock signal REFCLK and the frequency detection signal FD to output the up-signal UP. Based on the frequency detection signal FD, the first multiplexer1341may output, as the up-signal UP, one of the first detection signal UPP and the reference clock signal REFCLK. When the frequency detection signal FD stays disabled to a low logic level, the first multiplexer1341may output the first detection signal UPP as the up-signal UP. When the frequency detection signal FD becomes enabled to a high logic level, the first multiplexer1341may output the reference clock signal REFCLK as the up-signal UP. The second multiplexer1342may receive the second detection signal DNP, the reference clock signal REFCLK and the frequency detection signal FD to output the down-signal DN. Based on the frequency detection signal FD, the second multiplexer1342may output, as the down-signal DN, one of the second detection signal DNP and the reference clock signal REFCLK. When the frequency detection signal FD stays disabled to a low logic level, the second multiplexer1342may output the second detection signal DNP as the down-signal DN. When the frequency detection signal FD becomes enabled to a high logic level, the second multiplexer1342may output the reference clock signal REFCLK as the down-signal DN. FIGS.15A and15Bare diagrams illustrating configurations1500A and1500B of the charge pump1350in accordance with an embodiment. Any of the configurations1500A and1500B of the charge pump1350may be applied as the charge pump1350illustrated inFIG.12. Referring toFIG.15A, the charge pump1500A may include a pull-up circuit1510, a pull-down circuit1520, and a turn-on control circuit1530A. The pull-up circuit1510may receive the up-signal UP and may pull-up drive an output node ONA based on the up-signal UP. The delay control voltage VC may output through the output node ONA. When the up-signal UP is enabled, the pull-up circuit1510may provide the output node ONA with an up-current IUP to raise the voltage level of the output node ONA. The pull-down circuit1520may receive the down-signal DN and may pull-down drive the output node ONA based on the down-signal DN. When the down-signal DN is enabled, the pull-down circuit1520may couple the output node ONA with a down current IDN to discharge the output node ONA which in turn may lower the voltage level of the output node ONA. The turn-on control circuit1530A may receive the frequency detection signal FD and may pull-up drive the output node ONA based on the frequency detection signal FD. When the frequency detection signal FD is enabled, the turn-on control circuit1530A may provide the output node ONA with an additional up-current IUPA to raise, together with the pull-up circuit1510, the voltage level of the output node ONA. An amount of the up-current IUP may be substantially the same as an amount of the down-current IDN. An amount of the additional up-current IUPA may be less than the amount of the up-current IUP or the amount of the down-current IDN. The pull-up circuit1510may include an up-current source1511and a first switch1512. The up-current source1511may be coupled to the power voltage VDD at one end. The up-current source1511may provide, through the first switch1512, the output node ONA with the up-current IUP. The first switch1512may receive the up-signal UP, may be coupled at one end to the other end of the up-current source1511and may be coupled at the other end to the output node ONA. When the up-signal UP is enabled, the first switch1512may be turned on and may provide the output node ONA with the up-current IUP. The pull-down circuit1520may include a down-current source1521and a second switch1522. The down-current source1521may be coupled to the ground voltage VSS at one end. The down-current source1521may discharge, through the second switch1522, the down-current IDN from the output node ONA to the ground voltage VSS. The second switch1522may receive the down-signal DN, may be coupled at one end to the other end of the down-current IDN and may be coupled at the other end to the output node ONA. When the down-signal DN is enabled, the second switch1522may be turned on and may discharge the down-current IDN from the output node ONA. The turn-on control circuit1530A may include an additional up-current source1531A and a third switch1532A. The additional up-current source1531A may be coupled to the power voltage VDD at one end. The additional up-current source1531A may provide, through the third switch1532A, the output node ONA with the additional up-current IUPA. The third switch1532A may receive the frequency detection signal FD, may be coupled at one end to the other end of the additional up-current source1531A and may be coupled at the other end to the output node ONA. When the frequency detection signal FD is enabled, the third switch1532A may be turned on and may provide the output node ONA with the additional up-current IUPA. The charge pump1500A may further include a capacitor1540A. The capacitor1540A may stabilize the voltage levels of the output node ONA and the delay control voltage VC. The capacitor1540A may be coupled to the output node ONA at one end and may be coupled to the ground voltage VSS at the other end. When the frequency detection signal FD becomes disabled, the charge pump1500A may receive the first detection signal UPP as the up-signal UP and may receive the second detection signal DNP as the down-signal DN, from the selection controller1340illustrated inFIG.12. The pull-up circuit1510and the pull-down circuit1520may be turned on respectively according to the first detection signal UPP and the second detection signal DNP. The voltage level of the delay control voltage VC may change according to the turn-on of the pull-up circuit1510and the turn-on of the pull-down circuit1520. When the frequency detection signal FD becomes enabled, the charge pump1500A may receive the reference clock signal REFCLK, as the up-signal UP and the down-signal DN, from the selection controller1340. Therefore, the pull-up circuit1510and the pull-down circuit1520may be turned on at the same time and may maintain turned on during the same amount of time and thus the deterioration may evenly occur in the pull-up circuit1510and the pull-down circuit1520. The voltage level of the delay control voltage VC may be maintained to a specific level as the pull-up circuit1510and the pull-down circuit1520are evenly turned on. For example, the voltage level of the delay control voltage VC may be maintained, by the pull-up circuit1510and the pull-down circuit1520, to a voltage level corresponding to a half of the power voltage VDD. The turn-on control circuit1530A may pull-up drive the output node ONA based on the frequency detection signal FD. Therefore, the voltage level of the delay control voltage VC may gradually rise to the voltage level of the power voltage VDD. By the turn-on control circuit1530A, the voltage level of the delay control voltage VC may rise to a level corresponding to a high logic level. When the delay cells DC1 to DC9 of the delay line1320have the structure that the delay cells DC1 to DC9 are turned on by the delay control voltage VC having a high logic level as illustrated inFIGS.8A,9A, and10A, the turn-on control circuit1530A may raise the voltage level of the delay control voltage VC to a level corresponding to a high logic level such that all of the delay cells DC1 to DC9 are turned on. Therefore, the turn-on control circuit1530A may control deterioration to evenly occur in the delay cells DC1 to DC9. Referring toFIG.15B, the charge pump1500B may include a pull-up circuit1510, a pull-down circuit1520, and a turn-on control circuit1530B. The pull-up circuit1510and the pull-down circuit1520illustrated inFIG.15Bmay have the same configuration and may perform the same function as the pull-up circuit1510and the pull-down circuit1520illustrated inFIG.15A, respectively. The turn-on control circuit1530B may include an additional down-current source1531B and a third switch1532B. The additional down-current source1531B may be coupled to the ground voltage VSS at one end. The additional down-current source1531B may discharge, through the third switch1532B, an additional down-current IDNA from an output node ONB to the ground voltage VSS. The third switch1532B may receive the frequency detection signal FD, may be coupled at one end to the other end of the additional down-current source1531B and may be coupled at the other end to the output node ONB. When the frequency detection signal FD is enabled, the third switch1532B may be turned on and may discharge the additional down-current IDNA from the output node ONB. An amount of the additional down-current IDNA may be less than the amount of the up-current IUP or the amount of the down-current IDN. When the frequency detection signal FD becomes enabled, the turn-on control circuit1530B may pull-down drive the output node ONB based on the frequency detection signal FD. Therefore, the voltage level of the delay control voltage VC may gradually fall to the voltage level of the ground voltage VSS. By the turn-on control circuit1530B, the delay control voltage VC may fall to a voltage level corresponding to a low logic level. When the delay cells DC1 to DC9 of the delay line1320have the structure that the delay cells DC1 to DC9 are turned on by the delay control voltage VC having a low logic level as illustrated inFIG.10B, the turn-on control circuit1530B may lower the voltage level of the delay control voltage VC to a level corresponding to a low logic level such that all of the delay cells DC1 to DC9 are turned on. Therefore, the turn-on control circuit1530B may control deterioration to evenly occur in the delay cells DC1 to DC9. Hereinafter, described with reference toFIGS.12to15Bwill be the operation of the analogue delay locked loop circuit1300in accordance with an embodiment. When a semiconductor apparatus including the analogue delay locked loop circuit1300operates in a normal mode, the reference clock signal REFCLK may have a higher frequency than the reference frequency and the frequency detector1310may keep the frequency detection signal FD disabled. The normal mode may be an operational mode, in which the semiconductor apparatus can be powered up to perform a normal operation. Based on the disabled frequency detection signal FD, the analogue delay locked loop circuit1300may perform a general delay-lock operation. Based on the disabled frequency detection signal FD, the selection controller1340may provide the first detection signal UPP as the up-signal UP and may provide the second detection signal DNP as the down-signal DN. The phase detector1330may compare the phases of the first internal clock signal ICLKD and the feedback clock signal FBCLK to generate the first detection signal UPP and the second detection signal DNP. Therefore, the charge pump1350may adjust the voltage level of the delay control voltage VC based on the up-signal UP and the down-signal DN, which are respectively generated according to the first detection signal UPP and the second detection signal DNP. When the first internal clock signal ICLKD is in phase with the feedback clock signal FBCLK, the voltage level of the delay control voltage VC may be kept constant and the delay-lock operation of the analogue delay locked loop circuit1300may be completed. When the semiconductor apparatus including the analogue delay locked loop circuit1300operates in a mode other than the normal mode, the reference clock signal REFCLK may have the reference frequency or lower and the frequency detector1310may enable the frequency detection signal FD. For example, the mode other than the normal mode may include any of a power-down mode, a stand-by mode, a low-power mode and a test mode of the semiconductor apparatus. Based on the enabled frequency detection signal FD, the selection controller1340may provide the reference clock signal REFCLK as the up-signal UP and the down-signal DN. Therefore, the pull-up circuit1510and the pull-down circuit1520of each of the charge pump1500A and the charge pump1500B may be turned on at the same time and may stay turned on for the same amount of time. Accordingly, there may occur even and symmetrical deterioration in the pull-up circuit1510and the pull-down circuit1520. The turn-on control circuits1530A and1530B of the charge pump1500A may change the delay control voltage VC to a high logic level and a low logic level, respectively. Therefore, the delay cells DC1 to DC9 configuring the delay line1320may be continuously turned on, which may minimize a phase skew or a phase error due to the uneven deterioration that occurs in the analogue delay locked loop circuit1300in the mode other than the normal mode of the semiconductor apparatus. FIG.16is a diagram illustrating a configuration of an analogue delay locked loop circuit1600in accordance with an embodiment. Referring toFIG.16, the analogue delay locked loop circuit1600may have a similar configuration as the analogue delay locked loop circuit1300illustrated inFIG.12. InFIGS.12and16, the same element is indicated by the same reference number. The description on the same element will not be repeated here. The analogue delay locked loop circuit1600may include the delay line1320, a selection controller1640, a phase detector1630and a charge pump1650. The selection controller1340may be coupled to the output node of the phase detector1330within the analogue delay locked loop circuit1300illustrated inFIG.12but the selection controller1640may be coupled to an input node of the phase detector1630within the analogue delay locked loop circuit1600illustrated inFIG.16. The selection controller1640may receive the internal reference clock signal (i.e., the first internal clock signal ICLKD), the feedback clock signal FBCLK, the reference clock signal REFCLK and a deterioration enable signal DEN to output a first selection clock signal REFS and a second selection clock signal FEBS. The deterioration enable signal DEN may be enabled when there is a possibility of the asymmetrical deterioration in the analogue delay locked loop circuit1600. In an embodiment, the deterioration enable signal DEN may be a frequency detection signal generated by detecting the frequency of the reference clock signal REFCLK. When the deterioration enable signal DEN is the frequency detection signal, the analogue delay locked loop circuit1600may further include the frequency detector1310. In an embodiment, the deterioration enable signal DEN may be a control signal provided from an external to the analogue delay locked loop circuit1600. A semiconductor apparatus including the analogue delay locked loop circuit1600may provide the analogue delay locked loop circuit1600with the deterioration enable signal DEN, which is enabled, under a situation that there may occur the asymmetrical deterioration within the analogue delay locked loop circuit1600. For example, the deterioration enable signal DEN may be a DLL disable signal for deactivating the analogue delay locked loop circuit1600. Based on the deterioration enable signal DEN, the selection controller1640may output the internal reference clock signal (i.e., the first internal clock signal ICLKD) and the feedback clock signal FBCLK respectively as the first selection clock signal REFS and the second selection clock signal FEBS or may output the reference clock signal REFCLK as the first selection clock signal REFS and the second selection clock signal FEBS. Based on the deterioration enable signal DEN, which is disabled, the selection controller1640may output the internal reference clock signal (i.e., the first internal clock signal ICLKD) as the first selection clock signal REFS and may output the feedback clock signal FBCLK as the second selection clock signal FEBS. Based on the deterioration enable signal DEN, which is enabled, the selection controller1640may output the reference clock signal REFCLK as the first selection clock signal REFS and the second selection clock signal FEBS. The selection controller1640may have substantially the same configuration as the selection controller1340illustrated inFIG.14except for the received signals and the output signals thereof. The phase detector1630may receive the first selection clock signal REFS and the second selection clock signal FEBS from the selection controller1640and may compare the phases of the first selection clock signal REFS and the second selection clock signal FEBS to generate the up-signal UP and the down-signal DN. When the deterioration enable signal DEN becomes disabled, the phase detector1630may receive the internal reference clock signal and the feedback clock signal FBCLK respectively as the first selection clock signal REFS and the second selection clock signal FEBS and therefore may generate the up-signal UP and the down-signal DN according to the phase difference between the internal reference clock signal and the feedback clock signal FBCLK for the analogue delay locked loop circuit1600to perform a general delay-lock operation. When the deterioration enable signal becomes enabled, the phase detector1630may receive the reference clock signal REFCLK as the first selection clock signal REFS and the second selection clock signal FEBS and therefore may generate the up-signal UP and the down-signal DN at the same time and for the same amount of time, which controls even deterioration to occur in the charge pump1650and the delay line1320configuring the analogue delay locked loop circuit1600. The charge pump1650may have substantially the same configuration and may operate substantially in the same manner as the charge pump1350illustrated inFIG.12except the receiving of the deterioration enable signal DEN instead of the frequency detection signal FD. In an embodiment, the analogue delay locked loop circuit1300illustrated inFIG.12may be modified to utilize the deterioration enable signal DEN instead of the frequency detection signal FD. The selection controller1340and the charge pump1350of the analogue delay locked loop circuit1300may be modified to receive the deterioration enable signal DEN, instead of the frequency detection signal FD, to operate based on the deterioration enable signal DEN, which is similar to the selection controller1640and the charge pump1650of the analogue delay locked loop circuit1600. The frequency detector1310of the analogue delay locked loop circuit1300may be modified to generate the deterioration enable signal DEN instead of the frequency detection signal FD. When the deterioration enable signal DEN is a control signal provided from an external to the analogue delay locked loop circuit1300, the analogue delay locked loop circuit1300might not include the frequency detector1310. While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the delay line, delay locked loop circuit and semiconductor apparatus using the same should not be limited based on the described embodiments. Rather, the delay line, delay locked loop circuit and semiconductor apparatus using the same described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings. | 162,385 |
11942956 | DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTs Hereinafter, example embodiments of the present disclosure will be described with reference to the attached drawings. The components described in the present disclosure (e.g., units, circuits, dividers, converters, oscillators, detectors, etc.) may be implemented with hardware, but the present disclosure is not limited thereto. The components may be implemented with software or a combination of hardware and software. For example, the circuit may be implemented as a digital circuit as well as an analog circuit. FIG.1is a block diagram illustrating a digital phase-locked loop according to some example embodiments. Referring toFIG.1, a digital phase-locked loop1includes a time-to-digital converter20, an oscillator DCO, and a divider40. The time-digital converter20may receive a phase-locked loop input clock CKREF and a feedback clock CKFB and detect a phase difference between the phase-locked loop input clock CKREF and the feedback clock CKFB. A loop filter30may receive a loop filter input signal LF_IN generated based on the phase difference detected by the time-digital converter20and generate an output signal LF_OUT to be applied to the oscillator DCO. The loop filter input signal LF_IN input to the loop filter30and the output signal LF_OUT output by the loop filter30may be digital codes (e.g., digital codes formed of multi bits). The output signal output signal LF_OUT may be a digital code generated based on the phase difference detected by the time-digital converter20. The oscillator DCO may receive the output signal LF_OUT and generate the oscillation clock CKDCO. The oscillator DCO may be implemented, for example, as a digitally controlled oscillator DCO. The divider40may receive the oscillation clock CKDCO and generate the feedback clock CKFB obtained by dividing a frequency of the oscillation clock CKDCO by an integer or a fraction. FIG.2is a block diagram illustrating a time-to-digital converter according to some example embodiments.FIG.3is a timing view explaining an operation of the time-to-digital converter according to some example embodiments.FIG.4is a graph explaining nonlinearity generated in the time-to-digital converter. Referring toFIG.2, the time-to-digital converter20includes a phase frequency detector (PFD)200, a ring oscillator201, a counter array203, a multiplexer (MUX)204, an analog-to-digital converter (ADC)205, a calibrator210, and an adder207. The phase frequency detector200receives the phase-locked loop input clock CKREF and the feedback clock CKFB. The phase frequency detector200may generate a ring oscillator enable signal EN_RO that enables the ring oscillator201. The ring oscillator201includes a plurality of inverters202ato202nconnected in series. Although not illustrated, the time-to-digital converter (20) according to some example embodiments may further include, for example, an XOR gate configured to generate pulses with a duration indicative of the phase difference by receiving two signals (e.g., an UP signal and a DOWN signal) generated by detecting the phase difference between the phase-locked loop input clock CKREF and the feedback clock CKFB generated by the phase frequency detector200, and a flip-flop configured to detect a polarity of the phase difference between the phase-locked loop input clock CKREF and the feedback clock CKFB generated by the phase frequency detector200, based on a relative time of a rising or falling edge. Outputs of each of the plurality of inverters202ato202nin the ring oscillator201may be connected to the counter array203and the multiplexer204. The ring oscillator201may perform oscillation with multiple phases. Alternatively, the ring oscillator201may perform oscillation with multi-phase clocks. The counter array203may generate the number of oscillations N_CNT by counting the number of times that the ring oscillator201oscillates in a certain period, as the number of positive integers, during a pulse width at which the ring oscillator201is turned on. In addition, the counter array203may generate a plurality of zones N_ZONE by dividing one count or one cycle of the number of oscillations N_CNT that occur as the number of positive integers into a plurality of zones using multi-phase information (or voltage information of multi-phase clocks). This will be described with reference toFIG.3. Referring toFIGS.2and3, a first pulse width in which the phase difference occurs between the phase-locked loop input clock CKREF and the feedback clock CKFB may be formed from 0 to P1. The ring oscillator enable signal EN_RO that turns on the ring oscillator201during the first pulse width may be generated. That is, the ring oscillator201may be turned on during the first pulse width to perform oscillation. In this case, the ring oscillator201may perform oscillation in a first period PRO. The counter array203may count the number of times that the ring oscillator201oscillates during the first pulse width. The counter array203connected to the outputs of each of the plurality of inverters202ato202nincluded in the ring oscillator201may generate the number of oscillations N_CNT of a positive integer in which the number of oscillations is counted in the first period P_RO during the first pulse width. In addition, the counter array203may generate the plurality of zones N_ZONE by dividing one count (e.g., when N_CNT=0) or one cycle (e.g., during a P_RO period of N_CNT=0) of the number of oscillations N_CNT that occurs as the number of positive integers into the plurality of zones, using multi-phase information, through which counting may be performed. For example, when the ring oscillator201performs three or more and less than four oscillations in the first period P_RO during the first pulse width, the counter array203may output the number of oscillations N_CNT counted from 0 to 3. In addition, the number of oscillations for the plurality of zones N_ZONE that are further subdivided during the first period P_RO period may be output by counting the number of oscillations at all the rising edges of the multi-phase clocks. In other words, the number of oscillations N_CNT to digital output values counted in an integer cycle and the number of oscillations for the plurality of zones N_ZONE may be generated by the counter array203. The ring oscillator201may perform an oscillation operation with multiple phases. It will be described with reference toFIG.4together. Referring toFIGS.2to4, the ring oscillator201may perform oscillation with, for example, 13 phases in the first period PR_RO. In this case, while the ring oscillator201oscillates during the first pulse width, an oscillation width between two different neighboring phases may not be constant. In other words, a multi-phase mismatch may occur. For this reason, a time-digital converter output (TDC output) value for a time-digital converter input (TDC input) (e.g., the phase difference between the phase-locked loop input clock CKREF and the feedback clock CKFB may have nonlinear characteristics. For example, within a first ring oscillation period 1 RO period, an ideal interval between multiple phases may be an ideal zone interval from a first time t1 to a second time t2. However, an actual zone interval may be from a first′ time t1′ to a second′ time t2′ due to the multi-phase mismatch described above. For this reason, a time-digital converter output (TDC output) graph for the time-digital converter input (TDC input) does not have an ideal value such as a dotted line, and may have nonlinear characteristics such as a solid line. In other words, the plurality of zones that are intervals between the multiple phases may be formed during the first ring oscillation period 1 RO period. For example, a digital code indicative of one zone N_ZONE among the plurality of zones may be output by the counter array203connected to the outputs of each of the plurality of inverters202ato202nof the ring oscillator201. In addition, the output of each of the plurality of inverters202ato202nmay be connected to the multiplexer204to select voltage information of a plurality of neighboring phase signals included in the one zone N_ZONE of the plurality of zones and transmit the selected voltage information to an analog-digital converter205. Through the multiplexer204, the one zone N_ZONE selected from the plurality of zones may be, for example, a zone from the first′ time t1′ to the second′ time t2′ inFIG.4. In addition, referring toFIGS.2to4, in order to improve the resolution of the time-to-digital converter20according to some example embodiments, the analog-to-digital converter205may be connected to the multiplexer204. That is, the analog-to-digital converter205may generate time-to-digital converter output information on the time-to-digital converter input (TDC input) in the one zone N_ZONE among the plurality of zones received through the multiplexer204. For example, the analog-to-digital converter205may receive the voltage information of two phase signals corresponding to the zone N_ZONE from the first′ time t1′ to the second′ time t2′ from the multiplexer204. The analog-to-digital converter205may be used, for example, for an analog-to-digital converter205-based time-to-digital converter20. For example, the analog-to-digital converter205may use a flash analog-to-digital converter. In this case, the flash analog-to-digital converter may achieve a high conversion speed, but may require numerous comparators that increase the power consumption of the time-to-digital converter. As another example, the analog-to-digital converter205may be a pipeline analog-to-digital converter. The pipeline analog-to-digital converter may require several operational amplifiers that significantly increase the power consumption of the time-to-digital converter. As another example, the analog-to-digital converter205may be a successive approach register (SAR) analog-to-digital converter. The SAR analog-to-digital converter may consume less power. However, the SAR analog-to-digital converter may be restricted by a setting time, which is the time required to charge a capacitive digital-to-analog converter. To improve the setting time, a top-plate sampling may be used. This is because when the top plate sampling is used, the number of unit capacitors of the capacitive digital-to-analog converter may be reduced by half compared to a case of using a bottom-plate sampling. Meanwhile, the top-plate sampling can increase the effect of parasitic capacitance, which can cause the SAR analog-to-digital converter to undergo clipping due to gain and full-scale errors. In addition, when using the top plate sampling, a common mode of the capacitive digital-to-analog converter may be determined by a common mode of an input signal to the analog-to-digital converter. When changing the common mode of the input signal, the speed of a comparator may also be changed to affect a conversion time of the SAR analog-to-digital converter. The change in a process, voltage, and temperature (PVT) may exacerbate problems related to clipping and the conversion time of the analog-to-digital converter. In other words, even though the analog-to-digital converter205is used to improve the resolution of the time-to-digital converter20according to some example embodiments, the nonlinear characteristics may occur in the output of the time-to-digital converter20due to the clipping of the analog-to-digital converter205. Accordingly, the time-to-digital converter20according to some example embodiments includes a calibrator210to remove the nonlinear characteristics that may occur in the output of the time-to-digital converter20. The calibrator210may receive the loop filter input signal LF_IN generated by the time-digital converter20as feedback, receive an analog-digital conversion output ADC_OUT from the analog-digital converter205, and generate a calibrated analog-digital conversion output ADC_OUT_CAL by calibrating the nonlinear characteristics included in the analog-digital conversion output ADC_OUT. The time-to-digital converter20according to some example embodiments may generate the loop filter input signal LF_IN by adding the calibrated analog-to-digital conversion output ADC_OUT_CAL and the plurality of zones N_ZONE generated based on the multi-phase information and the number of oscillations N_CNT counted through the counter array203by the adder207. In other words, the time-digital converter20according to some example embodiments may receive feedback for the loop filter input signal LF_IN and generate the calibrated analog-to-digital conversion output ADC_OUT_CAL by calibrating the nonlinear characteristics included in the analog-to-digital conversion output ADC_OUT, thus removing the nonlinear characteristics included in the loop filter input signal LF_IN generated by the time-to-digital converter20via continuous feedback. Hereinafter, a structure and an operation of removing the nonlinear characteristics included in the loop filter input signal LF_IN, which is an output of the time-digital converter20according to some example embodiments, via the calibrator210, will be described in detail with reference toFIGS.5to12. FIG.5is a block diagram illustrating the calibrator according to some example embodiments. Referring again toFIGS.2and5, the calibrator210includes a zone identifier212, an offset lookup table generation circuit220, a gain-corrected analog-to-digital conversion output generator (or gain-corrected analog-to-digital conversion output circuit)230, and an adder214. The zone identifier212may receive information on the analog-to-digital conversion output ADC_OUT received from the analog-to-digital converter205and the one zone N_ZONE among the plurality of zones received from the counter array203and generate a signal for selecting one zone from the plurality of zones. In addition, a sub-zone selection signal for selecting one sub-zone from sub-zones in which one zone is divided into a plurality of zones may also be generated. The sub-zone may be a unit obtained by dividing one zone described inFIG.4into the plurality of sub-zone. In the following descriptions, it is explained that zones are divided into13zones and sub-zones are divided into four zones for each zone. However, this is an example, and the zones can be divided into any natural numbers, and the sub-zones may also be divided into any natural numbers for each zone. The offset lookup table generation circuit220may generate an offset value applied to each zone based on a zone selection signal and/or a sub-zone selection signal received from the zone identifier212. For example, for a first zone that is one of the plurality of zones, an operation of the offset lookup table generation circuit220for the plurality of sub-zones (first sub-zone to fourth sub-zone) that are present in the first zone will be described as an example. The offset lookup table generation circuit220includes a de-multiplexer221, a plurality of offset lookup table calculators222_1to222_13, a first multiplexer223, and a second multiplexer224. The offset lookup table generation circuit220first receives the loop filter input signal LF_IN via the de-multiplexer221. In this case, the de-multiplexer221may receive the zone selection signal and the sub-zone selection signal from the zone identifier212and transmit information included in the loop filter input signal LF_IN to each of the lookup table offset calculators222_1to222_13. In this case, each of the plurality of offset lookup table calculators222_1to222_13calculates offset errors for each of the plurality of zones during the first pulse width at which the ring oscillator201oscillates, and stores the offset errors as lookup tables. For example, a first offset lookup table calculator222_1may store the offset error generated in the first zone as a lookup table, and the 13thzone offset lookup table calculator222_13may store the offset error generated in the 13thzone as a lookup table. The offset error may be a difference value between an ideal time-digital converter output and the time-digital converter output with the nonlinear characteristics, described with reference toFIG.4. For example, the offset error may be a value obtained by subtracting the average in each zone of the time-to-digital converter output with the nonlinear characteristics from the average in each zone of the ideal time-to-digital converter output. Each of the plurality of offset lookup table calculators222_1to222_13may be configured as illustrated inFIG.6. Even thoughFIG.6describes the first offset lookup table calculator222_1as an example, a description thereof may be applied to a description of the remaining offset lookup table calculators222_2to222_13. FIG.6is a block diagram illustrating an offset lookup table calculator according to some example embodiments. Referring toFIGS.5and6, the first offset lookup table calculator222_1may include a plurality of aggregators2220_1to2220_4. Each of the plurality of aggregators2220_1to2220_4may calculate offset errors for each of the sub-zones included in the first zone. In other words, each of the plurality of aggregators2220_1to2220_4may calculate the offset errors for each of the first to fourth sub-zone. Thereafter, the offset errors calculated via each of the plurality of aggregators2220_1to2220_4may be stored in offset lookup tables (Offset1[0] to Offset1[3]), respectively. For example, it may be stored in a register included in the first offset lookup table calculator222_1. In other words, each of the offset lookup tables (Offset1[0] to Offset1[3]) may be a value in which the offset errors for the first to fourth sub-zones for the first zone are stored as the lookup tables. Referring back toFIGS.2and5, the first multiplexer223receives the zone selection signal from the zone identifier212, select one of the 1stto 13thzones, and transmits lookup table values for the corresponding zones to the second multiplexer224. For example, when an Nth zone selection signal is received from the zone identifier212, the first multiplexer223may transmit offset lookup tables (OffsetN[0] to OffsetN[3]) calculated and stored for the plurality of sub-zones for an Nth zone to the second multiplexer224. The second multiplexer224may select one of the lookup tables (OffsetN[0] to OffsetN[3]) based on the sub-zone selection signal received from the zone identifier212and transmit the selected lookup table as an offset lookup table error value to the adder214. The gain-corrected analog-to-digital conversion output generator230may generate a gain-corrected analog-to-digital conversion output ADC_OUT_MULT that offsets a difference between the first gain having the ideal time-to-digital converter output and the second gain having the time-to-digital converter output with the nonlinear characteristics. For example, the gain-corrected analog-to-digital conversion output generator (or gain-corrected analog-to-digital conversion output generator circuit)230includes an adder231, a de-multiplexer232, a plurality of gain calibration factor calculators (or gain calibration factor calculator circuits)233_1to233_13, a multiplexer234, and a multiplier235. The gain-corrected analog-to-digital conversion output generator230may receive two offset lookup tables for each zone and obtain a difference between the two offset lookup tables. For example, the gain-corrected analog-to-digital conversion output generator230may receive the offset lookup table OffsetN[0] of the first sub-zone for the Nth zone and the offset lookup table OffsetN[3] of the fourth sub-zone for the Nth zone and transmit the same to an Nth gain calibration factor calculator via the de-multiplexer232. In other words, since N is a natural number between 1 and 13, offset lookup table values may be received for the two sub-zones for each of a total of 13 zones, and a difference value between the offset lookup table values may be transmitted to each of the gain calibration factor calculators233_1to233_13via the de-multiplexer232. In this case, the de-multiplexer232may transmit the differences between the offset lookup table values to the gain calibration factor calculators233_1to233_13based on the zone selection signal received by the zone identifier212. The two offset lookup tables in which the gain-corrected analog-to-digital conversion output generator230obtains the differences through the adder231are not limited to the first and fourth sub-zones of each of the zones. In addition, the number of offset lookup tables received by the gain-corrected analog-to-digital conversion output generator230through the adder231is not limited to two. As described inFIG.4, the sub-zones are sufficient that can obtain the difference between the first gain having the ideal time-digital converter output and the second gain having the time-digital converter output with the nonlinear characteristics. Each of the plurality of gain correction coefficient calculators233_1to233_13may be adders. In other words, each of the plurality of gain calibration factor calculators233_1to233_13may calculate the difference between the first gain having the ideal time-digital converter output and the second gain having the time-digital converter output with the nonlinear characteristics, through the adder, as described inFIG.4, and generate a gain calibration factor (GCF) for each of the plurality of zones. Thereafter, the multiplexer234may output the gain correction coefficient GCF for one zone, using the zone selection signal received by the zone identifier212, and transmit the same to the multiplier235. The multiplier235that has received the analog-to-digital conversion output ADC_OUT transmits the gain-corrected analog-to-digital conversion output ADC_OUT_MULT, which is an output for applying the gain calibration factor to each of the zones, to the adder214. The adder214may generate and output a calibrated analog-to-digital conversion output ADC_OUT_MULT by applying the gain-corrected analog-to-digital conversion output (ADC_OUT_CAL) and an output to which the offset lookup table (OffsetN[M]) is applied. Hereinafter, an operation of the time-to-digital converter according to some example embodiments will be described together with graphs. FIG.7is an example graph explaining an output for an input of a time-to-digital converter in the first zone.FIG.8is an example graph explaining a difference between an ideal output and a nonlinear output for an input of the time-digital converter in the first zone.FIG.9is an example graph explaining a calibrated result using the gain calibration factor for the nonlinear output via the time-to-digital converter according to some example embodiments.FIG.10is an example graph explaining the difference between the ideal output and the nonlinear output after calibration using the gain calibration factor for the nonlinear output via the time-digital converter according to some example embodiments. Referring toFIGS.4,5,7, and8, as the output for the time-digital converter input, the time-digital converter output may have the time-digital converter output with the nonlinear characteristics different from the ideal time-digital converter output. In other words, a time-digital converter error obtained by subtracting a time-digital converter output value with the nonlinear characteristics from the ideal time-digital converter output may occur as illustrated inFIG.8. In this case, the gain calibration factors may be calculated for each of the plurality of zones through the gain-corrected analog-to-digital conversion output generator230, and the time-to-digital converter output with the nonlinear characteristics may be multiplied by the analog-to-digital conversion output and the gain calibration factor. Accordingly, a gain of the time-to-digital converter output with the nonlinear characteristics may be made equal to that of the ideal time-to-digital converter output, as illustrated inFIG.9. Therefore, as illustrated inFIG.10, the same time-to-digital converter error value may occur for each of the plurality of sub-zones. FIG.11is an example graph explaining a calibrated result using an offset lookup table for a nonlinear output via a time-digital converter according to some example embodiments, andFIG.12is an example graph explaining a difference between an ideal output and a nonlinear output after calibration using an offset lookup table for the nonlinear output via the time-digital converter according to some example embodiments. In addition, referring toFIGS.5and11, through the offset lookup table generation circuit220, the offset lookup table error values in which the offset errors for each of the sub-zone in the plurality of zones are obtained and stored may be added through the adder214, and accordingly, the ideal time-digital converter output and the time-digital converter output with the nonlinear characteristics may have the same value as illustrated inFIG.11. In other words, as illustrated inFIG.12, the time-digital converter error between the time-digital converter output with the nonlinear characteristics and the ideal time-digital converter output may be eliminated to remove nonlinearity that occurs in the loop filter input signal LF_IN generated by the time-digital converter20. Although the example embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the disclosed example embodiments, but may be implemented in various different ways, and the present disclosure may be embodied in many different forms without changing technical subject matters and essential features as will be understood by those skilled in the art. Therefore, example embodiments set forth herein are exemplary only and not to be construed as a limitation. | 25,953 |
11942957 | DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE DISCLOSURE Overview The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started. The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described herein are set forth below and the accompanying drawings. Time-Interleaved ADCs There are many flavors of ADCs, each aiming to output a digital representation of the analog input provided to the ADC. An example flavor of ADCs is the time-interleaved ADC, where an ADC has K multiple subADCs (of any suitable architecture), which can run at a sample rate of 1/K of the overall system sample rate. Many (low-speed) ADCs can be used in parallel, operating in sequence in a time-interleaved fashion, using appropriate clocking, to increase the effective combined ADC sampling rate.FIG.1shows an example time-interleaved ADC having two subADCs, andFIG.2shows a timing diagram illustrating sampling edges for the example time-interleaved ADC ofFIG.1. In particular,FIG.1shows an example of a time-interleaved ADC having two subADCs, ADC_0and ADC_1, each able to produce Y million samples per second (MS/s). The subADCs can produce N-bit samples. Together, with appropriate clocking shown inFIG.2, the two subADCs can provide an overall sampling rate up to 2×Y MS/s. The appropriate clocking can be provided by clock generator (“clock gen” block) to produce clock signals or selection signals, q0and q1, having different phases, to alternately select a subADC for converting the analog input signal to a digital output. Referring back toFIG.1, the two subADCs, ADC_0and ADC_1, alternately (i.e., in sequential order or according to a fixed sequence) sample the input signal Vinand produce corresponding digital outputs, Dout0and Dout1respectively, which are then combined by the digital combiner (“dig combiner” block) to produce the Y MS/s digital output Dout. In this example, the subADCs operate according to a fixed sequence of [ . . . ADC_0, ADC_1, ADC_0, ADC_1, ADC_0, ADC_1, . . . ], e.g., in a round-robin fashion. A time-interleaved ADC having two subADC is described herein as an example for understanding the operations of a time-interleaved ADC, and is not intended to be limiting to the disclosure. Other time-interleaved ADCs having more than two subADCs are envisioned by the disclosure. Furthermore, time-interleaved ADCs having three or more subADCs can operate in a fixed sequence, a randomized sequence, or a pseudo-randomized sequence. Two or more ADCs can sample, interleaved in time according to a randomized sequence or a pseudo-randomized sequence, the analog input. In such an example, the ADCs can be built fast enough that having as little as two ADCs can sample the analog input in a randomized sequence. In some embodiments, three or more ADCs can sample, interleaved in time according to a randomized sequence or pseudo-randomized sequence. In such an example, one or more of the three or more ADCs may be “busy”, while two or more ones of the three or more ADCs may be “idle” (waiting to be selected/used). When the next sample is to be made, one of the “idle” ADCs can be selected at random from the ones which are “idle” to take the next sample in the pseudo-randomized sequence. Another flavor of ADCs are multi-stage ADCs comprising multiple stages of analog-to-digital conversion, or multiple ADCs in cascade. Each stage generally includes an ADC. Stages can use the same or different ADC architectures to resolve different parts of digital output code. Typically, a first analog-to-digital conversion stage resolves the most significant bit(s) based on the analog input and generates an output for the second (following the first) analog-to-digital conversion stage. The output can be a residue representing the difference between the analog input and the digital output generated by a particular stage (i.e., the value of the most significant bit(s) resolved by the first stage). The second analog-to-digital conversion stage then performs analog-to-digital conversion on the residue signal to resolve further bit(s) of the digital output. The second stage can generate a further residue signal for following stage(s) of the multi-stage ADC. In some cases, a successive approximation register ADC can be considered a multi-stage ADC (e.g., if a segmented design is implemented to resolve the most significant bits using a simple ADC and further bits are resolved by a successive-approximation-register (SAR) charge distribution architecture). Residue type ADCs including two-step ADCs, algorithmic ADCs, and pipeline ADCs are also considered as multi-stage ADCs. While the algorithmic ADCs can reuse a single stage, each phase the single ADC is being reused can be considered a stage in the multi-stage ADC. Another form of multi-stage ADCs is a multi-stage noise shaping sigma-delta (MASH) ADC, comprising multiple stages of delta-sigma ADCs or a combination of other type(s) of ADCs (e.g., flash ADC) and delta-sigma ADC(s). The above-described ADC architectures are not intended to be limiting to the disclosure. As will be appreciated by one skilled in the art, other architectures may be realized by the present disclosure. Interleaved Gain Error FIG.3shows another illustrative embodiment of a time-Interleaved ADC. Analog-to-digital conversion is the process of translating analog signals to digital values. An example is the conversion of human voice to digital values for storage and/or processing. Time-Interleaved means that there are two (or more) ADCs (each one called subADC or slice) sampling one at a time. In the example ofFIG.3, there are two subADCs shown. Each subADC samples 1/Fsseconds after the previous subADC. Fsis the sampling rate of the overall ADC, i.e., the number of conversions that happen every second. t represents time. Ts=1/Fsis the sampling period. n is an index to differentiate each sample. FIG.4is an illustrative block diagram of an ADC producing a gain error according to an embodiment of the present disclosure. The subADCs may be different instances of what is designed to be identical circuits within a chip. However, although designed to be identical, in practice some instances may differ from others, in different ways within the same chip, and from chip to chip, due to one or more process, voltage, and/or temperature (PVT) variations. One critical difference that may arise between different instances of subADCs is that of gain (i.e., the gains of different subADC may be different despite the fact that these subADCs may be designed to have the same gain). This may result in errors in conversion relative to each other. With reference toFIG.4, for example, if an input voltage of 1 volt is provided to the interleaved ADC, one subADC may output “1.1” while the other may output “0.9”. The gain error shows up at the output of the interleaved ADC as an oscillatory error, e.g., {1.1, 0.9, 1.1, 0.9, . . . }, as shown in the example ofFIG.4. Such oscillatory error may show up as spurs or tones in the output spectrum of the time-interleaved ADC. The difference in gain between subADCs can be referred to as interleaved gain error. Example of Correcting a Gain Error FIG.5is an illustrative block diagram of an ADC correcting a gain error according to an embodiment of the present disclosure. With reference to the illustrative embodiment ofFIG.5, the gain error of one subADC may be estimated with respect to the other, and its gain may be adjusted (also called corrected or calibrated), as to reduce or minimize the interleaved gain error. For instance, circuitry and/or digital output of subADC1may be adjusted until its output matches the output of subADC0. In the example ofFIG.5, output subADC1is adjusted by a factor α=1.1/0.9=1.222 (approximately). The output of the overall ADC is 1.1, which has a small error, however, the interleaved error is reduced or gone, i.e., the output of the ADC ofFIG.5is not oscillating as inFIG.4, but is now a constant value {1.1, 1.1, 1.1, 1.1, . . . }, while a substantially constant voltage, e.g., 1 volt, is provided at its input. Example of Gain Estimates FIG.6is an illustrative block diagram of an ADC with gain estimates according to an embodiment of the present disclosure. Gain estimation is shown in the illustrative embodiment ofFIG.6. Different subADC gains may result in different output powers per subADC. This may be used to sense which subADC has higher or lower gain. For example, the power of the signal coming out of each subADC may be estimated, and the difference of these power estimate may indicate which subADC has the largest gain. In this example, “power” means summing the square (X[m]2) of the M subADC samples. M is the number of samples used for the power estimation. In some examples, M is a number of samples in a data block, or the data block size. In some embodiments, M is in the order of tens of thousands. The “mean”, “offset,” or “average” of a given subADC (labeled as μ0and μ1inFIG.6) is subtracted from each subADC sample prior the squaring operation. The “mean” (or equivalents) can be computed by averaging the M subADC samples. Thus, the variance of the output of each subADC may be estimated. Phrased differently, each sample with the mean value removed is squared, and the squared value is summed over M samples. In mathematical terms, the power is Σm=0M−1(X[m]−μ)2. InFIG.6, m is used as an index, wherein m may go from 0 to M−1 in steps of 1. Each m may be a different n for each subADC. Herein, n is an index for the overall interleaved-ADC. Herein, m is an index per subADC. In the example ofFIG.6, n=2m for subADC0(because subADC0has even n), while n=2m+1 for subADC1(because subADC1has odd n). Example of Thresholding to Determine if the Signal is Valid: Amplitude Evaluation and Power Evaluation In the example ofFIG.6, each of the X0[m] and X1[m] values may be compared to a “Maximum Amplitude Threshold,” and if any exceeds this threshold, no calibration is performed, and the value may be discarded or a new subADC data capture is started, e.g., as shown inFIG.11. For example, if X0[m]>(Max Amplitude) or if X0[m]<−(Max Amplitude), the signal may be too large and the value may be discarded from calibration. In some embodiments, the sample may be evaluated to determine if the sample is within a specific range of values (defined by a lower bound and an upper bound indicating a valid amplitude). If the sample is not within the range of values, then the sample fails to meet a valid amplitude condition. In some embodiments, each of the X0[m] and X1[m] values may be compared to a “Minimum Amplitude Threshold,” and if any is below this threshold, no calibration is performed, and the value may be discarded or a new subADC data capture is started. For example, if X0[m]<(Min Amplitude) or if X0[m]>−(Min Amplitude), the signal may be too small or non-existent and the value may be discarded from calibration. In the example ofFIG.6, the power estimates A0and A1may be used to detect other invalid conditions, e.g., power is too low or power is too high, in which calibration may be unwanted and/or a new subADC data capture may be started. For example, if either A0or A1is below a “Minimum Power Threshold,” it may be decided not to calibrate. In some cases, if A0or A1is above a “Maximum Power Threshold,” it may be decided not to calibrate. In some embodiments, the power estimate may be evaluated to determine if the power is within a specific range of values (defined by a lower bound and an upper bound indicating a valid power). If the power is not within the range of values, then the power fails to meet a valid power condition. Improvements to Amplitude Evaluation and Power Evaluation A counter may be provided for any one or more of the threshold comparisons or evaluations to avoid considering the signal to be invalid too early, easily, or frequently. For instance, the sample value may need to exceed a “Maximum Amplitude Threshold” P number of times before the method considers the signal to be invalid. In another instance, past P evaluations of the sample value are stored and checked to see more than a predetermined number of the evaluations indicate that the sample value exceeds the “Maximum Amplitude Threshold”, before the method considers the signal to be invalid. A filter may be provided for any one or more of the threshold comparisons or evaluations to dampen noisy evaluations (e.g., singular or occasional crossing of the threshold) and avoid considering the signal to be invalid too early, easily, or frequently. Logic may be provided to combine a suitable combination of threshold comparisons/evaluations to provide a final determination that the signal is invalid. Such improvements can improve stability of the evaluations and overall calibration method. Example of Interleaved Gain Error Estimate FIG.7is an illustrative block diagram of an ADC with interleaved gain error estimate according to an embodiment of the present disclosure. In the illustrative embodiment ofFIG.7, an interleaved gain error may be calculated as: Aerr=A0−A1. Aerrmay be added with previous Aerrestimates (i.e., it may be accumulated) to update the correction value used to adjust the subADC's gain (i.e., to perform correction). Updating the correction value can be performed in a least means squared (LMS) loop. As seen inFIG.7, the measured interleaved gain error, Aerr, is multiplied by a timing constant μ, and added to the old correction value α(old) to determine the updated correction value α(new). The accumulated, updated correction value, α(new), is the value that may be used to adjust subADC1's gain. This is also a value shown inFIG.5. The LMS loop, as it runs to iteratively update the correction value, may converge to reduce the measured interleaved gain error Aerr(e.g., making the measured interleaved gain error smaller and smaller), and to yield an updated correction value that is closer to the “true” correction value that would cause the gains of the subADCs to match. Example of a Chip Implementing an ADC The calibration process may be running continuously in background. This is to ensure good matching between subADCs as time goes by. The gain error will typically change as the chip's conditions change (temperature, input signal, sampling rate, supply, etc.). The calibration process preferably does not interrupt the output data of the interleaved-ADC, i.e., a user may operate the chip normally. FIG.8is an illustrative block diagram of chip embedding an ADC according to an embodiment of the present disclosure. As shown in the illustrative embodiment ofFIG.8, the calibration algorithm may be controlled by an on-chip microprocessor806in chip802that runs firmware with the calibration steps described above. The microprocessor may trigger a capture of M subADC samples on an on-chip random access memory804. After capture is completed, the microprocessor may read the subADC samples and execute the algorithm. The microprocessor is preferably on-chip to make the implementation more efficient, since data capture and transfers to components off-chip can be inefficient, power hungry, and requires additional data interface hardware. In some cases, one or more calculations/operations of the algorithm can be implemented in dedicated digital hardware as opposed to being implemented in firmware running on the microprocessor. The dedicated digital hardware can read and/or store samples or results of the calculations/operations in the on-chip random access memory. Histogram-Based Qualification of Data used in Background or Blind Calibration of Interleaving Errors of Time-Interleaved ADCs FIG.9is a flow diagram illustrating an example method for qualifying data used for background/blind calibration of interleaving errors, according to some embodiments of the disclosure. The method may be part of the calibration algorithm controlled and/or executed by the on-chip microprocessor ofFIG.8. The method can identify problematic input conditions, such as coherent input frequencies. The method is distinct from checking samples or estimated gain values against thresholds. In902, a data block may be captured. The data block comprises (digital) output values generated by one of the plurality of time-interleaved ADCs (one of the subADCs). In some embodiments, a qualification histogram may be generated by a histogram function in a qualifier based on the values generated by one of the plurality of time-interleaved ADCs. Depending on the implementation, the histogram function may run in real time. In904, the data block may be qualified by evaluating a variability measurement of a qualification histogram generated from the data block. A qualifier can measure an amount of clustering in a qualification histogram generated from the data block and output a qualification result based on the amount of clustering. In response to determining that the data block fails qualification (“N” path from904), an update of the background/blind calibration of the interleaving error may be skipped (906). In response to determining that the data block qualifies (“Y” path from904), the data block may be used to update the background/blind calibration of the interleaving error (908). An interleaving error calibration engine may be controllable by a qualification result from the qualifier. The qualification result may dictate whether the interleaving error calibration engine is to hold a previous value of an interleaving error correction coefficient or to update an interleaving error correction coefficient. An interleaving error calibration engine may include an interleaving error extractor to derive the interleaving error and update an interleaving error correction coefficient based on the interleaving error. For instance, the interleaving error extractor may derive the iterleaving error from corrected output values. The interleaving calibration error engine may further include an interleaving error correction block to apply interleaving error correction coefficient to reduce the interleaving error. The interleaving error correction coefficient can be applied digitally to the uncorrected output values generated by the plurality of time-interleaved ADCs to generate corrected output values. A data combiner may combine the corrected output values to generate a final output Dout. The signal range can dramatically change the variability measurement. A small signal can appear clustered in a few bins of the histogram since the full range of the histogram is not being exercised, which could lead the data block to fail qualification unnecessarily. To address this issue, a qualifier may perform a signal range check or perform a signal range estimate, and adjust the qualifier according to the signal range. In some cases, a qualifier can use a subset of the output values from a subADC for this purpose (e.g., during a first half of a calibration cycle), and use the rest of the output values (or all of the output values) to build a qualification histogram (e.g., during a second half of a calibration cycle). In some embodiments, a range histogram can be generated based on a first part of the data block (e.g., the subset of output values). A signal range may be estimated based on the range histogram. A qualifying histogram may be generated according to the signal range, based on the second part of the data block (e.g., the rest of the output values). If the signal is not changing frequently, the signal range estimate may be skipped in some cycles. FIG.10is a flow diagram illustrating another example method for qualifying data used for background/blind calibration of interleaving errors, according to some embodiments of the disclosure. The method may be part of the calibration algorithm controlled by the on-chip microprocessor806ofFIG.8. In1002, a signal range of the data block may be determined. In some embodiments, the signal range can be determined from a range histogram generated from the subset of output values. One or more upper empty bins of the range histogram may be an indicator of signal range. A smaller signal would leave upper bins empty since a small signal cannot exercise the full range of the range histogram. In1004, a range for the qualification histogram may be set based on the signal range. For instance, the upper limit of the range for the qualification histogram may be shifted to the point where the one or more upper empty bins begin. In1006, one or more programmable thresholds for evaluating the variability measurement of the qualification histogram may be set based on the signal range. This feature can allow the threshold to be adjustable for the signal range such than an optimum threshold with the appropriate sensitivity can be used for different signal ranges. In1008, a qualification histogram may be generated, e.g., based on the range set in1004using the rest of the output values. The qualification histogram may be generated using only the most significant bits or some bits below the most significant bits. The latter works by binning any output value above the range in the top bin and binning any output value below the range in the bottom/zero bin. For a given range of the qualification histogram, values above the upper limit of the range may be collected in the highest (or “top”) histogram bin. Based on the qualification histogram, one or more checks may be performed in1008to generate the qualification result. Enhancement to the Histogram-Based Qualification of Data A memory may be added, e.g., to the qualifier, to store the output from1008. This enables to keep track of a number of P previous qualifier outputs.908may be configured to calibrate only if1008is “Y” for at least P calibration cycles.908may be configured not to calibrate if there is at least one single “N” in the P previous outputs. A counter, filter, or logic can be provided to evaluate the P previous qualifier outputs. Keeping track of the P previous outputs may be implemented in firmware, such as firmware running on microprocessor806ofFIG.8. The P previous qualifier outputs may be stored in memory804ofFIG.8. Such enhancement can improve stability of the histogram-based qualifier and the overall calibration method. Example of Combining Gain Estimation, Thresholding, and Histogram-Based Qualification of Data FIG.11is a flow diagram illustrating a firmware-based interleaved-ADC gain calibration with hardware-thresholding enhancements of an illustrative embodiment. The method may be part of the calibration algorithm controlled by the on-chip microprocessor806ofFIG.8. In1102, output data (e.g., output samples) is captured from a subADC. This data capture may be performed in the flow diagram ofFIG.9orFIG.10, e.g., in902, as a part of902or separate from902, but the present disclosure is not limited to the examples ofFIG.9andFIG.10. In1104, amplitude may be evaluated per sample, e.g., as described in the examples with reference toFIG.6. In some cases, the evaluation may be based on several samples or a short block of samples instead of just one sample. In some embodiments, a sample or an absolute value of a sample may be compared against a threshold, such as a maximum amplitude threshold, and a minimum amplitude threshold. In hardware, it is possible to implement a thresholding operation based on one or more of the most significant bits. For instance, if a number of most significant bits of the sample all have the value zero, the amplitude of the sample may be too small. In1106, the power may be estimated using a sum of squares method, e.g., as described in the examples with reference toFIG.6. In1108, the power may be evaluated, e.g., as described in the examples with reference toFIG.6. In some cases, the evaluation may be based on several power values computed for several data blocks. The power can be compared against a threshold, such as a maximum power threshold, and a minimum power threshold. Based on thresholding, it may be determined whether or not the converted signal is valid, e.g., as described in the examples with reference toFIG.6. If the signal is found to be invalid (e.g., based on1104and/or1108), then the subADC data may be discarded and a new subADC data capture may be started, e.g., (as illustrated by the N path out of1104and the N path out of1118). If the signal is found to be valid, the method proceeds to1112, where it may be determined if the signal has a certain undesirable input condition (e.g., where the input frequency is a coherent sampling frequency that would cause the calibration to diverge or fail) based on the histogram memory, e.g., as described withFIG.8,FIG.9, and under the header “Enhancement to the histogram-based qualification of data”. The histogram memory may be implemented as the memory804shown inFIG.8. The histogram memory may be a part of the memory shown inFIG.8. If the signal is found to be invalid (based on histogram memory), then the subADC data may be discarded and a new subADC data capture may be started, e.g., illustrated by the N path out of1112inFIG.11. If the signal is found to be valid (based on histogram memory), calibration proceeds to1114,1116, and1118, illustrated by the Y path out of1112inFIG.11. In1114, the interleaved error may be estimated, as described withFIG.7. In1116, the error may be accumulated, as described withFIG.7. In1118, the error may be corrected, e.g., as described withFIG.5andFIG.7. Whenever a new subADC data capture is started (following one of the N paths inFIG.11), error extraction and calibration may be skipped and previously captured samples from a subADC may be discarded. Parts of the illustrated method ofFIG.11may be performed in parallel and not necessarily in the sequence shown. For instance, amplitude evaluation1104may be performed in parallel with power estimation1106. In another instance, amplitude evaluation1104may be performed in parallel with power evaluation1108. Other examples of parallelism and pipelining are envisioned by the disclosure. Select Examples Example 1 is a method to extract interleaving gain errors of a time-interleaved analog-to-digital converter having sub-analog-to-digital converters (subADCs) to sample an analog input signal in a time-interleaved manner, the method comprising: capturing a first data block of first output samples of a first subADC of the subADCs; evaluating whether one or more of the first output samples meet an amplitude condition; estimating a first power based on at least some of the first output samples of the first data block; evaluating whether the first power meets a power condition; qualifying, by a qualifier, whether first data block is suitable for interleaving gain error extraction; determining to proceed with extraction of a first interleaving gain error based on a memory storing a number of previous qualifier results from the qualifier; estimating the first interleaving gain error based the first power and a second power estimated based on second output samples of a second subADC of the subADCs. In Example 2, the method of Example 1 can optionally include capturing the first data block comprising: triggering the capturing by an on-chip microprocessor; and storing the first data block in on-chip memory. In Example 3, the method of Example 1 or 2 can optionally include evaluating whether the one or more of the first output samples meet the amplitude condition comprising: comparing one of the first output samples against a minimum amplitude threshold. In Example 4, the method of any one of Examples 1-3 can optionally include evaluating whether the one or more of the first output samples meet the amplitude condition comprising: comparing one of the first output samples against a maximum amplitude threshold. In Example 5, the method of any one of Examples 1-4 can optionally include evaluating whether the one or more of the first output samples meet the amplitude condition comprising: determining whether one of the first output samples is within a valid amplitude range. In Example 6, the method of any one of Examples 1-5 can optionally include: in response to a result of the evaluating of the one or more of the first output samples indicating the analog input signal is invalid, discarding the first data block and starting a new capture of a second data block of second output samples of the first subADC. In Example 7, the method of any one of Examples 1-6 can optionally include estimating the first power comprising: computing a sum of squares of the at least some of the first output samples. In Example 8, the method of any one of Examples 1-7 can optionally include estimating the first power comprising: computing a variance of the at least some of the first output samples. In Example 9, the method of any one of Examples 1-8 can optionally include estimating the first power comprising: for each sample of the first output samples in the first data block, removing a mean value from the sample and squaring a value of the sample with the mean value removed; and summing the squared values. In Example 10, the method of any one of Examples 1-9 can optionally include evaluating whether the first power meets the power condition comprising: comparing the first power against a minimum power threshold. In Example 11, the method of any one of Examples 1-10 can optionally include evaluating whether the first power meets the power condition comprising: comparing the first power against a maximum power threshold. In Example 12, the method of any one of Examples 1-11 can optionally include evaluating whether the first power meets the power condition comprising: determining whether the first power is within a valid power range. In Example 13, the method of any one of Examples 1-12 can optionally include in response to a result of the evaluating of the first power indicating that the analog input signal is invalid, discarding the first data block and starting a new capture of a second data block of second output samples of the first subADC. In Example 14, the method of any one of Examples 1-13 can optionally include qualifying whether the first data block is suitable for interleaving gain error extraction comprising: applying a histogram function on the first data block; and determining that the first data block is suitable for interleaving gain error extraction based on a variability measurement of the histogram. In Example 15, the method of any one of Examples 1-14 can optionally include determining to proceed with the extraction of the first interleaving gain error comprising: determining to proceed if all previous qualifier results indicate that a number of previous data blocks are suitable for interleaving gain error extraction. In Example 16, the method of any one of Examples 1-15 can optionally include determining to proceed with the extraction of the first interleaving gain error comprising: determining to not proceed if at least one of the previous qualifier results indicate that at least one of a number of previous data blocks are not suitable for interleaving gain error extraction. In Example 17, the method of any one of Examples 1-16 can optionally include in response to determining to not proceed with the extraction, discarding the first data block and starting a new capture of a second data block of second output samples of the first subADC. In Example 18, the method of any one of Examples 1-17 can optionally include estimating the first interleaving gain error comprising: determining a difference between the first power and the second power. In Example 19, the method of any one of Examples 1-18 can optionally include accumulating the estimated first interleaving gain error, using a time constant, with a previous estimate of the first interleaving gain error. In Example 20, the method of any one of Examples 1-19 can optionally include applying a correction value to an output of one of the subADCs based on the first interleaving gain error. Example 21 is a time-interleaved analog-to-digital converter, comprising: sub-analog-to-digital converters (subADCs) to sample an analog input signal in a time-interleaved manner; microprocessor on-chip with the subADCs; and memory; wherein the microprocessor is to: trigger a capture a first data block of first output samples of a first subADC of the subADCs in the memory; evaluate whether one or more of the first output samples meet an amplitude condition; estimate a first power based on at least some of the first output samples of the first data block; evaluate whether the first power meets a power condition; qualify, by a qualifier, whether first data block is suitable for interleaving gain error extraction; determine to proceed with extraction of a first interleaving gain error based on a memory storing a number of previous qualifier results from the qualifier; and estimate the first interleaving gain error based the first power and a second power estimated based on second output samples of a second subADC of the subADCs. In Example 22, the time-interleaved analog-to-digital converter of Example 21 can optionally include the microprocessor further being to perform any one or more of the methods in Examples 2-20. Example 23 is one or more computer-readable media having instructions stored thereon, wherein the instructions, when executed by one or more processors on-chip with a time-interleaved analog-to-digital converter having sub-analog-to-digital converters (subADCs) to sample an analog input signal in a time-interleaved manner, are to cause the one or more processors to perform the following: trigger a capture a first data block of first output samples of a first a of the subADCs in the memory; evaluate whether one or more of the first output samples meet an amplitude condition; estimate a first power based on at least some of the first output samples of the first data block; evaluate whether the first power meets a power condition; qualify, by a qualifier, whether first data block is suitable for interleaving gain error extraction; determine to proceed with extraction of a first interleaving gain error based on a memory storing a number of previous qualifier results from the qualifier; and estimate the first interleaving gain error based the first power and a second power estimated based on second output samples of a second subADC of the subADCs. In Example 24, the one or more computer-readable media of Example 23 can optionally include the instructions are to cause the one or more processors to further perform: any one or more of the methods in Examples 2-20. Example A is an apparatus comprising means to carry out any one or more of the methods in Examples 1-20. Other Implementation Notes, Advantages, Variations, and Applications Capture memory to store subADC samples, e.g., the memory shown inFIG.8, may be an on-chip memory. The microprocessor, such as shown inFIG.8, may access the stored samples to use with the algorithm, such as the algorithm shown inFIG.11. Power estimates using square of each subADC sample to estimate gain error, such as shown inFIG.6, may be less sensitive to certain input conditions compared to commonly used absolute values to estimate gain error. Thresholding, such as described in the examples with reference toFIG.6and in the example ofFIG.11, may include Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or the Histogram Output Memory. Herein, histogram memory means that a previous P histogram outputs may be kept in memory. These may be stored in a different memory (e.g., as a firmware variable) than the memory used for subADC data capture. The thresholding ensures no calibration is performed under undesirable input conditions. It is to be understood that not necessarily all objects or advantages may be achieved in accordance with any particular embodiment described herein. Thus, for example, those skilled in the art will recognize that certain embodiments may be configured to operate in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. It is also imperative to note that all of the specifications, dimensions, and relationships outlined herein (e.g., the number of modules/systems, logic operations, etc.) have only been offered for purposes of example and teaching only. Such information may be varied considerably without departing from the spirit of the present disclosure. The specifications apply only to some non-limiting examples and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular arrangements of components. The description and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense. Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the drawings may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. Note that in the present description, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “alternative embodiment”, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications. Note that all optional features of the systems and methods described above may also be implemented with respect to the methods or systems described herein and specifics in the examples may be used anywhere in one or more embodiments. As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied in various manners (e.g., as a method, a system, a computer program product, or a computer-readable storage medium). Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Functions described in this disclosure may be implemented as an algorithm executed by one or more hardware processing units, e.g., one or more microprocessors, of one or more computers. In various embodiments, different steps and portions of the steps of each of the methods described herein may be performed by different processing units. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable medium(s), preferably non-transitory, having computer-readable program code embodied, e.g., stored, thereon. The detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the select examples. In the description, reference is made to the drawings, where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the drawings are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. The disclosure describes various illustrative embodiments and examples for implementing the features and functionality of the present disclosure. While particular components, arrangements, and/or features are described below in connection with various example embodiments, these are merely examples used to simplify the present disclosure and are not intended to be limiting. It will of course be appreciated that in the development of any actual embodiment, numerous implementation-specific decisions must be made to achieve the developer's specific goals, including compliance with system, business, and/or legal constraints, which may vary from one implementation to another. Moreover, it will be appreciated that, while such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. In the present disclosure, reference may be made to the spatial relationships between various components and to the spatial orientation of various aspects of components as depicted in the attached drawings. However, as will be recognized by those skilled in the art after a complete reading of the present disclosure, the devices, components, members, apparatuses, etc. described herein may be positioned in any desired orientation. Thus, the use of terms such as “above”, “below”, “upper”, “lower”, “top”, “bottom”, or other similar terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of such components, should be understood to describe a relative relationship between the components or a spatial orientation of aspects of such components, respectively, as the components described herein may be oriented in any desired direction. When used to describe a range of dimensions or other characteristics (e.g., time, pressure, temperature, length, width, etc.) of an element, operations, and/or conditions, the phrase “between X and Y” represents a range that includes X and Y. If used, the terms “substantially,” “approximately,” “about,” etc., may be used to generally refer to being within +/−20% of a target value, e.g., within +/−10% of a target value, based on the context of a particular value as described herein or as known in the art. For the purposes of the present disclosure, the phrase “A and/or B” or notation “A/B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” or notation “A/B/C” mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). | 43,759 |
11942958 | DETAILED DESCRIPTION The present disclosure will refer to a method and device for compensating electrical device variabilities in configurable output circuits realized on a semiconductor substrate. Just as an example, the method is applied to a circuit structure including a plurality of electric components such as resistive elements, but nothing prevents from applying the teachings of the present disclosure to other kind of electronic components such as capacitive elements or inductive elements or even transistors. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein The principle of the present disclosure may be adopted for interconnected passive electronic components as well as for active electronic components realized inside integrated circuits manufactured on a semiconductor substrate and subject to possible process variations that may modify their characteristic if compared to a nominal ideal value. For a better understanding of the present disclosure, it should be first remarked that variations can be classified as uncontrollable (random) variations and controllable (systematic) variations which are topologically dependent. The random variations are uncontrollable and can be spontaneous, which changes the function of the electrical devices but is outside the scope of the present disclosure. On the contrary, controllable or systematic variation can be tuned for the desired optimum performance of the electrical devices. The controllable or systematic variation can be depicted, in some cases, as a surface gradient affecting the electrical behavior of the devices, according to the geometrical disposal of its components. Generally speaking the device or circuit components are arranged in the most possible compact area, i.e. a rectangle “tending to a square” or a square. The intensity of the surface gradient is related to the poorness of the process, electrical variations by mechanical stress, electrical bias dependence of the device characteristics. FIG.1schematically shows a TDAC (Thermometric Digital to Analog Converter) but the idea underlining the present disclosure may also be applied to other kinds of circuits based on switching a series of device components from an electrical level to another level. Just as an example, a TDAC is a circuit made by a set of resistive components sharing a common terminal OUT, the output of the DAC. For instance,FIG.1shows a schematic view of a known circuit structure concerning a voltage divider1including a first set2of resistive components biased by a first (e.g., higher) reference voltage level VH and a second set3of resistive components biased by a second (e.g., lower) reference voltage level VL. Some of the resistive components are connected to the higher reference voltage source VH through a switch SWH while some other resistive components are connected to the second lower reference voltage source VL through a switch SWL. Switches SWH and SWL may be representative of switches present on each branch of the circuit (not shown). Each component has its own switch. Such a circuit1represents a resistive voltage divider, between the voltage reference VH and the other voltage reference VL, including a series of “n” paralleled resistive components and “M-n” paralleled resistive components, where M is the total number of resistive components, and “n” varies between 0 and M according to the DAC input code. Usually M is a power of 2 minus 1 and the DAC output has M+1 configurations. The example of the TDAC shown inFIG.1has been provided adopting M=8 and n=2; however, in a more complex configuration with M=63 an ideal linear output may be defined by the line20reported in the diagram ofFIG.2. InFIG.2the Input Code value is represented on the horizontal axis, while the corresponding TDAC output voltage is represented on the vertical axis. As it may be appreciated, we have assumed that the 64 configurations of an ideal TDAC have a linear input to output relation. In fact, the value M=63 is only provided for the present explanation but shall not be considered a limiting factor. Moreover, output voltage ranging from VL (e.g., when all resistive elements are coupled between VL and OUT) to VH (e.g., when all resistive elements are coupled between VH and OUT); all resistive elements are assumed to be equal in this example. FIG.3represents only the possible real response of the TDAC circuit, as depicted by the following disclosure, including the 63 resistive components and the curved line30is indicative of the drift from the ideal values20. Such a deviation may be ascribed to process variability in some cases, as described below. For example, the 63 resistive components (+1 for the “closure”) of real TDAC circuit may be laid out and represented by a square matrix 8×8 shown inFIG.4. Due to lack of uniformity during processing, respective actual resistance values of each resistive component may increase from the first top row to the last bottom row, for example. The assumption of a preferential gradient is for explanation only. In fact, it is usually unknown to the producer. Finally, the number in the matrix describe the sequence of the resistive components commutations from VL to VH. The square 8×8 matrix shown inFIG.4also includes numbers that represent the sequence by which the coupling of each resistive component is switched from the lower reference VL to the higher reference VH (the other node remaining coupled to OUT). Initially (input code=0) all components are biased at VL, then the first (i.e., the number 0) resistive component R0is switched to VH (input code=1), next the second resistive component R1is switched to VH (input code=2), and so on. The side arrow represents the topological gradient of this example affecting the resistive components of a non-ideal TDAC circuit. The process gradient is unknown before the semiconductor device is manufactured and could vary among different lots and/or wafers and/or positions on the same wafer, either in terms of intensity and in terms of direction. The input to output characteristic response represented by the curved line30inFIG.3has been obtained just with the matrix distribution of the resistance values shown inFIG.4and the deviation of the curve line30is evident if compared with the ideal linear case of the line20. The maximal deviation for this example is 258 A.U. [arbitrary units] representing an undesirable high variability which may lead to the degradation of the performance of the electrical circuits. As an alternative, we may consider that there are various cases which can be taken in consideration and wherein the sequence by which each resistive component is switched from the lower reference VL to the higher reference VH. For instance,FIG.5represents a case wherein the order of switching of the square 8×8 resistive component matrix is mirrored for improving the process, the electrical variations by mechanical stress or the electrical bias dependence of the device characteristics. FIG.6is a diagram like the diagram ofFIG.3and represents the TDAC response of the square matrix shown inFIG.5with a mirrored order of switching. The diagram compares the resulting input to output characteristic curved line response60, obtained from the real resistances of the TDAC resistive components, with the ideal case previously discussed is still represented by the line20. The maximal deviation in this case is 254 [arbitrary units] representing a decrement of a very negligible variability in the electrical circuit and thus providing no significant improvement. Extending the previous considerations, the Applicant has tested the possibility to vary the sequence order of the resistive components switching, for instance from a selection that we may define “orthogonal” to the process gradient to a selection that may be considered “parallel” to the process gradient. FIG.7represents a schematic example wherein the sequence order of the resistive component switching has been varied. Previously, with reference toFIGS.4and5, the sequence order of the resistive component switching was orthogonal to the process gradient. In this further example ofFIG.7the sequence order of the resistive component switching is made parallel to the process gradient. FIG.8shows the TDAC response of the varied sequence order of the resistive components as shown inFIG.7thus obtaining an input to output characteristics depicted by the line80that is compared in that diagram with the usual ideal case input to output characteristics depicted by the line20. As it may be appreciated, this variation of the sequence order of the resistive component provides a good improvement with maximum deviation of 32 A.U. [arbitrary units] only, such a variation is dependent on the orientation of the process gradient which is however unknown in the real world. FIG.9represents a further square 8×8 resistive component matrix wherein another interleaved switching sequence is adopted. When half of the resistive components are biased by the upper reference voltage (VH) and half are biased by the lower reference voltage (VL) in a symmetrical configuration the output yield by this sequence is overlaid on the ideal output. The TDAC response of the interleaved switching sequence is shown inFIG.10and depicts that the curve90is similar to the ideal line20. The curve90here represents the obtained input to output characteristics while the line20represents as usual the ideal case of the input to output characteristics. This picture is very similar to the result of experimental outcome of silicon TDAC designed by the Applicant aside of other circuital limitations that move the “middle” point and dirty the “ends” of the curves. The adopted gradient intensity previously disclosed has been chosen according to the Applicant's testing activity but could be different in other cases. The previously disclosed cases show that the sequence order in which the resistive components are switched from one voltage reference to the other have a clear impact on the displacement of the real TDAC response with respect to the ideal TDAC response. However, if the process gradient was known a proper resistive component sequence could reduce the TDAC displacement from the ideal TDAC case, for instance like in the example ofFIG.8in which a maximal deviation of 32 [arbitrary units] has been obtained. Unfortunately, in real cases the orientation of the process gradient is unknown and usually unpredictable and none of the prior switching sequence methods provides a solution to bypass this problem. Hence, in consideration of the above-mentioned problem there is a need for a method to generate a sequence order of resistive components that is process gradient direction agnostic and hence is not affected by the orientation of the process gradient. The solution proposed by the present disclosure overcomes the drawbacks of the previous methods and suggests generating a sequence order of the resistive components that is process gradient direction agnostic through a checkerboard/negative-checkerboard pattern that has a capability to reach an ideal output response without the knowledge of the orientation of the process gradient. The present disclosure claims a method to generate a sequence order of resistive component that is process gradient direction agnostic through a checkerboard/negative-checkerboard pattern that has a capability to approach an ideal output without the knowledge of the orientation of the process gradient. Moreover, the present disclosure claims, a method to provide a compensation technique with respect to process variability. The method utilizes an algorithm for arrangement of elements to bypass process gradient problem. In one of arrangement of circuital elements, the problem of orientation of process gradient is minimized to reduce output variations. Furthermore, present disclosure claims a method to generate a switching sequence that is gradient direction agnostic. According to the method, a sequence of electrical components (as the resistive components in former explication example) that has been used where checkerboard (positive and negative) topology is being implemented to calculate parameter variations from ideal case. The method is based on a matrix representation of device topology with the cells representing intrinsic characteristics of an electric component of the device. The matrix is then considered as a group of surrounding circles starting from a central core portion and relates on staying on whatever circle, choosing whatever resistive component on that circle, considering that the closer neighbor resistive components on the circle are those most similar in resistance to the chosen resistive component and then follows the resistive components neighbors of the former neighbor resistive components and so on to achieve process gradient agnostic approach. Making now reference to the example ofFIG.11, it may be appreciated that the first square 8×8 resistive components matrix100may be considered as a checkerboard (positive or negative according to the situations) wherein each cell represents an electrical or resistive component having a real resistive value R derived by the manufacturing process on silicon. In this respect it is possible to identify a radius RD of concentric circles expanding from the central point of the matrix and variable by arbitrary units A.U. assuming a matrix of square cells of unit side. A first matrix100in the left end corner ofFIG.11shows with a colored circular-symmetric gradient a group of concentric circles formed by cells having a same distance D from the central point of the matrix. Such a distance D is of course variable according to the expansion of the circles of cells and we will refer hereinafter to different distances with a plurality of numbered reference signs d1, d2, . . . , dN. The inner four cells in the matrix core are equally distant from the central point of the matrix and this first distance d1, may be identified by half diagonal, for instance: SQR[(A.U./2)2+(A.U./2)2] with the previous assumption of unity cell's side. Similarly, each cell in each of the surrounding circles has a distance d2, . . . , dNthat is the same for all the other cells of the same circle. All electrical or resistive components are designed to have the same resistance value R, in this example. However, as consequence of processing, each component will have an actual resistance value that differs from the designed one by a variation that depends on the gradient (both direction and amplitude) and the distance d1, d2, . . . , dN. (also considering direction). In the subsequent matrixes reported inFIG.11the cells have been reported as organized in circles starting from the core portion of the central four cells previously mentioned as having a first distance d1from the central point of the matrix. This core portion is indicated with the number110wherein all the four cells have the same distance d1from the matrix center, for instance a spatial distance of value of 0.71 A.U. The cells of the core portion110may be considered part of a first circle having a first radius RD1. If we consider the eight cells located around this central core portion110, we may define this second group of cells as a second circle120surrounding the core portion110. The cells of this second circle have all the same distance d2from the central point of the matrix, for instance a value of 1.58 A.U., and may be considered part of a second circle having a second radius RD2. Proceeding in this manner from the central portion toward the periphery of the array we may identify groups of cells that may be considered part of an external circle having a higher radius RD3, RD4, . . . , RDN. For instance, the four cells located at the corners of a third circle130represent a common group located at a distance d3from the central point of the matrix or, in other words, positioned at a radius RD3from the matrix center. The common characteristic of the cells that are part of a circle is the same distance D from the central point of the matrix, see for instance the cells of the third circle130having a radius RD3and a common distance d3from the central point of the matrix of value 2.12 A.U. Similarly, we may proceed to identify other external circles with electric or resistive components having the same distance difrom the central point of the matrix if compared with a more internal circle. See for instance a fourth circle140having radius RD4and with resistive components positioned at a distance d4having a value 2.92 A.U. FIG.11shows the other remaining circles that have been identified as: a fifth circle150having radius RD5and with a distance d5from the central point of the matrix having a value of 2.55 A.U.; a sixth circle160having radius RD6and with a distance d6from the central point of the matrix having a value of 3.54 A.U.; a seventh circle170having radius RD7with a distance d7from the central point of the matrix having a value of 3.81 A.U.; an eighth circle180having radius RD8with a distance d8from the central point of the matrix having a value of 4.3 A.U. and a final ninth circle190having radius RD9with a distance d9from the central point of the matrix having a value of 4.95 A.U. The method of the present disclosure does work with any linear gradient of unknown orientation; the principle is based on switching the elements starting with the elements of inner core110, e.g., the cells that are very similar in resistance because very close to each other and then proceeding with cells on progressively increasing radius circles (jumping on diameters) adding then the cells that are deviating in opposite way, whichever the (liner) gradient is. This principle will be further explained with reference to a subsequentFIG.16. Focusing now our attention on the examples of theFIGS.12and13, we may appreciate that the same square 8×8 resistive components matrix may be examined under a different point of view and more particularly splitting the cells of the former circles in two main groups including positive checkerboard and negative checkerboard resistive values, respectively. FIG.12represents splitting out the resistive components picking out the resistive components belonging to a positive checkerboard. The positive checkerboard topology has been depicted with varying radius. Similarly,FIG.13represents splitting out the resistive components picking out the resistive components belonging to a negative checkerboard. The negative checkerboard topology has been depicted with varying radius. For instance, the square 8×8 resistive components matrix300shown inFIG.12includes only positive checkerboard electric components. The other matrixes ofFIG.12shows only couples of cells that are located at the same distance D from the central point of the matrix and that are selected in the switching sequence of the disclosed method. The other matrixes shown inFIG.12reports the various circles previously disclosed with reference toFIG.11and having radius from RD1to RD9but including only the positive checkerboard resistive values. In other words, the number310serves to indicate the cells of the first circle having radius RD1and located on a distance d1from the central point of the matrix (e.g., the cells in the core of the matrix). The number320is indicative of the cells of the second circle having radius RD2and located in the positive checkerboard at the distance d2from the matrix center. These cells may be paired according to the respective position being symmetric with respect to the matrix center. Paired cells will be switched in sequence to optimize linear output. The other matrixes shown inFIG.12, from330to390, reports the various circles with increased radius with the respective cells located on the positive checkerboard. Cells in each circle may be paired according to the respective position being symmetric to the matrix center. Paired cells will be activated in sequence to optimize linear output. Similarly,FIG.13shows a square 8×8 negative checkerboard matrix400of electric or resistive components. The other matrixes ofFIG.13shows only couples of cells that are located at the same distance D from the central point of the matrix and that are selected in the switching sequence of the disclosed method. In thisFIG.13the number410serves to indicate the cells of the first circle having radius RD1and located on a distance d1diagonal D from the central point of the matrix (e.g., the cells in the core of the matrix). The number420is indicative of the cells of the second circle having radius RD2and located in the negative checkerboard at the distance d2from the matrix center. These cells may be paired according to the respective position being symmetric with respect to the matrix center. Paired cells will be switched in sequence to optimize linear output. The other matrixes shown inFIG.13, from430to490, reports the various circles with increased radius with the respective cells located on the negative checkerboard. Cells in each circle may be paired according to the respective position being symmetric to the matrix center. Paired cells will be activated in sequence to optimize linear output. To be completely clear, in the non-limiting example disclosed herewith with respect to electric components having a specific resistive characteristic with an intrinsic resistive value, each element in the cell of the matrix is switched starting from the elements of inner core (i.e. the cells that are very similar in resistance because very close to each other) then proceeding with cells on progressively increasing radius circles (jumping on the opposite cell located at the same distance from the matrix center) adding then the cells that are deviating in opposite way, whichever the gradient is. The previous considerations may be expressed also in a different manner. If we consider the first central group or circle of cells110,310or410as a first reference of electric components having an intrinsic resistive value and the other resistive components laying on any diameter of the first central circle we may realize that there is a difference in these resistive values, with respect to the average RD value, and this difference is given by +DR and −DR, where DR can vary from zero to DRmax (>0, according to the position of the cells, e.g., both the radius of the circle and direction). Then, if we consider any other possible circle previously identified by the radius RD (from RD1to RD9) we may realize that staying on whatever circle and chosen whatever resistive component on that circle, the resistive component closer to the chosen resistive component is the one having most similar value in the resistive value. This evidence appears from the previously reported matrix representation including real values of each next neighbors resistive components located on the external circle surrounding the one taken in consideration. This is true from the central portion to the periphery but also in the opposite direction. In the following we describe the method of the present disclosure. Firstly, a “middle sequence” interleaved pattern for interconnecting the components can be adopted so that the specific configuration is by construction symmetrical to whatever gradient due to the process variables thus yielding a better performance even for reaching an ideal output starting from an unknown direction topological gradient. Secondly, the sequence may proceed on the selected circle along diagonal lines indicated in the drawings with dotted lines connecting ideally opposite cells located at the same distance from the matrix center for selecting the best resistive value for compensating the previous element in the interconnection sequence, since the two opposite elements of these cells are affected by the same and opposite deviations from an average resistive value. In view of the above considerations and according to one of the preferred embodiments, a method is disclosed to provide a compensation technique with respect to process variability. The method utilizes a switching or an interconnection sequence for interconnecting the electric components of the circuit device to compensate process gradient problem. In one arrangement of the circuital elements the problem of orientation of process gradient is minimized to reduce output variations, this is reported in the flow chart ofFIG.19. According to one embodiment of the present disclosure it is disclosed a method for compensating electrical device variabilities in configurable output circuits comprising: coupling a first set of electric components to a common node; coupling a second set of electric components to the common node; selecting and interconnecting some electric components of the first set to a first reference voltage and some electric components of the second set to a second reference voltage to provide a variable output at the common node between said second and first reference voltages based on a configuration; implementing an interconnecting sequence of said electric components based on an intrinsic characteristic of said electric components and according to an agnostic gradient direction of the physical location of the electric components. The electric components in the disclosed example are resistive components and said intrinsic characteristic is the resistive value of the component. However, nothing refrains from using other electric components such as capacitive or inductive components, in such a case the corresponding intrinsic characteristic will be the capacitance or inductance, respectively. Just as an example, an electric device to whom the method may be well implemented is a TDAC (Thermometric Digital to Analog Converter); however, other circuit device may adopt the compensation method of the present disclosure. In a further embodiment of the present disclosure the method relates to a compensating technique for electrical device variabilities in configurable output circuits comprising: representing the electric device layout and topography as a matrix of cells each representing an electric component having an intrinsic characteristic value; identifying in said matrix a plurality of surrounding circles of cells having increasing radius starting from a central first circle including a first squared group of cells; selecting and interconnecting the electric components represented in the matrix according to an interconnecting sequence that is agnostic to gradient direction of the physical topographical location of the electric components. Another embodiment of the present disclosure relates to an electric device or circuit including a plurality of electric or electronic components realized on a semiconductor substrate and having an intrinsic characteristic, comprising: a first set of electric components coupled to a common node, the common node configured to provide an output; a second subset of second electric components coupled to the common node; said electric components being interconnected to a first reference voltage or to a second reference voltage according to a sequence based on an agnostic gradient direction of the physical topographical location of the electric components thus limiting the manufacturing process variabilities. In some embodiments the first reference voltage is a higher voltage than the second reference voltage. In some embodiments the second reference voltage is a ground voltage. In some embodiments the output is a variable output voltage between the second and the first reference voltage. In some embodiments the electric components comprise one of a resistor, a capacitor or an inductor. In some embodiments the electric components have a same nominal value, e.g., comprise resistors with same resistance other than process-related resistance variations. In one of the embodiments, it is disclosed a method to generate a switching or an interconnecting sequence of electric components that is gradient direction agnostic and reduces dramatically the possible manufacturing process variabilities affecting said electric components. The method firstly suggests defining a matrix of cells representing the electric device layout and topography and wherein each cell represents an electric component having an intrinsic characteristic, for instance a resistive value. Then, starting on whatever circle representation of electric components, choosing whatever intrinsic characteristic of the chosen electric components, for instance the resistive value of that specific component, selecting and interconnecting the closer neighbor component having the most similar characteristic value, for instance the resistive value on the diagonal crossing externally that circle, continuing in the selection and interconnection of the neighbors components of the more external circle and so on up to the end of the matrix to achieve a process gradient agnostic approach. These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the examples of theFIGS.14and15. A systematic approach is implemented to bypass problem of process gradient and introduce the compensation technique of the present disclosure for configurable-output circuits. FIG.19shows a method to generate a switching sequence that is gradient direction agnostic. First, if a “middle sequence” interleaved pattern that is parallel to the gradient can yield a better performance than a “middle sequence” checkerboard/negative-checkerboard pattern can reach an ideal output for an unknown direction topological gradient. Secondly, if we consider the center of the rectangle that allocates the resistive components we can say that the resistive components oppositely laying on any diameter of a circle centered in the center of the rectangle have a difference in values with respect to the average R value equal to +DR and −DR, where DR can vary from zero to DRmax (>0, according to the position of the cells, e.g., both the radius of the circle and the direction). Finally, staying on whatever circle for what said in the former point, chosen whatever resistive component on that circle, its most close neighbor resistive components are the ones most similar in resistance to the chosen resistive component, then follow the resistive components neighbors of the former neighbor resistive components and so on. For a better understanding of the methodology, let's start in a first step “A” from the matrix checkerboard300ofFIG.14wherein the group of resistive components has been split out in subsets of resistive components characterized by having the same distance from the center of the central area, or central core, hosting the first circle of resistive components. Different subsets ranging from RD1to RD9have been represented and shown by grid diagrams. FIG.14presents an overview of the method steps of most convenient switching and/or interconnecting sequence for the electric components here taken in consideration, that is to say: the resistive components of the disclosed example. Starting from the most inner circle of the positive checkerboard Ck subsets of the matrix300we may select as second step “B” a resistive component of the main diagonal line as the first switching element and interconnect as third step the opposite resistive component on the same diagonal line of the same circle with RD1 Having selected the second component of the interconnection sequence the method suggests coming back the same circle but in this first passage all the resistive components have been covered. Therefore, the sequence proceeds on the following or surrounding circle selecting the resistive component that is the closest to the former initial resistive component. This is evidences inFIG.14with the curved dotted arrow500indicating a passage to a circle having larger radius. Thus, a new circle with radius RD2has been reached in a fourth step “D” and the algorithm proceeds in selecting the symmetric (with respect to the center of the matrix) resistive component located on the diagonal line on the opposite side of the same circle; see in theFIG.14the step “E”. The above passages is repeated for all remaining components of that circle. Therefore, on the same circle the next component to be selected is the one diagonally opposite to the last selected component. Then, jumping or coming back on the same circle, it will be selected the next closest component before the diagonal jump, according to a convenient rotation direction (clockwise or counterclockwise), see for instance the counterclockwise curved dotted arrow510indicating the selection of a subsequent cell on the same circle.FIG.14presents also sequence example for the resistive component's checkerboard subsets with rotation inversion when convenient. This passage is evidenced by the sixth step “F” InFIG.14, resulting in selection of component in cell4. Once the cells of a circle are completed (e.g., further selecting cell5, symmetrically located on the same diagonal as cell4), the selection passes to the next surrounding circle as shown by the dotted arrow520indicating a passage to a circle having larger radius. The procedure is repeated for all the other cells (and corresponding components) of a same circle thus repeating the steps “D”, “E” and “F”. The procedure will proceed in this manner up to the point wherein all the available resistive components (i.e. cells) of the positive Ck subsets are completed, thus reaching step “G” Reported in the last bottom right corner of the matrix300. Then, the selection passes or continues in step “G” with the other negative checkerboard wherein the switching sequence proceeds with a new second step “B” applied on the negative checkerboard400shown inFIG.15starting from two remaining negative cells410of the core inner four cells. Here, starting again from the most inner circle of the negative CkN subsets of the matrix400we may select as third step “C” a resistive component of the main diagonal line as the first switching element and interconnect to the opposite resistive component on the same diagonal line of the same circle with RD1. Then, a new circle with radius RD2is reached in a fourth step “D” and the algorithm proceeds in selecting the opposite symmetric (with respect to the center of the matrix) resistive component located on the diagonal line on the opposite side of the same circle; see in theFIG.15the fifth step “E”. FIG.15presents also sequence example for the resistive component's negative checkerboard subsets with rotation inversion (clockwise) when convenient. The whole procedure is thus repeated similarly for all the CkN subsets for reaching in step “END” The last bottom left cell of the matrix400. The algorithm stops when all the resistive components of the TDAC are crossed out. FIG.16shows a final representation of a matrix600reporting the sequence of the interconnected cells. Each cell number represents the order of the interconnecting sequence, e.g., the switching of electric component in respective cell from a low reference voltage to a high reference voltage (VL and VH nFIG.1, for example), obtained with the method previously disclosed. FIG.17shows a graphical representation of a real TDAC output vs. an ideal TDAC output based on the sequence shown in the matrix ofFIG.16. It may be appreciated that the result is particularly close to the ideal value since the two lines are substantially overlapping since the variability of the electric components has been compensated. FIG.18shows a schematic view of an example illustrating an integrated circuit device realized on a semiconductor substrate and having a plurality of electric components that have been interconnected according an agnostic gradient direction of their physical topographical variation in line with the method of the present disclosure. FIG.18shows resistive components, however the circuit can be realized with inductive of capacitive components or a mixture of them. On both sides of the central portion900of resistive components arranged as in a rectangular or square matrix, as the matrix100, there are circuit portions700and800including a plurality of inverters acting as switches for selectively interconnecting the various electric components to the first or to the second reference voltage values VH and VL. Each resistive component has one terminal coupled to a common node OUT and another terminal coupled to respective switch (an inverter in the example depicted). The interconnection sequence of the electric components of the central matrix portion900is based on the method previously disclosed. Accordingly, inverters coupled to respective resistive components are sequentially activated so that the terminal of the corresponding resistor is switched from VL to VH starting from the resistors located in the central core of the matrix and followed by symmetric resistors in same circle and then by resistors in surrounding circles with increasing radius, according to the sequence described with reference to drawings11-16. The variable voltage provided at the common node OUT changes between VL and VH based on the circuit input driving the inverters or switches. It should be noted that while circuit portions are depicted in the periphery (e.g., at the left and at the right of central matrix portion900), in other embodiments the disposition may be different; for example, inverters and/or switches may be positioned adjacent to respective component. It should be further noted that the method of the present disclosure could be implemented in a different manner. Instead of starting from the central core of the matrix of the positive Ck and negative CkN checkerboard patterns, it would be possible to start from the outer circles of the two patterns and proceed inwardly. As a further alternative, it would be possible to start from central core portion of the matrix of positive Ck checkerboard pattern and reprise from the outer circle of the negative CkN checkerboard pattern. Another possible alternative would suggest starting from the outer circle of the positive Ck checkerboard pattern and reprise from the inner circle (center) of the negative CkN checkerboard pattern or swap Ck and CkN for any of the above possibilities. Moreover, also within a selected pattern the initial resistive component to switch is not unique. All these procedures give the same results, they can vary according the real gradient direction and the TDAC design (i.e.: if the resistive components are initially all connected to VL and at the end all connected to VH or vice versa) Process/mechanical/bias gradient driven electrical variations of components of circuits meant to realize an output varying between two extremes deviates the expected result with respect to the theoretical input and output curve in relation to the intensity of the variation gradient. The presented method/algorithm/technique can be as much as four times better than a generic “natural” switching sequence. The proposed method, in its more general terms, relies on the fact that when moving in sequence the electrical components of the configurable-output circuit from one reference source to the other it is convenient to alternatively move one component with a certain variation followed by one with the opposite variation of similar intensity trying to minimize the variability of the absolute variation as common rule. In this way the composition of the electrical behavior of the different components tend to average out instead of, potentially, reinforce each other. Under this strategy the proposed method is a reasonable way to obtain a better working configuration with respect to a “naturally drawn” design. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims. | 41,826 |
11942959 | DETAILED DESCRIPTION The present disclosure is directed to adaptive linearization calibration for a system with respect to ADC performance in a final application based on DNL/INL. FIG.1Aillustrates a schematic diagram of a calibration circuit100with a direct sensing path in accordance with aspects of the disclosure. The calibration circuit100comprises a signal generator circuit110, a feedback circuit120, and an Analog-to-Digital Converter (ADC)130. The signal generator circuit110, the feedback circuit120, and the ADC130are provided on a same chip, which may be that of a microcontroller. The calibration circuit100is coupled to an analog Low Pass Filter (LPF)10that is not on the same chip as the calibration circuit100, although the disclosure is not necessarily limited in this respect. The signal generator circuit110comprises a digital delta sigma (AZ) modulator112and an input/output (I/O) driver114. The signal generator circuit110is configured to generate and drive an analog input signal S114for input to the analog LPF10, and which is based on a digital input word Sin that is modulated S112. More specifically, the digital ΔΣ modulator112is configured to modulate the digital input word Sin to output the analog input signal S112. The driver114, which is coupled to the ΔΣ modulator112, is configured to drive the analog input signal S112from the digital ΔΣ modulator112to output the analog input signal S114. The I/O driver is the significant contributor to analog signal S10inaccuracies, because of the non-linearity in the I/O driver, disturbing the 1-bit PDM modulation information after the driver. The ADC130is configured to convert an analog reference signal S10to a digital calibration word S130used for calibration of the ADC130. The analog reference signal S10is a low-pass-filtered version of the analog input signal S114generated by the signal generator circuit110. The ADC130may be a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC, for example. And the system being calibrated may comprise a microcontroller. The feedback circuit120comprises an analog modulator122, a digital low pass filter (LPF)124, and a processor126. The feedback circuit120is configured to output the digital input word Sin depending on a digital feedback signal S124, which is based on a modulated analog ref signal S122of the analog reference signal S10. More specifically, the analog modulator122is configured to modulate the analog reference signal S10into the modulated analog reference signal S122. The digital LPF124is coupled between the analog modulator122and the processor126, and is configured to low-pass-filter the analog modulated analog reference signal S122to output the digital feedback signal S124. And the processor126is configured to output the digital input word Sin of the signal generator circuit110by adjusting the digital calibration word S130based on the digital feedback signal S124. The processor126may be software, firmware, and/or hardware-based. The digital LPF124may comprise a cascaded integrator-comb (CIC) filter and/or a finite impulse response (FIR) filter. The analog reference signal S10corresponds with the analog input signal on the x-axis of the ADC transfer function300ofFIG.3. The ADC130is the ADC under test. And the digital calibration word S130corresponds with the digital output word on the y-axis of the ADC transfer function300ofFIG.3. The ideal ADC curve is a step function in LSB steps for a linear voltage ramp on the input. But the actual ADC curve deviates from the ideal stepwise function ADC curve. The ADC130has non-linearity, which causes inaccuracies visible at the digital output word. To be able to characterize the non-linearity of the ADC, the analog reference signal S10needs to be more accurate than the ADC under test. The inaccuracies in analog reference signal S10are mainly caused by the I/O driver114. This is due to a pull-up pull-down circuit114.2(shown inFIG.1B) of the I/O driver114having asymmetry between a pull-up of the PMOS versus a pulldown of the NMOS, and its filtered transfer function results a deviation in analog reference signal S10. This is especially the case if the I/O driver114output (driven analog input voltage114) is close to half of the maximum input voltage when both the PMOS and NMOS are alternatingly active. The feedback circuit120in combination with the signal generator circuit110improves the quality of the analog reference signal S10. The digital calibration word S130can be used for the final application. After the calibration, the ADC130error may be provided to be used to compensate for nonlinear errors of the ADC. The calibration may be performed at system start-up or during run time. Since the sensitivity of the ADC130is more accurate, the calibration disclosed herein avoids a need for an application to have as significant a non-linearity margin for error for the entire voltage and temperature range in volume production. The digital ΔΣ modulator112and analog modulator122are of corresponding types. The digital ΔΣ modulator112may be a High Speed Pulse Density Modulator (HSPDM), and the analog modulator122may be an Enhanced Delta-Sigma (EDS) ADC. Alternatively, the digital ΔΣ modulator112may be a delta-sigma Digital-to-Analog Converter (DAC), and the analog modulator122a delta-sigma ADC. The digital ΔΣ modulator112may be a digital pulse frequency modulator, and the analog modulator122an analog pulse frequency modulator. The digital ΔΣ modulator112may be a digital pulse width modulator, and the analog modulator122an analog pulse width modulator. Or the digital ΔΣ modulator112be a digital pulse code modulator, and the analog modulator122an analog pulse code modulator. These digital and analog modulators are examples and not meant to be limiting. FIG.1Billustrates a schematic diagram of a specific examples of components of the calibration circuit100ofFIG.1A. The digital ΔΣ modulator112is a second order feed-forward (FF) digital delta sigma (AZ) modulator. The I/O driver114comprises a level shifter114.1and a pull-up pull-down circuit114.2. The analog LPF10comprises a resistor capacitor (RC) circuit. The analog modulator212is a second order feed-forward (FF) analog delta sigma (AZ) modulator. And the digital LPF124comprises a cascaded integrator-comb (CIC) filter124.1coupled with a finite impulse response (FIR) filter124.2. This figure is provided merely as an example and not meant to be limiting. Also, the operations of the specific components should be understood by those of skill in the art, and for the most part, are outside the scope of this disclosure. For the sake of brevity and to not obscure more important aspect of the disclosure, detailed descriptions of these components are not provided here. FIG.2Aillustrates a schematic diagram of a calibration circuit200with an indirect sensing path in accordance with aspects of the disclosure. The calibration circuit200is similar to the calibration circuit100ofFIG.1A, except that the feedback circuits120and220differ slightly. The feedback circuit120ofFIG.1Ahas a direct sensing path from the analog reference signal S10. On the other hand, this feedback circuit220has an indirect sensing path from the driven analog input signal S114. The calibration circuit200comprises the signal generator circuit110, a feedback circuit220, and the ADC130. The signal generator circuit110, the feedback circuit220, and the ADC130are provided on a same chip. The calibration circuit200is coupled to the analog LPF10, which is not on the same chip as the calibration circuit200, although the disclosure is not necessarily limited in this respect. The signal generator circuit110, its components modulator123and I/O driver114, and the ADC130are described above with respect to the calibration circuit100ofFIG.1A. The feedback circuit220comprises a digital LPF224and a processor226. There is no analog modulator as in the feedback circuit120ofFIG.1A. The digital LPF224thus receives the digital signal directly from the I/O. More specifically, inFIG.1Adescribed above, the LPF124receives the modulated analog reference signal S122from the analog modulator122, which modulates the analog reference signal S10. In contrast, this LPF224receives the driven modulated analog input signal S114from the signal generator circuit110. The feedback circuit220is configured to output the digital input word Sin depending on a digital feedback signal S224, which is based on S114. More specifically, the processor226is configured to adjust the digital input word Sin based on the driven analog input signal S114of the signal generator circuit110. And the digital LPF224, which is coupled to the processor226, is configured to low-pass-filter the driven analog input signal S114to output the digital feedback signal S224. The processor226may be software, firmware, and/or hardware-based. The digital LPF224, like digital LPF124, may comprise a CIC filter and/or a FIR filter. Again, there is no analog modulator receiving an analog reference signal S10from outside the calibration circuit as in calibration circuit100ofFIG.1A. Rather, the LPF224of the feedback circuit220receives from within the calibration circuit200the driven modulated analog input signal S114from the I/O driver114, which is a circuit element likely contributing to S10analog reference signal inaccuracies. An advantage in this feedback circuit220is there is no analog modulator requiring additional area and current. FIG.2Billustrates a schematic diagram of specific examples of components of the calibration circuit200ofFIG.2A. Specific examples of components of calibration circuit200are the same as that of the calibration circuit100ofFIG.1Adiscussed above, with the obvious exception of the analog modulator122. The aspects disclosed herein do not require an expensive external signal generator for ADC performance characterization. Measurements may be made during microcontroller runtime and under application conditions on a customer board; external measurements in a final application are not possible for the accuracies required. The aspects can be used as a tool for printed circuit board design assessment for ADC, and for DNL/INL assessment of a customer system. And the external analog LPF10may be reused for the measurement with no additional cost. The techniques of this disclosure may also be described in the following examples. Example 1. A calibration circuit, comprising: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word for measuring its DNL and INL performance, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip. Example 2. The calibration circuit of claim1, wherein the feedback circuit comprises: an analog modulator configured to modulate the analog reference signal into the modulated analog reference signal; and a processor configured to adjust the digital input word of the signal generator circuit based on the digital feedback signal. Example 3. The calibration circuit of claim2, wherein the feedback circuit further comprises: a digital Low Pass Filter (LPF), coupled between the analog modulator and the processor, and configured to low-pass-filter the modulated analog reference signal to output the digital feedback signal. Example 4. The calibration circuit of claim3, wherein the digital LPF is a cascaded integrator-comb (CIC) filter or a finite impulse response (FIR) filter. Example 5. The calibration circuit of claim2, wherein the signal generator circuit comprises: a digital modulator configured to modulate the digital input word to output the analog input signal. Example 6. The calibration circuit of claim5, wherein the signal generator circuit further comprises: a driver, coupled to the digital modulator, and configured to drive the modulated analog input signal from the digital modulator to output the modulated analog input signal. Example 7. The calibration circuit of claim5, wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM), and the analog modulator is an Enhanced Delta-Sigma (EDS) ADC. Example 8. The calibration circuit of claim5, wherein the digital modulator and analog modulator are of corresponding types. Example 9. The calibration circuit of claim8, wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC) and the analog modulator is a delta-sigma ADC, or the digital modulator is a pulse frequency digital modulator and the analog modulator is a pulse frequency analog modulator, or the digital modulator is a pulse width digital modulator and the analog modulator is a pulse width analog modulator, or the digital modulator is a pulse code digital modulator and the analog modulator is a pulse code analog modulator. Example 10. The calibration circuit of claim1, wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC. Example 11. The calibration circuit of claim1, wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC. Example 12. A calibration circuit, comprising: a signal generator circuit configured to generate an analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word based on an analog feedback signal, which is based on the analog input signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip. Example 13. The calibration circuit of claim12, wherein the feedback circuit comprises: a processor configured to adjust the digital input word based on the analog input signal of the signal generator circuit. Example 14. The calibration circuit of claim13, wherein the feedback circuit further comprises: a Low Pass Filter (LPF), coupled to the processor, and configured to low-pass-filter the analog input signal to output the analog feedback signal. Example 15. The calibration circuit of claim12, wherein the signal generator circuit comprises: a digital modulator configured to modulate the digital input word to output the analog input signal. Example 16. The calibration circuit of claim15, wherein the signal generator circuit further comprises: a driver, coupled to the digital modulator, and configured to drive the analog input signal output by the digital modulator to output the analog input signal. Example 17. The calibration circuit of claim15, wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM). Example 18. The calibration circuit of claim15, wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC), a pulse frequency digital modulator, a pulse width digital modulator, or a pulse code digital modulator. Example 19. The calibration circuit of claim12, wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC. Example 20. The calibration circuit of claim12, wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC. Example 21. A calibration method, comprising: generating, by a signal generator circuit, a modulated analog input signal, which is based on a digital input word that is modulated; converting, by an Analog-to-Digital Converter (ADC), an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and outputting, by a feedback circuit, the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip. Example 22. The calibration method of claim21, wherein the adjusting by the feedback circuit comprises: modulating, by an analog modulator, the analog reference signal into the modulated analog reference signal; and adjusting, by a processor, the digital input word of the signal generator circuit based on the digital feedback signal. Example 23. The calibration method of claim22, wherein the adjusting by the feedback circuit further comprises: low-pass-filtering, by a digital Low Pass Filter (LPF) coupled between the analog modulator and the processor, the modulated analog reference signal to output the digital feedback signal. Example 24. The calibration method of claim23, wherein the digital LPF is a cascaded integrator-comb (CIC) filter or a finite impulse response (FIR) filter. Example 25. The calibration method of claim22, wherein the generating by the signal generator circuit comprises: modulating, by a digital modulator, the digital input word to output the modulated analog input signal. Example 26. The calibration method of claim25, wherein the generating by the signal generator circuit further comprises: driving, by a driver coupled to the digital modulator, the analog input signal from the digital modulator to output the analog input signal. Example 27. The calibration method of claim25, wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM), and the analog modulator is an Enhanced Delta-Sigma (EDS) ADC. Example 28. The calibration method of claim25, wherein the digital modulator and analog modulator are of corresponding types. Example 29. The calibration method of claim28, wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC) and the analog modulator is a delta-sigma ADC, or the digital modulator is a pulse frequency digital modulator and the analog modulator is a pulse frequency analog modulator, or the digital modulator is a pulse width digital modulator and the analog modulator is a pulse width analog modulator, or the digital modulator is a pulse code digital modulator and the analog modulator is a pulse code analog modulator. Example 30. The calibration method of claim21, wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC. Example 31. The calibration method of claim21, wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC. Example 32. A calibration method, comprising: generating, by a signal generator circuit, a modulated analog input signal, which is based on a digital input word that is modulated; converting, by an Analog-to-Digital Converter (ADC), an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and outputting, by a feedback circuit, the digital input word by adjusting the digital calibration word based on an analog feedback signal, which is based on the analog input signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip. Example 33. The calibration method of claim32, wherein the adjusting by the feedback circuit comprises: adjusting, by a processor, the digital input word based on the analog input signal of the signal generator circuit. Example 34. The calibration method of claim33, wherein the adjusting by the feedback circuit further comprises: low-pass-filtering, by a Low Pass Filter (LPF) coupled to the processor, the analog input signal to output the analog feedback signal. Example 35. The calibration method of claim32, wherein the generating by the signal generator circuit comprises: modulating, by a digital modulator, the digital input word to output the analog input signal. Example 36. The calibration method of claim35, wherein the signal generator circuit further comprises: driving, by a driver coupled to the digital modulator, the analog input signal output by the digital modulator to output the modulated analog input signal. Example 37. The calibration method of claim35, wherein the digital modulator is a High Speed Pulse Density Modulator (HSPDM). Example 38. The calibration method of claim35, wherein the digital modulator is a delta-sigma Digital-to-Analog Converter (DAC), a pulse frequency digital modulator, a pulse width digital modulator, or a pulse code digital modulator. Example 39. The calibration method of claim32, wherein the ADC is a sample-and-hold ADC, a successive approximation register (SAR) ADC, or a pipelined ADC. Example 40. The calibration method of claim32, wherein the digital calibration word is for measuring differential non-linearity (DNL) or integrated non-linearity (INL) performance of the ADC. While the foregoing has been described in conjunction with exemplary embodiment, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Accordingly, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the disclosure. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the specific embodiments discussed herein. | 22,441 |
11942960 | DETAILED DESCRIPTION Analog to digital converters are used to take an analog signal as the input data and convert that data into a digital output. This analog to digital conversion may be done by taking a transformed value of the analog input signal, which is referenced against a stable external reference used for performing the analog to digital conversion. The digital output is proportional to the ratio of the analog input signal over the external reference. The external reference may be a precision reference standard, which is considered to be “precise” and which outputs a signal that is known to the system. A secondary bias, supply, or reference circuit can provide a reference bias that at least has a substantially stable electrical output the exact value of this reference bias may not be known to the system. This configuration allows for the precision reference standard to be powered off to conserve power while using the reference bias as an analog to digital measurement reference. Power is saved when the reference bias uses less power than the reference standard. For example, the reference bias could be an existing bias that is given an additional purpose as reference, or a lower power reference bias. The reference standard only has to be powered on during a calibration mode that uses the reference standard in order to determine an appropriate correction factor. If the reference bias has a slow variation in time the system may need to periodically or recurrently need to be placed back in calibration mode in order to maintain the correct correction factor. This correction factor is used to convert the digital output that was referred to the reference bias into one that is referred to the reference standard. Periodic or recurrent re-calibration of this correction factor may be required to account for slow variation of the reference bias. This takes advantage of the fact that the reference bias, while not precisely known, can be used by the analog to digital converter to determine a value for the digital signal that only needs to be corrected by the correction factor that was determined during the calibration mode. During a calibration mode, a correction factor or correction value is calculated, such as to capture the relationship between the reference bias and the reference standard. In some examples, the system also has the ability to monitor battery/supply health, such as when the system is deriving a reference bias from its battery or power supply. In some examples, the calculation of linear or non-linear and transient system factors, such as temperature dependencies or mechanical stress, can be accounted for in the calculation of the correction factor that is stored and used by the system. This correction factor can be determined by measuring the signal from a temperature or stress dependent circuitry using an analog to digital converter, and using a digital circuit to calculate the correction factor. The use of such a computational correction factor that takes into account such additional factors can help eliminate the need for analog adders and amplifiers to be included as part of a compensation circuit “upstream” from the analog-to-digital signal converter (ADC). The correction factor can be stored in a calibration storage, and can then be used during normal operating mode, to scale the output voltage. It is appreciated that the digital calculation of the correction factor allows for advanced digital noise attenuation and eliminates errors introduced by analog adders or amplifiers. In other examples, the external precision reference standard can be replaced by a computational reference standard. This computational reference standard is calculated by taking a linear combination of measurements of electrical signals from one or more temperature and/or stress dependent circuitries. Each signal is measured by an analog to digital converter that uses a reference bias that may not be known to the system. The resulting computational reference standard therefore is also determined with respect to that reference bias. The correction factor equals the reciprocal of the computational reference standard. It is appreciated that this embodiment does not require any analog adders or amplification circuitry, reducing sources of error. Advanced digital noise filtering can be applied to improve precision. It is also appreciated that measurements of the temperature and stress dependent signals can be done sequentially, such circuits can be reconfigured instead of being replicated in order to reuse a reference or sensor. This allows for elimination of matching errors. For example, a computational band-gap reference could be implemented with a single diode, that for each measurement is biased at a different current density. FIG.1illustrates a schematic of the ADC system100in a calibration mode. In the calibration mode, the ADC converter102takes as an input a reference bias the bias signal circuitry110at the system ADC input node106. Switch118bis used to control switching between when the ADC system100is in calibration mode or, alternatively, in operating mode (described with respect toFIG.2). Switches118a-118ccan be controlled by control circuitry120which can, at particular times, change the system from running in calibration mode to operating mode, either on a set recurrent schedule or when a user of the system sends a command signal to the ADC system100. In some implementations, the reference bias doesn't need to be sampled for the calibration mode or only once or, for example, if sampled, not sampled more than once per minute or even less often for a reference bias that has a slow drift, such as a slow discharging battery. When in calibration mode, switch118bis set to connect the reference bias from the bias signal circuitry110to the ADC input node106. This reference bias output by the bias signal circuitry110is a stable source. In some examples, the reference bias output from the bias signal circuitry110can be from a battery, capacitor, or any circuitry that outputs a stable signal as an output. To save power, this output must stay stable in time for multiple signal conversions taken by the ADC converter102. When the bias signal circuitry110is also acting as the power supply to the ADC system100, then the ADC converter102is powered by connecting the reference bias through power supply node114. In some examples, the reference bias is a supply voltage signal coupled to a battery or other power supply node. The ADC converter102also includes a measurement reference node116, which receives a signal from a reference standard108. Switch118cis used to control which reference signal is received at the measurement reference node116of the ADC converter102. While in calibration mode switch118cis in a position to couple a reference signal from the reference standard108to the measurement reference node116of the ADC converter102. The reference standard108circuitry may include large bypass capacitors that do not allow for fast power cycling such that a high quiescent current can be consumed by reference standard108circuitry. The reference standard108can be switched out and substituted by a secondary “known” voltage reference, which may be a precision reference or a less precise reference bias from the bias signal circuitry110. Using this known voltage reference at its measurement reference node116, the ADC converter102can perform an analog to digital conversion that presents a digital output at the output node122that is highly calibrated, accurate, and not prone to drifting due to heat or other packaging stresses. In some examples, the reference standard108is left on continuously. However, leaving the reference standard108in an “on” state is not ideal for low power applications. In some low power applications of the ADC converter102, the reference standard108is only turned on in periodic or recurrent fashion to use the reference standard108to determine a correction factor that can be stored in a calibration storage112. Since the bias signal circuitry110in some examples can also be the power supply for the ADC system100, the reference standard108in some examples can be turned on and off by switch118a. The correction factor may be represented mathematically as the ratio of the value at the ADC input node106and the value at the measurement reference node116. In calibration mode, the value of the ADC input node106may be represented as a voltage input Vin, where Vinis the voltage from the reference bias Vsupply. Therefore, Vin=Vsupplywhen in calibration mode. In calibration mode, the input at the measurement reference node116is the voltage Vreffrom the reference standard108. The correction factor may be represented as the ratio between the voltage input Vinand the voltage Vrefof the reference standard108. Therefore, the ratio VsupplyVref is stored in the calibration storage112as the correction factor. In other examples, these calculations can be done with a current or power input or reference instead of a voltage input or reference. FIG.2illustrates a schematic of the ADC system100when it is run in operating mode. The ADC converter102is powered by connecting the reference bias from the bias signal circuitry110through power supply node114. Once the correction factor is determined and saved within the calibration storage112, the control circuitry120can switch the ADC system100from calibration mode to operating mode by reconfiguring the switches118a-118c. The control circuitry120is configured to reduce power or to even turn off the power to the reference standard108when the ADC system100is run in operating mode. The system can be set up to use the minimum power-cycle frequency (calibration duty cycle) between running the system in calibration mode where the reference standard108is turned on and running the system in operating mode where the reference standard108is turned off or run in a low power mode. Turning off the reference standard108also allows the ADC system100the ability to take advantage of ultra-low noise properties of most battery chemistries. Precise supply calibration of the bias signal circuitry110is not required. Switch118aturns off the power to the reference standard108. Switch118capplies the bias signal circuitry110to the measurement reference node116of the ADC converter102. Switch118bis reconfigured to take in an analog input signal at the system input node104from an external source attached to the ADC input node106. In some examples, this may be a voltage signal or a current signal. In some implementations, the voltage input can be sampled at a high rate, such as every nanosecond or microsecond. Since the reference standard108is no longer consuming power, when turned off, this lowers the average power consumption of the ADC system100. The ADC converter102takes the correction factor saved in the calibration storage and uses it to correct the result of the ADC converter102before outputting the corrected digital signal at the output node122of the ADC system100. At the output node122of the ADC system100the output may be mathematically represented as a ratio of the input value over the reference value multiplied by the stored correction factor. The system input node104may be a voltage input (Vin). The input at the measurement reference node116, in operation mode, is the voltage from the reference bias Vsupply. In some implementations this value can be further corrected by one or more additional scaling factors (full scale value Fs). Therefore, applying the correction factor to output of the ADC converter102results in digital output value being a factor of known values Vinand Vref. Output=VinVsupply·VsupplyVref·FS=VinVref·FS Where digital computation may be power intensive, this method of calibrating a ADC converter102uses less power because it uses only multiplicative scaling to determine the output at the output node122. The correction factor VsupplyVref is determined without any additional calculation. FIG.3illustrates an alternative schematic of the ADC system300. This alternative schematic uses fewer switches, switch302aand switch302bthan the above discussed ADC system100. In this alternative schematic, when in calibration mode, the reference standard108is connected to the ADC input node106, such as by switches302aand302b. In some embodiments (not pictured) the ADC converter102, and the reference standard108when in calibration mode, are powered by the bias signal circuitry110. InFIG.3the ADC converter102, the reference standard108, and the bias signal circuitry110are powered by a power source at power supply node114. When the ADC system300is run in calibration mode the control circuitry120turns switch302aon to power the reference standard108as well as switch302bto sample signal from the reference standard at the ADC input node106of the ADC converter102. In one embodiment, the calibration calculation circuitry304can be used to find a reciprocal value of the correction factor and then can save the correction factor in calibration storage112. In another embodiment (not pictured) the reciprocal value may be determined by the calibration calculation circuitry304and applied to the digital output during the operating mode, while only the reciprocal of the correction factor is stored in the calibration storage112during the calibration mode. In some implementations of the ADC system300, the reference standard108only has to supply a charge during the calibration mode and is not disconnected from the ADC system300when it is not in use. Therefore, the system does not have to do any charge balancing after turning off the reference standard108. The switches can be operated to take in an analog input signal from an external source attached to the input node and to reduce the load on the reference standard108during calibration. Therefore, less power overall is used by the ADC system300. Just as in the previous implementation, the correction factor may be represented mathematically as the ratio of the value at the ADC input node106and the value at the measurement reference node116. However, in this case, the voltage at the ADC input node106can be represented by Vinbeing the voltage from the reference standard108Vref. Therefore, Vin=Vrefwhen in calibration mode. The input at the measurement reference node116is the voltage from the bias signal circuitry110Vsupply. The correction factor may be represented as the ratio between the voltage input and the voltage of the reference. Therefore the ratio VrefVsupply is stored in the calibration storage112as the correction factor. To make later calculations easier, the calibration storage112may save the reciprocal value of the correction factor VsupplyVref. In other examples using ADC system300, these calculations can be done with current or power inputs or references, as desired. In the operating mode (not pictured) switch302bare set to accept an input value from the system input node104from an external source. Once the correction factor or correction factor is determined and saved within the calibration storage112, the control circuitry120can switch the ADC system300from calibration mode to operating mode by reconfiguring the switch302aand switch302b. The ADC system300can be set up to use the minimum power-cycle frequency (calibration duty cycle) between running the system in calibration mode, in which the reference standard108is turned on, and running the system in operating mode, in which the reference standard108is turned off. Switch302aturns off the power to the reference standard108. Switch302bis activated to take in an analog input signal from an external source attached to the system input node104. In some examples, this may be an electrical signal such as a voltage signal or a current signal. In some implementations the voltage input can be sampled at a high rate, such as every nanosecond or microsecond. The ADC system300takes the reciprocal value of the correction factor saved in the calibration storage112to correct the analog to digital conversion result of the ADC converter102before outputting the corrected digital signal at the output node122of the ADC system300. At the output node122of the ADC system300, the output may be mathematically represented as a ratio of the input value (at system input node104) over the reference value (at measurement reference node116) multiplied by the stored correction factor. For example, an input voltage value of the ADC input node106may be represented as a voltage input Vin. The input reference value at the measurement reference node116, in operation mode, is the voltage from the reference bias Vsupply, for example. In some implementations, one or more of these values can be further corrected by one or more additional scaling factors (Fs), as needed. Therefore, applying the correction factor to the output of the ADC converter102results in the corrected digital output value being a factor of known values Vinand Vref. Output=VinVsupply·VsupplyVref·FS=VinVref·FS This can help allow for one or more additional parameters such as temperature or strain, or both, to be accounted for during calibration. Additional digital computation can be done during the determination of the correction factor at the computational calculation circuitry408before storing the correction factor in the calibration storage112. The correction factor can be understood to be related to the ratio of the stable measurement of the signal from the reference standard108over the bias signal circuitry110. The correction factor is stored in the calibration storage112. One or more other parameters that represent different package stresses such as temperature or strain, etc., for example, may also be measured in relation to the bias signal circuitry110. These values may be determined and used for analog to digital conversion correction in a manner such as described below with respect toFIG.4. The final digital calculation can apply the inverse of the correction factor to the ratio of the input signal over the bias signal circuitry110. While this approach does calculate an inverse of the correction factor which is stored in the calibration storage112before applying the correction factor to the raw digital output signal at the output node122, where the digital computation is not computationally power intensive, this approach can still help save power. FIG.4. illustrates an alternative schematic of an ADC system400using a computationally determined correction factor applied to the raw digital output of the ADC converter102. This method can be used with one or more of the other methods described above. The correction factor can take into account sensed signals that are due to one or multiple temperature or package stress dependent inputs. The correction factor is calculated, in calibration mode, from these sensed signals and computed values which represent the one or multiple temperature or package stress dependent inputs and saved as a calibration factor that is applied in the digital domain when the system is in operation mode. This can enable a combination of precision reference and precision data converter techniques with minimum overhead. The ADC system400as a whole does need to have some degree of stability between calibration cycles in order to make the measurements of an analog input signal for analog to digital conversion. However, even where the ADC system400as whole has variations, the correction factor would still be considered accurate so long as the variation in the systems are either slow or well corrected by calibration using the control circuitry. Slow variations in some examples can be on the order of seconds. These slow variations can be also handled using low pass or other filter circuitry in the system such as to attenuate variation in the reference standard output signal, such as based on a signal threshold. The reference standard circuitry includes the low pass or other filter circuitry to attenuate variation in the reference standard signal based on the indicated signal threshold in order to account for the temperature or stress dependent input. Adding a digital filter enables attenuation of reference noise and using a median filter it can also eliminate telegraph noise. Therefore, the system can take full advantage of a low-noise battery reference. This can be done by performing a reference computation of a series of filters attenuated by a correction factors, removing the noise from the system. InFIG.4the ADC converter102, the reference bias, and the reference standard are powered by a power source at the power input node at114. In some embodiments (not pictured) the ADC converter102is powered by connecting the reference bias which is output from the bias signal circuitry110through measurement reference node116. While only two package stress dependent inputs,402and404, are shown, the system can have many others that can be considered and corrected. In some examples these package stress dependent inputs such as402and404can input non-constant observations such as from one or more diodes, resistance temperature detectors (RTDs), stress sensors, or other similar devices. While two such devices are represented inFIG.4, the system can include more such inputs. The package stresses can be handled in the analog domain before inputting the signal to the system input node104into the ADC converter102of the ADC system400. However, doing so can increase the power consumption of the system. Therefore, there are benefits to having a computed calibrated reference that computes a reference value that applies the various package stress inputs402and404as well as reference standard (not shown) which is input at measurement reference node116. Then, the control circuitry120can be used to control switches to select which signal is used to generate the reference standard signal (which may also be referred to as the computational correction factor) based on a sensed signal and one or more computed values.FIG.4shows this as using input multiplexer406which acts as a control switch however other known switching circuit designs can be used. The computation correction factor is calculated digitally in the computational calculation circuitry408before being stored in calibration storage112. The computational correction factor may be represented mathematically as the ratio of the value at the ADC input node106and the bias signal circuitry110, which the control circuitry120can switch between. The corresponding computational correction factors can be saved in the calibration storage as needed for use with the particular signal value at the measurement reference node116. In an example, the calibration mode value of the ADC input node106may be a voltage input (Vin). The voltage input Vincan represent the voltage from the package stress dependent input402and404Vf1through Vfn, respectively. While only two package stress dependent inputs402and404are being considered within the system inFIG.4, more can be considered. In an example, the signal input at the measurement reference node116is the voltage from the reference bias Vsupply. The correction factor may be represented as the ratio between the voltage at the system input node104and the voltage of the reference at measurement reference node116. Therefore, the ratio VinVsupply is stored in the calibration storage112which may include multiple correction factors (such as C1, . . . , Cn) to determine a composite computation correction factor. In other examples these calculations can be done with current or power input or reference voltages, as desired. ComputationalCalibration=VinVsupply=C1Vf1Vsupply+…+CnVfnVsupply When in operating mode, a reciprocal value of the composite computational correction factor can be determined in the digital domain and applied to the raw digital output signal to provide a corrected digital output signal. The corrected digital output signal is then output at the output node122. Output=VinVsupply·VsupplyVref·FS=VinVref·FS While the above implementation need not use a reference standard108, a reference standard can be applied similarly to the approaches described above. This may have the advantage of not needing to find the reciprocal value of the computational correction factor before applying the computational correction factor to the raw digital output to get the corrected digital output at the output node122. The above description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. | 27,662 |
11942961 | DETAILED DESCRIPTION In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments. Figures parts, elements or components which have already been described with reference to previous Figures are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description. The present solution refers to an electronic circuit which includes at least a digital to analog converter coupled to a sign comparator and to a method for testing such an electronic circuit. In brief, the solution here described includes coupling two equal structures, or channels, including each a digital to analog converter coupled to a sign comparator through a switch network, so that when in self-test mode, the output of the DAC of one structure is coupled to an input of the sign comparator of the other structure, the other input of the sign comparator still being maintained coupled to its respective DAC in the structure. Thus, each of the sign comparator is performing a comparison of the two DAC outputs. A ramp generating circuit is provided which feeds to the two DACs two digital code ramps, in particular each ramp comprising a rising ramp to the DAC full scale value and a falling ramp. One of the ramps is shifted in value of a programmable offset and delayed of a programmable delay, which cover all the input codes of the DAC, i.e., they arrive to the DAC full scale value. A circuit is provided at the output of the sign comparators configured to evaluate the sign comparator outputs and to issue a go/no go signal, on the basis of the values assumed by the sign comparator, in particular a change of sign of the outputs for a time interval within the ramp duration interval. In this way, an automatic DAC integrity check is performed for all possible digital codes, thus providing the possibility of converting a semi-manual check performed at ATE, in which during the device testing all possible digital codes are set via communication protocol and outputs are checked via pin remap, in a complete automatic self-test GO-NOGO runnable both at an ATE and during run-time. InFIG.1it is shown an electronic circuit10comprising a digital portion50and an analog portion60. In the analog portion60it is provided a first channel20, which includes a first digital to analog converter, or DAC,21, which output is fed to the inverting input of a first sign comparator23, i.e., an analog comparator which compares the analog quantities at its two inputs and outputs a high level or low level depending on which quantity is greater. In the example, output countup0is of the high level if the value of the signal at the negative input is greater than the value of the signal at the positive input. It may be embodied by a differential amplifier, as shown inFIG.1. A second channel30includes a second DAC31which output is fed to the inverting input of a second sign comparator33. Each of the first and second channel20,30includes a respective switch22,32commanded by a self-test signal SE, which is for example a logic signal. In the example, if the self-test signal SE is logic zero, this signals operation in normal mode of the first and second channel20,30, while if the self-test signal SE is logic one, it signals a self-test mode, in which the channels20,30are tested for possible faults. As it will be also explained in the following, in the embodiment here shown both the channels20and30in self-test mode are DUT, Devices Under Test. Thus, in a first position the switch22or32couples a respective sense current Isense0or Isense1with the other input of the respective sign comparator23or33. InFIG.1it is not shown in detail, but the comparator23,33there represented is preferably embodied by a voltage comparator, thus corresponding voltages may be obtained from the sense current Isense0or Isense1, e.g., coupling resistors (not shown inFIG.1) at the corresponding input to obtain a voltage drop at the comparator input. Alternatively the comparator23,33may be a current comparator comparing directly currents coming from the DACs and sense currents Isense0, Isense1. In a second position the first switch22couples the output of the second DAC31with the other input of the first sign comparator23, the second switch32couples the output of the second DAC31with the other input of the first sign comparator23. The digital portion50includes a self-test circuit40, comprising a ramp generator41, which is configured to output a ramp RP of digital codes, as shown inFIG.2, i.e., a sequence of increasing digitally coded values. The self-test circuit40includes a summation block42, as well. The self-test circuit40receives from a register56, in particular a SPI interface register, which is clocked by a clock signal CK, a programmed offset PO value, without sign, which is summed or subtracted in the sum block42to or from the codes of the ramp RP, to obtain an offset ramp ORP. The outputs of the self-test circuit40, i.e., ramps RP and ORP, are fed to two two-inputs multiplexers51and52, which respective outputs are coupled to the inputs of the first DAC21and the second DAC32respectively. The other input of the multiplexers51and52receives a respective digital signal FUNCT0, FUNCT1which represents in the example here shown the threshold value for the analog to digital arrangement embodied by channels20,30during normal operation. The channel20or30during normal operation, e.g., SE=0, has the switch22,32coupled to the sense current Isense0, Isense1, which is in this way supplied to the non-inverting input of the comparator22,32, i.e., an operational amplifier, and the DAC21,31provides a digitally programmable threshold, FUNCT0, FUNCT1at the inverting input. The comparator22,32then produces a logic-high output whenever the sense current Isense0, Isense1is more positive than its threshold. As also discussed in the following, the channel20,30can be used also in a different way, depending on the signals which are brought as input to the DAC and to the sign comparator of a channel in normal mode. The present solution is not specifically directed to the analog to digital conversion via such channels, but rather to the test of the channels themselves, which in variant embodiments can be comprised also in different circuits. As for the DAC input selection, the multiplexers51and52receive as selection signal selecting one of their inputs, the self-test signal SE. The circuits of the digital portion50just described control the inputs of the channels20,30, while their outputs, the output signals countup0and countup1of the sign comparators23and33, are brought to two respective delay flip-flop circuits53,54, which outputs are fed to an output check logic block55. Also the ramp RP, or information IRP on the ramp RP, as better discussed in the following, is fed to the output check logic block55. The two delay flip-flop circuits53,54receive at their clock input a clock signal CLK and programmed delay signal PD. Flip-flop circuits53,54in particular sample the signals countup0and countup1of the comparators23,33maintaining for a programmed delay PD the output or outputs of said comparators23,33, in particular to take in account the time required by the channel under test to react to the applied test input. The output check logic block55on the basis of the value of the digital output signals DO53and DO54of the flip-flop circuits53,54issues a test status signal GNG, specifically a GO/NOGO signal, i.e., a signal with two values, one indicating that the test detects no faults in the channel20,30operation and it is possible then to GO, and the other that a fault is detected, thus the status is NOGO. Thus, recapitulating, when the self-test signal SE assumes a first logic value, e.g., 0, associated to the normal operation, the switches22,32couple the sense current Isense0, Isense1to the positive input of the sign comparator23,33, while the multiplexers51,52select the programmed threshold FUNCT0, FUNCT1, as the respective inputs of the DAC21,31. This is a normal operation configuration. The circuit10assumes a self-test configuration when the self-test signal SE, under the control of a control circuit, for instance a microprocessor or DSP here not shown, takes a second logic value, e.g., 1, associated to the self-test operation. In this case the first switch22couples the output of the second DAC31, which is indicated with AO31inFIG.2, with the other input of the first sign comparator23, the second switch32couples the output of the second DAC21, AO21, with the other input of the first sign comparator23. In the same time the first multiplexer51couples the input of the first channel20with the ramp generator41output, i.e., the ramp RP is fed to the first DAC arrangement20, while the second multiplexer52couples the input of the second channel with the output of the summation block42, i.e., the offset ramp ORP is fed to the second channel30. In this self-test configuration the second DAC31output AO31is mapped on the first sign comparator23in order to compare it with the first DAC21output AO21; instead, on the second channel the inputs of the second sign comparator33are switched with respect to the inputs of the first comparator23. By applying on two DACs two different ramps, one shifted by a programmed offset value in comparison with the other one, i.e., RP and ORP, the expected two sign comparators23,33outputs countup0and countup2at a given time should be always have values which are opposite and coherent with the ramps, i.e., in accordance with the relative positions of the code values of the ramps at such given time, i.e., coherent with which ramp has the current value greater than the value of the other ramp. InFIG.2it is shown a time diagram representing as a function of time t the codes at the input of DAC21,31, determined by ramps RP, ORP, i.e., inputs IN21, IN31, during the test phase TP. With NP is indicated when the test phase is finished. The ramps RP and ORP have both a rising ramp portion, in which the code values increase, and a falling ramp in which the code values decrease. As it can be seen fromFIG.2, the ramp with offset ORP, which corresponds to input IN31, in the rising portion of the ramp, is offset by a programmed offset value PO, added by the summation block42and coming from the SPI register56under the control of a clock CK. InFIG.2it is shown also that each step of the ramps, i.e., each code value, is maintained a for a given time step, TS, which in the example is 5 clock cycles Tclk, i.e., time step TS represents the time between each increase of one LSB (Least Significant Bit. The programmed delay PD is set preferably to a value equal to the given time step TS, e.g., 5 clock cycles Tclk. Such programmed delay PD, as mentioned, is applied at the flip-flop circuits53,54where the sign comparators23,33output is sampled, so that are checked in the output check logic block55with a delay that can be regulated to take in account the time required by the tested structure to react to the applied stimuli. This is order to align in time and value digital outputs DO53and DO54when they are checked in the output check logic block55. The check operation at output check logic block55takes place in the same instant at the end of every ramp step (after delay PD). For each step after the analog part60is introduced a delay PD to provide stable outputs and the digital block55evaluates them before to move to the next codes. By way of example, offset PO can be 10 and delay PD5. Offset PO=10 means DAC code shifted up/down (according to ramp phase) by 10 of one of DACs. Programmed delay PD may be considered as clock cycles Tck, therefore PD=5 means 5*Tck. When the offset ramp ORP in the rising ramp reaches the value corresponding to the upper limit of the scale or range, full-scale FS value, of the DAC converter31, a decreasing or falling ramp is generated by the ramp generator41, in particular the ramp generator being configured to apply the programmable offset PO and programmable delay PD to the rising ramp applied to one of the DACs and to the falling ramp applied to the other DAC. This may be obtained simply by having the DAC which was shifted up during the rising ramp shifted down during the falling ramp and vice versa. To the first DAC21is supplied a code sequence corresponding to the ramp RP which, in case of rising ramp goes from zero to full-scale FS minus the programmed offset PO value, and in the falling ramp goes from the full-scale FS to the programmed offset PO value, while for the second DAC31, which receives the sequence of codes of the ramp with offset ORP, in the rising ramp portion there is an additional offset PO, thus its code values correspond to the ramp RP values plus offset PO, in the falling ramp offset is subtracted, it is ramp RP values minus offset PO. For this reason, inFIG.1it is shown the summation block42as operating only the ramp supplied to DAC31, since for the DAC21the ramp RP for both the falling and rising ramp starts from one of the ends of the DAC scale, 0 on rising and full-scale FS on falling ramp. This allows to invert the comparators outputs during the two phases. If as in the example, PO=10, TS,PD=5, and the number N of bits of the DAC is 4, as shown inFIG.2, from the initial time the offset ramp ORP increases starting from the initial time, and the ramp RP follows after a programmed delay PD, i.e., 5 clock cycles. The ramp ORP with offset may reach the full-scale value FS of the DAC at time 2{circumflex over ( )}Nbit−1*TS, in the example 75 clock cycles. The full-scale value may be 25 counts, so ramp RP value is 15 and ramp with offset ORP value is 25 Then after expiration of delay PD, which is 5, i.e., at a time of 80 clock cycles, ramp RP value is set to 25 and ramp with offset ORP value is 15, and the falling ramps are started. InFIG.3it is shown a diagram of the analog outputs AO21, AO31of the DAC21and31during the test phase TP and of the outputs countup0, countup1of the sign comparators23,33, in a condition where there is no fault. As it can be seen, the analog signals AO21, AO31increase both linearly with the same angular coefficient, displaced of offset PO, and swap their relative position, i.e., the offset PO is applied on the other DAC, e.g.,31, and thus manifests on its corresponding other output, after the reaching of the full-scale value FS. InFIG.4it is shown a diagram of the outputs AO21, AO31of the DAC21and31during the test phase TP and of the outputs countup0, countup1of the sign comparators23,33, in a condition where there is a gain error on the first DAC21. The slope of the linear increase for the first DAC21is greater than the slope of the linear increase for the second DAC22, to which the offset PO is applied. When the linear increase of the value of the output AO21of the first DAC21surpasses the one AO31of the second DAC31, the outputs countup0, countup1of the sign comparators23,33swap value, i.e., one passes from high to low and the other from low to high. Since this occurs before reaching the maximum, i.e., the DAC full scale FS, thus an error ED can be detected at the output check logic block55. The outputs countup0, countup1are opposite, but the swap of their logic values is not coherent with the swap of the positions of the ramps RP, ORP or outputs AO21, AO31when changing from rising to falling ramp, in particular the swap of outputs countup0, countup1happens before. Thus, the output check logic block55, which receives the ramp RP or information IRP on the ramp parameters sufficient to establish which of the inputs IN21, IN31has greater code value at a given time, issues a status signal GNG which indicates an error, i.e., NOGO status, compares the outputs DO53, DO54of the flip flops53,54with the information IRP on the ramp parameters, i.e., checks if such outputs DO53, DO54correspond to an expected logic value given the relative position of said ramps and/or the time of the change of slope, from rising to falling, with associated swap of the vertical ramp position, indicated by the information IRP or by the received ramp RP itself. More in general, the output check logic block55checks if the comparators23,33, as sampled by flip-flops53,54, provide the opposite values as output or opposite and/or coherent with the ramp relative position. If this is not verified, a fault is present on one of two channels20,30and a flag is set, status signal GNG. The output check logic block55, by way of example, may be configured to perform a logic exclusive OR (XOR) between the outputs of the comparators23,33, more specifically outputs DO53, DO54, with delay PD, to verify if they are opposite, but this may not be sufficient. The comparators23,33could provide outputs which are opposite in logic value, but not coherent with the position of the respectively applied ramps. For instance in the example shown inFIG.2the output DO53of flip flop53has to be low and the output DO54of the flip flop54high during the time instants belonging to the rising ramp. Also comparators23,33may undergo output stuck-at fault or an excessive required time to stabilize the DAC plus comparator chain could cause signals DO53, DO54at output of flip flops53,54to be equal. Thus, the output check logic block55checks if the outputs of flip flops53,54with the applied delay PD are opposite in logic value and also if the logic value taken is coherent with the application of the offset to the ramps, e.g., the output of the comparator23corresponding to the not offset ramp RP has to be low and the other high. Of course, this coherence evaluation may take in account possible logic circuits which have the effect of inverting the outputs flip flops53,54, in that case output check logic block55checks that output53is high and output54is low. Thus in general the output check logic block55to check coherence receives information on the relative position of said ramps RP, ORP in time. This information can be represented by the ramp RP or both the ramps RP, ORP themselves, or by parameters of the ramps which enable to evaluate such relative position in time, such as the full-scale value FS of the range of the code sequence, the offset PO and the time step TS value to calculate the time instant of changing from rising ramp to falling ramp, where the relative position is swapped and/or the time instant of changing itself and/or any set of parameters which can be used to represent ramps like ramps RP, ORP. The output check logic block55is then configured to check if the comparator outputs correspond to, i.e., are coherent with, an expected value given said relative position of said ramps, for instance, as already mentioned, sampled outputs DO53low and DO54high during the rising ramp. As also mentioned, the expected value can depend on the specific circuitry, e.g., if the comparator output or input is inverted in some point or not, the output check logic block55, which is general a logic circuit or processing circuit, which can be also a portion of another logic or processing circuit, can be configured to set if the expected value for a given relative position of the ramp is high or low logic value. InFIG.5it is shown a diagram of the outputs AO21, AO31of the DAC21and31during the test phase TP and of the outputs countup0, countup1, of the sign comparators23,33, in a condition where there is a local shift on both DAC21,31. As shown a first local shift LS1takes place on the output AO31, i.e., a spike of increase of such analog output, however since the output AO31is determined by the offset ramp ORP (signal IN31) at input at the second DAC31in the rising ramp portion, output AO31has all values above output AO21at the time instants of the rising ramp, thus no swap takes place in the outputs of the sign comparators23,33. When a second local shift LS2takes place on the output AO31, since the output AO21is determined by the ramp RP (signal IN21) at input at the first DAC21in the rising ramp portion, a swap of the outputs countup0, countup1of the sign comparators23,33takes place, for a duration which is equal to the time length of the local shift LS2, then the outputs countup0, countup1revert back to the previous value. As the length of the local shift LS2is in general smaller of the total time to perform a rising or falling ramp, a feature such a pulse D1with its time width or a glitch identifies the length of the local shift LS2. The first local shift LS1is instead detected, as shown, during the falling ramp, where the ramp ORP is assigned to the other DAC, thus the increase due to the local shift LS1can determine a swap (pulse D2). It is here underlined that inFIG.1is exemplified an electronic circuit10comprising a digital to analog converter coupled to a respective sign comparator and receiving at its other input an analog electric quantity, in normal mode, i.e., the self-test signal SE is not asserted. Circuit10can operate as analog to digital converter, but the electronic circuit10is just exemplary of circuits which may include a digital to analog converter coupled to a respective sign comparator also for other purposes. The specific signal at the DAC21,21input and at the positive input of the sign comparator23,33can be different according to the application, and so can be different the output of the comparators in normal mode. The solution here is directed to an electronic circuit10which in general comprises a first digital to analog converter, e.g.,21, coupled to a respective first sign comparator.23, receiving at its other input a first analog electric quantity, sense current Isense0. Then, in order to perform the self-test such electronic circuit further comprises a second channel30comprising at least a second digital to analog converter31receiving at its other input a second analog quantity, sense current Isense1, the second digital to analog converter31in said second channel being coupled to a second sign comparator33, a switch network22,32configured to selectively couple, upon reception of a self-test mode signal SE signaling a test phase TP, the output AO21, AO31of the second digital to analog converter21,31at the input of the first sign comparator33,23, the other input of the first sign comparator23being maintained coupled to the output AO21of the first digital to analog converter21, and also the output AO21of the first digital to analog converter21at an input of said second sign comparator (33), the other input of the second sign comparator (33) being maintained coupled to the output (AO31) second digital to analog converter (31). Thus, the switch network also decouples from the analog electric quantity, sense current Isense0or Isense1, by the input of the corresponding comparator. The circuit further comprises a ramp generation circuit41configured to send to the input of said first DAC21and second DAC31two identical ramps RP, ORP of digital codes, which are shifted of a programmable offset value PO one with respect to the othera checking circuit55, the output check logic block, coupled to the outputs DO53, DO54of the sign comparators, in particular through the sampling performed at flip flops55with the programmed delay PD; configured to evaluate the sign comparator outputs and to issue a test status signal, which is for instance a flag signaling if there is error or not, in particular a go/nogo signal indicating the result of a pass/fail test, on the basis of the values assumed by the sign comparators, in particular a change of sign of the outputs for a time interval within the ramp duration interval and/or a coherence check. It will be appreciated that in variant embodiments the circuit55may check only the opposite values or the coherence. Now, by way of example, a calculation of the test time TSELFTESTDACnecessary or suitable to test a DAC by the solution here described is discussed. By considering by way of example the following values:the shift between two ramps, offset PO, may be set to 10, as mentioned this being DAC codes;the time required to have stable result each step, programmed delay PD, could be 4, e.g., 4 clock cycles Tclk;a duration of each communication, TCOMM, requires typically few μs (max 10 μs), depending on the frequency of communication;IC code changes requires a settling time, TSETTL, typically of 1 μs;a common DAC has usually N=10 bits;clock cycle TCLKis usually equal to 62.5 ns (fCLK=16 MHz);the total test time TSELFTESTDACof the solution here described can be calculated with this formula: TSELFTESTDAC=[2·(TSETTL+TREAD)]*+[2·(2N−PO)·PD·TCLK]=22 μs+507 μs≅529 μswhich is four magnitude orders lower than the test time of the prior art solution. In variant embodiments, the solution could be also implemented for a single comparator by exploiting a second DAC (no cross check with two comparators). More in detail in case only one comparator is present, i.e., the second comparator, e.g.,33, is missing because a second DAC31without sign comparator is exploited, the first DAC21output is remapped on comparator33in order to compare it with second DAC31output. In this case the check is focused only on the single comparator output, which should respect that the comparator output takes logic values corresponding to the relative positions of the ramps (i.e., upper position, ramp with offset PO lower position down ramp without offset PO). A sampling flip flop such as flip-flop53or54may also be present, which may also introduce a programmed delay, in order to supply the correct timing to the analogic portion60. In this case the checking circuit55may be used to evaluate only the coherence of the single comparator output, i.e., to check if the comparator output corresponds to an expected value given the relative position of the ramps RP, ORP. Thus, more in general the solution here described is directed to an electronic circuit comprising a first channel20comprising a first digital to analog converter (21) coupled to a respective first sign comparator23receiving at its other input a first analog electric quantity, such as sense current Isense0, whereinsaid electronic circuit comprisesa second channel30comprising at least a second digital to analog converter31receiving at its other input a second analog quantity, Isense1,a switch network22,32configured to selectively couple, upon reception of a self-test mode signal SE signaling a test phase TP, at least the output AO21, AO31of the second digital to analog converter21,31at the input of the first sign comparator33,23, the other input of the first sign comparator23being maintained coupled to the output AO21of the first digital to analog converter21,a ramp generation circuit41configured to send to the input of said first digital to analog converter21and second digital to analog converter31two identical ramps RP, ORP of digital codes, which are shifted of a programmable offset value PO one with respect to the other,a checking circuit55coupled at least to the output of said first sign comparator23,33configured to evaluate at least said first sign comparator output23,33and to issue a test status signal GNG, in particular a go/nogo signal, on the basis of values assumed by at least said first sign comparator output23,33. The solution just described, thus, by considering a structure, i.e., channel, composed of a DAC and a sign comparator, used in particular for A/D conversion, a self-test can be implemented by exploiting simultaneously two equal structures that test each other. The self-test covers the DAC integrity along all possible codes with a rising and a falling ramp, and the capability of two comparators to correctly provide 0 and 1. In case, during the ramps, comparators provide the same outputs or opposite and incoherent with the ramps, a fault is present on one of two DUTs and a flag is set. The self-test provides the possibility to configure the shift between two applied ramps (in order to consider the DAC uncertainty) and the time delay between digital codes applying and outputs sampling (in order to cover the time required by the tested structure to react to the applied stimuli). This solution replaces the actual routine for a DAC structure with only a sign comparator in an automatic and quicker self-test, which does not require any external equipment. The solution here described reduces test time and related costs maintaining test coverage by implementing a self-test. More in detail, the possibility to convert a semi-manual check (where the stimuli are sent via communication protocol) in a complete automatic self-test GO-NOGO runnable both at ATE and run-time, provides the possibility to reduce test time, related costs and effort for test program. Moreover, it is added the feature to re-run the test also on-field Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure. An electronic circuit may be summarized as including a first channel (20) including a first digital to analog converter (21) coupled to a respective first sign comparator (23) receiving at its other input a first analog electric quantity (Isense0), wherein said electronic circuit including a second channel (30) including at least a second digital to analog converter (31) receiving at its other input a second analog quantity (Isense1), a switch network (22,32) configured to selectively couple, upon reception of a self-test mode signal (SE) signaling a test phase (TP), at least the output (AO21, AO31) of the second digital to analog converter (21,31) at the input of the first sign comparator (33,23), the other input of the first sign comparator (23) being maintained coupled to the output (AO21) of the first digital to analog converter (21), a ramp generation circuit (41) configured to send to the input of said first digital to analog converter (21) and second digital to analog converter (31) two identical ramps (RP, ORP) of digital codes, which are shifted of a programmable offset value (PO) one with respect to the other, a checking circuit (55) coupled at least to the output of said first sign comparator (23,33) configured to evaluate at least said first sign comparator output (23,33) and to issue a test status signal (GNG), in particular a go/nogo signal, on the basis of values assumed by at least said first sign comparator output (23,33). Said second digital to analog converter (31) in said second channel may be coupled to a second sign comparator (33), and said switch network (22,32) may be configured to selectively couple, upon reception of a self-test mode signal (SE) signaling a test phase (TP), also the output (AO21) of the first digital to analog converter (21) at an input of said second sign comparator (33), the other input of the second sign comparator (33) being maintained coupled to the output (AO31) of said second digital to analog converter (31), said checking circuit (55) being coupled to the outputs (DO53, DO54) of the sign comparators (23,33) and configured to evaluate the sign comparator (23,33) outputs and to issue a test status signal, in particular a go/nogo signal, on the basis of the values assumed by said outputs (DO53, DO54) of the sign comparators (23,33). Said switch network (22,32) may include a first switch (22) selectively coupling said other input of the first sign comparator (23) to said first analog quantity or to the output of said second digital to analog converter (31) under the control of a mode selection signal (SE), a second switch (32) selectively coupling said other input of the second sign comparator (33) to said second analog quantity or to the output of said first digital to analog converter (21) under the control of said mode selection signal (SE). Each ramp (RP, ORP) may include a rising ramp and a falling ramp, in particular the ramp generator being configured to apply the programmable offset (P0) to the rising ramp applied to one of the digital to analog converters and to the falling ramp applied to the other digital to analog converter. May include one or more circuits (53,54) in particular delay flip flops, to sample the output or outputs of the comparator (23,33) maintaining for a programmed delay (PD) the output or outputs of said comparator (23,33), in particular to take in account the time required by the channel under test to react to the applied test input. Said checking circuit (55) may receive information on the relative position of said ramps (RP, ORP) in time and it is configured to check if the comparator output or outputs correspond to an expected value given said relative position of said ramps Said checking circuit (55) RP, ORP) may check if the comparator outputs are opposite. Said channels (20,30) may be included in an analog to digital conversion circuit. 9. A method for testing a circuit comprising a first channel (20) may be summarized as including a first digital to analog converter (21) coupled to a respective first sign comparator (23) receiving at its other input a first analog electric quantity (Isense0), including providing a second channel (30) including second digital to analog converter (31) coupled to a respective second sign comparator (33) receiving at its other input a second analog quantity (Isense1), selectively coupling by a switch network (22,32) upon reception of a self-test mode signal (SE) signaling a test phase (TP), at least the output (AO21, AO31) of the second digital to analog converter (21,31) at the input of the first sign comparator (33,23), the other input of the first sign comparator (23) being maintained coupled to the output (AO21) of the first digital to analog converter (21), generating (41) and sending to the input of said first DAC (21) and second DAC (31) two identical ramps (RP, ORP) of digital codes, which are shifted of a programmable offset value (PO) one with respect to the other, evaluating (55) at least said first sign comparator output (23,33) and to issue a test status signal (GNG), in particular a go/nogo signal, on the basis of values assumed by at least said first sign comparator output (23,33). A method may include providing to a second sign comparator (33) coupled to said second digital to analog converter (31) in said second channel, and said selectively coupling, upon reception of a self-test mode signal (SE) signaling a test phase (TP), also the output (AO21) of the first digital to analog converter (21) at an input of said second sign comparator (33), the other input of the second sign comparator (33) being maintained coupled to the output (AO31) second digital to analog converter (31), said evaluating (55) includes evaluating the sign comparator (23,33) outputs and to issue a test status signal, in particular a go/nogo signal, on the basis of the values assumed by said outputs (DO53, DO54) of the sign comparators (23,33). Said selectively coupling may include a first switch (22) selectively coupling said other input of the first sign comparator to said first analog quantity or to the output of said second digital to analog converter under the control of a mode selection signal (SE), a second switch (32) selectively coupling said other input of the second sign comparator to said second analog quantity or to the output of said first digital to analog converter under the control of said mode selection signal (SE). Each ramp (RP, ORP) may include a rising ramp and a falling ramp, in particular the ramp generator being configured to apply the programmable offset (P0) to the rising ramp applied to one of the digital to analog converters and to the falling ramp applied to the other digital to analog converter. A method may include introducing a programmed delay (PD) in the sampling the output or outputs of the comparator (23,33) maintaining for a programmed delay (PD) the output or outputs of said comparator (23,33), in particular to take in account the time required by the channel under test to react to the applied test input. Said evaluating (55) may include receiving information on the relative position of said ramps (RP, ORP) in time and checking if the comparator output or outputs correspond to an expected value given said relative position of said ramps Said evaluating (55) may include checking if the comparator outputs are opposite. A computer-program product that can be loaded into the memory of at least one processor and may be summarized as including portions of software code for implementing the method. The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. | 38,322 |
11942962 | In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not to scale. Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s). DETAILED DESCRIPTION In many examples, Analog to Digital (A/D) conversion is performed by dedicated ADC circuitry. The implementation and functionality of an ADC circuit may depend on the surrounding compute resources and how the converted digital values are used. For example, if the ADC circuitry is implemented within a microcontroller, it may support applications that include but are not limited to (a) sensing and control, and (b) signal processing. As used herein, sensing and control applications refer to any application that gathers data about a device or environment and performs actions to control the device or environment. Sensing and control applications include but are not limited to Internet of Things enabled devices, automotive control systems such as automated emergency breaking, lane keeping or gear shifting, flight control systems such as drone stabilization, robotic pose estimation, etc. Due to their relatively low frequency of A/D conversion requests, many sensing and control applications may access the conversion results as soon as the conversion occurs to determine a control action. In some examples, a single ADC circuit may be used by different application threads, where each thread uses a different ADC channels and expects the converted ADC result in a separate register. In such examples, an ADC circuit may have a set of registers with a one to one correspondence between a specific thread and a register. As used herein, a register refers to a specific address in memory that an ADC circuit can access and store conversion results in. Sensing and control applications are explored further inFIG.2. Some ADC circuits may support signal processing applications. As used herein, signal processing applications refer to any application that analyzes, modifies, or synthesizes signals. Examples of signal processing applications may be found in audio processing, image processing, video processing, wireless communications, etc. Due to their relatively high frequency of A/D conversion requests, signal processing applications may wait to access multiple conversion results at once to reduce the amount of resources used to access results. Signal processing applications are explored further inFIG.3. Previous implementations of ADC circuitry fail to provide a single set of registers that can both provide conversion results as soon as they are generated (as requested by control and sensing applications) and buffer high frequency conversion results (as requested by signal processing applications). Furthermore, the addition of a second set of registers to a previous ADC circuitry implementation, such as (a) the addition of buffer registers to an ADC circuit configured for sensing and control applications or (b) the addition of registers that immediately transfer results to an ADC circuit configured for signal processing applications, would increase the memory required to implement the ADC circuitry and be computationally expensive. Example systems, methods, and apparatus disclosed herein implement a single set of registers to store ADC results that can both provide conversion results as soon as they are generated for some threads and buffer high frequency conversion results for others. Example configurable ADC circuitry includes sequencer circuitry to receive a conversion mode and a First In First Out (FIFO) mode from a software application. The sequencer circuitry accesses a configuration from a memory control register based on a read pointer and updates the read pointer based on the conversion mode. A/D conversion circuitry determines digital values based on the configuration and stores the values into result registers based on a write pointer. The sequencer circuitry updates the write pointer based on the FIFO mode. In doing so, the configurable ADC circuitry supports single channel sensing and control, multi-channel sensing and control, single channel signal processing, and multi-channel signal processing modes of operation. FIG.1is a block diagram of an example implementation of computer circuitry.FIG.1includes example computer circuitry100, physical mediums102A-102B, and a network104. The example computer circuitry100includes example interface circuitry106, an example software application108, software triggers110, example clock circuitry112, example configurable ADC circuitry114, interrupts126, example Direct Memory Access (DMA) circuitry128, and example main memory130. The example configurable ADC circuitry114includes but is not limited to example sequencer circuitry116, example sample and hold circuitry118, example A/D conversion circuitry120, result registers122, and example interrupt circuitry124. The interface circuitry106ofFIG.1receives analog signals from one or more external sources. A first external source may provide the analog signals corresponding to sensing and control applications over a wired connection via the physical medium102A. In other examples, a second external source may provide the analog signals corresponding to signal processing applications over a wired connection via the physical medium102B. In other examples, a third external source may provide analog signals corresponding to either type of software application over a wireless connection via the network104. The analog signals may contain any type of information and come from any external source. The example software application108ofFIG.1requests digital values that represent the information encoded in the analog signals received at the interface circuitry106. The requests for digital values may be referred to as software triggers110. The example software application108may include a sensing and control application and/or a signal processing application. The example clock circuitry112ofFIG.1generates periodic pulses at a specific time interval. The periodic pulses, which may be referred to as a clock signal, are used to help determine when to sample an analog signal. The example configurable ADC circuitry114ofFIG.1receives the analog signals from the interface circuitry106and the software triggers110. Upon receiving a software trigger110A, the example sequencer circuitry116instructs the sample and hold circuitry118to sample the analog signal using a set of conversion parameters. In some examples, the set of conversion parameters may be referred to as a conversion configuration. The example A/D conversion circuitry120converts the sampled analog voltage to a digital value using the clock signal and the conversion configuration. Based on input from the example software application108, the example sequencer circuitry116stores the digital value in one of the result registers122. The example sequencer circuitry116determines whether one or more digital values should be moved from the result registers122. If the example sequencer circuitry116determines one or more digital values should be moved, the interrupt circuitry124generates interrupts126. As used herein, an interrupt refers to a request for processor circuitry to interrupt currently executing code and process the stored digital value in a timely manner. The example interrupt circuitry124provides the interrupts126to the DMA circuitry128. The example configurable ADC circuitry114supports A/D conversion in the following states: (a) single channel sensing and control, (b) multi-channel sensing and control, (c) single channel signal processing, or (d) multi-channel signal processing. The example configurable ADC circuitry114may include additional functionality not illustrated inFIG.1for simplicity. The example configurable ADC circuitry114is explored further inFIG.4. The example DMA circuitry128ofFIG.1responds to interrupts126by initiating transfers of A/D conversion results from the example configurable ADC circuitry114to main memory130. The example DMA circuitry128performs the transfer on a communication bus that may be utilized by other hardware functionality not illustrated inFIG.1. In some examples, the example DMA circuitry128may be referred to as a DMA controller. The main memory130stores the A/D conversion results and provides the results to the example software application108. The main memory130may be implemented by any type of RAM, including but not limited to Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The example computer circuitry100ofFIG.1implements an example software application108that accesses information from analog signals using the example configurable ADC circuitry114. The example configurable ADC circuitry114supports both sensing and control applications and signal processing applications when previous solutions fail to do so. FIG.2is an example timing diagram for sensing and control applications.FIG.2includes an analog signal from the physical medium102A, software triggers110A-110C, and interrupts126A-126C. The illustrative example ofFIG.2may be implemented by a compute device that includes at least the example configurable ADC circuitry114, processor circuitry, and main memory. The analog signal from the physical medium102A is any signal that contains data used by a sensing and control application. For example, the example analog signal ofFIG.2may describe the ambient temperature of a room over an amount of time. The software triggers110A-110C ofFIG.2represent instances when a sensing and control application requests a digital value from the analog signal. The sensing and control application may request a digital value to gather data about a device or environment. When the example configurable ADC circuitry114receives a software trigger110A, the A/D conversion circuitry120produces a digital value that is stored in one of the result registers122. Once the value is stored, the example interrupt circuitry124generates an interrupt126A. This interrupt causes the example DMA circuitry128to transfer the digital value to main memory130. The example DMA circuitry128may transfer data from a variety of hardware components. In some examples, all DMA transfers throughout a compute device may share a single communication bus. The illustrative example ofFIG.2shows that an ADC circuit may generate an interrupt126A-126C each time a software trigger110is received. This is achievable because sensing and control applications send software triggers110to the example configurable ADC circuitry114at relatively low frequencies (i.e., in the magnitude of thousands of conversions per second). As a result, a compute device may determine that an amount of DMA bus utilization attributable to a sensing and control application does not prohibit further bus utilization from other resources. FIG.3is an example timing diagram for signal processing applications.FIG.3includes an analog signal from the physical medium102B, software triggers110A-110L, and interrupts126A-126C. The illustrative example ofFIG.3may be implemented by a compute device that includes at least the example configurable ADC circuitry114, processor circuitry, and main memory. The analog signal from the physical medium102B is any signal that contains data used by a signal processing application. For example, the example analog signal ofFIG.3may represent audio data of a person speaking. To access the information in the signal302, the signal processing application sends software triggers110A-110L to the example configurable ADC circuitry114. As a result, the A/D conversion circuitry120performs an A/D conversion for each of the software triggers110-110L. In contrast to sensing and control applications, signal processing applications requires A/D conversions at a relatively high frequency (i.e., millions of conversions per second). If an ADC circuit were to generate an interrupt and trigger a DMA transfer after each A/D conversion for a signal processing application, a compute device may determine that an amount of DMA bus utilization attributable to the sensing and control application prohibits further bus utilization from other resources. To prevent this, the example configurable ADC circuitry114stores multiple results in the result registers122. The example interrupt circuitry124may then generate an interrupt126A after the example sequencer circuitry116determines a threshold number of digital values are stored in the result registers122. When an interrupt126A is generated, the DMA circuitry128may move any A/D conversion results currently in the result registers122to main memory. The results may be stored in and taken from the result registers122using a FIFO technique. The use of a FIFO technique to store and access multiple A/D conversion results inFIG.3ensures the number of interrupts126A-126C is smaller than the number of software triggers110A-110L sent by a signal processing application. In doing so, the example configurable ADC circuitry114is able to generate A/D conversion results at a high frequency as required by a signal processing application while also minimizing the DMA bus utilization attributable to the sensing and control application. FIG.4is a block diagram of example configurable ADC circuitry114to convert analog signals into digital values.FIG.4includes example multiplexer circuitry402, example sample and hold circuitry118, example A/D conversion circuitry120, example clock pre-scaler circuitry408, example sample control circuitry410, example software trigger110A, example sequencer circuitry116, an example conversion mode414, an example FIFO mode416, an example read pointer417, example memory control registers418, an example write pointer419example result registers122, example virtual address mapper circuitry424, and example interrupt circuitry124. The example multiplexer circuitry402ofFIG.4receives analog signals from the interface circuitry106. The example multiplexer circuitry402provides at least one of the analog signals to the sample and hold circuitry118based on a channel select signal. The example sample and hold circuitry118ofFIG.4samples the analog signal and holds the sampled voltage for a pre-determined time interval. The sample and hold circuitry118provides the sampled voltage to A/D conversion circuitry120. The sample and hold circuitry118samples the analog circuitry based on a sample configuration and a software trigger. The example A/D conversion circuitry120ofFIG.4receives the sampled analog voltage from the sample and hold circuitry118and converts it into a digital bit. The example A/D conversion circuitry120may group n conversion results together to produce a n-bit digital value, where n is an integer. The clock pre-scaler circuitry408receives a signal of periodic signals from the clock circuitry112and scales the pulses. To scale the received signal, the clock pre-scaler circuitry408may divide the frequency of the received signal into a pre-determined number of scaled pulse signals. The clock pre-scaler circuitry408provides the scaled pulses to the sample control circuitry410. For example, the clock pre-scaler circuitry408may receive a signal at 40 Mega Hertz (MHz) from the clock circuitry112and divide the signal by 4. In such an example, the clock pre-scaler circuitry provides a 10 MHz scaled pulse signal to the sample control circuitry410. The sample control circuitry410receives the scaled pulse signal from the clock pre-scaler circuitry408. The sample control circuitry410may receive a software trigger110A from the example software application108. In response to receiving the software trigger110A, the sample control circuitry410provides the software trigger110A to the sequencer circuitry116based on timing from the scaled pulse signal. In other examples, the sample control circuitry410may receive an event trigger from the interface circuitry106, where an event trigger is a request to perform an A/D conversion in response to an event caused by an external device. Events caused by external devices include but are not limited to keystrokes, mouse movement, etc. The example sequencer circuitry116ofFIG.4receives the software trigger110A from the sample control circuitry410and the scaled pulse signal from the clock pre-scaler circuitry408. The example sequencer circuitry116also receives a conversion mode414and a FIFO mode416from the example software application108. The conversion mode414may be in a repeat single channel state or a repeat multiple channel state. The FIFO mode416may be in a signal processing state or a sensing and control state. In some examples, the signal processing state may be referred to as a single transfer state. Similarly, in some examples, the sensing and control state may be referred to as a multiple transfer state. The example configurable ADC circuitry114may operate in either the signal processing state or the sensing and control state. The conversion mode414and FIFO mode416are explored further inFIGS.5-11. The example sequencer circuitry116uses the conversion mode414and a read pointer417to access a conversion configuration from a register in the memory control registers418. As used herein, a conversion configuration refers to a set of parameters that describe how an A/D conversion should be performed. Example parameters within a conversion configuration include but are not limited to which of the analog signals to select, threshold voltage values to compare against the analog sample voltage, sample period, etc. The example sequencer circuitry116initiates an A/D conversion based on the conversion configuration. For example, the A/D conversion circuitry120provides a channel select signal to the multiplexer circuitry402, a software trigger to the sample and hold circuitry118, a start conversion signal to the A/D conversion circuitry120, and an end conversion signal to the A/D conversion circuitry120. The example result registers122ofFIG.4stores the n-bit digital values that are generated by the A/D conversion circuitry120. The example sequencer circuitry116determines which of the result registers122should hold a given n-bit digital value based on the FIFO mode416and a write pointer419. The virtual address mapper circuitry424assigns virtual address to the result registers122. The DMA circuitry128then uses the virtual address to identify the result registers122and transfers results to main memory130. In some example implementations, the DMA circuitry128is unable to support wrap-around addressing. In wrap-around addressing, the DMA circuitry128accesses a group of results that wrap around a section of memory. For example, suppose ten virtual addresses are numbered 0-9 for simplicity. A DMA circuitry128in wrap around mode may access five values from the example virtual addresses, where the first three values are stored in virtual addresses 7, 8, 9, and the last two values are stored in virtual addresses 0 and 1. Wrap-around addressing techniques may be used when the FIFO mode416is in the signal processing state. To support DMA circuitry128that does not implement wrap around addressing, the virtual address mapper circuitry424maps each of the result registers122to a single virtual address when the FIFO mode416is in the signal processing state. As a result, all DMA circuitry128implementations, regardless of wrap-around addressing support, may refer to the single virtual address to access any of the result registers122. When the FIFO mode416is in the sensing and control state, the virtual address mapper circuitry424may map the result registers122to multiple virtual addresses. The example interrupt circuitry124ofFIG.4generates interrupts based on a received signal from the sequencer circuitry116. In some examples, the interrupt circuitry124generates an interrupt that causes the DMA circuitry128to move data from the result registers122into main memory130. In other examples, the interrupt circuitry124may generate an interrupt for other purposes such as reporting a status to processor circuitry. The example configurable ADC circuitry114includes sequencer circuitry116that determines when the example software application108wants an A/D conversion, what conversion configuration should be used to perform the A/D conversion, and where the resulting digital value should be stored. In doing so, the result registers122can be configured such that each new digital value triggers a DMA transfer, as used when the example software application108is categorized as sensing and control. Alternatively, the result registers122can configured to store results in a FIFO technique such that a single DMA transfer moves multiple digital values to main memory130, as used when the example software application108is categorized as signal processing. The example sequencer circuitry116is explored further inFIGS.5-11. FIG.5is an illustrative example of a repeat single channel conversion state and a sensing and control state.FIG.5includes the software trigger110A, sequencer circuitry116, read pointer417, write pointer419, memory control registers418, and result registers122. The example software trigger110A ofFIG.5indicates that an A/D conversion has been requested. InFIG.5, the software trigger110A is provided by the example software application108. The example read pointer417points to one of the memory control registers418. When a software trigger110A is received, the example sequencer circuitry116initiates an A/D conversion based on the conversion configuration stored in the register identified by the current value of the read pointer417. In the illustrative example ofFIG.5, the read pointer417identifies Memory Control register3(MEMCTL3). The conversion mode414indicates how the read pointer417should be updated after the example sequencer circuitry116initiates the A/D conversion. In the illustrative example ofFIG.5, the conversion mode414is in the repeat single channel state. This means that the read pointer417should remain pointing at MEMCTL3, which holds the conversion configuration for both the current and the next A/D conversion. In some examples, the conversion mode414also indicates how many A/D conversions should be performed in response to a single software trigger. In some examples, a single A/D conversion occurs for a single software trigger. In other examples, the conversion mode414indicates a different value of A/D conversions should occur for a single software trigger110A. In such examples, if the conversion mode414is in the repeat single channel state as illustrated inFIG.5, each of the x A/D conversions occur using the conversion configuration stored in MEMCTL3, where x is the different value. The example write pointer419points to one of the result registers122. After an A/D conversion occurs, the sequencer circuitry116stores the results at the current value of the write pointer419. The FIFO mode416provided by the example software application108indicates how the write pointer419should be updated after an A/D conversion. In the illustrative example ofFIG.5, the FIFO mode416is in the sensing and control state. In the sensing and control state, the index of the write pointer419matches the index of the read pointer417. As used herein, an index of a pointer (i.e., the read pointer417or write pointer419) refers to a numerical value that represents which register the pointer currently identifies. Therefore, inFIG.5, the write pointer419remains at MEMRES3 after one or more A/D conversions because the read pointer417remains at MEMCTL3 after the one or more A/D conversions. The use of the sensing and control state as illustrated inFIG.5results in more than one A/D conversion results being stored in the same register. As a result, the example sequencer circuitry116may cause the interrupt circuitry124to generate an interrupt as soon as first results as from a first A/D conversion are stored in one of the result registers122. In response to the interrupt, the DMA circuitry128may move the first results into main memory130. This immediate transfer of digital values prevents the first results from being overwritten by second results from a second A/D conversion that are stored in the same register. As a result, the non-FIO state may be beneficial for an example software application108that expects A/D conversion results as soon as they are generated and requests a relatively low number of A/D conversions, such as sensing and control applications. FIG.6is an illustrative of a repeat multiple channels conversion state and a sensing and control state.FIG.6includes a software trigger110A, sequencer circuitry116, read pointer417, write pointer419, memory control registers418, and result registers122. LikeFIG.5, the example software trigger110A ofFIG.6indicates that an A/D conversion has been requested. InFIG.6, the software trigger110A is provided by the example software application108. The example read pointer417points to one of the memory control registers418. When a software trigger110A is received, the example sequencer circuitry116initiates an A/D conversion based on the conversion configuration stored in the register identified by the current value of the read pointer417. In the illustrative example ofFIG.6, the read pointer417begins at MEMCTL1. In the illustrative example ofFIG.6, the conversion mode414is in the repeat multiple channel state. In the repeat multiple channel state, the example software application108provides a start address and end address. The example sequencer circuitry116uses the conversion configuration from the start address (i.e., MEMCTL1 inFIG.6) for a first A/D conversion and then updates the read pointer417to the next register in the memory control registers418(i.e., MEMCTL2). Upon receiving a request for a second A/D conversion, the example sequencer circuitry116uses the conversion configuration from the current read pointer417index (i.e., MEMCTL2) and then updates the read pointer417to the next register (i.e., MEMCTL3). This conversion and update process repeats until the read pointer417identifies the end address (i.e., MEMCTL5 inFIG.5). After an A/D conversion that uses the conversion configuration indicated by the end address, the read pointer417is updated to the start address rather than the next register. The start address and end address may indicate any registers in the result registers122provided the end address comes after the start address numerically. LikeFIG.5, the FIFO mode416ofFIG.6is in the sensing and control state. As a result, after storing an A/D conversion result in a register in the result registers122as indicated by the current write pointer419value, the sequencer circuitry116updates the write pointer419index to match the read pointer417index. Therefore, conversion results using the configuration in MEMCTL1 are stored in MEMRES1, conversion results using the configuration MEMCTL2 are stored in MEMRES2, etc. FIG.5andFIG.6illustrate two different ADC configurations that may be utilized by sensing and control applications. The use of the sensing and control state allows the example software application108to request A/D conversion results from either one or multiple conversion configurations and to receive the results as soon as they are generated. FIG.7is an illustrative example of a repeat single channel conversion state and a signal processing state.FIG.7includes a software trigger110A, sequencer circuitry116, read pointer417, write pointer419, memory control registers418, and result registers122. The example software trigger110A ofFIG.7indicates that an A/D conversion has been requested. InFIG.7, the software trigger110A is provided by the example software application108. The example read pointer417points to one of the memory control registers418. As illustrated inFIG.5, a conversion mode414in the repeat single channel state means that the example sequencer circuitry116may trigger one or more A/D conversions using the same conversion configuration (i.e., MEMCTL3 inFIG.7) without updating the read pointer417. The FIFO mode416provided by the example software application108indicates how the example sequencer circuitry116should update the write pointer419after an A/D conversion. In the illustrative example ofFIG.7, the FIFO mode416is in the signal processing state. In the signal processing state, the write pointer419is not required to match the read pointer417index. Rather, the result registers122are ordered from a first result register to a last result register. As described by FIFO technique, the write pointer419is updated to identify a next result register where a new result should be stored based on the order of the result registers and a current result register where the previous result is stored. For example, inFIG.7, the write pointer419may initially point to the first result register, MEMRES0. In such an example, a first A/D conversion using MEMCTL3 may produce a first digital value that is stored in MEMRES0, and the write pointer419would be updated to identify MEMRES1. A second A/D conversion using MEMCTL3 would produce results stored in MEMRES1, the write pointer419would be updated to identify MEMRES2, etc. This process repeats until the write pointer419reaches the last result register MEMRES7 and wraps back to the first result register MEMRES0. In the signal processing state, the sequencer circuitry116causes the interrupt circuitry124to generate interrupts such that the DMA circuitry128transfers digital values from the result registers122in a group according to the order in which they were stored. The example sequencer circuitry116may determine the number of digital values in a group based on a pre-determined threshold value provided by the example software application108. For example, suppose the pre-determined threshold in the illustrative example ofFIG.7is four registers, and the write pointer419beings at MEMRES0. The sequencer circuitry116would therefore generate an interrupt to cause a single DMA transfer once MEMRES0-MEMRES3 all contain A/D conversion results. After the fourth conversion result is stored in MEMRES3, the sequencer circuitry116updates the write pointer419to identify MEMRES4. This allows additional A/D conversion results to be stored in a second subset of result registers122(e.g., MEMRES4-MEMRES7) while a first DMA transfer moves the conversion results from a first subset of results registers122(e.g., MEMRES0-MEMRES3) into main memory130. Following the first DMA transfer, the example sequencer circuitry116would trigger a second DMA transfer after the next four conversion results are stored in MEMRES4-MEMRES7. The pre-determined threshold value of the signal processing state may be based on how the use of DMA transfers by the example configurable ADC circuitry114affects an overall bus utilization of a computing device. In the foregoing example, the pre-determined threshold referred to four out of eight total result registers122. In some examples, the pre-determined threshold value may refer to a different portion of result registers122. FIG.8is an illustrative example of repeat multiple channel conversion state and a signal processing state.FIG.8includes a software trigger110A, sequencer circuitry116, read pointer417, write pointer419, memory control registers418, and result registers122. The example software trigger110A ofFIG.8indicates that an A/D conversion has been requested. InFIG.8, the software trigger110A is provided by the example software application108. The conversion mode414in the illustrative example ofFIG.8is in the repeat multiple channel state. As described inFIG.6, when in the repeat multiple channel state, the example sequencer circuitry116updates the read pointer417after each A/D conversion such that the read pointer417loops between a start address and an end address within the memory control registers418. The FIFO mode416in the illustrative example ofFIG.8is in the signal processing state. As described inFIG.7, when in the signal processing state, the example sequencer circuitry116updates the write pointer419sequentially and causes the interrupt circuitry124to generate an interrupt after a pre-determined threshold number of result registers have been filled. The number of memory control registers418that are traversed in repeat multiple channels mode may be independent of the pre-determined threshold number of result registers needed to trigger a DMA transfer. For example, inFIG.8, the read pointer417loops between five memory control registers (MEMCTL1-MEMCTL5), but the sequencer circuitry116may trigger a DMA transfer after four of the result registers122contain digital values. FIGS.7and8illustrate how the example configurable ADC circuitry114may be configured to move digital values in to and out of the result registers using a FIFO technique that minimizes the total number of DMA transfers. Such a configuration would be beneficial for an example software application108that performs signal processing and therefore requests A/D conversion results at a relatively high frequency. Furthermore,FIGS.7and8illustrate how an example software application108that performs signal processing may choose to receive multiple conversion results using a single conversion configuration or using multiple conversion configurations. While an example manner of implementing the example configurable ADC circuitry114ofFIG.1is illustrated inFIG.4, one or more of the elements, processes, and/or devices illustrated inFIG.4may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example includes example multiplexer circuitry402, example sample and hold circuitry118, example A/D conversion circuitry, example clock pre-scaler circuitry408, example sample control circuitry410, example sequencer circuitry116, example memory control registers418, example result registers122, example virtual address mapper circuitry424, example interrupt circuitry124and/or, more generally, the example configurable ADC circuitry114ofFIG.4, may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, any of the example multiplexer circuitry402, example sample and hold circuitry118, example A/D conversion circuitry, example clock pre-scaler circuitry408, example sample control circuitry410, example sequencer circuitry116, example memory control registers418, example result registers122, example virtual address mapper circuitry424, example interrupt circuitry124and/or, more generally, the example configurable ADC circuitry114ofFIG.4, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). Further still, the example configurable ADC circuitry114ofFIG.1may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG.4, and/or may include more than one of any or all of the illustrated elements, processes, and devices. Flowcharts representative of example hardware logic circuitry, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the example configurable ADC circuitry114ofFIG.4are shown inFIGS.9-11. The machine readable instructions may be one or more executable programs or portion(s) of an executable program for execution by processor circuitry, such as the processor circuitry1212shown in the example processor platform1200discussed below in connection withFIG.12. The program may be embodied in software stored on one or more non-transitory computer readable storage media such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), or a non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), FLASH memory, an HDD, an SSD, etc.) associated with processor circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed by one or more hardware devices other than the processor circuitry and/or embodied in firmware or dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN)) gateway that may facilitate communication between a server and an endpoint client hardware device). Similarly, the non-transitory computer readable storage media may include one or more mediums located in one or more hardware devices. Further, although the example program is described with reference to the flowcharts illustrated inFIGS.9-11, many other methods of implementing the example configurable ADC circuitry114may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The processor circuitry may be distributed in different network locations and/or local to one or more hardware devices (e.g., a single-core processor (e.g., a single core central processor unit (CPU)), a multi-core processor (e.g., a multi-core CPU), etc.) in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, a CPU and/or a FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings, etc.). The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data or a data structure (e.g., as portions of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of machine executable instructions that implement one or more operations that may together form a program such as that described herein. In another example, the machine readable instructions may be stored in a state in which they may be read by processor circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, machine readable media, as used herein, may include machine readable instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s) when stored or otherwise at rest or in transit. The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc. As mentioned above, the example operations ofFIGS.9-10may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on one or more non-transitory computer and/or machine readable media such as optical storage devices, magnetic storage devices, an HDD, a flash memory, a read-only memory (ROM), a CD, a DVD, a cache, a RAM of any type, a register, and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the terms non-transitory computer readable medium and non-transitory computer readable storage medium are expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media. FIG.9is a flowchart representative of example machine readable instructions and/or example operations900that may be executed and/or instantiated by processor circuitry to perform and store one or more A/D conversions. The machine readable instructions and/or the operations900ofFIG.9begin when the example sequencer circuitry116receives a trigger event. (Block902). InFIG.9, the trigger event is be provided by the example sample control circuitry410in response to a software trigger generated by the example software application108. In other examples, the sample control circuitry410may provide a trigger event in response to an event trigger. The example sequencer circuitry116accesses a conversion configuration (Block904). The example sequencer circuitry116uses the read pointer417index to access the conversion configuration. The read pointer417identifies one of the memory control registers418, where each register contains a conversion configuration. The example configurable ADC circuitry114samples an analog signal based on the conversion configuration. (Block906). Specifically, the multiplexer circuitry402determines which of the analog signals to select based on the conversion configuration, and the sample and hold circuitry118holds the sampled analog voltage for an amount of time based on the conversion configuration. The example A/D conversion circuitry120converts the sampled analog value to a digital value based on the conversion configuration. (Block908). To determine the digital value, the example A/D conversion circuitry120compares the sampled analog voltage to one or more reference voltages provided in the conversion configuration. The example sequencer circuitry116writes the digital value to one of the result registers122. (Block910). Block910is explored further inFIG.10. The example configurable ADC circuitry114conditionally moves one or more digital values to main memory130. (Block912). Block912is explored further inFIG.11. The example sequencer circuitry116determines whether the conversion configuration should be updated (Block914). The sequencer circuitry116makes the determination of block914based on the conversion mode414. If the conversion mode414is in the repeat single channel state, the conversion configuration does not require updating. Conversely, if the conversion mode414is in the repeat multiple channel state, the conversion configuration does require updating. The conversion mode414is provided to the example sequencer circuitry116by the example software application108. If the example sequencer circuitry116determines the conversion configuration should not be updated, the example machine readable instructions and/or operations900proceed to block918. If the example sequencer circuitry116determines the conversion configuration should be updated, the example sequencer circuitry116updates the conversion configuration (Block916). The example sequencer circuitry116updates the conversion configuration by updating the read pointer417index as described inFIGS.6and8. In doing so, the example sequencer circuitry116will access a different conversion configuration whenever the next software trigger110B is received. The operations of block916occur when the conversion mode414is in the repeat multiple channels state. The example sequencer circuitry116updates the read pointer417sequentially until the read pointer417identifies an end address. After the conversion configuration identified by the end address is used to perform an A/D conversion, the sequencer circuitry116updates the read pointer417to identify a start address. In repeat multiple channels mode, the example software application108indicates which of the memory control registers418is used as the start address and which of the memory control registers418is used as the end address. The example sequencer circuitry116determines whether another A/D conversion is requested. (Block918). In some examples, a conversion configuration may indicate that the example sequencer circuitry116should initiate multiple A/D conversions in response to a single trigger event. In other examples, there is a one to one correspondence between trigger events and A/D conversions. In such examples, the example sequencer circuitry116may determine another A/D conversion is requested in response to receiving an additional trigger event. If the example sequencer circuitry116determines that another A/D conversion is requested, the machine readable instructions and/or operations900proceed to block904where the sequencer circuitry116accesses a conversion configuration based on the current value of the read pointer417. If the example sequencer circuitry116determines that another A/D conversion is not requested, the machine readable instructions and/or operations900end. FIG.10is a flowchart representative of example machine readable instructions and/or example operations that may be executed by example processor circuitry to write a digital value to a result register as described inFIG.9. The machine readable instructions and/or operations of block910begin when the sequencer circuitry116determines whether the FIFO mode416is in the signal processing state. (Block1002). The sequencer circuitry116receives the FIFO mode416from the example software application108. If the FIFO mode416is in the sensing and control state (i.e., a ‘no’ is determined at block1002), the sequencer circuitry116determines the write pointer419index to match the read pointer417index. (Block1004). For example, if the read pointer417currently identifies MEMCTL3, then the sequencer circuitry116sets the write pointer419to identify MEMRES3. In some examples, the write pointer419may currently identify MEMRES3 before block910is executed. In such examples, the sequencer circuitry116may verify the write pointer419identifies the same index as the read pointer417. If the FIFO mode416is in the signal processing state, the example sequencer circuitry116updates the write pointer419based on a FIFO technique. (Block1006). For example, the example sequencer circuitry116may update the write pointer419to identify the next register in the result registers122that does not currently contain a digital value. In the signal processing state, the write pointer419index and read pointer417index may identify different numbered registers. The example sequencer circuitry116stores the digital value at the result register corresponding to the write pointer419index. (Block1008). The example machine readable instructions and/or operations900return to block912after block1008. FIG.11is a flowchart representative of example machine readable instructions and/or example operations that may be executed by example processor circuitry to conditionally trigger a DMA transfer as described inFIG.9. The example machine readable instructions and/or operations900of block912begin when the example sequencer circuitry116determines whether the FIFO mode416is in the signal processing state. (Block1102). The example sequencer circuitry116receives the FIFO mode416from the example software application108. If the FIFO mode416is in the sensing and control state (i.e., a ‘no’ is determined at block1102), the example machine readable instructions and/or operations of block912proceed to block1106. If the FIFO mode416is in the signal processing state, the sequencer circuitry116determines whether the number of result registers containing digital values satisfies a threshold. (Block1104). To satisfy the threshold of block1104, the number of result registers122containing digital values may be required to be greater or equal than a pre-determined threshold value. In such examples, the example software application108may provide the pre-determined threshold value to the example sequencer circuitry116. If the sequencer circuitry116determines the number of result registers containing digital values does not satisfy the threshold of block1104, the example machine readable instructions and/or operations900return to block914. If the sequencer circuitry116determines the number of result registers containing digital values does satisfy the threshold of block1104, the example machine readable instructions and/or operations of block912proceed to block1106. The example sequencer circuitry116notifies the DMA circuitry128. (Block1106). The example sequencer circuitry116may notify the DMA circuitry128causing the interrupt circuitry124to generate an interrupt126A. In response to the notification, the example DMA circuitry128moves a number of digital values to main memory130via DMA transfer. (Block1108). The example sequencer circuitry116determines the number of digital values to transfer based on the FIFO mode416. For example, if the FIFO mode416is in the sensing and control state, then the sequencer circuitry116may instruct the DMA circuitry128to transfer a single digital value from the result register identified by the current value of the write pointer419. However, if the FIFO mode416is in the signal processing state, the example sequencer circuitry116may instruct the DMA circuitry128to transfer a number of digital values equal to the pre-determined threshold value of block1104. After block1108, the example machine readable instructions and/or operations900return to block914. FIG.12is a block diagram of an example processor platform1200structured to execute and/or instantiate the machine readable instructions and/or the operations ofFIGS.9-11to implement the example computer circuitry100ofFIG.1. The processor platform1200can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device. The processor platform1200of the illustrated example includes processor circuitry1212. The processor circuitry1212of the illustrated example is hardware. For example, the processor circuitry1212can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry1212may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry1212implements at least the example software application108, example sequencer circuitry116, example interrupt circuitry124, and example virtual address mapper circuitry424. The processor circuitry1212of the illustrated example includes a local memory1213(e.g., a cache, registers, etc.). The processor circuitry1212of the illustrated example is in communication with a main memory including a volatile memory1214and a non-volatile memory1216by a bus1218. The volatile memory1214may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAIVIBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory1216may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory1214,1216,130of the illustrated example is controlled by a memory controller. The processor platform1200of the illustrated example also includes interface circuitry1220. The interface circuitry1220may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface. In the illustrated example, one or more input devices1222are connected to the interface circuitry1220. The input device(s)1222permit(s) a user to enter data and/or commands into the processor circuitry1212. The input device(s)1222can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system. One or more output devices1224are also connected to the interface circuitry1220of the illustrated example. The output device(s)1224can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry1220of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU. The interface circuitry1220of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network1226. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc. The processor platform1200of the illustrated example also includes one or more mass storage devices1228to store software and/or data. Examples of such mass storage devices1228include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and/or SSDs, and DVD drives. The machine executable instructions1232, which may be implemented by the machine readable instructions ofFIGS.9-11, may be stored in the mass storage device1228, in the volatile memory1214, in the non-volatile memory1216, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD. From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that provide a single set of registers that can both provide conversion results as soon as they are generated (as requested by control and sensing applications) and buffer high frequency conversion results (as requested by signal processing applications). Disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by implementing a conversion mode and a FIFO mode to determine where to store results and when to transfer them to memory. Disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device. “Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous. It is noted that this patent claims priority from Indian Patent Application Number 202141043961, which was filed on Sep. 28, 2021, and is hereby incorporated by reference in its entirety. The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent. | 63,429 |
11942963 | DETAILED DESCRIPTION The following describes the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and the features in the embodiments can be combined with each other if no conflict will result. It should be noted that the drawings provided in this disclosure only illustrate the basic concept of the present disclosure in a schematic way, so the drawings only show the components related to the present disclosure. The drawings are not necessarily drawn according to the number, shape and size of the components in actual implementation; during the actual implementation, the type, quantity and proportion of each component can be changed as needed, and the components' layout may also be more complicated. Referring toFIG.1, which is a schematic diagram of a traditional gate-voltage-bootstrap sampling switch based on NMOS transistors. When the input signal VIN changes, a gate-voltage-bootstrap circuit generates a bootstrap voltage to keep its input and output voltages at a constant value, thus enabling a sampling NMOS transistor M9to obtain a constant gate-source voltage difference, thereby improving the linearity of a sampling NMOS transistor M1. When the sampling switch is in a charge storage state, a sampling clock signal CLK is 1, a PMOS transistor M4is off, and the sampling switch M9is off. A NMOS transistor M7conducts one terminal of a bootstrap capacitor Cp to ground, and a charge pump consisting of C1, C2, M1and M2makes a NMOS transistor M2conduct. At this time, the voltage difference between the two terminals of the bootstrap capacitor Cp is VDD. When the sampling switch is in a sampling state, the sampling clock signal CLK becomes 0, the PMOS transistor M4is on, the NMOS transistor M8is on, the NMOS transistor M7is off, one terminal of the bootstrap capacitor Cp is connected to the input signal VIN, and the charge pump consisting of C1, C2, M1and M2turns the NMOS transistor M2off. At this time, the voltage difference between the two terminals of the bootstrap capacitor Cp is VIN+VDD, thus keeping the gate-source voltage difference of the sampling switch M9as VDD. If the charge sharing effect of the parasitic capacitor is ignored, theoretically the gate voltage of M1is VIN+vdd; then, when M1is on, its gate-source voltage difference is kept as vdd, and its conducting resistance can be expressed as Rboot,n=1μnCox(WL)n(vdd-Vthn) μnis the carrier mobility, Coxis the MOS transistor's gate capacitance; (W/L) is the MOS transistor's aspect ratio; Vthnis the MOS transistor's threshold voltage. As can be seen from the above equation, due to the presence of the NMOS transistor M1's gate-voltage-bootstrap circuit, the conducting resistance of the NMOS sampling switch does not vary with the input signal VIN and is a fixed value; therefore, the sampling switch M1can provide a good linearity. However, the above traditional bootstrap sampling switch has a problem that a charge pump circuit is introduced to generate a higher voltage to control the on and off of the M2transistor. The charge pump circuit requires two capacitors C1and C2to generate a high voltage, which makes the sampling switch larger and more costly due to the presence of the capacitors. A schematic diagram and a timing diagram of a follow-hold switch with a traditional structure is shown inFIG.2. When the sampling control signal CLK is 0 and its inverted signal CLKN is 1, the follow-and-hold switch is in a holding state. At this time, the switch M1is off and the switch M2is on, and the voltage on sampling capacitor Cp is the voltage obtained by sampling. When the sampling control signal CLK is 1 and its inverted signal CLKN is 0, the follow-hold switch is in a following state. At this time, the switch M1is on and the switch M2is off, and the source voltage V1of the switch M1follows the change of the input signal VIN. However, one disadvantage of this structure is that both switches M1and M2are controlled by standard clocks, and the gate-source voltage differences of the switches vary with the input signal VIN, which results in poor linearity. Based on the aforementioned bootstrap structure and the traditional follow-and-hold switch structure, another traditional follow-and-hold switch structure[1] was proposed, whose circuit and timing diagrams are shown inFIG.3. When the sampling control signal CLK is 0 and its inverted signal CLKN is 1, the follow-and-hold switch is in a holding state. At this time, switches M1and M3are off, switches M2and M4are on, and the voltage on the sampling capacitor Cp is the voltage obtained by sampling. When the sampling control signal CLK is 1 and its inverted signal CLKN is 0, the follow-and-hold switch is in a following state. At this time, switches M1and M3are on, switches M2and M4are off, and the output voltage of switch M3follows the input signal VIN. Problems of the above traditional structure follow-and-hold switch include: 1) When the follow-and-hold switch is in a holding state, the switch bootstrap capacitor Cb is pulled down to 0. For a fully differential structure, this means lower plates of bootstrap capacitors Cb in both differential sampling switches are pulled down to 0, instead of an input common-mode voltage, which causes the linearity of the sampling switches to degrade. 2) In the traditional structure, one terminal of the sampling capacitor Cp is connected to the sampling switch M2and the other terminal of the sampling capacitor Cp is grounded, which causes the charge to be injected into the upper plate of the sampling capacitor Cp when the sampling switch is turned off, thus affecting the sampling accuracy. 3) In order to improve the linearity of the sampling switch, a charge pump is usually used to boost the gate voltage of the sampling switch, which will required multiple capacitors as previously described, increasing the area of the board. Referring toFIG.4, the present disclosure provides a follow-hold switch circuit, including a follower, a sampling sub-circuit, a bootstrap-control sub-circuit, and a sampling-switch-control sub-circuit. In one embodiment, by means of a clock signal and an inverted clock signal, the circuit as a whole is controlled to be in a following state or a holding state. In one embodiment, the follower includes a first MOS transistor M1and a constant current source Ib. The sampling sub-circuit includes a second MOS transistor M2, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sampling capacitor Cp; wherein M2acts as a sampling switch. The sampling-switch-control sub-circuit includes: a sixth MOS transistor M6, a third MOS transistor M3, and a thirteenth MOS transistor M13. In one embodiment, the bootstrap-control sub-circuit includes a switch module and a bootstrap module. In one embodiment, the switch module includes the seventh to twelfth MOS transistors, numbered M7to M12in that order. In one embodiment, the bootstrap module may include a bootstrap capacitor Cb. The sub-circuits are connected as follows: The first MOS transistor M1has a drain connected to a supply voltage VDD, a gate connected to one terminal of the sampling capacitor Cp and a drain of the fifth MOS transistor M5, respectively, and a source connected to a positive terminal of the constant current source Ib; a negative terminal of the constant current source Ib is grounded. A source of the fourth MOS transistor M4and a source of the fifth MOS transistor M5are connected to a common-mode voltage Vcm; a gate of the fourth MOS transistor M4is connected to an inverted clock signal CLKN, and a gate of the fifth MOS transistor M5is connected to a clock signal CLK. The other terminal of the sampling capacitor Cp is connected to a drain of the second MOS transistor M2and a drain of the fourth MOS transistor M4, respectively; a gate of the second MOS transistor M2is connected to a drain of the twelfth MOS transistor M12and a drain of the thirteenth MOS transistor M13, respectively. A gate of the thirteenth MOS transistor M13is connected to a gate of the sixth MOS transistor M6and a gate of the third MOS transistor M3, respectively, and to the inverted clock signal CLKN; a source of the thirteenth MOS transistor M13, a source of the third MOS transistor M3, and a source of the sixth MOS transistor M6are connected together and then connected to the common mode voltage Vcm; a drain of the sixth MOS transistor M6is connected to a gate of the seventh MOS transistor M7and a drain of the eleventh MOS transistor M11; a drain of the third MOS transistor M3is connected to one terminal of the bootstrap capacitor Cb, a source of the second MOS transistor M2, a drain of the seventh MOS transistor M7, and a source of the eighth MOS transistor M8; the other terminal of the bootstrap capacitor Cb is connected to a source of the tenth MOS transistor M10, a source of the eleventh MOS transistor M11, and a source of the twelfth MOS transistor M12. A source of the seventh MOS transistor M7is connected to the input voltage VIN; the other terminal of the bootstrap capacitor Cb is connected to a source of the tenth MOS transistor M10, a source of the eleventh MOS transistor M11, and a source of the twelfth MOS transistor M12respectively; a drain of the ninth MOS transistor M9is connected to a gate of the eleventh MOS transistor M11, a gate of the twelfth MOS transistor M12, and a drain of the eighth MOS transistor M8; a gate of the ninth MOS transistor M9is connected to a gate of the eighth MOS transistor M8and connected to the clock signal CLK; a source of the ninth MOS transistor M9is connected to a drain of the tenth MOS transistor M10and connected to the supply voltage VDD; a gate of the tenth MOS transistor M10is connected to the clock signal CLK. In one embodiment, MOS transistors M1to M8are NMOS transistors, and MOS transistors M9to M12are PMOS transistors. When the sampling clock signal CLK is 0 and the inverted clock signal CLKN is 1, the follow-hold structure is in a holding state, and its equivalent circuit is shown inFIG.5; the switches shown inFIG.5(except M1) are all off, and the switches that are on has been represented by straight lines. At this time, the voltages on two terminals of the bootstrap capacitor Cb are Vcm and VDD, respectively, the bootstrap capacitor Cb is in a charge storage state, and the gate voltage of M5is the input voltage from the last clock cycle. In the traditional structure, Vc would be grounded at this time, resulting in the drain of M7transistor and the source of M2transistor having zero voltage when the follow-hold structure is in a holding state. Since the traditional follow-hold structure is usually a fully differential structure, the Vc in both differential follow-hold structures is 0 instead of the common-mode voltage, which affects the linearity of the entire follow-hold structure. With the structure of the present disclosure, when the follow-hold structure is in a holding state, Vc in both differential follow-hold structures is the common-mode voltage Vcm, which can significantly improve the linearity of the follow-hold structure. At this time, the voltage difference across the two terminals of the sampling capacitor is Vcm−Vi. When the sampling clock signal CLK is 1 and CLKN is 0, the follow-hold structure is in a following state, and its equivalent circuit is shown inFIG.6; the switches shown inFIG.6(except M1, M2and M7) are off; since M2and M7are on, the drain voltage Vc of M7is equal to VIN; since switch M3is off, the bootstrap capacitor Cb is in a bootstrap state, and Va is bootstrapped to VIN+VDD, and therefore the gate voltages of switches M2and M7are bootstrapped to VIN+VDD, improving the linearity of the sampling switches M2and M7. At this time, the voltage difference across the two terminals of the sampling capacitor is VIN-Vcm. The advantage of this structure is that, the traditional bootstrap sampling switch needs at least three capacitors to achieve voltage bootstrapping, but this structure only needs one capacitor to achieve voltage bootstrapping, which obviously reduces the area of the circuit and lowers the cost of the circuit. In summary, from the law of conservation of charge, it follows that Vi=2Vcm−VIN when the follow-hold structure is in a holding state; and since the circuit is a fully differential circuit, the sampling voltage of the differential follow-hold switch can be expressed as VIP−VIN, thus, achieving following and sampling. In one embodiment, in order to further verify the above advantages of the present disclosure, the aforementioned two structures (the traditional structure [1] and the structure of the present disclosure) are designed under 40 nm CMOS process, and the same input/output transistors and load transistor dimensions are used for both structures. In the present disclosure, the bootstrap capacitor Cb is has a capacitance of 0.1 pF, the sampling capacitor Cp has a capacitance of 0.2 pF, the supply voltage VDD is 1.2V, and the input bias voltage is 0.6V. Comparison of simulation results of the spurious-free dynamic ranges (SFDR) of two sampling switch structures with the SFDR varying with the frequency of an input signal is shown inFIG.7, where the horizontal coordinate is the frequency of the input signal and the vertical coordinate is the SFDR. FromFIG.7, it can be seen that the present disclosure improves the SFDR by about 10 dB when the input frequency is low and by about 8 dB when the input frequency is high, compared with the traditional structure [1]. Comparison of simulation results of the signal noise distortion ratio (SNDR) of two sampling switch structures with the SNDR varying with the frequency of an input signal is shown inFIG.8, where the horizontal coordinate is the frequency of the input signal and the vertical coordinate is SNDR. FromFIG.8, it can be seen that the present disclosure improves the SNDR by about 9.8 dB when the amplitude of the input signal is low and by about 11 dB when the amplitude of the input signal is high compared with the traditional structure [1]. In summary, a follow-hold switch circuit is provided by the present disclosure, in which a bootstrap capacitor Cb is introduced to achieve gate voltage bootstrapping of a sampling switch transistor, which obviously simplifies the circuit structure, reduces the circuit area and lowers the cost of the circuit compared with the traditional structure; having introduced a sampling switch control structure consisting of M3, M6and M13, when the follow-hold switch in a holding state, reset voltages at the Vc points in both differential switches are equal to a common mode voltage Vcm, which significantly improves the linearity of the sampling switch, compared to the traditional structure where the reset voltage at Vc is 0. A sampling network consisting of switches M4, M5, and a sampling capacitor Cp ensures that, when the sampling process ends, M5is off first, M2is then off, and finally M4is on, so that any charge injection caused by the disconnection of M2does not affect the accuracy of the entire sampling switch. Therefore, the present disclosure effectively overcomes various shortcomings of the prior art and has a high value for industrial application. The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present disclosure, but are not used to limit the present disclosure. Any person skilled in the art may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concepts disclosed by the present disclosure should still be covered by the attached claims of the present disclosure. | 16,282 |
11942964 | To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. Elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION Aspects of the present disclosure provide apparatus, methods, processing systems, and computer program products for encoding (and/or decoding) for new radio (NR) access technology (e.g., 5G radio access). NR may refer to radios configured to operate according to a new air interface or fixed transport layer. NR may include support for enhanced mobile broadband (eMBB) service targeting wide bandwidth (e.g., 80 MHz and beyond), millimeter wave (mmW) service targeting high carrier frequency (e.g., 60 GHz), massive machine type communications (mMTC) service targeting non-backward compatible MTC techniques, and/or mission critical (MiCr) service targeting ultra-reliable low-latency communications (URLLC) service. These services may include latency and reliability requirements for a variety of uses, timing requirements, and other design considerations. NR may use low-density parity-check (LDPC) coding and/or polar codes. Aspects of the present disclosure provide techniques and apparatus for compactly describing LDPC code structure. In aspects, a single base graph or parity check matrix (PCM) can be stored for a set of lifting sizes (sometimes referred to as a family of liftings or a family of lifted LDPC codes). The PCM may correspond to one of the liftings for the set of liftings (e.g., the smallest or largest lifting) and the other members of the family can be generated based on a stored PCM using an operation (e.g., such as a floor operation or a modulo operation). In aspects, the same PCM can be used for members of the family of codes. In aspects, PCM for different families of codes can be generated based on the lifting values associated with one family. Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof. The techniques described herein may be used for various wireless communication networks such as Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, Single-Carrier FDMA (SC-FDMA) networks, etc. The terms “networks” and “systems” are often used interchangeably. A CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), CDMA2000, etc. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). CDMA2000 covers IS-2000, IS-95, and IS-856 standards. A TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA network may implement a radio technology such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Flash-OFDM®, etc. UTRA, E-UTRA, and GSM are part of Universal Mobile Telecommunication System (UMTS). 3GPP LTE and LTE-Advanced (LTE-A) are releases of UMTS that use E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). CDMA2000 is described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). NR is an emerging wireless communications technology under development in conjunction with the 5G Technology Forum (5GTF). These communications networks are merely listed as examples of networks in which the techniques described in this disclosure may be applied; however, this disclosure is not limited to the above-described communications network. For clarity, while aspects may be described herein using terminology commonly associated with 3G and/or 4G or LTE wireless technologies, aspects of the present disclosure can be applied in other generation-based communication systems, such as 5G and later, including NR technologies. An Example Wireless Communication System FIG.1illustrates an example communications network100in which aspects of the present disclosure may be performed. Wireless communications network100may be a new radio (NR) or 5G network. Wireless communications network100may include a transmitting device such as a user equipment (UE)120or a base station (BS)110. The transmitting device may perform encoding according to aspects described herein using lifted LDPC codes that may be compactly described (e.g., determined/generated/stored), and a receiving device (e.g., a UE120or a BS110) can perform corresponding decoding operations. For example, the transmitting device can select at least one lifting size value for generating a group of lifted LDPC codes comprising copies of a base LDPC code defined by a base matrix having a first number of base variable nodes and a second number of base check nodes. The lifting size value is selected from a range of values. The transmitting device can generate the base matrix based on a lifting value of a set of lifting values associated with the selected lifting size value and generate a matrix for a different lifting size value in the group based on the base matrix. As illustrated inFIG.1, wireless communications network100may include a number of BSs110and other network entities. ABS may be a station that communicates with UEs. Each BS110may provide communication coverage for a particular geographic area. In 3GPP, the term “cell” can refer to a coverage area of a Node B and/or a Node B subsystem serving this coverage area, depending on the context in which the term is used. In NR systems, the term “cell” and gNB, Node B, 5G NB, AP, NR BS, NR BS, TRP, etc., may be interchangeable. In some examples, a cell may not necessarily be stationary, and the geographic area of the cell may move according to the location of a mobile BS. In some examples, the BSs may be interconnected to one another and/or to one or more other BSs or network nodes (not shown) in wireless communications network100through various types of backhaul interfaces such as a direct physical connection, a virtual network, or the like using any suitable transport network. In general, any number of wireless networks may be deployed in a given geographic area. Each wireless network may support a particular radio access technology (RAT) and may operate on one or more frequencies. A RAT may also be referred to as a radio technology, an air interface, etc. A frequency may also be referred to as a carrier, a frequency channel, etc. Each frequency may support a single RAT in a given geographic area in order to avoid interference between wireless networks of different RATs. In some cases, NR or 5G RAT networks may be deployed. A BS may provide communication coverage for a macro cell, a pico cell, a femto cell, and/or other types of cell. A macro cell may cover a relatively large geographic area (e.g., several kilometers in radius) and may allow unrestricted access by UEs with service subscription. A pico cell may cover a relatively small geographic area and may allow unrestricted access by UEs with service subscription. A femto cell may cover a relatively small geographic area (e.g., a home) and may allow restricted access by UEs having association with the femto cell (e.g., UEs in a Closed Subscriber Group (CSG), UEs for users in the home, etc.). ABS for a macro cell may be referred to as a macro BS. ABS for a pico cell may be referred to as a pico BS. A BS for a femto cell may be referred to as a femto BS or a home BS. In the example shown inFIG.1, BS110a, BS110b, and BS110cmay be macro BSs for the macro cell102a, macro cell102b, and macro cell102c, respectively. BS110xmay be a pico BS for pico cell102x. BS110yand BS110zmay be femto BS for the femto cell102yand femto cell102z, respectively. ABS may support one or multiple (e.g., three) cells. Wireless communications network100may also include relay stations. A relay station is a station that receives a transmission of data and/or other information from an upstream station (e.g., a BS110or a UE120) and sends a transmission of the data and/or other information to a downstream station (e.g., a UE120or a BS110). A relay station may also be a UE that relays transmissions for other UEs. In the example shown inFIG.1, relay station110rmay communicate with BS110aand UE120rin order to facilitate communication between BS110aand UE120r. A relay station may also be referred to as a relay, a relay eNB, etc. Wireless communications network100may be a heterogeneous network that includes BSs of different types, for example, macro BS, pico BS, femto BS, relays, etc. These different types of BSs may have different transmit power levels, different coverage areas, and different impact on interference in the wireless communications network100. For example, a macro BS may have a high transmit power level (e.g., 20 Watts) whereas pico BS, femto BS, and relays may have a lower transmit power level (e.g., 1 Watt). Wireless communications network100may support synchronous or asynchronous operation. For synchronous operation, the BSs may have similar frame timing, and transmissions from different BSs may be approximately aligned in time. For asynchronous operation, the BSs may have different frame timing, and transmissions from different BSs may not be aligned in time. The techniques described herein may be used for both synchronous and asynchronous operation. Network controller130may couple to a set of BSs and provide coordination and control for these BSs. Network controller130may communicate with BSs110via a backhaul. BSs110may also communicate with one another, e.g., directly or indirectly via wireless or wireline backhaul. UEs120(e.g., UE120x, UE120y, etc.) may be dispersed throughout wireless communications network100, and each UE may be stationary or mobile. A UE may also be referred to as a mobile station, a terminal, an access terminal, a subscriber unit, a station, a Customer Premises Equipment (CPE), a cellular phone, a smart phone, a personal digital assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless phone, a wireless local loop (WLL) station, a tablet, a camera, a gaming device, a netbook, a smartbook, an ultrabook, a medical device or medical equipment, a biometric sensor/device, a wearable device such as a smart watch, smart clothing, smart glasses, a smart wrist band, smart jewelry (e.g., a smart ring, a smart bracelet, etc.), an entertainment device (e.g., a music device, a video device, a satellite radio, etc.), a vehicular component or sensor, a smart meter/sensor, industrial manufacturing equipment, a global positioning system device, or any other suitable device that is configured to communicate via a wireless or wired medium. Some UEs may be considered evolved or machine-type communication (MTC) devices or evolved MTC (eMTC) devices. MTC and eMTC UEs include, for example, robots, drones, remote devices, sensors, meters, monitors, location tags, etc., that may communicate with a BS, another device (e.g., remote device), or some other entity. A wireless node may provide, for example, connectivity for or to a network (e.g., a wide area network such as Internet or a cellular network) via a wired or wireless communication link. Some UEs may be considered Internet-of-Things (IoT) devices. InFIG.1, a solid line with double arrows indicates desired transmissions between a UE and a serving BS, which is a BS designated to serve the UE on the downlink and/or uplink. A finely dashed line with double arrows indicates interfering transmissions between a UE and a BS. Certain wireless networks (e.g., LTE) utilize orthogonal frequency division multiplexing (OFDM) on the downlink and single-carrier frequency division multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM partition the system bandwidth into multiple (K) orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers (K) may be dependent on the system bandwidth. For example, the spacing of the subcarriers may be 15 kHz and the minimum resource allocation (called a “resource block” (RB)) may be 12 subcarriers (i.e., 180 kHz). Consequently, the nominal Fast Fourier Transform (FFT) size may be equal to 128, 256, 512, 1024 or 2048 for system bandwidth of 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz, or 20 MHz, respectively. The system bandwidth may also be partitioned into subbands. For example, a subband may cover 1.08 MHz (i.e., 6 RBs), and there may be 1, 2, 4, 8 or 16 subbands for system bandwidth of 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz, or 20 MHz, respectively. NR may utilize OFDM with a CP on uplink and downlink and include support for half-duplex operation using TDD. A single component carrier bandwidth of 100 MHz may be supported. NR RBs may span 12 subcarriers with a subcarrier bandwidth of 75 kHz over a 0.1 ms duration. Each radio frame may consist of 50 subframes with a length of 10 ms. Consequently, each subframe may have a length of 0.2 ms. Each subframe may indicate a link direction (i.e., downlink or uplink) for data transmission and the link direction for each subframe may be dynamically switched. Each subframe may include DL/UL data as well as DL/UL control data. UL and DL subframes for NR may be as described in more detail below with respect toFIGS.6and7. Beamforming may be supported and beam direction may be dynamically configured. MIMO transmissions with precoding may also be supported. MIMO configurations in the DL may support up to 8 transmit antennas with multi-layer DL transmissions up to 8 streams and up to 2 streams per UE. Multi-layer transmissions with up to 2 streams per UE may be supported. Aggregation of multiple cells may be supported with up to 8 serving cells. Alternatively, NR may support a different air interface, other than an OFDM-based. In some examples, access to the air interface may be scheduled. For example, a scheduling entity (e.g., a BS110or UE120) allocates resources for communication among some or all devices and equipment within its service area or cell. Within the present disclosure, as discussed further below, the scheduling entity may be responsible for scheduling, assigning, reconfiguring, and releasing resources for one or more subordinate entities. That is, for scheduled communication, subordinate entities utilize resources allocated by the scheduling entity. BSs are not the only entities that may function as a scheduling entity. That is, in some examples, a UE may function as a scheduling entity, scheduling resources for one or more subordinate entities (e.g., one or more other UEs). In this example, the UE is functioning as a scheduling entity, and other UEs utilize resources scheduled by the UE for wireless communication. A UE may function as a scheduling entity in a peer-to-peer (P2P) network, and/or in a mesh network. In a mesh network example, UEs may optionally communicate directly with one another in addition to communicating with the scheduling entity. Thus, in a wireless communication network with a scheduled access to time-frequency resources and having a cellular configuration, a P2P configuration, and a mesh configuration, a scheduling entity and one or more subordinate entities may communicate utilizing the scheduled resources. The NR radio access network (RAN) may include one or more central units (CU) and distributed units (DUs). A NR BS (e.g., a gNB, a 5G NB, a NB, a 5G NB, a TRP, an AP) may correspond to one or multiple BSs. NR cells can be configured as access cells (ACells) or data only cells (DCells). DCells may be cells used for carrier aggregation or dual connectivity, but not used for initial access, cell selection/reselection, or handover. FIG.2illustrates an example logical architecture of a distributed RAN200, which may be implemented in wireless communications system100illustrated inFIG.1. 5G access node (AN)206may include access node controller (ANC)202. ANC202may be a CU of distributed RAN200. A backhaul interface to next generation core network (NG-CN)204may terminate at ANC202. A backhaul interface to neighboring next generation access nodes (NG-ANs) may terminate at ANC202. ANC202may include one or more TRPs208. TRPs208comprise DUs. TRPs208may be connected to one ANC (ANC202) or more than one ANC (not illustrated). For example, for RAN sharing, radio as a service (RaaS), and service specific AND deployments, the TRP may be connected to more than one ANC202. A TRP208may include one or more antenna ports. TRPs208may be configured to individually (e.g., dynamic selection) or jointly (e.g., joint transmission) serve traffic to a UE (e.g., a UE120). Example logical architecture of the distributed RAN200may be used to illustrate fronthaul definition. The logical architecture may support fronthauling solutions across different deployment types. For example, the logical architecture may be based on transmit network capabilities (e.g., bandwidth, latency, and/or jitter). The logical architecture may share features and/or components with LTE. NG-AN210may support dual connectivity with NR. NG-AN210may share a common fronthaul for LTE and NR. The logical architecture may enable cooperation between and among TRPs208. For example, cooperation may be pre-configured within a TRP208and/or across TRPs208via ANC202. There may be no inter-TRP interface. The logical architecture for distributed RAN200may include a dynamic configuration of split logical functions. As will be described in more detail with reference toFIG.5, the Radio Resource Control (RRC) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, Medium Access Control (MAC) layer, and a Physical (PHY) layers may be placed at the DU (e.g., a TRP208) or the CU (e.g., ANC202). FIG.3illustrates an example physical architecture of a distributed RAN300, according to aspects of the present disclosure. As shown inFIG.3, distributed RAN300includes centralized core network unit (C-CU)302, centralized RAN unit (C-RU)304, and DU306. C-CU302may host core network functions. C-CU302may be centrally deployed. C-CU302functionality may be offloaded (e.g., to advanced wireless services (AWS)), in an effort to handle peak capacity. C-RU304may host one or more ANC functions. Optionally, C-RU304may host core network functions locally. C-RU304may have a distributed deployment. C-RU304may be located near an edge the network. DU306may host one or more TRPs (edge node (EN), an edge unit (EU), a radio head (RH), a smart radio head (SRH), or the like). DU306may be located at edges of the network with radio frequency (RF) functionality. FIG.4illustrates example components of the BS110and the UE120illustrated inFIG.1, which may be used to implement aspects of the present disclosure for high performance, flexible, and compact LDPC coding. One or more of the components of BS110and UE120illustrated inFIG.4may be used to practice aspects of the present disclosure. For example, antenna(s)452a-454r, Demodulator(s)/Modulator(s)454a-454r, TX MIMO processor466, Receive Processor458, Transmit Processor464, and/or Controller/Processor480of UE120and/or antenna(s)434a434t, Demodulator(s)/Modulator(s)432a-434t, TX MIMO Processors430, Transmit Processor420, Receive Processor438, and/or Controller/Processor440of BS110may be used to perform the operations1300-1600described herein and illustrated with reference toFIGS.13-16, respectively. For a restricted association scenario, BS110may be macro BS110cinFIG.1, and UE120may be UE120y. BS110may also be a BS of some other type. BS110may be equipped with antennas434athrough434tand UE120may be equipped with antennas452athrough452r. At BS110, transmit processor420may receive data from data source412and control information from controller/processor440. The control information may be for the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid ARQ Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), or other control channel or signal. The data may be for the Physical Downlink Shared Channel (PDSCH), or other data channel or signal. Transmit processor420may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. For example, transmit processor420may encode the information bits using LPDC code designs discussed in greater detail below. Transmit processor420may also generate reference symbols, for example, for the primary synchronization signal (PSS), secondary synchronization signal (SSS), and cell-specific reference signal (CRS). Transmit (TX) multiple-input multiple-output (MIMO) processor430may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs)432athrough432t. Each modulator432may process a respective output symbol stream (e.g., for OFDM, etc.) to obtain an output sample stream. Each modulator432may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from modulators432athrough432tmay be transmitted via antennas434athrough434t, respectively. At UE120, antennas452athrough452rmay receive the downlink signals from BS110and may provide received signals to the demodulators (DEMODs)454athrough454r, respectively. Each demodulator454may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator454may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector456may obtain received symbols from all the demodulators454athrough454r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. Receive processor458may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE120to a data sink460, and provide decoded control information to controller/processor480. On the uplink, at UE120, transmit processor464may receive and process data (e.g., for the Physical Uplink Shared Channel (PUSCH) or other data channel or signal) from data source462and control information (e.g., for the Physical Uplink Control Channel (PUCCH) or other control channel or signal) from controller/processor480. Transmit processor464may also generate reference symbols for a reference signal. The symbols from transmit processor464may be precoded by TX MIMO processor466if applicable, further processed by demodulators454athrough454r(e.g., for SC-FDM, etc.), and transmitted to BS110. At BS110, the uplink signals from the UE120may be received by antennas434, processed by modulators432, detected by MIMO detector436if applicable, and further processed by receive processor438to obtain decoded data and control information sent by UE120. Receive processor438may provide the decoded data to data sink439and the decoded control information to controller/processor440. Memory442may store data and program codes for BS110and memory482may store data and program codes for UE120. Scheduler444may schedule UEs for data transmission on the downlink and/or uplink. FIG.5illustrates a diagram500showing examples for implementing a communications protocol stack per aspects of the present disclosure. The illustrated communications protocol stacks may be implemented by devices operating in a in a 5G system (e.g., a system that supports uplink-based mobility). Diagram500illustrates a communications protocol stack including RRC layer510, PDCP layer515, RLC layer520, MAC layer525, and PHY layer530. In an example, the layers of a protocol stack may be implemented as separate modules of software, portions of a processor or ASIC, portions of non-collocated devices connected by a communications link, or various combinations thereof. Collocated and non-collocated implementations may be used, for example, in a protocol stack for a network access device (e.g., ANs, CUs, and/or DUs) or a UE. A first option505-ashows a split implementation of a protocol stack, in which implementation of the protocol stack is split between a centralized network access device (e.g., ANC202) and distributed network access device (e.g., DU208). In the first option505-a, RRC layer510and PDCP layer515may be implemented by the CU, and RLC layer520, MAC layer525, and PHY layer530may be implemented by the DU. In various examples, the CU and the DU may be collocated or non-collocated. The first option505-amay be useful in a macro cell, micro cell, or pico cell deployment. A second option505-bshows a unified implementation of a protocol stack, in which the protocol stack is implemented in a single network access device (e.g., access node (AN), NR BS, a NR NBa network node (NN), TRP, gNB, etc.). In the second option, RRC layer510, PDCP layer515, RLC layer520, MAC layer525, and PHY layer530may each be implemented by the AN. The second option505-bmay be useful in a femto cell deployment. Regardless of whether a network access device implements part or all of a protocol stack, a UE may implement the entire protocol stack (e.g., RRC layer510, PDCP layer515, RLC layer520, MAC layer525, and PHY layer530). FIG.6is a diagram showing an example of a DL-centric subframe600. The DL-centric subframe600may include control portion602. Control portion602may exist in the initial or beginning portion of DL-centric subframe600. Control portion602may include various scheduling information and/or control information corresponding to various portions of DL-centric subframe600. In some configurations, control portion602may be a physical DL control channel (PDCCH), as shown inFIG.6. DL-centric subframe600may also include DL data portion604. DL data portion604may be referred to as the payload of DL-centric subframe600. DL data portion604may include the communication resources utilized to communicate DL data from the scheduling entity (e.g., UE or BS) to the subordinate entity (e.g., UE). In some configurations, DL data portion604may be a physical DL shared channel (PDSCH). DL-centric subframe600may also include common UL portion606. Common UL portion606may be referred to as an UL burst, a common UL burst, and/or various other suitable terms. Common UL portion606may include feedback information corresponding to various other portions of DL-centric subframe600. For example, common UL portion606may include feedback information corresponding to control portion602. Non-limiting examples of feedback information may include an acknowledgment (ACK) signal, a negative acknowledgment (NACK) signal, a HARQ indicator, and/or various other suitable types of information. Common UL portion606may additionally or alternatively include information, such as information pertaining to random access channel (RACH) procedures, scheduling requests (SRs), and various other suitable types of information. As illustrated inFIG.6, the end of DL data portion604may be separated in time from the beginning of common UL portion606. This time separation may be referred to as a gap, a guard period, a guard interval, and/or various other suitable terms. This separation provides time for the switchover from DL communication (e.g., reception operation by the subordinate entity (e.g., UE)) to UL communication (e.g., transmission by the subordinate entity (e.g., UE)). The foregoing is merely one example of a DL-centric subframe and alternative structures having similar features may exist without necessarily deviating from the aspects described herein. FIG.7is a diagram showing an example of an UL-centric subframe700. UL-centric subframe700may include control portion702. Control portion702may exist in the initial or beginning portion of UL-centric subframe700. Control portion702inFIG.7may be similar to control portion602described above with reference toFIG.6. UL-centric subframe700may also include UL data portion704. UL data portion704may be referred to as the payload of UL-centric subframe700. UL data portion704may refer to the communication resources utilized to communicate UL data from the subordinate entity (e.g., UE) to the scheduling entity (e.g., UE or BS). In some configurations, control portion702may be a PDCCH. As illustrated inFIG.7, the end of control portion702may be separated in time from the beginning of UL data portion704. This time separation may be referred to as a gap, guard period, guard interval, and/or various other suitable terms. This separation provides time for the switchover from DL communication (e.g., reception operation by the scheduling entity) to UL communication (e.g., transmission by the scheduling entity). UL-centric subframe700may also include common UL portion706. Common UL portion706inFIG.7may be similar to the common UL portion606described above with reference toFIG.6. Common UL portion706may additionally or alternatively include information pertaining to channel quality indicator (CQI), sounding reference signals (SRSs), and various other suitable types of information. The foregoing is merely one example of an UL-centric subframe and alternative structures having similar features may exist without necessarily deviating from the aspects described herein. In some circumstances, two or more subordinate entities (e.g., UEs) may communicate with each other using sidelink signals. Real-world applications of such sidelink communications may include public safety, proximity services, UE-to-network relaying, vehicle-to-vehicle (V2V) communications, Internet-of-Everything (IoE) communications, IoT communications, mission-critical mesh, and/or various other suitable applications. Generally, a sidelink signal may refer to a signal communicated from one subordinate entity (e.g., UE1) to another subordinate entity (e.g., UE2) without relaying that communication through the scheduling entity (e.g., UE or BS), even though the scheduling entity may be utilized for scheduling and/or control purposes. In some examples, the sidelink signals may be communicated using a licensed spectrum (unlike wireless local area networks (WLAN), which typically use an unlicensed spectrum). A UE may operate in various radio resource configurations, including a configuration associated with transmitting pilots using a dedicated set of resources (e.g., a radio resource control (RRC) dedicated state, etc.) or a configuration associated with transmitting pilots using a common set of resources (e.g., an RRC common state, etc.). When operating in the RRC dedicated state, the UE may select a dedicated set of resources for transmitting a pilot signal to a network. When operating in the RRC common state, the UE may select a common set of resources for transmitting a pilot signal to the network. In either case, a pilot signal transmitted by the UE may be received by one or more network access devices, such as an AN, or a DU, or portions thereof. Each receiving network access device may be configured to receive and measure pilot signals transmitted on the common set of resources, and also receive and measure pilot signals transmitted on dedicated sets of resources allocated to the UEs for which the network access device is a member of a monitoring set of network access devices for the UE. One or more of the receiving network access devices, or a CU to which receiving network access device(s) transmit the measurements of the pilot signals, may use the measurements to identify serving cells for the UEs, or to initiate a change of serving cell for one or more of the UEs. Example Error Correction Coding Many communications systems use error-correcting codes. Error correcting codes generally compensate for the intrinsic unreliability of information transfer (e.g., over the air medium) in these systems by introducing redundancy into the data stream. Low-density parity-check (LDPC) codes are one type of error correcting codes which use an iterative coding system. Gallager codes are an example of “regular” LDPC codes. Regular LDPC codes are linear block codes in which most of the elements of its parity check matrix H are ‘0’. LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs”). In a bipartite graph, a set of variable nodes corresponds to bits of a code word (e.g., information bits or systematic bits), and a set of check nodes correspond to a set of parity-check constraints that define the code. Edges in the graph connect variable nodes to check nodes. Thus, the nodes of the graph are separated into two distinctive sets and with edges connecting nodes of two different types, variable and check. Graphs as used in LDPC coding may be characterized in a variety of manners. A lifted code is created by copying a bipartite base graph (G) (or a protograph), a number of times, Z. The number of times is referred to herein as the lifting, lifting size, or lifting size value. A variable node and a check node are considered “neighbors” if they are connected by an “edge” (i.e., the line connecting the variable node and the check node) in the graph. In addition, for each edge (e) of the bipartite base graph (G), a permutation (generally an integer value associated with the edge permutation that is represented by k and referred to as the lifting value) is applied to the Z copies of edge (e) to interconnect the Z copies of G. A bit sequence having a one-to-one association with the variable node sequence is a valid code word if and only if, for each check node, the bits associated with all neighboring variable nodes sum to 0 modulo 2 (i.e., they include an even number of 1's). The resulting LDPC code may be quasi-cyclic (QC) if the permutations (liftings values) used are cyclic. FIGS.8-8Ashow graphical and matrix representations, respectively, of an example LDPC code, in accordance with certain aspects of the present disclosure. For example,FIG.8shows a bipartite graph800representing an example LDPC code. Bipartite graph800includes a set of five variable nodes810(represented by circles) connected to four check nodes820(represented by squares). Edges in bipartite graph800connect variable nodes810to check nodes820(the edges are represented by the lines connecting variable nodes810to check nodes820). Bipartite graph800consists of |V|=5 variable nodes and |C|=4 check nodes, connected by |E|=12 edges. Bipartite graph800may be represented by a simplified adjacency matrix, which may also be known as a parity check matrix (PCM).FIG.8Ashows a matrix representation800A of bipartite graph800. Matrix representation800A includes a PCM H and a code word vector x, where x1-x5represent bits of the code word x. H is used for determining whether a received signal was normally decoded. H has C rows corresponding to j check nodes and V columns corresponding to i variable nodes (i.e., a demodulated symbol), where the rows represent the equations and the columns represents the bits of the code word. InFIG.8A, matrix H has four rows and five columns corresponding to four check nodes and five variable nodes, respectively. If a j-th check node is connected to an i-th variable node by an edge (i.e., the two nodes are neighbors), then there is a 1 in the i-th column and in the j-th row of the parity check matrix H. That is, the intersection of an i-th row and a j-th column contains a “1” where an edge joins the corresponding vertices and a “0” where there is no edge. The code word vector x represents a valid code word if and only if Hx=0, for example, if for each constraint node, the bits neighboring the constraint, via their association with variable nodes, sum to 0 modulo 2 (i.e., they comprise an even number of 1′a). Thus, if the code word is received correctly, then Hx=0 (mod 2). When the product of a coded received signal and the PCM H becomes ‘0’, this signifies that no error has occurred. The number of demodulated symbols or variable nodes is the LDPC code length. The number of non-zero elements in a row (column) is defined as the row (column) weight d(c)d(v). The degree of a node refers to the number of edges connected to that node. For example, as shown inFIG.8, the variable node801has three degrees of connectivity, with edges connected to check nodes811,812, and813. Variable node802has three degrees of connectivity, with edges connected to check nodes811,813, and814. Variable node803has two degrees of connectivity, with edges connected to check nodes811and814. Variable node804has two degrees of connectivity, with edges connected to check nodes812and814. And variable node805has two degrees of connectivity, with edges connected to check nodes812and813. This feature is illustrated in the matrix H shown inFIG.8Awhere the number of edges incident to a variable node810is equal to the number of 1's in the corresponding column and is called the variable node degree d(v). Similarly, the number of edges connected with a check node820is equal to the number of ones in a corresponding row and is called the check node degree d(c). For example, as shown inFIG.8A, the first column in the matrix H corresponds to the variable node801and the corresponding entries in the column (1, 1, 1, 0) indicates the edge connections to the check nodes811,812, and813, while the 0 indicates that there is not an edge to check node814. The entries in the second, third, fourth, and fourth columns of H represent the edge connections of the variable nodes802,803,804, and805, respectively, to the check nodes. A regular graph or a regular code is one for which all variable nodes have the same degree and all constraint nodes have the same degree. On the other hand, an irregular code has constraint nodes and/or variable nodes of differing degrees. For example, some variable nodes may be of degree 4, others of degree 3, and still others of degree 2. “Lifting” enables LDPC codes to be implemented using parallel encoding and/or decoding implementations while also reducing the complexity typically associated with large LDPC codes. Lifting helps enable efficient parallelization of LDPC decoders while still having a relatively compact description. More specifically, lifting is a technique for generating a relatively large LDPC code from multiple copies of a smaller base code. For example, a lifted LDPC code may be generated by producing Z of parallel copies of the base graph (e.g., protograph) and then interconnecting the parallel copies through permutations of edge bundles of each copy of the base graph. The base graph defines the (macro) structure of the code and consists of a number (K) of information bit columns and a number (N) of code bit columns. Lifting the base graph a number of liftings Z results in a final block length of KZ. Thus, a larger graph can be obtained by a “copy and permute” operation where multiple copies of the base graph are made and connected to form a single lifted graph. For the multiple copies, like edges are a set of copies of single base edge, are permutated and connected to form a connected graph Z times larger than the base graph. FIG.9is a bipartite graph illustrating liftings of three copies of the bipartite graph800ofFIG.8. Three copies may be interconnected by permuting like edges among the copies. If the permutations are restricted to cyclic permutations, then the resulting bipartite graph900corresponds to a quasi-cyclic LDPC with lifting Z=3. The original graph800from which three copies were made is referred to herein as the base graph. To obtain graphs of different sizes, “copy and permute” operation can be applied to the base graph. A corresponding PCM of the lifted graph can be constructed from the parity check matrix of the base graph by replacing each entry in the base parity check matrix with a Z×Z matrix. The “0” entries (those having no base edges) are replaced with the 0 matrix and the 1 entries (indicating a base edge) are replaced with a Z×Z permutation matrix. In the case of cyclic liftings, the permutations are cyclic permutations. A cyclically lifted LDPC code can also be interpreted as a code over the ring of binary polynomials modulo xz+1. In this interpretation, a binary polynomial, (x)=b0+b1x+b2x2+ . . . +bz−1xx−1may be associated to each variable node in the base graph. The binary vector (b0, b1, b2, . . . , bz−1) corresponds to the bits associated to Z corresponding variable nodes in the lifted graph, that is, Z copies of a single base variable node. A cyclic permutation by k (referred to as a lifting value associated to the edges in the graph) of the binary vector is achieved by multiplying the corresponding binary polynomial by xkwhere multiplication is taken modulo xz+1. A degree d parity check in the base graph can be interpreted as a linear constraint on the neighboring binary polynomials B1(x), . . . , Bd(x), written as xk1B1(x)+xk2B2(x)+ . . . +xkdBd(x)=0xk1B1(x)+xk2B2(x)+ . . . +xkdBd(x)=0, the values, k1, . . . , kdare the cyclic lifting values associated to the corresponding edges. This resulting equation is equivalent to the Z parity checks in the cyclically lifted Tanner graph corresponding to the single associated parity check in the base graph. Thus, the parity check matrix for the lifted graph can be expressed using the matrix for the base graph in which 1 entries are replaced with monomials of the form xkand 0 entries are lifted as 0, but now the 0 is interpreted as the 0 binary polynomial modulo xz+1. Such a matrix may be written by giving the value k in place of xk. In this case the 0 polynomial is sometimes represented as “−1” and sometimes as another character in order to distinguish it from Typically, a square submatrix of the parity check matrix represents the parity bits of the code. The complementary columns correspond to information bits that, at the time of encoding, are set equal to the information bits to be encoded. The encoding may be achieved by solving for the variables in the aforementioned square submatrix in order to satisfy the parity check equations. The parity check matrix H may be partitioned into two parts M and N where M is the square portion. Thus, encoding reduces to solving Mc=s=Nd where c and d comprise x. In the case of quasi-cyclic codes, or cyclically lifted codes, the above algebra can be interpreted as being over the ring of binary polynomials modulo xz+1. In the case of the 802.11 LDPC codes, which are quasi-cyclic, the encoding submatrix M has an integer representation as shown inFIG.10. A received LDPC code word can be decoded to produce a reconstructed version of the original code word. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits may be used by decoders to detect and correct bit errors. LDPC decoder(s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may be repeated several times. For example, each variable node810in the graph800may initially be provided with a “soft bit” (e.g., representing the received bit of the code word) that indicates an estimate of the associated bit's value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel. LDPC codes designed for high speed applications often use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with higher code rates (e.g., the ratio of the message length to the codeword length) tend to have relatively fewer parity checks. If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges (e.g., the variable node may have a “double edge”). If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges. Having a base variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems. A double edge in a base LDPC code may trigger parallel reading of the same soft bit value memory location twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. Eliminating double edges in the LDPC code helps to avoid this extra complexity. LDPC code designs based on cyclic lifting can be interpreted, as codes over the ring of polynomials modulo may be binary polynomials modulo xz−1, where Z is the lifting size (e.g., the size of the cycle in the quasi-cyclic code). Thus encoding such codes can often be interpreted as an algebraic operation in this ring. In the definition of standard irregular LDPC code ensembles (degree distributions) all edges in the Tanner graph representation may be statistically interchangeable. In other words, there exists a single statistical equivalence class of edges. A more detailed discussion of lifted LDPC codes may be found, for example, in the book titled, “Modern Coding Theory,” published Mar. 17, 2008, by Tom Richardson and Ruediger Urbanke. For multi-edge LDPC codes, multiple equivalence classes of edges may be possible. While in the standard irregular LDPC ensemble definition, nodes in the graph (both variable and constraint) are specified by their degree, i.e., the number of edges they are connected to, in the multi-edge type setting an edge degree is a vector; it specifies the number of edges connected to the node from each edge equivalence class (type) independently. A multi-edge type ensemble is comprised of a finite number of edge types. The degree type of a constraint node is a vector of (non-negative) integers; the i-th entry of this vector records the number of sockets of the i-th type connected to such a node. This vector may be referred to as an edge degree. The degree type of a variable node has two parts although it can be viewed as a vector of (non-negative) integers. The first part relates to the received distribution and will be termed the received degree and the second part specifies the edge degree. The edge degree plays the same role as for constraint nodes. Edges are typed as they pair sockets of the same type. The constraint that sockets must pair with sockets of like type characterizes the multi-edge type concept. In a multi-edge type description, different node types can have different received distributions (e.g., the associated bits may go through different channels). Puncturing is the act of removing bits from a codeword to yield a shorter codeword. Thus, punctured variable nodes correspond to codeword bits that are not actually transmitted. Puncturing a variable node in an LDPC code creates a shortened code (e.g. due to the removal of a bit), while also effectively removing a check node. Specifically, for a matrix representation of an LDPC, code, including bits to be punctured, where the variable node to be punctured has a degree of one (such a representation may be possible through row combining provided the code is proper), puncturing the variable node removes the associated bit from the code and effectively removes its single neighboring check node from the graph. As a result, the number of check nodes in the graph is reduced by one. FIG.11is a simplified block diagram illustrating an encoder, in accordance with certain aspects of the present disclosure.FIG.11is a simplified block diagram1100illustrating a portion of radio frequency (RF) modem1150that may be configured to provide a signal including an encoded message for wireless transmission. In one example, convolutional encoder1102in a BS110(or a LTE120on the reverse path) receives message1120for transmission. Message1120may contain data and/or encoded voice or other content directed to the receiving device. Encoder1102encodes the message using a suitable modulation and coding scheme (MCS), typically selected based on a configuration defined by BS110or another network entity. Encoded bitstream1122produced by encoder1102may then be selectively punctured by puncturing module1104, which may be a separate device or component, or which may be integrated with encoder1102. Puncturing module1104may determine that bitstream1122should be punctured prior to transmission, or transmitted without puncturing. The decision to puncture bitstream1122is typically made based on network conditions, network configuration, RAN defined preferences and/or for other reasons. Bitstream1122may be punctured according to puncture pattern1112and used to encode message1120. Puncturing module1104provides output1124to mapper1106that generates a sequence of Tx symbols1126that are modulated, amplified and otherwise processed by Tx chain1108to produce an RF signal1128for transmission through antenna1110. Output1124of puncturing module1104may be the unpunctured bitstream1122or a punctured version of the bitstream1122, according to whether modem portion1150is configured to puncture the bitstream1122. In one example, parity and/or other error correction bits may be punctured in output1124of encoder1102in order to transmit message1120within a limited bandwidth of the RF channel. In another example, the bitstream may be punctured to reduce the power needed to transmit message1120, to avoid interference, or for other network-related reasons. These punctured code word bits are not transmitted. The decoders and decoding algorithms used to decode LDPC codewords operate by exchanging messages within the graph along the edges and updating these messages by performing computations at the nodes based on the incoming messages. Each variable node in the graph is initially provided with a soft bit, termed a received value, that indicates an estimate of the associated bit's value as determined by observations from, for example, the communications channel. Ideally, the estimates for separate bits are statistically independent. This ideal may be violated in practice. A received word is comprised of a collection of received values. FIG.12is a simplified block diagram illustrating a decoder, in accordance with certain aspects of the present disclosure.FIG.12is a simplified schematic1200illustrating a portion of a RF modem1250that may be configured to receive and decode a wirelessly transmitted signal including a punctured encoded message. The punctured code word bits may be treated as erased. For example, the log-likelihood ratios (LLRs) of the punctured nodes may be set to 0 at initialization. De-puncturing may also include deshortening of shortened bits. These shortened bits are not included in a transmission and, at the receiver/decoder, shortened bits are treated as known bits. In various examples, modem1250receiving the signal may reside at the UE, at the BS, or at any other suitable apparatus or means for carrying out the described functions. Antenna1202provides an RE signal1220to a receiver. RF chain1204processes and demodulates RF signal1220and may provide a sequence of symbols1222to demapper1226, which produces a bitstream1224representative of the encoded message. Demapper1206may provide a depunctured bitstream1224. In one example, demapper1206may include a depuncturing module that can be configured to insert null values at locations in the bitstream at which punctured bits were deleted by the transmitter. The depuncturing module may be used when the puncture pattern1210used to produce the punctured bitstream at the transmitter is known. Puncture pattern1210can be used to identify LLRs1228that may be ignored during decoding of bitstream1224by convolutional decoder1208. The LLRs may be associated with a set of depunctured bit locations in the bitstream1224. Accordingly, decoder1208may produce decoded message1226with reduced processing overhead by ignoring the identified LLRs1228. The LDPC decoder may include a plurality of processing elements to perform the parity check or variable node operations in parallel. For example, when processing a code word with lifting size Z, the LDPC decoder may utilize a number (Z) of processing elements to perform parity check operations on all edges of a lifted graph, concurrently. Processing efficiency of decoder1208may be improved by configuring decoder1208to ignore LLRs1228that correspond to punctured bits in a message transmitted in a punctured bitstream1222. The punctured bitstream1222may have been punctured according to a puncturing scheme that defines certain bits to be removed from an encoded message. In one example, certain parity or other error-correction bits may be removed. A puncturing pattern may be expressed in a puncturing matrix or table that identifies the location of bits to be punctured in each message. A puncturing scheme may be selected to reduce processing overhead used to decode the message1226while maintaining compliance with data rates on the communication channel and/or with transmission power limitations set by the network. A resultant punctured bitstream typically exhibits the error-correcting characteristics of a high rate error-correction code, but with less redundancy. Accordingly, puncturing may be effectively employed to reduce processing overhead at the decoder1208in the receiver when channel conditions produce a relatively high signal to noise ratio (SNR). At the receiver, the same decoder used for decoding non-punctured bitstreams can typically be used for decoding punctured bitstreams, regardless of how many bits have been punctured. In conventional receivers, the LLR information is typically de-punctured before decoding is attempted by filling LLRs for punctured states or positions (de-punctured LLRs) with 0's. The decoder may disregard de-punctured LLRs that effectively carry no information based, at least in part, on which bits are punctured. The decoder may treat shortened bits as known bits (e.g., set to 0). Example: Compactly Described Lifted Ldpc Code Features Certain systems (e.g., 802.11n, 802.11ad, WiMAX, ATSC, etc.) may use a multi-edge (ME) type low-density parity-check (LDPC) code structure. Multi-edge type LDPC codes may have advantages over the standard irregular LDPC codes. The ME framework may provide a framework for design of high-performance LDPC codes by using state nodes. The multi-edge type LDPC code structure may provide many more degrees of freedom than the standard irregular LDPC codes, which can be exploited to design codes with excellent performance, low encoding/decoding complexity, and/or other desirable properties. ME codes may have an accumulate chain of degree 2 parity-bits which make the code systematic and, thus, easy to encode. ME type LDPC codes may appear in the form of protograph based LDPC codes, in which the ME type LDPC codes are formed from a base parity-check matrix (PCM). As described above, the protograph and PCMs are used to represent an (n,k) LDPC codes. The PCM defines the base structure or the edge-types in the code. As described above, LDPC codes can be lifted by taking Z (size of the lift) copies of the base PCM and assigning random permutations (according to integer lifting values k) to each edge bundle to interconnect the Z copies and obtain the final PCM. The final PCM has a blocklength Z times the size of the base PCM. Typically, the permutation used is a cyclic permutation (e.g., using circulant matrices to obtain the final PCM). The final PCM can be represented by replacing the non-zero entries in the base PCM by integers up to the size Z−1. The integer represents the cyclic shift (by that integer value) associated to the lifted bundle of edges in the lifted code structure. In some cases, a range of blocklengths may be transmitted. In this case, different values of Z can be used for the same base graph to achieve different blocklengths (since the blocklength is equal to Z times the length of the base PCM). To obtain different code rates, different PCMs and/or different permutation (lifting values) can be used, for example, for a same lifting size Z. As an example, in the 802.11n standard the base PCM has codeblock length equal to 24 and the lifting sizes are given by Z=27, 54, 81. This gives codeblock lengths of 648, 1296 and 1944, respectively (e.g., by multiplying 24*27, 24*54, and 24*81, respectively). In the example of the 802.11n standard approach, a unique PCM is defined for each code rate and each blocklength. In 802.11n, there are four code rate points, thus, the number of defined PCMs is twelve (e.g., one PCM for each combination of the 4 code rates×3 codeblock lengths). In this case, when the number of blocklengths and code rate is large (e.g., as typically is the case in long term evolution (LTE)), describing (e.g., defining/generating/determining/storing) a different PCM for each pair of code rate and blocklength can lead to a large microcode to describe the PCMs (e.g., a large number of bits needed to store the different PCMs). Accordingly, techniques for a compact description of PCMs for large numbers of blocklengths and code rates, while maintaining high performance, are desirable. A technique for generating lifted LDPC codes (e.g., lifted ME LDPC codes) is provided herein, which lends itself to a compact description and provides finely granular blocklength scaling. FIG.13illustrates example operations1300for wireless communication, in accordance with certain aspects of the present disclosure. Operations1300may be performed, for example, by a transmitting device (e.g., UE120or BS110). Operations1300begin, at1302, by selecting a lifting size value Z (e.g., leader) and a first set of lifting values for generating a first lifted LDPC code (e.g., a multi-edge LDPC code). The lifting size value may be selected to achieve a target blocklength or range of blocklengths. At1304, the transmitting device generates the first lifted LDPC code by applying the first set of lifting values to interconnect edges in Z copies of a base PCM having a first number of base variable nodes and a second number of base check nodes to obtain a first lifted PCM corresponding to the first lifted LDPC code (an edge is a connection between a variable node and a check node). At1306, the transmitting device determines a second set of lifting values for generating a second lifted PCM corresponding to a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values. At1308, the transmitting device encodes a set of information bits based on at least one of: the first lifted LDPC code or the second lifted LDPC code to produce a code word. At1310, the transmitting device transmits the code word via a wireless medium. According to certain aspects, the matrix for the different lifting size value in the group is generated based on the base matrix by performing an operation involving the different lifting size value and an integer value associated with an edge in the base matrix (e.g., associated with a permutation of an entry in the base matrix), such as a modulo operations or a floor operation. According to certain aspects, a plurality of lifting size values (e.g., leaders) can be selected (e.g., families of a same code rate). A PCM can be generated for each of the selected lifting size values and members in the associated groups (e.g., families or equivalent classes) can be generated based on the PCM for their respective leader. In aspects, the transmitting device can store only the generated matrices (e.g., PCMs) that are based on the maximum lifting values (from which the PCMs for the other members in the family can be generated). Lifted LDPC codes can be described by assigning to each edge of the PCM a number (e.g., an integer) which may be less than the size of the lifting Z. That entry can be replaced with a circulant matrix obtained by cyclically shifting (e.g., to the right), the identity matrix of size Z×Z, by that number. Thus, PCMs can be given by a matrix of the size of the base PCM with integer entries corresponding to the cyclic liftings. According to certain aspects, a set of lifts can be defined as {a1, a2, . . . , ak}×2j, 0≤i≤m, where k is number of families or equivalent classes (e.g., associated with a same code rate), ajis family leader (e.g., a positive integer), and m is a maximum power of 2 (e.g., the number of members in each family or granularity of blocklengths that can be obtained). The smallest power of 2 may be 0, and the largest power of 2, m, may be a large number (e.g., 10) depending on the maximum desired blocklength. Each family j∈[1:k] can be described (e.g., generated) by its leader as and its power of 2 up to the maximum power m. In this case, there are (m+1)k lifting values. As an example, for four families or equivalent classes (k=4), a maximum power of 2 of six (m=6) can be used, where the leaders of the four families can be 16 (a1=16), 20 (a2=20), 24 (a3=24), and 28 (a4=28). In this the example, the lifting values of the four families can be defined (e.g., generated) based on power of 2 of the leader up to maximum power m (6in this example). Thus, the possible values of the lifts for the four families in this example can be given as: Z=16×{1,2,22,23,24,25,26}Z=20×{1,2,22,23,24,25,26}Z=24×{1,2,22,23,24,25,26}Z=28×{1,2,22,23,24,25,26} corresponding, respectively, to: Z=16,32,64128,256,512,1024Z=20,4080,160,320,640,1280Z=24,48,96,192,384,768,1536Z=28,56,112,224,448,896,1792 If independent lift values are used for each lift (e.g., blocklength), then (m+1)k PCMs (e.g., one PCM for each lifting value) are defined for each code rate point. In the example described above, for the four families and maximum power of 6, 28 PCMs (e.g., (6+1)×4=28) are defined. According to certain aspects, instead of defining (e.g., obtaining/generating/determining/storing) a PCM for each lifting value, a single PCM can be used for each family, for example, only the PCM corresponding to the largest lifting in the family (e.g., the leader times the maximum power of 2). For a family j, the PCM can be generated for the largest lifting value aj2m. The other lifting size values in the family include the leader multiplied by the other powers of 2. PCMs for the other members of the family can be obtained based on the PCM for the largest lifting. For example, edges in the PCM for the leader can be associated with a set of lifting values. PCM for the other members in the family of codes can be obtained by performing an operation involving the PCM for the largest lifting size value (e.g., based on the lifting values) and the desired lift size (e.g., the lift size of that family member). The operations may include a modulo with respect to the desired lift size, a floor operation, or other operation. For example, if an edge has a value s (e.g., an integer value) in the PCM (e.g., for the largest lifting size value) of the family j, then the corresponding integer value in the PCM for the desired lifting size value l, l<m, can be given by s mod aj2l. In the example of the floor operation, the corresponding integer value may be found by/floor (s*(desired lifting size value)/(maximum lifting size value)): floor(x)=⌊s*lmaxlift⌋ For each code rate, a PCM can be described for each family which corresponds to the PCM of the largest lift size in that family. Thus, for each code rate point, there are as many PCMs as there are families. In the example described above, for each code rate, four PCMs may be used—one PCM for each of the maximum lifting size value of the four families 1024, 1280, 1536, and 1792, respectively. That is, the PCM described for each family is for the largest lift size. In the case of the family with the leader of 16, an edge in the base graph (e.g., the PCM for the largest lifting size value in the family of 16 is 16*2{circumflex over ( )}6=1024) may be associated with an integer lifting value s of 678 (“s” is the value of the integer which represents the cyclic lift for that particular edge.) Values associated to all edges in the base PCM may be less than the maximum lifting size (1024 in this example). To obtain the integer value corresponding to the same edge in the graph for a different lifting size in the family, the operation s mod Z (e.g., when Z=128 the operation is 678 mod 128=38) can be performed to generate the lifting values for the PCM for that member of the family. Thus, when lifting with the lifting size value Z=128, for that edge, a circulant matrix of size 128×128 may be used, for example, which is the identity matrix (of size 128×128) shifted to the right by 38. Although in this example, a modulo operation is used, in other embodiments, as discussed above, a different operation may be used (e.g., a floor operation or other operation). LDPC codes are often designed so that the decoding graph has few small loops, for example, due to the nature of the iterative decoders whose performance degrades in the presence of small loops. A loop (or cycle) is defined as a closed path with no repeated nodes. This implies it has an even length. Liftings can be chosen to achieve loop properties in the graph. Accordingly, it is desirable to have a scheme for generating LDPC codes for multiple liftings that all have good loop properties (e.g., few, or no, small loops). Decoding LDPC codes to find the most likely original message involves passing probability messages around the graph of an LDCP code. The decoding is usually quickly computed if the graph contains no loops. Unfortunately, strong LDPCs use loops in their graphs. As a result, the LDCP algorithm is iterated repeatedly until it is told to stop or it converges to a solution. The reason is that in a short loop the value of an incorrect bit will propagate back around to itself, effectively reinforcing its belief and resisting efforts of the LDCP algorithm to correct it. However, this effect is diluted with longer loops, and does not affect the decoder's performance as much. Taking the modulo with respect to any arbitrary lift size (e.g., a lift size that does not belong to the family) could lead to generating a PCM that has bad loops/sets, which can lead to error-floors and degradation in performance. Each family j may be designed (e.g., optimized) such that taking the modulo within a family does not cause, or minimizes, the formation of bad loops. For example, the PCM for the lift size aj can be selected (e.g., designed) such that the formation of bad loops is minimized or avoided. The lift of size aj2 can be obtained by considering the PCM obtained in the first step and then further lifted by 2 so that the number of bad loops in the second step are minimized. This continues until the PCM for the largest lift size in the family is generated. Thus, generating a family involves describing the PCM corresponding to the largest lift size in the family by multiplying its leader and its power of 2 up to a maximum number. Next, the lifting values for the remaining liftings in the family are obtained using a modulo operation. According to certain aspects, for each code rate point, the PCM may be extended for an incremental redundancy (IR) hybrid automatic repeat request (HARQ) scheme. For each code rate point (e.g., the first transmission), the extended (IR HARQ) PCM can be described (e.g., generated) for each family corresponding to the largest lift size. Example: Independent Clustering Scheme for Efficiently Lifting LDPC Codes In a wireless communication system (e.g., wireless communications system100), a set of error correcting codes (e.g., LDPC codes) may be used, for example, for various ranges of blocklengths and/or code rates to be used. To increase efficiency in terms of implementation and compactness of description, it is desirable that the set of codes are related. As described above with respect toFIG.9, a base graph or parity check matrix (PCM) (having K information bits-columns and N total transmitted bit-columns) can be copied, and random permutations to each edge bundle to interconnect the copies, to provide a lifted LDPC code. Practical codes use cyclic permutations or circulant permutation matrices to interconnect the copies of the lifted base graph, resulting in quasi-cyclic codes, which may be easier to implement in hardware. In an example, for a lifting value Z, each edge in the base PCM is associated with an integer lifting value k in the range [0, Z−1]. The associated integer represents the cyclic shift of the identity matrix by that integer. A table may be used for the base PCM showing entries for the bit columns and check nodes. Each entry corresponds to the circulant matrix that is the identity matrix cyclically shifted by the integer value associated with an edge between a variable node and a check node. The entry ‘.’ May be used when there is no edge present between a base variable node and a base check node. When the base graph is reused without alteration the code rate (given by K/N) is same for all liftings Z (corresponding to the number of liftings or copies of the base graph). Using different lifting values can provide a set of codes (e.g., a code family) to achieve a range of block lengths (given by KZ). Thus, using different lifting values for the unaltered base graph can achieve a set of codes with a similar code rate but for different block lengths. For different codes rates, different base graphs may be used. To generate/describe a set of codes (e.g., code family) for a range of code rates and/or block lengths, one way to design the code family is to design a different base PCM for each code rate and each lift value. For example, in 802.11n there are four code rates (1/2, 2/3, 3/4 5/6) and three blocklengths (648, 1296, 1944) corresponding to the lift values of (27, 54, 81). There is a unique base PCM of size 24 bit-columns for each “tuple” (i.e., each pair of code rate and lift value) resulting in twelve base PCMs (e.g., for the combinations of code rate and lift value: (1/2, 27), (1/2, 54), (1/2, 81), . . . (5/6, 81)). Thus, for large Z, the set of liftings Z and lifting values k can lead to a large description complexity. Techniques for efficiently describing/generating the set of liftings are desirable. A set of liftings for a single parity matrix may be efficiently described as an increasing series of liftings that are closely spaced to each other in value. This allows liftings to be specified in a narrow range with a common set of bits, allowing for a compact description and good performance. In an example, a transmitter/encoder device (e.g., such as a BS110or a UE120) determines a base matrix that is associated with a cluster of lifting size values. The transmitting device selects a lifting size value, Z, for generating a lifted LDPC code by permutations of edges in the base matrix. The lifting size values in the cluster of lifting size values are within a defined range of each other. The transmitting device generates a lifted matrix based on the base matrix and/or the selected lifting size value. The transmitting device uses the generated lifted matrix to generate the lifted LDPC code, encodes a set of information bits based on the lifted LDPC code to produce a code word, and transmits the code word over a wireless medium. According to aspects of the present disclosure, a set liftings Z for a single base graph or PCM, to obtain a family of LDPC codes can be described (e.g., determined/generated) using lifting values that are close to each other in value for a compact description. The family of LDPC codes can be obtained using a base graph together with an increasing series of liftings with lifting values Z1, Z2, . . . , Znwhich may be referred to herein as a “tower” of liftings. A cluster includes members which are within a defined range of each other. For example, members of a cluster may be within a certain ratio of each other. In some cases, the values of the members of the cluster may be within a ratio of two of each other. One example of a cluster is the set of lifting values {4, 5, 6, 7} having a maximum ratio of 7/4. A tower can be obtained by applying an exponential power to an integer, such as a power of 2. Thus, a tower of clustered liftings may consist of the integers 2j{4, 5, 6, 7} for j=1, . . . , 7. This gives an approximately exponentially spaced set of 28 values for Z. Put another way, this gives the tower Z1, Z2, . . . , Z28=8 (21*4), 10, 12, 14, . . . , 896 (27*7). For a fixed j the four lifting values are within a factor of 7/4 of each other and may form a cluster of lifting values. For j=1, . . . , 7, a tower of clustered liftings may be represented as 2j{4, 5, 6, 7}. While the present example includes a set of lifts within a factor of 2 as clustered, other factors, (e.g., 3, 4 . . . , etc.) may be used. These factors need not be consecutive, but should be numerically within a defined range of each other. According to certain aspects, for any lifting size Z in the set of clustered liftings, the associated integer lifting values k for the edge permutations may be used for any of the other liftings in the set of clustered liftings. For example, lifting values may be designed for Z=2j4 that are also good for 2j{5, 6, 7}. Thus, describing (e.g., determining/generating/indicating/storing) a family of LDPC codes may be performed by identifying sets of clustered lift values (associated to edges in a base graph) that are close to each other, such as within a factor (e.g., a factor 2 or 3) of each other. In the example above, this corresponds to identifying the set of lifting values {4, 5, 6, 7} and the other sets in the tower of liftings, {16, 20, 24, 28}, {32, 40, 48, 56}, . . . {512, 640, 768, 896}, which are within a factor of 2 of each other. For each clustered set of liftings, the base PCM for the smallest lift value in the cluster (e.g., Z=8) may be optimized. That optimized base PCM may be used for the other lift values in that cluster (e.g., Z=10, Z=12, 14). Similarly, the optimized base PCM can be determined for the other sets of clustered liftings. Thus, liftings within a defined range of each can be specified (e.g., stored/indicated) other with a common set of bits. For example, j+2 bits per lifting value may be used to specify all lifts for the four stated liftings in the cluster 2j{4, 5, 6, 7}. These liftings may be further improved by having additional bits. For example, using j+3 bit to represent the lifting values k on an edge and defining the lifting by taking the j+3 bit value modulo Z for Z in 2j{4, 5, 6, 7} results in a lifting for Z=2j*4 given by the j+2 lower order bits and the higher order bit affects only the other 3 liftings. Higher order bits can similarly be used. The example presents a range of liftings within a factor of 2 of each other and all are specified using a j+2 (or slightly larger) bits. However, other factors may be used, so long as the factors are numerically within a defined range of each other. Generally, optimization of lifts and graphs targets reducing the number of small loops in the Tanner graph of the LDPC code. A loop in the lifted Tanner graph corresponds with a loop in the base graph by projecting the loop onto the base graph. Additional optimizations may take into account the degrees of nodes in the loops In the case of matched lifted graphs (e.g., cyclically lifted graphs) a loop in the base graph is also a loop in the lifted Tanner graph precisely when the lifting values traversed in the loop reduce to the identity permutation. According to certain aspects, using j+3 bit to represent the lifting and defining the lifting by taking the j+3 bit value modulo Z for Z in 2j{4, 5, 6, 7} results in a lifting for Z=2j4 given by the j+2 lower order bits and the higher order bit affects only the other 3 liftings. For the optimization of the base graph for a set of clustered liftings, liftings values may be selected within a range [0,(2j*4)−1]. In other words, the lifting values may be selected from a range that is smaller than the smallest lifting size in the set of clustered liftings. Thus, in example described herein, for the tower of clustered liftings for j=1, the lifting size values may be selected from the range [0:7]. For cyclically lifted graphs, each edge in the base graph has an associated integer as a lifting value. The value is taken positively when the edge is traversed in the variable-to-check direction and negatively in the check-to-variable direction. Given a loop in the base graph and a lifting size Z, the base loop will also be a lifted loop if the loop sum of the corresponding integers is 0 or has Z as a factor. Thus, when choosing integer value in the range [0,2j4] for the lifting values, the goal for Z=2j4 is to avoid summing to 0 or to having a factor of 2j4 in the loop sum. For small loops, the sum generally will not be large, so in general, there are more such loops with a sum of magnitude 2j4 than those with a sum of magnitude 2*2j4 or 3*2j4. Similarly, on average, sums of magnitude 2j{5, 6, 7} and its multiples are less frequent. Thus, the small loop avoidance design problem is similar for these closely related values, where lift values in the range [0:2j4] uses more than half the range available for Z=2j{5, 6, 7}. For a much larger Z, the used portion would be smaller and there may be a bigger gap between the best performance available for the large Z and that achievable by restricting liftings to a smaller Z. Thus, applying this approach over a relatively small range of Z values (e.g., within a factor of 2) is prudent. Hence, it is possible to find lift values that give good performance for four values simultaneously. By utilizing a range of liftings which are numerically within a defined range along with an independent set of bits for each j with j=1, . . . , 7 the number of bits required is 3+4+5+6+7+8+9=42 bits per edge to specify all of the liftings. By creating dependencies between different values of j this requirement may be further reduced. Additionally, often a structured LDPC graph will have special edges whose lifting values may be determined directly. For example, the edges connecting degree one variable nodes may always have lifting value 0. Edges on accumulate chains in encoding structures are also often set to 0. Such fixed lifting structure may not vary as the liftings vary and may be referred to as having a special invariant structure. The lifting values for such edges can be more compactly represented. However, the number of edges having such a special invariant structure is a small portion of the total number of edges in the graph and does not significantly detract from the benefits of the above method for those edges that do not have a special invariant structure. Example: Nested Scheme for Efficiently Lifting LDPC Codes As described above, liftings in a clustered set of liftings (e.g., a “tower” of liftings”) can use the same lifting values (integers associated with the edge permutations) and, thus, the number of bits used to specify all of the liftings and lifting values may be reduced. This size reduction may allow for a reduced amount of memory for storing descriptions of all of the LDPC codes. According to aspects of the present disclosure, a nested scheme for efficiently lifting LPDC codes may be used that further reduced the number of bits per edge in the base PCM. As all liftings, even for different j values (e.g., liftings in different clustered sets), are based on the same base graph, the structures found to work for a small j value (i.e., for liftings in the corresponding set of clustered liftings) may be scaled and reused for larger j values (i.e., for larger liftings in another set). For example, a structure optimized for a smaller j may be retained and scaled for a larger j in order to reuse optimized bits found for the smaller j. In one example, a transmitter/encoder device (e.g., such as a BS110or a UE120) determines a base matrix that is associated with a cluster of lifting size values. The transmitting device selects a first lifting size value from the cluster of lifting size values for generating a lifted LDPC code by permutations of edges in the base matrix. The lifting size values in the cluster of lifting size values are within a defined range of each other. The transmitting device generates a first lifted matrix based on the base matrix and/or selected first lifting size value and selects a set of bits associated with the selected first lifting size value. The transmitting device selects a selecting a second lifting size value from the cluster of lifting size values and generates a second lifted matrix based on the base matrix, second selected lifting size value, and the set of bits. The transmitting device uses the generated second lifted matrix to generate the lifted LDPC code, encodes a set of information bits based on the lifted LDPC code to produce a code word, and transmits the code word. In the example described above, for j=1, the set of clustered liftings is Z={8, 10, 12, 14} may be designed using lifting values in the range [0, 1, 2, . . . 7]. According to certain aspects, the liftings values selected for the j=1 graph can be multiplied by 2 and used for the j=2 graph, where the set of clustered liftings is Z={16, 20, 24, 28}. In this case, the larger lifted graph (for j=2) inherits and improves on the loop structure of the smaller graph as the larger graph for lifting 2Z consists of two parallel copies of the original smaller graph with lifting Z. Because the smaller graph is designed to avoid loops summing to a factor of Z, it also avoids loops summing to factors of 2Z. j=1 and j=2 are merely exemplary. In aspects, the lifting values for any set of clustered liftings may be used for another set of larger clustered liftings, and the lifting values can be multiplied by the factor of the difference in the liftings sizes of the two sets of liftings. Further optimization of the larger graph could be achieved by altering the lowest order bit in the liftings. For example, after multiplication by 2 all liftings would have their lowest order bit set to 0. More generally, to achieve the best possible performance, more than just the lowest order bit may be altered. For example, two or three least significant bits may be altered. Generally, optimizing the three least significant bits results in nearly optimal performance. This preserves the large scale properties of the liftings (the most significant) bits, scaled up accordingly (by multiplying by 2) and then refines the details (the lower order bits) to find an optimal solution for the base graph for the next set of clustered liftings. In one example, the three lowest order bits may be re-optimized. For the set of clustered liftings j=1, a 3-bit optimized lift per edge may be obtained. If the lifting values for an edge in the base graph (e.g., for the smallest lifting in the set j=1) are a, y, and z (i.e., 3 bits) in base 2 (i.e., where each of a, y, and z is an integer values of 0 or 1), then for the base graph for the set of clustered liftings j=2, the same edge will have lifting values of a, b, w, x, (i.e., 4 bits with one bit copied from the j=1 family) and in the base graph for the set of clustered liftings j=3, the edge will have lifting values a, b, c, u, v, (5 bits with 2 bits copied from the j=2 family) etc. Thus, the base graph for the set of clustered liftings j=7, the edge will have lifting value a, b, c, d, e, f g, r, s (i.e., 9 bits with 7 bits copied from the j=6 family) and the bits a, b, c, d, e, f g are reused for smaller set of clustered liftings j while the bits r and s are unique to j=7. The base graph for the set of clustered liftings uses j common bits and 2 unique bits. Thus, for all of the families j=1 . . . 7, there is a total of seven common bits and fourteen unique bits (i.e., 2 unique bits for each j), for a total of 21 bits to describe all seven code families. This is referred to as a “nested” scheme for describing the families of LDPC codes. If only the two lowest order bits were re-optimized then only 14 bits total would be needed. In some examples, most significant bits (MSBs) or any subset of consecutive bits can be used as common bits, rather than the LSBs. Both cases offer a substantial improvement on the 42-bit independent case. As discussed above, certain structured LDPC graph may have a special invariant structure, for example, some special edges may have liftings that are invariant. For example, the 802.11 encoding structure, uses liftings of values 0 and 1. If this structure is retained, the structure is consistent with the above optimization of lower order bits only when at least two of the lower order bits are optimized. This is because 2x1=2; so if only the lowest order bit is optimized, the value 1 cannot be reached as only 2 and 3 are possible values. In this case, it may be preferable to retain the lifting value of 1. A similar technique can be used in which the low order bits are retained across different j and the higher order bits are re-optimized. In general, some bits from a smaller j may be reused to define values for the larger j while leaving enough bits for optimization so as to achieve good performance. CONCLUSION The encoding techniques described herein for high performance, flexible, and compact LDPC codes may lead to improved processor performance. For example, the techniques may allow for a processor to efficiently encode information of various blocklengths and code rates using good codes (e.g., having few loops). For example, a device, such as a processing system in BS110or UE120shown inFIG.1, may encode and/or decode code words according to aspects of the present disclosure more quickly or more efficiently (e.g., consuming less power) than a device encoding and/or decoding code words according to previously known aspects. The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c). As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like. In some cases, rather than actually transmitting a frame, a device may have an interface to output a frame for transmission. For example, a processor may output a frame, via a bus interface, to an RF front end for transmission. Similarly, rather than actually receiving a frame, a device may have an interface to obtain a frame received from another device. For example, a processor may obtain (or receive) a frame, via a bus interface, from an RF front end for transmission. The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering. For example, means for encoding, means for determining, means for selecting, and/or means for generating may include one or more processors, such as the TX MIMO processor430, Transmit processor420, and/or the Controller/Processor440of the BS110illustrated inFIG.4; the TX MIMO processor466, Transmit Processor464, and/or the Controller/Processor480of the UE120illustrated inFIG.4; and/or the encoder1102of the encoder1100illustrated inFIG.11. Means for puncturing may comprise a processing system, which may include one or more of processors ofFIG.4, and/or the puncturing module1104of the encoder1100illustrated inFIG.11. Means for transmitting comprises a transmitter, which may include the Transmit processor420, TX MIMO processor430, modulator(s)432a-432t, and/or the antenna(s)434a-434tof the BS110illustrated inFIG.4; the Transmit processor464, TX MIMO Processor466, modulator(s)454a-454r, and/or antenna(s)452a-452rof the UE120illustrated inFIG.4; and/or the TX chain1108and antenna1110of the encoder1100illustrated inFIG.11. The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the PHY layer. In the case of a wireless node (seeFIG.1), a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system. If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on the machine-readable storage media. A computer-readable storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer readable storage medium with instructions stored thereon separate from the wireless node, all of which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Examples of machine-readable storage media may include, by way of example, RAM (Random Access Memory), flash memory, ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. The computer-readable media may comprise a number of software modules. The software modules include instructions that, when executed by an apparatus such as a processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media. Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a wireless node and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a wireless node and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized. It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims. | 100,805 |
11942965 | DETAILED DESCRIPTION Exemplary embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings. It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly indicates otherwise. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Herein, when one value is described as being about equal to another value or being substantially the same as or equal to another value, it is to be understood that the values are equal to each other to within a measurement error, or if measurably unequal, are close enough in value to be functionally equal to each other as would be understood by a person having ordinary skill in the art. For example, the term “about” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations as understood by one of ordinary skill in the art. Further, it is to be understood that while parameters may be described herein as having “about” a certain value, according to exemplary embodiments, the parameter may be exactly the certain value or approximately the certain value within a measurement error as would be understood by a person having ordinary skill in the art. Embodiments of the inventive concept provide an efficient soft RS decoder for decoding RS codes. RS codes are based, to a large extent, on the mathematical concepts of finite algebraic fields, linear vector spaces, dimension, affine spaces, polynomials, and linear equations. In mathematics, a field F is a set on which addition, subtraction, multiplication, and division are defined. The elements of the field are referred to as scalars. Each field F has its own zero (e.g., 0F) and unit (e.g., a+0F=a and a·1F=a). Examples of fields include the field of rational numbers, the field of real numbers and the field of complex numbers. A finite field or Galois field is a field that contains a finite number of elements. The most common examples of finite fields are given by the integers mod p when p is a prime number. The order of a finite field is its number of elements, which is either a prime number or a prime power. For every prime number p and every positive integer k there are fields of size pk, all of which are isomorphic (i.e., essentially the same). Finite fields are important in a number of areas of mathematics and computer science, including cryptography and coding theory. In mathematics, physics, and engineering, a vector space (also referred to as a linear space) over a field F is a set whose elements (e.g., referred to as vectors) may be added together and multiplied by scalars from F. A linear combination of vectors v1, . . . , vnthat belongs to a vector space V over F is defined as a linear combination, as that is a sum of these vectors where each is multiplied by a scalar αifrom the field F. Hence it is a vector v given by: v=Σ1≤i≤nαi·vi. Vector spaces are characterized by their dimension, which specifies the number of independent directions in the space. An affine space is the set resultant by adding a fixed vector to every element in a vector space. Polynomials over a field F, are algebraic expressions that consist of indeterminates (or variables) and coefficients. One can perform arithmetic operations such as addition, subtraction, multiplication and also positive integer exponents for polynomial expressions. An example of a polynomial of a single variable x, over the real numbers is 2·x3+x−5. The x occurring in a polynomial is referred to as a variable or an indeterminate. When the polynomial is considered as an expression, x is a fixed symbol which does not have any value (its value is “indeterminate”). However, when one considers the function defined by the polynomial, then x represents the argument of the function, and is therefore referred to as a “variable”. A polynomial over a field F in a single indeterminate x can always be written in the form P(x)=Σ0≤i≤nαi·xiwhere αiare elements (scalars) of the field F scalars of the field F. αiare called the coefficients of the polynomial. This expression may be read as a vector (or list) of n+1 scalars. The evaluation of the polynomial P(x) in element α of the field F denoted by P(α) is defined as the scalar value resultant by replacing x with α to yield P(α)=Σ0≤i≤nαi·αi. The degree of the polynomial P(x) is defined by the maximal index of a coefficient that is not zero. That is, the maximal i such that αi≠0. The degree of polynomial P(x) is denoted by deg(P(x)). A root of the polynomial P(x) in the field F is an element β in F such that the evaluation of polynomial P(x) in β is equal to zero. That is, it is a β in F such that: P(α)=0. The multiplication of the polynomial P(x) by a scalar is done multiplying each individual coefficient by that scalar. That is, for a scalar c in F we define: c·P(x)=Σ0≤i≤nc·αi·xi. The sum of two polynomials is given by adding corresponding coefficients. That is, for polynomials P(x) and Q(x) over the field F where: P(x)=Σ0≤i≤nαi·xiand Q(x)=Σ0≤i≤nbi·xiand their sum is defined as: P(x)+Q(x)=Σ0≤i≤n(αi+bi)·xi. Thus, the set of polynomials over the field F constitute a vector space over F. The product of two polynomials P(x) and Q(x) is defined as the sum of the products of every pair of coefficients wherein it is attached to the added corresponding powers. The product may be defined by: P(x)·Q(x)=Σ0≤i,j≤n(αi·bj) xi+j=Σ0≤s≤2n(Σ0≤i,j≤n, i+j=sαi·bj)·xs. One polynomial g (x) divides another polynomial ƒ(x), if there exists a third polynomial h(x) whose product by the first polynomial is equal to the second polynomial. A method of the inventive concept proposes that a first operation performed by the RS decoding system is an RS HD decoding, which includes the Berlekamp-Massey (BM) algorithm that can solve the Key equations. () Throughout the BM algorithm, the method may instruct the decoder to retain in a temporary memory (e.g., a RAM) the by-products (e.g., σi(x), ωi(x)) of the BM algorithm inFIG.7. These by-products are normally not kept by RS decoders after the BM ends. In an embodiment, only if the HD fails is the SD decoder of the inventive concept then used. The first SD stage (seeFIG.8) uses the stored elements (e.g., the by-products) as building blocks for the main SD procedure. BM is described to provide the groundwork forFIG.8. HD is mentioned here to explain the advantages offered by embodiments of the inventive concept over prior art. The key equations is a step of an RS decoding algorithm. The key equations embody a set of linear equations that encapsulate the entire network of relations between the received word and the error locations and error values. FIG.1is a block diagram illustrating an implementation of a data processing system including a memory system, according to an exemplary embodiment of the inventive concept. The memory system may include the above-described RS decoder. Referring toFIG.1, the data processing system10may include a host100and a memory system200. The memory system200shown inFIG.1may be utilized in various systems that include a data processing function. The various systems may be various devices including, for example, mobile devices, such as a smartphone or a tablet computer. However, the various devices are not limited thereto. The memory system200may include various types of memory devices. Herein, exemplary embodiments of the inventive concept will be described as including a memory device that is a non-volatile memory. However, exemplary embodiments are not limited thereto. For example, the memory system200may include a memory device that is a volatile memory. According to exemplary embodiments, the memory system200may include a non-volatile memory device such as, for example, a read-only memory (ROM), a magnetic disk, an optical disk, a flash memory, etc. The flash memory may be a memory that stores data according to a change in a threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), and may include, for example, NAND and NOR flash memories. The memory system200may be implemented using a memory card including a non-volatile memory device such as, for example, an embedded multimedia card (eMMC), a secure digital (SD) card, a micro SD card, or a universal flash storage (UFS), or the memory system200may be implemented using, for example, an SSD including a non-volatile memory device. Herein, the configuration and operation of the memory system200will be described assuming that the memory system200is a non-volatile memory system. However, the memory system200is not limited thereto. The host100may include, for example, a system-on-chip (SoC) application processor (AP) mounted on, for example, a mobile device, or a central processing unit (CPU) included in a computer system. As described above, the host100may include an AP110. The AP110may include various intellectual property (IP) blocks. For example, the AP110may include a memory device driver111that controls the non-volatile memory system200. The host100may communicate with the non-volatile memory system200to transmit a command (e.g., a read command, a write command, an erase command, etc.) related to a memory operation and receive a confirm command in response to the transmitted command. The non-volatile memory system200may include, for example, a memory controller210and a memory device220. The memory controller210may receive a command related to a memory operation from the host100, generate an internal command and an internal clock signal using the received command, and provide the internal command and the internal clock signal to the memory device220. The memory device220may store write data in a memory cell array in response to the internal command, or may provide read data to the memory controller210in response to the internal command. The memory device220may include a memory cell array that retains data stored therein, even when the memory device220is not powered on. The memory cell array may include as memory cells, for example, a NAND or NOR flash memory, a magnetoresistive random-access memory (MRAM), a resistive random-access memory (RRAM), a ferroelectric access-memory (FRAM), or a phase change memory (PCM). For example, when the memory cell array includes a NAND flash memory, the memory cell array may include a plurality of blocks and a plurality of pages. Data may be programmed and read in units of pages, and data may be erased in units of blocks. An example of memory blocks included in a memory cell array is shown inFIG.4. FIG.2is a detailed block diagram of the non-volatile memory device220ofFIG.1, according to an exemplary embodiment of the inventive concept. Referring toFIG.2, the non-volatile memory device220may include, for example, a memory cell array221, a control logic222, a voltage generation unit223, a row decoder224, and a page buffer225. The memory cell array221may be connected to one or more string select lines SSL, a plurality of word lines WL, one or more ground select lines GSL, and a plurality of bit lines BL. The memory cell array221may include a plurality of memory cells disposed at intersections between the plurality of word lines WL and the plurality of bit lines BL. The control logic222may receive a command CMD (e.g., an internal command) and an address ADD from the memory controller210and receive a control signal CTRL for controlling various functional blocks within the non-volatile memory device220from the memory controller210. The control logic222may output various control signals for writing data to the memory cell array221or reading data from the memory cell array221, based on the command CMD, the address ADD, and the control signal CTRL. In this manner, the control logic222may control the overall operation of the memory device220. The various control signals output by the control logic222may be provided to the voltage generation unit223, the row decoder224, and the page buffer225. For example, the control logic222may provide the voltage generation unit223with a voltage control signal CTRL_vol, provide the row decoder224with a row address X-ADD, and provide the page buffer225with a column address Y-ADD. The voltage generation unit223may generate various voltages for performing program, read, and erase operations on the memory cell array221based on the voltage control signal CTRL_vol. For example, the voltage generation unit223may generate a first driving voltage VWL for driving the plurality of word lines WL, a second driving voltage VSSL for driving the plurality of string select lines SSL, and a third driving voltage VGSL for driving the plurality of ground select lines GSL. In this case, the first driving voltage VWL may be a program voltage (e.g., a write voltage), a read voltage, an erase voltage, a pass voltage, or a program verify voltage. In addition, the second driving voltage VSSL may be a string select voltage (e.g., an on voltage or an off voltage). Further, the third driving voltage VGSL may be a ground select voltage (e.g., an on voltage or an off voltage). The row decoder224may be connected to the memory cell array221through the plurality of word lines WL, and may activate a part of the plurality of word lines WL in response to the row address X-ADD received from the control logic222. For example, in a read operation, the row decoder224may apply a read voltage to a selected word line and a pass voltage to unselected word lines. In a program operation, the row decoder224may apply a program voltage to a selected word line and a pass voltage to unselected word lines. In an exemplary embodiment, in at least one of a plurality of program loops, the row decoder224may apply the program voltage to the selected word line and an additionally selected word line. The page buffer225may be connected to the memory cell array221through the plurality of bit lines BL. For example, in a read operation, the page buffer225may operate as a sense amplifier that outputs data stored in the memory cell array221. Alternatively, in a program operation, the page buffer225may operate as a write driver that writes desired data to the memory cell array221. FIG.3is a block diagram illustrating the memory system200ofFIG.1, according to an exemplary embodiment of the inventive concept. Referring toFIG.3, the memory system200includes the memory device220and the memory controller210. The memory controller210may also be referred to herein as a controller circuit. The memory device220may perform a write operation, a read operation, or an erase operation under control of the memory controller210. The memory controller210may control the memory device220depending on a request received from the host100or an internally designated schedule. The memory controller210may include a controller core121, an internal memory124, a host interface block125, and a memory interface block126. The controller core121may include an RS encoder132and an RS decoder134. The controller core121may control and access the memory device220depending on a request received from the host100or an internally designated schedule. The controller core121may manage and execute various metadata and codes used to manage or operate the memory system200. The controller core121may perform error detection and correction on data read from memory cells of the memory device220using the RS decoder134. The internal memory124may be used, for example, as a system memory which is used by the controller core121, a cache memory which stores data of the memory device220, or a buffer memory which temporarily stores data between the host100and the memory device220. The internal memory124may additionally store a mapping table MT that indicates a relationship between logical addresses from the Host Device100assigned to the memory system200and physical addresses of the memory device220. The internal memory124may include, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). The internal memory124may be a buffer. The host interface block125may include a component for communicating with the host100such as, for example, a physical block. The memory interface block126may include a component for communicating with the memory device220such as, for example, a physical block. The host interface block125may provide the memory control core122with a first request REQ1 received from the host100. The first request REQ1 may include a command (e.g., a read command or a write command) and a logical address. The memory control core122may translate the first request REQ1 to a second request REQ2 suitable for the memory device220. For example, the controller core121may translate a format of the command. The controller core121may obtain address information AI with reference to the mapping table MT stored in the internal memory124. The controller core121may translate a logical address to a physical address of the memory device220by using the address information AI. The controller core121may provide the second request REQ2 suitable for the memory device220to the memory interface block126. The memory interface block126may register the second request REQ2 from the controller core121at a queue. The memory interface block126may transmit a request that is first registered at the queue to the memory device220as a third request REQ3. When the first request REQ1 is a write request, the host interface block125may write data received from the host100to the internal memory124. When the third request REQ3 is a write request, the memory interface block126may transmit data stored in the internal memory124to the memory device220. When data is completely written, the memory device220may transmit a third response RESP3 to the memory interface block126. In response to the third response RESP3, the memory interface block126may provide the controller core121with a second response RESP2 indicating that the data is completely written. After the data is stored in the internal memory124or after the second response RESP2 is received, the controller core121may transmit a first response RESP1 indicating that the request is completed to the host100through the host interface block125. When the first request REQ1 is a read request, the read request may be transmitted to the memory device220through the second request REQ2 and the third request REQ3. The memory interface block126may store data received from the memory device220in the internal memory124. When data is completely transmitted, the memory device220may transmit the third response RESP3 to the memory interface block126. As the third response RESP3 is received, the memory interface block126may provide the controller core121with the second response RESP2 indicating that the data is completely stored. As the second response RESP2 is received, the controller core121may transmit the first response RESP1 to the host100through the host interface block125. The host interface block125may transmit data stored in the internal memory124to the host100. In an exemplary embodiment, in the case in which data corresponding to the first request REQ1 is stored in the internal memory124, the transmission of the second request REQ2 and the third request REQ3 may be omitted. FIGS.4and5illustrate an example in which the memory system200is implemented using a three-dimensional flash memory. The three-dimensional flash memory may include three-dimensional (e.g., vertical) NAND (e.g., VNAND) memory cells. An implementation of the memory cell array221including three-dimensional memory cells is described below. Each of the memory cells described below may be a NAND memory cell. FIG.4is a block diagram of the memory cell array221ofFIG.2, according to an exemplary embodiment of the inventive concept. Referring toFIG.4, the memory cell array221according to an exemplary embodiment includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz has a three-dimensional structure (e.g., a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include structures extending in first to third directions. For example, each of the memory blocks BLK1 to BLKz may include a plurality of NAND strings extending in the second direction. The plurality of NAND strings may be provided, for example, in the first to third directions. Each of the NAND strings is connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL. That is, each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, and a common source line CSL. The memory blocks BLK1 to BLKz will be described in further detail below with reference toFIG.5. FIG.5is a circuit diagram of a memory block BLKi according to an exemplary embodiment of the inventive concept.FIG.5illustrates an example of one of the memory blocks BLK1 to BLKz in the memory cell array221ofFIG.4. The memory block BLKi may include a plurality of cell strings CS11 to CS41 and CS12 to CS42. The plurality of cell strings CS11 to CS41 and CS12 to CS42 may be arranged in column and row directions to form columns and rows. Each of the cell strings CS11 to CS41 and CS12 to CS42 may include a ground select transistor GST, memory cells MC1 to MC6, and a string select transistor SST. The ground select transistor GST, the memory cells MC1 to MC6, and the string select transistor SST, which are included in each of the cell strings CS11 to CS41 and CS12 to CS42, may be stacked in a height direction substantially perpendicular to a substrate. The columns of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be connected to different string select lines SSL1 to SSL4, respectively. For example, the string select transistors SST of the cell strings CS11 and CS12 may be commonly connected to the string select line SSL1. The string select transistors SST of the cell strings CS21 and CS22 may be commonly connected to the string select line SSL2. The string select transistors SST of the cell strings CS31 and CS32 may be commonly connected to the string select line SSL3. The string select transistors SST of the cell strings CS41 and CS42 may be commonly connected to the string select line SSL4. The rows of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be connected to different bit lines BL1 and BL2, respectively. For example, the string select transistors SST of the cell strings CS11 to CS41 may be commonly connected to the bit line BL1. The string select transistors SST of the cell strings CS12 to CS42 may be commonly connected to the bit line BL2. The columns of the plurality of cell strings CS11 to CS41 and CS12 to CS42 may be connected to different ground select lines GSL1 to GSL4, respectively. For example, the ground select transistors GST of the cell strings CS11 and CS12 may be commonly connected to the ground select line GSL1. The ground select transistors GST of the cell strings CS21 and CS22 may be commonly connected to the ground select line GSL2. The ground select transistors GST of the cell strings CS31 and CS32 may be commonly connected to the ground select line GSL3. The ground select transistors GST of the cell strings CS41 and CS42 may be commonly connected to the ground select line GSL4. The memory cells disposed at the same height from the substrate (or the ground select transistors GST) may be commonly connected to a single word line, and the memory cells disposed at different heights from the substrate may be connected to different word lines WL1 to WL6, respectively. For example, the memory cells MC1 may be commonly connected to the word line WL1. The memory cells MC2 may be commonly connected to the word line WL2. The memory cells MC3 may be commonly connected to the word line WL3. The memory cells MC4 may be commonly connected to the word line WL4. The memory cells MC5 may be commonly connected to the word line WL5. The memory cells MC6 may be commonly connected to the word line WL6. The ground select transistors GST of the cell strings CS11 to CS41 and CS12 to CS42 may be commonly connected to the common source line CSL. FIG.6illustrates a flow of encoded data to the system. The memory controller210may receive DATA (e.g., Information Bits including K symbols of m bits) from the Host and output the DATA to the RS encoder132. The DATA may be received along with a write request and write address. The RS encoder132operates on the Information Bits to generate an RS codeword x (e.g., including n symbols of m bits). Here K, m, and n are positive integers greater than 0. The memory controller220may store the RS codeword x in the memory device220a location based on the write address. At a later time, the Host may send a read request along with a read address for reading back the RS codeword x. The RS codeword x may be read through a Channel136such as the Memory Interface block126to the memory controller210. However, due to noise, the RS codeword may become converted into a Noisy codeword y (e.g., including n symbols of m bits) that has one or more errors. The RS decoder134of the memory controller210decodes the codeword y back to the original RS codeword x for output to the Host, assuming it is able to correct all the errors. If the RS decoder134is unable to correct the errors, the memory controller210may output an error message to the Host. The RS decoder134performs an efficient soft decoding of an RS code. An (n, k, d) RS code is defined over a Galois field with symbols of m bits. The Galois field may be denoted as F, where |F|=2m. Here n is the code length (number of symbols), wherein n<2m, k is the number of information symbols, and d is the RS code minimal distance. A RS code is a Minimum Distance Separable (MDS) that achieves the Singleton bound (d≤n−k+1). It is assumed that the channel136is an independent identical distributed channel, where each symbol xiof the codeword x passes through the channel independently, that is (y|x)=Πi=1nP(yi|xi). The output symbol may be an erasure (e) with probability Pe, the correct transmitted symbol q with probability Pc, or a different symbol (an error) p according Equation A below. P(y❘"\[LeftBracketingBar]"x=q)={ew·pPeqw·pPcpp∈F,p≠q[EquationA] In Equation A, p≠q, where p∈F and is typically uniformly distributed among the field symbols. Each symbol has probability Ps=1-Pe-Pc2m-1 or with some other distribution. The RS decoder134receives an output codeword y of the channel136and estimates the originally transmitted codeword x. The RS decoder134is a soft decision (SD) decoder. An RS Hard Decision (HD) decoder uses the Berlekamp-Massey (BM) algorithm and the Forney algorithm, where the decoder's aim is to find a code-word (CW) with the minimal Hamming distance from the received code word according to Equation B. xˆ=argminc∈RS(n,k,d)dH(y,c)[EquationB] The Hamming distance dH(y, c) is defined according to Equation C. dH(y,c)=∑i=1nδ(yi≠ciandyi≠e)[EquationC]whereδ(A)={1AisTRUE0o.w. The set of indexes of the symbols yiwith erasures is denoted by Equation D. An erasure is a symbol in the original transmitted codeword x that is missing from the received codeword y. E={i|yi=e,i∈[n]}[Equation D] The set of indexes of the symbols yiwith errors is denoted by Equation E. A symbol with an error means that the symbol in the original transmitted codeword x has a different value from the corresponding symbol in the received codeword y. T={i|yi≠xi,yi≠e,i∈[n]}[Equation E] A correct solution is guaranteed if the following Equation 1 is satisfied. |E|+2·|T|≤d−1 [Equation 1] From Equation 1, it follows that the code error correction capability is t=⌊d-12⌋ and the correct solution is guaranteed if |T|≤t. At least one embodiment of the inventive concept enables a lossless elimination of the erasures and passage to setting with only errors. Thus, it is assumed that there are only errors henceforth. The evaluation set Q of an RS code includes αjdistinct elements of F and is defined as Q={α1, α2, . . . αn}. An error Locator Polynomial (ELP) is defined by the following Equation a1. The ELP may be used to determine the locations of symbols that have errors. Λ(x)=Πj∈T(1−αj·x) [Equation a1] The ELP has degree |T|, is separable and its roots are αj−1for j∈T. Here, Λ(0)=1. If the roots of the ELP are known, the error locations are known. An Error Evaluator Polynomial (EEP) is defined by following Equation a2. While the ELP indicates the error locations, the EEP may be used to recover the error values via a Forney algorithm. Γ(x)=Σj∈TΠi∈\{j}(1−αi·x) [Equation a2] Thus, knowledge of the ELP and EEP enables the RS decoder134to detect and correct errors. At least one embodiment of the inventive concept provides an algorithm for determining the EEP assuming the ELP is given, known, or determinable. The RS decoder134may generate a Syndrome Polynomial S(x) during its decoding. The Syndrome Polynomial S(x) is denoted by the following Equation b1. S(x)=∑i=02t-1Si·xi[Equationb1] In Equation b1, Siare the coefficients of the Syndrome Polynomial S(x) and xiare the terms of the Syndrome Polynomial S(x) (e.g., x3, x2, etc.). The coefficients Siare calculated from the received codeword using the following Equation b2. Si≡Σ1≤j≤nyj·αji0≤i≤2t−1 [Equation b2] If the number of errors does not exceed 2t, the ELP and the EEP satisfy Equation b3 and also b4, b5, b6. Λ(x)·S(x)=Γ(x)mod(x2t)—key equations [Equation b3] The key equations satisfy properties of Equations b4-b6. deg(Γ(x))<deg(Λ(x)) [Equation b4] Λ(0)=1 [Equation b5] gcd(Λ(x),Γ(x))=1 [Equation b6] The Equation b3 means that every coefficient of the polynomial P(x)=Λ(x)·S(x) whose index is between zero and 2t−1 is equal to the corresponding coefficient in Γ(x). The equation b5 means that the first coefficient of Λ(x) (i.e., the coefficient whose index is zero) is equal to one. The equation b6 means that there is no polynomial with positive degree that divides both Λ(x) (e.g., the ELP) and Γ(x) (e.g., the EEP). The RS HD decoding algorithm is a process that tries to find the ELP and EEP. When it succeeds it recovers the transmitted codeword. When |T|≤t, it is guaranteed that there exists a unique pair of polynomials in F[x]: (λ(x), γ(x)), which satisfies the following four conditions, and it is also guaranteed that Λ(x) is equal to the ELP and γ(x) is equal to the EEP. The four conditions are as follows: I) λ(x)·S(x)=γ(x) mod(x2t), II) λ(0)=1, III) deg(γ(x))<deg(λ(x))≤t, and IV) gcd(λ(x), γ(x))=1. Note that by (II), the free coefficient of λ(x) is equal to 1. The Berlekamp-Massey (BM) algorithm finds the unique (λ(x), γ(x)), that satisfies (I)-(IV) when |T|≤t. The BM algorithm uses an iterative process assisted by an auxiliary polynomial ω(x) to find the ELP, which is illustrated inFIG.7. In this algorithm, μ is the last index for which the “If” condition holds. The term σi(x) corresponds to an “evolving ELP” at a given stage in the iterative process that seeks the ELP. The term ωi(x) corresponds to an “evolving EEP”. () Once the ELP candidate (e.g., Λ(x)) is determined, a Chien Search may be performed to find the error locations of the symbols within the received codeword y that have errors. One method for finding the error locations, evaluates Λ(x) on all the inverses of elements in Q by computing Λ(β−1)∀β∈Q. When Λ(αi−1)=0, then i is one of the error indices. In HD, when a polynomial λ(x) is an ELP candidate then it becomes a final candidate after the procedure illustrated inFIG.8is performed. If |T|≤t, the number of distinct roots that λ(x) has () is equal to deg(Λ(x)). In many practical situations, the channel136includes additional information on the channel symbols. For each symbol xi, information may be present as follows: xi={yiw.p.Pio.w.w.p.1-Pi When Pi=1, there is a complete confidence that yiis the correct value. The set of weak indices W={i|Pi≤Pth, i∈[n]}, is defined as the set of indices with confidence probability below some threshold Pth. A naive soft decision algorithm will puncture every subset of 2r+1 coordinate of the set W and apply the above-mentioned HD decoding algorithm. Puncturing the index i means replacing the channel value with an erasure yi=e. The confidence probability may be determined from channel soft information of the channels used to transmit the symbols of a codeword. For example, the channel soft information may include a probability for each symbol that indicates how likely the symbol is to be correct. In an embodiment, the RS decoder134performs a soft decision decoding algorithm with the ability to correct t+r errors for 1≤r<t. The soft decision decoding algorithm receives an additional input of the set W of indexes of weak symbols of the size |W|. The solution of the soft decision decoding algorithm is based on two observations I) if the number of errors |T|=t+r, then the ELP is included in an affine space of polynomials of dimension 2r, whose basis is accessible to the decoder (e.g., this affine space is the set of solutions to a suitable key equation), and II) if the set W includes at least 2r+1 errors, then it is guaranteed that the ELP is included in a small list of polynomials that the decoder134finds when r and |W| are not too large. The proposed SD-RS decoder finds a short list of pairs of polynomials. When the overall number of errors is t+r and W includes at least 2r+1 errors, then the pair (ELP, EEP) is guaranteed to be in this list. The list includes all the pairs of polynomials in F[x], (λ(x), γ(x), which satisfies the 6 conditions illustrated inFIG.9. When conditions 1-3 ofFIG.9holds, the key equations are equivalent to the set of (2t)×(t+r+1) linear equations which are illustrated inFIG.10. With the equation λ0≡1, the ELP can be written by Equation 2 and the EEP can be written by Equation 3. λ(x)=∑i=0t+rλi·xi[Equation2]y(x)=∑i=0t+r-1γi·xi[Equation3] The set of linear equations is also written by Equation 4 as follows: V_·λ=[γ0][Equation4] Since γ(x) is chosen freely in this set of linear equations, the set of first t+r equations is redundant andFIG.10is equivalent to the set of the t−r linear [nonhomogeneous] equations on t+r unknown over F, comprising the last t−r rows. In this set, the unknown are the coefficients of λ(x). The effectiveness of the algorithm is connected to the fact that the conditions ofFIG.10hold the dimension of the affine space of solutions toFIG.10is 2·r. The ELP is in the affine space of solutions toFIG.10. Therefore, the ELP can be represented by the following Equation 5: λ(x)=∑i=12r+1gi·λi(x)[Equation5] where {λi(x)}i=12ris a basis to the space of solutions of the homogenous linear equations in LE, λ2r+1(x) is one solution to the nonhomogeneous equations in LE, and {gi} are scalars in the field F and g2r+1=1. If only 2r errors were required in the set of weak locations, while a ELP would have been found that meets the requirements ofFIG.9, it would have resulted in a very large number of other polynomials (*) that meet these requirements. By requiring 2·r+1 errors in the weak set W, the list of polynomials that meet the requirements ofFIG.9is typically very short, and the ELP is always one of them, because it allows for one extra equation to screen false candidates. In practice, in vast majority of the cases, the ELP is the only polynomial in the list. FIG.11illustrate operations performed by the RS decoder134based on an input codeword y and input channel probabilities P to determine error locations (e.g., T) of symbols in the codeword y according to an exemplary embodiment of the inventive concept. The codeword y can be corrected using the determined error locations to estimate the originally transmitted codeword x. The RS decoder134first performs a syndrome calculation on the input code-word y to generate a syndrome polynomial Ŝ (S1101). The code-word y includes n symbols y1-yn. The following Equation 6 is used to calculate the syndrome polynomial Ŝ. Sˆ(x)=∑i=02t-1Sˆi·xi[Equation6] In equation 6, t is the code error correction capability where t=└(d−1)/2┘, xiare terms of the syndrome polynomial Ŝ, and Ŝiare syndrome coefficients of the syndrome polynomial Ŝ. The parameter d is the () minimal hamming distance of the code. The Hamming distance d is determined from the set E of the symbols with erasures and the set T of the symbols with errors according to above Equation 1, where a correct solution is guaranteed if |T|≤t. The syndrome coefficients Ŝiare calculating using the following Equation 7. Ŝi=Σ1≤j≤nyj·aji0≤i≤2t−1 [Equation 7] In Equation 7, yjare the symbols of the input codeword y and () αjare the RS code locators, which are elements of the Galois Field F. The RS decoder134next performs a puncture calculation on the syndrome polynomial Ŝ to generate a new syndrome polynomial S(x) (step S1102). The new syndrome polynomial S(x) does not consider the erasures located within the input codeword y. An erasure means that a symbol of the originally transmitted codeword x was lost. The puncture calculation includes calculation of an Erasure Location Polynomial (Erasure LP) λE(x) that represents the locations of the erasures within the input codeword y and a post-Erasure syndrome {tilde over (S)}(x). The Erasure LP λE(x) is calculated using the following Equation 8, the post-Erasure syndrome {tilde over (S)}(x) is calculated using the following Equation 9, and the New syndrome S(x) is calculated using Equation 10 where Sj={tilde over (S)}j|E|for j∈{0, 1, . . . , d−|E|−2} and d may be referred to as d−|E| for simplicity as if there were no erasures in the channel136. λE(x)=∏j∈E(1-x·αj)[Equation8]S˜(x)=λE(x)·Sˆ(x)mod(xd-1)≡∑j=0d-2SJ~·xj[Equation9]S(x)≡∑j=0d-2-|E|Sj·xj[Equation10] Next, the RS decoder134prepares a basis {λi(x)}i=12rto the space of solutions of the set of homogeneous linear equations ofFIG.10based on the new syndrome polynomial S(x) and generates a private solution λ2r+1(x) to the non homogeneous equations ofFIG.10. The said basis and said private solution may be found by performing a Gaussian elimination. In a preferred embodiment, the basis {λi(x)}i=12rmay be generated with far less complexity using the intermediate outputs a σi(x) of a Berlekamp-Massey (BM) algorithm as shown inFIG.7.FIG.12which demonstrates an algorithm for determining the said basis using the by-products (σi(x), ωi(x)) (e.g., by-products) of the BM algorithm. These byproducts of the BM algorithm are used as inputs to the algorithm ofFIG.12to generate the basis {λi(x)}i=12·ras its output. A private solution to the linear equations ofFIG.10is the BM algorithm output: λ2·r+1(x)=σ2t(x). Next, the RS decoder134determines a weak set W from the input code-word y (step S1104), which includes the indices of symbols of the input code word y with confidence (e.g., a confidence probability) below some threshold Pth. Step1104may be performed before or after any of steps S1101-S1103. Next, the RS decoder134computes a matrix A from {λi(x)}}i=12r+1and the weak set W(S1105). The computation of the matrix A may be referred to as evaluating the basis on the weak set. The set of indices with higher error probability is denoted as W={i1, i2, . . . i|W|}, Each polynomial of the affine space is given according to Equation 11. λ(x)=∑j=12·rgj·λj(x)+λ2r+1(x)[Equation11] For a polynomial to be the ELP, the requirement of λ(αij−1)=0 j∈J needs to be satisfied wherein J⊆[|W|] is a subset of size 2r+1. To verify this requirement, the RS decoder134computes the matrix shown in part (a) ofFIG.13where λj(αik−1) is the evaluation of the polynomial λj(x) at value αik−1, which corresponds to a point in the weak set. Next, 2r+1 elements can be found in the weak set, represented by mutually different pi∈[|W|] (with i∈[2·r+1]) such that the requirement is met as shown in part (b) ofFIG.13. In a straightforward approach, it means choosing all the combinations of 2·r+1 rows from W (i.e., (w2·r+1) combinations) and solving (2·r+1)×(2·r) linear equations for each combination. Next, the RS decoder134performs a solution search on the matrix A to determine candidates for the ELP (step S1106). The solution search may include solving the following Equation 12 where Akis a subset of the matrix A, of size 2r×(2r+1), where 2·r rows have been selected from A. Ak·g=0,k=1,2,…,K=(|W|2·r)[Equation12] There are (|W|2·r) such selections, and k=1,2,…K=(|W|2·r) are the indices of the different selections. For each k, there is a solution gk=[g1k, g2k, . . . g2r+1k] of coefficients which is a valid solution of the ELP λk(x) according to the following Equation 13. λk(x)=∑i=12r+1gik·λi(x)[Equation13] The above linear equations can be solved by performing a Gaussian Elimination (GE) process and sharing intermediate calculations to find efficiently different candidates of rows selection, based on a structure with lexicographic order. There are three types of GE operations that may performed on a matrix whose entries are in an algebraic field. Type 1 is adding a product of one row to another, type 2 is a product of one row by a scaler different than zero, and type 3 is interchanging two rows. A matrix is in Reduced Row Echelon (RRE) form if it satisfies conditions: (1) all rows consisting of only zeroes are at the bottom, (2) the leading coefficient of a nonzero row is always strictly to the right of the leading coefficient of the row above it, (3) the leading entry in each nonzero row is a 1 (called a leading 1), and (4) each column containing a leading 1 has zeros in all its other entries. Lexicographical order (also known as dictionary order) is a generalization of the alphabetical order of the dictionaries to sequences of ordered symbols. The following algorithm according to an embodiment of the inventive concept is an iterative process in which each iteration starts with a submatrix of A that was transformed to RRE form in previous iterations. The present iteration adds to it a new row from A. It then uses a procedure illustrated inFIGS.14A and14Bto turn the extended matrix to RRE form. The order of the sub matrices in the algorithm is similar to a depth first tree, but there are subtle differences that significantly reduce the complexity. The algorithm uses very little memory. Each iteration starts with a submatrix B, of A in RRE form. This submatrix comprises the rows 1≤i1<i2< . . . is≤w of A. During this iteration the running memory contains [a compressed version of] the RRE forms of each sub-matrix of B, called here B(u), with 1≤u<s, wherein B(u) is the matrix comprising of the rows 1≤i1<i2< . . . <iu≤w of A. The algorithm can by be viewed as a tree, wherein at the leaves of this tree there is an Mx(M+1) matrix B (over F) with the property that its first M columns are linearly independent. Such a matrix may be referred to as Strongly Full Ranked (SFR). For such a matrix B, there is a unique vector x=[x1, . . . , xM, 1]Twith entries in F such that B·x=0, x is referred to as the annihilator of B, and x is an (M+1)-length column vector with entries in F whose bottom entry is 1. In an embodiment of the algorithm, M=2r. It is assumed that a subset U⊆[w] is written as an increasing sequence: U={1≤u1<u2< . . . <us≤w}. AUis submatrix of A whose first row is the u1row of A and its second row is the u2row of A, etc. The algorithm process every AUwhen U belongs to the following set: Ω={U⊆[w]: 1≤|U|≤2r−1, w−(2r−|U|+1)≥max(U)}∪{U⊆[w]: |U|=2r, |U∩{w−1,w}|≤1}. It turns AUinto RRE form written by BU. The unit matrix of size n is the n×n square matrix with ones on the main diagonal and zeros elsewhere. An example of a 3×3 unit matrix Ais=[100010001]. The major intermediate goal of this algorithm is to process and assess every matrix AUwhere U is in Ω and |U|=2r. Notice that this AUis a sub matrix of A comprising 2r rows of A. If AUis not SFR, then the processing of AUis halted. Otherwise AUis SFR and therefore also BUis SFR. In such an event, the first 2r columns of BUform a 2r×2r unit matrix and the annihilator xUof BUis the last column of BUwith a 1 added at the end. Thus, xUis a (2r+1) column vector with entries in F whose bottom entry is 1. The decoder134stores xUor a signature of xUin a low cost manner (e.g. by storing the first symbol). The parameter U can be written according to the Equation 14 and the decoder has a fast and low cost mechanism to find out if there exists U′∈Ω according to the Equation 15 U={1≤u1<u2< . . . <u2r−1<u2r≤w}.[Equation 14] U′={1≤u1<u2< . . . u2r−1<u′2r≤w}[Equation 15] for which: u′2r<u2rand xU=xU′. Such an event may be referred to as a collision event. These are rare events and one (or more) of these events leads to finding the ELP when |T|=t+r and |T∩W|≥2r+1. Looking back at the sets U and U′ one sees that they differ in only the last element. When U*=U∪U′ is defined, then U* is of size 2r+1 and U*={1≤u1<u2< . . . <u2r−1<u′2r<u′2r≤w}. Thus, it holds for x=xU=xU′that: AU*·x=0. Further, for x=[x1, . . . , x2r, 1]T, it holds that the polynomial of Equation 16 is an ELP candidate. λ(x)=∑j=12·rxj·λj(x)+λ2r+1(x)[Equation16] Next, the RS decoder134checks if λ(x) satisfies the conditions inFIG.9. If the answer is yes, then λ(x) is a full ELP candidate. The following lexicographic order defines the search that may be used in the algorithm. The search enables optimization of the computations sharing, and it enables minimization of complexity. We define now a total order on S). Take V, U∈Ω and write: ={1≤u1<u2< . . . <ua≤w} and V={1≤v1<v2< . . . <vb≤w}, then U<V if either: i) a<b and u={u1, . . . , ua}={v1, . . . , va} or ii) for some 1≤i≤min(a,b) vi>uiand vj=ujfor all 1≤j<i. The algorithm goes through every U element of Ω with accordance to the LEX order and computes for U the unique RRE form of AUcalled here BU. When U has only one element, that is when, U={j} then the decoder only has to normalize A{j}so that leading element becomes 1 to obtain B{j}. For U={1≤u1<u2< . . . <us≤w} (1<s≤2r) we define U′={1≤u1<u2< . . . <us−1}. In such case as mentioned above the running memory already has BU′. Then by applying the algorithm ofFIGS.14A and14Bthe decoder efficiently computes BU. For s=2r, xUis equal to the last column of BUwith 1 added at the end. The second running memory is now presented for the case s=2r. It is assumed for j, us−1<j≤w: Uj={1≤u1<u2< . . . <us−1<j≤w}. When the processing of U begins the second memory comprises h(xU(j)) for us−1<j<us. For x∈F2r, h(x) is a fixed hash function that can be used. In an example, h(x) is fixed to be one of the symbols of x. This second memory is ordered lexicographically and therefore the complexity of inserting a new element into this memory is upper bounded by log2(w) comparisons. When h(xU) is inserted to the second memory the said lexicographic order enables the decoder to know instantly if there is collision. In the case that a collision occurs, one proceeds as described above. The memory and a quick storage of the annihilator can be run in a compressed hashed form. Taken U∈Ω and when it is represented as U={1≤u1<u2< . . . <us≤w}, U*[i]={1<u1<u2< . . . <ui≤w} is defined for 1≤i<s. When the algorithm starts the U-step, the first memory always includes Ũ={U*[i]: 1≤i<s} (e.g., typically in a compressed form. At this point, the decoder erases from the first memory every item (if exists) which is not in (the compressed form of) Ũ. When the U step ends, then if |U|<2r, the decoder adds BUto the first memory. An embodiment of the second memory with a specific hash is presented below. 1≤i*≤2r is fixed and for U∈Ω, with |U|=2r, U={1≤u1<u2< . . . <u2r≤w} yU(the hash of xU) is defined to be the i* symbol of xUand define for j, u2r−1<j≤w: U(j)={1≤u1<u2< . . . <u2r−1<j≤w}. When the algorithm starts the U-step, the second memory contains the list L:={yU(j): u2r−1<j≤w} ordered lexicographically. When the U-step ends, yUis inserted in this list with accordance to the lexicographic order. This provides an accurate and quick detection of collisions, that is, if yU=yU(j)for some u2r−1<j≤w, then the insertion procedure detects it. In such event, there is “collision alarm” and the decoder checks if xU=xU(j). If the answer is negative, then the above process continues as described. If the answer is positive, then it proceeds as discussed above where it states “it is assumed that a subset U⊆[w] is written as an increasing sequence: U={1≤u1<u2< . . . <us≤w}. AUis submatrix of A whose first row is the u1row of A and its second row is the u2row of A, etc.; the algorithm process every AUwhen U belongs to the following set: Ω−{U⊆[w]: 1≤|U|≤2r−1, w−(2r−|U|+1)≥max(U)}∪{U⊆[w]: |U|=2r, |U∩{w−1, w}|≤1}; and tt turns AUinto RRE from written by BU”. Next, the RS decoder134performs an interaction search on the result of the solution search (step S1107). The interaction search searches for intersections of size 2r, which is guaranteed to have 2r+1 erasures in W. Lastly, the RS decoder134performs a Chien Search on the remaining polynomial solutions λ(x) to find the error locations (step S1108). For example, the Chien Search may find t+r errors, such as deg(λ(x))=[J]. An error correction can then be performed on the symbols with the found error locations to generate corrected data, and the corrected data can be output to the Host100. FIG.15illustrates a method of reading data according to an exemplary embodiment of the inventive concept. The method includes reading data from memory. For example, the Host device100may send the memory controller210a read request including a read command and logical address of the memory device220, where the data is read from a physical address of the memory device220associated with the logical address. For example, the mapping table MT may be accessed using the logical address to retrieve the physical address. The read data (e.g., a codeword) may be temporarily stored in the page buffer130. The read of the data may be performed by the controller core121. The method may include performing a hard-decision decoding (HD) on the codeword (step S1501). If the hard-decision decoding is successful, the HD results in corrected data that can then be output to the Host100. If the hard-decision decoding fails, then the method ofFIG.15performs a soft-decision decoding on the codeword (see steps S1502-S1510). The soft-decision decoding includes performing a syndrome calculation on the codeword to generate a first syndrome polynomial (step S1502). The soft-decision decoding further includes performing a puncture calculation on the first syndrome polynomial to generate a second syndrome polynomial (step1503). The soft-decision decoding further includes generating a private solution of an affine space determined from the second syndrome polynomial (step S1504). The soft-decision decoding further includes determining a weak set of symbols of the codeword having a confidence below a certain threshold (step S1505). The soft-decision decoding further includes computing a matrix from the weak set and the private solution (step S1506). The soft-decision decoding further includes performing a solution search on the matrix to determine candidates of a certain size having a certain number of erasures in the weak set (step S1507). The soft-decision decoding further includes searching the candidates for intersections of a certain size having a certain number of erases in the weak set (step S1508). The soft-decision decoding further includes performing a Chien search on the candidates returned from the search to determine error locations (step S1509). The soft-decision decoding further includes correcting symbols having the error locations to generate corrected data (step S1510). The method may further include outputting the corrected data to the Host100. For example, the controller core121may output the resulting data to the Host device100. FIG.16is a block diagram of a computing system1200including a non-volatile memory system, according to an exemplary embodiment of the inventive concept. The non-volatile memory system inFIG.16may be the memory system200illustrated inFIG.1. In the computing system, which may be, for example, a mobile device or a desktop computer, the non-volatile memory system may be mounted as a non-volatile storage system, however exemplary embodiments are not limited thereto. The computing system may include, for example, a host1602including a CPU, a RAM1603, a user interface1604, and a device driver1605. The host1602may be the host100illustrated inFIG.1, and the device driver1605may be the memory device driver111illustrated inFIG.1. These elements are electrically connected to a bus1606. A non-volatile storage system1607may be connected to the device driver1605. The host1602may control the entire computing system and perform an operation corresponding to a user command input through the user interface1604. The RAM1603may function as a data memory of the host1602. The host1602may write user data to or read user data from the non-volatile storage system1607through the device driver1605. InFIG.16, the device driver1605that controls the operation and management of the non-volatile storage system1607is illustrated as being disposed outside the host1602, however exemplary embodiments are not limited thereto. For example, in an exemplary embodiment, the device driver1605may be disposed inside the host1602. In exemplary embodiments of the present inventive concept, a three-dimensional (3D) memory array is provided as the non-volatile storage system1607The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In exemplary embodiments of the present inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may include a charge trap layer. The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Pat. Pub. No. 2011/0233648. As is traditional in the field of the inventive concept, exemplary embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concept. Further, the blocks, units and/or modules of the exemplary embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept. Exemplary embodiments of the present invention may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may be tangibly embodied on a non-transitory program storage device such as, for example, in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, or any other form of storage medium known in the art. An exemplary storage medium may be coupled to the processor, such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. Further, in some aspects, the processor and the storage medium may reside in an application specific integrated circuit (ASIC). An example of decoding a received word according to an embodiment of the inventive concept is explained below. A codeword is first transmitted through a channel, and a word received in response to the transmission of the codeword. The channel may be a memory device (e.g.,220) including a plurality of memory cells. For example, the channel may include a line between the memory device220and the controller core121that includes the memory interface block126. The channel may also be a line between the host and the controller core121that includes the host interface block125. In the received word there may be some symbols that are erased and some symbols that have errors, while the rest of the symbols are unchanged. The decoder (e.g.,134) knows or can determine the locations of the erased symbols (i.e., the erasures). The decoder may place a zero at each erase symbol within the received word to generate a modified word. For example, if each symbol is 8 bits, and the decoder determines the first symbol was erased, the decoder could insert 8 zeros at the beginning of the received word. The decoder computes a first syndrome polynomial in accordance with the modified received word, and next the decoder computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial which is based on the location of the erasures. The second syndrome polynomial is equal to a syndrome resulting from the received word by puncturing a code at coordinates of the erasures. The decoder finds a basis and a private solution to an affine space V of polynomials that solve key equations based on the second syndrome polynomial. A first coefficient of every polynomial in V is one, and its degree does not exceed a maximal number of errors solvable by the decoder. The decoder determines a weak set of locations of symbols in the received word with confidence below a certain confidence level (i.e., with low confidence). The decoder computes a matrix A from the basis, the private solution, and the weak set. For example, a value at every entry in the matrix A that is not in the last column is an evaluation of a polynomial from the basis of a symbol of the weak set, and a value at every entry in the matrix that is in the last column is an evaluation of the private solution of a symbol of the weak set. The decoder then finds sub-matrices (e.g., square sub-matrices) of the matrix A whose rank is equal to a rank of the matrix, and then determines error location polynomial (ELP) candidates from the sub-matrices, the basis and the private solution. The sub-matrices may be those in which the last column is a unique linear combination of the preceding columns. The decoder may use coefficients of each linear combination to combine the basis and the private solution into a corresponding ELP candidate. The ELP candidates may be determined by solving linear equations where a solution is performed with computation sharing where at each iteration, the submatrices that have more columns than rows, are converted into a Reduced Row Echelon form, and this computation is based on computations done in former iterations. The optimal ELP is then selected (e.g., by performing a Chien Search) from among the ELP candidates, and then the received word is corrected using the optimal ELP. The optimal ELP could instead be selected by performing Gaussian elimination operations on subsets of rows of the matrix A, where computation sharing is frequently used. The optimal ELP may be determined by processing and storing a plurality of matrices in temporary storage, where each of the matrices has a first property that all rows consisting of only zeroes are at the bottom; a second property that a leading coefficient of a non-zero row is always strictly to the right of a leading coefficient of a row above the non-zero row; a third property that a leading entry in each non-zero row is a one and referred to as a leading 1; a fourth property that each column containing the leading 1 has zeros in all its other entries; and a fifth property that a linear space spanned by its rows is equal to a linear space spanned by a subset of rows of the matrix. An iterative process may be used to determine the optimal ELP. An input of each iteration of the iterative process comprises a second matrix B with the five properties and a row v of the matrix A, and wherein said iteration comprises Gaussian elimination operations that are performed on matrix B and v, and wherein an output of said iteration comprises a matrix with the five properties, whose rows span the linear space that is equal to the linear space spanned by the rows of B and v. A depth first tree may be used to determine B and v. While the present inventive concept has been particularly shown and described with reference to the exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. | 62,849 |
11942966 | DETAILED DESCRIPTION Memory devices may use error detection and/or correction techniques (e.g., error control techniques) to increase a reliability of stored or communicated data. Some error control techniques used at memory devices may include single-bit error (SBE) correction (SEC) techniques, double-bit error (DBE) detection (DED) techniques, and SECDED techniques. In some cases, an external device that stores data at a memory device (e.g., a host device) may also use internal error control techniques to confirm the reliability of data received from the memory device. In some cases, the error control techniques used at a memory device may differ from those used at a host device. For example, a host device may use a more robust error control technique than a memory device. In some scenarios, the use of different error control techniques at the host device versus the memory device may result in additional errors. For example, if a memory device applies an SEC technique to data that includes two or more bit errors, the memory device may improperly flip a correct bit of the data, which may increase the quantity of errors in the data from two bit errors to three bit errors. In such cases, a host device using SECDED techniques may be unable to detect and/or correctly identify the bit errors in received data when the memory device transmits the data with three bit errors, while the host device may have been able to detect the two original bit errors (e.g., without the additional error introduced by the memory device). The present disclosure provides techniques to increase the reliability of data transferred between a memory device and host device. For example, the memory device may store, at a register (e.g., a mode register) of the memory device, an indication of whether the memory device has detected an error associated with error control operation using one or more syndrome bits associated with the error control operation. The memory device may store the indication in the register, which, for example, may be accessed by the host device. The memory device may determine to store the indication based on multiple criteria. For example, the memory device may determine that a communication protocol (e.g., a DSF+ protocol) for reporting information (e.g., error correction code (ECC) information, syndrome check information) to the host device is disabled, and that an error control configuration is enabled (e.g., a configuration for reporting the indication of the detected error). The memory device may store the indication of the detected error at the mode register based on the determination that the communication protocol for reporting information to the host device is disabled and that the error control configuration is enabled. The host device may request data from the mode register of the memory device and the memory device may output the indication of whether the error was detected in response to the poll. By accessing the indication of whether an error was detected at the memory device, the host device may avoid using data that includes a quantity of errors that would otherwise exceed the capability of the technique used by the host device—e.g., a host device using SECDED techniques may avoid using data that includes three-bit errors. Features of the disclosure are initially described in the context of a memory system. Features of the disclosure are further described herein in the context of syndrome match checkers and memory subsystems that support coordinated error correction. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to coordinated error correction. Although the disclosure generally describes a DRAM system, the techniques described herein may be applicable to any memory system that implements error control or detection/correction techniques. FIG.1illustrates an example of a system100that supports managing error control information using a register in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110). The system100may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the system100may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device110may be a component of the system operable to store data for one or more other components of the system100. At least portions of the system100may be examples of the host device105. The host device105may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host or a host device105. In some examples, the host device105may use an error correction technique. The host device105may request data from (e.g., poll) a register of the memory device110. The host device105may access an indication of whether an error was detected at the memory device110and avoid using data that includes a quantity of errors that would otherwise exceed the capability of the error correction technique used by the host device. A memory device110may be an independent device or a component that is operable to provide physical memory addresses/space that may be used or referenced by the system100. In some examples, a memory device110may be configurable to work with one or more different types of host devices. Signaling between the host device105and the memory device110may be operable to support one or more of: modulation schemes to modulate the signals, various pin configurations for communicating the signals, various form factors for physical packaging of the host device105and the memory device110, clock signaling and synchronization between the host device105and the memory device110, timing conventions, or other factors. The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110may act as a secondary-type or dependent-type device to the host device105(e.g., responding to and executing commands provided by the host device105through the external memory controller120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands. The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host device105may be coupled with one another using a bus135. The processor125may be operable to provide control or other functionality for at least portions of the system100or at least portions of the host device105. The processor125may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor125may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or an SoC, among other examples. In some examples, the external memory controller120may be implemented by or be a part of the processor125. The BIOS component130may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system100or the host device105. The BIOS component130may also manage data flow between the processor125and the various components of the system100or the host device105. The BIOS component130may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory. The memory device110may include a device memory controller155and one or more memory dies160(e.g., memory chips) to support a desired capacity or a specified capacity for data storage. Each memory die160(e.g., memory die160-a, memory die160-b, memory die160-N) may include a local memory controller165(e.g., local memory controller165-a, local memory controller165-b, local memory controller165-N) and a memory array170(e.g., memory array170-a, memory array170-b, memory array170-N). A memory array170may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store at least one bit of data. A memory device110including two or more memory dies160may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package. The device memory controller155may include circuits, logic, or components operable to control operation of the memory device110. The device memory controller155may include the hardware, the firmware, or the instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160. A local memory controller165(e.g., local to a memory die160) may include circuits, logic, or components operable to control operation of the memory die160. In some examples, a local memory controller165may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller155. In some examples, a memory device110may not include a device memory controller155, and a local memory controller165or the external memory controller120may perform various functions described herein. As such, a local memory controller165may be operable to communicate with the device memory controller155, with other local memory controllers165, or directly with the external memory controller120, or the processor125, or a combination thereof. Examples of components that may be included in the device memory controller155or the local memory controllers165or both may include receivers for receiving signals (e.g., from the external memory controller120), transmitters for transmitting signals (e.g., to the external memory controller120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other circuits or controllers operable for supporting described operations of the device memory controller155or local memory controller165or both. The external memory controller120may be operable to enable communication of one or more of information, data, or commands between components of the system100or the host device105(e.g., the processor125) and the memory device110. The external memory controller120may convert or translate communications exchanged between the components of the host device105and the memory device110. In some examples, the external memory controller120or other component of the system100or the host device105, or its functions described herein, may be implemented by the processor125. For example, the external memory controller120may be hardware, firmware, or software, or some combination thereof implemented by the processor125or other component of the system100or the host device105. Although the external memory controller120is depicted as being external to the memory device110, in some examples, the external memory controller120, or its functions described herein, may be implemented by one or more components of a memory device110(e.g., a device memory controller155, a local memory controller165) or vice versa. The components of the host device105may exchange information with the memory device110using one or more channels115. The channels115may be operable to support communications between the external memory controller120and the memory device110. Each channel115may be examples of transmission mediums that carry information between the host device105and the memory device. Each channel115may include one or more signal paths or transmission mediums (e.g., conductors) between terminals associated with the components of the system100. A signal path may be an example of a conductive path operable to carry a signal. For example, a channel115may include a first terminal including one or more pins or pads at the host device105and one or more pins or pads at the memory device110. A pin may be an example of a conductive input or output point of a device of the system100, and a pin may be operable to act as part of a channel. Channels115(and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channels115may include one or more command and address (CA) channels186, one or more clock signal (CK) channels188, one or more data (DQ) channels190, one or more other channels192, or a combination thereof. In some examples, signaling may be communicated over the channels115using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal). The memory device110may support an internal (e.g., on-die) error control scheme configured to detect and in at least some cases correct errors in data read from a memory array170and communicated to a host device105. Further, the memory device110may indicate to the host device105whether the error control scheme at the memory device110has detected an error associated with a set of data (e.g., by storing the indication so that the host device105may later poll the memory device110for the indication or the memory device110may later include the indication in an error report). For example, the memory device110may store the indication at a register of the memory device. AlthoughFIG.1generally illustrates a DRAM system, the techniques described herein with reference toFIG.1may be applicable to any memory system that implements error control techniques (e.g., such as NAND, FeRAM, RRAM, or other memory technologies). FIG.2illustrates an example of a memory die200that supports managing error control information using a register in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG.1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1. A memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell205may include a logic storage component, such as capacitor230, and a switching component235. The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss. The memory die200may include one or more access lines (e.g., one or more word lines210and one or more digit lines215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding or operation. Memory cells205may be positioned at intersections of the word lines210and the digit lines215. Operations such as reading and writing may be performed on the memory cells205by activating or selecting access lines such as one or more of a word line210or a digit line215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in either a two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell205. Accessing the memory cells205may be controlled through a row decoder220or a column decoder225. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on the received column address. Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235using a word line210. The capacitor230may be coupled with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215when the switching component235is deactivated, and the capacitor230may be coupled with digit line215when the switching component235is activated. The sense component245may be operable to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on the stored state. The sense component245may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell205. The sense component245may compare a signal detected from the memory cell205to a reference250(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., to an input/output255), and may indicate the detected logic state to another component of a memory device that includes the memory die200. The sense component245may include various transistors or amplifiers to detect and amplify a difference in the signals. The detected logic state of memory cell205may be output through an error control block265(e.g., ECC block, error control circuitry, or ECC circuitry) by I/O255. The error control block265may perform an error correction operation on the detected logic state of memory cell205and output data (e.g., the stored data or corrected data) via I/O255. In some other cases, the detected logic state of memory cell205may bypass error control block265and be output via I/O255. In some cases, the detected logic state of memory cell205may be output to both the error control block265and the I/O255. Here, the detected logic state of memory cell205may be output from the memory die200by the I/O255at a same time as error control block265performs an error correction operation on the detected logic state of memory cell205. In some cases, the sense component245may be part of another component (e.g., a column decoder225, row decoder220). In some cases, the sense component245may be in electronic communication with the row decoder220or the column decoder225. The error control block265may output error control information, which may represent information used to detect and/or correct errors introduced while data is stored at the memory die200. The error control information may include, for example, ECC information or parity bits, which may indicate whether an error exists in a set of associated data. Additionally or alternatively, the error control information may include syndrome check information (e.g., as described with reference toFIGS.3and4). The syndrome check information may represent a probability or likelihood that an error exists in a set of data and/or the ECC information, based on a comparison of a set of syndromes. The syndromes may represent an intermediary result in an error detection or error correction process, and may be used by the error control block265to estimate (e.g., determine a probability of) whether an error has occurred in the set of data and/or the ECC information. The local memory controller260may control the operation of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245, and error control block265). The local memory controller260may be an example of the local memory controller165described with reference toFIG.1. In some cases, one or more of the row decoder220, column decoder225, sense component245, and error control block265may be co-located with the local memory controller260. The local memory controller260may be configured to receive commands and/or data from an external memory controller105(or a device memory controller155described with reference toFIG.1), translate the commands and/or data into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to the external memory controller105(or the device memory controller155) in response to performing the one or more operations. The local memory controller260may generate row and column address signals to activate the target word line210and the target digit line215. The local memory controller260may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die200. In some cases, the local memory controller260may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory die200. During a write operation, a memory cell205of the memory die200may be programmed to store a desired logic state. In some cases, a plurality of memory cells205may be programmed during a single write operation. The local memory controller260may identify a target memory cell205on which to perform the write operation. The local memory controller260may identify a target word line210and a target digit line215in electronic communication with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215), to access the target memory cell205. The local memory controller260may apply a specific signal (e.g., voltage) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor230of the memory cell205, the specific state (e.g., charge) may be indicative of a desired logic state. During the write operation, the error control block265or the local memory controller260may generate error detection or correction information. For example, the error control block265may receive data from the host device as part of a write operation. The error control block265may determine or generate error detection or correction information associated with the data. In some cases, the error control block265may include error detection logic or may cause error detection logic (not shown) to perform the error detection operations described herein. The error control block265may cause the data and the error detection or correction information to be stored in one or more memory cells205as part of the write operation. The type of error detection or correction information generated by the error control block265may correspond to a type of error detection operation performed by the error control block265. For example, if the error control block265performs a SEC or SECDED error detection operation, the error control block265may generate a SEC or SECDED codeword as part of the write operation. The SEC or SECDED codewords may correspond to error detection information used by the error control block265to detect and/or correct errors within the data when performing a SEC or SECDED error detection operation respectively. Alternatively, if the error control block265performs an error detection operation based on parity bits, the error control block265may generate parity bits as part of the write operation. The local memory controller260may control the accessing of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host device105based on performing the one or more operations. The local memory controller260may generate row signals and column address signals to activate the target word line210and the target digit line215. The local memory controller260may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200. The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller260in response to various access commands (e.g., from a host device105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205. During the read operation, the error control block265may retrieve data and associated error detection or correction information from the array of memory cells205. The error control block265may perform an error correction operation based on the data and the error detection or correction information. Performing an error correction operation at the memory device (e.g., by the error control block265or the local memory controller260) may improve the reliability of the memory device. The error control block265may be configured to perform a single type of error detection operation (e.g., a SEC or SECDED error detection operation, an error detection operation based on parity bits) or may be configured to perform a combination of error detection operations (e.g., an error detection operation based on parity bits and a SEC or SECDED error detection operation). In some memory architectures, accessing the memory cell205may degrade or destroy the logic state stored in a memory cell205. For example, a read operation performed in DRAM architectures may partially or completely discharge the capacitor of the target memory cell. The local memory controller260may perform a re-write operation or a refresh operation to return the memory cell to its original logic state. The local memory controller260may re-write the logic state to the target memory cell after a read operation. In some cases, the re-write operation may be considered part of the read operation. Additionally, activating a single access line, such as a word line210, may disturb the state stored in some memory cells in electronic communication with that access line. Thus, a re-write operation or refresh operation may be performed on one or more memory cells that may not have been accessed. The memory die200may support an internal (e.g., on-die) error control scheme configured to detect and in at least some cases correct errors in data read from a memory array170, as described with reference toFIG.1. In some cases, the error control scheme may be implemented by the error control block265or some other on-die error control component (e.g., implemented by error control circuitry or ECC component). Further, the memory die200may indicate to a host device whether the error control scheme at the memory die200has detected an error associated with a set of data (e.g., by storing the indication so that the host device may poll the memory die200for the indication or so that the memory die200may include the indication in an error report). For example, the memory die200may store the indication at a register of the memory device. AlthoughFIG.2generally illustrates a DRAM system, the techniques described herein with reference toFIG.2may be applicable to any memory system that implements error control techniques. FIG.3illustrates an example of error control circuitry300that supports managing error control information using a register in accordance with examples as disclosed herein. The error control circuitry300may be included in a memory device and may be configured to determine and indicate whether an on-die error control component (e.g., match circuit315) detects an error associated with data stored in a memory array (e.g., an error in the data, or an error in parity bits associated with the data) and requested by a host device. Error control circuitry300may be configured to detect errors in data stored in a memory cell. In some cases, error control circuitry300(e.g., or another component of the memory device) may also be configured to correct errors in data by flipping a data bit that has been identified as being corrupted—e.g., changing a corrupted data bit from a “1” to a “0,” or vice versa. In some cases, error control circuitry300may be configured to detect SBEs in requested data and to correct SBEs in requested data—e.g., error control circuitry300may be configured to use an SEC technique. In some other cases, error control circuitry300may be configured to detect DBE and to correct SBEs in requested data—e.g., error control circuitry300may be configured to use a SECDED technique. In other cases, error control circuitry300may be configured to detect triple-bit errors (TBEs). The examples described herein are merely illustrative, and error control circuitry300may be configured to detect up to any first quantity of errors and correct up to any second quantity of errors (that may be different than or the same as the first quantity). Error control circuitry300may be further configured to provide altered data—e.g., after performing one or more error correction techniques on the data—to an external device (e.g., a host device). The techniques described herein may be applied to an ECC scheme configured to detect and/or correct any quantity of errors, and any specific quantities used herein are purely for the sake of illustration and are non-limiting. Error control circuitry300may include a storage syndrome circuit305, an access syndrome circuit310, and a match circuit315. When error control circuitry300is configured to detect DBEs, storage syndrome circuit305, access syndrome circuit310, and match circuit315may each be configured to output an additional syndrome bit compared to when error control circuitry300is configured to implement an SEC scheme. Storage syndrome circuit305may be configured to generate one or more syndromes (e.g., an ECC) for data before storage of the data within a memory array. In some cases, the syndrome(s) generated by storage syndrome circuit305may be referred to as a “stored ECC,” “stored syndromes,” or stored “codeword.” Access syndrome circuit310may be configured to generate one or more other syndromes (e.g., another ECC) after data is read from the memory array—e.g., when the data stored in the memory array is requested by an external device. The syndrome(s) generated by access syndrome circuit310may be referred to as a “calculated ECC,” “calculated syndromes,” or “calculated codeword.” In some cases, access syndrome circuit310may use a same algorithm as storage syndrome circuit305to generate the calculated syndrome(s). Match circuit315may be configured to compare the stored syndrome(s) and the calculated syndrome(s). In some cases, match circuit315may compare the stored and calculated syndromes by performing exclusive or (XOR) operations on the corresponding bits of the stored and calculated syndromes. If each bit of the stored and calculated syndromes is the same—e.g., if the stored and calculated syndromes match—match circuit315may output all zeros. Otherwise, if the stored and calculated syndromes do not match, match circuit315may output one or more non-zero values (e.g., may output a respective non-zero value for each syndrome value or ECC value that does not match). In some cases, match circuit315may also be configured to output a location of a corrupted bit in a set of data or in an associated stored syndrome based on the comparison of the stored syndrome(s) and the calculated syndrome(s). For example, when match circuit315outputs a non-zero value, each output of match circuit may be used to represent a position of a respective bit in the stored codeword that is identified by the memory device as being corrupted—e.g., the outputs of match circuit315may represent up to 256 different bit positions. Error match circuit315may be configured to indicate whether match circuit315detected an error in or otherwise associated with data requested from the memory array. In some cases, if the output of match circuit315includes all zero values, match circuit315may output a first signal (e.g., a virtual ground voltage) that indicates a match (or a “match signal”). And if the output of match circuit315includes one or more non-zero values, match circuit315may output a second signal (e.g., a supply voltage) that indicates a mismatch (or a “mismatch signal”). In some cases, match circuit315outputs a Boolean “false” when match circuit315outputs all zero values (which may be represented by a virtual ground supply voltage), indicating a match. And if the output of match circuit includes at least one non-zero value, match circuit315outputs a Boolean “true”, indicating a mismatch. In other cases, if the output of match circuit315includes all zero values or less than some threshold quantity of non-zero values (e.g., includes a single non-zero value), match circuit315outputs a “false,” indicating a match or substantial match. In some cases, one or some other quantity of non-zero values below a threshold quantity may indicate that an error occurred in the syndrome bits and not in the stored data. And if the output of match circuit315includes a quantity of non-zero values that satisfies the threshold (e.g., two or more), match circuit315outputs as “true”, indicating a mismatch. In some cases, error control circuitry300may overwrite the stored syndrome(s) with the calculated syndrome(s) after identifying that one non-zero value was output by match circuit315and the corresponding data may be transmitted to a device that requested the data. The output of match circuit315may be signaled over memory error line325. In some cases, the output of match circuit315is signaled over memory error line325as a “memory syndrome flag.” In some cases, memory error line325may transmit an output of match circuit, as a memory syndrome flag, to a register (e.g. a mode register), which may be accessible to one or more external devices. The output of the match circuit may be stored at the register and accessed when requested (e.g., polled) by an external device (e.g., a host device). For example, the memory device may receive a command from a host device for reading information stored at the register (e.g., a register read command). The memory device may output the information (e.g., at least some information) stored at the register based on the command. In other cases, the data stored at the register may be provided to an external device during some error reporting procedures. In some examples, when the error control scheme supported by error control circuitry300is overpowered by data including more bit errors than a maximum quantity that the error control scheme can detect or correct, error control circuitry300may improperly alias (e.g., flip or otherwise alter) a bit having a correct value or otherwise introduce or fail to correct an error in a set of data read from the memory array. For example, when error control circuitry300is configured with an SEC scheme, error control circuitry300may detect an SBE in requested data that actually includes two or more bit errors. In such cases, error control circuitry300may unsuccessfully attempt to correct the detected error by flipping an uncorrupted bit in the requested data at a bit position indicated by match circuit315—e.g., turning a two-bit error into a three bit error (which may be referred to as “aliasing”). In some cases, error control circuitry300may provide the altered data to an external device (e.g., a host device) that requested the data. When error control circuitry300causes aliasing of data requested from a device, the external device (e.g., a host device) may be prevented from detecting errors in requested data that otherwise would have been detectable by the external device—e.g., an external device using a SECDED scheme that would have detected a DBE in requested data may be unable to reliably detect the TBE in the requested data caused by error control circuitry300. By identifying and indicating that error control circuitry300detected and attempted to correct an error (e.g., as indicated and stored by the memory device in the register), the external device may determine whether the memory device detected an error, attempted to correct an error, or otherwise whether aliasing may have occurred as a result of an attempted correction by error control circuitry300, as discussed in more detail herein and with respect toFIG.4. FIG.4illustrates an example of a memory system400that supports managing error control information using a register in accordance with examples as disclosed herein. Memory system400may include a memory device405and a host device425. Memory device405may be configured to store data—e.g., memory device405may be configured to store application or other data for host device425. Memory device405may include a data bus450, circuitry460, error control circuitry415, a register410, and a register420. Error control circuitry415may be configured similarly, or the same, as error control circuitry300as described with reference toFIG.3, for example, to detect and/or correct errors in data requested from host device425before delivering the requested data to host device425. Error control circuitry415may be configured to store, at register410, an indication of whether an error was detected in the requested data and/or an address associated with the requested data. Registers of memory device405(e.g., register410and register420) may each include multiple bits, each bit corresponding to a location where data or information may be stored within the corresponding register. For example, memory device405may store bit values in various locations of register410and register420, where each location may be associated with a corresponding type of information (e.g., configuration information, error control information, error reporting information). Memory device405may store values (e.g., binary values) in registers410and420, which may indicate or represent information associated with the corresponding location in the register. For example, memory device405may store a value in a first bit (e.g., first location) of register420indicating whether a communication protocol is enabled or disabled and may store a value in a second bit (e.g., second location) of register420indicating whether an error control configuration is enabled or disabled. Similarly, memory device405may store a value in a first bit (e.g., first location) of register410indicating error control information (e.g., indicating whether memory device405detected and/or corrected an error in a set of data, based on a result of a syndrome check operation). Memory device405may configure register410to operate in a mode (e.g., configuration) selected from a set of modes. For example, memory device405may configure register410to operate in a first mode (e.g., a syndrome check mode register read (MRR) mode, which may be referred to as S-CheckMRR) or a second mode (e.g., a master error log mode). Memory device405may configure register410to operate in one of these modes (e.g., among other modes) based on a communication protocol (e.g., a communication protocol for indicating error control information between memory device405and host device425) and an error control configuration (e.g., a syndrome check configuration). The communication protocol may specify whether memory device405is configured to transmit error control information (e.g., syndrome check information associated with an error control operation) to host device425(e.g., directly transmit, upon determining the error control information). If the communication protocol is enabled, error control circuitry415may transmit error control information, such as syndrome check information or results, to host device425. For example, error control circuitry415may transmit the error control information to host device425via data bus450or via any other communication method or channel (e.g., via circuitry460and circuitry455). In other examples, the communication protocol may be disabled and error control circuitry415may not transmit the error control information (e.g., syndrome check information) to host device425(e.g., may not directly or immediately transmit the error control information). For example, error control circuitry415may store a value indicative of the error control information in register410. Host device425may configure memory device405to operate according to the communication protocol, or to not operate according to the protocol, for example, during a startup or configuration procedure for the host device425and memory device405. Memory device405may store a value in register420, indicating whether the communication protocol is enabled or disabled (e.g., in a first bit of register420), based on the configuration indicated by host device425. The error control configuration may specify a method for detecting and/or correcting errors. For example, an error control configuration may be a syndrome check configuration, an error log configuration, a parity check configuration, or some other error control configuration. An example of an error control configuration (e.g., a syndrome check configuration) may be implemented by error control circuitry300as described with reference toFIG.3. Host device425may configure memory device405to operate according to the error control configuration, or to not operate according to the error control configuration, for example, during a startup or configuration procedure for the host device425and memory device405. Memory device405may store a value in register420, indicating whether the error control configuration is enabled or disabled (e.g., in a second bit of register420). When the error control configuration is enabled, memory device405may perform one or more error control procedures associated with or indicated by the error control configuration (e.g., may perform a syndrome check as described with reference toFIG.3). When the error control configuration is disabled, memory device405may refrain from performing the one or error control procedures (e.g., a syndrome check). Memory device405may configure register410to operate in the first mode (e.g., the syndrome check MRR mode), or the second mode (e.g., the master error log mode) based on the values stored in register420. The first mode may represent a mode for storing error control information (e.g., syndrome check information) in register410. The second mode may represent a mode for transmitting error control information (e.g., syndrome check information) to host device425. In some examples, the communication protocol for transmitting error control information to host device425may be disabled and the error control configuration (e.g., syndrome check) may be enabled. As such, memory device405(e.g., circuitry460) may configure register410to operate in a syndrome check MRR mode (e.g., S-CheckMMRmode or first mode) based on the values in register420indicating that the communication protocol (e.g., for transmitting error control information to host device425) is disabled and the error control configuration (e.g., syndrome check) is enabled. In some examples, circuitry460may determine whether the communication protocol is disabled and whether the error control configuration (e.g., syndrome check) is enabled based on the values stored in register420. Circuitry460may configure register410to operate in the first mode (e.g., the syndrome check MRR mode), or the second mode (e.g., the master error log mode), based on the values stored in register420. As described herein, circuitry460may represent any combination of circuitry within memory device405, such as communication and control circuitry. Memory device405may additionally operate according to one or more operational modes, for example, based on whether the one or more operational modes are enabled or disabled (e.g., by host device425such as during a startup or configuration procedure). In some cases, memory device405may operate according to a first operational mode, such as a master error log mode. In the master error log mode, memory device405may record one or more errors in an error log. The one or more errors may be associated with operation of one or more components of memory device405. Memory device405may additionally or alternatively operate according to a second operational mode, which may include indicating, by memory device405, whether one or more data pins of memory device405are communicating valid data. Memory device405may further configure register410to operate in the first mode or the second mode based on whether the first operational mode and/or second operational mode of memory device405is enabled or disabled. For example, memory device405may configure register410to operate in syndrome check MRR mode based on determining that the first and second operational modes of memory device405are both disabled. In some examples, circuitry460may determine whether the one or more operational modes are enabled or disabled. For example, circuitry460may determine whether the first operational mode and the second operational mode are enabled or disabled. In some examples, memory device405may store, at a bit or location within register410, an indication of an output of the error control operation performed by error control circuitry415. For example, error control circuitry415may perform one or more syndrome check operations (e.g., as described with reference toFIG.3) and may store a result of, or an indication of an output of, the one or more syndrome check operations at a bit or location within register410(e.g., when operating in syndrome check MRR mode or the first mode). The bit or location within register410may store a value corresponding to the result of a syndrome check operation. For example, error control circuitry415may convey an output signal to register410and register410may store an indication of the output signal using the bit or location. The output signal may be a memory syndrome flag (e.g., an indication of whether an error was corrected by memory device405) as described with reference toFIG.3. For example, the bit or location may store a value of ‘0’ if no errors were corrected by memory device405(e.g., if the syndrome check operation indicated that the syndromes matched) and may store a value of ‘1’ if at least one error was corrected by memory device405(e.g., if the syndrome check operation indicated that the syndromes did not match). As described herein, register410may operate according to a mode selected from a set of modes. For example, register410may operate according to a first mode (e.g., a syndrome check MRR mode) or a second mode (e.g., a master error log mode). In the master error log mode, memory device405may indicate that one or more errors associated with operation of one or more components of memory device405are recorded in an error log. For example, while operating in the master error log mode, register410may store one or more values corresponding to the error log at one or more bits of register410, as shown in Tables 1A and 1B. Tables 1A and 1B may correspond to examples of the different modes of register410, and the respective values of bits or locations of register410that may correspond to the different modes. TABLE 1AModeBit[7]Bit[6]Bit[5]Bit[4]Master Error LogFuse LoadUnintendedmBISTTemperatureTest ModeSensorS-CheckMRRFuse LoadUnintendedmBISTTemperatureTest ModeSensor TABLE 1BModeBit[3]Bit[2]Bit[l]Bit[0]Master Error LogRegister Bit[7]HealthCA ParityMasterMonitoringError LogS-CheckMRRRegister Bit[7]HealthCA ParitySyndromeMonitoringCheck As shown in Tables 1A and 1B, register410may operate according to a first or a second mode, such as a syndrome check MRR mode (e.g., S-CheckMRR) or a master error log mode. Each bit of the register410(e.g., bits 0 through 7) may store information related to error control and may be based on the corresponding mode of the register410. For example, a first bit (e.g., Bit[0]) may store a value corresponding to an error control operation. While operating in S-CheckMRRmode, Bit[0] may store a syndrome flag, which may indicate a result of a syndrome check operation and may be accessible to external devices. In some examples, the output of error control circuitry415may be stored in Bit[0] of register410and accessed when requested (e.g., polled) by an external device (e.g., host device425). While operating in the master error log mode, Bit[0] may store information associated with the log of one or more errors. Bit[1] through Bit[7] of register410may store additional values corresponding to error information, for example, when operating in a master error log mode. For example, Bit[1] through Bit[7] may each store a respective binary value corresponding to detection of a defined error detected during operation of memory device405. A binary value of ‘1’ may represent that an error condition has occurred for the associated error, while a binary value of ‘0’ may represent that an error condition has not occurred. For example, memory device405may use Bit[1] through Bit[7] to indicate whether an error has been detected in CA Parity, in health monitoring information, via a temperature sensor, in a fuse load, in a location or bit (e.g., Bit[7]) of another register, or if an unintended test mode has been detected, among other examples. Data bus450may be configured to convey data stored in memory device405to error control circuitry430(e.g., of the host device425). In some cases, data bus450may deliver data after a request (e.g., a read command) is received from host device425for the data. In some examples, data bus450may deliver the requested data after the requested data is processed by error control circuitry415—e.g., after the syndrome match checker performs a process to detect and correct errors in the requested data. In some examples, register410may store an indication of a syndrome check flag that indicates whether error control circuitry415detected or corrected an error in data requested by host device425—e.g., by indicating a match or mismatch in the syndromes—and/or an address associated with the requested data. Host device425may request the indication of the syndrome check flag from memory device405. For example, circuitry455of host device425may transmit a request to circuitry460of memory device405(e.g., a register read command). In response to the request (e.g., register read command), circuitry460may access the indication of the syndrome check flag from register410and transmit the indication to circuitry455. In some cases, the indication may include one or more bits. The bit(s) included in the indication may indicate that each of a first set of syndromes match corresponding syndromes of a second set of syndromes or that a mismatch has been detected between the different sets of syndromes. In some cases, the memory device405(e.g., circuitry460) may reset the information stored at register410based on receiving a register read command from the host device425. Additionally or alternatively, memory device405(e.g., circuitry460) may reset the information stored at register410based on receiving a command (e.g., a reset command) from the host device425, indicating for the memory device405to reset the register410. Resetting the information stored at the register410may include setting the values of the register to respective default values (e.g., to values of ‘0’). For example, the memory device405(e.g., circuitry460) may set the indication of the syndrome check flag to a default value that indicates that the different syndromes match. Host device425may be configured to access data stored in memory device405to support the functioning of an application. Error control circuitry430may be configured to detect errors in data received from memory device405—e.g., in data received over data bus450—and to indicate whether an error was detected in received data over channel error line435. Error control circuitry430may also be configured to correct errors detected in received data. In some cases, error control circuitry430may be configured similarly to error control circuitry300described with reference toFIG.3. among other examples. For example, error control circuitry430may support in-line ECC by host device425. In some cases, error control circuitry430may include an initial syndrome circuit that computes an initial ECC for application data before host device425writes the application data and the initial ECC to memory device405(e.g., as part of a single data burst, which may alternatively be referred to as a data packet, data package, or data codeword). In some cases, error control circuitry430may also include an access syndrome circuit that computes a calculated ECC for the application data after receiving the data from memory device405(e.g., by parsing a received data burst corresponding to the previously written data burst to obtain a first subset of the data burst corresponding to the previously written application data (payload) and a second subset of the data burst corresponding to parity information for the first subset that was previously calculated (generated) by host device425(initial ECC for the payload)). Additionally or alternatively, error control circuitry430may include a match circuit to compare the initial and calculated ECCs to determine there is an error in the received data. as well as an error indication circuit to indicate whether there is an error in the received data. In some cases, an error correction/detection circuit included in error control circuitry430may be configured to detect DBEs and to correct single errors in received data—e.g., error control circuitry430may use SECDED techniques—and each of the stored syndrome circuit, the access syndrome circuit, and the match circuit may be configured to output an additional syndrome bit. Channel error line435may be configured to convey an output signal generated by error control circuitry430to logic component440. In some examples, channel error line435may convey a “channel syndrome flag” that indicates whether error control circuitry430detected an error in the received version of data requested from memory device405. In some cases, channel error line435is a conductive trace. In other cases, channel error line435is a wireless link. Similarly, logic component440may be coupled with circuitry455, which may support communication of a “memory syndrome flag” (e.g., as received by circuitry455from the memory device405, based on the register read) from the circuitry455to logic component440. Logic component440may be configured to determine whether one or both of error control circuitry430or error control circuitry415detect an error in a processed set of data. In some cases, logic component440outputs a multi-bit error (MBE) flag if a memory syndrome flag (e.g., output by error control circuitry415or retrieved from register410) and channel syndrome flag (e.g., output by error control circuitry430) indicate that an error was detected. For example, logic component440may output an MBE flag that indicates an MBE has occurred when a memory syndrome flag indicates a mismatch and a channel syndrome flag indicates a mismatch. Data error line445may be configured to convey an output signal generated by logic component440. In some examples, logic component440may output an MBE flag that indicates that the requested data stored in memory device405includes multiple corrupted bits. One or more other components of the host device425may, for example, use the output on data error line445to determine whether to use, correct, or discard data received from the memory device. For example, if a correctable MBE has occurred, the host device425may correct the MBE. In other examples, if an uncorrectable MBE (e.g., a TBE or higher) has occurred, the host device425may determine to discard the data. In some other examples, if no errors have occurred, or if the host device425determines that the errors were detected or corrected, the host device425may use the data. Host device425may use the outputs of error control circuitry415, register410, error control circuitry430, and logic component440to detect errors (including MBEs) in received data, as shown in Table 2. Table 2 may correspond to an example where memory device405uses SEC techniques and host device425uses SECDED techniques, although other error control techniques are possible for both memory device405and host device425without departing from the scope of the present disclosure (e.g., host device425may use double error correction (DEC), triple error detection (TED), triple error correction (TEC)). TABLE 2State of RequestedData before ECC atMemory SECHost SECDEDMulti-Bitthe Memory DeviceSyndromeFlagSyndrome FlagError FlagHost Error DetectionNo Error000Detects No Error in Received DataSBE100Detects SBE CorrectionDBE w/out Aliasing111Detects DBE in Received DataDBE w/Aliasing111Detects MBE in Received Data-e.g.,won't treat detected error as SBEMBE111Detects MBE in Received Data-e.g.,won't treat odds as SBE In some examples, as shown in Table 2, requested data (e.g., before ECC at memory device405) may include an SBE, a DBE without aliasing, a DBE with aliasing, an MBE, or no error. If the requested data includes no error, host device425may detect that there is no error in received data. If the requested data includes an SBE, host device425may detect that the SBE was corrected by memory device405(e.g., based on the “memory syndrome flag” received from the register410of the memory device). If the requested data includes a DBE without aliasing, host device425may detect the DBE in the received data (e.g., based on the “memory syndrome flag”). If the requested data includes a DBE with aliasing, host device425may detect an MBE in received data (e.g., based on the “memory syndrome flag”) and may not treat the detected error as an SBE. If the request data includes an MBE, host device425may detect an MBE in received data and may not treat the MBE as an SBE. For example, host device425may detect higher order errors (e.g., DBEs and MBEs) that may have otherwise been undetectable, because the memory device405may indicate whether an error was detected or corrected at the memory device405(e.g., using error control circuitry415). In some examples, when a DBE or MBE is detected, host device425may determine not to use data associated with the errors. Host device425may also use the outputs of register410, error control circuitry430, and logic component440to manage the processing of data received from memory. In some examples, after receiving an indication from register410that no error was detected in requested data, host device425may forego performing an error detection procedure of the received data. For example, if error control circuitry415uses a SEC scheme and/or link protection (e.g., cyclic redundancy check (CRC) or link ECC) is being run for transmissions of data over the memory channel and error control circuitry430uses a SECDED scheme, host device425may refrain from performing ECC in some scenarios, as depicted in Table 3. TABLE 3State of RequestedData before ECC atMemory SECHost SECDEDMulti-BitHost ECC Calculationthe Memory DeviceSyndrome FlagSyndrome FlagErrorFlagDecision (Detection)No Error000Doesn't Calculate ECC (No Error)SBE100Doesn't Calculate ECC (No Error)DBE w/out Aliasing111Calculates ECC (DBE Detected)DBE w/Aliasing111Calculates ECC (MBE Detected)MBE111Calculates ECC (MBE Detected) In some cases (e.g., if host device425uses a syndrome match checker), host device425further refrains from performing an ECC calculation if the memory syndrome flag indicates that an error of a defined type (e.g., an SBE) was corrected. In some examples, as shown in Table 3, requested data (e.g., before ECC at memory device405) may include an SBE, a DBE without aliasing, a DBE with aliasing, a MBE, or no error. If the requested data includes no error or an SBE (e.g., as indicated by the “memory syndrome flag”), host device425may not calculate an ECC. If the requested data includes a DBE without aliasing (e.g., as indicated by the “memory syndrome flag” and the “host syndrome flag” together), host device425may calculate an ECC and detect the DBE in the received data. If the requested data includes a DBE with aliasing (e.g., as indicated by the “memory syndrome flag” and the “host syndrome flag” together), host device425may calculate an ECC and detect an MBE in received data. If the requested data includes an MBE, host device425may detect an MBE in received data (e.g., as indicated by the “memory syndrome flag” and the “host syndrome flag” together). Based on the indication of the “memory syndrome flag,” host device425may detect higher order errors (e.g., DBEs and MBEs) that may have otherwise been undetectable and forego performing other error detection procedures (e.g., unnecessary procedures). In some examples, when a DBE or MBE is detected, host device425may determine not to use data associated with the errors. In another example, if error control circuitry415uses a SECDED scheme and/or link protection (e.g., CRC or link ECC) is being run for transmissions of data over the memory channel and error control circuitry430uses a SECDED scheme, host device425may refrain from performing ECC in some scenarios, as depicted in Table 4. TABLE 4State of RequestedData before ECC atMemory SECDEDHost SECDEDMulti-BitHost ECC Calculationthe Memory DeviceSyndromeFlagSyndrome FlagError FlagDecision (Detection)No Error000Doesn't Calculate ECC (No Error)SBE100Calculates ECC (Corrected SBE Detected)DBE111Calculates ECC (DBE Detected)MBE111Calculates ECC (MBE Detected) In some cases, host device425further refrains from performing an ECC calculation if the memory syndrome flag indicates that an error of a defined type (e.g., an SBE) was corrected. In some examples, as shown in Table 4, requested data (e.g., before ECC at memory device405) may include an SBE, a DBE, an MBE, or no error. If the requested data includes no error or an SBE (e.g., as indicated by the “memory syndrome flag”), host device425may not calculate an ECC. If the requested data includes a DBE (e.g., as indicated by the “memory syndrome flag” and the “host syndrome flag” together), host device425may calculate an ECC and detect the DBE in the received data. If the requested data includes an MBE (e.g., as indicated by the “memory syndrome flag” and the “host syndrome flag” together), host device425may detect an MBE in received data. Based on the indication of the syndrome flag from memory device405, host device425may detect higher order errors (e.g., DBEs and MBEs) that may have otherwise been undetectable and forego performing other error detection procedures (e.g., unnecessary procedures). In some examples, when a DBE or MBE is detected, host device425may determine not to use data associated with the errors. Host device425may also use the outputs of register410, error control circuitry430, and logic component440to manage the storage of data in memory. In some examples, after identifying that data stored in memory device405includes multiple-bit errors, host device425may blacklist the memory address associated with the data. That is, host device425may indicate to memory device405that no application data for host device425is to be stored at the blacklisted memory address in a memory array of memory device405. Additionally or alternatively, host device425or memory device405may use the information to perform “smart scrubbing” of the memory array in memory device405—an error correction technique that involves periodically reading the contents of a memory array, performing an error correction on the contents of the memory array, and rewriting data that is identified as being corrupted with the correct version of the data may be referred to as “scrubbing.” That is, host device425may trigger memory device405to—or memory device405on its own—may scrub (e.g., only) data located at the memory addresses that have been identified by and/or indicated by memory device405as being corrupted. The scrubbing procedure may skip (e.g., ignore) pages or other sets of memory cells not associated with an identified error during a relevant time period (e.g., over the entire operation history of the device, or after a last scrubbing procedure). In some examples, host device425may not include error control circuitry430— e.g., host device425may not generate a host syndrome flag. In such cases, host device425may use the output of register410to detect, or aid in the detection of, errors in received data. For example, if error control circuitry415uses a SEC scheme and/or link protection (e.g., CRC or link ECC) is being run for transmissions of data over the memory channel and host device425does not include error control circuitry430, host device425may refrain from performing ECC in some scenarios, as depicted in Table 5. TABLE 5State of RequestedData before ECC atMemory SECHost SECDEDMulti-BitHost ECC Calculationthe Memory DeviceSyndrome FlagSyndrome FlagError FlagDecision (Detection)No Error0N/AN/ADoesn't Calculate ECC (No Error)SBE1N/AN/ACalculates ECC (No Error Detected)DBE w/out Aliasing1N/AN/ACalculates ECC (DBE Detected)DBE w/Aliasing1N/AN/ACalculates ECC (Detects SBE)MBE1N/AN/ACalculates ECC (Treats Odds as SBE) In some examples, as shown in Table 5, requested data (e.g., before ECC at memory device405) may include an SBE, a DBE without aliasing, a DBE with aliasing, a MBE, or no error. If the requested data includes no error, host device425may not calculate an ECC. If the requested data includes an SBE, host device425may calculate an ECC and may not detect an error. If the requested data includes a DBE without aliasing, host device425may calculate an ECC and detect the DBE in the received data. If the requested data includes a DBE with aliasing, host device425may calculate an ECC and detect an SBE in received data. If the request data includes an MBE, host device425may calculate an ECC and may treat odds as an SBE. Host device425may detect higher order errors (e.g., DBEs and MBEs) that may have otherwise been undetectable. In some examples, when an error is detected, host device425may determine not to use data associated with the errors. In another example, if error control circuitry415uses a SECDED scheme and/or link protection (e.g., CRC or link ECC) is being run for transmissions of data over the memory channel and host device425does not include error control circuitry430, host device425may refrain from performing ECC in some scenarios, as depicted in Table 6. TABLE 6State of RequestedData before ECC atMemory SECDEDHost SECDEDMulti-BitHost ECC Calculationthe Memory DeviceSyndrome FlagSyndrome FlagError FlagDecision (Detection)No Error0N/AN/ADoesn't Calculate ECC (No Error)SBE1N/AN/ACalculates ECC (No Error Detected)DBE1N/AN/ACalculates ECC (DBE Detected)MBE1N/AN/ACalculates ECC (Treats Odds as SBE) In some examples, as shown in Table 6, requested data (e.g., before ECC at memory device405) may include an SBE, a DBE, an MBE, or no error. If the requested data includes no error, host device425may not calculate an ECC. If the requested data includes an SBE, host device425may calculate an ECC and may not detect an error. If the requested data includes a DBE, host device425may calculate an ECC and detect the DBE in the received data. If the request data includes an MBE, host device425may calculate an ECC and may treat odds as an SBE. Host device425may detect higher order errors (e.g., DBEs and MBEs) that may have otherwise been undetectable. In some examples, when an error is detected, host device425may determine not to use data associated with the errors. FIG.5shows a block diagram500of a memory device520that supports managing error control information using a register in accordance with examples as disclosed herein. The memory device520may be an example of aspects of a memory device as described with reference toFIGS.1through4. The memory device520, or various components thereof, may be an example of means for performing various aspects of managing error control information using a register as described herein. For example, the memory device520may include an error control component525, a syndrome match component530, a register access component535, a device configuration component540, a register configuration component545, a register read component550, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses). The error control component525may be configured as or otherwise support a means for generating, at a memory device, a first set of multiple syndromes based on receiving data for storage at the memory device, the first set of multiple syndromes associated with an error control operation for the received data, each syndrome of the first set including error correction or error detection syndrome bits. In some examples, the error control component525may be configured as or otherwise support a means for generating, at the memory device, a second set of multiple syndromes based on retrieving the data, the second set of multiple syndromes associated with the retrieved data and the error control operation, each syndrome of the second set including error correction or error detection syndrome bits. The syndrome match component530may be configured as or otherwise support a means for determining whether the first set of multiple syndromes matches the second set of multiple syndromes based on comparing the first set of multiple syndromes and the second set of multiple syndromes. The register access component535may be configured as or otherwise support a means for storing, at a register of the memory device, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that a first communication protocol for reporting information to a host device is disabled. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that a first error control configuration is enabled for reporting a comparison of syndromes generated by the memory device according to the error control operation, where storing the indication at the register is based on determining that the first communication protocol is disabled and the first error control configuration is enabled. In some examples, the register access component535may be configured as or otherwise support a means for accessing a second register of the memory device that stores a status of the first communication protocol and a status of the first error control configuration, where determining that the first communication protocol is disabled and the first error control configuration is enabled is based on accessing the second register. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that an operational mode of the memory device is disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where storing the indication at the register is based on determining that the operational mode is disabled. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that a second operational mode of the memory device is disabled, the second operational mode for indicating whether one or more data pins of the memory device are communicating valid data, where storing the indication at the register is based on determining that the second operational mode is disabled. In some examples, the register read component550may be configured as or otherwise support a means for receiving, from a host device, a command for reading information stored at the register. In some examples, the register read component550may be configured as or otherwise support a means for outputting, to the host device, the indication based on receiving the command. In some examples, the register access component535may be configured as or otherwise support a means for resetting the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. In some examples, the register access component535may be configured as or otherwise support a means for receiving, from a host device, a command for resetting information stored at the register. In some examples, the register access component535may be configured as or otherwise support a means for resetting the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. In some examples, the register is configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting the indication of whether the first set of multiple syndromes matches the second set of multiple syndromes and a second mode for recording in an error log one or more errors associated with operation of one or more components of the memory device. In some examples, the indication includes one or more bits and a value of the one or more bits indicates that each of the first set of multiple syndromes match corresponding syndromes of the second set of multiple syndromes. In some examples, the indication includes one or more bits and a value of the one or more bits indicates that at least one of the first set of multiple syndromes does not match a corresponding syndrome of the second set of multiple syndromes. The device configuration component540may be configured as or otherwise support a means for determining, at a memory device, that a first communication protocol for reporting information to a host device is enabled or disabled. In some examples, the device configuration component540may be configured as or otherwise support a means for determining, at the memory device, that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled or disabled. The register configuration component545may be configured as or otherwise support a means for configuring a register of the memory device to operate in a first mode based on determining that the first communication protocol is disabled and the first error control configuration is enabled. In some examples, the register access component535may be configured as or otherwise support a means for accessing a second register of the memory device that stores a status of the first communication protocol and a status of the first error control configuration, where determining that the first communication protocol is enabled and the first error control configuration is enabled is based on accessing the second register. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that an operational mode of the memory device is disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where configuring the register to operate in the first mode is based on determining that the operational mode is disabled. In some examples, the device configuration component540may be configured as or otherwise support a means for determining that a second operational mode of the memory device is disabled, the second operational mode for indicating whether one or more data pins of the memory device are communicating valid data, where configuring the register to operate in the first mode is based on determining that the second operational mode is disabled. In some examples, the first mode indicates a location within the register for storing one or more bits indicative of a result of an error control operation performed by the memory device. In some examples, the register is configured to operate in a mode selected from a set of modes, the set of modes including the first mode and a second mode for recording in an error log one or more errors associated with operation of one or more components of the memory device. In some examples, the error control component525may be configured as or otherwise support a means for performing an error control operation to detect or correct one or more errors in data stored at the memory device. In some examples, the syndrome match component530may be configured as or otherwise support a means for determining whether a first set of multiple syndromes associated with the error control operation matches a second set of multiple syndromes associated with the error control operation. In some examples, the register access component535may be configured as or otherwise support a means for storing, at the register and based on configuring the register to operate in the first mode, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes. FIG.6shows a block diagram600of a host device620that supports managing error control information using a register in accordance with examples as disclosed herein. The host device620may be an example of aspects of a host device as described with reference toFIGS.1through4. The host device620, or various components thereof, may be an example of means for performing various aspects of managing error control information using a register as described herein. For example, the host device620may include a memory device configuration component625, a register read component630, an error control component635, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses). The memory device configuration component625may be configured as or otherwise support a means for writing, by a host device to a first register associated with a memory device, a first indication that a first communication protocol for reporting information from the memory device to the host device is disabled. In some examples, the memory device configuration component625may be configured as or otherwise support a means for writing, by the host device to the first register, a second indication that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled. The register read component630may be configured as or otherwise support a means for transmitting, to the memory device, a command to read information stored at a second register of the memory device based on the first communication protocol being disabled and the first error control configuration being enabled, the information indicating whether a first set of multiple syndromes matches a second set of multiple syndromes associated with an error control operation performed at the memory device. In some examples, the memory device configuration component625may be configured as or otherwise support a means for writing, by the host device to the first register of the memory device, a third indication that an operational mode of the memory device is disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where transmitting the command is based on determining that the operational mode is disabled. In some examples, the error control component635may be configured as or otherwise support a means for determining to request, from the memory device, information indicative of a result of the error control operation, where transmitting the command is based on determining to request the information. FIG.7shows a flowchart illustrating a method700that supports managing error control information using a register in accordance with examples as disclosed herein. The operations of method700may be implemented by a memory device or its components as described herein. For example, the operations of method700may be performed by a memory device as described with reference toFIGS.1through5. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware. At705, the method may include generating, at a memory device, a first set of multiple syndromes based on receiving data for storage at the memory device, the first set of multiple syndromes associated with an error control operation for the received data, each syndrome of the first set including error correction or error detection syndrome bits. The operations of705may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of705may be performed by an error control component525as described with reference toFIG.5. At710, the method may include generating, at the memory device, a second set of multiple syndromes based on retrieving the data, the second set of multiple syndromes associated with the retrieved data and the error control operation, each syndrome of the second set including error correction or error detection syndrome bits. The operations of710may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of710may be performed by an error control component525as described with reference toFIG.5. At715, the method may include determining whether the first set of multiple syndromes matches the second set of multiple syndromes based on comparing the first set of multiple syndromes and the second set of multiple syndromes. The operations of715may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of715may be performed by a syndrome match component530as described with reference toFIG.5. At720, the method may include storing, at a register of the memory device, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes. The operations of720may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of720may be performed by a register access component535as described with reference toFIG.5. In some examples, an apparatus as described herein may perform a method or methods, such as the method700. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for generating, at a memory device, a first set of multiple syndromes based on receiving data for storage at the memory device, the first set of multiple syndromes associated with an error control operation for the received data, each syndrome of the first set including error correction or error detection syndrome bits, generating, at the memory device, a second set of multiple syndromes based on retrieving the data, the second set of multiple syndromes associated with the retrieved data and the error control operation, each syndrome of the second set including error correction or error detection syndrome bits, determining whether the first set of multiple syndromes matches the second set of multiple syndromes based on comparing the first set of multiple syndromes and the second set of multiple syndromes, and storing, at a register of the memory device, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that a first communication protocol for reporting information to a host device may be disabled and determining that a first error control configuration may be enabled for reporting a comparison of syndromes generated by the memory device according to the error control operation, where storing the indication at the register may be based on determining that the first communication protocol may be disabled and the first error control configuration may be enabled. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for accessing a second register of the memory device that stores a status of the first communication protocol and a status of the first error control configuration, where determining that the first communication protocol may be disabled and the first error control configuration may be enabled may be based on accessing the second register. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that an operational mode of the memory device may be disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where storing the indication at the register may be based on determining that the operational mode may be disabled. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that a second operational mode of the memory device may be disabled, the second operational mode for indicating whether one or more data pins of the memory device may be communicating valid data, where storing the indication at the register may be based on determining that the second operational mode may be disabled. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving, from a host device, a command for reading information stored at the register and outputting, to the host device, the indication based on receiving the command. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for resetting the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. Some examples of the method700and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for receiving, from a host device, a command for resetting information stored at the register and resetting the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. In some examples of the method700and the apparatus described herein, the register may be configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting the indication of whether the first set of multiple syndromes matches the second set of multiple syndromes and a second mode for recording in an error log one or more errors associated with operation of one or more components of the memory device. In some examples of the method700and the apparatus described herein, the indication includes one or more bits and a value of the one or more bits indicates that each of the first set of multiple syndromes match corresponding syndromes of the second set of multiple syndromes. In some examples of the method700and the apparatus described herein, the indication includes one or more bits and a value of the one or more bits indicates that at least one of the first set of multiple syndromes does not match a corresponding syndrome of the second set of multiple syndromes. FIG.8shows a flowchart illustrating a method800that supports managing error control information using a register in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory device or its components as described herein. For example, the operations of method800may be performed by a memory device as described with reference toFIGS.1through5. In some examples, a memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using special-purpose hardware. At805, the method may include determining, at a memory device, that a first communication protocol for reporting information to a host device is enabled or disabled. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a device configuration component540as described with reference toFIG.5. At810, the method may include determining, at the memory device, that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled or disabled. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a device configuration component540as described with reference toFIG.5. At815, the method may include configuring a register of the memory device to operate in a first mode based on determining that the first communication protocol is disabled and the first error control configuration is enabled. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a register configuration component545as described with reference toFIG.5. In some examples, an apparatus as described herein may perform a method or methods, such as the method800. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining, at a memory device, that a first communication protocol for reporting information to a host device is enabled or disabled, determining, at the memory device, that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled or disabled, and configuring a register of the memory device to operate in a first mode based on determining that the first communication protocol is disabled and the first error control configuration is enabled. Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for accessing a second register of the memory device that stores a status of the first communication protocol and a status of the first error control configuration, where determining that the first communication protocol may be enabled and the first error control configuration may be enabled may be based on accessing the second register. Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that an operational mode of the memory device may be disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where configuring the register to operate in the first mode may be based on determining that the operational mode may be disabled. Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining that a second operational mode of the memory device may be disabled, the second operational mode for indicating whether one or more data pins of the memory device may be communicating valid data, where configuring the register to operate in the first mode may be based on determining that the second operational mode may be disabled. In some examples of the method800and the apparatus described herein, the first mode indicates a location within the register for storing one or more bits indicative of a result of an error control operation performed by the memory device. In some examples of the method800and the apparatus described herein, the register may be configured to operate in a mode selected from a set of modes, the set of modes including the first mode and a second mode for recording in an error log one or more errors associated with operation of one or more components of the memory device. Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing an error control operation to detect or correct one or more errors in data stored at the memory device, determining whether a first set of multiple syndromes associated with the error control operation matches a second set of multiple syndromes associated with the error control operation, and storing, at the register and based on configuring the register to operate in the first mode, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes. FIG.9shows a flowchart illustrating a method900that supports managing error control information using a register in accordance with examples as disclosed herein. The operations of method900may be implemented by a host device or its components as described herein. For example, the operations of method900may be performed by a host device as described with reference toFIGS.1through4and6. In some examples, a host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host device may perform aspects of the described functions using special-purpose hardware. At905, the method may include writing, by a host device to a first register associated with a memory device, a first indication that a first communication protocol for reporting information from the memory device to the host device is disabled. The operations of905may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of905may be performed by a memory device configuration component625as described with reference toFIG.6. At910, the method may include writing, by the host device to the first register, a second indication that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled. The operations of910may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of910may be performed by a memory device configuration component625as described with reference toFIG.6. At915, the method may include transmitting, to the memory device, a command to read information stored at a second register of the memory device based on the first communication protocol being disabled and the first error control configuration being enabled, the information indicating whether a first set of multiple syndromes matches a second set of multiple syndromes associated with an error control operation performed at the memory device. The operations of915may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of915may be performed by a register read component630as described with reference toFIG.6. In some examples, an apparatus as described herein may perform a method or methods, such as the method900. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for writing, by a host device to a first register associated with a memory device, a first indication that a first communication protocol for reporting information from the memory device to the host device is disabled, writing, by the host device to the first register, a second indication that a first error control configuration for reporting a comparison of syndromes generated by the memory device is enabled, and transmitting, to the memory device, a command to read information stored at a second register of the memory device based on the first communication protocol being disabled and the first error control configuration being enabled, the information indicating whether a first set of multiple syndromes matches a second set of multiple syndromes associated with an error control operation performed at the memory device. Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for writing, by the host device to the first register of the memory device, a third indication that an operational mode of the memory device may be disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the memory device, where transmitting the command may be based on determining that the operational mode may be disabled. Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining to request, from the memory device, information indicative of a result of the error control operation, where transmitting the command may be based on determining to request the information. It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined. Another apparatus is described. The apparatus may include error control circuitry operable to perform an error control operation on data received for storage at the apparatus, the error control circuitry further operable to, generate a first set of multiple syndromes associated with the error control operation based on the received data, each syndrome of the first set including error correction or error detection syndrome bits, generate a second set of multiple syndromes associated with the error control operation based on retrieving the data, each syndrome of the second set including error correction or error detection syndrome bits, determine whether the first set of multiple syndromes matches the second set of multiple syndromes based on comparing the first set of multiple syndromes and the second set of multiple syndromes, generate a signal indicative of whether the first set of multiple syndromes matches the second set of multiple syndromes, and a register operable to receive the signal from the error control circuitry and store, at a location of the register, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes based on receiving the signal. In some examples, the circuitry may be further operable to determine that a first communication protocol for reporting information to a host device may be disabled and determine that a first error control configuration may be enabled for reporting a comparison of syndromes generated by the apparatus according to the error control operation, where the register may be operable to receive the signal and store the indication based on determining that the first communication protocol may be disabled and the first error control configuration may be enabled. In some examples, the apparatus may include a second register operable to store a status of the first communication protocol and a status of the first error control configuration, the circuitry operable to access the information stored at the second register to determine that the first communication protocol may be disabled and the first error control configuration may be enabled. In some examples, the circuitry may be further operable to determine that an operational mode of the apparatus may be disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the apparatus, where the register may be operable to receive the signal and store the indication based on determining that the operational mode may be disabled. In some examples, the circuitry may be further operable to determine that a second operational mode of the apparatus may be disabled, the second operational mode for indicating whether one or more data pins of the apparatus may be communicating valid data, where the register may be operable to receive the signal and store the indication based on determining that the second operational mode may be disabled. In some examples, the circuitry may be further operable to receive, from a host device, a command for reading information stored at the register and output, to the host device, the indication based on receiving the command. In some examples, the circuitry may be further operable to reset the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. In some examples, the circuitry may be further operable to receive, from a host device, a command for resetting information stored at the register and reset the information stored at the register based on receiving the command from the host device, where resetting the information includes setting the indication to a default value that indicates that different syndromes match. In some examples of the apparatus, the register may be configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting the indication of whether the first set of multiple syndromes matches the second set of multiple syndromes and a second mode for recording in an error log one or more errors associated with operation of one or more components of the apparatus. In some examples of the apparatus, the indication includes one or more bits and a first value of the one or more bits indicates that each of the first set of multiple syndromes match corresponding syndromes of the second set of multiple syndromes. In some examples of the apparatus, the indication includes one or more bits and a second value of the one or more bits indicates that at least one of the first set of multiple syndromes does not match a corresponding syndrome of the second set of multiple syndromes. Another apparatus is described. The apparatus may include a register, circuitry operable to, determine that a first communication protocol for reporting information to a host device is enabled or disabled, determine that a first error control configuration for reporting a comparison of syndromes generated by the apparatus is enabled or disabled, and configure the register to operate in a first mode based on determining that the first communication protocol is disabled and the first error control configuration is enabled. In some examples, the circuitry may be further operable to receive, from the host device, an indication of a status of the first communication protocol and a status of the first error control configuration and store the status of the first communication protocol and the status of the first error control configuration. In some examples, the circuitry may be further operable to access the status of the first communication protocol and the status of the first error control configuration at the second register, where determining that the first communication protocol may be enabled and the first error control configuration may be enabled may be based on accessing the status of the first communication protocol and the status of the first error control configuration. In some examples, the circuitry may be further operable to determine that an operational mode of the apparatus may be disabled, the operational mode including recording in an error log one or more errors associated with operation of one or more components of the apparatus, where configuring the register to operate in the first mode may be based on determining that the operational mode may be disabled. In some examples, the circuitry may be further operable to determine that a second operational mode of the apparatus may be disabled, the second operational mode for indicating whether one or more data pins of the apparatus may be communicating valid data, where configuring the register to operate in the first mode may be based on determining that the second operational mode may be disabled. In some examples of the apparatus, the first mode indicates a location within the register for storing one or more bits indicative of a result of an error control operation performed by the apparatus. In some examples of the apparatus, the register may be configured to operate in a mode selected from a set of modes, the set of modes including the first mode and a second mode for recording in an error log one or more errors associated with operation of one or more components of the apparatus. In some examples, the circuitry may be further operable to perform an error control operation operable to correct one or more errors in data stored at the apparatus, determine whether a first set of multiple syndromes associated with the error control operation matches a second set of multiple syndromes associated with the error control operation, and output, to the register and based on configuring the register to operate in the first mode, an indication of whether the first set of multiple syndromes matches the second set of multiple syndromes, where the register may be configured to store the indication based on being configured to operate in the first mode. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths. The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors. The term “coupling” refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow. The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow. The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means. A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate. The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label. The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.” Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media. The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein. | 121,477 |
11942967 | DETAILED DESCRIPTION OF THE INVENTION FIG.1is a schematic block diagram of an embodiment of a communication system100that includes a plurality of computing devices12, one or more servers22, one or more databases24, one or more networks26, a plurality of analog to digital converters (ADCs)28, a plurality of sensors30, and a plurality of loads32. Generally speaking, an ADC28is configured to convert an analog signal31into a digital signal. In some examples, such an analog signal may be provided from and/or correspond a signal associated with a sensor30, or generally speaking, a load32(e.g., such as which is consumptive of current, voltage, and/or power, and/or such as which produces a current, voltage, and/or power signal). Also, in some examples, note that any one of the computing devices12includes a touch screen with sensors30, a touch & tactic screen that includes sensors30, loads32, and/or other components. A sensor30functions to convert a physical input into an output signal (e.g., an electrical output, an optical output, etc.). The physical input of a sensor may be one of a variety of physical input conditions. For example, the physical condition includes one or more of, but is not limited to, acoustic waves (e.g., amplitude, phase, polarization, spectrum, and/or wave velocity); a biological and/or chemical condition (e.g., fluid concentration, level, composition, etc.); an electric condition (e.g., charge, voltage, current, conductivity, permittivity, eclectic field, which includes amplitude, phase, and/or polarization); a magnetic condition (e.g., flux, permeability, magnetic field, which amplitude, phase, and/or polarization); an optical condition (e.g., refractive index, reflectivity, absorption, etc.); a thermal condition (e.g., temperature, flux, specific heat, thermal conductivity, etc.); and a mechanical condition (e.g., position, velocity, acceleration, force, strain, stress, pressure, torque, etc.). For example, piezoelectric sensor converts force or pressure into an eclectic signal. As another example, a microphone converts audible acoustic waves into electrical signals. There are a variety of types of sensors to sense the various types of physical conditions. Sensor types include, but are not limited to, capacitor sensors, inductive sensors, accelerometers, piezoelectric sensors, light sensors, magnetic field sensors, ultrasonic sensors, temperature sensors, infrared (IR) sensors, touch sensors, proximity sensors, pressure sensors, level sensors, smoke sensors, and gas sensors. In many ways, sensors function as the interface between the physical world and the digital world by converting real world conditions into digital signals that are then processed by computing devices for a vast number of applications including, but not limited to, medical applications, production automation applications, home environment control, public safety, and so on. The various types of sensors have a variety of sensor characteristics that are factors in providing power to the sensors, receiving signals from the sensors, and/or interpreting the signals from the sensors. The sensor characteristics include resistance, reactance, power requirements, sensitivity, range, stability, repeatability, linearity, error, response time, and/or frequency response. For example, the resistance, reactance, and/or power requirements are factors in determining drive circuit requirements. As another example, sensitivity, stability, and/or linear are factors for interpreting the measure of the physical condition based on the received electrical and/or optical signal (e.g., measure of temperature, pressure, etc.). Any of the computing devices12may be a portable computing device and/or a fixed computing device. A portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet, a video game controller, and/or any other portable device that includes a computing core. A fixed computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television set, a printer, a fax machine, home entertainment equipment, a video game console, and/or any type of home or office computing equipment. An example of the computing devices12is discussed in greater detail with reference to one or more ofFIG.2. A server22is a special type of computing device that is optimized for processing large amounts of data requests in parallel. A server22includes similar components to that of the computing devices12with more robust processing modules, more main memory, and/or more hard drive memory (e.g., solid state, hard drives, etc.). Further, a server22is typically accessed remotely; as such it does not generally include user input devices and/or user output devices. In addition, a server may be a standalone separate computing device and/or may be a cloud computing device. A database24is a special type of computing device that is optimized for large scale data storage and retrieval. A database24includes similar components to that of the computing devices12with more hard drive memory (e.g., solid state, hard drives, etc.) and potentially with more processing modules and/or main memory. Further, a database24is typically accessed remotely; as such it does not generally include user input devices and/or user output devices. In addition, a database24may be a standalone separate computing device and/or may be a cloud computing device. The network26includes one more local area networks (LAN) and/or one or more wide area networks WAN), which may be a public network and/or a private network. A LAN may be a wireless-LAN (e.g., Wi-Fi access point, Bluetooth, ZigBee, etc.) and/or a wired network (e.g., Firewire, Ethernet, etc.). A WAN may be a wired and/or wireless WAN. For example, a LAN may be a personal home or business's wireless network and a WAN is the Internet, cellular telephone infrastructure, and/or satellite communication infrastructure. In an example of operation, computing device12communicates with ADCs28, that are in communication with a plurality of sensors30. In some examples, the sensors30and/or ADCs28are within the computing device12and/or external to it. For example, the sensors30may be external to the computing device12and the ADCs28are within the computing device12. As another example, both the sensors30and the ADCs28are external to the computing device12. In some examples, when the ADCs28are external to the computing device, they are coupled to the computing device12via wired and/or wireless communication links. The computing device12communicates with the ADCs28to; (a) turn them on, (b) obtain data from the sensors30, loads32, one or more analog signals31, etc. individually and/or collectively), (c) instruct the ADC28on how to process the analog signals associated with the sensors30, loads32, one or more analog signals31, etc. and to provide digital signals and/or information to the computing device12, and/or (d) provide other commands and/or instructions. In an example of operation and implementation, a computing device12is coupled to ADC28that is coupled to a senor30. The sensor30and/or the ADC28may be internal and/or external to the computing device12. In this example, the sensor30is sensing a condition that is particular to the computing device12. For example, the sensor30may be a temperature sensor, an ambient light sensor, an ambient noise sensor, etc. As described above, when instructed by the computing device12(which may be a default setting for continuous sensing or at regular intervals), the ADC28is configured to generate a digital signal and/or information associated with the sensor30and to provide that digital signal and/or information to the computing device12. FIG.2is a schematic block diagram of an embodiment of a computing device12(e.g., any of the computing devices12inFIG.1). The computing device12includes a core control module40, one or more processing modules42, one or more main memories44, cache memory46, an Input-Output (I/O) peripheral control module52, one or more I/O interfaces54, one or more ADCs28coupled to the one or more I/O interfaces54and one or more loads32, optionally one or more digital to analog converters (DACs)29one or more I/O interfaces54, one or more input interface modules56, one or more output interface modules58, one or more network interface modules60, and one or more memory interface modules62. In some examples, the computing device12also includes a component processing module48. In an example of operation and implementation, such a component processing module48is implemented to facilitate operations associated with video graphics that may include any one or more of video graphics, display, a touch screen, a camera, audio output, audio input, and/or any other one or more computing device components, etc. A processing module42is described in greater detail at the end of the detailed description of the invention section and, in an alternative embodiment, has a direction connection to the main memory44. In an alternate embodiment, the core control module40and the I/O and/or peripheral control module52are one module, such as a chipset, a quick path interconnect (QPI), and/or an ultra-path interconnect (UPI). Each of the main memories44includes one or more Random Access Memory (RAM) integrated circuits, or chips. For example, a main memory44includes four DDR4 (4thgeneration of double data rate) RAM chips, each running at a rate of 2,400 MHz. In general, the main memory44stores data and operational instructions most relevant for the processing module42. For example, the core control module40coordinates the transfer of data and/or operational instructions from the main memory44and the memory64-66. The data and/or operational instructions retrieve from memory64-66are the data and/or operational instructions requested by the processing module or will most likely be needed by the processing module. When the processing module is done with the data and/or operational instructions in main memory, the core control module40coordinates sending updated data to the memory64-66for storage. The memory64-66includes one or more hard drives, one or more solid state memory chips, and/or one or more other large capacity storage devices that, in comparison to cache memory and main memory devices, is/are relatively inexpensive with respect to cost per amount of data stored. The memory64-66is coupled to the core control module40via the I/O and/or peripheral control module52and via one or more memory interface modules62. In an embodiment, the I/O and/or peripheral control module52includes one or more Peripheral Component Interface (PCI) buses to which peripheral components connect to the core control module40. A memory interface module62includes a software driver and a hardware connector for coupling a memory device to the I/O and/or peripheral control module52. For example, a memory interface62is in accordance with a Serial Advanced Technology Attachment (SATA) port. The core control module40coordinates data communications between the processing module(s)42and the network(s)26via the I/O and/or peripheral control module52, the network interface module(s)60, and a network card68or70. A network card68or70includes a wireless communication unit or a wired communication unit. A wireless communication unit includes a wireless local area network (WLAN) communication device, a cellular communication device, a Bluetooth device, and/or a ZigBee communication device. A wired communication unit includes a Gigabit LAN connection, a Firewire connection, and/or a proprietary computer wired connection. A network interface module60includes a software driver and a hardware connector for coupling the network card to the I/O and/or peripheral control module52. For example, the network interface module60is in accordance with one or more versions of IEEE 802.11, cellular telephone protocols, 10/100/1000 Gigabit LAN protocols, etc. The core control module40coordinates data communications between the processing module(s)42and input device(s)72via the input interface module(s)56and the I/O and/or peripheral control module52. An input device72includes a keypad, a keyboard, control switches, a touchpad, a microphone, a camera, etc. An input interface module56includes a software driver and a hardware connector for coupling an input device to the I/O and/or peripheral control module52. In an embodiment, an input interface module56is in accordance with one or more Universal Serial Bus (USB) protocols. The core control module40coordinates data communications between the processing module(s)42and output device(s)74via the output interface module(s)58and the I/O and/or peripheral control module52. An output device74includes a speaker, etc. An output interface module58includes a software driver and a hardware connector for coupling an output device to the I/O and/or peripheral control module52. In an embodiment, an output interface module56is in accordance with one or more audio codec protocols. This disclosure presents novel analog to digital converter (ADC) designs, architectures, circuits, etc. that provide much improved performance in comparison to prior art ADCs. Various aspects, embodiments, and/or examples of the invention (and/or their equivalents) that may be used to perform analog to digital conversion of signals provide very high resolution digital format data. Certain examples of such analog-to-digital conversion is performed based on sensing an analog current signal associated with a sensor, a load, etc. or any source of an analog signal. In many examples provided herein, a load32is employed as the element having an associated analog signal that is sensed and converted to a digital signal. Generally speaking, such a load32may be any of a variety of types of sources, devices, systems, etc. that has an associated analog signal that may be sensed and converted to a digital signal including a sensor, a computing device, a circuit, etc. within any type of application context including industrial, medical, communication system, computing device, etc. In addition, various aspects, embodiments, and/or examples of the invention (and/or their equivalents) that may be used to perform analog to digital conversion of signals may be implemented in accordance with providing both drive and sense capabilities such that a signal is driven from the ADC28to the load32to facilitate sensing of the analog signal associated with the load32. In some examples, the signal is driven from the ADC28to energize the load32and to facilitate its effective operation. Consider an example in which the load32is a sensor30. In such an example, the signal provided from the ADC28is operative to provide power to the sensor30and also simultaneously to sense the analog signal associated with the sensor30simultaneously via a single line. Alternatively, note that certain examples may operate such that the load32is provided power or energy from an alternative source. In such instances, the ADC28need not specifically be implemented to provide power or energy to the load32but merely to sense the analog signal associated with the sensor30. In some examples, a sensing signal is provided from the ADC28to the load32such that detection of any change of the sensing signal is used and interpreted to determine one or more characteristics of the analog signal associated with the load32. In certain examples, the providing of the sensing signal from the ADC28to the load32and the sensing of the analog signal associated with the load32are performed simultaneously via a single line that couples or connects the ADC28to the load32. FIG.3is a schematic block diagram showing various embodiments301,302,303, and304of analog to digital conversion as may be performed in accordance with the present invention. In the upper left portion of the diagram, with respect to reference numeral301, and analog AC signal is shown. Note that the analog AC signal may or may not have a DC offset. Consider an example in which the DC offset is X volts, and consider a sinusoidal analog AC signal oscillates and varies between a maximum of +Y volts to a minimum of −Y volts as a function of time based on a particular frequency of the analog AC signal. Note that this example of an analog AC signal is not exhaustive, and generally speaking, such an analog AC signal may have any variety of shapes, frequencies, characteristics, etc. Examples of such analog signals may include any one or more of a sinusoidal signal, a square wave signal, a triangular wave signal, a multiple level signal (e.g., has varying magnitude over time with respect to the DC component), and/or a polygonal signal (e.g., has a symmetrical or asymmetrical polygonal shape with respect to the DC component). Note also that such an analog signal may alternatively have only a DC component with no AC component. Note that any of the respective implementations of an ADC has described herein, or their equivalents, is also operative to detect an analog signal having only a DC component. Note that a totally non-varying analog signal having only a DC component, after undergoing analog-to-digital conversion, would produce a digital signal having a constant digital value as a function of time. That is to say, such a discrete-time signal generated based on a DC signal. In the upper right hand portion of the diagram, with respect reference numeral302, the analog AC signal shown with respect to reference numeral301is shown as undergoing analog-to-digital conversion in accordance with generating a digital signal. Generally speaking, the resolution and granularity of such a digital signal may be of any desired format including performing analog-to-digital conversion based on a range spanning any number of desired levels and generating a digital signal having any number of desired bits, N, where N is a positive integer. This particular example shows generation of additional signal in accordance with a range having 8 levels such that the digital signal includes 3 bits. For example, consider an analog AC signal having no DC offset and varying between a range spanning +Y/−Y volts, then that range is divided into 8 respective sub-range is, and when the value of the analog AC signal crosses from one sub-range into another sub-range as a function of time, then the value of the digital signal correspondingly changes as a function of time. With respect to reference numeral302, a digital representation of the analog AC signal shown with respect to reference numeral301is shown as a function of time. In the lower left-hand portion of the diagram, with respect to reference numeral303, a transfer function of a three bit ADC is shown with respect to a Z volt reference. As the magnitude of the analog AC signal varies as a function of time, a corresponding digital value is generated based on where the magnitude of the analog AC signal is within the range from zero to a Z volt reference. Note that this particular example shown with respect to reference numeral303is shown as varying between zero and a Z volt reference. In another example, such a transfer function may be implemented based on using −Y volts as a baseline such that, along the horizontal axis, 0 corresponds to −Y volts, and Z is twice the magnitude of Y (e.g., Z=2×MAG[Y]). For example, consider the analog AC signal shown with respect to reference301as being an analog AC signal having no DC offset and varying between a range spanning +Y/−Y volts, then the Z volt reference could correspond to Y (or alternatively some value greater than Y to facilitate detection of the analog AC signal bearing outside of a particular or expected range), then such an 8 level, 3 bit digital signal may be generated such as shown with respect to reference numeral302. In the lower right hand portion of the diagram, with respect to reference numeral304, an ADC28is shown as being coupled or connected to a load32. The ADC28is configured to sense an analog signal associated with the load32and to generate a digital signal based thereon. Note that the ADC28may be implemented to facilitate both drive and sense capabilities such that the ADC28is configured to drive an analog current and/or voltage signal to the load32while concurrently or simultaneously sensing the analog signal associated with the load32. In alternative examples, the ADC28is also operative to perform simultaneous driving and sensing of the analog signal associated with the load32when the load32is energized from another source such as from a battery, an external power source, etc. Note that the ADC28includes capability and functionality to perform sensing only or alternatively, to perform both drive and sense. In some examples, the ADC28is configured to perform sensing only of an analog signal (e.g., having AC and/or DC components) associated with the load32. In other example, the ADC28is configured to drive an analog current and/or voltage signal to the load32while concurrently and/or simultaneously sensing an analog signal (e.g., having AC and/or DC components) associated with the load32. For example, the ADC28is configured to provide power to or energize the load32while also concurrently and/or simultaneously sensing an analog signal (e.g., having AC and/or DC components) associated with the load32. Also, in certain alternative examples, the ADC28is also operative to perform simultaneous driving and sensing of the analog signal associated with the load32when the load32is energized from another source such as from a battery, an external power source, etc. Various aspects, embodiments, and/or examples of the invention (and/or their equivalents) include an ADC that is operative to sense an analog current signal. The ADC is implemented to convert the sensed analog current signal into a very high resolution digital format of a desired resolution (e.g., of a certain sampling rate, resolution, or number of bits, etc.). FIG.4is a schematic block diagram of an embodiment400of an analog to digital converter (ADC) in accordance with the present invention. In this diagram, an ADC is connected to or coupled to a load32via single line such that the ADC is configured to provide a load signal412via that single line and simultaneously to detect any effect414on that load signal via a single line. In certain examples, the ADC is configured to perform single line drive and sense of that load signal412, including any effect414thereon via that single line. Note that certain of the following diagrams show one or more processing modules24. In certain instances, the one or more processing modules24is configured to communicate with and interact with one or more other devices including one or more of ADCs, one or more components implemented within an ADC (e.g., filters of various types including low pass filters, bandpass filters, decimation filters, etc., gain or amplification elements, digital circuits, digital to analog converters (DACs) of varying types include N-bit DACs, analog to digital converters (ADCs) of varying types include M-bit ADCs, etc. Note that any such implementation of one or more processing modules24may include integrated memory and/or be coupled to other memory. At least some of the memory stores operational instructions to be executed by the one or more processing modules24. In addition, note that the one or more processing modules24may interface with one or more other devices, components, elements, etc. via one or more communication links, networks, communication pathways, channels, etc. (e.g., such as via one or more communication interfaces of the device, such as may be integrated into the one or more processing modules24or be implemented as a separate component, circuitry, etc.). Also, within certain of the following diagrams, there is a demarcation shown between the analog domain and the digital domain (e.g., showing the portion of the diagram that operates in the analog domain based on continuous-time signaling, and the portion of the diagram that operates in the digital domain that operates in the digital domain based on discrete-time signaling). Moreover, within certain of the following diagrams, there is a demarcation shown between the load domain and the ADC domain (e.g., Showing the connection or coupling between a load and/or an analog signal that is being sensed and the ADC that is sensing the analog signal, which may be associated with the load). In certain examples, an ADC is connected to or coupled to a load via a single line. Also, such an ADC may be implemented to perform simultaneous driving and sensing of a signal via that single line that connects or couples to the load. For example, such an ADC is operative to drive an analog signal (e.g., current and/or voltage) of the load32. With respect to implementations that operate in accordance with sensing analog current signals, such an ADC is operative to sense current signals within an extremely broad range including very low currents (e.g., currents below the 1 pico-amp range, within the 10s of pico-amps range, below the 1 nano-amp range, within the 10s of nano-amps range, below the 1 micro-amp range, within the 10s of micro-amps range, etc.) and also up to relatively much larger currents (e.g., currents in the 10s milli-amps range, 100s milli-amps range, or even higher values of amps range, etc.). In some examples, such as with respect to detecting currents that are provided from a photodetection or photodiode component, such an ADC is operative to sense current signals below the 1 pico-amp range, currents within the 100s of micro-amps range, etc. Also, in some examples, when using appropriately provisioned components (e.g., higher current, higher power, etc.), much higher currents can also be sensed using architectures and topologies in accordance with an ADC as described herein. For example, such an ADC implemented based on architectures and topologies, as described herein, using appropriately provisioned components be operative to sense even higher currents (e.g., is of amps, 10s of amps, or even higher values of amps range, etc.). In addition, such an ADC may be implemented to provide for extremely low power consumption (e.g., less than 2 μW). Such an ADC may be particularly well-suited for low-power applications such as remote sensors, battery operated applications, etc. The architecture and design of such an ADC requires very few analog components. this provides a number of advantages and improve performance over prior art ADCs including very little continuous static current being consumed. In certain examples, such an ADC is described herein provides for a 10×lower power consumption in comparison to prior art ADC technologies. Such extremely low power consumption implementations may be particularly well-suited for certain applications such as bio-medical applications including sensing of vital signs on the patient, low current sensors, remote sensors, etc. In addition, note that while such an ADC as described herein provides for significant improvement in a reduction in power consumption in comparison to prior art ADCs (e.g., including prior art ADCs such as successive approximation resolution (SAR) ADCs, D-sigma modulator ADCs, pipe-line ADCs, etc.), such an ADC is described herein may be implemented as a general-purpose ADC in any of a variety of applications. Moreover, the bandwidth of analog signals that may be sensed using such an ADC is described herein is extremely broad, ranging from DC up to and over 10 MHz. In certain particular examples, such an ADC has described herein is implemented for very low frequency measurements, such as from DC up to 1 kHz. Note also that an ADC as described herein may be designed and tailored particularly for a desired digital signal resolution to be generated based on a particular bandwidth to be sampled. In general, there may be a trade-off between bandwidth and power consumption within a particularly designed ADC. Consider an example in which a very high resolution digital signal is desired for a relatively low sampling bandwidth versus another example in which a relatively low resolution digital signal is desired for a relatively high sampling bandwidth. For example, consider a particularly designed ADC to provide a digital signal having 16-bit resolution for a sampling bandwidth below 100 kHz, then such an ADC may be implemented to consume less than 1 μW of energy. Such an ADC may be appropriately designed to meet criteria for a particular application. Consider an example in which a 24-bit digital signal is desired for a relatively low sampling bandwidth from DC up to 100 kHz. Consider another example in which a 12 bit digital signal desired for a relatively higher sampling bandwidth from DC up to 1 MHz. In comparing these two examples, as the sampling bandwidth is extended higher and higher, the ADC will consume more current and thereby be more power consumptive. Depending on the particular application at hand, a relatively low sampling bandwidth may be acceptable for the particular application at hand, and very significant power consumption savings may be achieved. Generally speaking, a trade-off in design implementation may be viewed as higher resolution/lower sampling bandwidth/lower power consumption versus higher resolution/higher sampling bandwidth/higher power consumption. In addition, note that many of the examples of an ADC included herein operate based on sensing a current signal as opposed to a voltage signal. In addition, when the ADC is implemented in an application to sense a voltage signal, an appropriately implemented voltage to current transforming element, such as the trans-impedance amplifier that is operative to transform voltage to current, or vice versa, may be implemented to generate a current signal from a voltage signal in any particular desired application. In any of the various diagrams, note that such a load32may be of any of a variety of types including electrode, a sensor, a transducer, etc. Generally speaking, such a load32may be any of a variety of types of components. Examples of such components may include any one or more of sources, devices, systems, etc. that has an associated analog signal that may be sensed and converted to a digital signal including a sensor, a computing device, a circuit, etc. within any type of application context including industrial, medical, communication system, computing device, etc. Also, note that such a load32as depicted within any diagram herein may be energized or powered based on the signal provided from the ADC or alternatively powered by another source such as a battery, external power source, etc. For example, consider the lower left-hand portion of the diagram and need demarcation between the load domain and the ADC domain, such that the load32is connected to the ADC via a single line. In certain examples, the ADC is implemented to facilitate single-line sense functionality such that a load signal412-1is provided to the load32for sensing only, and any effect414-1on that load signal is sensed and detected by the ADC. In such an example is this, power is provided to the load32from an external source. Referring again to the top portion of the diagram, the ADC is connected to or coupled to a load32via single line such that the ADC is configured to provide a load signal412via that single line and simultaneously to detect any effect414on that load signal via a single line. For example, the load signal412is an analog current signal. An analog capacitor, C, is implemented to be charged in accordance with the load signal412. Note that such an analog capacitor may alternatively be a load capacitance from the load32itself, such that a separate analog capacitor, C, is not needed when the load32itself provides a sufficient load capacitance. In an example of operation and implementation, a load voltage, Vload, is generated based on any effect414on that load signal charging the capacitor. This load voltage, Vload, serves as an input voltage, Vin, to one of the inputs of a comparator that also receives a reference signal, Vref (e.g., a voltage reference signal). Note that the reference signal, Vref, may be internally generated, provided from an external source, provided from a processing module24, etc. The comparator compares the input voltage, Vin, to the reference signal, Vref, and outputs a signal that is based on any difference between the input voltage, Vin, to the reference signal, Vref, that gets processed by a digital circuit410to generate a digital output (Do) 1 signal that may be viewed as being a digital stream of 0s and/or is at a clock rate (CLK) at which the digital circuit410is clocked. For example, consider that the input voltage, Vin, is greater than the reference signal, Vref, then the comparator output signal would be positive (e.g., such as a positive rail or power supply voltage of the ADC). Alternatively, consider that the input voltage, Vin, is less than or equal to the reference signal, Vref, then the comparator output signal would be negative (e.g., such as a negative rail or power supply voltage of the ADC). In another example, consider that the input voltage, Vin, is greater than the reference signal, Vref, then the comparator output signal would be positive or negative (e.g., such as a positive or negative rail or power supply voltage of the ADC). Alternatively, consider that the input voltage, Vin, is less than or equal to the reference signal, Vref, then the comparator output signal would be zero (e.g., such as a ground voltage potential). Generally speaking, the combined operation of the comparator and the digital circuit410may be viewed as performing the analog to digital conversion of a signal that is the difference (e.g., and error voltage, Ve) between the input voltage, Vin, and the reference signal, Vref (e.g., Ve=Vref−Vin) to generate a digital signal of a particularly desired resolution, which may be viewed as M bits, where M is a positive integer greater than or equal to 1. A processing module24is operative to process the Do1to generate a digital output (Do)2. Note that the processing module24may be implemented in any of a variety of examples to perform any desired digital signal processing on the Do1to generate the Do2. Examples of such digital signal processing may be increasing the output resolution (e.g., consider Do1having a resolution of M bits and Do2having a resolution of N bits, where N and M are both positive integers, where M is a positive integer greater than or equal to 1, and N is greater than M), performing filtering on the Do1to generate the Do2(e.g., such as low pass filtering or bandpass filtering based on certain parameters such as a particular frequency cut off for low pass filtering or a particular frequency range for bandpass filtering). The processing module24provides the Do2to an N-bit digital to analog converter (DAC)420. In some examples, the N-bit DAC420has a resolution of N<8 bits. This N-bit DAC420, based on the Do2provided from the processing module24, forces and output current to the load32that follows or tracks the load signal412due to the operation of the comparator that compares the input voltage, Vin, to the reference signal, Vref, and, in conjunction with the digital circuit410, generates Do1. From certain perspectives, considering the Do1and the Do2, the Do1may be viewed as a digital signal corresponding to the unfiltered load current signal including quantization noise, and the Do2may be viewed as another digital signal corresponding to a filtered load current signal. In this diagram, the positive input of the comparator is driven by the reference signal, Vref. The load voltage, Vload, will follow the reference signal, Vref, based on the comparator output signal that corresponds to the difference or error between the input voltage, Vin, and the reference signal, Vref. In many examples, the difference between the input voltage, Vin, and the reference signal, Vref, is very small (e.g., approaching 0, very close to 0, or actually 0) based on the Delta-sigma modulation operation of the comparator and the digital circuit410. For example, when there is any difference between the input voltage, Vin, and the reference signal, Vref, the ADC adapts/modifies the output current from the N-bit DAC420to match the current of the load so that difference or error between the input voltage, Vin, and the reference signal, Vref, will be forced to 0. Note that the comparator and the digital circuit410may be implemented using one or more other components and other examples while still providing the same overall functionality of the ADC. The following diagram shows some alternative possible examples of how the comparator and the digital circuit410may be implemented. Note that this implementation of an ADC includes very few number of analog components. For example, there may be instances in which no capacitors required whatsoever given that the load32inherently includes sufficient load capacitance to generate the load voltage, Vload. In certain implementations, the comparator is implemented by a component that performs analog to digital conversion of the load voltage, Vload, directly thereby further reducing the number of analog components within the ADC. Given the small number of analog components, such an ADC consumes little or no continuous static power thereby facilitating very low power consumption. The only static current being consumed is by the N-bit DAC420. This N-bit DAC420drives and output current that is same as the sensed load current thereby tracking or following the load current. Therefore, within implementations in which the load current is small, so will the corresponding output current from the N-bit DAC420be small. The smaller the current provided from the N-bit DAC420, which is based on the sensed load current, the lower the power consumption of the ADC. Note that there are certainly alternative implementations of an ADC that will consume some static current, such as when an M-bit analog to digital converter (ADC) is used or some other component that is implemented to perform the analog-to-digital conversion of the signal Vin to Do1. Also, note that the amount of power consumed by the DAC, particularly the digital power consumed by the DAC, scales with the clock rate, CLK. Note also that applications that are implemented to perform sensing of ADC signal, such as sensing ADC current signal, the clock frequency can be extremely low (e.g., within the range of 1 kHz to 100 kHz) thereby providing for a very small digital power consumption. FIG.5is a schematic block diagram showing alternative embodiments501,502,503, and504of various components may be implemented within an ADC in accordance with the present invention. Considering reference numeral501, a comparator operates in cooperation with the digital circuit410as described above such that the combined operation of the comparator and the digital circuit410may be viewed as performing the analog to digital conversion of a signal that is the difference (e.g., Ve) between the input voltage, Vin, and the reference signal, Vref (e.g., Ve=Vref−Vin) to generate a digital signal of a particularly desired resolution, which may be viewed as M bits, where M is a positive integer greater than or equal to 1. However, note that comparator and the digital circuit410may be implemented using any of a variety of other means while still facilitating proper operation of an ADC. With respect to reference numeral502, a digital comparator, which may alternatively be described as a clock (or dynamic) comparator structure (latched comparator) is shown. This singular device performs the operation of both a comparator and the digital circuit410within a single device. For example, the digital comparator is clocked at a particular clocking frequency (CLK) and outputs a stream of is and/or 0s based on the comparison of Vref and Vin. In comparison to a comparator that operates continuously and that will output one of two values, such as either a high signal or low signal, continually as a function of time, a digital comparator outputs a 1 or 0 at each clock cycle based on the comparison of Vref and Vin in accordance with generating the Do1(e.g., 1 when Vref>Vin and 0 when Vref<=Vin, or vice versa). Also note that by only clocking such a digital comparator at certain intervals, a higher accuracy and lower power consumption can be achieved in comparison to a comparator that operates continuously. With respect to reference numeral503, the output of the comparator is provided to a sample and hold circuit (S&H)510. Generally speaking, a S&H510holds, locks, or freezes its value at a constant level for a specified minimum period of time. This signal may be viewed as interpreted as a digital stream of 1s and/or 0s at the clocking frequency (CLK) in accordance with generating the Do1. Note that such a S&H510may be implemented in a variety of ways including a circuit that stores electric charge and a capacitor and also employs one or more switching elements such that the circuit stores electric charge is built up over each of certain intervals, and the switching element connects the output of the circuit that stores electric charge to the output at certain in the boroughs such as the clocking frequency (CLK) in accordance with generating the Do1. With respect to reference numeral504, the comparator and the digital circuit for 10 are replaced with a sigma-delta comparator, such as a one bit ADC, followed by a flip-flop circuit (FF)520. The sigma-delta comparator provides a high or low signal to the FF520based on comparison of Vref and Vin, and the FF520outputs a 1 or 0 at each clock cycle such as the clocking frequency (CLK) based on the comparison of Vref and Vin in accordance with generating the Do1. Generally speaking, note that the implementation of a comparator and the digital circuit410as shown within any of the diagrams herein may be alternatively implemented in a variety of different ways including those shown within this diagram and/or their equivalents. FIG.5Bis a schematic block diagram showing alternative embodiments505aand505bof servicing differential signaling using ADCs in accordance with the present invention. In addition to servicing and sensing single-ended lines and generating digital signals based thereon using ADCs as described herein, note that servicing and sensing of signals may also be performed. For example, with respect to reference numeral505a, a first instantiation of an ADC28and the second instantiation of an ADC28are each respectively coupled via a respective single line to a different perspective load32. Two respective load voltages, Vload1and Vload2, are respectively received by the first and second instantiations of an ADC28. Note that the first and second instantiation of an ADC28may be the same or may be different. Each respective instantiation of an ADC28in this example is operative to service and sense a respective single-ended line. Together, the first and second instantiations of an ADC28are operative to sense a differential signal that is based on the two load voltages, Vload1and Vload2, and to generate a corresponding digital signal based thereon. In certain examples a processing module24is implemented to combine a first digital signal that is based on Vload1and that is generated by the first instantiation of an ADC28and a second digital signal that is based on Vload2and that is generated by the second instantiation of an ADC28to generate a resultant digital signal that corresponds to the differential voltage between the two load voltages, Vload1and Vload2(e.g., Vdiff=Vload1−Vload2, or Vdiff=Vload2−Vload1). As another example, with respect to reference numeral505b, a differential load32-1is serviced such that the two signal lines corresponding to the differential signaling provided by the differential load32-1are respectively provided to a first instantiation of an ADC28and a second instantiation of an ADC28. Similarly, a processing module24may be implemented to generate a resulting digital signal that corresponds to the differential voltage associated with the differential load32-1. The first instantiation of an ADC28in the second instantiation of an ADC28operate cooperatively to provide a load signal1112and to detect any effect1114on the load signal that is based on the differential load32-1. A capacitor, C, is also implemented across the differential signal lines of the differential load32-1. In alternative implementations, two respective single-ended capacitors, C, are respectively connected to the differential signal lines and to ground instead of the capacitor, C, connected to the differential lead lines (e.g., a first single ended capacitor, C, connected to one of the differential signal lines and to ground, and a second single ended capacitor, C, also connected to the other of the differential signal lines and to ground). Note that any example, embodiment, etc. of any ADC described herein that is operative to sense an analog signal via a single line may be implemented within the first instantiation and the second instantiation of an ADC28in either of these examples corresponding to reference numerals505aand505band/or their equivalents. In an example of operation and implementation, an ADC (e.g., consider the ADC ofFIG.4) includes a capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current. In some examples, the ADC is coupled to the load via a single line. The ADC also includes a comparator. When enabled, the comparator operably coupled and configured to receive the load voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate a comparator output signal. The ADC also includes a digital circuit that is operably coupled to the comparator. When enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage. The ADC also includes one or more processing modules operably coupled to the digital circuit and to memory, which may be included within the ADC or external to the ADC. When enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the second digital output signal includes a higher resolution than the first digital output signal. The ADC also includes an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules. When enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal. Note that N is a positive integer. The DAC output current tracks the load current, and the load voltage tracks the reference voltage. Also, in some examples, the one or more processing modules, when enabled, is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the difference between the load voltage and the reference voltage. In alternative examples, the comparator includes a sigma-delta comparator, and the digital circuit includes a clocked flip flop. In even other examples, a digital comparator includes both the comparator and the digital circuit (e.g., the digital comparator is operative to perform the functionality of both the comparator and the digital circuit). When enabled, the digital comparator operably coupled and configured to receive the load voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage. In addition, in certain examples, the ADC includes a decimation filter coupled to the one or more processing modules. When enabled, the decimation filter is operably coupled and configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal. Alternative to or in addition to, another decimation filter is coupled to the digital circuit. When enabled, the other decimation filter the operably coupled and configured to process the first digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the first digital output signal. FIG.6is a schematic block diagram of another embodiment600of an ADC that includes one or more decimation filters in accordance with the present invention. This diagram has similarities with respect toFIG.4with at least one difference being that a decimation filter1and/or a decimation filter2are implemented to process the Do1and the Do2. For example, a decimation filter may be implemented to process a digital signal thereby lowering the sample rate thereof and increasing the output resolution. Consider a digital signal having a 12 bit resolution and a 100 kHz sampling rate. In one example, a decimation filter may operate to increase the resolution of that digital signal to be 24-bit resolution with a lower sampling rate of 50 kHz. In another example, decimation filter may operate to increase the resolution of that digital signal to be 18-bit resolution with a lower sampling rate of 75 kHz. generally speaking, any desired transformation of sampling rate and output resolution may be made performed using one or more decimation filters in accordance with any of the various examples of ADCs as described herein. In certain examples, only a decimation filter1is included thereby processing the Do1to generate the Do2. In other examples, both a decimation filter1is included thereby processing the Do1to generate the Do2and a decimation filter2is included thereby processing the Do2to generate a Do3(e.g., Do3having a lower sampling rate and increased output resolution in comparison to the Do2). FIG.7is a schematic block diagram showing alternative embodiments701,702, and703of one or more decimation filters and/or processing modules that may be implemented to perform digital domain processing within an ADC in accordance with the present invention. With respect to reference numeral701, a processing module24may be implemented to perform any of a variety of different digital signal processing operations on the Do1to generate the Do2such as decimation filtering, low pass filtering, bandpass filtering, etc. However, note that such an implementation of the output signals, such as Do1and the Do2may be implemented in different configurations as desired in particular applications. For example, with respect to reference numeral702, a decimation filter1and a decimation filter2may be implemented. As described above, only a decimation filter1may s included thereby processing the Do1to generate the Do2. In other examples, both a decimation filter1is included thereby processing the Do1to generate the Do2and a decimation filter2is included thereby processing the Do2to generate a Do3(e.g., Do3having a lower sampling rate and increased output resolution in comparison to the Do2). With respect to reference numeral703, the processing module24is configured to control the operation of the decimation filter1and decimation filter2. For example, the processing module24is configured to the manner in which decimation filtering may be performed by the decimation filter1and/or decimation filter2(e.g., including the manner of conversion of digital signal resolution, the modification of sampling rate, etc.). Note that any of the respective implementations shown within this diagram may be implemented within any other of the appropriate diagrams of an ADC as described herein. FIG.8is a schematic block diagram of another embodiment800of an ADC in accordance with the present invention. This diagram is similar to that ofFIG.4with at least one difference being that the capacitor, C, is replaced by an integrator. The integrator is implemented as an operational amplifier with a feedback capacitor, C. The use of the operational amplifier in place of only the capacitor, C, may be used for applications that are tailored to serve greater power than that ofFIG.4. Generally speaking, the feedback capacitor, C, implemented in cooperation with the operational amplifier serves a similar purpose of the capacitor, C, inFIG.4of being charged based on the load current and the output current from the N-bit DAC420thereby generating the Vin to be provided to the comparator and compared with Vref. In an example of operation and implementation, an ADC (e.g., consider the ADC ofFIG.800) includes an operational amplifier (op amp) that is operably coupled to a load via a first op amp input. Also, a capacitor is operably coupled to the first op amp input and an op amp output. When enabled, the op amp is operably coupled and configured to generate an output voltage at the op amp output that corresponds to a load voltage that is based on charging of the capacitor by a load current and a digital to analog converter (DAC) output current. In some examples, the ADC is coupled to the load via a single line. The ADC also includes a comparator that is operably coupled to the op amp. When enabled, the comparator operably coupled and configured to receive the output voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate a comparator output signal. The ADC also includes a comparator a digital circuit that is operably coupled to the comparator. When enabled, the digital circuit is operably coupled and configured to process the comparator output signal to generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage. The ADC also includes a comparator one or more processing modules operably coupled to the digital circuit and to memory, which is may be included within the ADC or external to the ADC. When enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage. Note that the second digital output signal includes a higher resolution than the first digital output signal. The ADC also includes an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules. When enabled, the N-bit DAC operably coupled and configured to generate the DAC output current based on the second digital output signal. Note that N is a positive integer. Also, the DAC output current tracks the load current, and the load voltage tracks the reference voltage. In some examples, the one or more processing modules, when enabled, is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the difference between the load voltage and the reference voltage. In some examples, the comparator includes a sigma-delta comparator, and the digital circuit includes a clocked flip flop. Also, in some other examples, a digital comparator includes both the comparator and the digital circuit (e.g., the digital comparator is operative to perform the functionality of both the comparator and the digital circuit). When enabled, the digital comparator operably coupled and configured to receive the load voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage. In addition, in certain examples, the ADC includes a decimation filter coupled to the one or more processing modules. When enabled, the decimation filter is operably coupled and configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal. Alternative to or in addition to, another decimation filter is coupled to the digital circuit. When enabled, the other decimation filter the operably coupled and configured to process the first digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the first digital output signal. FIG.9is a schematic block diagram of another embodiment900of an ADC in accordance with the present invention. This diagram has certain similarities with one or more of the previous diagrams with at least one difference being that a comparator and the digital circuit410, or a functionally equivalent component to the comparator and the digital circuit410, is replaced by a low resolution analog to digital converter (ADC), specifically, an M-bit ADC910, where M is a positive integer greater than or equal to 1. In certain particular examples, M is a positive integer within the range of 1-4 (e.g., 1, 2, 3, or 4). Also, in certain particular examples, N of the N-bit DAC420is less than or equal to M. In certain specific examples, N<8 bit resolution. For example, if N=4, then M=3, 2, or 1. The Do2may be viewed as a high-resolution digital signal (N bit resolution) compared to the Do1(M bit resolution), such that M<N. In addition, in some examples, the Do2is a modified version of the Do1after having undergone any desired digital signal processing within the processing module24. Note that the M-bit ADC910is operative to generate the Do1as being an error signal that corresponds to a difference between Vin and Vref and having a resolution of M bits and that is output based on the clocking rate, CLK. For example, the Do1is a digital signal that corresponds to corresponds to an error signal, Ve, such that Ve=Vref−Vin or Vin−Vref. The use of such an M-bit ADC910provides many performance improvements for certain applications including a reduction of quantization noise and an increase of the output resolution of the ADC, particularly with respect to the Do1. For example, instead of Do1being a single bit resolution digital signal (e.g., a digital stream of is and/or 0s), the Do1in this diagram is a digital signal having a higher resolution (e.g., of 2, 3, or 4 bits). In some examples, the Do1is then provided to the processing module24, and the processing module24is configured to perform any desired digital signal processing operation on the Do1to generate the Do2(e.g., increase the output resolution and lower the sampling rate, perform low pass filtering, perform bandpass filtering, etc.). In this diagram, note that the Do1may be passed directly to the N-bit DAC420such that the Do1is used to drive the N-bit DAC420. However, in certain examples, the Do2is used to drive the N-bit DAC420such as when it is a filtered and/or digital signal processed version of the Do1. In an example of operation and implementation, an ADC (e.g., the ADC ofFIG.900) includes a capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current. In some examples, the ADC is coupled to the load via a single line. The ADC also includes an M-bit analog to digital converter (ADC). When enabled, the M-bit ADC operably coupled and configured to receive the load voltage, receive a reference voltage, and compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage. The ADC also includes a processing module operably coupled to the digital circuit and to memory, which may be included within the ADC or external to the ADC. When enabled, the processing module is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage. Note that the second digital output signal includes a higher resolution than the first digital output signal. The ADC also includes an N-bit digital to analog converter (DAC) that is operably coupled to the processing module. When enabled, the N-bit DAC is operably coupled and configured to generate the DAC output current based on the second digital output signal. Note that the DAC output current tracks the load current, and the load voltage tracks the reference voltage. N is a first positive integer, and M is a second positive integer greater than or equal to 1. In some examples, N is greater than M. In other examples, N is the first positive integer that is less than or equal to 8, and M is the second positive integer that is greater than or equal to 1 and less than or equal to 4. In even other examples, the one or more processing modules, when enabled, is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the load voltage. In addition, in certain examples, the ADC includes a decimation filter coupled to the one or more processing modules. When enabled, the decimation filter is operably coupled and configured to process the second digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the second digital output signal. Alternative to or in addition to, another decimation filter is coupled to the digital circuit. When enabled, the other decimation filter the operably coupled and configured to process the first digital output signal to generate another digital output signal having a lower sampling rate and a higher resolution than the first digital output signal. FIG.10is a schematic block diagram of another embodiment1000of an ADC in accordance with the present invention. This diagram is similar to the previous diagram with at least one difference being that the capacitor, C, is replaced by an integrator. The integrator is implemented as an operational amplifier with a feedback capacitor, C. The use of the operational amplifier in place of only the capacitor, C, may be used for applications that are tailored to serve greater power than that of the previous diagram. Generally speaking, the feedback capacitor, C, implemented in cooperation with the operational amplifier serves a similar purpose of the capacitor, C, in the previous diagram of being charged based on the load current and the output current from the N-bit DAC420thereby generating the Vin to be provided to the comparator and compared with Vref. In addition, with respect to all of these examples of an ADC, the ADC operates by providing an output current to the load32to cancel out the load current. This may be viewed as providing an output current that is equal to and opposite polarity to the load current. Again, note that such an ADC may be implemented not only to sense an analog signal associated with the load32but also to provide power and/or energy to the load32within implementations where the load32is not energized via another source. In some examples, this providing of power and/or energy from the ADC to the load32is performed simultaneously via a single line via which the ADC senses and analog signal associated with the load32. Also, such an ADC may be implemented to perform sensing only of an analog signal associated with the load32without providing power and/or energy to the load32. FIG.11is a schematic block diagram of an embodiment1100of an ADC that is operative to process an analog differential signal in accordance with the present invention. This diagram shows an implementation of an ADC operating on a differential load32-1such that the ADC provides a load signal1112to the differential load32-1and also detects any effect1114on that load signal. In this diagram, a capacitor, C, is connected to the differential lead lines of the differential load32-1. In alternative implementations, two respective single-ended capacitors, C, are respectively connected to the differential signal lines and to ground instead of the capacitor, C, connected to the differential lead lines (e.g., a first single ended capacitor, C, connected to one of the differential signal lines and to ground, and a second single ended capacitor, C, also connected to the other of the differential signal lines and to ground). Also, the N-bit DAC420is replaced with a differential N-bit DAC1120, wherein N is a positive integer. The N-bit DAC420is operative to generate a differential output current signal that is provided to the differential load32-1based on the Do2. A differential signal may be viewed as being composed of two respective voltages corresponding to the two differential signal lines, Vp and Vn (e.g., sometimes referred to as a positive voltage, Vp, is a negative voltage, Vn). In this diagram, a common mode (CM) analog circuit1105is implemented to convert the differential signal to a single-ended signal. For example, the CM analog circuit1105is operative to generate an input voltage, Vin, such that Vin=(Vn+Vp)/2. In some examples, note that the CM analog circuit1105, the comparator, and the digital circuit410are all be implemented within a singular component or device that is operative to process a differential signal and to generate the Do1based thereon. FIG.12is a schematic block diagram of another embodiment1200of an ADC that is operative to process an analog differential signal in accordance with the present invention. This diagram has certain similarities with the previous diagram with at least one difference being that the CM analog circuit1105, the comparator, and the digital circuit410, or a functionally equivalent component to CM analog circuit1105, the comparator, and the digital circuit410, is replaced by a low resolution analog to digital converter (ADC), specifically, a differential M-bit ADC1210, where M is a positive integer greater than or equal to 1. In certain particular examples, M is a positive integer within the range of 1-4 (e.g., 1, 2, 3, or 4). Also, in certain particular examples, N of the differential N-bit DAC1120is less than or equal to M. In certain specific examples, N<8 bit resolution. For example, if N=4, then M=3, 2, or 1. The Do2may be viewed as a high-resolution digital signal (N bit resolution) compared to the Do1(M bit resolution), such that M<N. In addition, in some examples, the Do2is a modified version of the Do1after having undergone any desired digital signal processing within the processing module24. In certain examples, note that the differential M-bit ADC1210is operative to generate the Do1as being an error signal that corresponds to a difference between Vin (such that Vin=(Nv+Vp)/2) and Vref and having a resolution of M bits and that is output based on the clocking rate, CLK. For example, the Do1is a digital signal that corresponds to corresponds to an error signal, Ve, such that Ve=Vref−Vin or Vin−Vref. In other examples, note that the differential M-bit ADC1210is operative to generate the Do1as being an error signal that corresponds to a difference between the differential input voltage signal, Vin_diff, that is composed of Vn and Vp and a differential reference signal, Vref_diff (e.g., Vref_diff being a differential signal that is composed two different reference voltages, such as Vref1and Vref2, and having a resolution of M bits and that is output based on the clocking rate, CLK. For example, the Do1is a digital signal that corresponds to corresponds to an error signal, Ve_diff, that corresponds to the difference between the two differential signals, Ve_diff=Vref_diff−Vin_diff or Vin_diff−Vref_diff. The use of such a differential M-bit ADC1210provides many performance improvements for certain applications including a reduction of quantization noise and an increase of the output resolution of the ADC, particularly with respect to the Do1. For example, instead of Do1being a single bit resolution digital signal (e.g., a digital stream of is and/or 0s), the Do1in this diagram is a digital signal having a higher resolution (e.g., of 2, 3, or 4 bits). In some examples, the Do1is then provided to the processing module24, and the processing module24is configured to perform any desired digital signal processing operation on the Do1to generate the Do2(e.g., increase the output resolution and lower the sampling rate, perform low pass filtering, perform bandpass filtering, etc.). In this diagram, note that the Do1may be passed directly to the differential N-bit DAC1120such that the Do1is used to drive the differential N-bit DAC1120. However, in certain examples, the Do2is used to drive the differential N-bit DAC1120such as when it is a filtered and/or digital signal processed version of the Do1. FIG.13is a schematic block diagram of another embodiment1300of an ADC that is operative to process an analog differential signal in accordance with the present invention. This diagram has certain similarities to certain of the previous diagrams that operate based on differential signaling with at least one difference being that the capacitor, C, that was connected between the differential signal lines of the load32-1is replaced by a differential integrator with two respective feedback capacitors, C. The differential integrator is implemented as an operational amplifier with two respective feedback capacitors, C, and is operative to generate a differential input signal is based on Vn and Vp. The use of the operational amplifier in place of only the capacitor, C, two respective feedback capacitors, C may be used for applications that are tailored to serve greater power than that of the previous diagram. Generally speaking, the two respective feedback capacitors, C, implemented in cooperation with the differential operational amplifier serve a similar purpose of the capacitor, C, that was connected between the differential signal lines of the load32-1in the previous diagram of being charged based on the differential load current and the differential output current from the differential N-bit DAC1120thereby generating the Vin to be provided to the comparator and compared with Vref. Note that the CM analog circuit1105, the comparator, and the digital circuit410may alternatively be replaced with a differential M-bit ADC1210such as in accordance with the previous diagram. FIG.14Ais a schematic block diagram of an embodiment1401an ADC that is operative to perform voltage measurement in accordance with the present invention. This diagram has some similarities with the previous diagrams with at least one difference being that the load32is replaced by the load voltage32-1, which may be a voltage of any of a number of devices including the load32. Examples of such a load voltage32-1include any of the voltage of an electrode, sensor, transducer, etc. Another difference within this diagram is that a resistor, R, is placed in line with the single line that connects her couples the ADC that is operative to perform voltage measurement and the load voltage32-1. For example, the load voltage32-1, when dropping across the resistor, R, to generate the input voltage, Vin, will provide a current signal that will charge the capacitor, C, that is provided to one of the inputs of the comparator. Generally speaking, a load voltage32-1can be measured by inserting a resistor, R, between the load voltage32-1and the ADC so as to facilitate conversion of the load voltage32-1to a current, Iin, that is equal to the difference between the load voltage32-1, Vload, and Vin, such that Iin=(Vload−Vin)/R. note also that a prince impedance circuitry may alternatively be implemented that is operative to convert a voltage to a current signal such that the current signal may be sensed by an ADC as described herein. FIG.14Bis a schematic block diagram of an embodiment1402an transimpedance amplifier that may be implemented within an ADC that is operative to perform voltage measurement in accordance with the present invention. The trans-impedance circuitry includes a buffer, operational amplifier, etc. having a first input coupled to the ground potential, and a second input coupled to a node that is sourcing or sinking current, such as the node connected to the N-bit DAC420. An impedance (shown as an R or generically a Z, which may have inductive and/or capacitive reactants components) is also coupled from the second input to the output of the buffer, operational amplifier, etc. A current, I, that flows through the impedance generates an output voltage, V, that is based on the impedance times the current, I (e.g., V=R×I or Z×I). Such a trend impedance amplifier, or any appropriate circuit or component that is operative to perform voltage to current signal conversion, or vice versa, may be used in place of the resistor shown within the previous diagram. FIG.15is a schematic block diagram showing an embodiment1500of digital domain filtering within an ADC in accordance with the present invention. This diagram shows an alternative implementation to having a processing module24implemented to receive him perform any desired digital signal processing on the Do1and to generate the Do2. Specifically, a filter1510is implemented to process the Do1to generate the Do2. Note that the filter1510may be of any desired type of digital filter. In certain examples, bandpass filtering or low pass filtering is performed by the filter1510to filter out high-frequency quantization noise within the Do1in accordance with generating the Do2. Possible examples of a low pass filter or low pass filter operation may be implemented based on an accumulator or in integrator. For example, consider an application tailored for detecting a DC analog signal, or for detecting an analog signal having a frequency within the voice frequency bands such as 20 kHz to 100 kHz, then appropriate low pass filtering or bandpass filtering is performed by the filter1510to filter out high-frequency quantization noise within the Do1in accordance with generating the Do2. In certain examples, note that a processing module24may be in communication with the filter1510such that the particular filtering to be performed by the filter1510is configurable based on control signaling from the processing module24. For example, consider the filter1510to be a configurable or selectable filter that includes one or more options of bandpass filtering or low pass filtering. The processing module24is configured to select a first type of filtering to be performed at or during a first time and a second type of filtering to be performed at or during a second time, and so on. FIG.16is a schematic block diagram showing an embodiment1600of digital domain filtering using cascaded filters within an ADC in accordance with the present invention. This diagram shows digital signal processing based on a cascade of N and pass filters or N low pass filters. In a particular example, N=10. The gain elements, K1through KN, are amplification constants that are used to stabilize the feedback loop from any digital output signal that is generated by the respective cascade of N filter (e.g., filter1through filter N) that provide the digital input control signal to the N-bit DAC420. The different respective game factors operate to stabilize the feedback that is provided to the N-bit DAC420. Note that this implementation is operative to provide a number of different respective digital output signals, shown as Do1, Do2through Do N as corresponding to the respective outputs from the respective cascade of N filter (e.g., filter1through filter N). Note that any one or more decimation filters may also be implemented to perform decimation filtering of the digital output signals, shown as Do1, Do2through Do N as corresponding to the respective outputs from the respective cascade of N filter (e.g., filter1through filter N). FIG.17is a schematic block diagram showing another embodiment1700of digital domain filtering using configurable/adjustable cascaded filters within an ADC in accordance with the present invention. This diagram is similar to the previous diagram with at least one difference being that one or more processing modules24is coupled or connected to each of the respective gain elements (K1through KN) and the respective cascade of N filter (e.g., filter1through filter N). The one or more processing modules24is configured to adjust a gains of the respective gain elements (K1through KN) and mean particular characteristics by which filtering is performed by the respective cascade of N filter (e.g., filter1through filter N). For example, the one or more processing modules24is configured to select a first set of gains for the respective gain elements (K1through KN) and a first type of filtering to be performed by the respective cascade of N filter (e.g., filter1through filter N) at or during a first time and a second set of gains for the respective gain elements (K1through KN) and a second type of filtering to be performed by the respective cascade of N filter (e.g., filter1through filter N) at or during a second time. FIG.18is a schematic block diagram showing an embodiment1800of one or more processing modules implemented to perform digital domain filtering within an ADC in accordance with the present invention. This diagram includes one or more processing modules24that is operative to perform the filtering pictorially illustrated within the previous diagram. For example, one or more processing modules24may be implemented perform any desired digital signal processing of any of the respective digital output signals, shown as Do1, Do2through Do N including the digital signal processing pictorially described with respect to the previous diagram. In this diagram, the one or more processing modules24itself for themselves performs the digital signal processing. In the previous diagram, separate and distinct digital signal processing components are implemented, ending one or more processing modules24of that diagram are operative to control and configure the manner in which those digital signal processing components operate. In addition, alternative examples of an ADC may be implemented using a non-linear N-bit DAC that operates based on a non-linear function. For example, a non-linear N-bit DAC is operative to provide an output current based on the non-linear function of the digital input signal provided to it. Such a non-linear function may be described also as a non-linear companding function such that companding corresponds to a non-linear response of the ADC based on the signal it receives and/or senses. In such a non-linear N-bit DAC, the output current is a non-linear function of the input. Considering one possible example of an ADC that includes a non-linear N-bit DAC, the digital output signal (e.g., the Do1and/or the Do2signal) that is generated by such an ADC is a non-linear function of the analog signal that it is sensing. Consider an ADC that includes a non-linear N-bit DAC and operates based on a logarithmic function when sensing a current signal, then the digital output signal (e.g., the Do1and/or the Do2signal) is a logarithmic function of the input current. Such an ADC that includes a non-linear N-bit DAC may be referred to as a companding ADC. Generally speaking, such an ADC that provides for a non-linear response when generating a digital output signal based on the analog signal that it is sensing may be referred to as a companding ADC. Note that such a companding ADC may also be implemented to perform simultaneous driving and sensing of a signal via that single line that connects or couples to the load. For example, such an ADC is operative to drive an analog signal (e.g., current and/or voltage) of a load32. With respect to implementations that operate in accordance with sensing analog current signals, such a companding ADC is also operative to sense current signals within an extremely broad range including very low currents (e.g., currents below the 1 pico-amp range, within the 10s of pico-amps range, below the 1 nano-amp range, within the 10s of nano-amps range, below the 1 micro-amp range, within the 10s of micro-amps range, etc.) and also up to relatively much larger currents (e.g., currents in the 10s milli-amps range, 100s milli-amps range, or even higher values of amps range, etc.). In some examples, such as with respect to detecting currents that are provided from a photodetection or photodiode component, such a companding ADC is also operative to sense current signals below the 1 pico-amp range, currents within the 100s of micro-amps range, etc. Also, in some examples, when using appropriately provisioned components (e.g., higher current, higher power, etc.), much higher currents can also be sensed using architectures and topologies in accordance with a companding ADC as described herein. For example, such a companding ADC implemented based on architectures and topologies, as described herein, using appropriately provisioned components are be operative to sense even higher currents (e.g., is of amps, 10s of amps, or even higher values of amps range, etc.). In addition, note that various implementations of such a companding ADC may be implemented to cover a number of decades orders of magnitude. For example, consider a companding ADC that is implemented to detect current signals radiating from the 10s of pico-amps to ones of milli-amps. Such a companding ADC would cover a dynamic range of 7-8 decades or 7-8 orders of magnitude. Within such an example, such a very broad dynamic range may be divided using a log scale into the 7-8 decades, such that there are a few data points within each particular decade. Note also that there is a trade-off regarding the resolution of the digital output signal (e.g., the Do1and/or the Do2signal) that is generated by such a companding ADC and range of current signals that may be sensed. For example, when the dynamic range of signals to be sensed by such a companding ADC is relatively large, then there can be limitations on sensing very low currents with a high degree of accuracy. Generally speaking, the broader the dynamic range of signals to be sensed, then a higher resolution of the digital output signal (e.g., the Do1and/or the Do2signal) provides for a higher degree of accuracy, particularly when sensing very low currents. Consider an example in which currents within a dynamic range of 10s of pico-amps to 100s of micro-amps is to be sensed (e.g., within a photodetection or photodiode component), then generating a digital output signal using a certain number of bits (e.g., a resolution of 12 bits) may be insufficient to cover the entire range. Within such a particular example, increasingly resolution of the digital output signal (e.g., to a resolution of 16 bits) can help facilitate sensing of signals with higher resolution and also assist sensing very low currents with a high degree of accuracy. Several the following diagrams have similarities to the prior diagrams with at least one difference being that a non-linear N-bit DAC1920is implemented to generate the current that is output to a load that matches or tracks the current of the load. Similarly, as described with respect to other examples of an ADC, the companding ADCs of these subsequent diagrams also operate by providing an output current to the load32to cancel out the load current. This may be viewed as providing an output current that is equal to and opposite polarity to the load current. Note also that such a companding ADC may be implemented not only to sense an analog signal associated with the load32but also to provide power and/or energy to the load32within implementations where the load32is not energized via another source. In some examples, this providing of power and/or energy from the companding ADC to the load32is performed simultaneously via a single line via which the companding ADC senses and analog signal associated with the load32. Also, such a companding ADC may be implemented to perform sensing only of an analog signal associated with the load32without providing power and/or energy to the load32. Generally speaking, with respect to such non-linear N-bit DACs, such as the non-linear N-bit DAC1920, the output current provided there from is a non-linear function of the Do2. Therefore, the Do2itself is also an inverse function of the load current, given that the output current from the non-linear N-bit DAC1920is operative to match or track the current of the load (e.g., being equal and opposite of the current of the load thereby minimizing the error signal that is based on the difference between Vref and Vin). FIG.19is a schematic block diagram of an embodiment1900of an ADC that includes a non-linear N-bit digital to analog converter (DAC) in accordance with the present invention. This diagram is similar to certain of the previous diagrams (e.g.,FIG.4) that include a comparator and a digital circuit410that generates the Do1that is provided to the processing module24. The processing module24processes the Do1to generate the Do2. Also, an analog capacitor, C, is connected to a node that couples the load32to the companding ADC (e.g., an ADC that includes a non-linear N-bit digital to DAC, an ADC that provides for a non-linear response when generating a digital output signal based on the analog signal that it is sensing). However, in this diagram, a non-linear N-bit DAC1920is implemented to generate the current signal that is provided to the node that connects or couples the companding ADC to the load32to match and track the current signal of the load. Many of the subsequent diagrams include similar components and operate similarly with at least one difference being that they operate as companding ADCs such that they provide for a non-linear response when generating a digital output signal based on the analog signal that it is sensing. Many of the diagrams include a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.20is a schematic block diagram of another embodiment2000of an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.8with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.21is a schematic block diagram of another embodiment2100of an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.9with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.22is a schematic block diagram of another embodiment2200of an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.10with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.23is a schematic block diagram of an embodiment2300of an ADC that includes a non-linear N-bit DAC that is operative to process an analog differential signal in accordance with the present invention. This diagram is similar toFIG.11with a difference being that a differential non-linear N-bit DAC2320is implemented in place of the differential N-bit DAC1120. FIG.24is a schematic block diagram of another embodiment2400of an ADC that includes a non-linear N-bit DAC that is operative to process an analog differential signal in accordance with the present invention. This diagram is similar toFIG.12with a difference being that a differential non-linear N-bit DAC2320is implemented in place of the differential N-bit DAC1120. FIG.25is a schematic block diagram of an embodiment2500an ADC that includes a non-linear N-bit DAC and that is operative to perform voltage measurement in accordance with the present invention. This diagram is similar toFIG.14Awith a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. For example, implementing an appropriate element in-line between the companding ADC and a load voltage32-1(e.g., a resistor, R, a trans-impedance circuitry, and/or any appropriate complement to convert voltage to current, etc.) facilitates the conversion of the load voltage32-1to a load current that may be detected using such a companding ADC. In such an example, the non-linear N-bit DAC1920within the companding ADC operates based on a function of Do2. In an example that includes a resistor, R, implemented non-linear N-bit DAC1920, the Do2itself is an inverse function of the load voltage32-1divided by R (e.g., function of Vload/R). Certain of the following diagrams show the use of one or both of a PNP transistor (alternatively, Positive-Negative-Positive Bipolar Junction Transistor (BJT)) or an NPN transistor (alternatively, Negative-Positive-Positive BJT) to implement the non-linear conversion function. For example, the use of one or both of a PNP transistor or NPN transistor may be used to implement a logarithmic conversion function. In addition, certain of the following diagrams operate using a N-bit DAC420-1that provides an output voltage signal to be received by the base of an NPN transistor or a PNP transistor. In such examples, one or more of an NPN transistor or a PNP transistor is implemented to provide the current that matches or tracks the load current. Certain examples operate by sourcing current, and others operate by sinking current. Even other examples operate by providing both functionality of sourcing current and sinking current as may be required to match or track the load current. FIG.26Ais a schematic block diagram of an embodiment2601an ADC that includes a PNP transistor (alternatively, Positive-Negative-Positive Bipolar Junction Transistor (BJT)) implemented to source current in accordance with the present invention. Generally speaking, a BJT is a type of transistor including three terminals, a base (B), a collector (C), and an emitter (E). Such a BJT includes two semiconductor junctions that share a thin doped region in between them. Considering an NPN transistor, a thin p-doped region is implemented in between two n-type semiconductor regions thereby forming the two semiconductor junctions. Considering an PNP transistor, a thin n-doped region is implemented in between two p-type semiconductor regions thereby forming the two semiconductor junctions. With respect to such a transistor, the collector current, Ic, as a function of the voltage between the base (B) and emitter (E) is as follows: IC=IS(eqVBEkT-1), where, based on the Shockley diode equation or the diode law, Isthe reverse bias saturation current (alternatively referred to as scale current); VBEis the voltage across the semiconductor junction; VTis the thermal voltage, kT/q, which is the Boltzmann constant, k, times temperature, T, divided by electron charge, q. As such, the value of VBEis the output voltage of the N-bit DAC420-1, which operates based on a full-scale voltage shown as Vfull_scale, such that the N-bit DAC420-1is operative to provide an output voltage up to and including the full-scale voltage shown as Vfull_scale. Given that VBEis the output voltage of the N-bit DAC420-1, then it is also the conversion of the Do2to an analog signal. Therefore, the Do2is an inverse function of the above equation showing the collector current, Ic, as follows: Do2=VBE≈kTqln(ICIS) The full-scale voltage shown as Vfull_scale is a reference voltage for the N-bit DAC420-1, which also operates to control the full-scale output current.FIG.28BandFIG.28Cshow examples by which a temperature independent full-scale reference circuit may be implemented. Referring again toFIG.26A, this diagram shows a PNP transistor implemented to source current to a node that connects to the load32to match and track the load current. FIG.26Bis a schematic block diagram of an embodiment2602an ADC that includes an NPN transistor (alternatively, Negative-Positive-Positive BJT) implemented to sink current in accordance with the present invention. This diagram shows an NPN transistor implemented to sink current from a node that connects to the load32to match and track the load current. FIG.27is a schematic block diagram of an embodiment2700an ADC that includes both a PNP transistor implemented to source current and an NPN transistor implemented to sink current in accordance with the present invention. This diagram shows both a PNP transistor implemented to source current to a node that connects to the load32to match and track the load current and also an NPN transistor implemented to sink current from a node that connects to the load32to match and track the load current. In cooperation with one another, both the PNP transistor and the NPN transistor can operate either to sink or source current as may be needed to match and track the load current. FIG.28Ais a schematic block diagram of an embodiment2801an ADC that includes diodes implemented to source and/or sink current in accordance with the present invention. This diagram shows the two diodes implemented and controlled using switches, such as being controlled by the processing module24, to provide for sinking or sourcing current to or from the node that connects to the load32to match and track the load current. FIG.28Bis a schematic block diagram of an embodiment2802a PNP transistor diode configuration operative to generate a full scale voltage signal in accordance with the present invention. In addition, note that one way to have a temperature independent full-scale reference current is to use a PNP or NPN diode configuration to generate the full-scale voltage (Vfull_scale) based on an applied reference current Iref. This is to form a current mirror. The output bipolar transistor current to the load is a mirror copy of the reference current, Iref, which is scaled by the voltage value provided by the N-bit DAC420-1. The reference current is applied to the collector of the PNP (or NPN) and the base is connected to the collector to form a diode configuration. The base voltage of the PNP is the full-scale voltage (Vfull_scale) that is applied to the N-bit DAC. Such a configuration for a PNP transistor is shown with respect toFIG.28B. Such a configuration for an NPN transistor is shown with respect toFIG.28B. FIG.28Cis a schematic block diagram of an embodiment2803an NPN transistor diode configuration operative to generate a full scale voltage signal in accordance with the present invention. Such implementations of a companding ADC using one or more NPN transistors, PNP transistors, and/or diodes provide a number of advantages over prior art ADCs. For example, they may be operated using extremely low power. Also, they operate to provide direct conversion of a digital output (e.g., Do2) that is logarithmically proportional to the input current. Moreover, using an appropriate implementation, such as that described to provide a temperature independent full-scale reference current, such a companding ADC is temperature independent as opposed to the prior art ADCs, which are temperature dependent. Also, the accuracy and operation of such a companding ADC is independent of the Is current of the bipolar transistor [reverse bias saturation current (alternatively referred to as scale current)], which can have very wide tolerance across components. Certain of the following diagrams show the use of one or both of a P-channel or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) (alternatively, PMOS transistor) or an N-channel or N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (alternatively, NMOS transistor) to implement the non-linear conversion function. For example, the use of one or both of a PMOS transistor or an NMOS transistor may be used to implement a logarithmic conversion function. In addition, certain of the following diagrams operate using a N-bit DAC420-1that provides an output voltage signal to be received by the gate of an NMOS transistor or a PMOS transistor. In such examples, one or more of an NMOS transistor or a PMOS transistor is implemented to provide the current that matches or tracks the load current. Certain examples operate by sourcing current, and others operate by sinking current. Even other examples operate by providing both functionality of sourcing current and sinking current as may be required to match or track the load current. FIG.29Ais a schematic block diagram of an embodiment2901an ADC that includes a P-channel or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) (alternatively, PMOS transistor) implemented to source current in accordance with the present invention. For example, the use of one or both of an NMOS transistor or a PMOS transistor operates as a square root conversion function. For example, the drain current, ID, of a MOSFET is as follows: ID=μCOX2WL(VGS-VT)2,whereVGSis the voltage across the gate (G) to source (S) junction of the MOSFET;VTis the thermal voltage, kT/q, which is the Boltzmann constant, k, times temperature, T, divided by electron charge, q;W is gate width;L is gate length;μCoxis a process transconductance parameter; andμCox(W/L) is a MOSFET transconductance parameter. As such, the voltage across the gate (G) to source (S) junction of the MOSFET, VGS, is the output voltage of the N-bit DAC420-1. As such, the value of VGSis the output voltage of the N-bit DAC420-1. Given that VGSis the output voltage of the N-bit DAC420-1, then it is also the conversion of the Do2to an analog signal. Therefore, the Do2(shown as Do in the equation below) is a an inverse function of the above equation showing the drain current, ID, as follows: Do=VGS=2LμCOXWID-VT As can be seen, this shows the Do2(shown as Do in the equation above) as being a square root function of the input current, which is the drain current, ID. Also, note that parallel measurement similar to the log ratio-metric measurement may be used to remove the dependence on VT, which is the thermal voltage, kT/q, and which varies as a function of temperature. For example, a similar diode configuration and Iref current mirror as in the bipolar transistor variant can be applied here with respect to MOSFET devices. For example, consider generating a first digital output signal, shown as Do1below, and also a first digital output signal, shown as Do2below: Do1=VGS=2LμCOXWID1-VT,andDo2=VGS=2LμCOXWID2-VT, then the difference between them is as follows: Do1-Do2=2LμCOXWID1-2LμCOXWID2, which is temperature independent and has no dependence on VT, which is the thermal voltage, kT/q. Referring again toFIG.29A, this diagram shows a PMOS transistor implemented to source current to a node that connects to the load32to match and track the load current. FIG.29Bis a schematic block diagram of an embodiment2902an ADC that includes an N-channel or N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (alternatively, NMOS transistor) implemented to sink current in accordance with the present invention. This diagram shows an NMOS transistor implemented to sink current from a node that connects to the load32to match and track the load current. FIG.30is a schematic block diagram of an embodiment3000an ADC that includes both a PMOS transistor implemented to source current and an NMOS transistor implemented to sink current in accordance with the present invention. This diagram shows both a PMOS transistor implemented to source current to a node that connects to the load32to match and track the load current and also an NMOS transistor implemented to sink current from a node that connects to the load32to match and track the load current. In cooperation with one another, both the PMOS transistor and the NMOS transistor can operate either to sink or source current as may be needed to match and track the load current. FIG.31is a schematic block diagram showing an embodiment3100of digital domain filtering within an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.15with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.32is a schematic block diagram showing an embodiment3200of digital domain filtering using cascaded filters within an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.16with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.33is a schematic block diagram showing another embodiment3300of digital domain filtering using configurable/adjustable cascaded filters within an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.17with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIG.34is a schematic block diagram showing an embodiment3400of one or more processing modules implemented to perform digital domain filtering within an ADC that includes a non-linear N-bit DAC in accordance with the present invention. This diagram is similar toFIG.18with a difference being that a non-linear N-bit DAC1920is implemented in place of the N-bit DAC420. FIGS.35A,35B, and35Care schematic block diagrams showing various embodiments3501,3502, and3503, respectively, of analog to digital converters (ADCs) with improved bandwidth in accordance with the present invention. Referring to embodiment3501, this diagram has certain similarities with other diagrams, for example,FIG.4. An ADC is connected to or coupled to a load32via single line such that the ADC is configured to provide a load signal412via that single line and simultaneously to detect any effect414on that load signal via a single line (including any change thereof). In certain examples, the ADC is configured to perform single line drive and sense of that load signal412, including any effect414thereon via that single line. This embodiment similarly includes a charging capacitor, C, that is coupled to one or the inputs of a comparator as voltage signal, Vin. The other input of the comparator receives a reference voltage signal, Vref. The output of the comparator is provided to a digital circuit410(e.g., which is clocked by a clock signal CLK and is configured to generate a digital output signal Do1at the particular clock rate of the clock signal CLK). Note that while a comparator coupled to a digital circuit410is shown in this diagram note that such a combination of elements may be alternatively implemented using any of the variations found in certain other diagrams herein, such as with respect toFIG.5A. Note that any of the various implementations501,502,503,504, may alternatively be implemented in place of the combination of a comparator and a digital circuit410within this diagram and any other diagram herein. The output of the digital circuit410provides a digital output signal Do1. As may be desired, the digital output signal Do1is provided to one or more processing modules24that is configured to communicate and interact with one or more other devices as described herein. In some examples, the one or more processing modules24is configured to process the digital output signal Do1to generate another digital output signal Do2that is fed back to the N-bit DAC420that is configured to generate a feedback current signal Ifbk. That interacts with the load current Iloadto generate a quantization noise current, Iload−Ifbk, that charges the capacitor C thereby generating the voltage is provided to the input of the comparator that is coupled to that capacitor C. In this diagram, a current sensor3510is implemented and configured to measure the quantization noise current, Iload−Ifbk, that charges the capacitor C and thereby generates a signal that is representative of the quantization noise current, Iload− Ifbk. Note that the signal that is representative of the quantization noise current, Iload− Ifbk, maybe a scaled version of the quantization noise current, Iload−Ifbk(e.g., scaled by some scaling factor k<1). Note that any of a variety of types of current sensors may be implemented to effectuate the operation of the current sensor3510. Note that any such scheming information as may be performed by the current sensor3510when generating the signal that is representative of the quantization noise current, Iload−Ifbk, that it gets provided to the ADC3512will be compensated for as the ADC3512generates the output digital signal from the ADC3512that undergoes combination with the digital output signal Do2. For example, any appropriate information regarding scaling of the signal generated by the current sensor3510will be included within the digital signal that is generated by the ADC3512(e.g., if the signal generated by the current sensor3510corresponds to a scaled representation of the quantization noise current, Iload−Ifbk, by a factor of ½ then the ADC3512will scale up the digital output signal by a factor of 2; if the signal generated by the current sensor3510corresponds to a scaled representation of the quantization noise current, Iload−Ifbk, by a factor of ¼ then the ADC3512will scale up the digital output signal by a factor of 4; and so on). Some various options (non-exhaustive) by which current sensing and current sensing circuits may be implemented are shown with respect toFIGS.35D through35K. The current measurement signal that is provided from the current sensor3510is a signal that is representative of the sensed quantization noise current, Iload− Ifbk, that charges the capacitor C and thereby generates the voltage signal, Vinthat is provided to one of the inputs of the comparator. Note that this current measurement signal may be viewed as a signal that is representative of the quantization noise current, Iload−Ifbk. This current measurement signal is provided to an ADC3512that is configured to generate additional signal that is provided to a combiner (e.g., a subtract or a summer such that one of the inputs is inverted before combination) to be combined with the other digital output signal Do2to subtract the quantization noise from that other digital output signal Do2. The output of the combiner, after combination of the other digital output signal Do2and the digital signal that is generated by the ADC3512that corresponds to the quantization noise current (e.g., representative of the quantization noise current, Iload−Ifbk), is yet another/third digital output signal Do2′ that has significantly lower quantization noise than the other digital output signal Do2. Note that the ADC3512may be implemented similar to an ADC as shown in the top portion of the diagram, such as similar to that ofFIG.4and/or other implementations of an ADC as described herein. An ADC implemented based on this embodiment3501and others presented herein provide much improved bandwidth compared to other ADCs. For example, by sensing and subtracting the quantization noise current, or effectively within the digital domain by subtracting the quantization noise from the other digital output signal Do2, a signal having a much higher bandwidth may be achieved with relatively little complexity, if any. For example, an ADC as implemented based on this embodiment3501and others presented herein provide the benefits of a third or fourth quarter modulator, such as a sigma delta modulator, without any extra added complexity. By subtracting out the quantization noise from the digital output signal Do2, the other digital output signal Do2′ is generated that has a significantly extended operational bandwidth in comparison to the digital output signal Do2. In addition, such an ADC as implemented based on this embodiment3501and others presented herein may be implemented much more economically than prior art ADCs. Not only can such an ADC as implemented based on this embodiment3501and others presented herein be implemented to provide much improved performance including in terms of improved bandwidth, but it may also be implemented without any extra added complexity, and may be implemented more economically than prior art ADCs. As may be desired in certain implementations, the decimation filter may be implemented to process the other/third digital output signal Do2′ to generate yet another/fourth digital output signal Do2″ having a lower sampling rate and a higher resolution than the other/third digital output signal Do2′. In certain examples, note that the other/fourth digital output signal Do2″ is provided to one or more other devices such as one or more processing modules that is configured to process the other/fourth digital output signal Do2″ to interpret information contained therein. Also, many other embodiments, diagrams, etc. show one or more digital output signals being generated by the various components therein. Similarly, in certain examples, note that any such one or more digital output signals is provided to one or more other devices such as one or more processing modules that is configured to process the one or more digital output signals to interpret information contained therein. Within this diagram as well as any other diagram herein that includes a decimation filter, note that information included within the digital signal being provided to the decimation filter and the digital signal being output from the decimation filter both include comparable information. The decimation filter is operative to modify the sampling rate and resolution between digital signal being provided to the decimation filter and the digital signal being output from the decimation filter. The quantization noise current, Iload−Ifbk, that is provided to one of the inputs of the comparator that operates in cooperation with the digital circuit410is configured to generate a digital signal that is oversampled with a high-frequency clock in the digital circuit410. Again, the comparator and the digital circuit410may be implemented in an alternative implementation, yet the clock signal is such that it generates an oversampled digital output signal Do1. The N-bit DAC420is configured to generate the feedback current signal, Ifbk, that undergoes combination with the load current signal to generate the quantization noise current, Iload−Ifbk. In an ideal implementation, N of the N-bit DAC420is infinite such that the N-bit DAC four and20generates a feedback current signal having zero quantization noise. However, in a real application implementation, N of the N-bit DAC420is finite such that the feedback current signal, Ifbk, does include some effect that is caused by the quantization noise. Such an implementation of an ADC as shown in this diagram significantly expands the bandwidth of operation having a very high signal to noise ratio (SNR). For example, the operational frequency range extends significantly, in some instances up to 200-300 kHz (e.g., with a 20 MHz sampling rate), by sensing and removing the effects of the quantization noise current via the sensing of the quantization noise current, Iload− Ifbk, and combination with the digital output signal Do2thereby generating a digital output signal Do2′ having much lower quantization noise. The sensing of and subtracting of the quantization noise from the digital output Do2significantly improves the overall functionality of the ADC by extending the bandwidth having a very high SNR. Also, note that such an ADC is configured to consume a very low-power in operation. For example, in once this example, the entire power consumption of the ADC is approximately 6 milli-Watts (mW) (e.g., consuming less than 6 mW during operation). Note that the implementation of such an ADC includes a mixture of approximately 90% digital circuitry and 10% analog circuitry. One of the larger components in the overall ADC is the and-bit DAC420. Given the significant amount of digital circuitry within such an implementation, the power consumption of the ADC is very low. In addition, given the significantly small number of analog components within the ADC, thermal noise is significantly reduced. Generally speaking, reducing the number of analog components will facilitate reduction in thermal noise of the overall circuit. In some implementations, the digital output signal Do2′ (after subtraction of the quantization noise from the digital output signal Do2) or the other digital output signal Do2″ (output from the decimation filter) is implemented to have 14-16 bits of resolution. In some specific implementations when the bandwidth is extended even more significantly, and the resolution of these digital output signals Do2′ or Do2″ may be even greater, such as more than 20 bits of resolution (e.g., 21 bits of resolution in one specific example). With such an extension of bandwidth to an upper range of approximately 200-300 kHz (e.g., with a 20 MHz sampling rate), such an ADC that is operative to consume very little power and provide very high accuracy while also providing such a broad operational bandwidth, such an ADC may be implemented in a broad range of applications. For example, by providing an operational bandwidth up to approximately 100 kHz, such an ADC may be implemented within audio applications while providing high accuracy and while consuming very low-power. For example, considering audio applications, such as processing of human speech, such an ADC is configured to detect with very high accuracy even very small variations within a person's voice. Also, with respect to the ADC3512implemented near the bottom of the diagram, note that the ADC3512may be as simple as that 1-bit ADC. Such an ADC may be approximately ¼ of the size of the N-bit DAC420located towards the top of the diagram. In other implementations, the ADC3512is replaced with a single comparator. In addition, note that the one or more processing modules24may be viewed as operating as an integrator in certain examples. For example, consider a 6-bit digital output signal Do2coming out of the one or more processing modules24as being representative of the signal plus noise (e.g., as including quantization noise). In an example of operation and implementation, the analog to digital converter (ADC) includes a capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current. Note that the ADC is coupled to the load via a single line. The ADC also includes a current sensor that is operably coupled and configured to sense a quantization noise current that is based on the load current and the DAC output current and to generate a signal that is representative of the quantization noise current. The ADC also includes a comparator operably coupled and configured to receive the load voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate a comparator output signal. The ADC also includes a digital circuit that is operably coupled to the comparator and configured to process the comparator output signal to generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage. The ADC also includes one or more processing modules that is operably coupled to the digital circuit and the memory and configured to execute operational instructions (e.g., such as operational instructions stored in memory) to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage. In certain examples, the second digital output signal includes a higher resolution than the first digital output signal. The ADC also includes an N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules and configured to generate the DAC output current based on the second digital output signal. Note that N is a positive integer. Also, the DAC output current tracks the load current, and the load voltage tracks the reference voltage. The ADC also includes another ADC that is operably coupled to the current sensor and configured to generate a digital signal that is representative of the quantization noise current based on the signal that is representative of the quantization noise current. The ADC also includes a combining circuit that is operably coupled to the another ADC and the one or more processing modules and configured to subtract the digital signal that is representative of the quantization noise current from the second digital output signal to generate a third digital output signal. In certain examples, the one or more processing modules is further configured to process the first digital output signal in accordance with performing band pass filtering or low pass filtering to generate the second digital output signal that is representative of the difference between the load voltage and the reference voltage. In certain other examples, the comparator includes a sigma-delta comparator, and the digital circuit includes a clocked flip flop. In even other examples, a digital comparator includes both the comparator and the digital circuit. The digital comparator operably coupled and configured to receive the load voltage via a first input of the comparator, receive a reference voltage via a second input of the comparator, and compare the load voltage to the reference voltage to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage. In certain alternative examples, the ADC also includes a decimation filter coupled to the combining circuit. When enabled, the decimation filter operably coupled and configured to process the third digital output signal to generate a fourth digital output signal having a lower sampling rate and a higher resolution than the third digital output signal. Note that the load may be of any of a variety of types including an electrode, a sensor, or a transducer. In certain examples, the ADC includes an operational bandwidth having an upper range of 200 kHz or 300 kHz. Also, in certain specific implementations, the ADC is configured to consume less than 6 mW during operation. Referring to embodiment3502, this diagram is similar to the previous diagram with the least one difference being that the ADC3512shown at the bottom of the previous diagram is replaced with an N- or M-bit ADC3520. For example, this ADC at the bottom of the diagram may be implemented as an N-bit ADC3520similar to the N-bit DAC420at the top of the diagram (e.g., N corresponds to a positive integer less than or equal to 8 bit resolution, N<8). In one particular implementation, N corresponds to a positive integer less than or equal to 8 bit resolution (N<8), and M corresponds to a positive integer between 1 and 4 bit resolution (M=1 to 4), inclusive. In certain implementations as described above, the N- or M-bit ADC3520may be implemented using an M-bit ADC3520, such that M<N, given that the signal that is representative of the quantization noise current, Iload−Ifbk, that is generated by the current sensor3510will generally be a much smaller signal (e.g., a much smaller current signal in terms of magnitude) than the quantization noise current, Iload−Ifbk, itself. In this diagram, the N- or M-bit ADC3520is implemented instead of the ADC3512of the previous diagram. For example, the N- or M-bit ADC3520is operably coupled to the current sensor and configured to generate a digital signal that is representative of the quantization noise current based on the signal that is representative of the quantization noise current. Note that M is a positive integer that is less than or equal to N. Referring to embodiment3503, this diagram has certain similarities with the previous two diagrams with at least one difference being that the ADC at the bottom of the prior two diagrams is replaced with a comparator operating in conjunction with a digital circuit410that is clocked by a clock signal CLK. In this diagram, a charging capacitor C is connected to one of the inputs of the comparator to generate a voltage signal at that input of the comparator. In addition, a reference voltage Vref (QN) is provided to the other input of the comparator to facilitate detection of a voltage signal corresponding to the quantization noise current, Iload−Ifbk. Also note that the combination of the comparator and the digital circuit410may alternatively be implemented using any of a number of variations including those described with respect toFIG.5A. In this diagram, a first and second charging capacitor C, a first and second comparator, and a first and second digital circuit410are implemented. The second charging capacitor C, the second comparator, and the second digital circuit410are implemented instead of the ADC3512or the N- or M-bit ADC3520of the previous diagrams. FIGS.35D,35E,35F,35G,35H,35I,35J, and35Kare schematic block diagrams showing various embodiments3504,3505,3506,3507,3508,3509,3521, and3522, respectively, of current sensor circuitry that may be implemented in accordance with the present invention. These diagrams show some samples of various means by which current may be sensed. Note that these examples are non-not exhaustive and any other equivalent type current sensing capable device may alternatively be used. Referring to embodiment3504, a current sensor3510generates a current signal I2that is representative of the current flowing through the line from left to right I1. For example, the current signal I2may be a scaled up or scale down versions of the current signal I1. Such a current sensor3510may be implemented in a variety latest including a ferromagnetic current sensor that encompasses the wire or line that includes the current signal I1being sensed. Based on the coupling of magnetic field is generated by the current signal I1within the ferromagnetic current sensor, the current signal I2is induced within the magnetic core of the ferromagnetic current sensor. Referring to embodiment3505, a current sensor3510-1generates a voltage signal Voutthat is representative of the current flowing through the line from left to right I1. For example, the voltage signal Voutmay is a signal that is representative of the current signal I1. There may be some instances in which a voltage signal Voutthat is representative of the current signal I1is more desirable than a current signal I2that is representative of the current signal I1. Referring to embodiment3506, in this diagram, the current signal I1is provided to a resistor R1. The difference in voltage between the two ends of the resistor R1(V1and V2) along with the value of the resistor R1are used to determine the current signal I1based on Ohm's Law (Delta V=ΔV=V1−V2=I1×R1, and I1=(V1−V2)/R1). Note that the symbol A is sometimes used in place of the word Delta herein, and vice versa; they both mean the same thing being the difference of, change of, difference between two values, etc. as is understood in the art. Referring to embodiment3507, this diagram shows a current mirror circuit. This included two transistor implementation of the current mirror that is based on the relationship that two equal sized transistors at the same temperature with the same characteristics, such as the VBE(voltage drop between the base and emitter of an NPN transistor in this implementation of two NPN BJTs (alternatively, Negative-Positive-Negative Bipolar Junction Transistors)) have the same collector current Ic. The current mirror is a circuit that functions to produce a copy of the current flowing into or out of an input terminal, such as the current signal I1that is flowing through the resistor R1and into the collector of the transistor Q1on the left-hand side of the diagram. The collector and the base of the transistor Q1are connected together. Also, the collector of the transistor Q1is connected to the base of the transistor Q2. The voltage at the collector note of the transistor Q1corresponds to the VBEof that same transistor Q1. This same voltage potential is provided to the base of the transistor Q2. As such, of the current signal I2that will be induced to flow at the collector note of the transistor Q2will be the same as the current signal I1. Referring to embodiment3508and3509, these diagrams correspond to high side current sensing and low side current sensing, respectively based on a load being implemented above or below a resistor R1. A power supply voltage, Vpwr supp, provides a voltage potential that is higher than ground and thereby facilitates the flow of current signal I1via the load and the resistor R1. One or more operational amplifiers/circuits is implemented to generate an output voltage signal Voutthat is representative of the current signal I1that is flowing via the load and the resistor R1. Referring to embodiment3508, this diagram depicts high side current sensing such that the current sensing connects to the resistor between the power supply of the load. The sensed voltage signal may be scaled, such as amplified, by one or more operational amplifiers/circuits to generate the output voltage signal Voutthat is representative of the current signal I1that is flowing via the load and the resistor R1. Some advantages of performing include eliminating ground disturbance, detecting the high load current caused by accidental electrical shorts, having the load connecting to the system ground directly, etc. Referring to embodiment3509, this diagram depicts low side current sensing such that the current sensing connects to the resistor between the load and ground. The sensed voltage signal may be scaled, such as amplified, by one or more operational amplifiers/circuits to generate the output voltage signal Voutthat is representative of the current signal I1that is flowing via the load and the resistor R1. Some advantages of performing low side current sensing include providing a low input common mode voltage, a ground referenced input and output, and a relatively simple and low-cost implementations, etc. Referring to embodiment3521, this diagram shows a metal-oxide-semiconductor field-effect transistor (MOSFET) current splitter implemented using PMOS transistors. For example, consider a current signal I1entering the node connected to the sources of the PMOS transistors of the MOSFET current splitter. Also, a voltage bias, Vbias is provided to the gates of the PMOS transistors of the MOSFET current splitter. Considering a MOSFET current splitter that includes two PMOS transistors M1and M2of the same size, then the current signal I1will be evenly split between the two PMOS transistors M1and M2as follows: I1=I1a+I1b, and I1a=I1b. Alternatively, considering a MOSFET current splitter that includes two PMOS transistors M1and M2of not of the same size, and PMOS transistor M1is less in size than the PMOS transistor M2, then the current signal I1will be split between the two PMOS transistors M1and M2as follows: I1=I1a+I1b, and I1a<I1b. In an alternative implementation, considering a MOSFET current splitter that includes two PMOS transistors M1and M2of not of the same size, and PMOS transistor M1is greater in size than the PMOS transistor M2, then the current signal I1will be split between the two PMOS transistors M1and M2as follows: I1=I1a+I1b, and I1a>I1b. Referring to embodiment3522, this diagram shows a bipolar current splitter implemented using PNP transistors (alternatively, Positive-Negative-Positive Bipolar Junction Transistors (BJT)). For example, consider a current signal I1entering the node connected to the emitters of the PNP BJT transistors of the bipolar current splitter. Also, a voltage bias, Vbias is provided to the bases of the PNP BJT transistors of the bipolar current splitter. Considering a bipolar current splitter that includes two PNP BJT transistors Q1and Q2of the same size, then the current signal I1will be evenly split between the two PNP BJT transistors Q1and Q2as follows: I1=I1a+I1b, and I1a=I1b. Alternatively, considering a bipolar current splitter that includes two PNP BJT transistors Q1and Q2of not of the same size, and PNP BJT transistor Q1is less in size than the PNP BJT transistors Q2, then the current signal I1will be split between the two PNP BJT transistors Q1and Q2as follows: I1=I1a+I1b, and I1a<I1b. In an alternative implementation, considering a bipolar current splitter that includes two PNP BJT transistors Q1and Q2of not of the same size, and PNP BJT transistor Q1is greater in size than the PNP BJT transistors Q2, then the current signal I1will be split between the two PNP BJT transistors Q1and Q2as follows: I=I1a+I1b, and I1a>I1b. Note that any one of these examples of different ways in which to perform current sensing may be limited within an ADC as described herein. Generally speaking, any desired current sensor implementations may be used in various embodiments of the invention. FIG.35Fshows multiple performance diagrams of ADC output3581,3582,3583, and3584, respectively, expressed as power spectral density (PSD [dB]) as a function of frequency (kilo-Hertz [kHz]) in accordance with the present invention. Referring to diagram3581, this diagram shows the ADC output with no thermal noise in the clock jitter effect. The ADC providing improved bandwidth as described herein by subtracting out the quantization noise from the digital output Do2(e.g., shown as improved IADC in the diagram). As can be seen, the operational bandwidth of the ADC is significantly extended in the upper frequency ranges (e.g., into the 100s of kHz and even the low/10s of MHz upper limits). Referring to diagram3582, this diagram shows the ADC output with thermal noise and also with clock jitter effect. The thermal noise raises the overall noise floor within the ADC providing improved bandwidth, but the ADC providing improved bandwidth still provides improved bandwidth as described herein by subtracting out the quantization noise from the digital output Do2(e.g., shown as improved IADC in the diagram). Note that the thermal noise dominates at lower frequencies in the quantization noise dominates at higher frequencies. By subtracting out quantization noise from the digital output Do2, the operational bandwidth of the ADC is it significantly extended (e.g., into the 100s of kHz and even the low/10s of MHz upper limits). Referring to diagram3583, this diagram shows the ADC output with thermal noise and also shows that quantization noise is largely negligible at lower frequencies. Although quantization noise can become exacerbated at higher frequencies, the ADC providing improved bandwidth does provide an operational bandwidth extending into the higher frequencies (e.g., into the 100s of kHz and even the low/10s of MHz upper limits). As can be seen in this diagram, such an ADC providing improved bandwidth as described herein helps lower the quantization noise at higher frequencies. As can also be seen in this diagram, the ADC providing improved bandwidth provides improved bandwidth as described herein by subtracting out the quantization noise from the digital output Do2(e.g., shown as improved IADC in the diagram). Referring to diagram3584, this diagram also shows the ADC output with thermal noise and also with clock jitter effect. As can also be seen in this diagram, the ADC providing improved bandwidth provides improved bandwidth as described herein by subtracting out the quantization noise from the digital output Do2(e.g., shown as improved IADC in the diagram). FIG.36Ais a schematic block diagram showing an embodiment3601of an ADC implemented with a thermometer decoder in accordance with the present invention. Referring to embodiment3601, this diagram has certain similarities to others herein including a single line that is coupled from the ADC to a load32, thereby facilitating single line drive and sense by providing a load signal412and detecting an effect414on that load signal, a charging capacitor C, a comparator implemented with a digital circuit410(which may alternatively be implemented using any of the variations including those inFIG.5A), etc. However, this diagram has certain differences from other diagrams herein as well. For example, a N-bit accumulator3610(shown as N-bit ACC3610and the diagram) is implemented to process the digital output signal from the digital circuit410(or alternative one or more components that generates the digital output signal generated by those one or more components). For example, the N-bit accumulator3610is configured to convert the digital output signal to a digital signal having a certain number of bits. In some examples, this operation involves converting a digital output signal that includes one bit every clock signal of the clocking signal that is provided to the digital circuit410to an N-bit signal that includes N-bits every clock signal. In one specific example, this operation involves conversion of a one-bit digital signal to a 7-bit signal or an 8-bit signal. Generally speaking, the N-bit accumulator3610may be configured in various alternative implementations to generate an N-bit signal having any desired number of bits, such that N is a positive integer greater than or equal to 2. Note also that the decimation filter may be implemented to process the output digital signal from the N-bit accumulator3610as well. For example, the decimation filter is configured to process the digital output signal provided from the N-bit accumulator3610to generate another digital output signal having a lower sample rate and a higher resolution. In addition, the digital signal that is generated by the N-bit accumulator3610is provided to a thermometer decoder3612. The thermometer decoder3612is configured to generate an output symbol that includes a sequence of 0s followed by a sequence of is in most instances, or alternatively all 0s or all Is. For example, with respect to a thermometer code, there cannot be any 0s in between two Is. Generally speaking, with respect to a thermometer code, an input value representing a particular number (e.g., 3=011 binary) generates an output value such that the lowermost bits are all of value 1, and the other uppermost bits or all of value 0. Generally speaking, for an n-bit binary code, the corresponding thermometer code will have 2n−1 symbols. As such, as many bits are needed to represent the thermometer code. The top portion of the diagram pictorially illustrates an example of a thermometer code with 8 symbols each having 7 bits. Consider 8 binary input symbols composed of 3 bits each: 0=000, 1=001, 2=010, 3=011, 4=100, 5=101, 6=110, and 7=111. Based on the input value, the thermometer code will generate the following output symbols. Input 0=000, then output=0000000 Input 1=001, then output=0000001 Input 2=010, then output=0000011 Input 3=011, then output=0000111 Input 4=100, then output=0001111 Input 5=101, then output=0011111 Input 6=110, then output=0111111 Input 7=111, then output=1111111 Note that while this example corresponds to a thermometer code operating on input symbols composed of three bits each and generating output symbols composed of seven bits each, different sized thermometer codes may alternatively be implemented using the thermometer decoder3612. For example, consider input symbols composed of 7 or 8 bits each, then corresponding output symbols in accordance with the thermometer code may be generated based on these principles. In an example of operation and implementation, the thermometer decoder3612outputs thermometer code symbols based on the inputs provided from the N-bit accumulator3610. A number of PNP BJTs (alternatively, Positive-Negative-Positive Bipolar Junction Transistors) and NPN BJTs (alternatively, Negative-Positive-Positive BJTs) are implemented to perform digital to analog conversion of the output symbols provided from the thermometer decoder3612. Generally speaking, any desired total number X of PNP BJTs and NPN BJTs are implemented (e.g., consider Nb PNP BJTs and also Nb NPN BJTs, such that Nb is a positive integer greater than or equal to 2). By using a thermometer decoder3612to provide the inputs to and facilitate the operation of the Nb PNP BJTs and also Nb NPN BJTs that are implemented to perform digital to analog conversion thereby generating a source current and/or a sink current, as few as only one current source for current sink is switched on or off at a time during any transition between two successive respective values output by the thermometer decoder3612. For example, consider the input to the thermometer decoder3612transitioning from 2=010 to 3=011, then the output from the thermometer decoder3612would transition from 0000011 to 0000111. Note that only one bit of the output from the thermometer decoder3612changes during such a transition. By using a thermometer decoder3612to facilitate operation of the Nb PNP BJTs and also Nb NPN BJTs that are implemented to perform digital to analog conversion, a significant reduction in noise may be facilitated with respect to the adaptation of a source current and/or a sink current that is set back within the ADC to regulate the input voltage (Vin) to the comparator to the input reference voltage (Vref) to the comparator. This implementation provides a significant improvement over alternative implementations that would switch on or off a large number of current sources and/or current sinks. The thermometer decoder3612facilitates adaptation of the feedback source current and/or a sink current in a manner that is very low noise, high precision, etc. In certain examples, note that the sampling rate within such an ADC implemented with a thermometer decoder is programmable. For example, the sampling rate may be anywhere within the range of 400 kHz to 40 MHz in certain implementations. In addition, the reference currents that may be used within such an ADC implemented with a thermometer decoder may be of extremely low value, such as varying between 1 μA to 100 μA in certain implementations. Also, in certain examples, note that the input reference voltage signal Vref is provided as a programmable sinusoidal signal. Note that such an ADC implemented with a thermometer decoder is operative to operate using very low power, and can sink and or source current to the load32. FIGS.36B and36Care schematic block diagrams showing embodiments3602and3603, respectively, of one or more PNP BJTs (alternatively, Positive-Negative-Positive Bipolar Junction Transistors) and NPN BJTs (alternatively, Negative-Positive-Positive BJTs) implemented to sink and source current within embodiments of ADCs implemented with a thermometer decoder in accordance with the present invention. Referring to embodiment3602, this diagram shows the number of NPN BJTs (e.g., Nb NPN BJTs) that are implemented such that an output symbol from a thermometer decoder is provided to the respective base terminals of the NPN BJTs. For example, each of the respective bits of the output symbol from the thermometer decoder is provided via a respective line to a respective one of the base terminals of the NPN BJTs. Considering an example of an output symbol from the thermometer decoder being 0000011, then the respective bits that are provided via the respective lines to the base terminals of the NPN BJTs are as follows: 0 is provided to 5 of the NPN BJTs, and 1 is provided to 2 of the NPN BJTs (e.g., 0 to NPN BJT 1, 0 to NPN BJT 2, 0 to NPN BJT 3, 0 to NPN BJT 4, 0 to NPN BJT 5, 1 to NPN BJT 6, and 1 to NPN BJT 7). As mentioned above, when the output from the thermometer decoder changes up or down by a particular value, only one of the bits of the output symbol of the thermometer decoder changes, and as such, only one of the respective NPN BJTs is switched on or off Such an implementation of a number of NPN BJTs is configured to sink current based on the number of NPN BJTs that are switched on in response to the output symbol from the thermometer decoder. Referring to embodiment3603, this diagram shows the number of PNP BJTs (e.g., Nb PNP BJTs) that are implemented such that an output symbol from a thermometer decoder is provided to the respective base terminals of the PNP BJTs. This operates similarly to the implementation of the previous diagram with a difference being that the number of PNP BJTs is configured to source current based on the number of PNP BJTs that are switched on in response to the output symbol from the thermometer decoder. As such, the desired sink current and/or source current is provided to the single line that is connected to and/or coupled to the load32. Implementing both the embodiments3602and3603, as such, the desired sink current and/or source current is provided to the single line that is connected to and/or coupled to the load32. Note that various implementations may include the structure of one or both of the embodiments3602and/or3603as may be desired in various implementations that may operate by sinking and/or sourcing current. FIG.36Dis a schematic block diagram showing an alternative embodiment3604of an ADC implemented with a thermometer decoder in accordance with the present invention. This diagram is similar to the embodiment3601ofFIG.36Awith at least one difference being that the PNP BJTs (alternatively, Positive-Negative-Positive Bipolar Junction Transistors) and NPN BJTs (alternatively, Negative-Positive-Positive BJTs) are replaced respectively with PMOS and NMOS metal-oxide-semiconductor field-effect transistors (MOSFETs) (PMOS and NMOS transistors). The PMOS and NMOS transistors operate similarly to source and/or sink current based on the to the single line that is connected to and/or coupled to the load32. In certain examples, it is preferable to implement PMOS and NMOS transistors instead of PNP and NPN BJTs to source and/or sink current. FIGS.36E and36Fare schematic block diagrams showing embodiments of one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) including one or more PMOS transistors and NMOS transistors implemented to sink and source current within embodiments of ADCs implemented with a thermometer decoder in accordance with the present invention. Referring to embodiments3605and3606, these diagrams are similar to the embodiments3602and3603ofFIG.36BandFIG.36C, respectively, with at least one difference being that the PNP BJTs (alternatively, Positive-Negative-Positive Bipolar Junction Transistors) and NPN BJTs (alternatively, Negative-Positive-Positive BJTs) are replaced respectively with PMOS and NMOS metal-oxide-semiconductor field-effect transistors (MOSFETs) (PMOS and NMOS transistors). Referring to embodiment3605, this diagram shows the number of NMOS transistors that are implemented such that an output symbol from a thermometer decoder is provided to the respective gate terminals of the NMOS transistors. For example, each of the respective bits of the output symbol from the thermometer decoder is provided via a respective line to a respective one of the gate terminals of the NMOS transistors. Such an implementation of a number of NMOS transistors is configured to sink current based on the number of NMOS transistors that are switched on in response to the output symbol from the thermometer decoder. As such, the desired sink current is provided to the single line that is connected to and/or coupled to the load32. Referring to embodiment3606, this diagram shows the number of PMOS transistors that are implemented such that an output symbol from a thermometer decoder is provided to the respective gate terminals of the PMOS transistors. This operates similarly to the implementation of the previous diagram with a difference being that the number of PMOS transistors is configured to source current based on the number of PMOS transistors that are switched on in response to the output symbol from the thermometer decoder. As such, the desired source current is provided to the single line that is connected to and/or coupled to the load32. Implementing both the embodiments3605and3606, as such, the desired sink current and/or source current is provided to the single line that is connected to and/or coupled to the load32. Note that various implementations may include the structure of one or both of the embodiments3605and/or3606as may be desired in various implementations that may operate by sinking and/or sourcing current. FIG.36Gis a schematic block diagram showing an alternative embodiment3607of an ADC implemented with a thermometer decoder in accordance with the present invention. Referring to embodiment3607, this diagram has similarity to the embodiment3601and embodiment3604with at least one difference being that the Nb PNP BJTs and also Nb NPN BJTs or replaced by resistor banks that operate to sink and/or source current. For example, consider a number of resistors (e.g., R1to Rxconnected to ground to sink current and/or R1to Rxconnected to ground to a power supply such as VDD to source current) that are implemented within respective resistor banks such that any desired number of those resistors in each of the respective banks may be connected or disconnected as desired to facilitate a particular current sink and/or current source to be fed back to the single line that is connected to and/or coupled to the load32. In an example of operation and implementation, a smaller sink current and/or smaller source current is provided from the respective resistor banks based on all of the resistors therein being switched in. For example, number of resistors implemented in parallel provides a lower resistance than any one of the respective resistor is singularly switched in while the others are not connected. Based on the value of the output symbol from the thermometer decoder3612, the appropriate number of resistors are switched in within the one or more resistor banks thereby facilitating the desired current sink and/or current source to be fed back to the single line that is connected to and/or coupled to the load32. Note that alternative implementations, circuits, etc., may be implemented to provide the desired current sink and/or current source to be fed back to the single line that is connected to and/or coupled to the load32based on the value of the output symbol from the thermometer decoder3612. For example, a number of independent and/or dependent current sources may alternatively be implemented and controlled based on the output symbol from the thermometer decoder3612, a number of current buffers may alternatively be implemented and controlled based on the output symbol from the thermometer decoder3612, etc. FIGS.37A,37B, and37Care schematic block diagrams showing various embodiments3701,3702, and3703, respectively, of differential current sensing circuits in accordance with the present invention. Referring to embodiment3701, the two respective inputs to a comparator are connected via two respective resistors Rs that connect to the two respective terminals of a resistor R. One of the terminals of the resistor R is connected to load32. Based on the voltage difference across the resistor R (Delta V=V1−V2, such that V1is the voltage at one of the terminals of the resistor R and V to is the voltage at the other terminal of the resistor R that is connected to load32), the current I flowing through the resistor R is measured using the differential current sensing circuit. The differential current sensing circuit includes the comparator whose inputs are connected via the two respective resistors Rs. The output signal from the comparator is provided to digital circuit410that is configured to generate digital output signal Do1. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. One or more processing modules24is configured to process the digital output signal Do1to generate another digital output signal Do2. In certain examples, a decimation filter is implemented to process the digital output signal Do2to generate another digital output signal Do3. For example, the decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. The digital output signal Do2is also provided to a differential N-bit DAC1120, wherein N is a positive integer. The differential N-bit DAC1120is operative to generate a differential output current signal that is provided to the differential load lines that are respectively connected to the inputs of the comparator. Also, a capacitor C is connected between the respective inputs of the comparator. In alternative implementations, two respective single-ended capacitors, C, are respectively connected to the differential signal lines and to ground instead of the capacitor, C, connected to the differential lead lines (e.g., a first single ended capacitor, C, connected to one of the differential signal lines and to ground, and a second single ended capacitor, C, also connected to the other of the differential signal lines and to ground). Note that the two respective resistors Rs are implemented to convert the voltages V1and V2to respective current signals I1and I2, respectively, to be provided to the respective inputs of the comparator. As such, differential current sensing is performed, which senses (V2−V1)/Rs. by knowing Rs, then the current flowing through the resistor R may be determined. In addition, note that a voltage source is implemented to supply the voltage V1to facilitate current flow I through the resistor R. The current flowing to the load Iload is the difference between the current I and the current I2(Iload=I−I2). As can be seen, this differential current sensing circuit has similarities to an ADC as described herein that is configured to sense current. By implementing the resistor R, the ADC is configured to sense the differential voltage across the resistor R (after conversion of that differential voltage to current signals via the two respective resistors Rs), and the ADC is then configured to determine the current I flowing through the resistor R based on the voltages V1and V2based on the following relationship. DeltaV=V2−V1=I×R I=(V2−V1)/R In certain examples, note also that the majority of components of this differential current sensing circuit may be implemented on-chip (e.g., within an integrated circuit). For example, as can be seen by the dotted line extending from the lower left of the diagram upward into the right, all the components to the right of the dotted line may be implemented on-chip. The other components may be implemented off-chip in certain examples. As such, an integrated circuit having the two respective outputs, pins, leads, etc. to facilitate connection to the two respective resistors Rs is configured to connect with such off-chip components to facilitate differential current sensing of the current flowing through the resistor R that is connected to the load32. This differential current sensing circuit provides a relatively low complexity circuitry that is operative to sense current. Note that this differential current sensing circuit has some similarities to other implementations described herein of an ADC as described herein that is configured to sense current. By modifying certain connectivity and components of those other implementations of an ADC, a very high accuracy current measurements may be made by generating and using the differential current sensing circuit of this diagram. Referring to embodiment3702, this diagram is similar to the previous diagram with at least one difference being that this diagram includes two respective buffers implemented in-line via the lines that connect to the inputs of the comparator. These buffers are implemented to facilitate isolation between the inputs of the comparator and the two respective resistors Rs while still providing signals representative of the current signals flowing through the two respective resistors Rs. In an implementation in which many of the components are implemented on-chip, these buffers also operate to provide isolation between the on-chip components and the off-chip components. Generally speaking, a current buffer is configured to present a signal source from being effective by other electrical effects. For example, a current buffer is configured to transform a current from a first circuit to a second circuit. Often times the first circuit has a relatively lower output impedance then the second circuit, which has a relatively higher output impedance. The current buffer is configured to prevent the two respective circuits from loading one another thereby generating any adverse effects that may interfere with the desired operation of the circuits. In an example of operation and implementation, a current buffer is configured to transfer current signal from the input to the output such that the current is unchanged. In some implementations, the gain of such a current buffer is 1 or unity, such that the output current follows or tracks the input current. In alternative implementations, the output current is a scaled version of the input current (e.g., scaled up or down as may be desired in a particular implementation). Referring to embodiment3703, this diagram is similar to the previous two diagrams with at least one difference being that this diagram includes a differential buffer implemented in-line via the lines that connect to the inputs of the comparator. For example, comparing this diagram to the previous diagram, a differential buffer is implemented in place of the two respective buffers that are implemented in-line via the lines that connect to the inputs of the comparator. The differential buffer of this diagram operates similarly to provide isolation between the on-chip components and the off-chip components. FIGS.38A and38Bare schematic block diagrams showing various embodiments3801and3802, respectively, of power sensing circuits in accordance with the present invention. Referring to embodiment3801, portions of this diagram have similarities to other diagrams in. For example, the components on the left-hand side of the diagram, to the left of the dotted line, the implementation of a voltage source, a resistor R such that one of its terminals is connected to load32, and two respective resistors Rs that are connected to the two respective terminals of the resistor R, are similar to the previous diagrams (e.g.,FIGS.37A,37B, and37C). However, that in this diagram, each of the two respective resistors Rs is connected to a respective ADC that is configured to measure current. For example, the two respective ADCs are configured to measure the two respective currents I1and I2that travel respectively via the two resistors Rs. A first ADC is implemented to measure the current I1, and a second ADC is implemented measure the current I2. For example, each of the respective ADCs that is configured to measure current includes a capacitor C that is connected to one of the inputs of a comparator, and the other input of the comparator is provided with an input voltage reference signal Vref. The output from the comparator is provided to a digital circuit410that is configured to generate a digital output signal Do1. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. One or more processing modules24is configured to process the digital output signal Do1to generate another digital output signal Do2. In certain examples, a decimation filter is implemented to process the digital output signal Do2to generate another digital output signal Do3. For example, the decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Note that the digital output signals Do1, Do2, and Do3may be understood with reference to the ADC implemented on the bottom right hand portion of the diagram. Similarly, the digital output signals Do3, Do4, and Do6may be understood with reference to the ADC implemented on the upper right hand portion of the diagram. The digital output signal Do2is also provided to an N-bit DAC420that is configured to generate an output current signal that is provided to the line that is connected to one of the input of the comparator, namely, the input is connected to the capacitor C and is also connected to one of the resistors Rs. In an example of operation and implementation, a first ADC is configured to measure the current I1flowing through one of the resistors Rs, and a second ADC is configured to measure the current I2flowing through the other one of the resistors Rs. Once the measurement of these two respective currents I1and I2are known, based on the current sensing of the first ADC of the second ADC, then the current I flowing through the resistor R may be calculated. Once the current I flowing to the resistor R and the current I2are known, then the current being delivered to the load32may be calculated based on Iload=I−I2. Note that either one of the instantiations of the one or more processing modules24may be implemented to perform such calculations (e.g., in some examples, they are in communication with one another via a communication link), and/or one or more other processing modules (not shown) that may be implemented to process the digital output signals Do3and Do6to perform such calculations. The digital output signal Do6(and/or the corresponding input to the decimation filter Do5) is the digital signal that is representative of the current I2, and the digital output signal Do3(and/or the corresponding input to the decimation filter Do2) is the digital signal that is representative of the current I1. For example, the respective digital output signals Do3and Do6or representative of the two respective currents I1and I2. Sense I1: Do3corresponds to (V1−Vref)/Rs. Sense I2: Do6corresponds to (V2−Vref)/Rs. V1and V2can be determined based on knowing Vref, Rs, and Do3as well as Do6. I1=(V1−Vref)/Rs I2=(V2−Vref)/Rs The current I flowing through the resistor R may be calculated based on: I=(V1−V2)/R Once these values have been calculated, the power being delivered to the load32may be calculated based on: Power=Iload×V2=(I−I2)×V2 Referring to embodiment3802, this diagram is similar to the previous diagram with at least one difference being that buffers are implemented in-line with respect to the lines that connect from one of the inputs of the comparator to the respective resistors Rs. As described above, such buffers are implemented to facilitate isolation between the inputs of the comparators and the two respective resistors Rs while still providing signals representative of the current signals flowing through the two respective resistors Rs. In an implementation in which many of the components are implemented on-chip, these buffers also operate to provide isolation between the on-chip components and the off-chip components. FIGS.39A and39Bare schematic block diagrams showing various embodiments3901and3902, respectively, of impedance sensing circuits (including complex impedance sensing capability) in accordance with the present invention. Referring to embodiment3901, this diagram also has certain similarities to other embodiments, diagrams, etc. herein including an ADC that is configured to sense current. For example, this diagram includes a capacitor C connected to one of the input terminals of the comparator, the comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1, one or more processing modules24is configured to process the digital signal Do1to generate another digital signal Do2that is provided as an input to an N-bit DAC420, the N-bit DAC420is configured to generate a feedback current signal that is provided to the single line that is connected to and/or coupled to the load32such that the single line connects to the input terminal of the comparator to which the capacitor C is connected. Also, as may be desired in certain applications, a decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. A signal generator is configured to provide an input voltage reference signal Vref to the other input terminal of the comparator. In addition, the input voltage reference signal Vref is provided to a quadrature generator. The quadrature generator is configured to generate a pair of quadrature sine and cosine signals based on the input voltage reference signal Vref. The pair of quadrature sine and cosine signals are provided to a demodulator that is configured to receive the digital output signal Do3from the decimation filter and to extract in-phase and quadrature (I and Q) signal components therefrom. The in-phase component I is generated within the demodulator and corresponds to the sine signal output from the quadrature generator multiplied by the digital output signal Do3. The quadrature component Q is generated within the demodulator and corresponds to the cosine signal output from the quadrature generator multiplied by the digital output signal Do3. In an example of operation and implementation, consider an implementation which the load32includes a reactive component, such as based on having characteristics of a capacitor and/or inductor, thereby having an impedance component that includes capacitive reactance and/or inductive reactance. For example, consider that the impedance of the load32is both resistive and reactive such that Z=R+j X, where the reactive impedance component X may correspond to capacitive reactance, inductive reactance, or some combination thereof. For example, consider Z=R+j XLor Z=R−j XC, such that XL=ωL and XC=−(1/ωC), etc. where ω=2πf, where f is frequency, and j is the imaginary unit that is the square root of −1. Note that when both inductive reactance and capacitive reactance are both present, they may be combined together to generate the reactive impedance component X=XL+XC=ωL−(1/ωC). Note that Z is the complex impedance, measured in Ohms. R is the resistance, measured in Ohms and is the real part of the complex impedance Z. X is the reactance, measured in Ohms and is the imaginary part of the complex impedance Z. By extracting and generating the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3, both any real and any reactance components of the impedance of the load32may be determined. By having both the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3, the total impedance including the complex impedance of the load32may be determined. For example, the sine signal generated by the quadrature generator multiplied by the digital output signal Do3provides the in-phase component of the complex impedance of the load32corresponding to the real part of the complex impedance Z. The cosine signal generated by the quadrature generator multiplied by the digital output signal Do3provides the quadrature component of the complex impedance of the load32corresponding to the reactive/imaginary impedance component X of the complex impedance Z. Note that such an impedance sensing circuit (including complex impedance sensing capability) as presented within this diagram is configured to measure the impedance of the load32that may have any impedance characteristics including entirely real, entirely imaginary, or any combination thereof. Also note that the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3correspond to the complex impedance Z of the load32. Generally speaking, such an impedance sensing circuit as described herein is configured to perform impedance sensing while driving in input reference voltage signal Vref and generating a digital signal that includes information corresponding to the measured load current Imeasured. By appropriately interpreting the digital signal, the load impedance is determined based on Vref/Imeasured. In certain examples, note that the input reference voltage signal Vref is sinusoidal. However, generally speaking, the input reference voltage signal Vref may take any desired form (e.g., a sinusoidal signal, a square wave signal, a triangular wave signal, a multiple level signal (e.g., has varying magnitude over time with respect to the DC component), and/or a polygonal signal (e.g., has a symmetrical or asymmetrical polygonal shape with respect to the DC component). Referring to embodiment3902, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the load32and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the load32while still providing a signal representative of the load current signal Iload. FIGS.40A and40Bare schematic block diagrams showing various embodiments of resistance sensing circuits in accordance with the present invention. Referring to embodiment4001, this diagram also has certain similarities to other embodiments, diagrams, etc. herein including an ADC that is configured to sense current. For example, this diagram includes a capacitor C connected to one of the input terminals of the comparator, the comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1, one or more processing modules24is configured to process the digital signal Do1to generate another digital signal Do2that is provided as an input to an N-bit DAC420, the N-bit DAC420is configured to generate a feedback current signal that is provided to the single line that is connected to and/or coupled to the load32such that the single line connects to the input terminal of the comparator to which the capacitor C is connected. Also, as may be desired in certain applications, a decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. A signal generator is configured to provide an input voltage reference signal Vref to the other input terminal of the comparator. In an example of operation and implementation, two different input voltage reference signals Vref1and Vref2are provided by the signal generator at different respective times. Note that the two different input voltage reference signals. Vref1and Vref2have different voltage levels, magnitudes, etc. For example, a first input voltage reference signal Vref1is provided by the signal generator at a first time, and a second input voltage reference signal Vref2is provided by the signal generator at a second time, such that a difference between the two input voltage reference signals, Vref1and Vref1, is calculated based on Delta Vref=Vref1−Vref2. When the first input voltage reference signal Vref1is set at a first time, a first value of the digital output signal Do3is generated, such as Do3(t1). When the second input voltage reference signal Vref2is set at a second time, a second value of the digital output signal Do3is generated, such as Do3(t2). The difference between these two digital output signals, Do3(t1) and Do3(t2), provides a digital output signal difference that corresponds to the resistance of the load32. For example, Delta Do3=Do3(t1)=Do3(t2). By having the difference between the two input voltage reference signals, Delta Vref=Vref1−Vref2, as well as the difference between the two digital output signals, Delta Do3=Do3(t1)=Do3(t2), which corresponds to the load current, the resistance of the load32may be calculated based on Ohm's law such that V=I×R. for example, the difference between the two input voltage reference signals divided by the difference between two digital output signals, which corresponds to the load current, generates a measurement corresponding to the resistance of the load32. Generally speaking, such a resistance sensing circuit as described herein is configured to perform impedance sensing while driving in input reference voltage signal Vref and generating a digital signal that includes information corresponding to the measured load current Imeasured. By appropriately interpreting the digital signal, the load resistance is determined based on Delta Vref/Delta Imeasured (the difference or Delta being the difference between the measurements made at two different times). In certain examples, note that the input reference voltage signal Vref is sinusoidal. However, generally speaking, the input reference voltage signal Vref may take any desired form (e.g., a sinusoidal signal, a square wave signal, a triangular wave signal, a multiple level signal (e.g., has varying magnitude over time with respect to the DC component), and/or a polygonal signal (e.g., has a symmetrical or asymmetrical polygonal shape with respect to the DC component). Also, note that a resistance sensing circuit is relatively simpler and cheaper to implement than an impedance sensing circuit (e.g., as described above with respect to other embodiments of sensing circuits). Referring to embodiment4002, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the load32and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the load32while still providing a signal representative of the load current signal Iload. FIG.41Ais a schematic block diagram showing an embodiment4101of photodiode equivalent circuit in accordance with the present invention. A photodiode is a circuit that is configured to generate a current that is representative of the level of illumination incident on the photodiode. For example, the photodiode includes a photosensitive region that is configured to receive incident photons, and the photodiode is configured to generate an output current signal that is representative of those incident photons. Photodiodes have a wide variety of applications ranging from precision light meters to high-speed fiber-optic receivers, to ambient light detection, to interior room light detection, to any of a number of various applications. With respect to typical photodiodes, the short-circuit current generated thereby it is typically very linear over a particular range of light intensity. As such, photodiodes are often used to generate a measure of absolute light levels. However, with respect to certain photodiodes, because of them having a large temperature coefficient and being affected by temperature, the diode voltage of a photodiode is often not used as a measure of light intensity. As can be seen in the diagram, the shunt resistance RSH(t) is typically in the range of approximately 1000 mega-Ohms at room temperature. With respect to some photodiodes, note that the shunt resistance RSH(t) may vary significantly across a much broader range, such as between 100 kilo-Ohms at 100 giga-Ohms. A typical characterization of photodiodes is that the shunt resistance RSH(t) decreases by a factor of two for every 10° C. rise in temperature. In addition, the diode capacitance Cj is a function of the Junction area and the diode bias voltage. A typical value of the diode capacitance Cj is approximately 50 pF at a 0 V bias for typical small area diodes. The following table provides some typical values that may be seen with respect to the short-circuit current of the photodiode versus light intensity (e.g., when operating within a photovoltaic mode). IlluminationShort-circuitEnvironment(foot-candle/fc)currentDirect sunlight100030μAOvercast day1003μATwilight10.3μAFull moonlit night0.13000pAClear night/no0.00130pAmoon FIGS.41B and41Care schematic block diagrams showing various embodiments4102and4103, respectively, of photodiode sensor circuits in accordance with the present invention. Referring to embodiment4102, note this diagram also has certain similarities to other embodiments, diagrams, etc. herein (e.g., includingFIG.26A, which includes a load32instead of photodiode as depicted in this diagram) including an ADC that is configured to sense current. For example, this diagram includes a capacitor C connected to one of the input terminals of the comparator, the comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1, one or more processing modules24is configured to process the digital signal Do1to generate another digital signal Do2that is provided as an input to an N-bit DAC420-1, the N-bit DAC420-1is configured to generate a feedback current signal that is provided to the single line that is connected to and/or coupled to the photodiode such that the single line connects to the input terminal of the comparator to which the capacitor C is connected. Also, as may be desired in certain applications, a decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. An input voltage reference signal Vref is provides to the other input terminal of the comparator. Note that such a bipolar PNP BJT transistor provides a logarithmic voltage to current (V2I) conversion within the photodiode sensor circuit of this diagram. In addition, note that the digital output signal Do3includes information that is representative of the logarithmic photodiode current. That is to say, anyone of the digital output signals Do1, Do2, or Do3would be representative of the logarithmic photodiode current. The logarithmic relationship is based on the properties and characteristics of the PNP BJT transistor. Note that an alternative implementations that would replace the PNP BJT transistor with a metal-oxide-semiconductor field-effect transistor (MOSFET) would not exhibit logarithmic characteristics, given the non-logarithmic response of a MOSFET. Referring to embodiment4103, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the photodiode and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the photodiode while still providing a signal representative of the photodiode current. FIGS.42A and42Bare schematic block diagrams showing various embodiments4201and4202, respectively, of charge and/or capacitive change sensing circuits in accordance with the present invention. Referring to embodiment4201, note that the right-hand portion of this diagram is similar toFIG.39A, that includes an impedance sensing circuit. Also, this diagram includes a capacitor C connected to one of the input terminals of the comparator, the comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1, one or more processing modules24is configured to process the digital signal Do1to generate another digital signal Do2that is provided as an input to an N-bit DAC420, the N-bit DAC420is configured to generate a feedback current signal that is provided to the single line that is connected to and/or coupled to the load32such that the single line connects to the input terminal of the comparator to which the capacitor C is connected. Also, as may be desired in certain applications, a decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. A signal generator is configured to provide an input voltage reference signal Vref to the other input terminal of the comparator. In addition, the input voltage reference signal Vref is provided to a quadrature generator. The quadrature generator is configured to generate a pair of quadrature sine and cosine signals based on the input voltage reference signal Vref. The pair of quadrature sine and cosine signals are provided to a demodulator that is configured to receive the digital output signal Do3from the decimation filter and to extract in-phase and quadrature (I and Q) signal components therefrom. The in-phase component I is generated within the demodulator and corresponds to the sine signal output from the quadrature generator multiplied by the digital output signal Do3. The quadrature component Q is generated within the demodulator and corresponds to the cosine signal output from the quadrature generator multiplied by the digital output signal Do3. This diagram also operates similarly with respect toFIG.39Asuch that, by extracting and generating the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3, both any real and any reactance components of the impedance of the load32may be determined. By having both the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3, the total impedance including the complex impedance of the load32may be determined. For example, the sine signal generated by the quadrature generator multiplied by the digital output signal Do3provides the in-phase component of the complex impedance of the load32corresponding to the real part of the complex impedance Z. The cosine signal generated by the quadrature generator multiplied by the digital output signal Do3provides the quadrature component of the complex impedance of the load32corresponding to the reactive/imaginary impedance component X of the complex impedance Z. Note that such charge and/or capacitive change (including complex impedance sensing capability so as to detect charge and/or change of capacitance) as presented within this diagram is configured to measure the impedance of the load32that may have any impedance characteristics including entirely real, entirely imaginary, or any combination thereof. Also note that the in-phase and quadrature (I and Q) signal components based on the digital output signal Do3correspond to the complex impedance Z of the load32. Generally speaking, such an charge and/or capacitive change sensing circuit as described herein is configured to perform impedance sensing while driving in input reference voltage signal Vref and generating a digital signal that includes information corresponding to the measured load current Imeasured. By appropriately interpreting the digital signal, the load impedance (e.g., charge and/or change of capacitance) is determined based on Vref/Imeasured. In certain examples, note that the input reference voltage signal Vref is sinusoidal. However, generally speaking, the input reference voltage signal Vref may take any desired form (e.g., a sinusoidal signal, a square wave signal, a triangular wave signal, a multiple level signal (e.g., has varying magnitude over time with respect to the DC component), and/or a polygonal signal (e.g., has a symmetrical or asymmetrical polygonal shape with respect to the DC component). In addition, considering some differences between this diagram and that ofFIG.39A, on the left-hand side of the diagram, note that a charge amplifier for a capacitive sensor is shown. The equivalent circuit includes a voltage bias Vc in connected to parallel implemented capacitors C1and Delta C, which is the change to C1. Note that the change in charge Delta Q is a function of the change in capacitance Delta C multiplied by the difference between the input voltage reference signal Vref and that the voltage bias Vc. DeltaQ=DeltaC×(Vref−Vc) note that there are wide variety of devices this may operate based on high impedance charge output sensors. For example, high impedance transistors such as PAs electric sensors, hydrophones, and some accelerometers operate based on detecting a transfer of charge. Typical implementations of such charge transducers operate by detecting charge and/or capacitive change. The charge and/or capacitive change sensing circuit operates with much greater precision than any prior art such sensors given the fine resolution and broad range that may be achieved using such an architecture as described herein. The current measurement capabilities of such a charge and/or capacitive change sensing circuit operates far better than prior art sensors that seek to measure such parameters. With respect to the left-hand side of the diagram, note that the change in capacitance Delta C produces a change in charge Delta Q that is a function of the input voltage reference signal Vref and that the voltage bias Vc, as described by the equation above. The charge and/or capacitive change sensing circuit of this diagram is configured to measure the change of capacitance Delta C. Given that the voltage bias Vc and the input voltage reference signal Vref are known, then the change in charge Delta Q can be calculated as described above. Note that measurements taken at two different times (e.g., t1and t2) are performed to determine change of capacitance Delta C. For example, the first capacitance measurement C1is made at a first time t1, and a second capacitance measurement C2is made at a second time t2. The change of capacitance Delta C is the difference between these two capacitance measurements. DeltaC=C1−C2 then, once the change of capacitance Delta C is known, and given that the voltage bias Vc and the input voltage reference signal Vref are known, then the change in charge Delta Q can be calculated as described above. Referring to embodiment4202, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the circuitry on the left-hand side of the diagram (that includes C1and Delta C) and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the photodiode while still providing a signal representative of the current associated with the circuitry on the left-hand side of the diagram (that includes C1and Delta C). FIG.43Ais a schematic block diagram showing an embodiment4301of response of a thermistor that may be implemented within a temperature sensing circuit in accordance with the present invention. Referring to embodiment4301, a thermistor is a temperature sensitive device such that the resistance varies as a function of temperature. Such resistance temperature devices can operate and provide great accuracy when detecting temperature. However, the efficacy of sensing temperature using a thermistor depends greatly upon the accuracy by which the impedance of the resistance temperature device can be measured. For example, using an ADC as described here in that is implemented to detect change in impedance, resistance, and/or any other electrical characteristic of a component, very high accuracy measurement of the resistance of the resistance temperature device may be made thereby providing a highly accurate temperature measurement. Generally speaking, thermistors or low-cost temperature sensitive resistors and are constructed of solid conductor materials that exhibit a positive or negative temperature coefficient, such that the resistance of the device changes as a function of the temperature to which the thermistor is exposed. Generally, thermistors are most commonly implemented having a negative temperature coefficient such that the resistance of the device decreases as a function of increasing temperature. Also, a thermistor is generally a highly nonlinear device such that the resistance of the device does not change when nearly as a function of change in temperature. The right-hand side of the diagram shows the resistance characteristics of a 10 kilo-Ohm negative temperature coefficient thermistor. The diagram shows the thermistor resistance and kilo-Ohms along the vertical axis as a function of temperature in degrees Celsius. Note that different thermistors may have different resistance characteristics as a function of change in temperature, and this is one example of one type of thermistor. The thermistor has a nominal value of approximately 10 kilo-Ohms at 25° C. By having an accurate mapping of the resistance characteristics of the thermistor, then by measuring the resistance of the device, the temperature to which the thermistors expose may be determined (e.g., such as using the graph on the right hand side of the diagram that describes the resistance characteristics of the thermistor). FIGS.43B,43C,43D, and43Eare schematic block diagrams showing various embodiments4302,4303,4304, and4305, respectively, of temperature sensing circuits operative with a thermistor in accordance with the present invention. Referring to embodiment4302, note this diagram also has certain similarities to other embodiments, diagrams, etc. herein including an ADC that is configured to sense current. For example, this diagram includes a capacitor C connected to one of the input terminals of the comparator, the comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1, one or more processing modules24is configured to process the digital signal Do1to generate another digital signal Do2that is provided as an input to an N-bit DAC420, the N-bit DAC420is configured to generate a feedback current signal that is provided to the single line that is connected to and/or coupled to the thermistor such that the single line connects to the input terminal of the comparator to which the capacitor C is connected. Also, as may be desired in certain applications, a decimation filter is configured to process the digital output signal Do2provided from the one or more processing modules24to generate another digital output signal Do3having a lower sample rate and a higher resolution. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. An input voltage reference signal Vref is provides to the other input terminal of the comparator. By having a highly accurate measurement of the current flowing in the thermistor, the impedance of the thermistor may be determined. For example, by detecting the current flowing in the thermistor and by knowing the input voltage reference signal Vref, and by detecting the other voltage going into the other input of the comparator Vin, the resistance of the thermistor may be determined. In addition, any of the other implementations described herein that are operative to In this diagram, compared to certain other embodiments included herein, the load32is replaced with a thermistor. In this diagram, a nonlinear mapping module is configured to process the digital output signal Do3to deal with the non-linear mapping of the resistance characteristics of the thermistor, such as with respect to a graph of a thermistor as shown on the right-hand side of the previous diagram such that the resistance characteristics of the thermistor very non-linearly as a function of temperature. In certain examples, the resistance characteristics of the thermistor as a function of temperature may be stored in a lookup table (LUT), and once the resistance of the thermistor is determined, the corresponding temperature may be looked up within the LUT and determined. Note that such a nonlinear mapping module may be implemented using one or more processing modules, such as the one or more processing modules24as may be desired in certain embodiments. Alternatively, the nonlinear mapping module may be implemented using another one or more processing modules. The nonlinear mapping module is configured to interpret the digital output signal Do3to extract the temperature related information regarding the thermistor and to generate the digital output signal Do4. The nonlinear mopping module is configured to perform the nonlinear conversion, which is similar to a logarithmic converter operation as described herein, to make the temperature reading of the thermistor linear, such that the digital output signal Do4corresponds to a linearized response of resistance of the thermistor as a function of temperature. Referring to embodiment4303, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the thermistor and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the thermistor while still providing a signal representative of the current associated with the thermistor. Referring to embodiment4304, this diagram is similar toFIG.43Bwith at least one difference being that the N-bit DAC420is replaced with a non-linear N-bit DAC1920that is implemented to generate the current that is output to a thermistor that matches or tracks the current of the thermistor. Generally speaking, with respect to such non-linear N-bit DACs, such as the non-linear N-bit DAC1920, the output current provided there from is a non-linear function of the Do2. Therefore, the Do2itself is also an inverse function of the load current, given that the output current from the non-linear N-bit DAC1920is operative to match or track the current of the load (e.g., being equal and opposite of the current of the load thereby minimizing the error signal that is based on the difference between Vref and Vin). In certain examples, using such a non-linear N-bit DAC1920instead of the N-bit DAC420, the nonlinear mapping that is needed to compensate for the nonlinear response of the thermistor is performed by the non-linear N-bit DAC1920itself. As may be needed in certain implementations in which the non-linear N-bit DAC1920does not fully address the nonlinear mapping of the thermistor, subsequent digital signal processing may be performed on the digital signal Do3to generate a linearized response of resistance of the thermistor as a function of temperature. Alternatively, consider an alternative embodiment in which the N-bit DAC420is still implemented instead of the non-linear N-bit DAC1920, such subsequent digital signal processing may perform all needed processing on the digital signal Do3to generate a linearized response of resistance of the thermistor as a function of temperature. Referring to embodiment4305, this diagram is similar to the previous diagram with at least one difference being that a buffer is implemented in-line with respect to the line that connects from one of the inputs of the comparator that connect to the thermistor and that has the capacitor C connected thereto. As described above, such a buffer is implemented to facilitate isolation between the input of the comparator and the thermistor while still providing a signal representative of the current associated with the thermistor. FIGS.44A,44B, and44Care schematic block diagrams showing various embodiments4401,4402, and4403, respectively, of high accuracy resistance sensing circuits operative with a thermistor in accordance with the present invention. Note that alternative prior art means to measure resistance with a high degree of accuracy may be implemented in certain ways such as using a Wheatstone bridge. The Wheatstone bridge has been around for nearly 200 years and is still used as one of the most accurate resistance measurement techniques known in the prior art based on ratio metric measurement that is independent of temperature and voltage tolerance. Referring to embodiment4401, the left-hand side of the diagram shows a typical for resistor Wheatstone bridge, such that four resistors R1R2R3and R4are connected as shown, and when a voltage VB is applied to the junction between resistors R3and R4, and resistors R1and R2are connected at a junction that is grounded, then the voltage VO between a first junction between resistors R1and R4and a second junction between resistors R3and R2is measured. If the values of the four resistors R1R2R3and R4are such that the ratios of the resistances of the resistors R1and R4is the same as the ratios of the resistances of the resistors R3and R4, then the voltage VO is zero. VO=oifR1/R4=R2/R3 However, if the ratios of the resistances of the resistors R1and R4are not the same as the ratios of the resistances of the resistors R3and R4, then the voltage VO is as follows: VO=[(R1)/(R1+R4)]×VB−[(R2)/(R2+R3)]×VB VO=[(R2/R4)−(R2/R3)]/[(1+(R1/R4))×(1+(R2/R3))]×VB Referring also to embodiment4401, the right-hand side of the diagram shows an alternative circuit that is operative to perform high accuracy resistance sensing using only two resistors as opposed to four that are required in a Wheatstone bridge. Note this diagram also has certain similarities to other embodiments, diagrams, etc. herein including an ADC that is configured to sense current. In this diagram, two resistors R1and R2are respectively coupled to the two respective input terminals of the comparator. In addition, capacitor C is connected between the two respective input terminals of the comparator. In alternative implementations, two respective single-ended capacitors, C, are respectively connected to the differential signal lines and to ground instead of the capacitor, C, connected to the differential lead lines (e.g., a first single ended capacitor, C, connected to one of the differential signal lines and to ground, and a second single ended capacitor, C, also connected to the other of the differential signal lines and to ground). The comparator provides a signal to the digital circuit410, the digital circuit410is configured to generate digital signal Do1. An N-bit accumulator3610(shown as N-bit ACC3610and the diagram) is implemented to process the digital output signal from the digital circuit410(or alternative one or more components that generates the digital output signal generated by those one or more components) to generate another digital signal Do1. Similarly, as with respect to other embodiments, diagrams, etc. herein, the comparator and the digital circuit410may be alternatively implemented including using those alternative implementations described with respect toFIG.5A. For example, the N-bit accumulator3610is configured to convert the digital output signal output from the N-bit accumulator3610to a digital output signal Do1having a certain number of bits. In some examples, this operation involves converting a digital output signal that includes one bit every clock signal of the clocking signal that is provided to the digital circuit410to an N-bit signal that includes N-bits every clock signal. In one specific example, this operation involves conversion of a one-bit digital signal to a 7-bit signal or an 8-bit signal. Generally speaking, the N-bit accumulator3610may be configured in various alternative implementations to generate an N-bit signal having any desired number of bits, such that N is a positive integer greater than or equal to 2. Note also that a decimation filter may be implemented to process the digital output digital Do1from the N-bit accumulator3610as well. For example, the decimation filter is configured to process the digital output digital Do1provided from the N-bit accumulator3610to generate another digital output signal Do2having a lower sample rate and a higher resolution. In addition, the digital output digital Do1that is generated by the N-bit accumulator3610is provided to a thermometer decoder3612. The thermometer decoder3612is configured to generate an output symbol that includes a sequence of 0s followed by a sequence of is in most instances, or alternatively all 0s or all Is. For example, with respect to a thermometer code, there cannot be any 0s in between two Is. Generally speaking, with respect to a thermometer code, an input value representing a particular number (e.g., 3=011 binary) generates an output value such that the lowermost bits are all of value 1, and the other uppermost bits are all of value 0. Generally speaking, for an n-bit binary code, the corresponding thermometer code will have output symbols of 2n−1 bits each. As such, as many bits are then needed to represent the thermometer code (n=3, 8 output symbols of 7 bits each of the thermometer code). A differential N-bit DAC1120, wherein N is a positive integer is configured to process the output signal from the thermometer decoder3612to generate two current signals I1and I2that are provided via lines that connect respectively to the resistors R1and R2to keep the two input voltages V at the two terminals of the comparator the same. That is to say, the differential N-bit DAC1120is configured to regulate I1and I2to keep the two input voltages V at the two terminals of the comparator the same. The N-bit DAC420is operative to generate a differential output current signal that is provided based on the output signal from the thermometer decoder3612. The use of a current node ADC as described herein for high accuracy resistance measurement is much improved over that which exists in the prior art. For example, such a high accuracy resistance sensing circuit operates with very low ADC power consumption. Also, high accuracy resistance measurement may be achieved using only two resistor elements as opposed to four resistor elements as implemented within a Wheatstone bridge. This can result in significant reduction in cost and also a reduction in mismatched errors between the respective resistive elements. Having a smaller number of elements is operative to enhance the accuracy of Delta R/R measurements. The mathematical their patient to show ratio metric measurements is provided below. I1+I2=IREFVR1+VR2=IREF⇒V=R1.R2R1+R2IREFI1=R2R1+R2IREFI2=R1R1+R2IREFΔI=I2-I1=IREFR1-R2R1+R2=IREFΔRR1+R2⇒ΔIIREF=ΔRR1+R2 Compare this novel high accuracy resistance sensing circuit to various implementations of a first implementation of Wheatstone bridge in which: R1=R3=R R4=R2=R+ΔR Then, within this high accuracy resistance sensing circuit, such a measurement is alternatively made as follows: ForR1=R&R2=R+ΔR, then ΔIIREF=12ΔRR+ΔR2 As can be seen, such a high accuracy resistance measurement circuit may be implemented using only two resistors as opposed to four that required a Wheatstone bridge. Alternatively, compare this novel high accuracy resistance sensing circuit to various implementations of a second implementation of Wheatstone bridge in which: R4=R1=R R3=R−ΔR&R2=R+ΔR Then, within this high accuracy resistance sensing circuit, such a measurement is alternatively made as follows: ForR1=R−ΔR&R2=R+ΔR, then ΔIIREF=12ΔRR Note that the digital output signal Do2includes information that may be interpreted to determine the change in current ΔI such that the change in resistance ΔR may subsequently be determined. Referring to embodiment4402, this diagram is similar to the previous two diagrams with at least one difference being that this diagram includes two respective buffers implemented in-line via the lines that connect from the output of the differential N-bit DAC1120to the two respective inputs of the comparator. For example, comparing this diagram to the previous diagram, the two respective buffers are implemented to provide isolation between the two respective inputs of the comparator and the differential N-bit DAC1120. Referring to embodiment4403, this diagram is similar to the previous two diagrams showing a conceptual representation of a current node ADC. Consider a current source that provides the current signal: I1+I2=IREF. This current signal is split to provide the two current signals I1and I2that are operative to keep the two input voltages V1and V2at the input terminals of comparator the same. Note that the two respective buffers may also be implemented as desired in certain examples. FIG.45Ais a schematic block diagram showing an embodiment4501of a photo-diode that is operative with an ADC in accordance with the present invention. On the left-hand side of the diagram, a photo-diode is shown as operating to generate a photo-diode current based on incident photons coming into contact with the active portion of the photo-diode. Generally speaking, the photo-diode is a semiconductor device with a P-N junction that is operative to convert incident photons into an electrical current, namely, a photo-diode current. Similar to other types of semiconductor devices, the P layer includes holes, and the N layer includes electrons. Generally speaking, the P layer corresponds to the positive portion of the substrate, and the N layer corresponds to the negative portion of the substrate. Note that photo-diodes may be built based on a number of different types of materials including silicon, gallium arsenide, indium gallium arsenide, germanium, and other materials. Depending on the material used, the particular characteristics of the active region of the photo-diode, its dimensions, etc., the photo-diode will respond to incident photons in a particular way. For example, some photo-diodes are designed to respond to a broad spectrum of visible light, others are more finely tuned to particular wavelengths of the visible spectrum, etc. Generally speaking, diffusion of holes and electrons occurs in response to an based on the incident electrons within the depletion region of the photo-diode, which corresponds to the region between N layer and the P layer within the photo-diode. For example, based on a photon coming into contact with the depletion region, and electrons-hole pair is created. Photons absorbed in the depletion region, or sufficiently close to it, create electron-hole pairs that move to the opposite ends due to the electric field existent within the photo-diode between the anode and cathode. From certain perspectives, the depletion region may be viewed as creating a capacitance within the photo-diode, and the different layers of the substrate of the photo-diode, the P type substrate, and the N type substrate, may be viewed as operating as the parallel plates of a capacitor within the photo-diode. Note that photo-diodes may be implemented in a variety of ways, and sometimes a reverse bias voltage is applied to the photo-diode so as to affect the capacitance of the depletion region. Also, note that a photo-diode may sometimes generate a dark current within the photo-diode even when there is no incident light. For example, a photo-diode current generated within the photo-diode even in the absence of light is referred to as dark current. This dark current can be a source of noise within a photo-diode system. However, note that photo-diodes may be operated without any voltage bias as well. For example, without any added voltage across the depletion region, any dark current within photo-diode will typically be very small or even close to zero thereby reducing the overall noise within the photo-diode system. Note also with respect to the pictorial illustration of a photo-diode, the photo-diode current actually moves in the opposite direction of the diode illustrated within the photo-diode. That is to say, based on incident photons coming in contact with the active portion of the photo-diode, current will flow towards the photo-diode, which is opposite to the direction of the diode illustrated within the photo-diode. Generally speaking, note that photo-diode current may be positive or negative, depending on what particularly is happening with the photo-diode. As a photo-diode is receiving incident photons, it will draw current, but as a photo-diode is not receiving incident photons, and a dark current may be generated within the photo-diode, it will source current. Also, generally speaking, considering incident photons coming into contact with the photo-diode that are time-varying intensity, the overall photo-diode current may have a DC offset and an AC component as well, such that the magnitude of the photo-diode current is varying as a function of time. Considering such an implementation, consider that the photo-diode current undergoes some low pass filtering so as to remove the DC component, the remaining AC component will then include both positive and negative components such that the remaining AC component will have no DC offset and be positive but sometimes a negative at others based on a time-varying light intensity. FIG.45Bis a schematic block diagram showing an embodiment4502of a pixel array of a photo-diode image sensor that is operative with an ADC in accordance with the present invention. In this diagram, a pixel array is composed of a number of photo-diodes. In one implementation, consider that each respective square of the pixel array corresponds to one photo-diode. In another implementation, consider that each respective square of the pixel array includes three photo-diodes (e.g., RGB such as one for red, one for green, and one for blue), so that each respective square of the pixel array is operative to detect red, green, or blue light therein. Regardless of the particular implementation of the pixel array, whether each particular square includes one photo-diode, or multiple photo-diodes, consider an example in which one particular square of the pixel array including a photo-diode, an analog signal provided from the photo-diode, a photo-diode current, is generated based on incident photons on that photo-diode and that analog signal is detected by and analog to digital converter (ADC) that is operative to generate a digital signal that is output to one or more desired recipients, such as a circuit board, a digital signal processor (DSP), another device that is operative to process the digital signal, etc. Note also that the digital control may be provided as input to the pixel array. Based on which particular squares within the pixel array detect incident photons, and consider that respective ADCs are in communication with those respective photo-diodes, at a particular time, the photons that are incident on the respective photo-diodes within the pixel array will correspond to an image detected by the pixel red at that time. Note that such image sensors that include pixel arrays composed of photo-diodes may be implemented in a variety of different ways, and this diagram illustrates the interaction between one particular photo-diode and an ADC that is operative to generate a digital signal based on the photo-diode current, the analog signal, associated with that particular photo-diode. FIG.45Cis a schematic block diagram showing an embodiment4503of passive pixel topology that is operative with a pixel array of a photo-diode image sensor. This diagram shows one possible implementation by which multiple respective photo-diodes are serviced within a passive pixel topology. For example, consider the photo-diodes (PDs) as corresponding to different respective rows within a pixel array, row1, row2, and so on up to row n. Consider the photo-diode the top of the diagram, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) transistor is coupled to the photo-diodes is that the source connects to the photo-diode and the drain is connected to one of the inputs of an operational amplifier. This is similar for the other respective rows that are serviced by this operational amplifier. Another NMOS transistor and integration capacitor in the feedback loop are connected from the input to the output of the operational amplifier. At the other one of the inputs of the operational amplifier, a common mode voltage signal, VCM, is provided. At the gate of the NMOS transistor in the feedback loop of the operational amplifier, a reset signal is provided, phi(row<RST>). Note that the operation of this NMOS transistor serving as a reset switch and the integration capacitor in the feedback loop, CF, introduce noise into the system. As the overall pixel array is read starting with the top photo-diode and continuing down the respective rows of the pixel array to the other photo-diodes of the other rows, the signal provided to the gates of the NMOS transistors, phi, transitions down the respective rows phi(row<1>), to phi(row<2>), and so on to phi(row<n>) until all of the rows are read. Within such an implementation in which one particular operational amplifier is operative to generate an output voltage, VO, that is representative of the occurrence of photons incident on one or more of the photo-diodes, note that such an implementation can inherently include deleterious effects such as crosstalk between the pixels of the pixel array thereby degrading the image producing quality of the pixel array itself. In addition, such as architecture of a passive pixel topology can produce a large green eyes due to the large capacitive loading among all of the photo-diodes serviced by the operational amplifier. FIG.45Dis a schematic block diagram showing an embodiment4504of vertical and horizontal scanners operative with a pixel array of a photo-diode image sensor. This diagram also corresponds to the passive pixel topology shown in the previous diagram such that a vertical scanner and horizontal scanner are implemented respectively to scan the rows and columns of the pixel array. For example, a number of NMOS transistors are implemented so that each respective photo-diode the pixel array may be switched into communication with the vertical scanner or the horizontal scanner, depending on what particular scanner is operational at a particular time. In an example of operation and implementation, consider that vertical scanning is performed before horizontal scanning such that the rows of the pixel array are detected followed by the columns of the pixel array. Based on detection in both the vertical and horizontal directions, one or more processing models in communication with the vertical scanner and the horizontal scanner is configured to generate an image corresponding to the incident photons on the photo-diodes of the pixel array. FIG.45Eis a schematic block diagram showing an embodiment4505of a three transistor pixel structure (3T) that is operative with a pixel of a pixel array of a photo-diode image sensor. This implementation includes three respective NMOS transistors such that a first NMOS transistor includes its source being coupled to the photo-diode and operates as a reset transistor based on the signal, phi(RST), that is provided to the gate of that reset transistor. The reset power supply voltage is provided to the drain of the reset transistor. In addition, the gate of a source-follower transistor is also connected to the photo-diode, and the drain of this source-follower transistor is connected to a power supply (e.g., VDD). The gate of a row select NMOS transistor is connected to a row select signal, phi(row), the drain of the row select NMOS transistor is connected to the source of the source-follower transistor, and the source of the row select NMOS transistor provides a voltage corresponding to the pixel associated with the photo-diode. The source of the row select NMOS transistor is also connected to a current supply providing a bias current, IBIAS. As can be seen with respect to this diagram in comparison to the passive pixel topology ofFIG.45C, this diagram of the 3T pixel structure includes three transistors as opposed to two transistors. This implementation has a larger fill factor, and this implementation can unfortunately generate noise caused by the reset transistor. FIG.45Fis a schematic block diagram showing an embodiment4506of a four transistor pixel structure (4T) that is operative with a pixel of a pixel array of a photo-diode image sensor. This implementation may be viewed as an extension of the implementation of the previous diagram. As can be seen, within such a 4T pixel structure, an additional transfer transistor is implemented between the photo-diode and the reset transistor that is connected to the photo-diode. This additional transfer transistor is operative to prevent any dark current from flowing to the gates of the source-follower transistor. The inclusion of the additional transfer transistor affects the performance of the 4T pixel structure to operate more as a pinned photo-diode including a drastic reduction in dark current compared to the 3T pixel structure. In addition, a small integration capacitor is implemented on the floating diffusion (FD) node, shown as CFDin the diagram. This small integration capacitor operates to increase the value of the conversion gain of the 4T pixel structure. This implementation within this diagram does have improved performance over the prior diagram, with better noise performance, larger conversion gain, and smaller dark current. However, as can be seen, this implementation does include four transistors as opposed to three transistors of the previous diagram (or two transistors of a further previous diagram,FIG.45C). FIG.45Gis a schematic block diagram showing an embodiment4507of a capacitive transimpedance amplifier including an inverter structure that is operative with a pixel of pixel array of a photo-diode image sensor. FIG.45His a schematic block diagram showing an embodiment4508of a capacitive transimpedance amplifier including a differential amplifier structure that is operative with a pixel of pixel array of a photo-diode image sensor. The two diagrams show two alternative implementations of a capacitive trans-impedance amplifier pixel and are similar to the passive pixel technology described above, such as with respect toFIG.45C. Within each of these diagrams, note that a capacitor is shown as being representative of parasitic capacitance of the photo-diode, CPD. Referring to embodiment4507ofFIG.49G, this diagram is similar to the implementation shall in withinFIG.45C, with the addition of the capacitor, CPD, and the operational amplifier being replaced with an inverter, and the overall structure servicing a single photo-diodes in this diagram. The output of the inverter is an output voltage, VPIX, that is representative of the occurrence of photons incident on the photo-diode. Referring to embodiment4508ofFIG.49H, this diagram is similar to the implementation shall in withinFIG.45C, with the addition of the capacitor, CPD, and the overall structure servicing a single photo-diodes in this diagram. FIG.45Iis a schematic block diagram showing an embodiment4509of a digital pixel structure that is operative with a pixel of pixel array of a photo-diode image sensor. In this diagram, an ADC and memory, shown as static random access memory, SRAM, replaced the source-follower transistor, the row select transistor, and current source of the 4T pixel structure ofFIG.45F. This implementation is operative to provide much faster speed within an image sensor such that an ADC is employed inside the pixel, however, while this does provide an improvement over other implementations including the 4T pixel structure of FIG.45F, there are still multiple components that may be sources of noise, crosstalk, interference, and may adversely affect the overall performance of the device. FIG.45Jis a schematic block diagram showing an embodiment4510of a chain block diagram of a photo-diode image sensor. This diagram provides a pictorial illustration of the respective stages within a chain block diagram of a photo-diode image sensor. For example, many of the respective stages are shown within the various implementations of the previous diagrams. A photo detection stage includes the photo-diode, a charge to voltage (Q to V) conversion stage follows the photo detection stage, a source-follower stage follows the charge to voltage conversion stage, an amplifier stage follows the source-follower stage, and an ADC stage follows the amplifier stage. As can be seen, such a pixel structure that is operative to service a photo-diode within an image sensing device, such as a pixel array, can include a number of stages, and each respective stage made unfortunately be a source of noise, interference, crosstalk, etc. thereby adversely affecting the overall performance of the device. For example, consider these respective stages is corresponding to and implementation of the 4T pixel structure of theFIG.45F, then each respective stage and the components associated therewith may each unfortunately be a contributor to a reduction in the overall performance of the device. In an ideal and perfect situation, the transfer function between the photons incident on the photo-diode in the final output of the ADC stage would be linear. Unfortunately, these respective stages that are implemented in between the photo detection stage and the ADC stage introduce nonlinearity into the overall transfer function and also introduce noise and other deleterious effects. FIG.45Kis a schematic block diagram showing an embodiment4511of a chain block diagram of a photo-diode image sensor in accordance with the present invention. This diagram shows an ADC stage directly connected to our coupling to the photo detection stage. By taking the ADC stage all the way back to the photo detection stage within the device, there is a significant reduction if not the elimination of all of the noise and nonlinearity generated by the respective stages of the chain between the photo detection stage and the ADC stage of the previous diagram. As described herein with respect to various aspects, embodiments, and/or examples of the invention (and/or their equivalents), an ADC may be constructed that operates based on very low power, introduces very little noise, provides linearity in response, and can operate based on converting a detected current and generating a corresponding digital signal therefrom. For example, consider the current signal generated by a photo-diode, the photo-diode current, that is the current that is detected by an ADC that is operative to detect a current signal and to generate a corresponding digital signal therefrom. FIG.46Ais a schematic block diagram showing an embodiment4601of an ADC implemented based on a single-ended direct interface dual DAC feedback photo-diode sensor in accordance with the present invention. This diagram has certain similarities to other ADCs described. Certain differences include the ADC use particularly connected to or coupled to a photo-diode. A charging capacitor, C, is connected to the single line that connects the ADC to the photo-diode, and the single line that connects the ADC to the photo-diode is coupled to a self-referenced latched comparator. The self-referenced latched comparator is operatively coupled and configured simultaneously to provide the load signal412and to detect any effect414on the load signal corresponding to the photo-diode current signal that is operative to charge the charging capacitor, C, thereby generating a photo-diode voltage. The photo-diode voltage is received at an input of the self-referenced latched comparator. The self-referenced latched comparator is operative to generate a digital output signal, Do0, based the photo-diode voltage. This digital output signal, Do0, is provided to a first one or more processing modules24and also to a second one more processing modules24. Note that these respective one or more processing modules24are configured to perform any desired digital signal processing. Examples of such digital signal processing may include functions corresponding to low pass filtering (LPF), accumulating (ACC) such as the operation described with respect to an N-bit accumulator and other diagrams herein, all pass filtering (APF), etc. The first one or more processing modules24is configured to provide another digital input signal to an N-bit DAC420-2that is implemented to operate as a current source to the single line connecting the ADC to the photo-diode, and the second one or more processing modules24is configured to provide yet another digital input signal to an M-bit DAC420-3that is implemented to operate as a current sink to the single line connecting the ADC to the photo-diode. Note that N and M are both positive integers greater than or equal to 1. In some implementations, note that M is equal to N. In other implementations, N is greater than M. In certain examples, the amount of current that is sourced by the N-bit DAC420-2is more than the amount of current that is sunk by the M-bit DAC420-3. In other examples, the amount of current that is sourced by the N-bit DAC420-2is less than the amount of current that is sunk by the M-bit DAC420-3. Consider an example where the amount of current that is sourced by the N-bit DAC420-2is more than the amount of current that is sunk by the M-bit DAC420-3, then N being greater than M operates to provide more source current than sink current. In In certain examples, note that the N-bit DAC420-2will be a higher power consuming component then the M-bit DAC420-3. In an example of operation and implementation, the M-bit DAC420-3is implemented to provide a sync current to ensure that the voltage at the input of the self-referenced latched comparator is the same as the threshold voltage associated with the self-referenced latched comparator. Generally speaking, note that the combination of both the N-bit DAC420-2and the M-bit DAC420-3allow for sourcing and/or sinking current to track the photo-diode current. In this diagram, note that the self-referenced latched comparator does not receive a separate reference signal has certain comparators and/or operational amplifiers and other diagrams do. This is a further reduction in complexity compared to other architectures. By using a self-referenced match comparator, the comparison of the photo-diode voltage is too a threshold voltage associated with the self-referenced latched comparator in accordance with generating the digital output signal, Do0. For example, the self-referencing of the self-referenced latched comparator is based on a threshold voltage associated with the self-referenced latched comparator. Note that the threshold voltage of the self-referenced latch comparator may be of a variety of types, including 0.3 V, 0.5 V, 0.7 V, 1 V, greater than 1 V, or some other value. In an example of operation and implementation, based on the photo-diode voltage that is received by the self-referenced latched comparator comparing favorably to the threshold voltage of the self-referenced latched comparator, the self-referenced latched comparator outputs a first digital value. Based on the photo-diode voltage that is received by the self-referenced latched comparator comparing unfavorably to the threshold voltage of the self-referenced latched comparator, the self-referenced latched comparator outputs a second digital value. For example, consider that the photo-diode voltage is greater than the threshold voltage of the self-referenced latched comparator, then the self-referenced latched comparator outputs the first digital value (e.g., digital value of 1). Alternatively, consider that the photo-diode voltage is less than or equal than the threshold voltage of the self-referenced latched comparator, then the self-referenced latched comparator outputs the second digital value (e.g., digital value of 0). As the photo-diode voltage varies as a function of time, digital output signal, Do0, output from the self-referenced latched comparator will include a stream of digital values composed of the first digital value in the second digital value, based on comparison of the photo-diode voltage to the threshold voltage of the self-referenced latched comparator. Also, note that the first one or more processing modules24and the second one or more processing modules24is also operative to provide the digital signals that are provided respectively to the N-bit DAC420-2and the M-bit DAC420-3also to a first decimation filter and the second decimation filter that are operative to generate digital output signals, Do1and Do2, respectively. That is to say, the very same digital signals that are generated by the first one or more processing modules24and the second one or more processing modules24based on processing of the digital output signal, Do0, are provided respectively to the first decimation filter and the second decimation filter. In certain examples, a decimation filter is configured to process a first digital signal to generate a second digital signal having a lower sample rate and a higher resolution than the first digital signal. In another example, the first one or more processing modules24that is configured to process the digital output signal, Do0, to generate the digital signal is provided to the N-bit DAC420-2is also configured to process the digital output signal, Do0, to generate another the digital output signal, Do0′, to be provided to the first decimation filter. The second one or more processing modules24that is configured to process the digital output signal, Do0, to generate the digital signal is provided to the N-bit DAC420-2is also configured to process the digital output signal, Do0, to generate another the digital output signal, Do0″, to be provided to the second decimation filter. For example, note that the first and second one or more processing modules are configured to provide the very same digital signals that they respectively provide to the N-bit DAC420-2and the M-bit DAC420-3to the first and second decimation filters, or alternatively, respectively provide different digital signals to the first and second decimation filters. In a particular implementation of the self-referenced latched comparator, the self-referenced latched comparator includes a first inverter, a second inverter, and a digital circuit. The first inverter is operably coupled to the photo-diode and the charging capacitor, C, and is configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator. In certain examples, this threshold voltage associated with the self-referenced latched comparator corresponds to a threshold voltage of this first inverter. A second inverter is operably coupled to the first inverter, and the digital circuit410-1is operably coupled to the second converter and is configured to output the digital output signal, Do0. The digital circuit410-1may be viewed as that component that is operative to perform the data latch thereby generating the appropriate first or second digital value (e.g., 1 or 0) of the signal is output from the second inverter thereby generating the digital output signal, Do0, at some desired clock frequency. Note that the complexity of any inverter is much less than that of a comparator or an operational amplifier. In addition, note that the use of inverters within a cell-referenced latched comparator provides for a very small size with very low power consumption. Note that such an ADC as described with respect to this diagram is operative to consume very low power. For example, consider a particular implementation in which the photo-diode is detecting very strong light, and the photo-diode is generating a photo-diode current in the range of 10s of microamps, and consider a power supply of the ADC to be in the range of 2 V. Within such an implementation, the overall power consumption of the ADC will be in the range of a couple microwatts. In some implementations, note that the majority of power consumption will be within the N-bit DAC420-2, such as where a larger source current is provided in comparison to the sink current to ensure tracking of the photo-diode current that is operative to charge the charging capacitor, C, and to generate the photo-diode voltage that is received at the input of the self-referenced latched comparator. Given such an extremely low level of power consumption of such an ADC that is operative to service a photo-diode, an extremely large number of photo-diodes can be serviced while still providing very small size, low power consumption, low noise, etc. Such an ADC provides a significant improvement over existing technologies that are directed towards servicing one or more photo-diodes. Note that some alternative implementations may include one ADC as described herein that is operative to service more than one photo-diode, such as with respect to an appropriate switching, multiplexing, or other time-division implementation such that the ADC services different perspective photo-diodes at different perspective times. In other implementations, note that one respective ADC is implemented to service each respective photo-diode. FIG.46Bis a schematic block diagram showing an embodiment4602of a self-referenced latched comparator that is operative with an ADC in accordance with the present invention. This diagram shows one particular implementation of a self-referenced latched comparator. In this implementation, the first two inverters of the self-referenced latched comparator are similarly implemented, but a third inverter including an input that is operatively coupled to an output of the second inverter and an output operably coupled to a node coupling an output of the first inverter to an input of the second inverter via switch facilitates operation of the self-referenced latched comparator in accordance with the sampling mode and a latched mode. For example, consider that a power supply, VDD, is connected to the first inverter via a switch, and the first inverter is also connected to ground via switch. Depending on the configuration of these switches, the operational mode of the self-referenced latched comparator may be performed in accordance with the sampling mode or the latched mode. For example, during a first configuration, corresponding to the switches phi_1, associated with the first inverter being closed, then the first inverter turns on, and the switch, phi_2, is open thereby turning off the third inverter so that the self-referenced latched comparator operates in accordance with a sampling mode. Alternatively, during a second configuration, corresponding to the switches phi_1, associated with the first inverter being open, then the first inverter turns off, and the switch, phi_2, is closed thereby turning on the third inverter so that the self-referenced latched comparator operates in accordance with a latched mode. Note that this is one particular implementation by which the self-referenced latched comparator may be done to facilitate operation of the ADC ofFIG.46A. Generally speaking, any implementation of a self-referenced latched comparator that is operative to compare the photo-diode voltage to a threshold voltage associated with the self-referenced latched comparator so as to generate a digital signal that is based on a difference between the photo-diode voltage and the threshold voltage associated with the self-referenced latched comparator is operative to facilitate operation of the ADC without the requirement of any reference signal to be provided to assist in the generation of the digital output signal, Do0. Such an architecture provides a reduction in complexity while providing high precision, low noise, high performance, and high accuracy with respect to detection of the photo-diode current that is associated with the photo-diode. In addition, note that such an ADC, being directly connected or coupled to the photo-diode also provides a significant reduction if not the elimination of all of the noise and nonlinearity generated by any intermediate respective stages between the photo detection stage and the ADC stage of previous diagrams as described herein. By completely obviating the requirement for any such intermediate respective stages, a significant improvement in performance is achieved in comparison to other designs. Such a ADC design that is operative to service a photo-diode provides very low noise. When implemented in an image sensor based application, this reduction in noise will provide for a much improved image quality. In addition, the overall device consumes much less power than prior technologies as the analog circuitry included within such an ADC design that is operative to service a photo-diode is minimized. Consider adding image sensing application, such an ADC design that is operative to service a photo-diode may be implemented to provide for a very high-speed image sensor with as many as one ADC per pixel within a pixel array of the image sensor. Again, the very small size, low noise, and low power consumption of such an ADC design that is operative to service a photo-diode makes it well tailored for image sensing applications. In an example of operation and implementation, an ADC includes a capacitor, a self-referenced latched comparator, one or more processing modules, an N-bit DAC, and an M-bit DAC. In some examples, the ADC includes memory that stores operational instructions such that the one or more processing modules is configured to execute the operational instructions. The capacitor is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The ADC is coupled to the photo-diode via a single line. The self-referenced latched comparator is operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. The one or more processing modules is operably coupled to the self-referenced latched comparator and configured to execute the operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. The N-bit DAC is operably coupled to the one or more processing modules and configured to generate the DAC source current based on the second digital signal (e.g., N is a first positive integer. The M-bit DAC is operably coupled to the one or more processing modules and configured to generate the DAC sink current based on the third digital signal (e.g., M is a second positive integer). Note that the DAC source current and/or the DAC sink current tracks the photo-diode current. In some examples, a first one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the N-bit DAC and is configured to execute first operational instructions to process the first digital signal to generate the second digital signal and to provide the second digital signal to the N-bit DAC, and a second one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the M-bit DAC and is configured to execute second operational instructions to process the first digital signal to generate the third digital signal and to provide the second digital signal to the M-bit DAC. In another of operation and implementation, a first one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the N-bit DAC and is configured to execute first operational instructions to process the first digital signal to generate a fourth digital signal, and a second one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the M-bit DAC and is configured to execute second operational instructions to process the first digital signal to generate a fifth digital signal. In yet another specific example, a first decimation filter is operably coupled to the first one or more processing modules and configured to process the fourth digital signal to generate a first digital output signal having a lower sampling rate and a higher resolution than the fourth digital signal. A second decimation filter is operably coupled to the second one or more processing modules and configured to process the fifth digital signal to generate a second digital output signal having a lower sampling rate and a higher resolution than the fifth digital signal. In another example, a first one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the N-bit DAC and is configured to execute first operational instructions to process the first digital signal to generate the second digital signal and to provide the second digital signal to the N-bit DAC and to a first decimation filter. A second one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the M-bit DAC and s configured to execute second operational instructions to process the first digital signal to generate the third digital signal and to provide the second digital signal to the M-bit DAC and to a second decimation filter. Note that the first decimation filter is operably coupled to the first one or more processing modules and is configured to process the first digital signal to generate a first digital output signal having a lower sampling rate and a higher resolution than the first digital signal, and the second decimation filter is operably coupled to the second one or more processing modules and is configured to process the second digital signal to generate a second digital output signal having a lower sampling rate and a higher resolution than the second digital signal. In some examples, the self-referenced latched comparator is implemented to include a first inverter operably coupled to the photo-diode and the capacitor and configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator that corresponds to a threshold voltage of the first inverter, a second inverter operably coupled to the first inverter, and a digital circuit operably coupled to the second inverter and configured to output the first digital signal. In some other examples, the self-referenced latched comparator is implemented to include a first inverter operably coupled to the photo-diode and the capacitor and configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator that corresponds to a threshold voltage of the first inverter, a second inverter operably coupled to the first inverter, a third inverter including an input operably coupled to an output of the second inverter and an output operably coupled to a node coupling an output of the first inverter to an input of the second inverter via a switch to facilitate operation of the self-referenced latched comparator in accordance with a sampling mode and a latched mode, and a digital circuit operably coupled to the second inverter and configured to output the first digital signal. In certain implementations, the N-bit DAC is a higher power consuming component than the M-bit DAC (e.g., N is greater than M), and the DAC source current is larger than the DAC sink current. In other implementations, N is equal to M. Alternatively, N is than less than or equal M. In an example of operation and implementation, the N-bit DAC is further configured to generate and provide the DAC source current based on the photo-diode voltage comparing favorably to the threshold voltage associated with the self-referenced latched comparator (e.g., N is a first positive integer), and an M-bit DAC is further configured to generate and provide the DAC sink current based on the photo-diode voltage comparing unfavorably to the threshold voltage associated with the self-referenced latched comparator, wherein the DAC source current and/or the DAC sink current tracks the photo-diode current. For example, the photo-diode voltage compares favorably to the threshold voltage associated with the self-referenced latched comparator based on the photo-diode voltage being greater than the threshold voltage associated with the self-referenced latched comparator, and the photo-diode voltage compares unfavorably to the threshold voltage associated with the self-referenced latched comparator based on the photo-diode voltage being less than the threshold voltage associated with the self-referenced latched comparator. In even other examples, the ADC also includes a decimation filter operably coupled to the one or more processing modules and configured to process the first digital signal to generate a digital output signal having a lower sampling rate and a higher resolution than the first digital signal. In yet other examples, the ADC also includes a decimation filter operably coupled to the one or more processing modules and configured to process the second digital signal to generate a digital output signal having a lower sampling rate and a higher resolution than the second digital signal. In another example of operation and implementation, an ADC includes an ADC includes a capacitor, a self-referenced latched comparator, one or more processing modules, an N-bit DAC, an M-bit DAC, and a decimation filter. In some examples, the ADC includes memory that stores operational instructions such that the one or more processing modules is configured to execute the operational instructions. The capacitor is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The ADC is coupled to the photo-diode via a single line. The self-referenced latched comparator is operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. The one or more processing modules is configured to execute the operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. The N-bit DAC is operably coupled to the one or more processing modules and is configured to generate and provide the DAC source current based on the second digital signal and also based on the photo-diode voltage comparing favorably to the threshold voltage associated with the self-referenced latched comparator (e.g., N is a first positive integer). The M-bit DAC is operably coupled to the one or more processing modules and is configured to generate and provide the DAC sink current based on the third digital signal based on the second digital signal and also based on the photo-diode voltage comparing unfavorably to the threshold voltage associated with the self-referenced latched comparator. The DAC source current and/or the DAC sink current tracks the photo-diode current (e.g., M is a second positive integer). Also, the decimation filter operably coupled to the one or more processing modules and configured to process the second digital signal to generate a first digital output signal having a lower sampling rate and a higher resolution than the second digital signal or to process the third digital signal to generate a second digital output signal having a lower sampling rate and a higher resolution than the third digital signal. In some examples, the photo-diode voltage compares favorably to the threshold voltage associated with the self-referenced latched comparator based on the photo-diode voltage being greater than the threshold voltage associated with the self-referenced latched comparator, and the photo-diode voltage compares unfavorably to the threshold voltage associated with the self-referenced latched comparator based on the photo-diode voltage being less than the threshold voltage associated with the self-referenced latched comparator. Also, in certain examples, a first one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator, and the N-bit DAC and is configured to execute first operational instructions to process the first digital signal to generate the second digital signal and to provide the second digital signal to the N-bit DAC. A second one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator, and the M-bit DAC and is configured to execute second operational instructions to process the first digital signal to generate the third digital signal and to provide the second digital signal to the M-bit DAC. In some implementations, a first one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator, and the N-bit DAC and configured to execute first operational instructions to process the first digital signal to generate a fourth digital signal. A second one or more processing modules of the one or more processing modules is operably coupled to the self-referenced latched comparator and the M-bit DAC and is configured to execute second operational instructions to process the first digital signal to generate a fifth digital signal. In some examples, a first decimation filter is operably coupled to the first one or more processing modules and is configured to process the fourth digital signal to generate a first digital output signal having a lower sampling rate and a higher resolution than the fourth digital signal, and a second decimation filter is operably coupled to the second one or more processing modules and is configured to process the fifth digital signal to generate a second digital output signal having a lower sampling rate and a higher resolution than the fifth digital signal. Also, in some specific implementations, the self-referenced latched comparator is implemented to include a first inverter operably coupled to the photo-diode and the capacitor and configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator that corresponds to a threshold voltage of the first inverter, a second inverter operably coupled to the first inverter, and a digital circuit operably coupled to the second inverter and configured to output the first digital signal. Also, in certain implementations, the N-bit DAC is a higher power consuming component than the M-bit DAC (e.g., N is greater than M), and the DAC source current is larger than the DAC sink current. In other implementations, N is equal to M. Alternatively, N is than less than or equal M. FIG.47is a schematic block diagram showing an embodiment4700of an ADC implemented based on a single-ended direct interface DAC feedback and current sink photo-diode sensor in accordance with the present invention. This diagram has some similarities to the previous diagram with at least a few differences being that the M-bit DAC420-3is replaced by a current sink device, I2, towards the bottom of the diagram that is controlled by the digital output signal, Do0, and an N-bit accumulator (ACC)3610is implemented to process the digital output signal, Do0, to generate the digital signal is provided to the N-bit DAC420-2. In this diagram, the current sink provides a path to sink current when there is no photo-diode current. In this diagram, the self-referenced latched comparator outputs the digital signal, Do0, that is provided to the N-bit ACC3610and also to the switch that is connected between the current sink and the input of the self-referenced latched comparator. In certain examples, the N-bit ACC3610is configured to provide the same digital signal to a decimation filter that it provides to the N-bit DAC420-2, and the decimation filter is configured to output digital output signal, Do1. In other examples, the ACC3610is configured to process the digital output signal, Do0, that is output from the self-referenced latched comparator to generate another digital output signal, Do0′, that is provided to the decimation filter, and the decimation filter is configured to process this another digital output signal, Do0′, to generate digital output signal, Do1. This diagram shows even a further simplification of the ADC of the previous diagrams,FIGS.46A and46B. By using the N-bit ACC3610, a very small sink current may be used at the bottom of the diagram, and the sink current is operative to sink some current even when there is no photo-diode current, so as to maintain the voltage at the input of the self-referenced latched comparator to be same as a threshold voltage associated with the self-referenced latched comparator. Note that the self-referenced latched comparator of this diagram may be similarly modified in accordance withFIG.46Bas described above. In addition, this diagram includes further simplification by replacing the one or more processing modules24with the N-bit ACC3610. FIG.48is a schematic block diagram showing an embodiment4800of an ADC implemented based on a single-ended direct interface DAC feedback and current sink with improved settling time photo-diode sensor in accordance with the present invention. This diagram includes similarity to the previous diagram with at least one difference being that the current sink at the bottom of the diagram includes a modified configuration that is operative to compensate for the switching time of the previous diagram when this switch connected between the current sink and the input to the self-referenced latched comparator is closed so that the current sink is turned on. For example, within an actual physical system, it does take some finite amount of time for the current to change from zero to some DC current value (e.g., not instantaneous). The current sink to the bottom of the diagram still is operative to provide a path to sink current when there is no photo-diode current. However, by providing an alternative path, such that the current sink is connected to a power supply (e.g., VDD) when the switch between the current sink in the input to the self-reference latched comparator is open, and improved settling time is achieved when the current sink actually does get switched into the input of the self-referenced latched comparator when that switch is closed. By including two switches connected to the current sink at the bottom of the diagram, one switch connected between the current sink and the input to the self-referenced latched comparator, and another switch connected to a power supply (e.g., VDD), such that the two switches are oppositely controlled such that when one is open, the others closed, and vice versa. To compensate for the settling time of the turn on or turn off of the current sink, this implementation includes and means by which current can be pulled immediately such that the current never goes to zero. For example, depending on the connectivity of the switches, the current can be steered to the power supply (e.g., VDD) or alternatively to the input of the self-referenced latched comparator. FIGS.49A and49Bare schematic block diagrams showing various embodiments (embodiment4901ofFIG.49Aand embodiment4902ofFIG.49B) of an ADC implemented based on a single-ended direct interface dual DAC feedback differential signaling photo-diode sensor in accordance with the present invention. Referring to embodiment4901ofFIG.49A, this diagram has some similarities to the ADC ofFIG.46Awith certain differences being that this ADC provides for a differential implementation. In this diagram, the self-referenced latched comparator is replaced with a comparator that is connected or coupled to a digital circuit410that is operated based on an oversampling clock and the N-bit DAC420-2and the M-bit DAC420-3are replaced by differential N-bit DAC1120and differential M-bit DAC4910, respectively. Also, an additional/second charging capacitor, C, is connected to one of the differential inputs of the differential N-bit DAC1120. Note that only one of the differential leads of the ADC, corresponding to the two respective inputs to the comparator, is connected to the photo-diode. In this implementations, the comparator compares two inputs. One of the inputs to the comparator corresponds to a photo-diode voltage that is generated via first ones of the differential leads of the differential N-bit DAC1120and differential M-bit DAC4910(e.g., a first differential lead of the differential leads of the differential N-bit DAC1120and a first differential lead of the differential M-bit DAC4910) that is connected to the first charging capacitor, C, that is also connected to the photo-diode. The other input to the comparator corresponds to the second ones of the differential leads of the differential N-bit DAC1120and differential M-bit DAC4910(e.g., a second differential lead of the differential leads of the differential N-bit DAC1120and a second differential lead of the differential M-bit DAC4910) that is connected to the second charging capacitor, C). Referring to embodiment4901ofFIG.49B, this diagram as similar to the previous diagram with at least one difference being that the comparator and the digital circuit410is replaced with a digital comparator that is operated based on an oversampling clock. FIGS.50A and50Bare schematic block diagrams showing various embodiments (embodiment5001ofFIG.50Aand embodiment5002ofFIG.50B) of an ADC implemented based on a single-ended direct interface DAC feedback and current sink differential signaling photo-diode sensor in accordance with the present invention. Referring to embodiment5001ofFIG.50A, this diagram is similar to the diagram ofFIG.49Awith the replacement of the one or more processing modules with an N-bit ACC3610that is operative to generate the digital signal that is provided to the differential N-bit DAC1120. In addition, the differential M-bit DAC4910is replaced with a current sink that is connected via two respective leads via two respective switches to the two respective inputs of the comparator. Again, note that one of the respective inputs of the comparator is connected to the charging capacitor, C, and the photo-diode and is configured to receive the photo-diode voltage. Note that the digital output signal, Do0, that is generated by the digital circuit410is operative to control the two respective switches that are connected between the current sink and the two respective inputs of the comparator. In an example of operation and implementation, when one of the switches is closed, the other is open, and vice versa. In certain examples, the same digital signal that is provided from the N-bit ACC3610to the differential N-bit DAC1120is provided to a decimation filter. Alternatively, a first digital signal is provided from the N-bit ACC3610to the differential N-bit DAC1120, and a second digital signals is provided from the N-bit ACC3610to the decimation filter. This diagram provides a simplification of the diagram ofFIG.49Awith the replacement of the one or more processing modules with the N-bit ACC3610. Referring to embodiment5002ofFIG.50B, this diagram as similar to the previous diagram with at least one difference being that the comparator and the digital circuit410is replaced with a digital comparator that is operated based on an oversampling clock. FIGS.51A,51B,51C, and51Dare schematic block diagrams showing various embodiments (embodiment5101ofFIG.51A, embodiment5102ofFIG.51B, embodiment5103ofFIG.51C, embodiment5104ofFIG.51D) of an ADC implemented based on a single-ended direct interface DAC feedback and current sink with chopper differential signaling photo-diode sensor in accordance with the present invention. Referring to embodiment5101ofFIG.51A, this diagram is similar to the diagram ofFIG.50Awith the replacement of the current sink at the bottom of the diagram with two respective current sinks, I2, that provide for differential current sinking corresponding to the two respective differential lines that are input to the comparator, such that one of the differential lines is connected to the charging capacitor, C, and photo-diode. However, using such an implementation may present problems when there are mismatches between the two current sinks. For example, variation or mismatch between current sinks may be as much as 1-2%.FIG.51Cprovides an alternative implementation to mitigate or reduce entirely any adverse effects of such mismatches. Referring to embodiment5102ofFIG.51B, this diagram as similar to the previous diagram with at least one difference being that the comparator and the digital circuit410is replaced with a digital comparator that is operated based on an oversampling clock. Referring to embodiment5103ofFIG.51C, as mentioned above, this diagram is similar to the diagram ofFIG.51Awith at least one difference being that the two current sinks, I2, that provide for differential current sinking corresponding to the two respective lines that are input to the comparator, such that one of the differential lines is connected to the charging capacitor, C, and photo-diode, are replaced instead with two respective current sinks, I2and I3, that each are connected using a pair of switches to the two respective differential leads of the respective inputs of the comparator such that one of the differential leads is connected to the charging capacitor, C, and the photo-diode and is configured to receive the photo-diode voltage. Specifically, one of the current sinks, I2, is connected via two switches to the two respective inputs of the comparator, and the other of the one of the current sinks, I3, is also connected via two switches to the two respective inputs of the comparator. For each of these respective switches that are connected to the two respective current sinks, I2and I3, when one of the switches is closed, the other is open, and vice versa. Considering the current sink, I2, when the switch on the left that is connected to the charging capacitor, C, and the photo-diode and is configured to receive the photo-diode voltage is closes, then the other switch is open, and vice versa. Similarly, considering the current sink, I3, when the switch on the left that is connected to the charging capacitor, C, and the photo-diode and is configured to receive the photo-diode voltage is closed, then the other switch is open, and vice versa. In an example of operation and implementation, the operation of these with two respective current sinks, I2and I3, and their connectivity to the two respective lines that are input to the comparator, such that one of the differential lines is connected to the charging capacitor, C, and photo-diode, operates as a chopper to remove any offset current and flicker noise that may be existent within the photo-diode current. Note that the switches may be operated a clock that is slower than the oversampling clock that is used for the digital circuit410. Together, these two respective current sinks, I2and I3, and their switches operate to get rid of any offset between the two respective current sinks, I2and I3. In an example of operation and implementation, by operating the switches, such as using a clock that is even slower than the oversampling clock that is used for the digital circuit410, any DC offset current between the two respective current sinks, I2and I3, is converted to an AC current. Then after performing very simple low pass filtering (LPF), then the only remaining component is a DC component. Generally speaking, this may be viewed as averaging out a low frequency offset by introducing a high-frequency AC offset that is a function of the clock frequency. Then, this DC offset is converted to an AC offset, and very simple low pass filtering (LPF) may be used to filter out the AC offset completely. In some examples, that such low pass filtering (LPF) may be performed in accordance with the conversion of the analog signal to the digital output signal, Do0, within the digital circuit410, within the N-bit ACC3610, within the decimation filter, and/or within one or more other processing modules that are implemented to perform such low pass filtering (LPF). Such low pass filtering (LPF) may be performed in the analog domain and/or the digital domain. In other examples, one or more analog LPFs for implemented between the two respective current sinks, I2and I3, and the two respective inputs to the comparator. Referring to embodiment5104ofFIG.51D, this diagram as similar to the previous diagram with at least one difference being that the comparator and the digital circuit410is replaced with a digital comparator that is operated based on an oversampling clock. With respect to various aspects, embodiments, and/or examples of the invention (and/or their equivalents) corresponding to pixel arrays, image sensors, photo detection devices, devices including one or more photo-diodes, etc., including many of the embodiments and/or examples described below, note that any embodiment of an ADC may be implemented to service one or more photo-diodes included within any such device. For example, while many embodiments and/or examples described herein particularly include a photo-diode therein, note that any embodiment of an ADC as described herein (and/or their equivalents) may be implemented to service a photo-diode. Several examples are described below corresponding to image sensors that include multiple pixels. As described above, a particular pixel is pictorially illustrated as a square in certain diagrams, and a given pixel may include one or more photo-diodes therein. In some examples, each respective pixel includes one single photo-diode. In other examples, each respective pixel includes more than one photo-diode (e.g., such as three respective photo-diodes, each particularly tailored for a particular portion of the visible spectrum, such as red, green, and blue (RGB)). FIG.52Ais a schematic block diagram showing an embodiment5201of a photo-diode image sensor in accordance with the present invention. In this diagram a pixel array is shown as including multiple pixels. In one example, consider each square within the array includes one photo-diode. Also, one ADC is implemented to service each respective photo-diode of the array such that the number of ADCs corresponds to the number of pixels in the array. Note that while this particular pixel array is shown as being square in shape, including a common number of rows and columns within the pixel array, note that a pixel array may generally be implemented within any desired shape. Examples of such shapes might include square, rectangular, circular, oval, and/or any other desired shape of an image sensor that includes photo-diodes therein. In various embodiments described below, different implementations of ADCs servicing one or more photo-diodes are described. FIG.52Bis a schematic block diagram showing various embodiments5202of groupings of pixels within a photo-diode image sensor in accordance with the present invention. This diagram is similar to the previous diagram showing a pixel array, but in this diagram, one or more groups of pixels are grouped together within subgroups. For example, on the upper left-hand corner of the pixel array, a 3×3 pixel subgroup is shown. In the upper right-hand corner of the pixel array, a 2×2 pixel subgroup is shown. In other portions the pixel array, a 2×3 pixel subgroup is shown, and a 4×4 pixel subgroup is shown. Note that different respective pixel subgroups may be implemented in other examples. Generally speaking, any group of two or more pixels may be grouped together to form a pixel subgroup. Note also that a pixel may be included in more than one subgroup in certain particular examples. In other examples, each respective subgroup is included with only one subgroup. Also, note that while different respective pixel subgroups are shown in this diagram of being different size including different numbers of pixels, another example includes pixel subgroups each having the same number of pixels there in and being of the same size. For example, consider a pixel array that is subdivided such that it is composed of a number of pixel subgroups of size N×N or N×M, such that N and M are each positive integers greater than or equal to 1. In a specific example, consider that a pixel array is subdivided into uniformly sized 2×2 pixel subgroups, 3×3 pixel subgroups, 4×4 pixel subgroups, or some other size. In another specific example, consider the pixel array is subdivided into the uniformly sized 2×4 pixel subgroups, 3×5 pixel subgroups, or some other size. When a pixel array is subdivided into a number of pixel subgroups, note that each respective pixel subgroup may be serviced by one ADC. For example, consider a pixel array that includes X pixels in total that are divided into Y pixel subgroups each of size Z×Z, such that X, Y, and Z are positive integers, and X is greater than Y, then one respective ADC may be implemented for each of the Y pixel subgroups. For example, a ADC that services the Z respective pixels within a given one of the Y pixel subgroups such that that particular ADC services a first pixel of the Z pixels within the pixel subgroup at a first time, a second pixel of the Z pixels within the pixel subgroup at a second time, a third pixel of the Z pixels was in the pixel subgroup the third time, and so on. After the ADC has serviced each of the Z respective pixels within that particular one of the Y pixel subgroups, the ADC would return back to the first pixel of the Z pixels within the pixel subgroup. Over time, that one ADC would continue to progress through the respective Z respective pixels within that particular one of the Y pixel subgroups. Also, note that any desired pattern of scanning of the Z respective pixels within that particular one of the Y pixel subgroups may be performed. That is to say, the scanning need not necessarily go in one particular order during each scan. In some examples, a scan through the Z respective pixels starts at the top left of the pixel subgroup and proceed along the top row of that pixel subgroup until that particular row of that pixel subgroup is completed, then proceeds to the second two top row of that pixel subgroup, and proceeded along the second row from left to right, and so on through the entire pixel subgroup. Alternatively, different respective stands may sample different respective pixels of the pixel subgroup at different times. For example, consider the Z respective pixels within that particular one of the Y pixel subgroups, during a first scan, perhaps a first subgroup of those Z respective pixels are serviced by the ADC. And during a second scan, a second subgroup of those Z respective pixels are serviced by the ADC, such that different respective subgroups of those Z respective pixels are serviced during different respective scans. Generally speaking, the scanning of the pixels within the pixel subgroup may be performed in accordance with any desired pattern, periodicity, etc. FIG.52Cis a schematic block diagram showing an embodiment5203a device stack-up within a photo-diode image sensor in accordance with the present invention. This diagram shows a view of a portion of the stack-up of a device that includes an image sensor. In this example, the bottom shows a printed circuit board (PCB), above that is an ADC chip, it and above that is a sensor chip. Note that the sensor chip may include one or more photo-diodes, and the ADC chip may include one or more ADCs. For example, consider an implementation in which the sensor chip corresponds to one pixel of the pixel array and includes one photo-diode, then the ADC chip may include one ADC that services that particular sensor chip. In another example, consider an inclination in which the sensor chip corresponds to a pixel subgroup that includes multiple pixels, then the ADC chip may include one ADC that services all of the pixels of that particular subgroup within the sensor chip. As described herein, in ADC implemented in accordance with various aspects, embodiments, and/or examples of the invention (and/or their equivalents), including ADC that is implemented to service one or more photo-diodes, may be implemented having much smaller size than those employed within previous technologies. For example, consider a pixel array as described herein including X×Y pixels. Each respective pixel of the pixel array is very small (e.g., 12 microns×12 microns, where 1 micron=1μ-meter). In ADC that is implemented as described here is smaller than the size of a pixel within a pixel array, and can be implemented directly underneath a pixel within a pixel array. This is a significant improvement over prior technologies such that, by implementing ADCs as described herein, a respective ADC may be implemented underneath each respective pixel within a pixel array. In certain alternative embodiments, such as using an ADC to service more than one pixel of the pixel array, there is even more space available underneath the pixel array. For example, using some form of multiplexing, time-division servicing, etc. of an ADC servicing more than one pixel of the pixel array, such as when the pixels of the pixel array are subdivided into pixel subgroups, there is even more space available underneath the pixel array. One of the many advantages of using ADC as described herein to service one or more photo-diodes is that the very small size and low power consumption of such an ADC allows for it to be implemented directly beneath a pixel. In one particular implementation, there is one photo-diode implemented for each respective pixel of the pixel array (e.g., each respective ADC implemented directly underneath its corresponding pixel of the pixel array so as to service the photo-diode of that particular pixel). In another implementation, there is one photo-diode implemented underneath a pixel subgroup of the pixel array (e.g., each respective ADC implemented directly underneath its corresponding pixel subgroup so as to service the photo-diodes of those particular pixels of that pixel subgroup). FIG.52Dis a schematic block diagram showing an embodiment5204of multiple ADCs respectively servicing photo-diodes within a photo-diode image sensor in accordance with the present invention. This diagram shows multiple ADCs implemented to service photo-diodes such that each respective ADC is connected or coupled to a corresponding photo-diode. In an example, each respective photo-diode corresponds to one pixel of a pixel array of an image sensor. In another example, more than one photo-diode corresponds to one pixel of a pixel array of an image sensor, such that more than one photo-diodes service a pixel of the pixel array (e.g., RGB including three photo-diodes the service a particular pixel of the pixel array). Each of the ADCs is also coupled to the memory, such that as the ADCs service the respective photo-diodes, that information generated thereby is provided in digital format for storage in the memory. In addition, the pixel scanner is coupled to the memory. In an example of operation and implementation, the pixel scanner accesses the memory according to a desired pattern, periodicity, etc. so that the device processes information corresponding to each of the respective pixels of the pixel array. FIG.53Ais a schematic block diagram showing an embodiment5301of a single ADC respectively servicing multiple photo-diodes within a photo-diode image sensor in accordance with the present invention. This diagram has some similarities to the previous diagram including a pixel scanner and a memory. In an example, each respective photo-diode corresponds to one pixel of a pixel array of an image sensor. In another example, more than one photo-diode corresponds to one pixel of a pixel array of an image sensor, such that more than one photo-diodes service a pixel of the pixel array (e.g., RGB including three photo-diodes the service a particular pixel of the pixel array). This diagram shows a single ADC implemented to service photo-diodes such that the ADC is connected or coupled to the photo-diodes via some multiplexing, switching, etc. means. For example, a multiplexer may be implemented such that the pixel scanner selects which particular photo-diode is connected to or coupled to the ADC at a particular time. Alternatively, the ADC is connected to or coupled to the respective photo-diodes via a switching mechanism such that the pixel scanner can select which one of the photo-diodes is connected to or coupled to the ADC at a particular time. In an example, the pixel scanner selects a first photo-diode to be serviced by the ADC at a first time, a second photo-diode be serviced by the ADC is a second time, a third photo-diode the service by the ADC is a third time, and so on. As the ADC services the respective photo-diodes to which it is connected or coupled via the multiplexing, switching, etc. means, the digital information generated by the ADC provided in digital format for storage in the memory. FIG.53Bis a schematic block diagram showing an embodiment5302of a multiple instantiations of single ADCs each respectively servicing multiple photo-diodes within a photo-diode image sensor in accordance with the present invention. This diagram has some similarities to the previous diagram including a pixel scanner and a memory. This diagram is similar to the previous diagram but includes multiple instantiations of ADCs that respectively service more than one photo diode. The first ADC is implemented to service a first group of photo-diodes via a first multiplexing, switching, etc. means, and a second ADC is implemented to service the second group of photo-diodes via a second multiplexing, switching, etc. means. Generally seeking, any number of instantiations of ADCs that respectively service more than one photo-diode may be implemented within a device. It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, text, graphics, audio, etc. any of which may generally be referred to as ‘data’). As may be used herein, the terms “substantially” and “approximately” provide an industry-accepted tolerance for its corresponding term and/or relativity between items. For some industries, an industry-accepted tolerance is less than one percent and, for other industries, the industry-accepted tolerance is 10 percent or more. Other examples of industry-accepted tolerance range from less than one percent to fifty percent. Industry-accepted tolerances correspond to, but are not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, thermal noise, dimensions, signaling errors, dropped packets, temperatures, pressures, material compositions, and/or performance metrics. Within an industry, tolerance variances of accepted tolerances may be more or less than a percentage level (e.g., dimension tolerance of less than +/−1%). Some relativity between items may range from a difference of less than a percentage level to a few percent. Other relativity between items may range from a difference of a few percent to magnitude of differences. As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item. As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal1has a greater magnitude than signal2, a favorable comparison may be achieved when the magnitude of signal1is greater than that of signal2or when the magnitude of signal2is less than that of signal1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship. As may be used herein, one or more claims may include, in a specific form of this generic form, the phrase “at least one of a, b, and c” or of this generic form “at least one of a, b, or c”, with more or less elements than “a”, “b”, and “c”. In either phrasing, the phrases are to be interpreted identically. In particular, “at least one of a, b, and c” is equivalent to “at least one of a, b, or c” and shall mean a, b, and/or c. As an example, it means: “a” only, “b” only, “c” only, “a” and “b”, “a” and “c”, “b” and “c”, and/or “a”, “b”, and “c”. As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, “processing circuitry”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, processing circuitry, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, processing circuitry, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, processing circuitry, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, processing circuitry and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, processing circuitry and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture. One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof. In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines. In addition, a flow diagram may include an “end” and/or “continue” indication. The “end” and/or “continue” indications reflect that the steps presented can end as described and shown or optionally be incorporated in or otherwise used in conjunction with one or more other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained. The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones. Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art. The term “module” is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules. As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid-state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information. While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations. | 289,367 |
11942968 | DETAILED DESCRIPTION Various example embodiments will be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Like reference numerals refer to like elements throughout this application. A multi-level signaling scheme may be used as a means of compressing the bandwidth required to transmit data at a given bit rate. In a simple binary scheme, two single symbols, usually two voltage levels, may be used to represent ‘1’ and ‘0,’ and thus the symbol rate may be equal to the bit rate. In contrast, the principle of the multi-level signaling scheme may be to use a larger alphabet of m symbols to represent data, so that each symbol may represent more than one bit of data. As a result, the number of symbols that needs to be transmitted may be less than the number of bits (e.g., the symbol rate may be less than the bit rate), and thus the bandwidth may be compressed. In other words, the multi-level signaling scheme may be used to increase a data transmission (or transfer) rate without increasing the frequency of data transmission and/or a transmission power of the communicated data. An example of one type of the multi-level signaling scheme may be a pulse amplitude modulation (PAM) scheme, where a unique symbol of a multi-level signaling may represent a plurality of bits of data. FIG.1is a block diagram illustrating a transmitter and a receiver according to some example embodiments. Referring toFIG.1, a transmitter (TX)100and a receiver (RX)200may be connected to each other through a channel50. The transmitter100may generate an output data signal TX_OUT based on an input data signal TX_IN including a plurality of binary input bits. The output data signal TX_OUT may include a plurality of PAM-3 symbols and each of the plurality of PAM-3 symbols may have a first voltage level VL1, a second voltage level VL2 and a third voltage level VL3. The output data signal TX_OUT may be transmitted to the receiver200through the channel50. The receiver200may generate an output data signal RX_OUT including a plurality of binary output bits based on an input data signal RX_IN including a plurality of PAM-3 symbols. For example, the three voltage levels of the output data signal TX_OUT may include a first voltage level VL1, a second voltage level VL2 higher than the first voltage level VL1, and a third voltage level VL3 higher than the second voltage level VL2. The first voltage level VL1, the second voltage level VL2 and the third voltage level VL3 may be referred to as a low level, a middle (or mid) level and a high level, respectively. For example, the output data signal RX_OUT may have two voltage levels that are different from each other, and one value (or data) included in the output data signal RX_OUT that is the binary signal may represent one value (or bit) included in the input data signal TX_IN. For example, the two voltage levels of the output data signal RX_OUT may include the first voltage level VL1 and a fourth voltage level VL4 higher than the first voltage level VL1. The first voltage level VL1 and the fourth voltage level VL4 may be referred to as a low level and a high level, respectively. For example, the fourth voltage level VL4 may be higher than the third voltage level VL3, and may be about 1.2V. In other words, a swing width (e.g., a voltage difference between the low and high levels) of the output data signal RX_OUT may be greater than a swing width of the output data signal TX_OUT. For example, the input data signal TX_IN that is the binary signal may also have two voltage levels that are different from each other. For example, although not illustrated inFIG.1, a low level of the input data signal TX_IN may be substantially equal to the first voltage level VL1, and a high level of the input data signal TX_IN may be substantially equal to the third voltage level VL3. The transmitter100and the receiver200according to some example embodiments may have a structure for reducing occupied area and power consumption. Detailed configurations and operations of the transmitter100will be described with reference toFIGS.2through12. Detailed configurations and operations of the receiver200will be described with reference toFIGS.13through17. FIG.2is a block diagram illustrating an example of the transmitter inFIG.1according to some example embodiments. Referring toFIG.2, the transmitter100may include an encoder110and a driver190. The encoder110may divide a first number of binary input bits of the input data signal TX_IN into a first bit group BTG1 and a second bit group BTG2, may generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 differently and may generate a first symbol group SG1 and a second symbol group SG1 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2, respectively. Each of the first symbol group SG1 and the second symbol group SG2 may include a plurality of symbols and each of the plurality of symbols may have three different voltage levels. The driver190may generate the output data signal TX_OUT by concatenating the first symbol group SG1 and the second symbol group SG2 and may transmit the output data signal TX_OUT to the receiver200through the channel50. For example, when the input data signal TX_IN includes a first number of binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10, the first bit group BTG1 may include a second number of binary input bits b0, b1, b2, b3 and b4, the second bit group BTG2 may include a third number of binary input bits b5, b6, b7, b8, b9 and b10 and the third number may be greater than the second number. The first number may correspond to eleven, the second number may correspond to five and the third number may correspond to six. In addition, the first symbol group SG1 may include a plurality of first symbols S0, S1 and S2 and the second symbol group SG2 may include a plurality of second symbols S3, S4, S5 and S6. That is, the first symbol group SG1 may include a fifth number of first symbols S0, 51 and S2 and the second symbol group SG2 may include a sixth number second symbols S3, S4, S5 and S6. The encoder110may include an intermediate data generator120, a first sub encoder170and a second sub encoder180. The intermediate data generator120may generate the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 by manipulating the first bit group BTG1 including binary input bits b0, b1, b2, b3 and b4 and the and the second bit group BTG2 including the binary input bits b5, b6, b7, b8, b9 and b10. The first sub encoder170may generate the first symbol group SG1 including the first symbols S0, S1 and S2 by encoding the first intermediate bit group IBTG1. The second sub encoder180may generate the second symbol group SG2 including the second symbols S3, S4, S5 and S6 by encoding the second intermediate bit group IBTG2. FIG.3is a block diagram illustrating an example of the intermediate data generator in the transmitter ofFIG.2according to some example embodiments. Referring toFIG.3, the intermediate data generator120may include a check value generator121, a first demultiplexer123, a second demultiplexer125, a first data manipulator,130, a second data manipulator140, a first multiplexer160and a second multiplexer165. The check value generator121may receive the first bit group BTG1 and may generate a check value CHK indicating whether a value of the first bit group BTG1 is equal to or greater than a first threshold value. The check value generator121may generate the check value CHK having a first logic level (e.g., a logic low level) in response to the value of the first bit group BTG1 being smaller than the first threshold value and may generate the check value CHK having a second logic level (e.g., a logic high level) in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value. For example, the first threshold value may be 26. The first demultiplexer123may receive the first bit group BTG1 and the second bit group BTG2, may provide the first bit group BTG1 and the second bit group BTG2 to the first data manipulator130in response to the check value CHK indicating that the value of the first bit group BTG1 is smaller than the first threshold value and may provide the first bit group BTG1 and the second bit group BTG2 to the second data manipulator140in response to the check value CHK indicating that the value of the first bit group BTG1 is equal to or greater than the first threshold value. The second demultiplexer125may receive the check value CHK, may provide the check value CHK to the first data manipulator130in response to the check value CHK indicating that the value of the first bit group BTG1 is smaller than the first threshold value and may provide the check value CHK to the second data manipulator140in response to the check value CHK indicating that the value of the first bit group BTG1 is equal to or greater than the first threshold value. The first data manipulator130may generate a first sub intermediate bit group IBTG11 and a second sub intermediate bit group IBTG12 by manipulating the first bit group BTG1 and the second bit group BTG2 according to a first scheme, respectively, in response to the value of the first bit group BTG1 being smaller than the first threshold value and based on the check value CHK. The first data manipulator130, in response to the value of the first bit group BTG1 being smaller than the first threshold value, may generate the first sub intermediate bit group IBTG11 based on the first bit group BTG1 and may generate the second sub intermediate bit group IBTG12 based on the second bit group BTG2 and the check value CHK. The second data manipulator140may generate a third sub intermediate bit group IBTG21 and a fourth sub intermediate bit group IBTG22 by manipulating the first bit group BTG1 and the second bit group BTG2 according to a second scheme different from the first scheme, respectively, in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value and based on the check value CHK. The second data manipulator140, in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value, may generate the third sub intermediate bit group IBTG21 based on the first bit group BTG1 and the second bit group BTG2, and may generate the fourth sub intermediate bit group IBTG22 based on the check value CHK and the second bit group BTG2. Here, the first scheme and the second scheme may include circuitry configured to perform certain mathematical operations. For example, the first bit group BTG1 and the second bit group BTG2 may be used by the first data manipulator130to generate the first sub intermediate bit group IBTG11 and the second sub intermediate bit group IBTG12 based on circuitry configured to perform the first scheme. For example, the first bit group BTG1 and the second bit group BTG2 may be used by the second data manipulator140to generate the third sub intermediate bit group IBTG21 and the fourth sub intermediate bit group IBTG22 based on circuitry configured to perform the second scheme. The first multiplexer160may receive the first sub intermediate bit group IBTG11 and the third sub intermediate bit group IBTG21 and may output one of the first sub intermediate bit group IBTG11 and the third sub intermediate bit group IBTG21 as the first intermediate bit group IBTG1, based on the check value CHK. The second multiplexer160may receive the second sub intermediate bit group IBTG12 and the fourth sub intermediate bit group IBTG22 and may output one of the second sub intermediate bit group IBTG12 and the fourth sub intermediate bit group IBTG22 as the second intermediate bit group IBTG2, based on the check value CHK. The first multiplexer160may provide the first sub intermediate bit group IBTG11 as the first intermediate bit group IBTG1 in response to the check value CHK having a first logic level (e.g., in response to the value of the first bit group BTG1 being smaller than the first threshold value) and may provide the third sub intermediate bit group IBTG21 as the first intermediate bit group IBTG1 in response to the check value CHK having a second logic level (e.g., in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value). The second multiplexer165may provide the second sub intermediate bit group IBTG12 as the second intermediate bit group IBTG2 in response to the check value CHK having a first logic level and may provide the fourth sub intermediate bit group IBTG22 as the second intermediate bit group IBTG2 in response to the check value CHK having a second logic level. When the check value CHK has a first logic level and indicates that the value of the first bit group BTG1 is smaller than the first threshold value, the first data manipulator130generates the first sub intermediate bit group IBTG11 and the second sub intermediate bit group IBTG12 by manipulating the first bit group BTG1 and the second bit group BTG2 according to the first scheme, respectively, and the first multiplexer160and the second multiplexer165provide the first sub intermediate bit group IBTG11 and the second sub intermediate bit group IBTG12 as the first intermediate bit group IBTG1 and the second intermediate bit group IBTC2, respectively. When the check value CHK has a second logic level and indicates that the value of the first bit group BTG1 is equal or greater than the first threshold value, the first data manipulator130generates the third sub intermediate bit group IBTG21 and the fourth sub intermediate bit group IBTG22 by manipulating the first bit group BTG1 and the second bit group BTG2 using the check value CHK and according to the second scheme, respectively, and the first multiplexer160and the second multiplexer165provide the third sub intermediate bit group IBTG21 and the fourth sub intermediate bit group IBTG22 as the first intermediate bit group IBTG1 and the second intermediate bit group IBTC2, respectively. FIG.4illustrates an operation of the first data manipulator in the intermediate data generator ofFIG.3according to some example embodiments. Referring toFIGS.3and4, in response to the value of the first bit group BTG1 being smaller than the first threshold value, the first data manipulator130provides the first bit group BTG1 including first binary input bits b0, b1, b2, b3 and b4 as the first sub intermediate bit group IBTG11 (operation S111), provides the check value CHK and second bit group BTG2 including second binary input bits b5, b6, b7, b8, b9 and b10 as the second sub intermediate bit group IBTG12 (operation S112), and the first multiplexer160and the second multiplexer165output the first sub intermediate bit group IBTG11 and the second sub intermediate bit group IBTG12 as the first intermediate bit group IBTG1 (operation5113) and the second intermediate bit group IBTC2 (operation S114), respectively. Therefore, when the value of the first bit group BTG1 is smaller than the first threshold value, each of first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 of the first intermediate bit group IBTG1 is the same as a respective one of the first binary input bits b0, b1, b2, b3 and b4, and each of second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 of the second intermediate bit group IBTG2 is the same as a respective one of the check value CHK and the second binary input bits b5, b6, b7, b8, b9 and b10. FIG.5illustrates an operation of the second data manipulator in the intermediate data generator ofFIG.3according to some example embodiments. Referring toFIGS.3and5, in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value, the second data manipulator140provides a manipulated portion b2×b3, b3′ and b4 of the first binary input bits b0, b1, b2, b3 and b4 of the first bit group BTG1 and a portion b5 and b6 of the second binary input bits b5, b6, b7, b8, b9 and b10 of the second bit group BTG2 as the third sub intermediate bit group IBTG21 (operation S211), provides the check value CHK, specific constants 0 and 0 and a remaining portion b7, b8, b9 and b10 of the second binary input bits b5, b6, b7, b8, b9 and b10 of the second bit group as the fourth sub intermediate bit group IBTG22 (operation S212), and the first multiplexer160and the second multiplexer165output the third sub intermediate bit group IBTG21 and the fourth sub intermediate bit group IBTG22 as the first intermediate bit group IBTG1 (operation5213) and the second intermediate bit group IBTC2 (operation S214), respectively. Here, “x” denotes a logical multiplication and “ ” denotes a logical NOT. Therefore, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, each of first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 of the first intermediate bit group IBTG1 corresponds to respective one of b2×b3, b3′, b4, b5 and b6, and each of second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 of the second intermediate bit group IBTG2 corresponds to respective one of CHK, 0, 0, b7, b8, b9 and b10. The first intermediate bit group IBTG1 may include a second number of the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4, and the second intermediate bit group may include a fourth number of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 and the fourth number is greater than the third number by one. The fourth number may be 7. FIG.6illustrates an example of the second data manipulator in the intermediate data generator ofFIG.3according to some example embodiments. Referring toFIG.6, the second data manipulator140may include an AND gate141and an inverter142. The AND gate141may perform an AND operation on binary input bits b2 and b3 and provide a result of the AND operation as an intermediate bit Ib0. The inverter142may provide an intermediate bit Ib1 by inverting a binary input but B3 and a specific constant “0” may be assigned to each of intermediate bits Ib6 and Ib7. In some example embodiments, a specific constant “1” may be assigned to each of intermediate bits Ib6 and Ib7. In addition, the second data manipulator140may provide a binary input bit b4 as an intermediate bit Ib2, may provide a binary input bit b5 as an intermediate bit Ib3, may provide check value CHK as an intermediate bit Ib4, and may provide each of binary input bits b7, b8, b9 and b10 as respective one of intermediate bits Ib8, Ib9, Ib10 and Ib11. FIG.7illustrates operations of the first sub encoder and the second sub encoder in the encoder ofFIG.2according to some example embodiments. Referring toFIG.7, the first sub encoder170may generate the first symbol group SG1 including the first three symbols S0, S1 and S2 by performing a first encoding of 5-bit to 3-symbol (5b3S) on the first intermediate bit group IBTG1 including the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4. The second sub encoder180may generate the second symbol group SG2 including the second four symbols S3, S4, S5 and S6 by performing a second encoding of 7-bit to 4-symbol (7b4S) on the second intermediate bit group IBTG2 including the second intermediate bits Ib5, Ib6, Ib7, Ib8, 1119 and Ib10. The first sub encoder170may perform the first encoding in parallel with the second sub encoder180performing the second encoding. The encoder110in the transmitter100ofFIG.2, instead of encoding 11-bit of binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10 into seven symbols at one time, may divide the 11-bit of binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10 into the first bit group BTG1 including a second number of binary input bits b0, b1, b2, b3 and b4 and the second bit group BTG2 including a third number of binary input bits b5, b6, b7, b8, b9 and b10, may generate the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 differently according to the value of the first bit group BTG1 and may generate the first symbol group SG1 including the first three symbols S0, S1 and S2 and the second symbol group SG2 including the second four symbols S3, S4, S5 and S6 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 in parallel. Therefore, the encoder110may reduce an occupied area and power consumption when compared with a case that the encoder110encodes 11-bit of binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10 into seven symbols at one time. FIG.8illustrates an example of a first look-up table that the first sub encoder inFIG.7uses according to some example embodiments. Referring toFIG.8, the first sub encoder170inFIG.7may perform a first encoding of 5-bit to 3-symbol (5b3S) by using a first look-up table LUT1 indicating mapping relation between the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 and the first symbols S0, S1 and S2. InFIG.8, Ib(0:4) denotes the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4, and when the value of the first bit group BTG1 is smaller than the first threshold value (e.g., 26), each of first intermediate bits Ib0, Ib0, Ib2, Ib3 and Ib4 of the first intermediate bit group IBTG1 is the same as respective one of the first binary input bits b0, b1, b2, b3 and b4 as mentioned above. Therefore, Ib(0:4) inFIG.8corresponds to the first binary input bits b0, b1, b2, b3 and b4. When the first binary input bits b0, b1, b2, b3 and b4 are mapped to the first symbols S0, S1 and S2, 25(i.e., 32) combinations are possible. When the value of the first bit group BTG1 is equal to or greater than the first threshold value (e.g., 26), the first binary input bits b0, b1, b2, b3 and b4 are not assigned to the first symbols S0, S1 and S2. When a value of the first binary input bits b0, b1, b2, b3 and b4 corresponds to one of ‘0’ through ‘25’, the first binary input bits b0, b1, b2, b3 and b4 are mapped to the first symbols S0, S1 and S2. The symbol S0 may represent 2-bit t[0:1] of the output data signal TX_OUT, the symbol S1 may represent 2-bit t[2:3] of the output data signal TX_OUT, and the symbol S2 may represent 2-bit t[4:5] of the output data signal TX_OUT. FIG.9is an example table that implements the first look-up table ofFIG.8with gate-level logic. Referring toFIG.9, the check value CHK and bits t0, t1, t2, t3, t4 and t5 of the output data signal TX_OUT in the first look-up table LUT1 are represented as following expression 1. CHK=Ib0×Ib1×Ib3+Ib0×Ib1×Ib2 [Expression 1] t0=Ib0′+Ib1 t1=Ib0×Ib1×Ib4+Ib0′×Ib1′ t2=Ib0′×Ib2′+Ib1′×Ib2′+Ib2×Ib4 t3=Ib2′×Ib3+Ib3×Ib4 t4=Ib0′×Ib4+Ib1′×Ib4+Ib2 t5=bI2×Ib4+Ib2×Ib3 The bits t0, t1, t2, t3, t4 and t5 of the output data signal TX_OUT may be obtained based on combinations of the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4. FIGS.10A,10B and10Cillustrate an example of a second look-up table that the second sub encoder inFIG.7uses according to some example embodiments. Referring toFIGS.10A,10B and10C, the first sub encoder180inFIG.7may perform a second encoding of 7-bit to 4-symbol (7b4S) by using a second look-up table LUT2 indicating mapping relation between the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9 and Ib10 and the second symbols S3, S4, S5 and S6. InFIGS.10A,10B and10C, Ib[5:11] denotes the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 and when the value of the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 is equal to or greater than the 80 (e.g., a second threshold value), the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 are not mapped to the second symbols S3, S4, S5 and S6. When the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 are mapped to the second symbols S3, S4, S5 and S6, 27 (i.e.,128) combinations are possible, however, the second sub encoder180may use 80 combinations when the value of the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 corresponds to one of ‘0’ through ‘79’ and the second sub encoder180does not use the combinations in which the value of the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 is equal to or greater than 80. The symbol S3 may represent 2-bit 46:71 of the output data signal TX_OUT, the symbol S4 may represent 2-bit 48:91 of the output data signal TX_OUT, the symbol S5 may represent 2-bit t[10:11] of the output data signal TX_OUT, and the symbol S6 may represent 2-bit t[12:13] of the output data signal TX_OUT. Referring to the first look-up table LUT1 inFIG.8and the second look-up table LUT2 inFIGS.10A,10B and10C, when the value of the first bit group BTG1 is smaller than the first threshold value, the first sub encoder170inFIG.7may generate 26 combinations of the first symbols S0, S1 and S2 based on the first binary input bits b0, b1, b2, b3 and b4 and the second first sub encoder180inFIG.7may generate 64 combinations of the second symbols S3, S4, S5 and S6 based on the second binary input bits b5, b6, b7, b8, b9 and b10. Therefore, when the value of the first bit group BTG1 is smaller than the first threshold value, the first sub encoder170and the second sub encoder180inFIG.7may generate 1664 (i.e., 26×64) combinations of symbols S0, S1, S2, S3, S4, S5 and S6. In addition, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, the first sub encoder170may generate 24 combinations of the first symbols S0, S1 and S2 based on the first binary input bits b0, b1, b2, b3 and b4 and a portion b5 and b6 of the second binary input bits b5, b6, b7, b8, b9 and b10 and the second first sub encoder180may generate 16 combinations of the second symbols S3, S4, S5 and S6 based on a remaining portion b7, b8, b9 and b10 of the second binary input bits b5, b6, b7, b8, b9 and b10. Therefore, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, the first sub encoder170and the second sub encoder180inFIG.7may generate384(i.e., 24×16) combinations of symbols S0, S1, S2, S3, S4, S5 and S6. Therefore, the encoder110may generate 2048 combinations of symbols S0, S1, S2, S3, S4, S5 and S6 based on the first number of the binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10. FIG.11is an example table that implements the second look-up table ofFIGS.10A,10B and10Cwith gate-level logic. Referring toFIG.11, bits t6, t7, t8, t9, t10, t11, t12 and t13 of the output data signal TX_OUT in the second look-up table LUT2 are represented as following expression 2. t6=Ib5′×Ib6′+Ib8×Ib9′+Ib8×Ib11+Ib6×Ib8 [Expression 2] t7=Ib5×Ib8×Ib9′×Ib10+Ib5×Ib8×Ib10×Ib11+Ib6′×Ib7+Ib7×Ib8 t8=Ib5′×Ib8+Ib8×Ib11+Ib8×Ib9+Ib6 t9=Ib5×Ib8×Ib9×Ib11+Ib5×Ib8×Ib9×Ib10+Ib6×Ib8+Ib6×Ib7 t10=Ib5′×Ib9′+Ib8′×Ib9′+Ib5′×Ib11+Ib8′×Ib11 t11=Ib5′×Ib9′×Ib10+Ib8′×Ib9′×Ib10+Ib5′×Ib10×Ib11+Ib8′×Ib10×Ib11 t12=Ib5′×Ib11+Ib8′×Ib11+Ib5′×Ib9+Ib8′×Ib9 t13=Ib5×Ib9×Ib11+Ib8′×Ib9×Ib11+Ib5′×Ib9×Ib10+Ib8′×Ib9×Ib10 The bits t6, t7, t8, t9, t10, t11, t12 and t13 of the output data signal TX_OUT may be obtained based on combination of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11. FIG.12is a block diagram illustrating an example of the receiver inFIG.1according to some example embodiments. Referring toFIG.12, the receiver200may include a decoder210and a buffer290. The decoder210may generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by decoding a first symbol group SG1 and a second symbol group SG2 of an input data signal (RX_IN inFIG.1), respectively, each of which includes a plurality of symbols having three different voltage levels, and may generate a first bit group BTG1 and a second bit group BTG2 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 differently based on a value of a specific bit of the second intermediate bit group IBTG2. The buffer290may generate an output data signal RX_OUT including a first number of binary output bits by buffering the first bit group BTG1 and the second bit group BTG2. The output data signal RX_OUT may be referred to as a recovered data signal RDT. The decoder210may include a first sub decoder220, a second sub decoder230and a data recovery circuit240. The first sub decoder220may generate the first intermediate bit group IBTG1 including first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 by decoding the first symbol group SG1 including first symbols S0, S1 and S2. The second sub decoder230may generate the second intermediate bit group IBTG2 including second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 by decoding the second symbol group SG2 including second symbols S3, S4, S5 and S6. The first sub decoder220may generate the first intermediate bit group IBTG1 including the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 of five bits by perform a first decoding of 3-symbol to 5-bit (3S5b) on the first symbol group SG1 including the first three symbols S0, S1 and S2. The second sub decoder220may generate the second intermediate bit group IBTG2 the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 of seven bits by perform a second decoding of 4-symbol to 7-bit (4S7b) on the second symbol group SG2 including the second four symbols S3, S4, S5 and S6. The first sub decoder220may perform the first decoding in parallel with the second sub decoder230performing the second decoding. The data recovery circuit240may recover the first bit group BTG1 and the second bit group BTG2 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 differently based on a value of the specific bit of the second intermediate bit group IBTG2. FIG.13is a block diagram illustrating an example of the data recovery circuit in the receiver ofFIG.12according to some example embodiments. Referring toFIG.13, the data recovery circuit240may include a check value extractor241, a demultiplexer243, a first data recovering logic250, a second data recovering logic260, a first multiplexer270and a second multiplexer275. The check value extractor241may output a check value CHK by extracting a specific bit from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 of the second intermediate bit group IBTG2. The check value extractor241may extract a first bit Ib5 from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 as the check value CHK and may provide the check value CHK to the demultiplexer243, the first multiplexer270and the second multiplexer275. The demultiplexer243may provide the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 to the first data recovering logic250in response to the check value CHK having a first logic level (e.g., a logic low level), and may provide the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 to the second data recovering logic260in response to the check value CHK having a second logic level (e.g., a logic high level). The first data recovering logic250may generate a first sub bit group BTG11 and a second sub bit group BTG12 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 according to a first scheme, respectively, in response to the check value having a first logic level. The second data recovering logic260may generate a third sub bit group BTG21 and a fourth sub bit group BTG22 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 according to a second scheme different from the first scheme, respectively, in response to the check value having a second logic level. The first multiplexer270may receive the first sub bit group BTG11 and the third sub bit group BTG21 and may output one of the first sub bit group BTG11 and the third sub bit group BTG21 as the first bit group BTG1 based on the check value CHK. The second multiplexer275may receive the second sub bit group BTG12 and the fourth sub bit group BTG22 and may output one of the second sub bit group BTG12 and the fourth sub bit group BTG22 as the second bit group BTG2 based on the check value CHK. The first multiplexer270and the second multiplexer275may output the first sub bit group BTG11 and the second sub bit group BTG12 as the first bit group BTG1 and the second bit group BTG2, respectively, in response to the check value having a first logic level, and may output the third sub bit group BTG21 and the fourth sub bit group BTG22 as the first bit group BTG1 and the second bit group BTG, respectively, in response to the check value having a second logic level. FIG.14illustrates an operation of the first data recovering logic inFIG.13according to some example embodiments. Referring toFIGS.13and14, in response to the check value having a first logic level, the first data recovering logic250provides the first intermediate bit group IBTG1 including the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 as the first sub bit group BTG11 (operation S611) and provides the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 as the second sub bit group BTG12 by eliminating the first bit Ib5 from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 (operation S613). In addition, because the first multiplexer270and the second multiplexer275may output the first sub bit group BTG11 and the second sub bit group BTG12 as the first bit group BTG1 and the second bit group BTG2, respectively, output data bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10 of the recovered data signal RDT may include the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 and the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10 (operation S615). As described with reference toFIG.4, each of the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 corresponds to respective one of the bits b0, b1, b2, b3 and b4, and each of the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10 corresponds to respective one of the bits b5, b6, b7, b8, b9 and b10. FIG.15illustrates an operation of the second data recovering logic inFIG.13according to some example embodiments. Referring toFIGS.13and15, in response to the check value having a second logic level, the second data recovering logic260provides the third sub bit group BTG21 including bits 1, 1, Ib1+Ib0, Ib′, Ib2 by filling the specific bit with a specific constant and by manipulating a portion of the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 of the first intermediate bit group IBTG1 (operation S621), and provides remaining portion Ib3 and Ib4 of the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 and a portion Ib8, Ib9, Ib10 and Ib11 of the second intermediate bit group IBTG2 as the fourth sub bit group BTG22 (operation S623). In addition, because the first multiplexer270and the second multiplexer275may output the third sub bit group BTG21 and the fourth sub bit group BTG22 as the first bit group BTG1 and the second bit group BTG2, respectively, output data bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10 of the recovered data signal RDT may include the bits 1, 1, Ib1+Ib0, Ib1 Ib2 and the bits Ib3, Ib4, Ib8, Ib9, Ib10 and Ib11 (operation S625). FIG.16illustrates an example table that represents relationship between bits of the first symbols and the first intermediate bits in the receiver ofFIG.12according to some example embodiments. Referring toFIG.16, a relationship between bits t0, t1, t2, t3, t4 and t5 of the first symbols S0, S1 and S2 and the first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 is represented as following expression 3. Ib0=t2′×t4′+t0′ [Expression 3] Ib1=t0×t1′+t2×t4′ Ib2=t2′×t4′+t5 Ib3=t2′×t5+t3 Ib4=t1×t2′×t4′+t2×t4 The first sub decoder220may use expression 3 when the first sub decoder220performs the first decoding by using the first look-up table LUT ofFIG.8. FIG.17illustrates an example table that represents relationship between bits of the second symbols and the second intermediate bits in the receiver ofFIG.12according to some example embodiments. Referring toFIG.17, relationship between bits t6, t7, t8, t9, t10, t11, t12 and t13 of the second symbols S3, S4, S5 and S6 and the second intermediate bits second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11 is represented as following expression 4. Ib5=t6′×t8′+t10′×t12′ [Expression 4] Ib6=t6′×t8×t10+t6′×t8×t12+t9×t10+t9×t12 Ib7=t6′×t9×t10+t6′×t9×t12+t7×t10+t7×t12 Ib8=t6×t8+t10×t12 Ib9=t10′×t12+t6′×t10′+t9×t10′+t9×t13 Ib10=t6′×t9×t10′×t12′+t7×t10′×t12′+t10′×t13×t11 Ib11=t6×t8×t10′×t12′+t10×t12 The second sub decoder230may use expression 4 when the second sub decoder230performs the second decoding. FIG.18is a flow chart illustrating a method of operating a transmitter according to some example embodiments. Referring toFIGS.2through11and18, the encoder110of the transmitter100divides a first number of binary input bits of the input data signal TX_IN into a first bit group BTG1 and a second bit group BTG2 (operation S100). When the input data signal TX_IN includes a first number of binary input bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9 and b10, the first bit group BTG1 includes a second number of binary input bits b0, b1, b2, b3 and b4, the second bit group BTG2 includes a third number of binary input bits b5, b6, b7, b8, b9 and b10 and the third number may be greater than the second number. The intermediate data generator120of the encoder110generates a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 differently based on a value of the first group BTG1 (operation S200). The first intermediate bit group IBTG1 may include a second number first intermediate bits Ib0, Ib1, Ib2, Ib3 and Ib4 and the second intermediate bit group IBTG2 may include a fourth number of second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10 and Ib11. The fourth number may be greater than the third number. The first sub encoder170and the second sub encoder180of the encoder170generate a first symbol group SG1 including first symbols S0, S1 and S2 and a second symbol group SG2 including second symbols S3, S4, S5 and S6 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2, respectively (operation S300). The driver190may generate the output data signal TX_OUT by concatenating the first symbol group SG1 and the second symbol group SG2 (operation S400) and may transmit the output data signal TX_OUT to the receiver200through the channel50. FIG.19is a flow chart illustrating operations of generating a first intermediate bit group and a second intermediate bit group. Referring toFIGS.3and19, for generating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 (operation S200), the check value generator121determines whether a value of the first bit group BTG1 (e.g., decimal value of the first bit group BTG1) is equal to or greater than a first threshold value (operation S210). The check value generator121receives the first bit group BTG1 and may generate a check value CHK indicating whether the value of the first bit group BTG1 is equal to or greater than the first threshold value. In response to the value of the check value CHK being smaller than the first threshold value (NO in S210), the first data manipulator130and the first multiplexer160generates the second intermediate bit group IBTG2 based on the check value CHK and the second bit group BTG2 while generating the first intermediate bit group IBTG1 based on the first bit group BTG1 (operation S230). In response to the value of the check value CHK being equal to or greater than the first threshold value (YES in S210), the second data manipulator140and the second multiplexer165generates the second intermediate bit group IBTG2 based on the check value CHK and the second bit group BTG2 while generating the first intermediate bit group IBTG1 based on the first bit group BTG1 and the second bit group BTG2 (operation S250). Therefore, according to the transmitter and a method of operating a transmitter, the encoder110, instead of encoding the first number of binary input bits into symbols at one time, divides the first number of binary input into the first bit group including a second number of binary input bits and the second bit group including a third number of binary input bits, generates the first intermediate bit group and the second intermediate bit group by manipulating the first bit group and the second bit group differently according to the value of the first bit group and generates the first symbol group and the second symbol group by encoding the first intermediate bit group and the second intermediate bit group in parallel. Accordingly, the encoder110may reduce an occupied area and power consumption. FIG.20is a block diagram illustrating a memory system according to some example embodiments. Referring toFIG.20, a memory system300may include a memory controller305and a semiconductor memory device400. The memory system300may further include a plurality of signal lines330that electrically connect the memory controller305with the semiconductor memory device400. The semiconductor memory device400may be controlled by the memory controller305. For example, based on requests from a host (not illustrated), the memory controller305may store (e.g., write or program) data into the semiconductor memory device400, or may retrieve (e.g., read or sense) data from the semiconductor memory device400. The plurality of signal lines330may include control lines, command lines, address lines, data input/output (I/O) lines and power lines. The memory controller305may transmit a command CMD, an address ADDR and a control signal CTRL to the semiconductor memory device400via the command lines, the address lines and the control lines, may exchange a data signal MLDAT with the semiconductor memory device400via the data I/O lines, and may transmit a power supply voltage PWR to the semiconductor memory device400via the power lines. For example, a data signal MLDAT may be a PAM-3 multi-level signal that is generated and transmitted according to some example embodiments. Although not illustrated inFIG.20, the plurality of signal lines330may further include data strobe signal (DQS) lines for transmitting a DQS signal. In some example embodiments, at least a part or all of the signal lines330may be referred to as a channel the term “channel” as used herein may represent signal lines that include the data I/O lines for transmitting the data signal MLDAT. However, example embodiments are not limited thereto, and the channel may further include the command lines for transmitting the command CMD and/or the address lines for transmitting the address ADDR. FIGS.21and22are block diagrams illustrating an example embodiment of a memory system ofFIG.20. Referring toFIGS.21and22, a memory system301may include a graphic processing unit (GPU)310, a semiconductor memory device400aand a plurality of channels31a,31band31c. The GPU310may include a plurality of transmitters25a,25band25c, a plurality of receivers27a,27band27c, and a plurality of data I/O pads29a,29band29c. The semiconductor memory device400amay include a plurality of transmitters45a,45band45c, a plurality of receivers47a,47band47c, and a plurality of data I/O pads49a,49band49c. Each of the plurality of transmitters25a,25b,25c,45a,45band45cmay generate a PAM-3 multi-level signal, may perform the method of generating multi-level signal. Each of the plurality of receivers27a,27b,27c,47a,47band47cmay receive the PAM-3 multi-level signal. The plurality of transmitters25a,25b,25c,45a,45band45cand the plurality of receivers27a,27b,27c,47a,47band47cmay transmit and receive PAM-3 multi-level signal through the plurality of channels31a,31band31c. Each of the plurality of transmitters25a,25b,25c,45a,45band45cmay employ the transmitter100ofFIG.2an each of the plurality of receivers27a,27b,27c,47a,47band47cmay employ the receiver200ofFIG.12. Each of the plurality of data I/O pads29a,29b,29c,49a,49band49cmay be connected to a respective one of the plurality of transmitters25a,25b,25c,45a,45band45cand a respective one of the plurality of receivers27a,27b,27c,47a,47band47c. The plurality of channels31a,31band31cmay connect GPU310with the semiconductor memory device400a. Each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters25a,25band25cand a respective one of the plurality of receivers27a,27band27cthrough a respective one of the plurality of data I/O pads29a,29band29c. In addition, each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters45a,45band45cand a respective one of the plurality of receivers47a,47band47cthrough a respective one of the plurality of data I/O pads49a,49band49c. The PAM-3 multi-level signal may be transmitted through each of the plurality of channels31a,31band31c. FIG.21illustrates an operation of transferring data from the GPU310to the semiconductor memory device400a. For example, the transmitter25amay generate an output data signal DS11, which is the PAM-3 multi-level signal, based on input data DAT11, the output data signal DS11 may be transmitted from the GPU310to the semiconductor memory device400athrough the channel31a, and the receiver47amay receive the output data signal DS11 to obtain data ODAT11 corresponding to the input data DAT11. Similarly, the transmitter25bmay generate an output data signal DS21, which is the PAM-3 multi-level signal, based on input data DAT21, the output data signal DS21 may be transmitted to the semiconductor memory device400athrough the channel31b, and the receiver47bmay receive the output data signal DS21 to obtain data ODAT21 corresponding to the input data DAT21. The transmitter25cmay generate an output data signal DSN1, which is the PAM-3 multi-level signal, based on input data DATN1, the output data signal DSN1 may be transmitted to the semiconductor memory device400athrough the channel31c, and the receiver47cmay receive the output data signal DSN1 to obtain data ODATN1 corresponding to the input data DATN1. For example, the input data DAT11, DAT21 and DATN1 may write data to be written into the semiconductor memory device400a. FIG.22illustrates an operation of transferring data from the semiconductor memory device400ato the GPU310. For example, the transmitter45amay generate an output data signal DS12, which is the PAM-3 multi-level signal, based on input data DAT12, the output data signal DS12 may be transmitted from the semiconductor memory device400ato the GPU310through the channel31a, and the receiver27amay receive the output data signal DS12 to obtain data ODAT12 corresponding to the input data DAT12. Similarly, the transmitter45bmay generate an output data signal DS22, which is the PAM-3 multi-level signal, based on input data DAT22, the output data signal DS22 may be transmitted to the GPU310through the channel31b, and the receiver27bmay receive the output data signal DS22 to obtain data ODAT22 corresponding to the input data DAT22. The transmitter45cmay generate an output data signal DSN2, which is the PAM-3 multi-level signal, based on input data DATN2, the output data signal DSN2 may be transmitted to GPU310through the channel31c, and the receiver27cmay receive the output data signal DSN2 to obtain data ODATN2 corresponding to the input data DATN2. For example, the input data DAT12, DAT22 and DATN2 may be read data retrieved from the semiconductor memory device400a. FIG.23is a block diagram illustrating an example of the semiconductor memory device included in the memory system ofFIGS.21and22according to some example embodiments. Referring toFIG.23, the semiconductor memory device400amay include a control logic circuit410, an address register420, a bank control logic430, a refresh counter445, a row address multiplexer440, a column address latch450, a row decoder460, a column decoder470, a memory cell array510, a sense amplifier unit485, an I/O gating circuit490, an error correction code (ECC) engine590, an on-die termination (ODT) circuit497and a data I/O buffer495. For example, the semiconductor memory device400amay be a volatile memory device and may include a graphic double data rate 7 GDDR7 synchronous dynamic random access memory (SDRAM) device. The memory cell array510includes first through eighth bank arrays510a-510h. The row decoder460includes first through eighth bank row decoders460a-460hrespectively coupled to the first through eighth bank arrays510a-510h, the column decoder470includes first through eighth bank column decoders470a-470hrespectively coupled to the first through eighth bank arrays510a-510h, and the sense amplifier unit485includes first through eighth bank sense amplifiers485a-485hrespectively coupled to the first through eighth bank arrays510a-510h. The first through eighth bank arrays510a-510h, the first through eighth bank row decoders460a-460h, the first through eighth bank column decoders470a-470hand first through eighth bank sense amplifiers485a-485hmay form first through eighth banks. Each of the first through eighth bank arrays510a-510hmay include a plurality of memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-line BTL. The address register420may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from a memory controller in the GPU310. The address register420may provide the received bank address BANK_ADDR to the bank control logic430, may provide the received row address ROW_ADDR to the row address multiplexer440, and may provide the received column address COL_ADDR to the column address latch450. The bank control logic430may generate bank control signals in response to the bank address BANK_ADDR. One of the first through eighth bank row decoders510a-510hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the first through eighth bank column decoders470a-470hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals. The row address multiplexer440may receive the row address ROW_ADDR from the address register420, and may receive a refresh row address REF_ADDR from the refresh counter445. The row address multiplexer440may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer440is applied to the first through eighth bank row decoders460a-460h. The refresh counter445may sequentially output the refresh row address REF_ADDR under control of the control logic circuit410. The activated one of the first through eighth bank row decoders460a-460h, by the bank control logic430, may decode the row address RA that is output from the row address multiplexer440, and may activate a word-line corresponding to the row address RA. For example, the activated bank row decoder applies a word-line driving voltage to the word-line corresponding to the row address. The column address latch450may receive the column address COL_ADDR from the address register420, and may temporarily store the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch450generates column addresses COL_ADDR′ that increment from the received column address COL_ADDR. The column address latch450may apply the temporarily stored column address COL_ADDR or generated column address COL_ADDR′ to the first through eighth bank column decoders470a-470h. The activated one of the first through eighth bank column decoders470a-470hmay activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit490. The I/O gating circuit490may include a circuitry for gating input/output data, and further includes input data mask logic, read data latches for storing data that is output from the first through eighth bank arrays510a-510h, and write drivers for writing data to the first through eighth bank arrays510a-510h. Codeword CW read from one bank array of the first through eighth bank arrays510a-510hmay be sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and may be stored in the read data latches. The codeword CW stored in the read data latches may be provided to the memory controller via the data I/O buffer495after ECC decoding is performed on the codeword CW by the ECC engine590. The multi-level data MLDAT to be written in one bank array of the first through eighth bank arrays510a-510hmay be provided to the data I/O buffer495from the memory controller, may be provided to the ECC engine590from the data I/O buffer495, the ECC engine590may perform an ECC encoding on multi-level data MLDAT to generate parity bits, the ECC engine590may provide the multi-level data MLDAT and the parity bits to the I/O gating circuit490and the I/O gating circuit490may write the multi-level data MLDAT and the parity bits in a sub-page in one bank array through the write drivers. The data I/O buffer495may provide the multi-level data MLDAT to the ECC engine590in a write operation of the semiconductor memory device400a, and may provide the multi-level data MLDAT from the ECC engine590to the memory controller in a read operation of the semiconductor memory device400a. The ECC engine590may perform an ECC encoding and an ECC decoding on the multi-level data MLDAT according to a control of the control logic circuit410. The control logic circuit410may control operations of the semiconductor memory device400a. For example, the control logic circuit410may generate control signals for the semiconductor memory device400ain order to perform a write operation or a read operation. The control logic circuit410may include a command decoder411that decodes the command CMD received from the memory controller and a mode register412that sets an operation mode of the semiconductor memory device400a. For example, the command decoder411may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The ODT circuit497may be connected to a data I/O pad499and the data I/O buffer495. When the ODT circuit497is enabled, the ODT circuit497may perform ODT operation. When the ODT operation is performed, signal integrity of transmitted/received signal may be enhanced by preventing signal reflection due to impedance matching. Although the semiconductor memory device included in the memory system according to some example embodiments is described based on a DRAM, the semiconductor memory device according to other example embodiments may be any volatile memory device, and/or any nonvolatile memory device, e.g., a flash memory, a phase random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc., but example embodiments are not limited thereto. FIG.24illustrates an example embodiment of the first bank array in the semiconductor memory device ofFIG.23. Referring toFIG.24, the first bank array510amay include a plurality of word-lines WL0-WLm-1 (where m is an even number equal to or greater than two), a plurality of bit-lines BTL0-BTLn-1 (where n is an even number equal to or greater than two), and a plurality of memory cells MCs disposed at intersections between the word-lines WL0-WLm-1 and the bit-lines BTL0-BTLn-1. The bit-lines BTL0-BTLn-1 may extend in a first direction D1 and the word-lines WL-WLm-1 may extend in a second direction D2 crossing the first direction D1. Each of the memory cells MCs includes an access (cell) transistor coupled to one of the word-lines WL0-WLm-1 and one of the bit-lines BTL0-BTLn-1 and a storage (cell) capacitor coupled to the cell transistor. That is, each of the memory cells MCs has a DRAM cell structure. In addition, the memory cells MCs may have different arrangement depending on that the memory cells MCs are coupled to an even word-line (for example, WL0) or an odd word-line (for example, WL1). That is, a bit-line coupled to adjacent memory cells may be different depending on whether a word-line selected by an access address is an even word-line or an odd word-line. However, example embodiments are not limited thereto. The memory cells MCs coupled to the even word-line (for example, WL0) and the odd word-line (for example, WL1) may have the same or substantially the same arrangement. FIG.25is a block diagram illustrating a semiconductor memory device according to some example embodiments. Referring toFIG.25, a semiconductor memory device700may include at least one buffer die710and a plurality of memory dies720-1to720-p(p is a natural number equal to or greater than three) providing a soft error analyzing and correcting function in a stacked chip structure. The plurality of memory dies720-1to720-pare stacked on the buffer die710and convey data through a plurality of through silicon via (TSV) lines. Each of the memory dies720-1to720-pmay include a memory core to store data and a cell core ECC engine722which generates transmission parity bits (e.g., transmission parity data) based on transmission data to be sent to the at least one buffer die710. The cell core721may include a plurality of memory cells having DRAM cell structure. The buffer die710may include a via ECC engine712which corrects a transmission error using the transmission parity bits when a transmission error is detected from the transmission data received through the TSV liens and generates error-corrected data. The buffer die710may further include a receiver713and a transmitter714. The transmitter714may employ the transmitter100ofFIG.2and the receiver713may employ the receiver200ofFIG.12. Therefore, the transmitter714, instead of encoding the first number of binary input bits provided from the via ECC engine712into symbols at one time, divides the first number of binary input into the first bit group including a second number of binary input bits and the second bit group including a third number of binary input bits, generates the first intermediate bit group and the second intermediate bit group by manipulating the first bit group and the second bit group differently according to the value of the first bit group and generates the first symbol group and the second symbol group by encoding the first intermediate bit group and the second intermediate bit group in parallel. Accordingly, the transmitter714may reduce an occupied area and power consumption of an encoder included in the transmitter714. In addition, the receiver713may perform an operation on input data signal from the memory controller, which is opposite to the operation of the transmitter714. The semiconductor memory device700may be a stack chip type memory device or a stacked memory device which conveys data and control signals through the TSV lines. The TSV lines may be also called ‘through electrodes’. The cell core ECC engine722may perform error correction on data which is outputted from the memory die720-pbefore the transmission data is sent. A transmission error which occurs at the transmission data may be due to noise which occurs at the TSV lines. Since data fail due to the noise occurring at the TSV lines may be distinguishable from data fail due to a false operation of the memory die, it may be regarded as soft data fail (or a soft error). The soft data fail may be generated due to transmission fail on a transmission path, and may be detected and remedied by an ECC operation. With the above description, a data TSV line group732which is formed at one memory die720-pmay include TSV lines L1 and L2 to Lp, and a parity TSV line group734may include TSV lines L10 to Lq. The TSV lines L1 and L2 to Lp of the data TSV line group732and the parity TSV lines L10 to Lq of the parity TSV line group734may be connected to micro bumps MCB which are correspondingly formed among the memory dies720-1to720-p. At least one of the memory dies720-1to720-pmay include DRAM cells each including at least one access transistor and one storage capacitor. The semiconductor memory device700may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host through a data bus B10. The buffer die710may be connected with the memory controller through the data bus B10. The cell core ECC engine723may output transmission parity bits as well as the transmission data through the parity TSV line group734and the data TSV line group732respectively. The outputted transmission data may be data which is error-corrected by the cell core ECC engine723. The via ECC engine712may determine whether a transmission error occurs at the transmission data received through the data TSV line group732, based on the transmission parity bits received through the parity TSV line group734. When a transmission error is detected, the via ECC engine712may correct the transmission error on the transmission data using the transmission parity bits. When the transmission error is uncorrectable, the via ECC engine712may output information indicating occurrence of an uncorrectable data error. FIG.26is a diagram illustrating a semiconductor package including the stacked memory device according to some example embodiments. Referring toFIG.26, a semiconductor package900may include one or more stacked memory devices910and a GPU920, and the GPU920includes a memory controller (CONT)925. The stacked memory devices910and the GPU920may be mounted on an interposer930, and the interposer930on which the stacked memory devices910and the GPU920are mounted may be mounted on a package substrate940. The package substrate940may be mounted on solder balls950. The memory controller925may employ the memory controller inFIG.1. Each of the stacked memory devices910may be implemented in various forms, and may be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. Accordingly, each of the stacked memory devices910may include a buffer die and a plurality of memory dies, each of the plurality of memory dies may include a cell core, a cell core ECC engine and the buffer die may include a via ECC engine, a transmitter and a receiver. The plurality of stacked memory devices910may be mounted on the interposer930, and the GPU920may communicate with the plurality of stacked memory devices910. For example, each of the stacked memory devices910and the GPU920may include a physical region, and communication may be performed between the stacked memory devices910and the GPU920through the physical regions. The inventive concepts may be applied to various electronic devices and systems that include the memory devices and the memory systems. For example, the inventive concepts may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc., but example embodiments are not limited thereto. It will be understood that elements and/or properties thereof described herein as being “substantially” the same and/or identical encompasses elements and/or properties thereof that have a relative difference in magnitude that is equal to or less than 10%. Further, regardless of whether elements and/or properties thereof are modified as “substantially,” it will be understood that these elements and/or properties thereof should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated elements and/or properties thereof. One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The foregoing is illustrative of some example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts. | 66,208 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.