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11943882 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The descriptions of embodiments below refer to accompanying drawings in order to illustrate certain embodiments which the present application can implement. The directional terms of which the present application mentions, for example, “top,” “bottom,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “inside,” “outside,” “side,” etc., are just refer to directions of the accompanying figures. Therefore, the used directional terms are for illustrating and understanding the present application, but not for limiting the present application. In the figures, units with similar structures are indicated by the same reference numerals. Embodiments the present application provide a display device and a display method. The display device includes a display mechanism and a motion mechanism. The display mechanism includes a plurality of first display groups, a plurality of second display groups, and a plurality of third display groups arranged along a first direction, and The motion mechanism is respectively connected to the first display groups, the second display groups, and the third display groups, and is configured to be able to guide the first display groups, the second display groups, the third display groups to move along the first direction. In the embodiments of the present application, by disposing the motion mechanism in the display device, and by configuring the motion mechanism to be able to guide each of the display groups in the display mechanism to move, extension of the display region is realized, and there is no superimposed region of the screen when the display device has a relative small display region, thereby avoiding increment of a thickness. The display device provided by the present application is described in detail below in combined with specific embodiments. Please refer toFIG.1toFIG.3.FIG.1is a structural schematic diagram of a display device provided by one embodiment of the present application.FIG.2is a schematic diagram of a display region of the display device provided by one embodiment of the present application in a contraction state.FIG.3is a schematic diagram of the display region of the display device provided by one embodiment of the present application in an extension state. The display device includes a middle display region A1and an extension display region A2defined side by side and along a first direction with the middle display region A1. Wherein, the first direction refers to a direction from the middle display region A1to the extension display region A2. The display device has a first display mode and a second display mode. The first display mode corresponds to a display mode that the display device is in a complete contraction state. The second display mode corresponds to a display mode that the display device is in an extension state. In the complete contraction state, the display region of the display device concentrates in the middle display region A1, i.e., only the middle display region A1serves a display function, and the extension display region A2does not serve the display function. In the extension state, the middle display region A1and at least part of the extension display region A2of the display device serve the display function, thereby realizing extension of the display region and performing a larger display screen. Optionally, the extension display region A2is located on a side of the middle display region A1. When the display device is changed from the contraction state to the extension state, the display region of the display device extend from the middle display region A1to the extension display region A2of one side of the display device. When the display device is in a complete extension state, the display region of the display device covers all the middle display region A1and all the extension display region A2. Optionally, the extension display region A2includes two sections located on two opposite sides of the middle display region A1. When the display device is changed from the contraction state to the extension state, the display region of the display device extend from the middle display region A1to the extension display region A2of two sides of the display device. When the display device is in the complete extension state, the display region of the display device covers all the middle display region A1and all the extension display region A2. Please further refer toFIG.4andFIG.5.FIG.4is a schematic diagram of a display mechanism of the display device provided by one embodiment of the present application in a contraction state.FIG.5is a schematic diagram of the display mechanism of the display device provided by one embodiment of the present application in an extension state. The display device10includes a control mechanism10. The display mechanism10includes a plurality of first display groups101, a plurality of second display groups102, and a plurality of third display groups103arranged along a first direction. The first display groups101, the second display groups102, and the third display groups103are sequentially arranged along the first direction, and one of the second display groups103and one of the third display groups102are arranged between every two adjacent first display groups101. The first display groups101include a plurality of first light-emitting elements L1arranged along a second direction. The second display groups102include a plurality of second light-emitting elements L2arranged along the second direction. The third display groups103include a plurality of third light-emitting elements L3arranged along the second direction. The first direction and the second direction can be two directions which are perpendicular to each other. The plurality of first light-emitting elements L1located in one same first display group101emit light simultaneously or can also emit light independently. Each of the first light-emitting elements L1is controlled by an independent light-emitting control unit. The plurality of second light-emitting elements L2located in one same second display group102can emit light simultaneously or can also emit light independently. Each of the second light-emitting elements L2is controlled by the independent light-emitting control unit. The plurality of third light-emitting elements L3located in one same third display group103emit light simultaneously or can also emit light independently. Each of the third light-emitting elements L3is controlled by the independent light-emitting control unit. Optionally, the first light-emitting elements L2include red diodes, the second light-emitting elements L2include green diodes, and the third light-emitting elements L3include blue diodes. Wherein, the red diodes, the green diodes, and the blue diodes can all be micro light-emitting diodes. When the display mechanism10is manufactured, the mass transfer technology for the micro light-emitting diodes can be used to complete manufacturing of the first display groups101, the second display groups102, and the third display groups103. In the first display mode, i.e., when the display device is in the complete contraction state, the first display groups101, the second display groups102, and the third display groups103are all located in the middle display region A1, and distances between the first display groups101, the second display groups102, and the third display groups103are the smallest. At this time, a display area of the display device is the smallest, but a pixel density in the display area is the highest, and a resolution of a display screen is the highest. In the second display mode, i.e., when the display device is in an extension display state, the first display groups101, the distances between the first display groups101, the second display groups102, and the third display groups103are enlarged. Therefore, a part of the first display groups101, a part of the second display groups102, and a part of the third display group103are allowed to enter the extension display region A2. At this time, the display area of the display device is increased, which realizes the extension of the display screen. Meanwhile, the pixel density in the display area is reduced, and the resolution of the display screen is also reduced. In this embodiment, by controlling motion of each display group in the display mechanism, the extension and contraction of the display area is realized. Unlike a solution that the display region changed through folding and unfolding of a screen realized in the foldable display device, this embodiment can prevent increment of thickness of the display device. Please refer toFIG.1toFIG.6.FIG.6is a first principle diagram of the display device provided by one embodiment of the present application. In this embodiment, the display device further includes a motion mechanism20connected to the display mechanism10and the control mechanism30configured to control the motion mechanism20to move. Wherein, the motion mechanism20is connected to the first display groups101and is configured to guide the first display groups101to move along the first direction; the motion mechanism20is connected to the second display groups102and is configured to guide the second display groups102to move along the first direction; and the motion mechanism20is connected to the third display groups103and is configured to guide the third display groups103to move along the first direction. By guiding the first display groups101, the second display groups102, and the third display groups103to move by the motion mechanism20, extension and contraction of the display region are realized. Specifically, the motion mechanism20includes skid rails extended along the first direction. The skid rails cross the middle display region A1and the extension display region A2. The first display groups101, the second display groups102, and the third display groups103can slide along the skid rails. The skid rails include magnetic wheel201respectively connected to the first display groups101, the second display groups102, and the third display groups103, and magnetic rails202movably connected to the magnetic wheels201. The magnetic wheels201and the magnetic rails202are respectively electrically connected to the control mechanism30. Under control of the control mechanism30, the magnetic rail202and the magnetic wheel201respectively generate magnetic fields with specific intensities and specific directions. Under interaction between the magnetic fields of the magnetic wheels201and the magnetic rails202, the magnetic wheels201guide the first display groups101, the second display groups102, and the third display groups103to move to realize extension and contraction of the display region. Optionally, the magnetic wheel201and the magnetic rail202can be respectively disposed on two opposite sides of the display mechanism10, thereby simultaneously guiding the display mechanism10to move from the two sides. Wherein, the control mechanism30controls the motion mechanism20to move by receiving a display extension instruction or a display contraction instruction. The display extension instruction and the display contraction instruction can be instructions inputted to the display device through an input device, or can be the instructions generated from the display device itself by calculating size parameters, resolution parameters, and other data of a screen to be displayed. Please refer toFIG.1toFIG.5, andFIG.7.FIG.7is a second principle diagram of the display device provided by one embodiment of the present application. In this embodiment, the display device further includes a motion mechanism20connected to the display mechanism10and the control mechanism30configured to control the motion mechanism20to move. The motion mechanism20is connected to the first display groups101and is configured to guide the first display groups101to move along the first direction; the motion mechanism20is connected to the second display groups102and is configured to guide the second display groups102to move along the first direction; and the motion mechanism20is connected to the third display groups103and is configured to guide the third display groups103to move along the first direction. By guiding the first display groups101, the second display groups102, and the third display groups103to move by the motion mechanism20, extension and contraction of the display region are realized. Wherein, the first display groups101, the second display groups102, and the third display groups103are sequentially arranged along the first direction. The motion mechanism20includes first telescopic elements20adisposed between the first display groups101and the second display groups102, second telescopic elements20bdisposed between the second display groups102and the third display groups103, and third telescopic elements20cdisposed between the third display groups103and the first display groups101. The first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20ccan be a same type of telescopic elements, or can be different types of telescopic elements. The motion mechanism20further includes motion rails203. When the first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20care performed in extension and contraction motions, the first display groups101, the second display groups102, and the third display groups103are pushed by the telescopic elements to move along the motion rails203, thereby realizing extension and contraction of the display region. Optionally, the first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20ccan be respectively disposed on two opposite sides of the display mechanism10, thereby simultaneously guiding the display mechanism10to move from the two sides. The control mechanism30controls the motion mechanism20to move by receiving a display extension instruction or a display contraction instruction. The display extension instruction and the display contraction instruction can be instructions inputted to the display device through input equipment, or can be the instructions generated from the display device itself by calculating size parameters, resolution parameters, and other data of a screen to be displayed. In summary, the display device provided by the embodiments of the present application includes the display mechanism and the motion mechanism. The display mechanism includes the plurality of first display groups, the plurality of second display groups, and the plurality of third display groups arranged along the first direction. The motion mechanism is respectively connected to the first display groups, the second display groups, and the third display groups. The motion mechanism is configured to guide the first display groups, the second display groups, the third display groups to move along the first direction. In the embodiments of the present application, by disposing the motion mechanism in the display device, and by configuring the motion mechanism to be able to guide each of the display groups in the display mechanism to move, extension and contraction of the display region is realized, and there is no superimposed region of the screen when the display device has a relative small display region, thereby avoiding increment of thickness. Embodiments of the present application further provides a display method. The display method is applied in a display device. The display device is the display device provided by the aforesaid embodiments of the present application. Please refer toFIG.1toFIG.7. The display device includes a display mechanism10and a motion mechanism20. The display mechanism10includes a plurality of first display groups101, a plurality of second display groups102, and a plurality of third display groups103arranged along a first direction. The display device includes a middle display region A1and an extension display region A2. The first display groups101include a plurality of first light-emitting elements L1arranged along a second direction. The second display groups102include a plurality of second light-emitting elements L2arranged along the second direction. The third display groups103include a plurality of third light-emitting elements L3arranged along the second direction. The first direction and the second direction can be two directions which are perpendicular to each other. The plurality of first light-emitting elements L1located in one same first display group101can emit light independently. The plurality of second light-emitting elements L2located in one same second display group102can emit light independently. The plurality of third light-emitting elements L3located in one same third display group103can emit light independently. The motion mechanism20is respectively connected to the first display groups101, the second display groups102, and the third display groups103, and is configured to guide the first display groups101, the second display groups102, the third display groups103to move along the first direction. Optionally, the motion mechanism20can refer toFIG.6. The motion mechanism20includes magnetic wheels201respectively connected to the first display groups101, the second display groups102, and the third display groups103, and magnetic rails202movably connected to the magnetic wheels201. Under interaction between the magnetic fields of the magnetic wheels201and the magnetic rails202, the magnetic wheels201guide the first display groups101, the second display groups102, and the third display groups103to move. Optionally, the motion mechanism20can further refer toFIG.7. The motion mechanism20includes first telescopic elements20adisposed between the first display groups101and the second display groups102, second telescopic elements20bdisposed between the second display groups102and the third display groups103, third telescopic elements20cdisposed between the third display groups103and the first display groups101, and motion rails203. When the first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20care performed in extension and contraction motions, the first display groups101, the second display groups102, and the third display groups103are pushed by the telescopic elements to move along the motion rails203. On the basis of the aforesaid display device, the display method provided by one embodiment of the present application includes following steps. Step101: obtaining a display extension instruction. The display extension instruction can be an instruction inputted to the display device through input equipment, or can be the instructions generated from the display device itself by calculating size parameters, resolution parameters, and other data of a screen to be displayed. The display extension instruction can include a range of a size of extension of the display region, for example, an extension region completely covers the extension display region A2, or partially covers the extension display region A2. Step102: controlling the motion mechanism20to guide the first display groups101, the second display groups102, and the third display groups103to extend to the extension display region A2according to the display extension instruction. Optionally, the magnetic wheels201and the magnetic rails202of the motion mechanism20are controlled to generate magnetic fields respectively according to the display extension instruction. Under interaction between the magnetic fields of the magnetic wheels201and the magnetic rails202, the magnetic wheels201guide the first display groups101, the second display groups102, and the third display groups103to move to the extension display region A2to realize extension of the display region. Optionally, the first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20cof the motion mechanism20are controlled to extend to drive the first display groups101, the second display groups102, and the third display groups103to move to the extension display region A2along the motion rails203according to the display extension instruction, thereby realizing extension of the display region. Furthermore, the display method provided by this embodiment further includes following step: obtaining a display contraction instruction; and controlling the motion mechanism20to guide the first display groups101, the second display groups102, and the third display groups103to contract to the middle display region A1according to the display contraction instruction. Specifically, the display contraction instruction can be an instruction inputted to the display device through input equipment, or can be the instructions generated from the display device itself by calculating size parameters, resolution parameters, and other data of a screen to be displayed. The display contraction instruction can include a range of a size of contraction of the display region, for example, the display region is completely contracted to the middle display region A1. The magnetic wheels201and the magnetic rails202of the motion mechanism20are controlled to generate magnetic fields respectively according to the display contraction instruction. Under interaction between the magnetic fields of the magnetic wheels201and the magnetic rails202, the magnetic wheels201guide the first display groups101, the second display groups102, and the third display groups103to move to the middle display region A1to realize contraction of the display region. Or, the first telescopic elements20a, the second telescopic elements20b, and the third telescopic elements20cof the motion mechanism20are controlled to contract to drive the first display groups101, the second display groups102, and the third display groups103to move to the middle display region A1along the motion rails203according to the display contraction instruction, thereby realizing contraction of the display region. In summary, the display method provided by this embodiment realizes the extension and contraction of the display region by controlling the motion mechanism to drive each display group of the display mechanism to move in a specific direction. The display method is different from a method of changing the display region by folding and unfolding a screen. This embodiment can avoid increment of thickness of the display device when the display region is contracted. It should be noted that although the present application has disclosed the specific embodiments as above, the above-mentioned embodiments are not to limit to the present application. A person skilled in the art can make any change and modification; therefore, the scope of protection of the present application is subject to the scope defined by the claims. | 22,904 |
11943883 | DETAILED DESCRIPTION The use of hinge systems to provide the necessary rotatable movement of component parts of devices is well known in the art. However, many of these hinge systems are complex, require the use of springs, a ratchet and pawl mechanism, or the like, and generally require multiple associated components. In time, such hinge systems become worn down and components of such hinge systems fail. Thus, there is a need for improved hinge systems for consumer products and the like. To address these shortcomings, an improved hinge system can be integrated within the housing of a device, such as an electronic charging case. In accordance with aspects of the disclosure, the improved hinge system can implement a magnetic bistable hinge system that will allow for rotation of the lid of an electronic charging case about an axis, as well as control movement of the lid about the axis. For example, such magnetic bistable hinge mechanism will enable the lid to move from a first closed position to a bistable open position, as well as a fully open position. The ease with which a user can open and close the lid greatly improves the user experience, as well as improves the overall reliability and durability of both the product and the hinge system. It additionally helps to provide greater control for the opening and closing of the lid. According to aspects of the disclosure, a device incorporating a magnetic bistable hinge system can include a computer, an electric charging case, a tablet and the like. For ease of discussion, a magnetic bistable hinge system will be discussed in the context of an electric charging case, but it is to be appreciated that the bistable hinge system disclosed herein may be used in a wide variety of applications, devices, and larger systems. The electric charging case may include a primary housing and a lid. Implementing an example magnetic bistable hinge system within charging case can allow for the lid to freely move from a closed position to a set bistable open position, as well as into a fully open or extended position. An example magnetic bistable hinge system can further include a first rotatable assembly plate that is coupled to the lid of a charging case. The first rotatable plate may rotate about the axis of a pin attached to a hinge bracket. A first magnet may be positioned within the first plate. A second magnet may be spaced away a predetermined distance from the first magnet and positioned within a housing that separates the first and second magnets. When the lid is in the closed position, the first magnet and second magnet may be positioned so that the south pole of the first magnet indirectly faces the south pole of the second magnet. This causes the first and second magnets to repel one another and create a downward force on the hinge to secure the hinge in the closed position. When a user opens the lid, the magnets repel each other at the bistable point causing the hinge to flip open. In the bistable position, the south pole of the first magnet and the south pole of the second magnet directly face one another. Due to the positioning of the first and second magnets relative to one another, the rotatable plate and lid directly open to the bistable position from the close position. When a user desires to open the lid all of the way, the user can apply a force that overcomes the polarity of the magnets, and allows the lid to remain open and fully extended. A control system can determine the position of the lid of the charging device. For example, the control system may be able to detect the position of the second magnet, which will indicate the position of the lid. The position of the lid can be a first closed position or an open position (either bistable open position or otherwise). At least one position sensor can be implemented within the charging device to determine the magnitude or magnetic field generated by the hinge magnet, as it rotates about the hinge bracket and causes rotation of the rotatable assembly plate and lid. An example sensor can be a hall effect sensor. Example Magnetic Bistable Hinge System for Example Charging Case FIG.1is an example40of a charging case50according to aspects of the disclosure andFIG.2is a cross-sectional view of charging case50showing an example magnetic bistable hinge system100. As shown, charging case50includes an elongated main body52and lid54that are rotatably connected to one another. A lower interior housing56may be seated within a cavity60of the main body52of charging case50. An upper interior housing57is seated within a cavity62of the lid54of charging case50. The top surface59upper interior surface59of the lid54is shown directly adjacent the top surfaces58of the interior housing57of the main body52when the lid54is closed. Referring toFIG.3, another cross sectional view, the interior housing56includes recesses64A and64B that can be used to receive and charge an electronic device or accessory, such as wireless earbuds208(FIG.11) or the like. The main body52and lid54are shown as having a rounded profile, but in other examples, the main body52and lid54can take on a variety of different shapes and sizes. A magnetic bistable hinge system100may be utilized within various devices to allow for movement of components of the device. In one example, magnetic bistable hinge system100may be implemented within example charging case50, to allow for movement of the lid54about the main body52. As shown inFIG.2, magnetic bistable hinge system100can include a hinge subassembly104and a system magnet106. System magnet106may be positioned within the interior housing56of the main body52. A system magnet housing108can be used to retain system magnet106within the interior of charging case50and in close proximity to the hinge subassembly104. As shown, system magnet106is positioned at an angle relative to a vertical axis V-V that extends through a length of charging case50. In one example, the magnet is offset by an angle A, which is a pre-determined angle or number of degrees from vertical axis V-V, such as at least 20 degrees. But, in other examples, the magnet may be offset by greater than or less than 20 degrees or there may be no offset at all. Similarly, the degree of offset may range between 15-45 degrees. System magnet106is shown oriented so that north pole112faces toward the front of charging case50and its south pole114faces toward the back of charging case50and toward hinge subassembly104. In one example, as shown inFIG.3, system magnet106may be secured between the recesses64A and64B of charging case50. System magnet106may be shaped like a house with a rectangular lower portion and a sloped and triangular-shaped upper portion. This is in part due to the shape of the space created between the recesses64A,64B. But, in other examples, the shape and size of the magnet may differ. Further, the system magnet may be formed from two or more smaller magnets that may be joined together or spaced apart from one another. Due to its location and size, system magnet106can serve a dual purpose and also secure any electronic devices that may be positioned within the respective recesses64A and64B. For example, ear buds (not shown) may be secured by the system magnet106within the charging case50. FIGS.4and5illustrate an example hinge subassembly104of the magnetic bistable hinge system100. The hinge subassembly104may include a hinge bracket116and a rotatable assembly plate118fixed to the hinge bracket116by a pin120. The hinge bracket116may be coupled to a rear portion of the main body using known methods. The hinge bracket116can be used to secure the rotatable assembly plate118in place, as well as limit and guide rotational movement of the assembly plate118. The assembly plate118may extend between the main body52and lid54of charging case to couple these two components together. The assembly plate118includes an elongated body that extends within and couples to the lid54. Movement of the assembly plate118can cause lid54to move from a closed position to a bistable open position, as discussed further below. The base122of assembly plate118may include a recess124(FIG.5) for receiving a hinge magnet126. Hinge magnet126may be positioned within the assembly plate118, such that when assembly plate118rotates, hinge magnet126rotates with the assembly plate118about the axis A of pin120. As shown inFIG.6, the north pole128of hinge magnet126faces toward the top of charging case50and the south pole130of the hinge magnet126faces toward the bottom of charging case50. Similarly, the assembly plate includes a first end facing toward the system magnet106and an opposed second end facing away or positioned further away from system magnet106. Hinge magnet126may be positioned at the first end of assembly plate118, such that movement of the magnet causes the opposed second end to rotate from the first bistable or closed position to a second bistable or open position, as discussed more fully below. The assembly plate118and hinge bracket116may be comprised of a ferromagnetic material, such as iron or iron alloys, to enhance the magnetic features of the hinge subassembly104and to allow for attraction of these components to the system magnet106. In other examples, the assembly plate118and hinge bracket116may be comprised of different materials, such as steel, other metals, or non-metals. Alternatively, only one of the assembly plate118and hinge bracket may be comprised of a ferromagnetic material. With reference back toFIG.2, system magnet106and the hinge magnet126may differ in size and magnitude. As shown, system magnet106may be significantly larger in size than hinge magnet126. This allows for system magnet106to create a large magnetic field. System magnet106may have a magnitude of strength greater than the magnitude of strength relative to the rotatable magnet126. By way of example only system magnet106may have a magnitude of 384 G and hinge magnet126may have a magnitude of 52 G. In other examples, the magnitude of the system magnet106may be greater or less than 384 G. Similarly, hinge magnet126may have a magnitude less than or greater than 52 G. In this regard, the magnitude, shape and sizes of the magnets may be different. For example, a smaller system magnet106may be utilized that has a significantly greater magnitude than the hinge magnet and can achieve the same results as disclosed herein. In still another example, the size of the magnets may be the same. When lid54is in the closed position, hinge magnet126is spaced apart from system magnet106by a predetermined distance such as, for example, 0.1 inches. In other examples, the system magnet106may be positioned within a range of predetermined distances away from hinge magnet126, such as between 0.01 to 0.30 inches. But, in still other examples, the hinge may be at a distance less than 0.01 inches or greater than 0.30 inches. Housing wall140may be positioned between system magnet106and hinge magnet126. In one example, housing wall140includes an angled wall surface142that abuts the housing108of system magnet106. The angled wall surface142may have a same angle relative to vertical axis V-V, as system magnet106can help to secure system magnet106at the desired angle. In an example where the system magnet may not be positioned at a fixed angle, the housing wall may be a continuously planar wall. FIG.6is an enlarged cross-sectional schematic view showing components of the bistable hinge system100in the closed position and removed from the remainder of the charging case for ease of discussion. As shown, south pole130of hinge magnet126is positioned toward a top portion or an upper end110of system magnet106. South pole114of hinge magnet126faces toward the south pole114of hinge magnet126, such that south pole130of hinge magnet126is positioned at an angle to the south pole114of system magnet106. The south pole130of hinge magnet126does not extend parallel to the south pole144of system magnet106. In this regard, the south pole130indirectly faces the south pole114of system magnet106. In an alternative embodiment, the north poles may instead be oriented to indirectly face each other and repel one another to achieve the same or similar effect discussed herein. The system magnet106and hinge magnet126cause the lid54to remain closed. As shown, the south pole114of system magnet106repels south pole130of hinge magnet126and creates a downward or pre-loaded force F1on the hinge subassembly104and the rotatable assembly plate118. The downward force F1causes rotatable plate118to be rotated towards hinge bracket116. Interior surface132of the rotatable assembly plate118abuts an outer surface134of hinge bracket116, such that outer surface134stops assembly plate118from further rotating about pin120. The downward force F1causes the lid to remain closed. It is to be appreciated that in other examples, the north poles of the hinge magnet126and the system magnet106may instead be oriented toward and repel one another. Turning toFIG.7, the lid54is shown in an open and bistable position150. When an opening force F2is applied to the lid54and hinge subassembly104that overcomes the pre-loaded force F1, the lid automatically opens to a bistable position150. It does not open to an intermediate position between the bistable position150and the closed position.FIG.8shows an enlarged and schematic view of the bistable hinge system100in the bistable position150. The bistable point occurs where the south pole130of the hinge magnet126directly faces the south pole114of the system magnet106. In this example, the south pole130of the hinge magnet126directly faces the top portion110of the system magnet106. The south pole130of hinge magnet126and the south pole114of the system magnet106repel each other at the bistable point, which causes the assembly plate118and lid54(FIG.2) to rotate about the pin120and flip open to the bistable point. In the bistable open position150, as also shown inFIG.8, the lower interior surface133can abut the lower outer surface135of the hinge bracket116. Further, the hinge magnet126may be rotated from the first bistable position into the second bistable open position150by moving at least approximately 20 degrees. In other examples, rotation can occur by moving the hinge magnet greater than or less than 20 degrees. Use of the system and hinge magnets106,126allows for minimal friction within the bistable hinge system100. The system and hinge magnets106,126eliminate the need for additional components in the hinge system, such as springs, pawl and ratchet, and the like, to achieve movement of the lid54. The only friction occurs between assembly plate118and pin120, as assembly plate118rotates about pin120. The reduced friction in the bistable hinge system100further prevents lid54from being placed or stuck in an intermediate position between the bistable position150and the closed position. This allows for smooth movement of the lid54from the closed to bistable open position150and vice versa, which enhances the user experience. FIG.9shows the lid54in a fully open and extended position152. In the extended position, the assembly plate118rotates around the pin120until south pole130of the hinge magnet126faces away from the south pole114of the system magnet106and breaks the magnetic field. A stopping surface144on the hinge bracket116prevents over rotation of the assembly plate118and retains the lid54in a fixed fully open and extended position. In this example, cover54of charging case50is capable of moving from a first bistable position, i.e., a closed position, to a second bistable position, i.e., an open position. In the first bistable position, the south pole130of hinge magnet126can be at a first angle relative to system magnet106. (FIG.6) For example, south pole30of hinge magnet126will indirectly face toward south pole114of system magnet106. In the second bistable position, south pole130of hinge magnet126will be at a second angle relative to system magnet106. (FIG.8.) The south pole130of hinge magnet126will more directly face toward south pole114of system magnet106, such that south pole130and south pole114are almost parallel to one another. Finally, to disengage the magnets and completely open the cover56, south pole130of hinge magnet126can be moved to a third angle relative to system magnet, in which the magnets no longer repel one another and the lid is in a fully open position. (FIG.9.) In such position, the south pole30of hinge magnet126may extend in a direction that is almost perpendicular to system magnet106. In other example embodiments, the first bistable (closed) and second bistable (open) positions can be still be achieved and/or modified by modifying features of one or both of the system and hinge magnets106,126. For example, the position and amount of space between the retention and hinge magnets106,126relative to one another, the magnitude of the retention and hinge magnets106,126, and the size of the retention and hinge magnets106,126each play a role in achieving the first and second bistable positions. Modifying any one of these features and/or the housing containing the magnets can affect the resulting bistable positions. In this regard, it is to be appreciated that while only one structural configuration showing the system magnet106and hinge magnet126is shown, many variations are possible. Further, while the hinge magnet is shown in the context of a charging case assembly, the hinge system can be implemented within other devices or structures that move between first and second positions, such as cases for other devices such as eyeglasses. Example Position Detecting and Notification Systems The magnetic bistable hinge system may communicate with other systems positioned within or in communication with the charging device. Examples of such systems may include a position detection system240and a notification system236(SeeFIG.11). But, numerous other systems may be implemented in connection with the position of the hinge, and in particular examples, the position of the hinge magnet126. An example position detecting system can be implemented within the charging case40to indicate the position of the hinge magnet126. In one example, the position detecting system can detect the magnitude and strength of the hinge magnet126as it rotates bout the hinge bracket. An example notification system can be implemented to notify another system or a user about the position of the hinge magnet126, rotatable member, and/or the lid54. In one example, the notification system notifies a user as to whether the lid of the charging device is in an open position or a closed position. For example, as shown in the perspective view ofFIG.10, where the case is in the fully extended position, the charging case may include a light204, such as an LED. (SeeFIGS.10-11.) When the case is in the open position, a light, a certain color of light, a pattern of blinking lights or the like can be emitted to provide a visual notification to a user that the case remains open. In one example, the LED may be a blinking red light to indicate that the case is in an open position. In other examples, different types of visual notification may be provided to a user such as on a graphical user interface. In still other examples, the notification system communicates with another system of the charging device to initiate or commence another action. Control System for Charging Case The charging case may also include a control system that can determine whether the lid of the charging case is in an open position or closed position, based on the information received from the position detection system240. In some examples, when the lid is determined to be in an open or closed position, the control system may provide instructions to another system communicating with the charging case to perform a specific function, such as notify a user that the lid is open or initiate charging of a device within the charging case. The control system may include one or more processors which process information in order to control aspects of the charging case. FIG.12illustrates an example200of a computing device or control system for an electronic device, such as the charging case50shown inFIGS.1-9. The computing device210may contain one or more processors, memory, and other components generally found in general purpose computing devices. As shown inFIG.12, the charging case may have one or more computing devices, such as computing device210containing one or more processors220, memory230, data232, instructions234and other components typically present in general purpose computing devices. The memory230can store information accessible by the one or more processors220, including data232and instructions234that may be executed or otherwise used by the processor220. The memory230may be of any type capable of storing information accessible by the processor, including a computing device-readable medium, or other medium that stores data that may be read with the aid of an electronic device, such as a hard-drive, memory card, ROM, RAM, DVD or other optical disks, as well as other write-capable and read-only memories. Systems and methods may include different combinations of the foregoing, whereby different portions of the instructions and data are stored on different types of media. The instructions234may be any set of instructions to be executed directly (such as machine code) or indirectly (such as scripts) by the processor. For example, the instructions may be stored as computing device code on the computing device-readable medium. In that regard, the terms “instructions” and “programs” may be used interchangeably herein. The instructions may be stored in object code format for direct processing by the processor, or in any other computing device language including scripts or collections of independent source code modules that are interpreted on demand or compiled in advance. Functions, methods and routines of the instructions are explained in more detail below. The data232may be retrieved, stored or modified by processor220in accordance with the instructions234. For instance, although the claimed subject matter is not limited by any particular data structure, the data may be stored in computing device registers, in a relational database as a table having a plurality of different fields and records, XML documents or flat files. The data may also be formatted in any computing device-readable format. The one or more processors220may be any conventional processors, such as commercially available CPUs. Alternatively, the one or more processors may be a dedicated device such as an ASIC or other hardware-based processor. AlthoughFIG.12functionally illustrates the processor, memory, and other elements of computing device210as being within the same block, it will be understood by those of ordinary skill in the art that the processor, computing device, or memory may actually include multiple processors, computing devices, or memories that may or may not be stored within the same physical housing. For example, memory may be a hard drive or other storage media located in a housing different from that of computing device210. Accordingly, references to a processor or computing device will be understood to include references to a collection of processors or computing devices or memories that may or may not operate in parallel. In one example, computing device210may be a control system incorporated into the charging case. The control system may be capable of communicating with various systems communicating with the charging case200, such as position detection system240, which can detect the position of the magnet; or notification system236for notifying a user that the lid of the charging case remains open. Control system210may receive signals from other systems in the charging device indicating that the lid of the charging case is in an open or closed position. In such example, such as if the charging case is in the closed position, control system210may initiate activity by systems, such as instructing the notification system to notify a user that the lid of the charging case is open. Again, although the notification systems236are shown as part of computing device210, in actuality, the position detection system240may be a separate system in communication with control system210. With reference toFIGS.6and12, when the control system210receives a message from the position detection system240, the control system can determine the position of the hinge magnet126and thereby the lid54. When the control system determines the hinge magnet126is in the first closed position, control system210can send instructions to the notification system236that the lid is fully closed and a notification to the user does not need to be provided. Conversely, when the control system210receives a message from the position detection system240that the hinge magnet126and thereby the lid54are in the second open position, control system210can send instructions to the notification system236that the lid is in an open position, control system210can send instructions to the notification system236that the lid is fully open and a notification to the user can be sent. The position of the hinge magnet can be determined by the control system. For example, as the hinge magnet126rotates about the hinge bracket116, one or more position sensors within the control system can be used to determine the position of the hinge magnet126. For instance, referring toFIGS.6and8, a position sensor202may be a hall sensor that is positioned within the charging device50. In this example, position sensor202may be fixed to or formed within the magnet housing108of system magnet106. Position sensor202can detect the magnetic field of the hinge magnet126, as it rotates about the axis of the hinge bracket116. As noted above, the hinge magnet126may be positioned at a base of the rotating assembly plate118. In one example, the hinge magnet126can detect either the hinge magnitude or a change in magnitude as it rotates around the hinge bracket. Position sensor202may communicate with control system210to indicate the position of the hinge magnet126. For example, when hinge magnet126is in a first closed position, where hinge magnet126indirectly faces system magnet106and the system magnet housing108, position sensor202can send a signal to control system210indicating the magnitude of hinge magnet126. In this example, detection of the position of the hinge magnet126can also indicate the position of the lid54of the charging case50. Based on the information received from the position sensor202, control system210can determine the position of the hinge magnet126, and whether the hinge magnet is in the closed position or whether the hinge magnet has moved to an open position. For example, because the position of the position sensor202is fixed, control system210can readily determine the position of the hinge magnet126. In other examples, control system210can determine the exact position of the hinge magnet. For example, multiple hall sensors210may be implemented within the charging case to provide additional information to the control system210so as to know the exact position of the hinge magnet, as opposed to simply whether the magnet is in an open or closed position. For example, the hinge magnet126may be rotated at 20 degrees relative to the position of the hinge magnet126in the closed position, which can be used to indicate at least one bistable open position. FIG.13is an example flow diagram300in accordance with some of the aspects described above that may be performed by one or more computing devices such as control system210. In this example, control system210receives a signal at block310. The signal can indicate the magnitude or magnetic field generated by the hinge magnet126. The control system210may then determine the position of the hinge magnet126, which in turn will determine whether the lid52is in a closed position or an open position. Control system can further determine whether the open position is the bistable position or other open position. At block320, the control system210can determine that the charging case is in the open position. At block330, the control system210can send a signal to a notification system. Thus, the features disclosed herein may provide for a magnetic bistable hinge system that can be implemented within any device or system, such as laptops, charging cases, tablets, accessories and the like. The features disclosed herein may address the shortcomings associated with known hinge systems. Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the bistable hinge system is not limited to use in any one device and may be implemented across many products. The provision of the examples described herein, as well as clauses phrased as “such as,” “including” and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. | 29,587 |
11943884 | DETAILED DESCRIPTION Technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to accompanying drawings. Obviously, the described embodiments are merely some but not all of embodiments of the present disclosure. All other embodiments obtained on a basis of the embodiments of the present disclosure by a person of ordinary skill in the art shall be included in the protection scope of the present disclosure. Unless the context requires otherwise, throughout the description and the claims, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as an open and inclusive meaning, i.e., “including, but not limited to”. In the description of the specification, the terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner. Hereinafter, the terms “first” and “second” are only used for descriptive purposes, and are not to be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined with “first”, “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the term “a/the plurality of” means two or more unless otherwise specified. In the description of some embodiments of the present disclosure, it will be understood that orientations or positional relationships indicated by terms “center”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, etc. are based on orientations or positional relationships shown in the drawings, which are merely to facilitate and simplify the description of the present disclosure, and are not to indicate or imply that the referred apparatuses or elements must have a particular orientation, or must be constructed or operated in a particular orientation. Therefore, they should not be construed as limitations to the present disclosure. In the description of some embodiments, the terms “coupled” and “connected” and their derivatives may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term “coupled” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein. Some embodiments of the present disclosure provide a foldable display terminal. The foldable display terminal is, for example, a mobile phone, a tablet computer, a smart wearable product (a smart watch or a smart bracelet), a personal digital assistant (PDA), or an on-board computer. The embodiments of the present disclosure do not specifically limit a specific form of the foldable display terminal. The foldable display terminal includes a foldable display apparatus and various electronic components, such as a camera, a battery, and a circuit board. In some embodiments, as shown inFIG.2, the foldable display apparatus includes a housing10. The housing10includes a first sub-housing11, a second sub-housing12, and a rotating shaft13located between the first sub-housing11and the second sub-housing12. The first sub-housing11and the second sub-housing12are located on two sides of the rotating shaft13and are rotatably connected through the rotating shaft13. The first sub-housing11and the second sub-housing12may independently rotate around the rotating shaft13to fold and unfold the foldable display apparatus. As shown inFIG.2, the foldable display apparatus further includes a display panel20for display images. In order to enable the display panel20to be folded, the display panel20is a flexible display panel and can be bent. For example, the display panel20may be a flexible organic light-emitting diode (OLED) display panel. As shown inFIG.3, the flexible OLED display panel includes a flexible base200and OLED devices disposed on the flexible base. A material of the flexible base200is, for example, polyimide (PI). That is, a base material of the OLED display panel is a flexible material, and the OLED display panel can be bent. The OLED device may emit light by itself, and there is no need to provide a backlight source in the display apparatus with the OLED display panel. The flexible OLED display panel further includes gate lines provided on the flexible base in a direction, data lines that cross with the gate lines in an insulating manner, and common power lines. The common power lines are usually parallel to the data lines. Herein, a sub-pixel may be defined by gate lines and data lines (and common power lines), which is not limited thereto. The sub-pixel refers to a basic unit for display an image, and the OLED device is located in the sub-pixel, so that the flexible OLED display panel displays an image through a plurality of sub-pixels. The flexible OLED display panel further includes a pixel circuit formed in each sub-pixel. The pixel circuit is electrically connected to the OLED device to drive the OLED device to emit light. The pixel circuit basically includes a switching thin film transistor, a driving thin film transistor, and a capacitor. In an example where an active driving type flexible OLED display panel has one sub-pixel with a 2T1C structure of two thin film transistors (i.e., one switching thin film transistor and one driving thin film transistor representing by “T”), and one capacitor (representing by “C”), the capacitor includes a first electrode plate and a second electrode plate. An interlayer insulating film is provided between the first electrode plate and the second electrode plate as a dielectric. The switching thin film transistor and the driving thin film transistor each include a semiconductor layer, a gate, a source, and a drain. The semiconductor layer of the switching thin film transistor and the semiconductor layer of the driving thin film transistor may be composed of amorphous silicon, single crystal silicon, polycrystalline silicon, or oxide semiconductor. The semiconductor layer of the switching thin film transistor and the semiconductor layer of the driving thin film transistor each include: a channel region that is not doped with an impurity, and a source region and a drain region that are formed by doping the impurity on two sides of the channel region. Herein, the impurity vary with types of thin film transistors, and may be an N-type impurity or P-type impurity. The gate of the switching thin film transistor is connected to a gate line, the source of the switching thin film transistor is connected to a data line, and the drain of the switching thin film transistor is connected to the gate of the driving thin film transistor. The source of the driving thin film transistor is connected to a common power line, and the drain of the driving thin film transistor is connected to a pixel electrode210of the OLED device through a via hole. The first electrode plate of the capacitor is connected to the gate of the driving thin film transistor, and the second electrode plate of the capacitor is connected to the source of the driving thin film transistor. The switching thin film transistor is turned on through a gate voltage applied to the gate line, thereby transmitting a data voltage applied to the data line to the driving thin film transistor. There is a certain difference between a common voltage applied from the common electrode line to the driving thin film transistor and the data voltage transmitted from the switching thin film transistor to the driving thin film transistor. A voltage corresponding to the difference is stored in the capacitor. A current corresponding to the voltage stored in the capacitor flows into the OLED device through the driving thin film transistor, so that the OLED device emits light. As shown inFIG.3, the OLED device includes a pixel electrode210, a light-emitting functional layer220, and a common electrode230. One of the pixel electrode210and the common electrode230is an anode (for supplying holes), and the other is a cathode (for supplying electrons). Electrons and holes are injected from the pixel electrode210and the common electrode230into the light-emitting functional layer220, and when excitons generated by combining the holes and the electrons transition from an excited state to a ground state, light emission is generated.FIG.3merely shows the driving transistor, and does not show the switching transistor. The pixel electrode210may be formed of metal with high reflectivity, and the common electrode230may be formed of a transparent conductive film. In this case, light emitting from the light-emitting functional layer220is reflected by the pixel electrode210and exits to outside through the common electrode230, and thus a top-emission type OLED device is formed. However, it is not limited thereto. In a case where the pixel electrode210is formed of a transparent conductive film and the common electrode230is formed of metal with high reflectivity, a bottom-emission type OLED device may be formed. Of course, in a case where both the pixel electrode210and the common electrode230are formed of a transparent conductive film, a double-sided emission OLED device may be formed. The light-emitting functional layer220may include an organic light-emitting layer223, and in addition, may further include at least one of a hole injection layer (HIL)221, a hole transport layer (HTL)222, an electron transport layer (ETL)224, and an electron injection layer (EIL)225. In a case where the light-emitting functional layer220includes all the above layers, the hole injection layer221, the hole transport layer222, the organic light-emitting layer223, the electron transport layer224, and the electron injection layer225are stacked on top of one another on the pixel electrode210as the anode. It will be noted thatFIG.3shows an example in which hole injection layers221, hole transport layers222, electron transport layers224, and electron injection layers225in different OLED devices are disconnected, but the embodiments of the present disclosure is not limited thereto. In some embodiments, in the different OLED devices, the hole injection layers221may also be connected as a whole, the hole transport layers222may also be connected as a whole, the electron transport layers224may also be connected as a whole, and the electron injection layers225may also be connected as a whole. The light-emitting functional layers220may include red light-emitting functional layers that emit red light, green light-emitting functional layers that emit green light, and blue light-emitting functional layers that emit blue light. The red light-emitting functional layer, the green light-emitting functional layer and the blue light-emitting functional layer respectively form a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B to display a color image. As shown inFIG.2, the display panel20includes a bendable portion23, and a first non-bendable portion21and a second non-bendable portion22respectively located on two sides of the bendable portion23. The first non-bendable portion21is accommodated in the first sub-housing11, and the second non-bendable portion22is accommodated in the second sub-housing12. The bendable portion23corresponds to the rotating shaft13between the first sub-housing11and the second sub-housing12. When the foldable display apparatus is folded from an unfolded state, the display panel20may be bent along the bendable portion23. In this case, a side of the display panel20connected to the housing10is a non-display side of the display panel20, and a side of the display panel20away from the housing10is a display side of the display panel20. In some embodiments, as shown inFIGS.9A and11A, in order to reduce an impact on the display panel20during a process of folding and unfolding the foldable display apparatus, the foldable display apparatus further includes at least one fixing assembly30. In some embodiments, as shown inFIGS.4and5, the fixing assembly30includes a first fixing seat31, a first connecting rod32, a second fixing seat33, and a second connecting rod34. As shown inFIGS.2,4and5, the first fixing seat31is fixed on a side S21of the first non-bendable portion21proximate to the first sub-housing11. One end E32-1of the first connecting rod32is fixedly connected to the first fixing seat31, and the other end E32-2of the first connecting rod32is rotatably connected to the rotating shaft13. For example, as shown inFIGS.4and5, the end E32-2of the first connecting rod32connected to the rotating shaft13is fixedly connected to a shaft sleeve32′. The shaft sleeve32′ is sleeved on the rotating shaft13. The first connecting rod32can rotate around the rotating shaft13through the shaft sleeve32′. In addition, as shown inFIG.4, the second fixing seat33is fixed on a side S322of the second non-bendable portion22proximate to the second sub-housing12. One end E34-1of the second connecting rod34is slidably connected to the second fixing seat33, and the other end E34-2of the second connecting rod34is rotatably connected to the rotating shaft13. For example, in some embodiments, as shown inFIGS.4and5, the end E34-2of the second connecting rod34connected to the rotating shaft13is fixedly connected to another shaft sleeve34′. The rotating shaft sleeve34′ is sleeved on the rotating shaft13. The second connecting rod34can rotate around the rotating shaft13through the shaft sleeve34′. FIGS.4and5show that the end E32-1of the first connecting rod32is fixedly connected to the first fixing seat31, and the end E34-1of the second connecting rod34is slidably connected to the second fixing seat33. However, it can be understood that in some other embodiments, one end of the first connecting rod32may be slidably connected to the first fixing seat31, and one end of the second connecting rod34may be fixedly connected to the second fixing seat33; or, one end of the first connecting rod32is slidably connected to the first fixing seat31, and one end of the second connecting rod34is slidably connected to the second fixing seat33. It will be noted that the first fixing seat31and the second fixing seat33may be fixed to the first non-bendable portion21and the second non-bendable portion22of the display panel20by means of adhesive bonding, respectively, for example, by means of strong double-sided adhesive bonding. The strong double-sided adhesive bonding has the advantages of simple operation, low cost, and good fixing effect. In some embodiments, in order to improve strength of the display panel20, steel sheets are bonded to the side of the display panel20proximate to the housing10. In this case, the first fixing seat31and the second fixing seat33are bonded to a steel sheet on the first non-bendable portion21and a steel sheet on the second non-bendable portion22, respectively. In the fixing assembly30provided by the embodiments of the present disclosure, one end of the second connecting rod34can rotate around the rotating shaft13. In this way, during a process of folding and unfolding the housing10, the second sub-housing12can rotate around the rotating shaft13. As a result, the second non-bendable portion22can also rotate around the rotating shaft13through the second connecting rod34, so that the display panel20can also be fold and unfold. Moreover, the other end of the second connecting rod34is slidably connected to the second fixing seat33. Therefore, during the process of folding and unfolding the housing10, the display panel20may be ensured to bend along the bendable portion23, so as to avoid a large deformation of the display panel20. In addition, the second fixing seat33and the second connecting rod34may also support and fix the second non-bendable portion22so as to keep the second non-bendable portion22stable during a folding and bending process. In other words, the fixing assembly30enables the display panel20to follow movement of the housing10smoothly. In addition, the first connecting rod32can rotate around the rotating shaft13, which will not affect the first non-bendable portion21during the process of rotating the second non-bendable portion22. It will be noted that beneficial effects of slidably connecting one end of the first connecting rod32to the first fixing seat31on the display panel20and the first non-bendable portion21are similar to the above, and will not be repeated here. In some embodiments, in order to enable the second connecting rod34to slide on the second fixing seat33, as shown inFIGS.4and5, the fixing assembly30further includes a sliding frame331. The sliding frame331is disposed on a surface S33of the second fixing seat33proximate to the second sub-housing12. The sliding frame331includes a plurality of sidewalls331a. The plurality of sidewalls331aare connected end to end in sequence to form the sliding frame331with a cavity336. A sliding block341is provided at the end E34-1of the second connecting rod34connected to the second fixing seat33. The sliding block341is disposed in the cavity336. The sliding block341is configured to move in the sliding frame331during a process of rotating the second non-bendable portion22, that is, during a process of the display panel20from a fully unfolded state to a folded state or from a folded state to a fully unfolding state. In some embodiments, the sliding block341is in a shape of a cuboid, or the sliding block341is in a shape of a cylinder. The embodiments of the present disclosure does not limit a specific shape of the sliding block341, as long as the sliding block341may slide stably in the sliding frame331. In addition, in order to enable the sliding block341to move in the sliding frame331, a width of the sliding frame331is greater than a width of the sliding block341in a sliding direction of the sliding block341(i.e., the left-right direction inFIG.4). In order to further enhance structural stability of the fixing assembly30, as shown inFIGS.4and6, magnetic films332are disposed on two sidewalls inside the sliding frame331in the sliding direction of the sliding block341. In this case, a material of the sliding block341may be a material that can be adsorbed by the magnetic films332. For example, the material of the sliding block341may be an iron alloy material, or the sliding block341may be subjected to magnetic treatment, so that the magnetic films332have attraction force on the sliding block341. In this way, when the foldable display apparatus is in a fully unfolded state or folded state, the magnetic films332can generate the attraction force on the sliding block341. As a result, the second connecting rod34connected to the sliding block341has a good stable ability to maintain a current state, and thus stability of the fixing assembly30is maintained. In addition, the sliding block341moves during the folding process, and the attraction force of magnetic films332on the sliding block341generates a damping feeling, which is fed back to an user, thereby improving the user experience. In some embodiments, as shown inFIG.6, the width of the sliding block341in the sliding direction thereof is d1. During the process of rotating the second non-bendable portion22(i.e., during a process of the display panel20from the fully unfolded state to the folded state or from the folded state to the fully unfolded state), a distance that the sliding block341moves in the sliding frame331in the sliding direction thereof is d2. A width of the magnetic film332in the sliding direction of the sliding block341is d3. On this basis, a width of the cavity336in the sliding direction of the sliding block341is d, and d is equal to a sum of d1, d2, and twice d3 (d=d1+d2+2×d3). In this way, when the second non-bendable portion22does not rotate (that is, the display panel20is in the fully unfolded state), as shown inFIG.4, the sliding block341is located at the magnetic film332on a side of the sliding frame331proximate to the rotating shaft13. When the second non-bendable portion22is located at the side S21of the first non-bendable portion21after rotating (that is, the display panel20is in the folded state), as shown inFIG.7, the sliding block341is located at the magnetic film332on a side of the sliding frame331away from the rotating shaft13. In this way, it may be ensured that the display panel is bent along the bendable portion23during the process of folding the display apparatus, so as to avoid large deformation of the display panel. In some embodiments, the magnetic films332may also be omitted. In this case, the width d of the cavity336is equal to a sum of d1 and d2 (d=d1+d2). On this basis, in order to enable the sliding block341to slide stably in the sliding frame331, and to prevent the sliding block341from falling out of the sliding frame331during a sliding process, as shown inFIG.5, an upper portion of the sliding frame331is further provided with an upper cover333. In addition, in order not to hinder a movement of the second connecting rod34in the sliding direction of the sliding block341, as shown inFIG.5, the upper cover333is provided with an opening334. During a movement of the sliding block341in the sliding frame331in the sliding direction of the sliding block341, the second connecting rod34can move in the opening334along the sliding direction of the sliding block341, so as to avoid hindering the folding and unfolding. In an example, when a foldable display terminal is unfolded from a folded state, as shown inFIG.1, a bendable region of the display panel20is prone to bulge. The foldable display apparatus provided by some embodiments of the present disclosure, as shown inFIGS.9A and11A, further includes one or more stretching assemblies01. Stretching assembly(s)01are fixed to the second non-bendable portion22and the second sub-housing12. The stretching assembly(s)01are configured to apply force directed from the first non-bendable portion21to the second non-bendable portion22to the second non-bendable portion22when the second non-bendable portion22rotates toward the first non-bendable portion21to approximately align the second non-bendable portion22with the first non-bendable portion21. In this way, when the foldable display apparatus is unfolded from the folded state, the stretching assembly(s)01apply the force directed from the first non-bendable portion21to the second non-bendable portion22to the second non-bendable portion22. As a result, the second non-bendable portion22moves in a direction away from the first non-bendable portion21, and drives the bendable portion23to move in the direction away from the first non-bendable portion21, and thus the bulge of the bendable portion23is unfolded under the force applied by the stretching assembly(s)01. It will be noted thatFIGS.9A and11Aare illustrated by taking an example in which the stretching assembly(s)01are fixed to the second non-bendable portion22and the second sub-housing12. In some embodiments, other stretching assembly(s)01are disposed on the first non-bendable portion21and the first sub-housing11. The stretching assembly(s)01are configured to apply force directed from the second non-bendable portion22to the first non-bendable portion21to the first non-bendable portion21when the foldable display apparatus is unfolded from the folded state. In a case where the foldable display apparatus includes a plurality of stretching assemblies01, the plurality of stretching assemblies01may all be disposed on the first non-bendable portion21and the first sub-housing11, or may all be disposed on the second non-bendable portion22and the second sub-housing12; or, a part of the plurality of stretching assemblies01are disposed on the first non-bendable portion21and the first sub-housing11, and another part of the plurality of stretching assemblies01are disposed on the second non-bendable portion22and the second sub-housing12. It will be noted that the second non-bendable portion22, the bendable portion23and the first non-bendable portion21moving under the force applied by the stretching assemblies01may mean that these three have obvious position changes, and may also mean deformation of these three. It can be seen from the foregoing that the foldable display apparatus provided by some embodiments of the present disclosure includes the housing10. The housing10fixes and protects the display panel20, and can be folded and unfolded. The foldable display apparatus further includes the fixing assembly30. The fixing assembly30can fix and support the display panel20. Furthermore, the fixing assembly30may ensure that the display panel is bent along the bendable portion23during the process of folding the display apparatus so as to avoid the large deformation of the display panel, and ensure the followability of the display panel20to the movement of the housing10. In addition, the foldable display apparatus further includes the stretching assembly01. The stretching assembly01can apply the force directed from the first non-bendable portion21to the second non-bendable portion22to the second non-bendable portion22when the foldable display apparatus is unfolded from the folded state, so that the second non-bendable portion22drives the bendable portion23to move in the direction away from the first non-bendable portion21, and the bendable portion23is fully unfolded. A specific structure of the stretching assembly01will be described in detail below. In some embodiments, as shown inFIGS.8A-1,8B, and8C, the stretching assembly01includes a spring40. One end E40-1of the spring40is fixed on a side S22of the second non-bendable portion22proximate to the second sub-housing12, and the other end E40-2of the spring40is fixed on a side S12of the second sub-housing12proximate to the second non-bendable portion22. When the foldable display apparatus is in the folded state, the spring40is in a naturally straight state. When the foldable display apparatus is unfolded from the fold state, the end of the spring40fixed to the second sub-housing12moves a certain distance along with the second sub-housing12in a direction perpendicular to the rotating shaft13and toward the second non-bendable portion22(e.g., the X direction inFIG.8A-1). In this case, the display panel20is in a bulged state at the bendable portion23and is not fully unfolded, and the end of the spring40fixed to the second non-bendable portion22does not move in the X direction. In this case, the spring40is in an unnaturally straight state, and applies elastic force to the second non-bendable portion22in the X direction, so that the second non-bendable portion22moves in the X direction, and thus the display panel20is further unfolded. In some embodiments, the fixing assembly may also be omitted. On this basis, when the foldable display apparatus is in the unfolded state, the spring40may be in the naturally straight state. When the foldable display apparatus is in the folded state, it can be seen from a situation shown inFIG.7that the display panel20is located on an outside of the housing10, and the bendable portion23of the display panel20is stretched. Since the bendable portion23is stretched, the bendable portion23applies elastic force to the second non-bendable portion22. As a result, the second non-bendable portion22moves toward the first non-bendable portion21. In this case, the spring40is in the unnaturally straight state. When the foldable display apparatus is unfolded from the folded state, the spring40in the unnaturally straight state returns to its original shape, and thus applies the elastic force to the second non-bendable portion22in the X direction. As a result, the second non-bendable portion22moves in the X direction, the display panel20is unfolded, and the display panel20is prevented from being in the bulged state at the bendable portion23. It will be noted that, as shown inFIG.8B, the end E40-2of the spring40fixed to the second sub-housing12may be located proximate to the rotating shaft13, and the end E40-1of the spring40fixed to the second non-bendable portion22may be located away from the rotating shaft13. Here, the rotating shaft13is represented by the dashed circle inFIG.8B. In this way, when the foldable display apparatus is unfolded, the spring40in a compressed state generates the elastic force. The elastic force pushes the second non-bendable portion22to move in the X direction. Or, as shown inFIG.8C, the end E40-2of the spring40fixed to the second sub-housing12may be located away from the rotating shaft13, and the end E40-1of the spring40fixed to the second non-bendable portion22may be located proximate to the rotating shaft13. Here, the rotating shaft13is represented by the dashed circle inFIG.8C. In this way, when the foldable display apparatus is unfolded, the spring40in a stretched state generates the elastic force. The elastic force pulls the second non-bendable portion22to move in the X direction. For convenience of description, a description may be made below by taking an example in which the end of the spring40fixed to the second sub-housing12is a side of the spring40proximate to the rotating shaft13and the end of the spring40fixed to the second non-bendable portion22is a side of the spring40away from the rotating shaft13. In some embodiments, in order to stabilize the spring40, as shown inFIG.8A-1, the stretching assembly01further includes a first spring fixing support41and a second spring fixing support42. As shown inFIG.8A-2, first spring fixing support41and the second spring fixing support42each include a base401and a sleeve402. One end E402of the sleeve402has an opening Q402. An outer sidewall S402-1of the sleeve402is fixed on the base401. A cross-section of the sleeve402perpendicular to its extension may be in a shape of a rectangle or round, and may be in the shape of the rectangle in order to be easily fixed on the base401. The embodiments of the present disclosure does not limit the shape of the sleeve402, as long as the sleeve402may accommodate the end of the spring40and may be stably fixed on the base401. As shown inFIG.8B, the base401of the first spring fixing support41is fixed on a side S12of the second sub-housing12proximate to the second non-bendable portion22. The base401of the second spring fixing support42is fixed on a side S22of the second non-bendable portion22proximate to the second sub-housing12. The first spring fixing support41and the second spring fixing support42may be fixed to the second sub-housing12and the second non-bendable portion22by means of adhesive bonding, respectively, for example, by means of strong double-sided adhesive bonding. In addition, in some embodiments, a steel sheet is bonded to the side of the display panel20proximate to the housing10. In this case, the base401of the second spring fixing support42is fixed on the steel sheet. In addition, as shown inFIG.8A-2, the opening Q402of the sleeve402of the first spring fixing support41and the opening Q402of the sleeve402of the second spring fixing support42are disposed opposite to each other in a direction perpendicular to the rotating shaft13(parallel to the X direction inFIG.8A-2). One end E40-2of the spring40passes through the opening Q402of the sleeve402of the first spring fixing support41and is fixed on an inner wall S402-2of the sleeve402of the first spring fixing support41. The other end E40-1of the spring40passes through the opening Q402of the sleeve402of the second spring fixing support42and is fixed on an inner wall S402-2of the sleeve402of the second spring fixing support42. On this basis, in order to stabilize the spring40and prevent accidental ejection of the spring40during use, the spring40may be fixed on the inner wall of the sleeve402by screws or clips. The above is illustrated by taking one fixing assembly and one stretching assembly as an example. The fixing assemblies and the stretching assemblies provided by some embodiments of the present disclosure are disposed on the display panel as shown inFIGS.9A and9B, andFIG.9Bis a side view ofFIG.9A. As shown inFIG.9A, the foldable display apparatus may include a plurality of fixing assemblies30and a plurality of stretching assemblies01. The embodiments of the present disclosure does not limit the number of the fixing assemblies30and the number of the stretching assemblies01of the foldable display apparatus, as long as the display panel may be stably fixed and may be fully unfolded. The stretching assembly01may also have other implementations. For example, in some embodiments, as shown inFIGS.10A and10B, the stretching assembly01includes a micro-motor50. The micro-motor50is fixed on a side of the second sub-housing12proximate to the second non-bendable portion22. For example, the micro-motor50may be fixed to the second sub-housing12by means of screw, glue bonding, strong double-sided adhesive bonding, etc. The embodiments of the present disclosure does not limit the manner of fixing the micro-motor50, as long as the micro-motor50may be stably fixed to the second sub-housing12. It will be noted that a size of the micro-motor50is sufficient to enable the micro-motor to be installed between the housing10and the display panel20. In order to enable the micro-motor50to generate pulling force on the second non-bendable portion22, as shown inFIGS.10A and10B, the stretching assembly01further includes a flexible sheet60. For example, the flexible sheet60may be made of polyethylene terephthalate (PET), polyimide (PI), or the like. As shown inFIGS.10Aand10B, one end of the flexible sheet60is fixed on a side of the second non-bendable portion22proximate to the second sub-housing12. An opposite end of the flexible sheet60is fixed on a rotating shaft51of the micro-motor50. In this way, when the foldable display apparatus is unfolded from the folded state, the flexible sheet60may wind around the rotating shaft51of the micro-motor50by controlling the rotating shaft51of the micro-motor50to rotate a certain angle. As a result, pulling force that is perpendicular to the rotating shaft13and directed from the first non-bendable portion21to the second non-bendable portion22is applied to the second non-bendable portion22, so as to drive the display panel20to be further unfolded and improve the bulge. It will be noted that, in order to ensure that when the rotating shaft51of the micro-motor50rotates, the flexible sheet60applies the stable pulling force directed from the first non-bendable portion21to the second non-bendable portion22to the second non-bendable portion22, a position where the flexible sheet60is fixed to the second non-bendable portion22is closer to the rotating shaft13than the micro-motor50. On this basis, in order to facilitate a user to control the micro-motor50, in some embodiments, the foldable display apparatus is provided with a control button to control the rotation of the micro-motor50. For example, when the foldable display apparatus is unfolded from the folded state, the user may control the rotating shaft51of the micro-motor50to rotate a certain angle in the first direction through the control button. For example, as shown inFIG.10B, the rotating shaft51of the micro-motor50rotates counterclockwise to a certain angle, so that the flexible sheet60winds around the rotating shaft of the micro-motor50, and applies the pulling force to the second non-bendable portion22to make the display panel further unfolded. When the foldable display apparatus is folded from the unfolded state, the control button controls the rotating shaft51of the micro-motor50to rotate a certain angle in a direction opposite to the first direction (for example, clockwise), so that the flexible sheet60unwinds (no longer winding). In addition, when the foldable display apparatus is in the folded state, the micro-motor50may be in a locked state. In this way, user experience may be improved, and the foldable display apparatus may be more stable. In some embodiments, the rotating shaft51of the micro-motor50may wind or unwind the flexible sheet60according to a predetermined step length. Each time the user presses the control button, the rotating shaft51of the micro-motor50rotates forward or backward by an angle of one step length. Correspondingly, the second non-bendable portion22moves a distance of one step length. For example, when the foldable display apparatus is unfolded from the folded state, the user presses the control button once, and the second non-bendable portion22moves one step length to right, for example, 1 mm. According to a relationship between a rotation angle of the rotating shaft51of the micro-motor50and a distance moved by the second non-bendable portion22, an angle at which the rotating shaft51of the micro-motor50needs to rotate when the second non-bendable portion22moves one step length may be calculated. Correspondingly, when the user presses the control button once, the rotating shaft51of the micro-motor50rotates the angle counterclockwise, so that the second non-bendable portion22gradually moves to the right to avoid damage to the display panel20caused by an excessive moving distance of the second non-bendable portion22. An arrangement of the stretching assembly and the fixing assemblies on the display panel is shown inFIGS.11A and11B, andFIG.11Bis a side view ofFIG.11A. It will be noted that the figures show an example in which one micro-motor50and one flexible sheet60are disposed on the display panel. An arrangement of the micro-motor50and the flexible sheet60in the embodiments of the present disclosure is not limited thereto. For example, a plurality of micro-motors50and a plurality of flexible sheets60may also be disposed in a direction parallel to the rotating shaft13. In some embodiments, the fixing assembly may also be omitted. The foregoing descriptions are merely specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements that a person skilled in the art could conceive of within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims. | 39,294 |
11943885 | DETAILED DESCRIPTION This disclosure generally relates to devices, systems, and methods to protect fragile elements of a computing device.FIG.1is a perspective view of a representation of a computing device100, according to at least one embodiment of the present disclosure. The computing device100includes a first portion102and a second portion104. The first portion102is rotatable relative to the second portion104about at least one hinge106. In the embodiment shown inFIG.1, the first portion102rotates relative to the second portion104about two hinges106. However, it should be understood that the computing device may include more or less hinges than two. For example, the computing device may include one, two, three, four, five, six, seven, eight, nine, ten, or more hinges. The number of hinges106may depend on various factors, such as the weight of the first portion102, the weight of the second portion104, the difference in weight between the first portion102and the second portion104, the desired resistance to rotation, the length of the computing device100, the width of the computing device100, the thickness of the computing device100, any other factor, and combinations thereof. In some embodiments, the first portion102and/or the second portion104may include one or more of glass covers, plastic covers, displays, ceramic plates, aluminum plates, magnesium plates, any other plate, material, or cover, and combinations thereof. For the purposes of this disclosure, unless otherwise stated, a discussion of parts, elements, and relationships with respect to the first portion102may be applied in a similar fashion to the second portion104in addition to the first portion102or as an alternative to the first portion102. The hinge106may be made from a steel alloy, aluminum, plastic, or other material. In the embodiment shown, the hinges106both rotate and translate relative to the first portion102and the second portion104. A rotating and a translating hinge may facilitate an increased range of motion between the first portion102and the second portion104. For example, the first portion102includes a first top side108-1and a first bottom side110-1, and the second portion104includes a second top side108-2and a second bottom side110-2. In a first closed position, the first bottom side110-1may be in close proximity with (e.g., parallel),and optionally in contact with, the second bottom side110-2, and in a second closed position the first top side108-1may be in close proximity with (and optionally contact) the second top side108-2. In some embodiments, the first portion102and/or the second portion104may be more fragile and/or brittle than the hinge106. Thus, if the hinge106contacts and/or bumps the first portion102or the second portion104, the portion may break, crack, or deform. This may reduce functionality of the computing device100by interfering with the view of a display, interfering with the sensitivity of a touch screen display, causing the first portion to separate from the hinge, cause some other reduction in functionality, and combinations of the foregoing. Furthermore, a broken or cracked first portion may be aesthetically unappealing or even dangerous to the user. FIG.2is a top-down view of the hinge106ofFIG.1in an open position. The hinge106connects the first portion102to the second portion104. A bumper112(e.g., a grommet) is located between the first portion102and the body114of the hinge106. The bumper112may be made from an impact resistant material (e.g., rubber or silicone). Thus, if the body114of the hinge106contacts the bumper112(e.g., by an overextension of the hinge106), the bumper112will absorb some or all of the energy from the impact. This may help to protect the relatively more fragile material of the first portion102from being damaged. The first portion102includes a profile116of the first portion102. The profile116is a cut-out in the first-portion102to make room for the hinge body114. In the embodiment shown, the profile116includes a length section118, a width section120, and a curved section122. The length section118is straight and parallel to a length of the body114. The width section120is straight and parallel to a width of the body114. The curved section122is curved and located between the length section118and the width section120. In other embodiments, the profile116may be a different shape, e.g., the cut-out may have a corner with no curved section122, or may be curved with no straight sections. The bumper102is located away from the body114of the hinge106with a rotational offset124and a width offset126. The rotational offset124provides room for the first portion102and the body114to rotate relative to each other. Furthermore, the rotational offset124is sufficient that the hinge does not damage the first portion102and/or contact the bumper112when the hinge106is closed. In some embodiments, the rotational offset124may be in a range having an upper value, a lower value, or upper and lower values including any of 0.1 mm, 0.2 mm, 0.3 mm. 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, or any value therebetween. For example, the rotational offset124may be greater than 0.1 mm. In another example, the rotational offset124may be less than 1.5 mm. In yet other examples, the rotational offset124may be any value in a range between 0.1 and 1.5 mm. In some embodiments, it may be critical that the rotational offset124is less than 1.0 mm to improve the aesthetics of the computing device. In some embodiments, the rotational offset124may be less than 0.1 mm or greater than 1.5 mm. The width offset126is the distance from the body114to the bumper112perpendicular to the axis of rotation of the hinge106. The width offset126may be sized to allow the body114and the first portion102to rotate relative to each other without the body114rubbing against the first portion102. In some embodiments, the width offset126may be in a range having an upper value, a lower value, or upper and lower values including any of 0.1 mm, 0.2 mm, 0.3 mm. 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, or any value therebetween. For example, the width offset126may be greater than0.1mm. In another example, the width offset126may be less than 1.5 mm. In yet other examples, the width offset126may be any value in a range between 0.1 and 1.5 mm. In some embodiments, it may be critical that the width offset126is less than 1.0 mm to improve the aesthetics of the computing device. In some embodiments, the width offset126may be less than 0.1 mm or greater than 1.5 mm. Reducing the offsets124and126allows for increased area for the corresponding portions (e.g., additional screen size if the portion is a display portion). Additionally, it may be aesthetically pleasing to reduce rotational offset124and the width offset126as much as possible. The rotational offset124and the width offset are therefore sized to accommodate normal, everyday use without contacting and/or damaging the first portion102. However, during use, the computing device may be dropped, bumped, jostled, or otherwise subject to a sudden force. This may cause relative movement of the first portion102and the hinge body114. If the movement is great enough, then the body114may move sufficient to contact the first portion102, potentially causing the first portion102to crack, deform, and/or break. Conventionally, to prevent damage, the rotational offset124and/or the width offset126is increased. This may reduce the functionality and/or aesthetic appeal of a computing device. By placing the bumper112between the first portion102and the body114, the rotational offset124and the width offset126may be reduced, with the bumper112absorbing at least some of the impact from a sudden force. This helps to protect the first portion102from cracking and/or breaking. Furthermore, by placing the bumper112between the first portion102and the body114, the first portion102may be further offset from the body114. This may increase the radius of curvature of the curved portion122. Increasing the radius of curvature of the curved portion may reduce the stress concentrations at the curved portion112, thereby further protecting the first portion102from cracking and/or breaking. In some embodiments, the radius of curvature may be in a range having an upper value, a lower value, or upper and lower values including any of 0.1 mm, 0.2 mm, 0.3 mm. 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, or any value therebetween. For example, the radius of curvature may be greater than 0.1 mm. In another example, the radius of curvature may be less than 1.5 mm. In yet other examples, the radius of curvature may be any value in a range between 0.1 mm and 1.5 mm. In some embodiments, it may be critical that the radius of curvature is greater than 0.5 mm to reduce the stress concentrations and protect the first portion102. In some embodiments, the radius of curvature may be less than 0.1 mm or greater than 1.5 mm. FIG.3is a side view of the hinge106ofFIG.1. As may be seen, the first portion102includes a first bumper112-1connected to a first upper surface108-1and a second bumper112-2connected to a first lower surface110-1. Similarly, the second portion104includes a third bumper112-3connected to a second upper surface108-2and a fourth bumper112-4connected to a second lower surface110-2. Thus, the first portion102and the second portion104may have a bumper between them and the hinge body114for all directions of rotation. This helps to protect the first portion102and/or the second portion104from damage regardless of the position the computing device is in when it is dropped. Moreover, the bumpers may also protect the hinge from deforming or breaking by cushioning the impact between the hinge and the relatively non-deformable portions102and104. In some embodiments, each bumper has the same dimensions as each other bumper. In some embodiments, at least one bumper has a distinct shape and/or size as compared to other bumpers. In some embodiments, a subset of the bumpers is sized to act as feet for the device (e.g., to extend beyond a surface of the corresponding portion). AlthoughFIG.3shows the bumpers112adhered to the portions102and104, in other embodiments, one or more of the bumpers are instead adhered to the hinge body114. FIG.4is a representation of a bumper assembly212, according to at least one embodiment of the present disclosure. The bumper assembly212includes an impact resistant material228(e.g., a deformable material such as rubber). The impact resistant material228is bonded to a connecting member230. The connecting member230is sized and configured to extend underneath a corresponding surface (e.g., the first upper surface108-1or the first lower surface110-1ofFIG.1) of the first or second portion to connect the impact resistant material228to the portion. The connecting member230may be adhered to the first portion using an adhesive layer232. Connecting the impact resistant material228to the first portion using a connecting member230may help to increase the strength of the connection, thereby working to prevent the impact resistant material from breaking or tearing away. FIG.5is a bottom view of a bumper assembly312, according to at least one embodiment of the present disclosure. The connecting member330has a connecting profile334that runs along the side of the connecting member330to which the impact resistant material328is connected. The connecting profile334includes one or more features336. The features336may be cut-outs or protrusions in the connecting profile334that strengthen the mechanical strength of the connection between the impact resistant material328and the connecting member330. In some embodiments, the features336may include surface features, such as knurling, cross-hatching, and other surface features. FIG.6is a representation of a cross sectional view of a bumper assembly412, according to at least one embodiment of the present disclosure. In the embodiment shown, the connecting member430includes a lip438. The lip438is a bend in the connecting member438that increases the mechanical strength of the connection between the impact resistant material428and the connecting member430. As may be seen inFIG.6, the impact resistant material428is molded to the connecting member430. For example, the impact resistant material428may be overmolded (such as through injection molding or another process) over the connecting member430. This may allow the impact resistant material428to match to contours of the connecting member430. As may also be seen inFIG.6, the impact resistant material428is secured to the first portion402through the connecting member430. The connecting member430is secured to the first portion402using an adhesive layer432. In the embodiment shown, the impact resistant material428is contacting the first portion402. In some embodiments, the impact resistant material may be adhered to the first portion402. FIG.7is a representation of a side view bumper assembly512, according to at least one embodiment of the present disclosure. In the embodiment shown, the impact resistant material528(e.g., bumper112) extends beyond the surface540of the portion502(e.g., the first portion102or the second portion104). In some embodiments, a first subset of the bumpers112are sized to extend beyond the corresponding portion surfaces while a second subset of the bumpers are sized to not extend (e.g., be flush with) the corresponding portion surfaces. For example, the bumpers that would contact a resting surface when the device is oriented in a laptop mode would be sized to extend beyond the corresponding surface, while the other bumpers would be not extend beyond their corresponding portion surfaces. Having the material528extend beyond the surface of the portion502may further help to protect the portion502from cracking, scratching, deforming, and/or breaking. Furthermore, this provides the portion502with a “foot,” or a support on which the computing device may rest when placed down on a support surface so that the surface540does not contact the support surface. This may help to prevent the surface540from being scratched, cracked, or broken. In addition, the bumper112is optionally adapted (e.g., textured and/or sized) to provide a desired coefficient of friction (CoF) between the device and a resting surface. In this way, the bumper112helps prevent the device from sliding during use and/or when the user is attempting to open the device. The impact resistant material528extends an extension height542beyond the surface540. In some embodiments, the extension height542may be in a range having an upper value, a lower value, or upper and lower values including any of 0.05 mm, 0.1 mm, 0.15 mm, 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, 0.40 mm, 0.50 mm, 0.60 mm, 0.70 mm, 0.80 mm, 0.90 mm, 1.00 mm, or any value therebetween. For example, the extension height542may be greater than 0.05 mm. In another example, the extension height542may be less than 1.00 mm. In yet other examples, the extension height542may be any value in a range between 0.05 mm and 1.0 mm. In some embodiments, it may be critical that the extension height542is greater than 0.30 mm to provide protection for the surface540of the first portion502. In some embodiments, the impact resistant material528is sized such that the extension height is greater than a deformation factor for the material so that the corresponding portion does not contact the resting surface even when a user is operating the device and providing a downward force on the device (e.g., due to the user resting their hands the device). In some embodiments, the extension height may be 0, negative, or greater than 1.0 mm. INDUSTRIAL APPLICABILITY This disclosure generally relates to devices, systems, and methods to protect elements of a computing device. A computing device may include a first portion and a second portion that are connected by one or more hinges. For example, the first portion and the second portion may include one or more of glass covers, plastic covers, displays, ceramic plates, aluminum plates, magnesium plates, or any other plate, material, or cover. In some embodiments, the hinge may be made from a steel alloy, aluminum, plastic, or other material. For the purposes of this discussion, unless otherwise stated, a discussion of parts, elements, and relationships with respect to the first portion may be applied in a similar fashion to the second portion in addition to the first portion or as an alternative to the first portion. The one or more hinges may facilitate relative rotation between the first portion and the second portion. In some embodiments, the one or more hinges may both rotate and translate relative to the first portion and/or the second portion. A rotating and a translating hinge may facilitate an increased range of motion between the first portion and the second portion. For example, the first portion may include a first top side and a first bottom side, and the second portion may include a second top side and a second bottom side. In a first position, the first bottom side may be parallel (and even contact) the second bottom side, and in a second position the first top side may be parallel (and even contact) the second top side. In some embodiments, the first portion may be more brittle than the hinge. Thus, if the hinge contacts and/or bumps the first portion, the first portion may break or crack. This may reduce functionality of a device by interfering with the view of a display, interfering with the sensitivity of a touch screen display, causing the first portion to separate from the hinge, cause some other reduction in functionality, and combinations of the foregoing. Furthermore, a broken or cracked first portion may be aesthetically unappealing to the user. In some embodiments, the first portion may have a greater compressive strength than the hinge, which may cause the hinge to bend, crack, or break upon contact with the first portion. This may cause the hinge to malfunction and/or be aesthetically unappealing to the user. In some embodiments, the first portion and/or the second portion may be both more brittle and have a harder compressive strength than the hinge. In this manner, a contact between the first portion and the hinge may damage, crack, break, or bend both the first portion and the hinge. In some embodiments, an impact resistant member may be affixed to the first portion. The impact resistant member may contact the hinge before the hinge contacts the first portion. The impact resistant member may be made from a material that is more resilient and/or have a greater elastic deformity than one or both of the first portion and the hinge. Thus, when the hinge would normally contact the first portion during rotation of the first portion, the hinge may contact the impact resistant layer. Because the impact resistant member has a greater resilience and/or elastic deformity, the impact resistant member may not break upon contact with the hinge. Thus, the impact resistant member may absorb the force of the impact from the hinge, thereby at least partially protecting (e.g., reducing the damage to) both the first portion and the hinge. In some embodiments, the impact resistant member may be fabricated from a material that has a lower compressive strength than both the first portion and the hinge. For example, the impact resistant member may be fabricated from, rubber, silicone, plastic, TPE, any other material, and combinations thereof. In some embodiments, the impact resistant member may be attached to a connecting member, and the connecting member may be attached to the first portion. For example, the connecting member may be a hard plate that is adhered to the second side of the first portion with an adhesive layer. The metal plate may extend past an edge of the first portion. The impact resistant member may then be connected to the connecting member. In some embodiments, the impact resistant member may be overmolded onto the connecting member. In some embodiments, a chemical primer may attached to the connecting member, and the chemical primer may further bond the impact resistant member to the connecting member. Thus, in some embodiments, the impact resistant member and the connecting member may become a single piece. In other words, the impact resistant member may not be removed from the connecting member without damaging or destroying the impact resistant member and/or the connecting member. In some embodiments, the connecting member may include mechanical interlock features, such as texturing, braiding, profiles, cross-hatching, knurling, other mechanical interlock features, and combinations of the foregoing. In some embodiments, the connecting member may include an edge having an edge profile, the edge profile being non-straight. These mechanical interlock features may increase the strength of the bond between the impact resistant member and the connecting member. In some embodiments, the connecting member may include a lip in the hinge area around which the impact resistant member is attached or molded. This lip may increase the strength of the impact resistant member and the resistance of the impact resistant member to damage and deformation from impact by the hinge. In some embodiments, the impact resistant member may be attached directly to the first portion. For example, the impact resistant member may be glued or molded onto the first portion. In some embodiments, the first portion may include mechanical interlock features, such as texturing, braiding, profiles, cross-hatching, knurling, other mechanical interlock features, and combinations of the foregoing. In some embodiments, the mechanical interlock features may be included in the first portion during manufacturing. In some embodiments, the mechanical interlock features may be included in the first portion post manufacturing, such as by grinding, milling, laser etching, other methods, and combinations thereof. In some embodiments, the impact resistant member may be connected directly to the hinge. For example, the impact resistant member may be overmolded onto, or adhered to, an outer circumference of the hinge. In some embodiments, it may be aesthetically preferable to attach the impact resistant member directly to the hinge. In some embodiments, the impact resistant member may be installed flush with a the first surface of the first portion. In some embodiments, the impact resistant member may extend proud above a height of the first portion. In other words, the impact resistant member may extend beyond the first surface of the first portion. In this manner, the impact resistant member may resemble a foot against which the mobile device may rest. This may help to protect the first portion from scratches, cracks, breaks, and other damage caused by a user placing the mobile device on a surface. In some embodiments, the extension past the first surface may be in a range having an upper value, a lower value, or upper and lower values including any of 0.05 mm, 0.1 mm, 0.15 mm, 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, 0.40 mm, 0.50 mm, 0.60 mm, 0.70 mm, 0.80 mm, 0.90 mm, 1.00 mm, or any value therebetween. For example, the extension may be greater than 0.05 mm. In another example, the extension may be less than 1.0 mm. In yet other examples, the extension may be any value in a range between 0.05 mm and 1.0 mm. In some embodiments, it may be critical that the extension is greater than 0.30 mm to properly protect the first surface. In some embodiments, the extension may be 0, negative, or greater than 1.0 mm. The first portion has a hinge profile, which is the profile of the first portion around the hinge. To prevent the hinge from contacting the first portion during normal operation or when a user drops the computing device, the profile is offset from the range of motion of the hinge with a profile offset. In some embodiments, the impact resistant member may be placed inside the profile offset. In this manner, the impact resistant member may extend from the profile of the first portion to the range of motion of the hinge. This may reduce the visible or spatial gap between the first portion and the hinge, which may be visually appealing to the user. The profile includes at least one corner having a first portion radius of curvature. In some embodiments, the first portion radius of curvature of the profile may be increased by offsetting the profile from the hinge. This may reduce the stress concentrations on the first portion. This may reduce the likelihood that the first portion may break or crack at the corner. In some embodiments, the first portion radius of curvature may be greater than 0 mm. For example, the radius of curvature may be greater than 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, or any value therebetween. In some embodiments, it may be critical that the first portion radius of curvature is greater than 0.5 mm to reduce the likelihood of the first portion cracking. In some embodiments, the impact resistant may follow the profile of the first portion. The impact resistant member may thus have an impact resistant member radius of curvature that is less than the first portion radius of curvature. In some embodiments, the impact radius of curvature may be approximately 0. In other words, the impact resistant member may make one or more sharp turns. One or more specific embodiments of the present disclosure are described herein. These described embodiments are examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, not all features of an actual embodiment may be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous embodiment-specific decisions will be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one embodiment to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. The articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements in the preceding descriptions. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. For example, any element described in relation to an embodiment herein may be combinable with any element of any other embodiment described herein. Numbers, percentages, ratios, or other values stated herein are intended to include that value, and also other values that are “about” or “approximately” the stated value, as would be appreciated by one of ordinary skill in the art encompassed by embodiments of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value. A person having ordinary skill in the art should realize in view of the present disclosure that equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made to embodiments disclosed herein without departing from the spirit and scope of the present disclosure. Equivalent constructions, including functional “means-plus-function” clauses are intended to cover the structures described herein as performing the recited function, including both structural equivalents that operate in the same manner, and equivalent structures that provide the same function. It is the express intention of the applicant not to invoke means-plus-function or other functional claiming for any claim except for those in which the words ‘means for’ appear together with an associated function. Each addition, deletion, and modification to the embodiments that falls within the meaning and scope of the claims is to be embraced by the claims. The terms “approximately,” “about,” and “substantially” as used herein represent an amount close to the stated amount that still performs a desired function or achieves a desired result. For example, the terms “approximately,” “about,” and “substantially” may refer to an amount that is within less than 5% of, within less than 1% of, within less than 0.1% of, and within less than 0.01% of a stated amount. Further, it should be understood that any directions or reference frames in the preceding description are merely relative directions or movements. For example, any references to “up” and “down” or “above” or “below” are merely descriptive of the relative position or movement of the related elements. The present disclosure may be embodied in other specific forms without departing from its spirit or characteristics. The described embodiments are to be considered as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. Changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. | 30,093 |
11943886 | DETAILED DESCRIPTION OF THE INVENTION FIG.1is a perspective view of a communication system1100having an electronic assembly1102in accordance with an exemplary embodiment.FIG.2is an exploded view of the communication system1100and the electronic assembly1102in accordance with an exemplary embodiment. The electronic assembly1102includes cable connector modules1104(FIG.2) electrically connected to an electronic package1106(FIG.2) by interposer assemblies1108(FIG.2). The electronic assembly1102is electrically connected to a host circuit board1110, such as using a board connector1112(FIG.2), which may transmit power and/or data between the host circuit board1110and the electronic assembly1102. In other various embodiments, the electronic assembly1102may be mounted directly to the host circuit board1110without the use of the board connector1112. In an exemplary embodiment, a compression assembly1114is used to load the electronic assembly1102to the interposer assemblies1108to electrically connect the cable connector modules1104to the electronic package1106. In an exemplary embodiment, the compression assembly1114includes a load plate1120used to press downward against various components of the electronic assembly1102to load the contacts of the electronic assembly1102. Compression hardware1116, such as threaded fasteners with biasing members (for example, springs), are used to couple the load plate1120to a bolster plate1118. Optionally, an insulator1128may be provided between the bolster plate1118and the host circuit board1110. The bolster plate1118may be located above the host circuit board1110in various embodiments. Alternatively, the bolster plate1118may be located below the host circuit board1110. The load plate1120is forced downward to couple the cable connector modules1104to the interposer assemblies1108. For example, the load plate1120may compress contacts of the interposer assemblies1108. In an alternative embodiment, the load plate1120is coupled to the cover assembly1130and/or the bolster plate1118using fixed hardware rather than compression hardware to fix the position of the load plate1120relative to the electronic package1106. In such embodiments, the compression of the cable connector modules1104may come from other compression members, such as internal springs. In an exemplary embodiment, the compression assembly1114includes a heat transfer element1122to dissipate heat from the electronic package1106and/or the cable connector modules1104. The load plate1120may define the heat transfer element1122. The heat transfer element1122may be a cold plate having cooling channels for active cooling of the cold plate. For example, the cooling channels may have liquid cooling to dissipate heat from the cold plate. In other various embodiments, the heat transfer element may be a heat sink having heat dissipating fins for passive cooling of the heat sink using airflow over the heat dissipating fins to dissipate heat from the heat sink. In various embodiments, the electronic package1106is an integrated circuit assembly, such as an ASIC. However, the electronic package1106may be another type of communication component. The cable connector modules1104are mated directly to the ASIC via the interposer assemblies1108independent of the host circuit board1110. For example, high-speed data signals are transmitted between the electronic package1106and the cable connector modules1104via the interposer assemblies1108without the high-speed data signals passing through the host circuit board1110. In an exemplary embodiment, a plurality of cable connector modules1104are coupled to the electronic package1106. For example, the cable connector modules1104may be provided on multiple sides of the integrated circuit or other communication element of the electronic package1106. In the illustrated embodiment, the cable connector modules1104are provided on all four sides of the integrated circuit. Other arrangements are possible in alternative embodiments. In an exemplary embodiment, the compression hardware1116includes spring members configured to transfer spring forces from the compression hardware1116to the load plate1120. Other types of compression members may be used in alternative embodiments. In the illustrated embodiment, the compression hardware1116is provided on all four sides of the load plate1120; however, the compression hardware1116may be coupled to other areas of the load plate1120in alternative embodiments. In an exemplary embodiment, the electronic assembly1102includes one or more cover assembly1130coupled to the electronic package1106. The cover assembly1130covers the cable connector modules1104and the interposer assemblies1108. In the illustrated embodiment, the electronic assembly1102includes multiple cover assemblies1130, such as at each side of the integrated circuit of the electronic package1106. Each cover assembly1130covers multiple cable connector modules1104. The cover assembly1130includes a cover1132and bridge assemblies1134coupled to the cover1132. The cover1132is coupled to the bolster plate1118using fasteners1136(FIG.18). The bridge assemblies1134are aligned with the cable connector modules1104. The bridge assemblies1134are used to transfer compression loads from the load plate1120to the interposer assemblies1108. The compression loads may come from the compression hardware1116. The compression loads may additionally or alternatively come from internal spring elements, such as spring elements within the bridge assemblies1134. The load plate1120presses against the bridge assemblies1134and drives the bridge assemblies1134into the cable connector modules1104. The forces from the load plate1120compress the interposer assemblies1108against the integrated circuit or the substrate of the electronic package1106. The bridge assemblies1134press the cable connector modules1104into the interposer assemblies1108. The compressive forces from the load plate1120may be transferred to the interposer contacts through the compressive forces applied to the individual cable connector modules1104. In an exemplary embodiment, the load plate1120may be thermally coupled to the cable connector modules1104through the bridge assemblies1134. For example, the bridge assemblies1134define heat spreaders for dissipating heat from the cable connector modules1104to the heat transfer element1122defined by the load plate1120. In an exemplary embodiment, the interposer assemblies1108define separable mating interfaces. For example, each interposer assembly1108includes an upper separable mating interface, such as a compressible interface. As such, the cable connector modules1104may be removable or replaceable. Each interposer assembly1108may include a lower separable mating interface, such as a compressible interface. The contacts of the interposer assembly1108may be compressible columnar contacts, such as conductive elastomeric contacts. In other embodiments, the contacts of the interposer assembly1108may be stamped and formed contacts, such as including spring beams. The spring beams may be provided at the top and/or the bottom of the interposer assembly1108. The contacts may be press fit contacts, solder contacts, or other types of contacts in alternative embodiments. In various embodiments, a plurality of interposer assemblies1108are mounted to the electronic package1106. For example, each cable connector module1104is mounted to a separate interposer assembly1108. In alternative embodiments, a plurality of cable connector modules1104may be mounted to a single interposer assembly1108. For example, separate interposer assemblies1108may be provided along each side of the electronic package1106. In another embodiment, a single interposer assembly is provided extending along all four sides of the electronic package1106. FIG.3is a perspective view of the electronic assembly1102in accordance with an exemplary embodiment. The electronic assembly1102includes the electronic package1106supporting a plurality of the cable connector modules1104. The interposer assemblies1108electrically connect the cable connector modules1104to the electronic package1106. The cover assembly1130is used to couple the cable connector modules1104to the electronic package1106. When the load plate1120(shown inFIG.1) is coupled to the cover assembly1130, the bridge assemblies1134are used to compress the interposer assemblies1108between the cable connector modules1104and the electronic package1106. The electronic package1106includes a package substrate1150having an upper surface1152and a lower surface1154. The electronic package1106includes an integrated circuit component1156mounted to the upper surface1152of the package substrate1150. The integrated circuit component1156may be a chip, an ASIC, a processor, a memory module or another component mounted to the top of the package substrate1150. In the illustrated embodiment, the integrated circuit component1156is rectangular and approximately centered on the package substrate1150; however, the integrated circuit component1156may have other shapes or locations or there may be more than one integrated circuit component in alternative embodiments. In an exemplary embodiment, the package substrate1150includes locating features1158for locating the electronic package1106relative to the host circuit board1110(shown inFIG.1). In the illustrated embodiment, the locating features1158are openings through the package substrate1150. Other types of locating features may be used in alternative embodiments, such as channels, dimples, extensions, tabs, posts, pins, and the like. The package substrate1150includes edges1160extending around the perimeter of the package substrate1150. In the illustrated embodiment, the package substrate1150is rectangular shape having four perpendicular edges. The package substrate1150may have other shapes including greater or fewer edges1160in alternative embodiments. The integrated circuit component1156is mounted to the package substrate1150at a component mounting area1162, which may be approximately centered between the edges1160. The package substrate1150includes package contacts (not shown) at the component mounting area1162used to electrically connect the integrated circuit component1156to the package substrate1150. The package contacts may be pads, traces, vias, and the like. The package substrate1150includes lower package contacts (not shown) at the lower surface1154of the package substrate1150. The lower package contacts are used to electrically connect the electronic package1106to the board connector1112(shown inFIG.2). In an exemplary embodiment, power and low-speed data signals are transmitted through the lower package contacts between the package substrate1150and the board connector1112. High speed data signals may additionally be transmitted through the lower package contacts. The lower package contacts are electrically connected to the integrated circuit component1156via corresponding package contacts. In an exemplary embodiment, the lower package contacts may be approximately centered along the lower surface1154, such as directly below the component mounting area1162. The package substrate1150includes upper package contacts (not shown) at the upper surface1152of the package substrate1150. The upper package contacts are used to electrically connect the electronic package1106to the cable connector modules1104via the interposer assemblies1108. In an exemplary embodiment, high-speed data signals are transmitted through the upper package contacts between the package substrate1150and the cable connector modules1104. The upper package contacts are electrically connected to the integrated circuit component1156via corresponding package contacts. In an exemplary embodiment, the upper package contacts are provided around the outer periphery of the package substrate1150. In an exemplary embodiment, the package substrate1150includes mounting areas1164around the outer periphery of the package substrate1150. The interposer assemblies1108and the cable connector modules1104are coupled to the package substrate1150at the mounting areas1164. The mounting areas1164are located between the integrated circuit component1156at the component mounting area1162and the edges1160. In the illustrated embodiment, the mounting areas1164are provided along all four sides of the integrated circuit component1156for the purpose of achieving short electrical traces (improved signal integrity) to/from the integrated circuit component1156. The electronic assembly1102has high channel density for data communication and power distribution to the integrated circuit component1156. For example, data channels are provided on both the upper surface1152and the lower surface1154of the package substrate1150. A subset of the data signals, such as the low speed and/or sideband data signals, are routed through the bottom of the electronic package1106to the host circuit board1110and a subset of the data signals, such as the high speed data signals, are routed through the top of the electronic package1106to the cable connector modules1104. The performance and design efficiency are enhanced by increasing the number of data channels to the integrated circuit component1156. Furthermore, by routing the high-speed data signals directly to the cable connector modules1104, rather than routing the high-speed data signals through the host circuit board1110, the performance of the communication system1100is enhanced. In an exemplary embodiment, the cable connector modules1104are coupled to the electronic package1106at multiple locations (e.g., at four sides of the chip) to increase density of the communication system1100and shorten electrical paths of the communication system1100. The arrangement reduces the number of interfaces needed along the bottom of the package substrate1150by routing the data channels to the top of the package substrate1150for take-off by the cable connector modules1104. The cable connector modules1104are separable from the electronic package1106using the interposer assemblies1108. Each cable connector module1104has its own compressive mating force using the corresponding bridge assemblies1134. The cover assembly1130can be removed to service an individual cable connector module1104, such as to adjust or replace the cable connector module1104. FIG.4is a perspective view of the cable connector module1104in accordance with an exemplary embodiment.FIG.5is a side view of the cable connector module1104in accordance with an exemplary embodiment.FIG.6is a bottom view of the cable connector module1104in accordance with an exemplary embodiment. In the illustrated embodiment, the cable connector module1104may be an optical module, such as including fiber optic data transmission. Alternatively, the cable connector module1104may be a copper cable module using a copper conductor cable to transmit electrical data signals. The cable connector module1104includes a connector module housing1170having a cavity1172that receives a connector module substrate1174. One or more cables1178extend from the connector module housing1170. In various embodiments, the cable connector module1104may be an optical module having an optical engine1176(shown in phantom) for optical-digital conversion. In an exemplary embodiment, the optical engine1176includes an electrical-to-optical converter configured to convert between electrical signals and optical signals. The optical engine1176may include other electrical components. The cables1178may be terminated to the optical engine1176. Alternatively, the cable connector module1104is an electrical module having signal conductors. For example, the cables1178may be copper cables terminated directly to the connector module substrate1174, such as being soldered to pads of the connector module substrate1174. The cables1178may be connected to the substrate1174or other component at separable interfaces. For example, the cables may be plugged into the connector module housing1170. The connector module substrate1174extends between a front1181and a rear1183of the cable connector module1104. The connector module substrate1174is provided at a bottom1185of the cable connector module1104. The connector module substrate1174extends between sides1187,1189of the cable connector module1104. The connector module substrate1174may be a printed circuit board or other suitable material for routing electrical traces. The connector module substrate1174includes module contacts1188configured to be electrically connected to the interposer assembly1108(shown inFIG.3). For example, the module contacts may be pads on the bottom of the connector module substrate1174. In an exemplary embodiment, the connector module substrate1174includes locating features1180configured to locate the cable connector module1104relative to the interposer assembly1108. In an exemplary embodiment, the connector module housing1170includes locating features1182configured to locate the cable connector module1104relative to the interposer assembly1108. The locating features1180,1182are defined by slots, which are aligned with each other and configured to receive a locating feature of the interposer assembly1108to align the cable connector module1104with the interposer assembly1108. Other types of locating features1180,1182may be provided in alternative embodiments, such as protrusions or pins. In an exemplary embodiment, the connector module housing1170is manufactured from a thermally conductive material, such as a metal material. The connector module housing1170may transfer heat from heat generating components, such as the optical engine1176or the cables1178or other components. In an exemplary embodiment, the bridge assembly1134(shown inFIG.2) is configured to engage a top1184of the connector module housing1170to dissipate heat from the cable connector module1104. FIG.7is a perspective view of the cable connector module1104in accordance with an exemplary embodiment.FIG.8is a side view of the cable connector module1104in accordance with an exemplary embodiment.FIG.9is a bottom view of the cable connector module1104in accordance with an exemplary embodiment. In the illustrated embodiment, the cable connector module1104is a copper cable module rather than an optic module. The cables1178are copper cables, such as coaxial cables, twin-axial cables. The cables1178extend into the connector module housing1170for termination to the connector module substrate1174. The connector module housing1170may be shaped differently, such as to accommodate the copper cables, which may be terminated to both the upper and lower surfaces of the connector module substrate1174. FIG.10is a side view of a portion of the cable connector module1104in accordance with an exemplary embodiment showing the cables1178terminated to the connector module substrate1174.FIG.11is a perspective view of a portion of the cable connector module1104in accordance with an exemplary embodiment showing the cables1178terminated to the connector module substrate1174. In an exemplary embodiment, conductors of the cables1178are soldered directly to the connector module substrate1174, such as to the upper surface and the lower surface of the connector module substrate1174. FIG.12is a top view of the interposer assembly1108in accordance with an exemplary embodiment.FIG.13is a bottom view of the interposer assembly1108in accordance with an exemplary embodiment.FIG.14is a perspective view of the interposer assembly1108in accordance with an exemplary embodiment. The interposer assembly1108includes an array of interposer contacts1200held together by a support plate1202. The interposer assembly1108includes an interposer frame1204holding the support plate1202and the interposer contacts1200. The interposer frame1204may be a multipiece frame, such as having an upper frame member and a lower frame member with the support plate1202sandwiched between the upper and lower frame members. The interposer frame1204extends around an outer periphery of the interposer assembly1108, such as along all four sides of the support plate1202. The interposer frame1204may have other shapes in alternative embodiments. In an exemplary embodiment, the interposer frame1204includes upper locating walls1210forming a socket1212configured to receive the corresponding cable connector module1104. The upper locating walls1210may form a rectangular socket1212; however, the socket1212may have other shapes in alternative embodiments. In an exemplary embodiment, an opening1214is provided in one of the upper locating walls1210. The opening1214is configured to receive a portion of the cable connector module1104. In an exemplary embodiment, interior surfaces of the upper locating walls1210form locating surfaces1216for locating the cable connector module1104in the socket1212. In an exemplary embodiment, the interposer frame1204includes locating features1218for locating the cable connector module1104. For example, edges of the upper locating walls1210facing the opening1214form the locating features1218. The locating features1218are configured to be received in the locating features1180,1182(for example, slots) of the cable connector module1104. In an exemplary embodiment, the interposer frame1204includes lower locating pins1219(FIG.13) extending downward from the lower frame member1208. The lower locating pins1219are used for locating the interposer assembly1108relative to the electronic package1106(shown inFIG.3). The lower locating pins1219are received in the package substrate1150(shown inFIG.3) to position the interposer frame1204and the interposer contacts1200relative to the package substrate1150. Other types of locating features may be used in alternative embodiments. FIG.15is a side view of a portion of the interposer assembly1108showing the support plate1202and a plurality of the interposer contacts1200located between the package substrate1150and the connector module substrate1174. In an exemplary embodiment, the support plate1202is a film having an upper surface1220and a lower surface1222. The support plate1202includes openings1214therethrough holding corresponding interposer contacts1200. The support plate1202is manufactured from an insulative material, such as a polyimide material, to electrically isolate the interposer contacts1200from one another. The interposer contacts1200are held by the support plate1202. In an exemplary embodiment, the interposer contacts1200are compressible contacts, such as conductive polymer columns. Each interposer contact1200includes an upper mating interface1226and a lower mating interface1228. The upper mating interface1226is located above the upper surface1220of the support plate1202and the lower mating interface1228is located below the lower surface1222of the support plate1202. The interposer contacts1200are compressible between the upper mating interfaces1226and the lower mating interfaces1228. Optionally, the upper and lower mating interfaces1226,1228may be planar interfaces oriented parallel to each other. Optionally, upper and lower sides1230,1232of the interposer contacts1200may be tapered. For example, the sides1230,1232may be oriented non-perpendicular to the upper and lower mating interfaces1226,1228. The upper and lower portions of the interposer contacts1200may be cone-shaped, such as being frusto-conical. Other types of interposer contacts1200may be utilized in alternative embodiments. FIG.16is a perspective view of a portion of the electronic assembly1102in accordance with an exemplary embodiment showing one of the interposer assemblies1108poised for mating with the electronic package1106. The package substrate1150includes a plurality of upper package contacts1166on the upper surface1152of the package substrate1150. The upper package contacts1166are arranged in an array complementary to the array of interposer contacts1200. The upper package contacts1166may be signal contacts and/or ground contacts and/or power contacts. The package substrate1150includes interposer locating features1168for locating the interposer assembly1108relative to the electronic package1106. In the illustrated embodiment, the interposer locating features1168are openings in the package substrate1150configured to receive the lower locating pins1219of the interposer assembly1108. Other types of locating features may be used in alternative embodiments, such as protrusions, posts, and the like. FIG.17is a perspective view of a portion of the electronic assembly1102in accordance with an exemplary embodiment showing one of the cable connector modules1104poised for mating with the corresponding interposer assembly1108and the electronic package1106. The cable connector module1104is configured to be received in the socket1212and engage the locating surfaces1216of the upper walls1210. The locating features1180,1182of the cable connector module1104are aligned with the locating features1218to locate the cable connector module1104relative to the interposer assembly1108. The opening1214receives a portion of the cable connector module1104. The connector module substrate1174is configured to be coupled to the interposer contacts1200of the interposer assembly1108. For example, the connector module contacts on the bottom surface of the connector module substrate1174are aligned with and coupled to corresponding interposer contacts1200. The connector module substrate1174electrically connects the interposer contacts1200with the cables1178, such as directly or through the optical engine1176. FIG.18is a perspective view of a portion of the electronic assembly1102in accordance with an exemplary embodiment showing one of the cover assemblies1130poised for mating with the electronic package1106over the cable connector modules1104. During assembly, the cover assembly1130is placed over the cable connector modules1104and the interposer assemblies1108. The cover assembly1130covers multiple cable connector modules1104. The cover1132holds the bridge assemblies1134and aligns the bridge assemblies1134with the cable connector modules1104. The cover1132is coupled to the bolster plate1118using the fasteners1136. When the cover assembly1130is coupled to the bolster plate1118, the bridge assemblies1134are used to press downward against the cable connector modules1104, such as by the load plate1120. The bridge assemblies1134transfer compression loads from the load plate1120to the interposer assemblies1108through the cable connector modules1104. FIG.19is a top view of the cover assembly1130in accordance with an exemplary embodiment.FIG.20is a side view of the cover assembly1130in accordance with an exemplary embodiment.FIG.21is a bottom view of the cover assembly1130in accordance with an exemplary embodiment.FIG.22is an exploded view of the cover assembly1130in accordance with an exemplary embodiment. The cover assembly1130includes the cover1132and the bridge assemblies1134. The cover1132includes a plate1140at a top of the cover1132. The plate1140includes openings1141for receiving the fasteners1136(shown inFIG.18). The cover1132includes walls1142extending from the bottom of the plate1140to form one or more connector module cavities1144. The walls1142may be separating walls1142between connector module cavities1144. The connector module cavities1144are configured to receive corresponding cable connector modules1104(shown inFIG.18). The separating walls1142separate the cable connector modules1104. The separating walls1142may be used to guide mating of the cover1132with the cable connector modules1104. The plate1140includes windows1146therethrough aligned with the connector module cavities1144. The bridge assemblies1134are received in corresponding connector module cavities1144and extend through the windows1146. Tops of the bridge assemblies1134may be located above the top of the plate1140to interface with the load plate1120(shown inFIG.1). Bottoms of the bridge assemblies1134may be located below the plate1140in the connector module cavity1144to interface with the cable connector modules1104. In an exemplary embodiment, the bridge assemblies1134are coupled to the cover1132, such as being welded to the bottom of the plate1140or secured by other means, such as using fasteners. In alternative embodiments, the cover1132has a single connector module cavity1144and a single window1146. Multiple covers1132may be arranged adjacent each other to form an array. FIG.23is a perspective view of the bridge assembly1134in accordance with an exemplary embodiment. The bridge assembly1134includes a plurality of plates1190arranged in a plate stack1192. A frame1194holds the plates1190in the plate stack1192. The plates1190may be coupled to the frame by internal spring elements (not shown), which allow the plates1190to move relative to the frame1194and/or relative to each other. For example, the frame1194extends circumferentially around the plate stack1192. The frame1194includes mounting tabs1195for mounting the bridge assembly1134to the cover1132(shown inFIG.22). The plates1190extend between upper edges1196and lower edges1198. In an exemplary embodiment, the plates1190include upper plates and lower plates interleved with each other. For example, the upper plates have the upper edges1196and the lower plates have the lower edges1198. The plates1190may be movable independently relative to each other and relative to the frame1194. For example, the upper plates and the lower plates are movable relative to each other with the internal spring elements biasing the upper and lower plates apart from each other, such as driving the upper plates into the load plate1120and the lower plates into the cable connector modules1104. Alternatively, the plates1190may be grouped together and the groups of plates1190may be movable relative to other group(s). The plates1190independently transfer the pressing forces from the load plate1120(shown inFIG.1) to the cable connector module1104(shown inFIG.18). The plates1190may conform to irregular shapes of the load plate1120and/or the cable connector module1104. The plates1190may be metal plates in various embodiments. In such embodiments, the plates1190may be thermally conductive, such as to transfer heat from the cable connector modules1104to the load plate1120(for example, the heat transfer element1122). As such, the plates1190form a thermal bridge between the cable connector modules1104and the load plate1120. Alternatively, the plates1190may be plastic, such as to reduce weight and/or cost of the bridge assembly1134. FIG.24is a perspective view of a portion of the electronic assembly1102in accordance with an exemplary embodiment showing one of the cover assemblies1130poised for mating with the electronic package1106over the cable connector modules1104. During assembly, the cover assembly1130is placed over the cable connector modules1104and the interposer assemblies1108. The cover assembly1130covers multiple cable connector modules1104. The cover1132holds the bridge assemblies1134and aligns the bridge assemblies1134with the cable connector modules1104. The cover1132is coupled to the bolster plate1118using the fasteners1136. When the cover assembly1130is coupled to the bolster plate1118, the bridge assemblies1134are used to press downward against the cable connector modules1104, such as by the load plate1120. The bridge assemblies1134transfer compression loads from the load plate1120to the interposer assemblies1108through the cable connector modules1104. In an exemplary embodiment, the electronic assembly1102may include both fiber modules1104aand copper cable modules1104b. Both the fiber modules1104aand copper cable modules1104bare configured to be coupled to the interposer assemblies1108. For example, the fiber modules1104aand copper cable modules1104bmay have a common footprint and contact layout for mating to any of the interposer assemblies1108. The interposer assemblies1108are designed for mating with both the fiber modules1104aand copper cable modules1104b. The cable connector modules1104are arranged in cable connector module sets1191. The cables1178of each cable connector module1104within the cable connector module set1191extend in a common direction (for example, from the same side of the electronic package1106). The cable connector modules1104are mounted to the electronic package1106such that fronts1181and rears1183of the cable connector modules1104within each cable connector module set1191are aligned. The sides1187,1189of the cable connector modules1104within the cable connector module set1191face each other and may abut against each other. During assembly, the interposer assemblies1108are coupled to the package substrate1150at the upper package contacts1166around the integrated circuit component1156on the upper surface1152of the package substrate1150. The cable connector modules1104are coupled to the corresponding interposer assemblies1108. The cables1178extend from the sides of the electronic package1106, and may extend from all four sides of the electronic package1106. The cables1178extend generally horizontally from the electronic package1106, thus limiting the height of the electronic assembly1102. The cover assemblies1130are coupled to the cable connector modules1104. The bridge assemblies1134are held in position by the cover1132and pressed downward against the cable connector modules1104by the compression assembly1114. FIG.25is a cross-sectional view of a portion of the communication system1100showing the electronic assembly1102coupled to the host circuit board1110. The bolster plate1118is mounted to the top of the host circuit board1110. The package substrate1150is mounted above the bolster plate1118, such as with the insulator1128between the package substrate1150and the bolster plate1118. The package substrate1150and bolster plate1118may be secured to the host circuit board1110using fasteners1126. The cover assembly1130is coupled to the package substrate1150and bolster plate1118over the cable connector modules1104. The cover assembly1130is coupled to the package substrate1150and bolster plate1118using the fasteners1136. The load plate1120is coupled to the cover1132using the compression hardware1116. The compression hardware1116presses the load plate1120downward against the bridge assemblies1134. The load plate1120forces the plates1140against the cable connector modules1104to compress the cable connector modules1104against the interposer assemblies1108. The plates1140may be used to dissipate heat from the cable connector modules1104by forming thermal bridges between the cable connector modules1104and the load plate1120. FIG.26is a cross-sectional view of a portion of the communication system1100showing the electronic assembly1102coupled to the host circuit board1110.FIG.26shows the heat transfer element1122(for example, the load plate1120) thermally coupled to the bridge assemblies1134and the integrated circuit component1156. The heat transfer element1122dissipates heat from the cable connector modules1104and the integrated circuit component1156. In an exemplary embodiment, the heat transfer element1122is a cold plate and may be referred to hereinafter as cold plate1122. In the illustrated embodiment, the cold plate1122is a multi-piece cold plate including an outer cold plate1124and an inner cold plate1125received in the outer cold plate1124The inner cold plate1125is movable relative to the outer cold plate1124. The inner cold plate1125is compressible against the integrated circuit component1156. The inner cold plate1125has a thermal interface at a bottom surface of the inner cold plate1125. The thermal interface is compressed against the upper surface of the integrated circuit component1156to dissipate heat from the integrated circuit component1156. The outer cold plate1124holds the bridge assemblies1134. The outer cold plate1124is compressible against the bridge assemblies1134to press the bridge assemblies1134against the cable connector modules1104. The outer cold plate1124includes a thermal interface at the bottom of the outer cold plate1124thermally coupled to the plates1140of the bridge assemblies1134. FIG.27is a cross-sectional view of a portion of the communication system1100.FIG.27shows the load plate1120mechanically coupled to the bridge assembly1134. The bridge assemblies1134are pressed downward against the cable connector modules1104by the load plate1120. For example, the individual plates1140are pressed against the top of the connector module housing1170. The pressure on the cable connector module1104is transferred to the interposer assembly1108. For example, the connector module substrate1174compresses the interposer contacts1200between the connector module substrate1174and the package substrate1150to maintain electrical connection between the connector module substrate1174and the interposer contacts1200and between the package substrate1150and the interposer contacts1200. The bridge assemblies1134create a reliable electrical connection between the cable connector module1104and the interposer assembly1108and create a reliable electrical connection between the interposer assembly1108and the package substrate1150. The interposer contacts1200are compressed between the cable connector module1104and the package substrate1150. FIGS.28-36illustrate assembly of the communication system1100in accordance with an exemplary embodiment. FIG.28is a perspective view of a portion of the communication system1100during assembly.FIG.28shows the bolster plate1118poised for coupling to the circuit board1110. Alignment pins1117may be used to orient the bolster plate1118relative to the host circuit board1110. In an exemplary embodiment, the bolster plate1118includes openings1119that receive the board connectors1112. FIG.29is a perspective view of a portion of the communication system1100during assembly.FIG.29shows the insulator1128poised for coupling to the bolster plate1118. The insulator1128includes openings1129configured to be aligned with the openings1119of the bolster plate1118to receive the board connectors1112. The insulator1128may be a film or sheet manufactured from a dielectric material. FIG.30is a perspective view of a portion of the communication system1100during assembly.FIG.30shows the electronic package1106poised for coupling to the insulator1128and the bolster plate1118. The package substrate1150may be sized and shaped similar to the insulator1128and the bolster plate1118. For example, the package substrate1150may be rectangular. The electronic package1106is configured to be electrically connected to the board connectors1112. FIG.31is a perspective view of a portion of the communication system1100during assembly.FIG.31shows the interposer assemblies1108coupled to the package substrate1150of the electronic package1106. In the illustrated embodiment, the interposer assemblies1108are provided on all four sides of the integrated circuit component1156. Alignment features of the interposer assemblies1108may be used to align the interposer assemblies1108with the package substrate1150. FIG.32is a perspective view of a portion of the communication system1100during assembly.FIG.32shows the cable connector modules1104coupled to the interposer assemblies1108. The cable connector modules1104may be coupled to the interposer assemblies1108from above. Alignment features of the cable connector modules1104and the interposer assemblies1108are used to align the cable connector modules1104with the interposer assemblies1108. FIG.33is a top view of a portion of the communication system1100during assembly.FIG.33shows the cable connector modules1104coupled to the interposer assemblies1108. In the illustrated embodiment, the cable connector modules1104are arranged in the connector module sets1191on all four sides of the integrated circuit component1156. The cables1178extend outward in all four directions from the package substrate1150. FIG.34is a perspective view of a portion of the communication system1100during assembly.FIG.34shows the cover assemblies1130poised for coupling to the cable connector modules1104. In an exemplary embodiment, separate cover assemblies1130are provided for each connector module set1191. The fasteners1136are used to secure the covers1132to the bolster plate1118. The covers1132align the bridge assemblies1134with the cable connector modules1104. FIG.35is a perspective view of a portion of the communication system1100during assembly.FIG.35shows the cover assemblies1130coupled to the bolster plate1118over the cable connector modules1104. The fasteners1136secure the covers1132in place. FIG.36is a perspective view of a portion of the communication system1100during assembly.FIG.36shows the load plate1120poised for coupling to the cover assemblies1130. The load plate1120is secured to the cover assemblies1130using the compression hardware1116. In the illustrated embodiment, the load plate1120includes the outer cold plate1124and an inner cold plate1125. The inner cold plate1125is received in a pocket at a center of the outer cold plate1124. The inner cold plate1125may be secured to the outer cold plate1124using compression hardware1127. The inner cold plate1125is used for cooling the integrated circuit component1156. The outer cold plate1124is used for cooling the cable connector modules1104. For example, the outer cold plate1124may be thermally coupled to the cable connector modules1104via the thermal bridge is defined by the bridge assemblies1134. When the load plate1120is secured to the cover assemblies1130, the load plate1120is pressed against the bridge assemblies1134. The load plate1120compresses the bridge assemblies1134against the cable connector modules1104, which compresses the interposer contacts1200of the interposer assemblies1108. FIG.37is a perspective view of a portion of the communication system1100during assembly.FIG.37illustrates the load plate1120as a single piece cold plate rather than having the inner cold plate1125and the outer cold plate1124(shown inFIG.36). FIG.38is a perspective view of a portion of the communication system1100during assembly.FIG.37illustrates the load plate1120as a heatsink1121rather than a cold plate. The heat sink1121includes heat dissipating fins1123at the top of the heat sink1121. Airflow channels are defined between the heat dissipating fins1123. The heat sink1121is cooled by airflow that flows through the airflow channels to dissipate heat from the heat dissipating fins1123. It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with each other. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Dimensions, types of materials, orientations of the various components, and the number and positions of the various components described herein are intended to define parameters of certain embodiments, and are by no means limiting and are merely exemplary embodiments. Many other embodiments and modifications within the spirit and scope of the claims will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Further, the limitations of the following claims are not written in means-plus-function format and are not intended to be interpreted based on 35 U.S.C. § 112(f), unless and until such claim limitations expressly use the phrase “means for” followed by a statement of function void of further structure. | 44,222 |
11943888 | MODE FOR THE INVENTION FIG.1is a block diagram illustrating an electronic device101in a network environment100according to various embodiments. Referring toFIG.1, the electronic device101in the network environment100may communicate with an electronic device102via a first network198(e.g., a short-range wireless communication network), or an electronic device104or a server108via a second network199(e.g., a long-range wireless communication network). According to an embodiment, the electronic device101may communicate with the electronic device104via the server108. According to an embodiment, the electronic device101may include a processor120, memory130, an input device150, a sound output device155, a display device160, an audio module170, a sensor module176, an interface177, a haptic module179, a camera module180, a power management module188, a battery189, a communication module190, a subscriber identification module (SIM)196, or an antenna module197. In some embodiments, at least one (e.g., the display device160or the camera module180) of the components may be omitted from the electronic device101, or one or more other components may be added in the electronic device101. In some embodiments, some of the components may be implemented as single integrated circuitry. For example, the sensor module176(e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be implemented as embedded in the display device160(e.g., a display). The processor120may execute, for example, software (e.g., a program140) to control at least one other component (e.g., a hardware or software component) of the electronic device101coupled with the processor120, and may perform various data processing or computation. According to one embodiment, as at least part of the data processing or computation, the processor120may load a command or data received from another component (e.g., the sensor module176or the communication module190) in volatile memory132, process the command or the data stored in the volatile memory132, and store resulting data in non-volatile memory134. According to an embodiment, the processor120may include a main processor121(e.g., a central processing unit (CPU) or an application processor (AP)), and an auxiliary processor123(e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor121. Additionally or alternatively, the auxiliary processor123may be adapted to consume less power than the main processor121, or to be specific to a specified function. The auxiliary processor123may be implemented as separate from, or as part of the main processor121. The auxiliary processor123may control at least some of functions or states related to at least one component (e.g., the display device160, the sensor module176, or the communication module190) among the components of the electronic device101, instead of the main processor121while the main processor121is in an inactive (e.g., sleep) state, or together with the main processor121while the main processor121is in an active state (e.g., executing an application). According to an embodiment, the auxiliary processor123(e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module180or the communication module190) functionally related to the auxiliary processor123. The memory130may store various data used by at least one component (e.g., the processor120or the sensor module176) of the electronic device101. The various data may include, for example, software (e.g., the program140) and input data or output data for a command related thereto. The memory130may include the volatile memory132(e.g., DRAM, SRAM, or SDRAM) or the non-volatile memory134. The program140may be stored in the memory130as software, and may include, for example, an operating system (OS)142, middleware144, or an application146(e.g., application program). The input device150may receive a command or data to be used by other component (e.g., the processor120) of the electronic device101, from the outside (e.g., a user) of the electronic device101. The input device150may include, for example, a microphone, a mouse, or a keyboard. The sound output device155may output sound signals to the outside of the electronic device101. The sound output device155may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or playing record, and the receiver may be used for an incoming calls. According to an embodiment, the receiver may be implemented as separate from, or as part of the speaker. The display device160may visually provide information to the outside (e.g., a user) of the electronic device101. The display device160may include, for example, a display, a hologram device, or a projector and control circuitry to control a corresponding one of the display, hologram device, and projector. According to an embodiment, the display device160may include touch circuitry adapted to detect a touch, or sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of force incurred by the touch. The audio module170may convert a sound into an electrical signal and vice versa. According to an embodiment, the audio module170may obtain the sound via the input device150, or output the sound via the sound output device155or a headphone of an external electronic device (e.g., an electronic device102) directly (e.g., wiredly) or wirelessly coupled with the electronic device101. The sensor module176may detect an operational state (e.g., power or temperature) of the electronic device101or an environmental state (e.g., a state of a user) external to the electronic device101, and then generate an electrical signal or data value corresponding to the detected state. According to an embodiment, the sensor module176may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor. The interface177may support one or more specified protocols to be used for the electronic device101to be coupled with the external electronic device (e.g., the electronic device102) directly (e.g., wiredly) or wirelessly. According to an embodiment, the interface177may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface. A connecting terminal178may include a connector via which the electronic device101may be physically connected with the external electronic device (e.g., the electronic device102). According to an embodiment, the connecting terminal178may include, for example, a HDMI connector, a USB connector, a SD card connector, or an audio connector (e.g., a headphone connector). The haptic module179may convert an electrical signal into a mechanical stimulus (e.g., a vibration or a movement) or electrical stimulus which may be recognized by a user via his tactile sensation or kinesthetic sensation. According to an embodiment, the haptic module179may include, for example, a motor, a piezoelectric element, or an electric stimulator. The camera module180may capture a still image or moving images. According to an embodiment, the camera module180may include one or more lenses, image sensors, image signal processors, or flashes. The power management module188may manage power supplied to the electronic device101. According to one embodiment, the power management module188may be implemented as at least part of, for example, a power management integrated circuit (PMIC). The battery189may supply power to at least one component of the electronic device101. According to an embodiment, the battery189may include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell. The communication module190may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device101and the external electronic device (e.g., the electronic device102, the electronic device104, or the server108) and performing communication via the established communication channel. The communication module190may include one or more communication processors that are operable independently from the processor120(e.g., the application processor (AP)) and supports a direct (e.g., wired) communication or a wireless communication. According to an embodiment, the communication module190may include a wireless communication module192(e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module194(e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network198(e.g., a short-range communication network, such as Bluetooth™, wireless-fidelity (Wi-Fi) direct, or infrared data association (IrDA)) or the second network199(e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as multi components (e.g., multi chips) separate from each other. The wireless communication module192may identify and authenticate the electronic device101in a communication network, such as the first network198or the second network199, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module196. The antenna module197may transmit or receive a signal or power to or from the outside (e.g., the external electronic device) of the electronic device101. According to an embodiment, the antenna module197may include one or more antennas, and, therefrom, at least one antenna appropriate for a communication scheme used in the communication network, such as the first network198or the second network199, may be selected, for example, by the communication module190(e.g., the wireless communication module192). The signal or the power may then be transmitted or received between the communication module190and the external electronic device via the selected at least one antenna. At least some of the above-described components may be coupled mutually and communicate signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)). According to an embodiment, commands or data may be transmitted or received between the electronic device101and the external electronic device104via the server108coupled with the second network199. Each of the electronic devices102and104may be a device of a same type as, or a different type, from the electronic device101. According to an embodiment, all or some of operations to be executed at the electronic device101may be executed at one or more of the external electronic devices102,104, or108. For example, if the electronic device101should perform a function or a service automatically, or in response to a request from a user or another device, the electronic device101, instead of, or in addition to, executing the function or the service, may request the one or more external electronic devices to perform at least part of the function or the service. The one or more external electronic devices receiving the request may perform the at least part of the function or the service requested, or an additional function or an additional service related to the request, and transfer an outcome of the performing to the electronic device101. The electronic device101may provide the outcome, with or without further processing of the outcome, as at least part of a reply to the request. To that end, a cloud computing, distributed computing, or client-server computing technology may be used, for example. The electronic device according to various embodiments may be one of various types of electronic devices. The electronic devices may include, for example, a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the disclosure, the electronic devices are not limited to those described above. It should be appreciated that various embodiments of the present disclosure and the terms used therein are not intended to limit the technological features set forth herein to particular embodiments and include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B, or C”, “at least one of A, B, and C”, and “at least one of A, B, or C” may include all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, such terms as “1st” and “2nd”, or “first” and “second” may be used to simply distinguish a corresponding component from another, and does not limit the components in other aspect (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with”, “coupled to”, “connected with”, or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wiredly), wirelessly, or via a third element. As used herein, the term “module” may include a unit implemented in hardware, software, or firmware, and may interchangeably be used with other terms, for example, “logic”, “logic block”, “part”, or “circuitry”. A module may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to an embodiment, the module may be implemented in a form of an application-specific integrated circuit (ASIC). Various embodiments as set forth herein may be implemented as software (e.g., the program140) including one or more instructions that are stored in a storage medium (e.g., internal memory136or external memory138) that is readable by a machine (e.g., the electronic device101). For example, a processor (e.g., the processor120) of the machine (e.g., the electronic device101) may invoke at least one of the one or more instructions stored in the storage medium, and execute it, with or without using one or more other components under the control of the processor. This allows the machine to be operated to perform at least one function according to the at least one instruction invoked. The one or more instructions may include a code generated by a complier or a code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Wherein, the term “non-transitory” simply means that the storage medium is a tangible device, and does not include a signal (e.g., an electromagnetic wave), but this term does not differentiate between where data is semi-permanently stored in the storage medium and where the data is temporarily stored in the storage medium. According to an embodiment, a method according to various embodiments of the disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or be distributed (e.g., downloaded or uploaded) online via an application store (e.g., PlayStore™), or between two user devices (e.g., smart phones) directly. If distributed online, at least part of the computer program product may be temporarily generated or at least temporarily stored in the machine-readable storage medium, such as memory of the manufacturer's server, a server of the application store, or a relay server. According to various embodiments, each component (e.g., a module or a program) of the above-described components may include a single entity or multiple entities. According to various embodiments, one or more of the above-described components may be omitted, or one or more other components may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, according to various embodiments, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as they are performed by a corresponding one of the plurality of components before the integration. According to various embodiments, operations performed by the module, the program, or another component may be carried out sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be executed in a different order or omitted, or one or more other operations may be added. FIG.2Ais a view of the electronic device200in the unfolded state according to various embodiments of the disclosure.FIG.2Bis a view of the electronic device200in the folded state according to various embodiments of the disclosure.FIG.2Cis an exploded perspective view of the electronic device200according to various embodiments of the disclosure. With reference toFIG.2A,2B,2C, the electronic device200(e.g., electronic device101inFIG.1) may include a foldable housing210, a hinge cover230covering the foldable portion of the foldable housing210, and a display220(e.g., flexible display or foldable display) (e.g., display device160inFIG.1) disposed in the space formed by the foldable housing210. In the description, the surface on which the display220is disposed may be referred to as the front surface of the electronic device200, and the opposite side of the front surface may be referred to as the rear surface of the electronic device200. The surface surrounding the space between the front surface and the rear surface may be referred to as the side surface of the electronic device200. In one embodiment, the foldable housing210may include a first housing structure211, a second housing structure212including a sensor region215, a first rear cover213, and a second rear cover214. The foldable housing210the electronic device200are not limited to the shape or combination shown inFIGS.2A and2B, but may be implemented in various shapes or combinations. For example, in another embodiment, the first housing structure211and the first rear cover213may be formed as a single body, and the second housing structure212and the second rear cover214may be formed as a single body. In one embodiment, the first housing structure211and the second housing structure212may be disposed at both sides with respect to the folding axis (A) and may be substantially symmetrical with respect to the folding axis (A). In one embodiment, the angle or distance between the first housing structure211and the second housing structure212may vary depending upon whether the electronic device200is in the flat state or closed state, the folded state, or the intermediate state. In one embodiment, the second housing structure212includes the sensor region215where various sensors (e.g., sensor module176inFIG.1) are disposed, but may have a symmetrical shape with the first housing structure211in other regions. In one embodiment, the electronic device200may include a recess formed to accommodate the display220through a structural combination of the shapes of the first housing structure211and the second housing structure212. In one embodiment, the recess may have two or more different widths in a direction perpendicular to the folding axis (A) due to the sensor region215. For example, the recess may have a first width (W1) between a first portion211aof the first housing structure211parallel to the folding axis (A) and a first portion212aof the second housing structure212formed at the edge of the sensor region215, and have a second width (W2) between a second portion211bof the first housing structure211and a second portion211bof the second housing structure212that does not correspond to the sensor region215and is parallel to the folding axis (A). Here, the second width (W2) may be wider than the first width (W1). In other words, the recess may be formed to have the first width (W1) ranging from the first portion211aof the first housing structure211to the first portion212aof the second housing structure212(asymmetric shape), and the second width (W2) ranging from the second portion211bof the first housing structure211to the second portion212bof the second housing structure212(symmetric shape). In one embodiment, the first portion212aand the second portion212bof the second housing structure212may be located at different distances from the folding axis (A). The width of the recess is not limited to the example shown above. In various embodiments, the recess may have two or more different widths owing to the shape of the sensor region215or the asymmetry of the first housing structure211or the second housing structure212. In one embodiment, at least a portion of the first housing structure211and the second housing structure212may be made of a metal or non-metal material having a rigidity value selected to support the display232. In one embodiment, the sensor region215may be formed to have a preset area near to one corner of the second housing structure212. However, the arrangement, shape, or size of the sensor region215is not limited to the illustrated example. For example, in a certain embodiment, the sensor region215may be formed at another corner of the second housing structure212or in any region between the upper corner and the lower corner. In one embodiment, to perform various functions, the electronic device200may include components exposed to the front surface of the electronic device200through the sensor region215or through one or more openings provided in the sensor region215. The components may include, for example, at least one of a front camera, a receiver, a proximity sensor, an illuminance sensor, an iris recognition sensor, an ultrasonic sensor, or an indicator. In one embodiment, the first rear cover213may be disposed on the rear surface of the electronic device200and may have a substantially rectangular periphery. In one embodiment, at least a portion of the periphery may be wrapped by the first housing structure211. Similarly, the second rear cover250may be disposed on the rear surface of the electronic device200, and at least a portion of the periphery thereof may be wrapped by the second housing structure212. In the illustrated embodiment, the first rear cover213and the second rear cover214may have a substantially symmetrical shape with respect to the folding axis (A). In another embodiment, the first rear cover213and the second rear cover214may have various different shapes. In another embodiment, the first rear cover213may be formed as a single body with the first housing structure211, and the second rear cover214may be formed as a single body with the second housing structure212. In one embodiment, the first rear cover213, the second rear cover214, the first housing structure211, and the second housing structure212may be combined with each other so as to provide a space where various components (e.g., printed circuit board, antenna module, sensor module, and battery) of the electronic device200can be arranged. In one embodiment, one or more components may be disposed on or visually exposed via the rear surface of the electronic device200. For example, one or more components or sensors may be visually exposed through the first rear region241aof the first rear cover213. In another embodiment, one or more components or sensors may be visually exposed through the second rear region251of the second rear cover250. Here, the sensors may include a proximity sensor, a rear camera, and/or a flash. With reference toFIG.2B, the hinge cover230may be disposed between the first housing structure211and the second housing structure212so as to cover the internal components (e.g., hinge structure264inFIG.3). In one embodiment, the hinge cover230may be covered by portions of the first housing structure211and the second housing structure212or be exposed to the outside according to the operating state (e.g., flat state or folded state) of the electronic device200. For example, when the electronic device200is in the flat state as shown inFIG.2A, the hinge cover230may be covered by the first housing structure211and the second housing structure212so as not to be exposed. When the electronic device200is in the folded state (e.g., completely folded state) as shown inFIG.2B, the hinge cover230may be exposed to the outside between the first housing structure211and the second housing structure212. When the electronic device200is in the intermediate state where the first housing structure211and the second housing structure212make a certain angle, the hinge cover230may be partially exposed to the outside between the first housing structure211and the second housing structure212. In this case, the exposed portion may be less than that for the fully folded state. In one embodiment, the hinge cover230may include a curved surface. The display220may be disposed on the space formed by the foldable housing210. For example, the display220may be seated in the recess formed by the foldable housing210, and may be disposed to substantially occupy most of the front surface of the electronic device200. Hence, the front surface of the electronic device200may include the display220, a portion (e.g., edge region) of the first housing structure211close to the display220, and a portion (e.g. edge region) of the second housing structure212close to the display220. In one embodiment, the rear surface of the electronic device200may include the first rear cover213, a portion (e.g., edge region) of the first housing structure211close to the first rear cover213, the second rear cover214, and a portion (e.g. edge region) of the second housing structure212close to the second rear cover214. In one embodiment, the display220may refer to a display whose at least a portion may be deformed into a flat or curved surface. In one embodiment, the display220may include a folding region223, a first region221disposed on one side (e.g., right side of the folding region223) with respect to the folding region223, and a second region222disposed on the other side (e.g., left side of the folding region223). This demarcation of the display220is only an example, and the display220may be subdivided into plural regions (e.g., four or more regions) according to the structure or functionality. For example, in the embodiment ofFIG.2A, the area of the display220may be subdivided with respect to the folding area223or the folding axis (A) extending parallel to the y-axis. However, in another embodiment, the area of the display220may be subdivided with respect to a different folding region (e.g., folding region parallel to the x-axis) or a different folding axis (e.g., folding axis parallel to the x-axis). In one embodiment, the first region221and the second region222may have a symmetrical shape with respect to the folding region223. Although the second region222may include a notch region cut according to the presence of the sensor region215, it may have a symmetrical shape with the first region221in other portions. In other words, the first region221and the second region222may include portions with symmetrical shapes and portions with asymmetrical shapes. Next, a description is given of configurations of the first housing structure211and the second housing structure212and regions of the display220according to the operating state (e.g. flat state or folded state) of the electronic device200. In one embodiment, when the electronic device200is in the flat state (e.g., state ofFIG.2A), the first housing structure211and the second housing structure212may make an angle of 180 degrees, and the first region221and the second region222of the display220may be disposed to face in the same direction. In addition, the folding region223may be coplanar with the first region221and the second region222. In one embodiment, when the electronic device200is in the folded state (e.g., state ofFIG.2B), the first housing structure211and the second housing structure212may be disposed to face each other. The first region221and the second region222of the display220may face each other, making a narrow angle (e.g., between 0 degrees and 10 degrees). At least a portion of the folding area223may form a curved surface with a preset curvature. In one embodiment, when the electronic device200is in the intermediate state, the first housing structure211and the second housing structure212may be disposed to make a certain angle. The first region221and the second region222of the display220may form an angle greater than that for the folded state and less than that for the flat state. At least a portion of the folding area223may form a curved surface with a preset curvature. This curvature may be less than that for the folded state. With reference toFIG.2C, in one embodiment, the electronic device200may include a display unit250, a bracket assembly260, printed circuit board270, a first housing structure211, a second housing structure212, a first rear cover213, and a second rear cover214. In the description, the display230may be referred to as a display unit250, display module, or display assembly. The display unit250may include a display220, and at least one plate251or layer on which the display220is seated. In one embodiment, the plate251may be disposed between the display220and the bracket assembly260. The display220may be disposed on at least a portion of one surface (e.g., upper surface inFIG.2C) of the plate251. The plate251may be formed in a shape corresponding to the display220. For example, a portion of the plate251may be formed in a shape corresponding to the notch region225of the display220. The bracket assembly260may include a first bracket261, a second bracket262, a hinge structure264disposed between the first bracket261and the second bracket262, a hinge cover230to cover the hinge structure264when viewed from the outside, and a wiring member263(e.g., flexible printed circuit board (FPCB)) that crosses the first bracket261and the second bracket262. According to various embodiments, the wiring member263may electrically connect at least one component disposed on the first bracket261and at least one component disposed on the second bracket262. The wiring member263may be a transmission path for transmitting and receiving a signal between the first bracket261and the second bracket262. For example, the wiring member263may be used for transmitting a signal between a first PCB disposed on the first bracket261and a second PCB disposed on the second bracket262. For example, the wiring member263may be connected to the first PCB and the second PCB based on a connector. The wiring member263may include a radio frequency transmission line (hereinafter, may be referred to as an RF line), and the wiring member263may be formed of a member having a bending property. In one embodiment, the bracket assembly260may be disposed between the plate251and the printed circuit board270. For example, the first bracket261may be disposed between the first region221of the display220and the first printed circuit board271. The second bracket262may be disposed between the second region222of the display220and the second printed circuit board272. In one embodiment, at least a portion of the wiring member263and the hinge structure264may be disposed within the bracket assembly260. The wiring member263may be disposed in a direction crossing the first bracket261and the second bracket262(e.g., x-axis direction). The wiring member263may be disposed in a direction (e.g., x-axis direction) perpendicular to the folding axis (e.g., y-axis or folding axis (A) inFIG.2) of the folding region223. The printed circuit board270may include, as described above, the first printed circuit board271disposed on the side of the first bracket261, and the second printed circuit board272disposed on the side of the second bracket262. The first printed circuit board271and the second printed circuit board272may be disposed inside the space formed by the bracket assembly260, the first housing structure211, the second housing structure212, the first rear cover213, and the second rear cover214. Various components for implementing functions of the electronic device200may be mounted on the first printed circuit board271and the second printed circuit board272. In one embodiment, in a state where the display unit250is coupled to the bracket assembly260, the first housing structure211and the second housing structure212may be assembled to each other so as to be coupled to both sides of the bracket assembly260. As described below, the first housing structure211and the second housing structure212may be coupled to the bracket assembly260by being slid on both sides of the bracket assembly260. In one embodiment, the first housing structure211may include a first rotary support surface211c, and the second housing structure212may include a second rotary support surface212ccorresponding to the first rotary support surface211c. The first rotary support surface211cand the second rotary support surface212cmay include a curved surface corresponding to the curved surface included in the hinge cover230. In one embodiment, when the electronic device200is in the flat state (e.g., state ofFIG.2A), the first rotary support surface211cand the second rotary support surface212cmay cover the hinge cover230so that the hinge cover230may be not or minimally exposed to the rear surface of the electronic device200. When the electronic device200is in the folded state (e.g., state ofFIG.2B), the first rotary support surface211cand the second rotary support surface212cmay rotate along the curved surface included in the hinge cover230so that the hinge cover230may be maximally exposed to the rear surface of the electronic device200. FIG.3Ais a diagram illustrating a wiring member310disposed on a folding axis in an electronic device according to various embodiments,FIG.3Bis a diagram illustrating one surface and the other surface of the wiring member310, andFIG.3Cis a diagram illustrating a slit structure formed corresponding to a bending area of the wiring member300. Referring toFIG.3A, the electronic device (e.g., the electronic device101inFIG.1) may include at least one wiring member310(e.g., a flexible printed circuit board (FPCB)) for electrically connecting at least one component disposed on the first bracket261and at least one component disposed on the second bracket262. The wiring member310may be disposed to correspond to a direction (e.g., the x-axis direction) at least partially crossing the hinge structure264. There may be a plurality of wiring members310, which may be disposed to at least partially cross the hinge structure264. The wiring member310has a bending property, and thus can be folded or unfolded depending on a folded form of the hinge structure264. According to an embodiment, in the electronic device101, the first bracket261and the second bracket262may be folded symmetrically, based on the hinge structure264and the hinge cover230. According to an embodiment, the wiring member310may be disposed in a direction (e.g., the x-axis direction) perpendicular to the folding axis (e.g., the y-axis or the folding axis (A) inFIG.2A). FIG.3Bis a diagram illustrating one (e.g., front) surface and the other (e.g., rear) surface of the wiring member310. InFIG.3B, (a) shows the front surface of the wiring member310, and (b) shows the rear surface of the wiring member310. The wiring member310may include a first connector311corresponding to one direction and a second connector312corresponding to another direction. The wiring member310may be a member that electrically connects the first bracket261and the second bracket262of an electronic device (e.g., the electronic device101inFIG.1). For example, the first connector311of the wiring member310may be connected to a component disposed on the first bracket261, and the second connector312of the wiring member310may be connected to a component disposed on the second bracket262. The wiring member310may be a transmission path that electrically connects the first bracket261and the second bracket262and thereby transmits and receives a signal. According to an embodiment, the wiring member310may include at least one slit structure340corresponding to a bending area320in which the electronic device101is folded. FIG.3Cis a diagram illustrating the slit structure340formed corresponding to the bending area of the wiring member310. According to an embodiment, the wiring member310may include one or more RF lines333and334, one or more ground (GND) members330,331, and332, and a tape335. The wiring member310may be included in a flexible printed circuit board (FPCB), which may have a bending property. According to an embodiment, the one or more RF lines333and334and the one or more ground (GND) members330,331, and332may be formed based on a bendable material in order to have a bending property. According to an embodiment, the one or more RF lines333and334are paths of transmitting and receiving signals, and may transmit and receive signals between the first PCB and the second PCB. The one or more ground members330,331, and332may have at least one via336formed partially, and may perform a ground (GND) function through the via336. According to an embodiment, at least one of the one or more RF lines333and334and the one or more ground (GND) members330,331, and332may be attached by the adhesive member335(e.g., an adhesive tape). According to various embodiments, the wiring member310may have the slit structure340formed to correspond to the folded area (e.g., a bending area). Because of the slit structure340, the one or more RF lines333and334may be formed to have a thin thickness, and thereby durability against bending may be improved. The wiring member310according to various embodiments may maintain performance of the RF lines333and334related to transmission and reception of signals while improving durability against bending. FIG.4is a graph showing signal transmission performance of a radio frequency transmission line having a bending property according to various embodiments. Referring toFIG.4, shown are a signal transmission performance410based on a conventional radio frequency transmission line and a signal transmission performance420based on a radio frequency transmission line including a slit structure. According to an embodiment, the radio frequency transmission line (hereinafter referred to as an RF line) may have a micro strip shape implemented with two flexible copper clad laminates (FCCLs) or a strip shape implemented with three FCCLs.FIG.4shows the signal transmission performance410of the conventional RF line and the signal transmission performance420of the RF line including the slit structure, based on the microstrip shape RF line. According to various embodiments, even if the RF line includes the slit structure, the signal transmission performance can be maintained. FIGS.5A and5Bare diagrams illustrating a structure of a wiring member a micro strip shape according to various embodiments. According to an embodiment, the wiring member (e.g., the wiring member310inFIG.3A) may be implemented in the micro strip shape based on two substrates (e.g., a flexible copper clad laminate (FCCL)). For example, the wiring member of the micro strip shape may be manufactured by stacking two substrates, and the two substrates may be attached using an adhesive member. Referring toFIG.5A, shown are a plan view (a), a side view (b), and a cross-sectional view (c) of the wiring member310of the micro strip shape. Referring to the plan view (a) of the wiring member310, two cross sections (e.g., A-A′ and B-B′) are shown. The side view (b) shows the wiring member310when cut based on the B-B′ cross-section, and the cross-sectional view (c) shows the wiring member310when cut based on the A-A′ cross-section. Referring to the plan view (a), the wiring member310may include an RF line510(e.g., the RF lines333and334inFIG.3C) and one or more ground members511and512. One surface of the RF line510and the one or more ground members511and512may be at least partially attached by an adhesive member. According to an embodiment, the wiring member310may have a slit structure (e.g., a slit structure521in the side view (b) or an opening) formed at least partially corresponding to a bending area520where the RF line510is bendable. For example, the wiring member310of the micro strip shape may be formed by stacking two substrates, and may be formed to have a thickness corresponding to one substrate in the bending area520. The slit structure521may be formed such that the wiring member310has a thickness corresponding to one substrate. According to an embodiment, in the wiring member310of the micro strip shape, two substrates are stacked, and the slit structure521may be processed, using a laser and a drill, to form a thickness corresponding to one substrate in the bending area520. According to an embodiment, the wiring member310may be thinner in the bending area520, and thus durability against bending may be improved. According to an embodiment, even if the thickness is reduced in the bending area520, the signal transmission performance of the wiring member310may not be deteriorated. According to an embodiment, the one or more ground members511and512may have at least one via513formed partially, and may perform a ground (GND) function to each substrate through the via513. Referring to the side view (b), shown is the wiring member310in which two substrates (FCCLs) (e.g., a first substrate531and a second substrate533) are stacked. The first substrate531may function as the RF line510, and the second substrate533may function as a ground layer (GND). For example, the first substrate531may include the RF line510. The first substrate531and the second substrate533may be stacked using an adhesive member540. The wiring member310may have the slit structure521formed at least partially corresponding to the bending area520where the RF line510is bendable. According to an embodiment, in the bending area520, the RF line510may be formed to have a thickness corresponding to one substrate. According to an embodiment, the first substrate531and the second substrate533may be connected through the at least one via513, and the second substrate533may perform a ground (GND) function, based on the at least one via513. Referring to the cross-sectional view (c), the RF line510corresponding to the bending area520may be disposed in a central portion of the first substrate531. The one or more ground members511and512may be disposed on both left and right sides of the first substrate531. According to various embodiments, the wiring member310may be formed to have a thickness corresponding to one substrate (e.g., the thickness of the first substrate531) in the bending area520, and the second substrate533may have the slit structure521at least partially formed therein. According to various embodiments, the wiring member310of the micro strip shape may have the slit structure521formed to correspond to the bending area520. According to an embodiment, the wiring member310may be formed to have a thickness corresponding to one substrate (e.g., the first substrate531) in the bending area520. According to an embodiment, the other substrate (e.g., the second substrate533) may be formed in a shape having the slit structure521corresponding to the bending area520. FIG.5Bis a diagram specifically showing the shape of the micro strip shape wiring member.FIG.5Bmay be a view corresponding to the side view (b) of the wiring member shown inFIG.5A. Referring toFIG.5B, the micro strip shape wiring member has a form in which two substrates (FCCLs) (e.g., the first substrate531and the second substrate533) are stacked. The first substrate531includes an RF line (e.g., the RF line510inFIG.5A) and may thereby function as a signal transmission line, and the second substrate533may function as a ground member (GND). The first and second substrates531and533may include a copper (CU)-based conductive member (CU+Fill plating) and a polyimide film (base PI). According to an embodiment, a first cover layer561including a polyimide film (coverlay PI) may be attached to one surface (e.g., an upper surface) of the first substrate531, and a second cover layer562including a polyimide film (coverlay PI) may be attached to one surface (e.g., a lower surface) of the second substrate533. The first cover layer561and the second cover layer562may include an adhesive member, and may be attached to the substrate by using the adhesive member. In the electronic device101according to various embodiments, the RF line based on the first substrate531may be formed in the bending area (e.g., the bending area520inFIG.5A). The thickness of the wiring member corresponding to the bending area may be about 67.5 μm corresponding to one substrate (e.g., the first substrate531). For example, summing up all the thicknesses of the polyimide film (coverlay PI) (about 12.5 μm thick) and the adhesive member (about 15 μm thick), included in the first cover layer561, and the copper (CU)-based conductive member (about 15 μm thick) and the polyimide film (base PI) (about 25 μm thick), included in the first substrate531, may be about 67.5 μm. According to an embodiment, the wiring member corresponding to the bending area may be formed based on the first cover layer561and the first substrate531, and may include the polyimide film (coverlay PI), the adhesive member, the copper (CU)-based conductive member, and the polyimide film (base PI). The wiring member of the electronic device101according to various embodiments may be formed to have a thickness corresponding to one substrate (e.g., the first substrate531) in the bending area520. Even if it is formed to have a thickness corresponding to one substrate, the signal transmission performance of the wiring member can be maintained. The electronic device101according to various embodiments may include the wiring member formed to have a thickness corresponding to one substrate in the bending area520while maintaining signal transmission performance. According to various embodiments, the second substrate533may have at least one via513(e.g., the via513inFIG.5A) formed at least in part, and the first substrate531and the second substrate533may be connected through the via513. The second substrate533may perform a ground (GND) function for the first substrate531through the via513. FIGS.6A and6Bare diagrams illustrating a structure of a wiring member of a strip shape according to various embodiments. According to an embodiment, the wiring member (e.g., the wiring member310inFIG.3A) may be implemented in the strip shape based on three substrates (e.g., a flexible copper clad laminate (FCCL)). For example, the wiring member of the strip shape may be manufactured by stacking three substrates, and the three substrates may be attached using an adhesive member. Referring toFIG.6A, shown are a plan view (a), a side view (b), and a cross-sectional view (c) of the wiring member310of the strip shape. Referring to the plan view (a) of the wiring member310, two cross sections (e.g., A-A′ and B-B′) are shown. The side view (b) shows the wiring member310when cut based on the B-B′ cross-section, and the cross-sectional view (c) shows the wiring member310when cut based on the A-A′ cross-section. Referring to the plan view (a), the wiring member310may include an RF line610(e.g., the RF lines333and334inFIG.3C) and one or more ground members611and612. One surface of the RF line610and the one or more ground members611and612may be at least partially attached by an adhesive member. According to an embodiment, the wiring member310may have a slit structure (e.g., a first slit structure621and a second slit structure622in the side view (b) or an opening) formed at least partially corresponding to a bending area620where the RF line610is bendable. For example, the wiring member310of the strip shape may be formed by stacking three substrates, and may be formed to have a thickness corresponding to one substrate in the bending area620. One or more slit structures621and623may be formed such that the wiring member310has a thickness corresponding to one substrate. According to an embodiment, in the wiring member310of the strip shape, three substrates are stacked, and two slit structures (e.g., the first slit structure621and the second slit structure623) may be processed, using a laser and a drill, to form a thickness corresponding to one substrate in the bending area620. For example, three substrates may be stacked in the order of a first substrate631, a second substrate633, and a third substrate635. The first slit structure621may be processed corresponding to the first substrate631, and the second slit structure623may be processed corresponding to the third substrate635. According to an embodiment, the wiring member310may be thinner in the bending area620, and thus durability against bending may be improved. According to an embodiment, even if the thickness is reduced in the bending area620, the signal transmission performance of the wiring member310may not be deteriorated. According to an embodiment, the one or more ground members611and612may have at least one via613formed partially, and may perform a ground (GND) function to each substrate through the via613. Referring to the side view (b), shown is the wiring member310in which three substrates (FCCLs) (e.g., the first substrate631, the second substrate633, and the third substrate635) are stacked. The second substrate633may function as the RF line610, and the first and third substrates631and635may function as ground layers (GND). For example, the second substrate633may include the RF line610. The first substrate631, the second substrate633, and the third substrate635may be stacked using adhesive members641and642. For example, the first substrate631, the second substrate633, and the third substrate635may be sequentially stacked. In this case, the first substrate631and the second substrate633may be bonded using the first adhesive member641, and the second substrate633and the third substrate635may be bonded using the second adhesive member642. The wiring member310may have two slit structures621and623formed at least partially corresponding to the bending area620where the RF line610is bendable. For example, the first slit structure621corresponding to the first substrate631and the second slit structure623corresponding to the third substrate635may be formed. According to an embodiment, in the bending area620, the RF line610may be formed to have a thickness corresponding to one substrate. According to an embodiment, the first substrate631and the second substrate633may be connected through at least one via613(e.g., the first via), and the second substrate633and the third substrate635may be connected through at least one via613(e.g., the second via). According to an embodiment, the second substrate533may be connected to the first substrate631through the first via, and may perform a ground (GND) function, based on the first substrate631. According to an embodiment, the second substrate533may be connected to the third substrate635through the second via, and may perform a ground (GND) function, based on the third substrate635. Referring to the cross-sectional view (c), the RF line610corresponding to the bending area620may be disposed in a central portion of the second substrate633. The one or more ground members611and612may be disposed on both left and right sides of the second substrate633. According to various embodiments, the wiring member310may be formed to have a thickness corresponding to one substrate (e.g., the thickness of the second substrate633) in the bending area620, and each of the first and third substrates631and635may have the slit structure (e.g., the first slit structure621and the second slit structure623) at least partially formed therein. For example, the first substrate631may have the first slit structure621at least partially formed, and the third substrate635may have the second slit structure623at least partially formed. According to various embodiments, the wiring member310of the strip shape may have two slit structures (e.g., the first slit structure621and the second slit structure623) formed to correspond to the bending area620. According to an embodiment, the wiring member310may be formed to have a thickness corresponding to one substrate (e.g., the second substrate633) in the bending area620. According to an embodiment, the first and third substrates631and635may be formed in a shape having at least one slit structure (e.g., the first slit structure621and the second slit structure623) corresponding to the bending area620. FIG.6Bis a diagram specifically showing the shape of the strip shape wiring member.FIG.6Bmay be a view corresponding to the side view (b) of the wiring member shown inFIG.6A. Referring toFIG.6B, the strip shape wiring member has a form in which three substrates (e.g., the first substrate631, the second substrate633, and the third substrate635) are stacked. The first and third substrates631and635may function as ground members, and the second substrate531including an RF line (e.g., the RF line610inFIG.6A) may function as a signal transmission line. The first, second, and third substrates631,633, and635may include a copper (CU)-based conductive member (CU+Fill plating) and a polyimide film (base PI). According to an embodiment, a first cover layer661including a polyimide film (coverlay PI) may be attached to one surface (e.g., an upper surface) of the first substrate631, and a second cover layer662including a polyimide film (coverlay PI) may be attached to one surface (e.g., a lower surface) of the third substrate635. The first cover layer661and the second cover layer662may include an adhesive member, and may be attached to the substrate by using the adhesive member. In the electronic device101according to various embodiments, the RF line based on the second substrate633may be formed in the bending area (e.g., the bending area620inFIG.6A). The thickness of the wiring member corresponding to the bending area may be about 67.5 μm corresponding to one substrate (e.g., the second substrate633). For example, summing up all the thicknesses of the copper (CU)-based conductive member (about 15 μm thick) and the polyimide film (base PI) (about 25 μm thick), included in the second substrate633, the adhesive member (about 15 μm thick) between the first and second substrates631and633, and the polyimide film (coverlay PI) (about 12.5 μm thick), included in the first cover layer661, and may be about 67.5 μm. According to an embodiment, the wiring member corresponding to the bending area may be formed based on the second substrate633, and may include the copper (CU)-based conductive member and the polyimide film (base PI), included in the second substrate633, the adhesive member between the first substrate631and the second substrate633, and the polyimide film (base PI) included in the first substrate631. The wiring member of the electronic device101according to various embodiments may be formed to have a thickness corresponding to one substrate (e.g., the second substrate633) in the bending area620. According to various embodiments, the first substrate631corresponding to the bending area620may include the first slit structure621, and the third substrate635corresponding to the bending area620may include the second slit structure623. Even if the wiring member is formed to have a thickness corresponding to one substrate in the bending area620, the signal transmission performance of the wiring member can be maintained. The electronic device101according to various embodiments may include the wiring member formed to have a thickness corresponding to one substrate in the bending area620while maintaining signal transmission performance. According to various embodiments, at least one first via613_1(e.g., the via613inFIG.6A) may be formed between the first substrate631and the second substrate633, and the first and second substrates631and633may be connected through the first via613_1. The second substrate633may perform a ground (GND) function for the first substrate631through the first via613_1. According to various embodiments, at least one second via6132(e.g., the via613inFIG.6A) may be formed between the second substrate633and the third substrate635, and the second and third substrates633and635may be connected through the second via613_2. The second substrate633may perform a ground (GND) function for the third substrate635through the second via613_2. An electronic device according to various embodiments of the disclosure may include a first housing (e.g., the first bracket261inFIG.2C), a hinge part (e.g., the hinge structure264inFIG.2C) having a first surface connected to the first housing261, a second housing (e.g., the second bracket262inFIG.2C) connected to a second surface of the hinge part264opposite to the first surface, and a wiring member (e.g., the wiring member310inFIG.3) electrically connecting the first housing261and the second housing262. The wiring member310may be folded or unfolded based on the hinge part264, and may have a slit (e.g., the slit structure521inFIG.5B) formed to correspond to at least a portion of the folded or unfolded bending area (e.g., the bending area520inFIG.5A). According to various embodiment, the wiring member310may be formed based on a flexible printed circuit board (FPCB) which is bendable. According to various embodiment, the wiring member310may include a micro strip shape wiring member formed based on two substrates (e.g., the first substrate531and the second substrate533inFIG.5B) and a strip shape wiring member formed based on three substrates (e.g., the first substrate631, the second substrate633, and the third substrate635inFIG.6B). According to various embodiment, the micro strip shape wiring member may be formed based on a first substrate531and a second substrate533, and the first substrate531and the second substrate533may be stacked. According to various embodiment, the micro strip shape wiring member may include at least one radio frequency transmission line (RF line)510formed corresponding to the first substrate531, and a slit521formed corresponding to the second substrate533. According to various embodiment, the slit521may be formed to correspond to the bending area520in which the wiring member is folded or unfolded. According to various embodiment, the slit521may be formed by additional processing corresponding to the second substrate533in a state in which the first substrate531and the second substrate533are stacked. According to various embodiment, the micro strip shape wiring member may include at least one radio frequency transmission line510formed based on the first substrate531to correspond to the bending area, and a thickness of the wiring member corresponding to the bending area520may be determined corresponding to the first substrate531. According to various embodiment, the first substrate531and the second substrate533may be formed based on a copper (CU)-based conductive member (CU+Fill plating) and a polyimide film (PI). According to various embodiment, the strip shape wiring member may be formed based on a first substrate631, a second substrate633, and a third substrate635, and the first substrate631, the second substrate633, and the third substrate635may be stacked in order. According to various embodiment, the strip shape wiring member may include at least one radio frequency transmission line (RF line)610formed corresponding to the second substrate633, a first slit621formed corresponding to the first substrate631, and a second slit623formed corresponding to the third substrate635. According to various embodiment, the first and second slits621and623may be formed to correspond to the bending area620in which the wiring member is folded or unfolded. According to various embodiment, in a state in which the first substrate631, the second substrate633, and the third substrate635are stacked, the first slit621may be formed by additional processing corresponding to the first substrate631, and the second slit623may be formed by additional processing corresponding to the third substrate635. According to various embodiment, the strip shape wiring member may include at least one radio frequency transmission line610formed based on the second substrate633to correspond to the bending area620, and a thickness of the wiring member corresponding to the bending area620may be determined corresponding to the second substrate633. According to various embodiment, the first substrate, the second substrate, and the third substrate may be formed based on a copper (CU)-based conductive member (CU+Fill plating) and a polyimide film (PI). | 62,333 |
11943889 | DETAILED DESCRIPTION Referring toFIG.1,FIG.2, andFIG.3, an embodiment of the present disclosure discloses a server case100, including a case10, a drawer body30, and a adjustable device50. In this embodiment, the case10is a rack server case, in which at least one rack server is received. The height of the rack server is measured in U (1 U equals to 1.75 inches, or equals to 44.45 millimeters). The case10receives, for example, but not limited to, rack servers of specifications ranging from 1 U to 7 U. In this embodiment, a hard disk device70is assembled in the drawer body30. In this embodiment, the adjustable device50may be, for example, provided with a fan module90. In this embodiment, as shown inFIG.3, when the drawer body30is pulled out of the server case100having the adjustable device, the adjustable device50moves accordingly, and the distance between the fan module90and the hard disk device70is changed, to attenuate acoustic wave energy, reduce noise generated by an airflow from the fan module90on the hard disk device70, and at the same time maintaining the heat dissipation effect of the server case. The fan module90may generate the airflow by suction or blowing. A suction fan module will be illustrated as an example in the following specification, but the present disclosure is not limited thereto. The adjustable device50may be an independent kit. One or more adjustable device50may be configured to match cases10of different sizes, for example, but not limited to, server cases with different heights such as 1 U, 2 U, and 3 U, or server cases with different widths. Refer toFIG.1,FIG.2,FIG.3andFIG.4. As shown inFIG.2andFIG.3,FIG.2shows the drawer body30received in the case10, andFIG.3shows the drawer body30located outside the case10. The hard disk device70is assembled in the drawer body30. The drawer body30is received in the case10. Specifically, the drawer body30can be selectively received in the case10, or the drawer body30received in the case10can be pulled out of the case10, so that at least a part of the drawer body30is detached from the case10. The hard disk device70can be repaired or replaced by simply pulling the drawer body30out of the case10. The adjustable device50includes a first end50A and a second end50B, the second end50B is connected to the drawer body30, and a distance between the first end50A and the second end50B is changeable. The drawer body30received in the case10is moved until at least a part of the drawer body is located outside the case, to change the distance between the first end50A and the second end50B of the adjustable device50. Specifically, as shown inFIG.2andFIG.3, the case10includes a receiving end10A and an open end10B, and when the drawer body30is received in the case10, the first end50A is close to the receiving end10A of the case10, or presses against the receiving end10A of the case10. When a part of the drawer body30is detached from the case10, the first end50A is far from the receiving end10A of the case10, and is close to or presses against the open end10B of the case10. Because the second end50B of the adjustable device50is connected to the drawer body30, the adjustable device50is driven to moved when the drawer body30is pulled out. The adjustable device50is located between the case10and the drawer body30. As shown inFIG.4andFIG.5, a adjustable structure57is connected to the first end50A and the second end50B, and the distance between the first end50A and the second end50B is changeable. Specifically, the first end50A can be moved relative to the second end50B, to change the distance between the first end50A and the second end50B. In this embodiment, the server case100further includes a fan frame92. The fan frame92is disposed at the first end50A of the adjustable device50, and the fan module90is supported by the fan frame92. In this embodiment, the adjustable device50further includes a roller59. The roller59is disposed on the fan frame92, but the present disclosure is not limited thereto. The adjustable device50can be moved in the case10by means of the roller59. For example, referring toFIG.3andFIG.4, when the drawer body30is detached from the case10, the first end50A of the adjustable device50is close to or presses against the open end10B of the case10, and due to an acting force provided by the adjustable structure57, the first end50A is far from the second end50B. In this embodiment, the adjustable device50further includes a stopper93. The stopper93is disposed at the first end50A of the adjustable device50. The case10includes an opening portion11located at the receiving end10A. When the first end50A passes through the opening portion11, the stopper93presses against the receiving end10A of the case10, so that the first end50A is close to the second end50B. For example, the stopper93protrudes from the fan frame92at the first end50A, and when the drawer body30presses back into the case10, a part of the fan frame92passes through the opening portion11formed on the case10, to cause the stopper93to press against the receiving end10A of the case10. The stopper93is influenced by the pressing force from the receiving end10A and the force that pushes the drawer body back into the case10, so that the first end50A approaches the second end50B due to the adjustable structure57. Specifically, in the server case100, the hard disk device70can be assembled in the drawer body30, and the drawer body30is received in the case10. The second end50B of the adjustable device50is connected to the drawer body30, and the distance between the first end50A and the second end50B is changeable. The drawer body30can be selectively received in the case10, or the drawer body30received in the case10can be pulled out of the case10. When the drawer body30is pulled out, the unenclosed space weakens the airflow conveyance effect of the fan module90, leading to a degraded heat dissipation effect. In this case, the rotation speed of the fan module90needs to be increased to maintain the heat dissipation effect. However, as the rotation speed of the fan module90increases, the vibration and noise generated increase accordingly, affecting the read performance of the hard disk device70. Therefore, when the drawer body30is pulled out, the adjustable device50is also pulled, which moves along with the drawer body30, so that the adjustable structure57causes the first end50A to move relative to the second end50B, to increase the distance between the fan module90and the hard disk device70. When the rotation speed of the fan module90increases, the vibration and noise can be reduced by increasing the distance between the fan module90and the hard disk device70. In this embodiment, the adjustable device50includes a first body53and a second body55. The first body53is correspondingly located at the first end50A, and the second body55is correspondingly located at the second end50B. The adjustable structure57is connected to the first body53and the second body55and provides an acting force to change a distance between the first body53and the second body55. As shown inFIG.5, the adjustable structure57may cause the first body53to move relative to the second body55in various manners. As shown inFIG.5, in this embodiment, the adjustable structure57includes a adjustable rod component570. The adjustable rod component570is connected to the first body53and the second body55and provides an acting force to cause the first body53to move relative to the second body55. For example, referring toFIG.2andFIG.3, when the drawer body30is received in the case10, the drawer body30presses against the open end10B of the case10, so that the drawer body30is squeezed, and the adjustable rod component570contracts, so that the first body53and the second body55approach each other. When the drawer body30is pulled out of the case10by an external force, the pressing force exerted by the open end10B of the case10on the drawer body30is released, and the adjustable rod component570provides the acting force to cause the first body53to move away from the second body55. As shown inFIG.5, in this embodiment, the adjustable rod component570is a pneumatic rod, which is connected to the first body53and the second body55. As shown inFIG.4, due to limited space in the case10, the pneumatic rod is diagonally connected to the first body53and the second body55to take up as small space as possible, but the present disclosure is not limited thereto. Provided that the case10has enough space, the pneumatic rod may also be horizontally connected to the first body53and the second body55. In this embodiment, the pneumatic rod continuously provides a thrust to push the first body53away from the second body55. When the drawer body30is received in the case10, the drawer body30is squeezed, and the pneumatic rod is contracted by the pressing force exerted by the open end10B of the case10on the drawer body30. When the drawer body30is pulled out of the case10, the pneumatic rod, which is no longer limited by the pressing force, causes the first body53to move away from the second body55. As shown inFIG.6, in another embodiment, the adjustable rod component570is a adjustable rod571and a spring572, where the spring572is located between the first body53and the second body55, and the adjustable rod571is inserted to extend through the spring572. The adjustable rod571includes a first end571aand a second end571b. The second end571bis connected to the second body55, and the first end571ais inserted to extend through the first body53. In this another embodiment, the first end571aof the adjustable rod571extends from the first body53to a shaft receiving space921of the fan frame92. When the first body53is far from the second body55, the first end571apresses against the first body53; when the first body53is close to the second body55, the first end571apresses against the fan frame92. In this another embodiment, the telescoping rod571is inserted to extend through the spring572, and the spring572continuously provides an elastic force to push the first body53away from the second body55. When the drawer body30is received in the case10, the drawer body30is squeezed, and the spring572is contracted by the pressing force exerted by the open end10B of the case10on the drawer body30. When the drawer body30is pulled out of the case10, the spring572, which is no longer limited by the pressing force, causes the first body53to move away from the second body55. Referring again toFIG.5, in the embodiment shown inFIG.5, the adjustable structure57includes a adjustable sleeve573. The adjustable sleeve573connects the first body53at the first end50A to the second body55at the second end50B. The adjustable sleeve573includes a plurality of bending portions575. When the first body53is far from the second body55, that is, when at least a part of the drawer body30is located outside the case10, the adjustable sleeve573is in an unfolded state, and the plurality of bending portions575are unfolded. When the first body53is close to the second body55, that is, when the drawer body30is received in the case10, the adjustable sleeve573is in a contracted state and the plurality of bending portions575are folded up. In this embodiment, because the drawer body30is not in a sealed state, the fan module90is driven to move away from the hard disk device70when the drawer body30is detached from the case10. As a result, it is difficult for the airflow from the fan module90to reach the hard disk device70. In order not to reduce the heat dissipation efficiency, the first body53and the second body55are connected by the adjustable sleeve573. That is to say, the adjustable sleeve573is used to enclose the airflow from the first body53to the second body55, to prevent leakage of the airflow. In this embodiment, when the distance between the first body53and the second body55is changed by the adjustable rod component570, the adjustable sleeve573includes a plurality of bending portions575, to enable the adjustable sleeve573to change its length with the adjustable rod component570, so that the adjustable sleeve573can change between the unfolded state and the contracted state. When the first body53is far from the second body55, that is, when the adjustable sleeve573is in the unfolded state, the bending portions575are unfolded to elongate the adjustable sleeve573, and the bending portions575are unfolded to form an approximately V-shape. When the first body53is close to the second body55, that is, when the adjustable sleeve573is in the contracted state, the bending portions575are bended to shorten the adjustable sleeve573. As shown inFIG.5, the adjustable device50further includes a limiting component56. The limiting component56has a continuous cross structure561. The first body53includes a first limiting hole531and a first pivotal connection hole532. The first limiting hole531and the first pivotal connection hole532are located on two opposite sides of the first body53. The second body55includes a second limiting hole551and a second pivotal connection hole552. The second limiting hole551and the second pivotal connection hole552are located on two opposite sides of the second body55. The continuous cross structure561includes two movable portions562and two fixed portions563. The two movable portions562are respectively movably inserted to extend through the first limiting hole531and the second limiting hole551. The two fixed portions563are respectively pivotally connected to the first pivotal connection hole532and the second pivotal connection hole552. When the first body53moves away from the second body55, the two movable portions562move toward the two fixed portions563, and the two movable portions562respectively press against one end of the first limiting hole531and one end of the second limiting hole551. When the first body53moves toward the second body55, the two movable portions562move away from the two fixed portions563, and the two movable portions562respectively press against the other end of the first limiting hole531and the other end of the second limiting hole551. A maximum elongation distance and a minimum contraction distance of the adjustable rod component570can be limited by the continuous cross structure561. Referring again toFIG.6, in another embodiment, the adjustable structure57includes a slidable portion576and a guide portion577, where the slidable portion576is disposed on the first body53, the guide portion577is disposed on the second body55, and the first body53and the second body55are slidably connected to each other by the slidable portion576and the guide portion577. In this another embodiment, the slidable portion576is a slide rail, and the guide portion577is a slide block, but the present disclosure is not limited thereto. The slidable portion576may also be a slide block and the slide block577may also be a slide rail. In this another embodiment, the guide portion577on the second body55is engaged with the slidable portion576on the first body53, so that the first body53and the second body55can slide relative to each other. In this another embodiment, the adjustable structure57is a combination of multiple cubes, and relative positions of the first body53and the second body55can be changed by the slidable portion576and the guide portion577. To enclose the airflow generated by the fan module90, the second body55wraps the first body53so that the airflow from the first body53to the second body55does not leak easily, thereby maintaining the heat dissipation effect of the fan module90for the hard disk device70. Referring again toFIG.2andFIG.3, in the embodiments shown inFIG.2andFIG.3, the adjustable device50further includes a driver, which is electrically connected to the adjustable rod component570. The case10further includes a sensor12. The sensor12is in signal connection with the driver. When the sensor12detects a signal and transmits the signal to the driver, the driver drives the adjustable rod component570to move, to cause the first body53to move relative to the second body55. In this embodiment, the adjustable rod component570is an electrically-driven pneumatic rod, the elongation and shortening of which are controlled by signals. When the sensor12detects that the drawer body30is detaching from the case10, the sensor12transmits a signal to the driver, and the driver drives the adjustable rod component570to cause the first body53to move away from the second body55. When the sensor12detects that the drawer body30is being received in the case10, the sensor12transmits a signal to the driver, and the driver drives the adjustable rod component570to cause the first body53to move toward the second body55. Referring toFIG.7, in this embodiment, the adjustable device50further includes a receiving structure54. The receiving structure54is disposed between the first end50A and the second end50B. When the first end50A moves relative to the second end50B, a shape of the receiving structure54changes accordingly. In this embodiment, the receiving structure54can receive wires used in the adjustable device50, such as a power cable and a signal cable. Specifically, when the first end50A is moved away from the second end50B, the receiving structure54is stretched and unfolded. When the first end50A is moved toward the second end50B, the receiving structure54is compressed and bent, and the wires are received in the receiving structure54, so that the wires will not be messed up by the movement of the first end50A relative to the second end50B. The receiving structure54may be implemented in various manners. In this embodiment, the receiving structure54may be a plurality of housings541, where the plurality of housings541are pivotally connected to each other. In this embodiment, the housings541pivot relative to each other along with the movement of the first end50A relative to the second end50B. When the first end50A is moved toward the second end50B, the housings541pivoted relative to each other and form an approximately V-shape. When the first end50A is moved away from the second end50B, the housings541pivot relative to each other and form an approximately arch shape. In another embodiment, the receiving structure54is a hose. When the first end50A is moved toward the second end50B, the hose is bent into an approximately V-shape. When the first end50A is moved away from the second end50B, the hose is stretched to form an approximately arch shape. Referring again toFIG.1,FIG.2, andFIG.3, a server is provided according to an embodiment. The same structures in the server as those in the server case100will not be described herein again. The server includes a case10, a drawer body30, a adjustable device50, a hard disk device70, and a fan module90. The drawer body30is received in the case10. The adjustable device50includes a first end50A, a second end50B, and a adjustable structure57. The second end50B is connected to the drawer body30, and the adjustable structure57is connected to the first end50A and the second end50B, so that a distance between the first end50A and the second end50B is changeable. The hard disk device70is assembled in the drawer body30. The fan module90is disposed at the first end50A of the adjustable device50. The drawer body received in the case10is moved until at least a part of the drawer body is located outside the case10, to change the distance between the first end50A and the second end50B of the adjustable device50. Based on the above, in the server case100provided by the present disclosure, the drawer body30is received in the case10. The second end50B of the adjustable device50is connected to the drawer body30, and the distance between the first end50A and the second end50B is changeable. The drawer body30can be selectively received in the case10, or the drawer body30received in the case10can be pulled out of the case10. When the drawer body30is pulled out, the unenclosed space weakens the airflow conveyance effect of the fan module90, leading to a degraded heat dissipation effect. In this case, the rotation speed of the fan module90needs to be increased to maintain the heat dissipation effect. However, as the rotation speed of the fan module90increases, the vibration and noise generated increase accordingly, affecting the read performance of the hard disk device70. Therefore, when the drawer body30is pulled out, the adjustable device50is also pulled, which moves along with the drawer body30, so that the adjustable structure57causes the first body53at the first end50A to move relative to the second body55at the second end50B, to increase the distance between the fan module90and the hard disk device70. When the rotation speed of the fan module90increases, the vibration and noise can be reduced by increasing the distance between the fan module90and the hard disk device70. | 20,859 |
11943890 | DESCRIPTION OF THE EMBODIMENTS This disclosure will now be described in more detail with reference to the accompanying drawings that show various embodiments of this disclosure. With reference toFIGS.1,2, and3A˜4B for the exploded view and perspective view of a trigger type self-locking device, and the schematic views showing various status of its operation in accordance with the first embodiment of this disclosure respectively, the trigger type self-locking device3of a server1and a rack2includes a trigger base31and a moving trigger32installed at an end of a slide rail moving section11on a surface of the server1, and the rack2has a latch base22for fixing the slide rail fixed section21to lock the slide rail moving section11together with the server1in the rack2temporarily. The trigger base31is a two-piece engaging structure having a pivot part311installed therein, and the surface of the trigger base31under the pivot part311has a first opening312, and the trigger base31in front of the pivot part311has a second opening313, and a stop block314is disposed between the second opening313and the pivot part311. It is noteworthy that a pair of installation hooks315are disposed on a side facing the second opening313for fixing the slide rail moving section11. The moving trigger32is designed as a J-shaped sheet structure and has a pivot hole321formed at a bent position for movably pivoting the pivot part311, and an end of the moving trigger32extending downwardly along the pivot hole321has a pulling part322, and a snap hook323linearly disposed at another end and passed out from the second opening313. In addition, an elastic plate324is disposed between the snap hook323and the pivot hole321and obliquely extending along the bottom edge of the moving trigger32for limiting its being assembled onto the stop block314, such that a linkage is formed after the moving trigger32is assembled to the trigger base31. During operation, the snap hook323is under the effect of the restoring elastic force of the elastic plate324, such that the moving trigger32generates a reciprocating swing inside the trigger base31to quickly complete a locking connection with the latch base22. It is noteworthy that there is a special feature of the manufacture of the elastic plate324of this disclosure, wherein the elastic plate324is manufactured by bending an edge of the moving trigger32and punching thin a position adjacent to where the elastic plate connected to the moving trigger to form an elastic restoring section3241. Since the thickness is reduced after punching, the elastic plate can have better restoring elasticity. In addition, the trigger type self-locking device1of this disclosure further includes a hook guard316extending from and disposed on a side of the trigger base31opposing to the first opening312, and the hook guard316is in a shape corresponsive to that of the moving trigger32for stopping the moving trigger32from being pulled further outward. The rigger type self-locking device1of this disclosure further includes a safety lock33, and a moving hole317formed between the second opening313and the pivot part311, and the moving trigger32has a safety hole325configured to be corresponsive to the safety lock33, and the safety lock33is movably passed into the moving hole317, and an end of the safety lock33remains at the exterior of the trigger base31, and the safety lock33is passed into the safety hole325to lock the moving trigger32. It is noteworthy that the safety lock33of this embodiment as shown inFIGS.3A˜4B has a sliding rod331installed thereon, and an end of the safety lock33remains at the exterior of the trigger base31having an elastic element332, and a camber318is formed around the periphery of the moving hole317, and the elasticity of the elastic element332is provided for driving the sliding rod331to rotate along the camber318to pass the safety lock33into the safety hole325. In order to facilitate the rotational operation, the safety lock33has a knob333disposed at an end remaining at the exterior of the trigger base31for facilitating the rotation of the safety lock33and the generation of the telescopic action of the safety lock33, so as to achieve the effect of locking or unlocking at the safety hole325. With reference toFIGS.5,6and7A˜8B for the exploded view and perspective view of a trigger type self-locking device, and the schematic views showing different operating statuses of the trigger type self-locking device in accordance with the second embodiment of this disclosure respectively, the components of the second embodiment are substantially the same as those of the first embodiment, except that the safety lock33of the second embodiment has an elastic element332sheathed on an end remaining inside the trigger base31, and a limit surface34disposed at another opposite end of the safety lock33and evenly aligned and abutted against a surface of the moving trigger32, and the elasticity of the elastic element332is provided for passing the safety lock33into the safety hole325, and an end of safety lock22abuts against the limit surface341to define a locked status. On the contrary, the safety lock33can be pulled outwardly to separate the safety lock33from the safety hole325to define an unlocked status in order to operate the moving trigger32. In this way, when the trigger type self-locking device1of this disclosure is used, the moving trigger32is latched into the latch base22to lock the safety lock33(by rotation or insertion) to complete the locking action, such that the moving trigger32cannot be operated. If it is necessary to pull out the server1, the safety lock33is opened (by rotating it in an opposite direction or pulling it out) to complete the unlocking action. When the server1is pulled out, the pulling part322is triggered to produce an operation similar to the firing of a pistol, such that the snap hook323is rotated in an opposite direction using the pivoting position as a fulcrum to separate the latch base22. In other words, the pulling part322and the hook guard316are the force applying positions, and the force pulls the server1out in an extending direction of the slide rail moving section11. In this disclosure, the moving trigger32comes with a design of an integrally formed elastic plate324, wherein two components are simplified and combined into one piece to achieve the functions such as compression and restoration, in addition to using the restoring characteristics of the metal material itself and punching technology, so that a simplified structure can be obtained to reduce the manufacturing and assembling costs and provide users with convenient and effective intuitive operations. | 6,684 |
11943891 | The exemplifications set out herein illustrate preferred embodiments of the invention, and such exemplifications are not to be construed as limiting the scope of the invention in any manner. DETAILED DESCRIPTION Embodiments of the present disclosure are described herein. It is to be understood, however, that the disclosed embodiments are merely examples and other embodiments can take various and alternative forms. The figures are not necessarily to scale; some features could be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting but are merely representative. The various features illustrated and described with reference to any one of the figures can be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combinations of features illustrated provide representative embodiments for typical applications. Various combinations and modifications of the features consistent with the teachings of this disclosure, however, could be desired for particular applications or implementations. FIG.1schematically illustrates an exemplary operating environment100for providing a secure electronics rack for assembly and transportation according to an exemplary embodiment of the present disclosure. The exemplary operating environment100depicts an aircraft electronic components assembly110including radio components and interconnecting cabling. In this exemplary embodiment, the electronic components assembly110is integrated into an aircraft electronics component rack115. The aircraft electronics component rack115is configured to be installed in an aircraft120. In this exemplary embodiment, the electronic components assembly110may be assembled within the aircraft electronics component rack115or may be assembled separately and then integrated into the aircraft electronics component rack115. The electronic components assembly110may include very high frequency (VHF) transmitters and receivers for communications and navigations, satellite transmitters and receivers, automatic direction finding (ADF) receivers, weather radar, radar altimeter, global positioning system (GPS), ground proximity warning system (GPWS), and other electromagnetic wave communications transmitters and receivers. These components are typically integrated within an equipment rack, such as the aircraft electronics component rack115, within the aircraft120. The aircraft electronics component rack115may be installed within the aircraft in such a way that the airframe provides additional rigidity and stability to the aircraft electronics component rack115once installed. For example, since it is desirable that all aircraft systems are lightweight to reduce fuel consumption and structural loading, the aircraft electronics component rack115may be fabricated from thin, lightweight metal components and therefore somewhat flexible and susceptible to physical damage before it is installed in the aircraft120. Once installed in the aircraft120, the aircraft electronics component rack115when integrated into the aircraft structure may then provide the desired level of rigidity and protection to the electronic components assembly110. Turning now toFIG.2, an exemplary fixture200for providing secure assembly and transportation of an electronics rack220according to an exemplary embodiment of the present disclosure is shown. In this exemplary embodiment, the fixture200, may be a dolly, fabrication fixture, fabrication rack, or the like, for securely restraining an electronics rack220during assembly, transportation, and installation. The fixture200may further provide environmental protection to the electronics rack220during transportation. The exemplary fixture200may include a frame210for providing additional rigidity to the electronics rack220. The top of the electronics rack220may be affixed using bolts or clamps at a top portion of the frame210. Likewise, the electronics rack220may be affixed to the bottom of the frame210using bolts or clamps. These bolts or clamps affix the electronics rack220to the frame210in a manner that may provide lateral rigidity and stability to the electronics rack220. In one exemplary embodiment, the bolts or clamps may be secured and unsecured using an Allen key. The Allen key may be part of a toolkit included with the fixture200during shipping. In addition, the frame210may include a lifting eye235affixed to a top portion of the frame235to facilitate reception of a lifting hook of a crane or other material handling device. The lifting eye235may be a metal ring having a moveable gate wherein the metal ring may be inserted through an aperture on the frame210to enable a mechanical coupling facilitating lifting of the frame210by the lifting hook or lifting loop. The moveable gate may employ a locking sleeve to prevent unintentional opening of the gate. Alternatively, the lifting eye235may be welded or immovably affixed to the frame210. The lifting eye236may be a flexible construction, such as a strap, fabric loop or the like. The frame210may further include one or more fork slots230to provide a structure to facilitate lifting of the frame210from the bottom by a forklift. The fork slots230may be rectangular tubes running from a front of a frame base232to a rear of the frame base232configured to accept forks of a forklift. The fork slots230may be spaced at a fixed distance, such as twenty four inches, or may be adjustable within a range of spacings. In addition, one or more wheels235, or castors, may be affixed to the frame base232to facilitating moving the frame210. One or more floor locks240may be installed on the frame base232to prevent movement of the frame210when the floor locks240are anchored or engaged. Turning now toFIG.3, an exemplary lateral support system300for use with the exemplary fixture according to an exemplary embodiment of the current disclosure is shown. To provide additional lateral support to the electronics rack310during assembly and transportation, one or more adjustable clamps330may be affixed to a uptight portion of the frame320wherein the clamp pad340may be extended by the adjustable clamp330to contact and/or assert a pressure on a side of the electronics rack310. In an exemplary embodiment, an adjustable clamp may be provided on one or more sides of the frame320to provide the clamping pressure such that the lateral support is provided. In one exemplary embodiment, the adjustable clamp330may be an extension clamp, such as a scissor clamp or the like, positioned at a midpoint on each side of the frame320to be adjustable laterally to position the clamp pad340. Turning now toFIG.4, a diagram illustrating a transportation configuration400for the exemplary fixture410is shown. The fixture410may include one or more removeable covers420which may be installed to provide environmental protection for the electronics rack during transportation. In one exemplary embodiment, the transportation configuration400may include a plurality of removable covers420such as a front cover and a rear cover each conformed to the shape of the electronics rack such that the electronics rack is shielded on each side from outside environmental factors. The front cover may be fastened to the fixture410by one or more latches. Likewise, the rear cover may also be fastened to the fixture with latches. One or more of the latches may include a receiving a padlock to restrict opening of the latch. In one exemplary embodiment, the electronics rack is affixed to the fixture, the various electronic components are assembled within the electronics rack, the removeable covers420are installed over the completed electronics and the fixture is ready for shipment. In addition, the removeable covers420may be constructed from an impact resistant material to provide impact protection for the electronics rack. The removeable covers420may be constructed from a rigid material, such as fiberglass, acrylonitrile butadiene styrene (ABS), polycarbonate, and/or metal. The removeable covers420may further include structural members integrated within the removeable covers420in order to provide additional rigidity to the removeable covers420. For example, the structural member may be metal and integrated into an ABS removable cover. When latched to the frame of the fixture410, the removeable covers420will be provided an additional level of structural rigidity to provide protection to the electronics rack during transportation of the fixture410. Turning now toFIG.5, an exemplary implementation of an apparatus500for providing an exemplary electronics rack transportation fixture is shown. In this exemplary embodiment, an apparatus including a frame510configured in a vertical orientation configured to receive an electronics rack, a front cover515and a back cover520, wherein the front cover515and the back cover520are configured to enclose the electronics rack when the front cover515is attached to the frame510and when the back cover520is attached to the frame515. The electronics rack may be populated with an electronic component during assembly while the electronics rack is installed in the frame510. The front cover515may be attached to a front of the frame510using a plurality of front cover latches590. In addition, the back cover520is attached to a back of the frame510using a plurality of back cover latches595. The exemplary frame510may further be configured to include a lifting ring545affixed to the top portion of the frame510for receiving a lifting hook or a corresponding lifting ring or the like. The exemplary apparatus500may further include a first fastener530for mechanically coupling a top portion of the electronics rack to a top portion of the frame510. In one exemplary embodiment, the first fastener530may include one or more nuts and bolts for coupling through a hole in the electronics rack and the first fastener530for securing the electronics rack to the frame510. Alternatively, the first fastener530may be a mechanical clamp operated by a series of threaded rods actuated by an Allen key for applying a pinching pressure on the top portion of the electronics rack while the mechanical clamp is affixed to the frame510. The exemplary apparatus500may further include a second fastener540for coupling a bottom portion of the electronics rack to a bottom portion of the frame510. The second fastener540may include one or more nuts and bolts for coupling through a hole in the electronics rack and the second fastener540for securing the electronics rack to the frame510. Alternatively, the first fastener530may be a mechanical clamp operated by a series of threaded rods actuated by an Allen key for applying a pinching pressure on the lower portion of the electronics rack while the mechanical clamp is affixed to the frame510. The second fastener540may provide a retention force that is perpendicular to the base555, thereby providing a mechanical force on a horizontal flange or surface of the electronics rack, or may apply a force parallel to the horizontal base555, thereby providing a mechanical force on a vertical flange or surface of the electronics rack. A lateral clamp550may be affixed to a side portion of the frame510to provide a lateral force between the side portion of the frame510and a side portion of the electronics rack. In one exemplary embodiment, the apparatus may include two lateral clamps550, one on each side of the frame510, to provide opposing forces to the electronics rack in order to stabilize the center of the electronics rack during transportation, assembly, and installation. The lateral clamp550may be configured for providing a pressure between a side of the frame510and a side of the electronics rack wherein the lateral clamp555is manually or automatically adjustable, such as a scissor jack configuration. A horizontal base555may be provided for supporting the frame510, the horizontal base555including a mechanical interface580for a material handling device, at least one castor560and at least one floor lock570. In one exemplary embodiment, the base555includes four castors560. The mechanical interface580may be configured to interface with a forklift fork. In one exemplary embodiment, the apparatus500is an electronics rack transportation container including a frame510having a vertical orientation configured for supporting an electronics rack, the frame510having an upper mechanical fastener530for securing an upper portion of the electronics rack, a lower mechanical fastener540for securing a lower portion of the electronics rack, a left side clamp550for providing a first lateral force between a left side of the frame510and a left side of the electronics rack, a right side clamp550for providing a second lateral force between a right side of the frame510and a right side of the electronics rack, The electronics rack transportation container may further include a front cover515configured to be affixed to a front side of the frame510and a back cover520configured to be affixed to a back side of the frame510such that the back cover520and the front cover515enclose the electronics rack when the front cover515is affixed to the front side of the frame510and the back cover520is affixed to the back side of the frame510. The electronics rack transportation container may further include a horizontal base555for supporting the frame510, the base555including a mechanical interface580for a material handling device, at least one castor560and at least one floor lock570. In addition, the electronics rack transportation container may include a lifting ring545affixed to the upper portion of the frame510. Turning now toFIG.6, a flow chart illustrating method for configuring an exemplary transportation fixture for transportation of an aircraft electronics rack is shown. In this exemplary embodiment, the method600is first operative for installing610an electronics rack into a transportation frame having a vertical orientation wherein an upper portion of the electronics rack is coupled to an upper portion of the transportation frame and a lower portion of the electronics rack is coupled to a lower portion of the transportation frame. In addition, the transportation frame may include a horizontal base for supporting the transportation frame wherein the horizontal base may include a mechanical interface for a material handling device, at least one castor and at least one floor lock. In addition, the transportation frame may include a left side clamp for providing a first lateral force between a left side of the transportation frame and a left side of the electronics rack and a right side clamp for providing a second lateral force between a right side of the transportation frame and a right side of the electronics rack. The method is next configured for installing620an electronic component into the electronics rack. The electronics may include aircraft radio components, aircraft radio components, aircraft satellite communications components or the like. The electronic component may include multiple electronic devices connected with interconnecting communication cables, power supplies, power supply cables, grounding cables and the like. The method is next operative for affixing630a front cover to a front side of the transportation frame. The front cover may be secured to the frame by a plurality of retention clips wherein a first portion of the retention clip is connected to the front cover and a second portion of the retention clip is connected to the frame. The exemplary clip may be a latch, a catch, hook and loop fastener or any clip or combination of clips that may provide sufficient retention force to keep the front cover secured to the frame during transportation of the electronics rack. The method is next operative for affixing640a back cover to a back side of the transportation frame. As with the front cover, the back cover may be affixed to the frame with a latch, a catch, hook and loop fastener or any clip or combination of clips that may provide sufficient retention force to keep the back cover secured to the frame during transportation of the electronics rack. The back cover and the front cover are configured to provide environmental protection to the electronics rack. The method may next be operative to transport650the transportation fixture. For example, in the instance of an aircraft electronics rack, the transportation fixture may be transported from an electronics assembly facility in one location, to an aircraft assembly facility in a second location. The transportation fixture may be transported via truck within a truck trailer, via sea container, or via cargo aircraft. In one exemplary embodiment, the transportation fixture is returned to the assembly facility once the aircraft electronics rack is installed in an aircraft. While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the disclosure as set forth in the appended claims and the legal equivalents thereof. | 17,745 |
11943892 | DETAILED DESCRIPTION Embodiments of the subject matter described herein relate to an electronics shelving assembly and method of assembly. The electronics shelving assembly may be used within a power system, such as a power generating system (e.g., a vehicle, a stationary power generating system, or the like) to control thermal conditions of electronic devices positioned on shelves of the electronics shelving assembly. Additionally, the assembly may be used to conductively couple the electronic devices with an electrical ground of the power system in which the electronics shelving assembly is disposed or is associated therewith. In one or more embodiments, the shelving assembly may include one or more vertical support members that may be coupled with a wall of the power system. The power system may be a vehicle or non-vehicular power system. The vertical support members may be conductively coupled with an electrical ground of the power system. In one embodiment, the wall of the power system may be an electrical ground of the power system. In another embodiment, the wall maybe conductively coupled with a separate electrical ground of the power system, such as a ground block or ground plane. The shelving assembly includes one or more shelves or shelf units, each having a horizontal support member. The electronic devices may be positioned on the horizontal support member. The shelves may include at least one vertical coupling members conductively and/or mechanically coupled with the horizontal support member. In one embodiment, one or more fastener assemblies may mechanically and conductively couple the shelves with at least one of the vertical support members. Each fastener assembly may include plural conductive plates that are sandwiched together and extend around a conductive fastener, such as a screw or bolt. The conductive fastener of each fastener assembly may be coupled with each of the plural conductive plates and secured to at least one of the vertical support members. For example, the conductive fastener may create a conductive pathway between each of the shelves and the electrical ground via the conductive plates and the at least one vertical support members. FIG.1illustrates one example of an electronics shelving assembly100in accordance with one embodiment. The electronics shelving assembly may be used to hold one or more electronic devices or components such as, but not limited to, processing units, communication systems or devices, controller systems, or the like. In one embodiment, the electronics shelving assembly may be disposed onboard a vehicle system, and electronic devices or components of the vehicle system may be disposed on shelves of the shelving assembly. The vehicle system may be a rail vehicle, an automobile, a truck (with or without a trailer), a bus, a marine vessel, an aircraft, a mining vehicle, an agricultural vehicle, or other off-highway vehicle. Optionally, the electronics shelving assembly may be used within or associated with a stationary and/or other non-vehicle power system. The vehicle systems described herein (rail vehicle systems or other vehicle systems that do not travel on rails or tracks) can be formed from a single vehicle or multiple vehicles, and optionally the operating system may extend between two or more of the multiple vehicles. With respect to multi-vehicle systems, the vehicles can be mechanically coupled with each other (e.g., by couplers) or logically coupled but not mechanically coupled. For example, vehicles may be logically but not mechanically coupled when the separate vehicles communicate with each other to coordinate movements of the vehicles with each other so that the vehicles travel together as a group. Vehicle groups may be referred to as a convoy, consist, swarm, fleet, platoon, and train. In one embodiment, the electronics shelving assembly may be retrofitted within an existing vehicle system. For example, the electronics shelving assembly may be positioned within an existing vehicle system, such as to replace an existing electronics shelving assembly, or to provide an electronics shelving assembly in an existing vehicle that was void a shelving assembly. In another embodiment, the electronics shelving assembly may be designed to be disposed within a new vehicle. For example, the electronics shelving assembly may be considered into the design of the new vehicle, such as by placing consideration on the shape and/or size of the electronic devices of the new vehicle, a new space in which the assembly may be placed, electrical and/or mechanical requirements of the new vehicle design, or the like. The electronics shelving assembly includes first and second vertical support members102,104. The vertical support members are laterally spaced apart from each other and extend in a substantially vertical direction between a top end120and a bottom end122of the assembly. The electronics shelving assembly extends between the top end and the bottom end, a first side124and an opposite second side126, a front end128, and an opposite rear end130. In the illustrated embodiment, the electronics shelving assembly includes first and second vertical support members, but optionally may include any number of vertical support members. The first and second vertical support members may have substantially the same shape and/or size, or alternatively one of the support members may have a shape and/or size that is unique relative to a shape and/or size of the other support member. For example, the shape, size, and spacing between the vertical support members may be based on a space or size of the vehicle system within which the electronics shelving assembly may be disposed, one or more needs or requirements by a user of the electronics shelving assembly, or the like. In one or more embodiments, the vertical support members may be operably coupled with a wall of the vehicle system. As one example, the vertical support members may be welded, fastened, or otherwise coupled with the wall. For example, the vertical support members may be manufactured of a metal or metal alloy, and may be coupled with the wall of the vehicle system such that the vertical supports may be conductively coupled with the wall of the vehicle system. In one embodiment, the wall of the vehicle system may be a ground block of the vehicle system. In another embodiment, the wall may be electrically and conductively coupled with an alternative ground block of the vehicle system. For example, the vertical support members may be conductively coupled with and electrically grounded with a ground block of the vehicle system. Optionally, the vertical support members may be operably coupled with a surface, sheet, or the like, and the surface, the sheet, or the like, may be electrically and mechanically coupled with the wall of the vehicle. The electronics shelving assembly also includes plural shelves106A-E that are operably coupled with the vertical support members. In the illustrated embodiment, the electronics shelving assembly includes five shelves or shelf assemblies, but optionally may include more than five or less than five shelves. The shelves are disposed such that the shelves are stacked on each other in a substantially vertical direction, with substantially uniform spacing between each and neighboring shelves above and below. Optionally, one or more of the shelves may be removed from the assembly and/or the shelves may be spaced apart by uniform and/or unique spacing distances. For example, the number of shelves and/or the placement of the shelves may be based on requirements of an end use of the electronics shelving assembly, different types and/or sizes of electronic devices that may be stored within the assembly, a space or size of the vehicle system within which the electronics shelving assembly may be disposed, a weight distribution requirement of the vehicle system in which the electronics shelving assembly may be used, or any combination therein. For example, the number of shelves and the placement of the shelves may be customized based on one or more needs or requirements by a user of the electronics shelving assembly. FIG.2illustrates a front perspective view of the shelf106A of the electronics shelving assembly shown inFIG.1, andFIG.3illustrates a rear perspective view of the shelf shown inFIG.2. The shelf or shelf assembly includes a horizontal support member108that extends between a first vertical coupling member110and a second vertical coupling member112. For example, the first and second vertical coupling members extend in a substantially vertical direction and are substantially parallel with the vertical support members. The horizontal support member extends in a substantially horizontal direction, and is substantially perpendicular with the first and second vertical coupling members. The horizontal support member may be substantially horizontal such that one or more electronic devices or components may be placed on a top surface of the horizontal support member. The horizontal support member may be coupled with the first and/or second vertical coupling members by welding, mating fastening features (e.g., snaps features, hooks and corresponding openings, or the like), fastening devices (e.g., screws, bolts, nails, straps, or the like), or the like. In one embodiment, the horizontal support member may be manufactured of a metal or metal alloy, and one or both of the vertical coupling members may be manufactured of the same metal or metal alloy as the horizontal support member, or a different metal or different metal alloy. The metal material(s) of the horizontal support member and the vertical coupling members may electrically and conductively couple the horizontal support member with the vertical coupling members. For example, the horizontal support member and the vertical coupling members may be mechanically coupled together and conductively coupled together. Optionally, one of the vertical coupling members (e.g., the first vertical coupling member110) may be mechanically and conductively coupled with the horizontal support member, and the other vertical coupling member (e.g., the second vertical coupling member112) may be manufactured of a non-metallic material such that the second vertical coupling member may be mechanically coupled with the horizontal support member but may not be conductively coupled with the horizontal support member. For example, one of the vertical coupling members may be manufactured of a non-metal material such that the non-metal vertical coupling member has a weight or mass that is less than a weight or mass of the metal vertical coupling member. Optionally, one or both of the vertical coupling members, and/or the horizontal support member may be manufactured of a non-metallic material, but may have a metallic coating (e.g., plating, finish, or the like) such that the coating enables the conductive coupling between the members. The horizontal support member extends between a vertical wall114and a front surface142of the shelf between the front and rear ends of the electronics shelving assembly. In one or more embodiments, the vertical wall, the front surface, and the horizontal support member may all be formed as a single, homogenous component. For example, the vertical wall, the front surface, and the horizontal support member may be formed as a homogenous single component, rather than a non-homogenous component or a component formed by two or more separate bodies that are then combined with each other. The homogenous component may have the same consistency and/or chemical makeup throughout the entirety or substantially all of the component. The vertical wall, the front surface, and the horizontal support member may be manufactured (e.g., stamped, formed, cast, molded, or the like) of a single piece of metal. Optionally, one or more of the vertical wall, the front surface, and the horizontal support member may be independently formed, and may be operably couple with one or more of the other components (e.g., welding, fastening, or the like). In the illustrated embodiment ofFIG.3, the shelf includes angled bodies146,148disposed on a rear side of the vertical wall. In the illustrated embodiment, the angled bodies extend a distance along the vertical wall in a substantially horizontal direction, and have a substantially triangular cross-sectional shape. Optionally, the shelf may include one or more angled bodies extending in a substantially vertical direction along the rear surface of the vertical wall. Optionally, the angled bodies may have an alternative cross-sectional shape. For example, the angled bodies may be shaped and/or positioned to define a gap (not shown) between the rear side of the vertical wall and the wall of the vehicle system (not shown). The gap may be an opening to allow air or other fluids to flow to move through the electronics shelving assembly between the vertical walls of each of the shelves and the wall of the vehicle system. In the illustrated embodiment, the horizontal support member frames an airflow opening132. The airflow opening may be shaped and/or sized based on a type of electronic device that may be held on the horizontal support member, based on an amount of thermal energy the electronic device is expected to generate, based on other electronic devices expected to be disposed on other shelves of the electronics shelving assembly, or the like. For example, the airflow opening may be positioned, shaped, and sized in order to control thermal energy of the one or more electronic components expected to be disposed within the electronics shelving assembly. For example, the airflow opening may allow air to flow through the horizontal support member. The first and second vertical coupling members have a substantially triangular shape and each extends between the vertical wall and about the front surface of the shelf in a first lateral direction, and are disposed at opposing ends of the horizontal support member in a second lateral direction. For example, the first and second vertical coupling members are laterally spaced apart from each other. The lateral spacing may be based on the spacing between the first and second vertical support members, based on space requirements in the area of the vehicle in which the electronics shelving assembly is disposed, or the like. In one or more embodiments, the lateral spacing between the first and second vertical coupling members may be based on the size of the one or more electronic devices that may be positioned on the horizontal support member. For example, the vertical coupling members may be laterally spaced to provide a space or gap between neighboring electronic devices disposed on the shelf. Optionally, one or more of the vertical coupling members may have an alternative shape and/or size. In one embodiment, the shelf may include the first vertical coupling member, but may be devoid the second vertical coupling member. For example, the shelf may be designed to hold a predetermined amount of weight of the electronic devices, and the first vertical coupling member alone may be capable of supporting the predetermined weight requirements. Alternatively, the shelf may include a third vertical coupling member disposed laterally between the first and second vertical coupling members. For example, the shelf may be required to hold a determined amount of weight that exceeds capabilities of the first and second vertical coupling members, and a third vertical coupling member may be required to achieve the weight requirement. In the illustrated embodiment, each of the first and second vertical coupling members frame respective airflow openings134,136, respectively. Like the airflow openings of the horizontal support member, the airflow openings of the vertical coupling members may be designed for thermal management of the electronic devices that may be held on the shelves of the electronics shelving assembly. For example, the airflow openings may allow air to flow between the first and second vertical coupling members. The shelf includes a wire organizational body116that is coupled with the front surface of the shelf. In the illustrated embodiment, the wire organizational body includes a first wire structure138and a second wire structure140that define annular shapes with the horizontal support member. The first and second wire structures project outwardly from the horizontal support member of the shelf. The first wire structure and the front surface of the shelf define a first wire opening182, and the first wire structure and the second wire structure define a second wire opening184. In one or more embodiments, wires of the electronic devices (not shown) may be positioned within one of the first or second wire openings of one or more of the plural shelves of the electronics shelving assembly. For example, the wires of electronic devices positioned on the shelves may be positioned within the first and/or second wire openings of the wire organizational bodies of each shelf. FIG.4illustrates a flowchart of one example of a method of assembling an electronics shelving assembly, such as the electronics shelving assembly shown inFIG.1. At step402, plural vertical support members are coupled with a wall of a vehicle. For example,FIG.5illustrates a front view of a portion of the electronics shelving assembly shown inFIG.1. The plural shelves are hidden from view for clarity. In the illustrated embodiment, the first and second vertical support members are coupled with a wall150of a vehicle system (not shown). In one embodiment, the wall may be disposed onboard the vehicle system. In another embodiment, the wall may be a separate structure, and may be coupled with a wall or surface of the vehicle. The vertical support members extend between the top end120and the bottom end122of the electronic shelving assembly. The vertical support members are manufactured of a metal material, or may have a metallic coating or finish, such that welding or coupling the vertical support members with the wall creates a conductive pathway between the vertical support members and the wall of the vehicle. One or more shelves of the electronics shelving assembly may be coupled (e.g., mechanically and electrically coupled) with the vertical support members subsequent to the vertical support members being coupled with the wall. Returning toFIG.4, at step404, hooks of one or more shelves may be positioned within corresponding openings of the vertical support members. As shown inFIG.3, each of the shelves may include one or more hooks144A,144B extending outwardly from a rear side of the first and second vertical coupling members110,112of each of the shelves. FIGS.6and7illustrate a magnified view of a portion of the electronics shelving assembly shown inFIG.5. The plural shelves are hidden from view inFIG.6, and are shown inFIG.7. As shown inFIGS.6and7, the vertical coupling members may include one or more openings156A,156B that correspond with the plural hooks of the vertical coupling members. For example, the hook144A of the first shelf106A may be positioned within the opening156A, and the hook144B of the first shelf may be positioned within the opening156B. The hooks and corresponding openings may be shaped to support and maintain the shelves in a position relative to the vertical coupling members while fastener assemblies and other coupling features may be coupled with the vertical support members to mechanically and electrically couple the shelves with the vertical support members. For example, the hooks may hold a position of the shelf to allow an operator or installer of the electronics shelving assembly to complete the fastening of other fastening features without the operator or installer having to manually hold or maintain the position of the shelf during installation. Returning toFIG.4, at step406, the shelves may be conductively and mechanically coupled with the vertical support members via one or more fastener assemblies.FIG.8illustrates a cross-sectional partial perspective view of the electronics shelving assembly shown inFIG.7. In the illustrated embodiment, the first shelf106A may be conductively and mechanically coupled with the first vertical support member102via a first fastener assembly152A, and the second shelf106B may be conductively and mechanically coupled with the first vertical member via a second fastener assembly152B. FIG.9illustrates a magnified view of the fastener assembly152A shown inFIG.8. The fastener assembly includes plural conductive plates162,164that are sandwiched together and extend around a conductive fastener158. In the illustrated embodiment, a first conductive plate162is disposed within the vertical wall114of the shelf, and a second conductive plate164is disposed within the first vertical support member102. The fastener assembly also includes a washer160positioned on a front side of the vertical wall, and a threaded receiving connector168positioned on a rear side of the first vertical support member. In the illustrated embodiment, the conductive fastener includes threads166that mate with threads170of the receiving connector. For example, the conductive fastener, coupled with the receiving connector, creates a conductive pathway between the first shelf and an electrical ground (e.g., the wall of the vehicle or another ground block of the vehicle conductively coupled with the wall) via the conductive plates and the first vertical support member. Additionally, the fastener assembly may provide a conductive pathway between the shelf and the first vertical support member across the gap defined by the angled bodies disposed on the rear side of the vertical wall of the shelf (shown inFIG.3). In the illustrated embodiment ofFIG.8, the first shelf is conductively and mechanically coupled with the first vertical support member via the a single fastener assembly. In alternative embodiments, two or more fastener assemblies may be used to conductively and mechanically couple the first shelf with the first and/or second vertical support members. In one or more embodiments, one or more of the shelves may include additional fastener assemblies172that may be used to conductively couple one or more electronic devices with the electric ground of the vehicle. For example,FIG.10illustrates a magnified partial view of the electronics shelving assembly shown inFIG.8. The first shelf includes tabs176that extend outwardly from front surface of the first shelf. Optionally, the first shelf may include less than two or more than two tabs. In the illustrated embodiment, the tabs include fastener assemblies coupled therein. For example, plural conductive plates178,180sandwiched together and extending around a conductive fastener174. The fastener assemblies may include a receiving connector (not shown) disposed on a bottom side of the tabs that may be mechanically coupled with the conductive fastener. In one or embodiments, one or more electronic devices or components (not shown) disposed on one of the shelves of the electronics shelving assembly may be conductively coupled with one of the fastener assemblies172, such as via a conductive grounding strap coupled with a grounding feature of the electronic device and the fastener assembly. Optionally, one or more electronics may be conductively coupled with one of the fastener assemblies152used to create a conductive pathway between the shelves and the vertical support members. The electronic devices or components may be conductively coupled with one of the fastener assemblies,172,152of the shelves. Additionally, the shelves may be conductively coupled with one or more of the vertical support members via one of the fastener assemblies152. Additionally, the vertical support members may be conductively coupled with an electrical ground of the vehicle via the welding or other conductive coupling joint between the wall of the vehicle and the vertical support members. For example, the fastener assemblies, alone with via one or more conductive ground straps, may create conductive pathways between the electronic devices disposed on the electronics shelving assembly and the electrical ground of the vehicle. As one example,FIG.11illustrates a partial front view of the electronics shelving assembly. In the illustrated embodiment, first and second electronic devices186A,186B are disposed on the horizontal support member108that extends in a substantially horizontal direction between the first vertical coupling member110and the second vertical coupling member (hidden from view inFIG.11). The electronic devices or components may be conductively coupled with one or more of the fastener assemblies of the shelving assembly. For example, the first electronic device186A may include a ground feature188. A first end of a grounding strap (not shown) may be conductively coupled with the ground feature of the first electronic device, and a second end of the grounding strap may be conductively coupled with the fastener assembly172. Optionally, the first electronic device may be conductively coupled with two or more fastener assemblies. Optionally, the first and second electronic devices may both be conductively coupled with the same fastener assembly. Optionally, the electronic devices disposed on the shelves of the electronics shelving assembly may be electrically ground to the electronics shelving assembly by an alternative and/or additional grounding path. Returning toFIG.4, at step408the shelves may be mechanically coupled with the vertical support members via one or more coupling features. For example,FIG.8illustrates the first shelf coupled with the first and second vertical support members. The first shelf is conductively and mechanically coupled with the first vertical support member via the fastener assembly152. Additionally, the first shelf is mechanically coupled with the first and second vertical support members via plural coupling features154. The coupling features may be screws, bolts, or the like. In one embodiment, the coupling features may be conductive coupling features, or alternatively may be non-conductive coupling features. In one aspect or example, an electronics shelving assembly includes vertical support members that can be coupled with a wall of a vehicle. The vertical support members are conductively coupled with an electrical ground. The electronics shelving assembly also includes shelves, each having a horizontal support member and at least one vertical coupling member coupled with each other. Fastener assemblies mechanically and conductively couple the shelves with the vertical support members. Each of the fastener assemblies includes plural conductive plates sandwiched together and extending around a conductive fastener. The conductive fasteners may be coupled with each of the conductive plates and may be secured to the shelves to create a conductive pathway between the shelves and the electrical ground via the conductive plates and at least one of the vertical support members. Optionally, at least one of the conductive plates in at least one of the fastener assemblies may be coupled with a conductive grounding strap that conductively couples the at least one of the fastener assemblies with the electrical ground. Optionally, the at least one vertical coupling member of each of the shelves includes first and second vertical coupling members. The shelves may also include a vertical wall extending between the first and second vertical coupling members with one or more angled bodies that may maintain a gap between the vertical wall and the wall of the vehicle. The fastener assemblies may provide the conductive pathways between the shelves and the vertical support members across the gap. Optionally, at least one vertical coupling member of each of the shelves may be a first vertical coupling member of the shelf. Each of the shelves may also include a second vertical coupling member laterally spaced apart from the first vertical coupling member. The first and second vertical coupling members may frame respective air flow openings for air to flow between the first and second vertical coupling members. Optionally, the horizontal support member of each of the shelves may frame an air flow opening for air to flow through the horizontal support member. Optionally, one or more of the shelves may include a wire organization body outwardly projecting from the one or more horizontal support members of the one or more shelves. The wire organization body of the one or more shelves may define annular shapes with the one or more horizontal support members for positioning wires of electronic components disposed on the horizontal support members. Optionally, the vertical coupling members of the shelves may include hooks and the vertical support members may include corresponding openings for receiving the hooks of the vertical coupling members. Optionally, the hooks may be shaped to support and maintain the shelves in position relative to the vertical coupling members while the fastener assemblies are coupled with the vertical coupling members and the vertical support members without additional manual force supporting the shelves. In one aspect of example, an electronics shelving assembly may include vertical support members that may be coupled with a wall of a vehicle. The vertical support members may be conductively coupled with an electrical ground. The electronics shelving assembly can include shelves, each having a horizontal support member and first and second vertical coupling members coupled with the horizontal support member. The first and second vertical coupling members can frame respective air flow openings for air to flow between the first and second vertical coupling members. Fastener assemblies may mechanically and conductively couple the shelves with the vertical support members. Optionally, each of the fastener assemblies may include plural conductive plates sandwiched together and extending around a conductive fastener. The conductive fasteners may be coupled with each of the conductive plates and may be secured to the vertical support members to create a conductive pathway between the shelves and the electrical ground via the conductive plates and at least one of the vertical support members. Optionally, at least one of the conductive plates in at least one of the fastener assemblies may be coupled with a conductive grounding strap that conductively couples the at least one of the fastener assemblies with the electrical ground. Optionally, the shelves may include vertical walls extending between the first and second vertical coupling members of each of the shelves. The shelves may include one or more angled bodies coupled with the vertical walls and may maintain a gap between the vertical walls and the wall of the vehicle. The fastener assemblies may provide the conductive pathways between the shelves and the vertical support members across the gap. Optionally, the horizontal support member of each of the shelves may frame a horizontal support air flow opening for air to flow through the horizontal support member. Optionally, one or more of the shelves may include a wire organization body outwardly projecting from the one or more horizontal support members of the one or more shelves. The wire organization body of the one or more shelves may define annular shapes with the one or more horizontal support members for positioning wires of electronic components disposed on the horizontal support members. Optionally, the vertical coupling members of the shelves may include hooks and the vertical support members may include corresponding openings for receiving the hooks of the vertical coupling members. Optionally, the hooks may be shaped to support and maintain the shelves in position relative to the vertical coupling members while the fastener assemblies are coupled with the vertical coupling members and the vertical support members without additional manual force supporting the shelves. In one aspect or example, an electronics shelving assembly may include support members that may be coupled with a wall of a vehicle. The support members may be conductively coupled with an electrical ground. The electronics shelving assembly can include shelf units, each having a shelf member and first and second coupling members coupled with the shelf member. Fastener assemblies may mechanically couple the first and second coupling members of the shelf units with the support members. Each of the fastener assemblies may include a respective conductive fastener that can be secured to the support members to create a conductive pathway between the shelf units and the electrical ground via the support members. Optionally, each of the fastener assemblies may include plural conductive plates sandwiched together and extending around the conductive fastener. The conductive fasteners may be coupled with each of the conductive plates and may be secured to the first and second support members to create the conductive pathway between the shelf units and the electrical ground via the conductive plates and at least one of the support members. Optionally, each of the shelf units may include a shelf unit wall extending between the first and second coupling members with one or more angled bodies that may maintain a gap between the shelf unit wall and the wall of the vehicle. The fastener assemblies may provide the conductive pathways between the shelf units and the support members across the gap. Optionally, one or more of the shelf units may include a wire organization body outwardly projecting from the one or more shelf members of the one or more shelf units. The wire organization body of the one or more shelf units may define annular shapes with the one or more shelf members for positioning wires of electronic components disposed on the shelf members. As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” do not exclude the plural of said elements or operations, unless such exclusion is explicitly stated. Furthermore, references to “one embodiment” of the invention do not exclude the existence of additional embodiments that incorporate the recited features. Moreover, unless explicitly stated to the contrary, embodiments “comprising,” “comprises,” “including,” “includes,” “having,” or “has” an element or a plurality of elements having a particular property may include additional such elements not having that property. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and do not impose numerical requirements on their objects. Further, the limitations of the following claims are not written in means-plus-function format and are not intended to be interpreted based on 35 U.S.C. § 112(f), unless and until such claim limitations expressly use the phrase “means for” followed by a statement of function devoid of further structure. The above description is illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with each other. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the inventive subject matter without departing from its scope. While the dimensions and types of materials described herein define the parameters of the inventive subject matter, they are exemplary embodiments. Other embodiments will be apparent to one of ordinary skill in the art upon reviewing the above description. The scope of the inventive subject matter should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. This written description uses examples to disclose several embodiments of the inventive subject matter, including the best mode, and to enable one of ordinary skill in the art to practice the embodiments of inventive subject matter, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the inventive subject matter is defined by the claims, and may include other examples that occur to one of ordinary skill in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims. | 36,870 |
11943893 | Corresponding reference numerals indicate corresponding features throughout the several views of the drawings. DETAILED DESCRIPTION Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments. Spatially relative terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. An electronics equipment cabinet according to one example embodiment of the present disclosure is illustrated inFIG.1and indicated generally by reference number100. The cabinet100includes multiple cabinet walls102A-102D defining an interior enclosure space104. The multiple walls102A-102D are coupled to one another to seal the interior enclosure space104to inhibit external ambient air from entering the interior enclosure space104. The cabinet100also includes multiple electronic devices106A and106B positioned within the interior enclosure space104. The electronic devices106A and106B each include corresponding fan108A or108B to selectively drive air through the electronic device106A or106B and at least partially circulate air within the interior enclosure space104. As shown inFIG.1, the cabinet100further includes an outer wall110positioned to shield solar radiation from the outer surface (e.g., an exterior side, etc.) of the cabinet wall102A, and an outer surface of the cabinet wall102C. The outer wall110defines a channel112between the outer wall110and the cabinet wall102A, and between the outer wall110and the cabinet wall102C. The outer wall110has two openings114A and114B extending therethrough, which are positioned to allow airflow116through the channel112. The cabinet additionally includes a fan118positioned to selectively drive external ambient air into the channel112via the opening114A, and out of the channel112via the opening114B. AlthoughFIG.1illustrates the outer wall110as adjacent the top cabinet wall102C and the side cabinet wall102A, in other embodiments the outer wall110may be adjacent to one or more other cabinet walls (e.g., a side wall, a front wall, a back wall, etc.), may shield only a portion of a cabinet wall, may not cover the top cabinet wall102C, etc. For example, the outer wall110may be a solar shield coupled to one or more cabinet walls102A-102D. Thus, a solar shield may define a small enclosure on a top, a side, a bottom, etc. of the cabinet100. In some embodiments, the outer wall110may be defined by inserting a partition into a region (e.g., an upper region etc.) of the interior space of the cabinet100, to separate an outer wall from the interior space defined within (e.g., below, etc.) the inserted partition, etc. Thus, a partition may define a small enclosure within a top portion, a side portion, a bottom portion, etc. of the interior space of the cabinet100. The outer wall110may include any suitable wall (e.g., solar shield, etc.) that reflects, inhibits, etc. at least some solar energy from heating the corresponding cabinet walls102A-D, to inhibit solar energy from raising the temperature of the interior enclosure space104, or at least reduce the magnitude of the increased temperature in the interior enclosure space104due to the solar energy (e.g., as compared to a magnitude of the increased temperature due to the solar energy if the solar shied110were not present). The outer wall110may be formed of a specific material or combination of materials for reflecting solar energy. For example, the outer wall110may be formed of aluminum (e.g., anodized aluminum, etc.), a fiberglass material, and/or another suitable material that has a desired reflection coefficient (e.g., a ratio of the radiation flux reflected by a surface to the incident radiation flux). In some embodiments, the outer wall110may include a material (e.g., a film, a paint, etc.) applied to the surface of the outer wall110, such as a reflective film, a lightly colored (e.g., white) paint, etc. As mentioned above, the cabinet100includes a fan118positioned to selectively drive external ambient air into the channel112via a first opening114A, and out of the channel112via a second opening114B. For example, the fan118may be located within the channel112(e.g., as shown inFIG.1) to drive the airflow116through the channel112, the fan118may be located outside of the channel112to direct airflow into or out of one of the openings114A or114B, more than one fan118may positioned within or outside of the channel112, etc. As described further below, in some embodiments the fan118may extend into the interior enclosure space104while being substantially sealed from the interior enclosure space104by a cover, etc. The fan118may then be open to the channel112on a side of the fan118opposite the cover/interior enclosure space104, in order to selectively drive the airflow116through the channel112. The fan118may include any suitable air circulation device, such as an axial fan, an impeller fan, etc. In some embodiments, the fan118includes a one rack unit (1RU) fan (e.g., 20 mm×20 mm, etc.). The fan118may cause a reduction in temperature within the cabinet100by any suitable amount, such as a reduction of about six degrees Celsius at an intake of the electronic devices106A and1068, etc. AlthoughFIG.1illustrates two electronic devices106A and106B positioned in the interior enclosure space104, other embodiments may include more or less electronic devices. For example, the interior enclosure space may house any suitable electronic devices, including power supply equipment (e.g., switched-mode power supplies, batteries, rectifiers, etc.), and electronic communication (e.g., telecommunications) equipment (e.g., radios, antennas, transmitters, computers, servers, etc.). FIG.2illustrates a view of an electronics equipment cabinet200according to another example embodiment, with some cabinet walls removed to show interior components. The example cabinet200may be similar to the cabinet100illustrated inFIG.1. As shown inFIG.2, the cabinet200includes multiple cabinet walls202A-202D defining an interior enclosure space204. The front and right-side cabinet walls are not illustrated inFIG.2to allow illustration of interior cabinet components. The multiple walls202A-202D are coupled to one another to seal the interior enclosure space204to inhibit external ambient air from entering the interior enclosure space204. For example, each cabinet wall202A-202D may be coupled to adjacent walls via an airtight connection, each joint may include a sealing gasket, caulk or another suitable sealing medium, etc. The cabinet200also includes multiple electronic devices206A,206B,207A and207B positioned within the interior enclosure space204. The electronic devices206A,206B,207A and207B may positioned in any suitable location, such as on one or more equipment racks220, etc. The electronic devices206A and206B each include a corresponding fan to selectively drive air through the electronic device206A or206B and at least partially circulate air within the interior enclosure space204. For example, the fan may be positioned at an air entry of the electronic device, an air exit of the electronic device, etc., to direct air through the electronic device. As shown inFIG.2, the cabinet200further includes an outer wall210positioned to shield solar radiation from an exterior side of the cabinet wall202A, and from an exterior side of the cabinet wall202C. The outer wall210defines a channel between the outer wall210and the cabinet wall202A, and between the outer wall210and the cabinet wall202C. The outer wall210has two openings214A and214B extending therethrough, which are positioned to allow airflow through the channel214. The cabinet additionally may include a fan positioned to selectively drive external ambient air into the channel via the opening214A, and out of the channel via the opening214B. FIGS.3-6illustrate an electronics equipment cabinet300according to another example embodiment of the present disclosure. As shown inFIG.3, the cabinet300generally includes multiple cabinet walls302A-302D defining an interior enclosure space304for housing electronic devices306A and306B, and an outer wall310coupled to an exterior side of the cabinet walls302A and302C. AlthoughFIG.3illustrates a single unitary outer wall covering both a side wall302A and a top wall302C, in other embodiments there may be multiple outer walls that are separate from one another, outer wall(s) that cover only a portion of one or more cabinet walls, etc. Also, in other embodiments the interior enclosure space304may house more or less than two electronic devices, which may include any suitable devices such as power devices (e.g., rectifiers), communication devices, etc. The cabinet300includes a divider wall322(e.g., a divider plate, etc.) positioned between the outer wall310and the cabinet walls302A and302C shield by the outer wall310. As shown inFIG.5, the divider wall322defines a channel312B along one side of the divider wall322and another channel312A along another second side of the divider wall322(e.g., the channel312A may be located along a side of the divider wall322that is opposite the wall along which channel312B is located). The cabinet wall302A shielded by the outer wall310has two internal (e.g., cabinet wall, etc.) openings324A and324B to allow internal cabinet air to flow between the interior enclosure space304and the channel312B, while inhibiting external ambient air from entering the interior enclosure space304and the channel312B. For example, the interior enclosure space304and the first channel312B may be sealed from the external ambient air, while still allowing the internal cabinet air to flow between the interior enclosure space and the first channel312B to cool the internal cabinet air. The outer wall310has two external (e.g., shield, etc.) openings314A and314B positioned to allow external ambient air to flow through the channel312A to cool the internal cabinet air in the channel312B via heat exchange through the divider wall322, while inhibiting the external cabinet air from mixing with the internal cabinet air. For example, internal cabinet air in the interior enclosure space304may be heated during operation of the electronic devices306A and306B, and the heated internal cabinet air may circulate through the channel312B via an airflow316B. In the airflow316B, the heated internal cabinet air may rise to the top of the interior enclosure space304to flow through the opening324A on the top cabinet wall302C, the heated internal cabinet air may be driven to the opening324A via one or more fans (e.g., a fan associated with one of the electronic devices306A and306B, a fan positioned in the channel312B, etc.). As the internal heated cabinet air moves down the channel312B towards the opening324B in the side cabinet wall302A, the air may be cooled via heat exchange through the divider wall322. For example, external ambient air may be cooler than the heated internal cabinet air, and the external ambient air may move through the channel312A on the opposite side of the divider wall322from the channel312B. As shown inFIG.5, the external ambient air may enter the channel312A via the opening314A in the outer wall310(e.g., via natural outdoor air flow, via a fan located in the channel312A, etc.). As the airflow316A of the external ambient air rises in the channel312A, the external ambient air may absorb heat from the heated internal cabinet airflow316B via heat exchange through the divider wall322. In some example embodiments herein, cooler portions of airflows may be represented by dashed arrows while hotter portions of airflows are represented by solid arrows. Accordingly, the divider wall322may include a material having a high thermal conductivity (e.g., a metal, a plastic, etc.) to allow heat to transfer from the heated internal airflow316B to the cooler external ambient airflow316A, while inhibiting mixture of external ambient air and internal cabinet air (e.g., to prevent contamination of the internal cabinet air by debris from the external ambient air, etc.). After the internal cabinet airflow316B has transferred at least some heat through the divider wall322, the now cooler internal cabinet airflow316B reenters the interior enclosure space304via the opening324B in the side cabinet wall302A. Similarly, after the external ambient airflow316A has absorbed at least some heat through the divider wall322, the now warmer external ambient airflow316A exits the outer wall310via the opening314B in the outer wall310. The divider wall322may generate a counterflow heat exchanger effect to reduce the temperature within the cabinet300by any suitable amount, such as about six degrees Celsius at an intake of the electronic devices306A and306B, etc. AlthoughFIG.5illustrates the opening324A on the top cabinet wall302C and the opening324B on the side cabinet wall302A, in other embodiments the openings in the cabinet walls may be located on different walls, on the same wall as one another, etc. Similarly, althoughFIG.5illustrates the opening314A on a lower end of the outer wall310and the opening314B on a top end of the outer wall310, in other embodiments the openings in the outer wall may be located on other outer wall surfaces, on the same outer wall surface, etc. As shown inFIGS.3-6, the divider wall322is positioned perpendicular to the outer wall310and the cabinet walls302A and302C. In this manner, the divider wall322may be considered to divide the outer wall310into two adjacent portions, where the edge of the divider wall322that contacts the outer wall310defines an intersection of the two adjacent portions of the outer wall310. Similarly, the divider wall322may be considered to divide the side cabinet wall302A into two adjacent portions, where another edge of the divider wall322that contacts the side cabinet wall302A defines an intersection of the two adjacent portions of the side cabinet wall302A. In the above example arrangement, the channel312A is located between the first portions of the outer wall310and the side cabinet wall302A (e.g., along one side of the divider wall322), and the channel312B is located between second portions of the outer wall310and the side cabinet wall302A. FIGS.3-6illustrate the divider wall322as extending in a vertical direction from a bottom of the side cabinet wall302A to a top of the side cabinet wall302A. The height of the divider wall322in the vertical direction is greater than a height of the side cabinet wall302A in the vertical direction. This arrangement allows the divider wall322to exchange heat along the length of the airflows316A and316B, while inhibiting mixture of the internal cabinet air and external ambient air along the length of the airflows316A and316B. In other embodiments, the divider wall322may have a non-vertical orientation, may be shorter than a height of the side cabinet wall302A, etc. As shown inFIG.4A, the electronics equipment cabinet300may include a fan318positioned to selectively drive the external ambient air through the channel312A.FIG.4Bis a sectional view of the fan318, taken at point A inFIG.4A. As shown inFIG.4B, the fan318may extend into the interior enclosure space304while being substantially sealed from the interior enclosure space304by a cover326. The fan318may then be open to the channel312A on a side of the fan318opposite the cover326and the interior enclosure space304, in order to in order to selectively drive the airflow316A through the channel312A. In other embodiments, the fan318may not extend into the interior enclosure space304and may not include a cover326, the fan318may be positioned in other locations such as outside the outer wall310adjacent the opening314A, etc. The fan318may include any suitable air circulation device, such as an axial fan, an impeller fan, etc. As described above, the outer wall310may include one or more openings, such as openings314A and314B illustrated inFIGS.3-6. Each opening may include a grate having multiple apertures, slots, etc. to define an open area percentage relative to an area of the opening314A or314B. For example, the grate may define about an eighty percent open area (e.g., the combined area of the apertures in the grate is about eighty percent of the total combined area of the apertures plus the row and column supports positioned between the apertures), the grate may define about a ninety percent open area, etc. The grate may be considered to have about, or substantially, an eighty percent, ninety percent, etc. open area, within manufacturing tolerances, within 1%, 5%, 10%, etc. FIG.6is another example diagram illustrating the internal cabinet airflow316B and the external ambient airflow316A through the respective channels312B and312A. As shown inFIG.6, the heated internal cabinet air flows out of the interior enclosure space304via the opening324A in the top cabinet wall302C, down the channel312B while transferring heat through the divider wall322, and back into the interior enclosure space304via the opening324B in the side cabinet wall302A. At the same time, the cooler external ambient air flows into the outer wall310via the opening314A, up the channel312A while absorbing heat through the divider wall322, and back out of the outer wall310via the opening314B. FIGS.7-11illustrate an electronics equipment cabinet400according to another example embodiment of the present disclosure. As shown inFIG.7, the cabinet400generally includes multiple cabinet walls402A-402D defining an interior enclosure space404for housing electronic devices406A and406B, and an outer wall410coupled to an exterior side of the cabinet walls402A and402C. AlthoughFIG.7illustrates a single unitary outer wall covering both a side wall402A and a top wall402C, in other embodiments there may be multiple outer wall that are separate from one another, outer wall (s) that cover only a portion of one or more cabinet walls, etc. Also, in other embodiments the interior enclosure space404may house more or less than two electronic devices, which may include any suitable devices such as power devices (e.g., rectifiers), communication devices, etc. The cabinet400includes a divider wall422positioned between the outer wall410and the cabinet walls402A and402C shielded by the outer wall. As shown inFIG.11, the divider wall422defines a channel412B along one side of the divider wall422and another channel412B along another second side of the divider wall422(e.g., the channel412A may be located along a side of the divider wall422that is opposite the wall along which channel412B is located). The cabinet wall402A shielded by the outer wall410has internal openings424A and424B to allow internal cabinet air to flow between the interior enclosure space404and the channel412B, while inhibiting external ambient air from entering the interior enclosure space404and the channel412B. For example, the interior enclosure space404and the first channel412B may be sealed from the external ambient air, while still allowing the internal cabinet air to flow between the interior enclosure space and the first channel412B to cool the internal cabinet air. The outer wall410has two shield openings414A and414B positioned to allow external ambient air to flow through the channel412A to cool the internal cabinet air in the channel412B via heat exchange through the divider wall422, while inhibiting the external cabinet air from mixing with the internal cabinet air. For example, internal cabinet air in the interior enclosure space404may be heated during operation of the electronic devices406A and406B, and the heated internal cabinet air may circulate through the channel412B via an airflow416B. In the airflow416B, the heated internal cabinet air may rise to the top of the interior enclosure space404to flow through the opening424A on the top cabinet wall402C, the heated internal cabinet air may be driven to the opening424A via one or more fans (e.g., a fan associated with one of the electronic devices406A and406B, a fan positioned in the channel412B, etc.). As the internal heated cabinet air moves down the channel412B towards the opening424B in the side cabinet wall402A, the air may be cooled via heat exchange through the divider wall422. For example, external ambient air may be cooler than the heated internal cabinet air, and the external ambient air may move through the channel412A on the opposite side of the divider wall422from the channel412B. The divider wall422may generate a counterflow heat exchanger effect to reduce the temperature within the cabinet400by any suitable amount, such as about seven degrees Celsius at an intake of the electronic devices406A and406B, etc. As illustrated inFIGS.7-11, the divider wall422is positioned parallel to the outer wall410, the side cabinet wall402A and the top cabinet wall402C (e.g., in contrast to the divider wall322positioned perpendicular to the outer wall310, the side cabinet wall402A and the top cabinet wall402C inFIGS.3-6). The divider wall422may be considered as extending horizontally from the left side of the cabinet wall402A to the right side of the cabinet wall402A. Due to the parallel orientation of the divider wall422, the outer wall410may be considered as overlapping or covering the divider wall422, while the divider wall422overlaps or covers the side cabinet wall402A. Accordingly, the external ambient air channel412A between the outer wall410and the divider wall422overlaps or covers the internal cabinet air channel412B between the divider wall422and the side cabinet wall402A. The above arrangement increases the surface area of the divider wall422between the external ambient air channel412A and the internal cabinet air channel412B (e.g., as compared to the divider wall322ofFIGS.3-6), which may facilitate a greater amount of heat transfer between the channels (e.g., as compared to the divider wall322ofFIGS.3-6). As shown inFIG.9A, the electronics equipment cabinet400may include a fan418positioned to selectively drive the external ambient air through the channel412A.FIG.9Bis a sectional view of the fan418, taken at point B inFIG.9A. As shown inFIG.9B, the fan418is positioned within the channel412A between the outer wall410and the divider wall422. The fan418may selectively drive the airflow416A through the channel412A. In other embodiments, the fan418may extend into the interior enclosure space404and may include a cover (e.g., to seal the fan418from the interior enclosure space), the fan418may be positioned in other locations such as outside the outer wall410adjacent the opening414A, etc. The fan418may include any suitable air circulation device, such as an axial fan, an impeller fan, etc. FIG.11includes example dimensions of the channels412A and412B for purposes of illustration only. In other embodiments, the channels412A and412B may have larger or smaller dimensions, dimensions that are different from one another, etc. FIGS.12A and12Billustrate an electronics equipment cabinet500for housing one or more electronic devices, according to another example embodiment of the present disclosure. The cabinet500includes multiple cabinet walls502A-502D defining an interior enclosure space504for housing electronic device(s), and an outer wall510positioned to shield from radiation the cabinet walls502A and502C, to define a channel512between the outer wall and the cabinet walls502A and502C. The outer wall510includes two openings514A and514B extending therethrough to allow external ambient air to flow through the channel512. The cabinet500also includes two inclined plates528A and528B positioned within the channel512.FIG.12Bis a sectional view of the inclined plates528A and528B taken at point C inFIG.12A. As shown inFIG.12B, each inclined plate528A and528B includes a first end530and a second end532. Each inclined plate528A and528B is oriented at a non-parallel angle with respect to the outer wall510to increase an airflow velocity of the external ambient air traveling through the channel512via the two openings514A and514B. For example, the inclined plate528A is positioned on the outer wall510and angled outwards from outer wall510towards the first end530of the inclined plate528A. Similarly, the inclined plate528B is positioned on the side cabinet wall502A and angled outward from the side cabinet wall502A towards the first end530of the inclined plate528B. The inclined plates528A and528B may be tilted at any suitable angle with respect to the outer wall510, with respect to the cabinet wall502A, etc. For example, the inclined plates528A and528B may be tilted at an angle of about five degrees, about ten degrees, about fifteen degrees, about twenty degrees, etc. The angles may be considered as about, or substantially, a specified degree if the angle is within a manufacturing tolerance of the specified degree, within 1%, within 5%, within 10%, etc. As shown inFIG.12B, a distance between the first ends530of the included plates528A and528B may be smaller than a distance between the second ends532of the inclined plates528A and528B. The air may flow through the included plates in a direction from the second ends532towards the first ends530, and the angles of the inclined plates528A and528B may increase a velocity of the air as it flows between the plates (e.g., due to the decreasing distance between the plates, etc.). AlthoughFIG.12Aillustrates only two inclined plates528A and528B, other embodiments may include more or less inclined plates, inclined plates positioned in other locations in the cabinets100,200,300,400,500, etc. For example, the inclined plates528A and528B may be located in the channel312A and/or the channel312B of the cabinet300, the channel412A and/or412B of the cabinet400, etc. The inclined plates528A and528B may be used in other embodiments described herein. Optionally, the fans118,218,318and418may be used in the channel512to further increase air velocity through the inclined plates528A and528B, or the inclined plates528A and528B may be used without a fan in the channel512. In some embodiments, the inclined plates528A and528B may increase the velocity of air flow to an amount sufficient to reduce a temperature within the cabinet500by any suitable amount, such as about two degrees Celsius at an intake of electronic devices in the interior enclosure space504, etc. Example embodiments and aspects of the present disclosure may reduce temperatures in the cabinet relative to embodiments that do not include divider walls, outer wall channel fans, inclined plates, etc. Table 1 below lists example temperature reduction values for different combinations of features described herein. These values are for purposes of illustration only. TABLE 1Perp.ParallelFan inDividerDividerInclinedOuter WallOuter WallWall - NoWall - NoPlates -Comp.OnlyChannelFanWith FanFanWith FanNo FanSafe LimitFanNoYesNoYesNoYesNo—Rectifier 17370706768626865IntakeRectifier 27671706669626865IntakeRectifier 37570706669626865IntakeRectifier 179777874787279—ExitRectifier 281777875787380—ExitRectifier 381777874797379—Exit The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. | 30,814 |
11943894 | MODES FOR CARRYING OUT THE DISCLOSURE Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below illustrates a comprehensive or concrete example. Components which are not described in the independent claim indicating the top concept among the components in the following embodiments will be described as arbitrary components. Further, each drawing in the accompanying drawings is a schematic drawing and is not necessarily illustrated exactly. Moreover, in each drawing, the same reference characters are assigned to substantially the same components, and therefore, redundant description may be omitted or simplified. <Configuration of Robot Control Device> A configuration of a control device1for a robot according to one embodiment is described. The robot control device1is a control device which controls operation of the robot. The robot to be controlled may be any kind of robot. For example, the robot to be controlled may be various robots, such as an industrial robot, a service robot, construction machinery, a tunnel boring machine, a crane, a cargo vehicle, and a humanoid. The service robot is a robot used in various service industries, such as nursing, medical, cleaning, guard or security, guidance, rescue, cooking, and goods offering services. In this embodiment, the robot to be controlled is described as an industrial robot, such as a vertical articulated robot, a horizontal articulated robot, a polar-coordinate robot, a cylindrical-coordinate robot, and a Cartesian-coordinate robot. Such an industrial robot is provided with servo motors as drive motors for driving joints etc. A servo amplifier used for controlling the servo motor includes a power module which generates heat by being supplied with power. FIG.1is a perspective view illustrating one example of a configuration of the robot control device1according to one embodiment, when seen from the front.FIG.2is a perspective view illustrating the example of the configuration of the robot control device1according to this embodiment, when seen from the rear.FIG.3is a perspective view illustrating the example of the configuration of the robot control device1according to this embodiment in a state where a door30is opened, when seen from the front.FIG.4is a view illustrating the robot control device1ofFIG.3in a state where a blower device40is removed. Below, the “robot control device” may simply be referred to as a “control device.” As illustrated inFIGS.1to3, the control device1is provided with a casing10. In this embodiment, although the shape of the casing10is a rectangular parallelepiped shape, it may be any kind of shape without being limited to the shape. The casing10has a main body20of the rectangular parallelepiped shape, and the door30. The main body20has a rectangular first opening20a, and second openings24a-24ddisposed at a side wall24, which is one example of a wall opposing to the first opening20a. The door30has a rectangular lid shape, and is provided to the main body20so as to open and close the first opening20a. For example, the door30is attached to a side wall23of the main body20via hinges31so that it constitutes a single swinging door. The shapes of the main body20and the door30are not limited to the rectangular parallelepiped shape and the rectangular shape. The main body20may have any structure as long as it has the first opening and the second openings disposed at the wall opposing to the first opening, and the door30opens and closes the first opening. The main body20includes a bottom wall21, a top wall25, and side walls22-24, and each wall has a rectangular shape. The side walls22-24rises from three circumferential edges of the bottom wall21, and bottom edges of the side walls22-24are joined to the circumferential edges of the bottom wall21. The side walls22-24are joined to each other at adjacent side edges. The side walls22and23oppose to each other, and they are substantially parallel in this embodiment. The top wall25is disposed so as to oppose to the bottom wall21, and in this embodiment, it is substantially parallel to the bottom wall21. The three circumferential edges of the top wall25are joined to upper edges of the side walls22-24. One of the circumferential edges of the bottom wall21, one of the circumferential edges of the top wall25, and one of the side edge of each of the side walls22and23form the rectangular first opening20a. The first opening20aand the side wall24oppose to each other. Here, a direction toward the top wall25from the bottom wall21is referred to as “above” or “up,” and the opposite direction is referred to as “below” or “down.” A direction toward the side wall23from the side wall22is referred to as “right,” and the opposite direction is referred to as “left.” A direction toward the side wall24from the first opening20ais referred to as “rear,” and the opposite direction is referred to as “front.” The first opening20aopens to the front. The second openings24a-24dopen to the rear, and are arrayed in the vertical direction. Note that the number of the second openings24a-24dis not limited to four as illustrated inFIG.2. Further, in the door30, first door openings30aand30band a second door opening30cwhich penetrate the door30are formed. The number of the first door openings30aand30bis not limited to two as illustrated inFIG.1. The first door openings30aand30bare arrayed in the vertical direction. When the door30closes the first opening20a, the first door openings30aand30band the second door opening30ccommunicate the inside of the casing10with the outside. Further, the positions of the first door openings30aand30boppose to the positions of the second openings24a-24d. From the second door opening30c, a breaker switch101aprojects to the outside of the door30. The breaker switch101ais connected to a breaker101(not illustrated), and is a switch for switching the breaker101between an operating state and a non-operating state. The breaker101is a breaker which intercepts a flow of current inside the control device1when it operates. The control device1is provided with the blower device40at or near the first opening20a. The blower device40is detachably provided to the main body20. The blower device40is provided with a fan41and it is not limited to this configuration, but in this embodiment, it is provided with four fans41arrayed in the vertical direction. The four fans41are disposed so that they are adjacent to the first door openings30aand30bin the front-and-rear direction when the door30closes the first opening20a(that is, they face the first door openings30aand30b). Therefore, the four fans41are disposed at or near the first door openings30aand30b. The four fans41forcibly introduce, by driving, outside air into the casing10through the first door openings30aand30bor the second openings24a-24d, and forcibly discharge the air inside the casing10to the outside through the second openings24a-24dor the first door openings30aand30b. The control device1is provided at the door30with a holding member32, a manipulator connector50, and a manipulation panel60. The manipulator connector50is one example of a connecting device, and is configured to be physically and electrically connected to the a communication connector of a manipulator of the robot (not illustrated). The control device1communicates a signal, current, etc. with the manipulator via the manipulator connector50. The holding member32holds the manipulator of the robot. For example, the holding member32is configured so that the manipulator is hooked thereon. For example, the manipulator may be a manipulator for teaching (instructing) the robot, or may be other manipulators. The manipulation panel60is a panel for adjusting controlled parameters of the control device1. For example, in the manipulation panel60, a mode setting device61for setting the operating mode of the robot and an emergency stopping device62of the robot are disposed. In the manipulation panel60, indication lights and a display device, such as a display, for displaying various information, and an adjuster for adjusting output may be disposed, for example. The emergency stopping device62of the robot is a device for stopping the robot when it operates, and may be an input device, such as a switch, for inputting an emergency stop command. The mode setting device61may be an input device, such as a changeover switch, for setting the operating mode. The operating mode to be set may include at least one of a teaching mode, a manual operation mode, an automatic operation mode, and a correctable automatic operation mode. The teaching mode is an operating mode for teaching operation, such as a work, to the robot, and, for example, is an operating mode for programming operation to the robot by an operator manually operating the robot using the manipulator. The manual operation mode is an operating mode for manually manipulating the robot by using the manipulator, and is an operating mode for causing the robot to perform operation according to manipulation inputted into the manipulator by the operator (i.e., operation tracing the manipulation). The automatic operation mode is an operating mode for automatically operating the robot, and is an operating mode for causing the robot to automatically perform operation, such as a work, according to a program set by teaching etc. The correctable automatic operation mode is an operating mode for accepting manual operation while the robot performs the automatic operation. For example, in the correctable automatic operation mode, the automatic operation and the manual operation may be combined, or a correction to the operation by the manual operation may be accepted during the automatic operation. Note that, in the door30, at least one of the breaker switch101a, the manipulator connector50, the mode setting device61, and the emergency stopping device62of the robot may be disposed. The control device1is provided at the side wall24of the main body20with a robot connector81(seeFIG.2). The robot connector81is configured to be physically and electrically connected to a communication connector (not illustrated) of the robot. The control device1communicates a signal, current, etc. with the robot via the robot connector81. The control device1is configured so that an electric wire extending from an external power source (may also be referred to as a “primary power source”) (not illustrated) is connected to the breaker101(described later). The control device1is supplied with current etc. from the external power source. The breaker101intercepts, by being activated, the supply of current from the external power source to the control device1. FIG.5is a plan view illustrating one example of the inside of the robot control device1ofFIG.3, when seen downwardly from above. As illustrated inFIGS.3to5, the main body20has partition walls26and27which partition an interior space thereof. The partition walls26and27extend in the front-and-rear direction and the vertical direction, and partition the interior space of the main body20in the left-and-right direction. The partition walls26and27extend along the side walls22and23, and in this embodiment, they are substantially parallel to the side walls22and23. A first chamber201is formed between the side wall23and the first partition wall26. A second chamber202is formed between the partition walls26and27. Third chambers203aand203bare formed between the side wall22and the second partition wall27. The first chamber201is surrounded by the bottom wall21, the side walls23and24, the top wall25, and the first partition wall26, and opens at the first opening20a. The second chamber202is surrounded by the bottom wall21, the side wall24, the top wall25, and the partition walls26and27, and opens at the first opening20aand the second openings24a-24d. The blower device40is disposed in the second chamber202, at or near the first opening20a. The third chambers203aand203bare surrounded by the bottom wall21, the side walls22and24, the top wall25, and the second partition wall27. The third chambers203aand203bare lined up in the front-and-rear direction, and are partitioned by a third partition wall28. The third chamber203ais open at the first opening20a, and the third chamber203bis closed by the third partition wall28. Note that the third partition wall28may be configured to be detachably attached to the main body20. When necessary, by removing the third partition wall28, it is possible to access the third chamber203bthrough the first opening20a, and when unnecessary, by attaching the third partition wall28, it is possible to limit the access to the third chamber203b. When the door30closes the first opening20a, it closes the first chamber201, communicates the second chamber202with the outside via the first door openings30aand30b, and closes the third chamber203a. For example, a sealing member, such as packing, may be disposed around the first chamber201at the first opening20a, in detail, the edges of the bottom wall21, the side wall23, the top wall25, and the first partition wall26. Therefore, the first chamber201can increase airtightness or the fluidtightness by the door30and the sealing member so that it can suppress entering of foreign materials, such as particulates and dusts. The sealing member, such as packing, may be disposed at the edges of the bottom wall21, the side wall22, the top wall25, and the second partition wall27, and the inner circumference of the second door opening30c. Thus, the third chamber203acan increase the airtightness or the fluidtightness by the door30and the sealing member so that it can suppress the entering of foreign materials, such as particulates and dusts. Further, the control device1includes a first circuit90disposed inside the first chamber201, heat sinks111-114disposed inside the second chamber202, and a second circuit100disposed inside the third chambers203aand203b. The first circuit90is a circuit for controlling the drive of the robot. The first circuit90includes a servo amplifier91and a power unit92. The servo amplifier91controls the servo motor by controlling current supplied to the servo motor (not illustrated) of the robot. The servo amplifier91may also include a power module for controlling current supplied to the servo motor. The power unit92supplies electric power supplied from the external power source (not illustrated) to each part of the control device1. The power unit92may also include a rectifier circuit or an AC/DC circuit which converts AC power into DC power. The servo amplifier91generates heat when power is supplied. The power unit92includes a capacitor, and generates heat when power is supplied. The servo amplifier91is one example of a first heat generating element, and the power unit92is one example of a second heat generating element. Note that the servo motor includes an electric motor, an encoder which detects a rotation angle of a rotator of the electric motor, and a current sensor which detects a current value of the electric motor. The servo motor operates the electric motor according to the current outputted from the servo amplifier91, and outputs detection values of the encoder and the current sensor to the servo amplifier91. The servo amplifier91detects a rotated amount, a rotational speed, etc. of the rotator of the servo motor based on the detection value of the encoder fed back from the servo motor, and controls a rotation start, a rotation stop, a rotational speed, and a rotational torque of the servo motor by using the detection results, such as the rotated amount and the rotational speed of the rotator, and the current value of the current sensor. Thus, the servo amplifier91can stop the servo motor at an arbitrary rotational position, can rotate it at an arbitrary rotational speed, and can operate it at an arbitrary rotational torque. Therefore, each part of the robot which is driven by the servo motor can operate variously and precisely. The second circuit100is an electric circuit and includes the breaker101and a transformer102. The breaker101is disposed in the third chamber203a, and the transformer102is disposed in the third chamber203b. The breaker101and the transformer102are connected electrically, and the breaker101intercepts current supplied to the transformer102when it operates. The transformer102transforms electric power supplied from the external power source via the breaker101, and supplies it to the power unit92of the first circuit90. The transformer102generates heat when power is supplied. Note that, in the third chamber203b, other electric circuits may be disposed, in addition to or instead of the transformer102. The heat sinks111-113are disposed at the first partition wall26, and the heat sink114is disposed at the second partition wall27. The heat sinks111-114are made of a material with high thermal conductivity. For example, the heat sinks111-114may be made of a metal with high thermal conductivity, such as aluminum, iron, and copper. FIG.6is a cross-sectional view of the robot control device1ofFIG.5, taken along a line VI-VI. As illustrated inFIG.6, the heat sink111is disposed at the first partition wall26via a supporting plate115. The heat sink111is attached to the supporting plate115. The supporting plate115is attached to the first partition wall26, and closes an opening (not illustrated) formed in the first partition wall26. The heat sink111is exposed to the first chamber201and the second chamber202. In the first chamber201, it is configured so that heat of the servo amplifier91of the first circuit90is transferred to the heat sink111. For example, the heat sink111is disposed adjacent to the servo amplifier91via a thin insulating member (not illustrated). Further, the heat sink111integrally includes a plurality of heat sinks which project to the second chamber202, and contacts air inside the second chamber202via the plurality of heat sinks to exchange heat. Therefore, the heat sink111can radiate the heat of the servo amplifier91to the second chamber202. Moreover, the heat sink111can increase the area for exchanging the heat by the plurality of heat sinks. Note that the supporting plate115may be made of a material with high thermal conductivity, similarly to the heat sink111. The supporting plate115and the heat sink111may be made of the same material, and may be integrated. Therefore, the area for radiating the heat of the servo amplifier91to the second chamber202can be increased. Further, a reduction of the number of components is possible. The heat sinks112and113are disposed at the first partition wall26via a supporting plate116, above the heat sink111. That is, the heat sinks112and113and the heat sink111are lined up in a direction which intersects with a direction from the first door openings30aand30btoward the second openings24a-24dwhich is a direction of air flow caused by the blower device40(air-flow direction). The heat sinks112and113are attached to the supporting plate116. The supporting plate116is attached to the first partition wall26, and closes an opening (not illustrated) formed in the first partition wall26. The heat sinks112and113are exposed to the first chamber201and the second chamber202. In the first chamber201, the heat sinks112and113are configured so that heat of the power unit92of the first circuit90is transferred thereto. For example, the heat sinks112and113are disposed adjacent to the power unit92via a thin insulating member (not illustrated). Further, each of the heat sinks112and113integrally includes a plurality of heat sinks which project in the second chamber202, and contacts air inside the second chamber202via the plurality of heat sinks to exchange heat. Therefore, the heat sinks112and113can radiate the heat of the power unit92to the second chamber202. In addition, each of the heat sinks112and113can increase the area for exchanging the heat by the plurality of heat sinks. Note that the supporting plate116may be made of a material with high thermal conductivity. Further, the supporting plate116and the heat sinks112and113may be made of the same material, and may be integrated. Therefore, the area for radiating the heat of the power unit92to the second chamber202can be increased. Further, a reduction of the number of components is possible. Returning toFIG.5, the heat sink114is disposed at the second partition wall27. The heat sink114is disposed at the opposite side of the heat sinks111-113in the second chamber202. The heat sink114may be disposed at the second partition wall27via a supporting plate (not illustrated) which closes an opening (not illustrated) formed in the second partition wall27, similarly to the heat sinks111-113. The heat sink114is exposed to the second chamber202and the third chamber203b. In the third chamber203b, it is configured so that heat of the transformer102is transferred to the heat sink114. For example, the heat sink114is disposed adjacent to the transformer102via a thin insulating member (not illustrated). Further, the heat sink114integrally includes a plurality of heat sinks which project in the second chamber202, and contacts air inside the second chamber202via the plurality of heat sinks to exchange heat. Therefore, the heat sink114can radiate the heat of the transformer102to the second chamber202. Further, the heat sink114can increase the area for exchanging heat by the plurality of heat sinks. Note that the supporting plate (not illustrated) which supports the heat sink114may be made of a material with high thermal conductivity, and, further, may be made of the same material as the heat sink114, and may be integrated therewith. Therefore, the area for radiating the heat of the transformer102to the second chamber202can be increased. Further, a reduction of the number of components is possible. Moreover, the control device1may be provided with a resistor131disposed at the second partition wall27. The resistor131is exposed to the second chamber202. The resistor131is an electrical resistive element which generates heat by being supplied with power. The resistor131is electrically connected to the first circuit90, and is configured to consume surplus power from the first circuit90. The resistor131consumes the supplied electric power by generating heat. The resistor131radiates the generated heat by contacting air inside the second chamber202and exchanging heat therewith. For example, the servo motor of the robot may regenerate power, and the regenerated power may be supplied to the first circuit90and may become the excessive electric power. The first circuit90supplies the excessive electric power to the resistor131in order to protect the circuit. <Operation of Control Device> Operation of the control device1according to this embodiment is described. As illustrated inFIGS.1and2, the door30of the casing10of the control device1is closed in a normal state including a use state where the robot (not illustrated) is controlled. At this time, the first chamber201, and the third chambers203aand203bof the casing10are closed. The second chamber202is open to the outside of the casing10via the first door openings30aand30b, the first opening20a, and the second openings24a-24d. As illustrated inFIGS.5and6, when the control device1is used, the control device1is supplied with power and, thereby, the first circuit90and the second circuit100are supplied with power. The first circuit90activates the blower device40. Further, the first circuit90drives the servo amplifier91and the power unit92to operate the robot (not illustrated) electrically connected to the control device1. In detail, the first circuit90drives the servo motor to operate joint(s), end effector(s) (not illustrated) of the arm of the robot, for example. The fans41of the blower device40rotate in one direction to forcibly generate an air flow from the front of the casing10toward the rear. That is, the fans41generate the air flow which flows into the second chamber202through the first door openings30aand30band the first opening20a, and flows out of the second chamber202through the second openings24a-24d. Therefore, the second chamber202constitutes a linear passage for the gas from the first door openings30aand30btoward the second openings24a-24d. Note that the fans41may rotate in the opposite direction to the one direction. In this case, inside the second chamber202, an air flow from the second openings24a-24dtoward the first door openings30aand30bis generated. By the fans41, outside air is forcibly introduced into the second chamber202and then forcibly discharged. The introduced outside air contacts the heat sinks111-114and exchange heat to absorb the heat. Therefore, the heat of the servo amplifier91and the power unit92of the first circuit90is absorbed by the outside air via the heat sinks111-113. Further, the heat of the transformer102of the second circuit100is absorbed by the outside air via the heat sink114. Moreover, the outside air contacts the resistor131and exchanges heat to absorb the heat. The heat sink111which absorb heat from the servo amplifier91, and the heat sinks112and113which absorb heat from the power unit92are disposed in the casing10so as to be separated in the vertical direction. The heat sink111and the heat sinks112and113are not disposed in an upstream or downstream spatial relationship of the outside air flow generated by the blower device40, but are disposed in a direction which intersects with the direction of the outside air flow. The outside air with which the heat sink111exchanges heat is not outside air after a heat exchange with the heat sink112or113, but is fresh outside air introduced from the outside of the casing10. The outside air with which the heat sinks112and113exchange heat is not outside air after a heat exchange with the heat sink111, but is fresh outside air introduced from the outside of the casing10. Therefore, the heat exchange by the heat sinks111-113is possible with high efficiency. Note that, inFIG.6, although the heat sink113is located downstream of the heat sink112in the flow of the outside air inside the second chamber202, it may be disposed above or below this location so that fresher outside air can be introduced into the heat sink113. The heat sink114is disposed at the opposite side of the heat sinks111-113with respect to the second chamber202, in the left-and-right direction of the casing10(i.e., the direction perpendicular to the outside air flow). The outside air with which the heat sink114exchanges heat is outside air having low influence by the heat exchange of the heat sinks111-113. Therefore, the heat exchange by the heat sink114is possible with high efficiency. Further, the first chamber201and the third chambers203aand203bare shielded from the second chamber so that they do not accept the forcible introduction of outside air. For this reason, entering of the foreign materials into the first chamber201and the third chambers203aand203bis suppressed. Further, the inlet and the outlet of the outside air are limited to the door30at the front of the casing10, and the side wall24at the rear. Moreover, the holding member32, the manipulator connector50, the manipulation panel60, and the breaker switch101aare disposed at the door30, and the robot connector81is disposed at the side wall24. For this reason, other devices, such as other control devices1, can be disposed around the casing10so as to be adjacent to the bottom wall21, the side walls22and23, and the top wall25. For example, a plurality of control devices1may be disposed so as to be stacked in the vertical direction and the left-and-right direction. Further, as illustrated inFIGS.3and5, the door30of the casing10is opened in a non-normal state including a maintenance state of the control device1. Only by opening the single door30, one can access the first chamber201, the second chamber202, and the third chambers203aand203bthrough the first opening20a. For example, it is possible to inspect, repair, and replace the first circuit90, the blower device40, and the breaker101. Further, an inspection etc., inside the third chamber203bis possible by removing the third partition wall28. Effects Etc The robot control device1according to this embodiment as described above includes the main body20having the first opening20a, and the second openings24a-24ddisposed at the side wall24opposing to the first opening20a, the casing10having the door30provided to the main body20so as to open and close the first opening20a, the first circuit90including the servo amplifier91as the heat generating element which generates heat by being supplied with power, and at least one blower device40. The main body20has the first chamber201which accommodates the first circuit90and is open at the first opening20a, and the second chamber202which is adjacent to the first chamber201via the first partition wall26and is open at the first opening20aand the second openings24a-24d. The door30has the first door openings30aand30bwhich penetrate the door30and are disposed so as to be communicatable with the second chamber202. When the door30closes the first opening20a, it closes the first chamber201and communicates the second chamber202with the outside via the first door openings30aand30b. The at least one blower device40is disposed at at least one of the position of the first door openings30aand30b, the position near the first door openings30aand30b, the position of the second openings24a-24d, and the position near the second openings24a-24d, and it is configured to introduce and discharge air into/from the second chamber202. For example, in this embodiment, the blower device40is disposed at or near the first door openings30aand30b. According to the above configuration, when the door30closes the first opening20a, the inflow and the outflow of the outside air into/from the second chamber202are possible. Therefore, via the first partition wall26, the heat exchange of the outside air inside the second chamber202, with the air inside the first chamber201and the first circuit90is possible so that the heat of the servo amplifier91is discharged to the second chamber202, for example. Further, by the blower device40introducing or discharging the air, it becomes possible to increase the heat exchanging amount of the air inside the second chamber202. Since the blower device40is disposed at the end part of the second chamber202, it is possible to effectively use the space inside the second chamber202. Further, when the blower device40is disposed at or near the first door openings30aand30b, it is possible to access the blower device40from the door30side. For example, when the door30opens the first opening20a, the inspection, repair, replacement, etc. of the blower device40are easy. Further, since the first chamber201is closed when the door30closes the first opening20a, entering of the foreign materials into the first circuit90is suppressed. Moreover, when the door30opens the first opening20a, it is possible to access the first chamber201and the second chamber202from the outside. The inspection, repair, replacement, etc. of the first circuit90are possible. Such a control device1can implement the above functions by the simple structure. Moreover, in this embodiment, the first opening20aand the second openings24a-24dmay be disposed at the positions opposing to each other. According to this configuration, the second chamber202which uses the first opening20aor the second openings24a-24das the inlet and the outlet can form a linear passage for air therein. Therefore, since it becomes possible to make the air flow inside the second chamber202smooth, the heat exchanging efficiency with the air improves. Further, when the first opening20ais located in the front part of the casing10, the second openings24a-24dare located in the rear part of the casing10. Therefore, it is possible to dispose other objects at the sides of the casing10and above and below the casing10. For example, it is possible to dispose the casing10so as to be stacked vertically and horizontally. Therefore, the disposed space of the control device1can be reduced. Further, in this embodiment, the control device1may be provided with first heat sinks111-113disposed at the first partition wall26, and the first heat sinks111-113may be disposed so that they contact the air inside the second chamber202, and the heat of the servo amplifier91and the power unit92of the first circuit90is transferable thereto. According to this configuration, the heat of the servo amplifier91and the power unit92is transferred to the first heat sinks111-113, and the transferred heat exchanges heat with the air inside the second chamber202which contacts the first heat sinks111-113and is absorbed. The first heat sinks111-113can effectively absorb the heat of the servo amplifier91and the power unit92, and can effectively radiate the heat to the air inside the second chamber202. Therefore, an improvement in the heat exchanging efficiency is possible. Moreover, in this embodiment, the first circuit90may include the servo amplifier91and the power unit92, and at least two first heat sinks111-113may be disposed so that the heat of the servo amplifier91and the power unit92is transferable thereto. Further, the first heat sink111to which the heat of the servo amplifier91can be transferred, and the first heat sinks112and113to which the heat of the power unit92can be transferred may be disposed in a direction which intersects with the flow direction of the air generated in the second chamber202by the blower device40. According to this configuration, it is suppressed that the air after exchanging the heat with the first heat sink111exchanges the heat with the first heat sinks112and113. It is suppressed that the air after exchanging the heat with the first heat sinks112and113exchanges the heat with the first heat sink111. Therefore, all of the first heat sink111and the first heat sinks112and113can exchange heat with fresh air. Therefore, an improvement in the heat exchanging efficiency is possible. Further, in this embodiment, the control device1may include the second circuit100in the third chambers203aand203bprovided to the main body20, and the third chambers203aand203bmay be adjacent to the second chamber202via the second partition wall27. According to this configuration, it is possible to exchange heat, via the second partition wall27, between the air inside the second chamber202, the air inside the third chambers203aand203b, and the second circuit100, and the heat of the second circuit100is discharged to the second chamber202. Therefore, it is possible to discharge the heat inside the first chamber201and the third chambers203aand203bby using one second chamber202. Therefore, a simplification of the structure of the control device1is possible. Note that the third chambers203aand203bmay be disposed at the opposite side of the first chamber201with respect to the second chamber202. Since the first chamber201, the second chamber202, and the third chambers203aand203bare lined up, a downsizing of the casing10is possible. Further, in this embodiment, the control device1may be provided with the second heat sink114disposed at the second partition wall27, and the second heat sink114may be disposed so that it contacts with the air inside the second chamber202and the heat of the second circuit100is transferable thereto. According to this configuration, the second heat sink114can effectively absorb the heat of the second circuit100, and can effectively radiate the heat to the air inside the second chamber202. Therefore, an improvement in the heat exchanging efficiency is possible. Moreover, in this embodiment, the third chamber203amay be open at the first opening20a, and when the door30closes the first opening20a, it may be closed by the door30. According to this configuration, since the third chambers203aand203bare closed when the door30closes the first opening20a, entering of the foreign materials into the second circuit100is suppressed. Further, when the door30opens the first opening20a, it is possible to access the third chambers203aand203bfrom the outside. Moreover, in this embodiment, the control device1may be provided in the door30with at least one of the breaker switch101a, the manipulator connector50as the connecting device with the manipulator of the robot, the mode setting device61for the operating mode of the robot, and the emergency stopping device62of the robot. According to this configuration, the devices of the control device1which the operator operates are disposed at the door30, and therefore, the devices may be further integrated. Therefore, the control device1may be disposed in any way as long as spaces at the front of the door30and the rear of the side wall24are secured. It is possible to effectively use the spaces at the sides, and up and down of the control device1, and to reduce the disposed space of the control device1. Modification A control device1A for the robot according to one modification of the embodiment is described. The robot control device1A according to this modification differs from the above embodiment in that an electric cable extending from the first circuit90passes through the second chamber202of the casing10. Below, as for the modification, the differences from the above embodiment are mainly described, and the description similar to the above embodiment is suitably omitted. FIG.7is a view illustrating one example of the configuration of the robot control device1A according to the modification, similarly toFIG.5.FIG.8is a view illustrating one example of the configuration of the robot control device1A according to the modification, similarly toFIG.6. As illustrated inFIGS.7and8, a plurality of electric cables120aextend from the servo amplifier91. The number of electric cables120acorresponds to the number of robotic arms and the number of servo motors of the end effector. The plurality of electric cables120apass through a plurality of insulating holding members121awhich penetrate the supporting plate115, and extend into the second chamber202from the first chamber201. The electric cables120ainside the second chamber202extend into the first chamber201through an opening26aformed in the first partition wall26, and are connected to the robot connector81. Note that a sealing member, such as packing, for increasing the airtightness or the fluidtightness at the opening26amay be disposed at an inner circumference of the opening26a. Further, a plurality of electric cables120bextend from the power unit92. The plurality of electric cables120bpass through an insulating holding member121bwhich penetrates the supporting plate116, and extend into the second chamber202from the first chamber201. The electric cables120binside the second chamber202extend into the first chamber201through a plurality of insulating holding members121cwhich penetrate the supporting plate115, and are connected to the servo amplifier91. Although the electric cables120aand120bgenerate heat when power is supplied to the servo amplifier91and the power unit92, they are cooled by contacting air inside the second chamber202and exchanging heat. By the generation of the heat at the electric cables120aand120bbeing suppressed, a generation of heat at the servo amplifier91and the power unit92is suppressed. In accordance with the robot control device1A according to the modification described above, effects similar to the above embodiment can be acquired. Further, the electric cables120aand120bextending from the servo amplifier91and the power unit92of the first circuit90may be disposed so as to pass through the second chamber202. The electric cables120aand120bgenerate heat when power is supplied. Moreover, the electric cables120aand120bmay receive heat transferred from the servo amplifier91and the power unit92. The electric cables120aand120bwhich pass through the second chamber202may be cooled by exchanging heat with air inside the second chamber202. Other Embodiments As described above, although the examples of the embodiment of the present disclosure are described, the present disclosure is not limited to the embodiment and the modification. That is, various modifications and improvements are possible within the scope of the present disclosure. For example, modes obtained by applying various modifications to the embodiment and the modification, and modes built by combining the components in different embodiments and modifications also fall within the scope of the present disclosure. For example, although in the above embodiment and modification the blower device40is disposed at or near the first door openings30aand30b, it is not limited to this configuration. For example, the blower device40may be disposed at the door30, or may be disposed at any positions inside the second chamber202. The blower device40is preferably configured so as to generate the air flow in the direction toward the second openings24a-24dfrom the first door openings30aand30b, or in the opposite direction. For example, the blower devices40may be disposed both at the first door openings30aand30band near the first door openings30aand30b. For example, the blower device or the blower devices40may be disposed one or both of at the second openings24a-24dand near the second openings24a-24d. That is, at least one blower device40may be disposed at least one of the positions at the first door openings30aand30band the positions near the first door openings30aand30b, the positions at the second openings24a-24d, and the positions near the second openings24a-24d. Two or more blower devices40may be disposed. When the blower device40is disposed at the second openings24a-24dor near the second openings24a-24d, since the blower device40is disposed at an end part of the second chamber202, it is possible to effectively use the space inside the second chamber202. Further, regardless of the door30being opened and closes, it is possible to access the blower device40. For example, regardless of the door30being opened and closed, it is possible to perform the inspection, repair, replacement, etc. of the blower device40. Moreover, although, in the above embodiment and modification the servo amplifier91, the power unit92, the transformer102, etc. are disposed as the heat generating elements in the first chamber201and the third chambers203aand203bof the casing10, the heat generating elements are not limited to this configuration. The heat generating element may be an electrical component or an electronic component, such as a resistance element, or may be other heating elements, as long as it is capable of generating heat. Further, although in the above embodiment and modification the first chamber201and the third chambers203aand203bare disposed at the opposite side with respect to the second chamber202, they are not limited to this configuration. The first chamber201and the third chambers203aand203bmay be disposed in any way as long as they are adjacent to the second chamber202. For example, the first chamber201may be adjacent to the first partition wall26, and the third chambers203aand203bmay be adjacent to the bottom wall21or the top wall25. | 43,327 |
11943895 | DETAILED DESCRIPTION Aspects and advantages of the invention will become apparent from the following detailed descriptions with the accompanying drawings. For purposes of explanation, one or more specific embodiments are given to provide a thorough understanding of the invention, and which are described in sufficient detail to enable one skilled in the art to practice the described embodiments. It should be understood that the following descriptions are not intended to limit the embodiments to one specific embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as can be included within the spirit and scope of the described embodiments as defined by the appended claims. Please refer toFIG.1toFIG.5, whereFIG.1is a partial perspective view of an electronic device1according to a first embodiment of the present disclosure,FIG.2is an exploded view of the electronic device1inFIG.1,FIG.3is another partial perspective view of the electronic device1inFIG.1,FIG.4is an exploded view of the electronic device1inFIG.3, andFIG.5is a cross-sectional view of a heat dissipation component300of the electronic device1inFIG.1. In this embodiment, the electronic device1may be a computer host or a server. The electronic device1includes a main body10and a liquid cooling device20. The main body10includes a bracket11, a first electronic component12, and a second electronic component16. The first electronic component12and the second electronic component16are respectively disposed at opposite sides of the bracket11. In detail, the bracket11has a first surface11A and a second surface11B. The second surface11B faces away from the first surface11A. In one embodiment, the bracket11may be placed in a vertical manner; in this case, a normal direction of the first surface11A of the bracket11may be perpendicular to a plumb line. Note that the bracket11in other embodiments may be placed in a horizontal manner. The first electronic component12includes a first circuit board13and a first heat source14disposed on the first circuit board13. The first circuit board13is disposed on the first surface11A of the bracket11. The second electronic component16includes a second circuit board17and a second heat source18disposed on the second circuit board17. The second circuit board17is disposed on the second surface11B of the bracket11. As shown, the first circuit board13and the second circuit board17are respectively disposed at two opposite sides of the bracket11. In this arrangement, the bracket11prevents heat generated by the first electronic component12and the second electronic component16from affecting each other. In this embodiment, the first electronic component12may be a graphics card; that is, the first circuit board13may be a circuit board of the graphics card, and the first heat source14may be an image processor of the graphics card. The second electronic component16may be a motherboard assembly; that is, the second circuit board17may be a motherboard, and the second heat source18may be a central processing unit. Note that the main body10may further include a casing, a power supply, a hard disk device, etc., but these components are omitted from the drawings for simplicity. The liquid cooling device20is configured to dissipate heat generated by the first heat source14and the second heat source18. The liquid cooling device20may contain any suitable coolant (e.g., water or any typical refrigerant) circulated therein. The liquid cooling device20includes a first heat exchanger100, a second heat exchanger200, a heat dissipation component300, and a fluid driving component400. The first heat exchanger100(can be served as a cold plate) has a first inlet110and a first outlet120and is thermally coupled with the first heat source14. The second heat exchanger200(can be served as a cold plate) has a second inlet210and a second outlet220and is thermally coupled with the second heat source18. Note that “one component is thermally couple with another component” refers to the mentioned components being in direct or indirect thermal contact with each other. As shown inFIGS.2,3, and5, the heat dissipation component300(can be served as a radiator) includes a first heat inlet301, a second heat inlet302, a heat outlet303, a first inlet chamber310, a second inlet chamber320, an outlet chamber330, a first heat dissipation structure340, and a second heat dissipation structure350. The first heat inlet301and the second heat inlet302are in fluid communication with the heat outlet303. The first heat inlet301is in fluid communication with the first outlet120. The second heat inlet302is in fluid communication with the second outlet220. The first inlet chamber310is in fluid communication with the first heat inlet301. The second inlet chamber320is in fluid communication with the second heat inlet302. The outlet chamber330is in fluid communication with the heat outlet303. The first heat dissipation structure340includes a plurality of first channels341. The first channels341are in fluid communication with the first inlet chamber310and the second inlet chamber320. The second heat dissipation structure350includes a plurality of second channels351. The second channels351are in fluid communication with the second inlet chamber320and the outlet chamber330. The coolant is pumped into the heat dissipation component300via the first heat inlet301or the second heat inlet302. Taking the first heat inlet301as an example, the first heat inlet301allows the coolant to flow into the first inlet chamber310(as indicated by arrows AA), and then the coolant flows towards the second inlet chamber320via the first channels341of the first heat dissipation structure340(as indicated by arrows BB). This causes the coolant in the second inlet chamber320to flow towards the end of the second inlet chamber320located away from the first heat dissipation structure340(as indicated by arrows CC). Then, the coolant flows into the second channels351of the second heat dissipation structure350(as indicated by arrows DD) and then enter the outlet chamber330. Then, the coolant is discharged out of the outlet chamber330via the heat outlet303(as indicated by arrows EE). It is understandable that the coolant flowing through the second heat inlet302will flow as indicated by the arrows CC, DD, and EE. In specific, the second heat inlet302allows the coolant to flow into the second inlet chamber320, and then the coolant in the second inlet chamber320flows towards the end of the second inlet chamber320located away from the first heat dissipation structure340(as indicated by arrows CC). Then, the coolant flows into the second channels351of the second heat dissipation structure350(as indicated by arrows DD) and then enter the outlet chamber330. Then, the coolant is discharged out of the outlet chamber330via the heat outlet303(as indicated by arrows EE). The heat contained in the coolant can be dissipated to the ambient air while the coolant is flowing through the first heat dissipation structure340and the second heat dissipation structure350. Optionally, one or more heatsinks (not shown) can be mounted or integrally formed on the first heat dissipation structure340and/or the second heat dissipation structure350to achieve a better heat exchange efficiency. The fluid driving component400may be a pump configured to pump the coolant. The fluid driving component400has a fluid inlet410, a first fluid outlet420, and a second fluid outlet430. The fluid inlet410is in fluid communication with the heat outlet303. The first fluid outlet420is in fluid communication with the first heat inlet301via the first heat exchanger100. The second fluid outlet430is in fluid communication with the second heat inlet302via the second heat exchanger200. Accordingly, the first heat exchanger100, the second heat exchanger200, the heat dissipation component300, and the fluid driving component400together form two circulation paths. One of the circulation paths can be seen from the arrows shown inFIG.1, the coolant can be pumped through the first heat exchanger100, the heat dissipation component300, and the fluid driving component400; in specific, the coolant absorbs heat generated by the first heat source14when passing through the first heat exchanger100, then the heat contained in the coolant is dissipated to the outside when the coolant is flowing through the heat dissipation component300, and then the coolant is sent back to the fluid driving component400to finish one circulation. The other circulation path can be seen from the arrows inFIG.3, the coolant can be pumped through the second heat exchanger200, the heat dissipation component300, and the fluid driving component400; in specific, the coolant absorbs heat generated by the second heat source18when passing through the second heat exchanger200, then the heat contained in the coolant is dissipated to the outside when the coolant is flowing through the heat dissipation component300, and then the coolant is sent back to the fluid driving component400to finish the other circulation. As discussed, these two circulation path share the fluid driving component400and the heat dissipation component300; that is, these two circulation path share the same pump and the same radiator. As such, the liquid cooling device20is able to support at least two heat sources that are arranged at different places at the same time with the least number of pump and radiator possible. Thus, the liquid cooling device20is beneficial to achieve a flexible internal space utilization of the electronic device1to achieve a balance between the miniaturization of liquid cooling device20and the heat dissipation efficiency for both the central processing unit and the graphics card. Optionally, in this embodiment, the heat dissipation component300may further include a centrifugal air generator360. The centrifugal air generator360may be a centrifugal fan. The centrifugal air generator360may be located between the first heat dissipation structure340and the second heat dissipation structure350and configured to generate airflows F towards the first heat dissipation structure340and the second heat dissipation structure350to increase the heat exchange efficiency of the heat dissipation component300with outside. According to the liquid cooling device and the electronic device discussed above, these two circulation path share the fluid driving component and the heat dissipation component; that is, these two circulation path share the same pump and the same radiator. As such, the liquid cooling device is able to support at least two heat sources that are arranged at different places at the same time with the least number of pump and radiator possible. Thus, the liquid cooling device is beneficial to achieve a flexible internal space utilization of the electronic device to achieve a balance between the miniaturization of liquid cooling device and the heat dissipation efficiency for both the central processing unit and the graphics card. In addition, the first circuit board and the second circuit board are respectively disposed at two opposite sides of the bracket. In this arrangement, the bracket prevents heat generated by the first electronic component and the second electronic component from affecting each other. The embodiments are chosen and described in order to best explain the principles of the present disclosure and its practical applications, to thereby enable others skilled in the art best utilize the present disclosure and various embodiments with various modifications as are suited to the particular use being contemplated. It is intended that the scope of the present disclosure is defined by the following claims and their equivalents. | 11,780 |
11943896 | 10.Water cooler11.Cooler body111.Lower installation slot112.Positioning groove113.First water outlet114.Heat dissipation groove115.Heat sink116.Heat dissipation area117.water pump installation area12.Cooling fan121.Fan mounting seat13.Fan cover131.Upper installation slot132.First through hole133.Upper protrusion134.Light-transmitting hole135.Clamp block14.Light guide15.LED light bar16.Second through hole20.Water pump21.Shock-absorbing rubber ring22.Sealed plug-in tube30.Water block301.Third water inlet302.Third water outlet31.Water block housing311.Air outlet32.Blowing fan33.Light guide cover34.Light-shielding cover341.Light-transmission groove342.Air inlet35.Buckle40.First hose50.Second hose. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS In the description of the present application, it should be noted that the terms “center”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “inner”, “outer”, etc. which are used to indicate position or positional relationship are based on the position or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the indicated position or element must have a specific orientation and be constructed in a specific orientation and operation, therefore cannot be understood as a limitation of the present application. In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms “installation”, and “connection” should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection, or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances. As shown inFIG.1-5, a water-cooling radiator includes a water block30, a water cooler10and a water pump20. The water cooler10comprises a cooler body11, a fan assembly, and a fan cover13. A heat dissipation area116and a water pump installation area117integrally extending from one end of the heat dissipation area116are arranged on the cooler body11. The cooler body11is rectangular, the water pump installation area117is located at one end of the cooler body11in the longitudinal direction. The fan assembly is arranged on the upper side of the heat dissipation area116, and the upper surface of the water pump installation area117is recessed with a lower installation slot111corresponding to the shape of the water pump20, wherein the lower installation slot111and the fan assembly are located on the same side of the cooler body11, wherein the water pump20is detachably arranged in the lower installation slot111and the axial direction of the water pump20is parallel to the width direction of the cooler body11. The fan cover13comprises a fan shielding area corresponding to the fan assembly and a water pump shielding area corresponding to the water pump20, the fan cover13is detachably covered on the cooler body11, wherein the fan shielding area and the water pump shielding area are respectively covered on the outside of the fan assembly and the water pump20, and the water pump20is connected with the water block30through a first hose40, and the water block30is connected with the cooler body11through a second hose50. In this application, the fan cover13is detachably connected to the cooler body11by locking screws on the side. In the actual production process, the fan cover13can also be detachably connected to the cooler body11in a snap-fit manner. Since the fan cover13is a detachable structure, different styles can be set according to user requirements to meet different customer needs. By locating the lower installation slot111and the fan assembly on the same side of the cooler body11, it is more conducive to the molding of the cooler body11and the production cost is reduced; by making the axial direction of the water pump20parallel to the width direction of the cooler body11, the overall length of the cooler body11is effectively shortened, and the installation space inside the computer case is saved. Specifically, a plurality of heat dissipation grooves114connected end to end in turn are arranged on the heat dissipation area116, wherein heat sinks115are arranged between the heat dissipation grooves114, the cooler body11is provided with a first water inlet and a first water outlet113which are in communication with the heat dissipation grooves114, the water pump20is provided with a second water inlet and a second water outlet, the water block30is provided with a third water inlet301and a third water outlet302, wherein the second water outlet is connected to the third water inlet301through the first hose40, and the third water outlet302is connected to the first water inlet through the second hose50. The first water outlet113is arranged in the lower installation slot111, and the second water inlet is provided with a sealed plug-in tube22corresponding to the first water outlet113. When assembling, the sealed plug-in tube22is inserted into the first water outlet113. When the fan cover13is installed on the water cooler, the water pump20is also fixed in the lower installation slot111synchronously, to avoid the situation that the sealed plug-in tube22is loose and the water-cooling liquid leaks. An upper installation slot131corresponding to the lower installation slot111is arranged on the lower surface of the water pump shielding area of the fan cover13, a first through hole132for partially exposing the water pump20is arranged in the middle of the upper installation slot131, an upper protrusion123is formed on the upper surface of the fan cover13at a position corresponding to the upper installation slot131. In the lower surface of the water pump shielding area, clamp blocks135for positioning the water pump20are provided on both sides of the first through hole132. In the present application, the water pump20is a water pump with an independent integrated water tank, and the water tank is transparent. By providing the first through hole132, it is possible to observe whether the water-cooling liquid in the water tank of the water pump20is flowing through the first through hole132, to determine whether the water pump20is working normally. Two shock-absorbing rubber rings21are sleeved on the peripheral surface of the water pump20, which are arranged spaced apart from each other. The lower installation slot111and the upper installation slot131are both provided with positioning grooves112for fixing the shock-absorbing rubber ring21, wherein when assembling, the shock-absorbing rubber ring21is partially embedded in the positioning groove112, and a gap is maintained between the peripheral surface of the water pump20and the inner surfaces of the lower and upper installation slots111,131. Therefore, the buffer and isolation effects of the shock-absorbing rubber ring21can prevent the water pump20from colliding with the cooler body11and the fan cover13during operation, thereby reducing the generation of noise. It should be understood that the number and spacing of the shock-absorbing rubber ring21can be set according to needs. In actual use, the shock-absorbing rubber ring21can also be replaced by a shock-absorbing gasket, and the shock-absorbing rubber ring21and the shock-absorbing gasket can be made of silicone, but it can also be made of other elastic materials. In the present application, a light guide14is provided between the fan assembly and the fan cover13, and an LED light bar15for guiding the light guide14is provided on the outer side of the light guide14, and the LED light bar15is located on the inner side of fan cover13, the fan cover13is provided with a plurality of light-transmitting holes134. The light-transmitting hole134can be set in a variety of different shapes, and the light emitted by the LED light bar15is transmitted through the light-transmitting hole134to form a visual effect, which increases the overall aesthetics of the product and meets the needs of different users. Both the light guide14and the fan cover13are provided with a second through hole16for exposing the fan assembly, so that the air flow is discharged from the second through hole16when the fan assembly is working. In the present application, the fan assembly comprises a fan mounting seat121and at least one cooling fan12arranged on the fan mounting seat121. In this embodiment, the number of cooling fans12is three arranged side by side. It should be understood that the number of cooling fans12can be set according to actual needs. As shown inFIG.5, a water block housing31is arranged on the upper side of the water block30, a blowing fan32that blows downward is arranged in the water block housing31, a downwardly inclined air outlet311is arranged at the lower part of the peripheral side of the water block housing31. By providing the air blowing fan32, the air blowing fan32can assist the water block30to dissipate heat and improve the heat dissipation efficiency. By providing the downwardly inclined air outlet311at the lower peripheral side of the water block housing31, part of the air flow blown by the air blowing fan32can be guided to the circuit on the peripheral side of the CPU, so that peripheral circuits and electronic components can be actively dissipated. The water block housing31is provided with a light source (not shown), the upper end of the water block housing31is provided with a light guide cover33, and the upper side of the light guide cover33is provided with a light-shielding cover34. A light-transmitting groove341for partially exposing the light guide cover33is arranged on the light-shielding cover34, air inlet holes342are arranged on the peripheral side of the light shielding cover34. The air inlet holes342are in communication with the inside of the water block housing31. The light-transmitting groove341can be set in a variety of different shapes. Through the cooperation of the light guide cover33and the light-shielding cover34, the LED light can be transmitted from the light-transmitting groove341. In this way, different luminous effects of the cold head30can be realized, the water-cooling radiator is more personalized, and the overall aesthetics of the product is increased. The water block30is provided with a buckle35for fixing the water block30to the CPU. When in use, the buckle35is locked on the main board by screws. The cold head30is provided with a labyrinth-shaped coolant water channel separated by a large number of shovel tooth copper sheets (not shown). The cooling water channel is in communication with the aforementioned third water inlet and third water outlet, and the upper side of the coolant water channel is provided with a metal upper cover. By providing a large number of shovel tooth copper sheets, the heat conduction area can be increased, and the heat dissipation efficiency can be improved. To sum up, in the present application, by providing the water pump installation area117on the cooler body, the water pump can be fixed on the cooler body through the fan cover, so that only the water cooler and the water block need to be fixed separately during installation, which is simple and convenient to use. In addition, the water pump of the present application can choose the same high-power water pump components as the split type water-cooling radiator. Compared with a water-cooling radiator with a water block integrated with a water pump, a water-cooling radiator with a water pipe integrated with a water pump, a water-cooling radiator with a water cooler integrated with a water pump, the independent water pump of the present application can provide a larger lift for the water-cooling radiator and greatly improve the heat dissipation efficiency. At the same time, this application does not need to change the internal structure of the water-cooling radiator, which reduces the complexity of the water-cooling radiator and reduces the production cost of the enterprise. When the water pump is not working properly, it can be easily replaced, and the space required for installation has not increased, and the user does not need to purchase a larger case, which reduces the cost for the user. The above are only the preferred embodiments of the present application and are not intended to limit the application. Therefore, any modification, equivalent replacement, improvement, etc., made to the above embodiments based on the actual technology of the present application still fall within the scope of the technical solution of the present application. | 12,902 |
11943897 | DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to the drawings, the liquid dielectric cooling immersion container will now be described with regard for the best mode and the preferred embodiment. In general, the device is a customizable, modular immersion container for liquid dielectric cooling. The embodiments disclosed herein are meant for illustration and not limitation of the invention. An ordinary practitioner will appreciate that it is possible to create many variations of the following embodiments without undue experimentation by varying such factors as width, length, height, inserts, etc. Unless otherwise specified herein, references to length refer to dimensions in the L direction shown inFIG.1, references to width refer to dimensions in the W direction, and references to height refer to dimensions in the H direction. The container1components may be formed by attaching multiple plastic corrugated panels with designed channels for liquid handling (channeling), as described in more detail below. The embodiments described below can be constructed in one piece by using 3D printing technology, or by using a variety of metals, plastics, fiberglasses, carbon fiber composites, or the like. In any of the embodiments, one or more of the components discussed herein comprise acrylonitrile butadiene styrene and corresponding thermoforming methods. Some examples of the cooling liquid that could be used with the container1include water, de-ionized water, mineral oils, two-phase dielectric coolants, single-phase dielectric coolants, or a combination thereof. Referring toFIGS.1-3, one embodiment of the container1comprises a tank10, a liner11, and a support base12. The tank10, liner11, and support base12mate together to define at least one inflow channel15and at least one outflow channel16. The tank10comprises one or more corrugations17, such as a channels, grooves, furrows, or other contoured features, each defining a down-flow channel18between the liner11and the tank10. In an embodiment, the corrugations17are tapered, being narrower at the bottom and wider at the top. This enables stacking of the tanks10of the containers1in arrays, as discussed in more detail below. The corrugations17may be linear or non-linear, regular or irregular, disposed vertically, diagonally, or in any other configuration that is suitable for the purposes discussed below. Referring toFIGS.4-6, one embodiment of the tank10generally defines the box-like shape of the container1embodiment introduced above. In this embodiment, the tank10comprises two end walls19and two sidewalls20. One or more dividers21are located inside the tank10in communication with a tank bottom22of the tank10. The dividers21are disposed to mate with the liner11to define the inflow channel(s)15and outflow channel(s)16, as described in more detail below. Referring toFIGS.7-9, an embodiment of the liner11has a rectangular, or box-like, shape for mating insertion inside the tank10. The liner11has liner end walls23, liner sidewalls24aand24b, and a liner bottom25having one or more liner vents26. The liner vents26permit passage of the dielectric cooling liquid to pass from the inflow channel(s)15to the interior of the container1. The liner vents26comprise one or more ports, apertures, slots, openings, or the like. The liner further comprises a shoulder31configured to support the support base12thereon in an elevated position relative to the liner bottom25. In this manner, the liner bottom25and the support base12define a chamber32therebetween, which becomes filled with the dielectric liquid as the liquid rises through the liner vents26. In one embodiment, a first liner sidewall24ahas a height H1and a second liner sidewall24bhas a height, H2, where H1is less than H2. Referring toFIGS.10-12, in one embodiment, the liner11mates with the tank10to define the inflow channel(s)15and the outflow channel(s)16. The liner bottom25is seated against the top of the one or more dividers21forming a liquid-impermeable seal at their interface, thereby defining the inflow channel(s)15and outflow channel(s)16. Further, the liner sidewalls24aand24bmate with the sidewalls20of10tank, forming a liquid-impermeable seal therebetween. In this manner, the corrugations17in the tank sidewall20define the down-flow channel(s)18, formed between the exterior surfaces of the sidewalls24aand24bof the liner11and the interior surfaces of corrugations17of the tank10. Referring toFIGS.13-15, one embodiment of the support base12comprises a bottom panel27having one or more vents28for promoting flow of the dielectric liquid inside the container1. The vent28may be an elongated opening, such as a slot, that permits ingress of dielectric liquid in a wall-like, or curtain-like, plume. In this embodiment, each vent28preferably has an aspect ratio of 2:1 or greater. The elongate circulation vents28could have any shape meeting or exceeding this aspect ratio, whether a rectangle, oval, elongated hexagon or octagon, an arc, serpentine, or other curved shape, or the like. Alternatively, each vent28could be a plurality of point vents disposed in an orientation where the combined effect of the point vents approximates the wall-like plume emitted from a single elongate vent28. Each point vent can take a variety of shapes and forms, each having an aspect ratio of less than 2:1. The point vents could have a cross-sectional shape that is circular, triangular, square, or other regular polygonal shape, a star, a cross, or any other suitable shape. The support base12may further comprise one or more stiffeners29, such as edge walls, stems, webs, or the like. The stiffeners29provide structural support to the support base bottom panel27to carry the load of the equipment being cooled in the container1. Referring toFIGS.16-18, in one embodiment of the container1, pressurized dielectric cooling liquid enters the container1via the inlet13. The liquid then flows through the inflow channel15and rises into the interior volume of the liner11via the liner vents26. The dielectric liquid fills chamber32, which is defined between the liner bottom25and the support base12. The dielectric liquid then continues to rise through the vents28of the liner12, whereby the equipment positioned on the support base12becomes immersed into the dielectric liquid. When the dielectric liquid level reaches the top of the first sidewall24aof the liner11(height H1), the liquid flows over the first sidewall24aand enters the down-flow channels18. Gravity causes the dielectric liquid to flow through the channels18, which direct the liquid into a first outflow channel16a. The dielectric liquid then flows through the first outflow channel16aand exits the tank10via the first outlet14a. Continuous circulation of the dielectric liquid along this flow path facilitates heat transfer between the dielectric liquid and the equipment positioned on the support base12, thereby effectively cooling the immersed equipment. In the event that the first outflow channel16abecomes blocked, the level of the dielectric liquid will continue to rise above the H1level. When the liquid level exceeds the height of the second sidewall24bof the liner11(height H2), the dielectric liquid flows or cascades over the second sidewall24bof the liner11and into the down-flow channels18defined by corrugations17on the side of the tank10abutting the second sidewall24b. The liquid passes through the down-flows channels18into a second outflow channel16b, where the liquid exits the container1via the second outlet14b. Thus, the differences in wall height H1and H2provide a fail-over safety feature in the event of blockage of the first outflow channel16a. Referring toFIGS.19-22, an embodiment of the container1may comprise one or more down-flow regulators30. The down-flow regulators30enable the dielectric liquid to flow down the down-flow channel(s)18without entraining air bubbles in the dielectric liquid. Air entrainment is disadvantageous to liquid dielectric cooling because it reduces the efficiency of heat transfer facilitated by the liquid. The down-flow regulators30may be corrugations30a, pipes30b, slats30c, folds30d, spiral tubes30e, cascades30f, finned conduits30g, baffles, rods, stringers, or other similar members that promote down-flow of the dielectric liquid coolant in a manner that reduces or eliminates air entrainment in the liquid. The regulators30can be used alone or in combination with other embodiments of regulators30, and they can be used in one or more down-flow channels18.FIGS.21and22show embodiments of the regulators30disposed in certain down-flow channels18. The regulators30may be disposed in all or only some of the down-flow channels18, and the regulators30disposed within the tank10may be all of the same type or different types. Referring toFIGS.23-27, in some embodiments, the inlets13and outlets14are disposed in the tank bottom22. This configuration enables end walls19of adjacent tanks10to abut one another, without requiring a clearance therebetween to accommodate the inlet(s)13and outlet(s)14(as shown inFIG.30). Furthermore, by disposing the inlet(s)13and outlet(s)14on the tank bottom22, the container1can be efficiently positioned on a rack35, as depicted inFIGS.28and29. Referring toFIGS.28and29, in an embodiment, the rack35has a plurality of slats38configured to support one or more containers1seated thereon.FIG.29depicts that the slats38are arranged such that the inlet(s)13and outlet(s)14are positioned within the spaces between the slats38. The rack35has legs39configured to elevate the container1, thereby creating sufficient clearance between the tank bottom22and the support surface to accommodate conduits40attached to the inlet(s)13and outlet(s)14for carrying the dielectric liquid to and from the container1. In other embodiments, the container1can comprise one or more inlets13or outlets14coupled to either end wall19or sidewall20of the tank10, while one or more inlets13or outlets14may be coupled to the tank bottom22. As shown inFIG.24, the location and orientation of the dividers21, which define the configurations of the inflow channel15and the outflow channels16, can be customized to provide efficient cooling to a variety of objects having various shapes. This customization may be applied to customize the configuration of the container1for efficient cooling of irregularly shaped objects. Referring toFIGS.25-27, the liquid dielectric immersion cooling containers1may be configured to be arranged in an array, wherein two or more containers1are arranging in a mating relationship with one another in a substantially planar orientation. In this embodiment, corrugations17aof a first container1aare disposed between the corrugations17bof a second container1b, defining a mating interface36between the first container1aand the second container1b. In this embodiment, exterior spaces between adjacent corrugations17aof the first tank10adefine receiving channels37aconfigured to accept corrugations17bof the second tank10b. In this manner, the first tank10acomprises a plurality of receiving channels37afor receiving corrugations17bof the second container10b, while the second tank10bcomprises a plurality of receiving channels37bfor receiving corrugations17aof the first tank10a. This configuration enables the sidewalls of containers10aand10bto be mated with one another. Multiple containers1can be arranged in an array by mating their respective corrugations17and channels37defined therebetween. An example of an array of six containers1a-1fis depicted inFIG.30. The containers1avail themselves to being arranged in various arrays, enabling efficient and space-saving stacking configurations. FIG.30depicts that equipment42—such as computer servers, crypto currency miners, batteries, etc.—can be placed containers1to be cooled by the dielectric liquid. As explained above, the shapes of containers1and dividers21and locations of the inlets13and outlets14can be customized to efficiently accommodate various shapes of objects42. Furthermore, by arranging containers1in arrays, the conduits40carrying the dielectric liquid can also be arranged efficiently—for example, in straight lines—and can be coupled to the appropriate inlets13and outlets14of containers1. One embodiment of the container1is generally rectangular, or box-like, in shape, and it comprises at least one inlet13and at least one outlet14for circulating the dielectric liquid coolant through the container1. The embodiment shown inFIG.1is generally rectangular in a top planar view (in the L-W plane). However, other embodiments of the container could have a circular, triangular, hexagonal, or an irregular shape in top planar view, as described in more detail below. FIGS.31-34depict container1having a generally circular shape in the top planar view. In this embodiment, container1includes a tank10and a liner11. The sidewall24of the liner11is disposed in an abutting contact with the interior of the sidewall20of the tank10. The tank10includes a plurality of corrugations17, the interior surface of which defines down-flow channels18. An inlet13is coupled to sidewall20of the tank10, thereby enabling pressurized dielectric liquid to flow into the interior volume of the tank10.FIG.32depicts that the interior surface of the tank bottom22has a divider21a, while the exterior surface of the liner bottom25has a corresponding divider21b. When the liner11is seated within the tank10, the dividers21aand21bare disposed in contact with each other to form a liquid-impermeable seal at the interface thereof, thereby defining an inflow channel15and an outflow channel16. The inflow channel15is in fluid communication with the inlet13, while the outflow channel16is in fluid communication with the outlet14. As most clearly depicted inFIG.34, dielectric liquid enters the inflow channel15via the inlet13. The dielectric liquid rises through the liner vents26and fills the chamber32formed between the liner bottom25and the support base12, which is seated on the shoulders31disposed within the liner11. The dielectric liquid rises through the vents28of the support base12and fills the interior volume of the liner11, whereby one or more objects positioned therein become immersed into the dielectric liquid. In this manner, heat is transferred from the one or more objects to the dielectric liquid. As the liquid level continues to rise and exceeds the height of the liner sidewall24, the liquid spills over the liner sidewall24and into the down-flow channels18. The down-flow channels18direct the dielectric liquid into the outflow channel16, from which the dielectric liquid exits the tank10. This continuous flow of the dielectric liquid enables efficient heat transfer and removal from the equipment housed within the container1. In this manner, the dielectric liquid cools the equipment. FIGS.35-38depict an embodiment of container1having an octagonal shape in a top planar view. This embodiment functions in the substantially the same manner as the circular embodiment described above. Another embodiment of the container1is depicted inFIGS.39-41. Unlike the embodiments described above, tank10does not have corrugations defining down-flow channels. Instead,FIGS.39and40depict that the down-flow channel18formed between the interior surfaces of the tank sidewall10and an exterior surface of the liner sidewall24. The tank10has a ledge44that facilitates the down-flow of the dielectric liquid into the outflow channel16. When the liner11is positioned within the tank10, a liquid-impermeable seal is established between the divider21disposed on the tank bottom22and the exterior surface of the liner bottom25. In this manner the divider21partitions the bottom of the tank10into an inflow channel15and outflow channel16. The inflow channel15is in fluid communication with the inlet13, while the outflow channel16is in fluid communication with the outlets14. The container1depicted inFIGS.39-41operates according to the same principle of operation described with respect to other embodiments disclosed above. The dielectric liquid enters the inflow channel15via the inlet13. The dielectric liquid rises and enters the chamber32formed between the liner bottom25and the support base12via the liner vents26. As the dielectric liquid continues to rise, it flows into the interior volume of the liner11via the vents28of the support base12.FIG.41depicts that the liner vents26and the support base vents28may be disposed in an orthogonal orientation relative to one another. As the dielectric liquid continues to flow through the support base vents28, the liquid fills the interior volume of the liner11. When the liquid level rises above the sidewall24, the liquid spills over into the down-flow channel18formed between the exterior surface of the liner sidewall24and the interior surface of the tank sidewall20. Gravity causes the liquid to flow through the down-flow channel18as guided by the slope of the ledge44and into the outflow channel16. From there, the dielectric liquid exits the tank10via the outlets14. The continuous flow of the dielectric liquid removes the heat from an object seated on the support base12via heat exchange that occurs between the colder dielectric liquid and the warmer object. The heat is carried out of the container1as the warmed dielectric liquid exits the tank10via the outlets14. FIGS.42-45depict another embodiment of the container1. Unlike other embodiments disclosed herein, the tank10does not have a divider21partitioning the bottom portion of the tank10into an inflow channel15and an outflow channel16. Instead, the outflow channel16is established between the inner surface of the tank sidewall20and the exterior surface of the liner sidewall24. The ledges44create down-flow channels18, which direct the flow of the dielectric liquid into the outflow channel16, which is coupled to the outlets14, enabling the dielectric liquid to exit the tank10. FIGS.46-49depict an embodiment of the tank1that uses directional nozzles46to direct the flow of the dielectric liquid into the specific target area48on the object42to facilitate more efficient cooling of critical components or hotspots. This embodiment involves nested liners11aand11b, which are most clearly depicted in the exploded view inFIG.48and the cross-sectional view inFIG.49. In this embodiment, the inflow channel15is formed within the volume enclosed between the liner11aand the liner11b, wherein the top edges of the sidewalls24and end wall23of the liner11form a liquid-impermeable seal with the underside of the top flange52of the liner11b. The liner11bhas a plurality of apertures50configured to fluidly couple to directional nozzles46. The dielectric liquid enters the liner11afrom the inlet13via opening51. The dielectric liquid then fills the inflow channel15formed between the interior surfaces of the sidewalls24and end walls23of the liner11aand the corresponding exterior surfaces of the tank11b. From the inflow channel15, the dielectric liquid flows into the directional nozzles46, which eject the dielectric liquid into target area48. To further control the flow of the dielectric liquid, some or all of the apertures50that are not coupled to directional nozzles46may be closed with designated plugs, thereby directing the flow of the dielectric liquid exclusively through the nozzles46. As the dielectric liquid enters the interior volume of the liner11b, the liquid level rises, filling the interior volume of the liner11band immersing the objects42into the dielectric liquid. When the liquid level exceeds the height of the sidewalls of the liner11b, the dielectric liquid begins to spill over the sidewalls and the end walls of the liner11band into the down-flow channels18formed between the interior surface of the corrugations17and the exterior surface of the liner11a. Down-flow regulators30may be disposed within one or more down-flow channels18. Gravity causes the dielectric liquid to flow through down-channels18into the outflow channel16, formed between the exterior surface of the liner bottom25and the interior surface of the tank bottom22. The dielectric liquid exits that tank10via the outlets14. In all of the embodiments described above, a pump can be used to circulate the dielectric liquid through the container1and control the pressure and the flow rate of the dielectric liquid through the container1. In addition, the dielectric liquid can be cooled upon exiting the container1and then the cooled dielectric liquid can reintroduced into the tank thereby maintaining circulation of cold dielectric liquid through the container1. The foregoing embodiments are merely representative of the liquid dielectric immersion-cooling container and not meant for limitation of the invention. For example, persons skilled in the art would readily appreciate that there are several embodiments and configurations of tanks, liners, inflow channels, outflow channels, down-flow channels, and support bases that will not substantially alter the nature of the immersion-cooling container and can be exchanged between the embodiments disclosed herein. In addition, although the above description focuses on cooling the objects positioned within the container, a person of ordinary skill in art will recognize that substantially the same technique can be used to heat or otherwise regulate the temperature of the objects without departing from the principles of the invention. Consequently, it is understood that equivalents and substitutions for certain elements and components set forth above are part of the invention described herein, and the true scope of the invention is set forth in the claims below. | 21,724 |
11943898 | DESCRIPTION OF EMBODIMENTS An embodiment of the present disclosure will hereinafter be described with reference to the drawings.FIGS.1A to1Hand the like illustrate an electronic apparatus1as an example of the embodiment. In the following description, X1and X2illustrated inFIGS.1A to1Hwill be set as a right direction and a left direction, respectively, Y1and Y2will be set as a forward direction and a rearward direction, respectively, and Z1and Z2will be set as an upward direction and a downward direction, respectively. However, these directions are defined to describe the shape, relative positional relation, movement, and the like of elements (parts, members, and portions) of the electronic apparatus1and do not limit the attitude of the electronic apparatus1at a time of usage. For example, whileFIG.1Aand the like illustrate the electronic apparatus1in a horizontal placement attitude, the electronic apparatus1may be disposed in a vertical placement attitude at a time of usage. (The “vertical placement attitude” is an attitude in which the right side surface or left side surface of the electronic apparatus1is a lower side.) The electronic apparatus1is, for example, an entertainment device that functions as a game device or an audio-visual apparatus. The electronic apparatus1outputs, to a display device such as a television, moving image data generated by executing a game program, video and audio data obtained through a network, and video and audio data obtained from a recording medium such as an optical disk. The electronic apparatus may, for example, be a personal computer. <General Configuration> As illustrated inFIG.2A, the electronic apparatus1includes an apparatus main body10, an upper exterior panel20A that covers the upper side of the apparatus main body10, and a lower exterior panel20B that covers the lower side of the apparatus main body10. As illustrated inFIG.3, the apparatus main body10includes a circuit board50, internal devices such as a heat radiating device70, and a housing30that houses the internal devices. The housing30includes an upper housing member30A that covers the upper side of the circuit board50, and a lower housing member30B that covers the lower side of the circuit board50. These housings are combined with each other in an upward-downward direction. The upper housing member30A forms the upper surface of the apparatus main body10. The lower housing member30B forms the lower surface of the apparatus main body10. The upper exterior panel20A may be detachable from the upper housing member30A. The lower exterior panel20B may be detachable from the lower housing member30B. The exterior panels20A and20B and the housing members30A and30B include, for example, a resin such as an acrylonitrile butadiene styrene (ABS) resin or a polycarbonate. As illustrated inFIG.1A, the apparatus main body10may have a power button2aand an optical disk ejecting button2bin the front surface of the apparatus main body10. The apparatus main body10may also have connectors3aand3bin the front surface thereof. Further, the apparatus main body10may have connectors4ato4e(seeFIG.1G) in the back surface of the apparatus main body10. As illustrated inFIG.3, the apparatus main body10includes, as internal devices, a cooling fan5, the heat radiating device70, and an optical disk drive6in addition to the circuit board50and a power supply unit60. As will be described later, the heat radiating device70includes heat sinks71and72(seeFIG.6B) and heat pipes73A to73F (seeFIG.13B). The upper surface of the circuit board50is covered by an upper board shield51that blocks electromagnetic waves from electronic parts mounted on the upper surface. The lower surface of the circuit board50is covered by a lower board shield52that blocks electromagnetic waves from electronic parts mounted on the lower surface. The board shields51and52are respectively attached to the upper surface and lower surface of the circuit board50. The board shields51and52are a metallic plate. The material of the metallic plates may be, for example, iron, stainless steel, aluminum, or the like. <Outline of Part Layout> The power supply unit60and the heat radiating device70are, for example, disposed on the upper side of the circuit board50(more specifically, on the upper side of the upper board shield51). An integrated circuit50a(seeFIG.3) that functions as a central processing unit (CPU), a graphics processing unit (GPU), or the like is mounted on the upper surface of the circuit board50. The integrated circuit50ais a heat generating device and is connected to the heat radiating device70. The power supply unit60is also a heat generating device. An airflow generated by the cooling fan5is supplied to the heat radiating device70and the power supply unit60. The layout of internal devices such as the heat radiating device70, the power supply unit60, and the cooling fan5is not limited to the example of the electronic apparatus1. The optical disk drive6is, for example, disposed on the lower side of the circuit board50(more specifically, on the lower side of the lower board shield52). A heat radiating device80(seeFIG.7A) may be disposed on the lower side of the circuit board50. An electronic part (for example, a power transistor that generates driving power for the integrated circuit50a) is mounted on the lower surface of the circuit board50. The heat radiating device80may be connected to this electronic part. <Cooling Fan> As illustrated inFIG.7A, the cooling fan5is disposed such that a rotational center line Cf of the cooling fan5is along the thickness direction of the circuit board50(upward-downward direction in the electronic apparatus1). In addition, the cooling fan5is disposed on the outside of an outer edge of the circuit board50. The cooling fan5is, for example, disposed on the right side of a right edge of the circuit board50. In the description here, the upward-downward direction of the electronic apparatus1is a direction along a normal to the circuit board50. In addition, directions referred to in the present specification do not limit the attitude of the electronic apparatus1at a time of usage. Hence, in a case where the electronic apparatus1is disposed in a vertical placement attitude, for example, the rotational center line Cf of the cooling fan5is a line along a left-right direction. The cooling fan5may have a part located above a horizontal plane Hp1including the circuit board50and a part located below the horizontal plane Hp1including the circuit board50. More specifically, a plurality of fins5athat rotate about the rotational center line Cf may each have a part5blocated above the horizontal plane Hp1and a part5clocated below the horizontal plane Hp1. This arrangement of the cooling fan5can generate an airflow F1along the upper surface of the circuit board50and an airflow F2along the lower surface of the circuit board50. It is therefore possible to cool heat generating devices arranged or mounted on the upper side of the circuit board50and heat generating devices arranged or mounted on the lower side of the circuit board50without increasing the number of parts. As illustrated inFIG.2A, the upper housing member30A has an upper inlet port31alocated on the upper side of the cooling fan5. As illustrated inFIG.2B, the lower housing member30B has a lower inlet port31blocated on the lower side of the cooling fan5. By thus respectively forming the inlet ports31aand31bin the upper surface and lower surface of the housing30, it is possible to take air into the inside of the housing30efficiently. An amount of heat generation of the heat generating devices arranged on the upper surface of the circuit board50may be larger than an amount of heat generation of the heat generating devices arranged on the lower surface of the circuit board50. For example, a total amount of heat generation of the integrated circuit50aand the power supply unit60arranged on the upper surface of the circuit board50may be larger than a total amount of heat generation of electronic parts50c(for example, a power transistor and an integrated circuit such as a memory) arranged on the lower surface of the circuit board50. When the heat generating devices are thus arranged, a center Ch of the cooling fan5in the upward-downward direction may be located above the horizontal plane Hp1including the circuit board50, as illustrated inFIG.7A. This enables a large amount of air to be supplied to the devices that generate a large amount of heat. As illustrated inFIG.7A, a distance D5between the upper inlet port31aand the lower inlet port31bcorresponds to a width in the upward-downward direction of the cooling fan5. Therefore, air is drawn in from the inlet ports31aand31band smoothly flows in the radial direction of the cooling fan5. In the example of the electronic apparatus1, a lower portion (specifically, a base plate5d, seeFIG.3) of the cooling fan5is attached to the edge of the lower inlet port31b. On the other hand, an upper end (specifically, an upper end of a rotor5e) of the cooling fan5is located at substantially the same height as the edge of the inlet port31a. A distance in the upward-downward direction between the upper housing member30A and the lower housing member30B at the positions of the inlet ports31aand31b, that is, the distance D5(seeFIG.7A) between the inlet ports31aand31b, may be smaller than a distance between the upper housing member30A and the lower housing member30B at other positions. In the example of the electronic apparatus1, the upper housing member30A has a recessed plate portion32a(seeFIG.2A) in an upper surface thereof. The recessed plate portion32ais recessed to the circuit board50side with respect to another portion32cin the upper surface. (In the description here, the other portion32cwill be referred to as a “main plate portion.”) The upper inlet port31ais formed in the recessed plate portion32a. The heat radiating device70, the power supply unit60, and the like are arranged between the main plate portion32cand the circuit board50. Similarly to the upper housing member30A, the lower housing member30B has a recessed plate portion32bin a lower surface thereof. As illustrated inFIG.2B, the recessed plate portion32bis recessed with respect to another portion32din the lower surface. (In the description here, the other portion32dwill be referred to as a “main plate portion.”) The lower inlet port31bis formed in the recessed plate portion32b. Fins81(seeFIG.8AandFIG.8B) of the heat radiating device80are arranged between the main plate portion32dand the circuit board50. Then, a distance between the upper and lower recessed plate portions32aand32bcorresponds to the height of the cooling fan5. According to this structure, it is possible to secure a sufficient distance between the upper and lower main plate portions32cand32dand secure a sufficient space for the heat radiating devices70and80arranged between the upper and lower main plate portions32cand32dwhile making the distance between the inlet ports31aand31bcorrespond to the height of the cooling fan5. As illustrated inFIG.3, the cooling fan5includes the rotor5ehaving the plurality of fins5aand the base plate5dthat supports the rotor5e. The rotor5eis rotatable relative to the base plate5d. As illustrated inFIG.8B, the base plate5dmay, for example, have a ring-shaped peripheral portion5f, a central portion5glocated on the inside of the peripheral portion5f, and bridges5ithat couple the peripheral portion5fand the central portion5gto each other. Such a base plate5dmay be attached to the lower housing member30B. Specifically, the ring-shaped peripheral portion5fmay be attached to the edge of the lower inlet port31b. Because such a base plate5dis located on the lower side of the cooling fan5, the air resistance of an upper portion of the cooling fan5is smaller than the air resistance of a lower portion of the cooling fan5. As described above, the amount of heat generation of the heat generating devices arranged on the upper surface of the circuit board50is larger than the amount of heat generation of the heat generating devices arranged on the lower surface of the circuit board50. That is, the cooling fan5is disposed such that the upper portion of the cooling fan5having a small air resistance corresponds to a flow passage in which the devices that generate a large amount of heat are arranged. The circuit board50may have a curved edge50b(seeFIG.15) curved in the shape of an arc as a right edge of the circuit board50. The cooling fan5is disposed on the inside of the curved edge50b. According to this arrangement of the circuit board50and the cooling fan5, an airflow can be generated on both the upper surface and lower surface of the circuit board50while an increase in size of the electronic apparatus1is suppressed. <Positional Relation between Cooling Fan and Heat Sink> The power supply unit60and the heat radiating device70may be abreast of each other in the left-right direction. For example, as illustrated inFIG.6B, a first heat sink71is disposed on the right of the power supply unit60. The cooling fan5may be disposed such that the center line Cf of the cooling fan5is located on the right of a right end of the first heat sink71. In the example of the electronic apparatus1, the whole of the cooling fan5is located on the right of the right end of the first heat sink71. According to this layout, the first heat sink71and the cooling fan5do not interfere with each other even when a size in a front-rear direction of the first heat sink71is increased. It is therefore possible to suppress an increase in size in the front-rear direction of the whole of the electronic apparatus1while securing a sufficient size in the front-rear direction of the first heat sink71. In the description here, the front-rear direction of the heat sink71is a direction in which air passes through the heat sink71. The left-right direction is a direction orthogonal to the direction in which air passes through the heat sink71. In addition, the directions referred to in the present specification do not limit the attitude of the electronic apparatus1at a time of usage. Hence, for example, the power supply unit60and the heat radiating device70may be arranged next to each other in the front-rear direction, and the cooling fan5and the heat sink71may also be arranged next to each other in the front-rear direction. In such a case, a size in the left-right direction of the heat sink71can be increased. As illustrated inFIG.6B, the cooling fan5is located rearward of a front end61nof a power supply unit case61to be described later. In addition, the center line Cf of the cooling fan5is located rearward of a front end of the first heat sink71. As illustrated inFIG.6B, a second heat sink72(heat radiating device) may be disposed on the right of the first heat sink71. Then, at least a part of the cooling fan5may be located in front of the second heat sink72. According to this arrangement of the cooling fan5and the second heat sink72, air flowing rearward from the cooling fan5can also be used effectively. As illustrated inFIG.6B, a width of the second heat sink72in the front-rear direction may be smaller than a width of the first heat sink71in the front-rear direction. Then, the cooling fan5may be disposed in front of the second heat sink72. According to this arrangement of the heat sinks71and72and the cooling fan5, it is also possible to make effective use of air flowing rearward from the cooling fan5while suppressing an increase in size in the front-rear direction of the electronic apparatus1. As will be explained later in detail, the heat radiating device70has a plurality of heat pipes73A to73F (seeFIG.13B). The two heat sinks71and72are thermally connected to each other by the plurality of heat pipes73. In addition, the two heat sinks71and72are fixed to a common base plate75(seeFIG.13A). Incidentally, unlike the example of the electronic apparatus1, the first heat sink71and the second heat sink72may not be coupled to each other by heat transfer means such as the heat pipes. For example, the second heat sink72may be used to cool a heat generating part (for example, an electronic part) different from the integrated circuit50ato which the first heat sink71is connected. In addition, the part disposed on the right of the first heat sink71and in the rear of the cooling fan5may not be the heat sink72. For example, a heat generating part (for example, an electronic part) to be cooled may be disposed in the rear of the cooling fan5. <Air Flow Passages between Housings and Exterior Panels> The upper surface of the housing30is covered by the upper exterior panel20A. A clearance Ua (seeFIG.20A) that allows air to flow to the upper inlet port31amay be formed between the upper surface of the housing30and the upper exterior panel20A. (The clearance Ua will hereinafter be referred to as an upper flow passage.) As described above, the upper surface of the upper housing member30A has the recessed plate portion32a(seeFIG.2A) recessed with respect to the main plate portion32c. The recessed plate portion32ais, for example, formed in a right front portion of the upper housing member30A, and the upper inlet port31ais formed in the recessed plate portion32a. For example, the upper flow passage Ua is secured between the recessed plate portion32aand the upper exterior panel20A. The upper flow passage Ua may, for example, open toward the front side and/or the right side of the electronic apparatus1. That is, an inlet port may be provided between a front edge of the upper surface of the upper housing member30A (specifically, a front edge of the recessed plate portion32a) and a front edge of the upper exterior panel20A, or an inlet port may be provided between a right edge of the upper surface of the upper housing member30A (specifically, a right edge of the recessed plate portion32a) and a right edge of the upper exterior panel20A. In the example of the electronic apparatus1, as illustrated inFIG.1CandFIG.1E, there is provided an inlet port Ea which continues from the upper surface of the upper housing member30A and the front edge of the upper exterior panel20A to the right edge of the upper exterior panel20A. The inlet port Ea may, for example, continue from a center in the left-right direction of the front edge of the upper exterior panel20A to a rear portion of the right edge of the upper exterior panel20A. The upper housing member30A may have louvers33A in the inlet port Ea. The lower surface of the housing30is covered by the lower exterior panel20B. The lower surface of the housing30and the lower exterior panel20B of the electronic apparatus1may have the same structure as the above-described structure of the housing30and the upper exterior panel20A. That is, a clearance Ub (seeFIG.20A) that allows air to flow to the lower inlet port31bmay be formed between the lower surface of the housing30and the lower exterior panel20B. (The clearance Ub will hereinafter be referred to as a lower flow passage Ub.) As described above, the lower surface of the lower housing member30B has the recessed plate portion32b(seeFIG.2B) recessed with respect to the main plate portion32d. The recessed plate portion32bis, for example, formed in a right front portion of the lower housing member30B, and the lower inlet port31bis formed in the recessed plate portion32b. For example, the lower flow passage Ub is secured between the recessed plate portion32band the lower exterior panel20B. The lower flow passage Ub may also, for example, open toward the front side and/or the right side of the electronic apparatus1. That is, an inlet port may be provided between a front edge of the lower surface of the lower housing member30B (specifically, a front edge of the recessed plate portion32b) and a front edge of the lower exterior panel20B, or an inlet port may be provided between a right edge of the lower surface of the lower housing member30B (specifically, a right edge of the recessed plate portion32b) and a right edge of the lower exterior panel20B. In the example of the electronic apparatus1, as illustrated inFIG.1CandFIG.1E, there is provided an inlet port Eb which continues from the lower surface of the lower housing member30B and the front edge of the lower exterior panel20B to the right edge of the lower exterior panel20B. The inlet port Eb may, for example, continue from a center in the left-right direction of the front edge of the lower exterior panel20B to a rear portion of the right edge of the lower exterior panel20B. The lower housing member30B may have louvers33B in the inlet port Eb. A part other than the recessed plate portion32ain the upper surface of the upper housing member30A, that is, the main plate portion32c, and the upper exterior panel20A are in proximity to each other. The main plate portion32cand the upper exterior panel20A may be in contact with each other, or a clearance having a smaller width in the upward-downward direction than the upper flow passage Ua may be formed between the main plate portion32cand the upper exterior panel20A. The airflows formed by driving the cooling fan5are discharged rearward from an exhaust port M (seeFIG.1GandFIG.6A) formed in the back surface of the housing30. Louvers33C and33D may be formed in the exhaust port M. As illustrated inFIG.2A, the main plate portion32cmay have a part32elocated on the rear side of the recessed plate portion32a. According to this structure, the main plate portion32ccan prevent the air exhausted rearward from the exhaust port M from flowing toward the inlet port31aagain. A part other than the recessed plate portion32bin the lower surface of the lower housing member30B, that is, the main plate portion32d, and the lower exterior panel20B are in proximity to each other. The main plate portion32dand the lower exterior panel20B may be in contact with each other, or a clearance having a smaller width in the upward-downward direction than the lower flow passage Ub may be formed between the main plate portion32dand the lower exterior panel20B. As illustrated inFIG.2B, the main plate portion32dmay have a part32flocated on the rear side of the recessed plate portion32b. According to this structure, the main plate portion32dcan prevent the air exhausted rearward from the exhaust port M from flowing toward the inlet port31bagain. The external surface of the electronic apparatus1is curved such that a width in the upward-downward direction of the electronic apparatus1is increased in a right front portion of the electronic apparatus1in which the inlet ports31aand31bare formed. In other words, the exterior panels20A and20B are curved such that a distance between the exterior panels20A and20B is increased in the right front portion of the electronic apparatus1. This external shape of the electronic apparatus1makes it easy to secure sufficient widths in the upward-downward direction of the above-described flow passages Ua and Ub. The curves of the exterior panels20A and20B will be explained later in detail. Incidentally, the positions of the inlet ports31aand31bformed in the housing30and the positions of the inlet ports Ea and Eb formed between the housing30and the exterior panels20A and20B are not limited to the example illustrated in the electronic apparatus1. For example, the inlet ports31aand31bmay be formed in a left portion of the housing30. In addition, the inlet ports31aand31bmay be formed in only either the upper surface or the lower surface of the housing30. The positions of the inlet ports Ea and Eb may be changed as appropriate according to the positions of the inlet ports31aand31b. As illustrated inFIG.6A, the electronic apparatus1may have a fan guard38A that is attached to the edge of the inlet port31aand covers the upper side of the cooling fan5. Similarly, the electronic apparatus1may have a fan guard38B that is attached to the edge of the inlet port31band covers the lower side of the cooling fan5. As illustrated inFIG.10A, the fan guard38A includes a plurality of rings38a, a central portion38blocated in the center of the plurality of ring38a, and a plurality of spokes38cextending from the outside rings38ato the central portion38b. In the example of the electronic apparatus1, the cooling fan5rotates in a clockwise direction as viewed in plan. The spokes38care inclined so as to conform to the direction of rotation of the cooling fan5. Specifically, the spokes38care inclined with respect to a radial direction so as to advance in the clockwise direction toward the center Cf. According to this structure, the spokes38ccan avoid becoming an air resistance. As illustrated inFIG.10B, the positions of the plurality of rings38aand the position of the central portion38bare raised toward the center Cf. In addition, the spokes38cextend obliquely so as to be raised toward the center Cf. This can increase the area of openings formed between the rings38aand the spokes38c. As described above, the spokes38cextend obliquely so as to be raised toward the center Cf. On the other hand, each of the rings38amay have a cross section along a plane perpendicular to the rotational center line Cf of the cooling fan5(plane Hp5inFIG.10B). This can increase the area of the openings formed between the rings38aand the spokes38c. The upper exterior panel20A is disposed on the upper side of the fan guard38A. As described above, the upper exterior panel20A is curved. The fan guard38A may be curved in conformity with the curve of the upper exterior panel20A. The fan guard38B that covers the lower side of the cooling fan5may have the same structure as the upper fan guard38A. That is, the fan guard38B may be obtained by inverting the upper surface and lower surface of the fan guard38A. <Power Supply Unit> As illustrated inFIG.7B, the power supply unit60includes a power supply circuit62and a power supply unit case61that houses the power supply circuit62. The power supply unit case61has a wall portion61alocated in front of the first heat sink71. A plurality of air intake holes61bmay be formed in the wall portion61a. (The wall portion61awill hereinafter be referred to as an “intake air wall.”) As illustrated inFIG.6B, the heat sinks71and72have a plurality of fins71aand72aabreast of one another in the left-right direction. Therefore, air passes through the heat sinks71and72in the front-rear direction. The intake air wall61ais disposed obliquely with respect to the front-rear direction and the left-right direction. The external surface of the intake air wall61afaces the first heat sink71. Here, the “external surface of the intake air wall61afaces the first heat sink71” means that a straight line extending from the external surface and perpendicular to the external surface intersects the first heat sink71. The cooling fan5is disposed so as to send air to the intake air wall61a. In the example of the electronic apparatus1, the cooling fan5is separated rightward from the external surface of the intake air wall61a. An airflow from the cooling fan5to the intake air wall61ais formed by flow passage walls34A and34B to be described later. According to the shape and disposition of the power supply unit case61, as illustrated inFIG.6B, a part of the air reaching the intake air wall61apasses through the air intake holes61band enters the inside of the power supply unit case61. In addition, another part of the air reaching the intake air wall61amoves to the first heat sink71while guided by the intake air wall61a. That is, the intake air wall61amakes it possible to secure an airflow to be supplied to the first heat sink71, and cool the power supply unit60by a cold air (air not warmed by another heat generating device or heat radiating device) at the same time. When the power supply unit60can be cooled by the cold air, a clearance between circuit parts62aand62bincluded in the power supply circuit62(for example, a transformer and a capacitor) can be reduced, so that the power supply unit60can be miniaturized. The power supply unit case61includes a case rear portion61clocated on the left side of the first heat sink71and a case front portion61dextending frontward beyond the position of the front end of the first heat sink71. In the example of the electronic apparatus1, the intake air wall61ais a right side wall of the case front portion61dand extends obliquely frontward and rightward from a right side wall61fof the case rear portion61c. On the other hand, a left side wall61eof the power supply unit case61extends frontward in a straight manner from the case rear portion61cto the case front portion61d. Hence, a width in the left-right direction of the case front portion61dincreases gradually toward the front. As illustrated inFIG.11B, the air intake holes61bmay be formed obliquely with respect to the intake air wall61a. That is, a center line Ch1of an air intake hole61bmay be inclined with respect to the intake air wall61a. For example, the center line Ch1of the air intake hole61bmay be along the left-right direction. This makes it easy for the air discharged from the cooling fan5to pass through the intake air wall61a. Incidentally, the structure of the air intake hole61bis not limited to the example of the electronic apparatus1. The center line Ch1of the air intake hole61bmay be inclined with respect to both the left-right direction and the front-rear direction in conformity with the direction of the airflow. For example, the center line Ch1may extend obliquely frontward and rightward from the intake air wall61a. As illustrated inFIG.11AandFIG.11B, air intake holes61mmay also be formed in the right side wall61fof the case rear portion61c. In such a case, a direction in which the air intake holes61mpenetrate the right side wall61f, that is, the direction of a center line Ch2of an air intake hole61m, may be the same as that of the air intake holes61bin the intake air wall61a. This can facilitate formation of the two kinds of air intake holes61band61m. As illustrated inFIG.7B, a part of the power supply circuit62may be disposed in a space provided within the case front portion61dand secured by the inclination of the intake air wall61a, that is, a space Sf (seeFIG.6B) formed on the inside of the intake air wall61a. Circuit parts62bincluded in the power supply circuit62are housed in this space and are located in front of the first heat sink71. According to such a layout, it is possible to make effective use of the volume of the power supply unit case61. The circuit parts62barranged in the space formed on the inside of the intake air wall61amay have a smaller size than other parts62a. This can facilitate an airflow within the power supply unit case61. A plurality of exhaust holes61gand61hmay be formed in the case rear portion61c. More specifically, as illustrated inFIG.7C, the plurality of exhaust holes61gmay be formed in a rear wall61iof the case rear portion61c, and the plurality of exhaust holes61hmay be formed in a rear portion61kof an upper wall61jof the power supply unit case61. In the example of the electronic apparatus1, the rear portion61kof the upper wall61jis recessed with respect to a front portion of the upper wall61j. Due to this recess, an air flow passage Se is secured between the upper housing member30A and the rear portion61k. The positions of the exhaust holes61gand61hare not limited to the example illustrated in the electronic apparatus1. For example, the exhaust holes61hformed in the upper wall61jmay not be present. A plurality of exhaust holes may be formed in a rearmost portion of the left side wall61e. <Flow Passage Walls Defining Air Flow Passage> The heat radiating device70includes the first heat sink71and the second heat sink72abreast of each other in the left-right direction. The cooling fan5is located in front of the second heat sink72. As illustrated inFIG.4andFIG.6B, the upper housing member30A may have a flow passage wall34A that defines the flow passage of the airflow sent out from the cooling fan5and guides the airflow toward the first heat sink71. The flow passage wall34A has a part curved along the outer circumference of the cooling fan5. In the example of the electronic apparatus1, the whole of the flow passage wall34A is curved. As illustrated inFIG.6B, as a distance from a starting point34aof the flow passage wall34A increases in the extending direction of the flow passage wall34A, a distance from the cooling fan5to the flow passage wall34A (distance in the radial direction of the cooling fan5) increases. The flow passage wall34A extends from the periphery of the cooling fan5toward the intake air wall61aof the power supply unit case61. The intake air wall61ais located on an extension of an end34bof the flow passage wall34A. Such a flow passage wall34A enables the air from the cooling fan5to be sent to the intake air wall61asmoothly. The intake air wall61amay be curved similarly to the flow passage wall34A. For example, the flow passage wall34A is formed along a curve defined by a predetermined function. The intake air wall61amay be disposed along the same curve. For example, the flow passage wall34A is formed along a clothoid curve having the rotational center line Cf of the cooling fan5as an origin. In such a case, the intake air wall61amay also be curved along the same clothoid curve. Thus, a smooth airflow is formed from the cooling fan5to the intake air wall61aand the first heat sink71. Incidentally, the curve on which the curving of the flow passage wall34A and the intake air wall61ais based may be, for example, an involute curve, a logarithmic spiral, a Nielsen spiral, or the like instead of the clothoid curve. The flow passage wall34A surrounds the periphery of the cooling fan5located on the outside of the outer edge of the circuit board50. The flow passage wall34A extends downward from a part forming the upper surface of the apparatus main body10in the upper housing member30A (the part is the recessed plate portion32ain the example of the electronic apparatus1). A lower edge of the flow passage wall34A may reach the lower housing member30B. In the example of the electronic apparatus1, as illustrated inFIG.4andFIG.8B, a flow passage wall34B that projects upward is formed on the lower housing member30B. Similarly to the flow passage wall34A, the flow passage wall34B defines the flow passage of the airflow sent out from the cooling fan5. The flow passage wall34B has a part curved along the periphery of the cooling fan5. In the example of the electronic apparatus1, similarly to the flow passage wall34A, the whole of the flow passage wall34B is curved. As illustrated inFIG.7B, the lower edge of the flow passage wall34A of the upper housing member30A is connected to the flow passage wall34B of the lower housing member30B in the upward-downward direction. The flow passage walls34A and34B are connected to each other to form one wall extending along the periphery of the cooling fan5. In the example of the electronic apparatus1, the flow passage walls34A and34B function as a wall on the front side of the cooling fan5. The structure of the flow passage walls34A and34B is not limited to the example of the electronic apparatus1. For example, only either the upper housing member30A or the lower housing member30B may have a flow passage wall formed thereon. Then, the flow passage wall formed on the one housing member may extend upward or downward until reaching the other housing member. As illustrated inFIG.4, the electronic apparatus1has a front exterior panel35that covers the flow passage walls34A and34B as a part of exterior members. The front exterior panel35is located on the front side and right side of the curved flow passage walls34A and34B and covers the whole of the flow passage walls34A and34B. Due to the presence of the front exterior panel35, a degree of freedom can be secured for the shape of the flow passage walls34A and34B. A circuit board mounted with switches operated by the power button2aand the optical disk ejecting button2bmay be attached to the front exterior panel35, or a circuit board mounted with the connectors3aand3bmay be attached to the front exterior panel35. <Air Flow Passage on Lower Side of Circuit Board> As described above, the power supply unit60and the heat radiating device70are arranged on the upper surface of the circuit board50, and the power supply unit60and the heat radiating device70are abreast of each other in the left-right direction. The air sent out from the cooling fan5passes through the heat radiating device70and the power supply unit case61. Hence, an airflow is formed in the whole of a space between the circuit board50and the upper housing member30A. On the other hand, the lower side of the circuit board50may be provided with a member that reduces the width of an air flow passage between the circuit board50and the lower housing member30B. Then, the width of the air flow passage between the lower surface of the circuit board50and the lower housing member30B may be narrower than the width of the air flow passage between the upper surface of the circuit board50and the upper housing member30A. This facilitates securing of a speed of an airflow formed on the lower side of the circuit board50. In the example of the electronic apparatus1, the optical disk drive6is disposed on the lower side of the circuit board50. The optical disk drive6reduces the width of the air flow passage between the circuit board50and the lower housing member30B. As illustrated inFIG.8B, the optical disk drive6is separated leftward from the cooling fan5as viewed in plan of the electronic apparatus1. The optical disk drive6has a disk drive case6a. A spindle motor (not illustrated) that rotates an optical disk, a pickup module (not illustrated), and the like are arranged within the disk drive case6a. As illustrated inFIG.8B, an air flow passage Sb from the cooling fan5to the exhaust port M (seeFIG.8A) is formed between the cooling fan5and the disk drive case6a. The disk drive case6alimits the air flow passage Sb to a right region on the circuit board50. The disk drive case6ahas a right side wall6bthat faces the cooling fan5and that extends in the front-rear direction at a position separated leftward from the cooling fan5. The air flow passage Sb is formed between the right side wall6band the cooling fan5. The plurality of fins81included in the heat radiating device80are arranged at a midpoint of the air flow passage Sb. A wall defining the air flow passage Sb may be formed on the lower housing member30B. As illustrated inFIG.4andFIG.8B, for example, the lower housing member30B may have a flow passage wall34cthat extends from the periphery of the cooling fan5toward the heat radiating device80. In the example of the electronic apparatus1, the flow passage wall34cextends from a starting point of the above-described flow passage wall34B curved on the periphery of the cooling fan5, toward the heat radiating device80. Incidentally, the electronic apparatus1may not have the optical disk drive6. In such a case, a wall may limit the air flow passage Sb. A wall portion formed on the lower housing member30B may be used as a member that reduces the width of the air flow passage between the circuit board50and the lower housing member30B as compared with the air flow passage between the circuit board50and the upper housing member30A. As illustrated inFIG.4, an opening30ccorresponding in size and shape to the disk drive case6ais formed in the lower housing member30B. The lower surface of the disk drive case6amay be exposed downward from the opening30c. According to this structure, the width in the upward-downward direction of the electronic apparatus1can be reduced by the thickness of the lower housing member30B. <Dust Collecting Chamber> As illustrated inFIG.6B, a dust collecting chamber Ds may be provided to the flow passage wall34A. The dust collecting chamber Ds captures dust included in the airflow formed on the upper side of the circuit board50and collects the captured dust. According to this structure, it is possible to reduce an amount of dust entering devices arranged downstream of the dust collecting chamber Ds, the devices being the first heat sink71, the power supply unit60, and the like. The dust collecting chamber Ds is defined by a dust collecting chamber wall34C (seeFIG.5). The dust collecting chamber wall34C is in a box shape opening in two directions to be described later. The dust collecting chamber wall34C is, for example, formed integrally with the upper housing member30A. This makes it possible to secure the dust collecting chamber Ds without increasing the number of parts. In addition, because the upper housing member30A is a member that covers the whole of the internal devices, a degree of freedom of the position of the dust collecting chamber Ds can be secured when the dust collecting chamber wall34C is formed integrally with the upper housing member30A. As viewed in plan of the electronic apparatus1, the cooling fan5rotates in the clockwise direction about the rotational center line Cf. In the example of the electronic apparatus1, the flow passage wall34A extends in the clockwise direction from the starting point34aof the flow passage wall34A along the periphery of the cooling fan5. The whole of the flow passage wall34A is curved. The dust collecting chamber Ds may be provided to the thus curved flow passage wall34A. More specifically, the dust collecting chamber Ds may be located at an end portion of the flow passage wall34A. The position of the dust collecting chamber Ds is not limited to the example of the electronic apparatus1. The dust collecting chamber Ds may be provided at a midpoint of the flow passage wall34A. Two devices each of which is a heat generating device or a heat radiating device may be disposed downstream of the air flow passage formed by the flow passage wall34A. The dust collecting chamber Ds may be located upstream of the two devices. In the example of the electronic apparatus1, the power supply unit60and the first heat sink71are located downstream of the air flow passage defined by the flow passage wall34A. The dust collecting chamber Ds is located upstream of the power supply unit60and the first heat sink71. In such a manner, sending dust to the two devices can be prevented by the one dust collecting chamber Ds. In the example of the electronic apparatus1, the dust collecting chamber Ds is located between the intake air wall61aof the power supply unit case61and the flow passage wall34A. As illustrated inFIG.12, the dust collecting chamber Ds has a first opening A1that opens in a direction along the circuit board50toward an air flow passage Sa defined by the flow passage wall34A and the intake air wall61a. Dust included in air flowing through the air flow passage Sa is captured from the first opening A1into the dust collecting chamber Ds. The dust collecting chamber Ds also has a second opening A2that opens to the outside of the air flow passage Sa in a direction intersecting the circuit board50. According to this structure of the dust collecting chamber Ds, the dust can be collected in the dust collecting chamber Ds, and the collected dust can be discharged through the second opening A2by relatively simple work. The direction in which the second opening A2opens is, for example, a direction orthogonal to the circuit board50. The second opening A2opens to the outside of the housing30, more specifically, to the upper side of the upper housing member30A. The upper exterior panel20A covers the second opening A2and prevents exposure of the second opening A2to the outside. A user can expose the second opening A2by removing the upper exterior panel20A from the upper housing member30A and extract the dust collected in the dust collecting chamber Ds. For example, the dust collected in the dust collecting chamber Ds can be sucked by a vacuum cleaner. In addition, because the upper exterior panel20A is used as a member that covers the second opening A2, an increase in the number of parts can be suppressed. The dust collecting chamber wall34C defining the dust collecting chamber Ds has a side wall34e(seeFIG.12) that extends downward from an edge of the second opening A2. As illustrated inFIG.6B, a part34fof the side wall34eis located between the flow passage wall34A and the intake air wall61aand faces the air flow passage Sa. (The part34fwill hereinafter be referred to as an “inner wall.”) The inner wall34fmay be curved in conformity with the flow passage wall34A. For example, the inner wall34fmay be formed along the curve of a function defining the curve of the flow passage wall34A (for example, a clothoid curve). Further, in another example, as indicated by a broken line inFIG.6B, the inner wall34fmay extend to the inside of the curve of the function defining the curve of the flow passage wall34A (for example, the clothoid curve). This can enlarge the first opening A1and increase an amount of air entering the dust collecting chamber Ds. As illustrated inFIG.12, the dust collecting chamber wall34C may have a bottom portion34glocated at a lower edge of the side wall34e. The dust captured in the dust collecting chamber Ds is collected on the bottom portion34g. The bottom portion34gmay have a bank portion34halong the edge of the first opening A1. According to this, it is possible to prevent the dust collected on the bottom portion34gfrom returning to the air flow passage Sa. The bottom portion34gmay be attached to the circuit board50by a boss34iand a screw59. Incidentally, when the upper exterior panel20A is attached to the upper housing member30A, a clearance may be formed between the edge of the second opening A2and the upper exterior panel20A. This facilitates formation of an airflow that enters the dust collecting chamber Ds from the first opening A1and that is discharged to the outside from the dust collecting chamber Ds through the second opening A2. Incidentally, the structure of the dust collecting chamber Ds is not limited to the example of the electronic apparatus1. For example, instead of using the upper exterior panel20A as a cover that covers the second opening A2, a dedicated cover (lid) that covers the second opening A2may be provided to the second opening A2. In another example, the dust collecting chamber Ds may be formed in the power supply unit case61instead of being formed in the upper housing member30A. As illustrated inFIG.27, a third opening A3may be formed in the upper housing member30A in addition to the second opening A2of the dust collecting chamber Ds. In an example illustrated inFIG.27, the upper housing member30A covers a heat radiating device170(seeFIGS.26A to26C) to be described later as a modification of the heat radiating device70. Fins171aof a heat sink171A on a front side are inclined with respect to the front-rear direction and the left-right direction. Therefore, a substantially triangular space is generated between a fin171clocated at an end portion in the heat sink171A and the right wall portion61fof the power supply unit case61. The third opening A3is located directly above this space. According to this structure, dust collected in the space between the heat sink171A on the front side and the right wall portion61fof the power supply unit case61can be extracted through the third opening A3. For example, the dust collected in this space can be sucked by a vacuum cleaner. <Heat Radiating Device on Upper Side> As illustrated inFIG.13B, the heat radiating device70has the plurality of heat pipes73A to73F in addition to the heat sinks71and72. In the example of the electronic apparatus1, the heat radiating device70has six heat pipes73A to73F. However, the number of heat pipes may be two or three, or may be larger than six. In the following description, in cases where the plurality of heat pipes73A to73F are not distinguished from each other, a reference numeral73is used for the plurality of heat pipes73A to73F. In addition, as illustrated inFIG.13A, the heat radiating device70may have the base plate75. The heat sinks71and72are fixed to the upper side of the base plate75. The fins71aand72aof the heat sinks71and72are, for example, fixed to the base plate75by solder. As illustrated inFIG.14A, each heat pipe73has a heat receiving portion73athermally connected to the integrated circuit50amounted on the circuit board50. Here, the “heat receiving portion73athermally connected to the integrated circuit50a” means that the heat receiving portion73aand the integrated circuit50aare in direct contact with each other or connected to each other via a metallic part having a high thermal conductivity such as copper or aluminum such that the heat of the integrated circuit50ais transmitted to the heat receiving portion73a. In the example of the electronic apparatus1, the heat receiving portion73ais a part located directly above the integrated circuit50a. The heat radiating device70may have a heat transfer member74disposed between the heat pipe73and the integrated circuit50a. The heat receiving portion73amay be connected to the integrated circuit50avia the heat transfer member74. As illustrated inFIG.14A, the heat receiving portions73aof the plurality of heat pipes73are abreast of each other in the left-right direction and may be in contact with the heat receiving portions73aof adjacent heat pipes73. The cross section of the heat receiving portions73ais substantially rectangular, and the heat receiving portions73ahave an upper surface, a lower surface, a left side surface, and a right side surface. Those side surfaces of the heat receiving portions73aare in contact with those of adjacent heat receiving portions73a. Two adjacent heat receiving portions73amay be in direct contact with each other or may be in contact with each other via a layer of a thermally conductive grease or the like. As illustrated inFIG.14A, each heat receiving portion73ahas a width W1in the upward-downward direction and has a width W2in the left-right direction. The width W1in the upward-downward direction is larger than the width W2in the left-right direction. According to this structure, it becomes easy to increase the number of heat pipes73. As a result, it becomes easy to increase the size of the heat sinks71and72to which the heat of the integrated circuit50ais transmitted through the heat pipes73. In the example of the electronic apparatus1, the width W2in the left-right direction is smaller than ¾ of the width W1in the upward-downward direction. The width W2in the left-right direction may be smaller than ⅔ of the width W1in the upward-downward direction. The width W2in the left-right direction may be larger than ½ of the width W1in the upward-downward direction. As illustrated inFIG.14A, a total width Wa (width in the left-right direction) of the heat receiving portions73aof the plurality of heat pipes73may correspond to a width in the left-right direction of the integrated circuit50a. More specifically, a difference in width between the total width Wa and the integrated circuit50amay be smaller than the thickness of one heat pipe73(the width W2in the left-right direction of a heat receiving portion73a). In the example of the electronic apparatus1, this difference is smaller than half of the thickness of one heat pipe73. Because the total width Wa thus corresponds to the width of the integrated circuit50a, all of the heat pipes73can be made to function effectively. As illustrated inFIG.14A, the heat transfer member74has two side portions74bseparated from each other in the left-right direction and a groove74aformed between the two side portions74b. The width of the groove74ain the left-right direction corresponds to the total width Wa of the heat receiving portions73aof the plurality of heat pipes73. The heat receiving portions73aof all of the heat pipes73are arranged within the groove74a. The side surfaces of heat receiving portions73alocated at a respective right and left ends may be in contact with the inner surface (side portion74b) of the groove74aof the heat transfer member74. The depth of the groove74acorresponds to the width W1in the upward-downward direction of the heat receiving portions73a. Therefore, the height of the upper surfaces of the heat receiving portions73aand the height of the upper surfaces of the side portions74bsubstantially coincide with each other. Lower edges of the fins71aincluded in the heat sink71are fixed to the upper surfaces of the side portions74b. The fins71aare fixed to the upper surfaces of the side portions74bby solder, for example. According to the side portions74b, heat can also be transmitted to the fins71alocated on the right side and left side of the heat receiving portions73a. The width in the upward-downward direction and the width in the left-right direction of the heat pipes73may be changed in the extending direction of the heat pipes73. Then, the heat pipes73may include a part whose width in the upward-downward direction is smaller than the width in the left-right direction in contrast to the heat receiving portions73a. This can facilitate bending of the heat pipes73and improve conductivity of heat from the heat pipes73to the heat sinks71and72. In the example of the electronic apparatus1, the width in the upward-downward direction of all of the heat pipes73changes in the extending direction of the heat pipes73. Unlike the example of the electronic apparatus1, the width in the upward-downward direction of only a part of the heat pipes73may be changed in the extending direction of the heat pipes73. As illustrated inFIG.13B, each of the heat pipes73has parts73band73cin contact with the heat sinks71and72at positions separated from the heat receiving portion73a(seeFIG.14A) in the extending direction of the heat pipe73. In the following, the part73bin contact with the first heat sink71will be referred to as a first heat radiating portion, and the part73cin contact with the second heat sink72will be referred to as a second heat radiating portion. For example, as illustrated inFIG.14B, the heat pipes73C and73D have a second heat radiating portion73cthat extends rightward on the lower side of the second heat sink72and is connected to the lower edge of each fin72a. The heat pipes73E and73F have a second heat radiating portion73cthat extends rightward on the upper side of the second heat sink72and is connected to the upper edge of each fin72a. In addition, as illustrated inFIG.13B, the heat pipes73A to73F have a first heat radiating portion73bin contact with the lower edge of the first heat sink71. A width possessed by the second heat radiating portions73cin a direction orthogonal to the extending direction of the second heat radiating portions73cand the upward-downward direction may be larger than a width possessed by the second heat radiating portions73cin the upward-downward direction. In the example of the electronic apparatus1, as illustrated inFIG.14B, the second heat radiating portions73chave a width W3in the upward-downward direction and have a width W4in the front-rear direction. Then, the width W4in the front-rear direction is larger than the width W3in the upward-downward direction. This makes it possible to transmit heat from the second heat radiating portions73cto the second heat sink72efficiently. Similarly, a width possessed by the first heat radiating portions73bin a direction orthogonal to the extending direction of the first heat radiating portions73band the upward-downward direction may be larger than a width possessed by the first heat radiating portions73bin the upward-downward direction. This can improve thermal conductivity from the first heat radiating portions73bto the first heat sink71. In each of the heat pipes73, the width W1in the upward-downward direction of the heat receiving portion73ais larger than the width in the upward-downward direction of the heat radiating portions73band73c(W1>W3). On the other hand, the width of the heat radiating portions73band73cin a direction orthogonal to the extending direction of the heat radiating portions73band73cand the upward-downward direction (for example, the width W4of the second heat radiating portions73c) is larger than the width of the heat receiving portions73ain a direction orthogonal to the extending direction of the heat receiving portions73aand the upward-downward direction (that is, the width W2) (W4>W2). According to this structure, it is possible to avoid a change in outer circumferential length of the cross section of each heat pipe73. Incidentally, the heat radiating portions73band73cmay not be arranged on the upper side or lower side of the heat sinks71and72. For example, the second heat radiating portions73cmay extend in the left-right direction on the front side or the rear side of the second heat sink72. In such a case, the width in the upward-downward direction of the second heat radiating portions73cmay be larger than the width in the front-rear direction. Further, in another example, holes that penetrate the respective fins72aof the second heat sink72in the left-right direction may be formed in the fins72a. Then, the second heat radiating portions73cmay be inserted into the through holes. In such a case, the upper surfaces and/or lower surfaces of the second heat radiating portions73cmay be in contact with edges of the through holes of the heat sink72. Then, the width in the front-rear direction of the second heat radiating portions73cmay be larger than the width in the upward-downward direction. The radius of curvature of an angular portion73dof a heat receiving portion73a(seeFIG.14A) may be smaller than the radius of curvature of an angular portion or a side portion of the heat radiating portions73band73c(for example, a side portion73eillustrated inFIG.14B). Thus, the cross section of the heat receiving portion73aapproaches a rectangle, so that the plurality of heat pipes73can be arranged on the upper side of the integrated circuit50aefficiently. As illustrated inFIG.14C, each of the heat pipes73has an intermediate portion73hlocated between the integrated circuit50amounted on the circuit board50and the first heat sink71. The intermediate portion73his a part located between the heat receiving portion73aand the first heat radiating portion73b. As viewed in plan of the heat radiating device70, the intermediate portions73hof the plurality of heat pipes73spread in a direction orthogonal to the extending direction of each heat receiving portion73a(left-right direction in the example of the electronic apparatus1) (seeFIG.13B). As illustrated inFIG.14C, an upper surface73iof the intermediate portion73his connected to the lower edge of a fin71aof the first heat sink71. The upper surface73iis parallel with the circuit board50and the lower edge of the fin71a. On the other hand, a lower surface73jof the intermediate portion73hmay be inclined such that a width W7in the upward-downward direction of the intermediate portion73his gradually decreased with an increase in distance from the heat receiving portion73a. This can improve a degree of freedom of the layout of the electronic parts50cbelow the intermediate portion73h. Incidentally, the lower surface73jof the intermediate portion73hmay not necessarily be inclined. A plurality of steps may be formed in the lower surface73jsuch that the width W7in the upward-downward direction of the intermediate portion73his gradually decreased. The base plate75has a bottom portion75clocated under the intermediate portion73h. A plurality of steps may be formed in the bottom portion75cto bias the lower surface73jof the intermediate portion73hto the heat sink71side. As described above, the second heat radiating portions73cof the heat pipes73E and73F are arranged along the upper side of the second heat sink72. Therefore, as illustrated inFIG.13A, the two heat pipes73E and73F may have a curved portion73gbending upward from the lower side of the first heat sink71to the upper side of the second heat sink72. As illustrated inFIG.9, the curved portion73ghas a width W5in the upward-downward direction. In addition, the curved portion73ghas a width W6in a direction orthogonal to the extending direction of the curved portion73gand the upward-downward direction (front-rear direction in the example illustrated inFIG.9). Then, the width W6may be larger than the width W5in the upward-downward direction. According to this structure of the heat pipes73E and73F, the heat pipes73E and73F are bent upward easily. Incidentally, the direction in which the curved portion73gis bent is not limited to the upward-downward direction. For example, in a case where the second heat radiating portion73cis disposed on the front side or the rear side of the second heat sink72, the curved portion73gmay be bent to the front side or the rear side. In such a case, the width of the curved portion73gin the upward-downward direction may be larger than the width of the curved portion73gin the front-rear direction. FIGS.26A to26Cis a diagram illustrating the heat radiating device170as a modification of the heat radiating device70.FIG.27is a plan view of the apparatus main body10having the heat radiating device170. InFIG.27, the heat radiating device170is covered by the upper housing member30A. In the heat radiating device170, the first heat sink71illustrated inFIG.13Aand the like is separated into two heat sinks171A and171B (two fin blocks) in a direction along the airflow (front-rear direction in the example of the electronic apparatus1), as illustrated inFIG.26A. The heat sinks171A and171B are fixed to the common base plate75. In addition, the heat sinks171A and171B are coupled to each other by common heat pipes73having heat receiving portions73athermally connected to the integrated circuit50amounted on the circuit board50. The heat sink171A on the front side is located leftward of the center line Cf of the cooling fan5, and a line along the left-right direction passes through the center line Cf and the heat sink171A (seeFIG.27). The heat transfer member74and the heat receiving portions73aof the heat pipes73are fixed to the heat sink171A on the front side (fin block on the front side). The heat sink171A on the front side is connected to the integrated circuit50athrough the heat transfer member74and the heat receiving portions73a. The heat sink171B on the rear side (fin block on the rear side) is located in the rear of the heat sink171A. The heat radiating portions73cof the plurality of heat pipes73are fixed to the heat sink171B on the rear side. The second heat sink72and the heat sink171B on the rear side are abreast of each other in the left-right direction. In the following description, the heat sink171A on the front side will be referred to as a first front heat sink, the heat sink171B will be referred to as a first rear heat sink, and the heat sink72will be referred to as a second heat sink as in the example ofFIG.13A. As illustrated inFIG.26A, the front edge of the first rear heat sink171B is separated rearward from the rear edge of the first front heat sink171A, and a gap Gn is secured between the front edge of the first rear heat sink171B and the rear edge of the first front heat sink171A. According to this structure, air that has passed through the rear edge of the first front heat sink171A is mixed in the gap Gn (that is, the flow of the air is disturbed in the gap Gn), and thereafter, the air enters the first rear heat sink171B. Therefore, the air into which heat is to be radiated is distributed to the whole of the first rear heat sink171B easily. As a result, it is possible to make effective use of the first rear heat sink171B and thus improve cooling performance. As illustrated inFIG.26A, in the heat radiating device170, the heat sinks171A and171B have a plurality of fins171aand171b, respectively, abreast of one another in the left-right direction. The fins171aincluded in the first front heat sink171A are inclined with respect to both the front-rear direction and the left-right direction. The wall61athat sends air to the first front heat sink171A (the intake air wall of the power supply unit case61, seeFIG.6B) is formed in front of the first front heat sink171A. Each of the fins171amay be inclined in the same direction as the wall61a. This enables air to pass through the heat sink171A smoothly. In the example of the electronic apparatus1, the wall61aextends obliquely rearward and leftward from the front edge of the wall61a. Similarly to the wall61a, each of the fins171aextends obliquely rearward and leftward from the front edge of the fin171a. The fins171aand the wall61amay not be parallel with each other. On the other hand, each of the fins171bof the first rear heat sink171B is arranged along the front-rear direction. Therefore, the fins171aof the first front heat sink171A are inclined with respect to the fins171bof the first rear heat sink171B. The gap Gn preferably secures a size necessary for air to be mixed. The gap Gn may, for example, be larger than ⅕ of the width in the front-rear direction of the first front heat sink171A. The gap Gn may be larger than ¼ of the width in the front-rear direction of the first front heat sink171A. In the example illustrated inFIG.26A, the intermediate portions73hof the plurality of heat pipes73are exposed in the gap Gn. As illustrated inFIG.26B, the upper surfaces of the heat receiving portions73aof the heat pipes73and the upper surfaces of the heat transfer member74are in contact with the lower edges of the fins171aof the first front heat sink. The heat radiating portions73cof the plurality of heat pipes73are in contact with the lower edges of the fins171bof the first rear heat sink171B. Hence, in the example illustrated inFIGS.26A to26C, the heat sinks171A and171B are both in contact with parts of the heat pipes73in which the widths W1and W3(FIG.14AandFIG.14B) in the upward-downward direction of the heat pipes73are uniform. <Heat Radiating Device on Lower Side> As illustrated inFIG.15, the heat radiating device80disposed on the lower surface of the circuit board50includes a base plate82, a plurality of fins81, and a heat pipe83. As illustrated inFIG.16A, the heat pipe83is disposed between the lower board shield52and the circuit board50. An opening52ais formed in the lower board shield52. The fins81are arranged on the inside of the opening52aand are exposed to the outside of the lower board shield52(lower side of the lower board shield52in the example of the electronic apparatus1). The fins81are arranged in the above-described air flow passage Sb (seeFIG.8B) formed between the circuit board50and the lower housing member30B. The base plate82is, for example, a metallic plate of copper, aluminum, stainless steel, or the like. The base plate82is formed by pressing the metallic plate. That is, parts possessed by the base plate82are formed by one metallic plate. The plurality of fins81are supported by the base plate82. The fins81are, for example, fixed to the lower surface of the base plate82by solder, for example. As illustrated inFIG.15, the heat pipe83has a heat receiving portion83nat a position separated from the fins81. The heat pipe83is in an L-shape, for example. The heat receiving portion83nis disposed between the optical disk drive6and the circuit board50described above. The fins81are arranged in a region not overlapping the optical disk drive6(region on the right side of the optical disk drive6in the example of the electronic apparatus1). In a process of manufacturing the circuit board50(process of mounting electronic parts on the circuit board50), a jig may be pressed against the surface of the circuit board50to suppress a warp in the circuit board50. The heat pipe83may have a shape in conformity with a region against which the jig is pressed. The heat receiving portion83nis in contact with the electronic parts50cmounted on the lower surface of the circuit board50. The electronic parts50care, for example, power transistors that generate driving power for the integrated circuit50a(specifically, a CPU) mounted on the upper surface of the circuit board50, from power supplied from the power supply unit60. The parts and devices cooled by the heat radiating device80are not limited to transistors, and the heat radiating device80may be used to cool a memory. As illustrated inFIG.16A, the heat pipe83has a connecting portion83aon an opposite side from the heat receiving portion83n. The connecting portion83ais located between the fins81and the circuit board50and extends in the left-right direction. A holding recessed portion82fextending in the left-right direction is formed in the lower surface of the base plate82. The lower surface of the base plate82is recessed upward in the holding recessed portion82f. A first through hole82gthat penetrates the base plate82in the left-right direction is formed at a left end of the holding recessed portion82f. A second through hole82hthat penetrates the base plate82in the left-right direction is formed at a right end of the holding recessed portion82f. The connecting portion83ais inserted into the holding recessed portion82ffrom the first through hole82gon the left side, for example, and is held within the holding recessed portion82f. The connecting portion83ais, for example, fixed to the holding recessed portion82fby solder. The holding recessed portion82fand the connecting portion83aare both a part extending linearly. As illustrated inFIG.16A, gaps G1and G2are generated between edges of the opening52aof the lower board shield52and the fins81. Specifically, the gap G1is generated between the edge (left edge) of the opening52aand a fin81located at a left end, and the gap G2is generated between the edge (right edge) of the opening52aand a fin81located at a right end. As illustrated inFIG.16A, the base plate82may have a plate left portion82clocated on the left side of the holding recessed portion82f. The plate left portion82cmay cover the lower surface of the heat pipe83(surface on the board shield52side) and close the gap G1. This can prevent electromagnetic waves from being transmitted outside the lower board shield52from the gap G1. The plate left portion82cmay have a size larger than the gap G1in the front-rear direction and close the whole of the gap G1. Similarly, as illustrated inFIG.16A, the base plate82may have a plate right portion82dlocated on the right side of the holding recessed portion82f. The plate right portion82dmay cover the lower surface of the heat pipe83(surface on the board shield52side) and close the gap G2. This can prevent electromagnetic waves from being transmitted outside the lower board shield52from the gap G2. The plate right portion82dmay have a size larger than the gap G2in the front-rear direction and close the whole of the gap G2. As illustrated inFIG.16A, the plate left portion82chas a width T1larger than a distance (gap G1) between the fin81located at the left end among the plurality of fins81and the edge (left edge) of the opening52aof the board shield52. Therefore, as viewed in plan of the circuit board50, the plate left portion82cis superposed on the fin81located at the left end and is also superposed on the edge of the opening52aof the board shield52. As a result, electromagnetic waves can be prevented from leaking from the gap G1effectively. In the example of the electronic apparatus1, a plurality of fins81are superposed on the plate left portion82c. As illustrated inFIG.16A, the plate right portion82dhas a width T2larger than a distance (gap G2) between the fin81located at the right end among the plurality of fins81and the edge (right edge) of the opening52aof the board shield52. Therefore, as viewed in plan of the circuit board50, the plate right portion82dis superposed on the fin81located at the right end and is also superposed on the edge of the opening52aof the board shield52. As a result, electromagnetic waves can be prevented from leaking from the gap G2effectively. In the example of the electronic apparatus1, a plurality of fins81are also superposed on the plate right portion82d. As illustrated inFIG.16B, the base plate82has a plate front portion82aand a plate rear portion82blocated on opposite sides from each other in the front-rear direction with the holding recessed portion82finterposed therebetween. The plate front portion82a, the plate rear portion82b, the plate left portion82c, and the plate right portion82dare coupled to one another and surround the holding recessed portion82f. The four parts82ato82dare located in the same plane along the circuit board50. The edges of the fins81are fixed to the lower surface of the plate front portion82aand the lower surface of the plate rear portion82bby solder, for example. Heat transmitted from the heat pipe83to the holding recessed portion82fis transmitted to the fins81via the plate front portion82aand the plate rear portion82b. The plate front portion82aextends frontward from the holding recessed portion82fand is superposed on the edge of the opening52aof the board shield52. The plate rear portion82bextends rearward from the holding recessed portion82fand is superposed on the edge of the opening52aof the board shield52. Thus, the base plate82may be superposed on the entire perimeter of the edges of the opening52aof the board shield52. This can effectively prevent electromagnetic waves from leaking. Each of the parts82ato82dmay be fixed to the edge of the opening52aof the board shield52by a fixture such as a screw or a rivet. The fixing structure of the base plate82and the lower board shield52is not limited to the example of the electronic apparatus1. For example, only the plate front portion82aand the plate rear portion82bmay be provided with a fixture for fixing the base plate82to the lower board shield52. As illustrated inFIG.16B, a width W11in the left-right direction of the first through hole82gmay be larger than a width (width in the left-right direction) of one fin81. Similarly, a width W12in the left-right direction of the second through hole82hmay be larger than the width (width in the left-right direction) of one fin81. The first through hole82gis closed by the plurality of fins81. The second through hole82his also closed by the plurality of fins81. Each fin81has, at an upper edge thereof, a fixing portion81bbent to an adjacent fin81. The fixing portion81bis in contact with the adjacent fin81, and there is no gap between the two fins81adjacent to each other. This can also prevent electromagnetic waves from leaking from a range between the two fins81adjacent to each other. As illustrated inFIG.16B, the base plate82may have a stopper82kthat faces an end in the left-right direction (right end in the example of the electronic apparatus1) of the heat pipe83, in the left-right direction. When the connecting portion83aof the heat pipe83is inserted into the holding recessed portion82ffrom the left side in a process of manufacturing the heat radiating device80, the stopper82kcan reduce a relative positional displacement between the connecting portion83aand the holding recessed portion82f. Incidentally, in the example of the electronic apparatus1, the base plate82has the plate left portion82cand the plate right portion82dthat are superposed on the edges of the opening52aof the board shield52, on the right side and left side of the holding recessed portion82f, respectively. Unlike this example, only either the plate left portion82cor the plate right portion82dmay be superposed on the edge of the opening52aof the board shield52. Further, in another example, the base plate82may not have the holding recessed portion82f. In such a case, the heat radiating device80may have a back plate that sandwiches the connecting portion83aof the heat pipe83together with the base plate82.FIGS.17A to17Care diagrams illustrating an example of such a heat radiating device. In the example illustrated in these diagrams, a heat radiating device180has a base plate182and a back plate184. As illustrated inFIG.17B, the base plate182is disposed between the connecting portion83aof the heat pipe83and the fins81. The upper edges of the fins81are fixed to the base plate182. Unlike the base plate82described above, no holding recessed portion is formed in the base plate182. The back plate184covers the upper surface of the connecting portion83aand is attached to the base plate182. A holding recessed portion184athat extends in the left-right direction is formed in the back plate184. The connecting portion83aof the heat pipe83is fitted in this holding recessed portion. The back plate184has a plate front portion184band a plate rear portion184clocated on opposite sides from each other with the holding recessed portion184ainterposed therebetween. The parts184band184care attached to the base plate182. Incidentally, in the heat radiating device180, unlike the heat radiating device80, the connecting portion83aof the heat pipe83may be curved, for example, instead of being linear. In such a case, the holding recessed portion184amay be curved in conformity with the connecting portion83a. As illustrated inFIG.17C, the base plate182has a plate left portion182clocated on the left side of the fins81and a plate right portion182dlocated on the right side of the fins81. The plate left portion182ccloses the gap G1. The plate right portion182dcloses the gap G2. This can prevent electromagnetic waves from leaking from the gaps G1and G2. As illustrated inFIG.17C, the plate left portion182cextends leftward beyond the edge (left edge) of the opening52aof the board shield52and overlaps the board shield52. The plate right portion182dextends rightward beyond the edge (right edge) of the opening52aof the board shield52and overlaps the board shield52. This can prevent electromagnetic waves from leaking from the gaps G1and G2more effectively. As illustrated inFIG.17B, the base plate182has a plate front portion182aand a plate rear portion182blocated on opposite sides from each other in the front-rear direction with the connecting portion83ainterposed therebetween. The plate front portion182aand the plate rear portion182balso respectively extend frontward and rearward beyond the edges of the opening52aof the board shield52and overlap the board shield52. Thus, the base plate182may be superposed on the entire perimeter of the edges of the opening52aof the board shield52. This can effectively prevent electromagnetic waves from leaking. The back plate184may have substantially the same size as the base plate182in at least one of the left-right direction and the front-rear direction. In the example of the electronic apparatus1, as illustrated inFIG.17A, a size K2in the front-rear direction of the back plate184is the same as that of the base plate182. In addition, a size K1in the left-right direction of the back plate184is the same as that of the base plate182. According to this structure of the back plate184and the base plate182, heat transmitted from the heat pipe83to the back plate184is transmitted to the whole of the base plate182easily and is therefore transmitted to the whole of the fins81easily. Incidentally, the back plate184may have substantially the same size as the base plate182in only either the left-right direction or the front-rear direction. Here, the back plate184and the base plate182having the same size in the front-rear direction means that frontmost portions thereof can be attached to the board shield52by a common fixture (a screw or a rivet) and that rearmost portions thereof can be attached to the board shield52by a common fixture. For example, attachment holes into which a common fixture is to be inserted are formed in each of the frontmost portions and the rearmost portions of the plates184and182. Similarly, the back plate184and the base plate182having the same size in the left-right direction means that rightmost portions thereof can be attached to the board shield52by a common fixture and that leftmost portions thereof can be attached to the board shield52by a common fixture. In addition, according to this structure, unlike the base plate82described above, the holes penetrating the base plate182(through holes82gand82hdescribed above) are not formed. Therefore, a leakage of electromagnetic waves can be prevented more effectively. <Memory Housing Chamber> As illustrated inFIG.15, a ground pattern50fthat includes a conductor and functions as an electric ground is formed on the lower surface of the circuit board50. InFIG.15, the ground pattern50fis shaded. The ground pattern50fsurrounds the entire perimeter of a region B1on which electronic parts50cand50eand the like are mounted (the region will hereinafter be referred to as a shielded region). The lower board shield52covers the shielded region B1. The lower board shield52has ground contact portions52b(seeFIG.7C) fixed to the ground pattern50fby a fixture such as a screw. As illustrated inFIG.15, a memory connector50gfrom which a semiconductor memory55(seeFIG.18A) is detachable may be mounted on a region on the outside of the shielded region B1in the lower surface of the circuit board50. In the example of the electronic apparatus1, the semiconductor memory55is disposed rightward from the memory connector50g. The lower board shield52may have a connector cover52c(seeFIG.18A) that covers the memory connector50g. A memory housing chamber R1(seeFIG.18A) that houses the semiconductor memory55is defined on the lower side of the circuit board50. As illustrated inFIG.18C, the lower board shield52has shield walls52eand52fformed along the memory housing chamber R1. According to this structure, it is possible to reduce an effect of static electricity on the semiconductor memory55while suppressing an increase in the number of parts. The shield walls52eand52fare walls higher than the semiconductor memory55and also have a length (width in the left-right direction) corresponding to the semiconductor memory55. In the example of the electronic apparatus1, the memory housing chamber R1is defined near a front surface10a(seeFIG.8A) of the electronic apparatus1. As illustrated inFIG.15, the memory housing chamber R1is located forward of the center of the circuit board50in the front-rear direction and is, for example, formed along a front edge50hof the circuit board50. The shield wall52eis formed on the front side of the memory housing chamber R1. According to this structure, when the user touches the front surface10aof the electronic apparatus1, a flow of static electricity to the semiconductor memory55can be suppressed by the shield wall52e. As illustrated inFIG.18C, the shield wall52fmay be formed on the rear side of the memory housing chamber R1. According to this, the effect of static electricity on the semiconductor memory55can be suppressed more effectively. As illustrated inFIG.15, the ground pattern50fmay have ground portions50iand50jformed along the memory housing chamber R1. The ground portions50iand50j, for example, have a length (length in the left-right direction) corresponding to the memory housing chamber R1. The ground portion50iis formed on the front side of the memory housing chamber R1. The ground portion50jis formed on the rear side of the memory housing chamber R1. In the following, the ground portion50iwill be referred to as a front ground portion, and the ground portion50jwill be referred to as a rear ground portion. As illustrated inFIG.18C, the lower board shield52has a contact portion52gin contact with the front ground portion50iand a contact portion52hin contact with the rear ground portion50j. The shield wall52eon the front side extends downward from the contact portion52g. The shield wall52fon the rear side extends downward from the contact portion52h. According to this structure, distances from the shield walls52eand52fto the ground pattern50fof the circuit board50are decreased. As a result, the effect of static electricity can be reduced more effectively. Incidentally, the structure of the ground pattern50fand the structure of the lower board shield52are not limited to the example illustrated in the electronic apparatus1. For example, the ground pattern50fmay have only one of the two ground portions50iand50j(for example, the front ground portion50i). In such a case, the lower board shield52may have only one of the two contact portions52gand52h(for example, the contact portion52gon the front side). As illustrated inFIG.18A, the memory housing chamber R1may be covered by a memory cover56. The memory cover56includes, for example, a conductive material (for example, a metal such as copper, aluminum, or iron). The memory cover56is electrically connected to the shield walls52eand52f. According to this, the effect of static electricity on the semiconductor memory55can be suppressed even more effectively. In the example of the electronic apparatus1, the memory cover56is electrically connected to the shield wall52ethrough a conductive cushion56a(FIG.18C) disposed between an edge of the memory cover56and an edge of the shield wall52eon the front side. In addition, the memory cover56is electrically connected to the shield wall52fthrough a conductive cushion56bdisposed between an edge of the memory cover56and an edge of the shield wall52fon the rear side. As illustrated inFIG.18C, an opening30dthat exposes the memory housing chamber R1is formed in the lower housing member30B. Supporting walls37a,37b, and37cthat surround the memory housing chamber R1may be formed on the lower housing member30B. The supporting walls37a,37b, and37care walls extending toward the circuit board50from edges of the opening30d. The supporting walls37a,37b, and37ccan secure a strength of the lower housing member30B on the periphery of the opening30d. As illustrated inFIG.18C, the shield walls52eand52fmay be located on the inside of the supporting walls37a,37b, and37c. The shield wall52eon the front side is, for example, disposed on the inside of the supporting wall37aon the front side and along the supporting wall37a. The shield wall52fon the rear side is, for example, disposed on the inside of the supporting wall37bon the rear side and along the supporting wall37b. In the example of the electronic apparatus1, the board shield52does not have a shield wall located on the inside of the supporting wall37cformed on the right side of the memory housing chamber R1. Unlike the example of the electronic apparatus1, the board shield52may have a shield wall located on the inside of the supporting wall37c. The outer peripheral edge of the memory cover56is, for example, disposed at lower edges of the supporting walls37a,37b, and37c. As illustrated inFIG.18A, a projecting portion56cis formed at an end portion (left end in the example illustrated in the electronic apparatus1) of the memory cover56. An opening into which the projecting portion56cis fitted in a horizontal direction is formed in the lower housing member30B. An end portion on an opposite side (right end in the example illustrated in the electronic apparatus1) of the memory cover56is disposed on the supporting wall37cand is fixed to the supporting wall37c. For example, a hole is formed in the supporting wall37c, and the end portion of the memory cover56is fixed to this hole by a fixture such as a screw58a. The semiconductor memory55may be fixed to the circuit board50or the upper board shield51at a position separated from the memory connector50g. For example, as illustrated inFIG.18A, a right end55aof the semiconductor memory55may be fixed to a screw hole51bformed in the upper board shield51by a screw58b. In such a case, a spacer57may be disposed between the upper board shield51and the right end55aof the semiconductor memory55. A hole50kused for disposing the spacer57may be formed at a position corresponding to the screw hole51bin the circuit board50. The electronic apparatus1may allow a plurality of semiconductor memories having different storage capacities to be used selectively. Such semiconductor memories have different lengths in the left-right direction according to the storage capacities. Accordingly, as illustrated inFIG.18A, a plurality of screw holes51bmay be formed in the upper board shield51such that such a plurality of semiconductor memories having different lengths can be fixed to the upper board shield51. In addition, in the circuit board50, holes used for disposing the spacer57may be formed at positions corresponding to the screw holes51b. Vent holes H1(seeFIG.18AandFIG.18B) that allow a flow of air between the inside and the outside of the memory housing chamber R1in a state in which the memory cover56is closed may be formed in the memory housing chamber R1. This can improve a heat radiation property for the semiconductor memory55. As described above, the memory housing chamber R1is disposed near the front surface10aof the electronic apparatus1. The vent holes H1may be formed in a wall portion on the rear side of the memory housing chamber R1. In the example of the electronic apparatus1, the vent holes H1may be provided in the shield wall52fon the rear side or the supporting wall37bon the rear side. In addition, the vent holes H1may open toward the rear side of the electronic apparatus1. According to this structure of the vent holes H1, the vent holes H1are distant from the front surface10aof the electronic apparatus1, and therefore, the vent holes H1can be effectively prevented from becoming a passage for static electricity. In the example of the electronic apparatus1, a plurality of gaps52i(seeFIG.19) are formed in the shield wall52fon the rear side. As illustrated inFIG.18B, the lower edge of the supporting wall37bof the lower housing member30B has recessed portions37eat positions corresponding to the gaps52i. The vent holes H1that open toward the rear side of the electronic apparatus1are formed between the recessed portions37eand an edge of the memory cover56. An attachment hole52j(seeFIG.18B) used for fixing the ground contact portion52hof the lower board shield52to the circuit board50may be formed in the gaps52i. The above-described lower flow passage Ub (seeFIG.20A) is formed between the lower surface of the lower housing member30B and the lower exterior panel20B. The vent holes H1open in the lower flow passage Ub. In addition, the vent holes H1open toward the inlet port31bof the lower housing member30B from the memory housing chamber R1(seeFIG.8A). Therefore, when the cooling fan5is driven, an airflow from the inside of the memory housing chamber R1to the inlet port31bthrough the vent holes H1is formed. In addition to the vent holes H1, holes opening to the outside of the memory housing chamber R1may be formed in the wall portions defining the memory housing chamber R1, the wall portions being the shield walls52eand52f, the supporting walls37a,37b, and37c, the circuit board50, and the like. When the cooling fan5is driven, air flows into the inside of the memory housing chamber R1through the holes. The holes opening to the outside of the memory housing chamber R1, that is, air intake holes, are, for example, the holes50kformed in the circuit board50to fix the semiconductor memory55. <Exterior Panel> As described above, the electronic apparatus1has the upper exterior panel20A attached to the upper surface of the apparatus main body10and the lower exterior panel20B attached to the lower surface of the apparatus main body10. The apparatus main body10has the upper housing member30A and the lower housing member30B combined with each other in the upward-downward direction. The upper exterior panel20A is attached to the upper surface of the upper housing member30A. The lower exterior panel20B is attached to the lower surface of the lower housing member30B. As illustrated inFIG.1C, the upper exterior panel20A may have, on a right side thereof, a right projecting portion20athat projects rightward beyond the position of a right side surface10bof the apparatus main body10(right side external surface of the front exterior panel35). In addition, the upper exterior panel20A may have, on a left side thereof, a left projecting portion20b(FIG.1G) that projects leftward beyond the position of a left side surface10cof the apparatus main body10(left side surface of the housing30). As illustrated inFIG.1B, the projecting portions20aand20bmay continue from a rear edge to a front edge of the upper exterior panel20A. The projecting portions20aand20bcan protect the apparatus main body10. For example, when the electronic apparatus1is placed vertically such that the right side surface10bof the electronic apparatus1is on the lower side, the right projecting portion20aabuts against a floor surface and supports the apparatus main body10, so that the side surface of the apparatus main body10can be prevented from being damaged or soiled. Similarly to the upper exterior panel20A, as illustrated inFIG.1C, the lower exterior panel20B may have, on a right side thereof, a right projecting portion20cthat projects rightward beyond the position of the right side surface10bof the apparatus main body10, and have, on a left side thereof, a left projecting portion20d(seeFIG.1G) that projects leftward beyond the position of the left side surface10cof the apparatus main body10. The projecting portions20cand20dmay continue from a rear edge to a front edge of the lower exterior panel20B. According to this structure of the exterior panels20A and20B, the apparatus main body10can be protected more effectively. As illustrated inFIG.1E, the upper exterior panel20A may have, on a front side thereof, a front projecting portion20ethat projects frontward beyond the position of the front surface10aof the apparatus main body10(front surface of the front exterior panel35). Similarly, the lower exterior panel20B may have, on a front side thereof, a front projecting portion20fthat projects frontward beyond the position of the front surface10aof the apparatus main body10. According to this structure of the exterior panels20A and20B, the front surface10aof the apparatus main body10and parts arranged in the front surface10a(for example, the buttons2aand2b, the connector3aand3b, and the like) can be protected. The front projecting portion20econtinues from a right edge to a left edge of the upper exterior panel20A. The front projecting portion20fcontinues from a right edge to a left edge of the lower exterior panel20B. In addition, the exterior panels20A and20B may have a rear projecting portion that projects rearward beyond the position of the rear surface of the apparatus main body10(rear surface of the housing30). Incidentally, the exterior panels20A and20B may have projecting portions on only a part of the right side, the left side, and the front side thereof. For example, the exterior panels20A and20B may not have the projecting portions20eand20fon the front side. In addition, only one of the two exterior panels20A and20B may have the projecting portions. As illustrated inFIG.1A, the upper exterior panel20A has a shape obtained by gently curving one plate in a thickness direction thereof and does not have, at an outer peripheral edge thereof, a wall portion that drops toward the lower exterior panel20B. That is, the upper exterior panel20A is not in a box shape. Hence, the upper exterior panel20A has a right end surface20g(seeFIG.1E) facing rightward and having a width T3(width in the upward-downward direction) corresponding to the thickness of the upper exterior panel20A. Similarly, the upper exterior panel20A has a left end surface facing leftward and having a width corresponding to the thickness of the upper exterior panel20A, a front end surface facing frontward and having a width corresponding to the thickness of the upper exterior panel20A, and a rear end surface facing rearward and having a width corresponding to the thickness of the upper exterior panel20A. Similarly to the upper exterior panel20A, the lower exterior panel20B does not have, at an outer peripheral edge thereof, a wall portion that extends toward the upper exterior panel20A. Hence, the lower exterior panel20B has a right end surface20h(seeFIG.1G) facing rightward and having a width T4(width in the upward-downward direction) corresponding to the thickness of the lower exterior panel20B, a left end surface facing leftward and having a width corresponding to the thickness of the lower exterior panel20B, a front end surface facing frontward and having a width corresponding to the thickness of the lower exterior panel20B, and a rear end surface facing rearward and having a width corresponding to the thickness of the lower exterior panel20B. <Curve of Exterior Panel> The upper exterior panel20A may have a curved section in a cutting plane that is along the upward-downward direction and intersects the left-right direction. This can increase the strength of the exterior member when the electronic apparatus1is placed vertically, as compared with a case where the upper exterior panel20A is a flat plate. As illustrated inFIG.20AandFIG.20B, the upper exterior panel20A may have sections curved in different manners in two cutting planes that are along the upward-downward direction and intersect each other. Here, the two cutting planes are, for example, a cutting plane indicated by a line XXa-XXa illustrated inFIG.1Dand a cutting plane indicated by a line XXb-XXb. The cutting planes are not limited to the example illustrated in FIG.1D and may, for example, be planes along the upward-downward direction and the front-rear direction. Also in such a case, the strength of the upper exterior panel20A (strength against a force acting in the left-right direction) can be increased. InFIG.1D, a first position P1, a second position P2located on an opposite side of a center Pc of the upper exterior panel20A from the first position P1, a third position P3, and a fourth position P4located on an opposite side of the center Pc of the upper exterior panel20A from the third position P3are set at four corners of the upper exterior panel20A. InFIG.1D, the first position P1is given at a right front corner, the second position P2is given at a left rear corner, the third position P3is given at a left front corner, and the fourth position P4is given at a right rear corner. When the four positions are thus defined in the example of the electronic apparatus1, a line L1that connects the first position P1and the second position P2to each other and is along the upper surface of the upper exterior panel20A is a curve bulging downward, as illustrated inFIG.20A. In other words, when a cutting plane along a first diagonal line of the electronic apparatus1is viewed, the upper exterior panel20A is curved along an arc about a point separated upward from the upper exterior panel20A. Here, the “first diagonal line” is the line XXa-XXa illustrated inFIG.1D. On the other hand, a line L2that connects the third position P3and the fourth position P4to each other and is along the upper surface of the upper exterior panel20A is a curve bulging upward, as illustrated inFIG.20B. In other words, when a cutting plane along a second diagonal line of the electronic apparatus1is viewed, the upper exterior panel20A may be curved along an arc about a point separated downward from the upper exterior panel20A. Here, the “second diagonal line” is the line XXb-XXb illustrated inFIG.1D. According to such curves of the upper exterior panel20A, as illustrated inFIG.20A, the thickness (width in the upward-downward direction) of the electronic apparatus1at the right front corner (first position P1) of the electronic apparatus1and the thickness (width in the upward-downward direction) of the electronic apparatus1at the left rear corner (second position P2) of the electronic apparatus1are increased. Therefore, when the electronic apparatus1is placed vertically, the attitude of the electronic apparatus1can be stabilized. For example, when the electronic apparatus1is placed vertically such that the right side surface of the electronic apparatus1is on the lower side, the right front corner (first position P1) having a large thickness is on the lower side and supports the electronic apparatus1. In addition, when the electronic apparatus1is placed such that the front surface of the electronic apparatus1is on the lower side, the right front corner (first position P1) having a large thickness is also on the lower side. When the electronic apparatus1is placed vertically such that the left side surface of the electronic apparatus1is on the lower side, on the other hand, the left rear corner (second position P2) having a large thickness is on the lower side and supports the electronic apparatus1. Hence, according to the above-described curves of the upper exterior panel20A, when the electronic apparatus1is placed vertically, the attitude of the electronic apparatus1can be stabilized. FIG.20Aillustrates a first distance D1at the first position P1(right front corner) and a second distance D2at the second position P2(left rear corner) as distances from the horizontal plane Hp1including the circuit board50to the upper surface of the upper exterior panel20A. In addition,FIG.20Billustrates a third distance D3at the third position P3(left front corner) and a fourth distance D4at the fourth position P4(right rear corner) as distances from the horizontal plane Hp1including the circuit board50to the upper surface of the upper exterior panel20A. As described above, the line L1connecting the first position P1and the second position P2to each other, the first position P1and the second position P2being defined on a diagonal line of the upper exterior panel20A, is a curve bulging downward, and the line L2connecting the third position P3and the fourth position P4to each other, the third position P3and the fourth position P4being on another diagonal line of the upper exterior panel20A, is a curve bulging upward. Therefore, each of the first distance D1and the second distance D2is larger than each of the third distance D3and the fourth distance D4. It is therefore possible to realize smooth air intake and exhaust by arranging devices and parts of a cooling system near the first position P1and near the second position P2. For example, as illustrated inFIG.1D, as viewed in plan of the electronic apparatus1, a line connecting the center Pc of the upper exterior panel20A and the first position P1to each other (line XXa-XXa indicating a cutting plane) passes the inlet port Ea (seeFIG.1C) formed between the upper exterior panel20A and the upper surface of the upper housing member30A. In addition, the line connecting the center Pc of the upper exterior panel20A and the first position P1to each other passes the upper flow passage Ua (seeFIG.20A) formed between the upper exterior panel20A and the recessed plate portion32a(seeFIG.2A) of the upper housing member30A. This facilitates securing of a sufficient width in the upward-downward direction of the inlet port Ea and a sufficient width in the upward-downward direction of the upper flow passage Ua. In addition, as viewed in plan of the electronic apparatus1, a line connecting the center Pc of the upper exterior panel20A and the second position P2to each other (line XXa-XXa indicating a cutting plane) may pass a flow passage from the cooling fan5to the exhaust port M provided in the back surface of the electronic apparatus1. In the example of the electronic apparatus1, the air flowing out of the cooling fan5passes through the inside of the power supply unit case61and is exhausted from the exhaust port M. As viewed in plan of the electronic apparatus1, the line connecting the center Pc of the upper exterior panel20A and the second position P2to each other (line XXa-XXa indicating a cutting plane) passes an air flow passage formed in the rear portion (case rear portion61c) of the power supply unit case61. Therefore, a sufficient size in the upward-downward direction of the rear portion of the power supply unit case61is secured easily, and exhaust efficiency can be improved. In addition, as viewed in plan of the electronic apparatus1, the line connecting the center Pc of the upper exterior panel20A and the second position P2to each other passes the rear wall61i(seeFIG.7C) of the power supply unit case61in which the exhaust holes61gare formed, and the rear portion61k(seeFIG.7C) of the upper wall61jin which the exhaust holes61hare formed. This facilitates securing of a sufficient size in the upward-downward direction of the rear wall61iof the power supply unit case61and securing of a sufficient width in the upward-downward direction of the air flow passage Se (seeFIG.7C) formed between the rear portion61kof the upper wall61jand the upper housing member30A. The lower exterior panel20B may also be curved as a whole. For example, as illustrated inFIG.20A, the lower exterior panel20B is curved when the cutting plane along the first diagonal line of the electronic apparatus1(line XXa-XXa inFIG.1D) is viewed. As illustrated inFIG.20B, when the cutting plane along the second diagonal line of the electronic apparatus1(line XXb-XXb inFIG.1D) is viewed, the lower exterior panel20B may be curved in a manner different from that in the cutting plane illustrated inFIG.20A. As described above, the optical disk drive6is disposed on the lower side of the circuit board50. The optical disk drive6is located in a left portion of the electronic apparatus1. Therefore, a left portion of the lower exterior panel20B is bulged downward so as to cover the lower side of the optical disk drive6. A right portion Br of the lower exterior panel20B may have a shape symmetric to a right portion of the upper exterior panel20A. Incidentally, the electronic apparatus1may not have the optical disk drive6on the lower side of the circuit board50. In such a case, the whole of the shape (curve) of the lower exterior panel20B may be symmetric to the shape (curve) of the upper exterior panel20A.FIG.21AandFIG.21Bare sectional views illustrating a lower exterior panel according to such a modification. In an example illustrated in these diagrams, a lower exterior panel120B and the upper exterior panel20A have shapes symmetric with respect to a horizontal plane Hp2.FIG.21Aillustrates sections of the exterior panels20A and120B which are obtained in the same cutting plane as the cutting plane indicated by the line XXa-XXa inFIG.1D.FIG.21Billustrates sections of the exterior panels20A and120B which are obtained in the same cutting plane as the cutting plane indicated by the line XXb-XXb inFIG.1D.FIG.21Cis a front view of an electronic apparatus101having the exterior panels20A and120B illustrated inFIG.21AandFIG.21B. In the example illustrated inFIG.21AandFIG.21B, a fifth position P5, a sixth position P6located on an opposite side of a center Pc of the lower exterior panel120B from the fifth position P5, a seventh position P7, and an eighth position P8located on an opposite side of the center Pc of the lower exterior panel120B from the seventh position P7are set at four corners of the lower exterior panel120B. For example, the fifth position P5is given at a right front corner of the lower exterior panel120B, the sixth position P6is given at a left rear corner of the lower exterior panel120B, the seventh position P7is given at a left front corner of the lower exterior panel120B, and the eighth position P8is given at a right rear corner of the lower exterior panel120B. Hence, as viewed in plan of the electronic apparatus1, the fifth position P5, the sixth position P6, the seventh position P7, and the eighth position P8respectively correspond to the first position P1, the second position P2, the third position P3, and the fourth position P4described above. When the four positions are thus defined in the lower exterior panel120B, a line L3that connects the fifth position P5and the sixth position P6to each other and is along the lower surface of the lower exterior panel120B may be a curve bulging upward, as illustrated inFIG.21A. On the other hand, a line L4that connects the seventh position P7and the eighth position P8to each other and is along the lower surface of the lower exterior panel120B may be a curve bulging downward, as illustrated inFIG.21B. Incidentally, the curved form of the upper exterior panel20A is not limited to the example of the electronic apparatus1. For example, the above-described four positions P1to P4defining the curved form of the upper exterior panel20A may not be the four corners of the upper exterior panel20A. For example, the first position P1may be defined at a center of the front edge of the upper exterior panel20A, the second position P2may be defined on an opposite side of the center Pc of the upper exterior panel20A from the first position P1, the third position P3may be defined at a center of the right edge of the upper exterior panel20A, and the fourth position P4may be defined on an opposite side of the center Pc of the upper exterior panel20A from the third position P3. When the four positions P1to P4are thus defined, the line that connects the first position P1and the second position P2to each other and is along the upper surface of the upper exterior panel20A may, for example, be a curve bulging downward. On the other hand, the line that connects the third position P3and the fourth position P4to each other and is along the upper surface of the upper exterior panel20A may be a curve bulging upward. In such a case, the curved form of the lower exterior panel20B may correspond to the curved form of the upper exterior panel20A. For example, the whole of the shape (curve) of the lower exterior panel20B may be symmetric to the shape (curve) of the upper exterior panel20A. Further, in another example, while only the upper exterior panel20A is curved as described above, the lower exterior panel20B may be in a flat plate shape. In yet another example, a part of the upper exterior panel20A or a part of the lower exterior panel20B may include a flat surface. <Exterior Panel Attachment Structures> As illustrated inFIG.2AandFIG.22, a plurality of attachment holes30eand30fare formed in the upper surface of the apparatus main body10(the upper surface of the upper housing member30A). A plurality of attachment target projecting portions21and22(seeFIG.2B) are formed on the lower surface of the upper exterior panel20A. The attachment target projecting portions21and22are fitted in the attachment holes30eand30f, respectively. The attachment holes30eand30fare, for example, holes that penetrate the upper housing member30A. InFIG.22, fitting directions in which the attachment target projecting portions21and22are respectively fitted into the attachment holes30eand30fare indicated by arrows Da. The fitting directions Da, for example, correspond to a direction in which the attachment target projecting portions21and22project from the lower surface of the upper exterior panel20A. In addition, the fitting directions Da, for example, correspond to a direction in which the attachment holes30eand30fpenetrate the upper housing member30A. Each of the fitting directions Da in which the plurality of attachment target projecting portions21and22are fitted into the attachment holes30eand30fis parallel with the other. The fitting direction Da may be inclined with respect to a plane perpendicular to the upward-downward direction (horizontal plane Hp3parallel with the circuit board50inFIG.22). For example, the fitting direction Da may be a direction inclined with respect to the horizontal plane Hp3and along a plane parallel with the upward-downward direction and the left-right direction. As described above, the upper exterior panel20A is curved in manners different from each other in two cutting planes that are along the upward-downward direction and intersect each other. That is, the upper exterior panel20A is curved so as to bulge downward in the cutting plane along the first diagonal line (line XXa-XXa inFIG.1D) and is curved so as to bulge upward in the cutting plane along the second diagonal line (line XXb-XXb inFIG.1D). As illustrated inFIG.22, the upper surface of the apparatus main body10is also curved in conformity with the upper exterior panel20A. When the fitting direction Da is inclined with respect to the horizontal plane Hp3, the curved upper exterior panel20A can be attached to the upper surface of the apparatus main body10that is similarly curved, and the upper exterior panel20A and the upper surface of the apparatus main body10can be brought into close contact with each other. FIG.23is a schematic diagram of assistance in explaining this. In an example illustrated in this figure, a horizontal portion30iand an inclined portion30jare formed in the upper housing member30A. A horizontal portion20iand an inclined portion20jare also formed in the upper exterior panel20A. The attachment target projecting portions21and22project in the direction Da inclined with respect to the horizontal plane. The attachment holes30eand30fpenetrate the upper housing member30A in the direction Da inclined with respect to the horizontal plane Hp3. The fitting direction Da is inclined more greatly than the inclined portions30jand20j. That is, an angle θ1formed between the horizontal plane Hp3and the fitting direction Da is larger than an angle θ2formed between the horizontal plane Hp3and the inclined portions20jand30j. Therefore, the attachment target projecting portions21and20can be inserted into the attachment holes30eand30fwithout the occurrence of an interference between the inclined portion20jand the inclined portion30jand an interference between the horizontal portion20iand the horizontal portion30i. In addition, after the insertion of the attachment target projecting portions21and20, the inclined portion20jand the inclined portion30jcan be brought into close contact with each other, and the horizontal portion20iand the horizontal portion30ican be brought into close contact with each other. For a reduction in size in the upward-downward direction of the electronic apparatus1, a method is effective in which the upper exterior panel20A and the upper housing member30A are attached to each other by, for example, sliding the upper exterior panel20A with respect to the upper housing member30A in a right direction or a left direction. However, that method causes a gap between the inclined portions20jand30jand an interference between another inclined portion of the upper exterior panel20A and the upper housing member30A. On the other hand, in the example of the electronic apparatus1, the fitting direction Da is inclined more greatly than the inclined portions20jand30j, and therefore, the upper exterior panel20A can be attached to the upper housing member30A without causing such a gap or an interference. Hence, it is desirable that the fitting direction Da of the attachment target projecting portions21and22and the attachment holes30eand30fbe inclined with respect to the horizontal plane Hp3more greatly than a part inclined most greatly in the upper exterior panel20A. Incidentally, the plurality of attachment holes30eand30fare preferably distributed over the entire upper surface of the upper housing member30A. This can bring the whole of the upper exterior panel20A into close contact with the upper surface of the upper housing member30A. In the example of the electronic apparatus1, the recessed plate portion32ais formed in the upper surface of the upper housing member30A. The attachment holes30eand30fare preferably distributed in a region other than the recessed plate portion32a. As illustrated inFIG.22, the attachment target projecting portion21has an engaging protruding portion21aat a base portion thereof. A recessed portion30his formed in the bottom surface of the attachment hole30e. The engaging protruding portion21ais fitted in the recessed portion30hand regulates slipping of the attachment target projecting portion21from the attachment hole30e. On the other hand, the attachment target projecting portion22has no protruding portion at a base portion thereof. The engaging protruding portion21ahas a surface21bthat faces a direction of pulling out the attachment target projecting portion21from the attachment hole30e. At the surface21b, the engaging protruding portion21aengages with the recessed portion30h. (The surface21bwill hereinafter be referred to as a locking surface.) The upper exterior panel20A holds the upper surface of the upper housing member30A with the locking surface21bof the attachment target projecting portion21and the attachment target projecting portion22. A plurality of attachment target projecting portions22are arranged along a left edge of the upper exterior panel20A. Unlike the attachment target projecting portion21, no projecting portion may be formed at base portions of the attachment target projecting portions22. The structure for attachment of the lower exterior panel20B to the lower housing member30B may be the same as the structure for attachment of the upper exterior panel20A to the upper housing member30A. That is, as illustrated inFIG.2A, the lower exterior panel20B may have an attachment target projecting portion25having a protruding portion formed at a base portion thereof and an attachment target projecting portion24not having such a protruding portion formed thereon. Attachment holes into which the attachment target projecting portions24and25are to be fitted may be formed in the lower surface of the lower housing member30B. Incidentally, the structure for fixing the upper exterior panel20A to the upper housing member30A is not limited to the example of the electronic apparatus1. For example, as illustrated inFIG.24, engaging protruding portions26may be formed in the lower surface of the upper exterior panel20A in place of the engaging protruding portion21aformed on the base portion of the attachment target projecting portion21. The engaging protruding portions26may, for example, be formed such that center lines thereof are along the upward-downward direction. On the other hand, holes or recessed portions into which the engaging protruding portions26are to be fitted may be formed in the upper housing member30A. According to this structure, the size of the projecting portions is increased easily as compared with the engaging protruding portion21aof the attachment target projecting portion21. As a result, the strength of the engaging protruding portions can be increased. <Disk Insertion Slot> As illustrated inFIG.1BandFIG.25, a disk insertion slot23ainto which an optical disk is to be inserted toward the optical disk drive6may be formed in the lower exterior panel20B. The lower exterior panel20B has a front slope23on the front side thereof. The front slope23is a surface that extends obliquely downward and rearward from a front edge20kof the lower exterior panel20B. The disk insertion slot23ais formed in the front slope23. This can prevent the disk insertion slot23afrom being conspicuous. As illustrated inFIG.25, a guide curved surface23cconnected to the edge of the disk insertion slot23ais formed on an upper portion of the disk insertion slot23a. The guide curved surface23ccan function as a guide for an optical disk D. In a case where a front edge of the optical disk collides immediately below the front edge20kof the lower exterior panel20B at a time of insertion of the optical disk D, for example, the guide curved surface23cguides the optical disk D to the inside of the disk insertion slot23a. In the example of the electronic apparatus1, the disk insertion slot23ais located in a left portion of the electronic apparatus1. The front slope23in which the disk insertion slot23ais formed is formed obliquely such that a right portion of the front slope23(part near the center in the left-right direction of the electronic apparatus1) is located forward of a left portion of the front slope23. Therefore, as illustrated inFIG.1H, a front edge23eof the disk insertion slot23ais inclined frontward from a left end of the front edge23eto the center (center in the left-right direction) of the electronic apparatus1in a bottom view of the electronic apparatus1. Therefore, at a time of insertion of the optical disk D, the guiding of the optical disk D starts early near the center of the electronic apparatus1. As illustrated inFIG.25, a slope23dis formed at a lower edge of the disk insertion slot23a. The slope23dextends obliquely rearward and upward from a front edge thereof. In a case where the front edge of the optical disk collides with the slope23d, the slope23dguides the optical disk D to an insertion opening6cformed in a front surface of the disk drive case6a. The insertion opening6cformed in the front surface of the disk drive case6ais located above a lower portion of the slope23d. Thus, a distance from the insertion opening6cto the disk insertion slot23aformed in the lower housing member30B is decreased. As a result, the work of inserting the optical disk D can be facilitated. As described above, in the electronic apparatus1, the housing30includes the upper housing member30A that covers the upper surface of the circuit board50, and the lower housing member30B that covers the lower surface of the circuit board50. The cooling fan5is disposed on the outside of the outer edge of the circuit board50. The cooling fan5has the rotational center line Cf along the upward-downward direction as the thickness direction of the circuit board50. The cooling fan5forms an airflow between the upper surface of the circuit board50and the upper housing member30A and an airflow between the lower surface of the circuit board50and the lower housing member30B. The upper housing member30A has the upper inlet port31adefined above the cooling fan5. The lower housing member30B has the lower inlet port31bdefined below the cooling fan5. According to the electronic apparatus1, one cooling fan5can send air to both surfaces of the circuit board50. It is therefore possible to cool parts disposed on both surfaces of the circuit board50without increasing the number of parts. In addition, because the upper inlet port31aand the lower inlet port31bare formed in the housing30, air can be taken in efficiently, so that cooling performance can be improved. In addition, the electronic apparatus1includes: the first heat sink71that allows air to pass through in the front-rear direction; the power supply unit60including the power supply circuit62and the power supply unit case61housing the power supply circuit62and having the intake air wall61ain which the plurality of air intake hole61bare formed; and the cooling fan5. The intake air wall61ais located in front of the first heat sink71. In addition, the intake air wall61ahas an external surface inclined with respect to both the front-rear direction and the left-right direction and facing the first heat sink71. The cooling fan5is disposed so as to send air to the intake air wall. Such an intake air wall61amakes it possible to secure an airflow to be supplied to the first heat sink71, and to cool the power supply unit60by a cold air (air not warmed by another heat generating device or heat radiating device) at the same time. When the power supply unit60can be cooled by the cold air, a clearance between the circuit parts62aand62bincluded in the power supply circuit62(for example, a transformer and a capacitor) can be reduced, so that the power supply unit60can be miniaturized. In addition, the electronic apparatus1includes: the circuit board50; the cooling fan5that forms an airflow for cooling parts mounted on the circuit board50; the flow passage wall34A that defines the flow passage of the airflow sent out from the cooling fan5; and the dust collecting chamber Ds that captures dust in the airflow and collects the captured dust, the dust collecting chamber Ds being provided to the flow passage wall34A. According to this structure, it is possible to reduce an amount of dust that enters devices arranged downstream of the dust collecting chamber Ds, the devices being the first heat sink71, the power supply unit60, and the like. In addition, the dust collecting chamber Ds has the first opening A1that opens toward the air flow passage Sa in a direction along the circuit board50, and the second opening A2that opens to the outside of the dust collecting chamber Ds in a direction intersecting the circuit board50. In the example of the electronic apparatus1, the direction in which the second opening A2opens is a direction orthogonal to the circuit board50. According to this structure of the dust collecting chamber Ds, the dust can be collected in the dust collecting chamber Ds, and the collected dust can be discharged through the second opening A2by relatively simple work. In addition, the heat radiating device70includes: the plurality of heat pipes73A to73F located above the integrated circuit50aand each having the heat receiving portion73athermally connected to the integrated circuit50a; and the heat sinks71and72connected to the plurality of heat pipes73A to73F. The heat receiving portions73aof the heat pipes73A to73F are abreast of each other in the left-right direction and are in contact with the heat receiving portions73aof adjacent heat pipes73. The heat receiving portions73ahave the first width W1in the upward-downward direction and have the second width W2smaller than the first width W1in the left-right direction. According to this structure, it becomes easy to increase the number of heat pipes73. As a result, it becomes easy to increase the size of the heat sinks71and72to which the heat of the integrated circuit50ais transmitted through the heat pipes73. Cooling performance for the integrated circuit50acan therefore be improved. In addition, the electronic apparatus1includes: the circuit board50; the board shield52that covers the circuit board50and has the opening52aformed therein; and the heat radiating device80. The heat radiating device80includes: the plurality of fins81arranged on the inside of the opening52a; the heat pipe83that has the connecting portion83alocated between the plurality of fins81and the circuit board50and extending in the left-right direction along the circuit board50; and the base plate82or182that supports the plurality of fins81. The base plate82or182has the plate left portion82cor182c. The plate left portion82cor182ccovers the lower surface of the heat pipe83, the lower surface facing the board shield52side, and closes the gap G1between the left end of the plurality of fins81and the left edge of the opening52aof the board shield52. According to this structure, it is possible to effectively suppress a leakage of electromagnetic waves from the gap G1between the left end of the plurality of fins81and the left edge of the opening52aof the board shield52. As described above, in the electronic apparatus1, the lower surface of the circuit board50has the shielded region B1on which the electronic parts50cand50eare arranged, and the board shield52covers the shielded region. The memory housing chamber R1capable of housing the semiconductor memory55is defined on the outside of the shielded region. The board shield52has the shield walls52eand52falong the memory housing chamber R1. Because the shield walls52eand52fare formed on the board shield52in the electronic apparatus1, the semiconductor memory55can be protected from static electricity while an increase in the number of parts is suppressed. As described above, the electronic apparatus1includes the upper exterior panel20A having an upper surface. The upper surface of the upper exterior panel20A has, on a peripheral portion thereof, the first position P1, the second position P2defined on an opposite side of the center Pc of the upper surface from the first position P1, the third position P3, and the fourth position P4defined on an opposite side of the center Pc from the third position P3. The line L1that connects the first position P1and the second position P2to each other and is formed along the upper surface is a curve bulging downward. The line L2that connects the third position P3and the fourth position P4to each other and is formed along the upper surface is a curve bulging upward. According to the electronic apparatus1, an external appearance is improved, and a strength of the exterior panel20A is secured easily. Incidentally, there may be an application to an electronic apparatus not having the exterior panel20A. In such a case, the upper surface of a housing that houses internal devices such as the circuit board50may be curved as described above. In addition, the electronic apparatus1includes the apparatus main body10having an upper surface and the right side surface10band the curved upper exterior panel20A. The upper exterior panel20A covers the upper surface of the apparatus main body10and is attached to the upper surface. The upper exterior panel20A has, at an end portion of the upper exterior panel20A, the right projecting portion20abeyond the position of the right side surface10b. According to the electronic apparatus1, the apparatus main body10can be protected by the upper exterior panel20A when the electronic apparatus1is placed vertically such that the right side surface10bis on the lower side. In addition, because the upper exterior panel20A is curved, a strength of the upper exterior panel20A can be secured as compared with a case where the upper exterior panel20A is in a flat plate shape, for example. In addition, the upper exterior panel20A has a curved section in a cutting plane that is along the upward-downward direction and that intersects the left-right direction (specifically, a cutting plane indicated by the line XXa-XXa inFIG.1D). According to this, a sufficient strength of the exterior panel20A can be secured. The cutting plane that is along the upward-downward direction and intersects the left-right direction may, for example, be a plane along the upward-downward direction and the front-rear direction. Also in such a case, a sufficient strength of the exterior panel20A against an external force acting in the left-right direction can be secured. In addition, the upper exterior panel20A is a panel to be attached to the housing30having an upper surface and the right side surface10band disposed over the housing30. The upper exterior panel20is curved, has the plurality of attachment target projecting portions21and22to be respectively attached to the plurality of attachment holes30eand30fformed in the upper surface of the housing30, and has, at an end portion thereof, the right projecting portion20abeyond the position of the right side surface10b. According to the upper exterior panel20A, the apparatus main body10can be protected by the upper exterior panel20A when the electronic apparatus1is placed such that the right side surface10bis on the lower side. | 131,134 |
11943899 | DETAILED DESCRIPTION The following describes various principles related to composite thermal-interface materials. More particularly, but not exclusively, some embodiments include devices and systems for transferring heat (e.g., for cooling heat-generating, electrical components) that incorporate such a composite thermal-interface material. Some disclosed thermal-interface materials include a dispersion of metallic filler within a silicone oil or other substrate, e.g., suitable organic materials. In some embodiments, the metallic filler is molten, or begins to melt, at or near typical ambient temperatures, which is surmised to improve a conductive heat-transfer path across a thermal interface between two components. As should be understood following a review of this disclosure, components and systems having attributes that are different from those specific examples discussed herein can embody one or more presently disclosed principles, and can be used in applications not described herein in detail. Accordingly, such alternative embodiments also fall within the scope of this disclosure. Concepts disclosed herein generally concern composite thermal-interface materials, and in some respects, their application to heat-transfer components and use in heat-transfer systems. For example, some disclosed concepts pertain to systems, methods, and components to facilitate cooling of heat-generating components, in part by applying a composite thermal-interface material to a surface of a heat-transfer component. In other respects, material composition and physical properties of disclosed composite thermal-interface materials are described. And in still other respects, methods of manufacturing and assembling components that incorporate disclosed composite thermal interface materials are described. Referring now toFIG.1, a cross-sectional view of a heat transfer assembly100is described. The assembly100includes a heat-generating component110cooled by a heat-transfer component120. A thermal-interface material130, e.g., a composite thermal-interface material as described herein, is disposed in the interstitial region between a major surface122of the heat-transfer component and an opposed major surface (un-numbered) of the heat-generating component110(e.g., a processing unit112mounted to a circuit board or other substrate113) to facilitate conductive heat-transfer from the heat-generating component110to the heat-transfer component120. The interstitial region between the heat-transfer component and the heat-generating component is enlarged inFIG.1for illustrative purposes. As noted above, a heat-transfer component120can assume any of a variety for configurations. Although not so limited,FIG.1schematically illustrates the heat-transfer component120as a heat sink. The illustrated heat-transfer component120includes a conductive base121having fins123extending upwardly from an upper surface thereof. The fins123define flow channels124(e.g., minichannels or microchannels) therebetween. Although the heat-transfer component120is depicted as a heat sink, a heat-transfer component as described herein can have any of a variety of configurations, e.g., an air-cooled heat sink, a liquid-cooled cold plate, an evaporatively cooled cold plate, or any of these alone or in combination with an embedded heat pipe base or a vapor chamber base. Nevertheless, the heat-transfer component has a major surface122that defines an intended thermal-contact region (e.g., the region of the surface122covered by the thermal-interface material130). Like the heat-transfer component120, the heat-generating component110can assume any of a variety of configurations. Although not so limited,FIG.1depicts the heat-generating component110as a processing unit having a single functional die112mounted in a so-called “flip-chip” arrangement to a functional substrate113. Solder bumps (not shown) can provide physical and electrical connectivity between circuitry defined by the package112and electrical circuitry defined by the substrate113. (The substrate's113further circuitry and solder connections are also omitted fromFIG.1for clarity.) Although a bare die is schematically illustrated, with some embodiments, the die112can be covered by, e.g., an integrated heat spreader or other packaging. In such embodiments, the integrated heat spreader or other packaging is positioned between the die112and the heat-transfer component120, and the heat transfer component120is placed into thermal contact with a top surface of the integrated heat spreader or other packaging, e.g., rather than the die112. Referring still toFIG.1, the composite thermal-interface material130disposed in the interstitial region between the surface122and the opposed upper surface of the heat-generating component110defines an heat-generating contact region in direct physical contact with the outer surface of the heat-generating component110. Similarly, the thermal-interface material130defines a heat-transfer-component-contact region in direct physical contact with the lower surface122of the base121. Consequently, as depicted schematically inFIG.2, the thermal-contact resistance at a solid-solid interface between the lower surface122of the base121and the opposed surface of the heat-generating component, improved with a thermal-interface material130, can be described as a sum of three discrete, constituent thermal resistances: (1) a thermal-contact resistance between the lower surface122of the heat-transfer component and the upper surface of the thermal-interface material (Rc2inFIG.2); (2) a thermal resistance across the thermal-interface material from the upper surface of the TIM to the lower surface of the TIM, corresponding to the bulk thermal conductivity of the thermal interface material130(RbulkinFIGS.2); and (3) a thermal-contact resistance (Rc1inFIG.2) between the lower surface the thermal-interface material and the upper surface of the heat-generating component, referred to as “Heat source” inFIG.2. As shown inFIG.3, a prior thermal-interface material300(e.g., prior greases, pastes and even metallic foils) has conventionally been applied to a region of a heat-transfer component, e.g., to the surface122of the heat-transfer component120inFIG.1, before placing the heat-transfer component into thermal contact with the heat-generating component (e.g., a bare die, an integrated heat spreader, or other packaging). Such prior approaches reduced the bulk thermal resistance (RbulkinFIG.2) across the interface compared to an unfilled air gap, but also introduced additional thermal-contact resistances (Rc1and Rc2inFIG.2), limiting the improvement to the overall thermal-contact resistance. By contrast to prior approaches, composite thermal-interface materials include a metallic filler dispersed within a carrier substrate. In some embodiments, the metallic filler is liquid, begins to melt or is otherwise partially or wholly in a liquid phase at or within a selected temperature range (e.g., at room temperature or another temperature expected during operation). For example, some disclosed thermal-interface materials incorporate a metallic filler that is in its liquid phase (at normal ambient atmospheric pressures) at about 10° C., e.g., between about 5° C. and about 25° C. Other fillers are in a liquid phase under normal ambient atmospheric pressures at higher, albeit expected operating, temperatures, e.g., between about 25° C. and about 95° C., such as, for example, between about 35° C. and about 80° C., with between about 40° C. and about 70° C., between about 50° C. and about 60° C., or about 55° C. being specific examples of temperatures at which phase transition from solid-to-liquid begins or completes for eutectic and non-eutectic fillers disclosed herein. Such composite thermal-interface materials can improve the constituent components of overall thermal-contact resistance shown inFIG.2. For example, a liquid-phase filler can wet the surface of the heat-transfer component, as well as the surface of the heat-generating component, reducing the thermal-contact resistance between those components and the thermal interface material, e.g., Rc1and Rc2inFIG.2. As well, the metallic filler can increase overall bulk thermal conductivity of the thermal-interface material thus reducing the bulk thermal resistance of the material compared to prior materials, e.g., RbulkinFIG.2. For example, because the metallic filler can have a bulk thermal conductivity in excess of 20 W/m-K, e.g., between about 15 W/m-K and about 75 W/m-K, such as, for example, between about 20 W/m-K and about 30 W/m-K, or about 25 W/m-K in a specific embodiment, the overall thermal resistance of a disclosed thermal interface using a metallic filler can be substantially lower than a similar thermal interface using a conventional paste or grease. In some instances, discrete particles (or “packets”) of the liquid-phase filler dispersed throughout the carrier substrate can migrate small distances within the carrier substrate when in an in situ environment, especially when compressive forces are applied to urge the heat-transfer component120toward the heat-generating component110, as inFIG.1(or “heat sink” toward the “heat source” inFIG.2). Such migration can lead to agglomeration among smaller “particles,” increasing the size of individuals “packets” of metallic filler within the composite TIM. The larger “packets” of metallic filler, in turn, can span across the interface gap between the heat-generating component and the heat-transfer component, providing a low-resistance conduction path through the thermal-interface material from the heat-generating component to the heat-transfer component and further improving thermal contact between the heat-generating component and the heat-transfer component. Metallic filler materials can be electrically conductive. Accordingly, composite thermal-interface materials as described can provide an inadvertent and unwanted electrical conduction path, as when excess material escapes from the interstitial region between a heat-generating component and a heat-transfer component. Moreover, agglomeration of filler material within the composite thermal-interface material, as can occur under compressive loads, can lead to regions or zones with relatively high electrical conductivity relative to a bulk electrical conductivity of the composite thermal-interface material. Referring now toFIG.4, a heat-transfer component400with a composite thermal-interface material410applied to a major surface of its base405, prior to being placed in thermal contact with a heat-generating component, is described. As shown inFIG.4, a second thermal-interface material420can circumscribe the composite thermal-interface material410. In some embodiments, the second thermal-interface material420has less of the metallic filler than the composite TIM410. In particular embodiments, the second TIM420is devoid of the metallic filler (at least when applied to the heat-transfer component400). As shown inFIG.4, the second thermal-interface material420can be applied to the base405in a manner so that the second TIM420extends around an outer periphery415of the composite thermal-interface material. For example, the second thermal-interface material420can extend around the outer periphery415, in spaced relation thereto, defining a peripheral gap430between the composite TIM410and the second TIM420. On assembly of the heat-transfer component400(having a composite TIM and second TIM so-applied) with a heat-generating component (e.g., heat-generating component110described in relation toFIG.1), the composite TIM410and the second TIM420can spread laterally outward, shrinking or even filling the peripheral gap430. By enclosing the periphery415of the composite TIM410when the heat-transfer component400is assembled with a heat-generating component, the second TIM420can encapsulate the metallic filler within the composite TIM410, inhibiting or altogether preventing the metallic filler from leaking, seeping or otherwise migrating out of the interface region defined between the heat-transfer component400and a heat-generating component. As noted above, a composite thermal-interface material can include a metallic filler dispersed throughout a carrier substrate. In some embodiments a composite thermal-interface material410includes a silicone-oil based carrier substrate, or other suitable organic substrates, and a gallium alloy (or substantially pure gallium). An example of a suitable gallium alloy includes, pure gallium, as well as a gallium, indium and tin alloy. Some such alloys are available commercially under the mark Galinstan®. Such alloys can melt at temperatures as low as −19° C. and thus are liquid at typical room temperature. Like disclosed composite TIMs, some embodiments of the second thermal-interface material420include a silicone-oil based carrier substrate. Nevertheless, to ensure material compatibility between a composite TIM410containing an alloy of gallium (or pure gallium) and the second TIM420, some embodiments of the second thermal-interface material are devoid of fillers that contain aluminum or other materials incompatible or reactive with gallium. Nevertheless, the second TIM420can include one or more other filler materials to enhance thermal contact in the interface region filled with the second TIM. These other fillers can remain in a solid phase during operation of the heat-generating component, e.g., a powdered or other small-particle form of a filler. Examples of such other fillers include particle forms of ceramics, e.g., silicon carbide, diamond, zinc oxide, boron nitride, aluminum oxide etc. It is preferable, but not necessary to have similar order of magnitude of viscosity and/or similar bond line thickness for the two TIM materials410and420. Other examples of suitable solid filler materials include particle forms of other metal alloys, e.g., alloys of copper or silver, that are non-reactive with the metallic filler in the composite TIM410. In still other embodiments, the second thermal-interface material can be a curable thermal-interface material (e.g., an elastomer or a thin bondline epoxy) that cures or polymerizes when exposed to air or elevated (relative to typical ambient) temperatures. A second TIM420, as described, can have a significantly higher thermal-interface resistance compared to disclosed thermal-interface materials410and even compared to conventional thermal-interface materials. Nevertheless, interface regions occupied by the second TIM typically are exposed to a significantly lower heat flux compared to interface regions occupied by disclosed composite thermal-interface material, and thus do not materially degrade overall thermal performance. Consequently, a deleterious effect on overall thermal performance from using the lower-performing second TIM420can be avoided by applying the composite TIM410in regions of high heat flux and applying the second TIM420to regions exposed to lower heat flux. Despite containing metallic fillers, disclosed composite thermal-interface materials can have relatively high (compared to metals) volume resistivity. For example, some disclosed composite thermal-interface materials have a volume resistivity that exceeds about 50 Ohm-cm. Nevertheless, some embodiments of the second thermal-interface material have a volume resistivity that is on-the-order of 1012. Accordingly, a ratio of volume resistivity of disclosed second thermal-interface materials to volume resistivity of disclosed composite thermal-interface material can exceed about 104, and can approach or exceed 106, 107, 108, 109, or even 1010. Other embodiments of the metallic filler include eutectic and non-eutectic alloys of gallium having a solid-to-liquid transition temperature between about 5° C. and about 95° C., e.g., between about 15° C. and about 95° C., such as, for example, between about 25° C. and about 80° C., with between about 40° C. and about 70° C., between about 50° C. and about 60° C., or about 55° C. being specific examples of temperatures at which phase transition from solid-to-liquid occurs, or at least begins. Disclosed metallic fillers can incorporate eutectic and non-eutectic mixtures of Bismuth, Indium, Tin and Gallium. As understood by those of ordinary skill in the art, eutectic mixtures exhibit a melting-point temperature (or a narrow-band of temperatures over which melting occurs) that is below the melting point of each constituent component in the mixture, while non-eutectic mixtures melt over a broader range of temperatures. Adjusting the relative weight percent of each constituent component in a mixture of, e.g., Bismuth, Indium, Tin and Gallium can correspondingly adjust the melting temperature (or range of temperatures for non-eutectic mixtures) of the mixture. A viscosity of some disclosed metallic fillers in a molten phase is very low, which can exacerbate leakage, seepage or other migration that can occur when a thermal-interface is under compressive load. Nevertheless, the second TIM420(FIG.4) that circumscribes the composite TIM410can be devoid of the metallic filler used in the TIM410. Such a second TIM420, by virtue of being devoid of the metallic filler in the composite TIM410, can inhibit or prevent migration, seepage, or leakage of the molten-phase metallic filler outside a desired region of the interface between the heat-transfer component and the heat-generating component. FIGS.5A and5Bshow a photograph of a working embodiment501of a composite TIM510circumscribed by a second TIM520applied to a major surface505of a base506of a heat-transfer component. The annotations inFIG.5Bdepict an inner region550of the major surface505and an outer region560of the major surface505. The composite TIM510has been applied to the major surface505within the inner region550and the second TIM520has been applied to the major surface505within the outer region560. As with the composite and second TIMs shown schematically inFIG.4, the second TIM520extends around an outer periphery of the composite TIM510in spaced relation to the composite TIM, defining a gap530therebetween. FIG.5A and5Bshow a majority of the thermal-interface material applied to the heat-transfer component being a composite material510, with just a single layer of second thermal-interface material520extending around the composite material. Other embodiments (e.g.,FIGS.5C and5E) rely on a relatively small quantity of composite material510applied to an interface region exposed to an expected “hot spot” (e.g., a region of high heat flux) with the remainder of the interface between the heat-transfer component and the heat generating component being filled with a relatively lower performance, but electrically insulating, second TIM520. In still other embodimentsFIGS.5D and5F), the composite material510can be applied to a plurality of interface regions (expected to be exposed to hot spots) interspersed among other regions filled with the second TIM520. In some respects, disclosed principles pertain to heat-transfer components having a layer of TIM applied to a heat-transfer surface before assembly of the heat-transfer component with a heat-generating (or a heat-absorbing) device. For example, a composite TIM and an enclosing, second TIM, as described herein, can be applied to a heat-transfer component, a heat-generating component, or both, using conventional approaches. For example, asFIGS.5A and5Bshow, a composite TIM, a second TIM, or both, can be screen printed. InFIGS.5A and5B, 6 rows of 4 rectangular “pixels” of composite TIM510has been screen printed on the surface505. InFIG.5A, each rectangular “pixel” is laterally spaced from the others and from the surrounding second TIM520. Further, each rectangular “pixel” is bisected by a diagonal gap, dividing each rectangular “pixel” into a pair of triangular “sub-pixels.” Similarly, the second TIM520has been screen printed in a pixelated arrangement inFIGS.5A and5B. As shown, the pixelated arrangement of the second TIM520, which surrounds the composite TIM510, has a single rectangular “pixel” depth, though like the composite TIM510, each rectangular “pixel” of the second TIM520is bisected by a diagonal gap, dividing each rectangular “pixel” into a pair of triangular “sub-pixels.” In some embodiments, the composite TIM and the second TIM can be screen printed using a single screen-printing template. For example, a template can be placed over a surface that will receive the composite TIM and the second TIM. The composite TIM and the second TIM can then be applied consecutively or concurrently, e.g., using a roller or other screen-printing tool. Alternatively, the composite TIM, the second TIM, or both, can be dispensed within the inner region550and outer region560, respectively from a tube, syringe, or other dispensing device. In some embodiments (e.g., dispensed and screen-printed embodiments), the composite TIM and the second TIM can be applied to a surface with little or no gap between them. For example, referring now toFIGS.6through9, methods of applying a composite TIM and a second, enclosing TIM are described. InFIG.6, a first region of TIM is applied to a major surface of a heat-transfer component, a heat-generating component, or both, at610. Such application can be effected by screen printing, dispensing (e.g., from a tube, syringe or other dispensing device) or otherwise applied.FIG.7shows an example of such a major surface700. The TIM applied to the first region can be a composite TIM (as shown by the composite TIM800inFIG.8A) or an enclosing second TIM (as shown by the second TIM850inFIG.8B). Referring still toFIG.6, a second region of TIM can be applied (e.g., via screen printing, dispensing, or another application technique) to the major surface at620, resulting in a major surface as shown inFIG.9. For example, when the composite TIM is applied at610, as inFIG.8A, the second thermal-interface material can be applied at620, leading to the arrangement inFIG.9. Alternatively, when the second TIM is applied at610, as inFIG.8B, the composite thermal-interface material can be applied at620, also leading to the arrangement inFIG.9. In further embodiments, the TIM applied at610can be applied to a major surface of a heat-generating component, and the TIM applied at620can be applied to a major surface of a heat-transfer component, or vice-versa. Further the TIM applied at610and the TIM applied at620can be applied to a major surface of a heat-generating component. At630, the heat-transfer component can be mounted in a manner that places it into thermal contact with the heat-generating component with the composite TIM and the second TIM disposed within the interstitial region between the components. Compression of the components toward each other can cause the composite TIM and the second TIM to spread laterally outward and to wet the major surfaces of the heat-transfer component and the heat-generating component, providing a low-thermal-resistance interface between these components. In connection with a multi-chip package, not shown, a “lattice” of thermal-interface materials can be applied to a heat-transfer component. For example, a plurality of composite and second TIM arrangements, each being similar to the arrangement shown inFIG.4, can be applied to a major surface of a heat-transfer component to be placed into thermal contact with each of several heat-generating components. The position, orientation and size of each composite and second TIM arrangement can correspond to a respective heat-generating component among a plurality of heat-generating components, providing enhanced heat transfer from each heat-generating component. In other embodiments, e.g., single-chip packages where the die defines one or more “hot-spots” or multi-chip packages where one or more of the plurality of dice defines one or more “hot-spots,” an application of composite TIM can correspond to each “hot-spot” location and shape, and each application of composite TIM can be circumscribed by a second TIM as described above in relation toFIG.4. Such alternative arrangements of composite TIM and second TIM are also amenable to screen printing or dispensing methods as described above. The embodiments described above generally concern composite thermal-interface materials, a component of which are liquid or can partially or wholly undergo phase transition within an expected range of operating temperatures. More particularly, but not exclusively, this disclosure pertains to devices and systems for transferring heat, e.g., for cooling heat-generating, electrical components, that incorporate such composite thermal-interface materials. Despite the description of certain details of composite thermal-interface materials, as well as heat-transfer components and heat-generating components, as well as electrical devices that incorporate them, the previous description is provided to enable a person skilled in the art to make or use the disclosed principles. Embodiments other than those described above in detail are contemplated based on the principles disclosed herein, together with any attendant changes in configurations of the respective apparatus or changes in order of method acts described herein, without departing from the spirit or scope of this disclosure. Various modifications to the examples described herein will be readily apparent to those skilled in the art. For example, heat-generating components may be embodied other than as shown inFIG.1. For example (e.g.,FIG.1A), a single package of an electrical device can have one or more “chiplets”112′ rather than the single die112shown inFIG.1. In such an embodiment, one or more of the chiplets112′ may be packaged under an integrated heat spreader (IHS) (not shown) and the IHS can be placed into thermal contact with a corresponding heat-transfer component. Still further, one or more of the chiplets112′ may have a bare die placed into thermal contact with a heat-transfer component. In some embodiments, each heat-generating die or other component is placed under an IHS, which is placed into thermal contact with the heat-transfer component. In some embodiments, each heat-generating component has a bare die, which is placed into thermal contact with the heat-transfer component. In still other system embodiments, one or more of the heat-generating die or other components is placed under an IHS, which is placed into thermal contact with the heat-transfer component, and one or more other of the heat-generating components has a bare die, which is also or alternatively placed into thermal contact with the heat-transfer component. Further alternative embodiments are possible. For example, the description above provides details of a thermal-interface material applied to a heat-transfer component prior to assembly of the heat-transfer component with a heat-generating component. In other embodiments, the thermal-interface material can be applied to an outer surface (e.g., un-numbered major surface inFIG.1) of a bare die or an outer surface of an IHS (e.g., rather than to the base122of the heat-transfer component120) prior to assembly of the heat-transfer component with the heat-generating component. Further, other system configurations and types incorporating composite thermal-interface materials of the type described herein can be cooled or heated. For example, one or more electrical components in a 1U (or even a ½-U) server (or other electronic device, such as, for example, a 5G cellular radio, a power generation or transmission device) can be cooled by a heat-transfer device and a disclosed thermal-interface material can be applied within an interstitial gap between the heat-transfer device and the electrical component. Many other types of electrical devices, such as, for example, a graphics processor, a television, power electronics devices (e.g., an IGBT), communications transmission devices and other networking devices, among others, have heat-dissipating devices that can incorporate metallic thermal-interface materials as described. As but one particular example, one or more heat-dissipating components in a communications or other network device (e.g., a so-called 5G transmission device) can be cooled by a heat-transfer device incorporating a pre-applied composite TIM. Similarly, some electrical storage batteries dissipate substantial amounts of heat while discharging or charging. For example, some batteries that can store substantial amounts of energy, e.g., a 5 kW-h to 50 kW-h or a 500 kW-h battery, can be cooled by a system that incorporates a composite thermal-interface material as described. Directions and other relative references (e.g., up, down, top, bottom, left, right, rearward, forward, etc.) may be used to facilitate discussion of the drawings and principles herein, but are not intended to be limiting. For example, certain terms may be used such as “up,” “down,”, “upper,” “lower,” “horizontal,” “vertical,” “left,” “right,” and the like. Such terms are used, where applicable, to provide some clarity of description when dealing with relative relationships, particularly with respect to the illustrated embodiments. Such terms are not, however, intended to imply absolute relationships, positions, and/or orientations. For example, with respect to an object, an “upper” surface can become a “lower” surface simply by turning the object over. Nevertheless, it is still the same surface, and the object remains the same. As used herein, “and/or” means “and” or “or”, as well as “and” and “or.” Moreover, all patent and non-patent literature cited herein is hereby incorporated by reference in its entirety for all purposes. And, those of ordinary skill in the art will appreciate that the exemplary embodiments disclosed herein can be adapted to various configurations and/or uses without departing from the disclosed principles. Applying the principles disclosed herein, it is possible to provide a wide variety of metallic thermal-interface materials and heat-transfer components incorporating such metallic thermal-interface materials, as well as related methods and systems. For example, the principles described above in connection with any particular example can be combined with the principles described in connection with another example described herein. Thus, all structural and functional equivalents to the features and method acts of the various embodiments described throughout the disclosure that are known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the principles described and the features and acts claimed herein. Accordingly, neither the claims nor this detailed description shall be construed in a limiting sense, and following a review of this disclosure, those of ordinary skill in the art will appreciate the wide variety of components, devices, systems, and related methods that can be devised using the various concepts described herein. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim feature is to be construed under the provisions of 35 USC 112(f), unless the feature is expressly recited using the phrase “means for” or “step for”. The appended claims are not intended to be limited to the embodiments shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to a feature in the singular, such as by use of the article “a” or “an” is not intended to mean “one and only one” unless specifically so stated, but rather “one or more”. Further, in view of the many possible embodiments to which the disclosed principles can be applied, we reserve the right to claim any and all combinations of features and technologies described herein as understood by a person of ordinary skill in the art, including the right to claim, for example, all that comes within the scope and spirit of the foregoing description, as well as the combinations recited, literally and equivalently, in any claims presented anytime throughout prosecution of this application or any application claiming benefit of or priority from this application, and more particularly but not exclusively in the claims appended hereto. | 32,441 |
11943900 | DETAILED DESCRIPTION Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. Existing liquid cooling transportation solutions are mainly developed for individual servers which is not efficient in scale. Embodiments of the current disclosure provides a fluid deployment unit and an end to end solution for large scale server liquid cooling testing, delivery, and/or deployment for data centers. According to a first aspect, a fluid deployment unit includes an expandable container containing mixed fluids in a gaseous region and a liquid region, where the expandable container includes a gas-out port, a liquid-out port, a gas-in port, and a liquid-in port, where at least the gaseous region is designed so that a volume can be expanded. The fluid deployment unit includes a first three-way valve having a first port coupled to the liquid-out port of the expandable container, a second port coupled to the gas-out port of the expandable container, and a third port matable to an inlet of an electronic rack. The fluid deployment unit includes a second three-way valve having a first port matable to an input port of a liquid to liquid exchange unit, a second port coupled to the gas-in port of the expandable container, and a third port matable to an outlet of the electronic rack, where the liquid-in port of the expandable container is matable to an output port of the liquid to liquid exchange unit. The fluid deployment unit can be used for server test, delivery, transport, and/or deployment purposes. In one embodiment, the fluid deployment unit further includes a first pump coupled between the gas-out port of the expandable container and the first port of the first valve, where the first pump extracts a mixed fluid in gaseous phase from the expandable container. In one embodiment, the fluid deployment unit further includes a second pump coupled between the gas-in port of the expandable container and the second port of the second valve, where the second pump pumps a mixed fluid in gaseous phase into the expandable container. In one embodiment, the expandable container includes a number of compartments each containing a mixed fluid in a gaseous region and a liquid region. In one embodiment, the mixed fluid includes an inert gas and the coolant liquid, where the coolant liquid is used as a two-phase coolant liquid. In one embodiment, the inert gas includes nitrogen gas. In one embodiment, the expandable container expands in volume when the expandable container is heated and/or pressurized, where the expandable container includes an expandable or collapsible membrane portion and a stainless steel portion. In one embodiment, the third port of the first three-way valve is matable to a facility inlet line, where the facility inlet line is coupled to inlets of a number of electronic racks. In one embodiment, the third port of the second three-way valve is matable to a facility outlet line, where the facility outlet line is coupled to outlets of a number of electronic racks. In one embodiment, the liquid to liquid exchange unit forms a coolant loop with the fluid deployment unit and the liquid to liquid exchange unit includes a compressor/condenser that cools a liquid of the coolant loop. In one embodiment, the fluid deployment unit is transportable for deployment separate from an electronic rack, where the fluid deployment unit is filled with a coolant liquid and the electronic rack is filled with an inert gas when transported. In one embodiment, when deploying the electronic rack, inert gas is discharged from the electronic rack to the fluid deployment unit during a first time interval, where a coolant liquid is charged from the fluid deployment unit to the electronic rack during a second time interval, where the inert gas is containable and reusable by the electronic rack and the fluid deployment unit. In one embodiment, when performing a test for the electronic rack, a coolant liquid recirculates between the electronic rack and a test assistant unit via the fluid deployment unit, wherein the test includes performance, verification, thermal cycle, thermal shock, reliability, functional, and/or acceleration tests. In one embodiment, when performing a test for the electronic rack, a coolant liquid is discharged from the electronic rack including the servers to the fluid deployment unit during a first time interval, wherein inert gas is charged from the fluid deployment unit to the electronic rack including the servers to a predetermined pressure during a second time interval, wherein the test includes a leakage test to test for a decrease in pressure of the inert gas containable in the one or more servers. This procedure can be used to prepare the racks and servers for transportation to a deployment site. In one embodiment, when performing a deployment of a number of electronics racks, inert gas is discharged from a first of the electronic racks to the fluid deployment unit during a first time interval, where a cooling liquid is charged from the fluid deployment unit to a second of the electronic racks during a second time interval. According to a second aspect, a method/system to deploy an electronic rack is disclosed. In response to determining the electronic rack has coolant liquid therein, the system removes the coolant liquid from the electronic rack. The system charges the electronic rack with an inert gas to a predetermined pressure. The system seals the electronic rack with the inert gas at the predetermined pressure, where the electronic rack having the inert gas is transport to a deployment. FIG.1is a block diagram illustrating a fluid deployment unit100according to one embodiment. fluid deployment unit (or unit)100includes a mix fluid container101having two regions121-123. A first region123can contain an inert gas127, such as a nitrogen gas. A second region121can contain a cooling (coolant) liquid129to cool server electronics, where the server electronics may or may not be submersed in cooling liquid129for cooling. In one embodiment, cooling liquid129includes propylene glycol plus purified or deionized water. In one embodiment, the cooling liquid129can operate in a single phase mode. For example, when the cooling liquid operates in the single phase mode, the cooling liquid in liquid phase can be circulated to server electronics in an electronic rack, where, when the server electronics operates, the server electronics generate heat that is transferred to the single phase cooling liquid, where the single phase cooling liquid circulates back to the fluid deployment unit. In one embodiment, cooling liquid129includes a dielectric solution which can operate in a phase change mode (two-phase mode). When a dielectric solution operates in phase change mode, cooling dielectric solution in liquid phase can be circulated to server electronics in an electronic rack, where, when the server electronics operates, the server electronics generate heat that is transferred to the dielectric solution, thereby causing at least some of the dielectric solution to turn into vapor phase. The dielectric solution in vapor phase then returns back to the fluid deployment unit. In one embodiment, region121and/or123can be designed with flexible containing material such as a polymer with an expandability factor greater than a predetermined threshold, so that a volume of the regions121-123can expand when operating under heat/pressure. For example, container101can include a stainless steel tank portion near region121, and an expandable/collapsible polymer balloon portion near region123, where the expandable/collapsible polymer balloon portion can expand when pressure increases in container101. In one embodiment, region123can be coupled to a gas-out line119and a gas-in line117. In one embodiment, region121can be coupled to a liquid-out line115and liquid-in line113. In one embodiment, liquid-out line115can include two-way valve111, and liquid-in line113can include two-way valve109. In one embodiment, a pump131is coupled between valves109and111. Pump131and valves109-111can be used to control a liquid flow through container101. In one embodiment, unit100includes a controller (not shown) electrically connected to the pumps and valves of unit100to control the operations of pumps and valves of unit100. In one embodiment, fluid deployment unit100can include ports #a, #b, #c, and #d, where ports #a and #b can be connected to an electronic rack, and ports #c and #d can be connected to a testing assistance unit, as further described inFIG.3. In one embodiment, the gas-out line119and liquid-out line115are connected to a three-way valve105, and three-way valve105is connected to port #a of unit100. For example, valve105can include port #1 coupled to port #a, port #2 coupled to gas-out line119, and port #3 coupled to liquid-out line115. Port #a is designed to mate to an inlet (supply) of an electronic rack. In one embodiment, liquid-in line113is extended to port #c. The gas-in line117is also extended to ports #b and #d through a three-way valve107. For example, three-way valve107can be coupled to gas-in line117, ports #b, and #d of unit100. Specifically, valve107can include port #4 coupled to port #b, port #5 coupled to port #d, and port #6 coupled to gas-in line117. The operations of valve105can be as follows. When ports #3→#1 are open, valve105charges cooling liquid from liquid region121of unit100to an electronic rack (shown inFIG.3) via port #a. When ports #2→#1 are open, valve105charges inert (such as nitrogen) gas from gas region123of unit100to an electronic rack via port #a. The operations of valve107can be as follows. When ports #4→#5 are open, valve107can return a cooling liquid from an electronic rack (shown inFIG.3) at port #b. Thereafter, the cooling liquid is directed to port #d and to a test assistant unit (shown inFIG.3), where the cooling liquid is circulated from the test assistant unit to region121of container101. When ports #4→#6 are open, valve107can return gas from an electronic rack at port #b, directing the gas to gas region123of unit100. In one embodiment, port #a can mate with an inlet of an electronic rack. In one embodiment, port #b can mate to an outlet of the electronic rack. Port #a and #b can be used to charge a liquid and extract a gas from the electronic rack, or charge a gas and extract a liquid from the electronic rack. In one embodiment, port #c can be coupled to a supply port of a test assistant unit (not shown), such as a cooler, for coolant fluid filling supply, and port #d can be coupled to a return port of the test assistant unit. The test assistant unit can provide a cooling capacity to unit100to support various tests (such as thermal and functional tests) provided by unit100. In another embodiment, port #c and #d of unit100can be coupled to a cooler that includes a condenser and compressor, or other type of cooling unit, as further shown inFIG.3. When unit100is coupled to the cooler, cooling liquid of unit100can circulate the cooler via port #c and #d for the cooling liquid to be cooled. FIG.2is a block diagram illustrating a fluid deployment unit200according to another embodiment. Fluid deployment unit200can represent fluid deployment unit100ofFIG.1. As shown, unit200includes two or more compartments203A-203C that are contained within container201. The compartments203A-203C can be individualized to have different sizes and/or volumes. In one embodiment, each compartment is associated with an electronic rack, where each compartment can include one pair of gas region and liquid region. As described inFIG.1with respect to container101, each compartment can include a stainless steel tank portion and an expandable polymer portion. In one embodiment, unit200is equipped with one or more electronic rack(s) during the rack testing, transporting, deployment, and commissioning phases. FIG.3is a block diagram illustrating a test system300according to one embodiment. As shown, system300can include electronic rack301, where electronic rack301is coupled to a fluid deployment unit100. Electronic rack301can include servers303A-303G. Each of servers303A-303G can be coupled to inlet305and outlet307of rack301, where inlet305supplies servers303A-303G with a cooling liquid from unit100, and outlet307returns the cooling liquid to unit100. In one embodiment, each of servers303A-303G can include either liquid cooling, where cooling liquid circulates through a head exchanger (heat sink) of server electronic, an immersion cooling where server electronics can be immersed in the cooling liquid supplied to servers303A-303G. For immersion cooling, each individual server can be designed as an independent immersion unit, and the cooling liquid can be a dielectric solution. In one embodiment, servers303A-303G are liquid cooled and/or air cooled without immersion cooling. In this setup, fluid deployment unit100can be coupled to an external cooler321only during a rack testing phase. In one embodiment, servers303A-303G can be configured to provide information technology (IT) services. Specifically, servers303A-303G can include a host server (referred to as a host node) and/or one or more compute servers (also referred to as computing nodes, such as CPU server and GPU server). The host server (having one or more CPUs) typically interfaces with clients (not shown) over a network (e.g., Internet) to receive a request for a particular service such as storage services (e.g., cloud-based storage services such as backup and/or restoration), executing an application to perform certain operations (e.g., image processing, deep data learning algorithms or modeling, etc., as a part of a software-as-a-service or SaaS platform). In response to the request, the host server distributes the tasks to one or more of the performance computing nodes or compute servers (having one or more GPUs) managed by the host server. In one embodiment, servers303A-303G can perform any type of computing task and/or may be any type of computing device (e.g., a server, a storage device, etc.). In one embodiment, servers303A-303G may be edge computing devices. Thus, while servers303A-303G provide the IT services, the equipment generates heat that is transferred into a cooling liquid (or phase change fluid). Fluid deployment unit100can function as an intermediate unit between electronic rack301and a test assistant unit321, for intermediate storage of cooling liquid in either gas or liquid phase. It needs to be mentioned that the deployment unit100stores both the gas and cooling fluids but fluid deployment unit100needs to connect with an external cooling source, such as test assistant unit (or a cooler)321, for cooling, since unit100does not have the capability for cooling according to one embodiment. In one embodiment, test assistant unit321includes a liquid-to-liquid heat exchange unit323and liquid-to-liquid heat exchange unit323can be coupled to refrigerant loop325. Refrigerant loop325can include a compressor and condenser unit. For example, ports #d and #c are coupled to a cooling liquid loop327to circulate a liquid for cooling. Cooling liquid loop327is coupled to test assistant unit321, which can be used for cooling the cooling fluid that runs to electronic rack301and liquid region121of container101. Test assistant unit321includes heat exchange unit323, used to exchange heat (e.g., cool) for the cooling fluid by extracting the heat to refrigerant loop325, where the compress and condenser removes the heat. The condenser can be an air cooled or liquid cooled condenser. In one embodiment, coolant fluid container101can also be charged by a facility-based source (not shown). Once supplied or the charging process is completed, valves105-107and/or pump103,125can be connected to electronic rack301with either inert gas or cooling liquid from coolant fluid container101via inlet/outlet305-307of the rack. FIG.4is a block diagram illustrating cooling fluid circulating at a test system300according to one embodiment. As shown, system300can provide full cycles of testing for electronic rack301. The types of tests can include performance, verification, thermal cycle, thermal shock, reliability, functional, acceleration testing, and so on. For example, a cooling fluid is recirculating among the servers via unit100and loop327to conduct the tests. In this case, valve105has ports #1 and #3 open, valve107has ports #4 and #5 open, valves109-111are open. Pump131can charge cooling liquid to flow between servers303A-303G, unit100, and condenser321, via loop327, inlet305, and outlet307. During a test phase, different types of functioning, performance, benchmark, acceleration tests, etc. can be conducted. FIG.5is a block diagram illustrating a cooling fluid/liquid being discharged from an electronic rack301to a fluid deployment unit100according to one embodiment. As shown, system300can provide a discharge operation for cooling liquid to be discharged from servers303A-303G to unit100. In this case, valve107has ports #4 and #5 open, valve109is open, and valve111is closed. Pump131can charge cooling liquid to flow from servers303A-303G to unit100, via outlet307. It needs to be mentioned that in order to fully release fluid out of electronic rack, pump131can be a high performance pump in an embodiment. FIG.6is a block diagram illustrating a gas being charged from a fluid deployment unit100to an electronic rack301according to one embodiment. As shown,FIG.6illustrates an inert gas (nitrogen) being charged from unit100to electronic rack301. In one embodiment, once liquid is discharged from servers303A-303G, valve105opens ports #1-#2. Pump125then operates to charge nitrogen gas from unit100to servers303A-303G via inlet305. In one embodiment, a leakage test can be performed for the electronic rack by discharging a coolant liquid from the electronic rack and charging the electronic rack with an inert gas as illustrated byFIGS.5-6. For example, a coolant liquid is discharged from servers303of electronic rack301to fluid deployment unit100during a first time interval and inert gas is charged from fluid deployment unit100to servers303of electronic rack301to a predetermined pressure during a second time interval. Associated valves (not shown) for servers303can keep the pressure contained within servers303. Thereafter in preparation of the electronic rack shipment, a decrease in pressure (for example via pressure sensor at the servers303) for any of servers303can be verified for gas leakage. In an embodiment, if the servers are not equipped with individual valves, then the pressure can be contained by rack side valves (not shown). FIG.7is a block diagram illustrating a fluid deployment unit and electronic racks in a transportation container according to one embodiment.FIG.7shows the operation when racks301are being transported to a data center in a transportation container700. In one embodiment, fluid unit100is transported together with one or more electronic racks301A-301C at the same time. In one embodiment, only container101is transported with racks301A-301C. In one embodiment, unit100are transported separately from racks301A-301C. In this case, racks301A-301C can be transported having servers filled with inert (nitrogen) gas127, where fluid unit100or container101can have a nearly empty gas region but with a liquid region filled with cooling fluid129. In one embodiment, racks301A-301C and servers therein are pressurized during the transportation. Having the servers303of racks301A-301C filled with inert gas eases transportation of electronic racks301A-301C.FIG.7shows only three electronic racks for the purposes of illustration, however, any other number of electronic racks can be transported by transportation container700. FIG.8is a block diagram illustrating a fluid deployment unit100and electronic racks301A-301C at deployment site800according to one embodiment. The deployment site800can be a data center facility, a test facility, or an intermediate site. In one embodiment, once racks301A-301C and servers303are delivered to the deployment site, an operator can check a pressure of servers303to ensure that there is no leak. Once the racks301A-301C and fluid deployment unit100are delivered, inlets and outlets of racks301A-301C and ports #a-#b of fluid deployment unit100can be mated to a data center fluid loop (fluid lines)801-803. In one embodiment, servers303of electronic racks301A-301C can be checked for pressure prior to mating to identify if there are any potential leaks. FIG.9is a block diagram illustrating electronic racks301A-301C discharging gas to a fluid deployment unit100according to one embodiment. As shown, when electronic racks301A-301C and fluid deployment unit100are mated to fluid loop (fluid lines)801-803, electronic racks301A-301C can release inert (nitrogen) gas to fluid deployment unit100and electronic racks301A-301C can be filled with cooling liquid via fluid deployment unit100, or vice versa, depending on the operations of unit100. In one embodiment, rack301A can be charged with cooling liquid at a first time interval. At a second time interval, rack301B-301C can be discharged of nitrogen gas. In one embodiment, the operation to discharge electronic racks301A-301C of nitrogen gas and to fill electronic racks301A-301C with cooling liquid can be perform one electronic rack at a time. In one embodiment, if a total volume of the inert (nitrogen) gas in container101and coolant liquid in container101is kept relatively constant, the reduction of the coolant fluid in the container101may enable more volume of the nitrogen gas to fill in container101. For an expandable container101, filling container101with nitrogen gas can expand container101for additional storage to store additional nitrogen gas. FIG.10is a block diagram illustrating a fluid deployment unit100charging a cooling liquid to electronic racks301A-301C at deployment site800according to one embodiment. As shown, unit100is charging electronic rack301B with cooling liquid. It can be seen that charging of rack301A is complete (rack301A is ready to begin server operations), while rack301C is being filled with nitrogen gas. In one embodiment, the connection of racks301A-301C to facility lines801-803can be mated/unmated one by one to prioritize charging/discharging of electronic racks that are in an immediate demand for services. Container101of unit100, inFIGS.8-10, can include a mixture of liquid and/or gas (not shown), and the mixture can be segregated. FIG.11is a block diagram illustrating a fluid deployment unit100charged a cooling liquid to electronic racks at deployment site800according to one embodiment. As shown, racks301A-301C are filled with cooling liquid, and are ready for services. Here, container101can contain the inert gas that are discharged from servers303of racks301A-301C. This way, the inert gas and cooling liquid are containable and reusable by electronic racks301A-301C and fluid deployment unit100. FIG.12is a flow diagram illustrating a process1200to deliver and deploy liquid cooling systems at scale according to one embodiment. Process1200may be performed by processing logic which may include software, hardware, or a combination thereof. For example, process700may be performed by unit100(or a controller of unit100) ofFIG.1. At block1201, in response to determining an electronic rack has coolant liquid therein, processing logic discharges the coolant liquid from the electronic rack to a fluid deployment unit. For example, as illustrated inFIG.5, unit100coupled to the electronic rack may operate pump131to draw liquid from electronic rack301via port #b, where valve107has ports #4 and #5 open, valve109is open, and valve111is closed. At block1203, processing logic charges the electronic rack with an inert gas to a predetermined pressure. For example, as illustrated inFIG.6, unit100operates pump125to charge servers303of electronic rack301with inert gas, via port #a, where valve105has ports #1 and #2 open. At block1205, processing logic seals the electronic rack with the inert gas at the predetermined pressure, where the electronic rack having the inert gas is transport to a deployment site. For example, port #a of unit100is decoupled from electronic rack301, where a valve corresponding to servers303are closed to prevent inert gas from leaking. In one embodiment, when at a deployment site, processing logic further discharges the inert gas of the electronic rack to the fluid deployment unit and charges the electronic rack with a coolant liquid from the fluid deployment unit, where the inert gas is containable and reusable by the electronic rack and the fluid deployment unit. For example, as illustrated inFIGS.8-11, after transportation, electronic racks301are coupled to facility lines801-803, where a valve corresponding to servers303are closed to prevent inert gas from leaking. In one embodiment, the fluid deployment unit contains mixed fluids in a gaseous region and a liquid region. In one embodiment, the inert gas includes nitrogen gas. In one embodiment, the fluid deployment unit includes an expandable container and the expandable container includes a number of compartments each containing mixed fluids in a gaseous region and a liquid region. In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the invention as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. | 26,691 |
11943901 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments of the present disclosure, examples of which are described herein and illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with embodiments and/or examples, it will be understood that they do not limit the present disclosure to these embodiments and/or examples. On the contrary, the present disclosure covers alternatives, modifications, and equivalents. Various embodiments are described herein for various apparatuses, systems, and/or methods. Numerous specific details are set forth to provide a thorough understanding of the overall structure, function, manufacture, and use of the embodiments as described in the specification and illustrated in the accompanying drawings. It will be understood by those skilled in the art, however, that the embodiments may be practiced without such specific details. In other instances, well-known operations, components, and elements have not been described in detail so as not to obscure the embodiments described in the specification. Those of ordinary skill in the art will understand that the embodiments described and illustrated herein are non-limiting examples, and thus it can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. Computing devices in data centers are often organized into pods. Pods are standardized blocks of racks, either in a row or pair of rows, that share some common infrastructure elements like power distribution units, and network routers/switches. Within a pod, the devices on the racks may all be oriented to pull cool air in from the same side of the rack (typically referred to as the front of the rack) and discharge hot air (heated by the computing devices) out the other side of the rack (typically referred to as the back or hot side of the rack). Turning now toFIG.2, the front side of one example of a pod110is shown. The pod110has a number of racks210that each have a number of shelves230for holding computing devices. For organization and management purposes, the shelves may be grouped together in switch sections220that are each supported by the same network switch. In each of the shelves230there may be multiple bin locations240that each hold a single computing device. Each computing device may be installed in a bin with connections for power and a network connection. Turning now toFIG.3, a more detailed frontal view of one shelf230in an example rack210is shown. In this example, a computing device310is installed in each bin240in the shelf230. In this example, computing device310is an ASIC miner, but other computing device types are possible and contemplated. ASIC miners typically include one or more cooling fans314that draw air through the center of the miner where there are multiple hash boards performing calculations and generating heat. Other types of computing devices are possible and contemplated, including GPU and FPGA miners, as well as more traditional computer servers. As shown in the figure, devices and bins may be identified by stickers340and350, respectively. These stickers may include visual indicators such as printed serial numbers, asset tag numbers, and or barcodes or QR codes. The devices also have one or more indicator lights (typically LEDs)330that are visible from the front side of the device, and many such devices provide an interface accessible via network connection that permits a system administrator to activate/deactivate the lights. Turning now toFIG.4, a perspective view of one example of a container-based data center in accordance with the present disclosure is shown. In this embodiment, container400is an ISO steel shipping container and has a plurality of triangular prism or trapezoidal prism shaped vents410on at least one side. The containers may be manufactured for example according to ISO standard 668, which defines a set of specifications for intermodal freight shipping containers that are commonly available. Standard containers are 8′6″ tall and so called High-Cube containers are 9′6″ tall, but they are both generally 8 feet wide. Other types of containers are also contemplated and may be used as well. Turning now toFIG.5, a side view of one example of a container-based data center in accordance with the present disclosure is shown. In this embodiment, a significant percentage of the surface area of the side of container400(e.g., at least 90%) is used for vents. A large surface area permits improved air flow and cooling for computing devices in container400, e.g., around 500 cfm, but other air flow rates are possible and contemplated. Turning now toFIG.6, an end view of one example of a container-based data center in accordance with the present disclosure is shown. In this embodiment, container400includes one or more doors600on one end of the container. Shipping containers often come with a double cargo door on one end of the container. This door opens in two sections allowing the entire interior end of the container to be accessed. In other embodiments, doors may be located on both of the short sides of container400, or on one of the longer sides of container400. Vents410may be trapezoidal prisms in shape as shown, or triangular prisms, or other shapes (e.g., rectangular prisms). In this embodiment the top side470of the vents (e.g., on the top row of the array of vents) is extended longer to provide additional rain and snow rejection. Turning now toFIG.7, an interior view of one example of a container having air intake openings700with vents410and filters720in accordance with the present disclosure is shown. As shown in the figure, the filters are not parallel with the opening and instead are positioned at an angle to the opening. This angle permits a greater surface area for the filter relative to the size of air intake openings700. With an angle of 45 degrees as shown in the figure, the air filter is substantially larger than the corresponding air intake opening, beneficially permitting filtering with less airflow reduction. Channels730may be used to hold air filter720in place while permitting removal for cleaning. In one embodiment, air filter720may be washable metal filters, but other filter types are possible and contemplated. In some embodiments, air filter720may also be mist eliminators. Filters that are mist eliminators can remove not only dust but also moisture droplets from the air in order to protect the computing devices in the storage container. Mist eliminators work by utilizing composite mesh or vane plate surfaces to separate the mist droplets from gas streams through mechanical impingement and inertial impaction. The large surface area allows for the collection of liquids without substantially impeding the flow of gas. In some embodiments, foggers can be used in connection with the containers400when ambient temperature is too high for efficient operation. Fogger systems typically comprise an inline filter, tubing, nozzles and high-pressure (e.g., 1000 psi) misting pump modules. Misting systems typically require high pressure in order to create 3-5 micron sized droplets that are desirable for cooling operation. The fog or mist is created by forcing water through a high-pressure pump module unit that is connected to specialized misting nozzles. This creates micro fine water particles that will subsequently evaporate. It also helps to filter the incoming water since even small particles can clog the tiny fog nozzle heads. The ambient temperature can beneficially be reduced up to 35 degrees when using an outdoor misting system in some environments (e.g., when humidity is low). In some embodiments, a channel740may be connected to a bottom edge of the rectangular air filters720to catch moisture collected by the air filter, and the channel may then direct the collected moisture out of the container (e.g., via drain holes or tubes). Turning now toFIG.8, an interior view of one example of a container having racks for computing devices in accordance with the present disclosure is shown. Computing devices310are positioned on rack210such that fans314draw air in from outside container through vents410via filters720. The exhaust of the computing device310is configured to directly feed the air heated by computing device310outside the container400via exhaust openings in the side of the container800. These openings generally do not need air filters, as the volume of exiting air directs dust and debris away, so they can be left open. In other embodiments, exhaust vents of matching design to air intake vents410may be used. In place of a filter, a simple wire mesh with a square or hexagonal design (e.g., chicken wire) may be used on the exhaust openings or vents to keep falling debris out or for safety. Reference throughout the specification to “various embodiments,” “with embodiments,” “in embodiments,” or “an embodiment,” or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in various embodiments,” “with embodiments,” “in embodiments,” or “an embodiment,” or the like, in places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Thus, the particular features, structures, or characteristics illustrated or described in connection with one embodiment/example may be combined, in whole or in part, with the features, structures, functions, and/or characteristics of one or more other embodiments/examples without limitation given that such combination is not illogical or non-functional. Moreover, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the scope thereof. It should be understood that references to a single element are not necessarily so limited and may include one or more of such elements. Any directional references (e.g., plus, minus, upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above, below, vertical, horizontal, clockwise, and counterclockwise) are only used for identification purposes to aid the reader's understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of embodiments. Joinder references (e.g., attached, coupled, connected, and the like) are to be construed broadly and may include intermediate members between a connection of elements and relative movement between elements. As such, joinder references do not necessarily imply that two elements are directly connected/coupled and in fixed relation to each other. The use of “e.g.” and “for example” in the specification is to be construed broadly and is used to provide non-limiting examples of embodiments of the disclosure, and the disclosure is not limited to such examples. Uses of “and” and “or” are to be construed broadly (e.g., to be treated as “and/or”). For example, and without limitation, uses of “and” do not necessarily require all elements or features listed, and uses of “or” are inclusive unless such a construction would be illogical. While processes, systems, and methods may be described herein in connection with one or more steps in a particular sequence, it should be understood that such methods may be practiced with the steps in a different order, with certain steps performed simultaneously, with additional steps, and/or with certain described steps omitted. All matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative only and not limiting. Changes in detail or structure may be made without departing from the present disclosure. It should be understood that a computer, a system, and/or a processor as described herein may include a conventional processing apparatus known in the art, which may be capable of executing preprogrammed instructions stored in an associated memory, all performing in accordance with the functionality described herein. To the extent that the methods described herein are embodied in software, the resulting software can be stored in an associated memory and can also constitute means for performing such methods. Such a system or processor may further be of the type having ROM, RAM, RAM and ROM, and/or a combination of non-volatile and volatile memory so that any software may be stored and yet allow storage and processing of dynamically produced data and/or signals. It should be further understood that an article of manufacture in accordance with this disclosure may include a non-transitory computer-readable storage medium having a computer program encoded thereon for implementing logic and other functionality described herein. The computer program may include code to perform one or more of the methods disclosed herein. Such embodiments may be configured to execute via one or more processors, such as multiple processors that are integrated into a single system or are distributed over and connected together through a communications network, and the communications network may be wired and/or wireless. Code for implementing one or more of the features described in connection with one or more embodiments may, when executed by a processor, cause a plurality of transistors to change from a first state to a second state. A specific pattern of change (e.g., which transistors change state and which transistors do not), may be dictated, at least partially, by the logic and/or code. | 13,819 |
11943902 | DESCRIPTION OF EMBODIMENTS Description of Embodiments of Present Disclosure First, aspects of the present disclosure will be listed and described. A circuit structure according to the present disclosure is (1) a circuit structure including: a heat generating component; a bus bar connected to a connection portion of the heat generating component; an insulating base member configured to hold the heat generating component and the bus bar; and a coolant flow path provided inside the base member and through which a coolant flows, wherein the bus bar is in thermal contact with the coolant flow path, the base member includes a passage wall portion constituting the coolant flow path, and the bus bar is brought into thermal contact with the coolant flow path due to a portion of the bus bar being embedded or press-fitted into the passage wall portion, and the passage wall portion includes a groove through which the coolant flows and a protruding portion that protrudes into the groove, the protruding portion includes a slit-shaped bus bar housing groove that is open in the upper surface thereof that does not face the groove, and the bus bar is press-fitted into the bus bar housing groove. With the circuit structure according to the present disclosure, the coolant flow path is provided in the base member that holds the heat generating component and the bus bar that is connected to the connection portion of the heat generating component, and the bus bar is brought into thermal contact with the coolant flow path. The bus bar to which heat from the heat generating component is transmitted can be brought into thermal contact with the coolant flow path and cooled, and, compared to a conventional structure, the dissipation of heat from the heat generating component can be more reliably promoted with a short heat transfer path, and the heat dissipation capacity of the circuit structure can be improved. In particular, the bus bar to which heat from the heat generating component is transferred is cooled by the coolant flowing through the coolant flow path, and thus a heat dissipation effect and a cooling effect can be improved in comparison with a conventional structure when the temperature of a chassis or a housing itself that is in thermal contact with the bus bar reaches high temperatures exceeding 70° C. Note that any coolant can be used as the coolant that flows through the coolant flow path provided that it is a coolant that can be used in a vehicle such as radiator fluid. Also, the thermal contact between the bus bar and the coolant flow path can be realized with a suitable structure in which, for example, the bus bar is arranged in the surrounding region of the coolant flow path, and the bus bar is brought into contact with the passage wall portion that constitutes the coolant flow path. Also, the bus bar is connected to the connection portion of the heat generating component, and thus heat from the heat generating component can be advantageously transmitted, but the bus bar connected to the connection portion of the heat generating component encompasses both a bus bar that is used as a conductive member and a bus bar that is used simply for heat dissipation. Also, by press-fitting a portion of the bus bar into the passage wall portion that constitutes the coolant flow path, the bus bar can be more reliably and stably brought into thermal contact with the coolant flow path, and the heat dissipation capabilities of the circuit structure of the present disclosure can be further advantageously improved (3) In (1), it is preferable that the base member includes a lower case including a lower passage wall portion and an upper case including an upper passage wall portion that is linked in a liquid-tight manner to the lower passage wall portion, and the coolant flow path is formed by including the lower passage wall portion and the upper passage wall portion linked to each other in a liquid-tight manner. This is because a simple structure in which the lower passage wall portion provided on the lower case constituting the base member and the upper passage wall portion provided on the upper case are linked in a liquid-tight matter can be used to form the coolant flow path in the base member in a space-efficient manner. (4) In (3), it is preferable that the upper passage wall portion includes a lid portion configured to cover the lower passage wall portion. The protruding portion of the upper passage wall portion protrudes into the groove that is demarcated by the lower passage wall portion and through which the coolant flows, and thus the protruding portion can be cooled quickly by the coolant that flows therearound. A portion of the bus bar is embedded or press-fitted into the protruding portion, and thus the bus bar can be quickly cooled using the coolant, and the dissipation of heat from the bus bar of the heat generating component can be further advantageously promoted. (5) In (3) or (4), it is preferable that at least one of the lower passage wall portion and the upper passage wall portion is configured to include a sealing rubber housing groove for housing a piece of sealing rubber, and due to the sealing rubber being compressed and brought into close contact with the sealing rubber housing groove, the lower passage wall portion and the upper passage wall portion are linked in a liquid-tight manner. The liquid-tight linking between the lower passage wall portion and the upper passage wall portion is reliably ensured by the sealing resin housed in the sealing rubber housing recess provided on at least one of the lower passage wall portion and the upper passage wall portion. Furthermore, by housing the sealing rubber in the sealing rubber housing groove, the holding properties and the positioning properties of the sealing rubber are ensured, and the attachment operation is made easier. (6) In (1), (2), (3), (4) or (5), it is preferable that a coolant input/output portion is provided protruding from the base member, one end portion of the coolant input/output portion being connected to the coolant flow path, and the other end portion being connected to an external coolant supply path. Coolant that can be used in a vehicle such as radiator fluid can be easily supplied to the coolant flow path via the coolant input/output portion. Details of Embodiments of Present Disclosure Specific examples of the circuit structure according to the present disclosure will be described with reference to the drawings below. Note that the present disclosure is not limited to these examples, and is intended to include all modifications that are indicated by the claims and are within the meaning and scope of equivalents of the claims. Embodiment 1 Embodiment 1 of the present description will be described with reference toFIGS.1to7. A circuit structure10is installed in a vehicle (not shown) such as an electric automobile or a hybrid automobile, for example, and supplies electric power from a power source12such as a battery to a load14such as a motor, and performs control (seeFIG.3). While the circuit structure10can be oriented in any direction, in the following description, the Z direction is regarded as the upward direction, the Y direction is regarded as the rightward direction in the length direction, and the X direction is regarded as the forward direction in the width direction. Furthermore, when more than one of the same member is provided, the reference numeral therefor may be provided to only some of the members and may be omitted for the rest. Schematic Circuit Configuration of Circuit Structure10 As shown inFIG.3, the circuit structure10includes a circuit structure10aprovided on a positive electrode side and a circuit structure10bprovided on a negative electrode side. The positive electrode of the power supply12is connected to the input side of the circuit structure10a, and the negative electrode of the power supply12is connected to the input side of the circuit structure10b. The positive electrode of the load14is connected to the output side of the circuit structure10a, and the negative electrode of the load14is connected to the output side of the circuit structure10b. Relays16that are heat generating components connected to the power supply12and the load14are respectively connected between the input side and the output side of the circuit structure10aand the circuit structure10b. In addition, a pre-charge circuit22is connected in series to the relay16connecting the positive electrodes of the power supply12and the load14so that a pre-charge resistor18and a pre-charge relay20bypass the relay16. Note that, in Embodiment 1 of the present disclosure, the pre-charge resistor18is connected to the input side of the pre-charge relay20, as shown inFIG.3. It should be noted that, although a pre-charge circuit22is also similarly connected to the relay16connecting the negative electrodes of the power supply12and the load14, in Embodiment 1 of the present disclosure, the pre-charge circuit22connected to the relay16connecting the negative electrodes of the power supply12and the load14is not illustrated in the drawings in order to facilitate comprehension. Also, both the relay16and pre-charge relay20are relays that switch a contact portion on and off by moving the contact portion in a state where an excitation coil is energized, and on/off control is performed by a control circuit (not shown). As described above, the circuit structure10aand the circuit structure10bhave substantially the same structure. Circuit Structure10 As shown inFIGS.1and6, for example, the circuit structure10includes a lower case24that is located on the lower side and an upper case26that is located on the upper side when installed in a vehicle, and an insulating base member28is formed by the lower case24and the upper case26. A bus bar29that connects the relay16and the pre-charge circuit22and a bus bar30that connects the interior of the pre-charge circuit22are housed between the lower case24and the upper case26when attached to each other. Also, two relays16and bus bars34and36respectively connected to connection portions32aand32bof the relays16are held by the base member28in which the lower case24and the upper case26are attached to each other. Lower Case24 The lower case24is formed by injection-molding an insulating synthetic resin into a predetermined shape. The synthetic resin forming the lower case24may include a filler such as glass fiber. As shown inFIG.1, for example, the lower case24has an overall horizontally-elongated flat block shape. As shown inFIG.1, screw holes37that have a rectangular cross-section and are open upward are provided in four corners of the lower case24. As shown inFIG.1, for example, the lower case24is provided with grooves38aand38bthat are open upward and extend along circumferential edge portions, in the vicinity of the two circumferential edge portions in the width direction of the lower case24. The grooves38aand38bare linked by a linking groove40that extends in the width direction of the lower case24at the center portion in the length direction of the lower case24and is open upward. A lower passage wall portion42is formed by wall portions of the grooves38aand38band the linking groove40. Also, at an end portion on one side in the length direction of the groove38a(the right side inFIG.1), a dividing wall portion44is provided protruding at a height that is the same as the depth of the groove38aat a central portion of the groove38a, and the groove38ais divided into two by the dividing wall portion44. The dividing wall portion44has a rectangular flat plate shape, and the end portion thereof on the one side in the length direction is linked to the wall portion of the groove38a, and a recessed portion46that spans the entire vertical length of the dividing wall portion44is formed in the end portion on the other side in the length direction (the left side inFIG.1). As described below, in order to form two hose attachment coolant input/output portions86through which coolant is to flow, the end portions where the groove38adivided into two are formed at different positions in the length direction. Furthermore, a groove-shaped sealing rubber housing recess48that extends along the circumferential edge portion of the grooves38aand38band the linking groove40and is open upward is formed on the lower passage wall portion42in the vicinity of the circumferential edge portions of the grooves38aand38band the linking groove40. An annular piece of sealing rubber50that is made of rubber is housed in the sealing rubber housing recess48. Also, as shown inFIG.1, for example, rectangular tube-shaped bus bar fixing portions52to which end portions of the bus bars34and36connected to the connection portions32aand32bof the relays16are to be bolted protrude upward at four positions of the central portion of the lower case24. The central portion of the protruding end surface of each bus bar fixing portion52is provided with a bolt insertion hole54that has a rectangular cross-section and is open upward. Relay fixing portions56that have a rectangular cross-section and to which later-described leg portions94of the relays16are to be bolted are formed open upward at six positions toward the center relative to the bus bar fixing portions52. Upper Case26 The upper case26is formed by injection-molding an insulating synthetic resin into a predetermined shape. The synthetic resin forming the upper case26may include a filler such as glass fiber. As shown inFIG.1, for example, the upper case26has an overall box shape that is open upward in which a peripheral wall60that protrudes upward is formed on an outer circumferential edge portion of an upper wall58that has a substantially horizontally-elongated rectangular flat plate shape. Bolt insertion holes62that extend through the upper wall58in the plate thickness direction thereof are provided in four corners of the upper wall58of the upper case26. As shown inFIG.1, the upper wall58of the upper case26is provided with lid portions64aand64bthat cover the corresponding grooves38aand38bof the lower case24and protrude in a recessed groove shape that is open downward. Furthermore, a lid portion that covers the linking groove40of the lower case24is constituted by a region A of the upper wall58that covers the linking groove40from above (the portion indicated with a broken line inFIGS.1and2). In other words, the lid portions64aand64band the region A of the upper wall58form an upper passage wall portion. Also, as shown inFIG.2showing a bottom surface68of the upper case26, lower surfaces66of the lid portions64aand64bare respectively provided with protrusion portions70aand70bthat protrude beyond the bottom surface68of the upper wall58of the upper case26. A protrusion portion76is provided in the region A of the upper wall58of the upper case, protruding from the bottom surface68. The protrusion portion76extends in the X direction shown inFIG.2and is linked as one piece with the protrusion portions70aand70bprovided at two end portions thereof. As shown inFIG.1, slit-shaped bus bar housing grooves74aand74bthat are open in upper surfaces72aand72bof the lid portions64aand64bare respectively formed in the upper surfaces72aand72b. Also, the bus bar housing grooves74aand74bextend in the length direction of the lid portions64aand64b(left-right direction inFIG.1). As described above, the upper passage wall portion is configured to include the lid portions64aand64band the region A of the upper wall58that cover the lower passage wall portion42, and the protrusion portions70a,70b, and the protrusion portion76respectively protruding from the lid portions64aand64band the region A. Also, as shown inFIG.1, for example, bus bar fixing portion open windows78that expose the bus bar fixing portions52provided on the lower case24to the upper side of the upper case26are provided at four positions in the central portion of the upper case26extending through the upper case26. Furthermore, six relay fixing portion open windows80for exposing the six relay fixing portions56provided on the lower case24to the upper side of the upper case26are provided extending through the upper case26. Also, a pre-charge resistor installation portion82and a pre-charge relay installation portion84that respectively house the pre-charge resistor18and the pre-charge relay20are provided open upward on the one side in the length direction of the upper wall58of the upper case26(the right side inFIG.1). Furthermore, a pair of coolant input/output portions86for supplying a coolant to later-described coolant flow paths104are formed on the front side of the pre-charge relay installation portion84. The pair of coolant input/output portions86each have a cylindrical shape that is open in the vertical direction, and are configured such that coolant flows therethrough via hoses (not shown) that supply a coolant and are attached to the upper opening portions thereof via metal hose joints88. Relay16 Each relay16is a mechanical relay, and is turned on and off by a control circuit (not shown). As shown inFIGS.1,4, and5, the relay16includes a block-shaped relay body90, a pair of annular connection portions32aand32b, and a plurality (three in the present embodiment) of leg portions94. The relay body90includes a contact portion and a coil portion (not shown) therein. The pair of connection portions32aand32bare arranged lined up in the width direction (the left-right direction inFIGS.1,4, and5) on the front surface of the relay body90. Due to a current flowing across the pair of connection portions32aand32bvia the contact portion of the relay body90, heat generated by the contact portion is transferred to the pair of connection portions32aand32bthat then generate heat. The connection portions32aand32beach include a bottomed cylindrical bolt insertion hole92that extends rearward. Two leg portions94are provided on a side surface on the one side in the width direction of the relay body90(right side inFIG.1), and one leg portion94is provided on the side surface on the other side in the width direction of the relay body90(the left side inFIG.1), the leg portions94being formed protruding outward in a flat plate shape. Each leg portion94has a bolt insertion hole96extending therethrough in the vertical direction. Bus Bars34and36 The pair of bus bars34and36are each formed by machining a metal plate member that has conductive properties. As shown inFIG.1, for example, the bus bars34and36are U-shaped, and the corresponding end portions thereof on one side are first connection portions34aand36athat are to be connected to the connection portions32aand32bof the relay16, and each include a bolt insertion hole98that extends therethrough in the front-rear direction, which is the plate thickness direction. By bolting the bus bars34and36to the connection portions32aand32bof the relay16, the bus bars34and36are electrically and thermally connected to the connection portions32aand32bof the relay16. The end portions on the other side of the bus bars34and36are respectively provided with second connection portions34band36bin extension end portions thereof that extend rearward in a straight line or in an L shape. The second connection portions34band36beach include a bolt insertion hole100extending therethrough in the vertical direction, which is the plate thickness direction. Also, the pair of bus bars34and36are respectively provided with extension portions102that extend away from each other from the bottom end portions of the first connection portions34aand36a. In Embodiment 1, of the pair of bus bars34and36, the bus bar34is connected to the connection portion32aon the positive side of the relay16, and the bus bar36is connected to the connection portion32bon the negative side of the relay16. Assembly Process of Circuit Structure10 Next, an example of an assembly process of the circuit structure10will be described. The assembly process of the circuit structure10is not limited by the following description. First, the lower case24and the upper case26constituting the base member28are prepared. Then, the bus bar29connecting the relays16and the pre-charge circuit22and the bus bar30that connects the interior of the pre-charge circuit22are disposed and housed in the lower case24from above. Further, the sealing rubber50is disposed and housed in the sealing rubber housing recess48. Next, the upper case26is placed, from above, onto the lower case24configured as described above, and bolts (not shown) are passed through the bolt insertion holes62provided in four corners of the upper case26and fastened to the screw holes37of the lower case24. Accordingly, the lower case24and the upper case26are attached to each other, thus ensuring insulation against other members external to the bus bars29and30. In a state where the lower case24and the upper case26are attached to each other, the leg portions94of the two relays16are placed on the corresponding relay fixing portions56exposed to the outside from the relay fixing portion open windows80in the upper case26and fixed thereto using bolts. Then, the bus bars34and36are respectively attached to the two relays16. More specifically, the first connection portions34aand36aof the bus bars34and36are placed on the front side of the connection portions32aand32bof the relays16, respectively. The second connection portions34band36bof the bus bars34and36are respectively placed on the bus bar fixing portions52of the lower case24that are exposed to the outside from the bus bar fixing portion open windows78. At the same time, the extension portions102of the bus bars34and36are respectively press-fitted into the bus bar housing grooves74aand74bprovided in the lid portions64aand64bof the upper case26. Lastly, the first connection portions34aand36aof the bus bars34and36are bolted and thus thermally and electrically connected to the connection portions32aand32bof the relays16, respectively. Accordingly, the second connection portions34band36bof the bus bars34and36are co-fastened with the bus bar29, on each of the bus bar fixing portions52of the lower case24, and the circuit structure10of the present embodiment is complete. The circuit structure10of the present embodiment configured in this manner is installed at a predetermined position of a vehicle and used with hoses for supplying a coolant attached to the pair of coolant input/output portions86of the upper case26via the hose joints88. In other words, one end portion of each of the pair of coolant input/output portions86is connected to the later-described coolant flow paths104, and the other end portions are connected to an external coolant supply path (not shown). In the present embodiment, by using a coolant that can be used in a vehicle such as radiator fluid, a coolant can be easily supplied to the coolant flow paths104via the pair of coolant input/output portions86. As shown inFIGS.1,5, and6, for example, in the circuit structure10thus configured, the lid portions64aand64band the region A of the upper wall58that form the upper passage wall portion are attached to and cover, from above, the lower passage wall portion42constituted by the wall portions of the grooves38aand38band wall portion of the linking groove40. At this time, as a result of the sealing rubber50housed in the sealing rubber housing recess48being compressed and brought into close contact with the sealing rubber housing recess48and the upper wall58of the upper case26, the lower passage wall portion42and the lid portions64aand64bof the upper case26constituting the upper passage wall portion are linked in a liquid-tight manner. The coolant flow paths104are formed by including the lower passage wall portion42and the lid portions64aand64bconstituting the upper passage wall portion that are linked in a liquid-tight manner. Also, the upper passage wall portion includes the protrusion portions70aand70bthat protrude from the lid portions64aand64bof the upper case26. The protrusion portions70aand70bprotrude into the grooves38aand38bthrough which the coolant flows and that are demarcated by the lower passage wall portion42, and divide the coolant flow paths104into two in the width direction as a result of the protruding end portions thereof coming into contact with the bottom surfaces of the grooves38aand38b. On the other hand, the region A of the upper wall58of the upper case26is attached to and covers, from above, the lower passage wall portion42that is constituted by the wall portion of the linking groove40that links the grooves38aand38b. In this case as well, as a result of the sealing rubber50housed in the sealing rubber housing recess48being compressed and brought into close contact with the sealing rubber housing recess48and the region A of the upper wall58of the upper case26, the lower passage wall portion42and the region A of the upper wall58of the upper case26are linked in a liquid-tight manner. A coolant flow path linking portion106is formed by including the lower passage wall portion42and the region A of the upper wall58of the upper case26that are linked in a liquid-tight manner The protrusion portion76provided in the region A of the upper wall58of the upper case26protrudes into the linking groove40through which the coolant flows and that is demarcated by the lower passage wall portion42, and divides the coolant flow path linking portion106into two in the left-right direction as a result of the protruding end portion thereof coming into contact with the bottom surface of the linking groove40(seeFIG.6). As a result of the above, as shown inFIG.7, for example, a coolant flow path108from which coolant that has entered from one of the pair of coolant input/output portions86exits through the other of the pair of coolant input/output portions86is formed by the coolant flow paths104and the coolant flow path linking portion106that have been divided into two. Accordingly, the coolant can flow smoothly, and thus the base member28near the coolant flow paths104and the coolant flow path linking portion106can be efficiently cooled by the coolant. Thus, the circuit structure10includes the coolant flow paths104and the coolant flow path linking portion106that allow a coolant to flow inside the base member28. As a result of the extension portions102of the bus bars34and36press-fitted into the bus bar housing grooves74aand74bof the protrusion portions70aand70bbeing in thermal contact with the coolant flow paths104via the protruding portions70aand70b, the bus bars34and36can also be efficiently cooled. Here, to facilitate comprehension, the coolant flow path108is shown with an imaginary line. The circuit structure10of the present disclosure with the above-described structure includes the coolant flow paths104that allow a coolant to flow inside the base member28. The extension portions102of the bus bars34and36are press-fitted into the bus bar housing grooves74aand74bof the protruding portions70aand70bprotruding into the grooves38aand38bthat constitute the coolant flow paths104, and the bus bars34and36come into thermal contact with the coolant flow paths104via the protruding portions70aand70b. Accordingly, the extension portions102of the bus bars34and36to which heat from the relays16, which are heat generating components, is transferred to via the pair of connection portions32aand32bcan be brought into thermal contact with the coolant flow paths104via the protruding portions70aand70band efficiently cooled. Thus, dissipation of heat from the relays16, which are heat generating components, can be more reliably promoted with a shorter heat transfer path in comparison to a conventional structure, and thus the heat dissipating properties of the circuit structure10itself can be improved. Furthermore, the bus bars34and36are cooled by coolant that flows through the coolant flow paths104, and thus a heat dissipation effect and a cooling effect can be improved in comparison with a conventional structure when the temperature of a chassis or a housing itself that is in thermal contact with the bus bars34and36reaches high temperatures exceeding 70° C. Also, the extension portions102of the bus bars34and36are fixed by being press-fitted into the bus bar housing grooves74aand74bof the protrusion portions70aand70b, and thus the bus bars34and36can be more reliably and stably brought into thermal contact with the coolant flow paths104. Therefore, the heat dissipating properties of the circuit structure10of the present disclosure can be advantageously improved. Furthermore, by using a simple structure in which the sealing rubber50is housed in the sealing rubber housing recess48provided in the lower passage wall portion42, and compressing the sealing rubber50using the lid portions64aand64band the region A constituting the upper passage wall portion, the lower passage wall portion42and the upper passage wall portion can be linked in a space-efficient and liquid-tight manner. Also, by housing the sealing rubber50in the sealing rubber housing recess48, the holding properties and the positioning properties of the sealing rubber50are ensured, and the attachment operation is made easier. OTHER EMBODIMENTS The technique disclosed in the present description is not limited to the embodiment described based on the description above and the drawings, and embodiments such as those described below are also included in the technical scope of the technique disclosed in the present description. (1) In the above embodiment, by press-fitting the extension portions102of the bus bars34and36into the bus bar housing groove portions74aand74bof the protrusion portions70aand70bthat protrude into the grooves38aand38bconstituting the coolant flow paths104, the bus bars34and36are brought into thermal contact with the coolant flow paths104via the protrusion portions70aand70b, but the present invention is not limited to this. Thermal contact between the bus bars34and36and the coolant flow paths104can be realized with a suitable structure in which, for example, the bus bars34and36are arranged in the surrounding region of the coolant flow paths104, and the bus bars34and36are brought into contact with the lower passage wall portion42and the lid portions64aand64bthat constitute the coolant flow paths104. (2) In the above embodiment, the bus bars34and36are used as conductive members, for example, but the present invention is not limited to this, and the bus bars may simply be used for heat dissipation as long as they are connected to connection portions of heat generating components. (3) In the above embodiment, the extension portions102of the bus bars34and36are press-fitted into the bus bar housing grooves74aand74bof the protrusion portions70aand70bthat protrude into the grooves38aand38bconstituting the coolant flow paths104, but the present invention is not limited to this. Portions of the bus bars34and36may be embedded in the lower passage wall portion42or the lid portions64aand64bthat constitute the upper passage wall portion through insert molding or the like. (4) In the circuit structure10according to the present disclosure, the lower passage wall portion42and the lid portions64aand64bconstituting the upper passage wall portion are all groove shaped, but there is no limitation to this. The upper passage wall portion may be formed by the region A of the flat plate-shaped upper wall58as is the case with the coolant flow path linking portion106, and the shapes of the lower passage wall portion, the upper passage wall portion, and the coolant flow path can be set as appropriate. (5) In the circuit structure10according to the present disclosure, the sealing rubber housing recess48is provided on the lower case24side, but the present invention is not limited to this, and the sealing rubber housing recess48may be provided on the upper case26, or provided on both the lower case24and the upper case26. LIST OF REFERENCE NUMERALS 10Circuit structure10aCircuit structure10bCircuit structure12Power supply14Load16Relay (heat generating component)18Pre-charge resistor20Pre-charge relay22Pre-charge circuit24Lower case26Upper case28Base member29Bus bar30Bus bar32a,32bConnection portion34Bus bar34aFirst connection portion34bSecond connection portion36Bus bar36aFirst connection portion36bSecond connection portion37Screw hole38a,38bGroove40Linking groove42Lower passage wall portion44Dividing wall portion46Recessed portion48Sealing rubber housing recess50Sealing rubber52Bus bar fixing portion54Bolt insertion hole56Relay fixing portion58Upper wall60Peripheral wall62Bolt insertion hole64a,64bLid portion66Lower surface68Bottom surface70a,70bProtruding portion72a,72bUpper surface74a,74bBus bar housing groove76Protruding portion78Bus bar fixing portion open window80Relay fixing portion open window82Pre-charge resistor installation portion84Pre-charge relay installation portion86Coolant input/output portion88Hose joint90Relay body92Bolt insertion hole94Leg portion96Bolt insertion hole98Bolt insertion hole100Bolt insertion hole102Extension portion104Coolant flow path106Coolant flow path linking portion108Coolant flow path | 33,188 |
11943903 | DETAILED DESCRIPTION FIG.1depicts an electronics (e.g., capacitor and power module) system for an electrically-powered vehicle100. The capacitor and power module system100may include a cooling mechanism or circuits, such as a fluid circuits that transfer waste heat (e.g., heat generated while in operation) from the system100to a coolant associated with the fluid circuits and transfer the fluid to a radiator, heat exchanger, or other engine components, as described herein. In one embodiment, the system100includes a capacitor housing102, capacitor104(such as, e.g., a DC-link capacitor), power module106, connectors108, upper manifolds110and111, and electrically conductive traces112and113. The capacitor housing102may hold, support, enclose, and/or otherwise contain the capacitor104. The capacitor housing102may be constructed substantially of plastic, but could also be made from any other suitable material including metals, alloys, and/or combinations thereof. As used herein, the phrase “being formed substantially of plastic” may be construed herein as including, for example, greater than 95% of an object's weight as being plastic. The plastic structure of capacitor housing102may be more flexible in terms of its packaging capabilities and mechanical layout. The capacitor housing102may include one or more coolant channels as set forth in further detail below. These coolant channels may also be referred to as or considered a part of fluid circuits. In some embodiments, the capacitor housing102may be configured to route coolant through the coolant channels in order to cool the capacitor and power module system100before, during, and/or after use. The capacitor housing102may include a bottom face114and a top face116that may be substantially parallel to the bottom face114, although other suitable configurations, e.g., offset or non-parallel surfaces are contemplated. The capacitor housing102may also contain at least one side surface connecting the bottom face114and top face116. In one embodiment, the capacitor housing102may have one or more, e.g., two upper manifolds110and111that are attached to the top face116. In one embodiment, upper manifolds110and111may be attached to the top face by ultra-sonic welding, also known as vibration welding. The two upper manifolds110and111may be mirror images of each other about the y axis. When an upper manifold110/111is attached to the top face116, these components together may define a volume that forms a part of the cooling system and channels mentioned herein. The upper manifolds110and111, when attached to the top face, may include a outlet148and inlet150that are in fluid connection with the coolant channels134and135(shown inFIGS.4and7) of the capacitor housing102. In one embodiment, the power module106is located on the top face116of the capacitor housing102, and its weight is structurally supported by capacitor housing102itself. Power module106may include, e.g., an 800-Volt Silicon Carbide Inverter for electrified vehicles, although other suitable structures also are contemplated. The power module may include one or more silicon carbide (SiC)-based power switches that deliver relatively high power densities and efficiencies needed to extent battery range and performance. The power module106may contain circuitry and components that are configured to convert DC current from the electric vehicle battery to AC current, which can be utilized within the electric motor that drives the propulsion system. The power module105may be installed on a power board assembly. The power module105assembly may include one or more power switches (e.g., six), one or more (e.g., two) heatsinks or cooling jackets, and mechanical components to ensure the mechanical integrity of the power module assembly. Power module105may contain an array of electronic packages and input/output (I/O) devices disposed on a circuit board. The capacitor and power module system100may include a set of electrically conductive traces112and113that connect the capacitor104to the power module106, and allow current to travel from one to the other. Each heatsink may include multiple components (e.g., three in total). The heatsink material may be selected based on the required thermal performance needed to cool the power switches. In some embodiments, the heatsinks may be similar to a radiator used in an internal combustion engine The power module106may be structurally connected to the capacitor housing102. In one embodiment, the power module106is stacked or positioned on top of the top face116of the capacitor housing102(with respect to gravity/the ground). In this way, the capacitor housing102provides structural support for the power module106. Further, the power module106and capacitor housing102may be connected in various ways, such as through screws, welding, or any other suitable mechanism. In one embodiment, connectors108may be used to attach the power module106to the capacitor housing102. In one embodiment, the connectors108are embedded within and/or otherwise extend through the top face116of the capacitor housing102. The connectors108may allow the power module106to attach to the capacitor housing102. The power module106may have corresponding recesses that receives or clips into connectors108. Arranging the power module106on top of the capacitor housing102, so that power module106is supported by capacitor housing102may help alleviate a vertical packaging constraint that occurs when the capacitor housing is mounted above the power module. The system's improved cooling may require less power to pump coolant through the system, thus increasing the potential mileage of the overall engine. The problem of rooting the coolant inside the housing by using complex casting designs, machining, and Friction Stir welded elements is solved by using the plastic structure of capacitor housing102to perform the routing. FIG.2depicts a cross sectional view of the capacitor and power module system (e.g., power inverter)100, with the electrical power schematic overlaid onto the figure. A housing casting (or inverter housing)120may be configured to at least partially receive the capacitor and power module system100for the electronically powered vehicle. The housing casting120may be configured to directly attach to a frame of a vehicle (not shown). The capacitor housing102may, in one embodiment, be physically and/or fluidically connected to the housing casting120. The housing casting120may be constructed substantially of metal, but could also be made from any other suitable material including plastic, alloys, and/or combinations thereof. As used herein, the phrase being formed/made “substantially of metal may be defined as including over 95% metal by weight. The housing casting may be configured to provide one or more coolant channels inlets and outlets as set forth in further detail below. In one embodiment, a fluid or coolant does not directly contact any surface of the housing casting120. Further, the housing casting120may include a bottom surface306, wheel well240, wall302, and wall300. The wheel well240may be shaped to follow the curvature of the wheel. Further, the walls of housing casting120may define a cavity308which houses the capacitor and power module100. The housing casting120may at least partially enclose the capacitor housing102and provide structural support to capacitor housing102. The capacitor housing102may be mounted to the housing casting120and connected in various ways, such as through screws or any other suitable mechanisms. A printed circuit board122is shown inFIG.2having electrical circuitry, according to one embodiment. The printed circuit board122is located on top of the power module106(with respect to gravity/the ground). The circuit board122may include a substrate made of a low temperature co-fired ceramic (LTCC), an organic material, a metal such as stainless steel or any other suitable material. The circuit board122may include electrical circuitry formed on the top side surface as shown and/or bottom side surface, as well as between laminated intermediate layers of the circuit board122. The circuit board122may further be configured with electrical circuitry in the form of surface mount components mounted on the circuit board, such as resistors, capacitors, diodes, transistors (e.g., FETs and IGBTs), and other semiconductor chips. The circuit board122may also have gate drivers and high voltage and low voltage flyback transformers. The gate voltage and transformers may work together help drive the IGBTs. The capacitor104includes an input terminal124and an output terminal126. The input of capacitor104may be coupled to a DC/DC boost converter located within the power module106and the output is coupled to a DC/AC output inverter located within the power module106. The connections are coupled through traces112and113. As set forth above, the capacitor104or capacitor housing102may be used as a structural attachment support/attachment area for the power module106and the printed circuit board122. Thus, printed circuit board122, power module106, and capacitor104may form a stacked structure. By stacking the capacitor104, power module106, and printed circuit board122, the system has improved packaging within the housing casting120. The following description will make reference toFIGS.3-7. In one embodiment, the housing casting120contains two openings146and147. The cross sectional view illustrates only opening146. The openings146and147allow coolant to flow in one opening146, through the capacitor system100, and out the second opening147. Openings146and147may be the only portions of the casting housing through which coolant is configured to flow. The openings may be in fluid communications with a heat exchanger or other engine components prior. The capacitor housing102also includes lower manifolds132and133, coolant channels134and135, and upper manifolds110and111, which allow coolant to flow through the capacitor housing102. Coolant channels134and134may also be referred to as side channels.FIG.3provides a cross sectional view that depicts a single lower manifold133, a single coolant channel134, and a single upper manifold111. The upper manifolds110and111are attached the top face116and the lower manifolds132and133are attached to bottom face114and may abut the housing casting120. The lower manifolds132and133contain openings128and129in the lower manifold and are in fluid communication with openings146and147in the capacitor housing. The connection may contain lower seals130to prevent leakage. When the capacitor and power module100is received by the housing casting120, a portion of the openings128and129of the lower manifolds133and132may extend through the corresponding openings146and147in the housing casting120, The seals130may include O-rings, gaskets, resin, fiber, and/or structural barriers that block any exit paths out of thermal interfaces. In some embodiments, a portion of the coolant channel134may have a cylindrical shape within the capacitor housing102, although this shape and structure is not limiting. For example, rectangular and other shaped channels also are contemplated. By integrating coolant channels through the capacitor housing102(as opposed to through casting120), the dc-link capacitor cooling method is greatly simplified. FIG.4displays one embodiment of the capacitor housing102that further depicts the coolant channels for the capacitor housing102and power module106.FIG.4displays an opening inlet142, which may receive coolant from lower manifold133(shown inFIG.7-9). The opening inlet142can be in fluid communication with the first coolant channel134. Further the system may contain upper manifolds111that is in fluid communication with coolant channel134. In one embodiment, the upper manifolds110and111include upper seal140located at distal ends of the upper manifolds. The upper seal140may prevent leakage when coolant leaves the capacitor housing102through upper manifold111and enter the power module106. The power module106may contain one or more coolant channels145(including, e.g., two or more parallel coolant channels extending therethrough) that may allow for coolant to flow through the power module106. The system100further includes a second upper seal140that is located at the connection of the power module106with a second upper manifold110and may prevent leakage. The upper manifold110may be in fluid communication with a second coolant channel135. The coolant channel135may have an outlet144that is in fluid communication with a lower manifold132(shown inFIG.7-9). The power module106and printed circuit board122are both located on top, from a gravitational perspective, of the capacitor housing102. In one embodiment, neither the power module106nor the printed circuit board122are directly mounted to the housing casting120. FIG.5illustrates an exploded view of the printed circuit board122, power module106and capacitor104. The overall stacked configuration depicted inFIG.5has a more favorable center of gravity, which may lead to less vibrational stress on leads of the inverter. By lower the vibrational stress, this may allow for the inverter's life to be extended. FIG.6displays a perspective view of the housing casting120. In one embodiment, the housing casting120contains opening146and opening147extending through a bottom surface. The openings of146and147in the capacitor housing correspond to openings in the lower manifolds132and133respectively and may be fluidly attached. Lower seals130may be located at the connections to prevent leakage. In some embodiments, casting housing120does not include complex channels for coolant (or does not include any channels/conduit/structure through which coolant will flow). For example, in some embodiments, coolant travels through a casting housing120only through one of opening inlet128or opening outlet129. The coolant may never directly contact any surface of the casting surface120. Further, in one embodiment, the housing casting120does not include any friction stir welded elements. In some embodiments, housing casting120may be of unitary construction. Further, the housing casting120contains the capacitor and power module100within cavity308. Casting housing120may have additional holes in the frame utilized for connecting the casting housing to the vehicle frame. FIG.7andFIG.8display bottom and top perspective views of one embodiment of the capacitor housing102. The capacitor housing includes a pair of lower manifolds132and133on the bottom face114. The lower manifolds132and133may be attached to the bottom face114through ultra-sonic welding, also known as vibration welding. The lower manifolds132and133may allow coolant to flow through them as set forth in greater detail below. The lower manifolds may be identical to one another, may be mirror images of one another, may be sized/shaped differently than one another, or may be related to one another in a different manner. The capacitor housing102may also include coolant channels134and135which contact respective coolant inlet150and coolant outlet148. Further, the coolant inlet150and outlet148may extend above the top face116as depicted inFIG.8, however other configurations may have the inlet150and outlet148level with top face116or even below the top face116. The coolant channels134and135may be hollow and allow for fluid to flow through them. Further, this embodiment depicts lower seals130which may prevent leakage between the lower manifolds and an outside coolant source and sink (not shown). FIG.8displays the capacitor housing102ofFIG.7from a top perspective view. The additional perspective depicts capacitor housing seals152, which may be used to prevent leakage from the coolant channels to upper manifolds110and111. The seals152may alternatively include O-rings, gaskets, resin, fiber, and/or structural barriers that block any exit paths out of thermal interfaces. FIG.9displays the capacitor housing102ofFIG.7andFIG.8from an exploded bottom perspective view. The capacitor housing102may include a groove or recess153on the bottom face114that correspond to the outline of the lower manifolds132and133. The groove or recess153may be referred to as a manifold recess. The indentation153may have a shape that corresponds to the shape of a protrusion on lower manifolds132and133. The lower manifolds132and133may be attached to the bottom face around or in the indentations. FIG.10displays an exploded perspective view of another embodiment of capacitor housing102which includes a pair of lower manifolds132and133and upper manifolds110and111that are attached to the capacitor housing102. In this embodiment, the lower manifolds132and133and upper manifolds110and111may be mirror images of one another. Each upper manifold110and111may include an opening165, wherein both openings165are fluidically separated in the absence of an intermediate conduit (e.g., in the absence of power module106). The capacitor housing102may also include one or more connectors108, which may allow for the power module to physically attach to the capacitor housing. FIG.11displays a side cross-sectional view of the capacitor housing102that depicts the lower manifold132, lower seal130and a coolant channel134. The coolant channel134is located within the capacitor housing102and defined by a cylindrical or otherwise suitably shaped surface. A proximal end of the coolant channel134, outlet144, may attach and be in fluid communication to the proximal end of the lower manifold132. FIG.12displays a cross sectional view of a lower manifold132and lower seal130. The lower manifold is depicted as attached to the bottom face114of the capacitor housing102. The bottom face114may have a groove or recess153that receives the lower manifold132. In particular, lower manifold132may have a protrusion/extension154that is received by a matching groove or recess153within the bottom face114. The lower manifold132may have a groove or recess156that receives the lower manifold seal130. The lower manifold seal130may be ovular in shape, but could be any other suitable shape such as rectangular or any shapes that corresponds to the shape of opening inlet128or opening outlet129. The system also contains an opening inlet128which may be any of various shaped openings in the lower manifold. The bottom face114, lower manifold walls155, and manifold bottom158create a lower manifold cavity157. The opening inlet128allows for fluid communication from outside the lower manifold132and the lower manifold cavity157. FIG.13Adepicts a perspective view of a lower manifold132or133. The lower manifold depicts a lower manifold cavity157, which is encompassed by lower manifold walls155, manifold bottom158, and a bottom face114of capacitor (shown inFIG.7). The lower manifold cavity157is in fluid connection with opening inlet128. The cavity157may also be in fluid connection with inlet142or outlet144from capacitor housing102(shown inFIG.4) when attached to the bottom face114of the capacitor housing102. A flange161, may extend circumferentially around the entirety of the cavity157. Further, a extension154wraps around an entire upper face159of the lower manifold132and extends from the flange161. The manifold bottom158may be shaped in an “L” like formation containing two sections, an elongated portion160and a widened portion162(shown inFIG.13A). FIG.13B-13Cdepicts perspective views of an upper manifold110or111. The upper manifold110and111depicts an upper manifold cavity176, which is encompassed by upper manifold walls178, manifold top180, and a top face116of capacitor (shown inFIG.7). The upper manifold110and111may have a protrusion170that wraps around the entirety of the lower face174of the upper manifolds110and111. A flange172, follows the entirety of the protrusion on the lower face174. Upper manifolds110and111may be formed of 3 sections: a first portion inlet164, a central portion166, and a straight portion168. The first portion inlet164may include an opening165, that may be in fluid communication with the power module106or other engine components. The connection may include upper seals140(shown inFIG.4). The central portion166may traverse the x/y plane (shown inFIG.10). Straight portion168may be perpendicular to the portion inlet164and be in fluid communication with channels134and135when upper manifold is attached to the top face116of the capacitor housing102through inlet150or outlet148. The housing casting120and capacitor housing102together form an inlet coolant circuit configured to convey coolant toward the capacitor, and an outlet coolant circuit configured to convey coolant away from the capacitor. The inlet coolant circuit may begin at the opening128in lower manifold133, which is located at the opening146of casting housing120. The inlet coolant circuit then includes the lower manifold cavity157, coolant channel134, and cavity176of upper manifold111. The inlet coolant circuit ends at opening165of the upper manifold111. The outlet coolant circuit may begin at opening165of the upper manifold110. The outlet coolant circuit then includes cavity176of upper manifold110, coolant channel135, and lower manifold cavity157. The outlet coolant circuit end at the opening129of lower manifold132. The opening129is located at opening147of casting housing120. In another embodiment, the inlet coolant circuit may be swapped with the outlet coolant circuit and the coolant may flow in the opposite direction. FIG.14illustrates a top view of the printed circuit board122. The printed circuit board122may have electrical circuitry (not shown). The printed circuit board122may include a substrate made of low temperature co-fired ceramic (LTCC), an organic material such as FR4, a metal such as stainless steel or any other suitable material. The circuit board122may include circuitry formed on the top surface and/or bottom surface, as well as between laminated intermediate layers on the circuit board122. The circuit board122may further be configured with electrical circuitry in the form of surface mount components mounted on the circuit board122, such as resistors, capacitor, diodes, transistors (e.g., FETs and IGBTs), and other semiconductor chips. In some embodiments, printed circuit board122does not include any fluid inlet and outlet ports. In other words, in some embodiments, cooling fluid does not travel through printed circuit board122in any capacity. The cutoff within the printed circuit board122, more specifically the gate driver board, are no longer required to route the coolant from the housing to a power module heatsink. The additional board space area may allow for electrical board layout simplification. FIG.15displays a cross sectional view of a first embodiment of a power module106and coolant system. The system may include a power module106stacked or attached to the top of a capacitor104. A coolant channel206may be located in between the capacitor104and power module106. The coolant channel206may be configured to have a channel inlet202and channel outlet204that are in fluid communication with each other via channel206. The channel inlet202and channel outlet204may be in fluid communication with capacitor housing102. The channel inlet202may receive coolant from the upper manifold111or from other engine components. The channel outlet204may disperse coolant into the capacitor housing102through upper manifold110. Alternatively, the channel outlet204may disperse the coolant to a heatsink through alternative engine components. Further, there may be a power module seal200between the coolant channel206and power module106to prevent leakage. The power module106may include an inlet210and outlet212on opposing sides of the power module106. The power module106may be configured to have one or more coolant channels within itself. In this embodiment, the power module has one module coolant channel that is in fluid connection from the inlet210and outlet212. In this embodiment, the capacitor housing102and the cooling system100do not include any heatsink or cold plate. Instead, coolant flows through channel206to remove heat (via conduction) directly from the surfaces of power module106. FIG.16displays a displays a cross sectional view of a second and alternative embodiment of a power module106and coolant system. In this embodiment, the power module may contain two coolant channels, coolant channel223and coolant channel224. In this embodiment, a thermal pad (heat sink/cold plate)226may be located between a coolant channel228and a power module106. Further, the power module106may contain a seal220located at an inlet230into the power module and a seal222at an outlet232. The coolant channel228may be located above capacitor104(not shown). The coolant channel228may be configured to have a channel inlet234and channel outlet236that are in fluid communication with each other. The channel inlet234and channel outlet236may be in fluid communication with capacitor housing102. The channel inlet235may receive coolant from the upper manifold111or from other engine components. The channel outlet204may disperse coolant into the capacitor housing102through upper manifold110. Alternatively, the channel outlet236may disperse the coolant to a heatsink through alternative engine components. The flow of coolant through system100is described as follows. One embodiment of a flow path of coolant for the system may be illustrated with reference toFIGS.3,4and10. Coolant may enter the system through an opening146in the housing casting120and enter the capacitor housing102through opening128. The coolant may be directed from a heat exchanger or other engine components prior to entering the system100. The coolant may then enter a first lower manifold133and travel along cavity157from the widened portion162to the elongated portion160. Next, the coolant exit the lower manifold133and enter a coolant channel134in the capacitor housing at outlet144. The coolant may flow through the channel134and exit the channel at outlet148and flow into the upper manifold111. The fluid may flow through the upper manifold cavity176beginning at the straight portion168, followed by a central portion166, and lastly through a first portion inlet164. The coolant then exits the upper manifold111. After exiting upper manifold111, the fluid may then enter the power module106and proceed to flow through one or more coolant channels through the system. The coolant may then leave the power module106and flow into a second upper manifold110through an opening165in the first portion inlet164, followed by a central portion166, and lastly through a straight portion168. The fluid will proceed to flow into a second coolant channel135at inlet150. Next the fluid will flow through coolant channel135and exit coolant channel135at outlet144and enter a second lower manifold132. The fluid may flow through the cavity157of lower manifold132from elongated portion160to widened portion162and then the lower manifold132out opening129. Coolant exits the system out opening128, flowing out of the housing casting120opening147in the process. The fluid may then proceed to flow through an opening147in the housing casting120and continue to flow to a radiator, heat exchanger, or to further engine components (not shown). Further, the coolant may absorb heat from the system throughout the process. Additionally, in another embodiment, the coolant may flow in the opposite direction of the first embodiment. With respect toFIG.15andFIG.16, a fluid path can be illustrated by drawn arrows. InFIG.15, a fluid may be directed to enter at the channel inlet202. The fluid may have previously traveled through the capacitor housing102. The fluid may proceed to flow through the coolant channel206. The fluid may also enter through inlet210and flow through the power module coolant channel208and exit the power module coolant channel208through outlet212. The coolant following both arrow sets may then exit through a channel outlet204. The fluid may then flow back into the capacitor housing102and or to a heat exchanger or other engine components to be cooled. The fluid may absorb heat from the power module during this process. In one embodiment, the fluid may flow in the opposite direction described herein. InFIG.16, a fluid may be directed to enter at the channel inlet234. The fluid may have previously flown through the capacitor housing102. The fluid may proceed to flow through the coolant channel228. The fluid may also enter through inlet230and flow through the power module coolant channel a223and coolant channel b224and exit through outlet232. The coolant following both arrows may then exit through a channel outlet236. The fluid may then flow back into the capacitor housing102and or to a heat exchanger or other engine components to be cooled. The fluid may absorb heat from the power module and thermal pad during this process. In one embodiment, the fluid may flow in the opposite direction described herein. The multiple embodiments may lead to a power module performance increase due to getter and more efficient cooling. FIG.17depicts a perspective view of the housing casting120. The housing casting may define a cavity308that serves as the base for the capacitor system for an electrically-powered vehicle100(not shown). The housing casting includes a curved section shaped to contact the wheel well240). The capacitor housing102may generally be placed on top of the housing casting120and may be screwed into the housing casting120. The housing casting may not include complex fabrication. Further, the problem of a vertical packaging constraint, is solved by the capacitor and power module system100utilizing the space within the housing casting120more efficiently. | 29,762 |
11943904 | DETAILED DESCRIPTION In the following specification and the claims, reference will be made to a number of terms, which shall be defined to have the following meanings. The singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “substantially,” and “approximately,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. Embodiments of the present disclosure include a thermosyphon cooling system. The cooling system includes a condenser configured to condense a coolant from a vapor state to a liquid state and an evaporator configured to evaporate the coolant from the liquid state to the vapor state. The cooling system further includes a vapor channel fluidly coupled to the condenser and the evaporator and configured to convey the coolant in the vapor state from the evaporator to the condenser, and a liquid channel coupled to the condenser and the evaporator and configured to convey the coolant in the liquid state from the condenser to the evaporator. The coolant may move passively through the cooling system due to convection and gravity. The evaporator defines a reservoir configured to contain a volume of the coolant in the liquid state. A heat generating component is disposed in the reservoir and immersed in the volume of the coolant in the liquid state, so that the heat generating component is cooled by dissipating heat into the coolant. In certain embodiments, the cooling system may include one or more condensers and/or one or more reservoirs. The number of condensers may or may not be the same as the number of reservoirs. In some embodiments, the cooling system may include additional cooling branches to reach additional heat generating components. For example, a branch (sometimes referred to herein as a “direct auxiliary branch”) may channel liquid coolant from the reservoir to a heat generating component to cool the heat generating coolant. Additionally or alternatively, a branch (sometimes referred to herein as an “indirect auxiliary branch”) may utilize a secondary coolant to cool a heat generating component. The secondary coolant may in turn be cooled by being channeled through a heat exchanger located in the reservoir. In certain such embodiments, an active fluid mover, such as a pump or blower, is used to facilitate movement of the coolant through the branch. FIG.1illustrates an example cooling system100(sometimes referred to herein as a “thermosyphon”). Cooling system100includes a condenser102, an evaporator104, a vapor channel106, and a liquid channel108. Condenser102is configured to condense a coolant (e.g., a dielectric fluid) from a vapor state to a liquid state by cooling the coolant, and evaporator104is configured to evaporate the coolant from the liquid state to the vapor state by heating the coolant. Vapor channel106is fluidly coupled to condenser102and evaporator104, and conveys the coolant in the vapor state from evaporator104to condenser102. Liquid channel108is also fluidly coupled to condenser102and evaporator104, and conveys the coolant in the liquid state from condenser102to evaporator104. Accordingly, cooling system100facilitates a transfer of heat from evaporator104to condenser102, where the heat may be dissipated to the surrounding environment. In some embodiments, condenser102is located at a higher elevation than evaporator104, so that the coolant may flow between condenser102and evaporator104due to gravity without the use of active fluid moving devices, such as pumps or fans. In some embodiments, condenser102may further contain air and/or liquid as a secondary fluid to remove the heat from the primary thermosyphon coolant. In some such embodiments, the secondary air and/or liquid, is moved by a pump or blower through condenser102. Alternatively, in certain embodiments, the secondary fluid movement may move without the use of a pump or blower. Evaporator104defines a reservoir110therein, which is fluidly coupled to vapor channel106and liquid channel108. Reservoir110contains a volume of liquid coolant112and a volume of vapor coolant114. One or more heat generating components116are disposed at least partially within reservoir110and immersed in the volume of liquid coolant112. Liquid coolant112may be received in reservoir110from liquid channel108, where liquid coolant112is heated by heat generating components116and transitions to a vapor state (i.e., converts to vapor coolant114), transferring heat from and cooling heat generating components116. In certain embodiments, the coolant has a boiling point in the range of −50 to +100 degrees Celsius at atmospheric pressure and varying pressure ranges. In various embodiment, the coolant may be, but is not limited to, commercial refrigerants, water, DI water, and heat transfer fluids such as R134a, R410a, R245fa, R1233zd(3), R1234yf, 3m NOVEC 649, 3M FC 72, NOVEC 7100, NOVEC 7500. In some embodiments, heat generating components116include IGBTs118, an inductor120, and/or other heat generating high-power electrical and electronic components. IGBTs118and inductor120may form portions of, for example, an inverter or power converter of a battery energy storage system or other power system. By using phase-change cooling, such as that facilitated by evaporator104, IGBTs118, inductor120, and other heat generating components116may be cooled more efficiently, and accordingly may be operated at higher currents, which in turn may reduce the number of heat generating components116needed in a given power system and reduce the overall cost of the power system. FIG.2illustrates another example cooling system200. Similar to cooling system100shown inFIG.1, cooling system200includes condenser102, evaporator104, vapor channel106, liquid channel108, and heat generating components116, which generally function as described with respect toFIG.1. Cooling system200further includes a direct auxiliary branch202and an indirect auxiliary branch204, which are used to cool additional heat generating components116. Direct auxiliary branch202includes a direct auxiliary channel206and a pump208. Direct auxiliary channel206is fluidly coupled at an inlet210and an outlet212to reservoir110of evaporator104, and is configured to receive liquid coolant112from reservoir110at outlet212and return liquid coolant112. Pump208is configured to cause liquid coolant112to move through direct auxiliary channel206from outlet212to inlet210. As liquid coolant112passes heat generating component116, heat is transferred to liquid coolant112to cool heat generating component116. WhileFIG.2illustrates the coolant passing through direct auxiliary channel206as remaining in a single state (i.e., the liquid state), in some embodiments, the coolant passing through direct auxiliary channel206may exist at multiple states. For example, the coolant may evaporate to the vapor state upon being heated by heat generating component116, and may return to the liquid state before being returned to reservoir110through inlet210. In some embodiments, evaporator104and/or direct auxiliary channel206includes flow control devices, such as manual or electromechanical valves and/or orifices, to control the flow within direct auxiliary channel206. Indirect auxiliary branch204includes an indirect auxiliary channel214, a fluid mover216, and a heat exchanger218. Indirect auxiliary channel214is coupled at both ends to heat exchanger218, which is disposed in reservoir110at least partially immersed in liquid coolant112. Indirect auxiliary channel214is configured to convey a secondary coolant, separate from the coolant present in reservoir110, in a loop between one or more heat generating components116and heat exchanger218. Fluid mover216is configured to cause the secondary coolant to move through indirect auxiliary channel214past heat generating component116and on through heat exchanger218. Fluid mover216may be, for example, a pump or a blower, depending on the state of the secondary coolant moving through fluid mover216. When the secondary coolant passes heat generating component116, heat is transferred to the second coolant to cool heat generating component116. When the secondary coolant passes through heat exchanger218, heat is transferred to liquid coolant112to cool the second coolant. In some embodiments, such as that shown inFIG.2, heat exchanger218may be shaped as a coil. Alternatively, heat exchanger218may be any suitable shape that enables sufficient heat to be exchanged from the second coolant to liquid coolant112, and may be disposed outside of reservoir110in a location where heat may be transferred to liquid coolant112. The secondary coolant may be a single state (e.g., always liquid or always vapor), or may have multiple states. For example, the secondary coolant may evaporate to the vapor state upon being heated by heat generating component116and condense to the liquid state upon being cooled by liquid coolant112. In certain embodiments, to reduce an overall system pressure drop, each loop of cooling system that is a thermosyphon (i.e., that relies on convective fluid movement) has one or more liquid bridges220. For example, a liquid bridge220is fluidly coupled between vapor channel106and liquid channel108. Liquid bridge220serves to return any entrained liquid in vapor channel106back to liquid channel108by-passing condenser102. In some embodiments, there is more than one liquid bridge220depending on the number of condensers102and of evaporators104present in cooling system100. FIGS.3A and3Billustrate different configurations for positioning heat generating components116within reservoir110of evaporator104. As shown inFIG.3A, in some embodiments, heat generating component116may be disposed entirely within liquid coolant112contained in reservoir110. In some such embodiments, impingement jets302are also positioned within liquid coolant112contained in reservoir110. Impingement jets302are configured to direct a local flow of liquid coolant112towards heat generating component116to increase the transfer of heat from heat generating component116to liquid coolant112and enable removal of vapor, if any, away from the heat generating component116. In certain embodiments, impingement jets302are passive and rely on, for example, convection to generate fluid movement towards heat generating component116. Alternatively, impingement jets302may include an active fluid moving device. In some embodiments, a surface304(e.g., a base plate and/or mounting plate surface) of heat generating component116may include microchannels that guide movement of liquid coolant112across surface304to increase transfer of heat from heat generating component116to liquid coolant112. For embodiments in which impingement jets302are present, impingement jets302may be aligned such that the fluid movement generated by impingement jets302causes further fluid movement through the microchannels of surface304. Surface304may include additional nucleating boiling enhancement features to increase critical heat flux and increase heat transfer due to boiling. For example, in some embodiments, surface304includes additive or conventionally fabricated mesh structures that act as nucleation sites, pitted surfaces, surfaces with drilled holes, and finned surfaces of different shapes and spacing. For example, such fins may be aligned and/or staggered, may be straight or wavy, and may have different shapes (e.g., parabolic, airfoil, pins, and/or studs). Such structures may be monolithic as part of surface304or separately fastened (e.g., glued, etc.) to be thermally and mechanically coupled to surface304. As shown inFIG.3B, in certain embodiments, heat generating component116is partially disposed in reservoir110of evaporator104. In such embodiments, a heated surface (e.g., surface304) is immersed in liquid coolant112, while other portions of heat generating component116are disposed externally to reservoir110. In some implementations, immersing only certain portions of heat generating component116may reduce potential compatibility issues when incorporating preexisting components into cooling systems100and/or200. As shown inFIG.4, in some embodiments, in which heat generating component116is immersed fully or partially in the reservoir110containing liquid coolant112, heat generating component116does not have a traditional packaging, so that heat transfer may be improved. For example, traditional IGBT power modules have a multi-layer construction where heat generated in the active layer (e.g., a Silicon layer) must transfer through multiple packaging materials to reach a heat sink and/or coolant. As shown inFIG.4, in some embodiments, heat generating component includes a substrate402and one or more active components404(e.g., diodes or integrated circuit (IC) chips) disposed on substrate402and in direct contact with liquid coolant112. In such embodiments, heat generating components116include no case, epoxy encapsulation, baseplate, or other such packaging, such that the active components of heat generating component116is exposed directly to the coolant, improving heat transfer and reducing a cost of heat generating component116. FIG.5is a flowchart illustrating an example method500for assembling a cooling system (such as cooling system100shown inFIG.1). Method500includes fluidly coupling502a vapor channel (such as vapor channel106) to a condenser (such as condenser102) configured to condense a coolant from a vapor state to a liquid state and to an evaporator (such as evaporator104) configured to evaporate the coolant from the liquid state to the vapor state, the evaporator defining a reservoir (such as reservoir110) configured to contain a volume of the coolant in the liquid state. The vapor channel is configured to convey the coolant in the vapor state from the evaporator to the condenser. Method500further includes fluidly coupling504a liquid channel (such as liquid channel108) to the condenser and the evaporator, the liquid channel configured to convey the coolant in the liquid state from the condenser to the evaporator. Method500further includes positioning506a heat generating component (such as heat generating component116) in the reservoir and immersed in the volume of the coolant in the liquid state. The heat generating component is configured to dissipate heat into the coolant. In some embodiments, method500further includes fluidly coupling a direct auxiliary channel (such as direct auxiliary channel206) to the reservoir at an inlet (such as inlet210) and an outlet (such as outlet212). The direct auxiliary channel is configured to convey the coolant from the outlet to the inlet. In such embodiments, method500further includes positioning a second heat generating component to dissipate heat into the coolant moving through the direct auxiliary channel. In certain such embodiments, a pump (such as pump208) is configured to move the coolant through the direct auxiliary channel. In some embodiments, method500further includes positioning a heat exchanger (such as heat exchanger218) in the reservoir. The heat exchanger defines a fluid path and is configured to transfer heat from a secondary coolant moving through the fluid path to the coolant in the reservoir. In such embodiments, method500further includes fluidly coupling an indirect auxiliary channel (such as indirect auxiliary channel214) to each end of the fluid path of the heat exchanger. The indirect auxiliary channel is configured to convey the secondary coolant. In such embodiments, method500further includes positioning a second heat generating component to dissipate heat into the secondary coolant moving through the indirect auxiliary channel. In certain such embodiments, a fluid moving device (such as fluid mover216) configured to move the secondary coolant through the indirect auxiliary channel. In some such embodiments, the heat exchanger is configured to cause the secondary coolant to change in state from a vapor to a liquid. In certain embodiments, method500further includes positioning an impingement jet (such as impingement jet302) in the reservoir. The impingement jet is configured to direct fluid movement of the coolant towards the heat generating component. In some embodiments, method500further includes forming microchannels on a surface (such as surface304) of the heat generating component. The microchannels are configured to increase a transfer of heat from the heat generating component to the coolant. In certain embodiments, the heat generating component is entirely disposed within the reservoir of the evaporator immersed in the coolant. In some embodiments, the heat generating component is partially disposed in the reservoir of the evaporator immersed in the coolant. In certain embodiments, method500further includes fluidly coupling a liquid bridge (such as liquid bridge220) between the vapor channel and the liquid channel. In some embodiments, the heat generating component includes one or more active components disposed in direct contact with the coolant. An example technical effect of the methods, systems, and apparatus described herein includes at least one of: (a) cooling a heat generating component by immersing the heat generating component within a coolant reservoir of an evaporator of a thermosyphon cooling system; (b) cooling a heat generating component by providing an channel in thermal communication with an evaporator of a thermosyphon cooling system configured to channel fluid to transfer heat from the heat generating component to the evaporator; and (c) reducing a number of heat generating components needed to implement a power system by cooling the heat generating components using a thermosyphon loop. Example embodiments of a cooling system are provided herein. The systems and methods of operating and manufacturing such systems and devices are not limited to the specific embodiments described herein, but rather, components of systems and/or steps of the methods may be utilized independently and separately from other components and/or steps described herein. For example, the methods may also be used in combination with other electronic systems, and are not limited to practice with only the electronic systems, and methods as described herein. Rather, the example embodiments can be implemented and utilized in connection with many other electronic systems. Some embodiments involve the use of one or more electronic or computing devices. Such devices typically include a processor, processing device, or controller, such as a general purpose central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, a reduced instruction set computer (RISC) processor, an application specific integrated circuit (ASIC), a programmable logic circuit (PLC), a field programmable gate array (FPGA), a digital signal processing (DSP) device, and/or any other circuit or processing device capable of executing the functions described herein. The methods described herein may be encoded as executable instructions embodied in a computer readable medium, including, without limitation, a storage device and/or a memory device. Such instructions, when executed by a processing device, cause the processing device to perform at least a portion of the methods described herein. The above embodiments are examples only, and thus are not intended to limit in any way the definition and/or meaning of the term processor and processing device. Although specific features of various embodiments of the disclosure may be shown in some drawings and not in others, this is for convenience only. In accordance with the principles of the disclosure, any feature of a drawing may be referenced and/or claimed in combination with any feature of any other drawing. This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims. | 21,125 |
11943905 | DETAILED DESCRIPTION The present disclosure relates generally to systems and methods for electromagnetic interference (EMI) or radio frequency (RF) shielding. More particularly, the EMI shielding devices described herein are configured to provide EMI or RF shielding for a general-purpose computing device, a specialized video game console or other specialized computing device, and other electronic devices such as electric motors. In some embodiments, EMI shielding devices according to the present disclosure are configured to allow rotation of a rotor relative to and/or through an aperture in a device housing. The rotor may be a fan rotor, such as an axial fan or transverse blower in a personal computer or video game console, or a shaft rotor, such as a drive shaft of an electric motor that transfers torque through a housing or chassis. In some embodiments, EMI shielding devices according to the present disclosure allow rotation of the rotor relative to the stator while limiting and/or preventing transmission of EMI into or out of the aperture in the device housing. In some embodiments, an EMI shielding device according to the present disclosure is positioned proximate a fan to receive heat from a computing component of the electronic device. In some examples, the computing component, such as a processor, system memory, hardware storage device, networking device, etc. may be susceptible to EMI that compromises the performance of the computing component. In other examples, the computing component may generate EMI that adversely affects the performance of other computing components of the electronic device. In some embodiments, an EMI shielding device according to the present disclosure is part of a fan. The fan may move air over, through, or past a thermal management device (such as a fin pack), which receives heat from at least one heat source in the electronic device and transfers the heat to the air. In some embodiments, the heat source is a processor, such as a central processing unit (CPU), a graphical processing unit (GPU); a storage device, such as random-access memory (RAM), other volatile memory, non-volatile memory, or combinations thereof. In some embodiments, the heat source is coupled directly to the thermal management device. In some embodiments, the heat source is thermally connected to the thermal management device with at least one thermally conductive or convective element therebetween. In some examples, the heat source is thermally connected to the thermal management device by a thermal interface material (TIM), such as a thermal paste, sandwiched between a surface of the heat source and a surface of the thermal management device. In some examples, the heat source is thermally connected to the thermal management device by a heat pipe, vapor chamber, heat spreader, or other thermally conductive or convective element that transports heat from a surface of the heat source to a surface of the thermal management device. The thermal management device is thermally connected to the heat source when at least element of the thermal management system is intended to physically connect the thermal management device to the heat source. In other words, a thermal management device that receives heat from the heat source only by ambient air flowing therebetween is not thermally connected, while a thermal management device connected to a heat source by a vapor chamber with a two-phase working fluid moving therein is thermally connected when a surface of the vapor chamber contacts a surface of the heat source and a surface of the thermal management device. In another example, a thermal management device is thermally connected to the heat source when the heat source is in contact with a first TIM, which contacts a surface of a heat pipe, which contacts a second TIM, which contacts a surface of the thermal management device. In some embodiments, an EMI shielding device according to the present disclosure allows airflow through an aperture to reject excess heat to the ambient atmosphere while also limiting and/or preventing EMI from passing through the aperture in the housing proximate the fan. In some embodiments, the EMI shielding device includes a plurality of channels between the rotor and stator. In some embodiments, the channels have a maximum transverse dimension (e.g., width) that is less than a longitudinal dimension (e.g., length) to limit the passage of EMI through the channel. FIG.1is a perspective view of an embodiment of a computing device100. The computing device100may include a first portion102and a second portion104movably connected to one another by a hinge106. In some embodiments, the first portion102of the computing device100may include a display108to present visual information to a user and the second portion104of the computing device100may include one or more input devices110, such as a trackpad, a keyboard, etc., to allow a user to interact with the computing device100. In embodiments in which the computing device is a hybrid computer, the first portion102may include the display108and at least a processor112. The first portion102may further include additional computer components, such as a storage device, system memory, a graphical processing unit, graphics memory, one or more communication devices (such as WIFI, BLUETOOTH, near-field communications), peripheral connection points, etc. In some embodiments, the first portion102may be removable from the hinge106and/or the second portion104. In some embodiments, the computing device100is a specialized computing device, such as a video game console, or a general-purpose desktop tower computer that is connected to an external display and/or audio devices. In such embodiments, the computing device100includes one or more of the computer components, such as a storage device, system memory, a graphical processing unit, graphics memory, one or more communication devices (such as WIFI, BLUETOOTH, near-field communications), peripheral connection points, etc. in a single housing of the computing device100. FIG.2is a detail view of cooling system114of a computing device100described in relation toFIG.1. The computing device100includes a variety of components that generate heat. The heat sources116can be any component of the computing device that generates heat but, particularly, may include a processor112(such as a central processing unit (CPU), a graphical processing unit (GPU), a physics processing unit, or other processors), system memory, video memory, storage devices, networking devices, display devices, input devices, optical drives, peripheral connection ports, or any other components of the computing device100. In some embodiments, the heat from the heat sources116is distributed from a heat source116across a surface by a heat spreader118. In other embodiments, the heat is conducted from the heat sources116toward a cooler region of the computing device100and/or toward an exhaust by a heat transfer element120. In yet other embodiments, the heat is conducted from a heat source116through a cold-plate to a heat transfer element120. The heat transfer element120may be a thermally conductive material, such as copper, silver, or aluminum that conducts heat from a region of higher thermal energy to a region of lower thermal energy. For example, the heat transfer element120will conduct thermal energy from the first end122of the heat transfer element120adjacent the heat sources116toward a cooler second end124of the heat transfer element120near a heat sink to lessen a temperature gradient along the heat transfer element120. In other examples, the heat transfer element120may be a heat pipe that may further aid in transferring thermal energy away from the heat sources116. At the higher temperature (“hot”) interface of a heat pipe a liquid in contact with a thermally conductive solid surface turns into a vapor by absorbing heat from that surface. The vapor then travels along the heat pipe to a lower temperature (“cold”) interface and condenses back into a liquid releasing the latent heat. The liquid then returns to the hot interface through, for example, capillary action, centrifugal force, or gravity, and the cycle repeats. Due to the high heat transfer coefficients for boiling and condensation, vapor cooling system heat pipes are effective thermal conductors. The effective thermal conductivity varies with heat pipe length and can approach 100 kW/(m·K) for long heat pipes, in comparison with approximately 400 W/(m·K) for copper. In some embodiments, the second end124of heat transfer element120is in contact with, in proximity to, or attached to a heat sink, such as a fin pack126. The fin pack126includes or is made of a thermally conductive material to conduct thermal energy from the second end124of the heat transfer element120into the fin pack126. The fin pack126has a plurality of fins, channels, rails, or other structures that increase the surface area of the fin pack126to dissipate the thermal energy. In some embodiments, the thermally conductive material has a thermal conductivity in a range having an upper value, a lower value, or upper and lower values including any of 100 Watts per meter-Kelvin (W/m·K), 125 W/m·K, 150 W/m·K, 175 W/m·K, 200 W/m·K, 250 W/m·K, 300 W/m·K, 400 W/m·K, 450 W/m·K, or any values therebetween. For example, the thermal conductivity may be greater than 100 W/m·K. In other examples, the thermal conductivity may be less than 450 W/m·K. In yet other examples, the thermal conductivity may be between 100 W/m·K and 450 W/m·K. In further examples, the thermal conductivity may be greater than 150 W/m·K. In at least one example, the thermal conductivity may be greater than 250 W/m·K. The cooling system114dissipates the thermal energy through air flowed through or over the fin pack126by a fan128. The fan128may move air flow through one or more channels of the fin pack126such that air absorbs thermal energy from the surfaces of the fin pack126. The dissipation of heat from the fin pack126reduces the temperature of the fin pack126to allow the heat transfer element120to transfer more heat from the heat sources116to the fin pack126. In a conventional computing device100, a Faraday cage130may be positioned around or over at least a portion of the electronic components. For example, the processor112or other electronic components of the computing device100generate EM radiation during operation. The EM radiation emitted by the processor112or other electronic components can interfere with the operation of an external electronic component132. In other examples, an external electronic component132produces EMI that may adversely impact the electronic components inside the Faraday cage130. The Faraday cage130defines an external side (external to the Faraday cage130) and an internal side (internal to the Faraday cage130). The Faraday cage130may include a conductive material to suppress the EM radiation from the processor112or other electronic components internally. The internal conduction of the EM radiation along the Faraday cage shields the EM radiation that may interfere with the operation of the external electronic component(s)132and vice versa. However, a conventional Faraday cage130is inefficient at transferring energy through the Faraday cage130and may cause the heat sources116to increase in temperature by limiting ventilation through the Faraday cage130. In some embodiments, an aperture134is provided in the Faraday cage130to allow air flow through the aperture to exhaust the thermal energy (via warm air) from the heat sources116and the computing device100. In some embodiments, the aperture134has a shaft positioned therethrough to transfer torque, such as produced by an electric motor or received by a generator. In either instance, the aperture134is a potential source of EMI leakage through the Faraday cage130. In some embodiments, an EMI shielding device according to the present disclosure limits and/or prevent EMI leakage through the aperture134by electrically connecting the rotor of the fan128or shaft in the aperture to the stator of the aperture and/or Faraday cage130housing of the computing device100. FIG.3-1is a top view of an EMI shielding device236according to the present disclosure. In some embodiments, the EMI shielding device236includes a rotor238that rotates relative to a stator240. While the embodiment of a rotor238illustrated inFIG.3-1is an axial fan, it should be understood that the rotor238may be other devices or components, as will be described herein. The rotor238is positioned in or proximate to an aperture234in the stator240, and the rotor238rotates relative to the stator240. In some embodiments, such as an axial fan and/or a blower, the aperture234allows airflow through a portion of the fan rotor238. The EMI shielding device236includes an electrical bridge between the rotor238and the stator240. In some embodiments, the electrical bridge includes conductive fibers242that provide an electrically conductive path between the rotor238and the stator240while the rotor238rotates relative to the stator240. The conductive fibers242may be a conductive metal fiber, such as copper, or an electrically conductive non-metal conductive fiber, such as graphite or an electrically conductive polymer. The conductive fibers242, inFIG.3-1are positioned on a proximate surface244of the fan rotor238proximate to a contact surface248of the aperture234in the housing stator240. In some embodiments, the proximate surface244is a radially outermost edge of the fan rotor238relative to the rotational axis246of the fan rotor238. The fan rotor238rotates around the rotational axis246to rotate relative to the housing stator240in which the aperture234is located. In some embodiments, the conductive fibers242are fixed to the fan rotor238. For example, the conductive fibers242are fixed in the embodiment illustrated inFIG.3-1to the proximate surface244(e.g., the radially outermost edge) of the fan rotor238that is proximate the contact surface248of the aperture234. In other embodiments, the conductive fibers242are fixed to the housing stator240. For example, the conductive fibers242may be fixed to the contact surface248of the aperture234that is opposite the proximate surface244of the fan rotor238. In yet other embodiments, the conductive fibers242are fixed to the fan rotor238and the housing stator240. For example, a first plurality of conductive fibers242are fixed to the proximate surface244(e.g., the radially outermost edge) of the fan rotor238that is proximate the contact surface248of the aperture234and a second plurality of conductive fibers242are fixed to the to contact surface248of the aperture, where the first plurality of conductive fibers242are positioned to contact and provide an electrical connection with the second plurality of conductive fibers242as the fan rotor238rotates relative to the housing stator240. The electrical bridge has a conductivity sufficient to allow transmission of electrical current across the electrical bridge to maintain the Faraday-cage effect. In some embodiments, the electrical bridge has a resistivity less than 500 milliohm per linear centimeter around an arc segment of 1 centimeter of the electrical bridge to provide sufficient conductivity. For example, the electrical bridge may have a resistivity less than 400 milliohm per linear centimeter. In other examples, the electrical bridge has a resistivity less than 250 milliohm per linear centimeter around an arc segment of 1 centimeter of the electrical bridge to provide sufficient conductivity. In some embodiments, the proximate surface244of the fan rotor238is continuous around the fan rotor238in the rotational direction around the rotational axis246. In some embodiments, the proximate surface244is an outermost surface of an annular body252around the fan rotor238. For example, the annular body252may be a continuous annulus around the fan blade(s)250of fan rotor238that provides a continuous and electrically conductive surface around the circumference of the fan rotor238. In some embodiments, at least a portion of the EMI leakage occurs in a gap254between the proximate surface244of the rotor238and the contact surface248of the stator240. In the embodiment illustrated inFIG.3-1, the gap254is an annular space between the radially outermost edge of the annular body252and the edge of the aperture234. An EMI shielding device236according to the present disclosure bridges that gap254with an electrical bridge to provide electrical conductivity between the rotor238and stator240, such as the conductive fibers242inFIG.3-1. In some embodiments, electrical bridge (e.g., the conductive fibers242) partitions the gap254into channels256. In some embodiments, the channels256allow airflow therethrough while attenuating EMI that would otherwise interfere with electronic components. FIG.3-2is a side partial cross-sectional view of the EMI shielding device236ofFIG.3-1. The EMI shielding device236includes a plurality of conductive fibers242arranged in rows258that define a plurality of channels256when contacting and providing electrical conductivity between the proximate surface244of the rotor238and the contact surface248of the stator240. The channels256may allow airflow and EMI therethrough. The channels256have a maximum transverse dimension260that is transverse to longitudinal direction of the channels256. For example, in the illustrated embodiment, the rows258and, therefore, the channel(s)256are oriented axially (e.g., substantially parallel to the rotational axis246). In other examples, the channel(s)256may have a longitudinal direction that is oriented at an angle to the rotational axis246of the rotor238. The maximum transverse dimension260in the illustrated embodiment is in the rotational direction between the rows258of conductive fibers242. In other examples, the maximum transverse dimension may be a gap height264between the proximate surface244of the rotor238and the contact surface248of the stator240. The attenuation of EMI by the EMI shielding device236is at least partially related to a ratio of the maximum transverse dimension260to a longitudinal dimension262of the channels256. The longitudinal dimension262of the channels256and the maximum transverse dimension260form a channel ratio. In some embodiments, the channel ratio is at least 2:1. For example, the longitudinal dimension262is at least double the maximum transverse dimension260. In some embodiments, the channel ratio is at least 2.5:1. For example, the longitudinal dimension262is at least two and a half times the maximum transverse dimension260. In some embodiments, the channel ratio is at least 3:1. For example, the longitudinal dimension262is at least three times the maximum transverse dimension260. In some embodiments, the channel ratio is at least 5:1. For example, the longitudinal dimension262is at least five times the maximum transverse dimension260. In a particular example, the longitudinal dimension262is 10.0 mm and the maximum transverse dimension260is no more than 2.0 mm. As used herein, a channel256is a substantially closed conduit that allows fluid flow in substantially one direction, such as a tube, pipe, or other structure with a transverse aspect ratio of less than 5:1. The transverse dimension260is measured through the transverse area of the channel256, and the aspect ratio is the ratio of the minimum value of the transverse dimension260to the maximum dimension. For example, a circular channel has a transverse aspect ratio of 1:1. In another example, a square channel has a transverse aspect ratio of 1.41:1. In another example, a rectangular channel that is 4 mm by 2 mm has a transverse aspect ratio of 1.73:1. In some embodiments, depending on the shape of the conductive fibers242or other electrical bridge and the positioning of the conductive fibers242or other electrical bridge between the rotor238and stator240, a channel256according to the present disclosure may have a transverse cross-section that is square, rectangular, triangular, other regular polygonal, non-regular polygonal, circular, elliptical, other regular curved shapes, irregular curved shapes, or combinations thereof. The maximum transverse dimension260of the channel256is the transverse dimension that is greatest. For example, the EM shielding of a Faraday-cage style shield is based upon the wavelength and the required attenuation at that wavelength. For example, the higher the frequency, the shorter the wavelength of the EM radiation. The shorter the wavelength, the smaller the pores or channel openings need to be to attenuate the EM radiation. A Faraday-style shield operates by balancing the electrical fields on either side of the shield. A substantially continuous Faraday shield allows the free conduction of electrical charge through the walls of the Faraday shield and becomes a hollow conductor. Introducing an aperture into the Faraday shield allows the leakage of EM radiation through the aperture. For the Faraday cage to function as such, the aperture size must be many times smaller than the wavelength of the interest. In some embodiments, by positioning the EMI shielding device in an aperture of an electronic device housing, the EMI shielding device divides the aperture into a collection of smaller openings based on the channel size. However, as the channels are elongated, the EMI shielding device offers additional attenuation for EM radiation wavelengths smaller than the channel size, as the EM radiation must pass through the length of the channels to leak from the EMI shielding device. For example, attenuation may be controlled by the grounding of the components of the EMI shielding device, the maximum transverse dimension and longitudinal dimension of the channels, quantity of the channels, frequency, other factors, or combinations thereof. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in a frequency range of 2.2 GHz to 2.6 GHz. In other embodiments, an EMI shielding device attenuates EMI in a frequency range of 800 MHz to 900 MHz. In further embodiments, an EMI shielding device attenuates EMI in a frequency range of 1.8 GHz to 2.0 GHz. In yet further embodiments, a thermal management device attenuates EMI in a frequency range of 5.0 GHz to 6.0 GHz. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in the frequency range by at least 20 dB throughout the frequency range. In other embodiments, an EMI shielding device attenuates EMI in the frequency range by at least 30 dB throughout the frequency range. In yet other embodiments, an EMI shielding device attenuates EMI in the frequency range by at least 40 dB throughout the frequency range. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in the frequency range by an average of at least 20 dB across the frequency range. In other embodiments, an EMI shielding device attenuates EMI in the frequency range by an average of at least 30 dB across the frequency range. In yet other embodiments, an EMI shielding device attenuates EMI in the frequency range by an average of at least 40 dB across the frequency range. In some embodiments, the proximate surface244, contact surface248, and/or electrical bridge (e.g., conductive fibers242ofFIGS.3-1and3-2) of the channels256include an electrically conductive material. Examples of suitable materials include, but are not limited to copper, aluminum, iron, tin, magnesium, or alloys thereof; graphite; and electrically conductive polymers. In other embodiments, the conductive fibers242of the electrical bridge are arranged substantially continuously around the proximate surface244between the proximate surface244and the contact surface248such that there are no channels256formed. For example, the conductive fibers242may form a continuous ring around at least a portion of the longitudinal length of the rotor238in the longitudinal direction of the rotational axis246. The continuous ring of conductive fibers242may substantially cover the space in the aperture234between the proximate surface244and the contact surface248. In other examples, the conductive fibers242may be staggered (such as the rows258positioned at an angle to the rotational axis246) or randomly, such that, in the longitudinal direction through the aperture234(e.g., from the perspective illustrated inFIG.2), the electrical bridge appears continuous. WhileFIGS.3-1and3-2illustrate an embodiment of an EMI shielding device236for an axial fan, in other embodiments, an EMI shielding device according to the present disclosure provides an electrical bridge to attenuate or shield EMI across other types of rotor-stator pairs.FIG.4is a side cross-sectional view of an embodiment of a blower fan with an axial EMI shielding device336according to the present disclosure. In some embodiments, a blower has a rotor338with fan blades350that draws a fluid (such as air) in through an aperture334(or blows fluid out through the aperture334), and the aperture334is a potential EMI leakage point of the housing. For example, a low-profile blower may be used in a laptop computing device, such as that described in relation toFIG.1, and the positioning of the electronic components of the computing device may be close to the aperture334. In some embodiments, the proximate surface344of the rotor338(in this case, a blower fan rotor) is not the radially outermost edge of the rotor338, but rather an axial surface366of the rotor338and/or a radially outward facing surface368of the rotor338that is not the radially outermost edge. The contact surface348, similarly, may be an axial surface or a radial surface that is opposite the proximate surface344of the rotor338. In some embodiments, the EMI shielding device336includes an electrical bridge that includes bearings370that provide an electrically conductive contact between the rotor338and the stator340. In some embodiments, the bearings370include race bearings, such as positioned between radial surfaces of the rotor338and stator340. In some embodiments, the bearings370include thrust bearings, such as positioned between axial surfaces relative to the rotational axis346of the rotor338. The electrical bridge includes, in some embodiments, a lubricant. In at least one example, the lubricant is an electrically conductive lubricant, such as graphite. An electrically conductive lubricant may be used with any of the electrical bridges herein to limit and/or prevent wear on the portions of the electrical bridge that provide a physical contact for electrical conductivity, such as the conductive fibers242described in relation toFIG.3-1andFIG.3-2. In other embodiments, the electrically conductive lubricant provides the electrical conductivity when other portions of the electrical bridge are electrically insulating. For example, a race bearing that includes ceramic bearings may include a graphite lubricant to provide electrical conductivity, despite the ceramic bearings being electrically non-conductive. WhileFIG.4illustrates an embodiment of an EMI shielding device336including a blower fan rotor338with a proximate surface344that is radially inside a radially outermost edge of the rotor338, in other embodiments, an electrical bridge including bearings may be positioned at the radially outermost edge of the rotor338, such as the location of the conductive fibers242described in relation toFIG.3-1andFIG.3-2. Referring now toFIG.5, a side cross-sectional view of an embodiment of an EMI shielding device436with a bearing470between a radially outermost edge of the rotor438and the stator440is shown. In some embodiments, at least a portion of the rotor438is received by a recess472or recesses of the housing stator440. In some embodiments, the recess472receives a portion of the rotor438. In some embodiments, the recess472receives a projection474projecting from the rotor438. The gap between a proximate surface444of the projection474and the contact surface448of the recess472is bridged by an electrical bridge. In some embodiments, the electrical bridge includes a bearing470, such as a race bearing and/or thrust bearing. In some embodiments, the electrical bridge includes one or more conductive fibers442. In some embodiments, the electrical bridge includes an electrically conductive lubricant. FIG.6is a perspective cross-sectional view of an embodiment of an EMI shielding device536with a flexible membrane576in a gap554between the rotor538and the stator540. In some embodiments, the flexible membrane576is electrically conductive, such as an electrically conductive metal membrane. The electrically conductive metal may be elastically deformed within the elastic deformation regime of the metal to apply a force between the proximate surface544of the rotor538and the contact surface548of the stator540. In some embodiments, the flexible membrane is a non-metal membrane that is electrically conductive, such as an electrically conductive polymer. In some embodiments, the flexible membrane576has an electrically conductive lubricant applied thereto to reduce wear between the flexible membrane576and the proximate surface544of the rotor538and the contact surface548of the stator540. In some embodiments, the flexible membrane576is elastically biased to apply a contact force between the proximate surface544of the rotor538and the contact surface548of the stator540. In at least one embodiment, the flexible membrane576is positioned and arranged to apply a contact force between the proximate surface544of the rotor538and the contact surface548of the stator540in response to a region of lower fluid pressure created by the rotation of the fan rotor538. For example, rotation of the fan rotor538causes the fan blades550to rotate and urge airflow578through the rotor538and out of the housing stator540. The resulting region of low fluid pressure580inside the housing stator540and/or on the opposite side of the rotor538urges the angled flexible membrane576to lever the flexible membrane576and increase and/or cause the contact force between the proximate surface544of the rotor538and the contact surface548of the stator540. For example, the flexible membrane576may be fixed to the contact surface548of the stator540and angled in the direction of airflow578of the fan rotor538. The flexible membrane576is urged toward the proximate surface544of the rotor538by the pressure difference and provides the electrical conductivity between the stator540and the rotor538. In at least one example, the pressure difference can assist in maintaining contact between the flexible membrane576and the proximate surface544as the flexible membrane576wears. For example, as the flexible membrane576wears due to friction with the proximate surface544(or with the contact surface548in embodiments with the flexible membrane576fixed to the rotor538), the contact point between the flexible membrane576and the rotor538may change. In a particular example, the contact point may move longitudinally along the annular body552of the rotor538as the flexible membrane576shortens due to wear. In other embodiments, the electrical bridge is not a solid member that contacts a surface or other solid member.FIG.7-1is a transverse cross-sectional view of an embodiment of an EMI shielding device636with a solid rotor638. In some embodiments, the rotor638is a solid or tubular shaft for transferring torque relative to the stator640. In some embodiments, the rotor638is a drive shaft for an electric motor. In some embodiments, the electrical bridge includes or is an electrically conductive fluid682positioned in a gap654between the proximate surface644of the rotor638and the contact surface648of the stator640. In some embodiments, the electrically conductive fluid682is a lubricant. In some embodiments, the electrically conductive fluid682is a liquid, such as metallic particle-bearing liquid. In some embodiments, the electrically conductive fluid682is a gas, such as a plasma. The electrically conductive fluid682contacts both the proximate surface644of the rotor638and the contact surface648of the stator640and provides an electrical path between the rotor638and stator640to attenuate and/or block EMI from passing through the gap654. In some embodiments, the electrically conductive fluid682circumferentially surrounds a portion the rotor638. In other embodiments, the electrically conductive fluid682is positioned around less than the full circumference of the rotor638. Referring now toFIG.7-2,FIG.7-2is a longitudinal cross-sectional view of the EMI shielding device636ofFIG.7-1. The electrically conductive fluid682may be retained longitudinally relative to the shaft (in the longitudinal direction of the rotational axis646) so as to hold the electrically conductive fluid682in contact with the proximate surface644and the contact surface648. In some embodiments, the electrically conductive fluid682is retained longitudinally with a magnetic trap684retaining the electrically conductive fluid682between the rotor638and the stator640. For example, the electrically conductive fluid682may be a ferromagnetic fluid. In other examples, the electrically conductive fluid682may be a plasma. The magnetic trap684includes one or more magnets686that establish a magnetic field that holds the electrically conductive fluid682in place, longitudinally, relative to the rotor638. In some embodiments, the magnets686are permanent magnets. In some embodiments, the magnets686are electromagnets. In some embodiments, the electrically conductive fluid682is retained longitudinally with one or more gaskets, seals, O-rings, or other physical elements that retain the electrically conductive fluid682between the rotor638and the stator640. For example, a magnetic trap684may be ineffective on an electrically conductive fluid682that is non-magnetic. The electrically conductive fluid682is an electrical bridge that provides electrical connection between the rotor638and the stator640. In at least one embodiment, an EMI shielding device with an electrical bridge according to the present disclosure attenuates or blocks EMI in rotational interfaces. In some embodiments, the EMI shielding device positions an electrical bridge between rotor and stator to substantially fill the gap therebetween and block EMI. In some embodiments, the electrical bridge divides the gap into channels allow airflow therethrough while attenuating the passage of EMI through the channels. INDUSTRIAL APPLICABILITY The present disclosure relates generally to systems and methods for electromagnetic interference (EMI) or radio frequency (RF) shielding. More particularly, the EMI shielding devices described herein are configured to provide EMI or RF shielding for a general-purpose computing device, a specialized video game console or other specialized computing device, and other electronic devices such as electric motors. In some embodiments, EMI shielding devices according to the present disclosure are configured to allow rotation of a rotor relative to and/or through an aperture in a device housing. The rotor may be a fan rotor, such as an axial fan or transverse blower in a personal computer or video game console, or a shaft rotor, such as a drive shaft of an electric motor that transfers torque through a housing or chassis. In some embodiments, EMI shielding devices according to the present disclosure allow rotation of the rotor relative to the stator while limiting and/or preventing transmission of EMI into or out of the aperture in the device housing. In some embodiments, an EMI shielding device according to the present disclosure is positioned proximate a fan to receive heat from a computing component of the electronic device. In some examples, the computing component, such as a processor, system memory, hardware storage device, networking device, etc. may be susceptible to EMI that compromises the performance of the computing component. In other examples, the computing component may generate EMI that adversely affects the performance of other computing components of the electronic device. In some embodiments, an EMI shielding device according to the present disclosure is part of a fan. The fan may move air over, through, or past a thermal management device (such as a fin pack), which receives heat from at least one heat source in the electronic device and transfers the heat to the air. In some embodiments, the heat source is a processor, such as a central processing unit (CPU), a graphical processing unit (GPU); a storage device, such as random-access memory (RAM), other volatile memory, non-volatile memory, or combinations thereof. In some embodiments, the heat source is coupled directly to the thermal management device. In some embodiments, the heat source is thermally connected to the thermal management device with at least one thermally conductive or convective element therebetween. In some examples, the heat source is thermally connected to the thermal management device by a thermal interface material (TIM), such as a thermal paste, sandwiched between a surface of the heat source and a surface of the thermal management device. In some examples, the heat source is thermally connected to the thermal management device by a heat pipe, vapor chamber, heat spreader, or other thermally conductive or convective element that transports heat from a surface of the heat source to a surface of the thermal management device. The thermal management device is thermally connected to the heat source when at least element of the thermal management system is intended to physically connect the thermal management device to the heat source. In other words, a thermal management device that receives heat from the heat source only by ambient air flowing therebetween is not thermally connected, while a thermal management device connected to a heat source by a vapor chamber with a two-phase working fluid moving therein is thermally connected when a surface of the vapor chamber contacts a surface of the heat source and a surface of the thermal management device. In another example, a thermal management device is thermally connected to the heat source when the heat source is in contact with a first TIM, which contacts a surface of a heat pipe, which contacts a second TIM, which contacts a surface of the thermal management device. In some embodiments, an EMI shielding device according to the present disclosure allows airflow through an aperture to reject excess heat to the ambient atmosphere while also limiting and/or preventing EMI from passing through the aperture in the housing proximate the fan. In some embodiments, the EMI shielding device includes a plurality of channels between the rotor and stator. In some embodiments, the channels have a maximum transverse dimension (e.g., width) that is less than a longitudinal dimension (e.g., length) to limit the passage of EMI through the channel. In some examples, a computing device includes a first portion and a second portion movably connected to one another by a hinge. In some embodiments, the first portion of the computing device may include a display to present visual information to a user and the second portion of the computing device may include one or more input devices, such as a trackpad, a keyboard, etc., to allow a user to interact with the computing device. In embodiments in which the computing device is a hybrid computer, the first portion may include the display and at least a processor. The first portion may further include additional computer components, such as a storage device, system memory, a graphical processing unit, graphics memory, one or more communication devices (such as WIFI, BLUETOOTH, near-field communications), peripheral connection points, etc. In some embodiments, the first portion may be removable from the hinge and/or the second portion. In some embodiments, the computing device is a specialized computing device, such as a video game console, or a general-purpose desktop tower computer that is connected to an external display and/or audio devices. In such embodiments, the computing device includes one or more of the computer components, such as a storage device, system memory, a graphical processing unit, graphics memory, one or more communication devices (such as WIFI, BLUETOOTH, near-field communications), peripheral connection points, etc. in a single housing of the computing device. The computing device includes a variety of components that generate heat. The heat sources can be any component of the computing device that generates heat but, particularly, may include a processor (such as a central processing unit (CPU), a graphical processing unit (GPU), a physics processing unit, or other processors), system memory, video memory, storage devices, networking devices, display devices, input devices, optical drives, peripheral connection ports, or any other components of the computing device. In some embodiments, the heat from the heat sources is distributed from a heat source across a surface by a heat spreader. In other embodiments, the heat is conducted from the heat sources toward a cooler region of the computing device and/or toward an exhaust by a heat transfer element. In yet other embodiments, the heat is conducted from a heat source through a cold-plate to a heat transfer element. The heat transfer element may be a thermally conductive material, such as copper, silver, or aluminum that conducts heat from a region of higher thermal energy to a region of lower thermal energy. For example, the heat transfer element will conduct thermal energy from the first end of the heat transfer element adjacent the heat sources toward a cooler second end of the heat transfer element near a heat sink to lessen a temperature gradient along the heat transfer element. In other examples, the heat transfer element may be a heat pipe that may further aid in transferring thermal energy away from the heat sources. At the higher temperature (“hot”) interface of a heat pipe a liquid in contact with a thermally conductive solid surface turns into a vapor by absorbing heat from that surface. The vapor then travels along the heat pipe to a lower temperature (“cold”) interface and condenses back into a liquid releasing the latent heat. The liquid then returns to the hot interface through, for example, capillary action, centrifugal force, or gravity, and the cycle repeats. Due to the high heat transfer coefficients for boiling and condensation, vapor cooling system heat pipes are effective thermal conductors. The effective thermal conductivity varies with heat pipe length and can approach 100 kW/(m·K) for long heat pipes, in comparison with approximately 400 W/(m·K) for copper. In some embodiments, the second end of heat transfer element is in contact with, in proximity to, or attached to a heat sink, such as a fin pack. The fin pack includes or is made of a thermally conductive material to conduct thermal energy from the second end of the heat transfer element into the fin pack. The fin pack has a plurality of fins, channels, rails, or other structures that increase the surface area of the fin pack to dissipate the thermal energy. In some embodiments, the thermally conductive material has a thermal conductivity in a range having an upper value, a lower value, or upper and lower values including any of 100 Watts per meter-Kelvin (W/m·K), 125 W/m·K, 150 W/m·K, 175 W/m·K, 200 W/m·K, 250 W/m·K, 300 W/m·K, 400 W/m·K, 450 W/m·K, or any values therebetween. For example, the thermal conductivity may be greater than 100 W/m·K. In other examples, the thermal conductivity may be less than 450 W/m·K. In yet other examples, the thermal conductivity may be between 100 W/m·K and 450 W/m·K. In further examples, the thermal conductivity may be greater than 150 W/m·K. In at least one example, the thermal conductivity may be greater than 250 W/m·K. The cooling system dissipates the thermal energy through air flowed through or over the fin pack by a fan. The fan may move air flow through one or more channels of the fin pack such that air absorbs thermal energy from the surfaces of the fin pack. The dissipation of heat from the fin pack reduces the temperature of the fin pack to allow the heat transfer element to transfer more heat from the heat sources to the fin pack. In a conventional computing device, a Faraday cage may be positioned around or over at least a portion of the electronic components. For example, the processor or other electronic components of the computing device generate EM radiation during operation. The EM radiation emitted by the processor or other electronic components can interfere with the operation of an external electronic component. In other examples, an external electronic component produces EMI that may adversely impact the electronic components inside the Faraday cage. The Faraday cage defines an external side (external to the Faraday cage) and an internal side (internal to the Faraday cage). The Faraday cage may include a conductive material to suppress the EM radiation from the processor or other electronic components internally. The internal conduction of the EM radiation along the Faraday cage shields the EM radiation that may interfere with the operation of the external electronic component(s) and vice versa. However, a conventional Faraday cage is inefficient at transferring energy through the Faraday cage and may cause the heat sources to increase in temperature by limiting ventilation through the Faraday cage. In some embodiments, an aperture is provided in the Faraday cage to allow air flow through the aperture to exhaust the thermal energy (via warm air) from the heat sources and the computing device. In some embodiments, the aperture has a shaft positioned therethrough to transfer torque, such as produced by an electric motor or received by a generator. In either instance, the aperture is a potential source of EMI leakage through the Faraday cage. In some embodiments, an EMI shielding device according to the present disclosure limits and/or prevent EMI leakage through the aperture by electrically connecting the rotor of the fan or shaft in the aperture to the stator of the aperture and/or Faraday cage housing of the computing device. In some embodiments, an EMI shielding device for a rotating interface includes a rotor that rotates relative to a stator. While the embodiment of a rotor described in the following examples is an axial fan, it should be understood that the rotor may be other devices or components, as will be described herein. The rotor is positioned in or proximate to an aperture in the stator, and the rotor rotates relative to the stator. In some embodiments, such as an axial fan and/or a blower, the aperture allows airflow through a portion of the fan rotor. The EMI shielding device includes an electrical bridge between the rotor and the stator. In some embodiments, the electrical bridge includes conductive fibers that provide an electrically conductive path between the rotor and the stator while the rotor rotates relative to the stator. The conductive fibers may be a conductive metal fiber, such as copper, or an electrically conductive non-metal conductive fiber, such as graphite or an electrically conductive polymer. In other embodiments, the conductive fibers of the electrical bridge are arranged substantially continuously around the proximate surface between the proximate surface and the contact surface such that there are no channels formed. For example, the conductive fibers may form a continuous ring around at least a portion of the longitudinal length of the rotor in the longitudinal direction of the rotational axis. The continuous ring of conductive fibers may substantially cover the space in the aperture between the proximate surface and the contact surface. In other examples, the conductive fibers may be staggered (such as the rows positioned at an angle to the rotational axis) or randomly, such that, in the longitudinal direction through the aperture (e.g., from a top perspective), the electrical bridge appears continuous. The conductive fibers may be positioned on a proximate surface of the fan rotor proximate to a contact surface of the aperture in the housing stator. In some embodiments, the proximate surface is a radially outermost edge of the fan rotor relative to the rotational axis of the fan rotor. The fan rotor rotates around the rotational axis to rotate relative to the housing stator in which the aperture is located. In some embodiments, the conductive fibers are fixed to the fan rotor. For example, the conductive fibers are fixed to the proximate surface (e.g., the radially outermost edge) of the fan rotor that is proximate the contact surface of the aperture. In other embodiments, the conductive fibers are fixed to the housing stator. For example, the conductive fibers may be fixed to the contact surface of the aperture that is opposite the proximate surface of the fan rotor. In yet other embodiments, the conductive fibers are fixed to the fan rotor and the housing stator. For example, a first plurality of conductive fibers are fixed to the proximate surface (e.g., the radially outermost edge) of the fan rotor that is proximate the contact surface of the aperture and a second plurality of conductive fibers are fixed to the to contact surface of the aperture, where the first plurality of conductive fibers are positioned to contact and provide an electrical connection with the second plurality of conductive fibers as the fan rotor rotates relative to the housing stator. The electrical bridge has a conductivity sufficient to allow transmission of electrical current across the electrical bridge to maintain the Faraday-cage effect. In some embodiments, the electrical bridge has a resistivity less than 500 milliohm per linear centimeter around an arc segment of 1 centimeter of the electrical bridge to provide sufficient conductivity. For example, the electrical bridge may have a resistivity less than 400 milliohm per linear centimeter. In other examples, the electrical bridge has a resistivity less than 250 milliohm per linear centimeter around an arc segment of 1 centimeter of the electrical bridge to provide sufficient conductivity. In some embodiments, the proximate surface of the fan rotor is continuous around the fan rotor in the rotational direction around the rotational axis. In some embodiments, the proximate surface is an outermost surface of an annular body around the fan rotor. For example, the annular body may be a continuous annulus around the fan blade(s) of fan rotor that provides a continuous and electrically conductive surface around the circumference of the fan rotor. In some embodiments, at least a portion of the EMI leakage occurs in a gap between the proximate surface of the rotor and the contact surface of the stator. In some embodiments, the gap is an annular space between the radially outermost edge of the annular body and the edge of the aperture. An EMI shielding device according to the present disclosure bridges that gap with an electrical bridge to provide electrical conductivity between the rotor and stator, such as conductive fibers. In some embodiments, electrical bridge (e.g., the conductive fibers) partitions the gap into channels. In some embodiments, the channels allow airflow therethrough while attenuating EMI that would otherwise interfere with electronic components. The EMI shielding device includes a plurality of conductive fibers arranged in rows that define a plurality of channels when contacting and providing electrical conductivity between the proximate surface of the rotor and the contact surface of the stator. The channels may allow airflow and EMI therethrough. The channels have a maximum transverse dimension that is transverse to longitudinal direction of the channels. For example, in the illustrated embodiment, the rows and, therefore, the channel(s) are oriented axially (e.g., substantially parallel to the rotational axis). In other examples, the channel(s) may have a longitudinal direction that is oriented at an angle to the rotational axis of the rotor. The maximum transverse dimension in the illustrated embodiment is in the rotational direction between the rows of conductive fibers. In other examples, the maximum transverse dimension may be a gap height between the proximate surface of the rotor and the contact surface of the stator. The attenuation of EMI by the EMI shielding device is at least partially related to a ratio of the maximum transverse dimension to a longitudinal dimension of the channels. The longitudinal dimension of the channel and the maximum transverse dimension form a channel ratio. In some embodiments, the channel ratio is at least 2:1. For example, the longitudinal dimension is at least double the maximum transverse dimension. In some embodiments, the channel ratio is at least 2.5:1. For example, the longitudinal dimension is at least two and a half times the maximum transverse dimension. In some embodiments, the channel ratio is at least 3:1. For example, the longitudinal dimension is at least three times the maximum transverse dimension. In some embodiments, the channel ratio is at least 5:1. For example, the longitudinal dimension is at least five times the maximum transverse dimension. In a particular example, the longitudinal dimension is 10.0 mm and the maximum transverse dimension is no more than 2.0 mm. As used herein, a channel is a substantially closed conduit that allows fluid flow in substantially one direction, such as a tube, pipe, or other structure with a transverse aspect ratio of less than 5:1. The transverse dimension is measured through the transverse area of the channel256, and the aspect ratio is the ratio of the minimum value of the transverse dimension260to the maximum dimension. For example, a circular channel has a transverse aspect ratio of 1:1. In another example, a square channel has a transverse aspect ratio of 1.41:1. In another example, a rectangular channel that is 4 mm by 2 mm has a transverse aspect ratio of 1.73:1. In some embodiments, depending on the shape of the conductive fibers or other electrical bridge and the positioning of the conductive fibers or other electrical bridge between the rotor and stator, a channel according to the present disclosure may have a transverse cross-section that is square, rectangular, triangular, other regular polygonal, non-regular polygonal, circular, elliptical, other regular curved shapes, irregular curved shapes, or combinations thereof. The maximum transverse dimension of the channel is the transverse dimension that is greatest, irrespective of orientation perpendicular to the longitudinal dimension. For example, the EM shielding of a Faraday-cage style shield is based upon the wavelength and the required attenuation at that wavelength. For example, the higher the frequency, the shorter the wavelength of the EM radiation. The shorter the wavelength, the smaller the pores or channel openings need to be to attenuate the EM radiation. A Faraday-style shield operates by balancing the electrical fields on either side of the shield. A substantially continuous Faraday shield allows the free conduction of electrical charge through the walls of the Faraday shield and becomes a hollow conductor. Introducing an aperture into the Faraday shield allows the leakage of EM radiation through the aperture. For the Faraday shield to function as such, the aperture size must be many times smaller than the wavelength of the interest. In some embodiments, by positioning the EMI shielding device in an aperture of an electronic device housing, the EMI shielding device divides the aperture into a collection of smaller openings based on the channel size. However, as the channels are elongated, the EMI shielding device offers additional attenuation for EM radiation wavelengths smaller than the channel size, as the EM radiation must pass through the length of the channels to leak from the EMI shielding device. For example, attenuation may be controlled by the grounding of the components of the EMI shielding device, the maximum transverse dimension and longitudinal dimension of the channels, quantity of the channels, frequency, other factors, or combinations thereof. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in a frequency range of 2.2 GHz to 2.6 GHz. In other embodiments, an EMI shielding device attenuates EMI in a frequency range of 800 MHz to 900 MHz. In further embodiments, an EMI shielding device attenuates EMI in a frequency range of 1.8 GHz to 2.0 GHz. In yet further embodiments, a thermal management device attenuates EMI in a frequency range of 5.0 GHz to 6.0 GHz. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in the frequency range by at least 20 dB throughout the frequency range. In other embodiments, an EMI shielding device attenuates EMI in the frequency range by at least 30 dB throughout the frequency range. In yet other embodiments, an EMI shielding device attenuates EMI in the frequency range by at least 40 dB throughout the frequency range. In some embodiments, an EMI shielding device according to the present disclosure attenuates EMI in the frequency range by an average of at least 20 dB across the frequency range. In other embodiments, an EMI shielding device attenuates EMI in the frequency range by an average of at least 30 dB across the frequency range. In yet other embodiments, an EMI shielding device attenuates EMI in the frequency range by an average of at least 40 dB across the frequency range. In some embodiments, the proximate surface, contact surface, and/or electrical bridge of the channels include an electrically conductive material. Examples of suitable materials include, but are not limited to copper, aluminum, iron, tin, magnesium, or alloys thereof; graphite; and electrically conductive polymers. In some embodiments, a blower has a rotor with fan blades that draws a fluid (such as air) in through an aperture (or blows fluid out through the aperture, and the aperture is a potential EMI leakage point of the housing. For example, a low-profile blower may be used in a laptop computing device, such as that described herein, and the positioning of the electronic components of the computing device may be close to the aperture. In some embodiments, the proximate surface of the rotor (in this case, a blower fan rotor) is not the radially outermost edge of the rotor, but rather an axial surface of the rotor and/or a radially outward facing surface of the rotor that is not the radially outermost edge. The contact surface, similarly, may be an axial surface or a radial surface that is opposite the proximate surface of the rotor. In some embodiments, the EMI shielding device includes an electrical bridge that includes bearings that provide an electrically conductive contact between the rotor and the stator. In some embodiments, the bearings include race bearings, such as positioned between radial surfaces of the rotor and stator. In some embodiments, the bearings include thrust bearings, such as positioned between axial surfaces relative to the rotational axis of the rotor. The electrical bridge includes, in some embodiments, a lubricant. In at least one example, the lubricant is an electrically conductive lubricant, such as graphite. An electrically conductive lubricant may be used with any of the electrical bridges herein to limit and/or prevent wear on the portions of the electrical bridge that provide a physical contact for electrical conductivity. In other embodiments, the electrically conductive lubricant provides the electrical conductivity when other portions of the electrical bridge are electrically insulating. For example, a race bearing that includes ceramic bearings may include a graphite lubricant to provide electrical conductivity, despite the ceramic bearings being electrically non-conductive. While some embodiments of an EMI shielding device includes a blower fan rotor with a proximate surface that is radially inside a radially outermost edge of the rotor, in other embodiments, an electrical bridge including bearings may be positioned at the radially outermost edge of the rotor. In some embodiments, at least a portion of the rotor is received by a recess or recesses of the housing stator. In some embodiments, the recess receives a portion of the rotor. In some embodiments, the recess receives a projection projecting from the rotor. The gap between a proximate surface of the projection and the contact surface of the recess is bridged by an electrical bridge. In some embodiments, the electrical bridge includes a bearing, such as a race bearing and/or thrust bearing. In some embodiments, the electrical bridge includes one or more conductive fibers. In some embodiments, the electrical bridge includes an electrically conductive lubricant. In some embodiments, the flexible membrane is electrically conductive, such as an electrically conductive metal membrane. The electrically conductive metal may be elastically deformed within the elastic deformation regime of the metal to apply a force between the proximate surface of the rotor and the contact surface of the stator. In some embodiments, the flexible membrane is a non-metal membrane that is electrically conductive, such as an electrically conductive polymer. In some embodiments, the flexible membrane has an electrically conductive lubricant applied thereto to reduce wear between the flexible membrane and the proximate surface of the rotor and the contact surface of the stator. In some embodiments, the flexible membrane is elastically biased to apply a contact force between the proximate surface of the rotor and the contact surface of the stator. In at least one embodiment, the flexible membrane is positioned and arranged to apply a contact force between the proximate surface of the rotor and the contact surface of the stator in response to a region of lower fluid pressure created by the rotation of the fan rotor. For example, rotation of the fan rotor causes the fan blades to rotate and urge airflow through the rotor and out of the housing stator. The resulting region of low fluid pressure inside the housing stator and/or on the opposite side of the rotor urges the angled flexible membrane to lever the flexible membrane and increase and/or cause the contact force between the proximate surface of the rotor and the contact surface of the stator. For example, the flexible membrane may be fixed to the contact surface of the stator and angled in the direction of airflow of the fan rotor. The flexible membrane is urged toward the proximate surface of the rotor by the pressure difference and provides the electrical conductivity between the stator and the rotor. In at least one example, the pressure difference can assist in maintaining contact between the flexible membrane and the proximate surface as the flexible membrane wears. For example, as the flexible membrane wears due to friction with the proximate surface (or with the contact surface in embodiments with the flexible membrane fixed to the rotor), the contact point between the flexible membrane and the rotor may change. In at particular example, the contact point may move longitudinally along the annular body of the rotor as the flexible membrane shortens due to wear. In other embodiments, the electrical bridge is not a solid member that contacts a surface or other solid member. In some embodiments, the rotor is a solid or tubular shaft for transferring torque relative to the stator. In some embodiments, the rotor is a drive shaft for an electric motor. In some embodiments, the electrical bridge includes or is an electrically conductive fluid positioned in a gap between the proximate surface of the rotor and the contact surface of the stator. In some embodiments, the electrically conductive fluid is a lubricant. In some embodiments, the electrically conductive fluid is a liquid, such as metallic particle-bearing liquid. In some embodiments, the electrically conductive fluid is a gas, such as a plasma. The electrically conductive fluid contacts both the proximate surface of the rotor and the contact surface of the stator and provides an electrical path between the rotor and stator to attenuate and/or block EMI from passing through the gap. In some embodiments, the electrically conductive fluid circumferentially surrounds a portion of the rotor. In other embodiments, the electrically conductive fluid is positioned around less than the full circumference of the rotor. In some embodiments, the electrically conductive fluid may be retained longitudinally relative to the shaft (in the longitudinal direction of the rotational axis) so as to hold the electrically conductive fluid in contact with the proximate surface and the contact surface. In some embodiments, the electrically conductive fluid is retained longitudinally with a magnetic trap retaining the electrically conductive fluid between the rotor and the stator. For example, the electrically conductive fluid may be a ferromagnetic fluid. In other examples, the electrically conductive fluid may be a plasma. The magnetic trap includes one or more magnets that establish a magnetic field that holds the electrically conductive fluid in place, longitudinally, relative to the rotor. In some embodiments, the magnets are permanent magnets. In some embodiments, the magnets are electromagnets. In some embodiments, the electrically conductive fluid is retained longitudinally with one or more gaskets, seals, O-rings, or other physical elements that retain the electrically conductive fluid between the rotor and the stator. For example, a magnetic trap may be ineffective on an electrically conductive fluid that is non-magnetic. The electrically conductive fluid is an electrical bridge that provides electrical connection between the rotor and the stator. In at least one embodiment, an EMI shielding device with an electrical bridge according to the present disclosure attenuates or blocks EMI in rotational interfaces. In some embodiments, the EMI shielding device positions an electrical bridge between rotor and stator to substantially fill the gap therebetween and block EMI. In some embodiments, the electrical bridge divides the gap into channels allow airflow therethrough while attenuating the passage of EMI through the channels. The present disclosure relates to systems and methods for EMI or RF shielding according to at least the examples provided in the sections below: [A1] In some embodiments, an EMI attenuation device includes a housing stator, a fan rotor, and an electrical bridge therebetween. The housing stator has an aperture therethrough, and at least a portion of the housing stator is electrically conductive. The fan rotor is adjacent to the aperture and has a rotational axis relative to the housing stator and a proximate surface proximate the housing stator. The fan rotor is electrically conductive, and the proximate surface is continuous around a rotational direction of the fan rotor. The electrical bridge is between the proximate surface of the fan rotor and a contact surface of the housing stator. [A2] In some embodiments, the electrical bridge of [A1] includes a plurality of electrically conductive fibers fixed to the proximate surface of the fan rotor and contacting the contact surface of the housing stator. [A3] In some embodiments, the electrical bridge of [A1] includes a plurality of electrically conductive fibers fixed to the contact surface of the housing stator and contacting the proximate surface of the fan rotor. [A4] In some embodiments, the electrical bridge of [A1] includes a first plurality of electrically conductive fibers fixed to the contact surface of the housing stator and a second plurality of electrically conductive fibers fixed to the proximate surface of the fan rotor and contacting the first plurality of electrically conductive fibers. [A5] In some embodiments, the electrical bridge of any of [A1] through [A4] includes a conductive lubricant between the proximate surface of the fan rotor and the contact surface of the housing stator. [A6] In some embodiments, the electrical bridge of [A1] includes a flexible membrane of electrically conductive material. [A7] In some embodiments, the flexible membrane of [A6] is fixed to the contact surface of the housing stator and contacting the proximate surface of the fan rotor. [A8] In some embodiments, the flexible membrane of [A6] is angled relative to a direction of the rotational axis. [A9] In some embodiments, the proximate surface of any of [A1] through [A8] is annular around the rotational axis. [A10] In some embodiments, the electrical bridge of [A1] includes a bearing contacting the contact surface of the housing stator and contacting the proximate surface of the fan rotor. [A11] In some embodiments, the electrical bridge, the contact surface of the housing stator, and the proximate surface of the fan rotor of any of [A1] through [A10] define a plurality of channels, and each channel of the plurality of channels has a maximum transverse dimension perpendicular to a longitudinal direction of the rotational axis of 2.0 millimeters (mm). [A12] In some embodiments, the electrical bridge, the contact surface of the housing stator, and the proximate surface of the fan rotor of any of [A1] through [A10] define a plurality of channels, and each channel of the plurality of channels has maximum transverse dimension perpendicular to a longitudinal direction of the rotational axis and a longitudinal dimension parallel to the rotational axis, and each channel of the plurality of channels has a channel ratio (longitudinal dimension to maximum transverse dimension) of at least 2:1. [A13] In some embodiments, the fan rotor of any of [A1] through [A12] is an axial fan. [A14] In some embodiments, the electrical bridge of any of [A1] through [A13] includes an electrically conductive fluid contacting the contact surface of the housing stator and contacting the proximate surface of the fan rotor. [A15] In some embodiments, the electrically conductive fluid of [A14] is magnetically retained between the contact surface of the housing stator and the proximate surface of the fan rotor. [B1] In some embodiments, an EMI attenuation device includes a stator having an aperture therethrough, a shaft rotor in the aperture, and an electrical bridge between the shaft rotor and a surface of the aperture. At least a portion of the stator proximate the aperture is electrically conductive. The shaft rotor has a rotational axis relative to the stator and a circular OD surface. The OD surface of the shaft rotor is electrically conductive, and the circular OD surface is continuous around a circumference of the shaft rotor. The electrical bridge is located between the circular OD surface of the shaft rotor and an ID surface of the aperture. [B2] In some embodiments, the shaft rotor is a drive shaft for transferring torque through the aperture, and the electrical bridge includes a race bearing. [C1] In some embodiments, an electronic device includes a housing with an aperture therein, a heat source, a heat transfer element, and an EMI shielding device located proximate the aperture. The heat transfer element is thermally connected to the heat source to transfer heat from the heat source toward an aperture in the housing. The EMI shielding device includes a stator having the aperture therethrough, and at least a portion of the stator is electrically conductive. The EMI shielding device also includes a fan rotor that is adjacent to the aperture, has a rotational axis relative to the stator, and has a proximate surface proximate the stator. The fan rotor is electrically conductive, and the proximate surface is continuous around a rotational direction of the fan rotor. The fan rotor is configured to exhaust heat from the heat transfer element through aperture. The electrical bridge is between the proximate surface of the fan rotor and a contact surface of the housing stator. [C2] In some embodiments, the heat transfer element of [C1] includes a fin pack adjacent to the fan rotor. [C3] In some embodiments, the fan rotor of [C1] or [C2] is a blower fan rotor. The articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements in the preceding descriptions. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. For example, any element described in relation to an embodiment herein may be combinable with any element of any other embodiment described herein. Numbers, percentages, ratios, or other values stated herein are intended to include that value, and also other values that are “substantially”, “about”, or “approximately” the stated value, as would be appreciated by one of ordinary skill in the art encompassed by embodiments of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value. A person having ordinary skill in the art should realize in view of the present disclosure that equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made to embodiments disclosed herein without departing from the spirit and scope of the present disclosure. Equivalent constructions, including functional “means-plus-function” clauses are intended to cover the structures described herein as performing the recited function, including both structural equivalents that operate in the same manner, and equivalent structures that provide the same function. It is the express intention of the applicant not to invoke means-plus-function or other functional claiming for any claim except for those in which the words ‘means for’ appear together with an associated function. Each addition, deletion, and modification to the embodiments that falls within the meaning and scope of the claims is to be embraced by the claims. It should be understood that any directions or reference frames in the preceding description are merely relative directions or movements. For example, any references to “front” and “back” or “top” and “bottom” or “left” and “right” are merely descriptive of the relative position or movement of the related elements. The present disclosure may be embodied in other specific forms without departing from its spirit or characteristics. The described embodiments are to be considered as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. Changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. | 75,909 |
11943906 | DETAILED DESCRIPTION Various technologies pertaining to electromagnetic shielding, including use and manufacture of electromagnetic shielding, are now described with reference to the drawings, where like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects. Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form. Further, as used herein, the term “exemplary” is intended to mean serving as an illustration or example of something and is not intended to indicate a preference. With reference now toFIGS.1-3, electromagnetic shielding100is illustrated, where the electromagnetic shielding100is particularly well-suited for shielding electronic devices from EMI in data centers. More specifically,FIG.1is an overhead view of the electromagnetic shielding100,FIG.2is a cross-sectional view of the electromagnetic shielding100along line A-A, andFIG.3is a perspective view of the electromagnetic shielding100. The electromagnetic shielding100exhibits various advantages over conventional structures used to shield electronic equipment from EMI. As will be described in greater detail herein, the electromagnetic shielding100is flexible yet durable, such that the electromagnetic shielding100can be draped over a selected piece of electrical equipment and/or a selected group of electrical equipment (such as an individual server computing device or a selected group of server computing devices). In contrast, conventional approaches for shielding electrical equipment from EMI in data centers involve shielding entire buildings or rooms. In addition, the electromagnetic shielding100is relatively lightweight, such that the electromagnetic shielding100can be readily moved so that a technician is able to quickly access electrical equipment that is being shielded from EMI by the electromagnetic shielding100. Moreover, the electromagnetic shielding100is inexpensive to manufacture and install when compared to conventional approaches for shielding electrical equipment in datacenters from EMI, such as structures for enclosing racks of servers. Still further, and as will be described in greater detail herein, the electromagnetic shielding100includes apertures through which air can flow, thereby preventing heat generated by electrical equipment from being confined by the electromagnetic shielding100. Put differently, air is able to freely flow through the apertures in the electromagnetic shielding100. The electromagnetic shielding100includes several layers of different materials, where the layers include a layer of (nonmagnetic) metal. The layer of metal can be, in an example, aluminum, copper, or other similar nonmagnetic metal (in the form of a foil). The layers additionally include a layer of thermoplastic polymer fabric. The thermoplastic polymer fabric can be a woven polyethylene fabric, a paraffin fabric, or other suitable thermoplastic polymer fabric. The layer of metal and the layer of thermoplastic polymer fabric may be relatively thin; for instance, the layer of metal may be approximately 0.02 millimeters thick, and the layer of thermoplastic polymer fabric may be approximately 2 millimeters thick. In another example, the layer of metal may be non-perforated aluminum foil that can be woven with a fabric to prevent ripping, such that the layer of metal (optionally woven with fabric) is approximately 2 millimeters thick. It is to be understood, however, that the layer of metal and the layer of thermoplastic polymer fabric may be thinner or thicker than 2 millimeters. In an example, the layer of metal is between 0.01 millimeter thick and 10 millimeters thick, and the layer of thermoplastic polymer fabric is between 1 millimeter thick and 10 millimeters thick. The layer of metal and the layer of thermoplastic polymer fabric are bonded together by way of a suitable adhesive. The layer of thermoplastic polymer fabric provides structural support for the electromagnetic shielding100. The electromagnetic shielding100includes several apertures102that extend through a thickness of the electromagnetic shielding100. Accordingly, the apertures102extend through the layer of metal and the layer of thermoplastic polymer fabric. The apertures102can have any suitable shape so long as the shape is associated with EMI attenuation. For example, the electromagnetic shielding attenuates EMI by a threshold amount when the EMI has a frequency within a predefined frequency range (such as 9 kHz-24 GHz). As illustrated inFIG.1, the apertures102are hexagonal and are arranged in the electromagnetic shielding100in a honeycomb pattern. Hence, the electromagnetic shielding100has a honeycomb waveguide pattern to capture and absorb energy. In other embodiments, however, the apertures102can have a “near hexagonal” shape, a circular shape, or other suitable polygonal shape. The apertures102have a major diameter D that is a function of frequencies that are to be attenuated by the electromagnetic shielding100. In an example, the major diameter D is between 4 millimeters and 15 millimeters. In a specific example, the major diameter D of the apertures102is approximately 6.4 millimeters. Further, each aperture in the apertures102can be separated from any other aperture in the apertures102by a minimum separation distance S. Such separation distance can be, for example, between 0.1 and 1 millimeters. Still further, the electromagnetic shielding100has a thickness T, where the thickness T can be between 10 millimeters and 30 millimeters. In a specific example, the thickness T is approximately 19 millimeters. As will be described in greater detail below, several layers of metal and or thermoplastic polymer fabric can be adhered together until the desired thickness T is achieved. Referring now toFIG.4, an exploded view diagram depicting manufacture of the electromagnetic shielding100is illustrated. As noted above, the electromagnetic shielding100includes several layers of different materials. In the example illustrated inFIG.4, the electromagnetic shielding100includes a first layer of metal402, a second layer of metal404, and a third layer of metal406. The electromagnetic shielding100also includes a first layer of thermoplastic polymer fabric408and a second layer of thermoplastic polymer fabric410. The electromagnetic shielding100also includes a first layer of adhesive412, a second layer of adhesive414, a third layer of adhesive416, and a fourth layer of adhesive418. The first layer of adhesive412bonds the first layer of metal402with the first layer of thermoplastic polymer fabric408, the second layer of adhesive414bonds the first layer of thermoplastic polymer fabric408with the second layer of metal404, the third layer of adhesive416bonds the third layer of metal404with the second layer of thermoplastic polymer fabric410, and the fourth layer of adhesive418bonds the second layer of thermoplastic polymer fabric410with the third layer of metal406. Hence, the first layer of thermoplastic polymer fabric408is positioned between the first layer of metal402and the second layer of metal404, and the second layer of thermoplastic polymer fabric410is positioned between the second layer of metal404and the third layer of metal406. While the layers of adhesive are shown as being planar for purposes of illustration, it is to be understood that the adhesive need not be planarly applied; rather, adhesive in a pattern can be employed to adhere different layers to one another. A number of layers of thermoplastic polymer fabric and or layers of metal can be a function of thickness of such layers and a desired thickness of the electromagnetic shielding100. Accordingly, presuming that the layers of adhesive412-418have no measurable thickness and presuming the thermoplastic and metal layers each have 1 millimeter thickness, then when the thickness of the electromagnetic shielding100is desirably 20 millimeters, the electromagnetic shielding100may have 10 layers of thermoplastic polymer fabric and 10 layers of metal. Each layer of metal provides redundancy for purposes of electromagnetic shielding, such that if one layer of metal is damaged, other layers of metal can nevertheless provide electromagnetic shielding. While the electromagnetic shielding100depicted inFIG.4is illustrated as with the first layer of metal402and the third layer of metal406being exterior surfaces of the electromagnetic shielding100, in other embodiments a layer of thermoplastic polymer fabric may be at least one exterior surface of the electromagnetic shielding100. Pursuant to an example, both exterior surfaces of the electromagnetic shielding100may be layers of thermoplastic polymer fabric. FIG.4further depicts a press420that has perforating extensions422extending therefrom. Upon the layers of metal402-406and the layers of thermoplastic polymer fabric408-410being adhered together, the press420is applied to the adhered layers and the perforating extensions perforate the stacked layers402-410, such that the apertures102are formed through each of the layers402-410. As indicated above, the layers of metal402-406and the apertures formed by the press420are configured to attenuate, by a threshold amount (such as −85 dB), EMI having frequencies within a predefined range (such as between 9 kHz and 24 GHz). The layers of thermoplastic polymer fabric408-410are configured to provide structural support to the layers of metal402-406while additionally providing flexibility for the electromagnetic shielding100. Thus, as we will be described below, the electromagnetic shielding100can be draped over electronic equipment in a data center, where it is desirable to shield the electronic equipment from EMI having frequencies within the predefined range. FIG.5is a schematic of an environment500in a data center (such as a room in the data center) where electronic equipment is desirably shielded from EMI. The environment500includes a ceiling502and a floor504, where electronic equipment506(such as a server computing device, a rack of server computing devices, etc.) is supported by the floor504. The environment500further includes the electromagnetic shielding100, where the electromagnetic shielding100is draped over the electronic equipment506to shield the electronic equipment506from EMI. A plate508is coupled to the ceiling502by way of an attachment510, such as a rope, a plastic post anchored to the ceiling502, etc. In embodiments, the plate508, the attachment510, or both plate508and attachment510are nonconductive. The plate508supports the electromagnetic shielding100such that the electromagnetic shielding100is able to be draped over the electronic equipment506, while maintaining a desired separation distance between the electronic equipment506and the electromagnetic shielding100. For instance, a minimum separation distance of 150 millimeters can be maintained between the electromagnetic shielding100and the electronic equipment506. Anchors512can be employed to anchor the electromagnetic shielding100to the floor504to ensure that the electronic equipment506is enclosed by a combination of the electromagnetic shielding100and the floor504. In an example, when the electronic equipment506is positioned on an upper floor in a building, the floor504can be separately shielded. Typically, however, the electronic equipment506is positioned on a concrete slab on grade. The anchors512can also be employed to shape the electromagnetic shielding100as the electromagnetic shielding100is draped over the electronic equipment506, such that the threshold distance between the electromagnetic shielding100and the electronic equipment506is maintained. Further, the anchors512may be grounding anchors, such that current imparted upon the electromagnetic shielding100by EMI is directed to ground. The electromagnetic shielding100prevents EMI generated by the electronic equipment506from propagating to other electronic equipment in the data center. The electromagnetic shielding100is further configured to prevent EMI generated by other electronic equipment (or an outside source) from deleteriously affecting the electronic equipment506. As illustrated inFIG.5, the apertures102in the electromagnetic shielding100allow for air to flow from the region that is enclosed by the electromagnetic shielding100and the floor504to the exterior environment. Accordingly, standard hot aisle/cold aisle methods typically used in data centers can be employed while the electromagnetic shielding shields the electronic equipment506from EMI. Turning briefly toFIG.6, the environment500is illustrated, where support posts602extend from the floor504to support the electromagnetic shielding100. The support posts602provide physical support to the electromagnetic shielding100to prevent stretching of the fabric (and the apertures102). The support posts602can be formed of any suitable nonconductive material, such as a plastic. While not illustrated, in a situation where the electromagnetic shielding100must have a sharp corner (e.g., because of the nature or shape of the electronic equipment506that is to be shielded from EMI and/or physical constraints of the environment), a cornering bracket (or other suitable apparatus) can be used, and two separate pieces of electromagnetic shielding100can coupled to the bracket to prevent stretching of the electromagnetic shielding100. When a technician needs to access the electronic equipment506, the technician can remove the anchors512(if such anchors512are used) and lift the electromagnetic shielding100to obtain access to the electronic equipment506. Upon completing a maintenance task, the technician can replace the anchors512, such that the electromagnetic shielding100returns to being draped over the electromagnetic equipment506. WhileFIGS.5and6depict the electromagnetic shielding100being draped over the electronic equipment506, it is to be understood that the equipment that the electromagnetic shielding100may be wrapped around includes wires between the wrapped equipment, to prevent data leakage or EMI from such wires, even if they are not themselves wrapped with other electromagnetic shielding. FIGS.7and8illustrate exemplary methodologies relating to use and manufacture of electromagnetic shielding. While the methodologies are shown and described as being a series of acts that are performed in a sequence, it is to be understood and appreciated that the methodologies are not limited by the order of the sequence. For example, some acts can occur in a different order than what is described herein. In addition, an act can occur concurrently with another act. Further, in some instances, not all acts may be required to implement a methodology described herein. Now referring toFIG.7, a methodology700for shielding electronic equipment in a data center from EMI is illustrated. The methodology700starts at702, and at704electromagnetic shielding is obtained, where the electromagnetic shielding is in the form of a flexible netting. The electromagnetic shielding includes a layer of metal and a layer of thermoplastic polymer fabric that is adhered to the layer of metal by a suitable adhesive. As described previously, several apertures extend through the electromagnetic shielding, where the layer of metal and the several apertures are configured to attenuate EMI by at least a threshold amount when the EMI has a frequency within a predefined frequency range, while simultaneously enabling airflow through the electromagnetic shielding. In an example, when honeycomb cells of the electromagnetic shielding have approximately ⅛ inch major diameter and approximately 1 inch of thickness, when air flow is approximately 200 Feet Per Minute (FPM) there is a static pressure drop of 0.01; when air flow id approximately 800 FPM, there is a static pressure drop of 0.04. When honeycomb cells of the electromagnetic shielding have approximately 3/16 inch major diameter and approximately 1 inch of thickness, when air flow is approximately 200 FPM there is almost no static pressure drop, while when air flow is approximately 800 FPM there is a static pressure drop of 0.03. At706, the electronic equipment is at least partially covered with the electromagnetic shielding. As noted above, the electromagnetic shielding can be supported from above the electronic equipment and is draped over the electronic equipment. The methodology700completes at708. Now referring toFIG.8, a methodology800for manufacturing electromagnetic shielding is illustrated. The methodology800starts at802, and at804a layer of metal (such as aluminum foil) is adhered to a layer of thermoplastic polymer fabric (such as a woven polyethylene fabric). At806, the layer of metal and the layer of thermoplastic polymer fabric are perforated to create apertures that extend through the layer of metal and the layer of thermoplastic polymer fabric. The layer of metal and the several apertures are configured to attenuate EMI by a threshold amount when the EMI has a frequency within a predefined frequency range. As indicated previously, the apertures may be hexagonal, and may collectively form a honeycomb pattern. The methodology800completes at808. Features have been described herein in accordance with at least the following examples.(A1) In an aspect, electromagnetic shielding that is configured to attenuate EMI is described herein. The electromagnetic shielding includes a layer of metal, a layer of thermoplastic polymer fabric, and an adhesive that adheres the layer of metal to the layer of thermoplastic polymer fabric. Several apertures extend through the electromagnetic shielding, where the layer of metal and the several apertures are configured to attenuate EMI by a threshold amount when the EMI has a frequency within a predefined frequency range.(A2) In some embodiments of the electromagnetic shielding of (A1), the layer of metal is formed of aluminum, and the layer of metal has a thickness of between 0.01 millimeter and 10 millimeters.(A3) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A2), the layer of the thermoplastic polymer fabric is woven polyethylene fabric, and the layer of the thermoplastic polymer has a thickness of between 1 millimeter and 10 millimeters.(A4) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A3), the layer of metal includes a first surface and a second surface that is opposite the first surface, where the adhesive layer adheres the layer of thermoplastic polymer to the first surface of the layer of metal. Additionally, the electromagnetic shielding also includes a second layer of thermoplastic polymer fabric and second adhesive that adheres the second surface of the layer of metal to the second layer of thermoplastic polymer fabric such that the layer of metal is between the layer of thermoplastic polymer fabric and the second layer of thermoplastic polymer fabric.(A5) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A4), the electromagnetic shielding also includes a second layer of metal, where the layer of thermoplastic polymer fabric is positioned between the layer of metal and the second layer of metal.(A6) In some embodiments of the electromagnetic shielding of (A1), the electromagnetic shielding includes several layers of metal and several layers of thermoplastic polymer fabric, where each layer of metal is disposed between two layers of thermoplastic polymer fabric.(A7) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A6), the apertures are hexagonal.(A8) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A7), the several apertures are arranged to form a honeycomb pattern.(A9) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A8), each aperture in the several apertures has a major diameter of between 4 millimeters and 15 millimeters.(A10) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A9), the electromagnetic shielding has a thickness in a direction that is orthogonal to the layer of metal and the layer of thermoplastic material, the thickness being between 10 millimeters and 26 millimeters.(A11) In some embodiments of the electromagnetic shielding of at least one of (A1)-(A10), the apertures are formed in the electromagnetic shielding subsequent to the layer of metal being adhered to the layer of thermoplastic polymer fabric.(B1) In another aspect, a method for protecting electronic equipment from EMI includes obtaining electromagnetic shielding, where the electromagnetic shielding includes a layer of metal, a layer of thermoplastic polymer fabric that is adhered to the layer of metal, and several apertures that extend through the electromagnetic shielding. The layer of metal and the several apertures are configured to attenuate EMI by a threshold amount when the EMI has a frequency within a predefined frequency range. The method also includes at least partially covering the electronic equipment with the electromagnetic shielding.(B2) In some embodiments of the method of (B1), at least partially covering the electronic equipment includes supporting the electromagnetic shielding with a support mechanism that is positioned above the electronic equipment. The method also includes draping the electromagnetic shielding around the electronic equipment.(B3) In some embodiments of the method of (B2), the support mechanism is affixed to a ceiling.(B4) In some embodiments of at least one of the methods of (B1)-(B3), the method also includes coupling the electromagnetic shielding to a grounding rod.(B5) In some embodiments of at least one of the methods of (B1)-(B4), the electronic equipment is a server computing device within a data center.(B6) In some embodiments of at least one of the methods of (B1)-(B4), the electronic equipment is a rack of servers within a data center.(B7) In some embodiments of at least one of the methods of (B1)-(B6), the electromagnetic shielding has a thickness between 10 millimeters and 26 millimeters.(C1) In another aspect, a method for manufacturing electromagnetic shielding that is configured to attenuate EMI includes adhering a layer of metal to a layer of thermoplastic polymer fabric. The method also includes perforating the layer of metal and the layer of thermoplastic polymer fabric to create apertures that extend through the layer of metal and the layer of thermoplastic polymer fabric, where the layer of metal and the several apertures are configured to attenuate EMI by a threshold amount when the EMI has a frequency within a predefined frequency range.(C2) In some embodiments of the method of (C1), the threshold amount is between −70 and −90 dB of attenuation, and the predefined frequency range is 9 kHz-24 GHz. What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable modification and alteration of the above devices or methodologies for purposes of describing the aforementioned aspects, but one of ordinary skill in the art can recognize that many further modifications and permutations of various aspects are possible. Accordingly, the described aspects are intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim. | 24,588 |
11943907 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, like reference numerals designate identical or corresponding features throughout the several views. Various exemplary implementations of an RF-shielded window apparatus in accordance with the present disclosure are shown generally at100in the several drawings presented herewith. Referring toFIGS.25,26and68, an RF-shielded window apparatus100may comprise a primary panel element110. Referring toFIGS.12,13and65, the primary panel element110may include a primary backing substrate114a, a primary shielding adhesion strip124a, a protective layer132, a primary RF shield layer128a, and a protective adhesion strip136. Referring toFIG.1, the primary backing substrate114amay have a primary peripheral edge120adefined thereabout, a primary inboard face116aand a primary outboard face118a. Referring toFIG.13, the primary shielding adhesion strip124amay extend along the primary peripheral edge120a, and may be in adhesive communication with the primary inboard face116aand primary outboard face118a. Referring toFIG.29, the primary shielding adhesion strip124amay be comprised of multiple individual strip segments. Referring toFIG.7, the protective layer132may have a protective inboard face152and a protective outboard face154. Referring toFIGS.6and13, the primary RF shield layer128amay have a primary shield periphery144aand may be disposed between the primary backing substrate114aand the protective layer132. The protective adhesion strip136may extend along the primary peripheral edge120aand may be in adhesive communication with the protective outboard face154and the primary shield periphery144a. Referring toFIGS.25,26and68, particular implementations of an RF-shielded window apparatus100may further comprise a secondary panel element112. Referring toFIGS.21and22, the secondary panel element112may include a secondary backing substrate114b, a secondary shielding adhesion strip124b, and optionally a secondary RF shield layer128b. Referring toFIGS.14and36, the secondary backing substrate114bmay have a secondary peripheral edge120bdefined thereabout, a secondary inboard face116band a secondary outboard face118b. Referring toFIGS.22, the secondary shielding adhesion strip124bmay extend along the secondary peripheral edge120band may be in adhesive communication with the secondary inboard face116band secondary outboard face118b. Referring toFIGS.36and44, the secondary shielding adhesion strip124bmay be comprised of multiple individual strip segments. Referring toFIGS.20and21, the secondary RF shield layer128bmay have a secondary shield periphery144band being disposed across the secondary inboard face116b. Referring toFIGS.25,26and65, in certain preferred implementations of the RF-shielded window apparatus100, the first panel element110and the second panel element112may be secured to one another such that the primary RF shield layer128a, the secondary RF shield layer128band the protective layer132are collectively disposed between the primary backing substrate114aand the secondary backing substrate114b. In particular such implementations, the primary RF shield layer128aand the secondary RF shield layer128bmay be in electrically-conductive communication with one another. By way of example, the electrically-conductive communication may be by way of, for example, the protective adhesion strip136. Referring toFIGS.24-26and68, the RF-shielded window apparatus100may further comprise a panel joining strip138facilitating the securement of the first panel element110to the second panel element112. In such case, the electrically-conductive communication between the primary RF shield layer128aand the secondary RF shield layer128bmay preferably be at least in part by way of the panel joining strip138. Referring toFIGS.33and35, in particular implementations of the RF-shielded window apparatus100, the primary RF shield layer128amay be comprised of a metallic mesh of interconnected primary shield filaments148adefining primary shield voids150atherebetween. Similarly, referring toFIGS.39and41, the secondary RF shield layer128bmay be comprised of a metallic mesh of interconnected secondary shield filaments148bdefining secondary shield voids150btherebetween. In particular such implementations of the RF-shielded window apparatus100, the primary shield voids150aare larger than the secondary shield voids150b. In alternate implementations of the RF-shielded window apparatus100, the primary shield voids150aare smaller than the secondary shield voids150b. In certain implementations of the RF-shielded window apparatus100, the primary RF shield layer128ais comprised of copper, and the secondary RF shield layer128bis comprised a copper and nickel. In particular implementations of the RF-shielded window apparatus100, the primary backing substrate114amay have a thickness of from 1/16 to ⅛ inches, and the secondary backing substrate114bmay have a thickness of from ¼ to ½ inches. Referring toFIGS.25,27and28, certain implementations the RF-shielded window apparatus100may include a light transmission zone156within which visible light can pass through the entire RF-shielded window apparatus100along a light transition axis140. In such implementations, the RF-shielded window apparatus100may have a visible transmittance of at least 70% within the light transmission zone156. The primary backing substrate114amay preferably be comprised of polycarbonate or the like, and in certain preferred implementations, may have a thickness122aof 1/16 to ⅛ inches. The secondary backing substrate114bmay preferably be comprised of polycarbonate or the like, and in certain preferred implementations, may have a thickness122bof ¼ to ½ inches. The protective layer132may preferably be comprised of polyethylene terephthalate (PET), thermoplastic polyurethane (TPU), or laminated tempered glass. In certain preferred implementations of the apparatus100, the protective adhesion strip136, the panel joining strip138may comprise one or more segments of electrically-conductive adhesive tape. The shielding adhesion strips may preferably comprise, for example, electrically-conductive two-sided adhesive tape, or the like. Referring toFIG.69, a method of manufacturing an RF-shielded window apparatus is shown generally at200. At block210, a primary panel element110is formed by way of a series of one or more of the steps represented, for example, by blocks212-224. At block212, a primary backing substrate114a, a primary shielding adhesion strip124a, a protective layer132, and a protective adhesion strip136are provided. The primary backing substrate114amay have a primary peripheral edge120adefined thereabout, a primary inboard face116aand a primary outboard face118a. The protective layer132may have a protective inboard face152and a protective outboard face154. At block214, and referring toFIGS.1,2and29, the primary shielding adhesion strip124amay be placed in adhesive communication with the primary inboard face116aand extending partly outward of the primary peripheral edge120a, thereby defining a primary adhesion edge158aoutward of the primary peripheral edge120a. At block216, and referring toFIGS.4,52and53, the primary shielding adhesion strip124amay be positioned in adhesive communication with a precursor sheet of primary RF shielding material202awhile the precursor sheet of primary RF shielding202ais subject to an in-plane tensile loading130. At block218, and referring toFIGS.5,6and55, the precursor sheet of primary RF shielding202amay be trimmed to terminate at the primary adhesion edge158a, thereby defining a primary RF shield layer128aadhered to the primary inboard face116aby way of the primary shielding adhesion strip124a. Referring toFIG.8, the primary RF shield layer128amay have a primary shield periphery144a. At block220, and referring toFIGS.7and8, the protective layer132may be applied onto the primary RF shield layer128a. A squeegee208or the like may be used to apply the protective layer132. Referring toFIGS.9and60, a protective outer peel layer (e.g., film)134may be peeled off of the protective layer132. At block222, and referring toFIGS.9,10and59, the primary shielding adhesion strip124amay be wrapped around the primary peripheral edge120aand onto the primary outboard face118a. At block224, and referring toFIGS.11-13and61-63, the protective adhesion strip136may be affixed to the protective outboard face154and the protective adhesion strip136may be wrapped around the primary peripheral edge120a, whereby the protective adhesion strip136may preferably be retained in electrically-conductive communication with the primary RF shield layer128a. The method200may further one or more steps shown at block226, wherein a secondary panel element112is formed by way of a series of one or more of the steps represented, for example, by blocks228-236. At block228, and referring toFIGS.14and44, a secondary backing substrate114band a secondary shielding adhesion strip124bmay be provided, wherein the secondary backing substrate114bmay have a secondary peripheral edge120bdefined thereabout, a secondary inboard face116band a secondary outboard face118b. At block230, and referring toFIGS.14-17,36and45, the secondary shielding adhesion strip124bmay be placed in adhesive communication with the secondary inboard face116band extending partly outward of the secondary peripheral edge120b, thereby defining a secondary adhesion edge outward of the secondary peripheral edge158b. As shown inFIGS.16and46, adhesive backing may be peeled from the adhesions strip124bto expose the underlying adhesive. At block232, and referring toFIGS.17and47, the secondary shielding adhesion strip124bmay be positioned in adhesive communication with a precursor sheet of secondary RF shielding material202bwhile the precursor sheet of secondary RF shielding is subject to an in-plane tensile loading130. At block234, and referring toFIGS.19,20,48and49, the precursor sheet of secondary RF shielding202bmay be trimmed to terminate at the secondary adhesion edge158b, thereby defining a secondary RF shield layer128badhered to the secondary inboard face116bby way of the secondary shielding adhesion strip124b. The secondary RF shield layer128bmay have a secondary shield periphery144b. At block236, and referring toFIGS.21,22and50, the secondary shielding adhesion strip124bmay be wrapped around the secondary peripheral edge120band onto the secondary outboard face118b. At block238, and referring toFIGS.23-26,64and65, the primary panel element110may be secured to the secondary panel element112such that the primary RF shield layer128a, the secondary RF shield layer128band the protective layer132are collectively disposed between the primary backing substrate114aand the secondary backing substrate114b. As a result of this step of securing (or potentially by other means), the primary RF shield layer128aand the secondary RF shield layer128bmay be in electrically-conductive communication with one another. Moreover, this electrically-conductive communication may preferably be by way of the protective adhesion strip136. At block240, and referring toFIGS.24-26and66-68, after the step of securing, a panel joining strip138may be applied in adhesive communication with the protective adhesion strip136and the secondary RF shield layer128b, thereby facilitating securement of the first panel element110to the second panel element112, and placing the panel joining strip138into electrically-conductive communication with the primary RF shield layer128aand secondary RF shield layer128b. RF Shielding Materials In certain preferred embodiments of the window apparatus, two RF shielding materials may be used to achieve higher clarity and high RF attenuation. The first material could be a copper mesh with areal density of 60-80 g/m2 and open area percentage of 80-90%. In other embodiments, the copper mesh may have a higher or lower areal density, and open area percentage, or may not necessarily be copper-based. The second material may be a nickel copper mesh, with any metal ratio that accomplishes a high level of RF shielding, with areal density of 20-50 g/m2, and thickness between 0.06 and 0.1 mm. In other embodiments, the copper/nickel mesh may have a higher or lower areal density, may be thinner or thicker, or may not necessarily be copper/nickel-based. In alternate embodiments, three or more layers of RF shielding material may be used, or layers that do not necessarily keep to the same specifications as those stated in the preferred embodiment. For example, two layers of copper mesh may be used, or two layers of nickel/copper mesh, or a nickel/copper mesh with a higher open area percentage with a copper mesh of a lower open area percentage. In alternate embodiments another RF shielding material may be used, such as carbon nano-fiber, silver, aluminum, or others. Challenges to Maintaining High Clarity Through Continued Usage of the Apparatus In the desired application of the disclosed apparatus, maintaining high clarity may be important. Aside from the importance of the RF shielding materials used, certain characteristics of the materials, which may be primarily flexible, may introduce challenges to the goal of high clarity. Typical issues with achieving high clarity may include waviness of the materials, creases, punctures, imperfections, etc. To overcome these issues, it may be important to ensure that the RF shielding materials become completely flat and blemish free, and most importantly, maintain that state permanently throughout usage of the product. In the past this may be difficult to achieve. Prior art and products in the market may not only offer lower clarity, but also may exhibit unstable window conditions where prolonged usage of the product can generate waviness, imperfections, and blemishes. A particular challenge to the practical usage of an RF shielded window might also be the thickness of the overall constructed window. Impractical prior art and products might present an RF shielded window with overall thickness that could require special mounting hardware and processes, and simply may be impractical when using with an RF enclosure such as is mentioned in this disclosure. The disclosed invention and manufacturing method of same may overcome the challenges of thickness of the overall constructed window, as well as maintaining high clarity and low blemishes through continued usage of the apparatus. Other Materials that May be Used to Construct the Apparatus, and Perform Manufacturing Method In the preferred embodiment, RF shielding materials may be combined with other materials, as described below. Copper Panel (Copper Mesh+Polycarbonate+Screen Protector) In a preferred embodiment, the copper mesh material may be “mounted” to a backing material that can allow it to become flat and maintain that state throughout usage of the product. The “backing material” (which may be otherwise referred to herein as a “backing substrate”) for this RF shielding material may be clear, such as polycarbonate, but may not necessarily need to maintain a high level of rigidity. In the preferred embodiment, the thickness of the polycarbonate material may be between 1/16″ and ⅛.″ To initially flatten the copper mesh and reduce visible imperfections, the copper mesh may first be stretched on a device, such as a silk screen panel stretcher. Conductive two-sided adhesive may be placed around the edges of the polycarbonate backing material, partly on the material and partly hanging off of the edge. This border may create an adhesive outer “frame” for the copper mesh to adhere to, but not within the inner visible portion of the window. The additional adhesive that hangs off the edge of the frame may provide an extra portion of copper mesh that could be “wrapped” around the edge of the backing material to provide more adhesive surface area, thereby decreasing the ability of the copper mesh to become undone from the adhesive and allowing for wrinkles or blemishes. Even still, another material may be required to keep the copper mesh stretched over time throughout continued usage of the product. This material may be referred to herein as a “protective layer,” which in some cases may be a screen protector commonly used for protecting phone/tablet screens during usage. A screen protector may provide high clarity while also just enough adhesive to keep the copper mesh from becoming wrinkled, but not so much adhesive that clarity is affected. The adhesive on the screen protector may hold the copper mesh in place, and may also push through the open areas to adhere to the backing material, even further holding the copper mesh in place. Other types of adhesives, such as optically clear liquid adhesive, may still reduce clarity, may introduce bubbles, or may incur increased costs/challenges during manufacturing. In the preferred embodiment, the application of the screen protector material may be simple, easier to deploy in manufacturing, and cheaper to purchase, thereby becoming a very desirable element of the overall construction of the disclosed RF shielded window. In alternate embodiments, the backing material may not be polycarbonate, but may be another material that offers clarify and a certain level of rigidity, such as glass. It may not be within the range of thickness mentioned, but instead may be thicker or thinner. A screen protector may not necessarily be used to keep the RF shielding layer in place and to reduce waves or blemishes, but instead another material could be used such as optically clear double sided adhesive, liquid adhesive, or not at all. In alternate embodiments the RF shielding material may be pressed between multiple layers of a backing material, or even may be embedded in another material, such as being embedded in a sheet of polycarbonate during the polycarbonate manufacturing process. Copper/Nickel Panel (Copper/Nickel Mesh+Polycarbonate) In certain preferred embodiments, the copper/nickel mesh material may be “mounted” to a backing material that can allow it to become flat and maintain that state throughout usage of the product. The “backing material” for this RF shielding material may be clear, such as polycarbonate, and may need to maintain a high level of rigidity. In the preferred embodiment, the thickness of the polycarbonate material may be between ¼″ and ½″. To initially flatten the copper/nickel mesh and reduce visible imperfections, the material may first be stretched on a device, such as a silk screen panel stretcher. Conductive two-sided adhesive may be placed around the edges of the polycarbonate backing material, partly on the material and partly hanging off of the edge. This border may create an adhesive outer “frame” for the copper/nickel mesh to adhere to, but not within the inner visible portion of the window. The additional adhesive that hangs off the edge of the frame may provide an extra portion of copper/nickel mesh that could be “wrapped” around the edge of the backing material to provide more adhesive surface area, thereby decreasing the ability of the copper/nickel mesh to become undone from the adhesive and allowing for wrinkles or blemishes. In alternate embodiments, the backing material may not be polycarbonate, but may be another material that offers clarify and a certain level of rigidity, such as glass. It may not be within the range of thickness mentioned, but instead may be thicker or thinner. In alternate embodiments the RF shielding material may be pressed between multiple layers of a backing material, or even may be embedded in another material, such as being embedded in a sheet of polycarbonate during the polycarbonate manufacturing process. Combine RF Shielding Layers into Assembled Window In certain preferred embodiments, two separate “panels” (which may be referred to herein as “panel elements”) may be created from two separate RF shielding materials, when combined with their backing materials and screen protector. These panels may then be combined together to assemble into a single unit. Double sided conductive adhesive may be placed on top of the screen protector that is positioned onto the Copper panel, around the border edges. This adhesive can be used to join the two panels together and hold them tightly. The Copper/nickel panel can be positioned with RF shielding material inside and polycarbonate material facing outside, against the Copper panel, also with RF shielding material inside and polycarbonate facing outside, and joined together. In this configuration, the innermost layers could be the screen protector from the Copper panel as well as the double-sided adhesive border joining both panels. When the screen protector is positioned between the RF shielding layers, it can provide protection of each of the RF shielding layers, as well as a thin layer of decoupling that can increase the level of RF shielding capability of the full final window assembly. To further ensure that the panels can be joined permanently into a single RF shielded window unit, and to ensure that conductivity is maintained between both RF shielding layers, conductive tape can be wrapped around the edges of the assembled unit, joining the RF shielding materials in both panels together conductively. The assembled window unit can then be installed into a metal frame that compresses all outer border edges of the window unit, using mechanical fasteners, such as threaded posts and nuts, at regular intervals. This metal frame can be part of the installation of an RF shielded enclosure, allowing the window to join the conductivity of the enclosure, or may be separate to provide for a rigid structure that can be integrated into other RF enclosures. For example, this metal frame may provide the outermost assembly component for this assembled window to be sold separately for integration into customer applications, such as shielded rooms or cabinets. In alternate embodiments there may not only be two panels, but may instead be three or more, with different or similar RF shielding materials and/or backing materials. For example, two panels copper/nickel mesh as well as a panel of copper mesh may be combined together. The panels may not actually be panels at all, but may instead be round, convex, flexible, or any other configuration or shape. For example, RF shielding materials may be combined with backing materials to create a convex RF shielded window that allows for various advantages for the user. When the panels or other materials are combined together, alternate embodiments may employ a different material than double sided adhesive to bind them together, or may use no adhesive at all. For example, they layers may simply be combined together and they may still offer roughly the same RF shielding as well as durability characteristics. They may be mechanically bound together using screws that sink directly into the backing material, or may be integrated into a final assembly that does not require adhesive or mechanical fasteners. The screen protector mentioned in the preferred embodiment may not necessarily exist between the RF shielding layers, and the RF shielding layers may instead be positioned against each other. The final assembly may not necessarily require an outer metal frame, but may instead exist without frame, or may use another material other than metal, such as plastic. The outer frame may not have regularly spaced mechanical fasteners to compress the panels, but may instead have a continuous edge or no edges at all. Notably, the distance between both shielding layers may be an important factor in the shielding. The RF shield layers should not be too far apart, or RF waves can pass through the layers more easily. They are close together to achieve a particular attenuation at particular frequencies. Preferably however, they are slightly decoupled by the thickness of the protective layer. This should enhance the attenuation by creating redundancy (vs. the RF shield layers joining together to effectively become one single shielding layer). The following listing matches certain terminology used within this disclosure with corresponding reference numbers used in the non-limiting examples illustrated in the several figures.100RF-shielded window apparatus102RF-shielded enclosure (e.g., box, room, lab or tent comprising an RF-shielded window apparatus)104electronic device (e.g., cell phone, tablet or laptop housed within the RF-shielded enclosure)106ambient environment108viewpoint110panel element (e.g., primary panel element)112panel element (e.g., secondary panel element)114aprimary backing substrate (e.g., polycarbonate; e.g., 1/16-⅛ inches thick)114bsecondary backing substrate (e.g., polycarbonate; e.g., ¼-½ inches thick)116aprimary inboard face (of primary backing substrate)116bsecondary inboard face (of secondary backing substrate)118aprimary outboard face (of primary backing substrate)118bsecondary outboard face (of secondary backing substrate)120aprimary peripheral edge (of primary backing substrate)120bsecondary peripheral edge (of secondary backing substrate)122athickness (of primary backing substrate; e.g., 1/16-⅛ inches)122bthickness (of secondary backing substrate; e.g., ¼-½ inches)124aprimary shielding adhesion strip (e.g., segments of electrically conductive two-sided adhesive tape)124bsecondary shielding adhesion strip (e.g., segments of electrically conductive two-sided adhesive tape)126outer peel layer (of shielding adhesion strip)128aprimary RF shield layer (e.g., copper mesh, nickel-copper mesh or the like)128bsecondary RF shield layer (e.g., copper mesh, nickel-copper mesh or the like)130tension direction (in-plane tensile loading)132protective layer (e.g., screen protector; e.g., polyethylene terephthalate (PET), thermoplastic polyurethane (TPU), or laminated tempered glass)134protective outer peel layer136protective adhesion strip (e.g., segments of electrically-conductive adhesive tape)138panel joining strip (e.g., segments of electrically-conductive adhesive tape)140light transmission axis (of RF-shielded window apparatus)142aprimary panel axis142bsecondary panel axis144aprimary shield periphery144bsecondary shield periphery146thickness of protective layer148aprimary shield filament148bsecondary shield filament150aprimary shield void (i.e., spacing between filaments)150bsecondary shield void (i.e., spacing between filaments)152protective inboard face (of protective layer)154protective outboard face (of protective layer)156light transmission zone158aprimary adhesion edge158bsecondary adhesion edge200method of manufacturing an RF-shielded window apparatus202aprecursor sheet of primary RF shielding material (e.g., electrically-conductive mesh)202bprecursor sheet of secondary RF shielding material (e.g., electrically-conductive mesh)204shielding stretching device (e.g., silk screen panel stretcher)206cutting device (e.g., blade)208squeegee210-240example steps of certain implementations of method200300template guide lines (for placement of adhesion strips)302template tool While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention. | 27,561 |
11943908 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “in,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As feature sizes of semiconductor devices continue to shrink, various problems may emerge in device fabrication. For SRAM devices, as the memory cell size becomes smaller, individual components in the memory cell, such as transistors, active areas of the transistors, intra-cell connections, and contacts, would naturally need to become smaller. However, current lithography and etching techniques limit how much the individual components can be shrunk. Thus, a memory cell of a SRAM device that includes a large density of components often has overlay problems. Any overlay would lead to a short circuit between different components and may cause device failure. FIG.1depicts an example diagram of a six-transistor (6-T) SRAM cell, in accordance with some embodiments. As shown inFIG.1, the SRAM cell100includes two pull-up transistors102(“PU1”) and104(“PU2”), two pull-down transistors106(“PD1”) and108(“PD2”), and two pass-gate transistors110(“PG1”) and112(“PG2”). The transistors102,104,106and108are connected in cross-coupled inverter configuration. That is, the transistors102and106form a first inverter, and the transistors104and108form a second inverter. Gate terminals of the pass-gate transistors110and112are both configured to receive a word-line signal122(“WL”). A pair of complementary bit lines124(“BL”) and126(“BLB”) are coupled to source/drain regions of the pass-gate transistors110and112respectively. The pass-gate transistors110is coupled to the pull-up transistor102and the pull-down transistor106at a node130, and the pass-gate transistors112is coupled to the pull-up transistor104and the pull-down transistor108at another node132. For example, the pull-up transistors102and104are P-channel transistors, and the pull-down transistors106and108are N-channel transistors. The pass-gate transistors110and112are N-channel transistors. FIG.2(A)depicts an example layout diagram of the SRAM cell as shown inFIG.1, in accordance with some embodiments. As shown inFIG.2(A), the transistors102,104,106and108are interconnected (e.g., through metal contacts, contact bars, or slot contacts). A source/drain region202of the transistor102(“PU1”) is connected to a source/drain region204of the transistor106(“PD1”) through a conduction structure230that corresponds to the node130. A source/drain region206of the transistor104(“PU2”) is connected to a source/drain region208of the transistor108(“PD2”) through a conduction structure232that corresponds to the node132. Furthermore, an intra-connection structure214connects a gate structure210of the transistor102(“PU1”) and the source/drain region206of the transistor104(“PU2”) laterally, so as to avoid overlay problems associated with vertical connection structures. As the intra-connection structure214is disposed laterally between the gate structure210and the source/drain region206, the intra-connection structure214may not come into contact with a conduction structure244associated with a source/drain region252of the pass-gate transistor112(“PG2”) or a conduction structure246associated with a source/drain region250of the transistor102(“PU1”). Similarly, another intra-connection structure216connects a gate structure212of the transistor104(“PU2”) and the source/drain region202of the transistor102(“PU1”) laterally. As the intra-connection structure216is disposed laterally between the gate structure212and the source/drain region202, the intra-connection structure216may not come into contact with a conduction structure240associated with a source/drain region234of the pass-gate transistor110(“PG1”) or a conduction structure242associated with a source/drain region236of the transistor104(“PU2”). For example, the conduction structure230and the conduction structure232include one or more conductive materials (e.g., metal-based materials). The intra-connection structure214and the intra-connection structure216include one or more conductive materials (e.g., metal-based materials). The gate structure210and the gate structure212include one or more conductive materials (e.g., metal-based materials, polysilicon). FIG.2(B)depicts an example diagram showing the intra-connection structure216, in accordance with some embodiments. As shown inFIG.2(B), the gate structure210of the transistor102(“PU1”) is electrically connected to the source/drain region206of the transistor104(“PU2”) through the intra-connection structure216. Specifically, the intra-connection structure216is in contact with one side of the gate structure212of the transistor104(“PU2”). FIG.3(A)depicts another example layout diagram of the SRAM cell as shown inFIG.1, in accordance with some embodiments. As shown inFIG.3(A), the transistors102,104,106and108are interconnected (e.g., through metal contacts, contact bars, or slot contacts), similar toFIG.2(A). An intra-connection structure294connects the gate structure210of the transistor102(“PU1”) and the source/drain region206of the transistor104(“PU2”) laterally. Similarly, another intra-connection structure296connects the gate structure212of the transistor104(“PU2”) and the source/drain region202of the transistor102(“PU1”) laterally. FIG.3(B)depicts an example diagram showing the intra-connection structure296, in accordance with some embodiments. As shown inFIG.3(B), the gate structure210of the transistor102(“PU1”) is electrically connected to the source/drain region206of the transistor104(“PU2”) through the intra-connection structure296. Specifically, the intra-connection structure296is in contact with one side and an end of the gate structure212of the transistor104(“PU2”). FIG.4(A)-FIG.4(D)depict example diagrams showing a process for fabricating a device structure including an intra-connection structure, in accordance with some embodiments. One or more fabrication processes (e.g., lithography, deposition, and/or etching) may be carried out to yield a structure as shown inFIG.4(A). For example, a sacrificial dielectric material (e.g., an insulating material320) that is formed between multiple gate structures (e.g., the gate structures302,304,306and308) is removed (e.g., through etching) after a lithography process. One or more source/drain regions (e.g., the source/drain regions312and314) are disposed between the gate structures and—exposed at least partially after the removal of the sacrificial dielectric material. A spacer material is disposed on each gate structure. As shown inFIG.4(A), the spacer material310covers at least part of the gate structure304, e.g., on a top surface and sidewalls of the gate structure304. For example, the spacer material310includes a dielectric material (e.g., silicon nitride). Another lithography process is performed, and part of the spacer material310is removed (e.g., through etching) to expose part of the gate structure304, as shown inFIG.4(B). For example, the spacer material310on the top surface of the gate structure304is partially removed. In addition, the spacer material310on a side wall of the gate structure304adjacent to the source/drain region312is removed. A conductive material330is formed (e.g., through lithography, deposition, etc.) on the gate structures and the source/drain regions. Chemical-mechanical planarization (CMP) is performed to remove part of the conductive material330, as shown inFIG.4(C). The conductive material330is in contact with the exposed gate structure304and the exposed source/drain regions312and is configured to electrically connect the gate structure304and the source/drain regions312. For example, the conductive material330covers part of the top surface of the gate structure304. Another conductive material is formed (e.g., through lithography, deposition, etc.) to fabricate multiple vertical conduction structures (e.g., vias). As shown inFIG.4(D), a vertical conduction structure340(e.g., a via) is formed on the conductive material330between the gate structure302and the gate structure304, and another vertical conduction structure342(e.g., a via) is formed on the conductive material330between the gate structure306and the gate structure308. The conductive material330between the gate structure304and the gate structure306serves as an intra-connection structure (e.g., the intra-connection structure214or the intra-connection structure216as shown inFIG.2(A), the intra-connection structure294or the intra-connection structure296as shown inFIG.3(A)). FIG.5depicts an example diagram showing a top view of the device structure as shown inFIG.4(D), in accordance with some embodiments. As shown inFIG.4(D)andFIG.5, the conduction structures340and342have a smaller width at the bottom to reduce the risk of contacting the intra-connection structure that includes the conductive material330between the gate structures304and306. The cross-sectional view shown inFIG.4(D)is associated with the cutline402. FIG.6(A)-FIG.6(D)depict example diagrams showing another process for fabricating a device structure including an intra-connection structure, in accordance with some embodiments. One or more fabrication processes (e.g., lithography, deposition, and/or etching) may be carried out to yield a structure as shown inFIG.6(A). For example, a sacrificial dielectric material (e.g., an insulating material520) that is formed between multiple gate structures (e.g., the gate structures502,504,506and508) is removed (e.g., through etching) after a lithography process. One or more source/drain regions (e.g., the source/drain regions512and514) are disposed between the gate structures and exposed at least partially after the removal of the sacrificial dielectric material. A spacer material is disposed on each gate structure. As shown inFIG.6(A), the spacer material510covers at least part of the gate structure504, e.g., on a top surface and sidewalls of the gate structure504. For example, the spacer material510includes a dielectric material (e.g., silicon nitride). Another lithography process is performed, and part of the spacer material510is removed (e.g., through etching) to expose part of the gate structure504, as shown inFIG.6(B). For example, the spacer material510on the top surface of the gate structure504is partially removed. In addition, the spacer material510on a side wall of the gate structure504adjacent to the source/drain region512is removed. A conductive material530is formed (e.g., through lithography, deposition, etc.) on the gate structures and the source/drain regions. A CMP process is performed to remove part of the conductive material530, as shown inFIG.6(C). The conductive material530is in contact with the exposed gate structure504and the exposed source/drain regions512and is configured to electrically connect the gate structure504and the source/drain regions512. For example, the conductive material530covers part of the top surface of the gate structure504. In certain embodiments, after the CMP process, the conductive material530does not cover any part of the top surface of the gate structure504, and is disposed completely between the gate structure504and the source/drain regions512. A dielectric material (e.g., an insulating material)550is formed (e.g., through deposition, etc.) to cover the gate structures. Another conductive material is formed (e.g., through lithography, deposition, etc.) to fabricate multiple vertical conduction structures (e.g., vias). As shown inFIG.6(D), a vertical conduction structure540(e.g., a via) is formed on the conductive material530between the gate structure502and the gate structure504, and another vertical conduction structure542(e.g., a via) is formed on the conductive material530between the gate structure506and the gate structure508. The conductive material530between the gate structure504and the gate structure506serves as an intra-connection structure (e.g., the intra-connection structure214or the intra-connection structure216as shown inFIG.2(A), the intra-connection structure294or the intra-connection structure296as shown inFIG.3(A)). FIG.7depicts an example diagram showing a top view of the device structure as shown inFIG.6(D), in accordance with some embodiments. As shown inFIG.6(D)andFIG.7, the intra-connection structure that includes the conductive material530between the gate structures504and506may not come into contact with the conduction structures540and542. The cross-sectional view shown inFIG.6(D)is associated with the cutline602. FIG.8(A)-FIG.8(D)depict example diagrams showing another process for fabricating a device structure including an intra-connection structure, in accordance with some embodiments. One or more fabrication processes (e.g., lithography, deposition, and/or etching) may be carried out to yield a structure as shown inFIG.8(A). For example, a sacrificial dielectric material (e.g., an insulating material720) that is formed between multiple gate structures (e.g., the gate structures702,704,706and708) is removed (e.g., through etching) after a lithography process. One or more source/drain regions (e.g., the source/drain regions712and714) are disposed between the gate structures and exposed at least partially after the removal of the sacrificial dielectric material. A spacer material is disposed on each gate structure. As shown inFIG.8(A), the spacer material710covers at least part of the gate structure704, e.g., on a top surface and sidewalls of the gate structure704. Another lithography process is performed, and part of the spacer material710is removed (e.g., through etching) to expose part of the gate structure704, as shown inFIG.8(B). For example, the spacer material710on the top surface of the gate structure704is partially removed. In addition, the spacer material710on a side wall of the gate structure704adjacent to the source/drain region712is removed. A conductive material730is formed (e.g., through lithography, deposition, etc.) on the gate structures and the source/drain regions. A CMP process is performed to remove part of the conductive material730, as shown inFIG.4(C). The conductive material730is in contact with the exposed gate structure704and the exposed source/drain regions712and is configured to electrically connect the gate structure704and the source/drain regions712. For example, the conductive material730covers part of the top surface of the gate structure704. In certain embodiments, after the CMP process, the conductive material730does not cover any part of the top surface of the gate structure704, and is disposed completely between the gate structure704and the source/drain regions712. A dielectric material (e.g., an insulating material)750is formed (e.g., through deposition, etc.) to cover the gate structures. Another conductive material is formed (e.g., through lithography, deposition, etc.) to fabricate multiple vertical conduction structures (e.g., vias). As shown inFIG.8(D), a vertical conduction structure740(e.g., a via) is formed on the conductive material730between the gate structure702and the gate structure704, and another vertical conduction structure742(e.g., a via) is formed on the conductive material730between the gate structure706and the gate structure708. The conductive material730between the gate structure704and the gate structure706serves as an intra-connection structure (e.g., the intra-connection structure214or the intra-connection structure216as shown inFIG.2(A), the intra-connection structure294or the intra-connection structure296as shown inFIG.3(A)). Higher level vertical conduction structures760and762(e.g., vias) may be fabricated (e.g., through lithography, deposition, etc.) on the conduction structures740and742respectively, as shown inFIG.8(E). FIG.9depicts an example diagram showing a top view of the device structure as shown inFIG.8(E), in accordance with some embodiments. As shown inFIG.9, the conduction structures740and742extend parallel to the gate structures, and may be used for interconnection between different active regions. The intra-connection structure that includes the conductive material730between the gate structures704and706may not come into contact with the conduction structures740,742,760and762. The cross-sectional view shown inFIG.8(E)is associated with the cutline802. FIG.10(A)depicts an example diagram showing a cross-sectional view of a device structure including an intra-connection structure, in accordance with some embodiments. The device structure900includes an intra-connection structure902between a gate structure904and a source/drain region906. In addition, the device structure900includes different vertical conduction structures. As shown inFIG.10(A), a vertical conduction structure908that includes a single conductive material may be formed through a process similar to what is shown inFIG.6(A)-FIG.6(D). Another vertical conduction structure910that includes two layers of conductive materials may be formed through a process similar to what is shown inFIG.8(A)-FIG.8(E).FIG.10(B)depicts an example diagram showing a top view of the device structure as shown inFIG.10(A), in accordance with some embodiments. The cross-sectional view shown inFIG.10(A)is associated with the cutline910. FIG.11(A)-FIG.11(E)depict example diagrams showing different masks for fabricating a device structure including an intra-connection structure, in accordance with some embodiments. As shown inFIG.11(A)-FIG.11(E), the masks1100,1102,1104,1106and1108can all be used for defining an intra-connection structure by removing part of a spacer material on a gate structure. Specifically, the mask1100includes simple pattern shapes with small pattern areas, and the mask1102may be implemented by a single patterning. In addition, the mask1104includes simple shapes with large pattern areas, and both the mask1106and the mask1108include large pattern areas. FIG.12depicts an example flow chart for fabricating a device structure including an intra-connection structure, in accordance with some embodiments. At1202, a first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate (e.g., “OD” inFIGS.4(A) through10(B)). A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. At1204, the first dielectric material is removed to expose at least part of the first source/drain region. At1206, at least part of the spacer material is removed to expose at least part of the first gate structure. At1208, a first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure. According to one embodiment, a method is provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure. According to another embodiment, a structure includes: a first gate structure formed on a substrate, a first source/drain region adjacent to the first gate structure, and a first conductive material formed between the first gate structure and the first source/drain region. The first conductive material is in contact with part of the first gate structure and in contact with part of the first source/drain region. According to yet another embodiment, a device includes: a gate structure associated with a first transistor, a source/drain region associated with a second transistor, the source/drain region being adjacent to the gate structure, and an intra-connection conductive material disposed in contact with a sidewall of the first gate structure and a top surface of the first source/drain region. In an embodiment, a device comprises: a first pull-up transistor comprising a first source/drain region and a first gate structure; a second pull-up transistor comprising a second source/drain region and a second gate structure; a first contact contacting the first source/drain region, the first contact extending into a second side of the second gate structure, the first contact physically contacting a top surface and an entirety of a sidewall of the second gate structure; a first spacer separating the first contact from a first side of the first gate structure, top surfaces of the first spacer and the first contact being coplanar; a second contact contacting the second source/drain region, the second contact extending into the first side of the first gate structure, the second contact physically contacting a top surface and an entirety of a sidewall of the first gate structure; and a second spacer separating the second contact from the second side of the second gate structure, top surfaces of the second spacer and the second contact being coplanar. In an embodiment, a device comprises: a first static random-access memory pull-up transistor comprising a gate structure over a semiconductor substrate; a second static random-access memory pull-up transistor comprising a first source/drain region in the semiconductor substrate adjacent the gate structure; a first spacer disposed between the first source/drain region and the gate structure; and a first contact over and physically contacting the first source/drain region and the semiconductor substrate, the first contact extending through the first spacer and into a side of the gate structure, the first contact over and physically contacting the gate structure, a top surface of the first contact being coplanar with a top surface of the first spacer. In an embodiment, a device comprises: a first pull-up transistor comprising a first source/drain region in a semiconductor substrate, a second source/drain region in the semiconductor substrate, and a first gate structure over the semiconductor substrate; a second pull-up transistor comprising a second gate structure, the second gate structure having a first top surface and a second top surface, the first top surface being disposed further from the semiconductor substrate than the second top surface; a first contact over the first source/drain region, the first contact physically contacting the first source/drain region, the first contact physically contacting a portion of the semiconductor substrate between the first source/drain region and the second gate structure, the first contact extending into a side of the second gate structure, the first contact physically contacting the second top surface of the second gate structure; a second contact over the second source/drain region, the second contact physically contacting the second source/drain region, the second contact separated from a side of the first gate structure; a first dielectric layer over the first gate structure, the second gate structure, the first contact, and the second contact; and a via extending through the first dielectric layer to contact the second contact, the via separated from the first contact. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 25,618 |
11943909 | DETAILED DESCRIPTION To provide a better understanding of the present invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements. Please refer toFIGS.1-3, a forming method of a semiconductor memory device according to the first preferred embodiment of the present invention is illustrated. In the present embodiment, the semiconductor memory device is for example a dynamic random access memory (DRAM) device, which includes at least one transistor (not shown in the drawings) and at least one capacitor structure (not shown in the drawings), thereto serve as the smallest unit in the DRAM array for accepting signals from word lines (not shown in the drawings) and bit lines101during the operation. Firstly, a substrate100such as a silicon substrate, a silicon containing substrate (such as SiC, SiGe) or a silicon-on-insulator (SOI) substrate is provided, a buried transistor (not shown in the drawings) is formed in the substrate100to function like the word line, and the bit line structure101and a conductive structure103are formed within a dielectric layer110on the substrate100. The dielectric layer110for example includes silicon nitride (SiN), but is not limited thereto. Precisely, the bit line structure101is electrically connected to a source/drain region (not shown in the drawings) of the transistor structure through a bit line contact (BLC, not shown in the drawings) disposed below a part of the bit line structure101, and the conductive structure103is electrically connected to another source/drain region (not shown in the drawings) of the transistor structure. Also, the conductive structure103includes a plug103adisposed at the bottom thereof, and a conductive pad130bdisposed at the top thereof, so that the conductive structure103may therefore perform like a T-shape. The plug103ais directly in contact with the another source/drain region of the transistor structure, to configure as a storage node contact (SNC), and the conductive pad130bis disposed over the plug103ato configure as a storage node (SN) pad. As shown inFIG.1, a stacked structure130and a mask structure150are sequentially formed on the dielectric layer110. The stacked structure130includes plural films with various materials alternately stacked on one over another. In the present embodiment, the stacked structure130includes a first layer131for example a nitride material layer including SiN or silicon carbonitride (SiCN), a second layer132for example including borophosphosilicate glass (BPSG), a third layer133for example an oxide material layer including silicon dioxide (SiO2), a fourth layer134, a fifth layer135and a sixth layer136stacked from bottom to top. In one embodiment, the fourth layer134and the sixth layer136include the same material as that of the first layer131, such as also being a nitride material layer including SiCN or SiN, and the fifth layer135includes the same material as the third layer133, such as also being an oxide material layer including SiO2. That is, the stacked structure130namely includes alternately stacked nitride material layers and oxide material layers. In another embodiment, the second layer132and the fifth layer135preferably include a relative greater thickness than that of other stacked layers. For example, the thickness of the second layer132or the fifth layer135is about 5 times greater than that of the first layer131, but is not limited thereto. Then, the entire thickness of the stacked structure130is about 1600 angstroms to 2000 angstroms, but not limited thereto. On the other hand, the mask structure150also includes plural films with various materials alternately stacked on one over another, and which may include a first mask layer151, a second mask layer152for example including silicon oxide, a third mask layer (not shown in the drawings) for example including organic dielectric layer (ODL), a fourth mask layer (not shown in the drawings) for example including silicon-containing hard mask (SHB), and a fifth mask layer (not shown in the drawings) for example including a photoresist layer like KrF, stacked from bottom to top. The fifth mask layer may include at least one opening patterns (not shown in the drawings) through firstly performing an exposure process. In one embodiment, the opening patterns of the fifth layer are sequentially transferred to the second mask layer152, and the fifth layer, and the fourth layer and the third layer are then removed, to form the stacked structure150as shown inFIG.1, with the second mask layer152including a plurality of corresponding opening patterns155. It is noted that, the first mask layer152preferably includes a material having a great etching selectivity related to the materials of each stacked layers of the stacked structure130, such as being amorphous silicon (a-Si), but is not limited thereto. Next, an etching process such as a dry etching process is performed to transfer the opening patterns155of the second mask layer152into the first mask layer151and a portion of the stacked structure130(namely, a portion of the sixth layer136) underneath, to form a plurality of primary openings155ato expose a portion of the sixth layer136, as shown inFIG.2. It is noted that, although the etching process is performed by using the second mask layer152as an etching mask, a portion of the second mask layer152may also be removed while etching the first mask layer151and the sixth layer136. That is, a second mask layer152awith a relative smaller height (thickness) is formed accordingly. Then, the second mask layer152ais used as another etching mask to perform another etching process such as a dry etching process, to further etching the stacked structure130(including the sixth layer136, the fifth layer135, the fourth layer134, the third layer133, the second layer132and the first layer131) through the primary openings155a, to form a plurality of corresponding openings200in the stacked structure130to expose the conductive structure103within the dielectric layer110, as shown inFIG.3. In one embodiment, while forming the primary openings155aand the openings200, the etched first mask layer151is therefore exposed and further reacted with the atmosphere in the environment, to form an oxide layer (not shown in the drawings) on exposed surface of the first mask layer151. The oxide layer may be completely removed while removing the first mask layer151in the subsequent process, and which will not be redundantly described hereinafter. Following these, the second mask layer152aand the first mask layer151are completely removed, and an electrode layer (not shown in the drawings) is then formed in the openings. Also, after removing the oxide material layers of the stacked structure130, other elements such as a capacitor dielectric layer and another electrode layer are further formed on the electrode layer, to form the capacitor structure of the semiconductor memory device. Through the above-mentioned processes, the method of forming a semiconductor memory device according to the first preferred embodiment of the present invention is completed. According to the forming method of the present embodiment, the conductive pads103bwith a greater size is formed on the plugs103ato together configure as the conductive structures103, and the capacitor structure is then formed thereon. In other words, the semiconductor memory device of the present embodiment utilizes the conductive pads103bto enhance the connection between the conductive structures103and the capacitor structure disposed over the conductive structures103, so as to avoid the defects in the subsequent processes resulting in the dislocation of the capacitor structure. Thus, the semiconductor memory device may therefore obtain a better performance thereby. It is also noted that, in the etching process of the present embodiment, the first layer131including a nitride material layer is used as a stop layer, for avoid the over-etching issues. However, under some situation, if the openings200are over dislocated in the stacked structure130, the openings200may be formed beyond the extending area of the conductive pad103bunderneath. At this time, the dielectric layer110may be easy to penetrate through during the etching process because the dielectric layer110includes similar material to that of the stacked structure130. Accordingly, while the electrode layer is formed in the subsequent process, the electrode layer may therefore fill in the penetrated dielectric layer110, to form a tiger tooth extension on the capacitor structure. The tiger tooth extension is downward extended from the capacitor structure, and which may cause possible short circuit between the conductive structure103and the bit line structures101at two sides of the conductive structure103. For avoiding said short circuit issue, people in the art shall easily realize that the method of forming the semiconductor memory device of the present invention is not limited to be formed through the aforementioned processes, and may also be formed through other forming methods. The following description will detail the different embodiments of the method of forming the semiconductor memory device. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols. Please refer toFIGS.4-12, forming method of a semiconductor memory device according to the second preferred embodiment of the present invention is illustrated. The formal steps in the present embodiment are similar to those in the aforementioned first embodiment, and the differences between the two embodiments are in that, the conductive pads103bformed over the plugs103aare omitted in the present embodiment, and a sacrificial layer138is additionally formed. Precisely, the bit lines structure101and the conductive structures103are also alternately disposed on the dielectric layer110in the present embodiment, and the conductive structure103only includes the plugs103awhich is directly in contact with the source/drain region of the transistors, with the conductive pads being omitted. That is, each of the conductive structures in the present embodiment may perform like an I-shape. Also, the stacked structure130and the mask structure150are formed on the dielectric layer110, and the sacrificial layer138is additionally formed between the first layer131and the second layer132of the stacked structure130, as shown inFIG.4. It is noted that, the sacrificial layer138includes a material having a greater etching selectivity relative to that of the nitride material layer (namely the first layer131, the fourth layer134and the sixth layer136) and the oxide material layer (namely, the third layer133and the fifth layer135) of the stacked structure130, such as being silicon or amorphous silicon but not limited thereto. For example, the etching selectivity relative between the sacrificial layer138, the nitride material layer and the oxide material layer is about 1:1:10. Furthermore, the sacrificial layer138preferably includes a relative greater thickness, for example being about 3-5 times greater than that of the first layer131, but not limited thereto. Except for the aforementioned difference, other features such as the materials or the thickness of each stacked layers of the stacked structure130are all similar to those in the first preferred embodiment, and the second mask layer152also includes a plurality of opening patterns155, and those will not be redundantly described hereinafter. As shown inFIG.5, an etching process such as a dry etching process is performed to transfer the opening patterns155of the second mask layer152into the first mask layer151and a portion of the stacked structure130(namely, a portion of the sixth layer136) underneath, to forma plurality of primary openings155a. Then, as shown inFIG.6, another etching process such as a dry etching process is performed to further etching the stacked structure130(including the sixth layer136, the fifth layer135, the fourth layer134, the third layer133and the second layer132) through the primary openings155a, to form a plurality of corresponding openings220in the stacked structure130to expose the sacrificial layer138. It is noted that, although the another etching process is performed by using the second mask layer152aas an etching mask, the second mask layer152aand a portion of the first mask layer151underneath may also be removed while etching the stacked structure130. That is, a first mask layer151awith a relative smaller height (thickness) is formed accordingly. Meanwhile, the thickness of the first mask layer151ais preferably the same as that of the exposed sacrificial layer138, as shown inFIG.6. Next, the sacrificial layer138is further etched, to form a plurality of expanding portions301in the sacrificial layer138to connect each opening220respectively. Firstly, an etching process such as an anisotropic etching process is performed by using the similar features between the first mask layer151aand the sacrificial layer138, to simultaneously remove the first mask layer151aand a portion of the sacrificial layer138, to exposed the first layer131underneath from the openings220. After that, the exposed portion of the first layer131is continuously removed, to expose the plugs103aformed within the dielectric layer110, as shown inFIG.7. Then, a lateral etching process is performed to further remove sidewalls of the sacrificial layer138and the first layer131to form the expanding portions301in connection with the openings220respectively, thereby forming the openings300as shown inFIG.8. In other words, each of the openings300includes a portion disposed within the sacrificial layer138and the first layer131to obtain a relative greater dimension, so as to form the expanding portion301. The rest portions (namely the portions disposed within the sixth layer136, the fifth layer135, the fourth layer134, the third layer133and the second layer132) of each of the openings300are not lateral etched, to retain the same dimension as that of the aforementioned openings220. Following these, an electrode layer310is formed in the openings300, with the electrode layer310being conformally formed on surfaces of the openings300to form corresponding expanding portions311at the bottom thereof, as shown inFIG.9. Subsequently, the oxide material layers (namely, the fifth layer135, the third layer133and the second layer132) of the stacked structure130are removed, the sacrificial layer138is then removed, and other elements are formed on the electrode layer310, to form the capacitor structure of the semiconductor memory device thereby. Precisely, in one embodiment, after forming the electrode layer310, an oxide layer (not shown in the drawings) such as including silicon oxide is firstly formed to entirely cover on the electrode layer310, and an etching back process is performed to partially removed the oxide layer and the electrode layer310disposed on the top surface (namely the surface of the sixth layer136) of the stacked structure130. That is, a silicon oxide layer330and an electrode layer310awith top surfaces being lower than that of the stacked structure130is obtained, as shown inFIG.10. Then, another oxide layer (not shown in the drawings) such as including silicon oxide is formed to cover the stacked structure130and to seal the openings300, and an etching process is performed through a mask layer (not shown in the drawings), to partially remove the another oxide layer to form an oxide layer320, with a portion of the top surface of the stacked structure130being exposed from the oxide layer320. That is, a portion of the stacked structure130(namely a portion of the sixth layer136) may be further removed through the exposed top surface thereof from the oxide layer320, to form the structure as shown inFIG.10. After that, as shown inFIG.11, an etching process such as a wet etching process is performed to further remove the oxide material layers (namely, the fifth layer135, the third layer133and the second layer132) of the stacked structure130through the etched portion of the sixth layer136, to only retain the nitride material layers of the stacked structure130. As shown inFIG.12, another etching process such as an anisotropic wet etching is further performed by using an etchant like tetramethylammonium hydroxide (TMAH) to completely remove the sacrificial layer138, with a weight percentage of tetramethylammonium hydroxide being provided in about 1-10%. In one embodiment, 6 wt % TMAH and 94 wt % propylene glycol are provided to remove the sacrificial layer138, but is not limited thereto. Following these, other elements such as a capacitor dielectric layer and another electrode layer may further be formed on the electrode layer310, to form the capacitor structure of the semiconductor memory device. Through the above-mentioned processes, the method of forming a semiconductor memory device according to the second preferred embodiment of the present invention is completed. According to the forming method of the present embodiment, the conductive pads103bformed in the aforementioned first embodiment have been omitted, and the sacrificial layer138is additionally formed between the first layer131and the second layer132of the stacked structure130, to function as a stop layer while forming the openings220. It is noted that, since the sacrificial layer138has a relative greater thickness and a greater etching selectivity related to the oxide material layers and the nitride material layers of the stacked structure130and the dielectric layer110, it is sufficient to avoid the aforementioned over-etching issue. After forming the openings220, the first mask layer151and a portion of the sacrificial layer138are simultaneously removed through the same etching process. Also, the sacrificial layer138may be completely removed while removing the oxide material layers of the stacked structure130after the electrode layer310is formed. The sacrificial layer138is further used to form the expanding portions301which are in connection with the openings220respectively, so that, the electrode layer310formed subsequently may also form the corresponding expanding portions311conformally. In other words, although the conductive pads are omitted in the semiconductor memory device of the present embodiment, the electrode layer310of the semiconductor memory device in the present embodiment further forms the corresponding expanding portions311at the bottom of the capacitor structure through the aforementioned processes. In this way, the capacitor structure of the present embodiment may therefore obtain a larger dimension at the bottom and a smaller dimension at the top, so as to perform like an inverted T-shape. The increased area of the bottom of the capacitor structure is able to enhance the connection between the plugs103aand the capacitor structure, so that it is sufficient to avoid any possible short circuit between the bit line structure101and the capacitor structure, or the poor connection between the plugs103aand the capacitor structure. Thus, the semiconductor memory device may therefore obtain a better performance under a simplify process flow. Overall speaking, the semiconductor memory device of the present invention improves the possible poor connection or the short circuit issue at the same time through the modify process. Although omitting the conductive pads disposed between the capacitor structure and the storage node contacts, the semiconductor memory device utilizes the additionally disposed sacrificial layer not only to avoid the possible over-etching issue through the openings, but also to form the corresponding expanding portions at the bottom of the capacitor structure. Accordingly, the corresponding expanding portions may enhance the connection between the storage node contacts and the capacitor structure, and also increase the capacitance of the capacitor structure via the increased bottom area thereof. With such arrangement, the semiconductor memory device may therefore obtain a better performance under a simplify process with some completely processes like the formation of the conductive pads being omitted. Furthermore, since disposing the sacrificial layer138may avoid the over-etching issue through the openings220, the expanding portions301may also be omitted in some embodiments. In other words, after forming the structure as shown inFIG.7, an electrode layer (not shown in the drawings) may be directly formed in the openings220followed by performing the subsequent processes. Otherwise, in another embodiment, the first layer131of the stacked structure130may be further omitted as shown inFIG.13, so that, only the sacrificial layer138is used as a stop layer while forming the openings220. Following these, the processes as shown inFIG.9of the aforementioned second embodiment may be performed, to form an electrode layer340in the openings220, so that, the electrode layer340may no longer form the aforementioned corresponding expanding portion311, so as to form the structure as shown inFIG.14. Then, the subsequent processes as shown inFIGS.10-12of the aforementioned second embodiment may be continuously performed, to sequentially remove the oxide material layer of the stacked structure130and the sacrificial layer138, and to form other elements on the electrode layer340to form the capacitor structure. With this arrangement, the conductive pads as well as the corresponding expanding portions are both omitted within the semiconductor memory device, so that, the semiconductor memory device is allowable to be formed under a further simplify process flow without leading to any possible short circuit or poor connection issues. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 22,385 |
11943910 | DETAILED DESCRIPTION Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. Some embodiments of the present disclosure are related to forming a doping region along a sidewall of a dielectric structure surrounding a passing word line to avoid an inversion layer from forming along the dielectric structure and extending to a substrate below. Junction leakage during turning on the passing word line is reduced accordingly. FIGS.1-4A and5-8illustrate cross section views of intermediate stages of a manufacturing method of a semiconductor device in accordance with some embodiments of the present disclosure. Referring toFIG.1, a substrate102is provided, and openings104are formed in the substrate102by using an etching process. The substrate102includes any suitable material, such as silicon. The etching process may include a selective wet etching process or a selective dry etching process. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, and other suitable parameters. In some other embodiments, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. In yet some other embodiments, a dry etching process may include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). In some embodiments, a hard mask over the substrate102with a particular pattern is used to form openings104. After forming the openings104in the substrate102, the hard mask is still in place and may be removed in a suitable process. Referring toFIG.2, a first implantation process IMP1is performed on the substrate102to form a doped active region103. The first implantation process IMP1is evenly performed throughout the substrate102in a direction perpendicular to the top surface of the substrate102. In some embodiments, the substrate102is doped by p-type dopants, such as boron, BF2, or the like, in the first implantation process IMP1, and a dose of the first implantation process IMP1is in a range from about 1×1012/cm2to about 1×1014/cm2. Referring toFIGS.3and4A, after forming the openings104in the substrate102and performing the first implantation process IMP1, dopants are implanted in the substrate102at a tilt angle with respect to a top surface of the substrate102from sidewalls106of the openings104such that doping regions108are partially formed in the substrate102at the sidewalls106of the openings104. Discussed in greater details, a second implantation process IMP2inFIG.3is performed to implant the dopants from first sides106aof the openings104at a first tilt angle a1with respect to a top surface of the substrate102, and a third implantation process IMP3inFIG.4Ais performed to implant the dopants from second sides106bof the openings104at a second tilt angle a2with respect to the top surface of the substrate102. The first side106aand the second side106bare opposite sides in the openings104. Therefore, the first tilt angle a1in the second implantation process IMP2and the second tilt angle a2in the third implantation process IMP3are opposite angles. After the second implantation process IMP2and the third implantation process IMP3, doping regions108aat the first sides106aand doping regions108bat the second sides106bare partially formed in the doped active region103of the substrate102. The doping region108aat the first side106aand doping region108bat the second side106bmerge at the bottom of the opening104to form a doping region108cat the bottom of the opening104. The implantation parameters, such as dose, energy and angle, can be tuned based on different situations. In some embodiments, doses of the second implantation process IMP2and the third implantation process IMP3are in a range from about 1×1012/cm2to about 1×1013/cm2respectively and are lower than the dose of the first implantation process IMP1. Energy of the second implantation process IMP2and the third implantation process IMP3is in a range from about 1 keV to about 5 keV respectively. If the second implantation process IMP2and the third implantation process IMP3are performed under the condition disclosed above, the doping regions108are formed only at the surface of the openings104. If the second implantation process IMP2and the third implantation process IMP3are performed out of the condition disclosed above, the doping regions108may be in contact with subsequently formed active word lines, which may cause adverse effect to the active word lines. In some embodiments, the first tilt angle a1and the second tilt angle a2are in a range from about 5° to about 20°. If the first tilt angle a1and the second tilt angle2are out of the disclosed range, it may be hard to implant the dopants from the sidewalls106of the openings104. In some embodiments, the doping region108has a thickness T1extending from the sidewall106of the opening104and the subsequently formed dielectric structure (such as the first dielectric structure112inFIG.6A), and the thickness T1is in a range from about 1 nm to about 10 nm. In some embodiments, the dopants in the second implantation process IMP2and the third implantation process IMP3are same as the dopants in the first implantation process IMP1, such as p-type dopants like boron, BF2, or the like. Therefore, the doping regions108and the doped active region103has the same conductivity type, and the doping regions108a(or108b,108c) are implanted twice in the first implantation process IMP1and the second implantation process IMP2(or the third implantation process IMP3), such that the dopant concentration of the doping regions108a(or108b,108c) are higher than that of the doped active region103. The doping regions108cat the bottom portion of the openings104reduce the probability of the subsequently formed passing word lines turning on the threshold voltage, thereby reducing disturbance caused by the subsequently formed passing word lines (such as the passing word lines132inFIG.7) in the dielectric structures (such as the first dielectric structures112inFIG.7) in the openings104to the subsequently formed active word lines (such as the active word lines134inFIG.7). The doping regions108aand108bat the sides of the openings104may improve the isolation of the subsequently formed dielectric structures in the openings104. In some embodiments, because the hard mask is still in place, the dopants are only implanted from the sidewalls106of the openings104and are not implanted from the top surface of the substrate102. FIG.4Billustrates a top view of the semiconductor device inFIG.4A, whereinFIG.4Bis the top view taken along a line A-A inFIG.4A. InFIG.4B, the direction of the second implantation process IMP2and the third implantation process IMP3are illustrated. It is noted that although both the second implantation process IMP2and the third implantation process IMP3are shown, it does not mean that the second implantation process IMP2and the third implantation process IMP3are performed at the same time. After the implantation processes, the doping regions108are formed adjacent to the openings104and are partially in the doped active region103from the top view. Referring toFIG.5, after the third implantation process IMP3, an annealing process is performed to the doping regions108aand108b. The annealing process AN is controlled to prevent from the dopants in the doping regions108aand108bnot moving too far from the surface of the openings104, thereby obtaining the doping regions108aand108bnear the surface of the openings104. Internal stress in the doping regions108aand108bmay also be reduced in the annealing process AN. Referring toFIG.6, dielectric materials are filled in the opening104to form first dielectric structures112and the second dielectric structures122. Discussed in greater details, the openings121may be first formed after the annealing process AN inFIG.5, and then the dielectric materials are filled in the openings104and the openings121. In some embodiments, the openings121are formed between the openings104and the sizes of the openings121are smaller than the openings104. Referring toFIG.7, the dielectric materials are first filled in the openings104and the openings121, and then an etching process is performed to partially etch the dielectric materials. Accordingly, openings112aand openings122aare respectively formed in the dielectric material and the first dielectric structures112and the second dielectric structures122are formed. The second dielectric structures122are formed between the adjacent first dielectric structures112. In some embodiments, the first dielectric structures112and the second dielectric structures122include one or more layers of a dielectric material, such as silicon oxide, titanium nitride, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the first dielectric structures112and the second dielectric structures122may be formed by CVD, atomic layer deposition (ALD) or any suitable method. In some embodiments, the etching process used to form the openings112aand the openings122amay be a selective wet etching or a selective dry etching. The difference between the first dielectric structures112and the second dielectric structures122is that the sizes of the second dielectric structures122are smaller than those of the first dielectric structures112. For example, the second dielectric structures122may be conformal thin layers to the openings121, and the first dielectric structures112are thicker layers, especially at the bottom portion of the openings104. The doping regions108are separated from the second dielectric structures122by the doped active region103. Stated another way, the second dielectric structures122are not in contact with the doping regions108. Although it is shown that there is only one second dielectric structure122between the adjacent first dielectric structures112, the number of the second dielectric structures122between the adjacent first dielectric structures112is not limited, such as 2 or more. Referring toFIG.8, passing word lines132are formed in the openings112aof the first dielectric structures112, and active word lines134are formed in the openings122aof the second dielectric structures122. Hence, the first dielectric structures112are formed between the substrate102and the passing word lines132, and the second dielectric structures122are formed between the substrate102and the active word lines134. In some embodiments, adhesion layers are formed in the openings112aand122abefore forming the passing word lines132and the active word lines134. The adhesion layers may respectively enable the passing word lines132and the active word lines134to have improved filling characteristics in the openings112aand122a, and therefore results in forming the passing word lines132and the active word lines134without leaving unfilled voids therein. In some embodiments, the adhesion layers may be made of titanium nitride (TiN). In some embodiments, the method of forming the passing word lines132and the active word lines134may include filling an adhesion material and a conductive material in the openings112aand122aand then performing a planarization operation. In some embodiments, the passing word lines132and the active word lines134may be made of conductive materials such as tungsten, titanium nitride, polysilicon or other suitable conductive/semiconductive materials. In some embodiments, the passing word line132and the active word line134are made of different materials. In other embodiments, the passing word line132and the active word lines134are made of same materials. Referring toFIG.9, dielectric layers142are formed over the passing word lines132and the active word lines134respectively. In some embodiments, the dielectric layers142are made of silicon nitride or other suitable dielectric materials. In some embodiments, the dielectric layers142are formed by chemical vapor deposition, ALD, or other suitable process. In some embodiments, the method of forming the dielectric layers142may include performing a first planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, to remove a portion of the passing word lines132and the active word lines134, forming the dielectric layers142to cover the passing word lines132and the active word lines134, and performing a second planarization operation, which is similar to the first planarization operation, such that a portion of the dielectric layers142is removed. In other words, top surfaces of the first dielectric structures112, top surfaces of the second dielectric structures122(if presented), and top surfaces of the dielectric layers142are at same horizontal level. After forming the dielectric layers142, the semiconductor device, as shown inFIG.9, includes the substrate102, the first dielectric structures112, the passing word lines132, the active word lines134, and the doping regions108. The substrate102includes the doped active region103therein. The first dielectric structures112are in the substrate102, and the passing word lines132are in the first dielectric structures112. The active word lines134are in the doped active region103of the substrate102, and some active word lines134are adjacent to the passing word lines132. The doping regions108are in the substrate102and at the sidewalls106of the first dielectric structures112. The doping regions108are between the active word lines134and the first dielectric structures112, and the doping regions108have a dopant concentration higher than a dopant concentration of the doped active region103. In some embodiments, the semiconductor device has the second dielectric structures122; therefore the active word lines134are in contact with the second dielectric structures122, as shown inFIG.9. In some other embodiments, the semiconductor device does not have the second dielectric structures122; therefore the active word lines134are directly in contact with the substrate102, as shown inFIG.12in later discussion. The doping regions108reduce the probability of the passing word lines132turning on the threshold voltage, thereby reducing disturbance caused by the passing word lines132to the active word lines134. The doping regions108avoid an inversion layer from forming along the first dielectric structures112and extending to the substrate102below. Hence, junction leakage during turning on the passing word lines132may be reduced. FIGS.10-12illustrate cross section views of intermediate stages of a manufacturing method of the semiconductor device in accordance with some other embodiments of the present disclosure. InFIGS.10-12, the second dielectric structures122are not formed. After the annealing process AN in FIG. the dielectric materials are filled in the openings104. Subsequently, the openings112aare formed in the dielectric materials to form the first dielectric structures112, and the openings122aare directly formed in the substrate102. The passing word lines132and the active word lines134are then respectively formed in the openings112aand122a. Other details related toFIGS.10-12are similar to the details related toFIGS.6-8; therefore, detailed description is not described herein. In summary, the doping region at the sidewall of the dielectric structure, in which a passing word line is in presence, may reduce the probability of the passing word line turning on the threshold voltage, thereby reducing disturbance caused by the passing word line to the active word line adjacent to the passing word line. Moreover, the doping regions avoid an inversion layer from forming along the dielectric structure and extending to the substrate below. Hence, junction leakage during turning on the passing word lines may be reduced. Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims. | 17,466 |
11943911 | DETAILED DESCRIPTION In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have been described in detail in order to avoid obscuring the invention. It will be understood that when an element is referred to as being “formed” on another element, it can be directly or indirectly, formed on the given element by growth, deposition, etch, attach, connect, or couple. And it will be understood that when an elements or a layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure. Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, “in”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures in turned over, elements described as “below” or “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventions. As used herein, the singular form “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Please refer toFIGS.3-7, which are schematic drawings illustrating a method for forming a semiconductor structure for a DRAM device provided by a first preferred embodiment of the present invention. As shown inFIG.3, a substrate200is provided. The substrate200can include a silicon (Si) substrate, a germanium (Ge) substrate, or a SiGe substrate, but not limited to this. The substrate200includes at least a memory cell region202and a peripheral circuit region204defined thereon. A plurality of shallow trench isolation (hereinafter abbreviated as STI) structures206are formed in the substrate200in the memory cell region202and the peripheral circuit region204. The STI structures206are formed to define a plurality of active regions208ain the memory cell region202and at least an active region208bin the peripheral circuit region204. The STI structures206are also formed to provide electrical isolations between the active regions208a/208b. Next, a plurality of recesses are formed in the substrate200and the STI structures206, and a dielectric layer210is then formed to cover sidewalls and bottoms of the recesses. Thereafter, a buried gate212is formed in each recess in the memory cell region202. It is noteworthy that a buried gate structure214is formed in the recess in the STI structure206in the peripheral circuit region204simultaneously with forming the buried gates212in the memory cell region202according to the preferred embodiment. And the buried gate structure214serves as a buried word line structure214. As shown inFIG.3, top surfaces of the buried gates212and the buried word line structure214are all lower than a surface of the substrate200. The buried gates212and the buried word line structure214can include doped semiconductor material such as doped silicon, metal material such as tungsten (W), aluminum (Al), titanium (Ti), and/or tantalum (Ta), metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN), and metal-semiconductor compound such as metal silicide, but not limited to this. After forming the buried gates212and the buried word line structure214, an insulating layer216is formed to seal the recesses. The insulating layer216can include silicon oxide (SiO), silicon nitride (SiN), and/or silicon oxynitride (SiON), but not limited to this. Thereafter, source/drain regions (not shown) are formed in the substrate200at two sides of the buried gates212and the buried word line structure214. Accordingly, a plurality of memory cells218are formed in the memory cell region202, and the memory cells218are arranged in array-like manner, i.e. in row and column directions in the memory cell region202. However, those skilled in the art would easily realize that the memory cells218can be formed by any other suitable processes, and thus steps for forming the memory cells are not limited to this. After forming the source/drain regions, an insulating layer220is blanketly formed on the substrate200. The insulating layer220can serve as a gate dielectric layer for subsequently formed transistors in the peripheral circuit region, and thus the insulating layer220can include SiO, SiN, SiON, and/or high-k material, but not limited to this. Please refer toFIG.4. A patterned process is then performed to remove portions of the insulating layer220, and thus a portion of the active regions208ain the memory cell region202and portions of the active region208bin the peripheral circuit region204are exposed as shown inFIG.4. In the memory cell region202, the portion of each active region208athat is in between the two buried gates212is exposed. In other words, the source/drain region in between the two buried gates212in each active region208ain the memory cell region202is exposed while the portions of the active region208bat two sides of the buried word line structure214in the peripheral circuit region204are exposed. In some embodiments of the present invention, steps as shown inFIG.5can be performed directly after exposing the abovementioned portions of the active region208a/208b. However, in other embodiments of the present invention, the exposed portions/substrate200can be etched and thus a recess222ais formed in between the two buried gates212in each active region208ain the memory cell region202, and recesses222bare formed in the active region208bat the two sides of the buried word line structure214in the peripheral circuit region204, as shown inFIG.4. Please refer toFIG.5. Next, a semiconductor layer224is blanketly formed on the substrate200and a metal-containing layer226is subsequently formed on the semiconductor layer224. According to the preferred embodiment, the semiconductor layer224can include a doped polysilicon layer, and the metal-containing layer226can be a metal layer and/or a metal silicide layer, but not limited to this. Please refer toFIG.6. After forming the semiconductor layer224and the metal-containing layer226, a patterning process is performed to form bit line contact plugs228and bit line structures250in the memory cell region202. Simultaneously, a conductive line structure or a planar gate structure230, a contact plug lower portion232, and a contact plug lower portion234are formed in the peripheral circuit region204. It is therefore concluded that the bit line contact plug228/the bit line structure250in the memory cell region202and the contact plug lower portion232, the contact plug lower portion234and the planar gate structure230in the peripheral circuit region204can include the same material. Furthermore, the patterning process can be simultaneously stopped at the insulating layer220, but not limited to this. As shown inFIG.6, the bit line contact plug228in the memory cell region202is physically and electrically connected to the source/drain region in between the two buried gates212in each active region208a, and the bit line structure250is electrically connected to the memory cells218arranged in the same column by the bit line contact plugs228. In the peripheral circuit region204, the planar gate structure230is directly formed on the buried word line structure214. Furthermore, the conductive line structure/the planar gate structure230overlaps the buried word line structure214and serves as a signal line structure. And the insulating layer216/220is sandwiched between the conductive line structure/the planar gate structure230and the buried word line structure214, such that the planar gate structure230and the buried word line structure214are physically spaced apart and electrically isolated from each other by the insulating layer216/220. The contact plug lower portion232is formed on the active region208bat a first side of the buried word line structure214, and the contact plug lower portion234is formed on the active region208bat a second side of the buried word line structure214opposite to the first side, as shown inFIG.6. Additionally, in some embodiments of the present invention, spacer liners can be formed on sidewalls of the planar gate structure230, sidewalls of the bit line structures250, and sidewalls of the contact plug lower portions232and234, but not limited to this. Please refer toFIG.7. It should be noted that though only the elements in the peripheral circuit region204are depicted inFIG.7, those skilled in the art should easily realize steps for forming elements in the memory cell region202, therefore those details are omitted in the interest of brevity. Next, an interlayer dielectric (hereinafter abbreviated as ILD) layer236is formed on the substrate200and followed by forming a first contact plug240, a contact plug upper portion242and a contact plug upper portion244in the ILD layer236in the peripheral circuit region204. It is therefore concluded that the first contact plug240, the contact plug upper portion242, and the contact plug upper portion244in the peripheral circuit region204all include the same material. As shown inFIG.7, in the peripheral circuit region204, the first contact plug240is directly formed on the planar gate structure230, and is physically and electrically connected to the planar gate structure230. The contact plug upper portion242is physically and electrically connected to the contact plug lower portion232, and thus a second contact plug232/242is constructed. The contact plug upper portion244is physically and electrically connected to the contact plug lower portion234, and thus a third contact plug234/244is constructed. Please still refer toFIG.7. After forming the first contact plug240, the second contact plug232/242and the third contact plug234/244, a connecting layer252and a connecting layer254are formed in the peripheral circuit region204. As shown inFIG.7, the connecting layer252electrically connects the first contact plug240and the second contact plug232/242, and the connecting layer254is electrically connected to the third contact plug234/244. It is noteworthy that the first contact plug240, the second contact plug232/242, and the connecting layer252construct a local inter connection structure260at the first side of the buried word line structure214, and the local inter connection structure260electrically connects the planar gate structure230and the active region208b. The third contact plug234/244and the connecting layer254construct an interconnection structure262on the active region208bat the second side of the buried word line structure214. More important, the interconnection structure262electrically connects the active region208bto a bit line BL, or alternatively electrically connects the active region208bto a bit line bar /BL. According to the method provided by the preferred embodiment, all elements in the peripheral circuit region204can be formed and integrated with the formation of the elements in the memory cell region202. Furthermore, since the gates for the transistors required in the peripheral circuit region204are replaced with the buried word line structure214, and the conductive line structure230is directly formed on the buried word line structure214, area occupied by those elements are reduced. Please refer toFIGS.3andFIGS.8-9, which are schematic drawings illustrating a method for forming a semiconductor structure for a DRAM device provided by a second preferred embodiment of the present invention. It is noteworthy that elements the same in both of the first and second preferred embodiments include the same numerals and can include the same material, and thus details are omitted in the interest of brevity. As shown inFIG.3, the method of the preferred embodiment provides a substrate200including at least a memory cell region202and a peripheral circuit region204defined thereon. A plurality of STI structures206are formed in the substrate200in the memory cell region202and the peripheral circuit region204. The STI structures206are formed to define a plurality of active regions208ain the memory cell region202and at least an active region208bin the peripheral circuit region204. Next, buried gates212are formed in the memory cell region202. It is noteworthy that a buried gate structure serving214as a word line structure214is formed in the STI structure206in the peripheral circuit region204simultaneously with forming the buried gates212. As shown inFIG.8, top surfaces of the buried gates212and the buried word line structure214are all lower than a surface of the substrate200. And an insulating layer216is formed on the buried gates212and the buried word line structure214. Thereafter, source/drain regions (not shown) are formed in the substrate200at two sides of the buried gates212and the buried word line structure214. Accordingly, a plurality of memory cells218are formed in the memory cell region202, and the memory cells218are arranged in array-like manner, i.e. in row and column directions in the memory cell region202. Please refer toFIG.8. A patterned process is then performed to remove portions of the insulating layer220, and thus a portion of the active regions208ain the memory cell region202and portions of the active region208bin the peripheral circuit region204are exposed. In some embodiments of the present invention, steps can be performed directly after exposing the abovementioned portions of active regions208a/208b. In other embodiments of the present invention, the exposed portions/substrate200can be etched and thus recesses are formed as shown inFIG.8. Next, a semiconductor layer224is blanketly formed on the substrate200and a metal-containing layer226is subsequently formed on the semiconductor layer224. A patterning process is then performed to form bit line contact plugs228and bit line structures250in the memory cell region202. Simultaneously, a planar gate structure230, a contact plug lower portion232, and a contact plug lower portion234are formed in the peripheral circuit region204. As shown inFIG.8, the bit line contact plug228in the memory cell region202is physically and electrically connected to the source/drain region in between the two buried gates212in each active region208a, and the bit line structure250is electrically connected to the memory cells218arranged in the same column by the bit line contact plugs228. In the peripheral circuit region204, the planar gate structure230is directly formed on the buried word line structure214. Furthermore, the planar gate structure230overlaps the buried word line structure214and serves as a signal line structure. And the insulating layer216/220is sandwiched between the planar gate structure230and the buried word line structure214, such that the planar gate structure230and the buried word line structure214are physically spaced apart and electrically isolated from each other by the insulating layer216/220. The contact plug lower portion232is formed on the active region208bat a first side of the buried word line structure214, and the contact plug lower portion234is formed on the active region208bat a second side of the buried word line structure214opposite to the first side, as shown inFIG.8. It is noteworthy that in the preferred embodiment, the insulating layer serving as an etch stop layer is removed from the active region208bat the two sides of the buried word line structure214. Therefore, the etching process performed to remove portions of the semiconductor layer224and the metal-containing layer226can be controlled by other parameters such as process duration, but not limited to this. Please refer toFIG.9. As mentioned above, it should be noted that thought only the elements in the peripheral circuit region204are depicted inFIG.9, those skilled in the art should easily realize steps for forming elements in the memory cell region202, therefore those details are omitted in the interest of brevity. Next, an ILD layer236is formed on the substrate200and followed by forming a first contact plug240, a contact plug upper portion242and a contact plug upper portion244in the ILD layer236in the peripheral circuit region204. It is therefore concluded that the first contact plug240, the contact plug upper portion242, and the contact plug upper portion244in the peripheral circuit region204all include the same material. As shown inFIG.9, in the peripheral circuit region204, the first contact plug240is directly formed on the planar gate structure230, and is physically and electrically connected to the planar gate structure230. The contact plug upper portion242is physically and electrically connected to the contact plug lower portion232, and thus a second contact plug232/242is constructed. The contact plug upper portion244is physically and electrically connected to the contact plug lower portion234, and thus a third contact plug234/244is constructed. Please still refer toFIG.9. After forming the first contact plug240, the second contact plug232/242and the third contact plug234/244, a connecting layer252and a connecting layer254are formed in the peripheral circuit region204. As shown inFIG.9, the connecting layer252electrically connects the first contact plug240and the second contact plug232/242, and the connecting layer254is electrically connected to the third contact plug234/244. It is noteworthy that the first contact plug240, the second contact plug232/242, and the connecting layer252construct a local inter connection structure260on the active region208bat the first side of the buried word line structure214, and the local inter connection structure260electrically connects the planar gate structure230and the active region208b. The third contact plug234/244and the connecting layer254construct an interconnection structure262on the active region208bat the second side of the buried word line structure214. And the interconnection structure262electrically connects the active region208bto a bit line BL, or alternatively to a bit line bar /BL. According to the method provided by the preferred embodiment, all elements in the peripheral circuit region204can be formed and integrated with the formation of the elements in the memory cell region202. Furthermore, since the gates for the transistors required in the peripheral circuit region204are replaced with the buried word line structure214, and the signal line structure230is directly formed on the buried word line structure214, area occupied by those elements are reduced. Compared with the first preferred embodiment as shown inFIG.6, since no insulating layer220is sandwiched between the semiconductor layer224and the substrate202, resistance between the second contact plug232/242and the active region208band resistance between the third contact plug234/244and the active region208bare reduced in accordance with the preferred embodiment. Please refer toFIGS.3and10-11, which are schematic drawings illustrating a method for forming a semiconductor structure for a DRAM device provided by a third preferred embodiment of the present invention. It is noteworthy that elements the same in both of the first and third preferred embodiments include the same numerals and can include the same material, and thus details are omitted in the interest of brevity. As shown inFIG.3, the method of the preferred embodiment provides a substrate200including at least a memory cell region202and a peripheral circuit region204defined thereon. A plurality of STI structures206are formed in the substrate200to define a plurality of active regions208ain the memory cell region202and at least an active region208bin the peripheral circuit region204. Next, buried gates212are formed in the memory cell region202, and a buried gate structure214serving as a buried word line structure214is simultaneously formed in the STI structure206in the peripheral circuit region204. As shown inFIG.3, top surfaces of the buried gates212and the buried word line structure214are all lower than a surface of the substrate200. An insulating layer216is then formed on the buried gates212and the buried word line structure214. Thereafter, source/drain regions (not shown) are formed in the substrate200at two sides of the buried gates212and the buried word line structure214. Accordingly, a plurality of memory cells218are formed in the memory cell region202. The memory cells218are arranged in array-like manner, i.e. in row and column directions in the memory cell region202. Please refer toFIG.10. A patterned process is then performed to remove portions of the insulating layer220, and thus a portion of the active regions208ain the memory cell region202and portions of the active region208bin the peripheral circuit region204are exposed. In some embodiments of the present invention, steps can be performed directly after exposing the abovementioned portions of active regions208a/208b. In other embodiments of the present invention, the exposed portions/substrate200can be etched and thus recesses are formed as shown inFIG.10. Next, a semiconductor layer224is blanketly formed on the substrate200and a metal-containing layer226is then formed on the semiconductor layer224. A patterning process is subsequently performed to form bit line contact plugs228and bit line structures250in the memory cell region202. Simultaneously, a planar gate structure230is formed in the peripheral circuit region204. As shown inFIG.10, the bit line contact plug228in the memory cell region202is physically and electrically connected to the source/drain region in between the two buried gates212in each active region208a, and the bit line structure250is electrically connected to the memory cells218arranged in the same column by the bit line contact plugs228. In the peripheral circuit region204, the planar gate structure230is directly formed on the buried word line structure214. Furthermore, the planar gate structure230overlaps the buried word line structure214and serves as a signal line structure. The insulating layer216/220is sandwiched between the planar gate structure230and the buried word line structure214, such that the planar gate structure230and the buried word line structure214are physically spaced apart and electrically isolated from each other by the insulating layer216/220. Additionally, the semiconductor layer224and the metal-containing layer226at two sides of the buried word line structure214are removed and thus the active region208bis exposed. It is noteworthy that in the preferred embodiment, the insulating layer serving as an etch stop layer is removed from the active region208bat the two sides of the buried word line structure214. Therefore, the etching process performing to remove portions of the semiconductor layer224and the metal-containing layer226can be controlled by other parameters such as process duration, but not limited to this. Please refer toFIG.11. As mentioned above, it should be noted that though only the elements in the peripheral circuit region204are depicted inFIG.11, those skilled in the art should easily realize steps for forming elements in the memory cell region202, therefore those details are omitted in the interest of brevity. Next, an ILD layer236is formed on the substrate200and followed by forming a first contact plug240, a second contact plug242′ and a third contact plug244′ in the ILD layer236in the peripheral circuit region204. In other words, the first contact plug240, the second contact plug242′ and the third contact plug244′ in the peripheral circuit region204include the same material. As show inFIG.11, in the peripheral circuit region204, the first contact plug240is directly formed on the planar gate structure230, and is physically and electrically connected to the planar gate structure230. The second contact plug242′ is physically and electrically connected to the active region208bat a first side of the buried word line structure214. And the third contact plug244′ is physically and electrically connected to the active region208bat a second side of the buried word line structure214opposite to the first side. Please still refer toFIG.11. After forming the first contact plug240, the second contact plug242′ and the third contact plug244′, a connecting layer252and a connecting layer254are formed in the peripheral circuit region204. As shown inFIG.11, the connecting layer252electrically connects the first contact plug240and the second contact plug242′, and the connecting layer254is electrically connected to the third contact plug244′. As mentioned above, the first contact plug240, the second contact plug242′, and the connecting layer252construct a local inter connection structure260on the active region208bat the first side of the buried word line structure214, and the local inter connection structure260electrically connects the planar gate structure230and the active region208b. The third contact plug244′ and the connecting layer254construct an interconnection structure262on the active region208bat the second side of the buried word line structure214. And the interconnection structure262electrically connects the active region208bto a bit line BL, or alternatively to a bit line bar /BL. According to the method provided by the preferred embodiment, all elements in the peripheral circuit region204can be formed and integrated with the formation of the elements in the memory cell region202. Furthermore, since the gates for the transistors required in the peripheral circuit region204are replaced with the buried word line structure214, and the signal line structure230is directly formed on the buried word line structure214, area occupied by those elements are reduced. Please refer toFIGS.12and17, which are schematic drawings illustrating a semiconductor structure provided by a preferred embodiment of the present invention. It should be noted that the semiconductor structure provided by the preferred embodiment shown inFIGS.12and17can be formed by performing the method provided by the abovementioned preferred embodiments.FIGS.7,9and11can be a cross-sectional view taken along a line A-A′ or B-B′ ofFIG.12, respectively, andFIG.17can be a cross-sectional view taken along a line C-C′ ofFIG.12. As shown inFIG.12, the layout structure of the semiconductor structure300aprovided by the preferred embodiment includes a plurality of active regions208bdefined by the STI structure (not shown) in the peripheral circuit region204of a DRAM device. In some embodiments of present invention, the active regions208brespectively can include a comb shape. The comb shape includes tooth portions, and the tooth portions are extended along a first direction D1. In the preferred embodiment, the active regions208brespectively include a first tooth portion209a, a second tooth portion209b, and a base portion209c, as shown inFIG.12. The layout structure of the semiconductor structure300afurther includes a buried word line structure214and a conductive line structure/planar gate structure230extended along a second direction D2. The second direction D2and the first direction D1are perpendicular to each other. More important, the conductive line structure/the planar gate structure230overlaps the buried word line structure214, but the conductive line structure/the planar gate structure230is physically spaced apart and electrically isolated from the buried word line structure214by the insulating layer216/220, as shown inFIGS.7,9,11and17. The second contact plug232/242(or242′) is formed on the active region208bat the first side of the buried word line structure214. That is, the second contact plug232/242(or242′) is formed on the base portion209c. And the third contact plug234/244(or244′) is formed on the active region208bat the second side of the buried word line structure214. More important, the second contact plug232/242(or242′) is formed on both of the first tooth portion209aand the second tooth portion209b. It is noteworthy that the third contact plug234/244(or244′) formed on the first tooth portion209aand the connecting layer254construct the interconnection structure262(shown inFIGS.7,9, and11) in accordance with the preferred embodiment, and the interconnection structure262is electrically connected to the bit line BL. And the third contact plug234/244(or244′) formed on the second tooth portion209band the connecting layer254construct the interconnection structure262(shown inFIGS.7,9, and11), and the interconnection structure262is electrically connected to the bit line bar /BL. The first contact plug240is formed on the conductive line structure/the planar gate structure230and electrically connected to the second contact plug232/242(or242′) by the connecting layer252, and thus the local inter connection structure260is constructed by the first contact plug240, the second contact plug232/242(or242′) and the connecting layer252(shown inFIGS.7,9, and11). Additionally, the buried word line structure214includes a first width W1, the conductive line structure/the planar gate structure230includes a second width W2as shown inFIGS.7,9,11,12, and17. It is noteworthy that the second width W2of the conductive line structure/the planar gate structure230is larger than the first width W1at where the first contact plug240is to be formed, thus process window for the first contact plug240is improved. On the other hand, the second width W2of the conductive line structure/the planar gate structure230is smaller than first width W1at where no first contact plug240is required. According to the semiconductor structure provided by the preferred embodiment, the signal line structure/the planar gate structure230receives a pre-charge voltage VBLP, and currents therefore flow into the base portion209cof the active region208bthrough the first contact plug240, the connecting layer252and the second contact plug232/242(or242′). Furthermore, the currents pass a channel region formed around the buried word line structure214and subsequently the first tooth portion209aof the active region208b, and then to the bit line BL through the interconnection structure262(that includes the third contact plug234/244(or244′) and the connecting layer254) as depicted by the dotted line shown inFIG.12. On other hand, the currents pass a channel region formed around the buried word line structure214and subsequently the second tooth portion209bof the active region208b, and then to the bit line bar /BL through the interconnection structure262(that includes the third contact plug234/244(or244′) and the connecting layer254). Consequently, the two pre-charge transistors are obtained in accordance with the preferred embodiment. Furthermore, the first tooth portion209a, the buried word line structure214, and the second tooth portion209bconstruct a BL equalizer transistor with the first tooth portion209a(electrically connected to bit line BL) and the second tooth portion209b((electrically connected to bit line bar /BL) respectively serving as a source and a drain of the BL equalizer transistor, as depicted by the bold line shown inFIG.12. Accordingly, the semiconductor structure provided by the preferred embodiment includes a pre-charge unit of a BL sensing amplifier in the DRAM device. And the buried word line structure214serves as the gates for the three transistors required by the pre-charge unit. Since the signal line structure or the planar gate structure that provides the pre-charge voltage VBLP is directly formed on the buried word line structure, area required by the pre-charge unit is reduced. Furthermore, landing pads which occupy large areas but are always required in the prior art can be taken out according to the present invention, and thus product yield is improved. Please refer toFIGS.13-16, which are schematic drawings respectively illustrating a semiconductor structure provided by preferred embodiments of the present invention. It is noteworthy that elements the same in the aforementioned embodiments and the instant embodiment can include the same numerals and can include the same material, and thus details are omitted in the interest of brevity. And steps for forming those elements are also omitted for brevity. Please refer toFIG.13. The difference between the embodiment depicted inFIG.13and that depicted inFIG.12is: two base portions of the two adjacent active regions208bcan be physically connected to each other according to the semiconductor structure300bprovided by the preferred embodiment. And thus a continuous common base portion209c′ is obtained. Furthermore, one first contact plug240can be formed on the signal line structure/the planar gate structure230, and one second contact plug232/242(or242′) can be formed on the common base portion209c′ in the preferred embodiment. Thus, layout and routing design for the pre-charge unit of the BL sensing amplifier can be simplified. However, in some modifications to the preferred embodiment, two second contact plugs can be formed on the common base portion209c′ and two first contact plugs can formed on the signal line structure/the planar gate structure230if required. Additionally, dummy structures (not shown) can be formed if required. Please refer toFIG.14. The difference between the embodiment depicted inFIG.14and that depicted inFIG.12is: all of base portions of the active regions208bare physically connected to each other according to the semiconductor structure300cprovided by the preferred embodiment. And thus a continuous common base portion209c′ is obtained. Thus layout and routing design for the pre-charge unit of the BL sensing amplifier can be further simplified. Furthermore, a plurality of second contact plugs232/242(or242′) can be formed on the common base portion209c′ and a plurality of first contact plugs240can be formed on the signal line structure/the planar gate structure230. In some embodiments of the present invention, the amount of the second contact plugs232/242(or242′) and the amount of the first contact plugs240can be equal to a pair number of the first tooth portion209aand the second tooth portion209b. However, in other embodiments of the present invention, only one first contact plug is formed on the signal line structure/the planar gate structure230and only one second contact plug is formed on the common base portion209c′ if required. Additionally, dummy structures (not shown) can be formed if required. Please refer toFIG.15. The difference between the embodiment depicted inFIG.15and that depicted inFIG.12is: the first tooth portion209aand the second tooth portion209bof the semiconductor structure300dare formed pair by pair. Thus different pairs of first tooth portion209aand second tooth portion209bcan include different lengths. By forming pairs of first tooth portion209aand second tooth portion209bwith different lengths, the third contact plugs234/244(or244′) can be formed in a stagger-like manner two-by-two, and thus process window for the third contact plugs234/244(or244′) is improved. Furthermore, in some embodiments of the present invention, the base portions209cof the adjacent the active regions208bcan be formed individually as shown inFIG.12. And in other embodiments of the present invention, the base portions can be physically connected to form a continuous common base portion209c′ as shown inFIG.15. Additionally, dummy structures (not shown) can be formed if required. Please refer toFIG.16. The difference between the embodiment depicted inFIG.16and that depicted inFIG.12is: the first tooth portion209aand the second tooth portion209bof the semiconductor structure300einclude different lengths. By forming the first tooth portion209aand the second tooth portion209bwith different lengths, the third contact plugs234/244(or244′) can be formed in a stagger-like manner one-by-one, and thus process window for the third contact plugs234/244(or244′) is improved. Furthermore, in some embodiments of the present invention, the base portions209cof the adjacent the active regions208bcan be formed individually as shown inFIG.12. And in other embodiments of the present invention, the base portions can be physically connected to form a continuous common base portion209c′ as shown inFIG.16. Additionally, dummy structures (not shown) can be formed if required. According to the semiconductor structure, the semiconductor structure for the memory device, and the method for forming the same provided by the present invention, the buried word line structure is formed in the peripheral circuit region. More important, the buried word line structure concurrently serves as the gates for the three transistors of the pre-charge unit of the BL sensing amplifier. And the signal line structure or the planar gate structure that provides the pre-charge voltage VBLP is directly formed on the buried word line structure. Consequently, area required by the pre-charge unit is reduced. Furthermore, landing pads which occupy large areas but are always required in the prior art can be taken out according to the present invention, and thus product yield is improved. Additionally, the present invention provides layout structures that comply with different requirements, and layout and routing design for the pre-charge unit of the BL sensing amplifier can be further simplified. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 38,973 |
11943912 | DETAILED DESCRIPTION Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate. FIG.1is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.FIG.2Ais a cross-sectional view of the semiconductor device taken along a line A-A′ shown inFIG.1.FIG.2Bis a cross-sectional view of the semiconductor device taken along a line B-B′ shown inFIG.1. The semiconductor device100in accordance with an embodiment of the present invention may include a transistor. The semiconductor device100may include a substrate101, a gate trench105, a fin region110, a buried gate structure100G, a first doping region111, and a second doping region112. The buried gate structure100G may include a gate dielectric layer106, a gate electrode BG1, and a capping layer109. The substrate101may be formed of a material that is appropriate for a semiconductor processing. The substrate101may include a semiconductor substrate. The substrate101may be formed of a silicon-containing material. The substrate101may include one selected from a group including silicon, monocrystalline silicon, polysilicon, amorphous silicon, a silicon germanium, a monocrystalline silicon germanium, a polycrystalline silicon germanium, a carbon-doped silicon, a combination thereof, or a multi-layer of two or more of them. The substrate101may include another semiconductor material, such as germanium. The substrate101may include a semiconductor substrate of a III/V-group material, e.g., a compound such as gallium arsenide (GaAs). The substrate101may include a Silicon-On-Insulator (SOI) substrate. An isolation layer102and an active region104may be formed in the substrate101. The isolation layer102may define a plurality of active regions104. The isolation layer102may be a Shallow Trench Isolation (STI) region. The isolation layer102may be formed by filling a shallow trench, e.g., an isolation trench103, with a dielectric material. The isolation layer102may be formed of any suitable material including, for example, a silicon oxide, a silicon nitride, or a combination thereof. The active region104may include the fin region110, the first doping region111, and the second doping region112. The first doping region111and the second doping region112may be regions doped with conductive dopants. For example, suitable conductive dopants may include phosphorus (P), arsenic (As), antimony (Sb), boron (B), or a combination thereof. The first doping region111and the second doping region112may be doped with dopants of the same conductive type. The first doping region111and the second doping region112may be isolated from each other by the gate trench105. The first doping region111and the second doping region112may be disposed on both sides of the gate trench105. The first doping region111and the second doping region112may be called a source region and a drain region, respectively. The lower surfaces of the first doping region111and the second doping region112may be positioned at a predetermined level from the upper surface of the active region104. The lower surfaces of the first doping region111and the second doping region112may be adjacent to a side wall of an upper portion of the gate trench105. The lower surfaces of the first doping region111and the second doping region112may be higher than a bottom surface of the gate trench105. The first doping region111and the second doping region112may be symmetrical. For example, the first doping region111and the second doping region112may form a junction of the same depth. According to another embodiment of the present invention, the first doping region111may be formed to be deeper than the second doping region112. A plurality of gate trenches105may be formed inside the substrate101. Referring toFIG.1, each of the gate trenches105may have a line shape extending in one direction that is intersecting with the active region104and the isolation layer102. Referring toFIG.26, each of the gate trenches105may include a first trench105A and a second trench105B. The first trench105A may be formed inside of the active region104. The second trench105B may be formed inside of the isolation layer102. The gate trench105may have a shape that is continuously extended from the first trench105A toward the second trench105B. The gate trench105may have a shallower depth than the isolation trench103. The bottom edges of the gate trench105as shown inFIGS.2A and2Bmay be substantially flat. However, the invention is not limited in this way and it is noted that the bottom edges of the gate trench105may have a round shape and then the shape of the gate trench105may be formed in a U shape. The gate trench105may be formed between the first doping region111and the second doping region112. The bottom surfaces of the first trench105A and the second trench105B may be positioned at different levels. For example, the bottom surface of the first trench105A may be at a higher level than the bottom surface of the second trench105B. The height difference between the first trench105A and the second trench105B may be caused as the isolation layer102is recessed. Therefore, the second trench105B may include a recessed region R having a bottom surface that is lower than the bottom surface of the first trench105A. The fin region110may be formed in the active region104due to the step height between the first trench105A and the second trench105B. Each fin region110may be positioned under a corresponding first trench105A, and the side walls of the fin region110may be exposed through a recessed isolation layer102F. A channel region may be defined by the gate trench105and the fin region110. The channel region may be formed in a U shape. The channel region may include a bottom channel and a side channel. The bottom channel may be defined by the fin region110, and the side channel may be defined by the side walls of the gate trench105. The bottom channel and the side channel may be in continuum. The U-shaped channel region may have a longer channel length than a general planar-type transistor. Therefore, it may prevent a short channel effect. The fin region110may be called ‘a saddle fin’. The fin region110may be able to increase the channel width and improve the electrical characteristics. The buried gate structure100G may be extended into the inside of the substrate101. For example, the buried gate structure100G may be formed inside of the gate trench105. The buried gate structure100G may be disposed in the active region104between the first doping region111and the second doping region112and extended into the inside of the isolation layer102. In the buried gate structure100G, the bottom surface of a portion disposed inside of the active region104and the bottom surface of a portion disposed inside of the isolation layer102may be positioned at different levels. The buried gate structure100G may include the gate dielectric layer106, the gate electrode BG1, and the capping layer109. The gate trench105may be lined with the gate dielectric layer106. The gate trench105lined with the gate dielectric layer106may be called ‘a lined trench’ or ‘a lined gate trench’. The gate dielectric layer106may be formed on the bottom and side walls of the gate trench105. The gate dielectric layer106may be formed of any suitable material including, for example, a silicon oxide, a silicon nitride, a silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include materials having greater dielectric constants than the dielectric constant of a silicon oxide. For example, the high-k material may be formed of any suitable material having a greater dielectric constant than 3.9. According to another embodiment of the present invention, the high-k material may be formed of any suitable material having a greater dielectric constant than 10. According to yet another embodiment of the present invention, the high-k material may be formed of any suitable material having a dielectric constant ranging from 10 to 30. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include a hafnium oxide, a hafnium silicon oxide, a hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include a lanthanum oxide, a lanthanum aluminum oxide, a zirconium oxide, a zirconium silicon oxide, a zirconium silicon oxynitride, an aluminum oxide, and combinations thereof. As for the high-k material, other known high-k materials may be selected and used. According to the embodiment of the present invention, the gate dielectric layer106may be formed by oxidizing the surface of the gate trench105. According to another embodiment of the present invention, the gate dielectric layer106may be formed by depositing a liner material and oxidizing the liner material. The liner material may include a liner polysilicon or a liner nitride. The capping layer109may protect the upper portion of the gate electrode BG1. The capping layer109may be formed of any suitable dielectric material. Examples of suitable dielectric materials for the capping layer109may include a silicon nitride, a silicon oxynitride, or a combination thereof. According to an embodiment of the present invention, the capping layer109may include a combination of a silicon nitride and a silicon oxide. For example, in order to form the capping layer109, the inner sidewall of the gate dielectric layer106which extends over the top surface of the gate electrode BG1and the top surface of the gate electrode BG1may be lined with a silicon nitride and then filled with a Spin-On-Dielectric (SOD) material. According to another embodiment of the present invention, the capping layer109may have an ONO (Oxide-Nitride-Oxide) structure. Hereafter, the gate electrode BG1is described. The upper surface of the gate electrode BG1may be positioned at a lower level than the upper surface of the active region104. In other words, the gate electrode BG1may fill a portion of the gate trench105. The gate electrode BG1may not overlap with the first doping region111and the second doping region112. The capping layer109may overlap with the first doping region111and the second doping region112. Herein, “overlap” means overlapping in a horizontal direction. Since the gate electrode BG1is buried inside of the gate trench105by the capping layer109, the gate electrode BG1may be called ‘a buried gate electrode’. The gate electrode BG1may have a bi-layer structure. The gate electrode BG1may have a bi-layer structure of the same material. The gate electrode BG1may be formed of a polycrystalline material. The gate electrode BG1may be formed of a polycrystalline material of columnar grains. The gate electrode BG1may include a polycrystalline material of different crystal grains. The gate electrode BG1may include a first crystal grain layer107and a second crystal grain layer108. The first crystal grain layer107may be formed over the gate dielectric layer106along the internal wall of the gate trench105. The first crystal grain layer107may be a thin layer. For example, the first crystal grain layer107may be a continuous layer that is formed in a uniform thickness along the internal wall of the gate trench105. Therefore, the first crystal grain layer107may be called a liner layer. The first crystal grain layer107may cover most of the gate dielectric layer106. The second crystal grain layer108disposed over the first crystal grain layer107may fill the gate trench105. Therefore, the second crystal grain layer108may be called ‘a filling gate conductor layer’. The second crystal grain layer108may fill most of the gate trench105. The first crystal grain layer107may be disposed between the second crystal grain layer108and the gate dielectric layer106. As a result, the second crystal grain layer108may not contact the gate dielectric layer106. The first crystal grain layer107may be disposed to cover the side surface and lower surface of the gate dielectric layer106inside of the gate trench105. The second crystal grain layer108may be disposed in such a manner that the side surface and lower surface of the second crystal grain layer108are surrounded by the first crystal grain layer107inside of the gate trench105. The first crystal grain layer107and the second crystal grain layer108may be formed of the same material. The first crystal grain layer107and the second crystal grain layer108may include a metal-based material to decrease the resistance of the gate electrode BG1. The first crystal grain layer107and the second crystal grain layer108may be formed of low-resistance metals. The first crystal grain layer107and the second crystal grain layer108may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. According to the embodiment of the present invention, the first crystal grain layer107and the second crystal grain layer108may be formed of a titanium nitride (TiN). Since the first crystal grain layer107and the second crystal grain layer108are formed of the same material, the gate electrode BG1may be called a buried gate electrode of a single material. For example, the gate electrode BG1may be formed of a titanium nitride alone. In other words, the gate electrode BG1may have ‘a TiN-only structure.’ The TiN-only structure may be able to decrease the resistance further lower than a TiN/W structure, which is a by-layer structure of a titanium nitride (TiN) and tungsten (W), and the TiN-only structure may perform gap-filling easily. Preferably, the first crystal grain layer107and the second crystal grain layer108may be formed of a fluorine-free material to prevent attacking the gate dielectric layer106by fluorine. The fluorine-free material refers to a material that does not contain fluorine. FIGS.3A and3Bare cross-sectional views comparing the size of crystal grains of the gate electrodes BG1. Referring toFIG.3A, the first crystal grain layer107may include a plurality of first crystal grains107G. The first crystal grains107G may be able to cover most of the gate dielectric layer106. The second crystal grain layer108may include a plurality of second crystal grains108G. The second crystal grains108G do not contact the gate dielectric layer106because of the first crystal grains107G which are disposed between the second crystal grains108G and the gate dielectric layer106. The first crystal grains107G and the second crystal grains108G may have different crystal grain sizes. For example, the size of the crystal grains of the first crystal grains107G may be smaller than the size of the crystal grains of the second crystal grains108G. The first crystal grains107G may have a small grain size, and the second crystal grains108G may have a large grain size. The first crystal grains107G and the second crystal grains108G may be metal crystal grains or metal nitride crystal grains. The size of crystal grains may be defined as an average grain size. Each of the first crystal grains107G may have a different crystal grain size. Also, each of the second crystal grains108G may have a different crystal grain size. Although the crystal grains have different sizes, the average crystal grain size of the first crystal grains107G may be smaller than the average crystal grain size of the second crystal grains108G. Although the first crystal grain layer107and the second crystal grain layer108include the same material, it may be possible to control the crystal grain sizes of the first crystal grains107G and the second crystal grains108G to be different from each other. When the first crystal grain layer107and the second crystal grain layer108be formed of a titanium nitride (TiN), the first crystal grains107G may be TiN crystal grains having a small crystal grain size, and the second crystal grains108G may be TiN crystal grains having a large crystal grain size. The first crystal grains107G and the second crystal grains108G may be of a columnar structure. The crystal grain sizes of the first crystal grains107G and the second crystal grains108G may be controlled by employing an annealing process. For example, the initial material for forming the first crystal grains107G and the second crystal grains108G may be crystalized through a subsequent annealing process. Through the annealing process, the initial material may be converted into the first crystal grains107G and the second crystal grains108G. The first crystal grains107G may have a small crystal grain size, and the second crystal grains108G may have a large crystal grain size. The second crystal grain layer108may include voids108V. The first crystal grain layer107may not include the voids108V. The voids108V may be generated and grow up while a deposition process and the annealing process are performed to form the second crystal grain layer108. For example, the voids108V may be formed between the second crystal grains108G. FIG.3Bis a cross-sectional view describing a case where the gate trench105is filled only with the second crystal grain layer108. Referring toFIG.3B, when the gate trench105is filled only with the second crystal grain layer108, the voids108V may be disposed on the interface between the second crystal grains108G and the gate dielectric layer106. Therefore, when the gate trench105is filled only with the second crystal grain layer108, delamination may occur by the voids108V. FIGS.4A and4Bare cross-sectional views comparing the buried gate electrodes around the fin region.FIG.4Ashows a result of disposing the first crystal grain layer107between the gate dielectric layer106and the second crystal grain layer108.FIG.4Bshows the gate trench105is filled only with the second crystal grain layer108. Referring toFIG.4A, the upper surface and side walls of the fin region110may be covered by the second crystal grains108G. Therefore, the voids108V may be disposed on the interface between the second crystal grains108G and the gate dielectric layer106. As illustrated inFIGS.3A and4A, the voids108V may not be disposed between the gate dielectric layer106and the first crystal grain layer107due to the first crystal grains107G. In this way, delamination may be suppressed. As a result, the interface characteristics between the gate electrode BG1and the gate dielectric layer106may be improved. Also, the second crystal grains108G may decrease the resistance of the gate electrode BG1. Since most of the gate trench105is filled with the second crystal grains108G having a large crystal grain size, the resistance of the gate electrode BG1may be decreased. As a comparative example, when the thickness of the first crystal grain layer107is increased, the resistance of the first crystal grain layer107may be increased due to the increase in the number of the first crystal grains107G. In short, the small crystal grain size of the first crystal grains107G may increase the resistance of the first crystal grain layer107. Therefore, the first crystal grain layer107may be formed to be thin so that the voids108V and the delamination may be improved. The first crystal grain layer107may preferably be formed in a thickness of approximately 100 Å or less. FIGS.5A and5Bare cross-sectional views of a semiconductor device in accordance with a first modified example of an embodiment of the present invention,FIG.5Ais a cross-sectional view of the semiconductor device taken along a line A-A′ in accordance with the first modified example of an embodiment of the present invention.FIG.5Bis a cross-sectional view of the semiconductor device taken along a line B-B′ in accordance with the first modified example of an embodiment of the present invention. Referring toFIGS.5A and5B, the semiconductor device100M may not include the fin region110. The constituent elements of the semiconductor device100M may be the same as the semiconductor device100ofFIG.2A, In the semiconductor device100M, the bottom surface of the first trench105A and the bottom surface of the second trench105B are positioned at the same level. Hence, according to the modified embodiment shown inFIGS.5A and5Bthe bottom surface of the first trench105A may be positioned at the same level as the bottom surface of the second trench105B. FIGS.6A and6Bare cross-sectional views of semiconductor devices100M1and100M2in accordance with second modified examples of an embodiment of the present invention. Referring toFIG.6A, the constituent elements except for a gate electrode BG1′ may be the same as the constituent elements of the semiconductor device100ofFIG.2A. In the semiconductor device100M1, the upper portion of the gate electrode BG1′ may partially overlap with the first doping region111and the second doping region112. The lower portion of the gate electrode BG1′ may overlap with a side wall of the gate trench105by a first height H1. The first height H1may be defined as a height between the lower surfaces of the first doping region111and the second doping region112and the lowermost part of the gate trench105. The upper portion of the gate electrode BG1′ may overlap with the first doping region111and the second doping region112by a second height H2. The first height H1may be longer than the second height H2. Referring toFIG.6B, the semiconductor device100M2is substantially identical to the semiconductor device100M1ofFIG.6Aexcept that the semiconductor device100M2does not include the fin region110. FIGS.7A to8Gare cross-sectional views illustrating a first example of a method for fabricating the semiconductor device in accordance with an embodiment of the present invention. Hereafter,FIGS.7A to8Gillustrate the first example of the method for fabricating the semiconductor device100shown inFIGS.2A and2B.FIGS.7A to7Gare cross-sectional views of the semiconductor device100taken along the line A-A′ shown inFIG.1.FIGS.8A to8Gare cross-sectional views of the semiconductor device100taken along the line B-B′ shown inFIG.1. Referring toFIGS.7A and8A, an isolation layer12may be formed in a substrate11. The isolation layer12may define an active region14. The isolation layer12may be formed through a Shallow Trench Isolation (STI) process. The STI process may be performed as follows. An isolation trench13may be formed by etching the substrate11. The isolation trench13may be filled with a dielectric material. As a result, the isolation layer12may be formed. The isolation layer12may be formed of any suitable material including, for example, a silicon oxide, a silicon nitride, or a combination thereof. The isolation trench13may be filled with a dielectric material through a Chemical Vapor Deposition (CVD) process or another deposition process. Also, a planarization process, such as Chemical-Mechanical Polishing (CMP) may be additionally performed following the deposition of the dielectric material. A hard mask layer15may be formed over the substrate11. The hard mask layer15may be formed of a material having an etch selectivity with respect to the substrate11. The hard mask layer15may be formed of any suitable material including, for example, a silicon oxide. In an embodiment, the hard mask layer15may include TEOS (Tetra-Ethyl-Ortho-Silicate). A gate trench16may be formed in the substrate11. The gate trench16may have a shape of a line that intersects with the active region14and the isolation layer12. The gate trench16may be formed by forming a mask pattern (not shown) over the substrate11, and performing an etch process by using the mask pattern as an etch mask. The gate trench16may be formed to be shallower than the isolation trench13. The depth of the gate trench16may be sufficiently deep to make a large average cross-sectional area of a buried gate electrode, which is to be formed subsequently. In this way, the resistance of the buried gate electrode may be decreased. The bottom edge of the gate trench16inFIG.7Ais substantially flat, however, the invention is not limited in this way. For example, in an embodiment, the bottom edge of the gate trench16may have a curvature. The curvature may reduce substantially the depression and protrusion in the bottom portion of the gate trench16, and may thus facilitate the filling of the gate electrode. A fin region14F may be formed. The fin region14F may be formed by recessing a portion of the isolation layer12. For example, the fin region14F may be formed by selectively removing the isolation layer12below the gate trench16. The side wall of the fin region14F may be exposed through the recessed isolation layer12F. Although not illustrated, after the fin region14F is formed, a channel doping may be performed. The channel doping may be performed onto the bottom and side walls of the gate trench16. In addition, a local channel doping may be performed onto the bottom of the gate trench16. When the channel doping is performed, the doping concentration may be controlled. Subsequently, a gate dielectric layer17may be formed onto the bottom surface and side walls of the gate trench16. The gate dielectric layer17may cover the upper surface of the recessed isolation layer12F and the side walls of the fin region14F. Before the gate dielectric layer17is formed, the surface of the gate trench16that is damaged from the etch process may be recovered. For example, a sacrificial oxide may be formed through a thermal treatment and then the sacrificial oxide may be removed. The gate dielectric layer17may be formed through a thermal oxidation process. For example, the gate dielectric layer17may be formed by oxidizing the bottom and side walls of the gate trench16. According to another embodiment of the present invention, the gate dielectric layer17may be formed through a deposition process, such as a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. When the gate dielectric layer17is formed through a deposition process, the gate dielectric layer17may cover the gate trench16and the hard mask layer15. The gate dielectric layer17may include a high-k material, such as an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include a hafnium oxide, a hafnium silicon oxide, a hafnium silicon oxynitride, or a combination thereof. The high-k material may include a lanthanum oxide, a lanthanum aluminum oxide, a zirconium oxide, a zirconium silicon oxide, a zirconium silicon oxynitride, an aluminum oxide, and combinations thereof. Other known high-k materials may also be selected and used. According to another embodiment of the present invention, the gate dielectric layer17may be formed by depositing a liner polysilicon layer and then radical-oxidizing the liner polysilicon layer. According to another embodiment of the present invention, the gate dielectric layer17may be formed by forming a liner silicon nitride layer and then radical-oxidizing the liner silicon nitride layer. Referring toFIGS.7B and8B, a first conductive layer18A may be formed over the gate dielectric layer17. The first conductive layer18A may be conformally formed on the surface of the gate dielectric layer17. The first conductive layer18A may be formed of a conductive material. The first conductive layer18A may be formed through a CVD process or an ALD process. The first conductive layer18A may be a thin layer. For example, the first conductive layer18A may be a continuous layer that is formed in a uniform thickness over the gate dielectric layer17along the internal wall of the gate trench16. The first conductive layer18A may be formed of any suitable material having a lower resistance than polysilicon. The first conductive layer18A may be formed of a metal-based material. The first conductive layer18A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. According to an embodiment of the present invention, the first conductive layer18A may include a metal nitride, or more specifically be formed of a titanium nitride (TiN). The first conductive layer18A may be polycrystalline. The first conductive layer18A may be of a titanium nitride having columnar crystal grains. In an embodiment, the first conductive layer18A may be formed in a thickness ranging from approximately 30 Å to approximately 40 Å. The first conductive layer18A may be deposited at a temperature ranging from approximately 500° C. to approximately 650° C. The temperature of approximately 500° C. to approximately 650° C. may be referred to as middle temperature MT. The first conductive layer18A may be an ALD-TiN that is formed of TiCl4and NH3. The ALD-TiN may be deposited at the temperature of approximately 500° C. to approximately 650° C. Therefore, in an embodiment, the first conductive layer18A may include an MT-ALD TiN. Referring toFIGS.7C and8C, a physical damage process19may be performed. The physical damage process19may include a process that may damage the first conductive layer18A. The physical damage process19may include a Reactive Ion Etching (RIE) process or an ion implantation process. Through the physical damage process19, the first conductive layer18A may be converted into a damaged first conductive layer18B. The damaged first conductive layer18B may be an amorphous layer. Hereafter, the damaged first conductive layer18B may be referred to as ‘an amorphous first conductive layer18B’. The first conductive layer18A before the physical damage process19is polycrystalline, but the first conductive layer18A that is exposed to the physical damage process19is converted into the amorphous first conductive layer18B. According to some embodiments of the present invention, the implantation process of the physical damage process19may use a dopant. Therefore, the amorphous first conductive layer18B may include a doped dopant. The dopant may be any suitable dopant including, for example, nitrogen (N), carbon (C), fluorine (F), ammonia (NH3) and the like. The amorphous first conductive layer18B may be doped with a dopant through the implantation process. According to some embodiments of the present invention, nitrogen (N), carbon (C), and fluorine (F) may be able to engineer the work function of the amorphous first conductive layer18B. For example, the dopant doping the amorphous first conductive layer18B may be able to engineer the work function of the amorphous first conductive layer18B into a high work function. The high work function material that covers the fin region14F may be able to improve the threshold voltage of a transistor. Referring toFIGS.7D and8D, a second conductive layer20A may be formed over the amorphous first conductive layer18B. The second conductive layer20A over the amorphous first conductive layer18B may fill the gate trench16. The amorphous first conductive layer18B and the second conductive layer20A may be formed of the same material. The second conductive layer20A may be formed through a CVD process or an ALD process. The second conductive layer20A may be formed of any suitable material having a lower resistance than polysilicon. The second conductive layer20A may be a metal-based material. The second conductive layer20A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The second conductive layer20A may be formed of a titanium nitride (TiN). The second conductive layer20A may be polycrystalline. The second conductive layer20A may be a titanium nitride having columnar crystal grains. The second conductive layer20A may fill the gate trench16. The second conductive layer20A may be formed in a thickness that is equal to or greater than approximately 200 Å. The second conductive layer20A may be deposited at a temperature ranging from approximately 500° C. to approximately 600° C. The second conductive layer20A may be an ALD-TiN that is formed of TiCl4and NH3. The ALD-TiN may be deposited at the temperature of approximately 500° C. to approximately 600° C. Therefore, the second conductive layer20A may include an MT-ALD TiN. The damaged first conductive layer18B, which is the amorphous first conductive layer18B, may increase its interface energy, when the second conductive layer20A is formed. Hence, during a subsequent annealing process, the growth of crystal grains may be delayed in the portion contacting the gate dielectric layer17. Referring toFIGS.7E and8E, a gate electrode21′ may be formed. The gate electrode21′ may include an amorphous first conductive layer pattern18′ and a second conductive layer pattern20′. The gate electrode21′ may be formed by recessing the amorphous first conductive layer18B and the second conductive layer20A through an etch-back process. The gate electrode21′ may be positioned at a lower level than the upper surface of the active region14. As a result, the gate electrode21′ may be positioned inside of the gate trench16. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. The CMP process may be performed by taking the hard mask layer15as an end point. As a result of performing the CMP process and the etch-back process onto the second conductive layer20A, the second conductive layer pattern20′ may be performed. Also, the amorphous first conductive layer pattern18′ may be formed by performing the CMP process and the etch-back process onto the amorphous first conductive layer18B. The gate electrode21′ may include the amorphous first conductive layer pattern18′ and polycrystalline second conductive layer pattern20′. The amorphous first conductive layer pattern18′ may cover the gate dielectric layer17. The polycrystalline second conductive layer pattern20′ may not contact the gate dielectric layer17. Referring toFIGS.7F and8F, an annealing process22may be performed. The second conductive layer pattern20′ and the amorphous first conductive layer pattern18′ may be exposed to the annealing process22. Through the annealing process22, crystal grains may grow up. In other words, the second conductive layer pattern20′ and the amorphous first conductive layer pattern18′ may be crystalized through the annealing process22. The annealing process22may be performed at a high temperature. For example, the annealing process22may be performed at a temperature of from approximately 300° C. to approximately 1100° C. Through the annealing process22, the gate electrode21′ may be converted into polycrystalline gate electrode21. For example, the amorphous first conductive layer pattern18′ may be converted into a polycrystalline material and the second conductive layer pattern20′ may be converted into a polycrystalline material having a larger crystal grain size. As described above, when the amorphous first conductive layer pattern18′ and the second conductive layer pattern20′ are exposed to the annealing process22, they may be converted into polycrystalline materials through a crystal grain growth. The amorphous first conductive layer pattern18′ may have a slower crystal grain growth speed than the second conductive layer pattern20′. The gate electrode21may include a first crystal grain layer18and a second crystal grain layer20. The first crystal grain layer18may be formed through the crystal grain growth of the amorphous first conductive layer pattern18′. The second crystal grain layer20may be formed through the crystal grain growth of the second conductive layer pattern20′. The first crystal grain layer18may cover the gate dielectric layer17. The first crystal grain layer18may cover the upper surface and side walls of the fin region14F. The second crystal grain layer20may fill the gate trench16over the first crystal grain layer18, The first crystal grain layer18may be disposed between the second crystal grain layer20and the gate dielectric layer17. The first crystal grain layer18may include a plurality of first crystal grains18G. The second crystal grain layer20may include a plurality of second crystal grains20G. The first crystal grains18G may correspond to the first crystal grains107G shown inFIG.3A. The second crystal grains20G may correspond to the second crystal grains108G shown inFIG.3A. For example, the first crystal grains18G and the second crystal grains20G may be metal crystal grains or metal nitride crystal grains. In an embodiment, the first crystal grains18G and the second crystal grains20G may be TiN crystal grains. Since the first crystal grains18G grow from the amorphous first conductive layer pattern18′, the first crystal grains18G may have a small crystal grain size. Since the second crystal grains20G grow from the polycrystalline second conductive layer pattern20′, the second crystal grains20G may have a large crystal grain size. Therefore, the first crystal grains18G may have a smaller crystal grain size than the second crystal grains20G. The polycrystalline second conductive layer (20A ofFIG.7D) may include a plurality of voids20V that are generated during a deposition process. While the second crystal grains20G grow through the annealing process22, the voids20V may grow or may be maintained. Therefore, the second crystal grain layer20may include the voids20V. The voids20V may have a relatively large size. Since the first crystal grain layer18is formed through the growth of the crystal grains of the amorphous first conductive layer pattern18′, the first crystal grain layer18may be substantially free of any voids or if there are any voids their size is relatively small compared to the size of the voids20V. The number of any voids in the first crystal grain layer18, if there are any, may be small. Referring toFIGS.7G and8G, a capping layer23may be formed over the gate electrode21. The capping layer23may be formed of any suitable a dielectric material. The gate trench16may be filled with the capping layer23over the gate electrode21. In an embodiment, the capping layer23may be formed of a silicon nitride. Subsequently, the capping layer23may be planarized in such a manner that the upper surface of the hard mask layer15is exposed. According to another embodiment of the present invention, the capping layer23may be formed of any suitable material including, for example, a silicon oxide, According to another embodiment of the present invention, the capping layer23may have a NON (Nitride-Oxide-Nitride) structure. As the capping layer23is formed, a buried gate structure may be formed. The buried gate structure may include the gate dielectric layer17, the first crystal grain layer18, the second crystal grain layer20, and the capping layer23. The buried gate structure may have a recessed shaped filling a portion of the gate trench16. The buried gate structure may be positioned at a lower level than the uppermost surface of the active region14. Subsequently, a first doping region24and a second doping region25may be formed. The first doping region24and the second doping region25may be formed through any suitable doping process, such as, for example, an ion implantation process. The first doping region24and the second doping region25may have the same depth. According to another embodiment of the present invention, the first doping region24may be deeper than the second doping region25. As described above, the physical damage process19is performed after the first conductive layer18A is deposited in the fabrication process according to the first example. For this reason, when the annealing process22is performed, the first crystal grains18G may be formed on the interface with the gate dielectric layer17without voids. FIGS.9A to9Dare cross-sectional views illustrating a second example of a method for fabricating the semiconductor device in accordance with an embodiment of the present invention. Hereafter,FIGS.9A to9Dillustrate the second example of the method for fabricating the semiconductor device100shown inFIG.2A. First of all, referring toFIG.7A, the structures from the isolation layer12to the gate dielectric layer17may be formed over the substrate11. Referring toFIG.9A, a first conductive layer31A may be formed over the gate dielectric layer17. The first conductive layer31A may be conformally formed on the surface of the gate dielectric layer17. The first conductive layer31A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The first conductive layer31A may be formed of a titanium nitride (TiN). The first conductive layer31A may be polycrystalline. The first conductive layer31A may be formed of a titanium nitride having columnar crystal grains. The first conductive layer31A may be formed in a thickness ranging from approximately 30 Å to approximately 40 Å. The first conductive layer31A may be formed through a low-temperature process31L. As a result of the low-temperature process31L, the first conductive layer31A may be formed to have a small crystal grain size. The first conductive layer31A may be formed at a lower temperature than the temperature that the first conductive layer18A shown inFIG.7Bis formed. The first conductive layer31A may be deposited at a temperature that is equal to or lower than approximately 500° C. The temperature of approximately 500° C. or lower may be referred to as low temperature LT. The first conductive layer31A may be formed of TiCl4and NH3. The first conductive layer31A may be formed of a titanium nitride (LT-TiN) that is deposited at a low temperature. The first conductive layer31A may be formed of a titanium nitride (ALD-TiN) that is formed through an Atomic Layer Deposition (ALD) process. The ALD-TiN may be deposited at a temperature ranging from approximately 50° C. to approximately 500° C. The first conductive layer31A may include an LT-ALD-TiN. As described above, agglomeration occurring on the interface between the first conductive layer31A and the gate dielectric layer17may be delayed during a subsequent annealing process by forming the first conductive layer31A to have a small crystal grain size. In short, the growth of crystal grains of the first conductive layer31A may be delayed on the interface between the first conductive layer31A and the gate dielectric layer17. When the first conductive layer31A is deposited through the low-temperature process31L, the crystal grain size of the first conductive layer31A may be smaller than the crystal grain size of the first conductive layer18A (seeFIG.7B) that is deposited at the middle temperature MT. Referring toFIG.9B, a second conductive layer32A may be formed over the first conductive layer31A. The second conductive layer32A over the first conductive layer31A may fill the gate trench16. The second conductive layer32A and the first conductive layer31A may be formed of the same material. The second conductive layer32A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The second conductive layer32A may be formed of a titanium nitride (TiN). The second conductive layer32A may be polycrystalline. The second conductive layer32A may be a titanium nitride having columnar crystal grains. The second conductive layer32A may be formed through a high-temperature process32H. The second conductive layer32A may be deposited at a higher temperature than the temperature that the first conductive layer31A is deposited. When the second conductive layer32A is deposited through the high-temperature process32H, the crystal grain size of the second conductive layer32A that is deposited through the high-temperature process32H may be larger than the crystal grain size of the second conductive layer32A that is deposited at the middle temperature MT. The second conductive layer32A may be formed to have a larger crystal grain size than the crystal grain size of the first conductive layer31A. The second conductive layer32A may be formed at a temperature of from approximately 600° C. or higher. The temperature of approximately 600° C. or higher may be called high temperature HT. The second conductive layer32A may be formed of TiCl4and NH3. The second conductive layer32A may be formed of a titanium nitride (HT-TiN) that is deposited at a high temperature. The second conductive layer32A may be formed of a titanium nitride (ALD-TiN) that is formed through an Atomic Layer Deposition (ALD) process. The ALD-TiN may be deposited at a temperature of from approximately 600° C. or higher. The second conductive layer32A may include a HT-ALD-TiN. As described above, since the second conductive layer32A is formed to have a large crystal grain size, the resistance may be decreased. Referring toFIG.9C, a gate electrode33′ may be formed. The gate electrode33′ may include a first conductive layer pattern31′ and a second conductive layer pattern32′. The gate electrode33′ may be formed by recessing the first conductive layer31A and the second conductive layer32A through an etch-back process. The gate electrode33′ may be positioned at a lower level than the upper surface of the active region14. As a result, the gate electrode33′ may be positioned inside of the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. The CMP process may be performed by taking the hard mask layer15as an end point. As a result of performing the CMP process and the etch-back process onto the second conductive layer32A, the second conductive layer pattern32′ may be performed. Also, the first conductive layer pattern31′ may be formed by performing the CMP process and the etch-back process onto the first conductive layer31A. The gate electrode33′ may include the first conductive layer pattern31′ and the second conductive layer pattern32′. The first conductive layer pattern31′ and the second conductive layer pattern32′ may be polycrystalline. The first conductive layer pattern31′ may include crystal gains of small crystal grain sizes. The second conductive layer pattern32′ may include crystal gains of large crystal grain sizes. The first conductive layer pattern31′ may include the LT-TiN, The second conductive layer pattern32′ may include the HT-TiN. The first conductive layer pattern31′ may cover and contact the gate dielectric layer17. The second conductive layer pattern32′ may not contact the gate dielectric layer17. Referring toFIG.9D, an annealing process34may be performed. The second conductive layer pattern32′ and the first conductive layer pattern31′ may be exposed to the annealing process34. Through the annealing process34, crystal grains may grow up. In other words, the second conductive layer pattern32′ and the first conductive layer pattern31′ may be crystalized through the annealing process34. The annealing process34may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process34, the gate electrode33′ may be converted into a gate electrode33with grown crystal grains. The gate electrode33may include a first crystal grain layer31and a second crystal grain layer32. The first crystal grain layer31may be formed as the crystal grains of the first conductive layer pattern31′ grow up. The second crystal grain layer32may be formed as the crystal grains of the second conductive layer pattern32′ grow up. The first crystal grain layer31may cover and contact the gate dielectric layer17. The first crystal grain layer31may cover the upper surface and side walls of the fin region14F. The second crystal grain layer32may fill the gate trench16over the first crystal grain layer31. The first crystal grain layer31may be disposed between the second crystal grain layer32and the gate dielectric layer17. The first crystal grain layer31may include a plurality of first crystal grains31G. The second crystal grain layer32may include a plurality of second crystal grains32G. The first crystal grains31G may correspond to the first crystal grains107G ofFIG.3A. The second crystal grains32G may correspond to the second crystal grains108G ofFIG.3A. The first crystal grains31G and the second crystal grains32G may be TiN crystal grains. Since the first crystal grains31G grow up from the first conductive layer pattern31′, the first crystal grains31G may have a small crystal grain size. Since the second crystal grains32G grow up from the second conductive layer pattern32′, the second crystal grains32G may have a large crystal grain size. Therefore, the crystal grain size of the first crystal grains31G may be smaller than the crystal grain size of the second crystal grains32G. The crystal grain size of the first crystal grains31G may be larger than the crystal grain size of the first conductive layer31A. Also, the crystal grain size of the second crystal grains32G may be larger than the crystal grain size of the second conductive layer32A. The difference between the crystal grain size after the deposition process and the crystal grain size after the annealing process34may originate from the growth of the crystal grains through the annealing process34. When the first conductive layer pattern31′ having a small crystal grain size is exposed to the annealing process34, agglomeration occurring on the interface between the first conductive layer pattern31′ and the gate dielectric layer17may be delayed. As a result, the growth of the crystal grains of the first conductive layer pattern31′ may be delayed on the interface between the first conductive layer31A and the gate dielectric layer17. Hence, the first crystal grains31G contacting the gate dielectric layer17may grow up in a small crystal grain size. Conversely, the second crystal grains32G that do not contact the gate dielectric layer17may grow up in a large crystal grain size. The second conductive layer (32A ofFIG.9B) may include a plurality of voids32V that are generated during a deposition process. While the second crystal grains32G grow through the annealing process34, the voids32V may grow or may be maintained. Therefore, the second crystal grain layer32may include the voids32V. The voids32V may have relatively large sizes. Since the first crystal grain layer31is formed through the growth of the crystal grains of the first conductive layer pattern31′, the first crystal grain layer31may be substantially free of voids. According to another embodiment of the present invention, there may be some voids in the first crystal grain layer31, however, their size and number may be substantially smaller than the size and number of the32V voids. Subsequently, through the method illustrated inFIG.7G, the capping layer23, the first doping region24, and the second doping region25may be sequentially formed. FIG.10is a cross-sectional view illustrating a semiconductor device200in accordance with an embodiment of the present invention. The semiconductor device200is identical to the semiconductor device100ofFIG.2Aexcept for a gate electrode207. The semiconductor device200may include a substrate101, a gate trench105, a fin region110, a buried gate structure200G, a first doping region111, and a second doping region112. The buried gate structure200G may include a gate dielectric layer106, a gate electrode207, and a capping layer109. Whereas the gate electrode BG1of the semiconductor device100has a bi-layer structure, the gate electrode207has a single-layer structure. In other words, a conductive layer for forming the gate electrode207may be formed at a uniform temperature without a change in the deposition temperature or a physical damage process. The conductive layer may be able to fill the gate trench105through a low-temperature process or a high-temperature process. Referring toFIG.10, the gate electrode207may be polycrystalline. The gate electrode207may include first crystal grains207G1and second crystal grains207G2. The first crystal grains207G1may have a small crystal grain size. The second crystal grains207G2may have a larger crystal grain size than the first crystal grains207G1. The gate electrode207may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. According to an embodiment of the present invention, the gate electrode207may be formed of a titanium nitride (TiN). The first crystal grains207G1and the second crystal grains207G2may be TiN crystal grains. The first crystal grains207G1may be first TiN crystal grains having a small crystal grain size. The second crystal grains207G2may be second TiN crystal grains having a larger crystal grain size than the first TiN crystal grains. The first crystal grains207G1and the second crystal grains207G2may be TiN crystal grains that are deposited at a low temperature, that is, TiN crystal grains that grow up from LT-TiN. According to another embodiment of the present invention, the first crystal grains207G1and the second crystal grains207G2may be TiN crystal grains that are deposited at a high temperature, that is, TiN crystal grains that grow up from HT-TiN. Although TiN crystal grains are deposited at a low temperature or a high temperature, the crystal grains may grow at different growth speeds on the interface that the crystal grains contact the gate dielectric layer106and in a portion that the crystal grains fill the gate trench105. Therefore, the crystal grain size of the first crystal grains207G1contacting the gate dielectric layer106may be smaller than the crystal grain size of the second crystal grains207G2filling the gate trench105. As described above, no voids may be positioned on the interface with the gate dielectric layer106due to the first crystal grains207G1. In this way, delamination may be suppressed. As a result, the first crystal grains207G1may improve the interface characteristics between the gate electrode207and the gate dielectric layer106. Meanwhile, there may be voids207V among the second crystal grains207G2. Also, since most of the gate trench105is filled with the second crystal grains207G2, the resistance of the gate electrode207may be decreased. FIGS.11A to11Dare cross-sectional views illustrating a first example of a method for fabricating the semiconductor device200in accordance with an embodiment of the present invention shown inFIG.10. First of all, as illustrated inFIG.7A, the structures from the isolation layer12to the gate dielectric layer17may be formed over the substrate11. Subsequently, referring toFIG.11A, a conductive layer41A may be formed over the gate dielectric layer17. The conductive layer41A over the gate dielectric layer17may completely fill the gate trench16. The conductive layer41A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The conductive layer41A may be formed of a titanium nitride (TiN), The conductive layer41A may be a polycrystalline layer. The conductive layer41A may be formed of a titanium nitride (TiN) of columnar crystal grains. The conductive layer41A may be formed through a low-temperature process41L. As a result of the low-temperature process41L, the conductive layer41A may include crystal grains of a small crystal grain size. As the conductive layer41A is formed to have a small crystal grain size, agglomeration on the interface between the conductive layer41A and the gate dielectric layer17may be delayed during a subsequent annealing process. In short, the growth of crystal grains of the conductive layer41A may be delayed on the interface between the conductive layer41A and the gate dielectric layer17. The conductive layer41A may be formed at a temperature that is equal to or lower than approximately 500° C. The conductive layer41A may be formed by reacting TiCl4and NH3. The conductive layer41A may be formed of a titanium nitride (LT-TiN) that is deposited at a low temperature. The conductive layer41A may be formed of a titanium nitride (ALD-TiN) that is formed through an Atomic Layer Deposition (ALD) process. The ALD-TiN may be deposited at a temperature ranging from approximately 50° C. to approximately 500° C. The conductive layer41A may include an LT-ALD-TiN. According to the embodiment of the present invention, which is described above, the gate trench16may be completely filled with the conductive layer41A through the low-temperature process41L. Referring toFIG.11B, a post-process42may be performed. Through the post-process42, impurities of the conductive layer41A may be removed. For example, an impurity contained in the conductive layer41A, such as chlorine (Cl), may be removed from the conductive layer41A. The post-process42may be performed in an atmosphere of hydrogen. The post-process42may include a Rapid Thermal Annealing (RTA) process. The post-process42may include a hydrogen Rapid Thermal Annealing (H-RTA) process. According to another embodiment of the present invention, the post-process42may include a Rapid Thermal Annealing (NH3-RTA) process that is performed in the atmosphere of ammonia (NH3), or a helium (He) plasma treatment. As described above, it is possible to remove the impurities from the conductive layer41A by performing the post-process42onto the conductive layer41A that is deposited through the low-temperature process41L. When the impurities are removed from the conductive layer41A, the agglomeration on the interface between the conductive layer41A and the gate dielectric layer17may be further delayed during the subsequent annealing process. Therefore, the growth of the crystal grains of the conductive layer41A may be further delayed on the interface between the conductive layer41A and the gate dielectric layer17. Referring toFIG.11C, a conductive layer pattern41′ may be formed. The conductive layer pattern41′ may be formed by recessing the conductive layer41A through an etch-back process. The conductive layer pattern41′ may be positioned at a lower level than the upper surface of the active region14. As a result, the conductive layer pattern41′ may be positioned inside of the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. Referring toFIG.11D, an annealing process43may be performed. The conductive layer pattern41′ may be exposed to the annealing process43. Through the annealing process43, crystal grains may grow up. In other words, the conductive layer pattern41′ may be crystalized through the annealing process43. The annealing process43may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process43, the conductive layer pattern41′ may be converted into a polycrystalline gate electrode41. The gate electrode41may include first crystal grains41G1and second crystal grains41G2. The first crystal grains41G1and the second crystal grains41G2may be formed through the growth of the crystal grains of the conductive layer pattern41′. The first crystal grains41G1may be able to cover and contact the gate dielectric layer17. The first crystal grains41G1may be able to cover the upper surface and side walls of the fin region14F. The second crystal grains41G2are crystal grains formed over the first crystal grains41G1and may fill the gate trench16. The first crystal grains41G1may be positioned between the second crystal grains41G2and the gate dielectric layer17. The first crystal grains41G1and the second crystal grains41G2may be TiN crystal grains. The first crystal grains41G1may correspond to the first crystal grains207G1shown inFIG.10. The second crystal grains41G2may correspond to the second crystal grains207G2shown inFIG.10. When the conductive layer pattern41′ deposited at a low temperature is exposed to the annealing process43, agglomeration occurring on the interface between the conductive layer pattern41′ and the gate dielectric layer17may be delayed. As a result, the growth of the crystal grains of the conductive layer pattern41′ may be delayed on the interface between the conductive layer pattern41′ and the gate dielectric layer17. As a result, the first crystal grains41G contacting the gate dielectric layer17may grow up in a small crystal grain size. Conversely, the second crystal grains42G that do not contact the gate dielectric layer17may grow up in a large crystal grain size. The second crystal grains41G2may include voids41V. The first crystal grains41G1may be substantially free of any voids. Even if there are some voids among the first crystal grains41G1, their size and number may be substantially smaller than that of the voids41V in the second crystal grains41G2. Subsequently, through the method illustrated inFIG.7G, the capping layer23, the first doping region24, and the second doping region25may be formed. FIGS.12A to12Dare cross-sectional views illustrating a second example of a method for fabricating the semiconductor device200in accordance with an embodiment of the present invention shown inFIG.10. First of all, as illustrated inFIG.7A, the structures from the isolation layer12to the gate dielectric layer17may be formed over the substrate11. Subsequently, referring toFIG.12A, a conductive layer51A may be formed over the gate dielectric layer17. The conductive layer51A may be formed over the gate dielectric layer17and may completely fill the gate trench16. The conductive layer51A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The conductive layer51A may be formed of a titanium nitride (TiN). The conductive layer51A may be polycrystalline. The conductive layer51A may be formed of a titanium nitride (TiN) of columnar crystal grains. The conductive layer51A may be formed through a high-temperature process51H. When the conductive layer51A is deposited through the high-temperature process51H, the amount of impurities in the conductive layer51A may be decreased. The conductive layer51A may be formed at a high temperature HT of approximately 600° C. or higher. The conductive layer51A may be formed by reacting TiCl4and NH3. The conductive layer51A may be formed of a titanium nitride (HT-TiN) that is deposited at a high temperature. In the HT-TiN, the amount of impurity, such as chlorine (Cl), may be decreased. To decrease the amount of the impurities, when the TiCl4/NH3are employed, the amount of purge of NH3may be increased. The conductive layer51A may be formed of a titanium nitride (ALD-TiN) that is formed through an Atomic Layer Deposition (ALD) process. The ALD-TiN may be deposited at a temperature of from approximately 600° C. or higher. The conductive layer51A may include an HT-ALD-TiN. As the conductive layer51A is formed to have a decreased amount of impurities in the conductive layer51A through the high-temperature process51H, agglomeration on the interface between the conductive layer51A and the gate dielectric layer17may be delayed during a subsequent annealing process. Referring toFIG.12B, a post-process52may be performed. Through the post-process52, the remaining impurities of the conductive layer51A may be removed. For example, an impurity contained in the conductive layer51A, such as chlorine (Cl), may be discharged52A to the outside. The post-process52may be performed in the atmosphere of hydrogen. The post-process52may include a Rapid Thermal Annealing (RTA) process. According to another embodiment of the present invention, the post-process52may include a Rapid Thermal Annealing (NH3-RTA) process that is performed in the atmosphere of ammonia (NH3), or a helium (He) plasma treatment. As described above, it is possible to remove the impurities from the conductive layer51A by performing the high-temperature process51H and the post-process52onto the conductive layer51A. When the impurities are removed from the conductive layer51A, the agglomeration on the interface between the conductive layer51A and the gate dielectric layer17may be further delayed during the subsequent annealing process. Therefore, the growth of the crystal grains of the conductive layer51A may be further delayed on the interface between the conductive layer51A and the gate dielectric layer17. Referring toFIG.12C, a conductive layer pattern51′ may be formed. The conductive layer pattern51′ may be formed by recessing the conductive layer51A through an etch-back process. The conductive layer pattern51′ may be positioned at a lower level than the upper surface of the active region14. As a result, the conductive layer pattern51′ may be positioned inside the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. Referring toFIG.12D, an annealing process53may be performed. The conductive layer pattern51′ may be exposed to the annealing process53. Through the annealing process53, crystal grains may grow up. In other words, the conductive layer pattern51′ may be crystalized through the annealing process53. The annealing process53may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process53, the conductive layer pattern51′ may be converted into a polycrystalline gate electrode51. The gate electrode51may include first crystal grains51G1and second crystal grains51G2. The first crystal grains51G1and the second crystal grains51G2may be formed through the growth of the crystal grains of the conductive layer pattern51′. The first crystal grains51G1may be able to cover and contact the gate dielectric layer17. The first crystal grains51G1may be able to cover the upper surface and side walls of the fin region14F. The second crystal grains51G2over the first crystal grains51G1may fill the gate trench16. The first crystal grains51G1may be positioned between the second crystal grains51G2and the gate dielectric layer17. The first crystal grains51G1may correspond to the first crystal grains207G1shown inFIG.10. The second crystal grains51G2may correspond to the second crystal grains207G2shown inFIG.10. When the conductive layer pattern51′ onto which the high-temperature process51H and the post-process52are performed is exposed to the annealing process53, agglomeration occurring on the interface between the conductive layer pattern51′ and the gate dielectric layer17may be delayed. As a result, the growth of the crystal grains of the conductive layer pattern51′ may be delayed on the interface between the conductive layer pattern51′ and the gate dielectric layer17. After all, the first crystal grains51G contacting the gate dielectric layer17may grow up in a small crystal grain size. Conversely, the second crystal grains52G that do not contact the gate dielectric layer17may grow up in a large crystal grain size. The second crystal grains51G2may include voids51V. The first crystal grains51G1may be substantially free of any voids. In another embodiment, even though there may be some voids in the first crystal grains51G1, their size and number may be substantially smaller than the voids51V in the second crystal grains51G2. Subsequently, through the method illustrated inFIG.7G, the capping layer23, the first doping region24, and the second doping region25may be formed. FIG.13is a cross-sectional view illustrating a semiconductor device300in accordance with a third embodiment of the present invention. The semiconductor device300in accordance with the third embodiment of the present invention may be similar to the semiconductor device100ofFIG.2Aexcept for a buried gate structure300G. Referring toFIG.13, the semiconductor device300may include the buried gate structure300G. The buried gate structure300G may be formed inside of a gate trench105. The buried gate structure300G may include a gate dielectric layer106, a crystallization delay layer320, a gate electrode308, and a capping layer109. The gate dielectric layer106may be formed of any suitable dielectric material including, for example, an oxide. In an embodiment, the gate dielectric layer106may be formed of a silicon oxide. The crystallization delay layer320may include a nitrogen-rich layer that contains a high concentration of nitrogen. The crystallization delay layer320may include a nitrogen-rich silicon oxynitride (N-rich SiON) or a nitrogen-rich silicon nitride. The crystallization delay layer320may include approximately 30 to 40 at % of nitrogen. The crystallization delay layer320may be formed by nitriding the upper surface of the gate dielectric layer106(seeFIGS.14A to14E). According to another embodiment of the present invention, the crystallization delay layer320may be formed through an Atomic Layer Deposition (ALD) process (seeFIGS.15A to15E). The gate electrode308may be polycrystalline. The gate electrode308may include first crystal grains308G1and second crystal grains308G2. The first crystal grains308G1may have a smaller crystal grain size than the second crystal grains308G2. The gate electrode308may have a single-layer structure. In other words, a conductive layer for forming the gate electrode308may be formed at a uniform temperature without a change in the temperature for a deposition process. The conductive layer may fill the gate trench105through a low-temperature process, a middle-temperature process, or a high-temperature process. The gate electrode308may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. According to an embodiment of the present invention, the gate electrode308may be formed of a titanium nitride (TiN). The first crystal grains308G1and the second crystal grains207G2may be TiN crystal grains. The first crystal grains308G1may be TiN crystal grains having a small crystal grain size. The second crystal grains308G2may be TiN crystal grains having a large crystal grain size. The small crystal grain size of the first crystal grains308G1may be controlled by employing the crystallization delay layer320. The high nitrogen concentration of the crystallization delay layer320may increase an interface trap charge density (Qit) and a fixed charge density (Qf). As the interface trap charge density (Qit) and the fixed charge density (Qf) are increased, the interface energy may be raised. The high interface energy may delay the growth of the crystal grains of the first crystal grains308G1contacting the crystallization delay layer320. Since the first crystal grains308G1having a small crystal grain size is formed by the crystallization delay layer320, there may be substantially no voids on the interface between the gate electrode308and the gate dielectric layer106. In this way, delamination may be suppressed. Also, since the second crystal grains308G2having a relatively large crystal grain size fill most of the gate trench105, the resistance of the gate electrode308may be decreased. FIGS.14A to14Eare cross-sectional views illustrating a first example of a method for fabricating the semiconductor device300in accordance with the third embodiment of the present invention shown inFIG.13. First of all, as illustrated inFIG.7A, the structures up to the gate dielectric layer17may be formed. The gate dielectric layer17may be formed of any suitable material including, for example, a silicon oxide. Subsequently, referring toFIG.14A, a crystallization delay layer61A may be formed over the gate dielectric layer17. The crystallization delay layer61A may include a nitrogen-rich layer containing a high concentration of nitrogen. The crystallization delay layer61A may include a nitrogen-rich silicon oxynitride (N-rich SiON), The nitrogen-rich silicon oxynitride may include approximately 30 to 40 at % of nitrogen. The crystallization delay layer61A may be formed through a plasma nitridation61P may be performed. The plasma nitridation61P may be performed by raising the flow rate of a nitrogen-containing gas. As a result, the concentration of nitrogen of the crystallization delay layer61A may be increased. Through the plasma nitridation61P, the surface of the gate dielectric layer17may be nitrided. Therefore, the crystallization delay layer61A may be formed over the gate dielectric layer17and a hard mask layer15. Referring toFIG.14B, a conductive layer62A may be formed over the crystallization delay layer61A. The conductive layer62A over the crystallization delay layer61A may completely fill the gate trench16. The conductive layer62A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The conductive layer62A may be formed of a titanium nitride (TIN). The conductive layer62A may be polycrystalline. The conductive layer62A may be formed of a titanium nitride (TiN) of columnar crystal grains. The conductive layer62A may be formed at a temperature which is a low-temperature process, a high-temperature process, or a middle-temperature process. The conductive layer62A may be a titanium nitride (ALD-TiN) that is formed of TiCl4and NH3. The conductive layer62A may include an LT-ALD TiN, an MT-ALD TiN, or an HT-ALD TiN. As described above, as the conductive layer62A is formed over the crystallization delay layer61A, agglomeration on the interface between the conductive layer62A and the crystallization delay layer61A may be delayed during a subsequent annealing process. In short, the growth of crystal grains of the conductive layer62A may be delayed on the interface between the conductive layer62A and the crystallization delay layer61A. Referring toFIG.14C, a conductive layer pattern62′ may be formed. The conductive layer pattern62′ may be formed by recessing the conductive layer62A through an etch-back process. The conductive layer pattern62′ may be positioned at a lower level than the upper surface of the active region14. As a result, the conductive layer pattern62′ may be positioned inside of the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. During the etch-back process for forming the conductive layer pattern62′, the gate dielectric layer17may be protected by the crystallization delay layer61A. Therefore, it is possible to protect the gate dielectric layer17from being damaged on the side wall of the upper portion of the gate trench16. According to another embodiment of the present invention, after the conductive layer pattern62′ is formed, the crystallization delay layer61A may be recessed. In this case, the upper surface of the crystallization delay layer61A and the upper surface of the conductive layer pattern62′ may be positioned at the same level. Referring toFIG.14D, an annealing process63may be performed. The conductive layer pattern62′ may be exposed to the annealing process63. Through the annealing process63, crystal grains may grow up. In other words, the conductive layer pattern62′ may be crystalized through the annealing process63. The annealing process63may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process63, a polycrystalline gate electrode62may be formed. The gate electrode62may be formed through the growth of the crystal grains of the conductive layer pattern62′. The gate electrode62may include first crystal grains62G1and second crystal grains62G2. The first crystal grains62G1may contact the crystallization delay layer61A. The first crystal grains62G1may cover and contact the crystallization delay layer61A. While the annealing process63is performed, the growth of the crystal grains may be delayed by the crystallization delay layer61A. Therefore, the first crystal grains62G1may be formed to have a small crystal grain size. The second crystal grains62G2do not contact the crystallization delay layer61A and, hence, may grow to have a larger crystal grain size than the first crystal grains62G1. A plurality of voids62V may be formed among the second crystal grains62G2. The voids62V may be generated during the deposition process for forming the conductive layer62A. While the crystal grains grow, the voids62V may grow as well or may be maintained. There may be substantially no voids formed among the first crystal grains62G1. Or even if, in an embodiment, there are some voids among the first crystal grains62G1, their size and their number may be substantially smaller than the voids among the second crystal grains62G2. The gate electrode62may fill a portion of the gate trench16. Referring toFIG.14E, a capping layer23may be formed over the gate electrode62, The capping layer23may include a dielectric material. The gate trench16may be filled with the capping layer23over the gate electrode62. The capping layer23may be formed of any suitable material including, for example, a silicon nitride. Subsequently, the capping layer23may be planarized in such a manner that the upper surface of the hard mask layer15may be exposed. According to another embodiment of the present invention, the capping layer23may be formed a silicon oxide. According to yet another embodiment of the present invention, the capping layer23may have an NON (Nitride-Oxide-Nitride) structure. After the capping layer23is planarizied, the crystallization delay layer61A may be planarizied. As a result, the crystallization delay layer61may be positioned inside of the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. The upper surfaces of the crystallization delay layer61, the capping layer23, and the hard mask layer15may be positioned at the same level. A buried gate structure may be completed by forming the capping layer23. The buried gate structure may include the gate dielectric layer17, the crystallization delay layer61, the gate electrode62, and the capping layer23. The buried gate structure may have a recessed shape that fills a portion of the gate trench16. The buried gate structure may be positioned at a lower level than the uppermost surface of the active region14. Subsequently, a first doping region24and a second doping region25may be formed. The first doping region24and the second doping region25may be formed any suitable doping process, such as an ion implantation process. The first doping region24and the second doping region25may have the same depth. According to another embodiment of the present invention, the first doping region24may be deeper than the second doping region25. FIGS.15A to15Eare cross-sectional views illustrating a second example of a method for fabricating the semiconductor device300in accordance with the third embodiment of the present invention shown inFIG.13. First of all, referring toFIG.7A, the structures from the isolation layer12to the gate dielectric layer17may be formed over the substrate11. The gate dielectric layer17may be formed of any suitable material including, for example, a silicon oxide. Subsequently, as illustrated inFIG.15A, a crystallization delay layer71A may be formed over the gate dielectric layer17. The crystallization delay layer71A may include a nitrogen-rich layer that contains a high concentration of nitrogen. The crystallization delay layer71A may include a nitrogen-rich silicon nitride (N-rich SiN). The nitrogen-rich silicon nitride may include approximately 30 to 40 at % of nitrogen. The crystallization delay layer71A may be formed through an Atomic Layer Deposition (ALD) process71D. The ALD process71D may use a silicon source gas and a nitrogen source gas (e.g., NH3), The ALD process71D may be performed by increasing the flow rate of the nitrogen source gas. In this way, the nitrogen concentration of the crystallization delay layer71A may be raised. The crystallization delay layer71A may be formed in a thickness thinner than approximately 10 Å. When the crystallization delay layer71A is thick, the gap-filling performance of a conductive layer, which is to be performed subsequently, becomes poor. Therefore, it is appropriate to form the crystallization delay layer71A as thin as possible. The crystallization delay layer71A may be formed through a method that is different from the method of forming the crystallization delay layer61A ofFIG.14A. Whereas the crystallization delay layer61A is formed through the plasma nitridation61P, the crystallization delay layer71A is formed through an ALD process71D. Referring toFIG.15B, a conductive layer72A may be formed over the crystallization delay layer71A. The conductive layer72A over the crystallization delay layer71A may completely fill the gate trench16. The conductive layer72A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The conductive layer72A may be formed of a titanium nitride (TiN). The conductive layer72A may be polycrystalline. The conductive layer72A may be formed of a titanium nitride (TiN) of columnar crystal grains. The conductive layer72A may be formed at a temperature which is a low-temperature process, a high-temperature process, or a middle-temperature process. The conductive layer72A may be a titanium nitride (ALD-TiN) that is formed by reacting TiCl4and NH3. The conductive layer72A may include an LT-ALD TiN, an MT-ALD TiN, or an HT-ALD TiN. As described above, as the conductive layer72A is formed over the crystallization delay layer71A, agglomeration on the interface between the conductive layer72A and the crystallization delay layer71A may be delayed during a subsequent annealing process. In short, the growth of crystal grains of the conductive layer72A may be delayed on the interface between the conductive layer72A and the crystallization delay layer71A. Referring toFIG.15C, a conductive layer pattern72′ may be formed. The conductive layer pattern72′ may be formed by recessing the conductive layer72A through an etch-back process. The conductive layer pattern72′ may be positioned at a lower level than the upper surface of the active region14. As a result, the conductive layer pattern72′ may be positioned inside of the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. Referring toFIG.15D, an annealing process73may be performed. The conductive layer pattern72′ may be exposed to the annealing process73. Through the annealing process73, crystal grains may grow up. In other words, the conductive layer pattern72′ may be crystalized through the annealing process73. The annealing process73may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process73, a polycrystalline gate electrode72may be formed. The gate electrode72may be formed through the growth of the crystal grains of the conductive layer pattern72′. The gate electrode72may include first crystal grains72G1and second crystal grains72G2. The first crystal grains72G1may contact the crystallization delay layer71A. The first crystal grains72G1may cover the crystallization delay layer71A. While the annealing process73is performed, the growth of the crystal grains may be delayed by the crystallization delay layer71A. Therefore, the first crystal grains72G1may be formed to have a small crystal grain size by the crystallization delay layer71A. The second crystal grains72G2that do not contact the crystallization delay layer71A may have a larger crystal grain size than the first crystal grains72G1. A plurality of voids72V may be formed among the second crystal grains72G2. The voids72V may be generated during the deposition process for forming the conductive layer72A. While the crystal grains grow, the voids62V may grow as well or may be maintained. There may be substantially no voids formed among the first crystal grains72G1. Even if, in an embodiment, there are some voids among the first crystal grains72G1, their size and number may be substantially smaller than the size and number of the voids62V which are formed among the second crystal grains. The gate electrode72may fill a portion of the gate trench16. Referring toFIG.15E, a capping layer23may be formed over the gate electrode72. The capping layer23may include a dielectric material. The gate trench16may be filled with the capping layer23over the gate electrode72. The capping layer23may be formed of any suitable material including, for example, a silicon nitride. Subsequently, the capping layer23may be planarized in such a manner that the upper surface of the hard mask layer15may be exposed. According to another embodiment of the present invention, the capping layer23may be formed of a silicon oxide. According to another embodiment of the present invention, the capping layer23may have an NON (Nitride-Oxide-Nitride) structure. After the capping layer23is planarizied, the crystallization delay layer61A may be planarizied. As a result, the crystallization delay layer71A may be positioned inside the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. The upper surfaces of the crystallization delay layer71, the capping layer23, and the hard mask layer15may be positioned at the same level. A buried gate structure may be completed by forming the capping layer23. The buried gate structure may include the gate dielectric layer17, the crystallization delay layer71, the gate electrode72, and the capping layer23. The buried gate structure may have a recessed shape that fills a portion of the gate trench16. The buried gate structure may be positioned at a lower level than the uppermost surface of the active region14. Subsequently, a first doping region24and a second doping region25may be formed. The first doping region24and the second doping region25may be formed through any suitable doping process, such as, for example, an ion implantation process. The first doping region24and the second doping region25may have the same depth. According to another embodiment of the present invention, the first doping region24may be deeper than the second doping region25. FIG.16is a cross-sectional view illustrating a semiconductor device in accordance with a modified example of the third embodiment of the present invention. Referring toFIG.16, the semiconductor device300M may include a buried gate structure300G′. The buried gate structure300G′ may be formed inside a gate trench105. The buried gate structure300G′ may include a gate dielectric layer106, an interface layer321, a crystallization delay layer320, a gate electrode308, and a capping layer109. The gate dielectric layer106may be formed of any suitable dielectric material including, for example, an oxide. The gate dielectric layer106may include, for example, a silicon oxide. The interface layer321may be a nitrogen-containing layer. The interface layer321may be formed by nitriding the upper surface of the gate dielectric layer106. The interface layer321and the crystallization delay layer320may have different nitrogen concentrations. The crystallization delay layer320may be formed with a high nitrogen concentration, and the interface layer321may be formed with a lower nitrogen concentration than the nitrogen concentration of the crystallization delay layer320. The interface layer321may be formed through a plasma nitridation. The crystallization delay layer320may include a nitrogen-rich layer that contains a high concentration of nitrogen. The crystallization delay layer320may include a nitrogen-rich silicon nitride. The crystallization delay layer320may include approximately 30 to 40 at % of nitrogen. The crystallization delay layer320may be formed through an Atomic Layer Deposition (ALD) process. The gate electrode308may be the same as the gate electrode308ofFIG.13. The gate electrode308may be polycrystalline. The gate electrode308may include first crystal grains308G1and second crystal grains308G2. The first crystal grains308G1may have a smaller crystal grain size than the second crystal grains308G2. The gate electrode308may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. According to the embodiment of the present invention, the gate electrode308may be formed of a titanium nitride (TiN). The first crystal grains308G1may be TiN crystal grains having a small crystal grain size. The second crystal grains308G2may be TiN crystal grains having a large crystal grain size. The small crystal grain size of the first crystal grains308G1may be controlled by employing the crystallization delay layer320. The high nitrogen concentration of the crystallization delay layer320may increase an interface trap charge density (Qit) and a fixed charge density (Qf). As the interface trap charge density (Qit) and the fixed charge density (Qf) are increased, interface energy may be raised. The high interface energy may delay the growth of the crystal grains of the first crystal grains308G1. As described above, since the first crystal grains308G1having a small crystal grain size are formed by the crystallization delay layer320, there may be substantially no voids on the interface between the gate electrode308and the gate dielectric layer106. In this way, delamination may be suppressed. Also, since the second crystal grains308G2having a relatively large crystal grain size fill most of the gate trench105, the resistance of the gate electrode308may be decreased. FIGS.17A to17Fare cross-sectional views illustrating an example of a method for fabricating the semiconductor device300M in accordance with the modified example of the third embodiment of the present invention shown inFIG.16. First of all, as illustrated inFIG.7A, the structures from the isolation layer12to the gate dielectric layer17may be formed. The gate dielectric layer17may be formed of any suitable material including, for example, a silicon oxide. Subsequently, referring toFIG.17A, an interface layer81may be formed over the gate dielectric layer17. The interface layer81may include a silicon oxynitride (SiON). The interface layer81may be formed through a plasma nitridation81P. The upper surface of the gate dielectric layer17may be nitrided through the plasma nitridation81P. The plasma nitridation81P may be performed under the conditions that are different from the conditions of the plasma nitridation61P ofFIG.15A. The plasma nitridation81P may be performed under a condition where the nitrogen concentration is not high. For example, the plasma nitridation81P may be performed at a lower nitrogen concentration than the plasma nitridation61P ofFIG.15A. Therefore, the interface layer81may have a lower nitrogen concentration than the crystallization delay layer61A ofFIG.15A. Since the interface layer81is formed, the electrical characteristics of the gate dielectric layer17may be improved. Referring toFIG.17B, a crystallization delay layer82A may be formed over an interface layer81. The crystallization delay layer82A may include a nitrogen-rich layer containing a high concentration of is nitrogen. The crystallization delay layer82A may include a nitrogen-rich silicon nitride (N-rich SiN), The nitrogen-rich silicon nitride may include approximately 30 to 40 at % of nitrogen. The crystallization delay layer82A may be formed through an ALD process82D. The ALD process82D may be performed using a silicon source gas and a nitrogen source gas (e.g., NH3). The ALD process71D may be performed by increasing the flow rate of the nitrogen source gas. In this way, the nitrogen concentration of the crystallization delay layer82A may be raised. The crystallization delay layer82A may be formed in a thickness thinner than approximately 10 Å. When the crystallization delay layer82A is thick, the gap-filling performance of a conductive layer, which is to be performed subsequently, becomes poor. Therefore, it is appropriate to form the crystallization delay layer71A as thin as possible. Referring toFIG.17C, a conductive layer83A may be formed over the crystallization delay layer82A. The conductive layer83A over the crystallization delay layer82A may completely fill the gate trench16. The conductive layer83A may be formed of any suitable material including a metal, a metal nitride, or a combination thereof. The conductive layer83A may be formed of a titanium nitride (TiN). The conductive layer83A may be polycrystalline. The conductive layer83A may be formed of a titanium nitride (TiN) of columnar crystal grains. The conductive layer83A may be formed at a temperature which is a low-temperature process, a high-temperature process, or a middle-temperature process. The conductive layer83A may be a titanium nitride (ALD-TiN) that is formed by reacting TiCl4and NH3, The conductive layer83A may include an LT-ALD TiN, an MT-ALD TiN, or an HT-ALD TiN. As described above, as the conductive layer83A is formed over the crystallization delay layer82A, agglomeration on the interface between the conductive layer83A and the crystallization delay layer82A may be delayed during a subsequent annealing process. In short, the growth of crystal grains of the conductive layer83A may be delayed on the interface between the conductive layer83A and the crystallization delay layer82A. Referring toFIG.17D, a conductive layer pattern83′ may be formed. The conductive layer pattern83′ may be formed by recessing the conductive layer83A through an etch-back process. The conductive layer pattern83′ may be positioned at a lower level than the upper surface of the active region14. As a result, the conductive layer pattern83′ may be positioned inside the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. Before the etch-back process is performed, a planarization process using a Chemical Mechanical Polishing (CMP) may be performed in advance. Referring toFIG.17E, an annealing process84may be performed. The conductive layer pattern83′ may be exposed to the annealing process84. Through the annealing process84, crystal grains may grow up. In other words, the conductive layer pattern83′ may be crystalized through the annealing process84. The annealing process84may be performed at a temperature ranging from approximately 300° C. to approximately 1100° C. Through the annealing process84, the conductive layer pattern83′ may be converted into a polycrystalline gate electrode83. The gate electrode83may include first crystal grains83G1and second crystal grains83G2. The first crystal grains83G1and the second crystal grains83G2may be formed through the growth of the crystal grains of the conductive layer pattern83′. The first crystal grains83G1may contact the crystallization delay layer82A. The first crystal grains83G1may be able to cover the upper surface and side walk of the fin region14F, The second crystal grains83G2over the first crystal grains83G1may fill the gate trench16. The first crystal grains83G1may be positioned between the second crystal grains83G2and the gate dielectric layer17. The first crystal grains83G1may correspond to the first crystal grains308G1shown inFIG.16. The second crystal grains83G2may correspond to the second crystal grains308G2shown inFIG.16. The first crystal grains83G1and the second crystal grains83G2may be TiN crystal grains. While the annealing process84is performed, the growth of the crystal grains may be delayed by the crystallization delay layer82A. Therefore, the first crystal grains83G1may grow up to have a small crystal grain size due to the crystallization delay layer82A. The second crystal grains83G2that do not contact the crystallization delay layer82A may have a larger crystal grain size than the first crystal grains83G1. A plurality of voids83V may be formed among the second crystal grains83G2. The voids83V may be generated during the deposition process for forming the conductive layer83A. While the crystal grains grow, the voids83V may grow as well or may be maintained. There may be substantially no voids formed among the first crystal grains83G1. Even through there are voids, the size and the number of the voids may be small. Referring toFIG.17F, a capping layer23may be formed over the gate electrode83. The capping layer23may include a dielectric material. The gate trench16may be filled with the capping layer23over the gate electrode83. The capping layer23may be formed of any suitable dielectric material including, for example, a silicon nitride. Subsequently, the capping layer23may be planarized in such a manner that the upper surface of the hard mask layer15may be exposed. According to another embodiment of the present invention, the capping layer23may be formed of a silicon oxide. According to yet another embodiment of the present invention, the capping layer23may have an NON (Nitride-Oxide-Nitride) structure. After the capping layer23is planarized, the crystallization delay layer82A and the interface layer81A may be planarized. As a result, the interface layer81and the crystallization delay layer82may be positioned inside the gate trench16with the top surface of the gate electrode positioned at a lower level than the top of the gate trench. The upper surfaces of the interface layer81, the crystallization delay layer82, the capping layer23, and the hard mask layer15may be positioned at the same level. A buried gate structure may be completed by forming the capping layer23. The buried gate structure may include the gate dielectric layer17, the interface layer81, the crystallization delay layer82, the gate electrode83, and the capping layer23. The buried gate structure may have a recessed shape that fills a portion of the gate trench16. The buried gate structure may be positioned at a lower level than the uppermost surface of the active region14. Subsequently, a first doping region24and a second doping region25may be formed. The first doping region24and the second doping region25may be formed through any suitable doping process, such as an ion implantation process. The first doping region24and the second doping region25may have the same depth. According to another embodiment of the present invention, the first doping region24may be deeper than the second doping region25. FIG.18is a cross-sectional view of a semiconductor device in accordance with an application example of an embodiment of the present invention.FIG.18illustrates a memory cell400to which the semiconductor device100ofFIG.2Ais applied. Referring toFIG.18, the memory cell400is illustrated. The memory cell400may include a cell transistor410, a bit line420, and a memory element430. The cell transistor410may be configured according to the semiconductor device100ofFIG.2A. The cell transistor410may include a buried word line structure BWL, a channel region110, a first doping region111, and a second doping region112. The first doping region111may be electrically connected to the bit line420through a first contact plug421. The second doping region112may be electrically connected to the memory element430through a second contact plug431. The buried word line structure BWL may be the same as the buried gate structure100G ofFIG.2A. The buried word line structure BWL may be formed inside of a gate trench105. The buried word line structure BWL may include a gate dielectric layer106, a word line WL, and a capping layer109. The word line WL may include a first crystal grain layer107and a second crystal grain layer108. The first crystal grain layer107may include first crystal grains (see the reference numeral ‘107G’ ofFIG.3A) of a small crystal grain size. The second crystal grain layer108may include second crystal grains (see the reference numeral ‘108G’ ofFIG.3A) of a large crystal grain size. The buried word line structure BWL of the cell transistor410may be replaced by the buried gate structure100G,200G,300G or300G′ in accordance with an embodiments and their modification examples. The memory element430may include a capacitor. The memory element430may include a storage node (not shown) that contacts the second contact plug431. The storage node may be a cylindrical shape or a pillar shape. A capacitor dielectric layer may be formed on the surface of the storage node. The capacitor dielectric layer may include at least one selected from a group including a zirconium oxide, an aluminum oxide, and a hafnium oxide. For example, the capacitor dielectric layer may have a ZAZ (ZrO2/Al2O3/ZrO2) structure where a first zirconium oxide, an aluminum oxide, and a second zirconium oxide are stacked. A plate node may be formed over the capacitor dielectric layer. The storage node and the plate node may include a metal-containing material. According to another embodiment of the present invention, the memory element430may include a variable resistance material. The variable resistance material may include a phase-change material. The phase-change material may include at least one selected from a group including tellurium (Te) and selenium (Se), which are chalcogenide elements. According to another embodiment of the present invention, the variable resistance material may include a transition metal oxide. According to yet another embodiment of the present invention, the variable resistance material may include a Magnetic Tunnel Junction (MTJ). As described above, the memory cell400may include the buried word line structure BWL that includes the first crystal grain layer107and the second crystal grain layer108. When the memory cell400is applied to a Dynamic Random Access Memory (DRAM) device, the refresh characteristics of the DRAM device may be improved. Also, it is possible to prevent off-leakage, which leads to improved retention time. The semiconductor devices in accordance with the embodiments of the present invention may be applied to an electronic device. The electronic device may include a plurality of semiconductor devices. For example, the electronic device may include at least one selected from the semiconductor devices100,200,300and300′ and the memory cell400in accordance with the embodiments of the present invention. The least one semiconductor device among the semiconductor devices included in the electronic device may include a buried gate structure that is formed inside of a gate trench. The buried gate structure may include first crystal grains and second crystal grains. The first crystal grains may contact a gate dielectric layer, and the second crystal grains may not contact the gate dielectric layer. The crystal grain size of the first crystal grains may be smaller than the crystal grain size of the second crystal grains. Since the first crystal grains are formed in a small crystal grain size, the interface characteristics between the gate dielectric layer and a gate electrode may be improved. Therefore, it is possible to realize rapid operation rates in electronic devices that are being miniaturized. According to embodiments of the present invention, void formation and delamination may be prevented by forming crystal grains of a small crystal grain size that cover and contact the gate dielectric layer. As a result, the characteristics of the interface between the gate dielectric layer and the gate electrode may be improved. Also, according to embodiments of the present invention, the resistance of the gate electrode may be improved by forming the crystal grains of a large crystal grain size filling most of the gate trench. Also, according to embodiments of the present invention, the resistance of the gate electrode may be improved by removing impurities through a subsequent process. While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. | 105,427 |
11943913 | DETAILED DESCRIPTION The present disclosure is described in detail with reference to the figures of the embodiments of the present disclosure. It should be appreciated, however, that the present disclosure can be embodied in a wide variety of implements and is not limited to embodiments described in the disclosure. Various features may be arbitrarily drawn at different scales for the sake of simplicity and clarity. Throughout the various views and illustrative embodiments, similar reference numbers are used to designate similar features/components. FIG.1A-FIG.1Mare cross-sectional views of various stages of manufacturing a semiconductor structure in accordance with an embodiment of the present invention. Referring toFIG.1A, a substrate100is provided, and the substrate100includes several trenches103extending downward from the top surface of the substrate100. The substrate100may include a semiconductor material. In some embodiments, the substrate100includes silicon, gallium arsenide, gallium nitride, germanium silicide, another suitable substrate material, or a combination thereof. In some other embodiments, the substrate100is a silicon-on-insulator (SOI) substrate. Next, a gate dielectric layer112is conformably formed on the surface of the substrate100, and a barrier material layer1150is sequentially and conformably formed on the gate dielectric layer112. As shown inFIG.1A, the gate dielectric layer112covers the sidewalls103sand the bottom surfaces103bof the trenches103and extends to the top surface100aof the substrate100. The barrier material layer1150is formed on the gate dielectric layer112. In some embodiments, the gate dielectric layer112is a single layer structure or a multilayer structure. The gate dielectric layer112may include silicon oxide, silicon nitride, silicon dioxide, another suitable material, or a combination thereof. For example, the gate dielectric layer112may be an oxide-nitride-oxide (ONO) structure, or an oxide-nitride-oxide-nitride-oxide (ONONO) structure. To simplify the diagram, a single-layer gate dielectric layer112is depicted for clear illustrations. Also, the gate dielectric layer112can be formed by a thermal oxidation process, a deposition process, another suitable process, or a combination thereof. In some embodiments, the barrier material layer1150includes one or more conductive metals. For example, the barrier material layer1150includes metal, metal alloy, metal nitride, or metal silicide. In some embodiments, the barrier material layer1150includes titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten nitride (WN), tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), aluminum (Al), another suitable conductive material, or a combination thereof. In some embodiments, the barrier material layer1150is formed on the gate dielectric layer112by a deposition process, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Next, referring toFIG.1B, a first work function material layer1160is formed on the barrier material layer1150, and the trenches103are fully filled with the first work function material layer1160. In one embodiment, the first work function material layer1160may include copper (Cu), tungsten (W), or other suitable conductive materials. Furthermore, the first work function material layer1160may be a single-layer conductive metal structure or a multi-layer conductive metal structure. In this example, the first work function material layer1160includes tungsten. Referring toFIG.1C, the first work function material layer1160is recessed subsequently. In one embodiment, the excess portions of the first work function material layer1160outside the trenches103may be removed by a chemical mechanical polishing (CMP) process, an etching back process or another suitable process. Next, the first work function material layer1160in the trenches103is recessed, such as by a selective etching process. The remaining portions1160R of the first work function material layer1160are disposed in the lower portions of the corresponding trenches103. After the first work function material layer1160is recessed, the upper portions of the sidewalls1150sof the barrier material layer1150are exposed. Next, according to an embodiment of the present disclosure, a mask can be formed on the remaining portions1160R of the first work function material layer1160after the first work function material layer1160is recessed. Then, the remaining portions1160R of the first work function material layer1160is etched according to the mask to remove the portion of the remaining portions1160R of the first work function material layer1160that is uncovered by the mask, thereby forming the corresponding holes. Then, the aforementioned holes are filled with a second work function material.FIG.1DtoFIG.1Gillustrate one of the manufacturing methods for forming a mask on the recessed remaining portions1160R of the first work function material layer1160. However, it should be known in the art that the details of the steps described below are merely for illustrative purposes, and are not intended to limit the manufacturing process of the present disclosure. Next, referring toFIG.1D, a first dielectric material layer1170is conformably deposited on the barrier material layer1150. As shown in theFIG.1D, the first dielectric material layer1170covers the top surface1150aof the barrier material layer1150and the upper portions of the sidewalls1150sof the barrier material layer1150. Also, an opening1171is formed in each of the trenches103. Furthermore, the first dielectric material layer1170may include silicon oxide, silicon nitride, silicon oxynitride, another suitable material, or a combination thereof. In some embodiments, the first dielectric material layer1170is formed by chemical vapor deposition or another suitable method. The thickness t1of the first dielectric material layer1170can be determined according to the size of a gap that is between the sidewalls of the barrier material layer1150in each of the trenches103. Also, the thickness t1of the first dielectric material layer1170can be used to control the width of the first portion121and the width of the second portion122of the second work function layer120that are formed subsequently (FIG.1M). Specifically, the width of the opening1171can be controlled by adjusting the thickness t1of the first dielectric material layer1170, thereby controlling the width of the mask HM to be formed subsequently, in accordance with some embodiments of the present disclosure. Accordingly, the width of the first portion121and the width of the second portion122of the second work function layer120can be determined and controlled by controlling the width of the mask HM to meet the requirements in the applications. As shown inFIG.1D, in some embodiments, the width WH of the opening1171is in a range of about ⅙ to about ½ of the width Wt of the trench103. For example, in one embodiment, the width WH of the opening1171is about ¼ of the width Wt of the trench103. However, the present disclosure is not limited to the numerical values provided herein. The width WH of the opening1171can be adjusted, depending on the design requirements of the application. Next, referring toFIG.1E, a second dielectric material layer1180is formed on the first dielectric material layer1170, and the openings1171are fully filled with the second dielectric material layer1180, in accordance with some embodiments of the present disclosure. In some embodiments, the second dielectric material layer1180may include silicon oxide, silicon nitride, silicon oxynitride, another suitable dielectric material, or a combination thereof. Also, the second dielectric material layer1180may be formed by a chemical vapor deposition (CVD) process or another suitable process. In some embodiments, the material of the first dielectric material layer1170is different from the material of the second dielectric material layer1180. For example, in one embodiment, the first dielectric material layer1170includes silicon oxide, and the second dielectric material layer1180includes silicon nitride. In another embodiment, the first dielectric material layer1170includes silicon nitride, and the second dielectric material layer1180includes silicon oxide. However, this disclosure is not limited to the aforementioned materials. Next, referring toFIG.1F, a portion of the second dielectric material layer1180is removed to expose the top surface1170aof the first dielectric material layer1170. In some embodiments, the second dielectric material layer1180outside the openings1171can be removed by a chemical mechanical polishing (CMP) process, an etching back process, another suitable process or a combination thereof. The remaining portions of the second dielectric material layer1180form the second dielectric layers118in the openings1171. Accordingly, the top surface1170aof the first dielectric material layer1170is level with the top surface118aof the second dielectric layer118after the portion of the second dielectric material layer1180is removed. Next, referring toFIG.1G, the portion of the first dielectric material layer1170that is not covered by the second dielectric layer118is removed. In some embodiments, the portion of the first dielectric material layer1170that is not covered by the second dielectric layer118can be removed by an etching back process. The remaining portion of the first dielectric material layer1170in each of the trenches103forms the first dielectric layer117. As shown inFIG.1G, the sidewalls117sof the first dielectric layer117are coplanar with the sidewalls118sof the second dielectric layer118in each of the trenches103. In this embodiment, the first dielectric layer117and the second dielectric layer118collectively define a mask HM that is used in the subsequent processes. Next, referring toFIG.1H, an etching step is performed to remove a part of the remaining portion1160R of the first work function material layer1160that is not covered by the mask HM in the trench103, thereby forming the first work function layer116in the trench103. In some embodiments, the part of the remaining portion1160R of the first work function material layer1160that is not covered by the mask HM in the trench103can be removed by, for example, reactive ion etching (RIE) or another suitable dry etching method. In this embodiment, after the etching step, the holes119-1and119-2are formed on opposite sides of the first work function layer116in the trench103, respectively. It should be noted that only the mask HM is used in the etching step and no extra photomask is required for etching the remaining portion1160R of the first work function material layer1160. Accordingly, this etching step can be regarded as a self-aligned etching process. Referring toFIG.1Hagain, after the etching step, the size of each of the holes119-1and119-2is gradually reduced from the top surface of the remaining portion1160R of the first work function material layer1160toward the direction of entering the remaining portion1160R of the first work function material layer1160, in accordance with some embodiments of the present disclosure. As shown inFIG.1H, the sidewall119-s1of the hole119-1and the sidewall119-s2of the hole119-2are respectively slanted to the sidewall1150sof the barrier material layer1150. In one embodiment, the sidewall119-s1of the hole119-1and the sidewall119-s2of the hole119-2are arc-shaped sidewalls. Next, referring toFIG.1I, the mask HM is removed. In some embodiments, the first dielectric layer117and the second dielectric layer118in each of the trenches103are removed to expose the first work function layer116. As shown inFIG.11, the first work function layer116includes a main portion116M and a protruding portion116P. In this embodiment, the main body116M is positioned in the lower portion of the corresponding trench103, and the protruding portion116P is disposed on the main body116M. Next, referring toFIG.1J, a portion of the barrier material layer1150is removed, and the remaining portion of the barrier material layer1150forms a barrier layer115. In one embodiment, the upper portion of the barrier material layer1150can be removed. For example, as shown inFIG.1J, in each of the trenches103, the portions of the barrier material layer1150that are higher than the bottom surfaces of the hole119-1and the hole119-2are removed. The remaining barrier layer115surrounds the side surface116M-s and the bottom surface116M-b of the main portion116M, in accordance with some embodiments of the present disclosure. In addition, the top surface115aof the barrier layer115may be substantially level with the bottom surface116P-b of the protruding portion116P. In one embodiment, the removal of the portion of the barrier material layer1150can be performed by, for example, a dry etching process, a wet etching process, another suitable process, or a combination thereof. Referring toFIG.1Jagain, the width of the protruding portion116P of the first work function layer116gradually increases from the top surface116P-a of the protruding portion116P toward the bottom surface116P-b of the protruding portion116P. In one embodiment, the width Wp of the top surface116P-a of the protruding portion116P of the first work function layer116is in a range of about ⅙ to about ½ of the width Wt of the trench103, in accordance with some embodiments of the present disclosure. In some embodiments, the width Wp of the top surface116P-a of the protruding portion116P of the first work function layer116is in a range of about ⅓ to about ½ of the width Wt of the trench103. In one example, the width Wp of the top surface116P-a of the protruding portion116P is about ½ of the width Wt of the trench103. Next, referring toFIG.1K, a second work function material layer1200is formed on the barrier layer115and the first work function layer116, in accordance with some embodiments of the present disclosure. The second work function material layer1200covers the barrier layer115and fills the trenches103. The second work function material layer1200further fills the holes119-1and119-2at opposite sides of the protruding portion116P of the first work function layer116. In some embodiments, the second work function material layer1200includes doped or undoped polysilicon, metal, metal alloy, metal nitride, or metal silicide. In some embodiments, the second work function material layer1200includes polysilicon, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten nitride (WN), tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), aluminum (Al), another suitable conductive material, or a combination thereof. In some embodiments, the second work function material layer1200can be formed by a deposition process, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, another suitable process, or a combination thereof. In some embodiments, the material of the second work function material layer1200is different from the material of the barrier layer115. Also, the material of the second work function material layer1200is different from the material of the first work function layer116. In addition, the work function of the second work function material layer1200is less than the work function of the barrier layer115, and the work function of the barrier layer115is less than the work function of the first work function layer117, in accordance with some embodiments of the present disclosure. Next, referring toFIG.1L, a part of the second work function material layer1200is removed until the first work function layer116is exposed, and a second work function layer120is formed. In one embodiment, for example, a part of the second work function material layer1200can be removed by an etching back process. As shown inFIG.1L, the second work function layer120includes a first portion121and a second portion122positioned at opposite sides of the protruding portion116P of the first work function layer116. The top surface116P-a of the protruding portion116P is level with the top surfaces121aand122aof the second work function layer120, in accordance with some embodiments of the present disclosure. In addition, in one embodiment, the second work function layer120covers the top surface115aof the barrier layer115. For example, as shown inFIG.1L, the bottom surface121bof the first portion121and the bottom surface122bof the second portion122of the second work function layer120contact and cover the barrier layer115. In addition, as shownFIG.1L, the two opposite sides of the second work function layer120, that is, the first side surface116P-s1and the second side surface116P-s2of the protruding portion116P inFIG.1L, are slanted to the top surfaces121aand122aof the second work function layer120, in accordance with some embodiments of the present disclosure. In one example, the two opposite side surfaces of the second work function layer120have arc-shaped side surfaces, as shown inFIG.1L. Next, referring toFIG.1M, an insulating layer124is formed in the trenches103. The insulating layer124covers the top surface116P-a of the protruding portion116P and the top surfaces121aand122aof the second work function layer120. In one embodiment, for example, an insulating material is deposited on the substrate100as a blanket layer. The insulating material covers the top surface of the gate dielectric layer112and fills the trenches103. Then, the excess portions of the insulating material and the gate dielectric layer112outside the trenches103are removed until the top surface100aof the substrate100is exposed. After the excess portions of the insulating material and the gate dielectric layer112are removed, an insulating layer124is formed in each of the trenches103. The material of the insulating layer124includes, for example, silicon nitride or another suitable insulating material. The insulating layer124may be formed by a chemical vapor deposition process or another suitable process. In addition, the top surface124aof the insulating layer124is substantially level with the top surface112aof the gate dielectric layer112and the top surface100aof the substrate100, in accordance with some embodiments of the present disclosure. As shown inFIG.1M, the insulating layer124is formed on the protruding portion116P of the first work function layer116and on the second work function layer120, in accordance with some embodiments of the present disclosure. The insulating layer124covers and contacts the top surface121aof the first portion121and the top surface122aof the second portion122of the second work function layer120. Also, the insulating layer124covers and contacts the top surface116P-a of the protruding portion116P of the first work function layer116. According to the aforementioned descriptions, in the semiconductor structure and its manufacturing method as provided in some embodiments of the present disclosure, the second work function layer120is provided at opposite sides of the protruding portion116P of the first work function layer116. Therefore, when a channel region of a memory device is switched on, the intensity of the electric field (for example, the electric field E2inFIG.1M) generated by the second work function layer120that is adjacent to the doped regions on can be reduced. In addition, referring toFIG.1Magain, when a channel region of a memory device is switched on, an electric field E1is generated near the side of the main portion116M of the first work function layer116(which is adjacent to the doped region of the substrate100as a drain region of the memory device), and an electric field E2is generated near the side of the protruding portion116P (which is also adjacent to the doped region of the substrate100as a drain region of the memory device), in accordance with some embodiments of the present disclosure. The intensity of the electric field E2is less than the intensity of the generated electric field E1, thereby solving the conventional problem of the gate induced drain leakage current (GIDL). In addition, in some embodiments, the area of the top surface of the protruding portion116P of the first work function layer116is less than the area of the bottom surface of the protruding portion116P of the first work function layer116. For example, the width of the protruding portion116P of the first work function layer116gradually increases from the top surface116P-a of the protruding portion116P toward the bottom surface116P-b of the protruding portion116P. When a channel region of a memory device is switched on, the intensity of the electric field E2shown inFIG.1Mcan be less than the intensity of the electric field E1, and the electric field E2also forms gradually increasing electric field intensity from top to bottom. Thus, the difference in the electric field intensity at the junction of the electric field E2and the electric field E1can be reduced, thereby greatly suppressing the gate induced drain leakage current (GIDL), in accordance with some embodiments of the present disclosure. If the intensity difference between the electric field E2and the electric field E1is too large, the tunneling effect on the electrons (e−) leads to the gate induced drain leakage current (GIDL). Specifically, the sudden increase of the electric field intensity in the electric field E1may pull the electrons that originally stayed in the electric field E2into the electric field E1, and a large leakage current would be generated, so that the gate induced drain leakage current (GIDL) problem cannot be effectively improved. Furthermore, when the memory device is operated, if the intensity difference between the electric field E2and the electric field E1is too large, it affects not only the stability of the operation performance of each word line, but also the overall electrical performance of the memory device. For example, a memory device typically contains 600 to 900 (or even more) word lines. When the word line is turned on, if there is a sudden change in the electric field intensity between the aforementioned electric field E2and the electric field E1, it would cause the problem of current leakage, and the amounts of the leakage current of each of the word lines cannot be controlled stably. This would further affect the overall operation speed of the device (for example, the response time of the word line having the lowest operation speed determines the overall response time of the memory device). Therefore, the semiconductor structure and its manufacturing method according to some embodiments of the present disclosure can not only effectively reduce the gate induced drain leakage current (GIDL), but also achieve the electrical uniformity of each of the word lines, thereby improving the electronic characteristics of the devices in the applications and increasing the stability of the operation performance of the devices in the applications. In addition, according to the manufacturing method proposed in some embodiments, the thickness of the first dielectric material layer can be adjusted according to the actual requirements of the application to determine the width of the mask that is subsequently formed. The mask can be used for etching the first work function material layer underneath, so that the positions and sizes of the holes formed for disposing another work function material (such as polysilicon) can be controlled. This etching step can be regarded as a self-aligned etching process since no extra mask is required for etching the first work function material layer. Therefore, according to the manufacturing method proposed in some embodiments, the manufacturing steps can be simplified, the number of the masks used in the manufacturing method can be reduced, and the manufacturing cost can be decreased. Also, the manufacturing method proposed in some embodiments of the present disclosure is compatible with the current manufacturing process, and has economic values in the applications. It should be understood that the disclosure has been described by way of example and in terms of the preferred embodiments is not limited to the disclosed embodiments and preferred embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. | 24,701 |
11943914 | DETAILED DESCRIPTION In order to make the description of the present disclosure more detailed and complete, the following illustratively describes implementation aspects and specific embodiments of the present disclosure; however, this is not the only form in which the specific embodiments of the present disclosure are implemented or utilized. The embodiments disclosed below may be combined with or substituted by each other in an advantageous manner, and other embodiments may be added to an embodiment without further recording or description. In the following description, numerous specific details will be described in detail to enable readers to fully understand the following embodiments. However, the embodiments of the present disclosure may be practiced without these specific details. Specific embodiments of the components and arrangements described below are intended to simplify the present disclosure. Of course, these are merely embodiments and are not intended to limit the present disclosure. For example, forming a first feature above or on a second feature in the subsequent description may include an embodiment in which the first feature and the second feature are formed as in direct contact, or include an embodiment in which an additional feature is formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, component symbols and/or letters may be repeated in various embodiments of the present disclosure. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed. Furthermore, spatial relative terms, such as “below”, “under”, “above”, “over”, etc., are intended to facilitate description of the relative relationship between a component or feature and another component or feature, as shown in the drawings. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is flipped up and down by 180 degrees, the relationship between a component and another component may change from “below” or “under” to “above” or “over”. Furthermore, the spatial relative narratives used herein should be interpreted the same. FIG.1is a flow chart illustrating a method of manufacturing a memory structure in accordance with some embodiments of this disclosure. As shown inFIG.1, the method100includes operation102, operation104, operation106, and operation108. The method for manufacturing the memory structure10will be further described according to one or more embodiments below.FIGS.2-8are cross-sectional views at various stages of method100according to some embodiments of the present disclosure. Reference is made toFIG.1andFIG.2. In the operation102of the method100, gate structures210and source/drain (S/D) regions220a,220bare formed in a substrate200. In some embodiments, the substrate200includes silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), gallium (Ga), gallium nitride (GaN), gallium arsenide (GaAs), epitaxy layer, combinations thereof, or the like. Each of the gate structures210may include a gate electrode214and a gate dielectric layer212disposed between the gate electrode214and the substrate200. An isolation structure216may be formed on each of the gate electrodes214. In some embodiments, the gate structure210may be a buried gate structure. In some embodiments, the buried gate structure can serve as a buried word line (BWL) for a DRAM device. The source/drain regions220a,220bare disposed on opposite sides of the gate structures210. In some embodiments, the source/drain regions220a,220binclude an n-type doped region. As shown inFIG.2, two gate structures210may share one S/D region220adisposed between thereof. One gate structure210and source/drain region220aand220bconstitute a transistor. A shallow trench isolation (STI) structure202is formed in the substrate200for defining at least one active region. Referring toFIG.1, in the operation104of the method100, a dry etching process is performed to form a trench between the gate structures.FIG.3andFIG.4illustrate the detail steps of implementing operation104in accordance with some embodiments of the present disclosure. Reference is made toFIG.3. A patterned mask layer218is formed on the gate structures210and the S/D regions220a,220b. In some embodiments, the patterned mask layer218may be a single-layered structure or a multi layered structure. The patterned mask layer218exposes a portion of the substrate200(e.g. the S/D region220a) between the gate structures210. Reference is made toFIG.4. The exposed substrate200between the gate structures210is then removed by the dry etching process. In some embodiments, the dry etching process is performed with a halogen-based gas. For example, HBr, Cl-containing, F-containing gas, or the like may be used to etch the substrate200. As such, the trench T1is formed in the substrate200and between the gate structures210. In some embodiments, the trench T1has a width W1of about 54-66 nm. In some embodiments, the trench T1has a depth D1of about 36-44 nm. For example, the width W1and the depth D1of the trench T1may be about 60 nm and about 40 nm, respectively. As shown inFIG.4, the trench T1has a vertical sidewall. That is, the trench T1may have substantially equal width W1from its bottom to top. In some embodiments, a cleaning process can follow the dry etching process to remove residues of the etching substances and/or undesired substances formed during the dry etching process. For example, dilute HF may be used in the cleaning process. Reference is made toFIG.1andFIGS.5A-5B. In the operation106of the method100, a wet etching process is performed to expand the trench T1(shown inFIG.4). After the dry etching process, the wet etching process laterally and vertically etches the substrate200to expand the trench T1. In some embodiments, the wet etching process is performed with a tetramethyl ammonium hydroxide (TMAH) based solution. In some examples, TMAH solution is used to etch the trench T1. A concentration of TMAH in the TMAH solution may be of about 2.35%, and a concentration of water may be 97.65%. The wet etching process may be performed at a temperature of about 25° C. for 170 seconds. The structural detail of the expanded trench T1′ is shown inFIG.5Band described as follow.FIG.5Bis an enlarged diagram illustrating the expanded trench T1′ inFIG.5A. It is noted that some elements adjacent to the expanded trench T1′ are not shown inFIG.5Bfor clarity. In some embodiments, the expanded trench T1′ has a polygonal shaped cross section profile. For example, the expanded trench T1′ may have a hexagonal cross section profile. The expanded trench T1′ has two tips laterally protruded toward the adjacent gate structures210respectively. The tips are constituted by a first tilt sidewall S1and a second tilt sidewall S2. In some embodiments, an angle θ1between the first tilt sidewall S1and a reference line A-A′ (the dashed line connecting the tips) is from about 52.7 to about 56.7 degrees, and an angle θ2between the second tilt sidewall S2and the reference line A-A′ is from about 52.7 to about 56.7 degrees. In some embodiments, the angle θ1is substantially equal to the angle θ2. For example, the angle θ1and the angle θ2may be 54.7 degrees, respectively. The angle θ1and the angle θ2may be related to the etching rate of the different crystal orientations. In some embodiments, the expanded trench T1′ has a top width W1′ greater than a bottom width W2. In some embodiments, a middle width W3is greater than the top width W1′ and the bottom width W2. In some embodiments, the top width W1′ is substantially equal to the width W1of the trench T1shown inFIG.4, and the middle width W3is greater than the width W1. In some embodiments, the top width W1′ is of about 54-66 nm, the bottom width W2is of about 28-36 nm, and the middle width W3is of about 79-100 nm. In some embodiments, the expanded trench T1′ has a depth D2of about 54-66 nm. The expanded trench T1′ has a lower portion (i.e., from a bottom surface of the expanded trench T1′ to the reference line A-A′) and an upper portion (i.e., from a top surface of the substrate200to the reference line A-A′). A depth of the lower portion is greater than that of the upper portion. In some examples, the top width W1′ may be 60 nm, the bottom width W2may be 32 nm, and the middle width W3may be 88 nm. The upper portion of the expanded trench T1′ may have a depth of about 20 nm, and the lower portion of the expanded trench T1′ may have a depth of about 40 nm. The dimension of the expanded trench T1′ is formed according to the demand of the subsequent formed bit line contact. In some embodiments, a cleaning process can follow the wet etching process to remove residues of the etching substances and/or undesired substances formed during the dry etching process. For example, DI water may be used in the wet cleaning process. In some embodiments, an implantation process may be further performed to the substrate200. For example, phosphorous (P) ions, or the like are implanted into the substrate200exposed by the expanded trench T1′ for decreasing the electrical resistance. Reference is made toFIG.1andFIGS.6A-6B. In the operation108of the method100, a bit line contact230is formed in the expanded trench T1′. In some embodiments, forming the bit line contact230in the trench T1includes forming a conductive material (not shown) in the expanded trench T1′ and then etching back the conductive material. In some embodiments, the bit line contact230includes phosphorous (P), arsenic (As), or carbon doped polysilicon. Specifically, the doped polysilicon can decrease the resistance of the bit line contact. Further, phosphorous has a smaller lattice constant than silicon, resulting in a tensile stress to increase the electron mobility of the NMOS. The structural detail of the bit line contact230is shown inFIG.6Band described as follow.FIG.6Bis an enlarged diagram illustrating the bit line contact230shown inFIG.6A. It is noted that some elements adjacent to the bit line contact230is omitted for clarity. As shown inFIG.6B, the bit line contact230may inherit the structure of the expanded trench T1′ shown inFIG.5B. That is, the bit line contact230has a polygonal shaped cross section profile. For example, the bit line contact230also has two tips laterally protruded toward the adjacent isolation structures216. In some embodiments, the bit line contact230has a first tilt sidewall S1′ and a second tilt sidewall S2′, and an angle between the first tilt sidewall S1′ and the second tilt sidewall S2′ is about 104-114 degrees. Specifically, an angle θ1′ between the first tilt sidewall S1′ and a reference line A-A′ (the dashed line connecting the tips) is from about 52.7 to about 56.7 degrees, and an angle θ2′ between the second tilt sidewall S2′ and the reference line A-A′ is from about 52.7 to about 56.7 degrees. In some embodiments, the angle θ1′ is substantially equal to the angle θ2′. In some examples, the angle θ1′ and the angle θ2′ may be 54.7 degrees, respectively. In some embodiments, the bit line contact230has a top width W1″ and a bottom width W2′ greater than the top width W1″, and a middle width W3′ is greater than the top width W1″ and the bottom width W2′. In some embodiments, the dimensions of the bit line contact may substantially equal to that of the expanded trench T1′ shown inFIG.5B. In some embodiments, the bit line contact230may have a substantially convex top surface. In other embodiments, the top surface of the bit line contact230may substantially level with the substrate200and the isolation structures216. Reference is made toFIG.7. The method further includes forming a bit line232on the bit line contact230. In some embodiments, the bit line232includes conductive material. In some embodiments, in the formation of the bit line232, a portion of the bit line contact230(e.g., the convex top surface) may be removed. The bit line232is electrically connected to the source/drain region220athrough the bit line contact230. Reference is made toFIG.8. The method further includes forming a plurality of capacitors270electrically connecting to the source/drain region220b. Specifically, an interlayer dielectric (ILD) layer240is formed over the bit line232. A plurality of contact plugs242are embedded in the ILD layer240and electrically connected to the source/drain regions220b. A plurality of conductive pads250are further formed on the contact plugs242. A dielectric layer260and the capacitors270are further formed on the conductive pads250. In some embodiments, the capacitor270includes a bottom electrode272, a top electrode276, and an isolation layer274disposed between thereof. As such, the capacitor270is electrically connected to the source/drain regions220bthrough the conductive pads250and the contact plugs242. Another aspect of the present disclosure is to provide a memory structure10. As shown inFIG.8, the memory structure10includes gate structures210, source/drain regions220a,220b, and a bit line contact230embedded in the substrate200. The source/drain regions220a,220bare disposed between the gate structures210. The bit line contact230is disposed on the source/drain region220aand has a polygonal shaped cross section profile. In some embodiments, the bit line contact230has two tips laterally protruded toward the adjacent gate structures210respectively. In some embodiments, the bit line contact230includes phosphorous, arsenic, or carbon doped polysilicon. A bit line232is further disposed on the bit line contact230. Each of the capacitor270sis electrically connected to one source/drain region220bthrough corresponding contact plug242and conductive pad250. In some embodiment, the memory structure10may be DRAM, but the present disclosure is not limited thereto. As described above, according to the embodiments of the present disclosure, a memory structure and a method of manufacturing thereof are provided. In the memory structure of the present disclosure, the bit line contact has a polygonal cross section profile. The bit line contact is formed by a dry etching process, followed by a wet etching and a deposition process. In specific, the wet etching process results in the polygonal shaped bit line contact. This profile increases the volume of the bit line contact and decrease electrical resistance. Further, the bit line contact includes doped polysilicon, such as phosphorous doped polysilicon, which can boost electron mobility of a NMOS. Therefore, the performance of the memory structure is enhanced. Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims. | 15,389 |
11943915 | DETAILED DESCRIPTION Advantages and features of the disclosure and methods to achieve them will become apparent from the descriptions of exemplary embodiments herein below and described with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein but may be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the disclosure to those skilled in the art. Because the figures, dimensions, ratios, angles, numbers of elements given in the drawings that describe embodiments of the disclosure are merely illustrative, the present disclosure is not limited to the illustrated matters. Throughout the specification, like reference numerals refer to like components. In describing the disclosure, when it is determined that a detailed description of the related art may obscure the gist or clarity of the disclosure, the detailed description thereof will be omitted. It is to be understood that the terms “comprising,” “having,” “including” and so on, used in the description and claims, should not be interpreted as being restricted to the means listed thereafter unless specifically stated otherwise. Where an indefinite or definite article (e.g., “a,” “an” or “the”) is used when referring to a singular noun, the article may include a plural of that noun unless specifically stated otherwise. In interpreting elements in embodiments of the disclosure, they should be interpreted as including error margins even in the absence of explicit statements. Also, in describing the components of the disclosure, there may be used terms such as first, second, A, B, (a), and (b). These are solely for the purpose of differentiating one component from another component and do not limit the substances, order, sequence or number of the components. Also, components in embodiments of the disclosure are not limited by these terms. These terms are used to merely distinguish one component from another component. Accordingly, as used herein, a first component may be a second component within the technical spirit of the disclosure. If a component is described as “connected,” “coupled” or “linked” to another component, it may mean that the component is not only directly “connected,” “coupled” or “linked” but also is indirectly “connected,” “coupled” or “linked” via a third component. In describing positional relationship, such as “an element A on an element B,” “an element A above an element B,” “an element A below an element B” and “an element A next to an element B,” one or more other elements may be disposed between the elements A and B unless the term “directly” or “immediately” is explicitly used. Features of various exemplary embodiments of the disclosure may be coupled, combined or separated partially or totally. Technically various interactions and operations are possible. Various exemplary embodiments can be practiced individually or in combination. Hereinafter, various examples of embodiments of the disclosure will be described in detail with reference to the accompanying drawings. FIG.1is a block diagram schematically illustrating a three-dimensional memory device in accordance with an embodiment of the disclosure. Referring toFIG.1, a three-dimensional memory device100in accordance with an embodiment of the disclosure may include a memory cell array110and a logic circuit120. The logic circuit120may include a row decoder (X-DEC)121, a page buffer circuit122and a peripheral circuit (PERI circuit)123. The memory cell array110may include a plurality of memory blocks BLK. While not illustrated, each of the memory blocks BLK may include a plurality of cell strings. Each cell string may include at least one drain select transistor, a plurality of memory cells and at least one source select transistor, which are coupled in series. While the following descriptions represent some embodiments in which the disclosure is illustrated using a vertical NAND flash memory, it is to be noted that the disclosure is not limited thereto and other embodiments may include different types of memories. The memory cell array110may be coupled to the row decoder121through a plurality of word lines WL. The memory cell array110may be coupled to the page buffer circuit122through a plurality of bit lines BL. The row decoder121may select any one from among the memory blocks BLK included in the memory cell array110, in response to a row address X_A provided from the peripheral circuit123. The row decoder121may transfer an operating voltage X_V, provided from the peripheral circuit123, to word lines WL coupled to a memory block BLK selected from among the memory blocks BLK included in the memory cell array110. The page buffer circuit122may include a plurality of page buffers PB which are coupled to the bit lines BL, respectively. The page buffer circuit122may receive a page buffer control signal PB_C from the peripheral circuit123, and may transmit and receive a data signal DATA to and from the peripheral circuit123. The page buffer circuit122may control the bit lines BL, which are arranged in the memory cell array110, in response to the page buffer control signal PB_C. For example, the page buffer circuit122may detect data, stored in a memory cell of the memory cell array110, by sensing the signal of a bit line BL of the memory cell array110in response to the page buffer control signal PB_C, and may transmit the data signal DATA to the peripheral circuit123depending on the detected data. The page buffer circuit122may apply a signal to a bit line BL based on the data signal DATA, received from the peripheral circuit123, in response to the page buffer control signal PB_C, and thereby, may write data to a memory cell of the memory cell array110. The page buffer circuit122may write data to or read data from memory cells, which are coupled to an activated word line. The peripheral circuit123may receive a command signal CMD, an address signal ADD and a control signal CTRL from outside the memory device100, and may transmit and receive data DATA to and from a device outside the memory device100, for example, a memory controller. The peripheral circuit123may output signals for writing data to the memory cell array110or reading data from the memory cell array110, for example, the row address X_A, the page buffer control signal PB_C and so forth, based on the command signal CMD, the address signal ADD and the control signal CTRL. The peripheral circuit123may generate various voltages including the operating voltage X_V, which are required in the memory device100. As the size of an electronic product, and in particular a mobile product, in which the memory device100is mounted decreases, continuously reducing the size of the memory device100is demanded. As the stack number of the word lines WL is increased due to a demand for high capacity, the number of wiring lines that couple the word lines WL and the row decoder121is being increased. In order to suppress an increase in the size of the memory device100due to an increase in the number of wiring lines and in order to increase the degree of integration, an efficient wiring line layout method is required. FIG.2is a perspective view illustrating a part of a three-dimensional memory device in accordance with an embodiment of the disclosure.FIG.3Ais a cross-sectional view taken along a line A-A′ ofFIG.2,FIG.3Bis a cross-sectional view taken along a line B-B′ ofFIG.2, andFIG.4is a perspective view illustrating an upper stack and a lower stack ofFIG.2. Referring toFIGS.2,3A and3B, a three-dimensional memory device in accordance with an embodiment of the disclosure may include a substrate10, a lower stack LS that is disposed on the substrate10, and an upper stack US that is disposed on or over the lower stack LS. The lower stack LS may include a plurality of first word lines WL1that are stacked alternately with a plurality of interlayer dielectric layers22A, and the upper stack US may include a plurality of second word lines WL2that are stacked alternately with a plurality of interlayer dielectric layers22B. The first word lines WL1and the second word lines WL2may include a conductive material. For example, the first word lines WL1and the second word lines WL2may include at least one selected from among a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a transition metal (e.g., titanium or tantalum). The interlayer dielectric layers22A and22B may include silicon oxide. The lower stack LS may further include a source select line SSL, which is disposed under the plurality of first word lines WL1, and the upper stack US may further include a drain select line DSL, which is disposed on or over the plurality of second word lines WL2. The lower stack LS may include a first cell part CELL1, which is disposed in a first cell region CR1, a second cell part CELL2which is disposed in a second cell region CR2, and a first staircase part SP1and a first coupling part CP1, which are both disposed in a slimming region SR between the first cell region CR1and the second cell region CR2. The first coupling part CP1may couple the first cell part CELL1and the second cell part CELL2. The first staircase part SP1may extend parallel to the first coupling part CP1, and may have a staircase shape, which is coupled to the first cell part CELL1and descends in a direction toward the second cell part CELL2. The upper stack US may include a third cell part CELL3, which is disposed in the first cell region CR1and overlaps with the first cell part CELL1in a vertical direction, and may include a fourth cell part CELL4, which is disposed in the second cell region CR2and overlaps with the second cell part CELL2in the vertical direction. The upper stack US may include a second staircase part SP2and a second coupling part CP2, which are both disposed in the slimming region SR. The second coupling part CP2may couple the third cell part CELL3and the fourth cell part CELL4. The second staircase part SP2may extend parallel to the second coupling part CP2, and may have a staircase shape that is coupled to the third cell part CELL3and descends in the direction toward the fourth cell part CELL4. Referring toFIG.4, each of the first word lines WL1included in the lower stack LS may have a first pad area PAD1. The first pad areas PAD1of the first word lines WL1may be disposed in a staircase shape in the first staircase part SP1. Similar to the lower stack LS, each of the second word lines WL2included in the upper stack US may have a second pad area PAD2. The second pad areas PAD2of the second word lines WL2may be disposed in a staircase shape in the second staircase part SP2. The second staircase part SP2of the upper stack US may overlap with the first coupling part CP1of the lower stack LS in the vertical direction, and the second coupling part CP2of the upper stack US may overlap with the first staircase part SP1of the lower stack LS in the vertical direction. The first staircase part SP1of the lower stack LS and the second staircase part SP2of the upper stack US may not vertically overlap with each other. Accordingly, the first pad areas PAD1and the second pad areas PAD2may be disposed in relatively different positions, both horizontally and vertically. Referring again toFIG.2, a plurality of vertical channels CH, which pass through the lower stack LS and the upper stack US, may be defined in the first cell region CR1and the second cell region CR2. While not illustrated in detail, each of the plurality of vertical channels CH may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon, and may include, in some regions thereof, a p-type impurity such as boron (B). The gate dielectric layer may have a shape that surrounds the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer and a blocking layer, which are sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stack structure in which an oxide layer, a nitride layer and an oxide layer are sequentially stacked. A source select transistor may be configured in areas or regions where the source select line SSL surrounds the vertical channels CH. Memory cells may be configured in areas or regions where the plurality of first word lines WL1and the plurality of second word lines WL2surround the vertical channels CH. A drain select transistor may be configured in areas or regions where the drain select line DSL surrounds the vertical channels CH. The source select transistor, the plurality of memory cells and the drain select transistor, which are disposed in a line along one vertical channel CH, may configure one cell string. The present embodiment illustrates a case in which the lower stack LS and the upper stack US are built up on the single substrate10. Thus, the first word lines WL1of the lower stack LS and the second word lines WL2of the upper stack US may be coupled in common to a single cell string. Referring again toFIGS.3A and3B, a first dielectric layer ILD1may be formed on the lower stack LS to cover the lower stack LS. The upper stack US may be disposed on the first dielectric layer ILD1. A second dielectric layer ILD2may be formed on the upper stack US to cover the upper stack US. A plurality of first vertical vias VIA1and a plurality of second vertical vias VIA2may be defined to pass through the lower stack LS and the first dielectric layer ILD1. The plurality of first vertical vias VIA1may correspond to the first pad areas PAD1, respectively, of the first staircase part SP1, and may pass through the first staircase part SP1at the corresponding first pad areas PAD1. The plurality of second vertical vias VIA2may pass through the first coupling part CP1. A plurality of third vertical vias VIA3and a plurality of fourth vertical vias VIA4may be defined to pass through the upper stack US and the second dielectric layer ILD2. The plurality of third vertical vias VIA3may pass through the second coupling part CP2, and may be coupled to the plurality of first vertical vias VIA1, respectively. The plurality of fourth vertical vias VIA4may correspond to the second pad areas PAD2, respectively, of the second staircase part SP2, and may be coupled to the second vertical vias VIA2by passing through the second staircase part SP2at the corresponding second pad areas PAD2. The first and second vertical vias VIA1and VIA2may be isolated from the first word lines WL1by dielectric patterns24A, which may be defined between outer walls of the plurality of first vertical vias VIA1and the plurality of second vertical vias VIA2and the plurality of first word lines WL1. The dielectric patterns24A may be disposed alternately with the plurality of interlayer dielectric layers22A along the outer walls of the plurality of first vertical vias VIA1in the first staircase part SP1and along the outer walls of the plurality of second vertical vias VIA2in the first coupling part CP1. The dielectric patterns24A may be formed of, for example, silicon oxide. The third and fourth vertical vias VIA3and VIA4may be isolated from the second word lines WL2by dielectric patterns24B, which may be defined between outer walls of the plurality of third vertical vias VIA3and the plurality of fourth vertical vias VIA4and the plurality of second word lines WL2. The dielectric patterns24B may be disposed alternately with the plurality of interlayer dielectric layers22B along the outer walls of the plurality of third vertical vias VIA3in the second coupling part CP2and along the outer walls of the plurality of fourth vertical vias VIA4in the second staircase part SP2. The dielectric patterns24B may be formed of, for example, silicon oxide. First hard mask patterns HM1may be defined on the first pad areas PAD1, respectively, of the first word lines WL1. The first hard mask patterns HM1may be made of a conductive material, and thereby, may electrically couple the first word lines WL1and the first vertical vias VIA1that correspond to each other, respectively. Second hard mask patterns HM2may be defined on the second pad areas PAD2, respectively, of the second word lines WL2. The second hard mask patterns HM2may be made of a conductive material, and thereby, may electrically couple the second word lines WL2and the fourth vertical vias VIA4that correspond to each other, respectively. The plurality of first vertical vias VIA1and the plurality of third vertical vias VIA3may be used to configure electrical paths for coupling the first word lines WL1to a row decoder (not illustrated). The plurality of second vertical vias VIA2and the plurality of fourth vertical vias VIA4may be used to configure electrical paths for coupling the second word lines WL2to the row decoder. Although not illustrated, a logic structure including the row decoder may be disposed under the substrate10or on the second dielectric layer ILD2, and thereby, may overlap with the lower stack LS and the upper stack US in a vertical direction. The logic structure, the lower stack LS and the upper stack US may be fabricated on a single wafer. The logic structure, however, may also be fabricated on a wafer separate from the lower stack LS and the upper stack US, and then, may be bonded by a bonding technique, such as for example, hybrid bonding. Because the logic structure overlaps, in the vertical direction, with the lower stack LS and the upper stack US, which configure a memory cell array (110ofFIG.1), a planar area occupied by the three-dimensional memory device may be reduced, and the degree of integration of the three-dimensional memory device may be increased. FIG.5is a perspective view illustrating a memory device in relation to the disclosure. Referring toFIG.5, in order to provide a space in which vertical vias VIA12are disposed for coupling first word lines WL1of a lower stack LS and second word lines WL2of an upper stack US to a row decoder (not illustrated), an opening OFC may be formed in the lower stack LS and the upper stack US in a slimming region SR. If the number of word lines is increased to improve the degree of integration, then the number of the vertical vias VIA12will need to increase by the number of increased word lines. However, because the number of the vertical vias VIA12that can be disposed in the opening OFC is limited, any increase in the degree of integration may be restricted or limited. Further, in order to couple vertical vias VIA11to pad areas, a width W1of a second staircase part SP2of the upper stack US may be smaller than a width W2of a first staircase part SP1of the lower stack LS so as to expose first pad areas PAD1of the lower stack LS. Due to this fact, the widths of first and second pad areas PAD1and PAD2W1may be smaller than the width W2of the first staircase part SP1of the lower stack LS. For example, width W1may be half of the width W2. If the widths of the first and second pad areas PAD1and PAD2are narrow, then an open failure, in which the vertical via VIA11is not coupled to a pad area, or a short failure, in which the vertical via VIA11is coupled to at least two pad areas, may occur due to the lack of an alignment margin when the vertical via VIA11is formed. Embodiments of the disclosure illustrated inFIGS.2to4may overcome the above-described disadvantages of a memory device having the structure ofFIG.5. Referring again toFIGS.2to4, according to embodiments of the disclosure, the second coupling part CP2of the upper stack US overlaps with the first staircase part SP1of the lower stack LS in the vertical direction, and the second staircase part SP2of the upper stack US overlaps with the first coupling part CP1of the lower stack LS in the vertical direction. The vertical vias VIA1and VIA3, which couple the first word lines WL1to the row decoder, pass through the first staircase part SP1of the lower stack LS and the second coupling part CP2of the upper stack US. The vertical vias VIA2and VIA4, which couple the second word lines WL2to the row decoder, pass through the first coupling part CP1of the lower stack LS and the second staircase part SP2of the upper stack US. Therefore, it is not necessary to form, in the lower stack LS and the upper stack US, a separate space or opening for disposing vertical vias, and it is not necessary to dispose the vertical vias only in a separately defined, limited space as seen inFIG.5. Accordingly, it is possible to increase the number of vertical vias, which is advantageous for improving the degree of integration. In addition, the first pad areas PAD1may be configured to have a wider width, such as a width W3ofFIG.4of the second coupling part CP2of the upper stack US, and the second pad areas PAD2may be configured to have a wider width, such as the width W3of the first coupling part CP1of the lower stack LS inFIG.4. Therefore, it is possible to contribute to preventing an open failure or a short failure that may occur when vertical vias are formed by increasing a margin for alignment when coupling vertical vias to the first and second pad areas PAD1and PAD2. FIGS.6A to13Aare perspective views illustrating steps of a method for manufacturing a three-dimensional memory device in accordance with an embodiment of the disclosure.FIGS.6B to13Bare cross-sectional views taken along lines A-A′ ofFIGS.6A to13A, respectively, andFIGS.6C to13Care cross-sectional views taken along lines B-B′ ofFIGS.6A to13A, respectively. Referring toFIGS.6A to6C, as a plurality of sacrificial layers20A and a plurality of interlayer dielectric layers22A are alternately stacked on a substrate10, a first pre-stack P1may be formed. The plurality of sacrificial layers20A and the plurality of interlayer dielectric layers22A may be formed of different materials. The plurality of sacrificial layers20A may be formed of a material that has an etching selectivity with respect to the plurality of interlayer dielectric layers22A. For example, the plurality of interlayer dielectric layers22A may be formed of an oxide, and the plurality of sacrificial layers20A may be formed of a nitride. As a partial width of the first pre-stack P1is etched into a staircase shape, a staircase part S1, which exposes the plurality of sacrificial layers20A in a staircase shape, and a coupling part C1, which is disposed parallel to the staircase part S1, may be formed. First hard mask patterns HM1each having a through hole H1may be formed on exposed areas, respectively, of the sacrificial layers20A that are positioned in the staircase part S1. The first hard mask patterns HM1may be formed of a material that has an etching selectivity with respect to the plurality of sacrificial layers20A and the plurality of interlayer dielectric layers22A. The first hard mask patterns HM1may be formed of a conductive material that has an etching selectivity with respect to the plurality of sacrificial layers20A and the plurality of interlayer dielectric layers22A. Referring toFIGS.7A to7C, a dielectric layer ILD1may be formed on the first pre-stack P1and the first hard mask patterns HM1. The dielectric layer ILD1may be formed of a dielectric material that has an etching selectivity with respect to the sacrificial layers20A. For example, if the sacrificial layers20A are formed of a nitride, then the dielectric layer ILD1may be formed of an oxide. After a mask pattern (not illustrated) having a plurality of openings is formed on the dielectric layer ILD1, the dielectric layer ILD1and the first pre-stack P1are etched using the mask pattern as an etch mask. A plurality of first vertical holes VH1are formed to pass through the staircase part S1of the first pre-stack P1, and a plurality of second vertical holes VH2are formed to pass through the coupling part C1of the first pre-stack P1. Each of the plurality of first vertical holes VH1may pass through and expose an area through a corresponding sacrificial layer20A, and may communicate with the through hole H1of the first hard mask pattern HM1, which is defined on the exposed area of the corresponding sacrificial layer20A. Referring toFIGS.8A to8C, an etchant E capable of removing the sacrificial layers20A may be injected into the plurality of first vertical holes VH1and the plurality of second vertical holes VH2. As portions of the sacrificial layers20A around or common to the plurality of first vertical holes VH1and the portions of sacrificial layers20A around or common to the plurality of second vertical holes VH2are removed by the etchant E, a plurality of horizontal grooves HH1may be formed. Referring toFIGS.9A to9C, dielectric patterns24A may be formed to fill the plurality of horizontal grooves HH1. For example, by depositing a thin dielectric material on sidewalls of the plurality of first vertical holes VH1and the plurality of second vertical holes VH2such that the plurality of horizontal grooves HH1are filled, the dielectric patterns24A may be formed. In another example, the dielectric patterns24A may be formed by using a dielectric material to fill the plurality of horizontal grooves HH1, the plurality of first vertical holes VH1and the plurality of second vertical holes VH2, and then removing the dielectric material filled in the plurality of first vertical holes VH1and the plurality of second vertical holes VH2and leaving the dielectric material in the plurality of horizontal grooves HH1. The dielectric patterns24A may be formed of an oxide. Referring toFIGS.10A to10C, a plurality of first vertical vias VIA1and a plurality of second vertical vias VIA2may be formed as the plurality of first vertical holes VH1and the plurality of second vertical holes VH2are filled with a conductive material. Each of the plurality of first vertical vias VIA1may be coupled to a corresponding first hard mask pattern HM1. Referring toFIGS.11A to11C, as a plurality of sacrificial layers20B and a plurality of interlayer dielectric layers22B are alternately stacked on the dielectric layer ILD1, a second pre-stack P2may be formed. The plurality of sacrificial layers20B and the plurality of interlayer dielectric layers22B may be formed of different materials. The plurality of sacrificial layers20B may be formed of a material that has an etching selectivity with respect to the plurality of interlayer dielectric layers22B. For example, the plurality of interlayer dielectric layers22B may be formed of an oxide, and the plurality of sacrificial layers20B may be formed of a nitride. As a partial width of the second pre-stack P2is etched into a staircase shape in a staircase part S2, which exposes the plurality of sacrificial layers20B in a staircase shape, and a coupling part C2, which extends parallel to the staircase part S2, may be formed. The staircase part S2of the second pre-stack P2may overlap with the coupling part C1of the first pre-stack P1in the vertical direction, and the coupling part C2of the second pre-stack P2may overlap with the staircase part S1of the first pre-stack P1in the vertical direction. Second hard mask patterns HM2each having a through hole H2may be formed on exposed areas, respectively, of the sacrificial layers20B that are positioned in the step portions of the staircase part S2. The second hard mask patterns HM2may be formed of a material that has an etching selectivity with respect to the plurality of sacrificial layers20B and the plurality of interlayer dielectric layers22B. For example, the second hard mask patterns HM2may be formed of a conductive material that has an etching selectivity with respect to the plurality of sacrificial layers20B and the plurality of interlayer dielectric layers22B. A dielectric layer ILD2may be formed on the second pre-stack P2and the second hard mask patterns HM2. The dielectric layer ILD2may be formed of a dielectric material that has an etching selectivity with respect to the sacrificial layers20B. For example, if the sacrificial layers20B are formed of a nitride, then the dielectric layer ILD2may be formed of an oxide. After a mask pattern (not illustrated) having a plurality of openings is formed on the dielectric layer ILD2, the dielectric layer ILD2and the second pre-stack P2are etched using the mask pattern as an etch mask. A plurality of third vertical holes VH3are formed to pass through the coupling part C2of the second pre-stack P2and to expose the plurality of first vertical vias VIA1, respectively, and a plurality of fourth vertical holes VH4are formed to pass through the staircase part S2of the second pre-stack P2and to expose the plurality of second vertical vias VIA2, respectively. Each of the plurality of fourth vertical holes VH4may pass through and expose an area common to a sacrificial layer20B, and may communicate with the through hole H2of the second hard mask pattern HM2, which is defined on the exposed area of the corresponding sacrificial layer20B. Referring toFIGS.12A to12C, an etchant capable of removing the sacrificial layers20B may be injected into the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4. As portions of the sacrificial layers20B around or common to the plurality of third vertical holes VH3and portions of the sacrificial layers20B around or common to the plurality of fourth vertical holes VH4are removed by the etchant, a plurality of horizontal grooves HH2may be formed. Referring toFIGS.13A to13C, dielectric patterns24B may be formed to fill the plurality of horizontal grooves HH2. For example, by depositing a thin dielectric material on sidewalls of the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4such that the plurality of horizontal grooves HH2are filled, the dielectric patterns24B may be formed. In another example, the dielectric patterns24B may be formed by using a dielectric material to fill the plurality of horizontal grooves HH2, the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4, and then removing the dielectric material filled in the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4and leaving the dielectric material in the plurality of horizontal grooves HH2. The dielectric patterns24B may be formed of an oxide. As the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4are filled with a conductive material, a plurality of third vertical vias VIA3and a plurality of fourth vertical vias VIA4may be formed. The plurality of third vertical vias VIA3are formed in the plurality of third vertical holes VH3, and may be coupled to the plurality of first vertical vias VIA1, respectively. The plurality of fourth vertical vias VIA4are formed in the plurality of fourth vertical holes VH4, and may each be coupled to a corresponding second vertical via VIA2and a corresponding second hard mask pattern HM2. Remaining portions of the sacrificial layers20A and20B may be replaced with an electrode material to form first and second word lines (WL1and WL2ofFIG.3A). FIG.14is a cross-sectional view illustrating first vertical vias in accordance with another embodiment of the disclosure, andFIGS.15A to16Bare cross-sectional views illustrating a method for forming the first vertical vias ofFIG.14. Referring toFIG.14, in a first staircase part SP1, an upper portion VIA1_U of a first vertical via VIA1, which passes through a dielectric layer ILD1, may have a larger width than a lower portion VIA1_L of the first vertical via VIA1that passes through the stack in first staircase part SP1. As described above, after a plurality of horizontal grooves (HH1ofFIGS.8B and8C) are formed through a process described with reference toFIGS.8A to8C, a dielectric material30may be used to fill the horizontal grooves (HH1ofFIGS.8B and8C), first vertical holes (VH1ofFIG.8A) and second vertical holes (VH2ofFIG.8A) as illustrated inFIGS.15A and15B. A mask pattern PR1may be formed on the dielectric layer ILD1. InFIG.15A, the mask pattern PR1may have a plurality of first openings OP1, which expose the dielectric material30and a portion of the dielectric layer ILD1around the first vertical holes (VH1ofFIG.8A). InFIG.15B, the mask pattern PR1may also have a plurality of second openings OP2, which expose the dielectric material30filled in the second vertical holes (VH2ofFIG.8A). As the dielectric layer ILD1and the dielectric material30are etched using the mask pattern PR1and the first hard mask patterns HM1as an etch mask, as illustrated inFIGS.16A and16B, the dielectric material30common to the first vertical holes VH1and second vertical holes VH2may be removed, while dielectric patterns24A may be formed from the dielectric material30remaining in the horizontal grooves (HH1ofFIGS.8B and8C). Because the first opening OP1of the mask pattern PR1exposes not only the dielectric material30filled in the first vertical hole (VH1ofFIG.8A), but also the dielectric layer ILD1around the first vertical hole (VH1ofFIG.8A), an upper portion of the first vertical hole VH1may have a width wider than that of a lower portion. The mask pattern PR1may be formed using a photoresist. The mask pattern PR1remaining after the dielectric material30and the dielectric layer ILD1are etched may be removed through a strip process. Thereafter, as the plurality of first vertical holes VH1and the plurality of second vertical holes VH2are filled with a conductive material, a plurality of first vertical vias VIA1(seeFIG.14) and a plurality of second vertical vias may be formed. FIGS.17A and17Bare cross-sectional views illustrating first vertical vias and fourth vertical vias in accordance with a further embodiment of the disclosure.FIGS.18A to21Bare cross-sectional views illustrating a method for forming the first vertical vias and the fourth vertical vias illustrated inFIGS.17A and17B. Referring toFIG.17A, a lower portion VIA1_L of a first vertical via VIA1may be positioned in a first staircase part SP1, and may be isolated from first word lines WL1by dielectric patterns24A. An upper portion VIA1_U of the first vertical via VIA1may pass through a dielectric layer ILD1and a portion of first hard mask pattern HM1common to a pad area, and thereby, may be directly coupled to a first pad area PAD1of a corresponding first word line WL1. In this embodiment, the first hard mask pattern HM1may be a conductive material or may be an insulating material. Referring toFIG.17B, a lower portion VIA4_L of a fourth vertical via VIA4may be positioned in a second staircase part SP2, and may be isolated from second word lines WL2by dielectric patterns24B. An upper portion VIA4_U of the fourth vertical via VIA4may pass through a dielectric layer ILD2and a portion of second hard mask pattern HM2common to a pad area, and thereby, may be directly coupled to a second pad area PAD2of a corresponding second word line WL2. In this embodiment, the second hard mask pattern HM2may be a conductive material or may be an insulating material. As described above, after a plurality of horizontal grooves (HH1ofFIGS.8B and8C) are formed through a process described with reference toFIGS.8A to8C, a dielectric material30may be used to fill the horizontal grooves (HH1ofFIGS.8B and8C), first vertical holes (VH1ofFIG.8A) and second vertical holes (VH2ofFIG.8A) as illustrated inFIGS.18A and18B. A mask pattern PR2may be formed on the dielectric layer ILD1. The mask pattern PR2may have a plurality of first openings OP1′, which expose the dielectric material30and a portion of the dielectric layer ILD1around the first vertical holes (VH1ofFIG.8A). The mask pattern PR2may also have and a plurality of second openings OP2′, which expose the dielectric material30filled in the second vertical holes (VH2ofFIG.8A). Using the mask pattern PR2and the first hard mask patterns HM1as an etch mask, the dielectric layer ILD1and the dielectric material30may be etched. Accordingly, as illustrated inFIGS.19A and19B, the dielectric material30common to the first vertical holes VH1and second vertical holes VH2may be removed, while dielectric patterns24A may be formed from the dielectric material30remaining in the horizontal grooves (HH1ofFIGS.8B and8C). As the first hard mask patterns HM1in the first vertical holes VH1are etched, portions of sacrificial layers20A immediately under the first hard mask patterns HM1may be exposed. The mask pattern PR2may be formed using a photoresist. The remaining mask pattern PR2may be removed through a strip process. Thereafter, as the plurality of first vertical holes VH1and the plurality of second vertical holes VH2are filled with a conductive material, a plurality of first vertical vias VIA1(seeFIG.17A) and a plurality of second vertical vias VIA2(seeFIG.17B) may be formed. As described above, after a plurality of horizontal grooves (HH2ofFIGS.12B and12C) are formed through a process described above with reference toFIGS.12A to12C, a dielectric material32may fill the horizontal grooves (HH2ofFIGS.12B and12C), third vertical holes (VH3ofFIG.12A) and fourth vertical holes (VH4ofFIG.12A) as seen inFIGS.20A and20B. A mask pattern PR3may be formed on the dielectric layer ILD2. The mask pattern PR3may have a plurality of first openings OP1″, which expose the dielectric material32and a portion of the dielectric layer ILD2around the third vertical holes (VH3ofFIG.12A). The mask pattern PR3may also have plurality of second openings OP2″, which expose the dielectric material32and a portion of the dielectric layer ILD2around the fourth vertical holes (VH4ofFIG.12A). Using the mask pattern PR3and the second hard mask patterns HM2as an etch mask, the dielectric layer ILD2and the dielectric material32may be etched. Accordingly, as illustrated inFIGS.21A and21B, the dielectric material32common to the third vertical holes VH3and fourth vertical holes VH4may be removed, while dielectric patterns24B may be formed from the dielectric material32remaining in the horizontal grooves (HH2ofFIGS.12B and12C). As the second hard mask patterns HM2in the fourth vertical holes VH4are etched, portions of sacrificial layers20B immediately under the second hard mask patterns HM2may be exposed. The mask pattern PR3may be formed using a photoresist. The remaining mask pattern PR3may be removed through a strip process. Thereafter, as the plurality of third vertical holes VH3and the plurality of fourth vertical holes VH4are filled with a conductive material, a plurality of third vertical vias VIA3(seeFIG.17A) and a plurality of fourth vertical vias VIA4(seeFIG.17B) may be formed. FIGS.22A to22Care views illustrating first vertical vias and fourth vertical vias in accordance with yet another embodiment of the disclosure. In detail,FIG.22Ais a perspective view,FIG.22Bis a cross-sectional view taken along a line A-A′ ofFIG.22A, andFIG.22Cis a cross-sectional view taken along a line B-B′ ofFIG.22A. Referring toFIGS.22A to22C, each of first vertical vias VIA1may include a conductive pad portion40, which is disposed on a first pad area PAD1of a corresponding first word line WL1and is directly coupled to the first pad area PAD1. The conductive pad portion40may have a flat plate shape that covers an upper surface of the first pad area PAD1of the corresponding first word line WL1. Each of fourth vertical vias VIA4may include a conductive pad portion42that is disposed on a second pad area PAD2of a corresponding second word line WL2and is directly coupled to the second pad area PAD2. The conductive pad portion42may have a flat plate shape that covers an upper surface of the second pad area PAD2of the corresponding second word line WL2. As previously described, after the step of forming the dielectric patterns24A described above with reference toFIGS.9A to9C, a process of removing first hard mask patterns (HM1ofFIG.9A) may be additionally performed. In the case of the present embodiment, the first hard mask patterns may be made of a conductive material or a dielectric material. Thereafter, in the process of filling first vertical holes (VH1ofFIG.9A) and second vertical holes (VH2ofFIG.9A) with a conductive material described above with reference toFIGS.10A to10C, spaces from which the first hard mask patterns are removed may be filled with the conductive material. The conductive material filling in the spaces where the first hard mask patterns are removed may form conductive pad portions40(seeFIG.22B) of the first vertical vias VIA1. As previously described, after the step of forming the dielectric patterns24B described above with reference toFIGS.13A to13C, a process of removing second hard mask patterns (HM2ofFIG.13A) may be additionally performed. In the process of filling third vertical holes (VH3) and fourth vertical holes (VH4) with a conductive material, spaces from which the second hard mask patterns are removed may be filled with the conductive material. The conductive material filling in the spaces from which the second hard mask patterns are removed may form conductive pad portions42(seeFIGS.22A and22C) of the fourth vertical vias VIA4. FIG.23is a view illustrating a three-dimensional memory device in accordance with still another embodiment of the disclosure. Referring toFIG.23, a lower stack LS may be configured in a first cell wafer CW1, and an upper stack US may be configured in a second cell wafer CW2, which is disposed on the first cell wafer CW1. The lower stack LS may include a plurality of first word lines WL1, which are stacked on a substrate10A of the first cell wafer CW1, and the upper stack US may include a plurality of second word lines WL2, which are stacked on a substrate10B of the second cell wafer CW2. The lower stack LS may further include a first source select line SSL1, which is disposed under the plurality of first word lines WL1, and a first drain select line DSL1, which is disposed on the plurality of first word lines WL1. The upper stack US may further include a second source select line SSL2, which is disposed under the plurality of second word lines WL2, and a second drain select line DSL2, which is disposed on the plurality of second word lines WL2. A plurality of first vertical channels CH1, which pass through the lower stack LS and are coupled to the substrate10A, may be defined in a first cell region CR1and a second cell region CR2. A plurality of second vertical channels CH2, which pass through the upper stack US and are coupled to the substrate10B, may be defined in the first cell region CR1and the second cell region CR2. The first cell wafer CW1and the second cell wafer CW2may be bonded to each other by a bonding technique, for example, by hybrid bonding. Although not illustrated, the substrate10B of the second cell wafer CW2may include a plurality of through vias for electrically coupling a plurality of first vertical vias VIA1to a plurality of third vertical vias VIA3, and a plurality of through vias for electrically coupling a plurality of second vertical vias VIA2to a plurality of fourth vertical vias VIA4. A logic wafer including a row decoder may be bonded to the bottom of the first cell wafer CW1or to the top of the second cell wafer CW2. FIG.24is a block diagram schematically illustrating a memory system including a three-dimensional memory device in accordance with an embodiment of the disclosure. Referring toFIG.24, a memory system600in accordance with an embodiment may include a nonvolatile memory device (NVM Device)610and a memory controller620. The nonvolatile memory device (NVM Device)610may be constituted by a three-dimensional memory device described above and may operate in the manner described above. The memory controller620may be configured to control the nonvolatile memory device (NVM Device)610. By the combination of the nonvolatile memory device (NVM Device)610and the memory controller620, a memory card or a solid state disk (SSD) may be provided. An SRAM621is used as a working memory of a processing unit (CPU)622. A host interface (Host I/F)623includes a data exchange protocol of a host, which is coupled with the memory system600. An error correction code block (ECC)624detects and corrects an error included in data read from the nonvolatile memory device (NVM Device)610. A memory interface (Memory I/F)625interfaces with the nonvolatile memory device (NVM Device)610of the present embodiment. The processing unit (CPU)622performs general control operations for data exchange of the memory controller620. Although not shown in the drawing, it is obvious to a person skilled in the art to which the embodiment pertains that the memory system600in accordance with the embodiment may be additionally provided with a ROM which stores code data for interfacing with the host. The nonvolatile memory device (NVM Device)610may be provided as a multi-chip package which is constituted by a plurality of flash memory chips. The memory system600in accordance with the embodiment, described above, may be provided as a storage medium of high reliability, which has a low probability of an error to occur. In particular, the nonvolatile memory device of the present embodiment may be included in a memory system such as a solid state disk (SSD) which is being actively studied recently. In this case, the memory controller620may be configured to communicate with an exterior (for example, the host) through one of various interface protocols such as a USB (universal serial bus) protocol, an MMC (multimedia card) protocol, a PCI-E (peripheral component interconnection express) protocol, an SATA (serial advanced technology attachment) protocol, a PATA (parallel advanced technology attachment) protocol, an SCSI (small computer system interface) protocol, an ESDI (enhanced small disk interface) protocol and an IDE (Integrated Drive Electronics) protocol. FIG.25is a block diagram schematically illustrating a computing system including a three-dimensional memory device in accordance with an embodiment of the disclosure. Referring toFIG.25, a computing system700in accordance with an embodiment may include a memory system710, a microprocessor (CPU)720, a RAM730, a user interface740and a modem750such as a baseband chipset, which are electrically coupled to a system bus760. In the case where the computing system700in accordance with the embodiment is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system700may be additionally provided. Although not shown in the drawing, it is obvious to a person skilled in the art to which the embodiment pertains that the computing system700in accordance with the embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and so on. The memory system710may configure, for example, an SSD (solid state drive/disk) which uses a nonvolatile memory to store data. Otherwise, the memory system710may be provided as a fusion flash memory (for example, an OneNAND flash memory). Although exemplary embodiments of the disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not for limiting the technological scope. The technological scope of the disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the disclosure should be interpreted by the appended claims and encompass all equivalents falling within the scope of the appended claims. | 48,046 |
11943916 | DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS FIG.1is a sectional view explaining semiconductor devices according to exemplary embodiments of the disclosure.FIGS.2to6are enlarged views showing a portion12ofFIG.1.FIGS.7to9are enlarged views showing a portion14ofFIG.1.FIG.10is an enlarged view showing a portion16ofFIG.1.FIG.11is an enlarged view showing a portion17ofFIG.1.FIG.12is an enlarged view showing a portion18ofFIG.1.FIG.13is an enlarged view showing a portion19ofFIG.1. For example, the semiconductor devices according to the exemplary embodiments of the disclosure may include a non-volatile memory such as VNAND or3D flash memory. The semiconductor devices according to the exemplary embodiments of the disclosure may include a cell-on-peripheral (COP) structure. Referring toFIG.1, the semiconductor devices according to the exemplary embodiments of the disclosure may include a substrate21, an element isolation layer23, a plurality of impurity regions25, a plurality of transistors27, a first insulating layer29, a plurality of peripheral circuit wirings31, a second insulating layer33, a third insulating layer35, a source line41, a fourth insulating layer43, a connecting electrode layer45G, a connecting mold layer45M, a fifth insulating layer47, a sixth insulating layer48, a supporter49, a seventh insulating layer55, an eighth insulating layer56, a ninth insulating layer57, a tenth insulating layer58, a stack structure68, a plurality of channel structures70, a plurality of dummy pillars81(i.e., a plurality of pillar structures), a plurality of word line isolation patterns82, a plurality of cell contact plugs83, a through electrode84, a plurality of bit plugs85(i.e., a plurality of bit line plugs), a plurality of first intermediate plugs86, a second intermediate plug87, and a plurality of bit lines89. The stack structure68may include a plurality of mold layers51and52and a plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62, which are alternately stacked on the substrate21. The plurality of mold layers51and52may include a plurality of first mold layers51and a plurality of second mold layers52. The plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62may include a plurality of first horizontal conductive layers61and a plurality of second horizontal conductive layers62N−2,62N−1,62N,62N+1 and62. Each of the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62may include a gate electrode GE and a connecting pad CP. The plurality of first mold layers51and the plurality of first horizontal conductive layers61may constitute a first stack structure66. The plurality of second mold layers52and the plurality of second horizontal conductive layers62N−2,62N−1,62N,62N+1 and62may constitute a second stack structure67. The substrate21may include a cell area CA, a connection area EXT in continuity with a side surface of the cell area CA, and a through area TH adjacent to the cell area CA and the connection area EXT. The substrate21may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The element isolation layer23may be formed on the substrate21. The plurality of impurity regions25may be formed in the substrate21. Each of the plurality of impurity regions25may include or be doped with N-type impurities or P-type impurities. The plurality of transistors27may be formed in the substrate21and/or on the substrate21in accordance with various methods. The plurality of transistors27may include a fin field effect transistor (FinFET), a multi-bridge channel transistor such as MBCFET®, a nanowire transistor, a vertical transistor, a recess channel transistor, a 3-D transistor, a planar transistor, or a combination thereof. The plurality of transistors27may include some of the plurality of impurity regions25. Some of the plurality of impurity regions25may correspond to a drain region or a source region. The first insulating layer29may be formed on the substrate21to cover the plurality of transistors27and the element isolation layer23. The plurality of peripheral circuit wirings31may be formed in the first insulating layer29. The plurality of peripheral circuit wirings31may include horizontal and vertical wirings having various shapes. Some of the plurality of peripheral circuit wirings31may contact the plurality of impurity regions25. The plurality of transistors27and the plurality of peripheral circuit wirings31may constitute a peripheral circuit. The second insulating layer33may be formed on the first insulating layer29and the plurality of peripheral circuit wirings31. The third insulating layer35may be formed on the second insulating layer33. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. The second insulating layer33may correspond to a capping layer or an etch stop layer. The second insulating layer33may include a material different from those of the first insulating layer29and the third insulating layer35. For example, the second insulating layer33may include silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. The first insulating layer29and the third insulating layer35may include silicon oxide. Each of the element isolation layer23, the first insulating layer29, the second insulating layer33, the third insulating layer35, the fourth insulating layer43, the connecting mold layer45M, the fifth insulating layer47, the sixth insulating layer48, the plurality of mold layers51and52, the seventh insulating layer55, the eighth insulating layer56, the ninth insulating layer57, the tenth insulating layer58, the plurality of dummy pillars81, and the plurality of word line isolation patterns82may include a single layer or multiple layers. Each of the element isolation layer23, the first insulating layer29, the second insulating layer33, the third insulating layer35, the fourth insulating layer43, the connecting mold layer45M, the fifth insulating layer47, the sixth insulating layer48, the plurality of mold layers51and52, the seventh insulating layer55, the eighth insulating layer56, the ninth insulating layer57, the tenth insulating layer58, the plurality of dummy pillars81, and the plurality of word line isolation patterns82may include silicon oxide, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), low-k dielectrics, or high-k dielectrics (for example, metal oxide such as HfO or AlO, metal silicate such as HfSiO, etc.). Each of the plurality of peripheral circuit wirings31, the source line41, the connecting electrode layer45G, the supporter49, the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62, the plurality of cell contact plugs83, the through electrode84, the plurality of bit plugs85, the plurality of first intermediate plugs86, the second intermediate plug87, and the plurality of bit lines89may include a single layer or multiple layers. Each of the plurality of peripheral circuit wirings31, the source line41, the connecting electrode layer45G, the supporter49, the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62, the plurality of cell contact plugs83, the through electrode84, the plurality of bit plugs85, the plurality of first intermediate plugs86, the second intermediate plug87, and the plurality of bit lines89may include a conductive material such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, amorphous silicon, monocrystalline silicon, or a combination thereof. The source line41and the fourth insulating layer43may be formed on the third insulating layer35. The source line41may correspond to a common source line (CSL). The source line41may include a conductive layer such as a polysilicon layer or a monocrystalline semiconductor layer. The source line41may be disposed in the cell region CA and the connection area EXT on the substrate21. The third insulating layer35may be disposed on the through area TH. The connecting electrode layer45G and the connecting mold layer45M may be formed on the source line41. The fifth insulating layer47may be formed on the fourth insulating layer43. The supporter49may be formed on the connecting electrode layer45G and the connecting mold layer45M. The connecting electrode layer45G and the connecting mold layer45M may be formed at substantially the same level. The sixth insulating layer48may be formed on the fifth insulating layer47. Upper surfaces of the supporter49and the sixth insulating layer48may be substantially coplanar with each other. The connecting electrode layer45G may contact the source line41. For example, the connecting electrode layer45G may include a conductive layer such as a polysilicon layer. The supporter49may include or may be a polysilicon layer. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes. The stack structure68, which includes the plurality of mold layers51and52and the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62stacked alternately, may be formed on the supporter49. The stack structure68may be disposed in the cell area CA and the connection area EXT on the substrate21. The gate electrode GE may be disposed in the cell region CA, and may extend into the connection area EXT. The connecting pad CP may be disposed in the connection area EXT, and may be in continuity with the gate electrode GE. The stack structure68may include a stepped shape in the connection area EXT on the substrate21. For example, the connecting pads CP may be at the ends of the horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62without vertically overlapping each other to provide connection sites where each horizontal conductive layer is connected to a corresponding cell contact plug83. The seventh insulating layer55may be formed to cover the stack structure68in the connection area EXT and the sixth insulating layer48. The seventh insulating layer55may contact an upper surface of the connecting pad CP and/or a side surface of the connecting pad CP. The stack structure68may be disposed in the cell region CA on the substrate21, and may extend on the connection area EXT. The connecting pad CP may be referred to as a “raised pad”. The plurality of channel structures70may be formed to extend into the source line41while extending through the stack structure68, the supporter49and the connecting electrode layer45G. The plurality of channel structures70may extend through the gate electrode GE. The plurality of channel structures70may be disposed in the cell region CA on the substrate21. Upper surfaces of the stack structure68, the plurality of channel structures70and the seventh insulating layer55may be substantially coplanar as each other. The eighth insulating layer56may be formed on the stack structure68, the plurality of channel structures70and the seventh insulating layer55. The plurality of dummy pillars81may be formed to extend into the source line41while extending through the eighth insulating layer56, the seventh insulating layer55, the stack structure68, the supporter49and the connecting mold layer45M. The plurality of dummy pillars81may be disposed in the connection area EXT on the substrate21. Each of the plurality of dummy pillars81(i.e., the plurality of pillar structures) may include an inactive pillar81P (i.e., a pillar) extending through the stack structure68while having a greater vertical height than a horizontal width, and a stud81S formed in the supporter49, the connecting mold layer45M and the source line41. The stud81S may surround a lower surface of the inactive pillar81P and a side surface of the inactive pillar81P. For example, the inactive pillar81P may include or may be formed of silicon oxide. The stud81S may include or may be formed of silicon oxide, silicon oxynitride, or a combination thereof. For example, the inactive pillar81P and the stud81S may be formed of the same material as each other. The present inventive concept is not limited thereto. For example, the inactive pillar81P and the stud81S may be formed of insulating materials different from each other. The plurality of dummy pillars81may serve to provide a structural support with the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62stacked alternately on the substrate21. For example, the dummy pillars81may prevent the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62from collapsing down while a semiconductor device is being processed, and the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62in the connection area EXT may be more securely in place. The through electrode84may be formed to extend through the eighth insulating layer56, the seventh insulating layer55, the sixth insulating layer48, the fifth insulating layer47, the fourth insulating layer43, the third insulating layer35, and the second insulating layer33such that the through electrode84contacts a corresponding one of the plurality of peripheral circuit wirings31. The word line isolation pattern82may be formed to extend through the eighth insulating layer56, the stack structure68, and the supporter49. The ninth insulating layer57may be formed on the eighth insulating layer56, the word line isolation pattern82, and the through electrode84. The plurality of cell contact plugs83may be formed to extend through the ninth insulating layer57, the eighth insulating layer56, and the seventh insulating layer55such that the plurality of cell contact plugs83contacts the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62. The plurality of cell contact plugs83may be disposed in the connection area EXT on the substrate21. Each of the plurality of cell contact plugs83may contact a corresponding connecting pad CP. Each of the plurality of cell contact plugs83may electrically contact a corresponding one of the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62. Each of the plurality of cell contact plugs83may be referred to as a “contact plug”. The tenth insulating layer58may be formed on the ninth insulating layer57. The plurality of bit plugs85may be formed to extend through the tenth insulating layer58, the ninth insulating layer57, and the eighth insulating layer56such that each of the plurality of bit plugs85contacts a corresponding one of the plurality of channel structures70. The plurality of bit lines89may be formed on the tenth insulating layer58to contact the plurality of bit plugs85. The plurality of first intermediate plugs86may be formed to extend through the tenth insulating layer58such that each of the plurality of first intermediate plugs86contacts a corresponding one of the plurality of cell contact plugs83. The second intermediate plug87may be formed to extend through the tenth insulating layer58and the ninth insulating layer57such that the second intermediate plug87contacts the through electrode84. At least one of the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62, which is disposed adjacent to a lower surface of the stack structure68, may correspond to a ground selection line. At least one of the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62, which is disposed adjacent to the upper surface of the stack structure68, may correspond to a string selection line. Some of the plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62may correspond to a word line. Referring toFIG.2, the plurality of second horizontal conductive layers62N−2,62N−1,62N,62N+1 and62may include an N−2-th conductive layer62N−2, an N−1-th conductive layer62N−1, an N-th conductive layer62N, and an N+1-th conductive layer62N+1. Each of the plurality of second horizontal conductive layers62N−2,62N−1,62N,62N+1 and62may include the gate electrode GE, and the connecting pad CP in continuity with the gate electrode GE. The horizontal width of the gate electrode GE may be greater than the vertical thickness of the gate electrode GE. The vertical thickness of the connecting pad CP may be greater than the vertical thickness of the gate electrode GE. The plurality of second mold layers52may be disposed among the plurality of second horizontal conductive layers62N−2,62N−1,62N,62N+1 and62. The seventh insulating layer55may contact the upper and side surfaces of the connecting pad CP. The dummy pillar81(i.e., the pillar structure) may include an inactive pillar81P (i.e., a pillar), and a plurality of extensions81E1,81E2and81E3. The plurality of extensions81E1,81E2and81E3may include a first extension81E1, a second extension81E2, and a third extension81E3. The inactive pillar81P may extend through the seventh insulating layer55, the connecting pad CP of the N-th conductive layer62N, the gate electrode GE of the N−1-th conductive layer62N−1, the gate electrode GE of the N−2-th conductive layer62N−2, and the plurality of second mold layers52. The horizontal height of the inactive pillar81P may be greater than the vertical height of the inactive pillar81P. Each of the first extension81E1, the second extension81E2and the third extension81E3may protrude from a side surface of the inactive pillar81P. Each of the first extension81E1, the second extension81E2and the third extension81E3may be materially in continuity with the side surface of the inactive pillar81P. For example, the first extension81E1, the second extension81E2, and the third extension81E3may include substantially the same material layer. For example, the first extension81E1, the second extension81E2and the third extension81E3may include silicon oxide, silicon oxynitride, or a combination thereof. The first extension81E1may be horizontally aligned with the connecting pad CP of the N-th conductive layer62N to be at the same vertical height above the substrate. The first extension81E1may have substantially the same vertical thickness as the connecting pad CP of the N-th conductive layer62N. A side surface of the first extension81E1may contact the side surface of the connecting pad CP. The horizontal width of the first extension81E1may be smaller than the vertical thickness of the first extension81E1. The second extension81E2may be spaced apart from the first extension81E1. The second extension81E2may be horizontally aligned with the gate electrode GE of the N-th conductive layer62N−1 to be at the same vertical height above the substrate. A corresponding one of the plurality of second mold layers52may be disposed between the first extension81E1and the second extension81E2. The second extension81E2may have substantially the same vertical thickness as the gate electrode GE of the N−1-th conductive layer62N−1. The vertical thickness of the second extension81E2may be smaller than the vertical thickness of the first extension81E1. A side surface of the second extension81E2may contact a side surface of the gate electrode GE. The horizontal width of the second extension81E2may be greater than the vertical thickness of the second extension81E2. The horizontal width of the second extension81E2may be greater than the horizontal width of the first extension81E1. A portion of the second extension81E2may vertically overlap with the connecting pad CP of the N-th conductive layer62N. A corresponding one of the plurality of second mold layers52may be disposed between the second extension81E2and the connecting pad CP. The third extension81E3may be spaced apart from the second extension81E2. The third extension81E3may be horizontally aligned with the gate electrode GE of the N−2-th conductive layer62N−2 to be at the same vertical height above the substrate. A portion of the third extension81E3may vertically overlap the connecting pad CP of the N-th conductive layer62N. A corresponding one of the plurality of second mold layers52may be disposed between the third extension81E3and the second extension81E2. The third extension81E3may have substantially the same vertical thickness as the gate electrode GE of the N−2-th conductive layer62N−2. A side surface of the third extension81E3may contact the side surface of the gate electrode GE. The horizontal width of the third extension81E3may be greater than the vertical thickness of the third extension81E3. The horizontal width of the third extension81E3may be greater than the horizontal width of the first extension81E1. The horizontal width of the third extension81E3may be substantially equal to the horizontal width of the second extension81E2. Each of the first extension81E1, the second extension81E2and the third extension81E3may have a round side surface. For example, each of the first extension81E1, the second extension81E2, and the third extension81E3may have a convex side surface which curves outward away from the inactive pillar81P. Each of the first extension81E1, the second extension81E2and the third extension81E3may have a smaller horizontal width at an upper surface thereof than at a central portion thereof. Each of the first extension81E1, the second extension81E2and the third extension81E3may have a greater horizontal width at a lower surface thereof than at the central portion thereof. The cell contact plug83may extend through the seventh insulating layer55such that the cell contact plug83contacts the connecting pad CP of the N-th conductive layer62N. The cell contact plug83may extend into the connecting pad CP. The cell contact plug83may be spaced apart from the first extension81E1. A portion of the second extension81E2may overlap with the cell contact plug83. Referring toFIG.3, each of the first extension81E1, the second extension81E2and the third extension81E3may have a side surface having various shapes. Each of the second extension81E2and the third extension81E3may have a side surface having a shape different from that of the first extension81E1. For example, the surface of the first extension81E1may include a stepped shape. Referring toFIG.4, the cell contact plug83may extend into the second extension81E2while extending through the seventh insulating layer55, the connecting pad CP of the N-th conductive layer62N, and a corresponding one of the plurality of second mold layers52. The cell contact plug83may be spaced apart from the first extension81E1. The cell contact plug83may contact the connecting pad CP. Referring toFIG.5, at least some of the first extension81E1, the second extension81E2and the third extension81E3may include a material different from that of the inactive pillar81P. For example, the inactive pillar81P may include or may be formed of silicon oxide, and the second extension81E2and the third extension81E3may include or may be formed of silicon oxynitride. For example, the first extension81E1may include a material different from those of the second extension81E2and the third extension81E3. The first extension81E1may include or may be formed of silicon oxide, whereas the second extension81E2and the third extension81E3may include or may be formed of silicon oxynitride. For example, the inactive pillar81P and the first extension81E1may include or may be formed of silicon oxide, whereas the second extension81E2and the third extension81E3may include or may be formed of silicon oxynitride. Referring toFIG.6, the first extension81E1, the second extension81E2and the third extension81E3may include a material different from that of the inactive pillar81P. The first extension81E1may include a material different from those of the second extension81E2and the third extension81E3. For example, the inactive pillar81P may include or may be formed of silicon oxide, the first extension81E1may include or may be formed of SiBON, and the second extension81E2and the third extension81E3may include or may be formed of silicon oxynitride. Referring toFIG.7, the dummy pillar81may include the inactive pillar81P and the stud81S. A lowermost end of the dummy pillar81may be disposed at a level different from that of a lowermost end of the channel structure70. The lowermost end of the dummy pillar81may be formed at a lower level than the lowermost end of the channel structure70. Referring toFIG.8, the lowermost end of the dummy pillar81may be formed at a higher level than the lowermost end of the channel structure70. Referring toFIG.9, the lowermost end of the dummy pillar81may be formed at substantially the same level as the lowermost end of the channel structure70. Referring toFIG.10, the connecting mold layer45M may include a lower mold layer45L, an upper mold layer45U on the lower mold layer45L, and an intermediate mold layer45C between the lower mold layer45L and the upper mold layer45U. The intermediate mold layer45C may include a material having etch selectivity with respect to the lower mold layer45L and the upper mold layer45U. For example, each of the lower mold layer45L and the upper mold layer45U may include or may be formed of silicon oxide. The intermediate mold layer45C may include or may be formed of silicon nitride. Referring toFIG.11, the channel structure70may include a core pattern77, a channel layer76surrounding an outside of the core pattern77, an information storage pattern75surrounding an outside of the channel layer76, and a bit pad78(i.e., a bit line pad) on the channel layer76. The information storage pattern75may include a tunnel insulating layer71surrounding the outside of the channel layer76, a charge storage layer72surrounding an outside of the tunnel insulating layer71, and a blocking layer73surrounding an outside of the charge storage layer72. The channel structure70may extend through the second horizontal layer62and the plurality of second mold layers52. The bit plug85may extend through the eighth insulating layer56such that the bit plug85contacts the bit pad78. The tunnel insulating layer71may include an insulating layer such as silicon oxide. The charge storage layer72may include an insulating layer such as silicon nitride. The blocking layer73may include an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics (for example, metal oxide such as HfO, AlO, or a combination thereof, or metal silicate such as HfSiO), or a combination thereof. The channel layer76may include a semiconductor layer made of polysilicon, amorphous silicon, monocrystalline silicon, or a combination thereof. The core pattern77may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, polysilicon, or a combination thereof. The bit pad78may include a conductive layer made of metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. Referring toFIG.12, the channel structure70may extend through the plurality of second mold layers52, the N-th conductive layer62N, and the N−1-th conductive layer62N−1. Referring toFIG.13, the connecting electrode layer45G may be disposed between the source line41and the supporter49. The first mold layer51may be disposed on the supporter49. The channel structure70may extend into the source line41while extending through the first mold layer51, the supporter49, and the connecting electrode layer45G. The connecting electrode layer45G may extend through a side surface of the information storage pattern75such that the connecting electrode layer45G contacts a side surface of the channel layer76. A lowermost end of the channel structure70may be disposed at a higher level than a lower surface of the source line41. The channel layer76may be electrically connected to the source line41via the connecting electrode layer45G. FIGS.14to16are sectional views explaining semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.14, the semiconductor devices according to the exemplary embodiments of the disclosure may include a substrate21, an element isolation layer23, a plurality of impurity regions25, a plurality of transistors27, a first insulating layer29, a plurality of peripheral circuit wirings31, a second insulating layer33, a third insulating layer35, a source line41, a fourth insulating layer43, a connecting electrode layer45G, a fifth insulating layer47, a sixth insulating layer48, a supporter49, a seventh insulating layer55, an eighth insulating layer56, a ninth insulating layer57, a tenth insulating layer58, a stack structure68, a plurality of channel structures70, a plurality of dummy pillars81, a plurality of word line isolation patterns82, a plurality of cell contact plugs83, a through electrode84, a plurality of bit plugs85, a plurality of first intermediate plugs86, a second intermediate plug87, and a plurality of bit lines89. In an extension area EXT, the supporter49may be formed at a lower level than in a cell area CA. In the extension area EXT, a lower surface of the supporter49may contact an upper surface of the source line41. In the extension area EXT, the sixth insulating layer48may extend on the supporter49. The plurality of dummy pillars81may extend into the source line41while extending through the eighth insulating layer56, the stack structure68, the sixth insulating layer48and the supporter49. Each of the plurality of dummy pillars81may include an inactive pillar81P, and a stud81S formed in the supporter49and the source line41. Referring toFIG.15, the semiconductor devices according to the exemplary embodiments of the disclosure may include a substrate21, an element isolation layer23, a plurality of impurity regions25, a plurality of transistors27, a first insulating layer29, a plurality of peripheral circuit wirings31, a second insulating layer33, a third insulating layer35, a source line41, a fourth insulating layer43, a connecting electrode layer45G, a fifth insulating layer47, a sixth insulating layer48, a supporter49, a seventh insulating layer55, an eighth insulating layer56, a ninth insulating layer57, a tenth insulating layer58, a stack structure68, a plurality of channel structures70, a plurality of dummy pillars81, a plurality of word line isolation patterns82, a plurality of cell contact plugs83, a through electrode84, a plurality of bit plugs85, a plurality of first intermediate plugs86, a second intermediate plug87, and a plurality of bit lines89. The plurality of dummy pillars81may be formed to extend into the source line41while extending through the stack structure68, the supporter49and the connecting mold layer45M. Each of the plurality of dummy pillars81may include an inactive pillar81P extending through the stack structure68while having a greater vertical height than a horizontal width, and a stud81S formed in the supporter49, the connecting mold layer45M and the source line41. Upper surfaces of the stud81S, the supporter49and the sixth insulating layer48may be substantially coplanar as each other. The inactive pillar81P may be formed on the stud81S. A lower surface of the inactive pillar81P may contact the upper surface of the stud81S. Referring toFIG.16, the semiconductor devices according to the exemplary embodiments of the disclosure may include a substrate21, an element isolation layer23, a plurality of impurity regions25, a plurality of transistors27, a first insulating layer29, a plurality of peripheral circuit wirings31, a plurality of first bonding structures31P, a third insulating layer35, a source line41, a fourth insulating layer43, a connecting electrode layer45G, a connecting mold layer45M, a fifth insulating layer47, a sixth insulating layer48, a supporter49, a seventh insulating layer55, an eighth insulating layer56, a ninth insulating layer57, a tenth insulating layer58, an eleventh insulating layer59, a stack structure68, a plurality of channel structures70, a plurality of dummy pillars81, a plurality of word line isolation patterns82, a plurality of cell contact plugs83, a through electrode84, a plurality of bit plugs85, a plurality of first intermediate plugs86, a second intermediate plug87, a plurality of bit lines89, a plurality of intermediate pads90, a twelfth insulating layer91, a plurality of bonding structures92, a first outer pad93, a thirteenth insulating layer95, and a second outer pad97. The plurality of first bonding structures31P may be formed in the first insulating layer29. Each of the plurality of first bonding structures31P may be connected to a corresponding one of the plurality of peripheral circuit wirings31. Upper surfaces of the plurality of first bonding structures31P and the first insulating layer29may be substantially coplanar as each other. The plurality of second bonding structures92may be formed in the twelfth insulating layer91. The twelfth insulating layer91and the plurality of second bonding structures92may be bonded to upper surfaces of the first insulating layer29and the plurality of first bonding structures31P. The plurality of second bonding structures92may be bonded to the plurality of first bonding structures31P in a wafer bonding manner. Each of the plurality of first bonding structures31P and the plurality of second bonding structures92may include or may be formed of, for example, copper (Cu). Each of the first insulating layer29and the twelfth insulating layer91may include or may be formed of, for example, silicon oxide. The eleventh insulating layer59, the plurality of bit lines89and the plurality of intermediate pads90may be disposed on the twelfth insulating layer91and the plurality of second bonding structures92. Each of the plurality of bit lines89may be connected to a corresponding one of the plurality of second bonding structures92. Some of the plurality of intermediate pads90may be connected to the plurality of second bonding structures92and the plurality of first intermediate plugs86, and some of the plurality of intermediate pads90may be connected to the plurality of second bonding structures92and the second intermediate plug87. The first outer pad93may be disposed on the third insulating layer35. The first outer pad93may be connected to the through electrode84. The thirteenth insulating layer95may cover a back surface of the substrate21. The second outer pad97may extend through the thirteenth insulating layer95and the substrate21such that the second outer pad97is connected to the plurality of peripheral circuit wirings31. A selected one of the first outer pad93and the second outer pad97may be omitted. FIGS.17,19,21,22and34,FIGS.37to40, andFIGS.43and46are sectional views explaining formation methods of semiconductor devices according to exemplary embodiments of the disclosure.FIG.18is an enlarged view showing a portion12ofFIG.17.FIG.20is an enlarged view showing a portion12ofFIG.19.FIGS.23to33are enlarged views showing a portion12ofFIG.22.FIGS.35and36are enlarged views showing a portion12ofFIG.34.FIGS.41and42are enlarged views showing a portion12ofFIG.40.FIGS.44and45are enlarged views showing a portion12ofFIG.43. Referring toFIGS.17and18, the semiconductor formation methods according to the exemplary embodiments of the disclosure may include forming an element isolation layer23, a plurality of impurity regions25, a plurality of transistors27, a first insulating layer29, and a plurality of peripheral circuit wirings31on a substrate21. A second insulating layer33may be formed on the first insulating layer29and the plurality of peripheral circuit wirings31. A third insulating layer35may be formed on the second insulating layer33. A source line41and a fourth insulating layer43may be formed on the third insulating layer35. A connecting mold layer45M and a fifth insulating layer47may be formed on the source line41and the fourth insulating layer43. A supporter49and a sixth insulating layer48may be formed on the connecting mold layer45M and the fifth insulating layer47. A preliminary stack structure68T and a seventh insulating layer55may be formed on the supporter49and the sixth insulating layer48. The preliminary stack structure68T may include a plurality of mold layers51and52and a plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T, which are alternately stacked on the substrate21. The plurality of mold layers51and52may include a plurality of first mold layers51and a plurality of second mold layers52. The plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T may include a plurality of first sacrificial layers61S and a plurality of second sacrificial layers62N−2T,62N−1T,62NT,62N+1T and62T. Each of the plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T may include a sacrificial electrode GET and a sacrificial pad CPT. The plurality of first mold layers51and the plurality of first sacrificial layers61S may constitute a first preliminary stack structure66T. The plurality of second mold layers52and the plurality of second sacrificial layers62N−2T,62N−1T,62NT,62N+1T and62T may constitute a second preliminary stack structure67T. A plurality of channel structures70, which extend into the source line41while extending through the preliminary stack structure68T, the supporter49and the connecting mold layer45M, may be formed. An eighth insulating layer56may be formed on the preliminary stack structure68T, the plurality of channel structures70and the seventh insulating layer55. The plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T may include a material having etch selectivity with respect to the plurality of mold layers51and52. The plurality of mold layers51and52may include or may be formed of silicon oxide, and the plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T may include or may be formed of silicon nitride. Referring toFIGS.19and20, a through electrode84, which contacts a corresponding one of the plurality of peripheral circuit wirings31while extending through the eighth insulating layer56, the seventh insulating layer55, the sixth insulating layer48, the fifth insulating layer47, the fourth insulating layer43, the third insulating layer35and the second insulating layer33, may be formed. A plurality dummy channel holes81H, which extend into the source line41while extending through the eighth insulating layer56, the seventh insulating layer55, the preliminary stack structure68T, the supporter49and the connecting mold layer45M, may be formed. Referring toFIG.21, a stud81S may be formed in lower regions of the plurality of dummy channel holes81H. Formation of the stud81S may include a thermal oxidation process or a chemical vapor deposition process. Referring toFIGS.22and23, a plurality of undercut regions E1G1, E2G2, and E3G3may be formed by expanding insides of the plurality of dummy channel holes81H. Formation of the plurality of undercut regions E1G1, E2G2, and E3G3may include an isotropic etching process. The plurality of undercut regions E1G1, E2G2, and E3G3may include a first undercut region E1G1, a second undercut region E2G2, and a third undercut region E3G3. Sidewalls of the plurality of undercut regions E1G1, E2G2, and E3G3may have a round shape (e.g., a convex sidewall). Referring toFIG.24, the sidewalls of the plurality of undercut regions E1G1, E2G2, and E3G3may have various shapes. Referring toFIG.25, a first sacrificial liner SL1may be formed on inner walls of the plurality of dummy channel holes81H and the plurality of undercut regions E1G1, E2G2, and E3G3. For example, the first sacrificial liner SL1may include or may be formed of silicon nitride or silicon oxynitride. Referring toFIG.26, the first sacrificial liner SL1may conformally cover the inner walls of the plurality of dummy channel holes81H and the plurality of undercut regions E1G1, E2G2, and E3G3. Referring toFIG.27, a second sacrificial liner SL2may be formed on the inner walls of the plurality of dummy channel holes81H and the plurality of undercut regions E1G1, E2G2, and E3G3. The second sacrificial liner SL2may cover the first sacrificial liner SL1. The second sacrificial liner SL2may include a material having etch selectivity with respect to the first sacrificial liner SL1. For example, the second sacrificial liner SL2may include or may be formed of polysilicon. The second sacrificial liner SL2may conformally cover the inner wall of the first undercut region E1G1. The second sacrificial liner SL2may completely fill insides of the second undercut region E2G2and the third undercut region E3G3. Referring toFIG.28, the first sacrificial liner SL1may be exposed by partially removing the second sacrificial liner SL2. The first sacrificial liner SL1may be exposed on the inner wall of the first undercut region E1G1. The second sacrificial liner SL2may remain in the insides of the second undercut region E2G2and the third undercut region E3G3. Referring toFIG.29, a third sacrificial liner SL3may be formed in the dummy channel hole81H. The third sacrificial liner SL3may completely fill the inside of the first undercut region E1G1. The third sacrificial liner SL3may include substantially the same material as the first sacrificial liner SL1and/or the plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T. For example, the third sacrificial liner SL3may include or may be formed of silicon nitride or silicon oxynitride. Referring toFIG.30, inner walls of the dummy channel hole81H may be exposed by partially removing the third sacrificial liner SL3. The third sacrificial liner SL3may remain in the inside of the first undercut region E1G1. During partial removal of the third sacrificial liner SL3, the first sacrificial liner SL1may also be partially removed. The first sacrificial liner SL1may remain in the insides of the first undercut region E1G1, the second undercut region E2G2, and the third undercut region E3G3. Referring toFIG.31, the first sacrificial liner SL1may be exposed by removing the second sacrificial liner SL2remaining in the insides of the second undercut region E2G2and the third undercut region E3G3. Referring toFIG.32, the first sacrificial liner SL1may be partially removed. The first sacrificial liner SL1and the third sacrificial liner SL3may locally remain in the inside of the first undercut region ELG1. Referring toFIG.33, side surfaces of the first undercut region E1G1, the second undercut region E2G2and the third undercut region E3G3may have various profiles. Referring toFIGS.34and35, a plurality of dummy pillars81may be formed in the plurality of dummy channel holes81H. Each of the plurality of dummy pillars81may include an inactive pillar81P, a first extension81E1, a second extension81E2, a third extension81E3, and the stud81S. The first extension82E1may be formed in the first undercut region E1G1, the second extension81E2may be formed in the second undercut region E2G2, and the third extension81E3may be formed in the third undercut region E3G3. Referring toFIG.36, side surfaces of the first extension81E1, the second extension81E2, and the third extension81E3may have various profiles. Referring toFIG.37, a plurality of isolation trenches82T, which extend through the eighth insulating layer56, the preliminary stack structure68T and the supporter49, may be formed. The connecting mold layer45M may be exposed at bottoms of the plurality of isolation trenches82T. Referring toFIG.38, a plurality of isolation spacers82S may be formed at sidewalls of the plurality of isolation trenches82T. Formation of the plurality of isolation spacers82S may include a thin film formation process and an anisotropic etching process. For example, the plurality of isolation spacers82S may include or may be formed of a polysilicon layer. A lower gap region45UC may be formed by partially removing the connecting mold layer45M. During formation of the lower gap region45UC, side surfaces of the information storage pattern (“75” inFIG.13) may be partially removed. Side surfaces of the channel layer76may be exposed in the lower gap region45UC. Referring toFIG.39, a connecting electrode layer45G may be formed in the lower gap region45UC. For example, the connecting electrode layer45G may include or may be formed of a polysilicon layer. Side surfaces of the preliminary stack structure68T may be exposed in the plurality of isolation trenches82T through removal of the plurality of isolation spacers82S. Referring toFIGS.40and41, the plurality of sacrificial layers61S,62N−2T,62N−1T,62NT,62N+1T and62T may be removed, thereby forming a plurality of gap regions61G and62G. During formation of the gap regions61G and62G, the plurality of dummy pillars81may function to prevent deformation of the plurality of mold layers51and52(for example, collapse). Side surfaces of the plurality of extensions81E1,81E2and81E3may be exposed in the plurality of gap regions61G and62G. Each of the plurality of extensions81E1,81E2and81E3may have a round side surface (e.g., a convex side surface). Referring toFIG.42, the side surfaces of the plurality of extensions81E1,81E2and81E3may have various profiles. Referring toFIGS.43and44, a plurality of horizontal conductive layers61,62N−2,62N−1,62N,62N+1, and62may be formed in the plurality of gap regions61G and62G. Each of the horizontal conductive layers61,62N−2,62N−1,62N,62N+1, and62may include a single layer or multiple layers. Each of the horizontal conductive layers61,62N−2,62N−1,62N,62N+1, and62may include a gate electrode GE and a connecting pad CP. For example, each of the horizontal conductive layers61,62N−2,62N−1,62N,62N+1 and62may include or may be formed of W, WN, Ti, TiN, Ta, TaN, Co, Ni, Ru, Pt, polysilicon, conductive carbon, or a combination thereof. Referring toFIG.45, boundary surfaces of the plurality of extensions81E1,81E2, and81E3, the gate electrode GE and the connecting pad CP may have various profiles. Referring toFIG.46, a plurality of word line isolation patterns82may be formed in the plurality of isolation trenches82T. A ninth insulating layer57may be formed on the eighth insulating layer56, the plurality of word line isolation patterns82and the plurality of dummy pillars81. A plurality of cell contact plugs83, which extend through the ninth insulating layer57, the eighth insulating layer56and the seventh insulating layer55and contact the connecting pad CP, may be formed. Each of the plurality of cell contact plugs83may include a single layer or multiple layers. For example, each of the plurality of cell contact plugs83may include or may be formed of W, WN, Ti, TiN, Ta, TaN, Co, Ni, Ru, Pt, polysilicon, conductive carbon, or a combination thereof. Again referring toFIGS.1to4, a tenth insulating layer58, a plurality of bit plugs85, a plurality of first intermediate plugs86, a second intermediate plug87and a plurality of bit lines89may be formed. FIGS.47to50are sectional views explaining formation methods of semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.47, a plurality of undercut regions E1G1, E2G2, and E3G3may be formed by selectively expanding an inside of a dummy channel hole81H through a method similar to the method described with reference toFIGS.17to23. A second sacrificial liner SL2may be formed on inner walls of the dummy channel hole81H and the plurality of undercut regions E1G1, E2G2, and E3G3. For example, the second sacrificial liner SL2may include or may be formed of silicon oxide or silicon nitride. Referring toFIG.48, the second sacrificial liner SL2may be partially removed, thereby recovering the first undercut region E1G1. The second sacrificial liner SL2may remain in the insides of the second undercut region E2G2and the third undercut region E3G3. For example, the second sacrificial liner SL2may be partially removed such that the second sacrificial liner SL2formed in the undercut region E1G1may be completely removed, and the second sacrificial liner SL2formed in the insides of the second undercut region E2G2and the third undercut region E3G3may remain. Referring toFIG.49, a third sacrificial liner SL3may be formed in the first undercut region E1G1. The first undercut region E1G1may be reduced by the third sacrificial liner SL3. The reduced first undercut region E1G1may communicate with the dummy channel hole81H. For example, the reduced first undercut region E1G1may be connected to the dummy channel hole81H. Referring toFIG.50, a dummy pillar81may be formed. The dummy pillar81may include an inactive pillar81P, a first extension81E1, a second extension81E2, and a third extension81E3. The first extension81E1may be in continuity with a side surface of the inactive pillar81P. The first extension81E1may include substantially the same material as the inactive pillar81P. Each of the second extension81E2and the third extension81E3may contact a side surface of the inactive pillar81P. Each of the second extension81E2and the third extension81E3may include the second sacrificial liner SL2. Semiconductor devices may be formed through a method similar to the method described with reference toFIGS.37to46. FIGS.51to54are sectional views explaining formation methods of semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.51, a plurality of undercut regions E1G1, E2G2, and E3G3may be formed by selectively expanding an inside of a dummy channel hole81H through a method similar to the method described with reference toFIGS.17to23. A second sacrificial liner SL2may be formed on inner walls of the dummy channel hole81H and the plurality of undercut regions E1G1, E2G2, and E3G3. The second sacrificial liner SL2may include or may be formed of polysilicon. The second sacrificial liner SL2may fill the second and third undercut regions E2G2, and E3G3, and may conformally cover the inner wall of the first undercut region E1G1without completely filling the first undercut region E1G1. Referring toFIG.52, the second sacrificial liner SL2may be partially removed, thereby recovering the first undercut region E1G1. The second sacrificial liner SL2may remain in the insides of the second undercut region E2G2and the third undercut region E3G3. For example, the second sacrificial liner SL2may be partially removed such that the second sacrificial liner SL2formed in the undercut region E1G1may be completely removed, and the second sacrificial liner SL2formed in the insides of the second undercut region E2G2and the third undercut region E3G3may remain. Referring toFIG.53, a third sacrificial liner SL3may be formed in the first undercut region E1G1. The first undercut region E1G1may be reduced by the third sacrificial liner SL3. The reduced first undercut region E1G1may communicate with the dummy channel hole81H. For example, the reduced first undercut region E1G1may be connected to the dummy channel hole81H. Referring toFIG.54, the second sacrificial liner SL2may be removed, thereby recovering the second undercut region E2G2and the third undercut region E3G3. For example, the second sacrificial liner SL2formed in the second undercut region E2G2and the third undercut region E3G3may be completely removed. Semiconductor devices may be formed through a method similar to the method described with reference toFIGS.34to46. FIGS.55and56are sectional views explaining formation methods of semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.55, etching lag ions may be implanted in a sacrificial pad CPT using an ion implantation process. For example, the etching lag ions may include or may be B, BF, BF2, or a combination thereof. Referring toFIG.56, a plurality of undercut regions E1G1, E2G2, and E3G3may be formed by selectively expanding an inside of a dummy channel hole81H. Formation of the plurality of undercut regions E1G1, E2G2, and E3G3may include an isotropic etching process. The etching rate of the sacrificial pad CPT may be lower than the etching rate of a sacrificial electrode GET due to implantation of the etching lag ions. The horizontal width of the first undercut region E1G1may be smaller than the horizontal width of the second undercut region E2G2or the third undercut region E3G3. Semiconductor devices may be formed through a method similar to the method described with reference toFIGS.34to46. FIGS.57and58are sectional views explaining formation methods of semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.57, etching lag ions may be implanted in a sacrificial pad CPT using an ion implantation process in accordance with a method similar to the method described with reference toFIG.55. For example, the etching lag ions may include or may be B, BF, BF2, or a combination thereof. A plurality of extensions81E1,81E2and81E3may be formed at sidewalls of a dummy channel hole81H using an oxidation process. The oxidation rate of the sacrificial pad CPT may be lower than the oxidation rate of a sacrificial electrode GET due to implantation of the etching lag ions. The horizontal width of the first extension81E1may be smaller than the horizontal width of the second extension81E2or the third extension81E3. The plurality of extensions81E1,81E2and81E3may include silicon oxynitride, silicon oxide, SiBON, SiBO, or a combination thereof. The first extension81E1may include a material different from those of the second extension81E2and the third extension81E3. The first extension81E1may include a material layer having a composition different from those of the second extension81E2and the third extension81E3. The first extension81E1may include or may be formed of silicon oxynitride, silicon oxide, SiBON, SiBO, or a combination thereof, whereas the second extension81E2and the third extension81E3may include or may be formed of silicon oxynitride, silicon oxide, or a combination thereof. Referring toFIG.58, an inactive pillar81P may be formed in the dummy channel hole81H. Semiconductor devices may be formed through a method similar to the method described with reference toFIGS.37to46. FIG.59is a view schematically showing an electronic system including semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.59, an electronic system1000may include a semiconductor device1100, and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one semiconductor device1100or a plurality of semiconductor devices1100, or an electronic device including a storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device or a communication device which includes one semiconductor device1100or a plurality of semiconductor devices1100. The semiconductor device1100may be a non-volatile memory device. For example, the semiconductor device1100may include a semiconductor device described with reference toFIGS.1to58. The semiconductor device1100may include a first structure1110F, and a second structure1100S on the first structure1110F. In exemplary embodiments, the first structure1110F may be disposed at one side of the second structure1100S. The first structure1110F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120and a logic circuit1130. The second structure1100S may be a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL. In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be diversely varied in accordance with embodiments. In exemplary embodiments, the upper transistors UT1and UT2may include a string selection transistor, whereas the lower transistors LT1and LT2may include a ground selection transistor. The first and second gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively. The first and second gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively. In exemplary embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2which are connected in series. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2which are connected in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used in an erase operation for deleting data stored in the memory cell transistors MCT using a gate-induced drain leakage (GIDL) phenomenon. The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110via first connecting lines1115extending from the first structure1110F to the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120via second connecting lines1125extending from the first structure1110F to the second structure1100S. In the first structure1110F, the decoder circuit1110and the page buffer1120may perform a control operation for a selection memory cell transistor of at least one of the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The electronic system1000may communicate with the controller1200through input/output pads1101electrically connected to the logic circuit1130. The input/output pads1101may be electrically connected to the logic circuit1130via an input/output connecting line1135extending from the first structure1110F to the second structure1100S. The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In accordance with embodiments, the electronic system1000may include a plurality of semiconductor devices1100. The controller1200may control the plurality of semiconductor devices1100. The processor1210may control overall operations of the electronic system1000including the controller1200. The processor1210may operate in accordance with predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221for processing communication with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, data to be read out from the memory cell transistors MCT of the semiconductor device1100, etc. may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the electronic system1000and an external host. Upon receiving a control command from an external host via the host interface1230, the processor1210may control the semiconductor device1100in response to the control command. FIG.60is a perspective view schematically showing an electronic system including semiconductor devices according to exemplary embodiments of the disclosure. Referring toFIG.60, an electronic system2000according to exemplary embodiments of the disclosure may include a main substrate2001, a controller2002mounted on the main substrate2001, at least one semiconductor package2003, and a dynamic random access memory (DRAM)2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by wiring patterns2005formed on the main substrate2001. The main substrate2001may include a connector2006including a plurality of pins to be coupled to an external host. The number and arrangement of the plurality of pins in the connector2006may be varied in accordance with a communication interface between the electronic system2000and the external host. In exemplary embodiments, the electronic system2000may communicate with the external host in accordance with any one of interfaces such as a universal serial bus (USB), peripheral component interconnect express (PCI-Express), serial advanced technology attachment (SATA), M-PHY for universal flash storage (UFS), etc. In exemplary embodiments, the electronic system2000may operate by power supplied from the external host. The electronic system2000may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller2002and the semiconductor package2003. The controller2002may write data in the semiconductor package2003or may read out data from the semiconductor package2003. The controller2002may also enhance an operation speed of the electronic system2000. The DRAM2004may be a buffer memory for reducing a speed difference between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004, which is included in the electronic system2000, may also operate as a kind of cache memory. The DRAM2004may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the controller2002may further include a DRAM controller for controlling the DRAM2004, in addition to the NAND controller for controlling the semiconductor package2003. The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, bonding layers2300respectively disposed at lower surfaces of the semiconductor chips2200, a connecting structure2400for electrically connecting the semiconductor chips2200and the package substrate2100with each other, and a molding layer2500covering the semiconductor chips2200and the connecting structure2400on the package substrate2100. The package substrate2100may be a printed circuit board including package upper pads2130. Each of the semiconductor chips2200may include input/output pads2210. The input/output pads2210may correspond to the input/output pads1101ofFIG.59. Each of the semiconductor chips2200may include gate stack structures3210and memory channel structures3220. Each of the semiconductor chips2200may include a semiconductor device described with reference toFIGS.1to58. For example, the gate stack structures3210may include the stack structure (“68” inFIG.1), and the memory channel structures3220may include the plurality of channel structures (“70” inFIG.1). In exemplary embodiments, the connecting structure2400may be bonding wires for electrically connecting the input/output pads2210and the package upper pads2130with each other, respectively. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically interconnected through wire bonding to each other, and may be electrically connected to the corresponding package upper pads2130of the package substrate2100. In accordance with embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically interconnected by a connecting structure including through-silicon vias (TSVs) in place of the bonding wire type connecting structure2400. In exemplary embodiments, the controller2002and the semiconductor chips2200may be included in one package. In an exemplary embodiment, the controller2002and the semiconductor chips2200may be mounted on a separate interpose substrate different from the main substrate2001. The controller2002and the semiconductor chips2200may be interconnected by wirings formed at the interposer substrate. FIGS.61and62are sectional views schematically showing semiconductor packages according to exemplary embodiments of the disclosure. Each ofFIGS.61and62explains an exemplary embodiment of the semiconductor package2003ofFIG.60, and conceptually shows an area of the semiconductor package2003taken along line I-I′ inFIG.60. Referring toFIG.61, in the semiconductor package2003according to the exemplary embodiments of the disclosure, the package substrate2100thereof may be a printed circuit board. The package substrate2100may include a package substrate body2120, package upper pads (“2130” inFIG.60) disposed at an upper surface of the package substrate body2120, lower pads2125disposed at a lower surface of the package substrate body2120or exposed through the lower surface of the package substrate body2120, and inner wirings2135electrically connecting the package upper pads (“2130” inFIG.60) and the lower pads2125with each other within the package substrate body2120. The package upper pads (“2130” inFIG.60) may be electrically connected to connecting structures (“2400” inFIG.60). The lower pads2125may be connected to the wiring patterns2005of the main substrate2010of the electronic system2000through conductive connectors2800, as shown inFIG.60. Each of the semiconductor chips2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral wirings3110. The second structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, memory channel structures3220extending through the gate stack structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate connecting wirings3225electrically connected to word lines (“WL” inFIG.59) of the gate stack structure3210. The first structure3100may include the plurality of impurity regions (“25” inFIG.1), the plurality of transistors (“27” inFIG.1), and the plurality of peripheral circuit wiring layers (“31” inFIG.1). The common source line3205may include the source line (“41” inFIG.1). The gate stack structure3210may include the stack structure (“68” inFIG.1). The memory channel structures3220may include the plurality of channel structures (“70” inFIG.1). The bit lines3240may include the plurality of bit lines (“89” inFIG.1). The gate connecting wirings3235may include the plurality of cell contact plugs (“83” inFIG.1). Each of the semiconductor chips2200may further include the plurality of dummy pillars81described with reference toFIGS.1to58. Each of the semiconductor chips2200may include a through wiring3245electrically connected to the peripheral wirings3110of the first structure3100while extending into the second structure3200. Each of the semiconductor chips2200may be electrically connected to the peripheral wirings3110of the first structure3100. The through wiring3245may be disposed outside the gate stack structure3210, and may be further disposed to extend through the gate stack structure3210. Each of the semiconductor chips2200may further include an input/output connecting wiring (“2210” inFIG.60) electrically connected to the peripheral wirings3110of the first structure3100. Referring toFIG.62, in a semiconductor package2003A according to the exemplary embodiments of the disclosure, each of semiconductor chips2200bthereof may include a semiconductor substrate4010, a first structure4100on the semiconductor substrate4010, and a second structure4200bonded to the first structure4100in a wafer bonding manner on the first structure4100. The first structure4100may include a peripheral circuit region including a peripheral wiring4110and first bonding structures4150. The second structure4200may include a common source line4205, a gate stack structure4210between the common source line4205and the first structure4100, memory channel structures4220extending through the gate stack structure4210, and second bonding structures4250electrically connected to the memory channel structures4220and word lines of the gate stack structure4210(“WL” inFIG.59), respectively. For example, the second bonding structures4250may be electrically connected to the memory channel structures4220and the word lines (“WL” inFIG.59) through bit lines4240electrically connected to the memory channel structures4220and gate connecting wirings4235electrically connected to the word lines (“WL” inFIG.59), respectively. The first bonding structures4150of the first structure4100and the second bonding structures4250of the second structure4200may be bonded to each other while contacting each other. Bonding portions of the first bonding structures4150and the second bonding structures4250may be made of, for example, copper (Cu). The first structure4100may include the plurality of impurity regions (“25” inFIG.16), the plurality of transistors (“27” inFIG.16), and the plurality of peripheral circuit wiring layers (“31” inFIG.16). The common source line4205may include the source line (“41” inFIG.16). The gate stack structure4210may include the stack structure (“68” inFIG.16). The memory channel structures4220may include the plurality of channel structures (“70” inFIG.16). The bit lines4240may include the plurality of bit lines (“89” inFIG.16). The gate connecting wirings4235may include the plurality of cell contact plugs (“83” inFIG.16). Each of the semiconductor chips2200bmay further include the plurality of dummy pillars81described with reference toFIGS.1to58. Each of the semiconductor chips2200bmay further include an input/output pad (“2210” inFIG.60) electrically connected to the peripheral wirings4110of the first structure4100. The semiconductor chips2200ofFIG.61and the semiconductor chips2200bofFIG.62may be electrically connected by bonding wire type connecting structures (“2400” inFIG.60). Semiconductor chips in one semiconductor package such as the semiconductor chips2200ofFIG.61and the semiconductor chips2200bofFIG.62may be electrically connected by a connecting structure including a through-silicon via (TSV). In accordance with the exemplary embodiments of the disclosure, a dummy pillar extending into a stack structure is provided. The dummy pillar includes an inactive pillar extending through a plurality of horizontal conductive layers, and at least one extension protruding from a side surface of the inactive pillar. The at least one extension is aligned with the plurality of horizontal conductive layers. The dummy pillar may function to prevent deformation of the stack structure. Semiconductor devices capable of preventing deformation of a multilayer structure and an electronic system including the semiconductor devices may be realized. While the embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various transitions may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation. | 72,796 |
11943917 | DETAILED DESCRIPTION A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other. First Embodiment First, a first embodiment will be described. FIG.1is a perspective view showing a semiconductor memory device according to the embodiment. FIG.2is a plan view showing the semiconductor memory device according to the embodiment. FIG.3is a cross-sectional view showing the semiconductor memory device according to the embodiment. FIG.4is a schematic circuit diagram showing the semiconductor memory device according to the embodiment. FIG.5AandFIG.5Bare partially enlarged cross-sectional views showing the semiconductor memory device according to the embodiment. BecauseFIG.1toFIG.4are drawings showing the general concept of the device, only some of the members are schematically drawn; and the other members are not illustrated. InFIG.4, conductive members23cof upper selection gate interconnect layers23described below are shown by broken lines; and comb-shaped members22cof word line interconnect layers22are shown by solid lines. First, a schematic configuration of the semiconductor memory device according to the embodiment will be described. As shown inFIG.1toFIG.4, a silicon substrate10is provided in the semiconductor memory device1according to the embodiment. Hereinbelow, an XYZ orthogonal coordinate system is employed in the specification for convenience of description. Two mutually-orthogonal directions parallel to the upper surface of the silicon substrate10are taken as an “X-direction” and a “Y-direction;” and a direction perpendicular to the upper surface is taken as a “Z-direction.” A memory region Rm, an interconnect draw-out region Rd, and a peripheral circuit region Rc are set in the semiconductor memory device1. Many memory cells are arranged three-dimensionally in the memory region Rm. The interconnect draw-out regions Rd are disposed on the two X-direction sides of the memory region Rm. The peripheral circuit regions Rc are disposed at the peripheries of the memory region Rm and the interconnect draw-out regions Rd. The peripheral circuit is formed in the peripheral circuit region Rc; and the memory cells are operated by inputting and outputting signals to and from the memory cells. The interconnect draw-out region Rd is a region for drawing out the interconnects extending in the X-direction from the memory region Rm and for connecting the interconnects to the peripheral circuit. For example, a stacked body20is configured by stacking, to be separated from each other with inter-layer insulating films31interposed, one layer of a lower selection gate interconnect layer21, multiple layers of the word line interconnect layers22, and one or more layers, e.g., two layers, of the upper selection gate interconnect layers23on the silicon substrate10. All of the layers of the stacked body20are disposed in the memory region Rm. In the interconnect draw-out region Rd, the configuration of the stacked body20is a staircase configuration that is drawn out more to the outer side toward the lower levels. In other words, the word line interconnect layers22and the upper selection gate interconnect layers23are not disposed in the regions directly above the two X-direction end portions of the lower selection gate interconnect layer21; the word line interconnect layers22and the upper selection gate interconnect layers23of the levels above one word line interconnect layer22are not disposed in the regions directly above the two X-direction end portions of the one word line interconnect layer22; and the upper selection gate interconnect layers23are not disposed in the regions directly above the two X-direction end portions of the word line interconnect layer22of the uppermost level. A memory trench MT that has a snake-like configuration extending in the Y-direction as an entirety while extending back and forth in the X-direction is formed in the stacked body20. Namely, MTx that extends in the X-direction and MTy that extends in the Y-direction are linked alternately in the memory trench MT. The memory trench MT pierces the stacked body20in the Z-direction and reaches the silicon substrate10. Multiple silicon pillars26are arranged in one column along the X-direction inside the portion MTx extending in the X-direction in the memory trench MT. The configuration of each of the silicon pillars26is a quadrilateral column extending in the Z-direction. The lower end of the silicon pillar26is connected to the silicon substrate10. The silicon pillars26are arranged in a matrix configuration along the X-direction and the Y-direction in the entire memory region Rm. An insulating member32that is made of, for example, silicon oxide is provided between the silicon pillars26inside the memory trench MT. The silicon pillars26are not disposed inside the portion MTy extending in the Y-direction in the memory trench MT; and the portion MTy is filled with the insulating member32. Further, a slit ST that has a rectangular configuration extending in the X-direction also is formed in the stacked body20. The slit ST pierces the stacked body20in the Z-direction and reaches the silicon substrate10. An insulating member33that is made of, for example, silicon oxide is filled into the slit ST. One end portion of the slit ST communicates with the portion MTy of the memory trench MT. Also, the greater part of the slit ST including the one end portion is surrounded in three directions by the memory trench MT having the snake-like configuration, but is separated from the portion MTx. Thereby, the portion of the upper selection gate interconnect layer23interposed between the memory trench MT and the slit ST is an upper selection gate line23aextending in the X-direction. Similarly also for the word line interconnect layer22and the lower selection gate interconnect layer21, the portions of the word line interconnect layer22and the lower selection gate interconnect layer21interposed between the memory trench MT and the slit ST respectively are a word line22aand a lower selection gate line21a. Therefore, the lower selection gate line21a, the word line22a, and the upper selection gate line23aare disposed on the two Y-direction sides of the silicon pillar26. The other end portion of the slit ST extends in the X-direction from the memory trench MT having the snake-like configuration and is terminated where the slit ST divides the upper selection gate interconnect layer23. Thereby, the upper selection gate interconnect layer23is divided by the memory trench MT and the slit ST into the conductive members23chaving the C-shaped configurations when viewed from the Z-direction. The two upper selection gate lines23athat extend in the X-direction and a link member23bthat connects the end portions of the two upper selection gate lines23ato each other are provided as one body in each of the conductive members23c. The conductive members23cthat have the C-shaped configurations are disposed in a meshing configuration from two sides in the X-direction. In other words, one of the upper selection gate lines23aof each of another two conductive members23cdisposed on the opposite side in the X-direction of one conductive member23care disposed between the two upper selection gate lines23aof the one conductive member23c. On the other hand, although the slit ST divides the word line interconnect layers22and the lower selection gate interconnect layer21at the boundary of the block, the slit ST does not divide the word line interconnect layers22and the lower selection gate interconnect layer21inside the block. Therefore, inside each block, the word line interconnect layer22is divided into two comb-shaped members22cby the memory trench MT and the slit ST. In each of the comb-shaped members22c, one link member22bthat extends in the Y-direction is provided; and the multiple word lines22athat extend in the X-direction extend from the link member22b. The two comb-shaped members22care disposed in a meshing configuration opposing each other from the two sides in the X-direction; and the two word lines22aof one comb-shaped member22cand the two word lines22aof another comb-shaped member22care arranged alternately along the Y-direction. The slit ST is disposed between the two word lines22aof one comb-shaped member22c; and the memory trench MT is disposed between the two word lines22abelonging to the two comb-shaped members22c. This is similar also for the lower selection gate interconnect layer21. In other words, the lower selection gate interconnect layer21is divided into two comb-shaped members21c; and in each of the comb-shaped members21c, one link member21bthat extends in the Y-direction and many lower selection gate lines21athat extend in the X-direction are provided. The memory region Rm will now be described. Bit line plugs27are provided on the silicon pillars26; and multiple bit lines28that extend in the Y-direction are provided on the bit line plugs27. Two bit lines28are disposed on the silicon pillars26arranged in one column along the Y-direction; and the bit lines28are connected to every other silicon pillar26via the bit line plugs27. Thereby, the two silicon pillars26that are adjacent to each other in the Y-direction are connected to mutually-different bit lines28. For example, the bit lines28are connected to sense amplifiers of the peripheral circuit. An inter-layer insulating film30that is made of, for example, silicon oxide is provided on the stacked body20; and the bit line plugs27and the bit lines28are buried inside the inter-layer insulating film30. InFIG.1, the bit line plugs27and the bit lines28are illustrated by straight lines for convenience of illustration. Also, the bit line plugs27and the bit lines28are not illustrated inFIG.2. A floating gate electrode film29is provided between each of the silicon pillars26and each of the word lines22a. The floating gate electrode film29is a conductive member that stores charge and is formed of, for example, polysilicon (Si). As shown inFIG.5AandFIG.5B, a tunneling insulating film36is provided between the silicon pillar26and the floating gate electrode film29. The tunneling insulating film36is a film in which a tunneling current flows when a prescribed voltage within the range of the drive voltage of the semiconductor memory device1is applied and is, for example, a single-layer silicon oxide film, or a three-layer film made of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Also, a high dielectric constant layer37athat is made of a high dielectric constant material such as silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), etc., is provided on the side surface of the floating gate electrode film29on the word line22aside, on the upper surface of the floating gate electrode film29, and on the lower surface of the floating gate electrode film29. The high dielectric constant layer37amay contain a metal such as ruthenium (Ru), titanium (Ti), etc. The configuration of the high dielectric constant layer37ain the YZ cross section is a C-shaped configuration surrounding the floating gate electrode film29. On the other hand, a high dielectric constant layer37cthat is made of a high dielectric constant material is formed on the side surface of the word line22aon the floating gate electrode film29side, on the upper surface of the word line22a, and on the lower surface of the word line22a; and a silicon oxide layer37bthat is made of silicon oxide (SiO2) is formed on the high dielectric constant layer37c. The configurations of the silicon oxide layer37band the high dielectric constant layer37cin the YZ cross section are C-shaped configurations surrounding the word line22a. Thereby, the high dielectric constant layer37a, the silicon oxide layer37b, and the high dielectric constant layer37care stacked in this order between the floating gate electrode film29and the word line22a. A blocking insulating film37includes the high dielectric constant layer37a, the silicon oxide layer37b, and the high dielectric constant layer37c. The blocking insulating film37is a film in which a current substantially does not flow even when a voltage within the range of the drive voltage of the semiconductor memory device1is applied. In the semiconductor memory device1, a transistor that includes one floating gate electrode film29is formed at each crossing portion between the silicon pillars26and the word lines22a; and the transistor functions as a memory cell. Also, a NAND string in which the multiple memory cells are connected in series is connected between the bit line28and the silicon substrate10. The interconnect draw-out region Rd will now be described. As shown inFIG.2, a contact41is provided on the link member23bof each of the conductive members23cof the upper selection gate interconnect layers23; and an intermediate interconnect42is provided on the contact41. When viewed from the Z-direction, the intermediate interconnect42is disposed in the interior of the link member23bevery link member23b. A via43is provided on the intermediate interconnect42; and an upper layer interconnect44that extends in the X-direction is provided on the via43. Thereby, each of the conductive members23cis connected to the upper layer interconnect44via the contact41, the intermediate interconnect42, and the via43. A contact45is provided on the link member22bof each of the comb-shaped members22cof each of the word line interconnect layers22; an intermediate interconnect46is provided on some of the contacts45; and an upper layer interconnect47that extends in the X-direction is provided on the intermediate interconnect46. Thereby, each of the comb-shaped members22cis connected to the upper layer interconnect47via the contact45and the intermediate interconnect46. Similarly for the lower selection gate interconnect layer21as well, each of the comb-shaped members21cis connected to an upper layer interconnect (not illustrated) via a contact (not illustrated) and an intermediate interconnect (not illustrated). As described above, because the configurations of the two X-direction end portions of the stacked body20are staircase configurations, the contacts45that are connected to the word line interconnect layers22are further on the outer side, that is, on the side distal to the memory region Rm, than are the contacts41connected to the upper selection gate interconnect layers23. Among the word line interconnect layers22, the contacts45that are connected to the word line interconnect layers22are positioned more on the outer side toward the lower layers. The contact that is connected to the lower selection gate interconnect layer21is further on the outer side than are the contacts45. In other words, among the word line interconnect layers22of two layers, the distance between the contact45connected to the link member22bof the word line interconnect layer22of the upper layer and the silicon pillar26most proximal to that contact45is shorter than the distance between the contact45connected to the link member22bof the word line interconnect layer22of the lower layer and the silicon pillar26most proximal to that contact45. For example, the positional relationship between the word lines22aand the silicon pillars26and the connectional relationship between the word lines22acan be expressed as follows. This is similar for the lower selection gate line21aas well. Namely, the multiple silicon pillars26are arranged in one column along the X-direction between the (4n+1)th word line22aand the (4n+2)th word line22aand between the (4n+3)th word line22aand the (4n+4)th word line22acounting along the Y-direction, where n is an integer of 0 or more. The silicon pillars26are not disposed between the (4n+2)th word line22aand the (4n+3)th word line22a. Also, the floating gate electrode film29is disposed between the silicon pillar26and the word line22a. Also, the (4n+1)th word line22aand the (4n+4)th word line22aare connected to each other by the first link member22bextending in the Y-direction; and the (4n+2)th word line22aand the (4n+3)th word line22aare connected to each other by the second link member22bextending in the Y-direction. Therefore, a first comb-shaped member22c(a first interconnect group) that includes the (4n+1)th word line22aand the (4n+4)th word line22aand a second comb-shaped member22c(a second interconnect group) that includes the (4n+2)th word line22aand the (4n+3)th word line22aare drivable independently from each other. Accordingly, the word lines22athat are disposed on the two Y-direction sides of one silicon pillar26are drivable independently from each other. Also, for example, the connectional relationship between the upper selection gate lines23acan be expressed as follows. The (8n+1)th upper selection gate line23aand the (8n+4)th upper selection gate line23acounting along the Y-direction are connected to each other by the link member23band are included in a first C-shaped conductive member23c. The (8n+3)th upper selection gate line23aand the (8n+6)th upper selection gate line23aare connected to each other by the link member23band are included in a second C-shaped conductive member23c. The (8n+5)th upper selection gate line23aand the (8n+8)th upper selection gate line23aare connected to each other by the link member23band are included in a third C-shaped conductive member23c. The (8n+7)th upper selection gate line23aand the (8n+10)th upper selection gate line23aare connected to each other by the link member23band are included in a fourth C-shaped conductive member23c. Also, the first to fourth conductive members23care drivable independently from each other. A method for manufacturing the semiconductor memory device according to the embodiment will now be described. FIG.6toFIG.11,FIG.13toFIG.15, andFIG.17toFIG.23are perspective views showing the method for manufacturing the semiconductor memory device according to the embodiment. FIG.12is a cross-sectional view showing the method for manufacturing the semiconductor memory device according to the embodiment. FIG.16is a plan view showing the method for manufacturing the semiconductor memory device according to the embodiment. First, the silicon substrate10is prepared as shown inFIG.3. Then, as shown inFIG.6, the stacked body20is formed by alternately forming the inter-layer insulating films31made of silicon oxide and sacrificial films51made of silicon nitride using, for example, CVD (chemical vapor deposition). Then, a hard mask film52that is made of silicon oxide is formed by CVD using TEOS (Tetra Ethyl Ortho Silicate: Si(OC2H5)4) as a source material. Then, as shown inFIG.7, a carbon film53and an anti-reflection film54are formed on the hard mask film52; and a resist film is coated onto the carbon film53and the anti-reflection film54. Then, a resist pattern55is formed by patterning the resist film using lithography. An opening55athat has a snake-like configuration extending in the Y-direction as an entirety while extending back and forth in the X-direction is formed in the resist pattern55. A portion of the opening extending in the X-direction is shown inFIG.7. Then, as shown inFIG.8, the pattern of the resist pattern55is transferred to the hard mask film52by performing anisotropic etching such as RIE (Reactive Ion Etching), etc. Then, the memory trench MT is formed by removing the portion of the stacked body20disposed in the region directly under the opening55aby performing RIE using the hard mask film52as a mask. Then, deposits are removed by performing wet processing. The hard mask film52remains in this stage as well. Then, as shown inFIG.9, recesses57are formed in the side surface of the memory trench MT by recessing the sacrificial films51exposed at the side surface of the memory trench MT by performing, for example, wet etching using hot phosphoric acid via the memory trench MT. The recesses57are formed in loop configurations surrounding the memory trench MT. Also, the recesses57of multiple levels are arranged along the Z-direction. Then, a cover oxide film59(referring toFIG.12) is formed by oxidizing the sacrificial films51exposed at the back surfaces of the recesses57by performing oxidation treatment. Then, as shown inFIG.10, the high dielectric constant layer37ais formed on the inner surface of the memory trench MT by depositing a high dielectric constant material including a metal. Then, a silicon film is formed on the high dielectric constant layer37aby depositing silicon. Then, the portions of the silicon film and the high dielectric constant layer37adeposited outside the recesses57are removed and the portions of the silicon film and the high dielectric constant layer37aare caused to remain in the interiors of the recesses57by recessing the silicon film and the high dielectric constant layer37aby performing wet etching using TMY (a choline aqueous solution), isotropic etching such as CDE (chemical dry etching), etc. Thereby, the high dielectric constant layer37ais formed on the inner surfaces of the recesses57; and the floating gate electrode films29that are made of silicon are formed inside the recesses57. Then, as shown inFIG.11, the tunneling insulating film36(referring toFIG.5B) is formed by depositing silicon oxide on the inner surface of the memory trench MT using, for example, ALD (Atomic Layer Deposition: atomic layer deposition). Then, a cover silicon film is formed on the inner surface of the memory trench MT. Then, the silicon substrate (referring toFIG.3) is exposed by using RIE to remove the cover silicon film and the tunneling insulating film36deposited on the bottom surface of the memory trench MT. Then, a body silicon film is filled into the memory trench MT by depositing silicon. The body silicon film contacts the silicon substrate10. Then, heat treatment for crystallizing the silicon is performed. A silicon member58is formed of the crystallized cover silicon film and body silicon film. The silicon member58covers the stacked body20and the hard mask film52and fills the interior of the memory trench MT. FIG.12is a partial cross-sectional view showing the structure at this stage. As shown inFIG.12, the memory trench MT is formed in the stacked body20in which the inter-layer insulating films31made of silicon oxide and the sacrificial films51made of silicon nitride are stacked alternately; and the recesses57where the sacrificial films51recede are formed in the inner side surface of the memory trench MT. The cover oxide film59is formed on the back surfaces of the recesses57; and the high dielectric constant layer37ais formed on the inner surfaces of the recesses57. The floating gate electrode films29that are made of polysilicon are filled into the interiors of the recesses57. Also, the tunneling insulating film36is formed on the side surface of the memory trench MT to cover the inter-layer insulating films31and the floating gate electrode films29. Then, the silicon member58is filled into the memory trench MT. Then, as shown inFIG.13, the hard mask film52is exposed by performing etch-back of the upper surface of the silicon member58. Thereby, the silicon member58remains only inside the memory trench MT. Then, as shown inFIG.14, a hard mask film61that is made of silicon oxide is formed on the entire surface by CVD using TEOS as the source material. Then, a carbon film62and an anti-reflection film63are formed. Then, a resist pattern64is formed by forming a resist film and by patterning using lithography. Openings64ahaving a line-and-space configuration extending in the Y-direction are formed in the resist pattern64. When viewed from the Z-direction, the openings64aare formed in a region directly above the entire portion MTy of the memory trench MT extending in the Y-direction and in a region crossing the portion MTx of the memory trench MT extending in the X-direction. Then, as shown inFIG.15, the pattern of the resist pattern64is transferred to the hard mask film61by performing RIE using the resist pattern64as a mask. Then, the silicon member58and the tunneling insulating film36that are filled into the memory trench MT are selectively removed and divided in the X-direction by performing RIE using the hard mask film61and the hard mask film52as a mask. This processing is called “AA patterning.” FIG.16is a plan view showing the configuration at this stage. As shown inFIG.16, as a result of the AA patterning, the silicon member58is divided into the multiple silicon pillars26. The silicon pillars26are arranged in one column along the X-direction inside each of the portions MTx and are arranged in a matrix configuration along the X-direction and the Y-direction in the entire memory region Rm. Further, the tunneling insulating film36also is divided every silicon pillar26. The floating gate electrode film29is exposed in the space where the silicon member58is removed. Then, as shown inFIG.17, the floating gate electrode29and the high dielectric constant layer37a(referring toFIG.16) that are filled into the recesses57are selectively removed by performing wet etching or isotropic etching such as CDE, etc., via the memory trench MT. Thereby, the floating gate electrode film29and the high dielectric constant layer37aare divided every silicon pillar26. Then, as shown inFIG.18, silicon oxide is deposited on the entire surface using CVD, coating, etc. Thereby, the insulating member32is formed to fill the gap between the silicon pillars26. Then, as shown inFIG.19, the upper surfaces of the silicon pillars26and the upper surface of the hard mask film52are exposed by performing etch-back using the silicon pillars26as a stopper. Then, as shown inFIG.20, a carbon film66, an anti-reflection film67, and a resist pattern68are formed on the stacked body20and the hard mask film52. An opening68athat has a rectangular configuration having the X-direction as the longitudinal direction is multiply formed in the resist pattern68by lithography. Each of the openings68ais disposed so that an end portion in the longitudinal direction of the opening68acontacts the portion MTy of the memory trench MT extending in the Y-direction. Then, as shown inFIG.21, the slits ST that pierce the stacked body20are multiply formed by performing RIE using the resist pattern68as a mask. The insulating member32that is made of silicon oxide is exposed at the end surface of each of the slits ST communicating with the memory trench MT. The inter-layer insulating films31that are made of silicon oxide and the sacrificial films51that are made of silicon nitride are exposed at the other side surfaces. Then, as shown inFIG.22, the sacrificial films51are removed via the slit ST by performing, for example, wet etching using hot phosphoric acid using the cover oxide film59(referring toFIG.12) as an etching stopper. At this time, the insulating member32and the inter-layer insulating films31that are made of silicon oxide are substantially not etched. Thereby, recesses71are formed in the space where the sacrificial films51are removed. The cover oxide film59is exposed at the back surfaces of the recesses71. Then, the cover oxide film59is removed. Then, as shown inFIG.23,FIG.5A, andFIG.5B, the silicon oxide layer37bis formed in the slit ST and on the inner surfaces of the recesses71by, for example, depositing silicon oxide using ALD. Then, the high dielectric constant layer37cis formed on the silicon oxide layer37bby depositing a high dielectric constant material such as silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), etc. Then, a barrier metal layer is formed on the high dielectric constant layer37cby, for example, depositing titanium nitride using CVD. Then, a tungsten film is formed by, for example, depositing tungsten (W) using CVD. The tungsten film is formed to fill the entire interiors of the recesses71. Then, the portions of the tungsten film and the barrier metal layer deposited outside the recesses71are removed by, for example, RIE and caused to remain inside the recesses71. Thereby, as shown inFIG.23andFIG.1toFIG.3, the interconnect layers are formed of the barrier metal layer and the tungsten film disposed inside the recesses71. In other words, the upper selection gate interconnect layers23are formed inside the recess71of the uppermost level and the recess71of the second level from the top; the comb-shaped member21cof the lower selection gate interconnect layer21is formed inside the recess71of the lowermost level; and the comb-shaped members22cof the word line interconnect layers22are formed inside the other recesses71. Then, as shown inFIG.1toFIG.3, the insulating member33is filled into the slit ST by depositing silicon oxide and by performing CMP (chemical mechanical polishing) using the silicon pillars26as a stopper. Then, the upper selection gate interconnect layers23are divided along the Y-direction and cut into the multiple C-shaped conductive members23c. Then, the link member23bof the upper selection gate interconnect layer23, the link member22bof the word line interconnect layer22, and a link member21bof the lower selection gate interconnect layer21are exposed by patterning the two X-direction end portions of the stacked body20into the staircase configuration. Then, the inter-layer insulating film30that buries the entire stacked body20is formed by, for example, depositing silicon oxide; and the contacts41and45, the intermediate interconnects42and46, the vias43, the bit line plugs27, the upper layer interconnects44and47, and the bit lines28are formed. Thus, the semiconductor memory device1according to the embodiment is manufactured. Effects of the embodiment will now be described. In the semiconductor memory device1according to the embodiment, in the program operation of one memory cell of two memory cells sharing one silicon pillar26, misprogramming to the other memory cell of the two memory cells can be suppressed because the two word lines22ahaving the silicon pillars26interposed can be driven independently from each other. For example, for the first and second word lines22athat have the same position in the Z-direction and have one silicon pillar26interposed, electrons can be injected into the first floating gate electrode film29disposed between the first word line22aand the silicon pillar26by applying, to the first word line, a programming voltage that is positive with respect to the silicon pillar26; and data can be programmed to the first memory cell. In such a case, by applying a voltage that is lower than the programming voltage to the second word line22aor by setting the second word line22ato a floating state, and by further setting the upper selection gate of the second word line side to be OFF, the injection of the electrons into the second floating gate electrode film29can be suppressed; and misprogramming of the second memory cell can be suppressed. Thus, according to the embodiment, a semiconductor memory device can be realized in which the reliability of the operation is high. Conversely, if the same programming voltage is applied to the first and second word lines22a, the operation of the first memory cell and the operation of the second memory cell are discriminated only by the voltage applied to the upper selection gate lines23a. That is, the operation of the program/non-program for two NAND strings sharing the same silicon pillar26is controlled only by setting the upper selection gate of the NAND string to be programmed to be ON, by setting the upper selection gate of the other NAND string of the two NAND strings to be OFF, and by setting the other NAND strings to the boost state. Therefore, there are cases where the electrons that are introduced to the silicon pillar26are injected into the second floating gate electrode film29. As a result, there is a risk that misprogramming of the second memory cell may undesirably occur in the program operation of the first memory cell. Second Embodiment A second embodiment will now be described. FIG.24is a plan view showing a semiconductor memory device according to the embodiment. FIG.25is a schematic circuit diagram showing the semiconductor memory device according to the embodiment. As shown inFIG.24, the semiconductor memory device2according to the embodiment differs from the semiconductor memory device1according to the first embodiment described above (referring toFIG.2) in that the slit ST divides the portion MTy of the memory trench MT extending in the Y-direction and divides the upper selection gate interconnect layer23every upper selection gate line23a. In other words, the link member23bis not provided in the upper selection gate interconnect layer23. The slit ST does not divide the link member22bof the word line interconnect layer22and the link member21bof the lower selection gate interconnect layer21. Thereby, as shown inFIG.25, the upper selection gate lines23aare separated from each other. Therefore, in the semiconductor memory device2, the upper selection gate lines23acan be driven independently one at a time. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. Third Embodiment A third embodiment will now be described. FIG.26is a plan view showing a semiconductor memory device according to the embodiment. FIG.27is a schematic circuit diagram showing the semiconductor memory device according to the embodiment. As shown inFIG.26, the semiconductor memory device3according to the embodiment differs from the semiconductor memory device1according to the first embodiment described above (referring toFIG.2) in that the slit ST is long. Similarly to the first embodiment, an end in the longitudinal direction of the slit ST contacts the portion MTy of the memory trench MT. On the other hand, unlike the first embodiment, the slit ST extends to the outer edge of the stacked body20and divides the upper selection gate interconnect layer23, the word line interconnect layer22, and the lower selection gate interconnect layer21. Therefore, similarly to the upper selection gate interconnect layer23, the word line interconnect layer22is subdivided into multiple C-shaped conductive members22dinstead of a pair of comb-shaped members. Two word lines22aare provided for each of the conductive members22d. A via48is provided on the conductive member22d; and an upper layer interconnect49that extends in the Y-direction is provided on the via48. Then, the multiple conductive members22dare connected commonly to the upper layer interconnect49by the vias48. This is similar for the lower selection gate interconnect layer21as well. Accordingly, as shown inFIG.27, the electrical connectional relationship of the word line interconnect layer22is similar to that of the first embodiment (referring toFIG.4). However, in the embodiment, the two word lines22aof each of the conductive members22dare bundled by the link member22b; and the conductive members22dare connected to each other by the upper layer interconnect49. For example, the connectional relationship between the word lines22aof the embodiment can be expressed as follows. This is similar for the lower selection gate line21aas well. Namely, where n is an integer of 0 or more, the (8n+1)th word line22aand the (8n+4)th word line22aare connected as one body by the first link member22b; the (8n+3)th word line22aand the (8n+6)th word line22aare connected as one body by the second link member22b; the (8n+5)th word line22aand the (8n+8)th word line22aare connected as one body by the third link member22b; and the (8n+7)th word line22aand the (8n+10)th word line22aare connected as one body by the fourth link member22b. Also, the first link member22band the third link member22bare connected to the first upper layer interconnect49by the vias48; and the second link member22band the fourth link member22bare connected to the second upper layer interconnect49by the vias48. According to the embodiment, the lithography for forming the slits ST (referring toFIG.20) is easy because the slits ST can be formed in a configuration that is nearly line-and-space. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. Fourth Embodiment A fourth embodiment will now be described. FIG.28is a perspective view showing a semiconductor memory device according to the embodiment. FIG.29is a plan view showing the semiconductor memory device according to the embodiment. FIG.30is a schematic circuit diagram showing the semiconductor memory device according to the embodiment. In the semiconductor memory device4according to the embodiment as shown inFIG.28andFIG.29, the memory trench MT is formed in a line-and-space configuration extending in the X-direction instead of the snake-like configuration. Also, compared to the semiconductor memory device1according to the first embodiment (referring toFIG.2), the slit ST is short; and the two X-direction end portions of the slit ST do not divide the upper selection gate interconnect layers23, the word line interconnect layers22, and the lower selection gate interconnect layer21. As a result, as shown inFIG.29andFIG.30, the upper selection gate interconnect layer23, the word line interconnect layer22, and the lower selection gate interconnect layer21respectively are divided into loop-shaped members23e,22e, and21esurrounding the slit ST. In the loop-shaped member23e, the two end portions of the two upper selection gate lines23aextending in the X-direction are connected by the two link members23b. Similarly, in the loop-shaped member22e, the two end portions of the two word lines22aextending in the X-direction are connected by the two link members22b; and in the loop-shaped member21e, the two end portions of the two lower selection gate lines21aextending in the X-direction are connected by the two link members21b. Also, the silicon pillars26are disposed between the two mutually-adjacent loop-shaped members23e. Also, the loop-shaped members23eare not connected to each other and can be driven independently. On the other hand, every other loop-shaped member22eis connected to a common upper layer interconnect49. In other words, the loop-shaped member22ethat is connected to a first upper layer interconnect49and the loop-shaped member22ethat is connected to a second upper layer interconnect49are arranged alternately along the Y-direction. The loop-shaped member21ealso is similar to the loop-shaped member22e. Thereby, the two word lines22athat have one silicon pillar26interposed can be driven independently from each other. For example, the connectional relationship between the word lines22aof the embodiment can be expressed as follows. This is similar for the lower selection gate line21aas well. Namely, where n is an integer of 0 or more, the (8n+2)th word line22aand the (8n+3)th word line22aare a portion of the first loop-shaped member22e; the (8n+4)th word line22aand the (8n+5)th word line22aare a portion of the second loop-shaped member22e; the (8n+6)th word line22aand the (8n+7)th word line22aare a portion of the third loop-shaped member22e; and the (8n+8)th word line22aand the (8n+9)th word line22aare a portion of the fourth loop-shaped member22e. Also, the first loop-shaped member22eis connected to the third loop-shaped member22evia the second upper layer interconnect49; and the second loop-shaped member22eis connected to the fourth loop-shaped member22evia the second upper layer interconnect49. According to the embodiment, the lithography for forming the memory trench MT (referring toFIG.7) is easy because the memory trench MT can be formed in a line-and-space configuration instead of the snake-like configuration. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. According to the embodiments described above, a semiconductor memory device can be realized in which the reliability of the operation is high. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. Additionally, the embodiments described above can be combined mutually. | 41,362 |
11943918 | DETAILED DESCRIPTION Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer on the floating gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer. Referring toFIG.1, a substrate100may be provided. A plurality of discrete memory gate structures may be formed on the substrate100. An isolation trench104may be between adjacent memory gate structures. The memory gate structure may include a first gate dielectric layer107, a floating gate layer101on the first gate dielectric layer107, a second gate dielectric layer102on the floating gate layer101, and a control gate layer103on the second gate dielectric layer102. Referring toFIG.2, an isolation layer105may be formed in the isolation trench104. The top surface of the isolation layer105may be lower than the top surface of the control gate layer103and higher than the bottom surface of the control gate layer103. Referring toFIG.3, an initial metal silicide layer106may be formed on the exposed surface of the control gate layer103and the top surface of the isolation layer105. In the above-mentioned embodiment, the initial metal silicide layer106may be subsequently annealed to form a metal silicide layer. The metal silicide layer may be used to reduce the contact resistance between the control gate layer and conductive structures, thereby improving the electrical performance of the memory structure. The initial metal silicide layer106may be formed by a physical vapor deposition process. The initial metal silicide layer106formed by the physical vapor deposition process may form accumulation at a junction A between the control gate layer103and the isolation layer105because the junction A is the intersection of the sidewall surface of the control gate layer103and the top surface of the isolation layer105, and the initial metal silicide layer106of such two surfaces may form relatively large accumulation at the junction A. Certain sharp protrusions (shown inFIG.4) may be generated at the junction A after subsequent annealing treatment. Since the sharp protrusions have small top areas and dense charges, and are easy to form strong electric fields, the electrical performance of finally formed memory structure may be reduced. The present disclosure provides a method for forming a memory structure. By forming an opening, which is at the junction of the sidewall surface of the control gate layer and the top surface of the isolation layer, on the sidewall of the control gate layer, the material accumulation of the initial metal silicide layer at the junction may be reduced. In the subsequent annealing treatment, the formation of sharp protrusions because of material accumulation may be reduced, and the generation of strong electric fields may be avoided, thereby improving the electrical performance of the memory structure. In order to further illustrate the above described objectives, features, and advantages of the present disclosure, various specific embodiments of the present disclosure are described in detail with reference to the accompanying drawings hereinafter. FIGS.5-12illustrate structural schematics corresponding to certain stages of a method for forming an exemplary memory structure according to various disclosed embodiments of the present disclosure. Referring toFIG.5, a substrate200may be provided (e.g., in S401ofFIG.13). In one embodiment, the substrate200may be made of silicon. In other embodiments, the substrate200may also be made of a material including germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, or any other suitable material(s). Referring toFIG.5, a plurality of discrete memory gate structures may be formed on the substrate200; an isolation trench204may be between adjacent memory gate structures; and the memory gate structure may include a floating gate layer201and a control gate layer203on the floating gate layer201(e.g., in S402ofFIG.13). In one embodiment, the memory gate structure may further include a first gate dielectric layer207, which is between the floating gate layer201and the substrate200, and a second gate dielectric layer202, which is between the floating gate layer201and the control gate layer203. In one embodiment, the method for forming the memory gate structure and the isolation trench204may include: forming a first gate dielectric material film on the substrate200; forming a floating gate material film on the first gate dielectric material film; forming a second gate dielectric material film on the floating gate material film; forming a control gate material film on the second gate dielectric material film; forming a mask structure on the control gate material film; forming a patterned layer on the mask structure, where the patterned layer may have an opening exposing a portion of the mask structure; using the patterned layer as a mask to etch the portion of the mask structure, the control gate material film, the second gate dielectric material film, the floating gate material film, and the first gate dielectric material film till the top surface of the substrate is exposed, and forming the memory gate structure and the isolation trench204; and removing the patterned layer and the mask structure (not shown) after forming the memory gate structure and the isolation trench204. In one embodiment, each of the floating gate material film and the control gate material film may be made of a semiconductor material. For example, the semiconductor material may be polysilicon doped with P-type or N-type ions. In one embodiment, the mask structure may include a first mask layer on an initial substrate and a second mask layer on the surface of the first mask layer. In other embodiments, the first mask structure may also be a single-layer structure. In one embodiment, the patterned layer may be on the second mask layer. The material of the patterned layer may include a photoresist, and the patterned layer may be formed by a photolithography patterning process. The patterned layer may be removed by a wet photoresist removing process or an ashing process, and the gas of the ashing process may be an oxygen-containing gas, such as oxygen or ozone. In one embodiment, the second gate dielectric layer202may be a multiple-layer structure. The second gate dielectric layer202may include a first silicon oxide layer (not labeled) on the floating gate layer201, a silicon nitride layer (not labeled) on the first silicon oxide layer, and a second silicon oxide layer (not labeled) on the silicon nitride layer. The first silicon oxide layer and the second silicon oxide layer of the second gate dielectric layer202may be better combined with base crystals; and the silicon nitride layer may be in the middle of such two layers, which may block the extension of defects (e.g., pinholes), such that functions of three layers may be complementary to each other in the design of the three-layer structure. In other embodiments, the second gate dielectric layer may also be a single-layer structure. In one embodiment, the isolation layer may be formed in the isolation trench204. The top surface of the isolation layer may be lower than the top surface of the control gate layer203and higher than the bottom surface of the control gate layer203. An opening may be formed on the exposed sidewall of the control gate layer203, and the bottom of the opening may be lower than or coplanar with the top surface of the isolation layer. The formation process of the isolation layer and the opening refers toFIGS.6-11. Referring toFIG.6, an initial isolation layer205may be formed in the isolation trench204; and the top surface of the initial isolation layer205may be lower than the top surface of the control gate layer203and higher than the bottom surface of the control gate layer203(e.g., in S403ofFIG.13). In one embodiment, forming the initial isolation layer205may include forming an isolation material film in the isolation trench204, where the isolation trench204may be filled with the isolation material film; and further include etching back a portion of the isolation material film to form the initial isolation layer205, where the top surface of the initial isolation layer205may be lower than the top surface of the control gate layer203and higher than the bottom surface (not shown) of the control gate layer203. Referring toFIG.7, a barrier layer208may be formed on the exposed surface of the control gate layer203. The barrier layer208and the initial isolation layer205may be made of different materials, such that when the initial isolation layer205is subsequently etched, the barrier layer208and the initial isolation layer205may generate a relatively large etching selection ratio. In one embodiment, the barrier layer208may be made of silicon nitride, and the initial isolation layer205may be made of silicon oxide. In one embodiment, the barrier layer208may be formed using a rapid thermal nitrogen process. The parameters of the rapid thermal nitrogen process may be: the reaction gas including NH3, NO or N2O, the temperature of about 600° C. to about 1100° C., and the duration of about 5 s to about 180 s. Through the rapid thermal nitrogen process, the nitrogen-containing gas may be directly used to react with the control gate layer203to generate silicon nitride, which may avoid the problem that silicon nitride may be formed on both the control gate layer203and the initial isolation layer205by the deposition process, and the silicon nitride on the initial isolation layer205needs to be further removed subsequently. Through the rapid thermal nitrogen process, the production steps may be simplified, and the production efficiency may be improved. Referring toFIG.8, a first etching process may be used to remove a portion of the initial isolation layer205and expose a portion of the control gate layer203to form an isolation layer209. In one embodiment, the first etching process may be a wet etching process, and the etching solution of the first etching process may include a hydrofluoric acid solution and a hydrogen peroxide solution. The portion of the initial isolation layer205may be removed by the first etching process to form the isolation layer209. The top surface of the formed isolation layer209may be lower than the top surface of the control gate layer203and higher than the bottom surface of the control gate layer203. For example, the top surface of the isolation layer209is lower than the bottom of the barrier layer208, such that the opening may be subsequently formed on the exposed sidewall of the control gate layer203between the bottom of the barrier layer208and the top surface of the isolation layer209. In one embodiment, the height of the removed portion of the initial isolation layer205may be about 50 angstroms to about 100 angstroms, and the height may be in a direction perpendicular to the top direction of the isolation layer209. If the height of the removed portion of the initial isolation layer205is excessively high, the height of the exposed sidewall of the control gate layer203may also be relatively high, and the opening formed by the subsequent etching process may also be relatively large, which may cause relatively large damage to the control gate layer203and further affect the performance of the finally formed memory structure. If the height of the removed portion of the initial isolation layer205is excessively low, the height of the exposed sidewall of the control gate layer203may also be relatively low, the opening formed by the subsequent etching process may be relatively small, and the surface area increased by the opening may also be small. Therefore, when the initial metal silicide layer is deposited subsequently, the material of the initial metal silicide layer may still accumulate at the junction A between the isolation layer209and the control gate layer203; furthermore, sharp protrusions may be formed after the annealing treatment and may generate strong electric fields, which may affect the performance of the finally formed memory structure. Referring toFIG.9, a second etching process may be used to remove a portion of the exposed control gate layer203to form an opening210. In one embodiment, the second etching process may be a wet etching process, and the etching solution of the second etching process may be a tetramethylammonium hydroxide solution (TMAH). The etching rate of the {100} crystal plane group and {110} crystal plane group of semiconductor materials by the tetramethylammonium hydroxide solution is greater than the etching rate of the {111} crystal plane group of semiconductor materials, such that the formed opening210may be processed into a sigma shape. The surface area of the opening210may be further increased through the sigma shape, and the material of the initial metal silicide layer deposited subsequently may be better distributed, which may avoid the material accumulation and reduce the formation of the sharp protrusions due to the material accumulation in the subsequent annealing treatment. In other embodiments, the etching solution of the second etching process may also be a mixed solution of hydrogen peroxide and ammonia heated to about 60° C. to about 80° C. The opening210may be formed on the exposed sidewall of the control gate layer203by the second etching process; the bottom of the opening210may be lower than or coplanar with the top surface of the isolation layer209; and the bottom direction of the opening210may be in a direction in parallel with the top surface of the isolation layer209(e.g., in S404ofFIG.13). Since the opening210is located at the junction A between the sidewall surface of the control gate layer203and the top surface of the isolation layer209, the surface area of the junction A may be effectively increased through the opening210. Therefore, when the initial metal silicide layer is subsequently formed, the material of the initial metal silicide layer may be effectively distributed through the increased surface area to avoid material accumulation; in the annealing treatment of the initial metal silicide layer, the formation of sharp protrusions due to material accumulation may be reduced; furthermore, the strong electric fields formed by the sharp protrusions may be reduced, which may affect the electrical performance of the finally formed memory structure. In one embodiment, the depth of the opening210may be about 40 angstroms to about 60 angstroms, and the depth may be in a direction perpendicular to the sidewall direction of the control gate layer203. If the depth of the opening is relatively deep, the damage to the control gate layer203may be relatively large, which may further affect the performance of the finally formed memory structure. If the depth of the opening is relatively shallow, the surface area increased by the opening210may also be small. Therefore, when the initial metal silicide layer is deposited subsequently, the material of the initial metal silicide layer may still accumulate at the junction A between the isolation layer and the control gate layer; furthermore, sharp protrusions may be formed in the annealing treatment, and the sharp protrusions may generate strong electric fields, which may affect the performance of the finally formed memory structure. Referring toFIG.10, after the opening210is formed, the barrier layer208may be removed. In one embodiment, the barrier layer208may be removed by a third etching process. The third etching process may be an isotropic wet etching process, and the etching solution may include a hydrofluoric acid solution and a hydrogen peroxide solution. Referring toFIG.11, an initial metal silicide layer206may be formed on the exposed surface of the control gate layer203and the top surface of the isolation layer209(e.g., in S405ofFIG.13). Since the opening210is formed at the junctionA, the surface area of the junction A may be effectively increased. Therefore, when the initial metal silicide layer206is deposited, the material of the initial metal silicide layer206may be effectively distributed through the increased surface area by the opening210, which may avoid the material accumulation of the initial metal silicide layer206at the junction A. In one embodiment, the material of the initial metal silicide layer206may be a nickel-platinum alloy, where the proportion of nickel may be about 90% and the proportion of platinum may be about 10%. The initial metal silicide layer206may be formed by a physical vapor deposition process; and the thickness of the initial metal silicide layer may be about 150 angstroms to about 200 angstroms. The initial metal silicide layer206formed in such thickness range may meet the requirement of reducing the contact resistance of the control gate layer203after the metal silicide layer is formed by the annealing treatment subsequently, and may also avoid that the amount of the initial metal silicide layer206is relatively large, and the accumulation is generated at the junction A to form sharp protrusions, which may affect the electrical performance of the finally formed memory structure. Referring toFIG.12, after the initial metal silicide layer206is formed, the annealing treatment may be performed on the initial metal silicide layer206, such that the initial metal silicide layer206reacts with the control gate layer203to form a metal silicide layer211. The function of the metal silicide layer211may be to reduce the contact resistance between the control gate layer203and the conductive structures, thereby improving the electrical performance of the memory structure. In one embodiment, the annealing treatment may include a first annealing treatment and a second annealing treatment. The parameters of the first annealing treatment may include an annealing temperature of about 270° C.˜290° C. and an annealing time of about 30 s˜120 s. The parameters of the second annealing treatment may include an annealing temperature of about 450° C. to 500° C. and an annealing time of about 30 s to 120 s. Referring toFIG.11, correspondingly, the present disclosure further includes a memory structure formed by the above-mentioned method. The memory structure may include the substrate200; the plurality of discrete memory gate structures on the substrate200, where the isolation trench may be between adjacent memory gate structures, and the memory gate structure may include the floating gate layer201and the control gate layer203on the floating gate layer201; the isolation layer209in the isolation trench, where the top surface of the isolation layer209may be lower than the top surface of the control gate layer203and higher than the bottom surface of the control gate layer203; the opening210on the exposed sidewall of the control gate layer203, where the bottom of the opening210may be lower than or coplanar with the top surface of the isolation layer209; and the initial metal silicide layer206formed on the exposed surface of the control gate layer203and the top surface of the isolation layer209. Although the present disclosure has been disclosed above, the present disclosure is not limited thereto. Any changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be determined by the scope defined by the appended claims. | 20,423 |
11943919 | DETAILED DESCRIPTION The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device. The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques. Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation. As used herein, a “memory device” means and includes a microelectronic device exhibiting, but not limited to, memory functionality. As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. As used herein, “vertically neighboring” or “longitudinally neighboring” features (e.g., regions, structures, devices) means and includes features located most vertically proximate (e.g., vertically closest) one another. In addition, as used herein, “horizontally neighboring” or “horizontally neighboring” features (e.g., regions, structures, devices) means and includes features located most horizontally proximate (e.g., horizontally closest) one another. As used herein, the term “pitch” refers to a distance between identical points in two neighboring features. As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way. As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure). As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met. As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value. As used herein, the terms “two-dimensional material” or “2D material” mean and include a crystalline material formed of and including a single (e.g., only one) monolayer, or multilayers (e.g., greater than or equal to two (2) layers), of units (e.g., atoms, molecules) bonded together through intramolecular forces (e.g., covalent bonds). Stated another way, a 2D material may be characterized as a crystalline material comprising about one or more monolayers bonded together though intramolecular forces. As used herein, the term “NMOS” transistor means and includes a so-called metal-oxide transistor having a P-type channel region, an N-type channel region, or an I-type channel region. The gate of the NMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. As used herein, the term “PMOS” transistor means and includes a so-called metal-oxide transistor having an P-type channel region, an N-type channel region, or an I-type channel region. The gate of the PMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. Accordingly, the gate structures of such transistors may include conductive materials that are not necessarily metals. FIG.1Ais a simplified, partial top-down view of a microelectronic device100, in accordance with embodiments of the disclosure.FIG.1Bis a simplified, partial cross-sectional view of a portion of the microelectronic device100shown inFIG.1Aabout the line A-A depicted inFIG.1A.FIG.1Cis a simplified, partial cross-sectional view of a portion of the microelectronic device100shown inFIG.1Aabout the line B-B depicted inFIG.1A. For clarity and ease of understanding of the drawings and related description, not all components (e.g., features, structures, devices) of the microelectronic device100depicted in one ofFIGS.1A through1Care depicted each other ofFIGS.1A through1C. For example, some components of the microelectronic device100vertically overlying other components of the microelectronic device100are not shown inFIG.1Aso as to provide a clearer top-down view of the other components. Referring toFIG.1A, the microelectronic device100may include dielectric structures104overlying an isolation structure102, a 2D material structure106extending over and between the dielectric structures104, gate structures118overlying regions (e.g., channel regions) of the 2D material structure106, and local contact structures114and global contact structures116coupled to additional regions (e.g., source regions, drain regions) of the 2D material structure106. As described in further detail below, the microelectronic device100may include additional components (e.g., features, structures, regions, devices) beyond those depicted inFIG.1A. The isolation structure102(e.g., an interlayer dielectric (ILD) structure) may be formed of and include one or more dielectric materials, such as one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, the isolation structure102may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. The isolation structure102include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one dielectric material. As used herein, the term “homogeneous distribution” means relative amounts of a material do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of a structure. Conversely, as used herein, the term “heterogeneous distribution” means relative amounts of a material vary throughout different portions of a structure. In some embodiments, the isolation structure102exhibits a substantially homogeneous distribution of dielectric material. In further embodiments, the isolation structure102exhibits a substantially heterogeneous distribution of at least one dielectric material. The isolation structure102may, for example, be formed of and include a stack (e.g., laminate) of at least two different dielectric materials. In some embodiments, the isolation structure102is formed of and includes silicon dioxide (SiO2). The dielectric structures104may exhibit horizontally elongate shapes (e.g., fin shapes, lamellar shapes, oblong shapes) extending in parallel in a first horizontal direction (e.g., the Y-direction shown inFIG.1A). As used herein, the term “parallel” means substantially parallel. In some embodiments, the dielectric structures104each exhibit substantially the same dimensions (e.g., substantially the same width W1in the X-direction (FIGS.1A and1C), substantially the same length L1in the Y-direction (FIG.1A) orthogonal to the X-direction, and substantially the same height H1in the Z-direction (FIG.1C)), shape, and spacing (e.g., substantially the same distance D1in the X-direction (FIGS.1A and1C)). In additional embodiments, at least one of the dielectric structures104exhibits one or more of at least one different dimension (e.g., a different length, a different width, a different height) and a different shape than one or more other of the dielectric structures104, and/or a distance between at least one pair of horizontally neighboring dielectric structures104is different than a distance between at least one other pair of horizontally neighboring dielectric structures104. The dimensions, shape, and spacing of the dielectric structures104may be selected to provide desirable dimensions and shape to the 2D material structure106, as described in further detail below. By way of non-limiting example, the dielectric structures104may each individually exhibit an aspect ratio (e.g., ratio of height Hx(FIG.1C) to width W) (FIGS.1A and1C)) within a range of from about 2:1 to about 5:1 (e.g., from about 2:1 to about 3:1), and a ratio of the width W1of each dielectric structure104to the distance D1(e.g., spacing) between horizontally neighboring dielectric structures104may be within a range of from about 0.1:1 to about 10:1. In some embodiments, each of the dielectric structures104exhibits a width W1(FIGS.1A and1C) of about 100 nm, a height H1(FIG.1C) within a range of from about 10 nm to about 500 nm, and a distance D1(FIGS.1A and1C) between horizontally neighboring dielectric structures104is within a range of from about 10 nm to about 100 nm. The dielectric structures104may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). Each of the dielectric structures104may individually include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one dielectric material. In some embodiments, each of the dielectric structures104exhibits a substantially homogeneous distribution of dielectric material. In further embodiments, at least one of the dielectric structures104exhibits a substantially heterogeneous distribution of at least one dielectric material. One or more of the dielectric structures104may, for example, be formed of and include a stack (e.g., laminate) of at least two different dielectric materials. In some embodiments, each of the dielectric structures104is formed of and includes aluminum oxide (Al2O3). For example, each of the dielectric structures104may comprise crystalline Al2O3having a hexagonal crystal structure or a rhombohedral crystal structure. Referring collectively toFIGS.1A and1C, the 2D material structure106may be formed on or over surfaces (e.g., upper surfaces, side surfaces) of the isolation structure102and the dielectric structures104. As shown inFIG.1C, the 2D material structure106may at least partially (e.g., substantially) conform to a topography defined by the surfaces (e.g., upper surfaces, side surfaces) upon which the 2D material structure106is formed. The 2D material structure106may extend (e.g., continuously extend) over surfaces (e.g., upper surfaces, side surfaces) of isolation structure102and the dielectric structures104. The 2D material structure106partially (e.g., less than completely) fills trenches (e.g., openings) horizontally intervening between (e.g., in the X-direction) between dielectric structures104. The 2D material structure106may be formed to a desired thickness T1, at least partially depending upon the horizontal distances (e.g., in the X-direction) between the horizontally neighboring dielectric structures104. For example, the 2D material structure106may exhibit a thickness T1less than or equal to about 10 nanometers (nm), such as less than or equal to about 8 nm, less than or equal to about 6 nm, or less than or equal to about 4 nm. In some embodiments, the thickness T1of the 2D material structure106is within a range of from about 1 nm to about 4 nm. The 2D material structure106may be formed of and include one or more of a transition metal di-chalcogenide (TMDC) having the general chemical formula MX2, wherein M is a transition metal (e.g., molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), hafnium (Hf), rhenium (Re), platinum (Pt), titanium (Ti), tantalum (Ta), vanadium (V), cobalt (Co) cadmium (Cd), chromium (Cr)) and X is a chalcogen (e.g., sulfur (S), selenium (Se), tellurium (Te)); a carbide or carbonitride having the general chemical formula Mn+1Xn(also referred to as an “MXene”) and including oxygen (—O), hydroxyl (—OH), or fluoro (—F) surface termination, wherein M is a transition metal from Groups IV or V of the Periodic Table of Elements (e.g., Ti, Hf, Zr, V, Nb, Ta) and X is selected from carbon (C) and nitrogen (N); graphene; graphene-oxide; stanine; phosphorene; hexagonal boron nitride (h-BN); borophene; silicene; graphyne; germanene; germanane; a 2D supracrystal; and a monolayer of a semiconductive material. In some embodiments, the 2D material structure106comprises one or more TMDC monolayer(s), such as one or more monolayer(s) of one or more of tungsten sulfide (WS2), tungsten selenide (WSe2), tungsten telluride (WTe2), molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), niobium sulfide (NbS2), niobium selenide (NbSe2), niobium telluride (NbTe2), zirconium sulfide (ZrS2), zirconium selenide (ZrSe2), zirconium telluride (ZrTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), hafnium telluride (ZrTe2), rhenium sulfide (ReS2), rhenium selenide (ReSe2), and rhenium telluride (ReTe2). In some embodiments, the 2D material structure106has electron mobility within a range of from about 10 centimeters squared per volt-second (cm2/Vs) to about 400 cm2/Vs (e.g., within a range from about 150 cm2/V s to about 400 cm2/Vs, such as from about 150 cm2/Vs to about 200 cm2/Vs), and a bandgap within a range of from about 1.2 electronvolts (eV) to about 2.5 eV (e.g., within a range of from about 1.8 eV to about 2.5 eV). By way of non-limiting example, the 2D material structure106may comprise one or more of WS2, WSe2, MOS2, and MoSe2. In some embodiments, the 2D material structure106is WSe2. In additional embodiments, the 2D material structure106is WS2. In further embodiments, the 2D material structure106is MoSe2. Referring toFIG.1B, the 2D material structure106may be formed to include channel regions108, first conductively doped regions110, and second conductively doped regions112. Each of the channel regions108of the 2D material structure106may individually be horizontally interposed (e.g., in the Y-direction) between a pair (e.g., two (2)) of the first conductively doped regions110, and each pair of the first conductively doped regions110may individually be horizontally interposed (e.g., in the Y-direction) between a pair (e.g., two (2)) of the second conductively doped regions112. As described in further detail below, the first conductively doped regions110may serve as offset regions (e.g., lateral double-diffused (LDD) offset regions) to horizontally offset the first conductively doped regions110from the gate structures118, and the second conductively doped regions112may serve as source regions and drain regions for transistors (e.g., driver transistors, such as string driver transistors) including the gate structures118, the channel regions108, the first conductively doped regions110, and the second conductively doped regions112. By way of non-limiting example, as shown inFIG.1B, the second conductively doped regions112may include source regions112A and drain regions112B. Each source region112A may be horizontally separated from the drain region112B most horizontally proximate thereto (e.g., in the Y-direction) by two (2) of the first conductively doped regions110and one of the channel regions108between the two (2) of the first conductively doped regions110. A single (e.g., only one) source region112A may be shared by two (2) horizontally neighboring transistors of the microelectronic device100. The first conductively doped regions110and the second conductively doped regions112(e.g., the source regions112A, the drain regions112B) of the 2D material structure106may be doped with any desired dopant(s). In some embodiments, the first conductively doped regions110and the second conductively doped regions112are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth), and the first conductively doped regions110are doped to exhibit relatively less free electrons than the second conductively doped regions112. For example, the first conductively doped regions110may comprise N−regions, and the second conductively doped regions112may comprise N+regions. In some such embodiments, the channel regions108are doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In additional embodiments, the first conductively doped regions110and the second conductively doped regions112are doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium), and the first conductively doped regions110are doped to exhibit relatively less deficiencies of valence electrons (commonly referred to as “holes”) than the second conductively doped regions112. For example, the first conductively doped regions110may comprise P−regions, and the second conductively doped regions112may comprise P+regions. In some such embodiments, the channel regions108are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In further embodiments, one or more of the first conductively doped regions110and the second conductively doped regions112of the 2D material structure106are substantially undoped. For example, the properties (e.g., 2D material composition) of the 2D material structure106may permit one or more of first conductively doped regions110and the second conductively doped regions112to comprise I-type regions. With continued reference toFIG.1B, the local contact structures114and the global contact structures116may contact (e.g., electrically contact, physically contact) the second conductively doped regions112of the 2D material structure106. For example, the local contact structures114may physically contact the drain regions112B of the 2D material structure106, and the global contact structures116may physically contact the source regions112A of the 2D material structure106. The local contact structures114may be formed to downwardly vertically extend (e.g., in the negative Z-direction) from the drain regions112B of the 2D material structure106and through the isolation structure102under the 2D material structure106; and the global contact structures116may be formed to upwardly vertically extend (e.g., in the positive Z-direction) from the source regions112A of the 2D material structure106. As shown inFIG.1B, in some embodiments, the local contact structures114are formed to downwardly vertically extend from upper boundaries of the drain regions112B of the 2D material structure106, such that the local contact structures114vertically extend through the drain regions112B of the 2D material structure106; and the global contact structures116are formed to upwardly vertically extend from upper boundaries of the source regions112A of the 2D material structure106. In additional embodiments, the local contact structures114are formed to downwardly vertically extend from lower boundaries of the drain regions112B of the 2D material structure106, such that the local contact structures114do not vertically extend through the drain regions112B of the 2D material structure106; and/or the global contact structures116are formed to upwardly vertically extend from lower boundaries of the source regions112A of the 2D material structure106, such that the global contact structures116vertically extend through the source regions112A of the 2D material structure106. As described in further detail below, the local contact structures114may electrically connect the 2D material structure106of the microelectronic device100to additional structures (e.g., additional conductive structures, such as conductive line structures and/or additional conductive contact structures) and/or devices vertically underlying the microelectronic device100; and the global contact structures116may electrically connect the 2D material structure106of the microelectronic device100to additional structures and/or devices vertically overlying the microelectronic device100. In additional embodiments, the local contact structures114and/or the global contact structures116physically contact the first conductively doped regions110of the 2D material structure106instead of the second conductively doped regions112. In further embodiments, the local contact structures114and/or the global contact structures116physically contact the first conductively doped regions110of the 2D material structure106in addition to the second conductively doped regions112. The local contact structures114and the global contact structures116may be each individually formed of and include at least one electrically conductive material, such as one or more of at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)); and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). The local contact structures114and the global contact structures116may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If one or more of the local contact structures114and the global contact structures116exhibit a substantially heterogeneous distribution of electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the one or more of the local contact structures114and the global contact structures116. In some embodiments, the local contact structures114and the global contact structures116each individually exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more of at least one of the local contact structures114and at least one of the global contact structures116exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of at least one of the local contact structures114and at least one of the global contact structures116may, for example, be formed of and include a stack of at least two different electrically conductive materials. Referring collectively toFIGS.1A and1B, the gate structures118may vertically overlie (e.g., in the Z-direction) the channel regions108(FIG.1B) of the 2D material structure106, and may exhibit horizontally elongate shapes (e.g., oblong shapes, rectangular shapes) extending in parallel in a second horizontal direction (e.g., the X-direction (FIG.1A)) orthogonal to the first horizontal direction (e.g., the Y-direction) in which the dielectric structures104(FIG.1A) extend. The gate structures118may be substantially horizontally aligned (e.g., in the Y-direction) with the channel regions108of the 2D material structure106. Each of the gate structures118may individually horizontally intervene (e.g., in the Y-direction) between one of the source regions112A of the 2D material structure106and one of the drain regions112B of the 2D material structure106most horizontally proximate (e.g., in the Y-direction) to the one of the source regions112A. The gate structures118may each exhibit substantially the same dimensions (e.g., width W2in the Y-direction (FIGS.1A and1B), length in the X-direction (FIG.1A), and height H2in the Z-direction (FIGS.1B and1C)) and shape as one another. In some embodiments, each of the gate structures118exhibits a width W2of about 18.5 micrometers (μm), and a distance D2(FIGS.1A and1B) between some horizontally neighboring gate structures is about 30.5 μm. The gate structures118may be formed of and include at least one electrically conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). The gate structures118may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If the gate structures118exhibit substantially heterogeneous distributions of the electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the gate structures118. In some embodiments, the gate structures118each exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more (e.g., each) the gate structures118exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of the gate structures118may, for example, be formed of and include a stack of at least two different electrically conductive materials. Referring toFIG.1C, the microelectronic device100may further include conductive structures120vertically extending (e.g., in the Z-direction) from the gate structures118toward the channel regions108of the 2D material structure106. The conductive structures120may effectively serve as protrusions or extensions of the gate structures118to accommodate the non-planar structure of the 2D material structure106effectuated by the combined topography of the dielectric structures104and the isolation structure102. The conductive structures120may horizontally intervene (e.g., in the X-direction) between horizontally neighboring dielectric structures104. The conductive structures120partially (e.g., less than completely) fills portions of the trenches (e.g., openings) horizontally intervening between (e.g., in the X-direction) between the dielectric structures104(e.g., portions of the trenches not occupied by the 2D material structure106). The conductive structures120may be formed to any desired dimensions, at least partially depending the dimensions (e.g., width in the Y-direction (FIG.1A) of the gate structures118), the dimensions (e.g., width in the X-direction (FIG.1C), height in the Z-direction (FIG.1C)) and the spacing (e.g., in the X-direction (FIG.1C)) of the dielectric structures104, and the dimensions (e.g., thickness) of the 2D material structure106. The conductive structures120may each individually exhibit a width in the Y-direction (FIG.1A) substantially equal to a width of the gate structures118in the Y-direction (FIG.1A), and may exhibit a height H3in the Z-direction (FIG.1C) and a thickness T2in the X-direction (FIG.1C) permitting the conductive structure120to be substantially equally offset (e.g., spaced apart) from all portions of the 2D material structure106proximate thereto in the X-direction and the Z-direction. The conductive structures120may be formed of and include at least one electrically conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). The conductive structures120may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If the conductive structures120exhibit substantially heterogeneous distributions of the electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the conductive structures120. In some embodiments, the conductive structures120each exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more (e.g., each) the conductive structures120exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of the conductive structures120may, for example, be formed of and include a stack of at least two different electrically conductive materials. A material composition of the conductive structures120may be substantially the same as a material composition of the gate structures118, or the material composition of the conductive structures120may be different than the material composition of the gate structures118. In some embodiments, the material composition of the conductive structures120is substantially the same as the material composition of the gate structures118. With continued reference toFIG.1C, the microelectronic device100may further include a gate dielectric material122positioned between (e.g., horizontally between, vertically between) the 2D material structure106and the gate structures118and the conductive structures120. The gate dielectric material122may extend from boundaries (e.g., horizontal boundaries, vertical boundaries) of the 2D material structure106to opposing boundaries (e.g., horizontal boundaries, vertical boundaries) of the gate structures118and the conductive structures120. The gate dielectric material122may fill remaining portions of the trenches (e.g., openings) horizontally intervening between (e.g., in the X-direction) between the dielectric structures104(e.g., portions of the trenches not occupied by the 2D material structure106and the conductive structures120). The gate dielectric material122may be formed to a desired thickness T3, at least partially depending the dimensions (e.g., width W2(FIG.1A)) of the gate structures118; the dimensions (e.g., width W2(FIG.1A), height H3(FIG.1C)) of the conductive structures120; the dimensions (e.g., width W1(FIG.1C), height H2(FIG.1C)) and the spacing (e.g., distance Dx(FIG.1C)) of the dielectric structures104; the dimensions (e.g., thickness Tx(FIG.1C)) of the 2D material structure106; and a distance (e.g., in the Z-direction (FIG.1C)) between upper surfaces of the dielectric structures104and lower surfaces of the gate structures118. By way of non-limiting example, the gate dielectric material122may be formed to exhibit a thickness T3less than or equal to about 15 nm, such less than or equal to about 10 nm, less than or equal to about 8 nm, or less than or equal to about 5 nm. In some embodiments, the gate dielectric material122exhibits a thickness T3within a range of from about 5 nm to about 10 nm. The gate dielectric material122may be formed of and include at least one dielectric material, such as one or more of at least one oxide dielectric material (e.g., one or more of SiOx, AlOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass), at least one nitride dielectric material (e.g., SiNy), and at least one low-K dielectric material (e.g., one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), and silicon oxycarbonitride (SiOxCzNy)). The gate dielectric material122may include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one dielectric material. In some embodiments, the gate dielectric material122exhibits a substantially homogeneous distribution of dielectric material. In further embodiments, the gate dielectric material122exhibits a substantially heterogeneous distribution of at least one dielectric material. In some embodiments, the gate dielectric material122is formed of and includes SiO2. Referring toFIG.1B, the gate structures118, the gate dielectric material122, and the channel regions108and first conductively doped regions110(including the source regions112A and the drain regions112B) and channel regions108of the 2D material structure106may form transistors124(e.g., driver transistors, such as string driver transistors) of the microelectronic device100. Each of the transistors124may include one of the gate structures118, the gate dielectric material122, one of the channel regions108of the 2D material structure106, one of the drain regions112B of the 2D material structure106, and one of the source regions112A of the 2D material structure106. Each of the transistors124also include the conductive structures120(FIG.1C) vertically extending from the gate structure118thereof. In some embodiments, the transistors124comprise high voltage (HV) transistors (e.g., HVNMOS transistors, HVPMOS transistors). HV transistors are operative at higher voltages than non-HV transistors (e.g., NMOS transistors, PMOS transistors). For example, HV transistors may have threshold voltages greater than the threshold voltage range (e.g., from about +0.5V to about +0.7V) of non-HV transistors, such as a threshold voltages greater than or equal to about +3 V higher than the threshold voltage range of non-HV transistors. For example, if the first conductively doped regions110of the 2D material structure106are doped with at least one N-type dopant, the transistors124comprise HVNMOS transistors. As another example, if the first conductively doped regions110of the 2D material structure106are doped with at least one P-type dopant, the transistors124comprise HVPMOS transistors. The non-planar topography of the 2D material structure106(e.g., as defined by the surfaces of the isolation structure102and the dielectric structures104(FIGS.1A and1C) upon which the 2D material structure106is formed) provides the transistors124with a so-called “folded channel” configuration. The folded channel configuration of the transistors124may provide the transistors124with greater effective channel width as compared to conventional transistors not exhibiting the folded channel configuration of the disclosure (e.g., conventional transistors exhibiting substantially planar channel configurations). In addition, the material composition of the 2D material structure106may provide the channel regions108of the transistors124with higher bandgap and comparable (or greater) electron mobility than conventional transistors employing semiconductive materials such as silicon and polysilicon for the channel regions thereof. Accordingly, the 2D material structure106may facilitate more favorable electrical properties in the transistors124(e.g., one or more of relatively higher on current (Ion), relatively lower off current (Ioff), relatively faster switching speed, improved breaking voltage (BV), relatively lower operating voltage, relatively reduced current leakage, relatively less scattering at an interface between the channel region108and the gate dielectric material122) of the disclosure as compared to conventional transistors. In addition, the 2D material structure106may be formed at relatively lower temperatures (e.g., temperatures less than or equal to about 600° C., such as temperatures within a range of from about 400° C. to about 600° C., or less than or equal to about 400° C.) to reduce or eliminate temperature incompatibilities with other structures and/or devices underlying of the microelectronic device100. Thus, in accordance with embodiments of the disclosure, a transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Moreover, in accordance with additional embodiments of the disclosure, a microelectronic device comprises discrete dielectric structures, a non-planar 2D material structure, gate structures, conductive structures, contact structures, and at least one additional contact structure. The discrete dielectric structures overlie an isolation structure and are separated from one another by filled trenches. The non-planar 2D material structure extends over surfaces of the isolation structure and the discrete dielectric structures inside and outside of the filled trenches, and comprises conductively doped regions and channel regions between the conductively doped regions. The gate structures overlie and are substantially aligned with the channel regions of the non-planar 2D material structure. The conductive structures extend from the gate structures and into the trenches. The contact structures are coupled to some of the conductively doped regions and extend into the isolation structure. The at least one additional contact structure is coupled to at least one other of the conductively doped regions and extends away from the isolation structure. In additional embodiments, the 2D material structure106may be formed to be substantially planar (e.g., substantially horizontally planar), such that transistors including the 2D material structure106exhibit a substantially planar (e.g., non-folded) channel configuration. In such embodiments, the dielectric structures104(FIGS.1A and1C) may be omitted (e.g., absent), such that the 2D material structure106substantially continuously horizontally extends over a substantially planar upper surface of the isolation structure102(thereby forming the 2D material structure106to also be substantially planar); and the conductive structures120(FIG.1C) vertically extending from the gate structures118may also be omitted. While such a planar configuration of the channel regions of the transistors may exhibit less effective channel width than the channel regions108of the transistors124, the material composition of the 2D material structure106may still impart the transistors with improved electrical properties as compared to conventional transistors employing semiconductive materials such as silicon and polysilicon for the channel regions thereof. WhileFIGS.1A through1Cdepict the microelectronic device100as including a single (e.g., only one) 2D material structure106and two (2) transistors124(FIG.1B) including portions of the 2D material structure106; the microelectronic device100may include additional 2D material structures106and additional transistors124including portions of the additional 2D material structures106. For example, the microelectronic device100may include multiple (e.g., more than one) 2D material structures106substantially similar to one another, and spaced apart from one another on the isolation structure102. Each of the multiple 2D material structures106may individually form portions (e.g., channel regions108, source regions112A, drain regions112B) of transistors124of the microelectronic device100, as well as source regions112A (FIG.1B) and drain regions112B (FIG.1B) for the transistors124of the microelectronic device100. In addition, the microelectronic device100may include additional local contact structures114and additional global contact structures116operatively associated with the additional 2D material structures106and the additional transistors124in substantially the same manner previously describe with reference toFIGS.1A through1C. The quantities, configurations, and arrangements of additional 2D material structures106, additional transistors124, additional local contact structures114, and additional global contact structures116of the microelectronic device100may be dependent on the quantities, configurations, and arrangements of additional structures and/or devices operatively associated with the microelectronic device100, as described in further detail below. Microelectronic devices (e.g., the microelectronic device100previously described with reference toFIGS.1A through1C) in accordance with embodiments of the disclosure may be used in embodiments of memory devices of the disclosure. For example,FIG.2Ais a simplified, partial top-down view of a memory device200(e.g., 3D NAND Flash memory device) including one or more embodiments of the microelectronic device100previously described with reference toFIGS.1A through1C.FIG.2Bis a simplified, partial cross-sectional view of a portion of the memory device200shown inFIG.2Aabout the line A-A depicted inFIG.2A.FIG.2Cis a simplified, partial cross-sectional view of a portion of the memory device200shown inFIG.2Aabout the line B-B depicted inFIG.2A. For clarity and ease of understanding of the drawings and related description, not all components (e.g., features, structures, devices) of the memory device200depicted in one ofFIGS.2A through2Care depicted over each other inFIGS.2A through2C. For example, some components of the memory device200vertically overlying other components of the memory device200are not shown inFIG.2Aso as to provide a clearer top-down view of the other components. As shown inFIGS.2B and2C, the microelectronic device100(including the components thereof previously described with reference toFIGS.1A through1C) of the memory device200may vertically overlie (e.g., in the Z-direction) and be operatively associated with a stack structure202of the memory device200. The stack structure202includes a vertically alternating (e.g., in the Z-direction) sequence of conductive structures204(e.g., access line plates, word line plates) and insulating structures206arranged in tiers208. In addition, as shown inFIGS.2A and2C, the stack structure202includes a memory array region202A, and a staircase region202B horizontally neighboring (e.g., in the X-direction) a first horizontal boundary of the memory array region202A. As described in further detail below, the memory device200further includes additional components (e.g., features, structures, devices) within horizontal boundaries of the different regions (e.g., the memory array region202A and the staircase region202B) of the stack structure202. Referring collectively toFIGS.2B and2C, the tiers208of the stack structure202of the memory device200may each individually include at least one of the conductive structures204vertically neighboring at least one of the insulating structures206. The stack structure202may include a desired quantity of the tiers208. For example, the stack structure202may include greater than or equal to ten (10) of the tiers208, greater than or equal to twenty-five (25) of the tiers208, greater than or equal to fifty (50) of the tiers208, greater than or equal to one hundred (100) of the tiers208, greater than or equal to one hundred and fifty (150) of the tiers208, or greater than or equal to two hundred (200) of the tiers208of the conductive structures204and the insulating structures206. The conductive structures204of the tiers208of the stack structure202may be formed of and include at least one electrically conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped poly silicon, conductively doped Ge, conductively doped SiGe), and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the conductive structures204are formed of and include a metallic material (e.g., a metal, such as W; an alloy). In additional embodiments, the conductive structures204are formed of and include conductively doped poly silicon. Each of the conductive structures204may individually include a substantially homogeneous distribution of the at least one electrically conductive material, or a substantially heterogeneous distribution of the at least one electrically conductive material. In some embodiments, each of the conductive structures204of each of the tiers208of the stack structure202exhibits a substantially homogeneous distribution of electrically conductive material. In additional embodiments, at least one of the conductive structures204of at least one of the tiers208of the stack structure202exhibits a substantially heterogeneous distribution of at least one electrically conductive material. The conductive structure204may, for example, be formed of and include a stack of at least two different electrically conductive materials. The conductive structures204of each of the tiers208of the stack structure202may each be substantially planar, and may each exhibit a desired thickness. The insulating structures206of the tiers208of the stack structure202may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the insulating structures206are formed of and include SiO2. Each of the insulating structures206may individually include a substantially homogeneous distribution of the at least one insulating material, or a substantially heterogeneous distribution of the at least one insulating material. In some embodiments, each of the insulating structures206of each of the tiers208of the stack structure202exhibits a substantially homogeneous distribution of insulating material. In additional embodiments, at least one of the insulating structures206of at least one of the tiers208of the stack structure202exhibits a substantially heterogeneous distribution of at least one insulating material. The insulating structure206may, for example, be formed of and include a stack (e.g., laminate) of at least two different insulating materials. The insulating structures206of each of the tiers208of the stack structure202may each be substantially planar, and may each individually exhibit a desired thickness. At least one lower conductive structure204of the stack structure202may be employed as at least one lower select gate (e.g., at least one source side select gate (SGS)) of the memory device200. In some embodiments, a single (e.g., only one) conductive structure204of a vertically lowermost tier208of the stack structure202is employed as a lower select gate (e.g., a SGS) of the memory device200. In addition, upper conductive structure(s)204of the stack structure202may be employed as upper select gate(s) (e.g., drain side select gate(s) (SGDs)) of the memory device200. In some embodiments, horizontally neighboring conductive structures204of a vertically uppermost tier208of the stack structure202are employed as upper select gates (e.g., SGDs) of the memory device200. Referring toFIGS.2A and2B, the stack structure202may be partitioned in the Y-direction by fdled slots210. The fdled slots210may, for example, vertically extend (e.g., in the Z-direction (FIG.2B)) completely through the stack structure202. The filled slots210may divide (e.g., in the Y-direction) the stack structure202into multiple blocks212. As shown inFIG.2B, the fdled slots210may each individually be filled with at least one dielectric structure214. The dielectric structure214may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, the dielectric structures214comprise SiO2. Prior to being filled with the dielectric structures214to become the filled slots210, preliminary slots may, for example, be employed to form the conductive structures204(FIG.1A) of the stack structure202through so-called “replace gate” or “gate last” processing acts. For example, a preliminary stack structure including a vertically alternating sequence of sacrificial structures and preliminary insulating structures may be formed through conventional material deposition processes; the preliminary slots may be formed through at least the preliminary stack structure by way of one or more conventional material removal processes to form modified sacrificial structures and the insulating structures206(FIG.2B); at least a portion of each of the modified sacrificial structures may be selectively removed by way of one or more additional conventional material removal processes to form recessed regions; and then the recessed regions may be at least partially (e.g., substantially) filled with conductive material to form the conductive structures204(FIG.2B). As shown inFIG.2A, each of the blocks212may exhibit substantially the same width W3(e.g., horizontal dimension in the Y-direction) as one another. In addition, each of the blocks212may be separated (e.g., in the X-direction) from each other horizontally neighboring block212by substantially the same distance D3(e.g., corresponding to the width of each of the filled slots210(FIG.2B)), such that the blocks212are substantially uniformly spaced from one another. Accordingly, a pitch Pi (FIG.2A) between centerlines of horizontally neighboring blocks212of the stack structure202may be substantially uniform throughout the stack structure202. For clarity and ease of understanding of the drawings and related description,FIGS.2A and2Bshow the stack structure202of the memory device200as including three (3) of the blocks212and two (2) of the slots210. However, the stack structure202may include different quantities (e.g., amounts, numbers) of the blocks212(e.g., greater than three (3) of the blocks212, less than three (3) of the blocks212) and the slots210(e.g., greater than two (2) of the slots210, less than two (2) of the slots210), and/or may include a different distribution of the blocks212(and, hence, the slots210). The quantities of blocks212and slots210included in the stack structure202at least partially depends on the quantities, dimensions, and arrangements of additional structures included in the memory device200, as described in further detail below. Referring toFIG.2A, within horizontal boundaries (e.g., in the X-direction and the Y-direction) of the memory array region202A of the stack structure202, the memory device200may include vertically extending pillar structures216. Each of the vertically extending pillar structures216may include a semiconductive pillar (e.g., a polysilicon pillar, a silicon-germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., a charge-trapping structure, such as a charge-trapping structure comprising an oxide-nitride-oxide (“ONO”) material; floating gate structures). Intersections of the vertically extending pillar structures216and the conductive structures204(FIGS.2B and2C) of the tiers208(FIGS.2B and2C) of the stack structure202(FIGS.2B and2C) may define vertically extending strings of memory cells218coupled in series with one another within the memory array region202A of the stack structure202. In some embodiments, the memory cells218formed at the intersections of the conductive structures204and the vertically extending pillar structures216within each the tiers208of the stack structure202comprise so-called “MONOS” (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells218comprise so-called “TANOS” (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called “BETANOS” (band/barrier engineered TANOS) memory cells, each of which are subsets of MONOS memory cells. In further embodiments, the memory cells218comprise so-called “floating gate” memory cells including floating gates (e.g., metallic floating gates) as charge storage structures. The floating gates may horizontally intervene between the central structures of the vertically extending pillar structures216and the conductive structures204of the different tiers208of the stack structure202. The memory device200may include any desired quantity and distribution of the vertically extending pillar structures216within the memory array region202A of the stack structure202. Referring collectively toFIGS.2A through2C, the memory device200may further include digit lines220(FIGS.2A and2C) (e.g., data lines, bit lines) vertically overlying the stack structure202and at least one source structure222(FIGS.2B and2C) (e.g., source line, source plate) vertically underlying the stack structure202. The vertically extending pillar structures216may substantially vertically extend between the digit lines220and the source structure222. The digit lines220and the source structure222may each individually be formed of and include at least one electrically conductive material, such as one or more of at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), at least one alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe), and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). The digit lines220and the source structure222may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If one or more of the digit lines220and the source structure222exhibit a substantially heterogeneous distribution of electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the one or more of the digit lines220and the source structure222. In some embodiments, the digit lines220and the source structure222each individually exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more of at least one of the digit lines220and the source structure222exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of at least one of digit lines220and the source structure222may, for example, be formed of and include a stack of at least two different electrically conductive materials. With continued reference toFIGS.2A and2C, within horizontal boundaries (e.g., in the X-direction) of the staircase region202B of the stack structure202, each of the blocks212of the stack structure202may include a staircase structure224at a horizontal end (e.g., in the X-direction) thereof. The staircase structure224of each of the blocks212of the stack structure202includes steps226at least partially defined by horizontal ends (e.g., in the X-direction) of the tiers208. The steps226of the staircase structures224may serve as contact regions to electrically couple the conductive structures204(FIG.2C) of the tiers208(FIG.2C) of the stack structure202to other components (e.g., features, structures, devices) of the memory device200, as described in further detail below. Each of the staircase structures224within the staircase region202B of the stack structure202may individually include a desired quantity of steps226. In addition, as shown inFIG.2C, in some embodiments, the steps226of each of the staircase structures224are arranged in order, such that steps226directly horizontally adjacent (e.g., in the X-direction) one another correspond to tiers208of the stack structure202directly vertically adjacent (e.g., in the Z-direction) one another. In additional embodiments, the steps226of one or more of the staircase structures224are arranged out of order, such that at least some steps226of the staircase structures224directly horizontally adjacent (e.g., in the X-direction) one another correspond to tiers208of stack structure202not directly vertically adjacent (e.g., in the Z-direction) one another. Still referring toFIGS.2A and2C, the memory device200may further include conductive contact structures228physically and electrically contacting at least some (e.g., each) of the steps226of the staircase structures224of the stack structure202to provide electrical access to the conductive structures204of the stack structure202. The conductive contact structures228may be coupled to the conductive structures204of the tiers208of the stack structure202at the steps226of the staircase structures224. As shown inFIG.2C, the conductive contact structures228may physically contact and upwardly vertically extend (e.g., in the positive Z-direction) from the conductive structures204of the tiers208of the stack structure202at the steps226of the staircase structures224. Each staircase structure224of each block212of the stack structure202may include at least one conductive contact structure228physically contacting each step226thereof; or one or more staircase structures224of one or more blocks212of the stack structure202may be free of at least one conductive contact structure228physically contacting at least one step226thereof. In some embodiments, each of the conductive contact structures228individually exhibits a columnar shape (e.g., a circular column shape, a rectangular column shape, an ovular column shape, a pillar shape), and is sized and positioned to physically contact a single (e.g., only one) step226of a single (e.g., only one) staircase structure224(e.g., a staircase structure224of a single block212) of the stack structure202. In additional embodiments, one or more of the conductive contact structures228exhibits a different shape, a different size, and/or a different position. The conductive contact structures228may be formed of and include at least one electrically conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a Mg-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), a conductively doped semiconductor material (e.g., conductively doped Si, conductively doped Ge, conductively doped SiGe). The conductive contact structures228may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If the conductive contact structures228exhibit substantially heterogeneous distributions of the electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the conductive contact structures228. In some embodiments, the conductive contact structures228each exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more (e.g., each) the conductive contact structures228exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of the conductive contact structures228may, for example, be formed of and include a stack of at least two different electrically conductive materials. Referring collectively toFIGS.2B and2C, optionally, the memory device200may further include conductive structures230physically contacting at least some of the conductive contact structures228of the memory device200. For example, the conductive structures230may individually be sized, shaped, and positioned to physically contact and horizontally extend beyond horizontal boundaries of (e.g., in the X-direction, in the Y-direction) of a conductive contact structure228located on a step226of the stack structure202. In some such embodiments, each of the conductive structures230individually physically contacts and horizontally extends past horizontal boundaries of one of the conductive contact structures228located one of the steps226of the stack structure202. In additional embodiments, at least some (e.g., all) of the conductive structures230are omitted. The conductive structures230, if present, may be formed of and include at least one electrically conductive material, such as one or more of a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a Mg-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), a conductively doped semiconductor material (e.g., conductively doped Si, conductively doped Ge, conductively doped SiGe). The conductive structures230may include substantially homogeneous distributions of the electrically conductive material, or may include substantially heterogeneous distributions of the electrically conductive material. If the conductive structures230exhibit substantially heterogeneous distributions of the electrically conductive material, amounts of the electrically conductive material may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the conductive structures230. In some embodiments, the conductive structures230each exhibit a substantially homogeneous distribution of electrically conductive material. In additional embodiments, one or more (e.g., each) the conductive contact structures228exhibits a substantially heterogeneous distribution of at least one electrically conductive material. One or more of the conductive structures230may, for example, be formed of and include a stack of at least two different electrically conductive materials. With continued reference toFIGS.2B and2C, the memory device200may further include an isolation material232on or over the stack structure202. The isolation material232may be vertically interposed (e.g., in the Z-direction) between the stack structure202and the isolation structure102. As shown inFIG.2C, the isolation material232may substantially cover the staircase structures224within the staircase region202B of the stack structure202, and may substantially surround side surfaces (e.g., sidewalls) of the conductive contact structures228on the steps226of the staircase structures224. The isolation material232may exhibit a substantially planer upper vertical boundary, and a substantially non-planar lower vertical boundary complementary to the topography of at least the stack structure202(including the staircase structures224thereof) thereunder. The isolation material232may be formed of and include at least one dielectric material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). The isolation material232may include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one dielectric material. In some embodiments, the isolation material232exhibits a substantially homogeneous distribution of dielectric material. In further embodiments, the isolation material232exhibits a substantially heterogeneous distribution of at least one dielectric material. The isolation material232may, for example, be formed of and include a stack (e.g., laminate) of at least two different dielectric materials. In some embodiments, the isolation material232is formed of and includes SiO2. Referring collectively toFIGS.2A through2C, the microelectronic device100according to embodiments of the disclosure may be located vertically above (e.g., in the Z-direction shown inFIGS.2B and2C) and at least partially (e.g., substantially) within horizontal boundaries (e.g., in the Y-direction and the X-direction shown inFIG.2A) of the staircase region202B of the stack structure202. The microelectronic device100may serve as a string driver assembly (e.g., an HV string driver assembly) for the memory device200. As described in further detail below, the transistors124(FIG.2B) (e.g., driver transistors, such as string driver transistors) of the microelectronic device100may be electrically coupled to the conductive structures204of the stack structure202by way of the local contact structures114, the conductive contact structures228(FIGS.2A and2C), and, if present, the conductive structures230(FIGS.2B and2C). As shown inFIGS.2A and2C, multiple 2D material structures106of the microelectronic device100may vertically overlie (e.g., in the Z-direction shown inFIG.2C) the stack structure202. Different 2D material structures106of the microelectronic device100may, for example, individually vertically overlie and at least partially (e.g., substantially) be located within horizontal boundaries (e.g., the X-direction) of steps226of the staircase structures224within the staircase regions202B of the stack structure202. As shown inFIG.2A, different 2D material structures106of the microelectronic device100may individually horizontally extend in the Y-direction across and between different steps226of the stack structure202horizontally neighboring one another in the Y-direction, and may be substantially confined within horizontal boundaries of the different, horizontally neighboring steps226in the X-direction. As a non-limiting example, as depicted inFIG.2A, three (3) 2D material structures106of the microelectronic device100may be operatively associated with three (3) groups of steps226of the stack structure202, wherein each of three (3) 2D material structure106individually vertically overlies and is located within horizontal boundaries (e.g., the X-direction) of one of the three (3) groups of steps226, and each group of steps226individually includes different steps226of the stack structure202horizontally neighboring one another (e.g., the Y-direction) and located at substantially the same vertical position (e.g., in the Z-direction) as one another in the stack structure202. A pitch P2between 2D material structures106of the microelectronic device100horizontally neighboring one another in the X-direction may be substantially equal to (e.g., substantially the same as) a pitch between steps226of the stack structure202horizontally neighboring one another in the X-direction. With continued reference toFIGS.2A and2C, gate structures118of the microelectronic device100may vertically overlie and be positioned with horizontal boundaries (e.g., in the Y-direction) of the blocks212of the stack structure202. As shown inFIG.2A, the gate structures118of the microelectronic device100may extend substantially the same horizontal direction (e.g., the X-direction) as the blocks212of the stack structure202, and may be located within horizontal boundaries of the blocks212of the stack structure202in the another horizontal direction (e.g., Y-direction) orthogonal to the horizontal direction in which the gate structures118and the blocks212extend. In some embodiments, centerlines of the gate structures118in the Y-direction are substantially aligned with centerlines of the blocks212in the Y-direction. A pitch between horizontally neighboring gate structures118(e.g., in the Y-direction) of the microelectronic device100may be substantially equal to (e.g., substantially the same as) the pitch P1(FIG.2A) between horizontally neighboring blocks212(e.g., in the Y-direction) of the stack structure202. Referring next toFIGS.2B and2C, the local contact structures114of the microelectronic device100may vertically extend (e.g., in the Z-direction) from the 2D material structures106of the microelectronic device100to the conductive structures230. For example, as shown inFIG.2B, the local contact structures114may vertically extend from some of the second conductively doped regions112(e.g., the drain regions112B) of the 2D material structures106to the conductive structures230. The local contact structures114may contact (e.g., physically contact, electrically contact) the conductive structures230. Accordingly, the local contact structures114, the conductive structures230, and the conductive contact structures228may electrically connect the transistors124(e.g., driver transistors, such as string driver transistors) of the microelectronic device100to the conductive structures204of the tiers208of the stack structure202. As shown inFIGS.2B and2C, the local contact structures114may be located within horizontal boundaries (e.g., in the Y-direction (FIG.2B) and in the X-direction (FIG.2C)) of the conductive structures230. In some embodiments, centerlines of at least some (e.g., all, less than all) of the local contact structures114in the X-direction (FIG.2C) are offset from centerlines in the X-direction of the conductive structures230that the at least some of the local contact structures114contact (e.g., physically contact, electrically contact). In additional embodiments, centerlines of at least some (e.g., all, less than all) of the local contact structures114in the X-direction are substantially aligned with centerlines in the X-direction of the conductive structures230that the at least some of the local contact structures114contact (e.g., physically contact, electrically contact). In additional embodiments, such as embodiments wherein the conductive structures230are omitted, the local contact structures114of the microelectronic device100may vertically extend (e.g., in the Z-direction) from the 2D material structures106to the conductive contact structures228. In such embodiments, the local contact structures114are at least partially (e.g., substantially) located within horizontal boundaries (e.g., in the Y-direction (FIG.2B) and in the X-direction (FIG.2C)) of the conductive contact structures228. Accordingly, the local contact structures114and the conductive contact structures228may electrically connect the transistors124of the microelectronic device100to the conductive structures204of the tiers208of the stack structure202. In further embodiments, one or more of the local contact structures114of the microelectronic device100may vertically extend (e.g., in the Z-direction) from the 2D material structures106to the steps226of the stack structure202. By way of non-limiting example, the conductive contact structures228and the conductive structures230may be omitted, and each of the local contact structures114may individually contact one of the steps226of the stack structure202. Accordingly, the local contact structures114may directly electrically connect the transistors124of the microelectronic device100to the conductive structures204of the tiers208of the stack structure202. WhileFIGS.2A through2Cdepict the microelectronic device100of the memory device200as being located within horizontal boundaries (e.g., in the X-direction, in the Y-direction) of the staircase region202B of the stack structure202of the memory device200, one or more portions of the microelectronic device100may be located outside of the horizontal boundaries of the staircase region202B of the stack structure202of the memory device200. For example, one or more portions (e.g., all, less than all) of one or more transistors124of the microelectronic device100may be located outside of the horizontal boundaries of the staircase region202B of the stack structure202. In such embodiments, the geometric configurations of one or more of the local contact structures114, the conductive structures230, and the conductive contact structures228connected (e.g., physically connected, electrically connected) to the one or more portions of the one or more transistors124may be modified relative to the geometric configurations depicted inFIGS.2A through2Cto facilitate electrical connections between the one or more transistors124and one or more of the conductive structures204of the stack structure202. As a non-limiting example, routes (e.g., paths) of one or more conductive structures230electrically connected to the one or more transistors124may be shaped to extend outside horizontal boundaries of the staircase region202B of the stack structure202and to the local contact structures114in contact with the one or more transistors124. Thus, in accordance with additional embodiments of the disclosure, a memory device comprises a stack structure, a staircase structure, a string driver transistor, at least one additional conductive structure, and a string of memory cells. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. The staircase structure is at a horizontal end of the stack structure. The staircase structure has steps comprising edges of the tiers. The string driver transistor vertically overlies the staircase structure and comprises a channel region comprising at least one 2D material. The at least one additional conductive structure extends from and between the string driver transistor and one of the steps of the staircase structure. The string of memory cells vertically extends through the stack structure. Microelectronic devices (e.g., the microelectronic device100previously described with reference toFIGS.1A through1C) and memory devices (e.g., the memory device200previously described with reference toFIGS.2A through2C) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.3is a block diagram of an illustrative electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, an embodiment of one or more of a microelectronic device (e.g., the microelectronic device100previously described with reference toFIGS.1A through1C) and a memory device (e.g., the memory device200previously described with reference toFIGS.2A through2C) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, include an embodiment of one or more of a microelectronic device (e.g., the microelectronic device100previously described with reference toFIGS.1A through1C) and a memory device (e.g., the memory device200previously described with reference toFIGS.2A through2C) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG.3, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include an embodiment of one or more of a microelectronic device (e.g., the microelectronic device100previously described with reference toFIGS.1A through1C) and a memory device (e.g., the memory device200previously described with reference toFIGS.2A through2C) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308may comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304. Thus, in accordance with embodiments of the disclosure, an electronic system comprises an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device comprises a stack structure, contact structures, a microelectronic device, and vertically extending strings of memory cells. The stack structure has tiers comprising conductive structures and insulating structures vertically neighboring the conductive structures, and comprises a staircase region and a memory array region. The staircase region comprises staircase structures having steps comprising horizontal ends of the tiers. The memory array region horizontally neighbors the staircase region. The contact structures are on the steps of the staircase structures. The microelectronic device is electrically coupled to the contact structures and comprises transistors vertically overlying and within horizontal boundaries of the staircase region of the stack structure. Each of the transistors comprises a channel region comprising a 2D material, conductively doped regions neighboring opposing horizontal boundaries of the channel region and comprising the 2D material doped with at least one conductive dopant, and a gate structure vertically overlying and at least partially horizontally aligned with the channel region. The vertically extending strings of memory cells are within the memory array region of the stack structure. The structures, devices, and systems of the disclosure advantageously facilitate one or more of improved simplicity, greater packaging density, and increased miniaturization of components as compared to conventional structures, conventional devices, and conventional systems. For example, the configurations of the microelectronic devices (e.g., the microelectronic device100) of the disclosure facilitate robust memory device (e.g., the memory device200) architectures exhibiting more components, less component congestion, and/or smaller horizontal dimensions as compared to conventional microelectronic devices and conventional memory devices. The structures, devices, and systems of the disclosure may increase performance, scalability, efficiency, reliability, and simplicity as compared to conventional structures, conventional devices, and conventional systems. While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents. | 88,879 |
11943920 | DETAILED DESCRIPTION In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims. Please refer toFIG.1andFIG.2.FIG.1is a schematic diagram of a partial layout of a semiconductor memory device1according to an embodiment of the present invention, andFIG.2is a cross-sectional view taken along line I-I′ inFIG.1. The semiconductor memory device1may be a non-volatile memory, for example, a split-gate memory. As shown inFIG.1, the semiconductor memory device1includes a semiconductor substrate100, such as a silicon substrate, but is not limited thereto. A fin structure F extending along the first direction D1is provided on the semiconductor substrate100. In the second direction D2, the select gate SG and the control gate CG extend across the fin structure F. The select gate SG is adjacent to the control gate CG and at least one insulating layer is provided between the select gate SG and the control gate CG. According to an embodiment of the present invention, the select gate SG is a polysilicon electrode. According to an embodiment of the present invention, the control gate CG is a polysilicon electrode. As shown inFIG.1andFIG.2, the semiconductor memory device1includes the select gate SG disposed on the fin structure F of the semiconductor substrate100. The select gate SG includes a first sidewall SW1and a second sidewall SW2opposite to the first sidewall SW1. A flat top surface PS is disposed between the first sidewall SW1and the second sidewall SW2. According to an embodiment of the present invention, a metal silicide layer SAS is formed on the flat top surface PS of the select gate SG. As shown inFIG.1andFIG.2, the semiconductor memory device1further includes a control gate CG disposed on the fin structure F of the semiconductor substrate100and adjacent to the second sidewall SW2of the select gate SG. The control gate CG includes a third sidewall SW3in proximity to the second sidewall SW2, a fourth sidewall SW4opposite to the third sidewall SW3, and a non-planar top surface NPS between the third sidewall SW3and the fourth sidewall SW4. According to an embodiment of the present invention, the non-planar top surface NPS includes a first surface region S1descending from the third sidewall SW3to the fourth sidewall SW4, and a second surface region S2located between the first surface region S1and the fourth sidewall SW4. The slope of the second surface region S2is greater than the slope of the first surface region S1. According to an embodiment of the present invention, the non-planar top surface NPS further includes a third surface region S3connecting the second surface region S2and the fourth sidewall SW4. According to an embodiment of the present invention, the third surface region S3is lower than the first surface region S1and the second surface region S2. According to an embodiment of the present invention, the second surface region S2, the third surface region S3and the fourth sidewall SW4constitute a step structure SS. According to an embodiment of the present invention, a metal silicide layer SAC is formed on the non-planar top surface NPS of the control gate CG. According to an embodiment of the present invention, the semiconductor memory device1further includes a charge storage layer120disposed between the control gate CG and the fin structure F of the semiconductor substrate100. The charge storage layer120extends to the second sidewall SW2, and may protrude beyond the non-planar top surface NPS of the control gate CG. According to an embodiment of the present invention, the charge storage layer120directly contacts the metal silicide layer SAS on the flat top surface PS of the select gate SG. According to an embodiment of the present invention, the charge storage layer120is an oxide-nitride-oxide (ONO) layer. According to an embodiment of the present invention, the semiconductor memory device1further includes a spacer SP1disposed on the first sidewall SW1of the select gate SG and a spacer SP4disposed on the fourth sidewall SW4of the control gate CG The spacer SP1and the spacer SP4may include silicon nitride, silicon oxide, silicon oxynitride, or the like, but are not limited thereto. In addition, a drain region102may be formed in the fin structure F near the spacer SP1, and a source region104may be formed in the fin structure F near the spacer SP4. Please refer toFIG.3toFIG.15, which illustrate a method of forming a semiconductor memory device, in which the same regions, devices, layers or materials are designated by the same numeral numbers or labels. As shown inFIG.3, a polysilicon layer210, a silicon oxide layer211, and a hard mask layer220are deposited in the memory region MR and the logic circuit region LR on the substrate100. Lithography and etching processes are then performed to form select gates SG crossing the fin structure F in the memory region MR. At this point, the select gate SG includes a patterned polysilicon layer210a, a patterned silicon oxide layer211a, and a patterned hard mask layer220a. According to an embodiment of the present invention, the thickness of the polysilicon layer210aof the select gate SG is smaller than that of the polysilicon layer210in the logic circuit region LR. Subsequently, a charge storage layer120, for example, an oxide-nitride-oxide (ONO) layer, is conformally deposited on the memory region MR and the logic circuit region LR. As shown inFIG.4, next, a polysilicon layer230and a silicon oxide layer240are conformally deposited on the charge storage layer120. According to an embodiment of the present invention, the polysilicon layer230and the silicon oxide layer240cover the memory region MR and the logic circuit region LR. According to an embodiment of the present invention, the polysilicon layer230does not completely fill the space between two adjacent select gates SG. According to an embodiment of the present invention, the thickness of the silicon oxide layer240may be about 80-120 angstroms, for example, 100 angstroms. As shown inFIG.5, a first self-aligned anisotropic dry etching process is performed. The silicon oxide layer240is first selectively etched to form spacers on the polysilicon layer230. A second self-alignment is then performed. The polysilicon layer230is etched, thereby forming self-aligned polysilicon patterns240aand240bnext to the select gate SG in the memory region MR. The polysilicon pattern240aserves as the control gate CG of the semiconductor memory device. The second self-aligned anisotropic dry etching process is stopped when the surface of the charge storage layer120is revealed. According to an embodiment of the present invention, the control gate CG includes a non-planar top surface NPS including a first surface region S1and a second surface region S2. The slope of the second surface region S2is greater than the slope of the first surface region S1. According to an embodiment of the present invention, the non-planar top surface NPS further includes a third surface region S3connected to the second surface region S2. According to an embodiment of the present invention, the third surface region S3is lower than the first surface region S1and the second surface region S2. According to an embodiment of the present invention, the second surface region S2, the third surface region S3and the sidewall of the control gate CG constitute a step structure SS. As shown inFIG.6, next, a patterned photoresist layer PR is formed on the memory region MR and the logic circuit region LR, so that the patterned photoresist layer PR covers the control gate CG, while an opening OP of the patterned photoresist layer PR exposes the polysilicon pattern240bopposite to the control gate CG. According to an embodiment of the present invention, the patterned photoresist layer PR may partially cover the select gate SG. Subsequently, an anisotropic dry etching process is performed, using the patterned photoresist layer PR and the hard mask layer220aas an etching resist mask, to etch the exposed polysilicon pattern240buntil the underlying charge storage layer120is exposed. As shown inFIG.7, the remaining patterned photoresist layer PR is removed, and a spacer layer, such as an oxide-nitride-oxide (ONO) layer, is formed on the memory region MR and the logic circuit region LR by using a chemical vapor deposition process. An anisotropic dry etching process is then performed to etch the spacer layer thereby forming spacers310on the sidewalls of the select gate SG and the control gate CG. An ion implantation process is then performed to form a drain region102and a source region104in the fin structure F adjacent to the spacers310. As shown inFIG.8, the hard mask layer220aof the select gate SG in the memory area MR and the hard mask layer220of the logic circuit area LR are removed so as to reveal the silicon oxide layer211ain the memory area MR and the silicon oxide layer211in the logic circuit area LR. A chemical vapor deposition process is then performed to deposit a spacer layer, such as an oxide-nitride (ON) layer, on the memory region MR and the logic circuit region LR in a conformal manner. An anisotropic dry etching process is then performed to etch the spacer layer, thereby forming spacers410on the sidewalls of the select gate SG and the control gate CG. As shown inFIG.9, a gate patterning process is performed in the logic circuit area LR, and the silicon oxide layer211and the polysilicon layer210in the logic circuit area LR are patterned into a dummy gate structure DP using lithography and etching processes. As shown inFIG.10, a spacer layer, such as a silicon nitride layer, is conformally deposited on the memory region MR and the logic circuit region LR by using a chemical vapor deposition process. The spacer layer is then etched by an anisotropic dry etching process, thereby forming spacers on the sidewalls of the select gate SG and the control gate CG in the memory region MR, respectively, and spacers SP on the sidewalls of the dummy gate structure DP in the logic circuit region LR. According to an embodiment of the present invention, an ion implantation process is then performed to form doped regions502and504in the substrate100in the logic circuit region LR. As shown inFIG.11, a metal silicide process is then performed to form a metal silicide layer SAS on the select gate SG in the memory region MR, and a metal silicide layer SAC on the non-planar top surface NPS of the control gate CG. According to an embodiment of the present invention, the metal silicide layer SAS and the metal silicide layer SAC may include nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, etc., but are not limited thereto. According to an embodiment of the present invention, a metal silicide block layer SAB can be formed on the part where the metal silicide layer is not required to be formed, for example, the dummy gate structure DP in the logic circuit area LR. As shown inFIG.12toFIG.15, a replacement metal gate (RMG) process is subsequently performed. For example, as shown inFIG.12, a chemical vapor deposition process is first performed in the memory region MR and the logic circuit region LR to conformally deposit a contact etch stop layer610. For example, the contact etch stop layer610may be a silicon nitride layer. According to an embodiment of the present invention, the contact etching stop layer610may have tensile stress. As shown inFIG.13, a dielectric layer620is then deposited on the contact etch stop layer610by using a chemical vapor deposition process, and then the dielectric layer620is planarized by using a chemical mechanical polishing (CMP) process. Subsequently, as shown inFIG.14, the dummy gate structure DP in the logic circuit area LR is removed to form a gate trench GT. Finally, as shown inFIG.15, gate materials such as a high dielectric constant layer HK, a barrier layer BL, and a low resistance metal layer MG are sequentially formed in the gate trench GT. It is one technical feature of the present invention that the select gate SG is formed first, and then the charge storage layer120is formed, and then the control gate CG is formed in a self-aligned manner. In this way, a photomask can be saved, cost is reduced, and the control gate CG is formed in a self-aligned manner, which can solve the problems of overlay shift and insufficient read/write operation margin of the memory. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 13,298 |
11943921 | DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientation depicted in the figures. The device or apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Even more, the terms “first”, “second”, “third”, “fourth”, and the like are merely generic identifiers and, as such, may be interchanged in various embodiments. For example, while an element (e.g., an opening) may be referred to as a “first” element in some embodiments, the element may be referred to as a “second” element in other embodiments. According to some methods for manufacturing an integrated circuit (IC) with embedded memory technology, a memory device is firstly formed on a memory region of a substrate including forming a pair of floating gate electrodes insulated by dielectric material, forming a pair of control gate electrodes over the floating gate electrodes, and forming a pair of select gate on opposite sides of the pair of control gate electrodes. Then, the memory device is covered and protected by a dummy capping layer, and a logic gate electrode is formed on a logic region next to the memory region and separated from the substrate by a logic gate dielectric. Then, the dummy capping layer is removed to expose the formed memory device, and a sidewall spacer is formed on sidewall surfaces of both the select gate electrodes of the memory device and the logic gate electrode of the logic device. Source/drain regions are subsequently formed within the substrate alongside the select gate electrodes of the memory device and the logic gate electrode of the logic device. A challenge with the methods described above is that the formation of the sidewall spacer on the sidewall surfaces of the select gate electrodes further narrows the lateral spaces between adjacent select gate electrodes. Since memory device has a higher gate height than that of the logic device, a narrow lateral space between adjacent select gate electrodes would result in a high aspect ratio for subsequent inter-layer dielectric (ILD) material filling-in for the memory device. As a result, voids could be formed between adjacent memory cells. The voids may lead to defects during subsequent manufacturing processes. For example, when forming plugs or contacts, the filled inter-layer dielectric material is etched to form a trench that is filled with conductive material. The voids within the inter-layer dielectric material may introduce unwanted shorting or bridging. In view of the foregoing, various embodiments of the present application are directed to an integrated circuit (IC) comprising an embedded memory and a method for forming the IC. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic device, but not disposed along a sidewall surface of the memory cell structure. As a result, the later formed contact etch stop layer (CESL) may contact the sidewall spacer within the logic region and directly contact the memory cell structure within the memory region. Thus, the inter-layer dielectric (ILD) fill-in spaces between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved. FIG.1shows a cross-sectional view an IC100according to some embodiments. The IC100has a substrate104including a memory region104mand a logic region104l. A plurality of memory cell structures108a,108bis disposed on the memory region104m, and a logic device110is disposed on the logic region104l. An inter-layer dielectric (ILD) layer162is filled between and overlying the plurality of memory cell structures108a,108band the logic device110. In some embodiments, a sidewall spacer160is disposed alongside the logic device110, and is absent from the memory cell structure108b. Thus, a space between adjacent memory cell structures (e.g. between the memory cell structures108aand108b) is broadened, compared to a memory device where the sidewall spacer160is formed alongside the memory cell structures108a,108b. The inter-layer dielectric (ILD) layer162is thereby better filled in the space, and voids are reduced or eliminated therein. It is noted that for simplicity, only components of the memory cell structure108bis labeled inFIG.1and described hereafter, however, the memory cell structure108aand other memory cell structures not shown or labeled inFIG.1could have same or different components than the memory cell structure108b. The substrate104may comprise, for example, a bulk silicon substrate, a group III-V substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate(s). In some embodiments, the memory cell structure108bcomprises a pair of individual memory source/drain regions126, a common memory source/drain region128, and a pair of selectively-conductive memory channels130. The individual memory source/drain regions126and the common memory source/drain region128are in a top of the substrate104, and the common memory source/drain region128is laterally spaced between the individual memory source/drain regions126. Further, the individual memory source/drain regions126and the common memory source/drain region128are doped semiconductor regions having a first doping type (e.g., p-type or n-type). The selectively-conductive memory channels130are doped semiconductor regions having a second doping type (e.g., p-type or n-type) opposite the first doping type. A pair of floating gate dielectric layers132, a pair of floating gate electrodes134, a pair of control gate dielectric layers136, and a pair of control gate electrodes138are stacked on the selectively-conductive memory channels130. For ease of illustration, only one of the floating gate dielectric layers132is labeled132, only one of the floating gate electrodes134is labeled134, only one of the control gate dielectric layers136is labeled136, and only one of the control gate electrodes138is labeled138. The floating gate dielectric layers132respectively overlie the selectively-conductive memory channels130and may be or otherwise comprise, for example, silicon oxide or some other suitable dielectric(s). The floating gate electrodes134respectively overlie the floating gate dielectric layers132, the control gate dielectric layers136respectively overlie the floating gate electrodes134, and the control gate electrodes138respectively overlie the control gate dielectric layers136. In some embodiments, a pair of control gate hard masks210respectively overlies the control gate electrodes138. The control gate hard masks210may each be or otherwise comprise, for example, silicon nitride, silicon oxide, some other suitable dielectric(s), or any combination of the foregoing. In some alternative embodiments, some or all of the control gate hard masks210may not present in the final device structure. The control gate electrodes138and the floating gate electrodes134may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s). The control gate dielectric layers136may be or otherwise comprise, for example, silicon nitride, silicon oxide, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the control gate dielectric layers136each comprise ONO films, such that the control gate dielectric layers136each comprise a lower oxide layer, an upper oxide layer, and a middle nitride layer sandwiched between the lower an upper oxide layers. A pair of control gate spacers140overlies each of the floating gate electrodes134. The control gate spacers140of each floating gate electrode respectively line opposite sidewalls of each of the corresponding control gate electrodes138. For ease of illustration, only some of the control gate spacers140are labeled140. Floating gate spacers142respectively overlie the selectively-conductive memory channels130, each laterally spaced from the common memory source/drain region128by a respective one of the floating gate electrodes134. Further, the floating gate spacers142each line a sidewall of the respective one of the floating gate electrodes134. The control gate spacers140and the floating gate spacers142may be or otherwise comprise, for example, silicon nitride, silicon oxide, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the control gate spacers140are each ONO films, the constituents of which are not shown for ease of illustration. An erase gate electrode144and an erase gate dielectric layer146overlie the common memory source/drain region128, laterally between the floating gate electrodes134. The erase gate electrode144overlies the erase gate dielectric layer146and, in some embodiments, has a top surface even with top surfaces respectively of the control gate electrodes138. The erase gate dielectric layer146cups an underside of the erase gate electrode144to vertically space the erase gate electrode144from the common memory source/drain region128, and to laterally space the erase gate electrode144from the floating gate electrodes134and the control gate spacers140. The erase gate electrode144may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s). The erase gate dielectric layer146may be or otherwise comprise, for example, silicon oxide, silicon nitride, or some other suitable dielectric(s). A pair of select gate dielectric layers148and a pair of select gate electrodes150are stacked on the selectively-conductive memory channels130. For ease of illustration, only one of the select gate dielectric layers148is labeled148. The select gate dielectric layers148respectively overlie the selectively-conductive memory channels130, each laterally spaced from the common memory source/drain region128by a respective one of the floating gate electrodes134. The select gate dielectric layers148may be or otherwise comprise, for example, silicon oxide, silicon nitride, or some other suitable dielectric(s). The select gate electrodes150may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s). The memory cell structure108bmay be or otherwise comprise, for example, third generation embedded superflash (ESF3) memory, first generation embedded superflash (ESF1) memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, or some other suitable type(s) of memory. The logic device110may be or otherwise comprise, for example, an insulated field-effect transistor (IGFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a double-diffused metal-oxide-semiconductor (DMOS) device, a bipolar complementary metal-oxide-semiconductor (CMOS) DMOS (BCD) device, some other suitable transistor device(s), or some other suitable semiconductor device(s). In some embodiments, the logic device110comprises a pair of logic source/drain regions152and a selectively-conductive logic channel154. Further, the logic source/drain regions152are doped semiconductor regions having a first doping type (e.g., p-type or n-type). Further, the selectively-conductive logic channel154is a doped semiconductor region having a second doping type (e.g., p-type or n-type) opposite the first doping type. A logic gate dielectric layer156overlies the selectively-conductive logic channel154, and a logic gate electrode158overlies the logic gate dielectric layer156. The logic gate electrode158may be or otherwise comprise conductive material, for example, doped polysilicon or some other suitable conductive material(s). The logic gate dielectric layer156may be or otherwise comprise, for example, silicon nitride, silicon oxide, a high κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. As used herein, a high κ dielectric is a dielectric with a dielectric constant κ greater than about 3.9. In some embodiments, the sidewall spacer160lines sidewall surfaces of the logic gate electrode158and the logic gate dielectric layer156. The sidewall spacers160may be or otherwise comprise, for example, silicon nitride, silicon oxide, or some other suitable dielectric(s). Further, in some embodiments, a contact etch stop layer (CESL)166is disposed along a top surface of the substrate104, extending upwardly along sidewall surfaces of the pair of select gate electrodes150within the memory region104m, and extending upwardly along a sidewall surface of the sidewall spacer160within the logic region104l. The contact etch stop layer (CESL)166is in direct contact with the sidewall surfaces of the pair of select gate electrodes150and separated from the sidewall surface of the logic gate electrode158by the sidewall spacer160. An inter-layer dielectric (ILD) layer162is disposed on the contact etch stop layer (CESL)166, covers the memory cell structures108a,108b, and the logic device110. The inter-layer dielectric (ILD) layer162may be or otherwise comprise, for example, silicon oxide, silicon nitride, a low κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. As used herein, a low κ dielectric is a dielectric with a dielectric constant κ less than about 3.9. Further yet, in some embodiments, contact vias164extend through the inter-layer dielectric (ILD) layer162to the logic source/drain regions152and the individual memory source/drain regions126. The contact vias164are conductive and may be or otherwise comprise, for example, tungsten, aluminum copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s). In some embodiments, silicide pads312respectively overlie the logic source/drain regions152, the individual memory source/drain regions126, the erase gate electrode144, the select gate electrodes150and/or the logic gate electrode158. For ease of illustration, only some of the silicide pads312are labeled312. The silicide pads312may be or otherwise comprise, for example, be nickel silicide or some other suitable silicide(s). With reference toFIG.2, an enlarged cross-sectional view200of some embodiments of the memory cell structure108binFIG.1is provided. In some embodiments, the control gate dielectric layer136comprises a lower oxide layer118l, an upper oxide layer118uoverlying the lower oxide layer118l, and a middle nitride layer118mvertically sandwiched between the lower oxide layer118land the upper oxide layer118u. The control gate spacers140may also comprise a middle nitride layer sandwiched between two oxide layers. With reference toFIG.3, a cross-sectional view300of some additional embodiments of the IC ofFIGS.1and2are provided. As illustrated, in some embodiments, the logic gate dielectric layer156is a high κ dielectric and the logic gate electrode158is metal. The select gate electrodes150, the erase gate electrode144, the control gate electrodes138, and the floating gate electrodes134are doped polysilicon. A first logic device110aand a second logic device110bare on the logic region104lof the substrate104, physically and electrically separated by a logic isolation structure310laterally between the first and second logic devices110a,110b. The logic isolation structure310may be or otherwise comprise, for example, an STI structure, a DTI structure, or some other suitable isolation structure(s). The first and second logic devices110a,110bmay each be, for example, an IGFET, a MOSFET, a DMOS device, a BCD device, some other suitable transistor device(s), or some other suitable semiconductor device(s). In some embodiments, the first logic device110ais an IGFET and the second logic device110bis a power MOFSET configured to operate at higher voltages (e.g., voltages an order of magnitude higher) than the second logic device110b. The power MOSFET may be or otherwise comprise, for example, a double-diffused metal-oxide-semiconductor (DMOS) device or some other suitable power MOSFET(s). The first and second logic devices110a,110beach comprise a pair of logic source/drain regions152and a selectively-conductive logic channel154. For ease of illustration, only some of the logic source/drain regions152are labeled152. The logic source/drain regions152of each pair are in a top of the substrate104and are laterally spaced. Further, the logic source/drain regions152of each pair are doped semiconductor regions having a first doping type (e.g., p-type or n-type). The selectively-conductive logic channels154is a doped semiconductor region having a second doping type (e.g., p-type or n-type) opposite the first doping type of the respective pair of logic source/drain regions152. The first logic device110aand the second logic device110bmay have different gate dielectric compositions for different operation voltages. As an example for non-limiting example, a first logic gate dielectric layer156a, a second logic gate dielectric layer156b, and a logic gate electrode158are stacked on the selectively-conductive logic channel154of the first logic device110a, while the first logic gate dielectric layer156ais absent from the second logic device110b. The logic gate electrodes158may be or otherwise comprise, for example, metal, or some other suitable conductive material(s). The first and second logic gate dielectric layer156a,156bmay be or otherwise comprise, for example, silicon nitride, silicon oxide, a high κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the first logic gate dielectric layers156aare silicon oxide and high κ dielectric stack, the second logic gate dielectric layers156bare thicker silicon oxide and high κ dielectric stack, and the logic gate electrodes158are metal. In some embodiments, the sidewall spacers160comprise a plurality of sidewall spacers respectively lining sidewalls of the logic gate electrodes158. A lower ILD layer162land an upper ILD layer162uare stacked on the substrate104and accommodate the contact vias164. For ease of illustration, only some of the contact vias164are labeled164. The lower ILD layer162lis to the sides of the memory cell structure108and to the sides of the first and second logic devices110a,110b. Further, the lower ILD layer162lhas a top surface that is even (e.g., planar or substantially planar) with a top surface of the memory cell structure108, a top surface of the cell boundary structure102, a top surface of the logic boundary structure304, a top surface of the first logic device110a, and a top surface of the second logic device110b. The upper ILD layer162ucovers the lower ILD layer162l, the memory cell structure108, the cell boundary structure102, the logic boundary structure304, the first logic device110a, and the second logic device110b. The lower and upper ILD layers162l,162umay be or otherwise comprise, for example, silicon oxide, silicon nitride, a low κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. Further, in some embodiments, the control gate spacers140overlying the floating gate electrodes134are or otherwise comprise ONO films, and/or silicide pads312respectively overlie the erase gate electrode144, the select gate electrodes150, the logic source/drain regions152, and the individual memory source/drain regions126. For ease of illustration, only one of the control gate spacers140is labeled140, and only some of the silicide pads312are labeled312. The ONO films may, for example, each comprises a first oxide layer140f, a second oxide layer140s, and a middle nitride layer140mlaterally sandwiched between the first and second oxide layers140f,140s. The silicide pads312may be or otherwise comprise, for example, be nickel silicide or some other suitable silicide(s). With reference toFIGS.4-26, a series of cross-sectional views400-2600illustrates some embodiments of a method for forming an IC comprising an embedded memory with no sidewall spacer within the memory region. As illustrated by the cross-sectional view400ofFIG.4, a substrate104is prepared including a memory region104mand a logic region104l. In some embodiments, a sacrificial lower pad layer402′ is formed covering the substrate104, and a sacrificial upper pad layer404′ is formed covering the sacrificial lower pad layer402′. The sacrificial lower pad layer402′ and the sacrificial upper pad layer404′ are formed of different materials and may, for example, be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, thermal oxidation, or some other suitable growth or deposition process(es). As used herein, a term (e.g., process) with a suffix of “(es)” may, for example, be singular or plural. The sacrificial lower pad layer402′ may, for example, be formed of silicon oxide or some other suitable dielectric(s), and/or the sacrificial upper pad layer404′ may, for example, be formed by silicon nitride or some other suitable dielectric(s). As illustrated by the cross-sectional view500ofFIG.5, the substrate104is recessed within the memory region104mand a sacrificial dielectric layer502is formed within the memory region104m. In some embodiments, the sacrificial upper pad layer404′ is patterned (according to a masking layer504) to form an opening corresponding to the memory region104mand to cover a logic region104l. A precursor layer502′ is formed from a top surface of the substrate104, and thus reduces a height of the top surface of the substrate104within the memory region104m. In some embodiments, the precursor layer502′ is an oxide layer and formed by a wet process or a thermal process. The precursor layer502′ is subsequently partially removed and a lower remaining portion of the precursor layer502′ forms the sacrificial dielectric layer502. As illustrated by the cross-sectional view600ofFIG.6, the sacrificial dielectric layer502and the sacrificial lower pad layer402′ (seeFIG.5) may be removed and replaced with a memory dielectric layer604in the memory region104mand a lower pad layer402in the logic region104l. The sacrificial upper pad layer404′ is removed and replaced with a memory pad layer602formed on the memory dielectric layer604in the memory region104mand an upper pad layer404formed on the lower pad layer402in the logic region104l. The memory pad layer602and the upper pad layer404may be a dielectric material deposited as one conformal layer. Then the portion of the conformal dielectric material in the memory region104mis etched and patterned to have a top surface aligned with that of the portion of the conformal dielectric material in the logic region104l. Then, isolation structures are formed through the memory pad layer602and/or upper pad layer404including a logic isolation structure310within the logic region104l. The isolation structure310divides the logic region104linto a first logic region104l1and a second logic region104l2. The first logic region104l1may, for example, support core logic devices formed hereafter, whereas the second logic region104l2may, for example, support high voltage logic devices formed hereafter. The high voltage logic devices may, for example, be logic devices configured to operate at higher voltages (e.g., an order of magnitude higher) than the core logic devices. The logic isolation structure310may, for example, comprise a dielectric material, and/or may be or otherwise comprise, for example, a STI structure, a DTI structure, or some other suitable isolation region(s). In some embodiments, a process for forming the logic isolation structure310and/or other isolation structures, such as isolation structures within the memory region104m, comprises patterning the lower and upper pad layers402,404with layouts of the logic isolation structure310and/or other isolation structures, and an etch is performed into the substrate104with the lower and upper pad layers402,404in place to form trenches with the layouts. A dielectric layer is formed filling the trenches, and a planarization is performed to the upper pad layer404to form the isolation structures in the trenches. The dielectric layer may, for example, be formed of silicon oxide or some other suitable dielectric material(s), and/or may, for example, be performed by CVD, PVD, sputtering, or some other suitable deposition process(es). The planarization may, for example, be performed by a chemical mechanical polish (CMP) or some other suitable planarization process(es). The patterning may, for example, be performed using photolithography and an etching process. As illustrated by the cross-sectional views700-1800ofFIGS.7-18, a series of manufacturing processes is performed so as a memory cell structure is formed on the memory region104mfrom a multilayer memory film, while leaving a remainder of the multilayer memory film on the logic region104l. Some of the manufacturing processes are described below as an example and not for limiting purpose. As illustrated by the cross-sectional view700ofFIG.7, the memory pad layer602and the sacrificial dielectric layer502(referred toFIG.6) are removed, and a memory dielectric layer706and a floating gate layer702are formed on the memory region104m. In some embodiments, a capping layer704is formed and patterned to act as a masking layer for forming and patterning the floating gate layer702. In some embodiments, the capping layer704may comprise one or more dielectric layers. For example, the capping layer704may comprise a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer. The capping layer704is formed and patterned to have an opening corresponding to the memory region104m, and to cover the logic region104l. The floating gate layer702is firstly formed over the memory dielectric layer706covering the memory region104mand formed over the capping layer704covering the logic region104l. The floating gate layer702may, for example, be formed conformally, and/or may, for example, be formed of doped polysilicon, metal, or some other suitable conductive material(s). In some embodiments, the floating gate layer702is formed by CVD, PVD, or some other suitable deposition process(es). Then, a planarization is performed into a top of the floating gate layer702until the capping layer704is reached, thereby removing the floating gate layer702from the capping layer704. In some embodiments, the planarization recesses a topmost surface of the floating gate layer702to about even with a topmost surface of the capping layer704. The planarization may, for example, be performed by a CMP or some other suitable planarization process(es). As illustrated by the cross-sectional view800ofFIG.8, the floating gate layer702is further lowered for better couple ratio. The floating gate layer702may be lowered by a wet etching back process. After lowering the floating gate layer702, the capping layer704may be subsequently removed. For example, at least the silicon oxide layer of the capping layer may be removed during or after lowering the floating gate layer702. As illustrated by the cross-sectional view900ofFIG.9, a multilayer memory film is formed covering the floating gate layer702and the upper pad layer404. The multilayer memory film comprises a control gate dielectric layer902, a control gate layer904, and a control gate hard mask layer906. In some embodiments, the control gate dielectric layer902comprises silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. For example, the control gate dielectric layer902may be an ONO film, and/or may comprise a lower oxide layer902l, a middle nitride layer902mcovering the lower oxide layer902l, and an upper oxide layer902ucovering the middle nitride layer902m. The control gate dielectric layer902may, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing. The control gate layer904is formed covering the control gate dielectric layer902. The control gate layer904may, for example, be formed conformally, and/or may, for example, be formed of doped polysilicon, metal, or some other suitable conductive material(s). Further, in some embodiments, the control gate layer904is formed by CVD, PVD, or some other suitable deposition process(es). The control gate hard mask layer906is formed covering the control gate layer904. In some embodiments, the control gate hard mask layer906comprises silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. For example, the control gate hard mask layer906may be a nitride-oxide-nitride (NON) film, and/or may comprise a lower nitride layer906l, a middle oxide layer906mcovering the lower nitride layer906l, and an upper nitride layer906ucovering the middle oxide layer906m. The control gate hard mask layer906may, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing. As illustrated by the cross-sectional view1000ofFIG.10, an etch is performed into the multilayer memory film to remove portions of the multilayer memory film from the memory region104m, thereby forming a pair of control gate electrodes138on the floating gate layer702. Further, the etch forms a pair of control gate dielectric layers136and a pair of control gate hard masks210. The control gate dielectric layers136respectively underlie the control gate electrodes138, and the control gate hard masks210respectively overlie the control gate electrodes138. In some embodiments, a process for performing the etch comprises forming and patterning a masking layer (e.g. a photoresist layer not shown in the figure) on the multilayer memory film so as to cover the logic region104l, and so as to partially cover the memory region104mwith a layout of the control gate electrodes138. An etchant is then applied to the multilayer memory film with the masking layer in place until the etchant reaches the floating gate layer702, and the masking layer is thereafter removed. As illustrated by the cross-sectional view1100ofFIG.11, a control gate spacer layer1102is formed covering and lining the structure ofFIG.10. The control gate spacer layer1102may, for example, be formed conformally, and/or may, for example, be formed of silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the control gate spacer layer1102is or otherwise comprise an ONO film, and/or comprises a lower oxide layer1102l, a middle nitride layer902moverlying the lower oxide layer902l, and an upper oxide layer1102uoverlying the middle nitride layer1102m. Further, the control gate spacer layer1102may, for example, be formed by CVD, PVD, or some other suitable deposition process(es). As illustrated by the cross-sectional view1200ofFIG.12, a first etch is performed into the control gate spacer layer1102(seeFIG.11) to form a control gate spacer140along sidewalls of the control gate electrodes138. In some embodiments, a process for performing the etch comprises applying one or more etchants to the control gate spacer layer1102until horizontal segments of the control gate spacer layer1102are removed. Then, a second etch is performed into the floating gate layer702and the memory dielectric layer706(seeFIG.11), with the control gate spacers140in place, to form a pair of floating gate electrodes134and a pair of floating gate dielectric layers132. The floating gate electrodes134respectively underlie the control gate electrodes138and are formed from the floating gate layer702. The floating gate dielectric layers132respectively underlie the floating gate electrodes134and are formed from the memory dielectric layer706. During the etch, the control gate spacers140and the control gate hard masks210serve as a mask. As illustrated by the cross-sectional view1300ofFIG.13, a floating gate spacer142is formed on sidewalls of the floating gate electrodes134and the control gate spacers140. In some embodiments, the floating gate spacer142comprises silicon oxide, some other suitable oxide(s), or some other suitable dielectric(s). Further, in some embodiments, a process for forming the floating gate spacer142comprises depositing a floating gate spacer layer followed by an etch to remove horizontal segments of the floating gate spacer layer without removing vertical segments of the floating gate spacer layer. The floating gate spacer layer may, for example, be deposited conformally, and/or may, for example, be formed by CVD, PVD, or some other suitable deposition process(es). Then, common memory source/drain region128is formed in the substrate104, laterally between the floating gate electrodes134. In some embodiments, a process for forming the common memory source/drain region128comprises forming and patterning a masking layer1302covering the logic region104land the memory region104moutside a common source/drain gap laterally between the floating gate electrodes134. Ion implantation or some other suitable doping process(es) is performed with the masking layer1302in place, and the masking layer is thereafter removed. As illustrated by the cross-sectional view1400ofFIG.14, an erase gate dielectric layer146is formed covering the common memory source/drain region128, and further lining sidewalls of the floating gate electrodes134and sidewalls of the control gate spacers140within the common source/drain gap. The erase gate dielectric layer146may, for example, be formed of oxide, nitride, or some other suitable dielectric(s). In some embodiments, a process for forming the erase gate dielectric layer146comprises high temperature oxidation (HTO), in situ steam generation (ISSG) oxidation, some other suitable deposition or growth process(es), or any combination of the foregoing. Further, in some embodiments, the process comprises removing dielectric material that forms on portions of the memory region104moutside the common source/drain gap. Then, a memory dielectric layer1402is formed covering portions of the memory region104mon opposite sides of the floating gate electrodes134. The memory dielectric layer1402may, for example, be formed of oxide, nitride, or some other suitable dielectric(s). The memory dielectric layer1402may, for example, be formed by HTO, ISSG oxidation, some other suitable deposition or growth process(es), or any combination of the foregoing. A memory gate layer1404and a memory hard mask layer1406are formed on the memory dielectric layer1402. The memory gate layer1404may, for example, be formed conformally, and/or may, for example, be formed of doped polysilicon, metal, or some other suitable conductive material(s). The memory gate layer1404may, for example, be formed by CVD, PVD, or some other suitable deposition process(es). As illustrated by the cross-sectional view1500ofFIG.15, the memory hard mask layer1406(seeFIG.14) is patterned to form a pair of select gate hard masks208on opposite sides of the common memory source/drain region128and an erase gate hard mask212overlying the common memory source/drain region128. Then, an etch is performed into the memory gate layer1404and the memory dielectric layer1402(seeFIG.14) with the select gate hard masks208and the erase gate hard mask212in place to form a pair of select gate electrodes150, an erase gate electrode144, and a pair of select gate dielectric layers148. As illustrated by the cross-sectional view1600ofFIG.16, a first hard mask ARC1602is formed covering the structure described above followed by a planarization process. As such, a top surface of the first hard mask ARC1602, top surfaces of the hard masks210,212,208, and a top surface of the control gate hard mask layer906are etched back together once the first hard mask ARC1602is sufficiently etched to expose lower portions of the hard masks210,212,208, and the control gate hard mask layer906. The first hard mask ARC1602may be formed by a coating process or may be deposited by, for example, CVD, PVD, or some other suitable deposition process(es). The planarization may, for example, be performed by a CMP or some other suitable planarization process(es). As illustrated by the cross-sectional view1700ofFIG.17, in some embodiments, the first hard mask ARC1602(seeFIG.16) is removed after the etch by, for example, another etching process or some other suitable removal process(es). A dummy liner layer1702is formed covering the structure ofFIG.16. The dummy liner layer1702may, for example, be formed conformally. In some embodiments, the dummy liner layer1702is formed of silicon oxide or some other suitable dielectric(s). A dummy capping layer1704is formed covering the dummy liner layer1702. In some embodiments, the dummy capping layer1704is formed of polysilicon or some other suitable material(s). Further, the dummy liner layer1702and/or the dummy capping layer1704may, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing, followed by a planarization process. As illustrated by the cross-sectional view1800ofFIG.18, within the logic region104l, an etch is performed into the dummy capping layer1704, the dummy liner layer1702, the control gate layer904, the control gate dielectric layer902, the upper pad layer404, and the lower pad layer402(seeFIG.17). In some embodiments, the etch is performed by forming and patterning a photoresist layer1802covering the memory region104m. An etchant is then applied with the photoresist layer1802in place until the etchant reaches an upper surface of the substrate104, and the photoresist layer1802is thereafter stripped. As illustrated by the cross-sectional view1900ofFIG.19, a logic device is formed within the logic region104l. In some embodiments, a variety of the logic devices are formed within the logic region104lwith varies gate dielectric and gate electrode compositions. As an example, a first logic device110ais formed in the first logic region104l1, and a second logic device110bis formed in the second logic region104l2. The first logic device110aand the second logic device110bmay be formed by forming a first logic gate dielectric layer156aand a second logic gate dielectric layer156brespectively in the first logic region104l1and the second logic region104l2. The second logic gate dielectric layer156bcan be formed by depositing and patterning a HV dielectric layer1902in the second logic region104l2and absent from the first logic region104l1. A logic dielectric layer is then formed and patterned on the HV dielectric layer1902in the second logic region104l2to form the first logic gate dielectric layer156aand directly on the substrate104in the first logic region104l1to form the second logic gate dielectric layer156bcollectively with the HV dielectric layer1902. Though not shown in the figure, the logic dielectric layer may comprise one or multiple oxide or other dielectric layers and may be formed and patterned with varies compositions and thicknesses in different logic regions of the substrate104. Further, a logic gate layer is formed and patterned on the first logic gate dielectric layer156ato form a first logic gate electrode158ain the first logic region104l1, and on the second logic gate dielectric layer156bto form a second logic gate electrode158bin the second logic region104l2. The HV dielectric layer1902may, for example, be formed of oxide, a high κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. The HV dielectric layer1902may be formed conformally, and/or are formed by CVD, PVD, some other suitable growth or deposition process(es), or any combination of the foregoing. The logic dielectric layer may, for example, be formed of oxide, a high κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. The logic gate layer may, for example, be formed of doped or undoped polysilicon, metal, some conductive material, or some other suitable material(s). In some embodiments, the logic dielectric layer and the logic gate layer are formed conformally, and/or are formed by CVD, PVD, electroless plating, electroplating, some other suitable growth or deposition process(es), or any combination of the foregoing. As illustrated by the cross-sectional view2000ofFIG.20, still with the dummy capping layer1704in place, a sidewall spacer160is formed along sidewalls of the logic gate electrodes158a,158b. The select gate electrodes150are covered by the dummy liner layer1702and the dummy capping layer1704, such that the sidewall spacer160is not formed alongside the select gate electrodes150. Compared to an alternative approach where the dummy capping layer1704and the dummy liner layer1702are removed from sides of the select gate electrodes150, and the sidewall spacer160is formed alongside the select gate electrodes150, a lateral space between adjacent select gate electrodes150is widened. Thus, the fill-in window for an inter-layer dielectric, which will be filled in the lateral space later (for example, as illustrated by the cross-sectional view2300ofFIG.23), is increased. Voids would be decreased, and the fill-in quality for the inter-layer dielectric would be improved. In some embodiments, the sidewall spacer160comprises silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. Further, in some embodiments, a process for forming the sidewall spacer160comprises depositing a spacer layer covering and lining the structure ofFIG.20. An etch back is then performed into the spacer layer to remove horizontal segments of the spacer layer without removing vertical segments of the spacer layer. The spacer layer may, for example, be deposited conformally, and/or may, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing. As illustrated by the cross-sectional view2100ofFIG.21, an etch is performed to the dummy capping layer1704and the dummy liner layer1702to be removed from the memory region104m. In some embodiments, a masking layer2102is used to cover and protect the logic devices110a,110bfrom etching. The etch may comprise a series of dry and/or wet etching processes. The masking layer2102may be formed by photoresist. As illustrated by the cross-sectional view2200ofFIG.22, individual memory source/drain regions126are formed within the memory region104m, respectively bordering the select gate electrodes150. Also, logic source/drain regions152are formed in pairs within the logic region104l, with the source/drain regions of each pair respectively bordering opposite sidewalls of the logic gate electrodes158a,158b. In some embodiments, a process for forming the individual memory source/drain regions126and the logic source/drain regions152comprises ion implantation into the substrate104. In other embodiments, some process other than ion implantation is used to form the individual memory source/drain regions126and the logic source/drain regions152. Also illustrated by the cross-sectional view2200ofFIG.22, silicide pads312are formed on the individual memory source/drain regions126and the logic source/drain regions152. For ease of illustration, only some of the silicide pads312are labeled312. The silicide pads312may be or otherwise comprise, for example, be nickel silicide or some other suitable silicide(s), and/or may, for example, be formed by a salicide process, or some other suitable growth process(es). As illustrated by the cross-sectional view2300ofFIG.23, a contact stop etch layer (CSEL)166and a lower inter-layer dielectric (ILD) layer162lare formed covering the structure ofFIG.22. The lower ILD layer162lmay, for example, be oxide, a low κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. The lower ILD layer162lmay, for example, be deposited by CVD, PVD, sputtering, or any combination of the foregoing followed by a planarization process. As illustrated by the cross-sectional view2400ofFIG.24, a planarization process is performed to the lower inter-layer dielectric (ILD) layer162land the contact stop etch layer (CSEL)166. The planarization process may also remove the control, select, and erase gate hard masks210,208,212and expose the corresponding gate electrodes. The planarization process may, for example, a CMP or some other suitable planarization process(es). The lower ILD layer162lis formed with a top surface that is coplanar or substantially coplanar with top surfaces of the remaining structure. The planarization process may, for example, a CMP or some other suitable planarization process(es). The planarization process may also recess a top surface of the lower ILD layer162lto about even with top surfaces of the logic gate electrodes158a,158b, thereby exposing the logic gate electrodes158a,158b, the erase gate electrode144and the select gate electrodes150. Though not shown inFIG.24, in some embodiments, silicide pads may also be formed on the erase gate electrode144and the select gate electrodes150similar as shown inFIG.3after the planarization process. As illustrated by the cross-sectional view2500ofFIG.25, a replacement gate process is then performed: an etch is performed into the logic gate electrodes158a,158bto remove the logic gate electrodes158a,158b. In some embodiments, the etch is performed with a masking layer in place to protect other regions of the structure until the logic gate electrodes158a,158bare removed. Metal gate electrodes158a′,158b′ are then formed in place of the logic gate electrodes158a,158b. The metal gate electrodes158a′,158b′ may, for example, be metal, a different material than the logic gate electrodes158a,158b, or some other suitable conductive material(s). In some embodiments, a process for forming the metal gate electrodes158a′,158b′ comprises forming a conductive layer by, for example, by CVD, PVD, electroless plating, electroplating, or some other suitable growth or deposition process(es). A planarization is then performed into the conductive layer until the lower ILD layer162lis reached. The planarization may, for example, be performed by a CMP or some other suitable planarization process(es). As illustrated by the cross-sectional view2600ofFIG.26, an upper ILD layer162uis formed covering the structure ofFIG.25and with a top surface that is planar or substantially planar. The upper ILD layer162umay, for example, be oxide, a low κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. Further, the upper ILD layer162umay, for example, be formed depositing the upper ILD layer162u, and subsequently performing a planarization into the top surface of the upper ILD layer162u. The deposition may, for example, be performed by CVD, PVD, sputtering, or any combination of the foregoing. The planarization may, for example, be performed by a CMP or some other suitable planarization process(es). Also illustrated by the cross-sectional view2600ofFIG.26, contact vias164are formed extending through the upper ILD layer162uand the lower ILD layer162lto the individual memory source/drain regions126, the logic source/drain regions152, the common memory source/drain region128, the control gate electrodes138, the select gate electrodes150, the erase gate electrode144, the logic gate electrodes158a,158b, or any combination of the foregoing. With reference toFIG.27, a flowchart2700of some embodiments of a method for forming an IC comprising an embedded memory boundary structure with a boundary sidewall spacer is provided. The IC may, for example, correspond to the IC ofFIGS.4-26. At2702, a substrate is provided. The substrate comprises a memory region and a logic region. A memory dielectric layer is formed in memory region. See, for example,FIG.4. At2704, the substrate is recessed within the memory region. A memory dielectric layer is formed within the memory region. See, for example,FIG.5. At2706, a multilayer memory film is formed within the memory region covering the substrate. See, for example,FIGS.6-9. At2708, memory cell structures are formed within the memory region from the multilayer memory film. See, for example,FIGS.10-16. At2710, a dummy capping layer is formed in the memory covering the memory cell structures. Then a logic device is formed within the logic region with the memory region protected by the dummy capping layer. See, for example,FIGS.17-19. At2712, with the dummy capping layer still in place covering the memory region, a sidewall spacer is formed alongside the logic device within the logic region. As a result, the sidewall spacer is not formed in memory region. See, for example,FIG.20. At2714, the dummy capping layer is removed the memory region. See, for example,FIG.21. At2716, source/drain regions are in memory region and logic regions. See, for example,FIG.22. At2718, a lower inter-layer dielectric layer is formed to fill spaces between the memory device structures in memory region and the logic devices within the logic region. An aspect ratio between memory devices is lowered for the inter-layer dielectric layer's filling in because of the absence of the sidewall spacer in memory region. See, for example,FIG.23. At2720, a replacement gate process is performed to replace the logic gate electrodes by metal gate electrodes for the logic devices within the logic region. See, for example,FIGS.24-25. At2722, an upper inter-layer dielectric layer is formed on the lower inter-layer dielectric layer overlying the memory device structures in memory region and the logic devices within the logic region. Contacts can be subsequently formed. See, for example,FIG.26. While the flowchart2700ofFIG.27is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. In view of the foregoing, some embodiments of the present application are directed towards an integrated circuit (IC). The IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region. Further, some embodiments of the present application are directed towards an integrated circuit (IC). The IC comprises a plurality of memory cell structures disposed on a memory region of a substrate. Each of the plurality of memory cell structures comprises a select gate electrode separated from the substrate by a select gate dielectric. The IC further comprises a lower inter-layer dielectric layer surrounding the plurality of memory cell structures and a contact etch stop layer (CESL) separating the lower inter-layer dielectric layer and the CESL and disposed along an outline of the plurality of memory cell structures and is in direct contact with sidewall surfaces of the select gate electrode and the select gate dielectric. Further, some embodiments of the present application are directed towards an integrated circuit (IC). The IC comprises a substrate including a memory region. A plurality of memory cell structures is disposed on the memory region. Each of the memory cell structure of the plurality of memory cell structures comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes. The IC further comprises source/drain regions on opposite sides of the pair of select gate electrodes within the memory region and a contact etch stop layer (CESL) disposed along sidewalls of the plurality of memory cell structures and in direct contact with sidewalls of the pair of select gate electrodes. The IC further comprises a lower inter-layer dielectric layer disposed on the CESL and surrounding the plurality of memory cell structures. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 55,230 |
11943922 | DETAILED DESCRIPTION A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked. FIG.1is a block diagram of one embodiment of a storage system100that implements the proposed technology described herein. In one embodiment, storage system100is a solid state drive (“SSD”). Storage system100can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system100is connected to host102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host102is separate from, but connected to, storage system100. In other embodiments, storage system100is embedded within host102. The components of storage system100depicted inFIG.1are electrical circuits. Storage system100includes a memory controller120connected to non-volatile memory130and local high speed volatile memory140(e.g., DRAM). Local high speed volatile memory140is used by memory controller120to perform certain functions. For example, local high speed volatile memory140stores logical to physical address translation tables (“L2P tables”). Memory controller120comprises a host interface152that is connected to and in communication with host102. In one embodiment, host interface152implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface152is also connected to a network-on-chip (NOC)154. A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC154can be replaced by a bus. Connected to and in communication with NOC154is processor156, ECC engine158, memory interface160, and DRAM controller164. DRAM controller164is used to operate and communicate with local high speed volatile memory140(e.g., DRAM). In other embodiments, local high speed volatile memory140can be SRAM or another type of volatile memory. ECC engine158performs error correction services. For example, ECC engine158performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine158is an electrical circuit programmed by software. For example, ECC engine158can be a processor that can be programmed. In other embodiments, ECC engine158is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine158is implemented by processor156. Processor156performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor156is programmed by firmware. In other embodiments, processor156is a custom and dedicated hardware circuit without any software. Processor156also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller120(e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e., the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory140cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die130and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory140. Memory interface160communicates with non-volatile memory130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface160(or another portion of controller120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die. In one embodiment, non-volatile memory130comprises one or more memory die.FIG.2Ais a functional block diagram of one embodiment of a memory die200that comprises non-volatile memory130. Each of the one or more memory die of non-volatile memory130can be implemented as memory die200ofFIG.2A. The components depicted inFIG.2Aare electrical circuits. Memory die200includes a memory array202that can comprises non-volatile memory cells, as described in more detail below. The array terminal lines of memory array202include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die200includes row control circuitry220, whose outputs208are connected to respective word lines of the memory array202. Row control circuitry220receives a group of M row address signals and one or more various control signals from System Control Logic circuit260, and typically may include such circuits as row decoders222, array terminal drivers224, and block select circuitry226for both reading and writing (programming) operations. Row control circuitry220may also include read/write circuitry. Memory die200also includes column control circuitry210including sense amplifier(s)230whose input/outputs206are connected to respective bit lines of the memory array202. Although only single block is shown for array202, a memory die can include multiple arrays that can be individually accessed. Column control circuitry210receives a group of N column address signals and one or more various control signals from System Control Logic260, and typically may include such circuits as column decoders212, array terminal receivers or driver circuits214, block select circuitry216, as well as read/write circuitry, and I/O multiplexers. System control logic260receives data and commands from memory controller120and provides output data and status to the host. In some embodiments, the system control logic260(which comprises one or more electrical circuits) include state machine262that provides die-level control of memory operations. In one embodiment, the state machine262is programmable by software. In other embodiments, the state machine262does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine262is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic262can also include a power control module264that controls the power and voltages supplied to the rows and columns of the memory structure202during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic262includes storage366(e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory array202. Commands and data are transferred between memory controller120and memory die200via memory controller interface268(also referred to as a “communication interface”). Memory controller interface268is an electrical interface for communicating with memory controller120. Examples of memory controller interface268include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used. In some embodiments, all the elements of memory die200, including the system control logic260, can be formed as part of a single die. In other embodiments, some or all of the system control logic260can be formed on a different die. In one embodiment, memory structure202comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers. In another embodiment, memory structure302comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used. The exact type of memory array architecture or memory cell included in memory structure202is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure202include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure202include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like. One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature. Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below. Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or another wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate. A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art. The elements ofFIG.2Acan be grouped into two parts: (1) memory structure202and (2) peripheral circuitry, which includes all of the other components depicted inFIG.2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system100that is given over to the memory structure202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system100is the amount of area to devote to the memory structure202and the amount of area to devote to the peripheral circuitry. Another area in which the memory structure202and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure202is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic260often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies. To improve upon these limitations, embodiments described below can separate the elements ofFIG.2Aonto separately formed dies that are then bonded together. More specifically, the memory structure202can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example. FIG.2Bshows an alternative arrangement to that ofFIG.2Awhich may be implemented using wafer-to-wafer bonding to provide a bonded die pair.FIG.2Bdepicts a functional block diagram of one embodiment of an integrated memory assembly207. One or more integrated memory assemblies207may be used to implement the non-volatile memory130of storage system100. The integrated memory assembly207includes two types of semiconductor die (or more succinctly, “die”). Memory die201includes memory structure202. Memory structure202includes non-volatile memory cells. Control die211includes control circuitry260,210, and220(as described above). In some embodiments, control die211is configured to connect to the memory structure202in the memory die201. In some embodiments, the memory die201and the control die211are bonded together. FIG.2Bshows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die211coupled to memory structure202formed in memory die201. Common components are labelled similarly toFIG.2A. System control logic260, row control circuitry220, and column control circuitry210are located in control die211. In some embodiments, all or a portion of the column control circuitry210and all or a portion of the row control circuitry220are located on the memory die201. In some embodiments, some of the circuitry in the system control logic260is located on the on the memory die201. System control logic260, row control circuitry220, and column control circuitry210may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller120may require few or no additional process steps (i.e., the same process steps used to fabricate controller120may also be used to fabricate system control logic260, row control circuitry220, and column control circuitry210). Thus, while moving such circuits from a die such as memory 2 die201may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die211may not require many additional process steps. The control die211could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry260,210,220. FIG.2Bshows column control circuitry210including sense amplifier(s)230on the control die211coupled to memory structure202on the memory die201through electrical paths206. For example, electrical paths206may provide electrical connection between column decoder212, driver circuitry214, and block select216and bit lines of memory structure202. Electrical paths may extend from column control circuitry210in control die211through pads on control die211that are bonded to corresponding pads of the memory die201, which are connected to bit lines of memory structure202. Each bit line of memory structure202may have a corresponding electrical path in electrical paths206, including a pair of bond pads, which connects to column control circuitry210. Similarly, row control circuitry220, including row decoder222, array drivers224, and block select226are coupled to memory structure202through electrical paths208. Each of electrical path208may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die211and memory die201. For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller120, state machine262, all or a portion of system control logic260, all or a portion of row control circuitry220, all or a portion of column control circuitry210, a microcontroller, a microprocessor, and/or other similar functioned circuits. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit. In some embodiments, there is more than one control die211and more than one memory die201in an integrated memory assembly207. In some embodiments, the integrated memory assembly207includes a stack of multiple control die211and multiple memory die201.FIG.3Adepicts a side view of an embodiment of an integrated memory assembly207stacked on a substrate271(e.g., a stack comprising control dies211and memory dies201). The integrated memory assembly207has three control dies211and three memory dies201. In some embodiments, there are more than three memory dies20land more than three control die211. Each control die211is affixed (e.g., bonded) to at least one of the memory dies201. Some of the bond pads282/284are depicted. There may be many more bond pads. A space between two dies201,211that are bonded together is filled with a solid layer280, which may be formed from epoxy or other resin or polymer. This solid layer280protects the electrical connections between the dies201,211, and further secures the dies together. Various materials may be used as solid layer280, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. The integrated memory assembly207may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds270connected to the bond pads connect the control die211to the substrate271. A number of such wire bonds may be formed across the width of each control die211(i.e., into the page ofFIG.3A). A memory die through silicon via (TSV)276may be used to route signals through a memory die201. A control die through silicon via (TSV)278may be used to route signals through a control die211. The TSVs276,278may be formed before, during or after formation of the integrated circuits in the semiconductor dies201,211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used. Solder balls272may optionally be affixed to contact pads274on a lower surface of substrate271. The solder balls272may be used to couple the integrated memory assembly207electrically and mechanically to a host device such as a printed circuit board. Solder balls272may be omitted where the integrated memory assembly207is to be used as an LGA package. The solder balls272may form a part of the interface between integrated memory assembly207and memory controller120. FIG.3Bdepicts a side view of another embodiment of an integrated memory assembly207stacked on a substrate271. The integrated memory assembly207ofFIG.3Bhas three control die211and three memory die201. In some embodiments, there are many more than three memory dies201and many more than three control dies211. In this example, each control die211is bonded to at least one memory die201. Optionally, a control die211may be bonded to two or more memory die201. Some of the bond pads282,284are depicted. There may be many more bond pads. A space between two dies201,211that are bonded together is filled with a solid layer280, which may be formed from epoxy or other resin or polymer. In contrast to the example inFIG.3A, the integrated memory assembly207inFIG.3Bdoes not have a stepped offset. A memory die through silicon via (TSV)276may be used to route signals through a memory die201. A control die through silicon via (TSV)278may be used to route signals through a control die211. Solder balls272may optionally be affixed to contact pads274on a lower surface of substrate271. The solder balls272may be used to couple the integrated memory assembly207electrically and mechanically to a host device such as a printed circuit board. Solder balls272may be omitted where the integrated memory assembly207is to be used as an LGA package. As has been briefly discussed above, the control die211and the memory die201may be bonded together. Bond pads on each die201,211may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu. When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller (or greater) sizes and pitches. Some embodiments may include a film on surface of the dies201,211. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies201,211, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA. FIG.4is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example,FIG.4shows a portion400of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack401of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions by isolation regions IR.FIG.4shows one isolation region IR separating two regions. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that inFIG.4, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Thus, the non-volatile memory cells are arranged in memory holes. More details of the three dimensional monolithic memory array that comprises memory structure202is provided below. FIG.4Ais a block diagram explaining one example organization of memory structure202, which is divided into four planes402,403,404and405. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. AlthoughFIG.4Ashows four planes, more or less than four planes can be implemented. In some embodiments, memory structure202includes eight planes. FIGS.4B-4Gdepict an example three dimensional (“3D”) NAND structure that corresponds to the structure ofFIG.4and can be used to implement memory structure202ofFIGS.2A and2B.FIG.4Bis a block diagram depicting a top view of a portion406of Block 2 of plane402. As can be seen fromFIG.4B, the block depicted inFIG.4Bextends in the direction of432. In one embodiment, the memory array has many layers; however,FIG.4Bonly shows the top layer. FIG.4Bdepicts a plurality of circles that represent the memory holes, which are also referred to as vertical columns. Each of the memory holes/vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each memory hole/vertical column implements a NAND string. For example,FIG.4Blabels a subset of the memory holes/vertical columns/NAND strings432,436,446.456,462,466,472,474and476. FIG.4Balso depicts a set of bit lines415, including bit lines411,412,413,414, . . .419.FIG.4Bshows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to memory holes/vertical columns of the block. Each of the circles representing memory holes/vertical columns has an “x” to indicate its connection to one bit line. For example, bit line411is connected to memory holes/vertical columns436,446,456,466and476. The block depicted inFIG.4Bincludes a set of isolation regions482,484,486and488, which are formed of SiO2; however, other dielectric materials can also be used. Isolation regions482,484,486and488serve to divide the top layers of the block into five regions; for example, the top layer depicted inFIG.4Bis divided into regions430,440,450,460and470. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different regions can be independently selected. In one example implementation, a bit line connects to one memory hole/vertical column/NAND string in each of regions430,440,450,460and470. In that implementation, each block has twenty four rows of active columns and each bit line connects to five rows in each block. In one embodiment, all of the five memory holes/vertical columns/NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses the drain side selection lines to choose one (or another subset) of the five to be subjected to a memory operation (program, verify, read, and/or erase). FIG.4Balso shows Line Interconnects LI, which are metal connections to the source line SL from above the memory array. Line Interconnects LI are positioned adjacent regions430and470. AlthoughFIG.4Bshows each region430,440,450,460and470having four rows of memory holes/vertical columns, five regions and twenty four rows of memory holes/vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of memory holes/vertical columns per region and more or less rows of vertical columns per block.FIG.4Balso shows the memory holes/vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the memory holes/vertical columns are not staggered. FIG.4Cdepicts a portion of one embodiment of a three dimensional memory structure202showing a cross-sectional view along line AA ofFIG.4B. This cross sectional view cuts through memory holes/vertical columns (NAND strings)472and474of region470(seeFIG.4B). The structure ofFIG.4Cincludes two drain side select layers SGD0 and SGD; teo source side select layers SGS0 and SGS1; two drain side GIDL generation transistor layers SGDT0 and SGDT1; two source side GIDL generation transistor layers SGSB0 and SGSB1; two drain side dummy word line layers DD0 and DD1; two source side dummy word line layers DS0 and DS1; dummy word line layers DU and DL; one hundred and sixty two word line layers WL0-WL161 for connecting to data memory cells, and dielectric layers DL. Other embodiments can implement more or less than the numbers described above forFIG.4C. In one embodiment, SGD0 and SGD1 are connected together; and SGS0 and SGS1 are connected together. In other embodiments, more or less number of SGDs (greater or lesser than two) are connected together, and more or less number of SGSs (greater or lesser than two) connected together. In one embodiment, erasing the memory cells is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at the GIDL generation transistors such that the carriers get injected into the charge trapping layers of the NAND strings to change threshold voltage of the memory cells.FIG.4Cshows two GIDL generation transistors at each end of the NAND string; however, in other embodiments there are more or less than three. Embodiments that use GIDL at both sides of the NAND string may have GIDL generation transistors at both sides. Embodiments that use GIDL at only the drain side of the NAND string may have GIDL generation transistors only at the drain side. Embodiments that use GIDL at only the source side of the NAND string may have GIDL generation transistors only at the source side. FIG.4Cshows two GIDL generation transistors at each end of the NAND string. It is likely that charge carriers are only generated by GIDL at one of the two GIDL generation transistors at each end of the NAND string. Based on process variances during manufacturing, it is likely that one of the two GIDL generation transistors at an end of the NAND string is best suited for GIDL. For example, the GIDL generation transistors have an abrupt pn junction to generate the charge carriers for GIDL and, during fabrication, a phosphorous diffusion is performed at the polysilicon channel of the GIDL generation transistors. In some cases, the GIDL generation transistor with the shallowest phosphorous diffusion is the GIDL generation transistor that generates the charge carriers during erase. However, in some embodiments charge carriers can be generated by GIDL at multiple GIDL generation transistors at a particular side of the NAND string. Memory holes/Vertical columns472and474are depicted protruding through the drain side select layers, source side select layers, dummy word line layers, GIDL generation transistor layers and word line layers. In one embodiment, each memory hole/vertical column comprises a vertical NAND string. Below the memory holes/vertical columns and the layers listed below is substrate453, an insulating film454on the substrate, and source line SL. The NAND string of memory hole/vertical column472has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement withFIG.4B,FIG.4Cshow vertical memory hole/column472connected to bit line414via connector417. For ease of reference, drain side select layers; source side select layers, dummy word line layers, GIDL generation transistor layers and data word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten, metal silicide, such as nickel silicide, tungsten silicide, aluminum silicide or the combination thereof. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL. In one embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers. The non-volatile memory cells are formed along memory holes/vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-W161 connect to memory cells (also called data memory cells). Dummy word line layers connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD0 and SGD1 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0 and SGS1 are used to electrically connect and disconnect NAND strings from the source line SL. FIG.4Cshows that the memory array is implemented as a two tier architecture, with the tiers separated by a Joint area. In one embodiment it is expensive and/or challenging to etch so many word line layers intermixed with dielectric layers. To ease this burden, one embodiment includes laying down a first stack of word line layers (e.g., WL0-WL80) alternating with dielectric layers, laying down the Joint area, and laying down a second stack of word line layers (e.g., WL81-WL161) alternating with dielectric layers. The Joint area are positioned between the first stack and the second stack. In one embodiment, the Joint areas are made from the same materials as the word line layers. In other embodiments, there can no Joint area or there can be multiple Joint areas. FIG.4Ddepicts a portion of one embodiment of a three dimensional memory structure202showing a cross-sectional view along line BB ofFIG.4B. This cross sectional view cuts through memory holes/vertical columns (NAND strings)432and434of region430(seeFIG.4B).FIG.4Dshows the same alternating conductive and dielectric layers asFIG.4C.FIG.4Dalso shows isolation region482. Isolation regions482,484,486and488) occupy space that would have been used for a portion of the memory holes/vertical columns/NAND stings. For example, isolation region482occupies space that would have been used for a portion of memory hole/vertical column434. More specifically, a portion (e.g., half the diameter) of vertical column434has been removed in layers SGDT0, SGDT1, SGD0, and SGD1 to accommodate isolation region482. Thus, while most of the vertical column434is cylindrical (with a circular cross section), the portion of vertical column434in layers SGDT0, SGDT1, SGD0, and SGD1 has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiO2. This structure allows for separate control of SGDT0, SGDT1, SGD0, and SGD1 for regions430,440,450,460, and470. FIG.4Edepicts a cross sectional view of region429ofFIG.4Cthat includes a portion of memory hole/vertical column472. In one embodiment, the memory holes/vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, memory hole/vertical column472includes an inner core layer490that is made of a dielectric, such as SiO2. Other materials can also be used. Surrounding inner core490is polysilicon channel491. Materials other than polysilicon can also be used. Note that it is the channel491that connects to the bit line and the source line. Surrounding channel491is a tunneling dielectric492. In one embodiment, tunneling dielectric492has an ONO structure. Surrounding tunneling dielectric492is charge trapping layer493, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure. FIG.4Edepicts dielectric layers DL as well as word line layers WL160, WL159, WL158, WL157, and WL156. Each of the word line layers includes a word line region496surrounded by an aluminum oxide layer497, which is surrounded by a blocking oxide layer498. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer493. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel491, tunneling dielectric492, charge trapping layer493, blocking oxide layer498, aluminum oxide layer497and word line region496. For example, word line layer WL160 and a portion of memory hole/vertical column472comprise a memory cell MC1. Word line layer WL159 and a portion of memory hole/vertical column472comprise a memory cell MC2. Word line layer WL158 and a portion of memory hole/vertical column472comprise a memory cell MC3. Word line layer WL157 and a portion of memory hole/vertical column472comprise a memory cell MC4. Word line layer WL156 and a portion of memory hole/vertical column472comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit. When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer493which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer493from the channel491, through the tunneling dielectric492, in response to an appropriate voltage on word line region496. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL. FIG.4Fis a schematic diagram of a portion of the three dimensional memory array202depicted in inFIGS.4-4E.FIG.4Fshows physical data word lines WL0-WL161 running across the entire block. The structure ofFIG.4Fcorresponds to a portion406in Block 2 ofFIG.4A, including bit line411. Within the block, in one embodiment, each bit line is connected to five NAND strings, one in each region of regions430,440,450,460,470. Thus,FIG.4Fshows bit line411connected to NAND string NS0 (which corresponds to memory hole/vertical column436of region430), NAND string NS1 (which corresponds to memory hole/vertical column446of region440), NAND string NS2 (which corresponds to vertical column456of region450), NAND string NS3 (which corresponds to memory hole/vertical column466of region460), and NAND string NS4 (which corresponds to memory hole/vertical column476of region470). Drain side select line/layer SGD0 is separated by isolation regions isolation regions482,484,486and488to form SGD0-s0, SGD0-s1, SGD0-s2, SGD0-s3 and SGD0-s4 in order to separately connect to and independently control regions430,440,450,460,470. Similarly, drain side select line/layer SGD1 is separated by isolation regions482,484,486and488to form SGD1-s0, SGD1-s1, SGD1-s2, SGD1-s3 and SGD1-s4 in order to separately connect to and independently control regions430,440,450,460,470; drain side GIDL generation transistor control line/layer SGDT0 is separated by isolation regions482,484,486and488to form SGDT0-s0, SGDT0-s1, SGDT0-s2, SGDT0-s3 and SGDT0-s4 in order to separately connect to and independently control regions430,440,450,460,470; drain side GIDL generation transistor control line/layer SGDT1 is separated by isolation regions482,484,486and488to form SGDT1-s0, SGDT1-s1, SGDT1-s2, SGDT1-s3 and SGDT1-s4 in order to separately connect to and independently control regions430,440,450,460,470. FIG.4Fonly shows NAND strings connected to bit line411. However, a full schematic of the block would show every bit line and five vertical NAND strings (that are in separate regions) connected to each bit line. Although the example memories ofFIGS.4-4Fare three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein. The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.FIG.5Ais a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell data are referred to as single level cells (“SLC”). The data stored in SLC memory cells is referred to as SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data.FIG.5Ashows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.”FIG.5Adepicts read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine a memory cells is erased (state E) or programmed (state P).FIG.5Aalso depicts verify reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv. FIGS.5B-Dillustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment ofFIG.5B, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell). FIG.5Bshows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the distribution E are negative and the threshold voltages in distributions A, B and C are positive. Each distinct threshold voltage distribution ofFIG.5Bcorresponds to predetermined values for the set of data bits. In one embodiment, each bit of data of the two bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 1 provides an example encoding scheme. TABLE 1EABCLP1001UP1100 In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state E directly to any of the programmed data states A, B or C using the process ofFIG.6(discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and/or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and/or from data state E to data state C. The arrows ofFIG.5Brepresent the full sequence programming. In some embodiments, data states A-C can overlap, with memory controller120(or control die211) relying on error correction to identify the correct data being stored. FIG.5Cdepicts example threshold voltage distributions for memory cells where each memory cell stores three bits of data per memory cells (which is another example of MLC data).FIG.5Cshows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for embodiments in which each bit of data of the three bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP) and an upper page (UP). TABLE 2ErABCDEFGUP11100001MP11001100LP10000111 FIG.5Cshows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, . . . ) a memory cell is in. FIG.5Calso shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG.FIG.5Calso shows Vev, which is an erase verify reference voltage to test whether a memory cell has been properly erased. In an embodiment that utilizes full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process ofFIG.6(discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and/or from data state Er to data state C, and so on. The arrows ofFIG.5Crepresent the full sequence programming. In some embodiments, data states A-G can overlap, with control die211and/or memory controller120relying on error correction to identify the correct data being stored. Note that in some embodiments, rather than using full sequence programming, the system can use multi-pass programming processes known in the art. In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare voltages/levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, ofFIG.5C) or verify operation (e.g. see verify target voltages/levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG ofFIG.5C) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased). There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used. FIG.5Ddepicts threshold voltage distributions when each memory cell stores four bits of data, which is another example of MLC data.FIG.5Ddepicts that there may be some overlap between the threshold voltage distributions (data states) S0-S15. The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. Note that in some embodiments, the threshold voltage distributions for a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other. The threshold voltage distributions ofFIG.5Dwill include read reference voltages and verify reference voltages, as discussed above. When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes known in the art. Each threshold voltage distribution (data state) ofFIG.5Dcorresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 3 provides an example of an encoding scheme for embodiments in which each bit of data of the four bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP), an upper page (UP) and top page (TP). TABLE 3S0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15TP1111100000110001UP1100000011111100MP1110000110000111LP1000110000011111 FIG.6is a flowchart describing one embodiment of a process for programming memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one example embodiment, the process ofFIG.6is performed for memory array202using the one or more control circuits (e.g., system control logic260, column control circuitry210, row control circuitry220) discussed above. In one example embodiment, the process ofFIG.6is performed by integrated memory assembly207using the one or more control circuits (e.g., system control logic260, column control circuitry210, row control circuitry220) of control die211to program memory cells on memory die201. The process includes multiple loops, each of which includes a program phase and a verify phase. The process ofFIG.6is performed to implement the full sequence programming, as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, the process ofFIG.6is used to implement any/each stage of the multi-stage programming process. Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program voltage pulses. Between program voltage pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program voltage pulses is increased with each successive pulse by a predetermined step size. In step602ofFIG.6, the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine262is initialized at 1. In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step604the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step606, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string. In step608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step608, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming. In step610, program-verify is performed, which includes testing whether memory cells being programmed have successfully reached their target data state. Memory cells that have reached their target states are locked out from further programming by the control die. Step610includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step610, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. In one embodiment of step610, a smart verify technique is used such that the system only verifies a subset of data states during a program loop (steps604-628). For example, the first program loop includes verifying for data state A (seeFIG.5C), depending on the result of the verify operation the second program loop may perform verify for data states A and B, depending on the result of the verify operation the third program loop may perform verify for data states B and C, and so on. In step616, the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine262, memory controller120, or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state. In step617, the system determines whether the verify operation in the latest performance of step610included verifying for the last data state (e.g., data state G of FIG.5C). If so, then in step618, it is determined whether the count from step616is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a status of “PASS” is reported in step614. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step618is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria. If in step617it was determined that the verify operation in the latest performance of step610did not include verifying for the last data state or in step618it was determined that the number of failed memory cells is not less than the predetermined limit, then in step619the data states that will be verified in the next performance of step610(in the next program loop) is adjusted as per the smart verify scheme discussed above. In step620, the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step624. If the program counter PC is less than the program limit value PL, then the process continues at step626during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts). After step626, the process continues at step604and another program pulse is applied to the selected word line (by the control die) so that another program loop (steps604-626) of the programming process ofFIG.6is performed. In one embodiment memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E ofFIG.5A, from states A/B/C to state E ofFIG.5B, from states A-G to state Er ofFIG.5Cor from states S1-S15to state S0ofFIG.5D. In one embodiment, the control circuit is configured to program memory cells in the direction from the erased data state toward the highest data state (e.g., from data state Er to data state G) and erase memory cells in the direction from the highest data state toward the erased data state (e.g., from data state G to data state Er). One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the memory cells. Herein, this is referred to as p-well erase. Another approach to erasing memory cells is to generate gate induced drain leakage (“GIDL”) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells. In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a GIDL generation transistor (e.g., transistors connected to SGDT0, SGDT1, SGSB0, and SGSB1). In some embodiments, a select gate (e.g., SGD or SGS) can be used as a GIDL generation transistor. A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the GIDL generation transistor drain voltage is significantly higher than the GIDL generation transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers (also referred to a charge carriers), e.g., holes, predominantly moving into the NAND channel, thereby raising or changing the potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of the memory cells (e.g., to charge trapping layer493) and recombine with electrons there, to lower the threshold voltage of the memory cells. The GIDL current may be generated at either end (or both ends) of the NAND string. A first GIDL voltage may be created between two terminals of a GIDL generation transistor (e.g., connected to SGDT0, SGDT1) that is connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a GIDL generation transistor (e.g., SGSB0, SGSB1) that is connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase. The technology described herein can be used with one-sided GIDL erase and two-sided GIDL erase. FIG.7depicts the programming signal Vpgm as a series of program voltage pulses, such that one pulse of the programming signal Vpgm is applied at each performance of step608ofFIG.6. These program voltage pulses are one example of doses of programming applied to a plurality of non-volatile memory cells being programmed. In one embodiment, the program voltage pulses increase in voltage magnitude from pulse-to-pulse by a step size ΔVpgm. In some embodiments, ΔVpgm can change during a programming process. As described byFIG.6, the system performs program-verification between the doses of programming (between or after programming voltage pulses), as depicted inFIGS.8A and8B.FIG.8A, which illustrates an example in which program-verify is performed for one verify level, depicts two of the programming voltage pulses702and704ofFIG.7. Between programming voltage pulses702and704is verify voltage pulse710. In one embodiment, verify voltage pulse710has a magnitude of any of the verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG (seeFIG.5C) and represents the system performing program-verify (step610) between the doses of programming (successive iterations of step608). In some embodiments, between programming voltage pulses the system will perform program-verify for multiple or all data states, while in other embodiments the system will perform program-verify for one data state at a time or a subset of data states.FIG.8B, which illustrates an example in which program-verify is performed for two verify levels, depicts two of the programming voltage pulses702and704ofFIG.7. Between programming voltage pulses702and704are verify voltage pulses710and712. In one embodiment, verify voltage pulses710and712are for different data states. The programming, verifying/sensing and erasing processes discussed above require that various voltages be applied to the word lines of the selected block(s) of memory cells.FIG.9is a block diagram that depicts charge pumps, control gate drivers, a switch network, and word line switches that are used to apply those voltages to the word lines.FIG.9shows a set of charge pumps902providing multiple different sources of voltages to multiple sets of control gate drivers including a first set of control gate drivers904, a second set of control gate drivers906, a third set of control gate drivers908, . . . a X set of control gate drivers910. Charge pumps902include multiple charge pumps that supply the different voltages needed to perform memory operations. In some embodiments, voltage generators can also generate some of the different voltages needed to perform memory operations. In one embodiment, there is a separate set of one or more charge pumps or voltage generator for each voltage needed to be applied to the word lines. In other embodiments, some charge pumps and/or voltage generators can be the source of multiple voltages by using voltage dividers or other circuits. Some embodiments may only include one charge pump or one source of one or more word line voltages. In one embodiment, first set of control gate drivers904includes multiple control gate drivers for supplying the necessary voltages to data word lines (e.g., Wl-WL161) in order to perform programming, erasing and reading. The output of the first set of control gate drivers904, CGout_A (which includes one separate output signal for each control gate driver) is provided (connected) to switch network920. The output of switch network920are driver lines980, which are configured to carry one or more word line voltages. First set of control gate drivers904are connected to the data word lines via switch network920and driver lines980. In one embodiment, all of the control gate drivers of the first set of control gate drivers904have the same structure, receive the same inputs (source of voltage) and provide the same set of voltage outputs. In one embodiment, second set of control gate drivers906includes multiple control gate drivers for supplying the necessary voltages to dummy word lines in order to perform programming, erasing and reading. The output of the second set of control gate drivers906, CGout_B (which includes one separate output signal for each control gate driver) is provided (connected) to switch network920. The second set of control gate drivers906are connected to the dummy word lines via switch network920and driver lines980. In one embodiment, all of the control gate drivers of the second set of control gate drivers906have the same structure, receive the same inputs (sources of voltage) and provide the same set of voltage outputs. In one embodiment, third set of control gate drivers908includes multiple control gate drivers for supplying the necessary voltages to select lines (e.g., SGD and SGS) in order to perform programming, erasing and reading. The output of the third set of control gate drivers908, CGout_C (which includes one separate output signal for each control gate driver) is provided (connected) to switch network920. The third set of control gate drivers908are connected to the select lines via switch network920and driver lines980. In one embodiment, all of the control gate drivers of the third set of control gate drivers908have the same structure, receive the same inputs (sources of voltage) and provide the same set of voltage outputs. FIG.9shows word lines WL0-WL161 for two example blocks (Block A and Block B). Each word line WL0-WL161 for each block is connected to one of driver lines980via a word line switch (e.g.,940-966). Thus, the word line switches selectively connect the driver lines980to the word lines. In one embodiment, each of word line switches940-966are implemented as a transistor. For example, word line WL0 of block A is connected to the output of word line switch966, WL159 of block A is connected to the output of word line switch964, WL160 of block A is connected to the output of word line switch962, WL161 of block A is connected to the output of word line switch960, WL0 of block B is connected to the output of word line switch946, WL159 of block B is connected to the output of word line switch944, WL160 of block B is connected to the output of word line switch942, and WL161 of block1is connected to the output of word line transistor960. The inputs to the word line switches are connected to driver lines980, which are the outputs of switch network920. In one embodiment, switch network920includes a plurality of high voltage switches (e.g., transistors) to connect the control gate drivers to the appropriate word lines by routing the output voltage from the control gate drivers to the appropriate word line switch transistors940-966connected to the word lines WL0-WL161 of each block. Note that in some embodiments, multiple word lines can share a single control gate driver. The switch network is also connected to the select lines SGS and SGD (which are omitted fromFIG.9to makeFIG.9easier to read). FIG.9also depicts voltage control circuit903, which is connected to charge pumps902(via signals905), Voltage control circuit903controls the output of charge pumps902. In one embodiment, voltage control circuit903receives a digital signal from the state machine or other processor that indicates the desired charge pump output, and voltage control circuit903includes a digital to analog conversion circuit that outputs signal905to charge pumps902that indicates the requested voltage signal to be output by the charge pumps. There is a trend to increase the density of the non-volatile memory. This includes implementing more non-volatile memory cells in memory array202. One means for including more non-volatile memory cells in memory array202is to implement additional levels to the three dimensional memory. For example,FIG.4Cshows 161 word lines vertically stacked. To include more non-volatile memory cells in memory array202, the memory can be implemented with more than 161 word lines vertically stacked. Adding additional word lines will require adding additional word line switches. Word line switches are traditionally implemented on the substrate of the die; for example, as part of row control circuitry220or power control264on memory die200(seeFIG.2A) or control die211(seeFIG.2B). Adding more word line switches, therefore, will use up more room on the substrate of the die, potentially requiring a bigger die. However, there is a trend to use a smaller or same size die because users want smaller electronic devices. To add more word line switches without increasing the die size, it is proposed to vertically stack the word line switches so that the word line switches occupy less space on the die. Therefore, the word line switches are arranged in a plurality of three dimensional stacks, with each stack of the plurality of three dimensional stacks comprising multiple word line switches vertically stacked. This arrangement is depicted inFIG.10. FIG.10is a cross section view of one embodiment of a three dimensional stack of word line switches802. The number of word line switches in a stack can vary. For example purposes only, three dimensional stack of word line switches802includes four word line switches804,806,808, and810, which can be used to implement any of word line switches940-966ofFIG.9. Three dimensional stack of word line switches802is surrounded by oxide (e.g., SiO2)812. At the center of stack of word line switches802is a central tower of gate material814that comprises multiple gates (for the different word line switches of the stack) mechanically and electrically connected together. Central tower of gate material814comprises a metal. Various different metals can be used. A non-exhaustive set of examples of suitable metals for central tower of gate material814includes Tungsten, and Copper. Central tower of gate material814is patterned into multiple gate regions to form gates for each of the word line switches804,806,808, and810of the stack802. For example, regions816and818of gate material814form a gate for word line switch810; regions818and820of gate material814form a gate for word line switch808; regions820and822of gate material814form a gate for word line switch806; and regions822and824of gate material814form a gate for word line switch804. In this manner, each stack of the plurality of three dimensional stacks comprises multiple word line switches that are vertically stacked and electrically connected together. Each word line switch of stack902includes a gate, a source connected to one of the driver lines (e.g., driver lines980ofFIG.9) and a drain connected to one of the word lines (e.g., word lines940-966ofFIG.9). For example, word line switch804comprises: a gate formed of regions822and824; drain830(e.g., Tungsten or other suitable metal); lightly doped drain832(e.g., silicon that has been lightly doped, differently than the channel to insure high voltage operation); channel834(e.g., silicon); gate oxide836(which is formed as part of oxide814); lightly doped drain840and source842(e.g., Tungsten or other suitable metal). Word line switch806comprises: a gate formed of regions820and822; drain844(e.g., Tungsten or other suitable metal); lightly doped drain846(e.g., silicon that has been lightly doped, differently than the channel to insure high voltage operation); channel848(e.g., silicon); gate oxide836(which is formed as part of oxide814); lightly doped drain852and source854(e.g., Tungsten or other suitable metal). Word line switch808comprises: a gate formed of regions818and820; drain856(e.g., Tungsten or other suitable metal); lightly doped drain860(e.g., silicon that has been lightly doped, differently than the channel to insure high voltage operation); channel858(e.g., silicon); gate oxide836(which is formed as part of oxide814); lightly doped drain864and source866(e.g., Tungsten or other suitable metal). Word line switch810comprises: a gate formed of regions816and818; drain868(e.g., Tungsten or other suitable metal); lightly doped drain870(e.g., silicon that has been lightly doped, differently than the channel to insure high voltage operation); channel872(e.g., silicon); gate oxide836(which is formed as part of oxide814); lightly doped drain876and source880(e.g., Tungsten or other suitable metal). Between source layers and between drain layers are dielectric regions826(e.g., SiO2).FIG.10also shows pillar shaped structures882and884(partially occluded) that run from above stack802and through stack802to the bottom of stack802in order to mechanically hold and support stack802so it does not collapse when parts of the stack are removed during fabrication. As mentioned above, each word line switch of stack902includes a source connected to one of the driver and a drain connected to one of the word lines. In that regard,FIG.10shows connection lines890-897. Connection line890connects source region842to a driver line, connection line892connects source region854to a driver line, connection line894connects source region866to a driver line, connection line896connects source region880to a driver line, connection line891connects drain region830to a word line, connection line893connects drain region844to a word line, connection line895connects drain region856to a word line, and connection line897connects drain region868to a word line. As can be seen fromFIG.10, the stack802has a profile that tapers toward the top of the respective stack. That is, the multiple word line switches (804,806,808,810) of stack802differ in horizontal width such that lower word line switches are wider than upper word line switches, thereby, forming a staircase profile in cross section. For example, word line switch808is wider that word line switch810, word line switch806is wider that word line switch808, and word line switch804is wider that word line switch806. In other words, multiple word line switches of stack802differ in horizontal width such that word line switches protrude out from one or more word line switches above in a first direction to connect to one of the word lines and protrude out from one or more word line switches above in a second directions to connect to one of the driver lines (e.g., word line switch804protrudes out from word line switch806, word line switch806protrudes out from word line switch808, and word line switch808protrudes out from word line switch810). FIG.11is a close-up cross section view of word line switch806, showing a gate formed of regions820and822, drain844, lightly doped drain846, channel848, gate oxide836, lightly doped drain852and source854. Each word line switch includes a gate (e.g., from the combination of regions820and822) that surrounds the channel (e.g., channel848), for example, surrounding the channel on at least four sides of the channel. In one example, the height of the gate and the height of the word line switch is 154 nm (see arrow1102). In one embodiment, the height of drain844, lightly doped drain846, channel848, lightly doped drain852and source854is 50 nm (see arrow1104). The gate includes a central portion860that protrudes through channel848. This can also be seen inFIG.12B, which shows a top view of channel848, with central portion860of the gate protruding through a hole in channel848.FIG.12Ais a perspective view of a portion of word line switch806. showing portion820of the gate (G), lightly doped drain846, and lightly doped drain852. Note that the hole in channel848and central portion860of the gate are not visible. FIG.13is a top view of one embodiment of three dimensional stacks of word line switches. In some embodiments, a memory system will include many word line switches that are arranged in a plurality of three dimensional stacks, such that each stack of the plurality of three dimensional stacks comprises multiple word line switches vertically stacked.FIG.13shows three stacks of word line switches802,1302and1304next to a block1312of non-volatile memory cells that are part of memory array202. In various embodiments, the stacks of word line switches can be on the same die or different die than the memory cells, and the stacks of word line switches can be adjacent to memory array202, underneath memory array202or in another location.FIG.13shows the area where the staircase profile is implemented on the drain side and where the staircase profile is implemented on the source side. Between stacks802,1302and1304are dielectric regions1306,1308and1310that electrically separate the stacks.FIG.13shows the top of connection lines890,891,892,893,894,895,896, and897.FIG.13also shows the top of pillar shaped structures882and884. InFIG.10, pillar shaped structures882and884are depicted as one pillar each to keep the drawing simple. However, in some embodiments, pillar shaped structures882and884comprise nine pillars each, as depicted inFIG.13.FIG.13also shows eight pillars (e.g., pillars1320,1322,1324,1326,1328and1330), made of SiO2, surrounding each of connection lines890,891,892,893,894,895,896, and897. FIG.14is a flow chart describing one embodiment of a process for fabricating a stack of word line switches, including the structure ofFIG.10. Step1402ofFIG.14includes creating a stack of alternating layers of material and one or more support structures through the layers to mechanically hold the stack so it does not collapse when parts of the stack are removed. Step1404includes adding source and drain regions at multiple levels of the stack. Step1406includes adding gate layers that are connected to each other, at multiple levels of the stack, to form word line switches at the multiple levels of the stack. Step1408includes connecting the source and drain regions at multiple levels of the stack to word lines and one or more sources of word line voltages. FIG.15is a flow chart describing one embodiment of a process for fabricating a stack of word line switches, including the structure ofFIG.10. The process ofFIG.15is an example implementation of the process ofFIG.14.FIGS.16-28depict one embodiment of a three dimensional stack of word line switches during the process for fabricating ofFIG.15. Step1502ofFIG.15includes creating a stack of alternating layers of Si and SiGe.FIG.16depicts the stack after step1502, and shows alternating layers of Si (1606) and SiGe (1608) below a top layer of oxide1604(e.g., SiO2) and above wafer1602. Step1504includes creating pillar shaped structures to mechanically hold the stack so it does not collapse when parts of the stack are removed. In one embodiment, step1504includes performing a dry etch to create the hole and then filling in with SiO2.FIGS.17A and17Bdepict the stack after step1502, and show pillar shaped structures882and884in the stack passing through the alternating layers of Si (1606) and SiGe (1608).FIGS.17A and17Bshow the stack at different cross sections, such that the cross section ofFIG.17Bgoes through pillar shaped structures882and884, and the cross section ofFIG.17Bis in front of pillar shaped structures882and884. Steps1502-1504are an example implementation of step1402ofFIG.14. Step1506includes creating recesses in the SiGe layers of the stack. In one embodiment, step1506includes performing a selective ion etch.FIG.18depicts the stack after step1506, and shows recesses1802. Step1508includes lining the recesses with doped Si. In one embodiment, step1508includes performing Chemical Vapor Deposition (“CVD”) or Atomic Layer Deposition (“ALD”) to add doped silicon.FIG.19depicts the stack after step1508, and shows doped Si liners1902. Step1510includes annealing and diffusing the dopant of the doped Si liners1902.FIG.20depicts the stack after step1510, and shows that the outer portions of what previously were Si layers1606are now lightly doped regions2002. Step1512includes creating recesses in the doped Si. For example, a dry etch is used to remove liners1902and a portion of lightly doped regions2002.FIG.21depicts the stack after step1512. Step1514includes filling the recesses with dielectric material. In one embodiment, Conformal CVD is used to add SiO2into the recesses.FIG.22depicts the stack after step1514and shows dielectric regions826added during step1514. In one embodiment, dielectric regions826and top layer of oxide1604have different densities. Step1516includes creating a staircase profile in cross section. In one embodiment, a dry etch process is used to etch away portions of lightly doped regions2002and dielectric regions826to create the staircase.FIG.23depicts the stack after step1516and shows lightly doped regions2002and dielectric regions826etched to form a staircase. Step1518includes replacing portion of doped Si with Tungsten. In one embodiment, a wet etch process is used to remove lightly doped regions2002and either CVD or Physical Vapor Deposition (“PVD”) is used to add Tungsten in place of lightly doped regions2002.FIG.24depicts the stack after step1518and shows the addition of Tungsten regions830,844,856and868which are used as drains and Tungsten regions842,854,866and880which are used as sources. Steps1506-1518are an example implementation of step1404ofFIG.14. Step1520includes creating slot in gate area and depositing oxide. In one embodiment, a hole is drilled through the stack and oxide is deposited on the stack.FIG.25depicts the stack after step1520and shows hole2502.FIG.25also shows oxide812deposited on the stack. Note that in one embodiment, oxide812has a different density than pillars882/884. Step1522includes removing Si in the slots and lining with oxide.FIG.26depicts the stack after step1522and shows that regions2602of Si layers1606have been removed around hole2503and filled with oxide (oxide deposition). Step1524includes replacing SiGe with metal gate material and depositing liner oxide. This step forms the connected gates for the word line switches of the stack.FIG.27depicts the stack after step1524and shows central tower of gate material814with a liner2702of oxide around the central tower of gate material814. Steps1520-1524are an example implementation of step1406ofFIG.14. Step1526includes adding signal lines to the source and drain for each level of the stack.FIG.27depicts the stack after step1524and shows the addition of connection lines890,891,892,893,894,895,896, and897. Steps1526is an example implementation of step1408ofFIG.14. A non-volatile memory system has been proposed that more efficiently utilizes space by stacking word line switch transistors. One embodiment includes a non-volatile memory apparatus, comprising: a plurality of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells; a plurality of driver lines configured to carry one or more word line voltages; and a plurality of word line switches that selectively connect the driver lines to the word lines, the word line switches are arranged in a plurality of three dimensional stacks, each stack of the plurality of three dimensional stacks comprise multiple word line switches vertically stacked. In one example implementation, each word line switch includes a gate, a source connected to one of the driver lines and a drain connected to one of the word lines. In one example implementation, each stack of the plurality of three dimensional stacks comprises multiple word line switches that are vertically stacked and electrically connected together. In one example implementation, each stack of the plurality of three dimensional stacks comprises multiple word line switches that are vertically stacked and have gates that are mechanically and electrically connected together. In one example implementation, each stack of the plurality of three dimensional stacks comprises multiple word line switches that are vertically stacked and a central tower of gate material electrically connected to each word line switch of the respective stack. In one example implementation, each stack of the plurality of stacks has a profile that tapers toward a top of the respective stack. In one example implementation, multiple word line switches of a stack differ in horizontal width such that lower word line switches are wider than upper word line switches. In one example implementation, the multiple word line switches of a stack differ in horizontal width forming a staircase profile in cross section. In one example implementation, multiple word line switches of a stack differ in horizontal width such that word line switches protrude out from one or more word line switches above in a first directions to connect to one of the word lines and protrude out from one or more word line switches above in a second directions to connect to one of the driver lines In one example implementation, each word line switch includes a gate surrounding a channel. In one example implementation, each word line switch includes a gate, a source, a drain and a channel; and the gate surrounds the channel on at least four side of the channel. In one example implementation, each word line switch includes a gate and a channel; and the gate protrude through the channel. One example implementation further comprises one or more sources of word line voltages connected to the plurality of driver lines. In one example implementation, the plurality of non-volatile memory cells are arranged in a three dimensional memory structure having multiple levels of non-volatile memory cells above one or more other levels of non-volatile memory cells. In one example implementation, the plurality of non-volatile memory cells are arranged in a three dimensional memory structure comprising vertical NAND strings. One embodiment includes a non-volatile memory apparatus, comprising: a block of non-volatile memory cells arranged in a three dimensional memory structure having multiple levels of non-volatile memory cells above other levels of non-volatile memory cells; a plurality of word lines connected to the non-volatile memory cells of the block; one or more sources of word line voltages; and a plurality of word line switches for the block that selectively connect the one or more sources of word line voltages to the word lines, the word line switches are arranged in three dimensional stacks, each stack comprises multiple word line switches vertically stacked. One embodiment includes a method, comprising: creating a stack of alternating layers of material and a support structure through the layers to mechanically hold the stack so it does not collapse when parts of the stack are removed; adding source and drain regions at multiple levels of the stack; adding gate layers that are connected to each other, at multiple levels of the stack to form word line switches at the multiple levels of the stack; and connecting the source and drain regions at multiple levels of the stack to word lines and one or more sources of word line voltages. In one example implementation, the creating the stack of alternating layers of material and support structure comprises: creating a stack of alternating layers of Si and SiGe; and creating pillar shaped structure to mechanically hold the stack so it does not collapse when parts of the stack are removed. In one example implementation, the adding source and drain regions at multiple levels of the stack comprises: creating recesses in the SiGe layers of the stack; lining the recesses with doped Si; annealing and diffusing the dopant; creating recesses in the doped Si; filling the recesses with dielectric material; creating a staircase profile in cross section; and replacing portion of doped Si with Tungsten. In one example implementation, the adding gate layers comprises: creating slot in gate area and deposit oxide; removing Si in the slot and lining with oxide; and replacing SiGe with metal gate material and depositing liner oxide. For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment. For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them. For purposes of this document, the term “based on” may be read as “based at least in part on.” For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects. For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects. The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. | 102,264 |
11943923 | Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer. As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend laterally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers. As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value). As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate. As used herein, the terms “staircase,” “step,” and “level” can be used interchangeably. As used herein, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A “staircase” refers to a vertical shift in the height of a set of adjoined surfaces. As used herein, the x-axis and the y-axis (perpendicular to the x-z plane) extend horizontally and form a horizontal plane. The horizontal plane is substantially parallel to the top surface of the substrate. As used herein, the z-axis extends vertically, i.e., along a direction perpendicular to the horizontal plane. The terms “x-axis” and “y-axis” can be interchangeably used with “a horizontal direction,” the term “x-y plane” can be interchangeably used with “the horizontal plane,” and the term “z-axis” can be interchangeably used with “the vertical direction.” As 3D memory devices scale down for higher memory capacity, more conductor layers, which function as gate electrodes of a 3D memory device, are stacked over a substrate within a designated space. Spacing between adjacent conductor layers along a vertical direction (i.e., the direction perpendicular to a top surface of the substrate) is reduced, resulting in a thinner gate-to-gate dielectric layer between the adjacent conductor layers. Conventionally, the gate-to-gate dielectric layer mainly includes silicon oxide (SiOx, e.g., SiO), of which the insulation is largely affected by its thickness and film quality between the adjacent conductor layers. Due to scaling, a thinner gate-to-gate dielectric layer, made of silicon oxide, can thus be susceptible to gate-to-gate leakage or even breakdown. In addition, a reduced spacing between adjacent conductor layers can also cause increased charge loss. For example, due to smaller distance between adjacent memory cells, charges trapped in a memory cell is more likely to escape from the memory cell and travel along a memory layer (e.g., along its extending direction). As a result, data retention in the memory layer can be impaired, and operations (e.g., read, write, and/or hold) on the memory cells may have reduced precision. Various embodiments in accordance with the present disclosure provide the structures and fabrication methods of 3D memory devices, which resolve the above-noted issues associated with thinner gate-to-gate dielectric layers. Embodiments of the present disclosure provide a gate-to-gate dielectric layer having at least one composite layer between adjacent conductor layers. The composite layer includes at least one sub-layer of silicon oxynitride (SiOxNy, e.g., SiON). As a high-k dielectric material, silicon oxynitride can provide better electric insulation between adjacent conductor layers. The gate-to-gate dielectric layer, even with a smaller thickness between adjacent conductor layers, can reduce the susceptibility to leakage and coupling. In some embodiments, the gate-to-gate dielectric layer includes at least an airgap between the adjacent conductor layers. In some embodiments, the gate-to-gate dielectric layer includes a pair of composite layers each on a different one of the adjacent conductor layers, and an airgap between the two composite layers. In some embodiments, the gate-to-gate dielectric layer includes a composite layer filling up the space between adjacent conductor layers without any airgap in between. The composite layer can include at least a sub-layer of silicon oxynitride. In some embodiments, the composite layer includes a plurality of sub-layers, which has at least one sub-layer of silicon oxynitride, each sandwiched by sub-layers of silicon oxide and/or silicon nitride. For example, the composite layer can include a plurality of alternatingly arranged sub-layers of silicon oxynitride and silicon oxide. Also, to reduce charge loss in 3D memory devices, in some embodiments, the memory layer in the semiconductor channel can have a “bent” structure or a “cut-off” structure to create a barrier between adjacent memory cells (e.g., conductor layers) for the charges. In a “bent” structure, the memory layer has a plurality of first memory portions and a plurality second memory portions. Each first memory portion partially surrounds a respective conductor layer, and each second memory portion connects adjacent first memory portions. The first memory portion includes a vertical portion (e.g., extending vertically) and a pair of lateral portions (e.g., extending laterally), connected together to partially surround a bottom of the respective conductor layer. The first memory portions and the second memory portions may thus extend in a staggered manner along the vertical direction, creating a barrier for the charges trapped in memory cells (e.g., first memory portions) along the vertical direction. This structure of the memory layer can reduce charge loss along the vertical direction. In a “cut-off” structure, different from the “bent” structure, the second memory portions between adjacent conductor layers are removed so the first memory portions are disconnected from one another. This structure of the memory layer can enhance the barrier for the charges between adjacent memory cells. FIGS.1A-1Eillustrate cross-sectional views of 3D memory devices each having a gate-to-gate dielectric layer, according to the present disclosure. Specifically,FIG.1Aillustrates a memory device101having a memory layer with a “cut-off” structure and a gate-to-gate dielectric layer with an airgap between adjacent conductor layers.FIG.1Billustrates a memory device102having a memory layer with a “cut-off” structure and a gate-to-gate dielectric layer without an airgap between adjacent conductor layers.FIG.1Cillustrates a memory device103having a memory layer with a “bent” structure and a gate-to-gate dielectric layer with an airgap between adjacent conductor layers.FIG.1Dillustrates a memory device104having a memory layer with a “bent” structure and a gate-to-gate dielectric layer without an airgap between adjacent conductor layers.FIG.1Eillustrates a memory device105having a memory layer without a “bent” structure or a “cut-off” structure and a gate-to-gate dielectric layer with an airgap between adjacent conductor layers.FIG.1Fillustrates a memory device106having a memory layer with a “bent” structure and a gate-to-gate dielectric layer with a pair of composite layers sandwiching a dielectric layer of a different material. For ease of description, same or similar parts inFIGS.1A-1Fare depicted using the same reference numbers. Embodiments of the present disclosure provide different types of memory devices configured for reducing the leakage and coupling between conductor layers and preventing trapped charges to travel in undesired directions. As examples, memory devices, having a semiconductor channel with a “cut-off” structure and a gate-to-gate dielectric layer with at least a sub-layer of a high-k dielectric material (e.g., silicon oxynitride) and an airgap, may be embodied by memory device101. Memory devices memory devices, having a semiconductor channel with a “bent” structure and a gate-to-gate dielectric layer with at least a sub-layer of a high-k dielectric material (e.g., silicon oxynitride), may be embodied by memory devices103,104, and106. Memory devices, formed by a “gate first” fabrication process and having a gate-to-gate dielectric layer with at least a sub-layer of a high-k dielectric material (e.g., silicon oxynitride) and an airgap, may be embodied by memory devices101,103, and105. Memory devices, formed by a “gate first” fabrication process, having a semiconductor channel with a “bent” structure and a gate-to-gate dielectric layer with at least a sub-layer of a high-k dielectric material (e.g., silicon oxynitride) and an airgap, may be embodied by memory device103. Memory devices, having a semiconductor channel with a “cut-off” structure and a gate-to-gate dielectric layer with at least a sub-layer of a high-k dielectric material (e.g., silicon oxynitride), may be embodied by memory devices101and102. Structures and fabrication processes of the memory devices are described in detail as follows. As shown inFIG.1A, memory device101includes a substrate10, a plurality of conductor layers18stacking over substrate10, and a plurality of gate-to-gate dielectric layers17each between and insulating adjacent conductor layers18. Conductor layers18, substrate10, and gate-to-gate dielectric layers17may form a stack structure. Memory device101may include a plurality of semiconductor channels14each extending vertically (e.g., along a direction perpendicular to a top surface of substrate10or the y-direction) through the stack structure into substrate10. Memory device101may also include a plurality of source structures extending through the stack structure and into substrate10. Each source structure may include a doped region16in substrate10, an insulating structure120extending through the stack structure, and a source contact121extending in insulating structure120and contacting doped region16. Source contact121may be electrically connected to semiconductor channel14through doped region16and substrate10. Substrate10can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOD, and/or any other suitable materials. In some embodiments, substrate10includes silicon. Conductor layers18can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. Gate-to-gate dielectric layer17may include one or more composite layers and at least an airgap between adjacent conductor layers18. In the present disclosure, a plurality of gate-to-gate dielectric layers17for insulating a plurality of conductor layers18in the stack structure (e.g., all the conductor layers18from top to bottom of the stack structure) may be referred to as a gate-to-gate dielectric structure. In some embodiments, gate-to-gate dielectric layer17includes a pair of composite layers17-1and17-2and an airgap173between composite layers17-1and17-2. In some embodiments, composite layers17-1and17-2may be formed in the space between adjacent conductor layers18and may be on the opposing surfaces of adjacent conductor layers18. In some embodiments, a thickness of a composite layer, e.g.,17-1or17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). In some embodiments, a thickness of airgap173may be dependent on the thicknesses of composite layers17-1and17-2, and the spacing between adjacent conductor layers18. Gate-to-gate dielectric layer17may include at least one sub-layer of a high-k dielectric material such as silicon oxynitride. In some embodiments, depending on the material of conductor layers18, the high-k dielectric material may also include material other than silicon oxynitride. In some embodiments, each composite layer, e.g.,17-1and17-2, may include a sub-layer of silicon oxynitride. Gate-to-gate dielectric layer17may also include sub-layers of other materials. In some embodiments, each composite layer, e.g.,17-1and17-2, may include at least a sub-layer of silicon oxide and/or silicon nitride. In some embodiments, each composite layer, e.g.,17-1and17-2, may include a plurality of sub-layers, having at least one sub-layer of silicon oxynitride, at least one sub-layer of silicon oxide, and at least one sub-layer of silicon nitride. In some embodiments, each composite layer, e.g.,17-1and17-2, may have a stack of sub-layers arranged as O/ON/O/ON/O, where “O” stands for silicon oxide and “ON” stands for silicon oxynitride. In some embodiments, each composite layer, e.g.,17-1and17-2, may have a stack of sub-layers arranged as O/ON/O/N/O/ON/O. In some embodiments, along the vertical direction, conductor layer18and the composite layers formed on conductor layer18(e.g., on the upper and lower surfaces of conductor layer18) are located in the space defined between ends of vertical portion132-1. In some embodiments, a total thickness of conductor layer18and the respective composite layers is less than a distance between the ends of vertical portion132-1. In some embodiments, an end of lateral portion132-2facing away from the respective vertical portion is exposed by a respective gate-to-gate dielectric layer17. For example, the end may be exposed by airgap173of the respective gate-to-gate dielectric layer17. In some embodiments, a composite layer, similar to or the same as17-1or17-2, may be formed on the top surface of substrate10. FIG.8Aillustrates an exemplary structure of gate-to-gate dielectric layer17. As shown inFIG.8A, x81represents a sub-layer of silicon oxide, x82represents a sub-layer of silicon oxynitride, and x83 represents an airgap. Sub-layers x81, x82, and x81, on one of the adjacent conductor layers18, may form a composite layer x8-1, and sub-layers x81, x82, and x81, on the other one of the adjacent conductor layers18, may form another composite layer x8-2. Composite layers x8-1, x8-2, and airgap x83may form a gate-to-gate dielectric layer17. It should be noted that the number of sub-layers in a composite layer should not be limited by the embodiments of the present disclosure. In some embodiments, a thickness of each of composite layers x81and x82is less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). Semiconductor channel14may include a blocking layer131, a memory layer132, a tunneling layer133, a semiconductor layer134, and a dielectric core19, arranged along a radial direction from the sidewall towards the center of semiconductor channel14. Blocking layer131may include a plurality of blocking portions, each under a bottom of a respective conductor layer18and disconnected from one another. Memory layer132may include a plurality of memory portions, each under the bottom of the respective conductor layer18and partially surrounds the respective conductor layer18. Each memory portion may be disconnected from one another. A memory portion may include a vertical portion132-1(e.g., extending along the vertical direction or the y-direction) and at least one lateral portion132-2(e.g., extending along the lateral direction or the x-direction) connected to vertical portion132-1. In some embodiments, a memory portion includes a vertical portion132-1and a pair of lateral portions132-2(e.g., each connected to a different end of vertical portion132-1). One end of lateral portion132-2may be connected to the respective vertical portion132-1, and the other end of lateral portion132-2may be facing away from the respective vertical portion132-1(e.g., being exposed by airgap173). The memory portion may be under and partially surrounding the respective block portion. Tunneling layer133, exposed by airgaps173, may be under and partially surrounding the respective memory portion. Blocking layer131can reduce or prevent charges from escaping into conductor layers18. Blocking layer131can include a single-layered structure or a multiple-layered structure. For example, blocking layer131can include a first blocking layer and a second blocking layer. The first blocking layer can be formed over the sidewall of a channel hole, and the second blocking layer may be formed over the first blocking layer. The first blocking layer can include a dielectric material (e.g., a dielectric metal oxide.) For example, the first blocking layer can include a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than 7.9.) Examples of the first blocking layer include AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, and/or alloys thereof. The second blocking layer can include a dielectric material that is different from the first blocking layer. For example, the second blocking layer can include silicon oxide, silicon oxynitride, and/or silicon nitride.FIG.7Aillustrates an exemplary blocking layer x31, which is the same as or similar to blocking layer131. As shown inFIG.7A, blocking layer x31includes a first blocking layer x31aand a second blocking layer x31b. First blocking layer x31amay include a high-k dielectric layer such as AIO. Second blocking layer x31bmay include a plurality of dielectric layers stacking laterally. For example, second blocking layer x31bmay include a pair of first dielectric layers x31cand a second dielectric layer x31d, where second dielectric layer x31dis sandwiched by first dielectric layers x31c. In some embodiments, first dielectric layer x31cincludes a silicon oxide, and second dielectric layer x31dincludes silicon oxynitride. Memory layer132can include a charge-trapping material and can be formed over blocking layer131. Memory layer132can include a single-layered structure or a multiple-layered structure. For example, memory layer132can include conductive materials and/or semiconductor such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, alloys thereof, nanoparticles thereof, silicides thereof, and/or polycrystalline or amorphous semiconductor materials (e.g., polysilicon and amorphous silicon). Memory layer132can also include one or more insulating materials such as SiN and/or SiON.FIG.7Billustrates an exemplary memory layer x32, which is the same as or similar to memory layer132. As shown inFIG.7B, memory layer x32may include a plurality of alternatingly arranged first memory sub-layers x32aand second memory sub-layers x32b. In some embodiments, first memory sub-layer x32aincludes silicon nitride, and second memory sub-layer x32bincludes silicon oxynitride. Tunneling layer133can include a dielectric material through which tunneling can occur under a suitable bias. Tunneling layer133can be formed over memory layer132and can include a single-layered structure or a multiple-layered structure. Tunneling layer133may include SiO, SiN, SiON, dielectric metal oxides, dielectric metal oxynitride, dielectric metal silicates, and/or alloys thereof.FIG.7Cillustrates an exemplary tunneling layer x33, which is the same as or similar to tunneling layer133. As shown inFIG.7C, tunneling layer x33may include a plurality of first tunneling sub-layers x33aand a second tunneling sub-layer x33b. In some embodiments, second tunneling sub-layer x33bmay be sandwiched by a pair of first tunneling sub-layers x33a. In some embodiments, first tunneling sub-layer x33aincludes silicon oxide, and second tunneling sub-layer x33bincludes a plurality of layers of silicon oxynitride. Semiconductor layer134can facilitate the transport of charges and can be formed over tunneling layer133. Semiconductor layer134can include one or more semiconductor materials such as a one-element semiconductor material, an III-V compound semiconductor material, an II-VI compound semiconductor material, and/or an organic semiconductor material. In some embodiments, semiconductor layer134includes a poly-silicon layer. Dielectric core19can include a suitable dielectric material and can fill up the space surrounded by semiconductor layer134. In some embodiments, dielectric core19includes silicon oxide (e.g., silicon oxide of sufficiently high purity). Doped region16can be formed in substrate10, contacting source contact121. Source contact121may be insulated from conductor layers18by insulating structure120. Source contact121may include any suitable conductive material that can be used as the source electrode, and doped region16may include a suitable doped (e.g., P-type or N-type) semiconductor region formed in substrate10and is opposite of the polarity of substrate10. In some embodiments, source contact121includes one or more of doped poly-silicon, copper, aluminum, cobalt, doped silicon, silicides, and tungsten. In some embodiments, doped region16includes doped silicon. In some embodiments, insulating structure120includes silicon oxide. FIG.1Billustrates a cross-section view of memory device102, according to some embodiments. Different from memory device101, gate-to-gate dielectric layer17has no airgap between adjacent conductor layers18and fills up the space between adjacent conductor layers18with a composite layer. In some embodiments, insulating structure120insulates source contact121from conductor layers18and gate-to-gate dielectric layers17. In some embodiments, the ends of lateral portions132-2, exposed portions of blocking layer131, and exposed portions of tunneling layer133, are covered by gate-to-gate dielectric layer17. In some embodiments, a composite layer fills up the space between substrate10and the conductor layer18closest to substrate10.FIG.8Billustrates an exemplary structure of the composite layer. As shown inFIG.8B, the composite layer may include a plurality of sub-layers, where at least one of the sub-layers include silicon oxynitride. In some embodiments, at least one of the sub-layers include silicon oxynitride and at least one of the sub-layers include silicon oxide. In some embodiments, at least one of the sub-layers include silicon oxynitride, at least one of the sub-layers include silicon oxide, and at least one of the sub-layers include silicon nitride. In some embodiments, x81represents silicon oxide and x82represents silicon oxynitride, and the composite layer include a plurality of alternatingly arranged sub-layers of silicon oxynitride and silicon oxide. In some embodiments, the number of sub-layers of each material and the thickness of each sub-layer may be associated with, e.g., the total thickness of the composite layer (e.g., the spacing between adjacent conductor layers18) and/or the fabrication process, and should not be limited by the embodiments of the present disclosure. FIG.1Cillustrates a cross-section view of memory device103, according to some embodiments. Different from memory device101, blocking layer131and memory layer132extend consistently along the horizontal direction and the vertical direction. Memory layer132may include a first memory portion132aunder and partially surrounding a bottom of the respective conductor layer18and composite layers on respective conductor layer18, and a second memory portion132bconnected to adjacent first memory portions132a. As shown inFIG.1C, blocking layer131may be over memory layer132, and may accordingly be under and partially surrounding the bottom of the respective conductor layer18and composite layers on respective conductor layer18. The lateral portions of blocking layer131may have contact with composite layers laterally. First memory portion132amay include a vertical portion132a-1and at least one lateral portion132a-2. In some embodiments, the first portion may include vertical portion132a-1and a pair of lateral portions132a-2. In some embodiments, second memory portion132bextends vertically. As shown inFIG.1C, second memory portions132band vertical portions132a-1of memory layer132may be staggered along the vertical direction. In some embodiments, a thickness of a composite layer, e.g.,17-1or17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). A detailed description of gate-to-gate dielectric layer17and composite layers17-1and17-2may be referred to the description of gate-to-gate dielectric layer17and composite layers17-1and17-2in memory device101, and is not repeated herein. FIG.1Dillustrates a cross-sectional view of memory device104, according to some embodiments. Different from memory device103, gate-to-gate dielectric layer17has no airgap between adjacent conductor layers18and fills up the space between adjacent conductor layers18with a composite layer. In some embodiments, a composite layer fills up the space between substrate10and the conductor layer18closest to substrate10. A detailed description of structures and materials of gate-to-gate dielectric layer17and the composite layer may be referred to the description of gate-to-gate dielectric layer17and the composite layer in memory device102, and is not repeated herein. FIG.1Eillustrates a cross-sectional view of memory device105, according to some embodiments. Different from memory devices101and103, memory device105includes a semiconductor channel14in which blocking layer131, memory layer132, tunneling layer133, and semiconductor layer134each extends continuously along the vertical direction. In some embodiments, a thickness of a composite layer, e.g.,17-1or17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). A detailed description of gate-to-gate dielectric layer17may be referred to the description of memory device101and is not repeated herein. FIG.1Fillustrates a cross-sectional view of memory device106, according to some embodiments. Different from memory device104, memory device106includes a dielectric layer170sandwiched by a pair of composite layers17-1and17-2, where dielectric layer170includes a material that is different from the materials of composite layers17-1and17-2. In some embodiments, dielectric layer170includes silicon nitride. Optionally, an adhesive layer124, including titanium and/or titanium oxide, is formed between conductor layer18and gate-to-gate dielectric layer17. In some embodiments, a thickness of a composite layer, e.g.,17-1or17-2, may be less than about 5 nm, such as less than 5 nm (e.g., 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). A detailed description of structures and materials of composite layers17-1and17-2may be referred to the description of composite layers17-1and17-2of memory device101, and is not repeated herein. FIGS.2A-2Gillustrate a method for forming a stack structure with semiconductor channels with “bent” structures, according to some embodiments. Structure200depicted inFIG.2Gcan be used as the base structure to form memory devices101-104.FIG.9Aillustrates the flowchart of fabrication process900depicted inFIGS.2A-2G. Referring toFIG.9A, at the beginning of the fabrication process, an initial channel hole is formed in a stack structure that has a plurality of alternatingly arranged first layers and second layers over a substrate (Operation902).FIGS.2A and2Billustrate corresponding structures. As shown inFIG.2A, a stack structure21having a plurality of alternatingly arranged first layers211and second layers212is formed over a substrate20. The material of substrate20may be referred to the description of substrate10and is not repeated herein. In some embodiments, substrate20includes silicon (N-type silicon). Stack structure21can provide the fabrication base for the formation of a 3D memory device. Memory strings (e.g., NAND memory strings) that include semiconductor channels and related structures/parts can be subsequently formed in stack structure21. In some embodiments, stack structure21includes a plurality of first layer211/second layer212pairs stacked vertically over substrate20, forming a staircase structure. Each first layer211/second layer212pair can include one first layer211and one second layer212, and can form a staircase/level. That is, stack structure21can include interleaved first layers211and second layers212stacked along the vertical direction. The number of first layer211/second layer212pairs in stack structure21(e.g.,32,64,96, or128) can set the number of memory cells in the 3D memory device. First layers211can each have the same thickness or have different thicknesses. Similarly, second layers212can each have the same thickness or have different thicknesses. Second layers212can include any suitable materials that are different from the material of first layers211so that an etchant (e.g., used in the subsequent fabrication process to remove first layers211) can have a higher etch rate on first layers211over second layers212. That is, the etchant can selectively etch first layers211over second layers212. In some embodiments, first layers211can include a sacrificial material and second layers212can include a conductor material. In some embodiments, first layers211can include a sacrificial material and second layers212can include another sacrificial layer. The specific choices of materials of first layers211and second layers212should be determined by the fabrication process (e.g., the gate-first fabrication process or the gate-last fabrication process) and will be explained in detail as follows. Stack structure21can be formed by, e.g., repetitively etching a dielectric stack of a plurality of first material layer/second material layer pairs vertically and laterally. The etching of the first material layer/second material layer pairs can include repetitively etching/trimming an etch mask (e.g., a photoresist layer) over the dielectric stack to expose the portion of first material layer/second material layer pair to be etched, and etching/removing the exposed portion using a suitable etching process. The etching of the etch mask and the insulating material layer/sacrificial material layer pairs can be performed using any suitable etching processes such as wet etch and/or dry etch. In some embodiments, the etching includes dry etch, e.g., inductively coupled plasma etching (ICP) and/or reactive-ion etch (RIE). An initial channel hole22can be formed in stack structure21. In some embodiments, initial channel hole22extends from a top surface of stack structure21to substrate20. In some embodiments, a bottom portion of initial channel hole22exposes substrate20. Initial channel hole22can be formed by any suitable fabrication process. For example, a patterned photoresist layer can be formed over stack structure21. The patterned photoresist layer can expose a portion of stack structure21for forming initial channel hole22. A suitable etching process can be performed to remove the portion of stack structure21until substrate20is exposed. The etching process can include a dry etching process. Referring back toFIG.9A, after initial channel holes are formed, a channel hole is formed by removing a portion of each first layer on a sidewall of the initial channel hole to form an offset between a side surface of a second layer and side surfaces of adjacent first layers (Operation904).FIG.2Cillustrates a corresponding structure. As shown inFIG.2C, a portion of each first layer211on the sidewall of initial channel hole22can be removed to form channel hole222. For ease of description, the surface of first layer211(or second layer212) facing initial channel hole22or channel hole222is referred to as a side surface of first layer211(or second layer212). In some embodiments, an offset224can be formed on the side surface of first layer211. The dimension or thickness of the removed portion (e.g., along the later direction or the x-direction) of first layer211can be any suitable value that allows an offset to be formed between the side surface of second layer212and first layer211. In some embodiments, the side surfaces of second layers212form protrusions along the sidewall of channel hole222. Any suitable selective etching process (e.g., a recess etch) can be performed to form offsets224. In some embodiments, the selective etching process has a high etching selectivity on first layers211over second layers212, causing little or no damage on second layers212. A wet etch and/or a dry etch can be performed as the selective etching process. In some embodiment, an RIE is performed as the selective etching process. Referring toFIG.9A, after the formation of the channel hole, a channel-forming structure is formed to fill up the channel hole, and a semiconductor channel is formed (Operation906).FIGS.2D-2Fillustrates corresponding structures. As shown inFIG.2D-2F, a semiconductor channel24can be formed by filling channel hole222with a channel-forming structure. The channel forming structure may include a blocking layer231deposited along the sidewall of channel hole222, a memory layer232over the blocking layer, a tunneling layer233over the blocking layer, a semiconductor layer234over the tunneling layer, and a dielectric core29filling up the rest of channel hole222. Each of these layers may be respectively the same as or similar to blocking layer131, memory layer132, tunneling layer133, semiconductor layer134, and dielectric core19illustrated inFIG.1A. A detailed description of the materials of these layers is thus not repeated herein. As shown inFIG.2D, in some embodiments, a blocking material layer, a memory material layer, and a tunneling material layer, are sequentially deposited in channel hole222along a radial direction from the sidewall towards the center of channel hole222. The materials of the blocking material layer, the memory material layer, and the tunneling material layer can be referred to the description of blocking layer131, memory layer132, and tunneling layer133, and are not repeated herein. The blocking material layer can be formed by a suitable deposition method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), low pressure CVD (LPCVD), and/or liquid source misted chemical deposition. The memory material layer can be formed by any suitable deposition method such as CVD, ALD, and physical vapor deposition (PVD). The tunneling material layer can be formed by a suitable deposition method such as CVD, ALD, and/or PVD. A recess etching process, such as dry etch, can be performed to remove portions of the blocking material layer, the memory material layer, and the tunneling material layer at the bottom of channel hole222to expose substrate20. Blocking layer231, memory layer232, and tunneling layer233can then be formed accordingly. As shown inFIGS.2E and2F, a semiconductor layer234is deposited over tunneling layer233and substrate20, and a dielectric core29is deposited over semiconductor layer234to fill up the rest of the space in channel hole222, forming semiconductor channel24. Semiconductor layer234can be formed by any suitable deposition method such as LPCVD, ALD, and/or metal-organic chemical vapor deposition (MOCVD). In some embodiments, dielectric core29includes SiO (e.g., SiO of sufficiently high purity) and can be formed by any suitable deposition method such as CVD, LPCVD, ALD, and/or PVD. Referring back toFIG.9A, after the formation of the semiconductor channel, a first initial slit opening is formed in the stack structure (Operation908).FIG.2Gillustrates a corresponding structure200. As shown inFIG.2G, a first initial slit opening25is formed to extend through the stack structure and expose substrate20. A suitable etching process, e.g., a dry etching process, can be performed to form first initial slit opening25. FIGS.3A-3Jillustrate a “gate first” method to form memory devices103and104based on structure200, according to some embodiments. Specifically,FIGS.3A,3C,3E,3G, and3Iillustrate the fabrication process to form memory device103based on structure200, andFIGS.3B,3D,3F,3H, and3Jillustrate the fabrication process to form memory device104based on structure200. In the “gate first” method, first layers211include a sacrificial material and second layers212include a conductor material for subsequently forming conductor layers18. In some embodiments, second layers212include polysilicon.FIG.9Billustrates the flowchart of fabrication process920depicted inFIGS.3A-3Jto form memory devices103and104. As shown inFIG.9B, at the beginning of the fabrication process, the plurality of first layers are removed (Operation922) and a gate-to-gate dielectric layer is formed between adjacent conductor layers (Operation924). A second initial slit opening is formed from the first initial slit opening.FIGS.3A and3Brespectively illustrate a corresponding structure. In some embodiments, an isotropic etching process (e.g., wet etch) is performed to remove first layers211and expose blocking layer231and substrate20. A plurality of lateral recesses can be formed from the removal of first layers211. As shown inFIG.3A, an oxidation reaction and/or a nitriding reaction may be performed to form a composite layer from a portion of second layer212that reacts with the reactants. The unreacted portion of second layer212may form a conductor layer38that can function as a gate electrode of memory device103. The reacted portion of second layer212may form a composite layer37-1or37-2(e.g., similar to or the same as17-1or17-2) covering conductor layer38. The composite layer may be formed from a top portion/upper surface of second layer212and from a bottom portion/lower surface of second layer212. An airgap373may be formed between composite layers37-1and37-2on adjacent conductor layers38. In some embodiments, a pair of composite layers (e.g.,37-1and37-2) facing each other and on adjacent conductor layers38and airgap373in between may form a gate-to-gate dielectric layer37, similar to or the same as gate-to-gate dielectric layer17illustrated inFIGS.1A and1C. In some embodiments, the composite layer (e.g.,37-1or37-2) may also be formed on the side surface of second layers212(e.g., the sidewall of first initial slit opening25), forming a second initial slit opening35A from first initial slit opening25. In some embodiments, a plurality of gate-to-gate dielectric layers37are formed by oxidizing and/or nitriding second layers212through first initial slit opening25and the lateral recesses. In some embodiments, to form plurality of gate-to-gate dielectric layers37, oxygen diffusion concentration and/or nitrogen diffusion concentration is controlled, such that each gate-to-gate dielectric layer37includes at least one sub-layer of silicon oxynitride. In some embodiments, each composite layer (e.g.,37-1or37-2) includes at least a sub-layer of silicon oxynitride. In some embodiments, oxygen and/or nitrogen diffusion concentration are controlled, so each of the plurality of gate-to-gate dielectric layers37can have the structures described inFIG.1A. For example, each gate-to-gate dielectric layer37includes a pair of composite layers (e.g.,37-1and37-2), each including a plurality of alternatingly arranged sub-layers of silicon oxynitride and silicon oxide. The specific structure of each composite layer should not be limited by the embodiments of the present disclosure. In some embodiments, a composite layer may be formed over substrate20from the oxidation and/or nitridation reaction. Different from the process to form gate-to-gate dielectric layer37from portions of second layers212, as shown inFIG.3B, gate-to-gate dielectric layer37can be formed by depositing a dielectric material to fill up the lateral recesses and performing an oxidizing reaction and/or a nitriding reaction to form the at least one sub-layer of silicon oxynitride in each gate-to-gate dielectric layer37. The process can be performed through the lateral recess and first initial slit opening25. In some embodiments, a dielectric material, such as silicon oxide or silicon nitride, may be deposited by a suitable deposition method, e.g., CVD, ALD, and/or PVD, to fill up the lateral recesses. An oxidizing reaction and/or a nitriding reaction may be performed on the deposited dielectric material between adjacent second layers212to form gate-to-gate dielectric layer37, which includes a composite layer having at least one sub-layer of silicon oxynitride. In some embodiments, each composite layer includes at least a sub-layer of silicon oxynitride. In some embodiments, oxygen and/or nitrogen diffusion concentration are controlled so each of the plurality of gate-to-gate dielectric layers37can have the structures described inFIG.1B. For example, each gate-to-gate dielectric layer37includes a composite layer having a plurality of alternatingly arranged sub-layers of silicon oxynitride and silicon oxide. No airgap is formed between adjacent second layers212. In some embodiments, gate-to-gate dielectric layer37covers blocking layer231. The specific structure of each composite layer should not be limited by the embodiments of the present disclosure. In some embodiments, second layers212form conductor layers38. In some embodiments, an adhesion layer (not shown) may be formed on second layers212before the deposition of the dielectric material. In some embodiments, the composite layer may also be formed on the side surface of second layers212(e.g., the sidewall of first initial slit opening25), forming a second initial slit opening35B from first initial slit opening25. In some embodiments, a composite layer may be formed over substrate20from the oxidation and/or nitridation reaction. Referring back toFIG.9B, after the formation of gate-to-gate dielectric layers, a doped region may be formed in the substrate at a bottom of the second initial slit opening (Operation926).FIGS.3Cand 3D illustrate corresponding structures. As shown inFIGS.3Cand 3D, a doped region36may be formed in substrate20at the bottom of the second initial slit opening (e.g.,35A inFIGS.3C and35BinFIG.3D). A suitable doping process, such as ion implantation, can be performed to form doped region36. In some embodiments, a portion of the composite layer at the bottom of the second initial slit opening (e.g.,35A and35B) is removed to expose substrate20before the doping process. In some embodiments, the portion of the composite layer at the bottom of the second initial slit opening (e.g.,35A and35B) is retained. Referring back toFIG.9B, after the formation of the doped region, a slit opening is formed from the second initial slit opening (Operation928).FIGS.3E and3Fillustrate corresponding structures. As shown inFIGS.3E and3F, a slit opening (e.g.,350A inFIGS.3E and350BinFIG.3F) is formed from respective second initial slit opening (e.g.,35A inFIGS.3C and35BinFIG.3D). In some embodiments, a recess etch is performed to remove any excess materials from the side surfaces of conductor layers38, forming slit opening350A/350B. In some embodiments, excess material (e.g., the material of a composite layer) over substrate20at the bottom of second initial slit opening35A/35B can also be etched and removed. The sidewall of slit opening350A/350B may expose conductor layers38. In some embodiments, the sidewall of slit opening350A exposes airgaps373. In some embodiments, the sidewall of slit opening350A/350B also exposes gate-to-gate dielectric layers37. Referring back toFIG.9B, an insulating structure is formed in the slit opening (Operation930).FIGS.3G and3Hillustrate corresponding structures. As shown inFIGS.3G and3H, an insulating structure (e.g.,320A inFIGS.3G and320BinFIG.3H) may be formed in respective slit structure (e.g.,350A inFIGS.3G and350BinFIG.3H). In some embodiments, insulating structure320A/320B is formed over the sidewall of respective slit opening350A/350B and exposes substrate20(e.g., or doped region36) at the bottom of respective slit opening350A/350B. In some embodiments, insulating structure320A/320B includes a dielectric material, such as silicon oxide, and is deposited by a suitable deposition process such as CVD, ALD, LPCVD, and/or PVD. In some embodiments, a recess etch (e.g., dry etch and/or wet etch) is performed to remove any excess material (e.g., material deposited during the formation of insulating structure320A/320B) at the bottom of slit structure350A/350B to expose substrate20(e.g., or doped region36). Referring back toFIG.9B, after the formation of insulating structure, a source contact is formed in the insulating structure (Operation932).FIGS.3I and3Jillustrate corresponding structures. As shown inFIGS.3I and3J, a suitable conductive material can be deposited in insulating structure320A/320B to form a respective source contact321. Any suitable deposition method can be used to form source contact321. For example, source contact321can be formed by CVD, ALD, and/or PVD. In some embodiments, source contact321includes tungsten and is deposited by CVD. In some embodiments, source contact321A, doped region36, and respective insulating structure320A/320B form a source structure. A suitable planarization process (e.g., recess etch and/or chemical-mechanical polishing) can be performed to planarize the top surface of the stack structure, e.g., planarizing the source structures, semiconductor channels24, and/or gate-to-gate dielectric layers37. FIGS.4A-4Gillustrate a “gate first” method to form memory devices101and102based on structure200, according to some embodiments. Specifically,FIGS.4A,4B,4D, and4F illustrate the fabrication process to form memory device101based on structure200, andFIGS.4A,4C,4E, and4Gillustrate the fabrication process to form memory device102based on structure200. In the “gate first” method, first layers211include a sacrificial material and second layers212include a conductor material for subsequently forming conductor layers18. In some embodiments, second layers212include polysilicon.FIG.9Cillustrates a flowchart940for fabrication processes depicted inFIGS.4A-4Gto form memory devices101and102. As shown inFIG.9C, at the beginning of the fabrication process, the plurality of first layers are removed (Operation942) and a memory layer having a memory portion under a bottom of each second layer is formed (Operation944). The memory portions are disconnected from one another.FIG.4Aillustrates a corresponding structure. In some embodiments, an isotropic etching process (e.g., wet etch) is performed to remove the first layers (e.g.,211) to form a plurality of lateral recesses that expose the blocking layer (e.g.,231) and the substrate (e.g.,20). As shown inFIG.4A, a blocking layer431having a plurality of blocking portions, each under a bottom of a respective second layer212and disconnected from each other, is formed. Also, a memory layer432having a plurality of memory portions, each under a respective blocking portion, is formed. Each memory portion may include a vertical portion432-1and at least one lateral portion432-2connected to vertical portion432-1. In some embodiments, each memory portion includes a pair of lateral portions432-2being connected to a different end of the respective vertical portion432-1. Each memory portion may surround the respective blocking portion under the bottom of the respective second layer212and may be disconnected from one another along the vertical direction. A tunneling layer433under and partially surrounding memory layer432is also formed and extend along the vertical direction consistently. In some embodiments, tunneling layer433may be exposed between adjacent second layers212. A suitable etching process (e.g., a wet etch) may be performed on structure200to remove portions of semiconductor channel24from first initial slit opening25and the lateral recesses. In some embodiments, at least second memory portions232bare removed to expose lateral portions232a-2of first memory portions232a. First memory portions232amay fully or partially be retained to form the memory portions. Depending on the etching process, lateral portions232-2may be over-etched, and the length of lateral portion232a-2may vary along the lateral direction in different applications. In some embodiments, portions of blocking layer231and tunneling layer233may also be removed during the etching process. Blocking portions, disconnected from one another and over memory portions, may be formed. Semiconductor channel24, after the formation of memory portions, may form a semiconductor channel44. Referring back toFIG.9C, a gate-to-gate dielectric layer is formed between adjacent conductor layers and a second initial slit opening is formed (Operation946). Also, a doped region is formed in the substrate at the bottom of the second initial list opening (Operation948).FIGS.4B and4Crespectively illustrate a corresponding structure. FIG.4Billustrates a gate-to-gate dielectric layer47with an airgap. As shown inFIG.4B, a gate-to-gate dielectric layer47, a conductor layer48, a second initial opening45A, and a doped region46may be formed in the stack structure. In some embodiments, gate-to-gate dielectric layer47includes a pair of composite layers47-1and47-2, and an airgap473between composite layers47-1and47-2. The fabrication process to form these structures may be referred to the fabrication process to form gate-to-gate dielectric layer37, conductor layer38, second initial slit opening35A, and doped region36illustrated inFIGS.3A and3C, and is not repeated herein. FIG.4Cillustrates a gate-to-gate dielectric layer47without an airgap. As shown inFIG.4C, gate-to-gate dielectric layer47, a conductor layer48, a second initial opening45B, and a doped region46may be formed in the stack structure. In some embodiments, gate-to-gate dielectric layer47includes a composite layer filling up the space between adjacent conductor layers48. In some embodiments, gate-to-gate dielectric layer47covers the exposed portions of blocking layer431, memory layer432, and tunneling layer433. The fabrication process to form these structures may be referred to the fabrication process to form gate-to-gate dielectric layer37, conductor layer38, second initial slit opening35B, and doped region36illustrated inFIGS.3B and3D, and is not repeated herein. Referring back toFIG.9C, after the formation of the doped region and gate-to-gate dielectric layer, a slit opening is formed from the second initial slit opening (Operation950) and an insulating structure is formed in the slit opening (Operation952).FIGS.4D and4Erespectively illustrate a corresponding structure. As shown inFIGS.4D and4E, a slit opening (e.g.,450A inFIGS.4D and450BinFIG.4E) and an insulating structure (e.g.,420A inFIGS.4D and420BinFIG.4E) can be formed. The fabrication process to form slit opening450A and insulating structure420A may be referred to the fabrication process to form slit opening350A and insulating structure320A inFIGS.3E and3G, and the fabrication process to form slit opening450B and insulating structure420B may be referred to the fabrication process to form slit opening350B and insulating structure320B inFIGS.3F and3H. Details are not repeated herein. Referring back toFIG.9C, after the formation of the slit opening and the insulating structure, a source contact is formed in the insulating structure (Operation954).FIGS.4F and4Grespectively illustrate a corresponding structure. As shown inFIGS.4F and4G, a source contact421is formed in respective insulating structure (e.g.,420A inFIGS.4F and420BinFIG.4G), contacting the respective doped region46. The fabrication process to form source contact421can be referred to the fabrication process to form source contact321illustrated inFIGS.3I and3J. Details are not repeated herein. FIGS.5A-5D,5E, and SI illustrate a “gate first” method to form memory device105, which has an airgap in a gate-to-gate dielectric layer, according to some embodiments.FIGS.5A-5D,5F, and5Jillustrate a “gate first” method to form a memory device without an airgap in a gate-to-gate dielectric layer, according to some embodiments.FIG.10illustrates a flowchart1000for fabrication processes depicted inFIGS.5A-5J. At the beginning of the fabrication process, a semiconductor channel is formed in a stack structure (Operation1002).FIGS.5A-5Cillustrate corresponding structures. As shown inFIGS.5A-5C, a semiconductor channel54can be formed in a stack structure51over a substrate50. As shown inFIG.5A, stack structure51may include a plurality of alternatingly arranged first layers511and second layers512forming a plurality of staircases, where each first layer511/second layer512form a staircase/level. First layers511may include a sacrificial material, and second layers512may include a conductor material for forming conductor layers that subsequently function as the gate electrodes of the memory device. Detailed description of the material of substrate50, and the material and fabrication process to form stack structure51can be referred to the description of substrate20and stack structure21inFIG.2A, and is not repeated herein. In some embodiments, substrate50includes silicon, first layer511includes silicon nitride and/or silicon oxide, and second layers512include polysilicon. As shown inFIG.5A, a channel hole52may be formed extending vertically through stack structure51. The fabrication process to form channel hole52may be similar to or the same as the fabrication process to form initial channel hole22(e.g., illustrated inFIG.2B). Different from the formation of channel hole222illustrated inFIG.2C, no offset is formed between side surfaces of first layer511and second layer512in channel hole52. That is, the side surfaces of first layer511and second layer512may be coplanar along the vertical direction. A blocking material layer531m, a memory material layer532m, and a tunneling material layer533mmay be sequentially deposited over the sidewall of channel hole52. The materials and deposition processes to form these material layers can be referred to the description of materials and deposition processes of the blocking material layer, the memory material layer, and the tunneling material illustrated inFIG.2D, and are not repeated herein. As shown inFIG.5B, portions of blocking material layer531m, memory material layer532m, and tunneling material layer533mmay be removed to expose substrate50. An etching process, similar to the etching process illustrated inFIG.2D, may be performed, and blocking layer531, memory layer532, and tunneling layer533, may be formed. As shown inFIG.5C, a semiconductor layer534and a dielectric core59may sequentially be deposited to fill up channel hole52and form semiconductor channel54. The materials and deposition processes to form semiconductor layer534and dielectric core may be referred to the description of materials and deposition processes to form semiconductor layer234and dielectric core29illustrated inFIGS.2E and2F, and are not repeated herein. Referring back toFIG.10, after the formation of the semiconductor channel, a gate-to-gate dielectric layer is formed between adjacent conductor layers, and a second initial slit opening is formed (Operation1004).FIGS.5D and5Eillustrate corresponding structures having a gate-to-gate dielectric layer with an airgap.FIGS.5D and5Fillustrate corresponding structures having a gate-to-gate dielectric layer without an airgap. As shown inFIG.5D, a first initial slit opening55can be formed extending vertically through the stack structure, and first layers511may be removed through first initial slit openings55to form a plurality of lateral recesses. The formation of first initial slit openings55can be referred to the formation of first initial slit opening25illustrated nFIG.2G, and the formation of lateral recesses and can be referred to the formation of lateral recesses illustrated inFIG.3A. In some embodiments, portions of block layer531are exposed in the lateral recesses. Details are not repeated herein. FIG.5Eillustrates a structure formed from the structure illustrated inFIG.5D. In some embodiments, as shown inFIG.5E, a gate-to-gate dielectric layer57and a second initial slit opening55A can be formed. Gate-to-gate dielectric layer57may be located between adjacent conductor layers58. Gate-to-gate dielectric layer57may include a pair of composite layers57-1and57-2, and an airgap573between composite layers57-1and57-2. The materials, structures, and fabrication process to form gate-to-gate dielectric layer57and second initial slit opening55A may be referred to the description of materials, structures, and fabrication process to form gate-to-gate dielectric layer37and second initial slit opening35A illustrated inFIG.3Aand are not repeated herein. FIG.5Fillustrates another structure formed from the structure illustrated inFIG.5D. In some embodiments, as shown inFIG.5E, a gate-to-gate dielectric layer57and a second initial slit opening55B can be formed. Gate-to-gate dielectric layer57may be located between adjacent conductor layers58and have no airgap between adjacent conductor layers58. Gate-to-gate dielectric layer57may include a composite layer between adjacent conductor layers58. The materials, structures, and fabrication process to form gate-to-gate dielectric layer57and second initial slit opening55B may be referred to the description of materials, structures, and fabrication process to form gate-to-gate dielectric layer37and second initial slit opening35B illustrated inFIG.3Band are not repeated herein. Referring back toFIG.10, after the formation of gate-to-gate dielectric layers and second initial slit openings, a doped region is formed at the bottom of the second slit structure and a slit structure is formed from the second initial slit structure (Operation1006).FIGS.5G and5Heach illustrates a respective structure. As shown inFIGS.5G and5H, a doped region56is formed in respective substrate50, and a slit structure (e.g.,550A inFIGS.5G and550BinFIG.5H) is formed extending through the stack structure and exposing substrate50(e.g., the respective doped region56). The specific fabrication processes to form doped region56and slit opening550A/550B should be referred to the description of fabrication processes to form doped region36and slit opening350A/350B, and are not repeated herein. Referring back toFIG.10, after the formation of the doped region and slit structure, an insulating structure is formed in the slit structure and a source contact is formed in the insulating structure (Operation1008).FIGS.5I and5Jeach illustrates a respective structure. As shown inFIGS.5I and5J, an insulating structure (e.g.,520A inFIGS.5I and520BinFIG.5J) and a source contact521are formed in respective insulating structure520A/520B. In some embodiments, source contact521contacts respective doped region36. Description of materials and fabrication processes to form insulating structures520A/520B and source contact521should be referred to the description of materials and fabrication processes to form insulating structures320A/320B and source contact521illustrated inFIGS.3I and3J, and are not repeated herein. FIGS.6A-6Iillustrate a “gate last” method to form memory devices with a gate-to-gate dielectric layer between adjacent conductor layers from structure200, according to some embodiments. Specifically,FIGS.6A,6B,6D,6F, and6Hillustrate the fabrication process to form a gate-to-gate dielectric layer from an entirety of each of the plurality of first layers, andFIGS.6A,6C,6E,6G, and6Iillustrate the fabrication process to form a gate-to-gate dielectric layer from a portion of each of the plurality of first layers. In some embodiments,FIGS.6A,6B,6D,6F, and6Hillustrate the fabrication process to form memory device104, andFIGS.6A,6C,6E,6G, and6Iillustrate the fabrication process to form memory device106. In this “gate last” method, first layers211include a dielectric material for forming the gate-to-gate dielectric layers and second layers212include a sacrificial material for forming the conductor layers that function as gate electrodes. The dielectric material may include silicon oxide and/or silicon nitride. In some embodiments, first layers211include silicon nitride. In some embodiments, second layers212include a different material than the material of first layers211. In some embodiments, second layers212include polysilicon, carbon, and/or organic films.FIG.9Dillustrates a flowchart960for fabrication processes depicted inFIGS.6A-6I. As shown inFIG.6A, at the beginning of the fabrication process, the plurality of second layers are removed (Operation962).FIG.6Aillustrates a corresponding structure. In some embodiments, an isotropic etching process (e.g., wet etch) is performed to remove second layers212and expose blocking layer231and substrate20. A plurality of lateral recesses62can be formed from the removal of second layers212through first initial slit opening25. Portions of blocking layer231can be exposed by lateral recesses62. Referring back toFIG.9D, after the removal of second layers and formation of lateral recesses, a gate-to-gate dielectric layer is formed between adjacent lateral recesses and a second initial slit opening is formed (Operation964).FIGS.6B and6Ceach illustrates a corresponding structure. In some embodiments, gate-to-gate dielectric layers67ofFIGS.6A and6Bare formed by oxidizing first layers211through first initial slit opening25and lateral recesses62. In some embodiments, to form a plurality of gate-to-gate dielectric layers67, oxygen diffusion concentration is controlled, such that each gate-to-gate dielectric layer37includes a desired number of sub-layers of silicon oxynitride and/or silicon oxide. The specific structure of each composite layer should not be limited by the embodiments of the present disclosure. A second initial slit opening (e.g.,65A inFIGS.6B and65BinFIG.6C) may be formed from the respective first initial slit opening (e.g.,25inFIG.6A) by the oxidation process on first layers211. In some embodiments, an oxidized layer61may be formed over substrate20at the bottom of second initial slit structure65A/65B from the oxidation reaction between oxygen and substrate20. FIG.6Billustrates the structure in which each gate-to-gate dielectric layer is formed by fully oxidizing each first layer211. As shown inFIG.6B, an oxidation reaction may be performed to form a gate-to-gate dielectric layer67from the oxidation of the entire portion of each first layer211. Each gate-to-gate dielectric layer67may include a composite layer that includes at least a sub-layer of silicon oxynitride, formed from the entire portion of a respective first layer211, between adjacent conductor layers that are subsequently formed. In some embodiments, each composite layer includes at least a sub-layer of silicon oxynitride and at least a sub-layer of silicon oxide. In some embodiments, each composite layer includes a plurality of alternating arranged sub-layers of silicon oxynitride and silicon oxide, such as the structure illustrated inFIG.8B. FIG.6Cillustrates the structure in which a gate-to-gate dielectric layer67is formed by partially oxidizing each first layer211. Gate-to-gate dielectric layer67may include a pair of composite layers (e.g.,67-1and67-2) that are formed from the oxidation of the outside portion, instead of the entire portion, of each first layer211. As shown inFIG.6C, an oxidation reaction may be performed to form a gate-to-gate dielectric layer67from the outside portion of each first layer211. Each gate-to-gate dielectric layer67may include a pair of composite layers (e.g.,67-1and67-2) formed between adjacent conductor layers that are formed subsequently. Each composite layer may be formed from an outside portion of first layer211. In some embodiments, composite layer67-1is formed from a top portion of first layer211(e.g., a portion extending from the upper surface of first layer211into the inside of first layer211) and composite layer67-2is formed from a bottom portion of the same first layer211(e.g., a portion extending from the lower surface of first layer211into the inside of first layer211). The unreacted portion of first layer211may be sandwiched or surrounded by composite layers67-1and67-2, and may be referred to as an unreacted dielectric layer670(e.g., consisting of silicon nitride). In some embodiments, gate-to-gate dielectric layer67includes a pair of composite layers67-1and67-2and unreacted dielectric layer670between composite layers67-1and67-2. The thicknesses of composite layers67-1and67-2, and unreacted dielectric layer670may each be determined by the oxidation process, where the thickness of unreacted dielectric layer670is greater than zero. In some embodiments, each composite layer67-1/67-2includes at least a sub-layer of silicon oxynitride. In some embodiments, each composite layer67-1/67-2includes at least a sub-layer of silicon oxynitride and at least a sub-layer of silicon oxide. In some embodiments, each composite layer includes a plurality of alternating arranged sub-layers of silicon oxynitride and silicon oxide, such as the structure illustrated inFIG.8B. In some embodiments, gate-to-gate dielectric layer67includes a pair of composite layers67-1and67-2, and the unreacted dielectric layer670between composite layers67-1and67-2. That is, gate-to-gate dielectric layer67includes a sub-layer of silicon nitride sandwiched by two alternatingly arranged stacks of sub-layers of silicon oxynitride and silicon oxide. Referring back toFIG.9D, after the formation of gate-to-gate dielectric layers, a plurality of conductor layers and a slit opening are formed (Operation966).FIGS.6D and6Eeach illustrates a corresponding structure. As shown inFIGS.6D and6E, a plurality of conductor layers68and a respective slit opening (e.g.,650A inFIGS.6D and650BinFIG.6E) is formed from the respective second initial slit opening65A/65B. In some embodiments, a conductor material layer can be deposited into each lateral recesses62to fill up the space in lateral recess62through respective second initial slit opening65A/65B, and a recess etch (e.g., dry and/or wet etch) can be performed to remove any excess conductor material layer and portions of composite layer67-1/67-2on the sidewall of second initial slit opening65A/65B, forming respective conductor layers68and respective slit opening650A/650B. In some embodiments, conductor layers68includes tungsten, copper, aluminum, cobalt, silicides, doped and/or polysilicon. In some embodiments, an adhesive layer624is deposited in lateral recesses62through respective second initial slit openings before the deposition of conductor material layer, e.g., to improve the adhesion between the conductor material layer and gate-to-gate dielectric layer67. In some embodiments, adhesion layer624includes titanium (Ti) and/or titanium nitride (TiN). In some embodiments, the conductor material layers and adhesive layers624are each deposited by a suitable method such as one or more of CVD, ALD, LPCVD, and/or PVD. Referring back toFIG.9D, after the formation of conductor layers, a doped region is formed in the substrate at a bottom of the slit opening and an insulating structure is formed in the slit opening (Operation968).FIGS.6F and6Geach illustrates a corresponding structure. As shown inFIGS.6F and6G, a respective doped region66can be formed in substrate20. Doped region16may include a suitable doped (e.g., P-type or N-type) semiconductor region formed in substrate10and is opposite from the polarity of substrate20. A suitable doping process, such as ion implantation, can be performed to form doped region66. In some embodiments, doped region66includes doped silicon. A respective insulating structure (e.g.,620A inFIGS.6F and620BinFIG.6G) can be formed to insulate respective conductor layers68from subsequently-formed source contacts. In some embodiments, insulating structure620A/620B each covers the sidewall of the respective slit opening and exposes substrate20(e.g., respective doped region66). In some embodiments, insulating structure620A covers the side surfaces of composite layers of gate-to-gate dielectric layer67, conductor layers68, and adhesion layer624. In some embodiments, insulating structure620B covers the side surfaces of composite layers of gate-to-gate dielectric layer67, unreacted dielectric layer670of gate-to-gate dielectric layer67, conductor layers68, and adhesion layer624. To form insulating structure620A/620B, a suitable insulating material can be deposited to cover the sidewall of the respective slit opening650A/650B, and a suitable recess etch (e.g., dry etch and/or wet etch) can be performed to remove excess portions of the insulating material on the sidewall and bottom of slit opening650A/650B. Respective oxidized layer61can also be removed by the recess etching process. Insulating structure620A/620B can be formed in slit opening650A/650B. In some embodiments, insulating structure120includes silicon oxide and is deposited by any one of CVD, ALD, LPCVD, and/or PVD. In various embodiments, the order to form respective insulating structure620A/620B and doped region66can vary based on different fabrication operations and should not be limited by the embodiments of the present disclosure. Referring back toFIG.9D, after the formation of insulating structures and doped regions, a source contact is formed in the insulating structure (Operation970).FIGS.6H and6Ieach illustrates a corresponding structure. As shown inFIGS.6H and6I, a source contact621is formed in respective insulating structure620A/620B. Source contact621may contact respective doped region66and form an electrical connection with semiconductor channels24through doped region66and substrate20. Source contact621can include one or more of tungsten, cobalt, copper, aluminum, silicides, and/or doped polysilicon, and can be deposited by one or more of CVD, PVD, and/or ALD. A suitable CMP and/or recess etch can be performed to remove the excess materials of insulating structure620A/620B and source contact621. In some embodiments, the “gate last” method is also employed to form a memory device that has a semiconductor channel with no lateral portions, e.g., extending along the vertical direction consistently. For example, to form the memory device, a semiconductor channel similar to or the same as semiconductor channel54(e.g., illustrated inFIG.5C) can be formed in a stack structure. The stack structure, different from stack structure51, can be have a plurality of alternatingly arranged first layers of a dielectric material layer and second layers of a sacrificial material layer, similar to or the same as the stack structure illustrated inFIGS.6A-6I. In some embodiments, the first layers include silicon nitride and the second layers include a different material than the first layers, such as polysilicon, carbon, and/or organic films. The second layers can be removed to form a plurality of lateral recesses, similar to the fabrication operation illustrated inFIG.6A. The first layer may then be oxidized using an oxidation reaction similar to the oxidation process illustrated inFIGS.6B and6Cto form a plurality of gate-to-gate dielectric layers. The stack structure may further be processed, using the fabrication processes illustrated inFIGS.6D-6I, to form other parts, e.g., source contacts, insulating structures, and conductor layers. A detailed description of the material and fabrication process to form the memory device can be referred to the description ofFIGS.5A-5JandFIGS.6A-6I, and is thus not repeated herein. In various embodiments, based on the material of the first layers and/or second layers, the gate-to-gate dielectric layer may include different materials than the materials introduced in the present disclosure. By using the methods of the present disclosure, the first layers and/or the second layers can undergo a suitable reaction (e.g., oxidizing and/or nitriding reaction) to form at least a sub-layer of a high-k dielectric material in the respective gate-to-gate dielectric layer. For example, x81may include hafnium oxide (HfOx) and x82may include hafnium oxynitride (HfOxNy, e.g., HfON). In some embodiments, gate-to-gate dielectric layer17of memory devices102and104may be formed by depositing hafnium oxide to fill up the lateral recesses which are formed by the removal of first layers211, and performing an oxidizing and/or nitriding process on the hafnium oxide between conductor layers18to form at least a sub-layer of hafnium oxynitride in gate-to-gate dielectric layer17. In some embodiments, in a “gate first” method, second layers212includes hafnium and gate-to-gate dielectric layer17of memory devices101,103,105, and106(e.g., each formed by a “gate first” method) includes at least a sub-layer of hafnium oxynitride. In some embodiments, in a “gate last” method, first layers211includes hafnium and gate-to-gate dielectric layer17of memory devices104and106(e.g., each formed by a “gate last” method) includes at least a sub-layer of hafnium oxynitride. The specific materials of the gate-to-gate dielectric layer should not be limited by the embodiments of the present disclosure. In some embodiments, a method for forming a 3D memory device includes the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions. The plurality of second memory portions are then removed to retain the plurality of first memory portions, the plurality of first memory portions being disconnected from one another. Also, a plurality of conductor layers are formed from the plurality of second layers. Further, a gate-to-gate dielectric layer is formed between the adjacent conductor layers, the gate-to-gate dielectric layer having at least one sub-layer of silicon oxynitride and an airgap. In some embodiments, removing the plurality of second memory portions includes the following operations. First, a first initial slit opening is formed extending through the stack structure and exposing the substrate. The plurality of first layers are removed through the first initial slit to form a plurality of lateral recesses that expose portions of the semiconductor channel. An etching process is performed on the exposed portions of the semiconductor channel through the plurality of lateral recesses and the first initial slit opening to remove the plurality of second memory portions. In some embodiments, filling the channel hole with a channel-forming structure includes forming a blocking layer over a sidewall of the channel hole, forming the memory layer over the blocking layer, forming a tunneling layer over the memory layer, forming a semiconductor layer over the tunneling layer, and forming a dielectric core over the semiconductor layer to fill up the channel hole. In some embodiments, removing the plurality of second memory portions includes removing a portion of the blocking layer over each one of the plurality of the second memory portions and removing the plurality of second memory portions to expose a portion of the tunneling layer under each one of the plurality of second memory portions. In some embodiments, forming the plurality of conductor layers, the gate-to-gate dielectric layer, and a second initial slit opening include forming a composite layer from a portion of each of the plurality of second layers, a remaining portion of the respective second layer forming a respective conductor layer, a pair of composite layers on the adjacent conductor layers and facing each other forming the gate-to-gate dielectric layer, and the first initial slit opening forming a second initial slit opening. The composite layer may have at least one sub-layer of silicon oxynitride. In some embodiments, the plurality of second layers include polysilicon and forming the composite layer includes performing, through the first initial slit opening and the plurality of lateral recesses, one or more of an oxidation reaction and a nitriding reaction on the plurality of second layers. A reacted portion of each of the plurality of second layers may form the respective composite layer and an unreacted portion of each of the plurality of second layers may form the respective conductor layer. In some embodiments, a composite layer is formed from each of a top portion and a bottom portion of the respective second layer. In some embodiments, forming the gate-to-gate dielectric layer further includes forming the airgap between the pair of composite layers. In some embodiments, forming the composite layer includes controlling the oxygen diffusion concentration such that the composite layer includes the at least one sub-layer of silicon oxynitride. In some embodiments, forming the composite layer further includes controlling the oxygen diffusion concentration such that the composite layer includes at least one sub-layer of silicon oxynitride and at least one sub-layer of silicon oxide. In some embodiments, forming the composite layer further includes controlling the oxygen diffusion concentration such that the composite layer includes a plurality of alternatingly arranged sub-layers of silicon oxynitride and sub-layers of silicon oxide. In some embodiments, forming the offset includes removing a portion of the side surface of each one of the plurality of first layers on the sidewall of the initial channel hole. In some embodiments, removing the portion of the side surface of each one of the plurality of first layers includes performing a recess etching process that selectively etches the plurality of first layers over the plurality of second layers. In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternatingly depositing a plurality of first material layers and a plurality of second material layers over the substrate to form an initial stack structure over the substrate. The plurality of first material layers may have a different etching selectivity than the plurality of second material layers. In some embodiments, the plurality of first layers and the plurality of second layers are formed by further repetitively etching the plurality of first material layers and the plurality of second material layers to form the stack structure having the plurality of first layers and the plurality of second layers arranged in a staircase structure. In some embodiments, depositing the plurality of first material layers includes depositing at least one of a silicon nitride material layer, a silicon oxide material layer, or a silicon oxynitride material layer. In some embodiments, the method further includes the following operations. First, a doped region is formed in the substrate at a bottom of the second initial slit opening. A slit opening is formed from the second initial slit opening by removing portions of the composite layer to expose the plurality of conductor layers on a sidewall of the slit opening and to expose the substrate at a bottom of the slit opening. An insulating structure is formed in the slit opening, the insulating structure being over the exposed portions of the plurality of conductor layers and exposing the substrate at the bottom of the slit opening. A source contact is formed in the insulating structure and in contact with the doped region. In some embodiments, forming an insulating structure in the slit opening includes depositing a layer of silicon oxide layer covering the exposed portions of the plurality of conductor layers and the gate-to-gate dielectric layer between adjacent conductor layers, and forming the source contact includes depositing at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, or silicides in the insulating structure. In some embodiments, a method for forming a 3D memory device includes the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions. Also, the plurality of second memory portions are removed to retain the plurality of first memory portions. The plurality of first memory portions may be disconnected from one another. A plurality of conductor layers may each be formed from a middle portion of a respective second layer. A composite layer may be formed from a surface portion of the second layer, the composite layer including at least one sub-layer of silicon oxynitride. An airgap may be formed between adjacent conductor layers. In some embodiments, removing the plurality of second memory portions includes forming a first initial slit opening extending through the stack structure and exposing the substrate, removing the plurality of first layers through the first initial slit to form a plurality of lateral recesses that expose portions of the semiconductor channel, and performing an etching process on the exposed portions of the semiconductor channel through the plurality of lateral recesses and the first initial slit opening to remove the plurality of second memory portions. In some embodiments, filling the channel hole with a channel-forming structure includes forming a blocking layer over a sidewall of the channel hole, forming the memory layer over the blocking layer, forming a tunneling layer over the memory layer, forming a semiconductor layer over the tunneling layer, and forming a dielectric core over the semiconductor layer to fill up the channel hole. In some embodiments, removing the plurality of second memory portions includes removing a portion of the blocking layer over each one of the plurality of the second memory portions and removing the plurality of second memory portions to expose a portion of the tunneling layer under each one of the plurality of second memory portions. In some embodiments, forming the plurality of conductor layers, the composite layer, and a second initial slit opening include forming the composite layer from each of a top portion and a bottom portion of each of the plurality of second layers, the middle portion between the top portion and the bottom portion forming a respective conductor layer, the first initial slit opening forming a second initial slit opening. In some embodiments, the plurality of second layers include polysilicon and forming the composite layer includes performing, through the first initial slit opening and the plurality of lateral recesses, one or more of an oxidation reaction and a nitriding reaction on the plurality of second layers. Reacted top and bottom portions of each of the plurality of second layers may form the respective composite layers and an unreacted portion between the reacted top and bottom portions of each of the plurality of second layers may form the respective conductor layer. In some embodiments, the method further includes forming the airgap between composite layers on adjacent conductor layers and facing each other. In some embodiments, forming the composite layer includes controlling the oxygen diffusion concentration such that the composite layer includes the at least one sub-layer of silicon oxynitride. In some embodiments, forming the composite layer further includes controlling the oxygen diffusion concentration such that the composite layer includes at least one sub-layer of silicon oxynitride and at least one sub-layer of silicon oxide. In some embodiments, forming the composite layer further includes controlling the oxygen diffusion concentration such that the composite layer includes a plurality of alternatingly arranged sub-layers of silicon oxynitride and sub-layers of silicon oxide. In some embodiments, forming the offset includes removing a portion of the side surface of each one of the plurality of first layers on the sidewall of the initial channel hole. In some embodiments, removing the portion of the side surface of each one of the plurality of first layers includes performing a recess etching process that selectively etches the plurality of first layers over the plurality of second layers. In some embodiments, the plurality of first layers and the plurality of second layers are formed by alternatingly depositing a plurality of first material layers and a plurality of second material layers over the substrate to form an initial stack structure over the substrate. The plurality of first material layers may have a different etching selectivity than the plurality of second material layers. In some embodiments, the plurality of first layers and the plurality of second layers are formed by repetitively etching the plurality of first material layers and the plurality of second material layers to form the stack structure having the plurality of first layers and the plurality of second layers arranged in a staircase structure. In some embodiments, depositing the plurality of first material layers includes depositing at least one of a silicon nitride material layer, a silicon oxide material layer, or a silicon oxynitride material layer. In some embodiments, the method further includes forming a doped region in the substrate at a bottom of the second initial slit opening, forming a slit opening from the second initial slit opening by removing portions of the composite layer to expose the plurality of conductor layers on a sidewall of the slit opening and to expose the substrate at a bottom of the slit opening, forming an insulating structure in the slit opening. The insulating structure may be over the exposed portions of the plurality of conductor layers and exposing the substrate at the bottom of the slit opening. The method may also include forming a source contact in the insulating structure and in contact with the doped region. In some embodiments, forming an insulating structure in the slit opening includes depositing a layer of silicon oxide layer covering the exposed portions of the plurality of conductor layers and the gate-to-gate dielectric layer between adjacent conductor layers, and forming the source contact includes depositing at least one of tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, or silicides in the insulating structure. In some embodiments, a 3D memory device includes a stack structure having a plurality of conductor layers insulated from one another by a gate-to-gate dielectric structure. The gate-to-gate dielectric structure may include at least a sub-layer of silicon oxynitride and an airgap between adjacent conductor layers along a vertical direction perpendicular to a top surface of the substrate. In some embodiments, the 3D memory device also includes a semiconductor channel extending from a top surface of the stack structure to the substrate. The semiconductor channel may include a memory layer having a plurality of memory portions each surrounding a bottom of a respective conductor layer and each being disconnected from one another. In some embodiments, the 3D memory device also includes a source structure extending from the top surface of the stack structure to the substrate. In some embodiments, the gate-to-gate dielectric structure includes a gate-to-gate dielectric layer between adjacent conductor layers. The gate-to-gate dielectric layer may include a pair of composite layers on the adjacent conductor layers and the pair of composite layers each having at least a sub-layer of silicon oxynitride. In some embodiments, the pair of composite layers each includes at least a sub-layer of silicon oxide and a sub-layer of silicon oxynitride. In some embodiments, the pair of composite layers each includes a plurality of alternatingly arranged sub-layers of silicon oxide and sub-layers of silicon oxynitride. In some embodiments, the gate-to-gate dielectric layer includes the airgap between the pair of composite layers. In some embodiments, the plurality of memory portions each includes a vertical portion along the vertical direction and at least one lateral portion along a lateral direction parallel to the top surface of the substrate. The vertical portion and the at least one lateral portion partially surrounding the respective conductor layer vertically and laterally. In some embodiments, along a radial direction from a sidewall of the semiconductor channel to a center of the semiconductor channel, the semiconductor channel includes a blocking layer, the plurality of memory portions over the blocking layer, a tunneling layer over the plurality of memory portions, a semiconductor layer over the tunneling layer, and a dielectric core over the semiconductor layer. In some embodiments, each composite layer is located between ends of the respective vertical portion of each of the plurality of memory portions along the vertical direction. In some embodiments, the blocking layer includes at least one of a first blocking layer and a second blocking layer, the first blocking layer including one or more of aluminum oxide (AlO), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, or alloys thereof, the second blocking layer including one or more of silicon oxide, silicon oxynitride, and silicon nitride. In some embodiments the memory layer includes a charge-trapping material that includes at least one of tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, alloys thereof, nanoparticles thereof, silicides thereof, polysilicon, amorphous silicon, SiN, or SiON. In some embodiments, the tunneling layer includes at least one of SiO, SiN, SiON, dielectric metal oxides, dielectric metal oxynitride, dielectric metal silicates, or alloys thereof. In some embodiments, the semiconductor layer includes at least one of a one-element semiconductor material, a III-V compound semiconductor material, a II-VI compound semiconductor material, or an organic semiconductor material. In some embodiments, the dielectric core includes SiO. In some embodiments, the plurality of conductor layers each including a layer of one or more of W, Co, Al, doped silicon, silicides, and a combination thereof, and the source structure each includes an insulating structure and a source contact in the insulating structure and conductively in contact with the substrate. The insulating structure may include silicon oxide, and the source contact including one or more of W, Co, Al, doped silicon, silicides, and a combination thereof. The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. | 99,309 |
11943924 | DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments of the invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense. The term “horizontal” as used in this document is defined as a plane parallel to the conventional plane or surface of a substrate, such as that underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. The terms “wafer” and “substrate” are used herein to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. A wafer may include a number of die in which an integrated circuit is disposed with respect to a respective substrate of the die. FIG.1is a cross-sectional representation of an embodiment of an example charge trap (CT) structure101, which can be included in a variety of electronic apparatus. Such apparatus can include a memory array, a memory device, an integrated circuit, or other apparatus that includes one or more cells to store charge. The CT structure101can include a semiconductor pillar103, a charge trap region105, a tunnel region107, a dielectric blocking region109, a dielectric barrier110, and a gate115. Gate115is adjacent to dielectric blocking region109to control storage of charge in the charge trap region105. At least a portion of gate115is separated from at least a portion of an adjacent gate by at least a void120. A void in a structure is a region of the structure without solid material and without liquid material. A void may be in the form of an evacuated region, an air gap, a gas-filled region, or similar construction. An air gap in a structure or between structures is a gap or region that is filled with air. Herein, the term air gap may include ambient gases enclosed in the gap, such as during formation of the gap. A void may be structured between at least a portion of gate115and at least a portion of a region above which charge trap structure101is directly disposed. In various embodiments, the arrangement of CT structure101with conductive region113can have a different structural arrangement. CT structure101can be separated from conductive region113by an access transistor that can be a transistor structure different from a CT that can operatively act as a transmission gate to provide operational coupling of conductive region113to CT structure101, In such an alternative structure, semiconductor pillar103of CT101may be coupled to and integrated in the access transistor such that coupling of semiconductor pillar103with conductive region113is made by a channel of the access transistor. In addition, a void120could also be utilized to at least partially separate a gate115from the access transistor structure. In other embodiments, the region on which charge trap structure101is directly disposed can be another charge trap structure, in which a void120could be used to at least partially separate a gate115of charge trap structure101from a gate of the charge trap structure on which charge trap structure101is directly disposed. Charge trap structure101can be disposed above conductive region113that is located a substrate102. An isolation region or other integrated circuit structures can separate components of the charge trap structure101from conductive region113. Alternatively, the CT structure101can be disposed on conductive region113, without a separation or coupling region, with gate115separated from conductive region113by a void120and a sealing dielectric122. As noted above, CT structure101can be disposed above conductive region113with gate115separated from an access transistor, which couples CT structure101to conductive region113, by a void120and a sealing dielectric122. Sealing dielectric122is a region for CT structure101used to seal off a void120during processing of different areas of the electronic apparatus in which CT structure101is integrated, where portions of sealing dielectric122remain in the completed structure, continuing to seal the void120. Void120can be contained within a region bounded by at least a portion of dielectric barrier110, at least a portion of conductive region113and/or at least a portion of a region on which CT structure101is directly disposed, at least a portion of gate115, and at least a portion of sealing dielectric122, where sealing dielectric122is disposed on portions of gate115. Alternatively, sealing dielectric122can be disposed along the entire surface of gate115, which may reduce the size of void120. The figures herein are not drawn to scale. Further, electrical connections of gate115, semiconductor pillar103, and conductive region113to other components of an apparatus, in which CT structure101is integrated, are not shown to focus on the CT structure101. Semiconductor pillar103is operable to conduct a current and gate115is operable to control storage of charge in the charge storage region. Gate115can be a metal gate. Gate115can include combinations of metal and metallic compound. Gate115is conductive and can include, but is not limited to, conductive titanium nitride and/or tungsten. For example, gate115include a conductive titanium nitride region115-1on which a tungsten region115-2is disposed. Gate115can be referred to as a control gate and dielectric blocking region109can be referred to as a control dielectric. Semiconductor pillar103can include, but is not limited to, polycrystalline silicon (poly silicon). The semiconductor material of semiconductor pillar103may have a majority carrier concentration that is less than the majority carrier concentration of conductive region113, with conductive region113structured as a semiconductor region. The difference in majority carrier concentration can be orders of magnitude in powers of base10. The regions of structure101shown inFIG.1can be arranged as rings of material around center region104. Center region104can be a dielectric. Center region104can be a region of dielectric material, such as, but not limited to, a dielectric oxide. An example of a dielectric oxide in center region104can include silicon oxide. Charge trap region105is separated from the semiconductor pillar103by a tunnel region107. Charge trap region105can be a dielectric material that can store charge from semiconductor pillar103. Charge trap region105can be a dielectric nitride region such as a region including dielectric silicon nitride. Other dielectric materials for charge trap region105can be used to trap charge. Tunnel region107can be constructed as an engineered region to meet a selected criterion, such as, for example but not limited to, an equivalent oxide thickness (EOT). The EOT quantifies the electrical properties of tunnel region107, such as capacitance, of a dielectric in terms of a representative physical thickness. For example, EOT can be defined as the thickness of a theoretical SiO2layer that would be required to have the same capacitance density as a given dielectric (tunneling region107), ignoring leakage current and reliability considerations. Tunnel region can include an oxide and a nitride. Tunnel region107may include a set of dielectric barriers. The example inFIG.1shows tunnel region107being a three region tunnel barrier. The three region tunnel barrier can be arranged as a region of dielectric oxide followed by a region of dielectric nitride followed by another region of dielectric oxide. Alternatively, tunnel region107can be a two region tunnel barrier or a one region tunnel barrier. Further, tunnel region107may have four or more regions, where the selection of material and thicknesses depends on the capability of the material with the given thicknesses to perform as a tunneling region to charge trap region105. Dielectric blocking region109is disposed on and contacting the charge trap region105. Dielectric blocking region109provides a mechanism to block charge from flowing from charge trap region105to gate115. Dielectric blocking region109can be an oxide or other dielectric such as used in tunnel region107. Gate115is disposed adjacent to dielectric blocking region109, but separate from dielectric blocking region109by dielectric barrier110that is between dielectric blocking region109and gate115, where the material of dielectric barrier110is different from the material of dielectric blocking region109. Dielectric barrier110, structured as a thin region, between dielectric blocking region109and gate115enables an enhanced tunneling barrier that prevents back-tunneling of electrons from gate115through dielectric blocking region109into charge trap region105, which can thereby limit operational erase saturation to small positive or small negative threshold voltage (Vt) levels. Dielectric barrier110can have a thickness in the range from about 15 angstroms to about 50 angstroms between dielectric blocking region109and gate115. Selection of material for dielectric barrier110can be based on the fabrication of CT structure101. For example, in a process in which CT structure101including void120is formed by removing of material from areas to the sides of CT structure101, the material for dielectric barrier110can be selected such that the material for dielectric barrier110resists removal at the processing chemistries and temperatures used in removal of these materials from the sides of CT structure101. The material for dielectric barrier110can act as a mask to prevent removal of dielectric blocking region109in such removal processes. Dielectric barrier110can be realized as an AlOxregion or a dielectric region having a higher dielectric constant, κ, than AlOx. (Use of nomenclature ABxindicates an AB material that is not limited to a particular stoichiometry for the AB compound.) The dielectric barrier110can have an electron affinity lower than that aluminum oxide. Dielectric barrier110can include one or more of aluminum oxide, hafnium oxide, zirconium oxide, or mixtures of hafnium oxide and/or zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. Examples of films that can be used include HfO2and/or ZrO2based materials, as well as mixtures with other materials such as AlOx, TiO2, GaOx, NbOx, and Ta2O5. Such materials may not be limited to a particular stoichiometry. In various embodiments, a memory device can be structured as a memory structure in which memory cells to store charge are arranged in different levels in a 3D structure. For example, the memory device can include a 3D NAND stack in which memory cells similar to CT structure101can be arranged. A NAND array architecture can be arranged as an array of memories (e.g., memory cells) arranged such that the memories of the array are coupled in logical rows to access lines. The access lines may be word lines. Memories of the array can be coupled together in series between common regions, such as source lines, and data lines. The data lines may be bit lines. The 3D NAND stack can be implemented with a dielectric barrier, such as dielectric barrier110, using materials for the dielectric barrier selected to enable processing of voids between CT structures arranged in the 3D NAND stack. Within CT cells in the 3D NAND stack, the gate of each such CT cell, which may be coupled to an access line, for example a word line, or formed as part of the access line, can be formed in a process in which an initially formed region, having material such as silicon nitride, is removed and replaced by a conductive gate in a number of CT cells in a vertical string in the stack. Such gates may be referred to as replacement gates. FIG.2is a schematic diagram of an embodiment of an example of a block architecture and page address mapping of a memory array212of a 3D memory device200. Memory device200can be realized in the form of a 3D NAND memory device200. Memory device200can comprise multiple vertical strings211of charge storage devices201. In the Z direction shown inFIG.2, each string211of charge storage devices can comprise multiple storage devices201stacked over one another with each charge storage device201corresponding to one of multiple tiers. For example, as shown inFIG.2. thirty-two charge storage devices are stacked over one another in a string with each charge storage device201corresponding to one of thirty-two tiers shown as Tier0-Tier31. The number of storage devices and tiers in the Z direction are not limited to thirty-two. The charge storage devices201of a respective string211may share a common channel region, such as one formed in a respective pillar of semiconductor material (e.g., polysilicon) about Which the string of charge storage devices are formed. The pillars may be polysilicon, monocrystalline silicon, or other semiconductor structure in which transistors can be fabricated. In the X direction shown inFIG.2, sixteen groups of strings may comprise eight strings that share thirty two access lines, CGs. Each of the access lines CGs may couple (e.g., electrically or otherwise operatively connect) the charge storage devices201corresponding to a respective tier of each string211of a corresponding one of the eight strings. The charge storage devices201coupled by the same access line, CG, (and thus corresponding to the same tier) may be logically grouped into, for example, two pages, such as P0/P32, P1/P33, P2/P34 and so on, when each charge storage device comprise a multi-level cell capable of storing multiple bits of information. Memory device200can be arranged to operate each charge storage device as a quad level cell. The page address mapping counts up horizontally in the same tier. In the Y direction shown inFIG.2, eight groups of strings can comprise sixteen strings coupled to a corresponding one of eight data lines (BLs). The structure with respect to the SGSs in this example is one plate294, which connects16pillar strings together, and the structure with respect to the CGs is one plate293, which connects16pillar strings together. The SGD is separated by one pillar string. The number of the strings, tiers, access lines, data lines, groups of strings in each direction, and/or pages may be greater or smaller than those shown inFIG.2. The vertical strings211can include a vertical pillar of semiconductor material with a number of charge storage devices201arranged along each vertical string. Each charge storage device201can include a charge trap region separated from the vertical pillar of a respective vertical string by a tunnel region; a dielectric blocking region on the charge trap region; a gate adjacent to the dielectric blocking region to control storage of charge in the charge storage region, the gate coupled to an access line; and a dielectric barrier between the dielectric blocking region and the gate, where there is a void between at least portions of the gate and at least portions of a gate of an adjacent charge storage device201. The gate of each charge storage device201can be coupled to (e.g., integrated with) an access line CG corresponding to the location in memory array212of the respective charge storage device201. Charge storage device201may be realized in a manner similar to the CT structure ofFIG.1. The components of charge storage device201can be implemented by selecting properties from a number of different parameters. The dielectric barrier of charge storage device201can include one or more of aluminum oxide, hafnium oxide, zirconium oxide, and mixtures of hafnium oxide and/or zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. The dielectric barrier can have a thickness in a range from about 15 angstroms to about 50 angstroms from the dielectric blocking region to the gate of charge storage device201. The tunnel region of charge storage device201can be implemented as a three region tunnel barrier. Such a three region tunnel barrier can be implemented as a region of dielectric oxide followed by a region of dielectric nitride followed by another region of dielectric oxide. The tunnel region of charge storage device201can be implemented as a multiple region barrier other than three regions. Such a multiple region barrier can be implemented such that the selection of material and thicknesses of the regions depends on the capability of the material with the given thicknesses to perform a tunneling region to the charge trap region of charge storage device201. The gate of charge storage device201can be implemented as a metal gate or a gate including a combination of metal and metallic compounds. The channel of charge storage device201in a string211can be implemented as a poly silicon channel. FIG.3is a cross-sectional representation of an embodiment of a number of CT structures, for example CT structures301-1,301-2, and301-3, in a vertical string311of a memory device300. Vertical string311can be one of multiple strings of a memory array, of a 3D memory. An example of a 3D memory device with multiple vertical strings is shown inFIG.2. Other 3D memory devices with multiple vertical strings can be structured with CT memory cells, similar to the CT structures of301. Other vertical strings in a 3D memory device can be structured similar to vertical string311, arranged with different sets of electrical connections. Vertical string311includes a vertical pillar303of semiconductor material coupled to and part of CT structures301-1,301-2, and301-3. Memory device300is not limited to three CT structures in a vertical string.FIG.3shows three CT structures to focus on the architecture of CT structures arranged in a vertical stack306along or as part of vertical string311. Vertical string311can be include more than three CT structures, for example, 8, 16, 32, 64, or other number of CT structures coupled to vertical pillar303of vertical string311depending on the memory size of memory device300or other factors for an architecture for memory device300. Each CT structure can be arranged as a memory cell of a string, where each CT structure is at a different vertical level than the other CT structures of the string, which each vertical level is a tier of the memory array of the memory device. Stack306can be supported by a base316. InFIG.3, a space is shown between the bottom of stack306and base316to indicate that there may be additional materials and/or integrated circuit structures between base316and stack306. In various applications, such additional integrated materials may include, for example, source-side select transistor material. Base316may include a conductive region313on a substrate302. Depending on the architecture of memory300, conductive region313may be a source region. Conductive region313may include semiconductor material. The semiconductor material may include, but is not limited to, monocrystalline silicon or polycrystalline silicon. Substrate302may be a semiconductor substrate or a substrate having a combination of semiconductor material and insulating material. CT structure3014is arranged as a first charge trap structure along vertical string311, above which charge trap structures301-2and301-3are arranged in vertical stack306with each of charge trap structures301-2and301-3disposed above another CT structure of vertical stack306. The semiconductor material of vertical pillar103is arranged as a channel303-1,303-2, and303-3for CT structures301-1,301-2, and301-3, respectively. Each of CT structures301-1,301-2, and301-3includes a tunnel region307-1,307-2, and307-3, respectively, adjacent and contacting their respective channels303-1,303-2, and303-3. Each of tunnel regions307-1,307-2, and307-3can be implemented as a set of barriers. For example, each of tunnel regions307-1,307-2and307-3can be implemented as a three region tunnel barrier. Such a three region tunnel barrier can be implemented as a region of dielectric oxide followed by a region of dielectric nitride followed by another region of dielectric oxide. Each of tunnel regions307-1,307-2, and307-3may be implemented as a two region tunnel barrier, Each of tunnel regions307-1,307-2, and307-3may be implemented as a one region tunnel barrier. Further, each of tunnel regions307-1,307-2, and307-3may have four or more regions, where the selection of material and thicknesses of these tunnel regions depends on the capability of the material with the given thicknesses to perform as a tunneling region. Each of CT structures301-1,301-2, and301-3includes a charge trap region305-1,305-2, and305-3, respectively, adjacent and contacting their respective tunnel regions307-1,307-2, and307-3. Each of charge trap regions315-1,315-2, and315-3can be a dielectric material that can store charge from channels303-1,303-2, and303-3, respectively. Charge trap regions315-1,315-2, and315-3can be a dielectric nitride region such as a region including dielectric silicon nitride. Other dielectric materials for charge trap regions315-1,315-2, and315-3can be used to trap charge. Each of CT structures301-1,301-2, and301-3includes a dielectric blocking region309-1,309-2, and309-3, respectively, adjacent and contacting their respective charge trap region305-1,305-2, and305-3. Each of CT structures301-1,301-2, and301-3can include a dielectric barrier310-1,310-2, and310-3and a gate315-1,315-2, and315-3, respectively, where each dielectric barrier310-1,310-2, and310-3is disposed between dielectric blocking region309-1,309-2, and309-3and gates315-1,315-2, and315-3of their respective CT structures301-1,301-2, and301-3. Each of dielectric barriers310-1,310-2, and310-3can be implemented using materials for the dielectric barriers selected to enable processing of voids between CT structures301-1,301-2, and301-3arranged in the 3D stack306associated with string311. 3D stack306can be realized as a 3D NAND stack306. Each of dielectric barriers310-1,310-2, and310-3can include an aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. Each dielectric barrier310-1,310-2, and310-3can extend to the dielectric barrier of an adjacent CT structure and can be arranged with gate315-1,315-2, and315-3of its respective CT structure301-1,301-2, and301-3and the gate of the adjacent charge trap structure, providing a void between the charge trap structure and the adjacent charge trap structure. Dielectric barrier310-3of CT structure301-3can extend to dielectric barrier310-2of CT structure301-2and is arranged with gate315-3of CT structure301-3and gate315-2of adjacent CT structure301-2such that void320-3is provided. Dielectric barrier310-2of CT structure301-2can extend to dielectric barrier310-1of CT structure301-1and is arranged with gate315-2of CT structure301-2and gate315-1of adjacent CT structure301-1such that void320-2is provided. Each CT structure301-1,301-2, and301-3is arranged with an adjacent CT structure, vertically up or vertically down in stack306associated with vertical string311. In addition, dielectric barrier310-1of CT structure301-1can extend to a region on which stack306is directly disposed. The region on which stack306is directly disposed may be an isolation region or another active device area such as an access transistor that couples stack306to conductive region313on substrate302. Dielectric barrier310-1of CT structure301-1can be arranged with gate315-1of CT structure301-1and the region on which stack306is directly disposed such that void320-1is provided. Alternatively, string311can be structured with electrical isolation between gate315-1and conductive region313being provided at least in part by void320-1. Each of voids320-1,320-2, and320-3can be sealed by a dielectric region322-1,322-2, and322-3, respectively. Dielectric region322-1can be located on the region on which stack306is disposed (alternatively conductive region313) and can extend to and be located on at least a portion of gate315-1of CT301-1. Void320-1can be contained within at least a portion of dielectric barrier310-1extended to at least a portion of the region on which stack306is directly disposed (alternatively conductive region313), at least a portion of gate315-1, at least a portion of dielectric region322-1on at least a portion of gate315-1, at least a portion of the region on which stack306is directly disposed (alternatively conductive region313), and at least a portion of dielectric region322-1on at least a portion of the region on which stack306is directly disposed (alternatively conductive region313). Dielectric region322-2can be located on gate315-2of CT structure301-2and can extend to and be located on gate315-1of CT301-1. Void320-2can be contained within at least a portion of dielectric barrier310-2extended to dielectric barrier310-1, at least a portion of gate315-2, at least a portion of dielectric region322-2on gate315-2of CT structure301-2, at least a portion of gate315-1of adjacent CT structure301-1, and at least a portion of dielectric region322-2on at least a portion of gate315-1of CT structure301-1. Dielectric region322-3can be located on gate315-3of CT301-3and can extend to and be located on gate315-2of CT structure301-2. Void320-3can be contained within at least a portion of dielectric barrier310-3extended to dielectric barrier310-2, at least a portion of gate315-3, at least a portion of dielectric region322-3on at least a portion of gate315-3of CT structure301-3, at least a portion of gate315-2of adjacent CT structure301-2, and at least a portion of dielectric region322-3on at least a portion of gate315-2of CT structure301-2. In some variations, dielectric regions322-1,322-2, and322-3may extend along the surfaces of the gates between which they are respectively located to the dielectric barrier extending between adjacent CT structures that are separated by the respective dielectric regions322-1,322-2, and322-3. In such variations, each associated void is contained within a dielectric barrier, a dielectric region on the gate of a charge trap structure, and a dielectric region on the gate of an adjacent charge trap structure. Such voids may be smaller than those in which the sealing dielectrics do not extend to their associated dielectric barriers. The voids between gates of adjacent CT structures can be largest in vertical extent at the dielectric barriers between the adjacent CT structures. Tunnel region307-1of first CT structure301-1can extend along vertical pillar303of semiconductor material associated with string311and can extend through the other CT structures301-2and301-3as tunnel regions307-2and307-3of each respective CT structure301-2and301-3. Charge trap region305-1of first CT structure301-1can extend along vertical pillar303of semiconductor material associated with string311and can extend through the other CT structures301-2and301-3as charge trap regions305-2and305-3of each respective CT structure301-2and301-3. Dielectric blocking region309-1of first CT structure301-1can extend along vertical pillar303of semiconductor material associated with string311and can extend through the other CT structures301-2and301-3as dielectric blocking region309-2and309-3of each respective CT structure301-2and301-3. Vertical pillar103of string311of memory device300can be structured as a doped semiconductor hollow channel. By hollow channel is meant that the region in the center of the 3-D channel can be filled by a material different than the material of the channel. Vertical pillar103can include poly silicon as a hollow channel surrounding a dielectric304. Vertical pillar103can operatively conduct a current between conductive region313and a conductive data line coupled to vertical pillar103. Such conductive data line may be coupled to vertical pillar103by an access transistor. In various 3D memory architectures, such arrangement of conductive region313and a conductive data line coupled to vertical pillar103can be provided with conductive region313being a source region and conductive data line being a data line. The current can be affected by the charge stored in CT structures301-1,301-2, and301-3along string311, where control of storing the charge is by the gates315-1,315-2, and315-3of CT structures301-1,301-2, and301-3. Gates315-1,315-2, and315-3can be incorporated in access lines of a memory array of memory device300. The access lines may be word lines. Voids320-1,320-2, and320-3between CT structure301-1and the region on which stack306is disposed (alternatively conductive region313), between CT structures301-2and301-1, and between CT structures301-3and301-2provide voids between access lines of a memory array of memory device300. These voids between access lines can decrease access line (gate) to access line (gate) capacitance relative to using conventional dielectric materials between access lines of a 3D memory device. Using voids, such as voids320-1,320-2, and320-3, for an acceptable capacitance, can allow the distance between access lines (gates) to CT cells to be smaller, allowing more room for the access lines (gates) to CT cells, that is, access lines (gates) can be vertically wider, which can lower the access line resistance. FIG.4is a flow diagram of features of an embodiment of an example method400of forming a charge trap structure above a conduction region. At410, a dielectric barrier is formed on a wall of an opening in a material stack. Forming the dielectric banter can include forming aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. Other dielectrics may be used. Forming the dielectric barrier can include forming the dielectric barrier with material that can withstand temperatures and etching chemistries in processing the charge trap structure to mask the dielectric blocking region from being etched during these processes. At420, a dielectric blocking region is formed on and contacting the dielectric barrier. The material of the dielectric blocking region is different from the material of the dielectric barrier. At430, a charge trap region is formed on and contacting the dielectric blocking region. Forming the charge trap region can include forming a dielectric nitride as the charge trap region. Other charge trapping material may be used. At440, a tunnel region is formed on and contacting the charge trap region. The tunnel region may be formed as a set of regions that can provide for transfer of transfer to the charge trap region. At450, a semiconductor pillar is formed on and contacting the tunnel region, the channel operable to conduct a current. The semiconductor pillar is separated from the charge trap region by the tunnel region. At460, a gate is formed on and contacting the dielectric barrier, the gate separated from the dielectric blocking region by the dielectric barrier. The gate is operable to control storage of charge in the charge trap region. Forming the gate can include forming tungsten as the gate. Forming the gate can include forming a titanium nitride region on and contacting the dielectric barrier and forming the tungsten on the titanium nitride region. At470, forming the gate can include the gate formed separated by a void from at least a portion of a region on which the charge trap structure is being directly disposed. Forming the gate can include forming a portion of the gate separated from at least a portion of an adjacent gate by at least a void. The dielectric barrier may be arranged with the gate such that the void is between the at least a portion of the gate and the at least a portion of the region on which the charge trap structure is being directly disposed. Methods similar or identical to method400can include forming the opening in the material stack with the material stack having alternating sacrificial regions and isolation dielectrics. The sacrificial regions adjacent to the dielectric barrier can be removed using a chemistry and process to remove the sacrificial region substantially without removing material for the dielectric barrier. The gate can be formed in a region in which a sacrificial region has been removed and the adjacent gate can be formed in a region in which another one of the sacrificial regions has been removed. Material from between the gate and the adjacent gate can be removed to form an open area by a chemistry and process to remove the isolation dielectrics previously formed between adjacent sacrificial regions without substantially removing the material for the dielectric barriers, without substantially removing material of the gate, and without substantially removing material of the adjacent gate. A dielectric can be formed in at least a portion of the open area to form the void. For a single charge trap structure above a location along a substrate, the region on which the charge trap structure is being directly disposed may be the conductive region. For multiple charge trap structures being formed in a stack above a location along a substrate, the region on which a charge trap structure is being directly disposed may include a gate of an adjacent charge trap structure, the gate being conductive material. The dielectric barrier can be extended to at least a portion of the region on which the charge trap structure is being directly disposed to form the void between at least a portion of the gate and the at least a portion of the region on which the charge trap structure is being directly disposed, with the dielectric barrier separating the void from the dielectric blocking region. A dielectric can be formed to seal the void. FIG.5is a flow diagram of features of an embodiment of an example method500of forming multiple charge trap structures with each charge trap structure separated from an adjacent charge trap structure by a void. At510, a stack of material is formed with an opening surrounded by material to form tunnel regions, charge trap regions, dielectric blocking regions, and dielectric barriers of multiple charge trap structures. The multiple charge trap structures, including a first charge trap structure, is formed with each trap structure, after the first charge trap structure, disposed above another one of the multiple charge trap structures. The material for the dielectric barriers can include aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. At520, multiple gates are formed contacting material for the dielectric barriers and material from the stack is removed such that each gate is separated from a vertically adjacent gate of the multiple gates by an open area, exposing portions of the material for the dielectric barriers. Forming multiple gates contacting material for the dielectric barriers and removing material such that each gate is separated from a vertically adjacent gate of the multiple gates can include, with the stack of material including alternating sacrificial regions and isolation dielectrics adjacent to the material to form tunnel regions, charge trap regions, dielectric blocking regions, and dielectric barriers: removing sacrificial regions adjacent to the material for the dielectric barriers using a chemistry and process to remove the sacrificial region substantially without removing material for the dielectric harrier; forming gate material in each region in which a sacrificial region is removed; and removing material from between each gate by a chemistry and process to remove the isolation dielectrics previously formed between adjacent sacrificial regions without substantially removing the material for the dielectric barriers and without substantially removing the gate material in each region. Forming the gate material in each region in which the sacrificial region is removed can include forming the gate material coupled to access lines in a memory array for a memory device. At530, the stack of material is processed further such that a portion of each open area is a void between gates of adjacent charge trap structures. Method500or methods similar to method500can include sealing, with a dielectric, the open area between gates of adjacent charge trap structures in forming the void. In various embodiments, methods including forming CT structure with associated voids can be performed using variations of methods similar to method400and/or method500. Note that these features may be performed in a number of different sequencing steps and are not limited to the order or features as presented inFIGS.4and5. FIGS.6A-6Nare cross-sectional views illustrating features of stages of an embodiment of forming multiple CT structures in an electronic device.FIG.6Ashows a material stack621above a conductive region613on substrate602. Material stack612includes alternating isolation dielectrics618and sacrificial regions619above conductive region613. The number of alternating isolation dielectrics618and sacrificial regions619may depend on the number of CT structures being formed in a vertical stack. In a 3D memory device, this number can depend on the number of tiers in a memory array of the memory device, for example, a pair of isolation dielectric618and sacrificial region619for each tier. Three isolation dielectrics618and three sacrificial regions619, which can correspond to three tiers in a memory array of a memory device, are shown inFIG.6Afor ease of discussion. Isolation dielectrics618can include, but are not limited to, an oxide such as silicon oxide, and sacrificial regions619can include but are not limited to, a nitride such as silicon nitride. The choice of material for isolation dielectrics618and sacrificial regions619can depend on the temperatures and chemistries used in fabricating multiple CT structures. Conductive region613can be a semiconductor region613. Semiconductor region613may be formed including poly silicon. InFIGS.6A-6N, a space is shown between conductive region613on substrate602and the lowest isolation dielectric618vertically from conductive region613to indicate that there may be additional materials and/or integrated circuit structures between this isolation dielectric618and conductive region613. FIG.6Bshows material stack621after a removal process has been conducted to form trenches614in which pillars for CT structures are being formed. The removal process can include masking areas and etching material stack621in the locations for the trenches614. Trenches614may be referred to as open pillars614in material stack621. Each open pillar614may become a separate individual string of CT structures in a memory array of a memory device. Each open pillar614may be cylindrical-like in shape or have some other similar shape that extends vertically though material stack621(z-direction), but extends a relatively short distance in material stack621in the y-direction. InFIG.6B, open pillars614are arranged along conductive region613in the x-direction, where multiple CT structures will be stacked on each other in the z-direction in each open pillar614. Though not shown for ease of discussion, open pillars614can be formed in the y-direction with multiple C′I′ structures stacked on each other in the z-direction in each open pillar614in the y-direction. See, for example,FIG.2. FIG.6Cshows one of the open pillars614associated withFIG.6B. The figures following6C show processing of this open pillar614, where such processing is being performed on the other similar open pillars associated with material stack621ofFIG.6B.FIG.6Dshows a material for a dielectric barrier610formed on a will of open pillar614ofFIG.6C. Forming the material for dielectric: barrier610can include depositing one or more of aluminum oxide, hafnium oxide, zirconium oxide, and mixtures of hafnium oxide and/or zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. The deposition can be performed using one or more of a number of deposition processes. For example, the deposition can be implemented using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other process suitable for forming a 3D memory device. These deposition techniques can be used in depositing material at various stages of forming the multiple CTs associated withFIGS.6A-6N. ALD allows formation of a region as a nanolaminate of a number of different compounds in each of sub-region of the region with the formed region having a total thickness in the nanometer region. The term “nanolaminate” means a composite film of ultra thin layers of two or more materials in a layered stack. Typically, each layer in a nanolaminate has a thickness of an order of magnitude in the nanometer range. Further, each individual material layer of the nanolaminate may have a thickness as low as a monolayer of the material or as high as 5 nanometers. The material for dielectric barrier610can be formed with a thickness from the wall of the open pillar614in the range of 20 to 50 angstroms. FIG.6Eshows a material for dielectric blocking region609formed on a surface of the material for dielectric barrier610opposite the wall of the open pillar614, The material for dielectric blocking region609can include silicon oxide or other dielectric material.FIG.6Fshows material for a charge trap region605formed on a surface of the material for dielectric blocking region609opposite the surface of the material for dielectric barrier610. The material for charge trap region605can include a dielectric nitride. For example, a dielectric nitride of charge trap region605can include silicon nitride. FIG.6Gshows material for a tunnel region607formed on the material for charge trap region605. The material for tunnel region607can be implemented as a three region tunnel barrier as shown inFIG.6E. Such a three region tunnel barrier can be implemented as a region of dielectric oxide followed by a region of dielectric nitride followed by another region of dielectric oxide. Alternatively, the material for tunnel region607may be implemented as a two region tunnel harrier. Also, the material for tunnel region607may be implemented as a one region tunnel barrier. Further, the material for tunnel region607may have four or more than regions, where the selection of material and thicknesses depends on the capability of the material with the given thicknesses to perform as a tunneling region to charge trap region605. The material for tunnel region607can include one or more dielectrics such as silicon oxide or dielectrics having a dielectric constant greater than that of silicon dioxide. FIG.6Hshows material for a semiconductor pillar603formed on the material for the material for tunnel region607. The material for a semiconductor pillar603may be formed as a doped hollow channel. The doped hollow channel can be coupled to conductive region613via material and/or integrated circuit structures coupled on and contacting conductive region613. For example, the material for semiconductor pillar603may be deposited to extend to and contact conductive region613. Conductive region613can be formed as a semiconductor region613having a majority carrier concentration at a concentration level higher than the majority carrier concentration of semiconductor pillar603. Semiconductor region613can be formed as a source region. From the processed structure inFIG.6H, procedures can be performed to generate gates and voids for CT structures of a completed device. On either side of the structure of open pillar614surrounded by materials for semiconductor pillar603, tunnel region607, dielectric blocking region609, and dielectric barrier610along with portions of isolation dielectrics618and sacrificial regions619shown inFIG.6H, vertical slits can be created through the set of isolation dielectrics618and sacrificial regions619to allow processing of isolation dielectrics618and sacrificial regions619adjacent the material for dielectric barrier610to form the appropriate gates and voids. SeeFIG.6Lfor an example of slits between the processed open pillars614. Such slits may have been created earlier in the process. FIG.6Ishows the structure ofFIG.6Hafter sacrificial regions619have been removed, where after removal air occupies the previous sacrificial regions619, The removal of sacrificial regions619can include etching the material of sacrificial regions619that is selective to the material for isolation regions618and the material for dielectric barrier610. By selective is meant that the etchant that removes the sacrificial regions619does not remove the material for isolation regions618and the material for dielectric barrier610, With the material for sacrificial regions619being a nitride such as silicon nitride, the material for isolation regions618being an oxide such as silicon oxide, and the material for dielectric barrier being a metal oxide such as AlOx, the nitride of sacrificial regions619may be removed using a hot phosphoric acid etchant. FIG.6Jshows the structure ofFIG.6Iafter deposition of material for gates615in the air regions that were previously sacrificial regions619. This technique of depositing material for gates615is typically referred to as a replacement gate deposition. The material for gates615can include a metal. Such a metal can include, but is not limited to, tungsten. The material for gates615can include a compound of a metal and a non-metal, where the compound has metallic properties. The material for gates615can include, but is not limited to, conductive titanium nitride. The material for gates615can include combinations of materials. For example, the material for gates615can include, but is not limited to, conductive titanium nitride and tungsten. In some structures, conductive titanium nitride of gates615may separate the material for isolation regions618and the material for dielectric harrier610from tungsten of gates615. The deposition of the material for gates615can be made with material at temperatures using deposition techniques that are selective to the material for isolation regions618and the material for dielectric barrier610. By selective deposition with respect to the material for isolation regions618and the material for dielectric barrier610is meant that the selected material for deposition is deposited at the desired location without substantial interaction with the material for isolation regions618and the material for dielectric barrier610. Interaction at the interfaces with the material the material for isolation regions618and the material for dielectric barrier610may occur, but leaving the material for isolation regions618and the material for dielectric barrier610substantially as before the deposition. For forming strings of memory cells in a memory device, forming the material for gates615can include isolating the material for gates615coupled to or integrated with access lines for the memory array. These access lines may be word lines. FIG.6Kshows the structure ofFIG.6Jafter the material for isolation regions618between the material for gates615has been removed. The removal of the tiers of isolation regions618is performed using a chemistry selected in conjunction with the selection of the material for gates615and the material for dielectric barrier610. A criterion used for the selection can include selecting a chemistry that is selective to the material for gates615and material for dielectric barrier610such that the chemistry does not substantially affect the material for gates615and the material for dielectric barrier610. The material for dielectric barrier610acts as a mask that allows tiers of isolation regions618to be removed without removing material for dielectric blocking region609. Removal of tiers of isolation regions618may include use of hydrogen fluoride (HF), a vapor etch, or other chemistry that the material for dielectric barrier610can withstand so that the underlying material for the dielectric blocking region609is not removed with the removal of tiers of isolation regions618. The material for dielectric barrier610, such as AlOxor other high-κ material are to be deposited to be able to resist both a hot phosphoric acid removal of sacrificial regions619, such as a nitride removal, as well as a HF or other chemistry used for removal of isolation regions618, such as an oxide tier removal. For AlOx, there are high temperature ALD processes, as well as halide based ALD processes, that may be implemented for the deposition of AlOxto withstand these chemistries. Halide processes exist for deposition of HfOxand other high-κ materials that may be implemented such that these deposited films stand up to the hot phosphoric acid as well as the HF and other oxide etch chemistries. Other processes for forming HfOxand/or other high-κ materials for dielectric barrier610, such that they survive removal processes, may include use of standard metal organic ALD precursors. Other processes to condition dielectric barrier610to survive removal processes may include using various treatments after ALD deposition. These other processes may include anneals (either in inert or reactive ambients), plasma treatments, etc. FIG.6Lshows the structure ofFIG.6Kwith respect to slits624in the x-direction to the sides of the CTs being formed in open pillar614.FIG.6Lalso indicates that other strings with CTs in a vertical stack are being processed with the structure ofFIG.6K.FIG.6Mshows the structure ofFIG.6Lafter dielectrics622are deposited via slits624to form voids620between gates615of adjacent CTs. Dielectrics622can be formed in a “pinch off” sealing process to seal voids620. The sealing process can be implemented using plasma-enhanced chemical vapor deposition (PECVD) or other depleting process. In forming a seal, using PECVD or other deposition process that is not completely conformal can provide a void. In such cases, the sealing films are typically deposited at sub atmospheric pressures of a few mTorr to a few Torr. This pressure remains inside the void after it is sealed up. This void may be referred to as an “air gap,” but the composition of gases would be that of the process when the void was sealed. This sealing process in forming CT memory cells for memory arrays of a memory device forms voids620between gates that are coupled to or integrated with access lines. For each region between adjacent gates615, dielectric622can be formed surfaces of both the adjacent gates615extending towards the material for the dielectric barrier610. In some embodiments, dielectric622may extend along surfaces of both the adjacent gates615to contact the dielectric harrier610, which may result in a smaller void than with the sealing process controlled, for example by a timed termination of the sealing process, such that, dielectric622does not contact dielectric barrier610. FIG.6Nillustrates a cross-sectional representation of an embodiment of a string611having multiple CTs in an electronic apparatus600resulting from processing in accordance with processing features illustrated inFIGS.6A-6M. The multiple CTs in an electronic apparatus600can be structured similar or identical to the CTs of memory device300ofFIG.3. Though the number of CTs shown is three, string611can have more or less than three CTs in string611. As noted in the discussion herein, electronic apparatus may be realized as a memory device having multiple strings of CT memory cells, where each memory cell is identical or similar except that that electrical connections to and locations within the memory array of the memory device will differ. Vertical string611includes a vertical pillar603of semiconductor material coupled to and part of CT structures601-1,601-2, and601-3in a vertical stack606along or as part of vertical string611above conductive region613on substrate602. InFIG.6N, a space is shown between the bottom of stack606and conductive region613to indicate that there may be additional materials and/or integrated circuit structures between the bottom of stack606and conductive region613. In various applications, such additional integrated materials may include, for example, source-side select transistor material. Depending on the architecture of electronic apparatus600that may include a memory device, conductive region613may be a source region. Conductive region613may include semiconductor material. The semiconductor material may include, but is not limited to, monocrystalline silicon or polycrystalline silicon. Substrate602may be a semiconductor substrate or a substrate having a combination of semiconductor material and insulating material. CT structure601-1is arranged as a first charge trap structure along vertical string611, above which charge trap structures601-2and601-3are arranged in vertical stack606with each of charge trap structures601-2and601-3are disposed above another CT structure of vertical stack606. The semiconductor material of semiconductor pillar603is arranged as a channel603-1,603-2, and603-3for CT structures601-1,601-2, and601-3, respectively. Each of CT structures601-1,601-2and601-3includes a tunnel region607-1,607-2, and607-3, respectively, adjacent and contacting their respective channels603-1,603-2, and603-3. Each of tunnel regions607-1,607-2, and607-3can be implemented as set of barriers, for example, a three region tunnel barrier. Such a three region tunnel barrier can be implemented as a region of dielectric oxide followed by a region of dielectric nitride followed by another region of dielectric oxide. Each of tunnel regions607-1,607-2, and607-3may be implemented as a two region tunnel barrier. Each of tunnel regions607-1,607-2, and607-3may be implemented as a one region tunnel barrier. Further, each of tunnel regions607-1,607-2, and607-3may have four or more regions, where the selection of material and thicknesses of these tunnel regions depends on the capability of the material with the given thicknesses to perform as a tunneling region. Each of CT structures601-1,601-2, and601-3includes a charge trap region605-1,605-2, and605-3, respectively, adjacent and contacting their respective tunnel regions607-1,607-2, and607-3. Each of charge trap regions605-1,605-2, and605-3can be a dielectric material that can store charge from channels603-1,603-2, and603-3, respectively. Charge trap regions605-1,605-2, and605-3can be a dielectric nitride region such as, for example, a region including dielectric silicon nitride. Other dielectric materials for charge trap regions605-1,605-2, and605-3can be used to trap charge. Each of CT structures601-1,601-2, and601-3includes a dielectric blocking region609-1,609-2, and609-3, respectively, adjacent and contacting their respective charge trap region605-1,605-2, and605-3. Each of CT structures601-1,601-2, and601-3include a dielectric barrier610-1,610-2, and610-3and a gate615-1,615-2, and615-3, respectively, where each dielectric barrier610-1,610-2, and610-3is disposed between dielectric blocking region609-1,609-2, and609-3and gates615-1,615-2, and615-3of their respective CT structures601-1,601-2, and601-3. Each of dielectric barriers610-1,610-2, and610-3can be implemented using materials for the dielectric barriers selected to enable processing of voids between CT structures601-1,601-2, and601-3arranged in the 3D stack606associated with string611. 3D stack606can be realized as a 3D NAND stack606. Each of dielectric barriers610-1,610-2, and610-3can include an aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. Each dielectric harrier610-1,610-2, and610-3extends to the dielectric barrier of an adjacent CT structure and is arranged with gate615-1,615-2, and615-3of its respective CT structure601-1,601-2, and601-3and the gate of the adjacent charge trap structure, providing a void between the charge trap structure and the adjacent charge trap structure. Dielectric barrier610-3of CT structure601-3extends to dielectric barrier610-2of CT structure601-2and is arranged with gate615-3of CT structure601-3and gate615-2of adjacent CT structure601-2such that void620-3is provided. Dielectric barrier610-2of CT structure601-2extends to dielectric barrier610-1of CT structure601-1and is arranged with gate615-2of CT structure601-2and gate615-1of adjacent CT structure601-1such that void620-2is provided. Each CT structure601-1,601-2, and601-3is arranged with an adjacent CT structure, vertically up or vertically down in stack606associated with vertical string611. In addition, dielectric barrier610-1of CT structure601-1extends to a region on which stack606is disposed. The region may be an isolation region or another active device area such as an access transistor that couples stack606to conductive region613on substrate602. Dielectric barrier610-1of CT structure601-1is arranged with gate615-1of CT structure601-1and the region on which stack606is disposed such that void620-1is provided. Alternatively, string611can be structured directly on conductive region613, where electrical isolation between gate615-1and conductive region613is provided at least in part by void620-1. Each of voids620-1,620-2, and620-3can be sealed by a dielectric region622-1,622-2, and622-3, respectively. Dielectric region622-1is located on the region on which stack606is disposed (alternatively conductive region613) and extends to and is located on gate615-1of CT601-1. Void620-1is contained within dielectric harrier610-1extended to the region on which stack606is disposed (alternatively conductive region613), gate615-1, dielectric region6224on gate615-1, the region on which stack606is disposed (alternatively conductive region613), and dielectric region622-1on the region on which stack606is disposed (alternatively conductive region613). Dielectric region622-2is located on gate615-2of CT structure601-2and extends to and is located on gate615-1of CT601-1. Void620-2is contained within dielectric barrier610-2extended to dielectric barrier610-1, gate615-2, dielectric region622-2on gate615-2of CT structure601-2, gate615-1of adjacent CT structure601-1, and dielectric region622-2on gate615-1of CT structure601-1. Dielectric region622-3is located on gate615-3of CT601-3and extends to and is located on gate615-2of CT structure601-2. Void620-3is contained within dielectric barrier610-3extended to dielectric barrier610-2. gate615-3, dielectric region622-3on gate615-3of CT structure601-3, gate615-2of adjacent CT structure601-2, and dielectric region622-3on gate615-2of CT structure601-2. In some variations, dielectric regions622-1,622-2, and622-3may extend along the surfaces of the gates between which they are respectively located to the dielectric barrier extending between adjacent CT structures that are separated by the respective dielectric regions622-1,622-2, and622-3. In such variations, each associated void is contained within a dielectric barrier, a dielectric region on the gate of a charge trap structure, and a dielectric region on the gate of an adjacent charge trap structure. Such voids may be smaller than those in which the sealing dielectrics do not extend to their associated dielectric barriers. The voids between gates of adjacent CT structures can be largest in vertical extent at the dielectric barriers between the adjacent CT structures. As can be seen inFIG.6N, tunnel regions607-1,607-2, and607-3, charge trap regions605-1,605-2and605-3, dielectric blocking regions609-1,609-2, and609-3of electronic apparatus600can be implemented similar to or identical to tunnel regions307-1,307-2, and307-3, charge trap regions305-1,305-3and305-3, dielectric blocking regions309-1,309-2, and309-3of memory device300ofFIG.3. Semiconductor pillar603of string611of memory device600can be structured as a doped semiconductor hollow channel. Semiconductor pillar603can include poly silicon as a hollow channel surrounding a dielectric604. Semiconductor pillar603can operatively conduct a current between conductive region613and a conductive data line coupled to semiconductor pillar603. Such conductive data line may be coupled to semiconductor pillar603by an access transistor. In various 3D memory architectures, such arrangement of conductive region613and a conductive data line coupled to semiconductor pillar603can be provided with conductive region613being a source region and conductive data line. The conductive data line can be a bit line. The current can be affected by the charge stored in CT structures601-1,601-2, and601-3along string611, where control of storing the charge is by the gates615-1,615-2, and615-3of CT structures601-1,601-2, and601-3. Gates615-1,615-2, and615-3can be incorporated in access lines of electronic apparatus of600. The access lines may be word lines. As with the memory device300ofFIG.3, voids620-1,620-2, and630-3between CT structure601-1and the region on which stack606is disposed (alternatively conductive region613), between CT structures601-2and601-1, and between CT structures601-3and601-2provide voids between access lines of electronic apparatus600. These voids can decrease access line (gate) to access line (gate) capacitance relative to using conventional dielectric materials between such access lines. Using voids, such as voids620-1,620-2, and630-3, for an acceptable capacitance, can allow the distance between access lines (gates) to CT cells to be smaller, allowing more room for the access lines (gates) to CT cells, that is, access lines (gates) can be vertically wider, which can lower the access line resistance. Using features associated with methods of forming one or more CTs, taught herein, a memory device can include a number of CT memory cells. A memory device can comprise: a number of vertical strings, where each vertical string includes a vertical pillar of semiconductor material; and multiple charge trap structures arranged in a vertical stack of each string with each charge trap structure vertically adjacent another one of the multiple charge trap structures in the vertical stack. Each charge trap structure can include: a tunnel region adjacent and contacting the vertical pillar; a charge trap region adjacent and contacting the tunnel region; a dielectric blocking region adjacent and contacting the charge trap region; a gate, the gate separated by a void from the gate of an adjacent charge trap structure; and a dielectric harrier between the dielectric blocking region and the gate. The void can be contained within the dielectric barrier, a dielectric region on the gate of the charge trap structure, and a dielectric on the gate of the adjacent charge trap structure. The memory device may include a number of arrangements of the multiple charge trap structures in the vertical stack. The tunnel region can extend along the vertical pillar of semiconductor material and can extend through the other charge trap structures as the tunnel region of each charge trap structure. The charge trap region can extend along the vertical pillar of semiconductor material and can extend through the other charge trap structures as the charge trap region of each charge trap structure. The dielectric blocking region of the first charge trap structure can extend along the vertical pillar of semiconductor material and can extend through the other charge trap structures as the dielectric blocking region of each charge trap structure. The dielectric barrier can extend along the vertical pillar of semiconductor material and can extend through the other charge trap structures as the dielectric barrier of each charge trap structure. The memory device may include a number of features in each charge trap structure. The dielectric barrier can include aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. The vertical pillar can be structured as a doped hollow channel. The doped hollow channel can include poly silicon surrounding a dielectric. The gates can be incorporated in access lines of a memory array of the memory device. FIG.7illustrates an embodiment of an example of a wafer700arranged to provide multiple electronic components. Wafer700can be provided as a wafer in which a number of dice705can be fabricated. Alternatively, wafer700can be provided as a wafer in which the number of dice705have been processed to provide electronic functionality and are awaiting singulation from wafer700for packaging. Wafer700can be provided as a semiconductor wafer, a semiconductor on insulator wafer, or other appropriate wafer for processing electronic devices such as an integrated circuit chips. Wafer700can be fabricated in accordance with methods associated with any embodiment or combination of embodiments related toFIGS.1-6. Using various masking and processing techniques, each die705can be processed to include functional circuitry such that each die705is fabricated as an integrated circuit with the same functionality and packaged structure as the other dice on wafer700. Alternatively, using various masking and processing techniques, various sets of dice705can be processed to include functional circuitry such that not all of the dice705are fabricated as an integrated circuit with the same functionality and packaged structure as the other dice on wafer700. A packaged die having circuits integrated thereon providing electronic capabilities is herein referred to as an integrated circuit (IC). Wafer700can comprise multiple dice705. Each die705of the multiple dice can include a charge trap structure. The charge trap structure and similar charge trap structures can include various of the features for charge flash structures associated withFIGS.1-6. The charge trap structure can include a semiconductor pillar operable to conduct a current; a charge trap region separated from the semiconductor pillar by a tunnel region; a dielectric blocking region on the charge trap region; a gate on the dielectric blocking region to control storage of charge in the charge trap region, the gate separated by a void from a region which the charge trap structure is directly disposed; and a dielectric barrier separating the dielectric blocking region from the gate. The dielectric barrier may be in an arrangement with the gate such that there is a void between the gate and the region which the charge trap structure is directly disposed. The void can be contained within the dielectric harrier, a dielectric region on and contacting the gate, and the region which the charge trap structure is directly disposed. The charge trap structure of each die705can be one of multiple charge trap structures arranged in a vertical stack along a vertical string of a number of vertical strings, where each trap structure is vertically adjacent another one of the multiple charge trap structures in the vertical stack. Each charge trap structure along a respective vertical string can include: a semiconductor pillar for the charge trap structure that is a portion of semiconductor material arranged vertically along the vertical string for all charge trap structures along the vertical string; a tunnel region adjacent and contacting the semiconductor pillar; a charge trap region adjacent and contacting the tunnel region; a dielectric blocking region adjacent and contacting the charge trap region; a gate, where the gate is separated by a void from the gate of an adjacent charge trap structure; and a dielectric barrier between the dielectric blocking region and the gate. The dielectric barrier of each charge trap structure can extend to the dielectric barrier of an adjacent charge trap structure and can be arranged with the gate of the respective charge trap structure and the gate of the adjacent charge trap structure, providing a void between the charge trap structure and the adjacent charge trap structure. The dielectric barrier can include aluminum oxide or a dielectric having a dielectric constant greater than that of aluminum oxide. The semiconductor pillar can include poly silicon surrounding a dielectric. FIG.8shows a block diagram of an embodiment of an example system800that includes a memory863structured with an array of CT structures as memory cells. The architectures of the CT structures and the memory can be realized in a manner similar to or identical to structures in accordance with various embodiments discussed herein. System800can include a controller862operatively coupled to memory863. System800can also include an electronic apparatus867and peripheral devices869. One or more of controller862, memory863, electronic apparatus867, and peripheral devices869can be in the form of one or more ICs. A bus866provides electrical conductivity between and/or among various components of system800. In an embodiment, bus866can include an address bus, a data bus, and a control bus, each independently configured. In an alternative embodiment, bus866can use common conductive lines for providing one or more of address, data, or control, the use of which is regulated by controller862. Controller862can be in the form or one or more processors. Electronic apparatus867may include additional memory. Memory in system800may be constructed as one or more types of memory such as, but not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, and magnetic based memory. Peripheral devices869may include displays, imaging devices, printing devices, wireless devices, additional storage memory, and control devices that may operate in conjunction with controller862. In various embodiments, system800includes, but is not limited to, fiber optic systems or devices, electro-optic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices such as wireless systems or devices, telecommunication systems or devices, and computers. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. | 71,493 |
11943925 | DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, semiconductor memory devices according to some embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. FIG.1is a block diagram illustrating a semiconductor memory device according to some embodiments of the inventive concepts. Referring toFIG.1, a semiconductor memory device may include a memory cell array1, a row decoder2, a sense amplifier3, a column decoder4, and a control logic 5. The memory cell array1may include a plurality of memory cells MC three-dimensionally arranged. The memory cell array1may include first conductive lines BL, second conductive lines SL intersecting the first conductive lines BL, and the plurality of memory cells MC disposed at intersection points of the first and second conductive lines BL and SL, respectively. In some embodiments, each of the memory cells MC may operate in a volatile memory mode or a non-volatile memory mode, depending on a voltage condition. Each of the memory cells MC may include first and second gate electrodes, a source electrode, and a drain electrode. The drain electrode of each of the memory cells MC may be connected to the first conductive line (e.g., a bit line BL), and the source electrode of each of the memory cells MC may be connected to the second conductive line (e.g., a source line SL). The first gate electrode of each of the memory cells MC may be connected to a first word line WL1, and the second gate electrode of each of the memory cells MC may be connected to a second word line WL2. The row decoder2may decode an address signal inputted from the outside to select one among the source lines SL of the memory cell array1. The address signal decoded in the row decoder2may be provided to a row driver (not shown), and the row driver may provide predetermined voltages to the source lines SL, respectively, in response to control signals of control circuits. The sense amplifier3may sense and amplify a voltage difference between a reference bit line and the bit line BL selected by an address signal decoded from the column decoder4and may output the amplified voltage difference to an external device (e.g., a memory controller). The column decoder4may provide a data transmission path between the sense amplifier3and an external device (e.g., a memory controller). The column decoder4may decode an address signal inputted from the outside to select one among the bit lines BL. The control logic 5 may generate control signals for controlling operations of writing/reading data into/from the memory cell array1. FIG.2is a perspective view schematically illustrating a semiconductor memory device according to some embodiments of the inventive concepts. Referring toFIG.2, a semiconductor memory device may include a cell array structure CS and a peripheral circuit structure PS on the cell array structure CS. The peripheral circuit structure PS may include core and peripheral circuits formed on a semiconductor substrate. The core and peripheral circuits may include the row and column decoders2and4(seeFIG.1), the sense amplifier3(seeFIG.1) and the control logic 5 (seeFIG.1), described with reference toFIG.1. The cell array structure CS may be disposed on the peripheral circuit structure PS and may include a memory cell array including memory cells three-dimensionally arranged on the peripheral circuit structure PS. The memory cell array may include horizontal patterns sequentially stacked on a substrate, vertical patterns vertically intersecting the horizontal patterns, and memory elements disposed between the horizontal patterns and the vertical patterns. In some embodiments, the peripheral circuit structure PS may be formed on a first semiconductor substrate, and the cell array structure CS may be formed on a second semiconductor substrate. Metal pads of the first semiconductor substrate may be connected to metal pads of the second semiconductor substrate by a bonding method, and thus the peripheral circuit structure PS may be electrically connected to the cell array structure CS. FIG.3is a perspective view illustrating a memory cell array of a semiconductor memory device according to some embodiments of the inventive concepts.FIG.4is an enlarged cross-sectional view of a portion ‘P’ ofFIG.3to illustrate a unit memory cell of a semiconductor memory device according to some embodiments of the inventive concepts. Referring toFIG.3, first conductive lines and second conductive lines, which intersect each other, may be provided on a substrate100. In the following embodiments, the first conductive lines will be described as bit lines BL, and the second conductive lines will be described as source lines SL. In certain embodiments, the first conductive lines may be source lines, and the second conductive lines may be bit lines. The substrate100may be a semiconductor substrate including a semiconductor material. For example, the semiconductor substrate may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Bit lines BL1and BL2may extend lengthwise in a first direction D1parallel to a top surface of the substrate100and may be stacked in a third direction D3perpendicular to the top surface of the substrate100. In some embodiments, the bit lines BL1and BL2may include first bit lines BL1provided at one side of the source lines SL, and second bit lines BL2provided at another side of the source lines SL. For example, the second bit lines BL2may be spaced apart from the first bit lines BL1in a second direction D2with the source lines SL interposed therebetween. The second direction D2parallel to a top surface of the substrate100may be different from the first direction D1. The source lines SL may be disposed between the first and second bit lines BL1and BL2and may extend lengthwise in the third direction D3perpendicular to the top surface of the substrate100. The source lines SL may be spaced apart from each other in the first direction D1on the substrate100. For example, the first and second bit lines BL1and BL2and the source lines SL may include at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). Memory cells MC1and MC2may be provided at intersection points of the source lines SL and the first and second bit lines BL1and BL2, respectively. For example, the memory cells MC1and MC2may be three-dimensionally arranged on the substrate100. In some embodiments, the memory cells MC1and MC2may include first memory cells MC1provided at intersection points of the first bit lines BL1and the source lines SL, respectively, and second memory cells MC2provided at intersection points of the second bit lines BL2and the source lines SL, respectively. The first and second memory cells MC1and MC2adjacent to each other in the second direction D2may share the source line SL. One of the first and second memory cells MC1and MC2may be selected by one selected among the first and second bit lines BL1and BL2and one selected among the source lines SL. Each of the first and second memory cells MC1and MC2may include a semiconductor pattern SP1or SP2. The semiconductor pattern SP1or SP2may have a bar shape having a long axis in the second direction D2. Each of the first memory cells MC1may include a first semiconductor pattern SP1, and each of the second memory cells MC2may include a second semiconductor pattern SP2. The first and second semiconductor patterns SP1and SP2of the first and second memory cells MC1and MC2may be spaced apart from each other in the first direction D1, the second direction D2and the third direction D3. For example, the first and second semiconductor patterns SP1and SP2may be three-dimensionally arranged on the substrate100. The first and second semiconductor patterns SP1and SP2may include at least one of silicon or germanium. Alternatively, the first and second semiconductor patterns SP1and SP2may include an oxide semi conductor material. Referring toFIG.4, each of the first and second semiconductor patterns SP1and SP2may include a source region SR having a first conductivity type (e.g., an N-type), a drain region DR having a second conductivity type (e.g., a P-type), and a channel region CR in an intrinsic state between the source region SR and the drain region DR. The source region SR may be doped with N-type dopants, and the drain region DR may be doped with P-type dopants. A length of the source region SR in the second direction D2may be different from a length of the drain region DR in the second direction D2. The drain region DR of the first semiconductor pattern SP1may be electrically connected to the first bit line BL1, and the drain region DR of the second semiconductor pattern SP2may be electrically connected to the second bit line BL2. The source regions SR of the first and second semiconductor patterns SP1and SP2adjacent to each other in the second direction D2may be electrically connected to one of the source lines SL. The first and second semiconductor patterns SP1and SP2may be mirror-symmetrical with respect to the source line SL. For example, the arrangement of the source region SR, the channel region CR, and the drain region DR of the first semiconductor pattern SP1may be mirror-symmetrical to the arrangement of the source region SR, the channel region CR, and the drain region DR of the second semiconductor pattern SP2with respect to the source line SL. Referring again toFIG.3, each of the first bit lines BL1may be connected to a corresponding one of the drain regions DR of the first semiconductor patterns SP1arranged in the first direction D1. Each of the second bit lines BL2may be connected to a corresponding one of the drain regions DR of the second semiconductor patterns SP2arranged in the first direction D1. Each of the source lines SL may be connected to a corresponding one of the source regions SR of the first and second semiconductor patterns SP1and SP2arranged in the third direction D3. First and second word lines WL1aand WL2amay extend in the first direction D1and the third direction D3between the first bit lines BL1and the source lines SL. The first and second word lines WL1aand WL2amay be spaced apart from each other in the second direction D2. The first and second word lines WL and WL2amay surround each of the first semiconductor patterns SP1. The first and second word lines WL1aand WL2amay be adjacent to the channel regions CH of the first semiconductor patterns SP1. Third and fourth word lines WL1band WL2bmay extend in the first direction D1and the third direction D3between the second bit lines BL2and the source lines SL. The third and fourth word lines WL1band WL2bmay be spaced apart from each other in the second direction D2. The third and fourth word lines WL1band WL2bmay surround each of the second semiconductor patterns SP2. The third and fourth word lines WL1band WL2bmay be adjacent to the channel regions CH of the second semiconductor patterns SP2. For example, the first, second, third and fourth word lines WL1a, WL2a, WL1band WL2bmay include at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). Charge storage patterns CSP may be disposed between the first semiconductor patterns SP1and the first and second word lines WL1aand WL2aand between the second semiconductor patterns SP2and the third and fourth word lines WL1band WL2b. For example, each charge storage pattern CSP may be disposed between a corresponding first semiconductor pattern of the first semiconductor patterns SP1and the first and second word lines WL1aand WL2a, and between a corresponding second semiconductor pattern of the second semiconductor patterns SP2and the first and second word lines WL1aand WL2a. The charge storage patterns CSP may surround sidewalls of the first and second semiconductor patterns SP1and SP2, respectively. Each of the charge storage patterns CSP may have a pipe or macaroni shape having opposite open ends. Each of the charge storage patterns CSP may be formed of a single thin layer or a plurality of thin layers. In some embodiments, each of the charge storage patterns CSP may include a tunnel insulating layer TIL, a charge trap layer CTL and a blocking insulating layer BIL, which are sequentially stacked on a surface of each of the first and second semiconductor patterns SP1and SP2. The charge trap layer CTL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nano-crystalline silicon layer, or a laminated trap layer. The tunnel insulating layer TIL may include at least one of materials of which energy band gaps are greater than that of the charge trap layer CTL. For example, the tunnel insulating layer TIL may be a silicon oxide layer. The blocking insulating layer BIL may include at least one of materials of which energy band gaps are less than that of the tunnel insulating layer TIL and greater than that of the charge trap layer CTL. For example, the blocking insulating layer BIL may include at least one of high-k dielectric layers such as an aluminum oxide layer and a hafnium oxide layer. As illustrated inFIGS.3and4, a first electrode EP1may be disposed between the source line SL and each of the first and second semiconductor patterns SP1and SP2, and a second electrode EP2may be disposed between the first semiconductor pattern SP1and the first bit line BL1, and between the second semiconductor pattern SP2and the second bit line BL2. For example, the first and second electrodes EP1and EP2may include or may be formed of at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, or TaSiN. FIG.5is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concepts.FIG.6is a cross-sectional view taken along line A-A′ ofFIG.5to illustrate a semiconductor memory device according to some embodiments of the inventive concepts.FIG.7is a cross-sectional view taken along line B-B′ ofFIG.5to illustrate a semiconductor memory device according to some embodiments of the inventive concepts.FIG.8is a cross-sectional view taken along line C-C′ ofFIG.5to illustrate a semiconductor memory device according to some embodiments of the inventive concepts. Referring toFIGS.5,6,7and8, stack structures ST may be disposed on a substrate100. The stack structures ST may be spaced apart from each other in the first direction D1and the second direction D2on the substrate100. For example, the stack structures ST may be separated from each other in the second direction D2by second separation insulating patterns120, and may be separated from each other in the first direction D1by first separation insulating patterns110. For example, the substrate100may be a single-crystalline silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate100may further include a thin layer formed on a semiconductor substrate. However, embodiments of the inventive concepts are not limited thereto. Each of the stack structures ST may include interlayer insulating layers ILD and first or second semiconductor patterns SP1or SP2, which are alternately stacked in the third direction D3perpendicular to the top surface of the substrate100. Each of the stack structures ST may include the interlayer insulating layers ILD and first conductive lines, which are alternately stacked in the third direction D3. In some embodiments, the first conductive lines may include first bit lines BL1and second bit lines BL2. The stack structures ST may include the first semiconductor patterns SP1provided at intersection points of the first bit lines BL1and source lines SL, respectively, and the second semiconductor patterns SP2provided at intersection points of the second bit lines BL2and the source lines SL, respectively. For example, in the stack structures ST, each first semiconductor pattern SP1may be provided at a corresponding one of the intersection points of the first bit lines BL1and the source lines SL, and each second semiconductor pattern SP2may be provided at a corresponding one of the intersection points of the second bit lines BL2and the source lines SL. The first semiconductor patterns SP1between the first bit lines BL1and the source lines SL may be spaced apart from each other in the first direction D1and the third direction D3. For the simplicity of drawings,FIG.5shows five stack structures disposed between the first bit lines BL1and the source lines SL, andFIGS.6and7show thirteen levels between the substrate100and an upper insulating layer130.FIG.6shows a single stack structure between the second separation insulating pattern120and the source line SL. The first semiconductor patterns SP1of each stack structure may be connected in common to a corresponding one of the source lines SL, and the first semiconductor patterns SP1at each level may be connected in common to a corresponding one of the first bit lines BL1. The first semiconductor patterns SP1located at the same level may be separated from each other in the first direction D1by the first separation insulating patterns110disposed therebetween. The first semiconductor patterns SP1spaced apart from each other in the third direction D3may be connected to the first bit lines BL1, respectively, and may be connected in common to a corresponding one of the source lines SL. The first semiconductor patterns SP1spaced apart from each other in the third direction D3may be separated from each other by the interlayer insulating layers ILD disposed therebetween. The second semiconductor patterns SP2between the second bit lines BL2and the source lines SL may be spaced apart from each other in the first direction D1and the third direction D3. The second semiconductor patterns SP2of each stack structure may be connected in common to a corresponding one of the source lines SL, and the second semiconductor patterns SP2at each level may be connected in common to a corresponding one of the second bit lines BL2. The second semiconductor patterns SP2located at the same level may be separated from each other by the first separation insulating patterns110disposed therebetween. The second semiconductor patterns SP2spaced apart from each other in the third direction D3may be connected to the second bit lines BL2, respectively, and may be connected in common to a corresponding one of the source lines SL. The second semiconductor patterns SP2spaced apart from each other in the third direction D3may be separated from each other by the interlayer insulating layers ILD disposed therebetween. The second semiconductor patterns SP2may be spaced apart from the first semiconductor patterns SP1in the second direction D2. Each of the first and second semiconductor patterns SP1and SP2may include or may be formed of a poly-crystalline silicon layer or a single-crystalline silicon layer. Each of the interlayer insulating layers ILD may include or may be formed of at least one of a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. In each of the stack structures ST, each of the first and second semiconductor patterns SP1and SP2may have a bar shape having a long axis in the second direction D2, as described above. Each of the first and second semiconductor patterns SP1and SP2may include a source region SR, a drain region DR, and a channel region CR between the source region SR and the drain region DR. The source and drain regions SR and DR may have conductivity types opposite to (i.e., different from) each other. Each of the first and second semiconductor patterns SP1and SP2may be locally provided between a pair of the first separation insulating patterns110adjacent to each other in the first direction D1and between a pair of the interlayer insulating layers ILD adjacent to each other in the third direction D3. The first and second semiconductor patterns SP1and SP2may be symmetrical with respect to the source line SL disposed therebetween. For example, the source regions SR of the first and second semiconductor patterns SP1and SP2adjacent to each other in the second direction D2may be connected in common to a corresponding source line SL. The drain regions DR of the first and second semiconductor patterns SP1and SP2adjacent to each other in the second direction D2may be connected to the first and second bit lines BL1and BL2, respectively. A first electrode EP1may be disposed between each of the source lines SL and each of the source regions SR of the first and second semiconductor patterns SP1and SP2, and a second electrode EP2may be disposed between each of the first and second bit lines BL1and BL2and each of the drain regions DR of the first and second semiconductor patterns SP1and SP2. The first and second bit lines BL1and BL2may extend in the first direction D1. The first and second bit lines BL1and BL2may be spaced apart from each other in the second direction D2on each of the interlayer insulating layers ILD and may be disposed between the interlayer insulating layers ILD adjacent to each other in the third direction D3. The lowermost one of the interlayer insulating layers ILD may be disposed between the substrate100and the lowermost ones of the first and second bit lines BL1and BL2. However, embodiments of the inventive concepts are not limited thereto. The first bit lines BL1(or the second bit lines BL2) may be spaced apart from each other in the third direction D3by the interlayer insulating layers ILD of each of the stack structures ST. Each of the stack structures ST may include a second conductive line (i.e., the source line SL) disposed between the first bit lines BL1and the second bit lines BL2. The source line SL may extend from the top surface of the substrate100in the third direction D3. The source lines SL between the first and second bit lines BL1and BL2may be spaced apart from each other in the first direction D1. The source lines SL may extend lengthwise in the third direction D3different from the first direction D1in which the first and second bit lines BL1and BL2extend. Lengths of the source lines SL in the third direction D3may be substantially equal to each other. Each of the source lines SL may penetrate the interlayer insulating layers ILD. The source lines SL may be disposed between the first semiconductor patterns SP1and the second semiconductor patterns SP2. The first and second bit lines BL1and BL2and the source lines SL may include or may be formed of a conductive material such as metal (e.g., copper, tungsten, or aluminum) and/or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride). The interlayer insulating layers ILD may include or may be formed of, for example, silicon nitride. Each of the first separation insulating patterns110may be disposed between the stack structures ST adjacent to each other in the first direction D1. The first separation insulating patterns110may extend from the top surface of the substrate100in the third direction D3and may be spaced apart from each other in the first direction D1. Each of the first separation insulating patterns110may extend in the second direction D2so as to be in contact with sidewalls of the first and second semiconductor patterns SP1and SP2. Each of the first separation insulating patterns110may be in contact with sidewalls of the source lines SL adjacent to each other in the first direction D1. Each of the source lines SL may be disposed between the first separation insulating patterns110adjacent to each other in the first direction D1. The first separation insulating patterns110may include or may be formed of, for example, an oxide, a nitride, and/or an oxynitride. The second separation insulating patterns120may be provided at opposite sides of the stack structures ST on the substrate100. The second separation insulating patterns120may cover opposite sidewalls of the stack structure ST. When the stack structures ST are viewed in a plan view as shown inFIG.5(hereinafter referred to as “in the plan view”), the second separation insulating patterns120may extend in the first direction D1. The second separation insulating patterns120may be spaced apart from each other in the second direction D2which is parallel to the top surface of the substrate100and intersects the first direction D1. The second separation insulating patterns120may be spaced apart from each other in the second direction D2with the stack structure ST interposed therebetween. The second separation insulating patterns120may include or may be formed of, for example, oxide, nitride, and/or oxynitride. First and second word lines WL and WL2a, and third and fourth word lines WL1band WL2bmay extend in the first direction D1to intersect the stack structures ST arranged in the first direction D1. The first and second word lines WL1aand WL2amay be provided between the first bit lines BL1and the source lines SL. The third and fourth word lines WL1band WL2bmay be provided between the second bit lines BL2and the source lines SL. The first and second word lines WL and WL2a, and the third and fourth word lines WL1band WL2bmay have substantially the same thickness in the third direction D3. The first and second word lines WL1aand WL2amay extend in the first direction D1and the third direction D3, thereby completely surrounding a channel region CR of each of the first semiconductor patterns SP1. The first and second word lines WL and WL2awith the first semiconductor patterns SP1may form gate-all-around (GAA) structures (i.e., GAA transistors). The first word line WL1amay be disposed between the source region SR and the drain region DR of the first semiconductor pattern SP1in the plan view, and the second word line WL2amay be disposed between the first word line WL1aand the drain region DR of the first semiconductor pattern SP1in the plan view. The third and fourth word lines WL1band WL2bmay extend in the first direction D1and the third direction D3, thereby completely surrounding the channel regions CR of the second semiconductor patterns SP2. The third and fourth word lines WL1band WL2bwith the second semiconductor patterns SP2may form a gate-all-around (GAA) structures (i.e., GAA transistors). The third word line WL1bmay be disposed between the source region SR and the drain region DR of the second semiconductor pattern SP2in the plan view, and the fourth word line WL2bmay be disposed between the third word line WL1band the drain region DR of the second semiconductor pattern SP2in the plan view. As described above, charge storage patterns CSP may be disposed between the channel regions CR of the first semiconductor patterns SP1and the first and second word lines WL1aand WL2aand between the channel regions CR of the second semiconductor patterns SP2and the third and fourth word lines WL1band WL2b, respectively. The charge storage patterns CSP may completely surround the channel regions CR of the first and second semiconductor patterns SP1and SP2. The charge storage patterns CSP may be spaced apart from each other in the first, second and third directions D1, D2and D3, like the first and second semiconductor patterns SP1and SP2. Each of the charge storage patterns CSP may include a tunnel insulating layer TIL, a charge trap layer CTL, and a blocking insulating layer BIL. The upper insulating layer130may be provided on the first and second word lines WL and WL2aand the third and fourth word lines WL1band WL2b. FIG.9is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concepts.FIG.10is a cross-sectional view taken along line A-A′ ofFIG.9to illustrate a semiconductor memory device according to some embodiments of the inventive concepts. Hereinafter, the descriptions to the same technical features as in the above embodiments ofFIGS.5to8will be omitted for the purpose of ease and convenience in explanation. Referring toFIGS.9and10, first semiconductor patterns SP1may be provided at intersection points of first source lines SL1and bit lines BL, respectively, and second semiconductor patterns SP2may be provided at intersection points of second source lines SL2and the bit lines BL, respectively. The first and second semiconductor patterns SP1and SP2adjacent to each other in the second direction D2may share the bit line BL. The first and second source lines SL1and SL2may be adjacent to each other in the second direction D2, and a second separation insulating pattern120may be provided between the first and second source lines SL1and SL2. The first source lines SL1may extend in the third direction D3and may be spaced apart from each other in the first direction D1by first separation insulating patterns110. Likewise, the second source lines SL2may extend in the third direction D3and may be spaced apart from each other in the first direction D1by the first separation insulating patterns110. FIG.11is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concepts.FIG.12is a cross-sectional view taken along line A-A′ ofFIG.11to illustrate a semiconductor memory device according to some embodiments of the inventive concepts. Hereinafter, the descriptions to the same technical features as in the above embodiments ofFIGS.5to8will be omitted for the purpose of ease and convenience in explanation. Referring toFIGS.11and12, first semiconductor patterns SP1may be provided at intersection points of first bit lines BL1and first source lines SL1, respectively, and second semiconductor patterns SP2may be provided at intersection points of second bit lines BL2and second source lines SL2, respectively. The first and second bit lines BL1and BL2may be adjacent to each other in the second direction D2, and a second separation insulating pattern120extending in the first direction D1may be provided between the first and second bit lines BL1and BL2. The first and second source lines SL1and SL2may be adjacent to each other in the second direction D2, and a third separation insulating pattern125may be provided between the first and second source lines SL1and SL2. The first source lines SL1may extend in the third direction D3and may be spaced apart from each other in the first direction D1by first separation insulating patterns110. Likewise, the second source lines SL2may extend in the third direction D3and may be spaced apart from each other in the first direction D1by the first separation insulating patterns110. The first semiconductor patterns SP1and the second semiconductor patterns SP2may be mirror-symmetrical with respect to the third separation insulating pattern125. For example, first stack structures ST1may be spaced apart from each other in the first direction D1between a pair of the second and third separation insulating patterns120and125, and second stack structures ST2may be spaced apart from each other in the first direction D1between a pair of the second and third separation insulating patterns120and125. Each of the first stack structures ST1may include interlayer insulating layers ILD and the first semiconductor patterns SP1, which are alternately stacked in the third direction D3. Each of the second stack structures ST2may include interlayer insulating layers ILD and the second semiconductor patterns SP2, which are alternately stacked in the third direction D3. FIGS.13,14and15are views for explaining an operation of a semiconductor memory device according to some embodiments of the inventive concepts.FIG.16is a timing diagram illustrating voltage conditions of write and read operations of a semiconductor memory device according to some embodiments of the inventive concepts. FIG.13illustrates an energy level in a thermal equilibrium state of the semiconductor memory device. Referring toFIG.13, in a thermal equilibrium state in which a bias is not applied to the source region SR, the drain region DR and first and second gate electrodes WL1and WL2, energy levels of a valence band and a conduction band of the drain region DR may be higher than those of the source region SR since a P-type Fermi level of the drain region DR is different from an N-type Fermi level of the source region SR. For example, an energy level of the drain region DR may be higher than an energy level of the channel region CR, and an energy level of the source region SR may be lower than the energy level of the channel region CR. For example, the P-type Fermi level Ef(P) may be higher than an intrinsic Fermi level Ef(I) of the channel region CR, which is an intrinsic semiconductor, and the N-type Fermi level Ef(N) may be lower than the intrinsic Fermi level Ef(I) of the channel region CR, and when the drain region DR, the source region SR, and the channel region CR are in the thermal equilibrium (e.g., no drain voltage is applied), the energy levels thereof may be shifted such that the P-type Fermi level Ef(P), the N-type Fermi level Ef(N), and the intrinsic Fermi level Ef(I) have the same energy level. FIG.14illustrates a write operation state in a volatile memory mode. Referring toFIGS.14and16, a first gate voltage VG1and a second gate voltage VG2which are opposite or complementary to each other may be applied to the first gate electrode WL1and the second gate electrode WL2, respectively. For example, in the volatile memory mode, the first and second gate voltages VG1and VG2may be about 3V and about −3V, respectively. In the volatile memory mode, the first and second gate voltages VG1and VG2opposite or complementary to each other may be applied to change an energy level of a first channel region CR1adjacent to the first gate electrode WL1and an energy level of a second channel region CR2adjacent to the second gate electrode WL2. When the first gate voltage VG1is greater than the second gate voltage VG2, the energy level of the first channel region CR1may be changed by the first gate voltage VG1as if the first channel region CR1is doped with dopants having the first conductivity type (e.g., an N-type), and the energy level of the second channel region CR2may be changed by the second gate voltage VG2as if the second channel region CR2is doped with dopants having the second conductivity type (e.g., a P-type). Thus, an energy barrier may be formed in the channel region in the intrinsic state. For example, a p-i-n structure of the semiconductor pattern SP2may be changed into a p-n-p-n structure, and electrons may be stored in the first channel region CR1, and holes may be stored in the second channel region CR2. When a drain voltage VD(e.g., about 1 V) is applied to the bit line BL in the state in which the channel region has the energy level of the p-n-p-n structure, an energy barrier between the drain region DR and the first channel region CR1may be increased, and thus a drain current through the semiconductor pattern SP2does not flow, which corresponds to writing zero (0) state. To read the data 0 state, the first and second gate voltages VG1and VG2opposite or complementary to each other may be applied to the first and second gate electrodes WL1and WL2, and the drain voltage VDfor a read operation, which may be lower than the drain voltage VDfor the write operation of the data zero state, may be applied to the bit line BL. The drain current does not flow due to an energy barrier between the first and second channel regions CR1and CR2, and thus no drain current may be determined as the data 0 state. When the first gate voltage VG1(e.g., −3 V) is less than the second gate voltage VG2(e.g., +3 V), the drain voltage VD(e.g., about 1 V) may be applied to the bit line BL in a state in which the first and second gate voltages VG1and VG2are applied, and thus the energy barrier between the drain region DR and the first channel region CR1may be reduced and the energy barrier between the source region SR and the second channel region CR2may be reduced. As a result, the drain current may flow through the semiconductor pattern SP2, and the flow of the drain current may correspond to writing one (1) state. For examples, charges may be injected into the first and second channel regions CR1and CR2, and thus the energy barriers between the source and drain regions SR and DR may disappear and at the same time, the semiconductor pattern SP2may operate like a diode in an internal forward bias state. This phenomenon may generate a memory window characteristic MW1in the volatile memory mode, as illustrated inFIG.18(data 1 state). To read the data 1 state, the first and second gate voltages VG1(e.g., +3 V) and VG2(e.g., −3 V) opposite or complementary to each other may be applied to the first and second gate electrodes WL1and WL2, and a read voltage may be applied to the bit line BL. The energy barriers between the first and second channel regions CR1and CR2may be reduced, and thus the drain current may flow. As a result, the data 1 state may be determined. FIG.15illustrates a write operation state in a non-volatile memory mode. Referring toFIGS.15and16, first and second gate voltages VG1and VG2in the non-volatile memory mode may be greater than the first and second gate voltages VG1and VG2in the volatile memory mode. For example, in the non-volatile memory mode, the first and second gate voltages VG1and VG2may be about 11 V and about −11 V. In the non-volatile memory mode, the first and second gate voltages VG1and VG2opposite or complementary to each other may be applied to change an energy level of the first channel region CR1adjacent to the first gate electrode WL1and an energy level of the second channel region CR2adjacent to the second gate electrode WL2. When the first gate voltage VG1is greater than the second gate voltage VG2, the energy level of the first channel region CR1may be changed by the first gate voltage VG1as if the first channel region CR1is doped with dopants having the first conductivity type (e.g., an N-type), and the energy level of the second channel region CR2may be changed by the second gate voltage VG2as if the second channel region CR2is doped with dopants having the second conductivity type (e.g., a P-type). Thus, an energy barrier may be formed in the channel region in the intrinsic state. For example, the p-i-n structure of the semiconductor pattern SP2may be changed into a p-n-p-n structure. When the drain voltage VD(e.g., about 2 V) is applied to the bit line BL in the state in which the semiconductor pattern SP2has the energy level of the p-n-p-n structure, the energy barrier between the drain region DR and the first channel region CR1may be increased, and thus the drain current through the semiconductor pattern SP2does not flow, which corresponds to writing 0 state. Since absolute values of the first and second gate voltages VG1and VG2in the non-volatile memory mode are greater than those in the volatile memory mode, charges may be accumulated in the first and second channel regions CR1and CR2of the semiconductor pattern SP2, and charges may be trapped in the charge trap layer CTL by a hot carrier injection phenomenon or charges stored in the charge trap layer CTL may be discharged into the first and second channel regions CR1and CR2. For example, a ground voltage may be applied to the source region SR, the first and second gate voltages VG1and VG2opposite or complementary to each other may be applied to the first and second gate electrodes WL1and WL2, and a predetermined drain voltage VDmay be applied to the bit line BL. For example, the first and second gate voltages VG1and VG2may be 11V and −11V, and the drain voltage VDmay be about 2V. Electrons may be trapped in the charge trap layer CTL adjacent to the first channel region CR1, and holes may be trapped in the charge trap layer CTL adjacent to the second channel region CR2. This phenomenon may generate a memory window characteristic MW2in the non-volatile memory mode, as illustrated inFIG.18. FIG.17is a graph showing operation characteristics according to drain voltage and gate voltage conditions of a semiconductor memory device according to some embodiments of the inventive concepts.FIG.18is a graph showing a drain current according to a drain voltage of a semiconductor memory device according to some embodiments of the inventive concepts. Referring toFIGS.17and18, a drain current according to a drain voltage may show hysteresis and may have a volatile memory characteristic or a non-volatile memory characteristic, depending on a drain voltage condition. The memory cell in the volatile memory mode has a first memory window MW1which corresponds to a width of the hysteresis of the drain current according to the drain voltage, and the memory cell in the non-volatile memory has a second memory window MW2which corresponds to a width of the hysteresis of the drain current according to the drain voltage. According to the embodiments of the inventive concepts, the memory cells without a separate data storage element may be three-dimensionally implemented on the substrate. Each of the memory cells may selectively operate in the volatile or non-volatile memory mode, depending on a voltage condition. While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description. | 42,267 |
11943926 | DETAILED DESCRIPTION Hereinafter, example embodiments will be described with reference to the accompanying drawings. FIG.1is a schematic cross-sectional view of a semiconductor device according to example embodiments.FIG.2is an enlarged view of a semiconductor device according to example embodiments.FIG.2is an enlarged view of region “A” ofFIG.1. Referring toFIGS.1and2, a semiconductor device100amay include a peripheral circuit structure PERI, including a first substrate201, and a memory cell structure CELL including a second substrate101. The memory cell structure CELL may be disposed above the peripheral circuit structure PERI. In contrast, in some other example embodiments, the memory cell structure CELL may be disposed below the peripheral circuit structure PERI. The peripheral circuit structure PERI may include the first substrate201, source/drain regions205and the device isolation layers210in the first substrate201, and circuit elements220, circuit contact plugs270, circuit interconnection lines280, and a peripheral insulating layer290disposed on the first substrate201. The first substrate201may have an upper surface extending in an X direction and a Y direction. An active region may be defined in the first substrate201by the device isolation layers210. Source/drain regions205, including impurities, may be disposed in a portion of the active region. The first substrate201may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, and/or a group II-VI compound semiconductor. The first substrate201may be provided as a bulk wafer or an epitaxial layer. The circuit elements220may include a planar transistor. Each of the circuit elements220may include a circuit gate dielectric layer222, a spacer layer224, and a circuit gate electrode225. Source/drain regions205may be disposed in the first substrate201on opposite sides of the circuit gate electrode225. The peripheral insulating layer290may be disposed on the circuit element220on the first substrate201. Circuit contact plugs270may penetrate through the peripheral insulating layer290to be connected to the source/drain regions205. An electrical signal may be applied to the circuit element220by the circuit contact plugs270. In a region, not illustrated, the circuit contact plugs270may also be connected to the circuit gate electrode225. The circuit interconnection lines280may be connected to the circuit contact plugs270and may be disposed as a plurality of layers. The memory cell structure CELL may include a second substrate101, a first horizontal conductive layer102disposed on the second substrate101, a second horizontal conductive layer104disposed on the first horizontal conductive layer104, a stack structure GS, a channel structure CH, and a separation structure SR. The stack structure GS may include a plurality of gate electrodes130stacked to be spaced apart from each other in a direction, perpendicular to an upper surface of the second horizontal conductive layer104, and a plurality of interlayer insulating layers120stacked alternately with the plurality of gate electrodes. The channel structure CH may penetrate through the stack structure GS, and the separation structure SR may penetrate through the stack structure GS and may extend in a length direction. The memory cell structure CELL may further include a first conductive pattern107protruding outwardly of the separation structure SR from a side surface of the separation structure SR. In example embodiments, the memory cell structure CELL may further include a third horizontal conductive layer105disposed on the second horizontal conductive layer104. The second substrate101may have an upper surface extending in the X direction and the Y directions. The second substrate101may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, and/or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, and/or silicon-germanium. The second substrate101may further include impurities. The second substrate101may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer. The first horizontal conductive layer102may be stacked on an upper surface of the second substrate101to be in contact with the second substrate101. At least a portion of the first horizontal conductive layer102may function as a portion of a common source line of the semiconductor device100a. For example, the horizontal conductive layer102may function as a common source line together with the second substrate101. As illustrated inFIG.2, the first horizontal conductive layer102may include a horizontal portion102a, disposed between the second substrate101and the second horizontal conductive layer104, and a vertical portion102bdirectly connected to the channel layer140on the periphery of the channel layer140. An upper surface of the vertical portion102bof the first horizontal conductive layer102may be disposed on a lower level than an upper surface of the second horizontal conductive layer104. In some example embodiments, in a process of etching a region corresponding to the separation structure SR to be described later with reference toFIG.11E, a metal pad MP may be formed prior to the etching process to easily stop the etching in a region adjacent to the second horizontal conductive layer104, even if the second horizontal conductive layer104is not formed to have a great thickness. In addition, since the second horizontal conductive layer104may not be formed to have a great thickness, difficulty of a process of removing a region corresponding to the vertical portion102bof the first horizontal conductive layer102may be reduced in a process of removing the first to third horizontal insulating layers111,112, and113to be described later with reference toFIG.11G. The first horizontal conductive layer102may include a semiconductor material, for example, polycrystalline silicon. The first horizontal conductive layer102may be a doped layer. In a region, not illustrated, the first horizontal conductive layer102may not extend downwardly of a region in which the gate electrodes130extend by different lengths to have a staircase shape. In this case, an insulating layer, rather than the first horizontal conductive layer102, may be disposed below the gate electrodes130. The second horizontal conductive layer104and the third horizontal conductive layer105may be sequentially stacked on the first horizontal conductive layer102. Each of the second horizontal conductive layer104and the third horizontal conductive layer105may be referred to as a support layer. A side surface of the second horizontal conductive layer104may be disposed to be farther from a central axis L of the separation structure SR than a side surface of the third horizontal conductive layer105. For example, the support layers104and105may include a first portion, adjacent to a lowermost interlayer insulating layer120L, among the interlayer insulating layer120, and a second portion comprising a side surface disposed to be farther from the central axis of the separation structure SR than a side surface of the first portion. In a region separated by the separation structure SR, a side surface of the second horizontal conductive layer104may be in contact with the first conductive pattern107. A distance W2between side surfaces in contact with the first conductive pattern107of the second horizontal conductive layer104may be greater than a minimum width W1of a first portion SR1of the separation structure SR. A side surface of the second horizontal conductive layer104is illustrated as being fully covered with the first conductive pattern107, but the present disclosure is not limited thereto. The side surface of the second horizontal conductive layer104may be in contact with a separation insulating layer185of the separation structure SR. The third horizontal conductive layer105may be disposed between the second horizontal conductive layer104and the stack structure GS. The third horizontal conductive layer105may be disposed on a higher level than the second portion SR2of the separation structure SR. The third horizontal conductive layer105may be disposed on an upper end T of the second portion SR2of the separation structure SR. The third horizontal conductive layer105may be disposed on a lower level than a lowermost interlayer insulating layer120L. The third horizontal conductive layer105may be disposed on a level higher than a region in which a width of the separation structure SR is discontinuously changed. The third horizontal conductive layer105may be disposed on the first conductive pattern107to cover an upper surface of the first conductive pattern107. The third horizontal conductive layer105may be in contact with the first conductive pattern107and the second horizontal conductive layer104. Since the third horizontal conductive layer105is disposed between at least a portion of the second portion SR2of the separation structure SR and the lowermost interlayer insulating layer120L, the first conductive pattern107may not be in contact with the lowermost interlayer insulating layer120L and may be formed in only a region adjacent to the second horizontal conductive layer104. At least a portion of the second and third horizontal conductive layers104and105may function as a portion of a common source line of the semiconductor device100a. For example, the at least a portion of the second and third horizontal conductive layers104and105may function as a common source line together with the second substrate101and the first horizontal conductive layer102. The second and third horizontal conductive layers104and105may include a semiconductor material, for example, polycrystalline silicon. The second and third horizontal conductive layers104and105may be doped layers or layers including impurities diffused from the first horizontal conductive layer102. In some example embodiments, when the second and third horizontal conductive layers104and105are formed of the same material, a boundary surface between the second and third horizontal conductive layers104and105may be confirmed or may not be confirmed. The first conductive pattern107may be disposed in a region adjacent to the second horizontal conductive layer104. The first conductive pattern107may be disposed on a level between the first horizontal insulating layer102and the lowermost interlayer insulating layer120L. The first conductive pattern107may protrude from a side surface of the separation structure SR in a direction of the second horizontal conductive layer104. The first conductive pattern107may be disposed between the separation structure SR and the second horizontal conductive layer104. The first conductive pattern107is illustrated as having an angular shape, but a shape thereof is not limited thereto. The first conductive pattern107may have various shapes such as a curved boundary surface. An upper surface of the first conductive pattern107may be covered with the third horizontal conductive layer105. The first conductive pattern107may be in contact with a side surface of the second horizontal conductive layer104, a lower surface of the third horizontal conductive layer105, and the separation structure SR. The first conductive pattern107may be disposed on a lower level than the lowermost interlayer insulating layer120L. In a manufacturing process to be described later with reference toFIG.11C, since the third horizontal conductive layer105is stacked on the second horizontal conductive layer104to be disposed on the metal pad MP, the lowermost interlayer insulating layer120L may not be etched in a process of etching the first to third horizontal insulating layers111,112, and113to be described later with reference toFIG.11G. Thus, the first conductive pattern107may not be in contact with the lowermost interlayer insulating layer120L. The first conductive pattern107may comprise a pair of patterns symmetrical with respect to the central axis L of the separation structure SR. A distance W2between side surfaces of the pair of first conductive patterns107in contact with the second horizontal conductive layer104may be greater than the minimum width W1of the first portion SR1of the separation structure SR. The first conductive pattern107may be formed of the same material as the first horizontal conductive layer102. The first conductive pattern107may include a semiconductor material, for example, polycrystalline silicon. The gate electrodes130may be spaced apart from each other vertically and stacked on the second substrate101to constitute a stack structure GS. The gate electrodes130may include a lower gate electrode130L constituting a gate of a ground select transistor, memory gate electrodes130M constituting a plurality of memory cells, and upper gate electrodes130U constituting gates of string select transistors. The number of memory gate electrodes130M, constituting memory cells, may be determined depending on capacity of the semiconductor device100a. According to example embodiments, the number of the upper gate electrodes130U and the number of the lower gate electrode130L may each be 1 to 4 or more, and the upper and lower gate electrodes130U and130L may have the same structure as or different structure from the memory gate electrodes130M. In example embodiments, the gate electrodes130may further include a gate electrode130disposed above the upper gate electrodes130U and/or below the lower gate electrodes130L and constituting an erase transistor used in an erase operation based on gate-induced drain leakage (GIDL). In addition, some of the gate electrodes130, for example, the memory gate electrodes130M, adjacent to the upper or lower gate electrodes130U and130L, may be dummy gate electrodes. The gate electrodes130may include a metal material such as tungsten (W). According to some example embodiments, the gate electrodes130may include polycrystalline silicon or a metal silicide material. In some example embodiments, the gate electrodes130may further include a diffusion barrier (not shown). For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN), or combinations thereof. The interlayer insulating layers120may be disposed between the gate electrodes130. Similarly to the gate electrodes130, the interlayer insulating layers120may be spaced apart from each other in a direction, perpendicular to an upper of the second substrate101, and may be disposed to extend in the X direction. The interlayer insulating layers120may include an insulating material such as a silicon oxide or a silicon nitride. According to some example embodiments, in which the separation structure SR includes the separation insulating layer185, the following description of the separation structure SR may be interpreted as a description of the separation insulating layer185. The separation structure SR may be disposed to extend through the gate electrodes130in the Y direction. The separation structure SR may penetrate through the stack structure GS including all of the gate electrodes130stacked on the second substrate101, the first horizontal conductive layer102, and the second horizontal conductive layer104to be connected to the second substrate101. In some example embodiments, a lowermost surface of the separation structure SR may be disposed on a higher level than a lowermost surface of the channel structure CH. The lowermost surface of the separation structure SR is illustrated as being disposed on the same level as a lower surface of the first horizontal conductive layer102, but the present disclosure is not limited thereto. The lowermost surface of the separation structure SR may be disposed on a lower level than the lower surface of the first horizontal conductive layer102. In some example embodiments, the separation structure SR may be formed to be recessed inwardly of at least a portion of the second substrate101. The separation structure SR may include a bent portion formed due to a difference in width in a region adjacent to the second and third horizontal conductive layers104and105. The separation structure SR may include a first portion SR1, having a continuously decreased width, and a second portion SR2disposed below the first portion SR1and having a discontinuously changed width. The first portion SR1of the separation structure SR may penetrate through the stack structure GS, and the second portion SR2may penetrate through the first and second horizontal conductive layers102and104. The second portion SR2of the separation structure SR may correspond to a region in which a metal pad MP to be described with reference toFIG.11Fis removed. The first portion SR1of the separation structure SR may have a shape in which a width thereof is decreased in a direction toward the second substrate101due to a high aspect ratio. The first portion SR1of the separation structure SR may have a minimum width W1in a lower portion of the first region SR1, and the second portion SR2may have a width W3greater than the minimum width of the first portion SR1. An upper portion of the second portion SR2of the separation structure SR may have a greater width than the lower portion of the first portion SR1. The second portion SR2of the separation structure SR may include a region, having a width increased in a direction toward the second substrate101, and a region having a width decreased in a direction toward the second substrate101. For example, the second portion SR2of the separation structure SR may have a maximum width between an upper end T of the second portion SR2and a lowermost surface of the separation structure SR. In the some example embodiments, the upper end T of the second portion SR2of the separation structure SR is defined as a point at which a width of the separation structure SR is discontinuously changed from the first portion SR1. At least a portion of the second portion SR2of the separation structure SR may be disposed on a higher level than the lowermost surface of the second horizontal conductive layer104. The third horizontal conductive layer105may be disposed on the upper end T of the second part SR2of the separation structure SR. A height H of the second portion SR2of the separation structure SR may be substantially the same as the sum of a thickness VT1of the first horizontal conductive layer102and a thickness VT2of the second horizontal conductive layer104, but is not limited thereto. In example embodiments, the height H1of the second portion SR2of the separation structure SR may be greater than the sum of the thickness VT1of the first horizontal conductive layer102and the thickness VT2of the second horizontal conductive layer104. The separation structure SR may include a separation insulating layer185. The isolation insulating layer185may include an insulating material. In example embodiments, the separation structure SR may further include a conductive layer disposed in the separation insulating layer185. In this case, the conductive layer may function as a common source line of the semiconductor device100aor a contact plug connected to the common source line. The channel structures CH may each constitute a single memory cell string, and may be disposed to be spaced apart from each other while forming a row and a column. Each of the channel structures CH have a columnar shape, and may have an inclined side surface narrowed in a direction toward the second substrate101according to an aspect ratio. The channel layer140may be disposed in the channel structures CH. In the channel structures CH, the channel layer140may be formed to have an annular shape surrounding a channel buried insulating layer150. However, according to example embodiments, the channel layer140may have a columnar shape such as a cylindrical shape or a prismatic shape without the channel buried insulating layer150. The channel layer140may be connected to the first horizontal conductive layer102in a lower portion thereof. The channel layer140may include a semiconductor material such as polycrystalline silicon or single-crystalline silicon. In the channel structure CH, channel pads155may be disposed on the channel layer140. The channel pads155may be disposed to cover the upper surface of the channel buried insulating layer150and to be electrically connected to the channel layer140. The channel pads155may include, for example, doped polycrystalline silicon. A gate dielectric layer145may be disposed between the gate electrodes130and the channel layer140. Although not illustrated in detail, the gate dielectric layer145may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer140. The tunneling layer may tunnel charges to the charge storage layer and may include, for example, a silicon oxide (SiO2), a silicon nitride (Si3N4), a silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include a silicon oxide (SiO2), a silicon nitride (Si3N4), a silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In example embodiments, at least a portion of the gate dielectric layer145may extend along the gate electrodes130in a horizontal direction. An upper separation region180may be disposed to penetrate through a portion of gate electrodes130including uppermost upper gate electrodes130U, among the gate electrodes130. The upper separation region180may separate a total of four gate electrodes130including the upper gate electrodes130U from each other in the Y direction. However, the number of gate electrodes130, separated from each other by the upper separation region180, may be changed in various manners in example embodiments. The upper gate electrodes130U, separated from each other by the upper separation region180, may constitute different string select lines. The upper separation region180may include an insulating material. The insulating material may include, for example, a silicon oxide, a silicon nitride, and/or a silicon oxynitride. A cell insulating layer190may be disposed on the stack structure GS. The cell insulating layer190may be formed of an insulating material, and may include a plurality of insulating layers. InFIGS.3to9, descriptions of the same components as those described inFIGS.1to2will be omitted, and only modified components of the semiconductor device will be described. FIG.3is a schematic cross-sectional view of a semiconductor device according to example embodiments.FIG.4is a partially enlarged view of a semiconductor device according to example embodiments.FIG.4is an enlarged view of region “B” ofFIG.3. Referring toFIGS.3and4, unlike the semiconductor device100aofFIG.1, a semiconductor device100bmay not include a third horizontal conductive layer105. In the semiconductor device100b, a memory cell structure CELL may include a separation structure SR, including a bent portion in a region adjacent to a lowermost interlayer insulating layer120L and a second horizontal conductive layer104, and a second conductive pattern108protruding outwardly of the separation structure SR from a side surface of the separation structure SR. A second conductive pattern108may be disposed in a region adjacent to the second horizontal conductive layer104. The second conductive pattern108may be disposed on a level between a first horizontal insulating layer102and a lowermost interlayer insulating layer120L. The second conductive pattern108may protrude from a side surface of the separation structure SR in a direction of the lowermost interlayer insulating layer120L on a boundary between a first portion SR1and a second portion SR2of the separation structure SR. The second conductive pattern108may be disposed between the separation structure SR and the lowermost interlayer insulating layer120L. The second conductive pattern108is illustrated as only being in contact with the lowermost interlayer insulating layer120L, but the present disclosure is not limited thereto. The second conductive pattern108may be in contact with a side surface of a second horizontal conductive layer104. The second conductive pattern108may be disposed on a higher level than a lower surface of the lowermost interlayer insulating layer120L. The second conductive pattern108may comprise a pair of patterns symmetrical with respect to a central axis L of the separation structure SR. In some example embodiments, in a semiconductor device manufactured by a manufacturing process to be described with reference toFIGS.12A to12E, the third horizontal conductive layer105ofFIGS.1and2is not formed. Therefore, in an etching process to be desired with reference toFIG.12D, at least a portion of the lowermost interlayer insulating layer120L may be removed together with first to third horizontal insulating layers111,112, and113. Accordingly, the second conductive pattern108may be in contact with the lowermost interlayer insulating layer120L. The second conductive pattern108may be formed of the same material as the first horizontal conductive layer102. The second conductive pattern108may include a semiconductor material, for example, polycrystalline silicon. The separation structure SR may include a first portion SR1, having a continuously decreased width, and a second portion SR2having a discontinuously changed width below the first portion SR1. That is, the width may be greater at an upper portion of the first portion SR1and smaller at a lower portion of the first portion SR1. The first portion SR1of the separation structure SR may penetrate through a stack structure GS, and the second portion SR2may penetrate through at least a portion the first and second horizontal conductive layers102and104and the lowermost interlayer insulating layer120L. At least a portion of the second portion SR2of the separation structure SR may be disposed on a higher level than a lower surface of the lowermost interlayer insulating layer120L. An upper end T of the second portion SR2of the separation structure SR may be disposed on a higher level than the second horizontal conductive layer104. The upper end T of the second portion SR2of the separation structure SR may be disposed on a higher level than the lower surface of the lowermost interlayer insulating layer120L. Among the interlayer insulating layers120, the lowermost interlayer insulating layer120L may include a first portion, having a side surface relatively close to a central axis L of the separation structure SR, and a second portion having a side surface disposed relatively distant from the central axis L of the separation structure SR. The first portion may be adjacent to a lowermost gate electrode130disposed on the lowermost interlayer insulating layer120L, and the second portion may be adjacent to the second horizontal conductive layer104. FIG.5is a schematic cross-sectional view of a semiconductor device according to example embodiments.FIG.6is a partially enlarged view of a semiconductor device according to example embodiments.FIG.6is an enlarged view of region “C” ofFIG.5 Referring toFIGS.5and6, a semiconductor device100cmay include a support layer including a first portion P1, adjacent to a lowermost interlayer insulating layer120L, and a second portion P2disposed below the first portion P1. In some example embodiments, the support layer may include a second horizontal conductive layer104, and a boundary surface may not be disposed between the first portion P1and the second portion P2of the support layer104. The first portion P1of the support layer104may protrude further to the separation structure SR than the second portion P2. A side surface of the first portion P1of the support layer104may be closer from a central axis L of the separation structure SR than a side surface of the second portion P2. A first conductive pattern107may be in contact with a lower surface of the first portion P1and a side surface of the second portion P2of the support layer104adjacent to the separation structure SR. An upper end T of the second portion SR2of the separation structure SR may be disposed on a lower level than an upper surface of the support layer104. For example, a point, at which a width of the separation structure SR is continuously decreased in a direction toward the second substrate101and is then discontinuously changed, may be disposed on a lower level than the upper surface of the support layer104. That is, the support layer104have a middle surface parallel to the upper and lower surfaces of the support layer104. FIG.7is a schematic cross-sectional view of a semiconductor device according to example embodiments. Referring toFIG.7, in a semiconductor device100d, a lowermost surface of a separation structure SR may be disposed on a lower level than a lower surface of a first horizontal conductive layer102. The lowermost surface of the separation structure SR may be disposed on a lower level than a lowermost surface of a channel structure CH. A height H of a second portion SR2of the separation structure SR is greater than the sum of a thickness VT1of the first horizontal conductive layer102and a thickness VT2of a second horizontal conductive layer104. When a metal pad MP to be described inFIG.11Bis formed, a degree of recessing the second substrate101may be adjusted to adjust a height of the metal pad MP may be adjusted. Since the metal pad MP serves as an etch-stop layer, the height of the metal pad MP may be freely changed to reduce difficulty of an etching process ofFIG.11E. As described above, when the metal pad MP is formed to be lower than the lowermost surface of the channel structure CH in a process of forming the metal pad MP ofFIG.11B, the lowermost surface of the separation structure SR is of the channel structure CH may be disposed to be lower than the lowermost surface of the channel structure CH. FIG.8is a schematic cross-sectional view of a semiconductor device according to example embodiments. Referring toFIG.8, in a semiconductor device100e, a lowermost surface of a separation structure SR may penetrate through an entire second substrate101. The lowermost surface of the separation structure SR may be disposed on a lower level than a lower surface of a first horizontal conductive layer102, and may be disposed on a lower level than a lowermost surface of a channel structure CH. The lowermost surface of the separation structure SR may be disposed on substantially the same level as a lower surface of the first substrate101. According to some example embodiments, the lowermost surface of the separation structure SR may be disposed on a lower level than an upper surface of a peripheral insulating layer290by recessing a portion of the peripheral insulating layer290. A height H of a second portion SR2of the separation structure SR may be greater than the sum of a thickness VT1of a first horizontal conductive layer102and a thickness VT2of a second horizontal conductive layer104. The height H of the second portion SR2of the separation structure SR may be substantially the same as the sum of the thickness VT1of the first horizontal conductive layer102, the thickness VT2of the second horizontal conductive layer104, and a thickness of the second substrate101. When the metal pad MP to be described inFIG.11Bis formed to penetrate through the entire second substrate101, the lowermost surface of the separating structure SR may be disposed on substantially the same level as a lowermost surface of the second substrate101. FIG.9is a schematic cross-sectional view of a semiconductor device according to example embodiments. Referring toFIG.9, a semiconductor device100fmay include a lower stack structure GS1and an upper stack structure GS2in which stack structures of gate electrodes130are vertically stacked. Channel structures CH may include lower channel structures CH1, penetrating through the lower stack structure GS1, and upper channel structures CH2penetrating through the upper stack structure GS2. Such a structure of the channel structures CH may be introduced to stably form the channel structures CH when the number of the stacked gate electrodes130is relatively great. The channel structures CH may have a shape in which the lower channel structures of the lower stack structure GS1and the upper channel structures CH2of the upper stack structure GS2are connected to each other, and may include a bent portion formed due to a difference in width in a connection region. A channel layer140and a channel insulating layer150may be in a state of being connected to each other between the lower channel structure CH1and the upper channel structure CH2. A channel pad155may be disposed on only the upper channel structure CH2. However, in example embodiments, each of the lower channel structure CH1and the upper channel structure CH2may include a channel pad155. In this case, the channel pad155of the lower channel structure CH1may be connected to the channel layer140of the upper channel structure CH2. An upper interlayer insulating layer125having a relatively great thickness may be disposed on an uppermost portion of the lower stack structure GS1. However, shapes of the interlayer insulating layers120and the upper interlayer insulating layer125may be changed in various ways in example embodiments. FIG.10is a schematic cross-sectional view of a semiconductor device according to example embodiments. Referring toFIG.10, in a semiconductor device100g, a memory cell structure CELL may be disposed below a peripheral circuit structure PERI. The memory cell structure CELL may further include a channel contact plug160disposed on channel pads155in the semiconductor device100adescribed inFIGS.1to2, bitlines165disposed on the channel contact plug160, an upper insulating layer192disposed on a cell insulating layer190, and an upper vertical interconnection170. The memory cell structure CELL may further include first bonding pads PAD1. At least some of the first bonding pads PAD1may be disposed between the bitlines172and a peripheral circuit structure PERI. The peripheral circuit structure PERI may further include second bonding pads PAD2in a region corresponding to the first bonding pads PAD1of the memory cell structure CELL. The second bonding pads PAD2may be brought into contact with the first bonding pads PAD1to be bonded thereto. A peripheral circuit may be disposed on the second bonding pads PAD2, and a first substrate201may be disposed on the peripheral circuit. The channel contact plug160, the bitlines165, and the upper vertical wiring170may be electrically connected to each other. The bitlines165may be electrically connected to a plurality of channel vertical structures CH between the peripheral circuit structure PERI and a stack structure GS. The upper insulating layer192may be formed of an insulating material. The upper vertical interconnection170and the bitlines165may be formed of a conductive material. The first bonding pad PAD1and the second bonding pad PAD2may include a conductive material, for example, copper (Cu). In example embodiments, the memory cell structure CELL and the peripheral circuit structure PERI may be bonded by, for example, copper-to-copper (Cu-to-Cu) bonding. The description of the semiconductor device100gofFIG.10may be equally applied to the semiconductor devices ofFIGS.1to9. FIGS.11A to111are schematic views illustrating a method of manufacturing a semiconductor device according to example embodiments. Referring toFIG.11A, a peripheral circuit structure PERI, including circuit elements220and lower interconnection structures, may be formed on a first substrate201, and a second substrate101, first to third horizontal insulating layers111,112, and113, and the second horizontal conductive layer104, provided by a memory cell structure CELL, may be formed on the peripheral circuit structure PERI. Device separation layers210may be formed in a first substrate201, and then a circuit gate dielectric layer222and a circuit gate electrode225may be sequentially formed on the first substrate201. The device isolation layers210may be formed by, for example, a shallow trench separation (STI) process. The circuit gate dielectric layer222and the circuit gate electrode225may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer222may be formed of a silicon oxide, and the circuit gate electrode225may be formed of at least one of polycrystalline silicon and metal silicide, but the present disclosure is not limited thereto. A spacer layer224and source/drain regions205may be formed on both sidewalls of the circuit gate dielectric layer222and the circuit gate electrode225. According to some example embodiments, the spacer layer224may include a plurality of layers. Then, an ion implantation process may be performed to form the source/drain regions205. Among the lower interconnection structures, circuit contact plugs270may be formed by forming a portion of a peripheral insulating layer290, etching the portion to be removed, and burying a conductive material. The circuit interconnection lines280may be formed by depositing a conductive material and patterning the deposited conductive material. The peripheral insulating layer290may include a plurality of insulating layers. The peripheral insulating layer290may be ultimately formed to cover the circuit elements220and the lower interconnection structures by forming a portion of the peripheral insulating layer290in each process of forming the lower interconnection structures and forming a portion of the peripheral insulating layer290on an uppermost circuit interconnection line280. The second substrate101may be formed on the peripheral insulating layer290. The first substrate101may be formed of, for example, polycrystalline silicon and may be formed by a CVD process. Polycrystalline silicon, forming the first substrate101, may include impurities. The first to third horizontal insulating layers111,112, and113may be sequentially stacked on the first substrate101. Some of the first to third horizontal insulating layers111,112, and113may be replaced with the first horizontal conductive layer102ofFIG.1through a subsequent process. The first and third horizontal insulating layers111and113may include a material different from a material of the second horizontal insulating layer112. For example, the first and third horizontal insulating layers111and113may be formed of the same material as interlayer insulating layers120to be described inFIG.11D, and the second horizontal insulating layer112may be formed of the same material as first sacrificial insulating layers110to be described inFIG.11D. The second horizontal conductive layer104may be formed on the first to third horizontal insulating layers111,112, and113. Referring toFIG.11B, a metal pad MP may be formed to penetrate through the first to third horizontal insulating layers111,112and113and the second horizontal conductive layer104. In a location corresponding to the separation structure SR ofFIG.1, a mask layer may be formed using a photolithography process, and then an etching process may be performed on the first to third horizontal insulating layers111,112, and113and the second horizontal conductive layer104to form an opening. An upper portion of the opening may be formed to have a width greater than a minimum width of the first portion SR1of the separation structure SR ofFIG.1. In example embodiments, the second substrate101may be etched together in the etching process, and the opening may be formed to have different heights by adjusting the degree of etching. The metal pad MP may be formed by burying a conductive material, for example, tungsten, or the like, in the opening and then performing a chemical mechanical polishing (CMP) process. An upper end of the metal pad MP may be formed to have a width greater than the minimum width of the first portion SR1of the separation structure SR ofFIG.1. According to the height of the opening, a lowermost surface of the metal pad MP may be disposed on substantially the same level as a lower surface of the first horizontal insulating layer111, or on a lower level than a lower surface of the first horizontal insulating layer111, or on substantially the same level as the lowermost surface of the second substrate101. Referring toFIG.11C, after the metal pad MP is formed, a third horizontal conductive layer105may be formed on the second horizontal conductive layer104and the metal pad MP. The third horizontal conductive layer105may be formed to cover an entire upper surface of the metal pad MP. Referring toFIG.11D, a sacrificial insulating layers110and an interlayer insulating layers120may be alternately stacked on the third horizontal conductive layer105to form a stack structure GS, and then an upper separation region180and channel structures CH may be formed to penetrate through the stack structure GS. Some of the sacrificial insulating layers110may be replaced with gate electrodes130(seeFIG.1) through a subsequent process. The sacrificial insulating layers110may be formed of a material different from a material of the interlayer insulating layers120, and may be formed of a material having an etch selectivity with respect to the interlayer insulating layers120under specific etching conditions. For example, the interlayer insulating layer120may be formed of a material, one selected from of silicon, a silicon oxide, a silicon carbide, and/or a silicon nitride, different from the material of the interlayer insulating layer120. In some example embodiments, the interlayer insulating layers120may not all have the same thickness. The thicknesses and the numbers of the interlayer insulating layers120and the sacrificial insulating layers110may be variously changed from those illustrated in the drawing. Since the third horizontal conductive layer105is formed to cover the upper surface of the metal pad MP inFIG.11Cbefore the interlayer insulating layers120are formed, a lowermost interlayer insulating layer120L may not be in contact with the metal pad MP. An upper separation region180may be formed by removing a portion of the sacrificial insulating layers110and the interlayer insulating layers120. The upper separation region180may be formed by exposing a region, in which the upper separation region180is to be formed, using a separate mask layer, removing a predetermined number of sacrificial insulating layers110and interlayer insulating layers120from an uppermost portion, and depositing an insulating material. The upper separation region180may extend downwardly of a region, in which the upper gate electrodes130U ofFIG.1are formed, in a Z direction. By performing an etching process in a location corresponding to the channel structures CH ofFIG.1, a channel through-hole may be formed to penetrate through the stack structure GS. The channel through-hole may be filled to form channel structures CH. Referring toFIG.11E, a through-hole HH may be formed in a region corresponding to the separation region SR ofFIG.1. The through-hole HH may be formed by etching the stack structure GS in which the sacrificial insulating layers110and the interlayer insulating layers120are alternately stacked. The metal pad MP may serve as an etch-stop layer due to etch selectivity with respect to neighboring elements. Accordingly, even when the second horizontal conductive layer104formed inFIG.11Adoes not have a great thickness, an etching process may be easily performed by the metal pad MP. When an upper end of the metal pad MP is formed to have a width greater than a minimum width of a lower portion of the through-hole HH, a misalignment between the through-hole HH and the metal pad MP may be reduced in the etching process. Since the height of the metal pad MP may be freely changed, the difficulty of an etching process of the through-hole HH may be reduced. Referring toFIG.11F, a sidewall spacer183may be formed on a sidewall of the through-holes HH, and then the metal pad MP may be removed. While the sidewall spacer183is formed along the sidewall of the through-hole HH, an etch-back process may be performed to expose the metal pad MP. Due to an etch selectivity of the metal pad MP with respect to peripheral components, only a portion of the metal pad MP may be selectively removed from the exposed region. Referring toFIG.11G, portions of the first to third sacrificial insulating layers111,112, and113and the gate dielectric layer145may be removed through an etching process to form a tunnel portion LT. The metal pad MP may be removed to selectively remove the exposed second horizontal insulating layer112, and then the first and third horizontal insulating layers111and113disposed thereabove and therebelow may be removed. The first to third horizontal insulating layers111,112, and113may be removed by, for example, a wet etching process. A portion of the gate dielectric layer145, exposed in the region in which the second horizontal insulating layer112is removed, may also be removed in the process of removing the first and third horizontal insulating layers111and113. In the some example embodiments, since the second horizontal conductive layer104may not be formed to a great thickness, the difficulty of an etching process of removing a portion of the gate dielectric layer145may be reduced. Since a region, in which the metal pad MP is removed, and the lowermost interlayer insulating layer120L are not in contact with each other and the third horizontal conductive layer105is disposed between the region, in which the metal pad MP is removed, and the lowermost interlayer insulating layer120L, the lowermost interlayer insulating layer120L may not be etched in the process of removing the first to third sacrificial insulating layers111,112, and113. Referring toFIG.11H, a conductive material may be deposited on the tunnel portion LT, in which the first to third horizontal insulating layers111,112, and113are removed, to form a preliminary first horizontal conductive layer102P. The sidewall spacers183may not be distinguished from the preliminary first horizontal conductive layer102P, and may be removed together in a process of forming a first horizontal conductive layer102P to be described with reference toFIG.11I. Referring toFIG.11I, a portion of the preliminary first horizontal conductive layer102P, disposed on a sidewall and a lower portion of the through-hole HH, may be removed to form a first horizontal conductive layer102and a first conductive pattern107. Then, the sacrificial insulating layers110may be replaced with a conductive material to form gate electrodes130. The first horizontal conductive layer102may be formed to be partially connected to the channel layer140while filling the tunnel portion LT ofFIG.11H. The first conductive pattern107may be formed by allowing a portion of preliminary first horizontal conductive layer102P to remain, and may constitute a pair of patterns on opposite sides based on a center of the through-hole HH. The sacrificial insulating layers110may be selectively removed with respect to the interlayer insulating layers120and the first to third horizontal conductive layers102,104, and105using an etching process. Accordingly, a plurality of openings may be formed between the interlayer insulating layers120. A conductive material, forming the gate electrodes130, may fill the openings. The conductive material may include a metal, polycrystalline silicon, and/or a metal silicide material. Returning toFIG.1, the through-hole HH region may be filled with an insulating material to form a separation structure SR including the separation insulating layer185. The separation structure SR may include a second portion SR2, corresponding to a region removed after the metal pad MP is formed, and a first portion SR1corresponding to a region in which an etching process is performed on the metal pad MP to form the through-hole HH. FIGS.12A to12Fare schematic views illustrating a method of manufacturing a semiconductor device according to example embodiments. Referring toFIG.12A, sacrificial insulating layers110and interlayer insulating layers120may be alternately stacked on the second horizontal conductive layer104and the metal pad MP ofFIG.11Bto form a stack structure GS, and then the upper separation region180and the channel structures CH may be formed to penetrate through the stack structure GS. The stack structure GS, the upper separation region180, and the channel structures CH may be formed by the same method as described inFIG.11D. A lowermost interlayer insulating layer120L may be formed to be in contact with the metal pad MP. Referring toFIG.12B, a through-hole HH may be formed in a region corresponding to the separation structure SR ofFIG.3. The manufacturing method described with reference toFIG.11Emay be equally applied. Referring toFIG.12C, a sidewall spacer183may be formed on a sidewall of the through-hole HH, and then the metal pad MP may be removed. The manufacturing method described with reference toFIG.11Fmay be equally applied. Referring toFIG.12D, portions of the first to third sacrificial insulating layers111,112, and113and the gate dielectric layer145may be removed through an etching process to form a tunnel portion LT. The manufacturing method described with reference toFIG.11Gmay be equally applied. In addition to the first to third horizontal insulating layers111,112, and113, the lowermost interlayer insulating layer120L disposed on the second horizontal conductive layer104may be exposed when the tunnel portion LT is formed. Thus, a portion of the lowermost interlayer insulating layer120L may be removed. Referring toFIG.12E, a conductive material may be deposited on the tunnel portion LT, in which the first to third horizontal insulating layers111,112, and113are removed, to form a preliminary first horizontal conductive layer102P. The preliminary first horizontal conductive layer102P may be deposited even on the region in which a portion of the lowermost interlayer insulating layer120L described inFIG.12Dis removed. Referring toFIG.12F, a portion of the preliminary first horizontal conductive layer102P, disposed on the sidewall and the lower portion of the through-hole HH, may be removed to form a first horizontal conductive layer102and a second conductive pattern108. Then, the sacrificial insulating layers110may be replaced with a conductive material to form gate electrodes130. The first horizontal conductive layer102P may be formed to be partially connected to the channel layer140while filling the tunnel portion LT ofFIG.12D. The second conductive pattern108may be formed by allowing a portion of the preliminary first horizontal conductive layer102P to remain, and may constitute a pair of patterns on opposite sides based on a center of the through-hole HH. The second conductive pattern108may be formed by allowing a portion of the preliminary first horizontal conductive layer120P adjacent to the lowermost interlayer insulating layer120L to remain, and may be in contact with the lowermost interlayer insulating layer120L. The manufacturing method described with reference toFIG.11Imay be equally applied to the gate electrodes130. Returning toFIG.3, a region of the through-hole HH may be filled with an insulating material to form a separation structure SR including the separation insulating layer185. The separation structure SR may include a second portion SR2, corresponding to a region removed after the metal pad MP is formed, and a first portion SR1corresponding to a region in which an etching process is performed on the metal pad MP to form the through-hole HH. FIG.13is a schematic view of a data storage system including a semiconductor device according to example embodiments. Referring toFIG.13, a data storage system1000according to some example embodiments may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be a storage device including one or more semiconductor devices1100, and/or an electronic device including a storage device. For example, the data storage system1000may be a solid state drive (SSD) device including one or more semiconductor devices1100, a universal serial bus (USB), a computing system, a medical device, and/or a communications device. The semiconductor device1100may be a nonvolatile memory device, for example, a NAND flash memory device described above with reference toFIGS.1to10. The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. In example embodiments, the first structure1100F may be disposed next to the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure including a bitline BL, a common source line CSL, wordlines WL, first and second upper gate lines UL1and UL2, first and second low gate lines LL1and LL2, and memory cell strings CSTR between the bitline BL and the common source line CSL. In the second structure1100s, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bitline BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be changed in various ways according to example embodiments. In example embodiments, the upper transistors UT1and UT2may include a string select transistor, and the lower transistors LT1and LT2may include a ground select transistor. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The wordlines WL may be gate electrodes of the memory cell transistors MCT, respectively. The upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively. The common source line CSL, the first and second gate lower lines LL1and LL2, the wordlines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending to the second structure1100S in the first structure1100F. The bitlines BL may be electrically connected to the page buffer1120through second interconnection lines1125extending from the first structure1100F to the second structure1100S. In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor, among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1000may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection interconnection1135extending from the first structure1100F to the second structure1100S. The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. According to some example embodiments, the electronic system1000may include a plurality of semiconductor devices1100. In this case, the controller1200may control the plurality of semiconductor devices1000. The processor1210may control all operations of the electronic system1000including the controller1200. The processor1210may operate based on predetermined firmware, and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221processing communications with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written to the memory cell transistors MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, and the like, may be transmitted through the NAND interface1221. The host interface1230may provide a communications function between the electronic system1000and an external host. When a control command is received from the external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command. FIG.14is a schematic perspective view of a data storage system including a semiconductor device according to some example embodiments. Referring toFIG.14, an electronic system2000according to example embodiments includes a main substrate2001, a controller2002mounted on the main substrate2001, and one or more semiconductor packages2003, and DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by interconnection patterns2005formed on the main substrate2001. The main board2001may include a connector2006including a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector2006may vary depending on a communications interface between the electronic system2000and the external host. In example embodiments, the electronic system may communicate with the external host according to one of interfaces such as a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), M-PHY for a universal flash storage (UFS), and the like. In example embodiments, the electronic system2000may operate using power supplied from an external host through the connector2006. The electronic system2000may further include a power management integrated circuit (PMIC) distributing power, supplied from the external host, to the controller2002and the semiconductor package2003. The controller2002may write data to the semiconductor package2003, or may read data from the semiconductor package2003. The controller2002may improve an operation speed of the electronic system2000. The DRAM2004may be a buffer memory for reducing a difference in speeds between the semiconductor package2003, a data storage space, and the external host. The DRAM2004, included in the electronic system2000, may also operate as a type of cache memory, and may provide a space for temporarily storing data in a control operation on the semiconductor packages2003. When the DRAM2004is included in the electronic system2000, the controller2002may further include a DRAM controller for controlling the DRAM2004, in addition to a NAND controller for controlling the semiconductor packages2003. The semiconductor package2003may include first and second semiconductor packages2003aand2003bdisposed to be spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300, respectively disposed on lower surfaces of the semiconductor chips2200, a connection structure2400electrically connecting the semiconductor chips2200and the package substrate2100to each other, and a molding layer2500covering the semiconductor chips2200and the connection structure2400on the package substrate2100. The package substrate2100may be a printed circuit board (PCB) including upper package pads2130. Each of the semiconductor chips2200may include an input/output pad2210. The input/output pad2210may correspond to the input/output pad1101ofFIG.13. Each of the semiconductor chips2200may include first and second stack structures ST1and ST2and channel structures CH. Each of the semiconductor chips2200may include the semiconductor device described with reference toFIGS.1to10. In example embodiments, the connection structure2400may be a bonding wire electrically connecting the input/output pad2210and the package upper pads2130to each other. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other using wire bonding, and may be electrically connected to the upper package pads2130of the package substrate2100. According to example embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a connection structure having a through-silicon via (TSV), rather than the connection structure2400using the wire bonding. In example embodiments, the controller2002and the semiconductor chips2200may be included in a single package. In example embodiments, the controller2002and the semiconductor chips2200are mounted on an additional interposer substrate different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected to each other by a wiring formed in the interposer substrate. FIG.15is a schematic cross-sectional view of a semiconductor package according to some example embodiments.FIG.15illustrates some example embodiments of the semiconductor package2003ofFIG.14, and conceptually illustrates a region taken along line I-I′ of the semiconductor package2003ofFIG.14. Referring toFIG.15, in a semiconductor package2003, a package substrate2100may be a printed circuit board (PCB). The package substrate2100may include a package substrate body portion2120, upper package pads2130disposed on an upper surface of the package substrate body portion2120, lower package pads2125disposed on a lower surface of the package substrate body portion2120or exposed through the package substrate body portion2120, and internal wirings2135electrically connecting the upper package pads2130and the lower package pads2125to each other within the package substrate body portion2120. The upper package pads2130may be electrically connected to a connection structures2400. The lower package pads2125may be connected to wiring patterns2005of the main substrate2010of the electronic system2000through conductive connection portions2800, as illustrated inFIG.14. Each of the semiconductor chips2200may include a semiconductor substrate3010and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral interconnections3110. The second structure3200may include a common source line3205, a stack structure3210on the common source line3205, channel structures3220and separation structures3230penetrating through the stack structure3210, bitlines3240electrically connected to the channel structures3220, and gate interconnection lines3235electrically connected to wordlines (WL ofFIG.13) of the stack structure3210. Each of the first structure3100, the second structure3200, and the semiconductor chips2200may further include a first conductive pattern107protruding outwardly of the separation structure SR from a side surface of the separation structure SR, as illustrated in the enlarged view. In addition, in each of the first structure3100, the second structure3200, and the semiconductor chips2200, the separation structure SR may include a first portion SR1, having a continuously decreased width, and a second portion SR2having a width discontinuously changed below the first portion SR1. Each of the semiconductor chips2200may include a through-interconnection3245electrically connected to peripheral interconnections3110of the first structure3100and extending inwardly of the second structure3200. The through-interconnection3245may penetrate through the stack structure3210, and may be further disposed outside the stack structure3210. Each of the semiconductor chips2200may further include an input/output interconnection line3265, electrically connected to the peripheral interconnections3110of the first structure3100and extending inwardly of the second structure3200, and an input/output pad2210electrically connected to the input/output interconnection line3265. The semiconductor chips2200ofFIG.15may be electrically connected to each other by connection structures2400in the form of bonding wires. However, in example embodiments, semiconductor chips in a single semiconductor package such as the semiconductor chips2200ofFIG.15may be electrically connected to each other by a connection structure including a through electrode TSV. As described above, before a wordline cut etching process is performed, a metal pad used as an etch-stop layer may be performed below a wordline cut to reduce difficulty of an etching process with an increase in the number of semiconductor devices to be stacked. Accordingly, a semiconductor device having reliability, improved through the metal pad below the wordline cut, and a data storage system including the semiconductor device may be provided. While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims. | 65,721 |
11943927 | DETAILED DESCRIPTION Specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms, and they should not be construed as being limited to the specific embodiments set forth herein. Various embodiments of the present disclosure are directed to a semiconductor memory device capable of decreasing an operating voltage and improving operating speed. FIG.1is a schematic circuit diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure. Referring toFIG.1, the semiconductor memory device may be a three-dimensional (3D) nonvolatile memory device or a two-dimensional (2D) nonvolatile memory device, According to an embodiment, the nonvolatile memory device may be a NAND flash memory device. The NAND flash memory device may include a memory cell string CS coupled to a bit line BL and a common source line CSL. The drawing illustrates a single memory cell string CS, but a plurality of memory cell strings may be coupled in parallel between the bit line BL and the common source line CSL. The memory cell string CS may include a source select transistor SST, a plurality of memory cells MC, and a drain select transistor DST disposed between the common source line CSL and the bit line BL. The source select transistor SST may control the electrical coupling between the plurality of memory cells MC and the common source line CSL. A single source select transistor SST may be disposed between the common source line CSL and the plurality of memory cells MC, Although not illustrated in the drawing, two or more source select transistors coupled in series to each other may be disposed between the common source line CSL and the plurality of memory cells MC. The source select transistor SST may be coupled to a source select line SSL. The operation of the source select transistor SST may be controlled by a source gate signal applied to the source select line SSL. The plurality of memory cells MC may be disposed between the source select transistor SST and the drain select transistor DST. The memory cells MC between the source select transistor SST and the drain select transistor DST may be coupled in series to each other. The memory cells MC may be coupled to respective word lines WL. The operation of the memory cells MC may be controlled by cell gate signals applied to the word lines WL. The drain select transistor DST may control the electrical coupling between the plurality of memory cells MC and the bit line BL. The drain select transistor DST may be coupled to a drain select line DSL. The operation of the drain select transistor DST may be controlled by a drain gate signal applied to the drain select line DSL. Each of the memory cells MC may store single-bit data or multi-bit data, FIG.2A,FIG.2B,FIG.2C,FIG.2D,FIG.2E, andFIG.2Fare views illustrating various embodiments for a semiconductor memory device. FIG.2A,FIG.2B, andFIG.2Care perspective views illustrating various embodiments for a 3D NAND flash memory device. Referring toFIG.2A,FIG.2B, andFIG.2C, the semiconductor memory device may include a stacked body100, a channel layer127A,127B, or127C, a tunnel insulating layer125A,125B, or125C, a data storage layer123A,123B, or123C, and a blocking insulating layer121A,121B, or121C. The stacked body100may include interlayer insulating layers101and word lines103. Each of the interlayer insulating layers101and the word lines103may be parallel to an X-Y plane. The interlayer insulating layers101and the word lines103may be stacked in a Z-axis direction perpendicular to the X-Y plane. The interlayer insulating layers101may be disposed alternately with the word lines103. The word lines103may be insulated from each other by the interlayer insulating layers101. The word lines103may be used as the gate electrodes of the memory cells MC described with reference toFIG.1, The word lines103may include at least one of a doped semiconductor, metal, a metal nitride, and a metal silicide. The interlayer insulating layers101may include a silicon oxide layer. The stacked body100may be penetrated by a hole111extending in the Z-axis direction. The sidewalls of the interlayer insulating layers101may be defined along the sidewall of the hole111. According to the embodiment illustrated inFIG.2A, the sidewalls of the word lines103may be defined along the sidewall of the hole111. According to the embodiments illustrated inFIG.2BandFIG.2C, each of the word lines103may have a sidewall that is disposed farther from the central axis of the hole111than the interlayer insulating layers101. Accordingly, a recess area115may be defined between the interlayer insulting layers101that are adjacent to each other in the Z-axis direction. The channel layer127A,127B, or127C may include a semiconductor, such as silicon or the like. The channel layer127A,127B, or127C may extend in the Z-axis direction. The channel layer127A,1278, or127C may form the channel area of the memory cell string CS illustrated inFIG.1. The channel layer127A,1278, or127C may be enclosed by the interlayer insulating layers101and the word lines103. The blocking insulating layer121A,121B, or121C may be interposed between the channel layer127A,127B, or127C and the stacked body100. The blocking insulating layer121A,121B, or121C may include a single layer or a plurality of layers. The data storage layer123A,123B, or123C may be interposed between the blocking insulating layer121A,1213, or121C and the channel layer127A,127B, or127C. The data storage layer123A,123B, or123C may include a charge trap layer or a floating gate layer. The tunnel insulating layer125A,1253, or125C may be interposed between the data storage layer123A,123B, or123C and the channel layer127A,127B, or127C. The tunnel insulating layer125A,1253, or125C may include Metal Organic Frameworks (MOF). The semiconductor memory device may further include a core insulating layer129that fills the central area of the hole111. The channel layer127A,127B, or127C may enclose the sidewall of the core insulating layer129. Unlike what is illustrated inFIGS.2A to2C, the core insulating layer129may be omitted, and the channel layer may extend to fill the central area of the hole111. The channel layer127A,1273, or127C, the tunnel insulating layer125A,125B, or125C, the data storage layer123A,123B, or123C, and the blocking insulating layer121A,121B, or121C may be formed in various structures. Referring toFIG.2A, the blocking insulating layer121A, the data storage layer123A, and the tunnel insulating layer125A may extend in the Z-axis direction along the sidewall of the channel layer127A. Each of the blocking insulating layer121A, the data storage layer123A, and the tunnel insulating layer125A may be disposed between each of the word lines103and the channel layer127A, and may extend into space between each of the interlayer insulating layers101and the channel layer127A. The blocking insulating layer121A may include a silicon oxide layer, but embodiments of the present disclosure are not limited thereto. In an embodiment, the blocking insulating layer121A may include a silicon oxide layer and a metal oxide layer between the silicon oxide layer and the stacked body100. The metal oxide layer may include an oxide having higher dielectric constant than that of the silicon oxide layer. In an embodiment, the metal oxide layer may include an aluminum oxide layer. The data storage layer123A may include a charge trap layer extending in the Z-axis direction along the sidewall of the channel layer127kIn an embodiment, the charge trap layer may include a silicon nitride layer. Referring toFIG.2B, the channel layer127B may include a vertical portion127VP extending in the Z-axis direction and a protrusion127PP protruding from the vertical portion127VP towards each of the word lines103. Each of the blocking insulating layer121B, the data storage layer123B, and the tunnel insulating layer125B may extend into the recess area115. Each of the blocking insulating layer121B, the data storage layer123B, and the tunnel insulating layer125B may be conformally formed along the recess area115, and may have a bending structure. Each of the blocking insulating layer121B, the data storage layer123B, and the tunnel insulating layer125B may enclose the protrusion127PP of the channel layer127B. The blocking insulating layer121B may include the same material as the blocking insulating layer121A described with reference toFIG.2A, and the data storage layer123B may include the same material as the data storage layer123A described with reference toFIG.2A. The charge trap layer as the data storage layer123B is formed in a bending structure, whereby a phenomenon in which charges stored in the charge trap layer move in the Z-axis direction may be reduced. Accordingly, the reliability of the operation of the semiconductor memory device may be improved. Although not illustrated inFIG.2B, the protrusion127PP of the channel layer127B may be omitted, and the tunnel insulating layer125B may be extended to fill the central area of the recess area115, in an embodiment. Referring toFIG.2C, the data storage layers123C may be spaced apart from each other in the Z-axis direction. Each of the data storage layers123C may be locally formed between the interlayer insulating layers101that are adjacent to each other in the Z-axis direction. The data storage layers123C are separated from each other in the Z-axis direction, whereby a phenomenon in which charges stored in the data storage layers123C move in the Z-axis direction may be prevented. Each of the data storage layers123C may include a charge trap layer or a floating gate layer. In an embodiment, the charge trap layer may include a silicon nitride layer. In an embodiment, the floating gate layer may include silicon. The blocking insulating layer121C may include a column portion between each of the interlayer insulating layers101and the tunnel insulating layer125and a bending portion between each of the word lines103and each of the data storage layers123C. The column portion of the blocking insulating layer121C may come into direct contact with the tunnel insulating layer125C, and the bending portion of the blocking insulating layer121C may be conformally formed along the recess area115. The blocking insulating layer121C may include a first oxide layer131, a nitride layer133, and a second oxide layer135, but embodiments of the present disclosure are not limited thereto. In an embodiment, the blocking insulating layer121C may include the same material as the blocking insulating layer121A described with reference toFIG.2A. In the above description, the first oxide layer131may be conformally formed along the sidewall of the hole111and the recess area115. The second oxide layer135may be interposed between the first oxide layer131and the tunnel insulating layer125C. The nitride layer133may be interposed between the first oxide layer131and the second oxide layer135. The first oxide layer131and the second oxide layer135may include silicon dioxide. FIG.2DandFIG.2Eare sectional views illustrating various embodiments for a 3D NAND flash memory device. Hereinafter, descriptions redundant with those describingFIGS.2A to2Cwill be omitted. Referring toFIG.2DandFIG.2E, a semiconductor memory device may include a stacked body100, a channel layer127D or127E, a tunnel insulating layer125D or125E, a data storage layer123D or123E, and a blocking insulating layer121D or121E. The interlayer insulating layers101and word lines103of the stacked body100may be penetrated by a hole111extending in the Z-axis direction. The sidewalls of the word lines103may be defined along the sidewall of the hole111. Each of the interlayer insulating layers101may have a sidewall that is disposed farther from the central axis of the hole111than the word lines103. Accordingly, a recess area117may be defined between the word lines103adjacent to each other in the Z-axis direction. In an embodiment, the central area of the hole111may be filled with a core insulating layer129. The channel layer127D or127E may enclose the core insulating layer129. The blocking insulating layer121D or121E between the stacked body100and the channel layer127D or127E may include a single layer or a plurality of layers. The data storage layer123D or123E between the channel layer127D or127E and the blocking insulating layer121D or121E may include a charge trap layer. The tunnel insulating layer125D or125E between the channel layer127D or127E and the data storage layer123D or123E may include Metal Organic Frameworks (MOF). Each of the blocking insulating layer121D or121E and the data storage layer123D or123E may include portions parallel to the sidewalls of the word lines103. Each of the blocking insulating layer121D or121E and the data storage layer123D or123E may have a bending portion conformally formed along the recess area117. The charge trap layer as the data storage layer123D or123E is formed in a bending structure, whereby a phenomenon in which charges stored in the charge trap layer move in the Z-axis direction may be reduced. According to the embodiment illustrated inFIG.2DandFIG.2E, the charge trap area may include an area enclosed by the word line103in the data storage layer123D or123E, and may extend to the area enclosing the edge of each of the word lines103, Accordingly, the data storage area may be enlarged. Referring toFIG.2D, the tunnel insulating layer125D may extend to be parallel to the data storage layer123D. The tunnel insulating layer125D may have portions parallel to the sidewalls of the word lines103and a bending portion conformally formed along the recess area117. The channel layer127D may include a vertical portion127VP′ extending in the Z-axis direction and a protrusion127PP′ protruding from the vertical portion127VP′ towards each of the interlayer insulating layers101. The tunnel insulating layer125D may enclose the protrusion127PP′ of the channel layer127D. Referring toFIG.2E, the tunnel insulating layer125E may include a vertical portion125VP extending in the Z-axis direction and a protrusion125PP protruding from the vertical portion125VP towards each of the interlayer insulating layers101. The protrusion125PP of the tunnel insulating layer125E may fill the central area of the recess area117. The channel layer127E may extend in the Z-axis direction so as to be parallel to the vertical portion125VP of the tunnel insulating layer125E. Referring toFIG.2DandFIG.2E, because a fringing field f generated by a voltage applied to the word lines103can be shielded through the tunnel insulating layer125D or125E formed in the recess area117, interference between memory cells adjacent to each other in the Z-axis direction may be reduced. Accordingly, variation in the threshold voltage of the memory cell may be reduced, and operation disturbance, such as program disturbance or the like, may be reduced. As a result, the reliability of the operation of the semiconductor memory device may be improved. FIG.2Fis a sectional view illustrating an embodiment for a 2D NAND flash memory device. Referring toFIG.2F, a semiconductor memory device may include a semiconductor substrate231, gate electrodes203, a tunnel insulating layer225, a data storage layer223, and a blocking insulating layer221. The semiconductor substrate231may include an active area. Although not illustrated in the drawing, the active area may be segmented by an isolation layer.FIG.2Fillustrates a section taken by cutting the active area of the semiconductor substrate231. The gate electrodes203may be disposed over the semiconductor substrate231. The gate electrodes203may be spaced apart from each other by a trench241along the direction in which the active area extends. Although not illustrated in the drawing, the upper portion of each of the gate electrodes203extends in the direction intersecting with the active area, thereby forming a word line. In the semiconductor substrate231on the opposite sides of the gate electrodes203, impurity areas231I may be disposed. A portion of the active area, overlapping each of the gate electrodes203and disposed between the impurity areas231I, may be defined as a channel area231C. The tunnel insulating layer225, the data storage layer223, and the blocking insulating layer221may be sequentially stacked between each of the gate electrodes203and the semiconductor substrate231. The blocking insulating layer221may be interposed between each of the gate electrodes203and the semiconductor substrate231. The blocking insulating layer221may include the same material as the blocking insulating layer121A described with reference toFIG.2A, or may include a structure in which the first oxide layer131, the nitride layer133, and the second oxide layer135described with reference toFIG.2Care stacked. The data storage layer223may be interposed between the blocking insulating layer221and the semiconductor substrate231. The data storage layer223may include a charge trap layer or a floating gate layer. The data storage layer223may be locally formed over the semiconductor substrate231between the impurity areas231I, and may be spaced apart from another data storage layer223. In other words, the data storage layers223adjacent to each other in the direction in which the active area of the semiconductor substrate231extends may be to separated from each other by the trench241, However, embodiments of the present disclosure are not limited thereto. Although not illustrated in the drawing, the charge trap layer as the data storage layer223may continuously extend along the active area of the semiconductor substrate231and overlap the impurity areas231I, in an embodiment. The tunnel insulating layer225may be interposed between the data storage layer223and the semiconductor substrate231. The tunnel insulating layer225may include Metal Organic Frameworks (MOF). In an embodiment, the tunnel insulating layer225may be penetrated by the trench241, but embodiments of the present disclosure are not limited thereto, Although not illustrated in the drawing, the tunnel insulating layer225may continuously extend along the active area of the semiconductor substrate231and overlap the impurity areas231I, in an embodiment. As described above with reference toFIGS.2A to2E, the tunnel insulating layer according to an embodiment of the present disclosure may include Metal Organic Frameworks (MOF). The MOF are porous compounds formed of a chemical combination of metal ions and organic ligands or a chemical combination of a metal duster and organic ligands. The MOF are a material that is controllable to have dielectric constant less than that of a silicon dioxide (SiO2). Because the MOF can be formed through Atomic Layer Deposition (ALD) having excellent step coverage, embodiments of the present disclosure may improve the thickness uniformity of the tunnel insulating layer. Because the dielectric constant to of the MOF may be controlled to be equal to or less than 2, tunneling of charges caused by a program voltage and an erase voltage may increase. Accordingly, embodiments of the present disclosure may improve the speed of a program operation and the speed of an erase operation. Because the dielectric constant of the tunnel insulating layer having MOF may be controlled to be low, the efficiency of shielding the fringing field, described with reference toFIG.2DandFIG.2E, may be improved. FIG.3is a view illustrating a tunnel insulating layer according to an embodiment of the present disclosure. Referring toFIG.3, the tunnel insulating layer is Metal Organic Frameworks (MOF) formed of metal centers Mn+coordinated to organic ligands L, and may have pores P. When the MOF are provided, a coordination number, the length of the ligands, a reaction environment for combining the metal centers Mn+with the organic ligands L, and the like may be variously controlled. Accordingly, the size of the pores P may be variously controlled, and the dielectric constant of the MOF may be controlled to be a low value within a range from 1 to 2. The metal centers Mn+of the MOF may include Zn2+, Zr4+, Al3+, and the like. The organic ligands L of the MOF may include 2-methylimidazole, 2-aminoterephthalic acid, 1,3,5-benzenetricarboxylate, and the like. The MOF may include MOF series, ZIF series, UIO series, SIM series, MIL series, HKUST series, and the like. For example, as the MOF series, MOF named MOF-1, MOF-177, or the like may be used as the tunnel insulating layer. As metallic salts for forming MOF, Zn4O(CO2)6, Zn3O(CO2)6, Cr3O(CO2)6, In3O(CO2)6, Ga3O(CO2)6, Cu2O(CO2)4, Zn2O(CO2)4; Fe2O(CO2)4, Mo2O(CO2)4, Cr2O(CO2)4, CO2O(CO2)4, Ru2O(CO2)4, Zr6O4(OH4), Zr6O4(CO2)12, Zr6O8(CO2)8, In(C5HO4N2)4, Na(OH)2(SO3)3, Cu2(CNS)4, Zn(C3H3N2)4, Ni4(C3H3N2)8, Zn3O3(CO2)3, Mg3O3(CO2)3, CO3O3(CO2)3, Ni3O3(CO2)3, Mn3O3(CO2)3, Fe3O3(CO2)3, Cu3O3(CO2)3, Al(OH)(CO2)2, VO(CO2)2, Zn(NO3)2, Zn(O2CCH3), Co(NO3)2, Co(O2CCH3), and the like may be used. As organic ligands for forming MOF, there are an oxalic acid, a fumaric acid, a terephthalic acid (H2BDC), H2BDC-Br, H2BDC—OH, H2BDC-NO2, H2BDC-NH2, H4DOT, H2BDC—(Me)2, H2BDC—(CI)2, H2BDC—(COOH)2, H2BDC—(OC3H5)2, H2BDC—(OC7H7)2, H3BTC, H3BTE, H3BBC, H4ATC, H3THBTS, H3ImDC, H3BTP, DTOA, H3BTB, H3TATB, H4ADB, TIPA, ADP, H6BTETCA, DCDPBN, BPP34C10DA, Ir(H2DPBPyDC)(PPy)2+, H4DH9PhDC, H4DH11PhDC, H6TPBTM, H6BTEI, H6BTPI, H6BHEI, H6BTTI, H6PTEI, H6TTEI, H6BNETPI, H6BHEHPI, HMeIM, and the like. FIG.4illustrates an energy band diagram of a memory cell according to an embodiment of the present disclosure in the state in which an electric field is not applied. Referring toFIG.4, a channel area CH, a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI may be sequentially disposed. The thickness of each of the channel area CH, the tunnel insulating layer TI, the data storage layer DS, and the blocking insulating layer BI may be changed depending on the material thereof. The channel area CH may be defined as one of the channel layers illustrated inFIGS.2A to2Eand the channel area of the semiconductor substrate illustrated inFIG.2F. The tunnel insulating layer TI may be one of the tunnel insulating layers illustrated inFIGS.2A to2F. The data storage layer DS may be one of the data storage layers illustrated inFIGS.2A to2F. The blocking insulating layer BI may be one of the blocking insulating layers illustrated inFIGS.2A to2F. The energy band gap of the tunnel insulating layer TI and the energy band gap of the blocking insulating layer BI may be greater than the energy band gap of the data storage layer DS. The energy band gap indicates the difference between the energy level Ev of a valence band and the energy level Ec of a conduction band. The dielectric constant of the tunnel insulating layer TI formed of MOF may be controlled to be less than the dielectric constant of the blocking insulating layer BI. The blocking insulating layer BI may include at least one of silicon dioxide and a high dielectric material having higher dielectric constant than the silicon dioxide. The tunnel insulating layer TI may be formed of MOF, and the dielectric constant of the MOF may be controlled to be equal to or less than half the dielectric constant of silicon dioxide. FIG.5is an energy band diagram for describing a program operation of a memory cell according to an embodiment of the present disclosure. Referring toFIG.5, an electric field may be formed in a direction from a blocking insulating layer BI to a channel area CH by a program voltage applied at the time of a program operation, and energy band bending may be caused by the electric field. When a program voltage is applied, electric fields in a tunnel insulating layer TI, a data storage layer DS, and the blocking insulating layer BI may be affected by the dielectric constant of each of the tunnel insulating layer TI, the data storage layer DS, and the blocking insulating layer BI. Because the tunnel insulating layer TI has a lower dielectric constant than the blocking insulating layer BI, the electric field applied to the tunnel insulating layer TI may be relatively higher than that applied to the blocking insulating layer BI. Accordingly, tunneling of electrons in the blocking insulating layer BI may be reduced. Also, because tunneling of electrons in the tunnel insulating layer TI can be improved, the program speed may be improved. According to an embodiment of the present disclosure, the tunnel insulating layer TI is formed of MOF, whereby the dielectric constant of the tunnel insulating layer TI may be formed to be equal to or less than half the dielectric constant of the blocking insulating layer BI, Further, the dielectric constant of the tunnel insulating layer TI may be lowered so as to be equal to or less than 2. Because a voltage decrease V1in the tunnel insulating layer TI increases as the dielectric constant of the tunnel insulating layer TI is lower, tunneling of electrons in the tunnel insulating layer TI can be secured even though the electric field is decreased, whereby program operation characteristics may be secured in a low electric field. FIG.6is an energy band diagram for describing an erase operation of a memory cell according to an embodiment of the present disclosure. Referring toFIG.6, an electric field may be formed in a direction from a channel area CH to a blocking insulating layer BI by an erase voltage applied at the time of an erase operation, and energy band bending may be caused by the electric field. By the electric field formed by the erase voltage, the hole of the channel area CH may be injected into a data storage layer DS, and electrons may be released from the data storage layer DS into the channel area CH. Because a tunnel insulating layer TI has a lower dielectric constant than the blocking insulating layer BI, the number of electrons injected into the blocking insulating layer BI from a word line may be reduced during the erase operation, based on a principle similar to that of a program operation. Because a voltage decrease V2in the tunnel insulating layer TI increases as the dielectric constant of the tunnel insulating layer TI is lower; even though an electric field is lowered, erase operation characteristics may be secured based on a principle similar to that of a program operation. As described above, embodiments of the present disclosure form a tunnel insulating layer TI as MOF, whereby the dielectric constant of the tunnel insulating layer TI may be lowered to be equal to or less than half the dielectric constant of a blocking insulating layer BI. Furthermore, the dielectric constant of the tunnel insulating layer TI may be lowered to be equal to or less than 2. Accordingly, an embodiment of the present disclosure may increase the efficiency of charge tunneling in the tunnel insulating layer TI, improve the operation speed of a memory cell, and reduce charge tunneling in the blocking insulating layer BI. FIG.7is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure. Referring toFIG.7, a memory system1100includes a memory device1120and a memory controller1110. The memory device1120may be a multi-chip package configured with a plurality of flash memory chips. The memory device1120may be a 2D NAND flash memory device or a 3D NAND flash memory device. The memory device1120may have a memory cell including a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer may include Metal Organic Frameworks (MOF) having a lower dielectric constant than the blocking insulating layer. The memory controller1110may control the memory device1120, and may include static random access memory (SRAM)1111, a central processing unit (CPU)1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111may be used as working memory of the CPU1112, the CPU1112may perform overall control operations for data exchange of the memory controller1110, and the host interface1113may be provided with a data interchange protocol of a host coupled to the memory system1100. The error correction block1114may detect errors included in data read from the memory device1120, and may correct the detected errors. The memory interface1115may interface with the memory device1120. The memory controller1110may further include read only memory (ROM) or the like that stores code data for interfacing with the host. The above-described memory system1100may be a memory card or a solid state drive (SSD) in which the memory device1120and the memory controller1110are combined with each other. For example, when the memory system1100is an SSD, the memory controller1110may communicate with an external device (e.g., a host) via one of various interface protocols, such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnection-express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (DATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), or an Integrated Drive Electronics (IDE). FIG.8is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Referring toFIG.8, a computing system1200may include a CPU1220, Random Access Memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210, which are electrically coupled to a system bus1260. When the computing system1200is a mobile device, a battery for supplying an operation voltage to the computing system1200may be further included, and an application chipset, an image processor, mobile DRAM, and the like may be further included. The memory system1210may be configured with a memory device1212and a memory controller1211. The memory device1212may be a 2D NAND flash memory device or a 3D NAND flash memory device. The memory device1212may have a memory cell including a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer may include Metal Organic Frameworks (MOF) having a lower dielectric constant than the blocking insulating layer. The present disclosure may decrease the operating voltage of a semiconductor memory device and improve the operating speed thereof through a tunnel insulating layer including Metal Organic Frameworks (MOF). | 30,845 |
11943928 | Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer. As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnection layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers. As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value). As used herein, the term “3D memory device” refers to a semiconductor device with vertically-oriented strings of memory cell transistors (i.e., region herein as “memory strings,” such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to a lateral surface of a substrate. Various embodiments in accordance with the present disclosure provide a 3D memory device with channel hole plug structures for a memory array (also referred to herein as an “array device”) and fabricating methods for forming the channel hole plug structures. In some embodiments, a channel hole can be formed to penetrate an alternating stack including a plurality of conductive/dielectric pairs or a plurality of oxide/nitride pairs. The number of the conductive/dielectric pairs or oxide/nitride pairs can be larger than or equal to 32. A polycrystalline silicon (polysilicon) plug can be formed above the channel hole to electrically connect with a channel structure in the channel hole and to cover the channel hole. That is, a projection of the polysilicon plug can in a lateral plane can fully cover the projection of the channel hole in the lateral plane. As such, the polysilicon plug can provide a reliable electrical connection to the channel structure in the channel hole and an increased area for contact alignment in the subsequent processes. Referring toFIG.1, a flow diagram of an exemplary method for forming a channel hole plug of a 3D memory device is shown in accordance with some embodiments of the present disclosure.FIGS.2A-2Hillustrate cross-sectional views of a region of an exemplary 3D memory device at certain fabricating stages of the method shown inFIG.1. As shown inFIG.1, the method starts at operation S2, in which an alternating dielectric stack is formed on a substrate. In some embodiments, the substrate can be any suitable semiconductor substrate having any suitable structure, such as a monocrystalline single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc. As shown inFIG.2A, an alternating dielectric stack100including a plurality of dielectric layer pairs can be formed on the substrate (not shown inFIG.2A). The alternating dielectric stack100can include an alternating stack of a first dielectric layer102and a second dielectric layer104that is different from first dielectric layer. The plurality of first dielectric layers102and second dielectric layers104are extended in a lateral direction that is parallel to a surface of the substrate. In some embodiments, there are more layers than the dielectric layer pairs made of different materials and with different thicknesses in the alternating dielectric stack100. The alternating dielectric stack100can be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the alternating dielectric stack100can include a plurality of oxide/nitride layer pairs. Each dielectric layer pair includes a layer of silicon oxide102and a layer of silicon nitride104. The plurality of oxide/nitride layer pairs are also referred to herein as an “alternating oxide/nitride stack.” That is, in the alternating dielectric stack100, multiple oxide layers102(shown in the areas with dotes) and multiple nitride layers104(shown in the areas with meshes) alternate in a vertical direction. In other words, except a top and a bottom layer of a given alternating oxide/nitride stack, each of the other oxide layers102can be sandwiched by two adjacent nitride layers104, and each of the nitride layers104can be sandwiched by two adjacent oxide layers102. Oxide layers102can each have the same thickness or have different thicknesses. For example, a thickness of each oxide layer can be in a range from 90 nm to 160 nm, preferably about 150 nm. Similarly, nitride layers104can each have the same thickness or have different thicknesses. For example, a thickness of each nitride layer can be in a range from 80 nm to 110 nm, preferably about 100 nm. It is noted that, in the present disclosure, the oxide layers102and/or nitride layers104can include any suitable oxide materials and/or nitride materials. For example, the element of the oxide materials and/or nitride materials can include, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicides, or any combination thereof. In some embodiments, the oxide layers can be silicon oxide layers, and the nitride layers can be silicon nitride layer. The alternating dielectric stack100can include any suitable number of layers of the oxide layers102and the nitride layers104. In some embodiments, a total number of layers of the oxide layers102and the nitride layers104in the alternating dielectric stack100is equal to or larger than 64. That is, a number of oxide/nitride layer pairs can be equal to or larger than 32. In some embodiments, alternating oxide/nitride stack includes more oxide layers or more nitride layers with different materials and/or thicknesses than the oxide/nitride layer pair. As shown inFIGS.1and2A, the method proceeds to operation S4, in which an insulating layer110and a hard mask layer120can be formed on the alternating dielectric stack100. In some embodiments, the insulating layer110can be the insulating layer110can be made by any suitable insulating material and/or dielectric material, such as silicon oxide. It is noted that, the material of the insulating layer110is different from the material of the nitride layer104in the alternating dielectric stack100. The insulating layer110can be formed on the top surface of the alternating dielectric stack100. The hard mask layer120can be formed on the top surface of the insulating layer110. In some embodiments, the hard mask layer120can include a nitride layer, such as a silicon nitride layer. The insulating layer110and the hard mask layer120can be formed by using any suitable deposition process including, but not limited to, CVD, PVD, ALD, and/or any suitable combination thereof. Referring toFIGS.1and2A-2B, the method proceeds to operation S6, in which a channel structure can be formed. The channel structure can include a channel hole190extending vertically through the alternating dielectric stack100, the insulating layer110and the hard mask layer120, a functional layer on the sidewall of the channel hole190, and a channel layer160between the functional layer and a filling structure. In some embodiments, fabrication processes to form the channel structure include forming a channel hole that extends vertically through the alternating dielectric stack100, the insulating layer110and the hard mask layer120. The channel hole190can be formed by etching the alternating dielectric stack100, the insulating layer110and the hard mask layer120, and a subsequent cleaning process. The etching process to form the channel hole190can be a wet etching, a dry etching, or a combination thereof. In some embodiments, fabrication processes to form a functional layer on the sidewall of the channel hole190. The functional layer can be a composite dielectric layer, such as a combination of a tunneling layer130, a storage layer140, and a barrier layer150. The functional layer, including the tunneling layer130, the storage layer140, and the barrier layer150, can be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. As shown inFIG.2A, the barrier layer150can be formed between the storage layer140and the sidewall of the channel190. The barrier layer150can be used for blocking the outflow of the electronic charges. In some embodiments, the barrier layer150can be a silicon oxide layer or a combination of silicon oxide/silicon nitride/silicon oxide (ONO) layers. In some embodiments, the barrier layer150includes high dielectric constant (high-k) dielectrics (e.g., aluminum oxide). In some embodiments, a thickness of the barrier layer150can be in a range from about 3 nm to 20 nm. The storage layer140can be formed between the tunneling layer130and the barrier layer150. Electrons or holes from the channel layer can tunnel to the storage layer140through the tunneling layer130. The storage layer140can be used for storing electronic charges (electrons or holes) for memory operation. The storage or removal of charge in the storage layer140can impact the on/off state and/or a conductance of the semiconductor channel. The storage layer140can include one or more films of materials including, but are not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer140can include a nitride layer formed by using one or more deposition processes. In some embodiments, a thickness of the storage layer140can be in a range from about 3 nm to 20 nm The tunneling layer130can be formed on the sidewall of the storage layer140. The tunneling layer130can be used for tunneling electronic charges (electrons or holes). The tunneling layer130can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer130can be an oxide layer formed by using a deposition process. In some embodiments, a thickness of the tunneling layer130can be in a range from about 3 nm to 20 nm. In some embodiments, fabrication processes to form the channel structure further include forming a channel layer160covering the sidewall of the functional layer and the top surface of hard mask layer120. In some embodiments, the channel layer160can be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process, such as ALD, CVD, PVD, or any other suitable process. In some embodiments, a thickness of the channel layer160can be in a range from about 5 nm to 20 nm. In some embodiments, fabrication processes to form the channel structure further include forming a filling structure170to cover the channel layer160and fill the channel hole190. In some embodiments, the filling structure170can be an oxide layer formed by using any suitable deposition process, such as ALD, CVD, PVD, etc. In some embodiments, the filling structure170can include one or more airgaps. Referring toFIG.2B, the portions of the channel layer160and the filling structure170located on the top surface of the hard mask layer120can be removed. In some embodiments, the removal process can include, but not limited to, wafer grinding, dry etch, wet etch, chemical mechanical planarization (CMP), any other suitable processes, or any combination thereof. In some embodiment, in the same removal process, the functional layer including the barrier layer150, the storage layer140and the tunneling layer130located on the top surface of the hard mask layer120can also be removed. FIG.5illustrates a top view of the channel structure of an exemplary 3D memory device in accordance with some other embodiments of the present disclosure. After the removal process, the top surface of the channel structure has an approximate round shape that is surrounded by the hard mask layer120. The top surface of the channel structure has a filling structure170in the center of the channel hole190, and multiple rings including the channel layer160, the tunneling layer130, the storage layer140and the barrier layer150that surround the filling structure170from inside to outside. The top surface of the filling structure170can have an approximate round shape. A diameter D1of the top surface of the filling structure170in the lateral direction can be in a range from about 40 nm to 100 nm. A diameter D2of the top aperture of the channel hole190(which is same as the diameter of the top surface of the channel structure) in the lateral direction can be in a range from about 100 nm to 140 nm. It is noted that, the sizes and/or proportions of various layers and/or structures shown in the figures are used for illustrative purpose only, may not reflect the actual sizes and/or proportions of the layers and/or structures, thus do not limit the scope of the present disclosure. Referring toFIGS.1and2C, the method proceeds to operation S8, in which a photoresist patterning180can be formed on the hard mask layer120. The photoresist patterning180can include an opening185to expose the top surface of the channel structure. In some embodiments, fabrication processes to form the photoresist patterning180can include forming a photoresist layer on the top surface of the hard mask layer120and the channel structure by using a spin-on coating process, and a subsequent patterning process to form the opening185that corresponds to the channel structure. In some embodiments, a diameter of the opening185can be slightly larger than the diameter D2of the top surface of the channel structure. Referring toFIGS.1and2D, the method proceeds to operation S10, in which a top portion of the channel structure can be removed to form a recess. In some embodiments, fabrication processes to remove the top portion of the channel structure can include an etching process and a cleaning process. By using the photoresist patterning180as the mask, one or more etching processes including, but not limited to, wet etching, dry etching, or combinations thereof, can be performed to remove the top portion of the channel structure. As such, a recess200penetrating the mask layer120, extending into at least a portion of insulating layer110, and above the remaining channel structure can be formed. In some embodiments, as shown inFIG.2D, the recess200may not have a perfect cylinder shape, but may have a shape approximating to a truncated cone. That is, the diameter of a top aperture of the recess200can be slightly larger than the diameter of a bottom aperture of the recess200. It is noted that, the diameter of the bottom aperture of the recess200is equal to or larger than the diameter D2of the top surface of the channel structure. After the recess200is formed, a cleaning process can be performed to remove the photoresist patterning180. Referring toFIGS.1and2D-2E, the method proceeds to operation S12, in which a channel hole plug can be formed in the recess. In some embodiments, fabrication processes to form the channel hole plug can include forming a semiconductor channel layer210to fill the recess200and cover the top surface of the hard mask layer120, as shown inFIG.2E. In some embodiments, the semiconductor channel layer210can be an amorphous silicon layer or a polysilicon layer formed by using a selective epitaxial process, or by using a thin film deposition process, such as ALD, CVD, PVD, or any other suitable process. The semiconductor channel layer210can be electrically in contact with the channel layer160in the channel structure. In some embodiments, fabrication processes to form the channel hole plug can include performing a removal to remove the hard mask layer120and a top portion of the semiconductor channel layer210to form the channel hole plug215, as shown inFIG.2F. In some embodiments, the removal process can include, but not limited to, wafer grinding, dry etch, wet etch, chemical mechanical planarization (CMP), any other suitable processes, or any combination thereof. The remaining portion of the semiconductor channel layer210can form the channel hole plug215that is electrically in contact with the channel layer160in the channel structure. In some embodiments, a depth of the channel hole plug215in the vertical direction can be in a range from about 100 nm to about 1000 nm. The projection of the channel hole plug215in a lateral plane can cover the projection of the entire channel hole190or the entire channel structure in the lateral plane. In the traditional fabricating method, the channel hole plug is formed on the sidewall of the channel layer160by recessing the filling structure170only. Due to the thickness limitation of the channel layer160and functional layer on the sidewall of the channel hole190, the diameter of the channel hole plug is significantly limited (e.g., up to the diameter D1of the top surface of the filling structure170in the lateral direction, as shown inFIG.5). Such small-sized channel hole plug may lead to a higher resistance and a higher contact resistance. The channel hole plug215formed by the disclosed method can have a larger area by a lateral expansion. For example, as shown inFIG.2G, a minimum diameter D3of the channel hole plug215in the lateral direction can be equal to or larger than the diameter D2of the top aperture of the channel hole190in the lateral direction. As such, the area of the channel hole plug215can be increased by at least 30% compared to the area of the channel hole plug formed by the traditional fabricating method. Thus, the disclosed channel hole plug215can have an increased channel hole electrical contact, thereby leading to an improved electric property. Further, it is noted that, subsequent processes can be performed to further fabricate the 3D memory device. In some embodiments, as shown inFIG.2G, a metal via220can be formed above the channel hole plug215for electronically connecting the channel hole plug215to back end of line (BEOL) metal lines, such as bit lines of double patterning structure. Since the area of the disclosed channel hole plug215is larger than the area of the channel hole plug made by the traditional method, a larger alignment margin for the metal via to land on the channel hole plug215can be achieved to enhance the product yield. In some other embodiments, as shown inFIG.2H, a second alternating dielectric stack300can be formed on the insulating layer110and the channel hole plug215. A second channel structure can be formed penetrating the second alternating dielectric stack300. A second channel layer360in the second channel structure is electrically in contact with the channel hole plug215. The fabrication processes and the physical and chemical properties of the second alternating dielectric stack300and the second channel structure can be referred to the alternating dielectric stack100and the channel structure described above. Since the area of the disclosed channel hole plug215is larger than the area of the channel hole plug made by the traditional method, a larger alignment margin for the second channel layer360to land on the channel hole plug215can be achieved to enhance the product yield. In some embodiments, a gate replacement process (also known as the “word line replacement” process) can be performed to replace second dielectric layers104(e.g., silicon nitride) of the alternating dielectric stack100with conductor layers (e.g., W). As a result, after the gate replacement process, the alternating dielectric stack100becomes alternating conductor/dielectric stack. The replacement of first dielectric layers with conductor layers can be performed by wet etching first dielectric layers (e.g., silicon nitride) selective to second dielectric layers (e.g., silicon oxide) and filling the structure with conductor layers (e.g., W). Conductor layers can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. Conductor layers can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. The formed alternating conductor/dielectric stack and remaining alternating dielectric stack can constitute an alternating stack. Referring toFIG.3, a flow diagram of another exemplary method for forming a channel hole plug of a 3D memory device in accordance with some other embodiments of the present disclosure.FIGS.4A-4Eillustrate cross-sectional views of a region of an exemplary 3D memory device at certain fabricating stages of the method shown inFIG.3. It is noted that, the description of the method below may only include the differences compared to the method described above in connection withFIGS.1and2A-2H. Some detailed information of the fabrication processes and physical and chemical properties of various operations of the method and/or various components of the 3D memory device can be referred to the corresponding descriptions above. As shown inFIGS.3and4A, the method starts at operation S52, in which an alternating dielectric stack100is formed on a substrate (not shown). The alternating dielectric stack100can include an alternating stack of a first dielectric layer102(e.g., silicon oxide layer) and a second dielectric layer104(e.g., silicon nitride layer) that is different from first dielectric layer. At operation S54, the method proceeds to form a first insulating layer110on the alternating dielectric stack100. Referring toFIGS.3and4A-4B, the method proceeds to operation S56, in which a channel structure can be formed. The channel structure can include a channel hole190extending vertically through the alternating dielectric stack100and the first insulating layer110, a functional layer on the sidewall of the channel hole190, and a channel layer160between the functional layer and a filling structure. The functionally layer can be a composite dielectric layer, such as a combination of a tunneling layer130, a storage layer140, and a barrier layer150. As shown inFIG.4B, a removal process can be performed to remove the potions of the functional layer, the channel layer160, and the filling structure outside of the channel hole190and above the first insulating layer110, and to planarize the top surface of the first insulating layer110and the channel structure. A top view of the channel structure can be referred toFIG.5and the corresponding description above. Referring toFIGS.3and4C, the method proceeds to operation S58, in which a second insulating layer112, a hard mask layer120and a photoresist layer180can be sequentially formed on the first insulating layer110. In some embodiments, the material of the second insulating layer112can be the same material of the first insulating layer110, such as silicon oxide. The second insulating layer112and the first insulating layer110can form a plug insulating layer115. Referring toFIGS.3and4D, the method proceeds to operation S60, in which an opening188can be formed in the hard mask layer120and the photoresist layer180. A position of the opening188can be aligned to match the top surface of the channel structure. In some embodiments, a diameter of the opening188can be slightly larger than the diameter D2of the top surface of the channel structure. In some embodiments, the opening188can be formed by using any suitable patterning process. Referring toFIGS.3and4E, the method proceeds to operation S62, in which a portion of the plug insulating layer115above the channel structure can be removed to form a recess. In some embodiments, fabrication processes to remove the portion of the plug insulating layer115above the channel structure can include an etching process and a cleaning process. By using the hard mask layer120and the photoresist patterning180as the mask, a wet/dry etching process can be performed to remove the portion of the plug insulating layer115above the channel structure. As such, a recess200penetrating the mask layer120, extending into the plug insulating layer115, and exposing the top surface of the channel structure can be formed. As shown inFIG.3, the method proceeds to operation S64, in which a channel hole plug can be formed in the recess (referring back to operation S12 described above in connection withFIGS.2E-2F). Further, the method can include any suitable subsequent processes, such as metal via formation process, additional alternating dielectric stack formation process, gate replacement process (referring back to the description above in connection withFIGS.2G-2H), etc. Since the area of the disclosed channel hole plug can be larger than the area of the channel hole plug made by the traditional method, a larger alignment margin for an interconnection structure (e.g., a metal via, an additional channel layer, etc.) to land on the channel hole plug can be achieved to enhance the product yield. Various embodiments in accordance with the present disclosure provide a channel hole plug structure of 3D memory devices and fabricating methods thereof. In some embodiments of method disclosed herein, the channel hole structure can be formed through a stack of alternating dielectric layers, which can be more easily etched to form channel holes therein compared with a stack of alternating conductor and dielectric layers, thereby reducing the process complexity and manufacturing cost. A channel hole plug can be formed above the channel hole to electrically connect with a channel structure in the channel hole. A projection of the polysilicon plug in a lateral plane can cover the projection of the channel hole in the lateral plane. As such, the polysilicon plug can provide a reliable electrical connection to the channel structure in the channel hole and an increased contact alignment in the subsequent processes. In some embodiments, the present disclosure provides a method for forming a channel hole plug structure in a three-dimensional (3D) memory device. The method can comprise: forming an alternating dielectric stack disposed on a substrate; forming an insulating layer and a hard mask layer on the alternating dielectric stack; forming a channel structure penetrating the insulating layer, the hard mask layer, and the alternating dielectric stack; forming a photoresist patterning on the hard mask layer; using the photoresist patterning as a mask to remove a top portion of the channel structure to form a recess; and forming a channel hole plug in the recess. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane. In some embodiments, forming the alternating dielectric stack comprises forming at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer. In some embodiments, forming the alternating dielectric stack comprises forming at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a silicon oxide layer and a silicon nitride layer. In some embodiments, forming the insulating layer and the hard mask layer comprises: forming an oxide layer on the alternating dielectric stack as the insulating layer; and forming a nitride layer on the oxide layer as the hard mask layer. In some embodiments, forming the channel structure comprises: forming a channel hole extending vertically through the alternating dielectric stack, the insulating layer and the hard mask layer; forming a functional layer on a sidewall of the channel hole; forming a channel layer covering a sidewall of the functional layer; and forming a filling structure to cover a sidewall of the channel layer and filling the channel hole. In some embodiments, forming the functional layer comprises: forming a barrier layer on the sidewall of the channel hole for blocking an outflow of the electronic charge; forming a storage layer on the surface of the barrier layer for storing electronic charges during operation of the 3D memory device; and forming a tunneling layer on the surface of the storage layer for tunneling electronic charges. In some embodiments, forming the photoresist patterning comprises: forming a photoresist layer on the hard mask layer and the channel structure; forming an opening in the photoresist layer to expose the top surface of the channel structure, wherein a diameter of the opening is equal to or larger than a diameter of the top surface of the channel structure; and removing the photoresist layer. In some embodiments, forming the channel hole plug in the recess comprises: forming a semiconductor channel layer on the hard mask layer and in the recess to electrically connect with the channel layer in the channel structure; and removing a portion of the semiconductor channel layer that is outside of the recess, and to planarize a top surface of the channel hole plug. In some embodiments, the method further comprises forming a metal via to electrically connect with the channel hole plug. In some embodiments, the method further comprises: forming a second alternating dielectric stack on the channel hole plug; forming a second channel structure penetrating the second alternating dielectric stack. A second channel layer in the second channel structure is electrically connected with the channel hole plug. In some embodiments, the method further comprises replacing first dielectric layers with conductor layers. Another aspect of the present disclosure provides a method for forming a channel hole plug structure in a three-dimensional (3D) memory device. The method comprises: forming an alternating dielectric stack disposed on a substrate; forming a first insulating layer on the alternating dielectric stack; forming a channel structure penetrating the first insulating layer and the alternating dielectric stack; forming a second insulating layer, a hard mask layer, and a photoresist patterning on the first insulating layer; forming an opening in the hard mask layer and the photoresist layer to expose the second insulating layer, wherein a projection of the opening in a lateral plane covers a top surface of the channel structure; removing a portion of the second insulating layer above the channel structure to form a recess using the hard mask layer or the photoresist layer as a mask; and forming a channel hole plug in the recess. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane. In some embodiments, forming the second insulating layer, the hard mask layer and the photoresist patterning comprises: forming an oxide layer on the first insulating layer and the channel structure as the second insulating layer; forming a nitride layer on the oxide layer as the hard mask layer; and forming a photoresist layer on the nitride layer. In some embodiments, forming the channel hole plug in the recess comprises: forming a semiconductor channel layer on the hard mask layer and in the recess to electrically connect with the channel layer in the channel structure; and removing a portion of the semiconductor channel layer that is outside of the recess, and to planarize a top surface of the channel hole plug Another aspect of the present disclosure provides a three-dimensional (3D) memory device, comprising: an alternating layer stack disposed on a substrate; an insulating layer disposed on the alternating dielectric stack; a channel hole extending vertically through the alternating dielectric stack and the insulating layer; a channel structure including a channel layer in the channel hole; and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane. In some embodiments, the alternating layer stack comprises at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer. In some embodiments, the alternating layer stack comprises at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a silicon oxide layer and a silicon nitride layer. In some embodiments, the alternating dielectric layer comprises at least 32 dielectric/conductor layer pairs stacked in a vertical direction, each dielectric layer pair includes a dielectric layer and a metal layer. In some embodiments, the alternating dielectric layer comprises at least 32 dielectric/conductor layer pairs stacked in a vertical direction, each dielectric layer pair includes a silicon oxide layer and a tungsten layer. In some embodiments, the insulating layer is an oxide layer, and the channel hole plug is a polysilicon layer. In some embodiments, the channel structure comprises a functional layer and a filling structure that sandwich the channel layer. In some embodiments, the functional layer comprises: a barrier layer on the sidewall of the channel hole configured to block an electric outflow tunnel electronic charges; a storage layer on the surface of the barrier layer configured to store electronic charges; and a tunneling layer between the storage layer and the channel layer configured to tunnel electronic charges. In some embodiments, a thickness of the channel hole plug is in a range from 100 nm to 1000 nm, and a minimum diameter of the channel hole plug is 100 nm. In some embodiments, the device further comprises: a second alternating layer stack on the channel hole plug; and a second channel structure penetrating the second alternating layer stack. A second channel layer in the second channel structure is electrically connected with the channel hole plug. In some embodiments, the device further comprises a metal via electrically connected with the channel hole plug. The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. | 40,657 |
11943929 | DETAILED DESCRIPTION OF THE INVENTION Embodiments will be described below with reference to the accompanying drawings. Note that the embodiments can be implemented with various modes, and it will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments. In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, the scale is not necessarily limited to that illustrated in the drawings. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof will not be repeated. Furthermore, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases. Note that the ordinal numbers such as “first”, “second”, and the like in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made even when “first” is replaced with “second” or “third”, as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those which specify one embodiment of the present invention. In this specification, terms for describing arrangement (e.g., over, above, under, and below) are used for convenience in describing a positional relation between components with reference to drawings. Furthermore, the positional relationship between components is changed as appropriate in accordance with a direction in which each component is described. Thus, the positional relation is not limited to that described with a term used in this specification and can be explained with another term as appropriate depending on the situation. Note that in this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of the “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring. Note that in this specification and the like, a nitride oxide refers to a compound that includes more nitrogen than oxygen. An oxynitride refers to a compound that includes more oxygen than nitrogen. The content of each element can be measured by Rutherford backscattering spectrometry (RBS), for example. In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases. In this specification and the like, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. In addition, the term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 800 and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 850 and less than or equal to 95°. In addition, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°. In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. Note that in this specification, a barrier film refers to a film having a function of inhibiting the penetration of oxygen and impurities such as hydrogen. The barrier film that has conductivity may be referred to as a conductive barrier film. In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, a metal oxide used in an active layer of a transistor is called an oxide semiconductor in some cases. In other words, an OS FET is a transistor including a metal oxide or an oxide semiconductor. Note that in this specification and the like, “In:Ga:Zn=4:2:3 or a neighborhood of In:Ga:Zn=4:2:3” refers to an atomic ratio where, when In is 4 with respect to the total number of atoms, Ga is greater than or equal to 1 and less than or equal to 3 (1≤Ga≤3) and Zn is greater than or equal to 2 and less than or equal to 4.1 (2≤Zn≤4.1). “In:Ga:Zn=5:1:6 or a neighborhood of In:Ga:Zn=5:1:6” refers to an atomic ratio where, when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and less than or equal to 2 (0.1<Ga≤2) and Zn is greater than or equal to 5 and less than or equal to 7 (5≤Zn≤7). “In:Ga:Zn=1:1:1 or a neighborhood of In:Ga:Zn=1:1:1” refers to an atomic ratio where, when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and less than or equal to 2 (0.1<Ga≤2) and Zn is greater than 0.1 and less than or equal to 2 (0.1<Zn≤2). Embodiment 1 In this embodiment, a structure, a manufacturing method, a circuit configuration, and an operation of a semiconductor device of one embodiment of the disclosed invention will be described with reference toFIG.1toFIGS.36A to36C. (Memory Transistor MT, Memory Cell Array700) First, structures of a memory transistor MT and a memory cell array700of the semiconductor device are described with reference toFIG.1toFIGS.3A and3B.FIG.1is a cross-sectional view of a memory cell array700.FIG.2Ais a top view of the memory cell array700. Note thatFIG.2Ais a top view taken along dashed-dotted line A5-A6inFIG.1and some components are not illustrated.FIG.1is a cross-sectional view taken along dashed-dotted line A1-A2inFIG.2A.FIG.2Bis a cross-sectional view taken along dashed-dotted line A3-A4inFIG.2A, which illustrates an example of a memory string.FIG.3Ais an enlarged cross-sectional view of a portion surrounded by dashed-dotted line791inFIG.1, which illustrates an example of a memory transistor MT functioning as a memory cell.FIG.3Bis an enlarged cross-sectional view of a portion surrounded by dashed-dotted line792inFIG.1, which illustrates an example of a transistor functioning as a selection transistor. Note that in the following description, rectangular coordinates using an x-axis, a y-axis, and a z-axis are set as illustrated inFIG.1andFIGS.2A and2Bfor the sake of convenience. Here, the x-axis and the y-axis are parallel to the top surface of a base720provided with the memory cell array700and the z-axis is perpendicular to the top surface of the base720. The memory cell array700includes: an insulator721over the base720; a stack in which a conductor701(conductors701_1to701_m(m is a natural number of 2 or more)) and an insulator722(insulators722_1to722_m) are alternately stacked over the insulator721; a conductor702over the stack; an insulator724over the conductor702and the stack; an insulator703(insulators703_1to703_4) in an opening portion formed through the insulator724, the conductor702, the stack, and the insulator721; an oxide704(oxides704_1to704_4) on the inner side of the insulator703; a layer716that contains at least one of a metal element, hydrogen, and nitrogen and is provided between the insulator703and the oxide704to be in contact with part of the oxide704; an insulator711(insulators711_1to711_4) on the inner side of the oxide704; a conductor712(conductors712_1to712_4) on the inner side of the insulator711; a conductor705(conductors705_1to705_4) electrically connected to upper end portions of the oxides704_1to704_4; a conductor706(conductors706_1to706_4) electrically connected to lower end portions of the oxides704_1to704_4; an insulator717and an insulator713over the insulator724and the conductor705; a conductor714and a conductor715electrically connected to each of the conductors712_1to7124; a conductor707(conductors707_1to707_m) electrically connected to the conductors701_1to701_m; and a conductor708(conductors708_1to708_m) electrically connected to the conductors707_1to707_m. Note that inFIG.1andFIGS.2A and2B, four or more stages of the conductors701are illustrated to show a plurality of conductors701; however, this embodiment is not limited toFIG.1and at least two stages of the conductors701are provided. As illustrated inFIG.1andFIG.2A, the conductor701extends in the x-axis direction. As illustrated inFIG.1andFIG.2B, the insulator703and the oxide704extend in the z-axis direction. That is, the conductor701and the insulator703and oxide704are preferably provided to cross each other perpendicularly. Furthermore, as illustrated inFIG.1, the conductor707extends in the z-axis direction. The conductor708may extend in the y-axis direction. In addition, a conductor functioning as a bit line BL connected to the conductor705may extend in the y-axis direction. Part of the conductor705may function as the bit line BL and the conductor705may extend in the y-axis direction. The conductor712is formed in a columnar shape and extends in the z-axis direction. In addition, the insulator711is provided to surround the conductor712and the oxide704is provided to surround the insulator711, each of which extends in the z-axis direction. In other words, the conductor712is provided as a core on the inner side of the columnar oxide704that extends in the z-axis direction, and the insulator711is provided between the oxide704and the conductor712. The insulator703is provided to surround the periphery of the side of the columnar oxide704. The conductor707is formed in a columnar shape and extends in the z-axis direction. The diameter of an opening formed in the insulator721, the insulator722, and the insulator724is larger than the diameter of an opening formed in the conductor701and the conductor702. The layer716is provided on the side surfaces of the insulators721,722, and724with the insulator703provided therebetween. The layer716is in contact with part of the oxide704, whereby the resistance of the contact region is reduced and a low-resistance region is formed. When the oxide704has a low-resistance region, in the memory string or memory cell array where the memory cells are stacked, the series resistance between the memory cells can be reduced. The columnar oxide704is electrically connected to the conductor706at the lower end in the z-axis direction and electrically connected to the conductor705at the upper end. As illustrated inFIG.2B, the conductor706is electrically connected to the lower ends of two adjacent columnar oxides704, and the upper ends of the two adjacent columnar oxides704are electrically connected to the electrically separated conductors705. In this embodiment, the U-shaped memory string in which the two columnar oxides704are electrically connected to each other through the conductor706is described; however, the present invention is not limited thereto. For example, the conductor706may serve as one of a bit line BL and a source line SL and the conductor705may serve as the other of the bit line BL and the source line SL. In this case, the conductor706may be electrically connected to a plurality of columnar oxide704or one columnar oxide704. Furthermore, the conductor705may be electrically connected to a plurality of columnar oxide704or one columnar oxide704. In the case where the lower end of the columnar oxide704is electrically connected to one of the bit line BL and the source line SL and the upper end thereof is electrically connected to the other, a selection transistor is preferably provided at around the lower end and upper end of the columnar oxide704. For example, in the case where the conductor706serves as part of the bit line BL and the conductor705serves as part of the source line SL, a selection transistor SST is provided between the conductor706and the memory transistor MT and a selection transistor SDT is provided between the conductor705and the memory transistor MT. Here, a region where the conductor701crosses the insulator703and the oxide704and the vicinity of the region serve as the memory transistor MT. In addition, a region where the conductor702crosses the insulator703and the oxide704and the vicinity of the region serve as the selection transistor. The channel length direction of each of the memory transistor MT and the selection transistor is parallel to the z-axis direction. The memory transistor MT and the selection transistor are electrically connected in series to form the memory string. FIG.3Ais an enlarged cross-sectional view of a portion surrounded by dashed-dotted line791inFIG.1, which illustrates a cross section of the memory transistor MT in a k-th stage (k is an integer greater than or equal to 2 and less than or equal to m−1). The memory transistor MT includes the conductor701_k, the insulator703(the insulators703a,703b, and703c), and the oxide704(the oxides704a,704b, and704c). In addition, the conductor712and the insulator711may be included. The conductor701_kserves as a gate of the memory transistor MT, the insulator703aserves as a gate insulating layer, the insulator703bserves as a charge accumulation layer, and the insulator703cserves as a tunnel insulating layer. Although the details are described later, the oxide704includes the oxide704a, the oxide704b, and the oxide704c, and the oxide704ahas an energy gap relatively wider than that of the oxide704b, and the oxide704chas an energy gap relatively wider than that of the oxide704b. In other words, the oxide704bhas an energy gap relatively narrower than those of the oxides704aand704c. In the oxide704, a region734that is positioned in the same layer as the conductor701_kserves as a channel formation region. Furthermore, in the oxide704, a region731(regions731aand731b) in contact with the layer716containing at least one of a metal element, hydrogen, and nitrogen serves as a low-resistance region. A region732(regions732aand732b) positioned between the region734and the region731serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region732may serve as a channel formation region like the region734or serve as a low-resistance region like the region731. The memory transistor MT in the k-th stage and the memory transistor MT in the k−1-th stage or the transistor MT in the k+1-th stage share the low-resistance region. The oxide704has a structure where the channel formation regions and the low-resistance regions are alternately stacked. When the oxide704has the low-resistance region, the series resistance between the memory cells can be reduced in the memory string where the memory cells are stacked or in the memory cell array. In the case where the conductor712is provided, the conductor701_kserves as a first gate and the conductor712serves as a second gate. Note that the first gate is referred to as a control gate or simply a gate, and the second gate is referred to as a back gate in some cases. The insulator711is provided between the oxide704and the conductor712and serves as a second gate insulating layer. At this time, the insulator703aserves as a first gate insulating layer. In the circuit operation of the memory transistor MT, the potential of the conductor712which serves as the second gate is controlled, whereby power consumption of the memory transistor MT can be reduced. FIG.3Bis an enlarged cross-sectional view of a portion surrounded by dashed-dotted line792inFIG.1, which illustrates a cross section of the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)). The selection transistor includes the conductor702, the insulator703(the insulators703a,703b, and703c), and the oxide704(the oxides704a,704b, and704c). In addition, the conductor712and the insulator711may be included. The conductor702serves as a gate of the selection transistor and the insulator703aserves as a gate insulating layer. As the gate insulating layer, at least the insulator703ais provided, and the insulator703band the insulator703care not necessarily provided. Alternatively, after the insulators703a,703b, and703care provided, the insulators703band703cmay be partly removed. The oxide704includes the oxide704a, the oxide704b, and the oxide704c, and the oxide704ahas an energy gap relatively wider than that of the oxide704b, and the oxide704chas an energy gap relatively wider than that of the oxide704b. In other words, the oxide704bhas an energy gap relatively narrower than those of the oxides704aand704c. In the oxide704, a region734that is positioned in the same layer as the conductor702serves as a channel formation region. Furthermore, in the oxide704, a region731(regions731aand731b) in contact with the layer716containing at least one of a metal element, hydrogen, and nitrogen serves as a low-resistance region. A region732(regions732aand732b) positioned between the region734and the region731serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region732may serve as a channel formation region like the region734or serve as a low-resistance region like the region731. In the case where the conductor712is provided, the conductor702serves as a first gate and the conductor712serves as a second gate. Note that the first gate is referred to as a top gate or simply a gate, and the second gate is referred to as a back gate in some cases. The insulator711is provided between the oxide704and the conductor712and serves as a second gate insulating layer. At this time, the insulator703aserves as a first gate insulating layer. With the conductor712which serves as the second gate, the threshold voltage of the selection transistor can be controlled. Note that the structure of the semiconductor device in this embodiment is an example, and the present invention is not limited to the number, the position, and the like of the circuit element, the wiring, and the like illustrated in the drawings and the like according to this embodiment. The number, the position, and the like of the circuit element, the wiring, and the like included in the semiconductor device in this embodiment can be set as appropriate in accordance with the circuit configuration and the driving method. The base720provided with the memory cell array700preferably has an insulating surface. As a substrate having an insulating surface, a semiconductor substrate provided with an insulator on its surface, an insulator substrate, a conductor substrate provided with an insulator on its surface, or the like is used. As the semiconductor substrate, a semiconductor substrate formed using silicon, germanium, or the like or a semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), a resin substrate, or the like is used. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate, is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. The conductor701serves as the gate of the memory transistor MT and is electrically connected to a word line. That is, the conductors701,707, and708also serve as part of the word line. Here, as illustrated inFIG.1, the conductor701is preferably provided in a step-like shape where the conductor701in the lower layer extends to be closer to the A2side than the conductor701in the upper layer does. The conductor701is provided in this manner, so that the conductor701in the upper layer does not overlap with a region of part of the top surface of the conductor701in the lower layer; thus, the regions in the conductors701can be connected to the respective conductors707. For the conductor701, a conductive material such as silicon or metal can be used. When silicon is used, amorphous silicon or polysilicon can be used. Furthermore, a p-type impurity or an n-type impurity may be added to form conductive silicon. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used for the conductor701. In the case where a metal material is used for the conductor701, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. The conductor702is provided over the conductor701. The conductor702serves as the gate of the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)) and is electrically connected to a wiring DGL and a wiring SGL. That is, the conductor702also serves as part of the wirings DGL and SGL. The conductor702can be formed using the material similar to that for the conductor701. The conductor702may be formed using the same material as the conductor701or a different material from that of the conductor701. The materials of the conductor701and the conductor702are determined depending on the usage in consideration of their work functions and the like. Insulating films provided over and under the conductors701and702can be formed using an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like which has an insulating property. For the insulating film, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like, which has a low relative permittivity, is preferably used. Although aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, or the like can be used for the insulating film, these materials have a high relative permittivity; thus, parasitic capacitance may be generated between the conductors701or between the conductor701and the conductor702. The material used for the insulating film can be determined depending on the design of the device or the usage. The insulator703includes the insulator703a, the insulator703b, and the insulator703c. The insulator703ais provided on the conductor701side, the insulator703cis provided on the oxide704side, and the insulator703bis provided between the insulator703aand the insulator703c. The insulator703aserves as a gate insulating layer, the insulator703bserves as a charge accumulation layer, and the insulator703cserves as a tunnel insulating layer. Note that the selection transistor may have the same structure as the memory transistor MT. However, as illustrated inFIG.3B, the selection transistor does not necessarily include the charge accumulation layer or the tunnel insulating layer. The transistor on the bit line side (SDT) and the transistor on the source line side (SST) may each have a structure where the insulators703band703care removed and only the insulator703ais provided as the insulator703. InFIG.3B, the oxide704has a three-layer structure of the oxides704a,704b, and704c; however, the present invention is not limited thereto. The oxide704may have a two-layer structure of the oxides704aand704bor a stacked-layer structure of four or more layers. As the second gate electrode, the conductor712may be provided. In this case, the conductor702serves as the first gate electrode, the insulator703aserves as the first gate insulating film, and the insulator711serves as the second gate insulating film. With the conductor712, the threshold voltage of the selection transistor can be controlled. For the insulator703a, silicon oxide or silicon oxynitride is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, a stack of any of these materials may be used for the insulator703a. The insulator703bis preferably formed using a material that serves as a charge accumulation layer and is preferably formed using silicon nitride or silicon nitride oxide. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. For the insulator703c, silicon oxide or silicon oxynitride is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, a stack of any of these materials may be used for the insulator703c. Furthermore, the insulator703cis preferably thinner than the insulator703a. Although details are described later, in writing or erasing data to/from the memory transistor MT, charge is transferred between the oxide704and the insulator703bthrough the insulator703c. That is, the insulator703cserves as a tunnel insulating layer. In particular, in the case where the insulator703is formed in the opening provided in the stack including the conductor701, the conductor702, and the insulating films, the insulator703formed on the bottom portion of the opening needs to be removed by anisotropic etching using dry etching or the like. In anisotropic etching, the side surface of the insulator703cis also exposed to plasma, a radical, a gas, a chemical solution, or the like. When the side surface of the insulator703cis damaged in this manner, trap centers might be formed in the insulator703cand might affect electrical characteristics of the transistor. To suppress the formation of the trap centers, the side surface of the insulator703cis required to have high resistance to damage due to etching. In this case, for the insulator703c, aluminum oxide, a stack of silicon oxide and aluminum oxide, or a stack of silicon oxynitride and aluminum oxide is preferably used. The insulators703a,703b, and703ccan be formed by an atomic layer deposition (ALD) method or a chemical vapor deposition (CVD) method. To prevent contamination of the interfaces between the insulator703a, the insulator703b, and the insulator703c, these insulators are preferably formed in succession without exposure to an air atmosphere in the same chamber or with a multi-chamber deposition apparatus including a plurality of chambers. The oxide704is preferably formed using a metal oxide functioning as an oxide semiconductor (hereinafter, the metal oxide is also referred to as an oxide semiconductor). The oxide semiconductor is preferably used, in which case a transistor including the oxide semiconductor can have more favorable on-state characteristics and higher mobility than a transistor including a semiconductor made of silicon, for example. For example, as the oxide704, a metal oxide such as an In-M-Zn oxide (M is one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is used. An In—Ga oxide or an In—Zn oxide may be used as the oxide704. The oxide704preferably includes the oxide704aprovided on the insulator703cside, the oxide704bprovided on the inner side of the oxide704a, and the oxide704cprovided on the inner side of the oxide704b. At this time, as the oxide704a, an oxide having an energy gap relatively wider than that of the oxide704bis preferably used. As the oxide704c, an oxide having an energy gap relatively wider than that of the oxide704bis preferably used. Here, an oxide having a wide energy gap is referred to as a wide gap and an oxide having a narrow energy gap is referred to as a narrow gap in some cases. In the case where the oxides704aand704care each a wide gap and the oxide704bis a narrow gap, an energy of the conduction band minimum of each of the oxides704aand704cis preferably higher than that of the conduction band minimum of the oxide704b. In other words, the electron affinity of each of the oxides704aand704cis preferably smaller than the electron affinity of the oxide704b. The oxides704a,704b, and704cpreferably have different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M to constituent elements in the metal oxide used as the oxides704aand704cis preferably greater than that in the metal oxide used as the oxide704b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxides704aand704cis preferably greater than that in the metal oxide used as the oxide704b. Moreover, the atomic ratio of the element In to the element M in the metal oxide used as the oxide704bis preferably greater than that in the metal oxide used as the oxides704aand704c. As the oxides704aand704c, for example, a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition which is in the neighborhood of any of the above atomic ratios can be used. As the oxide704b, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4:2:4.1, In:Ga:Zn=1:1:1, or In:Ga:Zn=5:1:6, or a composition which is in the neighborhood of any of the above atomic ratios can be used. The oxides704a,704b, and704care preferably formed to satisfy the above atomic ratio. For example, it is preferable that the oxides704aand704cbe each a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition which is in the neighborhood of the above atomic ratio and the oxide704bbe each a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4:2:4.1 or a composition which is in the neighborhood of the above atomic ratios. Note that the above composition shows the atomic ratio in an oxide formed over a base or the atomic ratio in a sputtering target. In addition, it is preferable that a CAAC-OS described later be used as the oxides704aand704cand a CAC-OS described later be used as the oxide704b. In the case where the CAAC-OS is used as the oxides704aand704c, the c-axes are preferably aligned parallel to x-y plane shown inFIG.1,FIGS.2A and2B, and the like, that is, perpendicular to the z-axis, and preferably aligned from the side surface of the opening to the central portion. Here, in a junction portion of the oxides704aand704band a junction portion of the oxides704cand704b, the conduction band minimum is gradually varied. In other words, the conduction band minimum in the junction portion of the oxides704aand704band the junction portion of the oxides704cand704bis continuously varied or continuously connected. To vary the conduction band minimum gradually, the density of defect states in a mixed layer formed at the interface between the oxides704aand704band the interface between the oxides704cand704bis decreased. Specifically, when the oxides704a,704b, and704ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide704bis an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as each of the oxides704aand704c. Accordingly, the density of defect states at the interface between the oxides704aand704band the interface between the oxides704cand704bcan be decreased. Thus, the influence of interface scattering on carrier conduction is small, and the memory transistor MT can have a high on-state current. Note that the details of the metal oxide that can be used as the oxide704are described later. FIG.3Ais the enlarged view of the memory transistor MT surrounded by dashed-dotted line791inFIG.1. As illustrated inFIG.3A, the oxide704bis sandwiched between the oxides704aand704c. In such a structure, carriers mainly flow in the component having a narrow gap when the carriers flow in the oxide704from the conductor705toward the conductor706or from the conductor706toward the conductor705. Thus, with the above structure, the oxide704bwhich is a narrow gap is sandwiched between the oxides704aand704cwhich are wide gaps, whereby carriers flowing through the oxide704can be confined in the oxide704b. This enables high current drive capability in the on state of the transistor, i.e., high on-state current and high field-effect mobility. The oxide704ais provided between the oxide704band the insulator703c, whereby the oxide704bthat serves as a carrier path and the insulator703care not in contact with each other, so that the formation of trap centers can be suppressed. The trap centers formed at the interface between the semiconductor (oxide semiconductor) and the insulator trap electrons and cause the threshold voltage of the transistor to shift in the positive direction, which might adversely affect the reliability and the on-off characteristics of the transistor. Thus, a transistor using the oxide does not affect electrical characteristics due to the trap centers. This enables higher current drive capability in the on state of the transistor, i.e., higher on-state current and higher field-effect mobility. Furthermore, the transistor and a semiconductor device including the transistor can have high reliability. To provide the low-resistance regions in the oxide704, the layer716containing at least one of a metal element, hydrogen, and nitrogen is preferably provided in contact with part of the oxide704. The layer716is provided on the side surfaces of the insulators721,722, and724with the insulator703provided therebetween. Although the details are described later, the diameter of the opening formed in the insulators721,722, and724is larger than the diameter of the opening formed in the conductors701and702, and the layer716is provided only in the same layers as the insulators721,722, and724. Thus, the oxide704includes a region in contact with the insulator703and a region in contact with the layer716. The layer716preferably has at least one of a function of supplying hydrogen to the oxide704, a function of supplying nitrogen to the oxide704, and a function of extracting oxygen from the oxide704. The layer716having such a function is in contact with the oxide704, whereby carriers are generated in the oxide704. Specifically, oxygen is extracted from the oxide704, whereby oxygen vacancies are generated in the oxide704. When hydrogen is trapped by these oxygen vacancies, carriers are generated. Alternatively, in the case where nitrogen is trapped by these oxygen vacancies, nitrogen is substituted for oxygen bonded to two indium atoms. When nitrogen is bonded to these two indium atoms, it is probable that nitrogen has an unpaired electron and serves as a carrier. As the material having a function of supplying hydrogen to the oxide704, silicon nitride containing hydrogen can be used. Furthermore, a material formed using a gas containing hydrogen when the material is formed can be used. For example, silicon, silicon oxide, silicon oxynitride, silicon nitride oxide, or the like formed using monosilane, disilane, ammonia, or the like can be used. As the material having a function of supplying nitrogen to the oxide704, a nitride containing silicon or a metal element can be used. As such a material, silicon nitride, silicon nitride oxide, silicon oxynitride, or the like can be used. Alternatively, a nitride containing one or more of aluminum, tantalum, and titanium can be used. Specifically, aluminum nitride, tantalum nitride, titanium nitride, a nitride containing aluminum and tantalum, a nitride containing aluminum and titanium, or the like can be used. After the layer716containing any one of a metal element, hydrogen, and nitrogen is provided in contact with the oxide704, heat treatment is preferably performed. The heat treatment is performed, whereby extraction of oxygen, supply of hydrogen, or supply of nitrogen is promoted, and the resistance of part of the oxide704can be efficiently reduced. In this manner, by providing the low-resistance region in the oxide704, the series resistance between the memory cells can be reduced in the memory string where the memory cells are stacked or in the memory cell array. In the case where the conductor712is provided, a material similar to that of the conductor701can be used for the conductor712. Since the conductor712needs to be formed in the opening having a large aspect ratio (in other words, the recession of the oxide704and the insulator711), the conductor712is preferably formed by a CVD method, an ALD method, or a plating method. In that case, the insulator711can be formed using a material similar to that used for the insulator703. In the case where the insulator711is provided on the inner side of the oxide704c, the insulator711is preferably formed using a material that can supply oxygen to the oxide704or a material that can supply impurities, such as hydrogen and nitrogen. When an oxide that contains hydrogen and nitrogen as little as possible is used for the insulator711, oxygen can be supplied to the oxide704in some cases. By supplying oxygen to the oxide704, impurities such as hydrogen and water contained in the oxide704can be removed and the oxide704is highly purified. When an oxide which contains impurities as little as possible is used as the oxide704, the memory transistor MT and the semiconductor device including the memory transistor MT can have high reliability. When an oxide containing hydrogen and nitrogen is used for the insulator711, hydrogen and nitrogen can be supplied to the oxide704in some cases. When hydrogen and nitrogen are supplied to the oxide704, the resistance of the oxide704might be decreased. The resistance of the oxide704is decreased such that it does not hinder the circuit operation, whereby the memory transistor MT can operate with lower driving voltage. This enables high current drive capability in the on state of the memory transistor MT, i.e., high on-state current and high field-effect mobility. Note that the top-view shape of the opening formed in the stack provided with the memory transistor MT is, but not limited to, circular as illustrated inFIG.2Aand the like; the top-view shape can alternatively be, for example, elliptic or polygonal, e.g., a triangle or a quadrangle. In the case where a polygonal shape is employed, corners thereof may be rounded. The top-view shapes of the insulator703and the oxide704may change depending on the top-view shape of the opening. The opening may have a shape where a lower cross section (on the conductor706side) is smaller than an upper cross section (on the conductor705side). The memory transistor MT is formed by the oxide704, the insulator703, and the conductor701(any one of the conductors701_1to701_m).FIG.1andFIGS.2A and2Bshow an example in which m stages of memory transistors MT (m is a natural number of 2 or more) are stacked. Note that inFIG.1andFIGS.2A and2B, four or more stages of the conductors701are illustrated to show a plurality of conductors701; however, this embodiment is not limited toFIG.1and at least two stages of the conductors701are provided. The conductor705is electrically connected to the oxide704and serves as part of the source line SL or part of the bit line BL. The conductor705is preferably formed using a conductive material containing a metal element. Alternatively, a conductive material among materials that can be used for the layer716can be used for the conductor705. In that case, the resistance of part of the oxide704is reduced as described above. A metal compound layer including the metal element contained in the conductor705and the component of the oxide704is preferably formed at the interface between the conductor705and the oxide704. The metal compound layer is preferably formed, in which case the contact resistance between the conductor705and the oxide704can be reduced. Alternatively, oxygen contained in the oxide704is absorbed by the conductor705and the resistance of the oxide704in the vicinity of the interface between the conductor705and the oxide704is reduced, whereby the contact resistance between the conductor705and the oxide704can be reduced. It is preferable that the conductor705be formed using a conductive material containing one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, chromium, tungsten, and copper. As illustrated inFIG.2B, the conductor706electrically connects the oxide704electrically connected to the conductor705which serves as part of the bit line BL to the oxide704electrically connected to the conductor705serving as part of the source line SL, so that the memory string is formed. A region surrounded by a dotted line inFIG.2Arepresents a memory string. In other words,FIG.2Aillustrates a memory cell array700including four memory strings. The conductor706can be formed using a material similar to that used for the conductor705. Alternatively, a conductive material among materials that can be used for the layer716can be used for the conductor706. In that case, the resistance of part of the oxide704is reduced as described above. The conductor706can be formed using the same material as the conductor705or a different material from that of the conductor705. A metal compound layer including the metal element contained in the conductor706and the component of the oxide704is preferably formed at the interface between the conductor706and the oxide704. The metal compound layer is preferably formed, in which case the contact resistance between the conductor706and the oxide704can be reduced. Alternatively, oxygen contained in the oxide704is absorbed by the conductor706and the resistance of the oxide704in the vicinity of the interface between the conductor706and the oxide704is reduced, whereby the contact resistance between the conductor706and the oxide704can be reduced. (Memory Cell Array700A) FIG.4is a top view illustrating a memory cell array700A in which a plurality of memory cell arrays700each including six stages of memory transistors MT are combined. Note that inFIG.4, some components are not illustrated for simplicity. For example, the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)) provided over the conductor701and the conductor702which is the component of the selection transistor are not illustrated. In addition, the conductor705serving as part of the bit line BL and the source line SL, the conductor708serving as part of the word line WL, and the conductor715serving as part of the wiring BG electrically connected to the conductor712serving as a second gate are shown by solid lines. In the memory cell array700A, each memory cell array700includes four memory strings including six stages of memory transistors MT. The ends of the memory strings on the bit line side are electrically connected to the respective bit lines BL (BL_1to BL_4). The ends of the memory strings on the source line side are electrically connected to the source line SL and are supplied with a common potential. The source line SL may be grounded or may be supplied with a constant potential. Alternatively, the potential may be changed depending on the operation of the circuit. The conductors701_1to701_6are electrically connected to the respective word lines WL. The conductors701_1to701_6on the bit line side are electrically connected to WLa_1to WLa_6, respectively, and the conductors701_1to701_6on the source line side are electrically connected to WLb_1to WLb_6, respectively. The conductors712are electrically connected to the wirings BG. AlthoughFIG.4shows an example where the conductors712aligned in the column direction are electrically connected to the common wiring BG, the present invention is not limited to this example. The conductors712aligned in the row direction may be electrically connected to the common wiring BG. Different potentials may be applied to the wirings BG. Alternatively, the same potential may be applied to the plurality of wirings BG. In this case, the plurality of wirings BG are preferably electrically connected to each other. The plurality of wirings BG may refer to all the wirings BG included in the memory cell array700A. In order that a given potential is applied to the wiring BG, the wiring BG is preferably electrically connected to a circuit that controls the potential of the wiring BG (also referred to as a BG driver or a BG driver circuit, or simply referred to as a driver or a driver circuit). The BG driver circuit may be provided for each of the wirings BG or the plurality of wirings BG may be electrically connected to one BG driver circuit. For example, the memory cell array700A may include one BG driver circuit and all the wirings BG included in the memory cell array700A may be electrically connected to the BG driver circuit. By appropriately selecting the bit line BL (from BL_1to BL_4) and the word line WL (from WLa_1to WLa_6and WLb_1to WLb_6), a given memory transistor MT in the memory cell array700can be selected. In addition, writing, reading, erasing, and the like can be performed on the selected memory transistor MT. Since the selection transistor (not illustrated) is provided in each memory string, the given memory cell array700in the memory cell array700A can be selected, and writing, reading, erasing, and the like can be performed on the given memory transistor MT in the selected memory cell array700. (Structure Example of Memory Device750) FIG.5illustrates a structure example of a memory device750in which the memory cell array700A is stacked over a circuit300. As illustrated inFIG.5, the memory cell array700A is stacked over a region where the circuit300including a transistor301, a transistor302, and a transistor303is formed. The transistor301and the transistor302are included in a sense amplifier304and the transistor303functions as a column selection switch. Specifically, the bit line BL of the memory cell array700A is electrically connected to one of a source and a drain of the transistor301, a gate of the transistor301is electrically connected to one of a source and a drain of the transistor302, and a gate of the transistor302is electrically connected to the other of the source and the drain of the transistor301. The one of the source and the drain of the transistor301and the other of the source and the drain of the transistor302are electrically connected to one of a source and a drain of the transistor303which functions as the column selection switch. Accordingly, the layout area of the memory device750can be reduced. Note thatFIG.5illustrates an example where 10 stages of memory transistors MT are provided and one memory string includes 20 memory transistors MT. However, the number of stages of stacked memory transistors MT is not limited thereto. For example, 32 stages of memory transistors, 64 stages of memory transistors, 128 stages of memory transistors, or 200 or more stages of memory transistors may be stacked. The bit line BL of the memory cell array700A is electrically connected to the sense amplifier304and the transistor303functioning as the column selection switch through the conductor752formed to be embedded in an insulator726, the insulator722, and the like. Note that circuits and transistors included in the circuit300are examples and the circuit configurations and the transistor structures are not limited to these examples. In addition to the above, an appropriate circuit or transistor can be provided in accordance with the component of the memory device750such as a control circuit, a row decoder, a row driver, a source line driver, or an input-output circuit, or the driving method thereof. The transistors301,302, and303are provided over a substrate311and each include a conductor316, an insulator315, a semiconductor region313that is a part of the substrate311, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. Note that as illustrated inFIG.5, one low-resistance region may be used in common for a source region or a drain region of one of the transistors301and302and a source region or a drain region of the other of the transistors301and302. In each of the transistors301,302, and303, the semiconductor region313(part of the substrate311) in which a channel is formed has a protruding portion. Furthermore, the conductor316is provided so as to cover the top and side surfaces of the semiconductor region313with the insulator315positioned therebetween. Note that the conductor316may be formed using a material for adjusting the work function. The transistors301,302, and303are also referred to as FIN transistors because they each utilize a protruding portion of the semiconductor substrate. An insulator functioning as a mask for forming the protruding portion may be provided in contact with the top surface of the protruding portion. Although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate. Although each of the transistors301,302, and303may be either a p-channel transistor or an n-channel transistor, the transistors301and302are preferably transistors having different polarities. It is preferable that a region of the semiconductor region313where a channel is formed, a region in the vicinity thereof, the low-resistance regions314aand314bfunctioning as the source and drain regions, and the like contain a semiconductor such as a silicon-based semiconductor, further preferably single crystal silicon. Alternatively, a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be contained. Silicon whose effective mass is adjusted by applying stress to the crystal lattice and thereby changing the lattice spacing may be contained. Alternatively, the transistors301,302, and303may each be a high-electron-mobility transistor (HEMT) with GaAs and GaAlAs, or the like. The low-resistance regions314aand314bcontain an element which imparts n-type conductivity, such as arsenic or phosphorus, or an element which imparts p-type conductivity, such as boron, in addition to the semiconductor material used for the semiconductor region313. The insulator315serves as a gate insulating film of each of the transistors301,302, and303. The conductor316functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or using a conductive material such as a metal material, an alloy material, or a metal oxide material. Note that since the work function of a conductor depends on a material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like for the conductor. Furthermore, in order to ensure the conductivity and embeddability, it is preferable to use a stacked layer of metal materials such as tungsten and aluminum for the conductor. It is particularly preferable to use tungsten in terms of heat resistance. An insulator317functioning as an etching stopper is preferably provided over the conductor316. In addition, an insulator318functioning as a spacer is preferably provided on the side surface of the insulator315. When the insulator317and the insulator318are provided, regions where the low-resistance regions314aand314band a conductor328are electrically connected to each other can be defined in a self-aligned manner. Thus, even when misalignment occurs in forming the openings for exposing part of the low-resistance regions314aand314b, the openings for exposing the intended regions can be formed. The conductor328provided in the openings formed in this manner can provide a favorable contact with reduced contact resistance between the low-resistance regions314aand314band the conductor328. The contact between the low-resistance regions314aand314bformed in this manner and the conductor328may be referred to as a self-aligned contact. Furthermore, a conductor329electrically connected to the conductor316so as to be embedded in the insulator317and an insulator322may be provided. An insulator320, an insulator322, an insulator324, an insulator326, and an insulator327are stacked in this order to cover the transistor301, the transistor302, and the transistor303. The insulator320, the insulator322, the insulator324, the insulator326, and the insulator327can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride. The insulator322may function as a planarization film for eliminating a level difference caused by the transistor301or the like underlying the insulator322. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity. The insulator324is preferably formed using a film having a barrier property that prevents hydrogen or impurities from the substrate311, the transistor301, or the like from diffusing to a region where the memory cell array700A is provided. For the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used, for example. The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the memory transistor MT, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the memory transistor MT and the transistor301or the like. The film that prevents hydrogen diffusion is specifically a film from which a small amount of hydrogen is released. The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator324that is converted into hydrogen atoms per unit area of the insulator324is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2, in the TDS analysis at a film surface temperature of the insulator324of higher than or equal to 50° C. and lower than or equal to 500° C., for example. Note that the permittivities of the insulators326and327are preferably lower than that of the insulator324. For example, the relative permittivities of the insulators326and327are preferably lower than 4, further preferably lower than 3. The relative permittivities of the insulators326and327are, for example, preferably 0.7 or less times that of the insulator324, further preferably 0.6 or less times that of the insulator324. In the case where a material with a low permittivity is used for an interlayer film, the parasitic capacitance between wirings can be reduced. The conductor328, the conductor329, a conductor330, and the like that are electrically connected to the memory cell array700A are provided in the insulator320, the insulator322, the insulator324, the insulator326, and the insulator327. Note that the conductors328,329, and330each function as a plug or a wiring. A plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and another part of the conductor functions as a plug. As a material for each of plugs and wirings (e.g., the conductors328,329, and330), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance. A wiring layer may be provided over the insulator327and the conductor330. For example, inFIG.5, an insulator350, an insulator352, and an insulator354are stacked sequentially. Furthermore, a conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring. Note that the conductor356can be formed using a material similar to those for the conductors328,329, and330. Note that the insulator350is preferably formed using an insulator having a barrier property against hydrogen, as with the insulator324, for example. Furthermore, the conductor356preferably contains a conductor having a barrier property against hydrogen. In particular, the conductor having a barrier property against hydrogen is formed in an opening of the insulator350having a barrier property against hydrogen. In such a structure, the transistor301and the like and the memory transistor MT can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor301and the like to the memory transistor MT can be prevented. Note that as the conductor having a barrier property against hydrogen, tantalum nitride is preferably used, for example. The use of a stack including tantalum nitride and tungsten having high conductivity can inhibit the diffusion of hydrogen from the transistor301and the like while the conductivity of a wiring is ensured. In that case, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator350having a barrier property against hydrogen. A wiring layer may be provided over the insulator354and the conductor356. For example, inFIG.5, an insulator360, an insulator362, and an insulator364are stacked sequentially. Furthermore, a conductor366is formed in the insulator360, the insulator362, and the insulator364. The conductor366functions as a plug or a wiring. Note that the conductor366can be formed using a material similar to those for the conductors328,329, and330. Note that the insulator360is preferably formed using an insulator having a barrier property against hydrogen, as with the insulator324, for example. Furthermore, the conductor366preferably contains a conductor having a barrier property against hydrogen. In particular, the conductor having a barrier property against hydrogen is formed in an opening of the insulator360having a barrier property against hydrogen. In such a structure, the transistor301and the like and the memory transistor MT can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor301and the like to the memory transistor MT can be prevented. The insulator722is provided over the insulator364and the conductor366, and the memory cell array700A is provided above the insulator722. A barrier film formed using a material similar to that of the insulator324may be provided between the insulator364and the insulator722. FIG.5illustrates an example of the memory cell array700A including the U-shaped memory string in which the two columnar oxides704are electrically connected to each other through the conductor706; however, the present invention is not limited to this example. InFIG.6, in the columnar oxide704including 8 stages of memory transistors MT and the two selection transistors (SDT and SST), the lower end of one columnar oxide704is electrically connected to a conductor705B functioning as the bit line BL and the upper end thereof is electrically connected to a conductor705S functioning as the source line SL. That is, one memory string is formed of one columnar oxide704. Although the conductor705B is electrically connected to the lower ends of four columnar oxides inFIG.6, the present invention is not limited thereto. One conductor705B may be electrically connected to one columnar oxide704, or one conductor705B may be electrically connected to two or more columnar oxides704. The conductor705S is electrically connected to upper ends of two columnar oxides; however, the present invention is not limited thereto. One conductor705S may be electrically connected to one columnar oxide704, or one conductor705S may be electrically connected to two or more columnar oxides704. The selection transistor SDT is provided between the conductor705B and the memory transistor MT and the selection transistor SST is provided between the conductor705S and the memory transistor MT. Such a structure in which the conductor705B serving as the bit line BL is electrically connected to the circuit300provided under the conductor705B is preferably used, in which case the number of wirings (lead wirings) and plugs for electrically connecting the memory cell array700A to the circuit300can be reduced and the layout area of the memory device750can be reduced. Note that inFIG.6, 8 stages of the memory transistors MT are stacked; however, the present invention is not limited thereto. The number of stages of memory transistors MT may be greater than or equal to 2 and less than or equal to 7, or may be greater than or equal to 9. For example, 32 stages of memory transistors, 64 stages of memory transistors, 128 stages of transistors, or 200 or more stages of memory transistors may be stacked. <<Metal Oxide>> A metal oxide that can be used for the oxide704of one embodiment of the present invention will be described below. The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained. Here, the case where the metal oxide is an In-M-Zn oxide that contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that two or more of the above elements may be used in combination as the element M. Note that in this specification and the like, a metal oxide containing nitrogen is also called a metal oxide in some cases. Moreover, a metal oxide containing nitrogen may be called a metal oxynitride. [Composition of Metal Oxide] Described below is the composition of a cloud-aligned composite oxide semiconductor (CAC-OS) applicable to a transistor disclosed in one embodiment of the present invention. In this specification and the like, “c-axis aligned crystal (CAAC)” or “cloud-aligned composite (CAC)” might be stated. Note that CAAC refers to an example of a crystal structure, and CAC refers to an example of a function or a material composition. A CAC-OS or a CAC metal oxide has a conducting function in a part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS or the CAC metal oxide has a function of a semiconductor. In the case where the CAC-OS or the CAC metal oxide is used in an active layer of a transistor, the conducting function is to allow electrons (or holes) functioning as carriers to flow, and the insulating function is to not allow electrons functioning as carriers to flow. By the complementary action of the conducting function and the insulating function, the CAC-OS or the CAC metal oxide can have a switching function (on/off function). In the CAC-OS or the CAC metal oxide, separation of the functions can maximize each function. The CAC-OS or the CAC metal oxide includes conductive regions and insulating regions. The conductive regions have the above-described conducting function, and the insulating regions have the above-described insulating function. In some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. In some cases, the conductive regions and the insulating regions are unevenly distributed in the material. The conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred, in some cases. Furthermore, in the CAC-OS or the CAC metal oxide, the conductive regions and the insulating regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material, in some cases. The CAC-OS or the CAC metal oxide includes components having different bandgaps. For example, the CAC-OS or the CAC metal oxide contains a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of such a composition, carriers mainly flow in the component having a narrow gap. The component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or the CAC metal oxide is used in a channel formation region of a transistor, high current drive capability in the on state of the transistor, that is, a high on-state current and high field-effect mobility, can be obtained. In other words, the CAC-OS or the CAC metal oxide can be called a matrix composite or a metal matrix composite. [Structure of Metal Oxide] An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. The CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where the nanocrystals are connected. The shape of the nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that it is difficult to observe a clear crystal grain boundary even in the vicinity of distortion in the CAAC-OS. That is, a lattice arrangement is distorted and thus formation of a grain boundary is inhibited. This is because the CAAC-OS can tolerate distortion owing to a low density of oxygen atom arrangement in the a-b plane direction, a change in interatomic bond distance by substitution of a metal element, and the like. The CAAC-OS tends to have a layered crystal structure (also referred to as a stacked-layer structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced by indium, the layer can also be referred to as an (In, M, Zn) layer. When indium of the In layer is replaced by the element M, the layer can also be referred to as an (In, M) layer. The CAAC-OS is a metal oxide with high crystallinity. By contrast, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur because it is difficult to observe a clear grain boundary. Entry of impurities, formation of defects, or the like might decrease the crystallinity of a metal oxide. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies (Vo)). Thus, a metal oxide containing a CAAC-OS is physically stable. Therefore, the metal oxide containing a CAAC-OS is resistant to heat and has high reliability. In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. The a-like OS is a metal oxide having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS. An oxide semiconductor (metal oxide) can have any of various structures which show various different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention. [Transistor Including Metal Oxide] Next, the case where the metal oxide is used for a channel formation region of a transistor will be described. When the metal oxide is used for a channel formation region of a transistor, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability. Here, an example of the hypothesis about electric conduction of a metal oxide will be described. Electric conduction in a solid is prevented due to a diffusion source which is called a scattering center. For example, it is known that in single crystal silicon, lattice scattering and ionized impurity scattering are main scattering centers. In other words, in the native state with few lattice defects and impurities, the carrier mobility is high because the electric conduction in the solid is not prevented. The above might be applied to the metal oxide. For example, it is thought that a metal oxide containing oxygen less than that in the stoichiometric composition contains many oxygen vacancies Vo. The atoms around the oxygen vacancies are arranged more randomly than the atoms in the native state. It is possible that the distortion due to the oxygen vacancies might become a scattering center. Furthermore, a metal compound containing more oxygen than that in the stoichiometric composition contains excess oxygen. Excess oxygen that is liberated in the metal compound becomes O−or O2−by receiving an electron. Excess oxygen that has become O−or O2−might be a scattering center. As described above, it is thought that in the case where the metal oxide has a native state containing oxygen that satisfies the stoichiometric composition, the carrier mobility is high. Since in an indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is one kind of metal oxide containing indium, gallium, and zinc, crystal growth tends to hardly occur particularly in the air, a crystal whose size is small (e.g., the above-described nanocrystal) makes a stable structure compared with a crystal whose size is large (here, a crystal whose size is several millimeters or several centimeters) in some cases. This is probably because in the case where small crystals are connected to each other, distortion energy is reduced as compared with the case of forming a large crystal. In a region where small crystals are connected to each other, defects may be formed to reduce the distortion energy of the region. Thus, the distortion energy is reduced without formation of a defect in the region, whereby the carrier mobility can be increased. Moreover, a metal oxide with low carrier density is preferably used for the transistor. In order to reduce the carrier density of the metal oxide film, the concentration of impurities in the metal oxide film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. The metal oxide has, for example, a carrier density lower than 8×1011/cm3, preferably lower than 1×1011/cm3, and further preferably lower than 1×1010/cm3, and higher than or equal to 1×10−9/cm3. A highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low density of defect states and accordingly has a low density of trap states in some cases. Charges trapped by the trap states in the metal oxide take a long time to be released and may behave like fixed charges. Thus, a transistor whose channel formation region is formed in a metal oxide having a high density of trap states has unstable electrical characteristics in some cases. In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the metal oxide. In addition, in order to reduce the concentration of impurities in the metal oxide, the concentration of impurities in a film that is adjacent to the metal oxide is preferably reduced. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given. [Impurity] Here, the influence of impurities in the metal oxide is described. When silicon or carbon that is one of Group 14 elements is contained in the metal oxide, defect states are formed. Thus, the concentration of silicon or carbon (measured by secondary ion mass spectrometry (SIMS)) is set to be lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3in the metal oxide or around an interface with the metal oxide. When the metal oxide contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including a metal oxide that contains an alkali metal or an alkaline earth metal for a channel formation region is likely to be a normally-on transistor. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the metal oxide, which is measured by SIMS, is lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3. When the metal oxide contains nitrogen, the metal oxide easily becomes n-type by generation of electrons functioning as carriers and an increase of carrier density. Thus, a transistor whose channel formation region includes a metal oxide that contains nitrogen is likely to be a normally-on transistor. For this reason, nitrogen in the metal oxide is preferably reduced as much as possible; for example, the concentration of nitrogen in the metal oxide measured by SIMS is set to lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, and still further preferably lower than or equal to 5×1017atoms/cm3. Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Entry of hydrogen into the oxygen vacancy generates an electron functioning as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron functioning as a carrier. Thus, a transistor including a metal oxide that contains hydrogen is likely to be normally-on. For this reason, hydrogen in the metal oxide is preferably reduced as much as possible. Specifically, the hydrogen concentration of the metal oxide measured by SIMS is lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, and still further preferably lower than 1×1018atoms/cm3. When a metal oxide with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the off-state current of the transistor can be reduced, and the transistor can have stable electrical characteristics. (A Method for Manufacturing Memory Cell) Next, one embodiment of a method for manufacturing a memory transistor MT that functions as a memory cell of the present invention is described with reference toFIGS.7A to7CtoFIGS.11A and11B. Note thatFIGS.7A to7CtoFIGS.11A and11Bare cross-sectional views illustrating a manufacturing process of the memory transistor MT. First, as illustrated inFIG.7A, the conductors701and the insulators722are alternately stacked. Then, as illustrated inFIG.7B, the conductors701and the insulators722are processed to form an opening with a diameter of φ1 in the conductors701and the insulators722. Next, as illustrated inFIG.7C, the insulators722are subjected to isotropic etching to increase the opening diameter of the insulators722. At this time, the diameter of the opening is φ2 (>φ1). In this case, it can be said that the insulator722is more recessed than the side surfaces of the conductors701between which the insulator722is sandwiched. Next, as illustrated inFIGS.8A and8B, the insulator703is formed in the opening.FIG.8Bis an enlarged view of a region surrounded by dashed-dotted line inFIG.8A, and illustrates a cross section of the conductor701_k−1 and the insulator722_k−1 in the k−1-th stage, the conductor701_kand the insulator722_kin the k-th stage, and the conductor701_k+1 in the k+1-th stage (k is an integer of 2 or more and m−1 or less). The insulator703is formed by stacking the insulator703a, the insulator703b, and the insulator703cin this order. The insulator703is formed with good coverage even on the recession of the insulator722, and the insulator703ais formed in contact with the side surface of the insulator722and the side surface, part of the top surface, and part of the bottom surface of the conductor701. Next, as illustrated inFIG.9A, a film716A containing at least one of a metal element, hydrogen, and nitrogen is formed in the opening.FIG.9Bis an enlarged view of a portion surrounded by dashed-dotted line inFIG.9A. As illustrated inFIG.9B, the film716A is formed to fill the recession with the insulator703provided between the film716A and the insulator722. However, the present invention is not limited thereto. As illustrated inFIG.9C, the film716A may be formed to fill not only the recession but also the whole opening. Next, the film716A is processed to form the layer716containing at least one of a metal element, hydrogen, and nitrogen (seeFIG.10A). The processing of the film716A can be performed by isotropic etching or anisotropic etching. In the case where the film716A fills the recession and does not completely fill the opening as illustrated inFIG.9A, the film716A is preferably processed by isotropic etching. In contrast, in the case where the film716A is formed to fill the recession and the opening as illustrated inFIG.9C, it is preferable to use anisotropic etching. By such processing, the layer716can be formed in the recession. Next, as illustrated inFIG.10B, the oxide704is formed in the opening. The oxide704positioned in the same layer as the conductor701is in contact with the insulator703, and the oxide704positioned in the same layer as the insulator722is in contact with the layer716. Next, the insulator711is formed on the inner side of the oxide704, and the conductor712is formed on the inner side of the insulator711(seeFIG.10B). Note that the conductor712is not necessarily provided, and the inside of the oxide704may be filled with the insulator711. Next, heat treatment is performed to reduce the resistance of the oxide704in contact with the layer716. The region731(the regions731aand731b) in the oxide704is in contact with the layer716, and thus have reduced resistance to become the low-resistance regions. In contrast, the resistance of the region734, which is not in contact with the layer716, is kept high. The region732(the regions732aand732b) positioned between the region731and the region734serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region734of the oxide704serves as a channel formation region of the memory transistor MT. The region731aserves as one of a source and a drain of the memory transistor MT and the region731bserves as the other. The conductor701_kserves as a first gate of the memory transistor MT, the conductor712serves as a second gate, the insulator703aserves as the first gate insulating layer, the insulator703bserves as a charge accumulation layer, the insulator703cserves as a tunnel insulating layer, and the insulator711serves as the second gate insulating layer. Note that the source or the drain of the memory transistor MT in which the conductor701_kserves as a gate may serve as a drain or a source in the transistor positioned over or under the memory transistor MT. For example, when the region731bserves as a source of a transistor in which the conductor701_kserves as a gate, the region731bmay serve as a drain of a transistor in which the conductor701_k+1 serves as a gate. Through the above steps, the memory transistor MT functioning as a memory cell can be formed. By the above method, the memory transistors MT in a plurality of layers can be formed at a time without performing patterning for forming the memory transistors MT for each layer. Furthermore, in the case where a memory cell array is formed by the above method, even when the number of layers of the memory transistors MT is increased, the number of steps of patterning and etching of the memory transistors MT is not increased. In this manner, the number of manufacturing steps of the memory cell array can be reduced; thus, a semiconductor device with high productivity can be provided. (Method for Manufacturing Memory Cell Array) Next, one embodiment of a method for manufacturing a memory cell array of the present invention is described with reference toFIGS.12A to12CtoFIGS.30A to30C.FIGS.12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A,25A,26A,27A,28A,29A, and30Aare top views seen from the z axis direction, andFIGS.12B,13B,14B,15B,16B,17B,18B,19B,20B,21B,22B,23B,24B,25B,26B,27B,28B,29B, and30Bare cross-sectional views taken along dashed-dotted line A1-A2inFIGS.12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A,25A,26A,27A,28A,29A, and30A.FIGS.12C,13C,14C,15C,16C,17C,18C,19C,20C,21C,22C,23C,24C,25C,26C,27C,28C,29C, and30Care cross-sectional views taken along dashed-dotted line A1-A2inFIGS.12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A,25A,26A,27A,28A,29A, and30A.FIGS.24D and26Dare enlarged cross-sectional views of a portion surrounded by dashed-dotted lines inFIGS.24B and26B, respectively. First, the conductor706is formed over the base720having an insulating surface, and the insulator721is formed to cover the conductor706(seeFIGS.12A to12C). A conductive film to be the conductor706is formed and processed by a lithography method, whereby the conductor706can be formed. Note that the method for forming the conductor706and the insulator721is not limited thereto. The insulator721may be formed over the base720and an unnecessary portion of the insulator721may be removed to form a groove or an opening, and the conductor706may be embedded in the groove or the opening. A formation method of such a conductor is referred to as a damascene method (a single damascene method or a dual damascene method) in some cases. When an insulating film is further formed over the conductor706formed by the damascene method and the insulator721, the structure illustrated inFIGS.12A to12Ccan be obtained. The conductor706and the insulator721can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like. Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can include a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas. By using the PECVD method, a high-quality film can be formed at a relatively low temperature. Furthermore, a thermal CVD method does not use plasma and thus causes less plasma damage to an object. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving charges from plasma. In that case, accumulated charges might break the wiring, electrode, element, or the like included in the semiconductor device. By contrast, when a thermal CVD method not using plasma is employed, such plasma damage is not caused and the yield of the semiconductor device can be increased. A thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained. An ALD method also causes less plasma damage to an object. An ALD method does not cause plasma damage during deposition, so that a film with few defects can be obtained. Unlike in a deposition method in which particles ejected from a target or the like are deposited, in a CVD method and an ALD method, a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used for covering a surface of an opening with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method. When a CVD method or an ALD method is used, composition of a film to be formed can be controlled with a flow rate ratio of the source gases. For example, by a CVD method or an ALD method, a film with a certain composition can be formed depending on a flow rate ratio of the source gases. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case where the film is formed while changing the flow rate ratio of the source gases, as compared to the case where the film is formed using a plurality of deposition chambers, time taken for the film formation can be reduced because time taken for transfer and pressure adjustment is omitted. Thus, semiconductor devices can be manufactured with improved productivity. In the lithography method, first, a resist is exposed to light through a photomask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching through the resist mask is conducted. The resist mask is formed by, for example, exposure of the resist to light using KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, or the like. Alternatively, a liquid immersion technique may be employed in which a portion between a substrate and a projection lens is filled with liquid (e.g., water) to perform light exposure. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a photomask is not necessary in the case of using an electron beam or an ion beam. To remove the resist mask, dry etching treatment such as ashing or wet etching treatment can be used. Alternatively, wet etching treatment can be performed after dry etching treatment. Further alternatively, dry etching treatment can be performed after wet etching treatment. A hard mask formed of an insulator or a conductor may be used instead of the resist mask. In the case where a hard mask is used, a hard mask with a desired shape can be formed in the following manner: an insulating film or a conductive film that is the material of the hard mask is formed over a conductive film, a resist mask is formed thereover, and then the material of the hard mask is etched. The processing can be performed by a dry etching method or a wet etching method. A dry etching method is suitable for microfabrication. As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate type electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel plate type electrodes may have a structure in which a high-frequency power source is applied to one of the parallel plate type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which different high-frequency power sources are applied to one of the parallel plate type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which high-frequency power sources with the same frequency are applied to the parallel plate type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which high-frequency power sources with different frequencies are applied to the parallel plate type electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used, for example. In the case where a hard mask is used for etching of the conductive film, the etching may be performed with or without the resist mask. In the latter case, the resist mask may be removed during the etching. The hard mask may be removed by etching after the etching of the conductive film. The hard mask does not need to be removed in the case where the material of the hard mask does not affect the subsequent process or can be utilized in the subsequent process. As the conductive film to be the conductor706, a conductive film containing a metal element is preferably formed by a sputtering method. Alternatively, the conductive film can be formed by a CVD method. The surface of the insulator721is preferably subjected to planarization treatment as needed. As the planarization treatment, a chemical mechanical polishing (CMP) method or a reflow method can be used. Conductive films701A and insulating films722A are alternately stacked over the conductor706and the insulator721. This embodiment shows an example in which the conductive film701A is formed over the insulator721and the insulating film722A is formed over the conductive film701A; however, the order of the formation is not limited thereto. The insulating film722A may be formed over the insulator721, and the conductive film701A may be formed over the insulating film722A. A CVD method can be used for the formation of the conductive film701A and the insulating film722A. Alternatively, a sputtering method may be used. Although four layers of the conductive films701A and four layers of the insulating films722A are formed in this embodiment, the number of stacked layers is not limited thereto. Five or more layers of the conductive films701A and the insulating films722A may be formed depending on the required performance of a semiconductor device. For example, the number of conductive films701A and the number of insulating films722A may each be 32, 64, 128, or 200 or more. A conductive film702A is formed over the uppermost layer of the insulating film722A. A mask723is formed over the conductive film702A (seeFIGS.13A to13C). The conductive film702A can be formed using a method and a material similar to those of the conductive film701A. Note that the conductive film702A may be formed by the same method as or a method different from that of the conductive film701A. The conductive film702A may be formed using the same material as or a material different from that of the conductive film701A. Next, the conductive film702A, the conductive film701A, and the insulating film722A are processed to form a step-like conductive film701B, a conductive film702B, and an insulating film722B illustrated inFIG.14B. In the processing of the conductive film702A, the conductive film701A, and the insulating film722A, etching of the conductive film702A, the conductive film701A, and the insulating film722A and slimming of the mask723are alternately performed, whereby the step-like conductive film701B, the conductive film702B, and the insulating film722B can be formed. By the processing of the conductive film702A, the conductive film701A, and the insulating film722A, the mask723is reduced in width and thickness to be a mask723A (seeFIGS.14A to14C). Then, the mask723A is removed, and the insulator724is formed. The insulator724can be formed by a CVD method. The insulator724is preferably subjected to planarization treatment by a CMP method or a reflow method. A mask725is formed over the insulator724. The mask725is formed over the planarized insulator724, whereby the accuracy of lithography can be improved (seeFIGS.15A to15C). Then, the insulator724, the conductive film702B, the conductive film701B, the insulating film722B, and the insulator721are processed with the mask725. By the processing, the conductor701serving as the gate of the memory transistor MT and electrically connected to the word line, and the conductor702serving as the gate of the selection transistor are formed. In addition, the insulating film722B is processed into the insulator722(seeFIGS.16A to16C). Then, the mask725is removed. Next, the insulator726is formed to be embedded in the portions in the insulator724, the conductive film702B, the conductive film701B, the insulating film722B, and the insulator721, which are removed by the above processing. The insulator726can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulator726may be formed by a combination of an ALD method and a CVD method. The insulator726is preferably subjected to planarization treatment by a CMP method or a reflow method. When the planarization treatment is performed by a CMP method, the insulator726may be polished until the surface of the insulator724is exposed. The insulator724and the insulator726may be polished together. In this case, the thickness of the insulator724becomes small. Next, the insulator724is processed by a lithography method to form first openings so that the conductor701is exposed. The first opening is formed to expose each of the conductors701formed in a step-like shape. Although not illustrated, an opening exposing the conductor702may be formed at the same time (seeFIGS.17A to17C). Next, the conductor707is formed to fill the first opening (seeFIGS.18A to18C). The conductor707can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the conductor707may be formed by a combination of an ALD method and a CVD method. The conductor707may have a stacked-layer structure of a plurality of layers. The conductor707can be formed in such a manner that a conductive film to be the conductor707is formed over the insulator724and in the first opening, and unnecessary portions of the conductive film are removed by CMP and the like. Next, a mask729is formed over the insulator724and the insulator726, the insulator724, the conductor702, the conductor701, the insulator722, and the insulator721are processed by a lithography method, and second openings are formed to expose the conductor706(seeFIGS.19A to19C). Next, the insulators721,722, and724are subjected to isotropic etching to make the diameter of the opening in the insulators721,722, and724large (seeFIGS.20A to20C). By this treatment, the diameter of the opening in the insulators is larger than that of the opening in the conductors701and702. It can be said that the insulators are more recessed than the side surface of the conductor (the conductor701or702) positioned over or under the insulators. Such processing can be performed by isotropic etching using dry etching with a gas, a radical, plasma, or the like, or by isotropic etching using wet etching with a liquid. A liquid used for wet etching may be referred to as an etchant. In the case where isotropic etching is performed using dry etching, a gas, a radical, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. The isotropic etching is preferably performed without removal of the mask729. Next, an insulating film703A to be the insulator703is formed over the insulator724and the conductor707and in the second opening (seeFIGS.21A to21C). Note that, although not illustrated, the insulating film703A may be formed by stacking an insulating film to be the insulator703a, an insulating film to be the insulator703b, and an insulating film to be the insulator703cin this order. The insulating film703A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulating film703A may be formed by a combination of an ALD method and a CVD method. The insulating film to be the insulator703a, the insulating film to be the insulator703b, and the insulating film to be the insulator703cmay be formed using the same deposition apparatus or different deposition apparatuses. Note that the insulating film to be the insulator703cis preferably formed to be thinner than the insulating film to be the insulator703a, in which case the insulator703cis thinner than the insulator703a. The insulating film703A formed by the above method can have high coverage and can be formed in the recessions of the insulators721,722, and724. That is, the insulating film703A can be formed in contact with not only the side surfaces of the insulators721,722, and724and the side surfaces of the conductors701and702, but also part of the top surfaces and part of the bottom surfaces of the conductors701and702. Then, the film716A containing at least one of a metal element, hydrogen, and nitrogen is formed in the second opening (seeFIGS.22A to22C). The film716A is formed to fill the recessions of the insulators721,722, and724, and does not need to fill the second opening entirely. The film716A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the film716A may be formed by a combination of an ALD method and a CVD method. Next, the film716A is processed to form the layer716containing at least one of a metal element, hydrogen, and nitrogen (seeFIGS.23A to23C). The processing of the film716A can be performed by isotropic etching or anisotropic etching. In the case where the film716A fills the recession and does not completely fill the opening as illustrated inFIGS.23A to23C, the film716A is preferably processed by isotropic etching. In contrast, in the case where the film716A is formed to fill the recession and the opening, it is preferable to use anisotropic etching. By such processing, the layer716can be formed in the recession. Then, the insulating film703A formed on the bottom portion of the second opening is removed, so that the insulator703is obtained. Anisotropic etching is preferably used to remove the insulating film703A. Here, the insulating film703A over the insulator724and the conductor707is also removed; thus, the insulator703is provided only on the side wall of the second opening (seeFIGS.24A to24D). The conductor706is exposed again by removing the insulating film703A on the bottom portion of the second opening. Here, as illustrated inFIG.24D, the insulators703band703cof the insulator703that are positioned in the upper portion of the second opening may be removed.FIG.24Dis an enlarged view of a portion surrounded by dashed-dotted line inFIG.24B. First, the material727(also referred to as a sacrifice layer) which can be easily removed in a later step is formed to be embedded in the second opening, and the material727is removed by etching or the like to a desired depth in the second opening. The insulators703cand703bexposed by the etching are removed in this order, whereby only the insulator703acan be used as the insulator703positioned in the horizontal direction (x-y direction) of the conductor702. In this case, the gate insulating film of each of the selection transistors SST and SDT include the insulator703a. After the insulators703cand703bare removed, the material727is removed. Next, an oxide film704A to be the oxide704is formed in the second opening. The oxide film704A can be formed in such a manner that an oxide film to be the oxide704a, an oxide film to be the oxide704b, and an oxide film to be the oxide704care formed in this order over the insulator724, the conductor707, and the insulator703and in the second opening. Part of the oxide704is formed in contact with the layer716. Part of the oxide704is formed in contact with the conductor706. The oxide film to be the oxide704a, the oxide film to be the oxide704b, and the oxide film to be the oxide704ccan be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the oxide films may be formed by a combination of an ALD method and a CVD method. Alternatively, the oxide films may be formed using different deposition methods or different deposition apparatuses. Then, an insulating film711A is formed on the inner side of the oxide film704A, and a conductive film712A is formed on the inner side of the insulating film711A. The insulating film711A and the conductive film712A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulating film711A and the conductive film712A may be formed by a combination of an ALD method and a CVD method (seeFIGS.25A to25C). The insulator711can be formed using a material for supplying oxygen to the oxide704or a material for supplying hydrogen to the oxide704in accordance with the characteristics needed for the memory transistors MT and the semiconductor devices including the memory transistors MT. Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen atmosphere at 200° C. to 500° C. inclusive, preferably 300° C. to 400° C. inclusive. The atmosphere in which heat treatment is performed is not limited to the above atmosphere as long as at least one of nitrogen, oxygen, and argon is contained. The heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric pressure atmosphere. When the heat treatment is performed in the state where the oxide film704A is in contact with the layer716, the resistance of the oxide film704A is reduced (seeFIGS.26A to26D). The mechanism to reduce the resistance of the oxide film704A is similar to that of the oxide704.FIG.26Dis an enlarged view of a region surrounded by dashed-dotted line inFIG.26B. As illustrated inFIG.26D, the region734of the oxide film704A is a low-resistance region. In contrast, in the oxide film704A, the resistance of the region731, which is not in contact with the layer716, is kept high. Furthermore, the above-described junction region may be provided between the region734and the region731. In addition, also when the heat treatment is performed in the state where the oxide film704A and the conductor706are in contact with each other, the resistance of the oxide film704A is reduced. When the oxide film704A is in contact with the conductor706, a metal compound layer including a metal element contained in the conductor706and the component of the oxide film704A are formed at the interface between the conductor706and the oxide film704A in some cases. The metal compound layer is preferably formed, in which case the contact resistance between the conductor706and the oxide film704A can be reduced. Oxygen contained in a region728of the oxide film704A is absorbed by the conductor706in some cases. At this time, the resistance of the oxide film704A in the vicinity of the interface between the conductor706and the oxide film704A is reduced, so that the contact resistance between the conductor706and the oxide film704A can be reduced. When the heat treatment is performed in the state where the oxide film704A and the conductor706are in contact with each other, the oxide film704A has lower resistance and the contact resistance between the conductor706and the oxide film704A is further reduced. Then, unnecessary portions of the conductive film712A, the insulating film711A, and the oxide film704A, which are portions above the dotted line inFIGS.26B and26C, are removed by a CMP method or the like to obtain the oxide704, the insulator711, and the conductor712(seeFIGS.27A to27C). Note that the above-described heat treatment may be performed after the removal of unnecessary portions of the conductive film712A, the insulating film711A, and the oxide film704A. Next, as illustrated inFIGS.28A to28C, the conductor705serving as part of the bit line BL, the source line SL, and the word line WL is formed. The conductor705is provided to be electrically connected to the oxide704and the conductor707. In the case where the conductor712is provided on the inner side of the oxide704, it is preferable that at least an opening which exposes the conductor712be provided in the conductor705so that the conductor705and the conductor712are electrically separated from each other. In this case, the opening may be provided to expose the insulator711. Part of the oxide704may be exposed. Then, as illustrated inFIGS.29A to29C, the insulator717is formed to cover the conductor705. In the insulator717, an opening which exposes part of the conductor705(the conductor705electrically connected to the oxide704on the bit line side) and the conductor712is provided. In the case where the opening which exposes the conductor712is formed, the diameter of the opening may be larger than that of the opening provided in the conductor705. Since the conductor705includes an opening, the opening which exposes the conductor712can be formed in a self-aligned manner, and a defect such as formation of the opening whose diameter at the bottom portion has an unintentional size and a defect such as displacement of the opening from the conductor712can be prevented. Then, as illustrated inFIGS.30A to30C, the insulator713is formed to cover the conductor705in the opening which is provided in the insulator717and exposes the conductor712. First, an insulating film to be the insulator713is formed over the insulator717by a CVD method or an ALD method, and then anisotropic etching is performed, whereby the insulating film formed at the bottom portion of the opening is removed. At this time, the insulating film over the insulator717is also removed to form the insulator713. The insulating film may be processed by a lithography method. At this time, the insulator713is also provided over the insulator717in some cases. Next, the conductor714and the conductor715that serve as the bit line BL and the wiring BG are formed. Although the conductors714and715are illustrated as different layers inFIGS.30A to30C, the present invention is not limited thereto. The conductor714and the conductor715may be formed as one conductor at a time. When the conductor714and the conductor715are separately formed, a conductive film to be the conductor714is formed over the insulator717to be embedded in the opening in the insulator717, and an unnecessary portion of conductive film is removed by a CMP method or the like, whereby the conductor714can be formed. After that, the conductor715is formed. The conductor715may be formed by a lithography method or a damascene method. At this time, the insulator713is provided on the side surface of the opening formed in the insulator717and the conductor705; thus, the conductor715electrically connected to the conductor712is not electrically connected to the conductor705. When the conductor714and the conductor715are formed at a time, a conductor serving as the conductor714and the conductor715can be formed by forming a conductive film over the insulator717to be embedded in the opening formed in the insulator717and processing the film by a lithography method. Through the above steps, the memory cell array can be manufactured. In the description of this manufacturing process, the memory cell array includes four layers of the memory transistors MT and four memory strings; however, the present invention is not limited thereto. The memory cell may include five or more layers of the memory transistors MT or five or more memory strings. For example, a memory cell array including 32 layers, 64 layers, or 128 layers of the memory transistors MT can be manufactured. Moreover, a memory cell array including 200 or more layers of the memory transistors MT can be manufactured. The memory cell array is manufactured in the above manner, whereby the memory transistors MT in a plurality of layers can be formed at a time without patterning for forming the memory transistors MT for each layer. Furthermore, in the case where a memory cell array is formed by the above method, even when the number of layers of the memory transistors MT is increased, the number of steps of patterning and etching is not increased. In this manner, the number of manufacturing steps of the memory cell array can be reduced; thus, a semiconductor device with high productivity can be provided. (Configuration Example of 3D NAND) FIG.31Aillustrates a configuration example of a three-dimensional NAND-type nonvolatile memory device (3D NAND). A memory device100illustrated inFIG.31Aincludes a control circuit105, a memory cell array110, and peripheral circuits. The control circuit105controls the memory device100collectively and performs data writing and data reading. The control circuit105processes a command signal from the outside and generates a control signal for the peripheral circuits. As the peripheral circuits, a row decoder121, a row driver122, a sense amplifier123, a source line driver124, and an input/output circuit125are provided. The memory cell array110includes a plurality of memory strings112.FIG.31Billustrates a circuit configuration example of the memory string112. In the memory string112, a selection transistor SST, memory transistors MT1to MT2k(k is an integer of 1 or more), and a selection transistor SDT are electrically connected in series between the bit line BL and the source line SL. Note that in the case where the memory transistors MT1to MT2kare not distinguished from each other, these memory transistors are referred to as memory transistors MT. The same applies to other elements. The selection transistors SST and SDT and the memory transistors MT1to MT2kare each a transistor in which the channel is formed using a metal oxide as described above. The memory transistor MT includes a charge accumulation layer and is included in the nonvolatile memory cell. A gate of the selection transistor SST and a gate of the selection transistor SDT are electrically connected to a wiring SGL and a wiring DGL which serve as selection gate lines, respectively. Gates of the memory transistors MT1to MT2kare electrically connected to word lines WL1to WL2k, respectively. The bit line BL extends in the column direction, and the wirings SGL and DGL and the word line WL extend in the row direction. The selection transistors SST and SDT and the memory transistor MT may each have a second gate as illustrated inFIG.31B. The second gate is electrically connected to the wiring BG.FIG.31Billustrates a wiring BG which is electrically connected to the second gates of the selection transistor SST and the memory transistors MT1to MTk and a wiring BG which is electrically connected to the second gates of the selection transistor SDT and the memory transistors MTk+1 to MT2k. Different potentials or the same potential may be applied to the wirings BG. Furthermore, the wirings BG may be electrically connected to each other. The wiring BG preferably extends in the column direction in parallel to the bit line BL but may extend in the row direction. With the wiring BG, the threshold values of the selection transistors SST and SDT can be controlled. Furthermore, the potential of the wiring BG may be controlled in accordance with the circuit operation of the memory cell array. The input/output circuit125performs temporarily holding data written to the memory cell array110, temporarily holding data read out from the memory cell array110, and the like. The source line driver124drives the source line SL. The bit line BL is electrically connected to the sense amplifier123. The sense amplifier123detects voltage that is read out from the memory string112to the bit line BL at the time of data reading and amplifies it. In addition, the sense amplifier123inputs voltage corresponding to the writing data to the bit line BL at the time of data writing. The row decoder121decodes address data input from the outside and selects a row to be accessed. The row driver122inputs voltage needed for writing, reading, and erasing data to the wirings DGL and SGL and the word lines WL in accordance with the decoded results by the row decoder121. The memory cell array110may be provided in a layer different from the peripheral circuits such as the control circuit105and the sense amplifier123. In particular, the memory cell array110is preferably stacked and overlapped with the sense amplifier123, in which case the wiring led from the memory cell array110to the sense amplifier123can be more compact.FIG.32shows a block diagram of the memory device100, shown inFIG.31A, with a three-dimensional structure in which the memory cell array110is provided over the control circuit105, the row decoder121, the row driver122, the sense amplifier123, the source line driver124, and the input/output circuit125to overlap with the sense amplifier123. A three-dimensional stacked-layer structure example of the memory cell array110is illustrated inFIG.33toFIG.35.FIG.33is a circuit diagram schematically illustrating the three-dimensional structure example of the memory cell array110. Some circuits (memory strings) are not illustrated for easy understanding.FIG.34is a perspective view illustrating the three-dimensional structure example of the memory cell array110.FIG.35is a perspective view illustrating the three-dimensional structure example of the connection portion of the word line WL and the conductor701. As illustrated inFIG.33, the memory cell array110is stacked over a region where the sense amplifier123is formed. Accordingly, the layout area of the memory device100can be reduced. As illustrated inFIG.34andFIG.35, even in the conductor701in the same stage, the conductor701aon the bit line BL side is connected to the word line WLa, and the conductor701bon the source line SL side is connected to the word line WLb. The wiring BG electrically connected to the conductor712is provided in the same layer as the bit line BL and extends in the column direction like the bit line BL in this example; however, the present invention is not limited thereto. An insulator may be provided over the bit line BL, and the wiring BG may be provided over the insulator. The wiring BG does not necessarily extend in the column direction and may extend in the row direction. Note thatFIG.33toFIG.35illustrate an example in which eight memory transistors MT1to MT8are provided in one memory string112. (Description of Circuit Operation of Memory Device) Next, operation of writing and reading data to/from the memory string112is described with reference toFIGS.36A to36C. Hereinafter, the memory transistors MT sharing each of the word lines WL1to WL2kare collectively called a page. Although the memory string112includes the memory transistors MT1to MT8as an example inFIGS.36A to36C, the number of memory transistors MT is not limited to this example. <Erasing Operation> In the case where data is written to the memory transistor MT, data is preferably erased before the writing operation. The operation of erasing data is also referred to as a reset operation in some cases. An erasing operation is performed on every memory string112(also referred to as block). For example, an erasing operation can be performed in the following manner: a block storing data to be erased is selected, a low potential (a potential at which the memory transistors MT1to MT8are turned off, such as 0 V) is applied to the word lines WL1to WL8, an erasing potential VE is applied to the source line SL and the bit line BL, and the selection transistors SDT and SST are turned on, as shown inFIG.36A. Through the reset operation, electrons stored in the charge accumulation layer of each of the memory transistors MT1to MT8can be extracted. Accordingly, the memory transistors MT1to MT8hold data “1”. Alternatively, the erasing operation can be performed by application of an erasing potential to the wiring BG. The erasing operation can be performed in the following manner: an erasing potential (e.g., 15 V) is applied to the wiring BG, a low potential (a potential at which the transistors MT1to MT8are turned off, such as 0 V) is applied to the wirings WL1to WL8, and the selection transistors SDT and SST are turned on. Alternatively, data of the memory transistor MT can be erased in the following manner: the selection transistors SDT and SST are turned off to set an oxide including a channel formation region of the memory transistor MT in a floating state, and a positive charge (e.g., 15 V) is applied to the wiring BG as the erasing potential. At this time, the selection transistors SDT and SST are off, and thus the bit line BL and the source line SL are set at any potential. For example, to the wirings WL1to WL8, a low potential (a potential at which the memory transistors MT1to MT8are turned off, such as 0 V) is applied. As a result, an oxide including a channel formation region is in a floating state; thus, the potential of the oxide increases with the increasing potential of the wiring BG, and electrons stored in the charge accumulation layer can be extracted to the oxide side. In another erasing operation, to the wirings WL1to WL8, a low potential (a potential at which the memory transistors MT1to MT8are turned off, such as 0 V) is applied, for example. Then, the selection transistors SDT and SST are turned on to increase the potentials of the bit line BL and the source line SL. At this time, the potentials of the bit line BL and the source line SL are set lower than that of the wirings BG. For example, the potentials of the bit line BL and the source line SL are set to 10 V and the potential of the wiring BG is set to 12 V. At this time, the memory transistor MT is turned on by the potential of the wiring BG, and an oxide included in the memory transistor MT holds a potential of 10 V. As a result, electrons stored in the charge accumulation layer can be extracted to the oxide side. The erasing operation is not limited to the above-described method. The erasing operation may be performed by sequentially selecting the memory transistors MT storing data to be erased, for example. In that case, the erasing operation does not need to be performed on all the memory transistors MT and only the memory transistors MT storing data to be erased may be selected and the data may be erased. For example, the erasing operation may be performed on only the memory transistor MT to which data “0” has been written. Note that data in the memory transistor MT which is not subjected to data rewriting is preferably stored in a different memory region in advance of the erasing operation of the block. <Writing Operation> Next, a data writing operation is described with reference toFIG.36B. A data writing operation can be performed for each of the above pages. First, a writing potential (e.g., 15 V) is applied to a word line of a page subjected to writing, and then a positive potential (a potential at which a transistor is turned on, such as 3 V) is applied to a word line of a page which is not subjected to writing. As shown inFIG.36B, a writing potential is applied to the word line WL1first, and then positive potentials are applied to the word lines WL2to WL8. Then, the selection transistor SST is turned off and a positive potential is applied to the selection transistor SDT to turn on the selection transistor SDT. Thus, data corresponding to the potential of the bit line BL is written to the memory transistor MT1. Specifically, when a potential of the bit line BL is a low potential (e.g., 0 V), electrons are injected into the charge accumulation layer of the memory transistor MT1because a potential difference between the word line WL1and the bit line BL is increased. In the case where the potentials of the selection transistors SDT and the bit line BL are both positive potentials, the selection transistor SDT is turned off. At this time, the memory transistor MT is brought into an electrically floating state, so that electrons are not injected into the charge accumulation layer of the memory transistor MT1. That is, when the low potential is applied to the bit line BL, data “0” is written to the memory transistor MT1, and when the positive potential is applied to the memory transistor MT1, the data of the memory transistor MT1remains “1”. Data writing can be performed page by page in such a manner that each of the bit lines BL is applied with a potential required in the corresponding memory string112. Multilevel data can be written to the memory transistor MT. For example, the amount of charges injected into the charge accumulation layer of the memory transistor MT can be controlled on the basis of a potential of the bit line BL or the like or a potential applying period. <Reading Operation> Then, a data reading operation is described with reference toFIG.36C. A data reading operation can also be performed for each of the pages. First, a low potential (e.g., 0 V) is applied to a word line of a page subjected to reading, and then a positive potential (a potential at which a transistor is turned on, such as 3 V) is applied to a word line of a page which is not subjected to reading. As shown inFIG.36C, a low potential is applied to the word line WL1first, and then positive potentials are applied to the wirings WL2to WL8. Then, the selection transistors SDT and SST are turned on. A reading potential (e.g., 1 V) is applied to the bit line BL, and a low potential (e.g., 0 V) is applied to the source line SL. At this time, when the memory transistor MT has data “1”, current flows to the memory string112, so that the potential of the bit line BL decreases. When data stored in the memory transistor MT1is “0”, current does not flow to the memory string112and the potential of the bit line BL does not change. The sense amplifier123detects the potential of the bit line BL and amplifies it. Through the above steps, data in the memory string112can be read out. At this time, a positive potential is applied to the wiring BG, whereby the threshold voltage (Vth) of the memory transistor MT may be shifted in the negative direction. The potential applied to the wiring BG is adjusted so that the memory transistor MT to which writing is not subjected becomes normally on. Thus, reading of wrong data can be prevented. In addition, a potential applied to the word line WL can be reduced, and power consumption of the memory device can be reduced. Data in each of the memory strings112is output to the bit line BL; thus, data per page can be read. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 2 In this embodiment, a structure and a manufacturing method of a semiconductor device of one embodiment of the present invention, which are different from those of Embodiment 1, will be described with reference toFIG.37toFIGS.67A to67C. Note that description of the same components as those in Embodiment 1 is omitted in some cases. In the semiconductor device illustrated inFIG.37toFIGS.67A to67C, components having the same functions as the components in the semiconductor device described in Embodiment 1 are denoted by the same reference numerals, and the detailed description thereof and the description of the formation method thereof are omitted in some cases. Furthermore, in the semiconductor device in this embodiment, the metal oxide described in Embodiment 1 can be used. (Memory Transistor MT, Memory Cell Array700) First, structures of a memory transistor MT and a memory cell array700of the semiconductor device are described with reference toFIG.37toFIGS.39A and39B.FIG.37is a cross-sectional view of a memory cell array700.FIG.38Ais a top view of the memory cell array700. Note thatFIG.38Ais a top view taken along dashed-dotted line A5-A6inFIG.37and some components are not illustrated.FIG.37is a cross-sectional view taken along dashed-dotted line A1-A2inFIG.38A.FIG.38Bis a cross-sectional view taken along dashed-dotted line A3-A4inFIG.38A, which illustrates an example of a memory string.FIG.39Ais an enlarged cross-sectional view of a portion surrounded by dashed-dotted line791inFIG.37, which illustrates an example of a memory transistor MT functioning as a memory cell.FIG.39Bis an enlarged cross-sectional view of a portion surrounded by dashed-dotted line792inFIG.37, which illustrates an example of a transistor functioning as a selection transistor. Note that in the following description, rectangular coordinates using an x-axis, a y-axis, and a z-axis are set as illustrated inFIG.37andFIGS.38A and38Bfor the sake of convenience. Here, the x-axis and the y-axis are parallel to the top surface of a base720provided with the memory cell array700and the z-axis is perpendicular to the top surface of the base720. The memory cell array700includes: an insulator721over the base720; a stack in which a conductor701(conductors701_1to701_m(m is a natural number of 2 or more)) and an insulator722(insulators722_1to722_m) are alternately stacked over the insulator721; a conductor702over the stack; an insulator724over the conductor702and the stack; an insulator703(insulators703_1to703_4) in an opening portion formed through the insulator724, the conductor702, the stack, and the insulator721; an oxide704(oxides704_1to704_4) on the inner side of the insulator703; a layer716containing at least one of a metal element, hydrogen, and nitrogen provided between the insulator703and the oxide704to be in contact with part of the oxide704; an insulator711(insulators711_1to711_4) on the inner side of the oxide704; an insulator719serving as a mask for the oxide704between the oxide704and the insulator711; a conductor712(conductors712_1to712_4) on the inner side of the insulator711; a conductor705(conductors705_1to705_4) electrically connected to upper end portions of the oxides704_1to704_4; a conductor706(conductors706_1to706_4) electrically connected to lower end portions of the oxides704_1to704_4; a conductor707(conductors707_1to707_m) electrically connected to the conductors701_1to701_m; a conductor708(conductors708_1to708_m) electrically connected to the conductors707_1to707_m; a conductor709electrically connected to the conductor702; a conductor710electrically connected to the conductor709; an insulator717and an insulator713over the insulator724, the conductor705, and the conductor708; and a conductor714and a conductor715electrically connected to each of the conductors712_1to712_4. Note that inFIG.37andFIGS.38A and38B, four or more stages of the conductors701are illustrated to show a plurality of conductors701; however, this embodiment is not limited toFIG.37and at least two stages of the conductors701are provided. As illustrated inFIG.37andFIG.38A, the conductor701extends in the x-axis direction. As illustrated inFIG.37andFIG.38B, the insulator703and the oxide704extend in the z-axis direction. That is, the conductor701and the insulator703and oxide704are preferably provided to cross each other perpendicularly. Furthermore, as illustrated inFIG.37, the conductor707extends in the z-axis direction. The conductor708may extend in the y-axis direction. In addition, a conductor functioning as a bit line BL connected to the conductor705may extend in the y-axis direction. Part of the conductor705may function as the bit line BL and the conductor705may extend in the y-axis direction. The conductor712is formed in a columnar shape and extends in the z-axis direction. In addition, the insulator711is provided to surround the conductor712and the oxide704is provided to surround the insulator711, each of which extends in the z-axis direction. In other words, the conductor712is provided as a core on the inner side of the columnar oxide704that extends in the z-axis direction, and the insulator711is provided between the oxide704and the conductor712. The insulator703is provided to surround the periphery of the side of the columnar oxide704. The conductor707is formed in a columnar shape and extends in the z-axis direction. The diameter of an opening formed in the conductor701and the conductor702is larger than the diameter of an opening formed in the insulator721, the insulator722, and the insulator724. It can be said that the conductors are more recessed than the side surfaces of the insulators. The insulator719is provided on the side surfaces of the conductor701and the conductor702with the insulator703and the oxide704provided therebetween. That is, the insulator703and the oxide704are provided on the side surfaces of the insulator721, the conductor701, the insulator722, the conductor702, and the insulator724along the recessions, and the insulator719is provided in the recessions with the insulator703and the oxide704provided therebetween. The oxide704has a low-resistance region, and when the low-resistance region is formed in part of the oxide704, the insulator719can serve as a mask to cover the oxide704in a portion where the low-resistance region is not formed. When the oxide704has a low-resistance region, in the memory string where the memory cells are stacked or in the memory cell array, the series resistance between the memory cells can be reduced. Furthermore, a region where the side surface of the oxide704is covered with the insulator719can serve as a channel formation region. The columnar oxide704is electrically connected to the conductor706at the lower end in the z-axis direction and electrically connected to the conductor705at the upper end. As illustrated inFIG.38B, the conductor706is electrically connected to the lower ends of two adjacent columnar oxides704, and the upper ends of the two adjacent columnar oxides704are electrically connected to the electrically separated conductors705. In this embodiment, the U-shaped memory string in which the two columnar oxides704are electrically connected to each other through the conductor706is described; however, the present invention is not limited thereto. For example, the conductor706may serve as one of a bit line BL and a source line SL and the conductor705may serve as the other of the bit line BL and the source line SL. In this case, the conductor706may be electrically connected to a plurality of columnar oxide704or one columnar oxide704. Furthermore, the conductor705may be electrically connected to a plurality of columnar oxide704or one columnar oxide704. In the case where the lower end of the columnar oxide704is electrically connected to one of the bit line BL and the source line SL and the upper end thereof is electrically connected to the other, a selection transistor is preferably provided at around the lower end and upper end of the columnar oxide704. For example, in the case where the conductor706serves as part of the bit line BL and the conductor705serves as part of the source line SL, a selection transistor SST is provided between the conductor706and the memory transistor MT and a selection transistor SDT is provided between the conductor705and the memory transistor MT. Here, a region where the conductor701crosses the insulator703and the oxide704and the vicinity of the region serve as the memory transistor MT. In addition, a region where the conductor702crosses the insulator703and the oxide704and the vicinity of the region serve as the selection transistor. The channel formation region of each of the memory transistor MT and the selection transistor is provided along the above recession. The memory transistor MT and the selection transistor are electrically connected in series to form the memory string. FIG.39Ais an enlarged cross-sectional view of a portion surrounded by dashed-dotted line791inFIG.37, which illustrates a cross section of the memory transistor MT in a k-th stage (k is an integer greater than or equal to 2 and less than or equal to m−1). The memory transistor MT includes the conductor701_k, the insulator703(the insulators703a,703b, and703c), and the oxide704(the oxides704a,704b, and704c). In addition, the conductor712and the insulator711may be included. The conductor701_kserves as a gate of the memory transistor MT, the insulator703aserves as a gate insulating layer, the insulator703bserves as a charge accumulation layer, and the insulator703cserves as a tunnel insulating layer. Although the details are described later, the oxide704includes the oxide704a, the oxide704b, and the oxide704c, and the oxide704ahas an energy gap relatively wider than that of the oxide704b, and the oxide704chas an energy gap relatively wider than that of the oxide704b. In other words, the oxide704bhas an energy gap relatively narrower than those of the oxides704aand704c. In the oxide704, a region734that is positioned in the same layer as the conductor701_kserves as a channel formation region. Furthermore, in the oxide704, a region731(regions731aand731b) not covered with the insulator719serves as a low-resistance region. A region732(regions732aand732b) positioned between the region734and the region731serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region732may serve as a channel formation region like the region734or serve as a low-resistance region like the region731. The memory transistor MT in the k-th stage and the memory transistor MT in the k−1-th stage or the transistor MT in the k+1-th stage share the low-resistance region. The oxide704has a structure where the channel formation regions and the low-resistance regions are alternately formed. When the oxide704has the low-resistance region, the series resistance between the memory cells can be reduced in the memory string where the memory cells are stacked or in the memory cell array. In the case where the conductor712is provided, the conductor701_kserves as a first gate and the conductor712serves as a second gate. Note that the first gate is referred to as a control gate or simply a gate, and the second gate is referred to as a back gate in some cases. The insulators711and719are provided between the oxide704and the conductor712and serves as a second gate insulating layer. At this time, the insulator703aserves as a first gate insulating layer. In the circuit operation of the memory transistor MT, the potential of the conductor712which serves as the second gate is controlled, whereby power consumption of the memory transistor MT can be reduced. FIG.39Bis an enlarged cross-sectional view of a portion surrounded by dashed-dotted line792inFIG.37, which illustrates a cross section of the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)). The selection transistor includes the conductor702, the insulator703(the insulators703a,703b, and703c), and the oxide704(the oxides704a,704b, and704c). In addition, the conductor712and the insulator711may be included. The conductor702serves as a gate of the selection transistor and the insulator703aserves as a gate insulating layer. As the gate insulating layer, at least the insulator703ais provided, and the insulator703band the insulator703care not necessarily provided. Alternatively, after the insulators703a,703b, and703care provided, the insulators703band703cmay be partly removed. The oxide704includes the oxide704a, the oxide704b, and the oxide704c, and the oxide704ahas an energy gap relatively wider than that of the oxide704b, and the oxide704chas an energy gap relatively wider than that of the oxide704b. In other words, the oxide704bhas an energy gap relatively narrower than those of the oxides704aand704c. In the oxide704, a region734that is positioned in the same layer as the conductor702serves as a channel formation region. Furthermore, in the oxide704, a region731(regions731aand731b) not covered with the insulator719serves as a low-resistance region. A region732(regions732aand732b) positioned between the region734and the region731serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region732may serve as a channel formation region like the region734or serve as a low-resistance region like the region731. In the case where the conductor712is provided, the conductor702serves as a first gate and the conductor712serves as a second gate. Note that the first gate is referred to as a top gate or simply a gate, and the second gate is referred to as a back gate in some cases. The insulators711and719are provided between the oxide704and the conductor712and serves as a second gate insulating layer. At this time, the insulator703aserves as a first gate insulating layer. With the conductor712which serves as the second gate, the threshold voltage of the selection transistor can be controlled. Note that the structure of the semiconductor device in this embodiment is an example, and the present invention is not limited to the number, the position, and the like of the circuit element, the wiring, and the like illustrated in the drawings and the like according to this embodiment. The number, the position, and the like of the circuit element, the wiring, and the like included in the semiconductor device in this embodiment can be set as appropriate in accordance with the circuit configuration and the driving method. The base720provided with the memory cell array700preferably has an insulating surface. As a substrate having an insulating surface, a semiconductor substrate provided with an insulator on its surface, an insulator substrate, a conductor substrate provided with an insulator on its surface, or the like is used. As the semiconductor substrate, a semiconductor substrate formed using silicon, germanium, or the like or a semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), a resin substrate, or the like is used. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate, is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. The conductor701serves as the gate of the memory transistor MT and is electrically connected to a word line. That is, the conductors701,707, and708also serve as part of the word line. Here, as illustrated inFIG.37, the conductor701is preferably provided in a step-like shape where the conductor701in the lower layer extends to be closer to the A2side than the conductor701in the upper layer does. The conductor701is provided in this manner, so that the conductor701in the upper layer does not overlap with a region of part of the top surface of the conductor701in the lower layer; thus, the regions in the conductors701can be connected to the respective conductors707. For the conductor701, a conductive material such as silicon or metal can be used. When silicon is used, amorphous silicon or polysilicon can be used. Furthermore, a p-type impurity or an n-type impurity may be added to form conductive silicon. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used for the conductor701. In the case where a metal material is used for the conductor701, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. The conductor702is provided over the conductor701. The conductor702serves as the gate of the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)) and is electrically connected to a wiring DGL and a wiring SGL. That is, the conductors702,709, and710also serve as part of the wirings DGL and SGL. The conductor702can be formed using the material similar to that for the conductor701. The conductor702may be formed using the same material as the conductor701or a different material from that of the conductor701. The materials of the conductor701and the conductor702are determined depending on the usage in consideration of their work functions and the like. Insulating films provided over and under the conductors701and702can be formed using an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like which has an insulating property. For the insulating film, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like, which has a low relative permittivity, is preferably used. Although aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, or the like can be used for the insulating film, these materials have a high relative permittivity; thus, parasitic capacitance may be generated between the conductors701or between the conductor701and the conductor702. The material used for the insulating film can be determined depending on the design of the device or the usage. The insulator703includes the insulator703a, the insulator703b, and the insulator703c. The insulator703ais provided on the conductor701side, the insulator703cis provided on the oxide704side, and the insulator703bis provided between the insulator703aand the insulator703c. The insulator703aserves as a gate insulating layer, the insulator703bserves as a charge accumulation layer, and the insulator703cserves as a tunnel insulating layer. Note that the selection transistor may have the same structure as the memory transistor MT. However, as illustrated inFIG.39B, the selection transistor does not necessarily include the charge accumulation layer or the tunnel insulating layer. The transistor on the bit line side (SDT) and the transistor on the source line side (SST) may each have a structure where the insulators703band703care removed and only the insulator703ais provided as the insulator703. InFIG.39B, the conductor712may be provided as the second gate electrode. In this case, the conductor702serves as the first gate electrode, the insulator703aserves as the first gate insulating film, and the insulator711serves as the second gate insulating film. With the conductor712, the threshold voltage of the selection transistor can be controlled. For the insulator703a, silicon oxide or silicon oxynitride is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, a stack of any of these materials may be used for the insulator703a. The insulator703bis preferably formed using a material that serves as a charge accumulation layer and is preferably formed using silicon nitride or silicon nitride oxide. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. For the insulator703c, silicon oxide or silicon oxynitride is preferably used. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, a stack of any of these materials may be used for the insulator703c. Furthermore, the insulator703cis preferably thinner than the insulator703a. Although details are described later, in writing or erasing data to/from the memory transistor MT, charge is transferred between the oxide704and the insulator703bthrough the insulator703c. That is, the insulator703cserves as a tunnel insulating layer. In particular, in the case where the insulator703is formed in the opening provided in the stack including the conductor701, the conductor702, and the insulating films, the insulator703formed on the bottom portion of the opening needs to be removed by anisotropic etching using dry etching or the like. In anisotropic etching, the side surface of the insulator703cis also exposed to plasma, a radical, a gas, a chemical solution, or the like. When the side surface of the insulator703cis damaged in this manner, trap centers might be formed in the insulator703cand might affect electrical characteristics of the transistor. To suppress the formation of the trap centers, the side surface of the insulator703cis required to have high resistance to damage due to etching. In this case, for the insulator703c, aluminum oxide, a stack of silicon oxide and aluminum oxide, or a stack of silicon oxynitride and aluminum oxide is preferably used. The insulators703a,703b, and703ccan be formed by an ALD method or a CVD method. To prevent contamination of the interfaces between the insulator703a, the insulator703b, and the insulator703c, these insulators are preferably formed in succession without exposure to an air atmosphere in the same chamber or with a multi-chamber deposition apparatus including a plurality of chambers. The oxide704is preferably formed using a metal oxide functioning as an oxide semiconductor (hereinafter, the metal oxide is also referred to as an oxide semiconductor). The oxide semiconductor is preferably used, in which case a transistor including the oxide semiconductor can have more favorable on-state characteristics and higher mobility than a transistor including a semiconductor made of silicon, for example. For example, as the oxide704, a metal oxide such as an In-M-Zn oxide (M is one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is used. An In—Ga oxide or an In—Zn oxide may be used as the oxide704. The oxide704preferably includes the oxide704aprovided on the insulator703cside, the oxide704bprovided on the inner side of the oxide704a, and the oxide704cprovided on the inner side of the oxide704b. At this time, as the oxide704a, an oxide having an energy gap relatively wider than that of the oxide704bis preferably used. As the oxide704c, an oxide having an energy gap relatively wider than that of the oxide704bis preferably used. Here, an oxide having a wide energy gap is referred to as a wide gap and an oxide having a narrow energy gap is referred to as a narrow gap in some cases. InFIGS.39A and39B, the oxide704has a three-layer structure of the oxides704a,704b, and704c; however, the present invention is not limited thereto. The oxide704may have a two-layer structure of the oxides704aand704bor a stacked-layer structure of four or more layers. In the case where the oxides704aand704care each a wide gap and the oxide704bis a narrow gap, an energy of the conduction band minimum of each of the oxides704aand704cis preferably higher than that of the conduction band minimum of the oxide704b. In other words, the electron affinity of each of the oxides704aand704cis preferably smaller than the electron affinity of the oxide704b. The oxides704a,704b, and704cpreferably have different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M to constituent elements in the metal oxide used as the oxides704aand704cis preferably greater than that in the metal oxide used as the oxide704b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxides704aand704cis preferably greater than that in the metal oxide used as the oxide704b. Moreover, the atomic ratio of the element In to the element M in the metal oxide used as the oxide704bis preferably greater than that in the metal oxide used as the oxides704aand704c. As the oxides704aand704c, for example, a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition which is in the neighborhood of any of the above atomic ratios can be used. As the oxide704b, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4:2:4.1, In:Ga:Zn=1:1:1, or In:Ga:Zn=5:1:6, or a composition which is in the neighborhood of any of the above atomic ratios can be used. The oxides704a,704b, and704care preferably formed to satisfy the above atomic ratio. For example, it is preferable that the oxides704aand704cbe each a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition which is in the neighborhood of the above atomic ratio and the oxide704bbe each a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4:2:4.1 or a composition which is in the neighborhood of the above atomic ratios. Note that the above composition shows the atomic ratio in an oxide formed over a base or the atomic ratio in a sputtering target. In addition, it is preferable that a CAAC-OS described later be used as the oxides704aand704cand a CAC-OS described later be used as the oxide704b. In the case where the CAAC-OS is used as the oxides704aand704c, the c-axes are preferably aligned parallel to x-y plane shown inFIG.37,FIGS.38A and38B, and the like, that is, perpendicular to the z-axis, and preferably aligned from the side surface of the opening to the central portion. Here, in a junction portion of the oxides704aand704band a junction portion of the oxides704cand704b, the conduction band minimum is gradually varied. In other words, the conduction band minimum in the junction portion of the oxides704aand704band the junction portion of the oxides704cand704bis continuously varied or continuously connected. To vary the conduction band minimum gradually, the density of defect states in a mixed layer formed at the interface between the oxides704aand704band the interface between the oxides704cand704bis decreased. Specifically, when the oxides704a,704b, and704ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide704bis an In—Ga—Zn oxide, it is preferable to use an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like as each of the oxides704aand704c. Accordingly, the density of defect states at the interface between the oxides704aand704band the interface between the oxides704cand704bcan be decreased. Thus, the influence of interface scattering on carrier conduction is small, and the memory transistor MT can have a high on-state current. Note that the details of the metal oxide that can be used as the oxide704are described later. FIG.39Ais the enlarged view of the memory transistor MT surrounded by dashed-dotted line791inFIG.37. As illustrated inFIG.39A, the oxide704bis sandwiched between the oxides704aand704c. In such a structure, carriers mainly flow in the component having a narrow gap when the carriers flow in the oxide704from the conductor705toward the conductor706or from the conductor706toward the conductor705. Thus, with the above structure, the oxide704bwhich is a narrow gap is sandwiched between the oxides704aand704cwhich are wide gaps, whereby carriers flowing through the oxide704can be confined in the oxide704b. This enables high current drive capability in the on state of the transistor, i.e., high on-state current and high field-effect mobility. The oxide704ais provided between the oxide704band the insulator703c, whereby the oxide704bthat serves as a carrier path and the insulator703care not in contact with each other, so that the formation of trap centers can be suppressed. The trap centers formed at the interface between the semiconductor (oxide semiconductor) and the insulator trap electrons and cause the threshold voltage of the transistor to shift in the positive direction, which might adversely affect the reliability and the on-off characteristics of the transistor. Thus, a transistor using the oxide does not affect electrical characteristics due to the trap centers. This enables higher current drive capability in the on state of the transistor, i.e., higher on-state current and higher field-effect mobility. Furthermore, the transistor and a semiconductor device including the transistor can have high reliability. To provide the low-resistance regions in the oxide704, the insulator719serving as a mask of the oxide704is preferably provided. The insulator719is provided on the side surfaces of the conductors701and702with the insulator703and the oxide704provided therebetween. The details thereof will be described later. The diameter of the opening formed in the conductors701and702is larger than the diameter of the opening formed in the insulators721,722, and724, and the insulator719is provided only in the same layers as the conductors701and702. Thus, the oxide704includes a region covered with the insulator719. When treatment for reducing resistance is performed on the oxide704that is not covered with the insulator719, the region731serving as the low-resistance region is formed in the oxide704. Examples of the treatment for reducing resistance include a method for injecting a specific element of a rare gas such as argon, hydrogen, nitrogen, a metal, or the like, and a method for extracting oxygen from the oxide704. In the case where a specific element is injected to the oxide704, plasma treatment, ion implantation treatment, ion doping treatment, or the like in an atmosphere containing the element can be used. The plasma treatment can be performed with an etching apparatus or a CVD apparatus. In addition, by using what is called reverse sputtering treatment using a sputtering apparatus, the element can be injected into the oxide704. In order to selectively reduce the resistance of the oxide704, at least one of metal elements that increase conductivity of the oxide704, such as aluminum, ruthenium, titanium, tantalum, tungsten, chromium, and indium, and an impurity is added to a desired region. As the impurity, the element that forms an oxygen vacancy, the element trapped by an oxygen vacancy, or the like may be used. Typical examples of the element are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas element. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon. As described above, when the content of the metal element that increases conductivity, the element that forms an oxygen vacancy, and the element trapped by an oxygen vacancy in the region731is increased, the carrier density is increased and the resistance can be reduced. For example, the resistance of the oxide semiconductor in the region731can be reduced by injecting impurities such as a rare gas into the region731by plasma treatment, ion implantation treatment, ion doping treatment, reverse sputtering treatment, or the like using the insulator719as a mask. Note that in this specification and the like, the reverse sputtering treatment refers to treatment in which voltage is applied to the substrate side with the use of a radio frequency (RF) power source and plasma is generated in the vicinity of the substrate to modify the substrate surface. The reverse sputtering treatment is preferably performed in such a manner that an inert gas (e.g., a rare gas such as argon or helium, nitrogen, or the like) is introduced into the treatment chamber. For the addition of the impurities such as a rare gas, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. In the case of performing mass separation, ion species to be added and its concentration can be adjusted properly. On the other hand, in the case of not performing mass separation, ions at a high concentration can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be employed. Note that the impurities and the metal elements to be added may be referred to as an element, dopant, ion, donor, acceptor, or the like. In order to reduce the resistance of the region731, for example, a metal film, an oxide film containing a metal element, a nitride film containing a metal element, or the like may be formed in contact with the region731of the oxide704. Specifically, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element is preferably provided in contact with the region731which is not covered with the insulator719. When the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is formed in contact with the region731of the oxide704, a metal element is diffused from the film into the region731of the oxide704and a metal compound is formed in the region731, whereby the resistance of the region731is reduced. Some oxygen in the oxide704at and near an interface between the region731and the metal film, the oxide film containing a metal element, or the nitride film containing a metal element may be absorbed by the film and an oxygen vacancy may be formed in the region731, so that the resistance of the region731may be reduced. Note that the regions of the oxide in which the resistance is reduced are not limited to the region731in this specification and the drawings regardless of the method of reducing resistance. The resistance of part of the region732may be reduced. The resistances of all of the layers included in the oxide704, which are the oxides704a,704b, and704c, do not need to be reduced, and the resistance of at least the oxide704b, which serves as a carrier path, need to be reduced. For example, the resistance of only the oxides704cand704bmay be reduced. Heat treatment is preferably performed in an atmosphere containing nitrogen in a state where the region731and the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is in contact with each other. By the heat treatment, the metal element is diffused from the metal film, the nitride film containing the metal element, or the oxide film containing the metal element into the region731of the oxide704; thus, the metal element can be added to the region731. At this time, the region731of the oxide704may be alloyed with the metal element. When the region731of the oxide704is alloyed with the metal element, the metal element added to the oxide semiconductor becomes relatively stable; therefore, a highly-reliable semiconductor device can be provided. If hydrogen in the oxide704diffuses into a region731and enters an oxygen vacancy in the region731, the hydrogen becomes relatively stable. Hydrogen in an oxygen vacancy in the region734is released from the oxygen vacancy by heat treatment at 250° C. or higher, diffuses into the region731, enters an oxygen vacancy in the region731, and becomes relatively stable. Thus, the resistance of the region731is further reduced, and the region734is purified (impurities such as water or hydrogen therein are reduced) and the resistance of the region734is increased. In contrast, the addition of the metal element to the regions of the oxide704(the region734and the region732) covered with the insulator719is suppressed because the insulator719is provided between the regions and the conductor702. Furthermore, absorption of oxygen atoms in the regions734and732of the oxide704by the above-described metal film, nitride film containing a metal element, or oxide film containing a metal element is suppressed. In the case where the metal film, the nitride film containing a metal element, or the oxide film containing a metal element has a property of absorbing hydrogen, hydrogen in the oxide704is absorbed by the film. Accordingly, hydrogen, which is an impurity in the oxide704, can be reduced. In a later step, the metal film, the nitride film containing a metal element, or the oxide film containing a metal element may be removed together with hydrogen absorbed from the oxide704. The metal film, the oxide film containing a metal element, or the nitride film containing a metal element is not necessarily removed. In the case where the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is oxidized by oxygen absorbed from the oxide704to be a high-resistant insulator, for example, the film may remain. In that case, the film may serve as a second gate insulating layer like the insulator711. In the case where a region having conductivity remains in the metal film, the oxide film containing a metal element, or the nitride film containing a metal element, for example, the region having conductivity is oxidized by heat treatment, so that the region becomes a high-resistant insulator. The heat treatment is preferably performed in an oxidation atmosphere, for example. In the case where a structure body containing oxygen is provided in the vicinity of the metal film, the oxide film containing a metal element, or the nitride film containing a metal element, by heat treatment, the metal film, the oxide film containing a metal element, or the nitride film containing a metal element may be reacted with oxygen contained in the structure body and oxidized. The metal film, the oxide film containing a metal element, or the nitride film containing a metal element can serve as a second gate insulating film like the insulator711when the film remains as an insulator. For example, the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is preferably formed to have a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm, further preferably greater than or equal to 1 nm and less than or equal to 2 nm. When aluminum having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm is oxidized by heat treatment, for example, aluminum oxide having a thickness of greater than or equal to 0.7 nm and less than or equal to 8 nm may be formed. Note that in the case where heat treatment is performed in the above oxidation atmosphere, such heat treatment is preferably performed after carrying out another heat treatment in which the oxide704is in contact with the metal film, the oxide film containing a metal element, or the nitride film containing a metal element in an atmosphere containing nitrogen. The heat treatment is performed in an atmosphere containing nitrogen once, in which case the oxygen in the oxide704is easily diffused into the metal film, the oxide film containing a metal element, or the nitride film containing a metal element. A memory transistor and a selection transistor formed using an oxide semiconductor is likely to have its electrical characteristics changed by impurities and oxygen vacancies in a channel formation region in the oxide semiconductor; as a result, the reliability is reduced, in some cases. Moreover, if the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor tends to have normally-on characteristics. Thus, oxygen vacancies in the region734where a channel is formed are preferably reduced as much as possible. The insulator719is preferably formed using a material that can supply oxygen to the oxide704, in which case the generation of oxygen vacancies can be suppressed or oxygen vacancies can be compensated in the region734. In the case where the conductor712is provided, a material similar to that of the conductor701can be used for the conductor712. Since the conductor712needs to be formed in the opening having a large aspect ratio (in other words, the recession of the oxide704and the insulator711), the conductor712is preferably formed by a CVD method, an ALD method, or a plating method. In that case, the insulator711can be formed using a material similar to that used for the insulator703. In the case where the insulator711is provided on the inner side of the oxide704c, the insulator711is preferably formed using a material that can supply oxygen to the oxide704or a material that can supply impurities, such as hydrogen and nitrogen. When an oxide that contains hydrogen and nitrogen as little as possible is used for the insulator711, oxygen can be supplied to the oxide704in some cases. By supplying oxygen to the oxide704, impurities such as hydrogen and water contained in the oxide704can be removed and the oxide704is highly purified. When an oxide which contains impurities as little as possible is used as the oxide704, the memory transistor MT and the semiconductor device including the memory transistor MT can have high reliability. When an oxide containing hydrogen and nitrogen is used for the insulator711, hydrogen and nitrogen can be supplied to the oxide704in some cases. When hydrogen and nitrogen are supplied to the oxide704, the resistance of the oxide704might be decreased. The resistance of the oxide704is decreased such that it does not hinder the circuit operation, whereby the memory transistor MT can operate with lower driving voltage. This enables high current drive capability in the on state of the memory transistor MT, i.e., high on-state current and high field-effect mobility. Note that the top-view shape of the opening formed in the stack provided with the memory transistor MT is, but not limited to, circular as illustrated inFIG.38Aand the like; the top-view shape can alternatively be, for example, elliptic or polygonal, e.g., a triangle or a quadrangle. In the case where a polygonal shape is employed, corners thereof may be rounded. The top-view shapes of the insulator703and the oxide704may change depending on the top-view shape of the opening. The opening may have a shape where a lower cross section (on the conductor706side) is smaller than an upper cross section (on the conductor705side). The memory transistor MT is formed by the oxide704, the insulator703, and the conductor701(any one of the conductors701_1to701_m).FIG.37andFIGS.38A and38Bshow an example in which m stages of memory transistors MT (m is a natural number of 2 or more) are stacked. Note that inFIG.37andFIGS.38A and38B, four or more stages of the conductors701are illustrated to show a plurality of conductors701; however, this embodiment is not limited toFIG.37and at least two stages of the conductors701are provided. The conductor705is electrically connected to the oxide704and serves as part of the source line SL or part of the bit line BL. The conductor705is preferably formed using a conductive material containing a metal element. Alternatively, a conductive material among materials that can be used for the metal film, the oxide film containing a metal element, or the nitride film containing a metal element can be used for the conductor705. In that case, the resistance of part of the oxide704is reduced as described above. A metal compound layer including the metal element contained in the conductor705and the component of the oxide704is preferably formed at the interface between the conductor705and the oxide704. The metal compound layer is preferably formed, in which case the contact resistance between the conductor705and the oxide704can be reduced. Alternatively, oxygen contained in the oxide704is absorbed by the conductor705and the resistance of the oxide704in the vicinity of the interface between the conductor705and the oxide704is reduced, whereby the contact resistance between the conductor705and the oxide704can be reduced. It is preferable that the conductor705be formed using a conductive material containing one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, chromium, tungsten, and copper. As illustrated inFIG.38B, the conductor706electrically connects the oxide704electrically connected to the conductor705which serves as part of the bit line BL to the oxide704electrically connected to the conductor705serving as part of the source line SL, so that the memory string is formed. A region surrounded by a dotted line inFIG.38Arepresents a memory string. In other words,FIG.38Aillustrates a memory cell array700including four memory strings. The conductor706can be formed using a material similar to that used for the conductor705. Alternatively, a conductive material among materials that can be used for the metal film, the oxide film containing a metal element, or the nitride film containing a metal element can be used for the conductor706. In that case, the resistance of part of the oxide704is reduced as described above. The conductor706can be formed using the same material as the conductor705or a different material from that of the conductor705. A metal compound layer including the metal element contained in the conductor706and the component of the oxide704is preferably formed at the interface between the conductor706and the oxide704. The metal compound layer is preferably formed, in which case the contact resistance between the conductor706and the oxide704can be reduced. Alternatively, oxygen contained in the oxide704is absorbed by the conductor706and the resistance of the oxide704in the vicinity of the interface between the conductor706and the oxide704is reduced, whereby the contact resistance between the conductor706and the oxide704can be reduced. The conductors707,708,709,710,714, and715can be formed using a material that can be used for the conductor701,702, or712. The conductors may be formed using the same material or different materials. (Memory Cell Array700A) FIG.40is a top view illustrating a memory cell array700A in which a plurality of memory cell arrays700each including six stages of memory transistors MT are combined. Note that inFIG.40, some components are not illustrated for simplicity. For example, the selection transistor (the transistor on the bit line side (SDT) and the transistor on the source line side (SST)) provided over the conductor701and the conductor702which is the component of the selection transistor are not illustrated. In addition, the conductor705serving as part of the bit line BL and the source line SL, the conductor708serving as part of the word line WL, and the conductor715serving as part of the wiring BG electrically connected to the conductor712serving as a second gate are shown by solid lines. In the memory cell array700A, each memory cell array700includes four memory strings including six stages of memory transistors MT. The ends of the memory strings on the bit line side are electrically connected to the respective bit lines BL (BL_1to BL_4). The ends of the memory strings on the source line side are electrically connected to the source line SL and are supplied with a common potential. The source line SL may be grounded or may be supplied with a constant potential. Alternatively, the potential may be changed depending on the operation of the circuit. The conductors701_1to701_6are electrically connected to the respective word lines WL. The conductors701_1to701_6on the bit line side are electrically connected to WLa_1to WLa_6, respectively, and the conductors701_1to701_6on the source line side are electrically connected to WLb_1to WLb_6, respectively. The conductors712are electrically connected to the wirings BG. AlthoughFIG.40shows an example where the conductors712aligned in the column direction are electrically connected to the common wiring BG, the present invention is not limited to this example. The conductors712aligned in the row direction may be electrically connected to the common wiring BG. Different potentials may be applied to the wirings BG. Alternatively, the same potential may be applied to the plurality of wirings BG. In this case, the plurality of wirings BG are preferably electrically connected to each other. The plurality of wirings BG may refer to all the wirings BG included in the memory cell array700A. In order that a given potential is applied to the wiring BG, the wiring BG is preferably electrically connected to a circuit that controls the potential of the wiring BG (also referred to as a BG driver or a BG driver circuit, or simply referred to as a driver or a driver circuit). The BG driver circuit may be provided for each of the wirings BG or the plurality of wirings BG may be electrically connected to one BG driver circuit. For example, the memory cell array700A may include one BG driver circuit and all the wirings BG included in the memory cell array700A may be electrically connected to the BG driver circuit. By appropriately selecting the bit line BL (from BL_1to BL_4) and the word line WL (from WLa_1to WLa_6and WLb_1to WLb_6), a given memory transistor MT in the memory cell array700can be selected. In addition, writing, reading, erasing, and the like can be performed on the selected memory transistor MT. Since the selection transistor (not illustrated) is provided in each memory string, the given memory cell array700in the memory cell array700A can be selected, and writing, reading, erasing, and the like can be performed on the given memory transistor MT in the selected memory cell array700. (Structure Example of Memory Device750) FIG.41illustrates a structure example of a memory device750in which the memory cell array700A is stacked over a circuit300. As illustrated inFIG.41, the memory cell array700A is stacked over a region where the circuit300including a transistor301, a transistor302, and a transistor303is formed. The transistor301and the transistor302are included in a sense amplifier304and the transistor303functions as a column selection switch. Specifically, the bit line BL of the memory cell array700A is electrically connected to one of a source and a drain of the transistor301, a gate of the transistor301is electrically connected to one of a source and a drain of the transistor302, and a gate of the transistor302is electrically connected to the other of the source and the drain of the transistor301. The one of the source and the drain of the transistor301and the other of the source and the drain of the transistor302are electrically connected to one of a source and a drain of the transistor303which functions as the column selection switch. Accordingly, the layout area of the memory device750can be reduced. Note thatFIG.41illustrates an example where 10 stages of memory transistors MT are provided and one memory string includes 20 memory transistors MT. However, the number of stages of stacked memory transistors MT is not limited thereto. For example, 32 stages of memory transistors, 64 stages of memory transistors, 128 stages of memory transistors, or 200 or more stages of memory transistors may be stacked. The bit line BL of the memory cell array700A is electrically connected to the sense amplifier304and the transistor303functioning as the column selection switch through the conductor752formed to be embedded in an insulator726, the insulator722, and the like. Note that circuits and transistors included in the circuit300are examples and the circuit configurations and the transistor structures are not limited to these examples. In addition to the above, an appropriate circuit or transistor can be provided in accordance with the component of the memory device750such as a control circuit, a row decoder, a row driver, a source line driver, or an input-output circuit, or the driving method thereof. The transistors301,302, and303are provided over a substrate311and each include a conductor316, an insulator315, a semiconductor region313that is a part of the substrate311, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. Note that as illustrated inFIG.41, one low-resistance region may be used in common for a source region or a drain region of one of the transistors301and302and a source region or a drain region of the other of the transistors301and302. In each of the transistors301,302, and303, the semiconductor region313(part of the substrate311) in which a channel is formed has a protruding portion. Furthermore, the conductor316is provided so as to cover the top and side surfaces of the semiconductor region313with the insulator315positioned therebetween. Note that the conductor316may be formed using a material for adjusting the work function. The transistors301,302, and303are also referred to as FIN transistors because they each utilize a protruding portion of the semiconductor substrate. An insulator functioning as a mask for forming the protruding portion may be provided in contact with the top surface of the protruding portion. Although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate. Although each of the transistors301,302, and303may be either a p-channel transistor or an n-channel transistor, the transistors301and302are preferably transistors having different polarities. It is preferable that a region of the semiconductor region313where a channel is formed, a region in the vicinity thereof, the low-resistance regions314aand314bfunctioning as the source and drain regions, and the like contain a semiconductor such as a silicon-based semiconductor, further preferably single crystal silicon. Alternatively, a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be contained. Silicon whose effective mass is adjusted by applying stress to the crystal lattice and thereby changing the lattice spacing may be contained. Alternatively, the transistors301,302, and303may each be a high-electron-mobility transistor (HEMT) with GaAs and GaAlAs, or the like. The low-resistance regions314aand314bcontain an element which imparts n-type conductivity, such as arsenic or phosphorus, or an element which imparts p-type conductivity, such as boron, in addition to the semiconductor material used for the semiconductor region313. The insulator315serves as a gate insulating film of each of the transistors301,302, and303. The conductor316functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or using a conductive material such as a metal material, an alloy material, or a metal oxide material. Note that since the work function of a conductor depends on a material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like for the conductor. Furthermore, in order to ensure the conductivity and embeddability, it is preferable to use a stacked layer of metal materials such as tungsten and aluminum for the conductor. It is particularly preferable to use tungsten in terms of heat resistance. An insulator317functioning as an etching stopper is preferably provided over the conductor316. In addition, an insulator318functioning as a spacer is preferably provided on the side surface of the insulator315. When the insulator317and the insulator318are provided, regions where the low-resistance regions314aand314band the conductor328are electrically connected to each other can be defined in a self-aligned manner. Thus, even when misalignment occurs in forming the openings for exposing part of the low-resistance regions314aand314b, the openings for exposing the intended regions can be formed. The conductor328provided in the openings formed in this manner can provide a favorable contact with reduced contact resistance between the low-resistance regions314aand314band the conductor328. The contact between the low-resistance regions314aand314bformed in this manner and the conductor328may be referred to as a self-aligned contact. Furthermore, the conductor329electrically connected to the conductor316so as to be embedded in the insulators317and322may be provided. An insulator320, an insulator322, an insulator324, an insulator326, and an insulator327are stacked in this order to cover the transistor301, the transistor302, and the transistor303. The insulator320, the insulator322, the insulator324, the insulator326, and the insulator327can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride. The insulator322may function as a planarization film for eliminating a level difference caused by the transistor301or the like underlying the insulator322. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity. The insulator324is preferably formed using a film having a barrier property that prevents hydrogen or impurities from the substrate311, the transistor301, or the like from diffusing to a region where the memory cell array700A is provided. For the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used, for example. The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the memory transistor MT, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the memory transistor MT and the transistor301or the like. The film that prevents hydrogen diffusion is specifically a film from which a small amount of hydrogen is released. The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator324that is converted into hydrogen atoms per unit area of the insulator324is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2, in the TDS analysis at a film surface temperature of the insulator324of higher than or equal to 50° C. and lower than or equal to 500° C., for example. Note that the permittivities of the insulators326and327are preferably lower than that of the insulator324. For example, the relative permittivities of the insulators326and327are preferably lower than 4, further preferably lower than 3. The relative permittivities of the insulators326and327are, for example, preferably 0.7 or less times that of the insulator324, further preferably 0.6 or less times that of the insulator324. In the case where a material with a low permittivity is used for an interlayer film, the parasitic capacitance between wirings can be reduced. The conductor328, the conductor329, the conductor330, and the like that are electrically connected to the memory cell array700A are provided in the insulator320, the insulator322, the insulator324, the insulator326, and the insulator327. Note that the conductors328,329, and330each function as a plug or a wiring. A plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and another part of the conductor functions as a plug. As a material for each of plugs and wirings (e.g., the conductors328,329, and330), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance. A wiring layer may be provided over the insulator327and the conductor330. For example, inFIG.41, an insulator350, an insulator352, and an insulator354are stacked sequentially. Furthermore, a conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring. Note that the conductor356can be formed using a material similar to those for the conductors328,329, and330. Note that the insulator350is preferably formed using an insulator having a barrier property against hydrogen, as with the insulator324, for example. Furthermore, the conductor356preferably contains a conductor having a barrier property against hydrogen. In particular, the conductor having a barrier property against hydrogen is formed in an opening of the insulator350having a barrier property against hydrogen. In such a structure, the transistor301and the like and the memory transistor MT can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor301and the like to the memory transistor MT can be prevented. Note that as the conductor having a barrier property against hydrogen, tantalum nitride is preferably used, for example. The use of a stack including tantalum nitride and tungsten having high conductivity can inhibit the diffusion of hydrogen from the transistor301and the like while the conductivity of a wiring is ensured. In that case, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator350having a barrier property against hydrogen. A wiring layer may be provided over the insulator354and the conductor356. For example, inFIG.41, an insulator360, an insulator362, and an insulator364are stacked sequentially. Furthermore, a conductor366is formed in the insulator360, the insulator362, and the insulator364. The conductor366functions as a plug or a wiring. Note that the conductor366can be formed using a material similar to those for the conductors328,329, and330. Note that the insulator360is preferably formed using an insulator having a barrier property against hydrogen, as with the insulator324, for example. Furthermore, the conductor366preferably contains a conductor having a barrier property against hydrogen. In particular, the conductor having a barrier property against hydrogen is formed in an opening of the insulator360having a barrier property against hydrogen. In such a structure, the transistor301and the like and the memory transistor MT can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor301and the like to the memory transistor MT can be prevented. The insulator722is provided over the insulator364and the conductor366, and the memory cell array700A is provided above the insulator722. A barrier film formed using a material similar to that of the insulator324may be provided between the insulator364and the insulator722. FIG.41illustrates an example of the memory cell array700A including the U-shaped memory string in which the two columnar oxides704are electrically connected to each other through the conductor706; however, the present invention is not limited to this example. InFIG.42, in the columnar oxide704including 8 stages of memory transistors MT and the two selection transistors (SDT and SST), the lower end of one columnar oxide704is electrically connected to a conductor705B functioning as the bit line BL and the upper end thereof is electrically connected to a conductor705S functioning as the source line SL. That is, one memory string is formed of one columnar oxide704. Although the conductor705B is electrically connected to the lower ends of four columnar oxides inFIG.42, the present invention is not limited thereto. One conductor705B may be electrically connected to one columnar oxide704, or one conductor705B may be electrically connected to two or more columnar oxides704. The conductor705S is electrically connected to upper ends of two columnar oxides; however, the present invention is not limited thereto. One conductor705S may be electrically connected to one columnar oxide704, or one conductor705S may be electrically connected to two or more columnar oxides704. The selection transistor SDT is provided between the conductor705B and the memory transistor MT and the selection transistor SST is provided between the conductor705S and the memory transistor MT. Such a structure in which the conductor705B serving as the bit line BL is electrically connected to the circuit300provided under the conductor705B is preferably used, in which case the number of wirings (lead wirings) and plugs for electrically connecting the memory cell array700A to the circuit300can be reduced and the layout area of the memory device750can be reduced. Note that inFIG.42, 8 stages of the memory transistors MT are stacked; however, the present invention is not limited thereto. The number of stages of memory transistors MT may be greater than or equal to 2 and less than or equal to 7, or may be greater than or equal to 9. For example, 32 stages of memory transistors, 64 stages of memory transistors, 128 stages of transistors, or 200 or more stages of memory transistors may be stacked. The metal oxide described in Embodiment 1 can be referred to for a metal oxide that can be used as the oxide704in the present invention. (A Method for Manufacturing Memory Cell) Next, one embodiment of a method for manufacturing a memory transistor MT that functions as a memory cell of the present invention is described with reference toFIGS.43A to43CtoFIGS.48A and48B. Note thatFIGS.43A to43CtoFIGS.48A and48Bare cross-sectional views illustrating a manufacturing process of the memory transistor MT. First, as illustrated inFIG.43A, the conductors701and the insulators722are alternately stacked. Then, as illustrated inFIG.43B, the conductors701and the insulators722are processed to form an opening with a diameter of φ1 in the conductors701and the insulators722. Next, as illustrated inFIG.43C, the conductors701are subjected to isotropic etching to increase the opening diameter of the conductors701. At this time, the diameter of the opening is φ2 (>φ1). In this case, it can be said that the conductor701is more recessed than the side surfaces of the insulators722between which the conductor701is sandwiched. Next, as illustrated inFIG.44A, the insulator703and the oxide704are formed in the opening. Although not illustrated inFIG.44A, the insulator703is formed by stacking the insulators703a,703b, and703cin this order. The oxide704is formed by stacking the oxides704a,704b, and704cin this order. Before the oxide704is formed, the insulator703in the bottom portion of the opening is preferably removed. The insulator703and the oxide704are formed with good coverage even on the recession of the conductor701, and the insulator703ais formed in contact with the side surface of the conductor701and the side surface, part of the top surface, and part of the bottom surface of the insulator722. Next, as illustrated inFIG.44B, an insulating film719A is formed in the opening. The insulating film719A is formed to fill the recession with the insulator703and the oxide704provided between the insulating film719A and the conductor701. However, the present invention is not limited thereto. The insulating film719A may be formed to fill not only the recession but also the whole opening. Next, the insulating film719A is processed to form the insulator719. The processing of the insulating film719A can be performed by isotropic etching or anisotropic etching. In the case where the insulating film719A fills the recession and does not completely fill the opening as illustrated inFIG.44B, the insulating film719A is preferably processed by isotropic etching. In contrast, in the case where the insulating film719A is formed to fill the recession and the opening, it is preferable to use anisotropic etching. By such processing, the insulator719can be formed in the recession (seeFIG.44C). Next, as illustrated inFIGS.45A and45BandFIGS.46A and46B, a low-resistance region is formed in part of the oxide704using the insulator719as a mask.FIG.45Bis an enlarged view of a portion surrounded by dashed-dotted line inFIG.45A.FIG.45Ashows an example in which argon is added to the region731of the oxide704by argon plasma to reduce the resistance. The element which is added by the treatment shown inFIG.45Ais not limited to the above example. Other than argon, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, helium, neon, krypton, xenon, or the like may be added thereto. Furthermore, a metal element that improves the conductivity of the oxide704, such as aluminum, ruthenium, titanium, tantalum, tungsten, chromium, or indium, may be added. The plasma treatment can be performed with an etching apparatus or a CVD apparatus. The treatment for adding the element is not limited to the plasma treatment and can be ion implantation treatment, ion doping treatment, reverse sputtering treatment using a sputtering apparatus, or the like. In addition,FIGS.46A and46Billustrate an example in which a film718including a metal film, an oxide film containing a metal element, or a nitride film containing a metal element is formed in contact with the region731of the oxide704to reduce the resistance of the region731. As illustrated inFIG.46A, the film718is formed, and heat treatment is performed as needed, whereby the resistance of the region731of the oxide704is reduced. After the resistance of the region731is reduced, the film718may be removed as illustrated inFIG.46B. Note thatFIG.45Bcorresponds to a portion surrounded by dashed-dotted line inFIG.46B. The metal film, the oxide film containing a metal element, or the nitride film containing a metal element is not necessarily removed. The film may remain in the following case: the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is an insulator or is oxidized by oxygen absorbed from the oxide704to be a high-resistant insulator, for example. In that case, the film may serve as a second gate insulating layer like the insulator711. The film718preferably has at least one of a function of supplying hydrogen to the oxide704, a function of supplying nitrogen to the oxide704, and a function of extracting oxygen from the oxide704. The film718having such a function is in contact with the oxide704, whereby carriers are generated in the oxide704. Specifically, oxygen is extracted from the oxide704, whereby oxygen vacancies are generated in the oxide704. When hydrogen is trapped by these oxygen vacancies, carriers are generated. Alternatively, in the case where nitrogen is trapped by these oxygen vacancies, nitrogen is substituted for oxygen bonded to two indium atoms. When nitrogen is bonded to these two indium atoms, it is probable that nitrogen has an unpaired electron and serves as a carrier. As the material having a function of supplying hydrogen to the oxide704, silicon nitride containing hydrogen can be used. Furthermore, a material formed using a gas containing hydrogen when the material is formed can be used. For example, silicon, silicon oxide, silicon oxynitride, silicon nitride oxide, or the like formed using monosilane, disilane, ammonia, or the like can be used. As the material having a function of supplying nitrogen to the oxide704, a nitride containing silicon or a metal element can be used. As such a material, silicon nitride, silicon nitride oxide, silicon oxynitride, or the like can be used. Alternatively, a nitride containing one or more of aluminum, tantalum, and titanium can be used. Specifically, aluminum nitride, tantalum nitride, titanium nitride, a nitride containing aluminum and tantalum, a nitride containing aluminum and titanium, or the like can be used. For example, the film718is preferably formed to have a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm, further preferably greater than or equal to 1 nm and less than or equal to 2 nm. When aluminum having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm is oxidized by heat treatment, for example, aluminum oxide having a thickness of greater than or equal to 0.7 nm and less than or equal to 8 nm may be formed. Note that in the case where heat treatment is performed in the above oxidation atmosphere, such heat treatment is preferably performed after carrying out another heat treatment in which the oxide704is in contact with the metal film, the oxide film containing a metal element, or the nitride film containing a metal element in an atmosphere containing nitrogen. The heat treatment is performed in an atmosphere containing nitrogen once, in which case the oxygen in the oxide704is easily diffused into the metal film, the oxide film containing a metal element, or the nitride film containing a metal element. After the film718containing any one of a metal element, hydrogen, and nitrogen is provided in contact with the oxide704, heat treatment is preferably performed. The heat treatment is performed, whereby extraction of oxygen, supply of hydrogen, or supply of nitrogen is promoted, and the resistance of part of the oxide704can be efficiently reduced. As described above, when a low-resistance region is provided in the oxide704, in the memory string or memory cell array where the memory cells are stacked, the series resistance between the memory cells can be reduced. Next, the insulator711is formed on the inner side of the oxide704and the insulator719, and the conductor712is formed on the inner side of the insulator711(seeFIG.47A). Note that the conductor712is not necessarily provided, and the inside of the oxide704may be filled with the insulator711. In addition,FIG.47Bis an enlarged view of a portion surrounded by dashed-dotted line inFIG.47A, and illustrates a cross section of the conductor701_k−1 and the insulator722_k−1 in the k−1-th stage, the conductor701_kand the insulator722_kin the k-th stage, and the conductor701_k+1 in the k+i-th stage (k is an integer of 2 or more and m−1 or less). Next, heat treatment may be performed. Through the heat treatment, oxygen is supplied from the insulator719to the oxide704. In addition, impurities such as hydrogen are removed from the region734, so that the region734is highly purified and the resistance of the region734is increased. The region732(the regions732aand732b) positioned between the region731and the region734serves as a junction region. The resistance of the region732is preferably lower than that of the region734. Furthermore, the resistance of the region732may be substantially equal to or higher than that of the region731. The region734of the oxide704serves as a channel formation region of the memory transistor MT. The region731aserves as one of a source and a drain of the memory transistor MT and the region731bserves as the other. The conductor701_kserves as a first gate of the memory transistor MT, the conductor712serves as a second gate, the insulator703aserves as the first gate insulating layer, the insulator703bserves as a charge accumulation layer, the insulator703cserves as a tunnel insulating layer, and the insulator711serves as the second gate insulating layer. Note that the source or the drain of the memory transistor MT in which the conductor701_kserves as a gate may serve as a drain or a source in the transistor positioned over or under the memory transistor MT. For example, when the region731bserves as a source of a transistor in which the conductor701_kserves as a gate, the region731bmay serve as a drain of a transistor in which the conductor701_k+1 serves as a gate. Through the above steps, the memory transistor MT functioning as a memory cell can be formed. By the above method, the memory transistors MT in a plurality of layers can be formed at a time without performing patterning for forming the memory transistors MT for each layer. Furthermore, in the case where a memory cell array is formed by the above method, even when the number of layers of the memory transistors MT is increased, the number of steps of patterning and etching of the memory transistors MT is not increased. In this manner, the number of manufacturing steps of the memory cell array can be reduced; thus, a semiconductor device with high productivity can be provided. FIG.48Aillustrates another example of the conductor701. InFIG.48A, the conductor701has a three-layer structure of a conductor701c, a conductor701d, and a conductor701e. The conductor701dis more recessed than the side surfaces of the conductors701cand701e, and the conductor701is provided to surround the side surfaces, top surfaces, and bottom surfaces of the region734and the region732of the oxide704with the insulator703provided therebetween. Such a shape is preferably used, in which case an electric field from the conductor701can be applied to not only the region734but also the region732, and the on-state characteristics of the memory transistor MT is improved. To make the conductor701dto be more recessed than the side surfaces of the conductors701cand701e, a material or etching conditions with which the etching rate of the conductor701din the isotropic etching is higher than those of the conductors701cand701eare used. For example, in the conditions where the conductor701dis formed using tungsten and the conductors701cand701eare formed using conductive materials containing tantalum or titanium, or a nitride thereof, the conductor701dmay be selectively etched using a gas containing chlorine. Alternatively, in the conditions where the conductor701dis formed using aluminum and the conductors701cand701eare formed using a conductive material containing tantalum or titanium, or a nitride thereof, wet etching may be selectively performed on the conductor701d. Alternatively, in the conditions where the conductor701dis formed using a material containing silicon, the conductors701cand701eare formed using a conductive material containing at least one of tantalum, titanium, and tungsten, or a nitride thereof, wet etching may be selectively performed on the conductor701d. FIG.48Billustrates another example of the conductor712. InFIG.48B, the insulator719is removed and the conductor712is provided to fill the region where the insulator719has been provided. With such a shape, an electric field from the conductor712can be effectively applied to the region734and the circuit operation of the memory device can be accurately performed as described later. In addition, the power consumption of the memory device can be reduced. (Method for Manufacturing Memory Cell Array) Next, one embodiment of a method for manufacturing a memory cell array of the present invention is described with reference toFIGS.49A to49CtoFIGS.67A to67C.FIGS.49A,50A,51A,52A,53A,54A,55A,56A,57A,58A,59A,60A,61A,62A,63A,64A,65A,66A, and67Aare top views seen from the z axis direction, andFIGS.49B,50B,51B,52B,53B,54B,55B,56B,57B,58B,59B,60B,61B,62B,63B,64B,65B,66B, and67Bare cross-sectional views taken along dashed-dotted line A1-A2inFIGS.49A,50A,51A,52A,53A,54A,55A,56A,57A,58A,59A,60A,61A,62A,63A,64A,65A,66A, and67A.FIGS.49C,50C,51C,52C,53C,54C,55C,56C,57C,58C,59C,60C,61C,62C,63C,64C,65C,66C, and67Care cross-sectional views taken along dashed-dotted line A1-A2inFIGS.49A,50A,51A,52A,53A,54A,55A,56A,57A,58A,59A,60A,61A,62A,63A,64A,65A,66A, and67A.FIGS.59D and62Dare enlarged cross-sectional views of a portion surrounded by dashed-dotted lines inFIGS.59B and62B, respectively. First, the conductor706is formed over the base720having an insulating surface, and the insulator721is formed to cover the conductor706(seeFIGS.49A to49C). A conductive film is formed and processed by a lithography method, whereby the conductor706is formed. Note that the method for forming the conductor706and the insulator721is not limited thereto. The insulator721may be formed over the base720and an unnecessary portion of the insulator721may be removed to form a groove or an opening, and the conductor706may be embedded in the groove or the opening. A formation method of such a conductor is referred to as a damascene method (a single damascene method or a dual damascene method) in some cases. When an insulating film is further formed over the conductor706formed by the damascene method and the insulator721, the structure illustrated inFIGS.49A to49Ccan be obtained. The conductor706and the insulator721can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The processing can be performed by a dry etching method or a wet etching method. A dry etching method is suitable for microfabrication. As the conductive film to be the conductor706, a conductive film containing a metal element is preferably formed by a sputtering method. Alternatively, the conductive film can be formed by a CVD method. The surface of the insulator721is preferably subjected to planarization treatment as needed. As the planarization treatment, a chemical mechanical polishing (CMP) method or a reflow method can be used. Conductive films701A and insulating films722A are alternately stacked over the conductor706and the insulator721. This embodiment shows an example in which the conductive film701A is formed over the insulator721and the insulating film722A is formed over the conductive film701A; however, the order of the formation is not limited thereto. The insulating film722A may be formed over the insulator721, and the conductive film701A may be formed over the insulating film722A. A CVD method can be used for the formation of the conductive film701A and the insulating film722A. Alternatively, a sputtering method may be used. Although four layers of the conductive films701A and four layers of the insulating films722A are formed in this embodiment, the number of stacked layers is not limited thereto. Five or more layers of the conductive films701A and the insulating films722A may be formed depending on the required performance of a semiconductor device. For example, the number of conductive films701A and the number of insulating films722A may each be 32, 64, 128, or 200 or more. A conductive film702A is formed over the uppermost layer of the insulating film722A. A mask723is formed over the conductive film702A (seeFIGS.50A to50C). The conductive film702A can be formed using a method and a material similar to those of the conductive film701A. Note that the conductive film702A may be formed by the same method as or a method different from that of the conductive film701A. The conductive film702A may be formed using the same material as or a material different from that of the conductive film701A. Next, the conductive film702A, the conductive film701A, and the insulating film722A are processed to form a step-like conductive film701B, a conductive film702B, and an insulating film722B illustrated inFIG.51B. In the processing of the conductive film702A, the conductive film701A, and the insulating film722A, etching of the conductive film702A, the conductive film701A, and the insulating film722A and slimming of the mask723are alternately performed, whereby the step-like conductive film701B, the conductive film702B, and the insulating film722B can be formed. By the processing of the conductive film702A, the conductive film701A, and the insulating film722A, the mask723is reduced in width and thickness to be a mask723A (seeFIGS.51A to51C). Then, the mask723A is removed, and the insulator724is formed. The insulator724can be formed by a CVD method. The insulator724is preferably subjected to planarization treatment by a CMP method or a reflow method. A mask725is formed over the insulator724. The mask725is formed over the planarized insulator724, whereby the accuracy of lithography can be improved (seeFIGS.52A to52C). Then, the insulator724, the conductive film702B, the conductive film701B, the insulating film722B, and the insulator721are processed with the mask725. By the processing, the conductor701serving as the gate of the memory transistor MT and electrically connected to the word line, and the conductor702serving as the gate of the selection transistor are formed. In addition, the insulating film722B is processed into the insulator722(seeFIGS.53A to53C). Then, the mask725is removed. Next, the insulator726is formed to be embedded in the portions in the insulator724, the conductive film702B, the conductive film701B, the insulating film722B, and the insulator721, which are removed by the above processing. The insulator726can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulator726may be formed by a combination of an ALD method and a CVD method. The insulator726is preferably subjected to planarization treatment by a CMP method or a reflow method. When the planarization treatment is performed by a CMP method, the insulator726may be polished until the surface of the insulator724is exposed. The insulator724and the insulator726may be polished together. In this case, the thickness of the insulator724becomes small. Next, the insulator724is processed by a lithography method to form first openings so that the conductors701and702are exposed. The first opening is formed to expose each of the conductors701formed in a step-like shape (seeFIGS.54A to54C). Next, the conductor707electrically connected to the conductor701and the conductor709electrically connected to the conductor702are formed to fill the first opening (seeFIGS.55A to55C). The conductors707and709can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the conductors707and709may be formed by a combination of an ALD method and a CVD method. The conductors707and709may each have a stacked-layer structure of a plurality of layers. The conductors707and709can be formed in such a manner that conductive films to be the conductors707and709are formed over the insulator724and in the first opening, and unnecessary portions of the conductive films are removed by CMP and the like. Next, a mask729is formed over the insulator724and the insulator726, the insulator724, the conductor702, the conductor701, the insulator722, and the insulator721are processed by a lithography method, and second openings are formed to expose the conductor706(seeFIGS.56A to56C). Next, the conductors701and702are subjected to isotropic etching to make the diameter of the opening in the conductors701and702large (seeFIGS.57A to57C). By this treatment, the diameter of the opening in the conductors is larger than that of the opening in the insulators721,722, and724. It can be said that the conductors are more recessed than the side surface of the insulator (the insulator721,722, or724) positioned over or under the conductors. Such processing can be performed by isotropic etching using dry etching with a gas, a radical, plasma, or the like, or by isotropic etching using wet etching with a liquid. A liquid used for wet etching may be referred to as an etchant. In the case where isotropic etching is performed using dry etching, a gas, a radical, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. In this embodiment, the isotropic etching is performed without removing the mask729; however, the present invention is not limited to this example. The isotropic etching may be performed after removing the mask729. Next, an insulating film703A to be the insulator703is formed to cover the insulator724, the insulator726, and the mask729, and in the second opening (seeFIGS.58A to58C). Note that, although not illustrated inFIGS.58A to58C, the insulating film703A may be formed by stacking an insulating film to be the insulator703a, an insulating film to be the insulator703b, and an insulating film to be the insulator703cin this order. The insulating film703A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulating film703A may be formed by a combination of an ALD method and a CVD method. The insulating film to be the insulator703a, the insulating film to be the insulator703b, and the insulating film to be the insulator703cmay be formed using the same deposition apparatus or different deposition apparatuses. Note that the insulating film to be the insulator703cis preferably formed to be thinner than the insulating film to be the insulator703a, in which case the insulator703cis thinner than the insulator703a. The insulating film703A formed by the above method can have high coverage and can be formed in the recessions of the conductors701and702. That is, the insulating film703A can be formed in contact with not only the side surfaces of the conductors701and702and the side surfaces of the insulators721,722, and724, but also part of the top surfaces and part of the bottom surfaces of the insulators721,722, and724. Then, the insulating film703A formed on the bottom portion of the second opening is removed, so that the insulator703is obtained. Anisotropic etching is preferably used to remove the insulating film703A. Here, the insulating film703A over the mask729is also removed; thus, the insulator703is provided only on the side wall of the second opening (seeFIGS.59A to59D). The conductor706is exposed again by removing the insulating film703A on the bottom portion of the second opening. Here, as illustrated inFIG.59D, the insulators703band703cof the insulator703that are positioned in the upper portion of the second opening may be removed.FIG.59Dis an enlarged view of a portion surrounded by dashed-dotted line inFIG.59B. First, the material727(also referred to as a sacrifice layer) which can be easily removed in a later step is formed to be embedded in the second opening, and the material727is removed by etching or the like to a desired depth in the second opening. The insulators703cand703bexposed by the etching are removed in this order, whereby only the insulator703acan be used as the insulator703positioned in the horizontal direction (x-y direction) of the conductor702. In this case, the gate insulating film of each of the selection transistors SST and SDT include the insulator703a. After the insulators703cand703bare removed, the material727is removed. Next, an oxide film704A to be the oxide704is formed in the second opening (seeFIGS.60A to60C). The oxide film704A can be formed in such a manner that an oxide film to be the oxide704a, an oxide film to be the oxide704b, and an oxide film to be the oxide704care formed in this order over the mask729and in the second opening. The oxide film704A is formed along the recessions of the conductors701and702with the insulator703provided therebetween. Part of the oxide film704A is formed in contact with the conductor706. The oxide film to be the oxide704a, the oxide film to be the oxide704b, and the oxide film to be the oxide704ccan be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the oxide films may be formed by a combination of an ALD method and a CVD method. Alternatively, the oxide films may be formed using different deposition methods or different deposition apparatuses. Next, the insulating film719A is formed in the second opening (seeFIGS.60A to60C). The insulating film719A is formed to fill at least the recessions of the conductors701and702with the insulator703and the oxide film704A provided therebetween, and does not need to fill the second opening entirely. The insulating film719A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulating film719A may be formed by a combination of an ALD method and a CVD method. Next, the insulating film719A is processed to form the insulator719(seeFIGS.61A to61C). The processing of the insulating film719A can be performed by isotropic etching or anisotropic etching. In the case where the insulating film719A fills the recession and does not completely fill the opening as illustrated inFIGS.60A to60C, the insulating film719A is preferably processed by isotropic etching. In contrast, in the case where the insulating film719A is formed to fill the recession and the opening, it is preferable to use anisotropic etching. By such processing, the insulator719can be formed in the recession. Next, a low-resistance region is formed in part of the oxide film704A using the insulator719as a mask. The low-resistance region is formed by adding an element such as argon, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, helium, neon, krypton, or xenon, or a metal element that improves the conductivity of the oxide704, such as aluminum, ruthenium, titanium, tantalum, tungsten, chromium, or indium to the oxide film704A. As the method for adding the element, the plasma treatment, ion implantation treatment, ion doping treatment, reverse sputtering treatment, or the like can be used. The plasma treatment can be performed with an etching apparatus or a CVD apparatus. The reverse sputtering treatment can be performed with a sputtering apparatus. In this embodiment, argon plasma treatment is used to reduce the resistance of the region731of the oxide film704A (seeFIGS.62A to62D). In addition, as a method for adding the above element to the oxide film704A, a film containing the above element is formed in contact with the region731of the oxide film704A, and heat treatment is performed as needed to reduce the resistance of the region731. By such treatment, the element may be injected to the oxide film704A. in addition, oxygen contained in the oxide film704A is extracted to the film, and carriers may be generated in the oxide film704A. Note that the film is not necessarily removed. In the case where the film is an insulator or is oxidized by oxygen absorbed from the oxide704to be a high-resistant insulator, for example, the film may remain. In that case, the film may serve as a second gate insulating layer like the insulator711. Then, an insulating film711A is formed on the inner side of the oxide film704A and the insulator719, and a conductive film712A is formed on the inner side of the insulating film711A. The insulating film711A and the conductive film712A can be formed by a CVD method or an ALD method. It is particularly preferable to employ an ALD method, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Alternatively, the insulating film711A and the conductive film712A may be formed by a combination of an ALD method and a CVD method (seeFIGS.63A to63C). The insulator711can be formed using a material for supplying oxygen to the oxide704or a material for supplying hydrogen to the oxide704in accordance with the characteristics needed for the memory transistors MT and the semiconductor devices including the memory transistors MT. Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen atmosphere at 200° C. to 500° C. inclusive, preferably 300° C. to 400° C. inclusive. The atmosphere in which heat treatment is performed is not limited to the above atmosphere as long as at least one of nitrogen, oxygen, and argon is contained. The heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric pressure atmosphere. In addition, when the heat treatment is performed in the state where the oxide film704A and the conductor706are in contact with each other, the resistance of the oxide film704A is reduced in some cases. When the oxide film704A is in contact with the conductor706, a metal compound layer including a metal element contained in the conductor706and the component of the oxide film704A are formed at the interface between the conductor706and the oxide film704A in some cases. The metal compound layer is preferably formed, in which case the contact resistance between the conductor706and the oxide film704A can be reduced. Oxygen contained in the oxide film704A is absorbed by the conductor706in some cases. At this time, the resistance of the oxide film704A in the vicinity of the interface between the conductor706and the oxide film704A is reduced, so that the contact resistance between the conductor706and the oxide film704A can be reduced. When the heat treatment is performed in the state where the oxide film704A and the conductor706are in contact with each other, the oxide film704A has lower resistance and the contact resistance between the conductor706and the oxide film704A is further reduced. Next, the mask729and unnecessary portions of the conductive film712A, the insulating film711A, the oxide film704A, the insulator703, and the like, which are portions above the dotted line inFIGS.63B and63C, are removed by a CMP method or the like to obtain the oxide704, the insulator711, and the conductor712(seeFIGS.64A to64C). Note that the above-described heat treatment may be performed after the removal of unnecessary portions of the conductive film712A, the insulating film711A, and the oxide film704A. In the case where the mask729is removed after the formation of the first opening and before the formation of the insulating film703A, the mask729is not necessarily removed in the present step. Next, as illustrated inFIGS.65A to65C, the conductor705serving as part of the bit line BL, the source line SL, and the word line WL is formed. The conductor705is provided to be electrically connected to the oxide704and the conductor707. In the case where the conductor712is provided on the inner side of the oxide704, it is preferable that at least an opening which exposes the conductor712be provided in the conductor705so that the conductor705and the conductor712are electrically separated from each other. In this case, the opening may be provided to expose the insulator711. Part of the oxide704may be exposed. Then, as illustrated inFIGS.66A to66C, the insulator717is formed to cover the conductor705. In the insulator717, an opening which exposes part of the conductor705(the conductor705electrically connected to the oxide704on the bit line side) and the conductor712is provided. In the case where the opening which exposes the conductor712is formed, the diameter of the opening may be larger than that of the opening provided in the conductor705. Since the conductor705includes an opening, the opening which exposes the conductor712can be formed in a self-aligned manner, and a defect such as formation of the opening whose diameter at the bottom portion has an unintentional size and a defect such as displacement of the opening from the conductor712can be prevented. Then, as illustrated inFIGS.67A to67C, the insulator713is formed to cover the conductor705in the opening which is provided in the insulator717and exposes the conductor712. First, an insulating film to be the insulator713is formed over the insulator717by a CVD method or an ALD method, and then anisotropic etching is performed, whereby the insulating film formed at the bottom portion of the opening is removed. At this time, the insulating film over the insulator717is also removed to form the insulator713. The insulating film may be processed by a lithography method. At this time, the insulator713is also provided over the insulator717in some cases. Next, the conductor714and the conductor715that serve as the bit line BL and the wiring BG are formed. Although the conductors714and715are illustrated as different layers inFIGS.67A to67C, the present invention is not limited thereto. The conductor714and the conductor715may be formed as one conductor at a time. When the conductor714and the conductor715are separately formed, a conductive film to be the conductor714is formed over the insulator717to be embedded in the opening in the insulator717, and an unnecessary portion of conductive film is removed by a CMP method or the like, whereby the conductor714can be formed. After that, the conductor715is formed. The conductor715may be formed by a lithography method or a damascene method. At this time, the insulator713is provided on the side surface of the opening formed in the insulator717and the conductor705; thus, the conductor715electrically connected to the conductor712is not electrically connected to the conductor705. When the conductor714and the conductor715are formed at a time, a conductor serving as the conductor714and the conductor715can be formed by forming a conductive film over the insulator717to be embedded in the opening formed in the insulator717and processing the film by a lithography method. Through the above steps, the memory cell array can be manufactured. In the description of this manufacturing process, the memory cell array includes four layers of the memory transistors MT and four memory strings; however, the present invention is not limited thereto. The memory cell may include five or more layers of the memory transistors MT or five or more memory strings. For example, a memory cell array including 32 layers, 64 layers, or 128 layers of the memory transistors MT can be manufactured. Moreover, a memory cell array including 200 or more layers of the memory transistors MT can be manufactured. The memory cell array is manufactured in the above manner, whereby the memory transistors MT in a plurality of layers can be formed at a time without patterning for forming the memory transistors MT for each layer. Furthermore, in the case where a memory cell array is formed by the above method, even when the number of layers of the memory transistors MT is increased, the number of steps of patterning and etching is not increased. In this manner, the number of manufacturing steps of the memory cell array can be reduced; thus, a semiconductor device with high productivity can be provided. The configuration example of 3D NAND in Embodiment 1 can be referred to for the configuration example of 3D NAND in this embodiment. The description of the circuit operation (erasing operation, writing operation, and reading operation) of the memory device in Embodiment 1 can be referred to for the description of the circuit operation of the memory device in this embodiment. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 3 In this embodiment, application examples of the storage device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment can be applied to, for example, storage devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desk-top computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to removable storage devices such as memory cards (e.g., SD cards), USB memories, and solid state drives (SSD).FIGS.68A to68Eschematically illustrate some structural examples of removable storage devices. A packaged memory chip including the semiconductor device described in the above embodiment is used in a variety of storage devices and removable memories, for example. FIG.68Ais a schematic diagram of a USB memory. A USB memory1100includes a housing1101, a cap1102, a USB connector1103, and a substrate1104. The substrate1104is held in the housing1101. For example, a memory chip1105and a controller chip1106are attached to the substrate1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip1105or the like on the substrate1104. FIG.68Bis a schematic external diagram of an SD card, andFIG.68Cis a schematic diagram illustrating the internal structure of the SD card. An SD card1110includes a housing1111, a connector1112, and a substrate1113. The substrate1113is held in the housing1111. For example, a memory chip1114and a controller chip1115are attached to the substrate1113. When the memory chip1114is also provided on the back side of the substrate1113, the capacity of the SD card1110can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate1113. With such a wireless chip, the memory chip1114can read and write data by radio communication between the host device and the SD card1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip1114or the like on the substrate1113. FIG.68Dis a schematic external diagram of an SSD, andFIG.68Eis a schematic diagram illustrating the internal structure of the SSD. An SSD1150includes a housing1151, a connector1152, and a substrate1153. The substrate1153is held in the housing1151. For example, a memory chip1154, a memory chip1155, and a controller chip1156are attached to the substrate1153. The memory chip1155is a work memory of the controller chip1156, and a DRAM chip may be used, for example. When the memory chip1154is also provided on the back side of the substrate1153, the capacity of the SSD1150can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip1154or the like on the substrate1153. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 4 In this embodiment, an AI system in which the semiconductor device of any of the above-described embodiments is used will be described with reference toFIG.69. FIG.69is a block diagram illustrating a structure example of an AI system4041. The AI system4041includes an arithmetic portion4010, a control portion4020, and an input/output portion4030. The arithmetic portion4010includes an analog arithmetic circuit4011, a DOSRAM4012, a NOSRAM4013, an FPGA4014, and a 3D-NAND4015. DOSRAM (registered trademark) stands for “dynamic oxide semiconductor RAM,” which is RAM including a 1T1C (one-transistor/one-capacitor) memory cell. NOSRAM (registered trademark) stands for “nonvolatile oxide semiconductor RAM”, which is RAM including a gain cell (2T or 3T) memory cell. DOSRAM and NOSRAM are each a memory utilizing a low off-state current of a transistor including an oxide in a semiconductor (hereinafter the transistor is referred to as an OS transistor). Hereinafter, a memory device including an OS transistor, such as NOSRAM, is referred to as an OS memory in some cases. The control portion4020includes a central processing unit (CPU)4021, a graphics processing unit (GPU)4022, a phase locked loop (PLL)4023, a static random access memory (SRAM)4024, a programmable read only memory (PROM)4025, a memory controller4026, a power supply circuit4027, and a power management unit (PMU)4028. The input/output portion4030includes an external memory control circuit4031, an audio codec4032, a video codec4033, a general-purpose input/output module4034, and a communication module4035. The arithmetic portion4010can perform neural network learning or neural network inference. The analog arithmetic circuit4011includes an analog/digital (A/D) converter circuit, a digital/analog (D/A) converter circuit, and a product-sum operation circuit. The analog arithmetic circuit4011is preferably formed using an OS transistor. The analog arithmetic circuit4011formed using an OS transistor includes an analog memory and can execute a product-sum operation necessary for the learning and the inference with low power consumption. The DOSRAM4012is a DRAM including an OS transistor which temporarily stores digital data sent from the CPU4021. The DOSRAM4012includes a memory cell including an OS transistor and a read circuit portion including a Si transistor. Because the memory cell and the read circuit portion can be provided in different layers that are stacked, the entire circuit area of the DOSRAM4012can be small. In the calculation with the neural network, the number of input data exceeds 1000 in some cases. In the case where the input data are stored in an SRAM, the input data has to be stored piece by piece because of the circuit area limitation and small storage capacity of the SRAM. The DOSRAM4012has a larger storage capacity than an SRAM because memory cells of the DOSRAM can be highly integrated even in a limited circuit area. Therefore, the DOSRAM4012can efficiently store the input data. The NOSRAM4013is a nonvolatile memory including an OS transistor. The NOSRAM4013consumes less power in writing data than the other nonvolatile memories such as a flash memory, a resistive random access memory (ReRAM), and a magnetoresistive random access memory (MRAM). Furthermore, unlike a flash memory and a ReRAM which deteriorate by data writing, the NOSRAM does not have a limit on the number of times of data writing. Furthermore, the NOSRAM4013can store multilevel data of two or more bits as well as one-bit binary data. The multilevel data storage in the NOSRAM4013leads to a reduction of the memory cell area per bit. Because the NOSRAM4013can store analog data as well as digital data, the analog arithmetic circuit4011can use the NOSRAM4013as an analog memory. The NOSRAM4013can store analog data as it is, and thus a D/A converter circuit and an A/D converter circuit are unnecessary. Therefore, the area of a peripheral circuit for the NOSRAM4013can be reduced. In this specification, analog data refers to data having a resolution of three bits (eight levels) or more. The above-described multilevel data might be included in the analog data. Data and parameters used in the neural network calculation can be once stored in the NOSRAM4013. The data and parameters may be stored in a memory provided outside the AI system4041via the CPU4021. However, the NOSRAM4013provided inside the AI system4041can store the data and parameters more quickly with lower power consumption. Furthermore, the NOSRAM4013enables a longer bit line than the DOSRAM4012and thus can have an increased storage capacity. The FPGA4014is an FPGA including an OS transistor. By including the FPGA4014, the AI system4041can establish a connection of a neural network such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network (DBN), or the like described later, with a hardware. The connection of the neural network with a hardware enables higher speed performance. The FPGA4014is an FPGA including an OS transistor. An OS-FPGA can have a smaller memory area than an FPGA formed using an SRAM. Thus, adding a context switching function only causes a small increase in area. Moreover, an OS-FPGA can transmit data and parameters at high speed by utilizing the boosting. The 3D-NAND4015is a nonvolatile memory using an oxide semiconductor. The 3D-NAND4015is a highly integrated memory in which the storage capacity per unit area is large. Furthermore, the 3D-NAND4015can store multilevel data of two or more bits as well as one-bit binary data. The multilevel data storage in the 3D-NAND4015leads to a reduction of the memory cell area per bit. As the 3D-NAND4015, for example, the semiconductor device in the above embodiment can be used. Since the area occupied by the memory cell can be reduced with use of such a semiconductor device, the 3D-NAND4015can be more highly integrated. Thus, the storage capacity per unit area of the 3D-NAND4015can be increased. In the AI system4041, the analog arithmetic circuit4011, the DOSRAM4012, the NOSRAM4013, and the FPGA4014can be provided on one die (chip). Thus, the AI system4041can perform calculation of the neural network quickly with low power consumption. The analog arithmetic circuit4011, the DOSRAM4012, the NOSRAM4013, and the FPGA4014can be manufactured through the same manufacturing process. This enables the AI system4041to be manufactured at low cost. Note that the arithmetic portion4010need not necessarily include all of the following: the DOSRAM4012, the NOSRAM4013, and the FPGA4014. One or more memories are selected from the DOSRAM4012, the NOSRAM4013, and the FPGA4014in accordance with a problem that is desired to be solved in the AI system4041. The AI system4041can implement a method such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN) in accordance with the problem that is desired to be solved. The PROM4025can store a program for implementing at least one of the methods. Part or the whole of the program may be stored in the NOSRAM4013or the 3D-NAND4015. The 3D-NAND4015, which is a highly integrated memory in which the storage capacity per unit area is large, can store high-capacity program. Most of the existing programs used as libraries are designed on the premise that the programs are processed by a GPU. Therefore, the AI system4041preferably includes the GPU4022. The AI system4041can execute the bottleneck product-sum operation among all the product-sum operations used for learning and inference in the arithmetic portion4010, and execute the other product-sum operations in the GPU4022. In this manner, the learning and inference can be performed at high speed. The power supply circuit4027generates not only a low power supply potential for a logic circuit but also a potential for an analog operation. The power supply circuit4027may include an OS memory. In this case, storing a reference potential in the OS memory can reduce the power consumption of the power supply circuit4027. The PMU4028is configured to temporarily stop the power supply to the AI system4041. As a register in each of the CPU4021and the GPU4022, an OS memory is preferably included. By including the OS memory, each of the CPU4021and the GPU4022can retain data (logic value) in the OS memory even when power supply is stopped. As a result, the AI system4041can save the power. The PLL4023is configured to generate a clock. The AI system4041performs an operation on the basis of the clock generated by the PLL4023. The PLL4023preferably includes an OS memory. When an OS memory is included in the PLL4023, an analog potential with which the clock oscillation frequency is controlled can be held. The AI system4041may store data in an external memory such as a DRAM. For this reason, the AI system4041preferably includes the memory controller4026functioning as an interface with the external DRAM. Furthermore, the memory controller4026is preferably provided near the CPU4021or the GPU4022. Thus, quick data transmission can be achieved. Some or all of the circuits illustrated in the control portion4020can be formed on the same die as the arithmetic portion4010. Thus, the AI system4041can execute neural network calculation at high speed with low power consumption. Data used for neural network calculation is stored in an external memory device such as a hard disk drive (HDD) or a solid state drive (SSD) in many cases. Therefore, the AI system4041preferably includes the external memory control circuit4031functioning as an interface with the external memory device. Because audio and video are often subjects of the learning and inference using the neural network, the AI system4041includes the audio codec4032and the video codec4033. The audio codec4032encodes and decodes audio data, and the video codec4033encodes and decodes video data. The AI system4041can perform learning or make an inference using data obtained from an external sensor. For this reason, the AI system4041includes the general-purpose input/output module4034. The general-purpose input/output module4034includes a universal serial bus (USB), an inter-integrated circuit (I2C), or the like, for example. The AI system4041can perform learning or make an inference using data obtained via the Internet. For this reason, the AI system4041preferably includes the communication module4035. The analog arithmetic circuit4011may include a multi-level flash memory as an analog memory. However, the flash memory has a limit on the number of rewriting times. In addition, the multi-level flash memory is extremely difficult to embed; in other words, the arithmetic circuit and the memory are difficult to form on the same die. Alternatively, the analog arithmetic circuit4011may include a ReRAM as an analog memory. However, the ReRAM has a limit on the number of rewriting times and also has a problem in storage accuracy. Moreover, because the ReRAM is a two-terminal element, the complicated circuit design is necessary for separating data writing and data reading. Further alternatively, the analog arithmetic circuit4011may include an MRAM as an analog memory. However, the MRAM has a problem in storage capacity because of its low magnetoresistive ratio. In consideration of the above, an OS memory is preferably used as an analog memory in the analog arithmetic circuit4011. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 5 Application Example of AI System In this embodiment, application examples of the AI system described in the above embodiment will be described with reference toFIGS.70A and70B. FIG.70Aillustrates an AI system4041A in which the AI systems4041described withFIG.69are arranged in parallel and a signal can be transmitted between the systems via a bus line. The AI system4041A illustrated inFIG.70Aincludes AI systems4041_1to4041_n(n is a natural number). The AI systems4041_1to4041_nare connected to each other via a bus line4098. FIG.70Billustrates an AI system4041B in which the AI systems4041described withFIG.69are arranged in parallel as inFIG.70Aand a signal can be transmitted between the systems via a network. The AI system4041B illustrated inFIG.70Bincludes the AI systems4041_1to4041_n. The AI systems4041_1to4041_nare connected to each other via a network4099. A communication module is provided in each of the AI systems4041_1to4041_n; such a configuration enables wireless or wired communication via the network4099. A communication module can communicate via an antenna. Communication can be performed when an electronic device is connected to a computer network such as the Internet (infrastructure of the World Wide Web, WWW), an intranet, an extranet, a personal area network (PAN), a local area network (LAN), a campus area network (CAN), a metropolitan area network (MAN), a wide area network (WAN), or a global area network (GAN), for example. In the case of performing wireless communication, it is possible to use, as a communication protocol or a communication technology, a communications standard such as Long-Term Evolution (LTE), Global System for Mobile Communication (GSM: registered trademark), Enhanced Data Rates for GSM Evolution (EDGE), Code Division Multiple Access 2000 (CDMA2000), or W-CDMA (registered trademark), or a communications standard developed by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark). With the configuration illustrated inFIG.70A or70B, analog signals obtained with external sensors or the like can be processed by different AI systems. For example, analog signals containing biological information such as brain waves, a pulse, blood pressure, and body temperature obtained with a variety of sensors such as a brain wave sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor can be processed by different AI systems. Since each of the AI systems performs signal processing or learning, the amount of information processed by each AI system can be reduced. Accordingly, the signal processing or learning requires a smaller amount of arithmetic processing. As a result, recognition accuracy can be increased. With the use of data obtained with each AI system, biological information that irregularly changes should be able to be collectively grasped instantly. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 6 This embodiment shows an example of an IC incorporating the AI system described in the above embodiment. In the AI system described in the above embodiment, a digital processing circuit (e.g., a CPU) that includes a Si transistor and a 3D-NAND, an OS-FPGA, an OS memory (e.g., a DOSRAM or a NOSRAM), and an analog arithmetic circuit that include OS transistors can be integrated into one die. FIG.71illustrates the example of the IC incorporating the AI system. An AI system IC7000illustrated inFIG.71includes a lead7001and a circuit portion7003. The AI system IC7000is mounted on a printed circuit board7002, for example. A plurality of such IC chips are combined and electrically connected to each other on the printed circuit board7002; thus, a circuit board on which electronic components are mounted (a circuit board7004) is formed. In the circuit portion7003, the circuits described in the above embodiment are provided on one die. The circuit portion7003has a stacked-layer structure as described in the above embodiment, which is broadly divided into a Si transistor layer7031, a wiring layer7032, and an OS transistor layer7033. Since the OS transistor layer7033can be stacked over the Si transistor layer7031, the size of the AI system IC7000can be easily reduced. Although a Quad Flat Package (QFP) is used as a package of the AI system IC7000inFIG.71, the package is not limited thereto. The digital processing circuit (e.g., a CPU) and the 3D-NAND, the OS-FPGA, the OS memory (e.g., a DOSRAM or a NOSRAM), and the analog arithmetic circuit that include OS transistors can all be formed in the Si transistor layer7031, the wiring layer7032, and the OS transistor layer7033. In other words, elements included in the AI system can be formed through the same manufacturing process. Thus, the number of steps in the manufacturing process of the IC described in this embodiment does not need to be increased even when the number of elements is increased, and accordingly the AI system can be incorporated into the IC at low cost. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 7 <Electronic Device> The semiconductor device of one embodiment of the present invention can be used for a variety of electronic devices.FIGS.72A and72BandFIGS.73A to73Fillustrate specific examples of the electronic devices each including the semiconductor device in one embodiment of the present invention. A robot2000illustrated inFIG.72Aincludes an arithmetic device2001, a sensor2002, a light2003, a lift2004, a driver portion2005, and a moving mechanism2011, and can take a still image and a moving image while being moved. Such a robot can be used for a security system or a monitoring system. The robot2000may further include a communication means2006, a speaker2007, a microphone2008, a display portion2009, a light-emitting portion2010, and the like. In the arithmetic device2001, the semiconductor device of one embodiment of the present invention can be used. As the arithmetic device2001, an IC in which the AI system of one embodiment of the present invention is incorporated can be used. The sensor2002functions as a camera which takes images of surroundings of the robot2000. The light2003is a light unit which can be used when the surroundings of the robot2000taken by the sensor2002. When a still image is taken by the sensor2002, the light2003preferably functions as a flashlight. The sensor2002is connected to a main body of the robot via the lift2004. The height of the sensor2002can be adjusted by the lift2004. The lift2004is preferably telescopic. Alternatively, the lift2004may be a foldable lift composed of a plurality of booms. The robot2000including the driver portion2005and the moving mechanism2011connected to the driver portion2005is preferably used, in which case an imaging range of the sensor2002, that is, a monitoring range, is expanded. The communication means2006can send data taken by the sensor2002to a manager or the server owned by the manager. In addition, when judging the occurrence of an emergency such as a crime, an accident, or a fire after the arithmetic device2001analyzes the image taken by the sensor2002, the arithmetic device2001can report to the security company, the police, the fire station, the medical institution, or the owner of the land or the building. The speaker2007can transmit information such as an alert to a criminal, a call to an injured person or an emergency patient, and evacuation guidance, to the surroundings of the robot. The microphone2008can be used to obtain sounds around the robot2000. The use of the communication means2006and the speaker2007enables the robot2000to function as a telephone. A person around the robot2000can have a conversation with the manager or a specific person. The display portion2009can display specific data. In emergency, the disaster information and the evacuation route can be displayed. The use in combination with the communication means2006, the speaker2007, and the microphone2008enables the robot2000to function as the videophone. A person around the robot2000can have a conversation with the manager or a given person while seeing the display portion2009. The light-emitting portion2010emits light or displays characters to show the direction of movement and the stopped state of the robot2000. In addition, emergency may also be shown. FIG.72Bis a block diagram illustrating a configuration of the robot2000. The arithmetic device2001adjusts turning on or off and the brightness of the light2003from data such as an image obtained by the sensor2002. In addition, the height of the lift2004is adjusted or the driver portion2005is controlled to align the positions of the robot2000and the sensor2002. The operating condition of the driver portion2005can be shown by using the light-emitting portion2010. With the communication means2006, information around the robot2000obtained from the sensor2002and the microphone2008can be transmitted to the manager or the server owned by the manager. Depending on the judgement of the arithmetic device2001or the manager, information can be sent to the surroundings of the robot2000with the speaker2007and the display portion2009. In the case where a sensor that can take an image even in dark surroundings is used as the sensor2002, the light2003is not necessarily provided. As such a sensor, an image sensor containing selenium (Se) in the light receiving portion can be used. Such a robot2000can be used in commercial facilities and for security of the office. Data obtained from the sensor2002and the microphone2008is stored in the arithmetic device2001or the server. The stored data is analyzed by an AI system to check whether there is an anomaly situation such as loss or damage of an object, entry of suspicious individual, or disaster such as a fire. For the data analysis, deep learning may be used. When there is an unusual situation, the robot2000performs report to the manager and transmits information to the surroundings, and records the conditions of the surroundings. The robot2000may be used for monitoring the growing conditions of the crops. The robot2000placed in a rice field or a field monitors the shapes, the sizes, or the colors of leaves or fruit by the sensor2002to check whether the crops are damaged or not or whether the crops are harmed by pests or not. Since the moving mechanism2011is provided for the robot2000, the growing conditions of the crops can be monitored in a wide range. In addition, since the robot2000is provided with the lift2004, the leaves and fruit at a certain height can be monitored regardless of the kind of crops and the growing conditions. The monitoring results are transmitted to a grower using the communication means2006, and the grower can determine the kind, the amount, and the spraying timing of fertilizer and agricultural chemicals necessary for the crops. Alternatively, the monitoring results may be analyzed with an AI system using the arithmetic device2001, and the kind, the amount, and the spraying timing of fertilizer and agricultural chemicals necessary for the crops may be determined and reported to the grower. Deep learning may be used for analysis of the monitoring results. FIG.73Aillustrates a sorting system3000using a robot3001. The robot3001includes an arithmetic device3002, a boom3003, and an arm3004. The robot3001may further include a wired or wireless communication means3011. In addition, the sorting system3000includes a housing3008including a sensor3009. The housing3008includes a communication means3010. The housing3008is provided for a ceiling, a wall, or a beam (not illustrated) of the sorting system3000or a sorting operation area. The housing3008may be provided in the robot3001. For example, the housing3008may be provided for the boom3003or the arm3004. In the case where the housing3008is provided in the robot3001, data obtained by the sensor3009may be transmitted to the arithmetic device3002without passing through the communication means3010or the communication means3011, and processed. The boom3003is movable, and the arm3004can be placed at a desired position. The arm3004may be telescopic. The arm3004placed over a desired object3007may be stretched to grab the desired object3007, shortened, and then moved by the boom3003. The sorting system3000can transfer the object3007in a container3005to a container3006. The container3005and the container3006may have the same shape or different shapes. Furthermore, a plurality of objects3007put in one container3005may be moved separately to a plurality of containers3006. As the container3005and the container3006, a container, a cardboard box, a box for packing a product, a case, a film, a bag, a tray for storing foods, a lunch box, or the like is used. Furthermore, at least one of the container3005and the container3006may be cooking utensils such as a pot or a frying pan. For the arithmetic device3002, the semiconductor device of one embodiment of the present invention can be used. In the arithmetic device3002, an IC in which the AI system of one embodiment of the present invention is incorporated can be used. The sensor3009receives the positions or the number of containers3005, the positions or the number of containers3006, the state of the inside of the container3005, and the state of the object3007in the container3005and transmits the data to the arithmetic device3002using the communication means3010. Transmission of data is performed with or without a wire. Alternatively, the data may be transmitted through a wire without the communication means3010. The arithmetic device3002analyzes the transmitted data. Here, the state of the object3007indicates the shape or the number of objects3007, the overlap between the objects3007, or the like. The arithmetic device3002performs analyzation on the basis of information from the sensor3009and obtains detailed information of the object3007. The three-dimensional shape and hardness (or softness) of the object3007are obtained by comparison with the data stored in the arithmetic device3002or the server that can be communicated with the robot3001. Depending on the three-dimensional shape and hardness (or softness) of the object3007, the shape of the arm3004can be changed. Furthermore, depending on the shape or the size of the object3007, the position in the container3006may be changed or a plurality of containers3006may be provided to sort the objects3007. To obtain the detailed data of the object3007, analysis using an AI system can be utilized. Deep learning may be used to analyze the data. FIG.73Billustrates an arm in which a pair of plates3021can move in the horizontal direction to pick up the object3007. The pair of plates3021moves toward the center horizontally, whereby the object3007can be picked up. Such an arm can hold a surface of the object3007, and is suitable for picking up the object3007with a columnar shape, such as a cube or a rectangular solid.FIG.73Cillustrates an arm in which a plurality of bars3022can move in the horizontal direction to pick up the object3007. The plurality of bars3022move toward the center horizontally, whereby the object3007can be picked up. Such an arm can pinch a point of the object3007, and is suitable for picking up the object3007in a spherical shape or in a non-fixed shape, that is, the object3007in an irregular shape. Note that although the number of bars3022is four inFIG.73C, this embodiment is not limited to this structure. The number of bars3022may be three or five or more.FIG.73Dillustrates an arm in which a pair of plates3023rotates around the common axis to be closer to each other to pick up the object3007. Such an arm can hold a surface of the object3007, and is suitable for picking up the object3007with a thin-film shape, such as paper or films.FIG.73Eillustrates an arm in which a pair of crook-shaped plates3024rotates around the common axis such that the ends of them are closer to each other to pick up the object3007. Such an arm can pinch a point or a side of the object3007, and is suitable for picking up the object3007with a thin-film shape, such as paper or films or the object3007with a smaller particulate shape. As illustrated inFIG.73F, a spatula3025may be attached to the tip of the arm, and the object3007with a smaller particulate shape may be scooped. The arms illustrated inFIGS.73A to73Fare just examples and one embodiment of the present invention is not limited to these shapes. In addition, the application of the arms is just an example and one embodiment of the present invention is not limited thereto. The robot3001moves the boom3003to move the arm3004to a position over the desired object3007in the container3005on the basis of signals from the arithmetic device3002. In the case of using the telescopic arm3004, the arm3004is stretched, and the tip of the arm3004is brought down to a position on the same level of the object3007. The tip of the arm is moved to catch the desired object3007. The arm is shortened while catching the object3007. The boom3003is moved again to transfer the arm3004to the desired position in the container3006. At this time, the arm3004may be rotated to adjust the angle of the object3007to the container3006. The arm3004is stretched to place the object3007in the container3006, and the arm3004releases the object3007. The above operation is repeated, so that the robot3001can move the object3007from the container3005to the container3006. Since the positional information on the containers3005and3006and the state of the object3007are analyzed using the AI system, the object3007can be moved surely regardless of the shape or hardness of the object3007. Examples of the object3007include not only an object packed in a box with a shape of a cube or a rectangular solid or a box or a case with a given shape but also shaped processed foods such as an egg, a hamburger steak, and a croquette, foods such as vegetables with an irregular shape such as a potato and a tomato, machine parts such as a screw and a nut, a thin film of a paper or a film, and the like. Since in the sorting system3000in this embodiment, the shape of the arm can be changed in consideration of the shape and the hardness of the object3007, the objects3007given above as examples can be transferred from the container3005to the container3006regardless of the shape and the hardness. A memory device including the semiconductor device of one embodiment of the present invention can hold control data, a control program, or the like of the above electronic device for a long time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be provided. An IC in which the above AI system is incorporated can be used for the arithmetic device or the like of the above-described electronic device, for example. Accordingly, the electronic device of this embodiment can perform optimal operations depending on circumstances with low power consumption by utilizing the AI system. This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments. This application is based on Japanese Patent Application Serial No. 2017-119073 filed with Japan Patent Office on Jun. 16, 2017, and Japanese Patent Application Serial No. 2017-132740 filed with Japan Patent Office on Jul. 6, 2017, the entire contents of which are hereby incorporated by reference. | 266,331 |
11943930 | DETAILED DESCRIPTION The specific structural or functional description disclosed herein is merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be implemented in various forms, and may not be construed as limited to the embodiments set forth herein. Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings in order for those skilled in the art to be able to readily implement the technical spirit of the present disclosure. Embodiments may provide a semiconductor memory device that may improve a threshold voltage distribution by suppressing charges trapped in a charge storage layer of a memory cell such that the charges are not emitted within a limited time in a program operation of the semiconductor memory device. Embodiments may also include methods of manufacturing and operating the semiconductor memory device. FIG.1is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present disclosure. Referring toFIG.1, the semiconductor memory device10may include a peripheral circuit PC and a memory cell array20. The peripheral circuit PC may be configured to control a program operation for storing data to the memory cell array20, a read operation for outputting data stored in the memory cell array20, and an erase operation for erasing data stored in the memory cell array20. In an embodiment, the peripheral circuit PC may include a voltage generator31, a row decoder33, a control circuit35, and a page buffer group37. The memory cell array20may include a plurality of memory blocks. The memory cell array20may be connected to the row decoder33through word lines WL, and may be connected to the page buffer group37through bit lines BL. The control circuit35may control the peripheral circuit PC in response to a command CMD and an address ADD. The voltage generator31may generate various operating voltages such as a pre-erase voltage, an erase voltage, a ground voltage, a program voltage, a verify voltage, a pass voltage, and a read voltage, which may be used for a program operation, a read operation, and an erase operation, under the control of the control circuit35. The row decoder33may select a memory block under the control of the control circuit35. The row decoder33may apply operating voltages to the word lines WL connected to the selected memory block. The page buffer group37may be connected to the memory cell array20through the bit lines BL. The page buffer group37may temporarily store data received from an input/output circuit (not shown) in a program operation under the control of the control circuit35. The page buffer group37may sense a voltage or current of the bit lines BL in a read operation or a verify operation under the control of the control circuit35. The page buffer group37may select the bit lines BL under the control of the control circuit35. Structurally, the memory cell array20may overlap with a portion of the peripheral circuit PC. FIG.2is a circuit diagram illustrating the memory cell array shown inFIG.1. Referring toFIG.2, the memory cell array20may include a plurality of cell strings CS1and CS2connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CS1and CS2may be commonly connected to a plurality of word lines WL1to WLn. Each of the plurality of cell strings CS1and CS2may include at least one source select transistor SST connected to the source line SL, at least one drain select transistor DST connected to the bit line BL, and a plurality of memory cells MC1to MCn connected in series between the source select transistor SST and the drain select transistor DST. Gates of the plurality of memory cells MC1to MCn may be connected, respectively, to the plurality of word lines WL1to WLn stacked to be spaced apart from each other. Two or more drain select lines DSL1and DSL2may be spaced apart from each other at a same level. A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST. The source line SL may be connected to a source of the source select transistor SST. A drain of the drain select transistor DST may be connected to a bit line corresponding to the drain of the drain select transistor DST. The plurality of cell strings CS1and CS2may be divided into string groups connected, respectively, to the two or more drain select lines DSL1and DSL2. Cell strings connected to the same word line and the same bit line may be independently controlled by different drain select lines. Also, cell strings connected to the same drain select line may be independently controlled by different bit lines. In an embodiment, the two or more drain select lines DSL1and DSL2may include a first drain select line DSL1and a second drain select line DSL2. The plurality of cell strings CS1and CS2may include a first cell string CS1of a first cell string group connected to the first drain select line DSL1and a second cell string CS2of a second string group connected to the second drain select line DSL2. FIGS.3A and3Bare perspective views schematically illustrating semiconductor memory devices in accordance with embodiments of the present disclosure. Referring toFIGS.3A and3B, each of the semiconductor memory devices10A and10B may include a peripheral circuit PC disposed on the substrate SUB and gate stack structures GST overlapping with the peripheral circuit PC. Each of the gate stack structures GST may include a source select line SSL, a plurality of word lines WL1to WLn, and two or more drain select lines DSL1and DSL2isolated from each other at a same level by a first slit S1. The source select line SSL and the plurality of word lines WL1to WLn may be formed in a plate shape which may expand in a first direction X and a second direction Y and may be parallel to a top surface of the substrate SUB. The first direction X may be a direction in which an X-axis faces in an XYZ coordinate system, and the second direction Y may be a direction in which a Y-axis faces in the XYZ coordinate system. The plurality of word lines WL1to WLn may be stacked to be spaced apart from each other in a third direction Z. The third direction Z may be a direction in which a Z-axis faces in the XYZ coordinate system. The plurality of word lines WL1to WLn may be disposed between the two or more drain select lines DSL1and DSL2and the source select line SSL. The gate stack structures GST may be isolated from each other by a second slit S2. The first slit S1may be formed shorter than the second slit S2in the third direction Z, and may overlap with the plurality of word lines WL1to WLn. Each of the first slit S1and the second slit S2may extend in a linear shape, extend in a zigzag shape, or extend in a wave form. A width of each of the first slit S1and the second slit S2may be variously changed according to a design rule. Referring toFIG.3A, in accordance with an embodiment, the source select line SSL may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1and DSL2. The semiconductor memory device10A may include a source line SL disposed between the gate stack structure GST and the peripheral circuit PC and a plurality of bit lines BL spaced more apart from the peripheral circuit PC than the source line SL. The gate stack structures GST may be disposed between the plurality of bit lines BL and the source line SL. Referring toFIG.3B, in accordance with an embodiment, the two or more drain select lines DSL1and DSL2may be disposed closer to the peripheral circuit PC than to the source select line SSL. The semiconductor memory device10B may include a plurality of bit lines BL disposed between the gate stack structures GST and the peripheral circuit PC and a source line SL that is disposed further from the peripheral circuit PC than from the plurality of bit lines BL. The gate stack structures GST may be disposed between the plurality of bit lines BL and the source line SL. Referring back toFIGS.3A and3B, the plurality of bit lines BL may be formed of various conductive materials. The source line SL may include a doped semiconductor layer. In an example, the source line SL may include an n-type doped silicon layer. Although not shown in the drawings, the peripheral circuit PC may be electrically connected to the plurality of bit lines BL, the source line SL, and the plurality of word lines WL1to WLn through interconnections having various structures. FIG.4is a perspective view illustrating a portion of a memory cell array of a semiconductor memory device in accordance with an embodiment of the present disclosure. Referring toFIG.4, the memory cell array20may include gate stack structures GST isolated from each other by a slit SI and channel structures CH penetrating each of the gate stack structures GST. The slit SI may be filled with a vertical structure VS. In an embodiment, the vertical structure VS may include an insulating material. Each of the gate stack structures GST may include interlayer insulating layers ILD and gate electrodes GA, which may be alternately stacked in one direction. Hereinafter, a direction in which the interlayer insulating layers ILD and the gate electrodes GA may be alternately stacked may be referred to as a stacking direction. The gate electrodes GA may include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride layer. Each of the gate electrodes GA may be used as a gate electrode of a memory cell or a gate electrode of a select transistor. The channel structure CH may extend in the stacking direction, and may be surrounded by the gate electrodes GA. FIG.5is an enlarged sectional view illustrating region X shown inFIG.4. Referring toFIG.5, the channel structure CH may include a compensation charge storage layer111, a blocking insulating layer113, a charge storage layer115, an emission preventing layer117, a tunnel insulating layer119, and a channel layer121, each of which extend in a vertical direction. The channel layer121may be used as a channel region of a cell string. The channel layer121may include a semiconductor layer. In an embodiment, the channel layer121may include silicon. The tunnel insulating layer119may surround a sidewall of the channel layer121. The tunnel insulating layer119may be formed as a silicon oxide layer through which charges may tunnel. The emission preventing layer117may surround a sidewall of the tunnel insulating layer119. The emission preventing layer117may be formed as a quantum dot monolayer. The emission preventing layer117may trap charges that may be released from the charge storage layer115. The charge storage layer115may surround a sidewall of the emission preventing layer117. The charge storage layer115may be formed as a material layer capable of storing data changed using Fowler-Nordheim tunneling. In an embodiment, the charge storage layer115may be formed as a charge trap nitride layer. The blocking insulating layer113may surround a sidewall of the charge storage layer115. The blocking insulating layer113may include an oxide layer capable of blocking charges. The compensation charge storage layer111may surround a sidewall of the blocking insulating layer. The compensation charge storage layer111may trap charges introduced from the gate electrode GA. The compensation charge storage layer111may be formed as a multi-layer. In an embodiment, the compensation charge storage layer111may be configured with a first layer109surrounding the sidewall of the blocking insulating layer113and a second layer107surrounding a sidewall of the first layer109. The first layer109may be a region in which no trap exists, and the second layer107may be a region in which a trap exists. In an embodiment, the compensation charge storage layer111may be formed of a high-K material such as Al2O3, HfO, ZrO, Ta2O3, HfTaxOy, LaHfO or HfSiO. The channel structure CH may further include a core insulating layer123extending in the vertical direction at the inside of the channel layer121. In accordance with the embodiment of the present disclosure, a memory cell may include the channel layer121, and the tunnel insulating layer119, the emission preventing layer117, the charge storage layer115, the blocking insulating layer113, and the compensation charge storage layer111, which may be sequentially stacked on the channel layer121. For example, the channel layer121, the tunnel insulating layer119, the emission preventing layer117, the charge storage layer115, the blocking insulating layer113, and the compensation charge storage layer111, which may be formed in a sidewall region of one gate electrode GA, may be components included in one memory cell. The semiconductor memory device shown inFIGS.4and5may be applied to the semiconductor memory device10A shown inFIG.3A. The semiconductor memory device shown inFIGS.4and5may be vertically reversed to be applied to the semiconductor memory device10B shown inFIG.3B. FIGS.6A to6Dare sectional views illustrating a method of manufacturing a memory cell array in accordance with an embodiment of the present disclosure. Referring toFIG.6A, a stack structure ST may be formed such that interlayer insulating layers101and sacrificial layers103are alternately stacked. The stack structure ST may be formed on a substrate (not shown) including a peripheral circuit. The sacrificial layer103may be formed of a material different from that of the interlayer insulating layers101. For example, the interlayer insulating layers101may be formed of an oxide such as a silicon oxide layer. The sacrificial layers103may be formed of a material having an etching rate different from that of the interlayer insulating layers101. For example, the sacrificial layers103may be formed of a nitride such as a silicon nitride layer. Referring toFIG.6B, holes105may be formed, which penetrate the stack structure ST. Subsequently, a compensation charge storage layer111, a blocking insulating layer113, a charge storage layer115, an emission preventing layer117, a tunnel insulating layer119, and a channel layer121may be sequentially formed on sidewalls of the holes105. In an embodiment, the compensation charge storage layer111may be formed as a multi-layer. For example, the compensation charge storage layer111may include a second layer107formed on the sidewall of the hole105and a first layer109formed on a sidewall of the second layer107. The first layer109may be a region in which no trap exists, and the second layer107may be a region in which a trap exists. The first layer109and the second layer107may be formed of Al2O3, and a trap may be formed through a redox mechanism by adjusting a composition ratio of AI and O in a process of forming the second layer107. The compensation charge storage layer111may be formed of a high-K material such as Al2O3, HfO, ZrO, Ta2O3, HfTaxOy, LaHfO or HfSiO. For example, the compensation charge storage layer111may include a layer including at least one of Al2O3, HfO, ZrO, Ta2O3, HfTaxOy, LaHfO, and HfSiO. The charge storage layer115may be formed as a charge trap layer, be formed as a material layer including a conductive nano dot, or be formed as a phase change material layer. For example, the charge storage layer115may store data changed using Fowler-Nordheim tunneling. To this end, the charge storage layer115may be formed as a silicon nitride layer in which charges may be trapped. The emission preventing layer117may be formed as a quantum dot monolayer. The emission preventing layer117may trap charges released from the charge storage layer115. The emission preventing layer117may be formed as a metal silicide layer. For example, the emission preventing layer117may be formed by sequentially depositing a tungsten thin film of 3 nm or less and a silicon thin film of 2 nm or less on a sidewall of the charge storage layer115and then performing a metal heat treatment process (RTA) of 700° C. or higher. The density and size of quantum dots of the emission preventing layer117may be adjusted according to the grain size of tungsten and the degree of reaction to silicon. In another embodiment, the emission preventing layer117may be formed by depositing a tungsten silicide (WSi2) layer on the sidewall of the charge storage layer115through a CVD or ALD process and then performing a metal heat treatment process (RTA) of 700° C. or higher. In another embodiment, the emission preventing layer117may be formed as a silicon layer. For example, a non-uniform Si quantum dot layer having a size of 2 to 5 nm may be formed by forming an SiO2layer of 10 nm or less or an SiO2or SiON layer containing excess Si and then performing a metal heat treatment process (RTA) of 700° C. or higher under an N2atmosphere. The tunnel insulating layer119may be formed as a silicon oxide layer through which charges may tunnel. The channel layer121may include a semiconductor layer. In an embodiment, the channel layer121may include silicon. When central regions of the holes105are opened by the channel layer121, the central regions of the holes105may be filled with a core insulating layer123. Accordingly, a channel structure125that includes the compensation charge storage layer111, the blocking insulating layer113, the charge storage layer115, the emission preventing layer117, the tunnel insulating layer119, the channel layer121, and the core insulating layer123may be formed to penetrate the stack structure ST. Referring toFIG.6C, a slit SI may be formed and may penetrate the stack structure ST. Sidewalls of the sacrificial layers103shown inFIG.6Bmay be exposed by the slit SI. Subsequently, the sacrificial layers103shown inFIG.6Bmay be removed through the slit SI. Accordingly, openings may be formed which expose a side portion of the compensation charge storage layer111. The openings may be defined between the interlayer insulating layers101. Referring toFIG.6D, spaces from which the sacrificial layers are removed may be filled with a gate electrode127. For example, a conductive material in the slit may be removed from the slit and deposited into the gate electrodes127such that the openings are filled therewith. Subsequently, a vertical structure129is formed by filling the slit with an insulating material. FIG.7is an energy band gap diagram of a memory cell in accordance with an embodiment of the present disclosure. The channel layer121, the tunnel insulating layer119, the emission preventing layer117, the charge storage layer115, the blocking insulating layer113, and the compensation charge storage layer111, which are described inFIG.5, may operate as one memory cell. When a program voltage having a high potential level is applied to a gate of the memory cell in a program operation, charges in the channel layer121tunnel into the tunnel insulating layer119and may be trapped in the charge storage layer115. Some charges among charges trapped in the charge storage layer115may be released within a limited time after a program voltage apply operation is completed. The emission preventing layer117again may trap the charges released from the charge storage layer115, to suppress the charges from being emitted to the outside of the semiconductor memory device. Thus, a threshold voltage of the memory cell may be uniformly maintained. A trap site may exist at the inside of the second layer107of the compensation storage layer. The trap site may be formed at an edge portion of a balance band of the second layer107. The trap site of the second layer107becomes empty in the program voltage apply operation. Subsequently, charges may be introduced from a gate electrode to be trapped in another operation except the program voltage apply operation. Thus, although some charges among the charges trapped in the charge storage layer115are emitted to the outside of the semiconductor memory device, the threshold voltage of the memory cell may be constantly maintained by the charges trapped in the second layer107. FIG.8is a flowchart illustrating a method of operating a semiconductor memory device in accordance with an embodiment of the present disclosure. FIG.9is a waveform diagram of voltages that illustrates the method shown inFIG.8. The method of operating the semiconductor memory device in accordance with an embodiment of the present disclosure will be described as follows with reference toFIGS.1,2,4,5, and7to9. In step S810, the control circuit35of the semiconductor memory device10may receive, from outside the semiconductor memory device, a command corresponding to a program operation, i.e., a program command CMD and an address ADD, and the peripheral circuit PC of the semiconductor memory device10may perform the program operation in response to the program command CMD and the address ADD. A program operation period PGM may include a program voltage apply operation and a verify operation, which may be alternately performed. In the program voltage apply operation, the page buffer group37may apply a program allow voltage (e.g., 0V) or a program inhibit voltage (e.g., a power voltage) to bit lines BLs according to data to be programmed. The voltage generator31may generate a program voltage Vpgm and a pass voltage under the control of the control logic35, and the row decoder33may apply the program voltage Vpgm generated by the voltage generator31to a selected word line Sel WL. The row decoder33may apply the pass voltage to unselected word lines. Therefore, charges may be trapped in the charge storage layer115of memory cells connected to the selected word line Sel WL. In the verify operation, the voltage generator31may generate at least one verify voltage Vverify under the control of the control circuit35, and the row decoder33may apply the verify voltage Vverify generated by the voltage generator31to the selected word line Sel WL. The row decoder33may apply the pass voltage to the unselected word lines. The page buffer group37may sense a potential level or current amount of the bit lines BLs, and may apply the program allow voltage (e.g., 0V) or the program inhibit voltage (e.g., the power voltage), based on a sensing result. In step S820, the semiconductor memory device10may receive a suspend command SUSPEND CMD from outside of the semiconductor memory device. The peripheral circuit PC may suspend an operation being performed currently, i.e., the program operation in response to the suspend command SUSPEND CMD. Therefore, the peripheral circuit PC may block the program voltage Vpgm or the verify voltage Vverify, which may be applied to the selected word line Sel WL, and may control the selected word line Sel WL to have a ground level. Accordingly, charges may be trapped in the compensation charge storage layer111of the memory cell. The suspend command SUSPEND CMD may be received from outside of the semiconductor memory device, when the performance of an urgent operation is required. For example, when the performance of an urgent operation is required, the suspend command SUSPEND CMD may be received to suspend the program operation being performed currently, and then, a command corresponding to the urgent operation may be received. In step S830, the semiconductor memory device10may receive the suspend command SUSPEND CMD from outside of the semiconductor memory device. In a suspend operation period SUSPEND in which the program operation may be suspended, the peripheral circuit PC may apply a positive voltage Vposi to the bit lines BLs, a source line SL, or the bit lines BLs and the source line SL. Therefore, a potential level of the channel layer121of the memory cells may be increased, and accordingly, the charges trapped in the charge storage layer115may be suppressed from being emitted to outside of the semiconductor device. In addition, the emission preventing layer117of the memory cell may trap charges released from the charge storage layer115. Thus, a threshold voltage of the memory cell may be prevented from being decreased. In step S840, the semiconductor memory device10may receive a resume command RESUME CMD from the outside. The resume command RESUME CMD may be a command for ending the suspend operation period SUSPEND and re-performing the suspended program operation. The peripheral circuit PC may re-perform the suspended program operation in response to the resume command RESUME CMD. The peripheral circuit PC may perform a read operation to determine a threshold voltage of the memory cells connected to the selected word line Sel WL. For example, the voltage generator31may generate at least one read voltage Vread under the control of the control logic35, and the row decoder33may apply the read voltage Vread generated by the voltage generator31to the selected word line Sel WL. The row decoder33may apply the pass voltage to the unselected word lines. The page buffer group37may sense a potential level or current amount of the bit lines BLs, and may determine the threshold voltage of the memory cells, based on a sensing result. Subsequently, the peripheral circuit PC may re-perform the program voltage apply operation and the verify operation, which are described above. FIG.10is a block diagram illustrating a configuration of a memory system1100in accordance with an embodiment of the present disclosure. Referring toFIG.10, the memory system1100may include a semiconductor memory device1120and a memory controller1110. The semiconductor memory device1120may include a plurality of channel structures penetrating a stack structure in which a plurality of interlayer insulating layers and a plurality of gate electrodes may be alternately stacked. Each of the plurality of channel structures may include a compensation charge storage layer, a blocking insulating layer, a charge storage layer, an emission preventing layer, a tunnel insulating layer, and a channel layer. The semiconductor memory device1120may be configured identically to the semiconductor memory device shown inFIG.4. The semiconductor memory device1120may be a multi-chip package configured with a plurality of flash memory chips. The memory controller1110may control the semiconductor memory device1120, and may include a Static Random Access Memory (SRAM)1111, a Central Processing Unit (CPU)1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111may be used as an operation memory of the CPU1112, the CPU1112may perform overall control operations for data exchange of the memory controller1110, and the host interface1113may include a data exchange protocol for a host connected with the memory system1100. The error correction block1114may detect and correct an error included in a data read from the semiconductor memory device1120. The memory interface1115may interface with the semiconductor memory device1120. The memory controller1110may further include a Read Only Memory (ROM) for storing code data for interfacing with the host, and the like. FIG.11is a block diagram illustrating a configuration of a computing system in accordance with an embodiment of the present disclosure. Referring toFIG.11, the computing system1200in accordance with the embodiment of the present disclosure may include a CPU1220, a random access memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210, which are electrically connected to a system bus1260. The computing system1200may be a mobile device. The memory system1210may include a semiconductor memory device1212and a memory controller1211. The semiconductor memory device1212may include a plurality of channel structures penetrating a stack structure in which a plurality of interlayer insulating layers and a plurality of gate electrodes are alternately stacked. Each of the plurality of channel structures may include a compensation charge storage layer, a blocking insulating layer, a charge storage layer, an emission preventing layer, a tunnel insulating layer, and a channel layer. The semiconductor memory device1212may be configured identically to the semiconductor memory device shown inFIG.4. In accordance with the present disclosure, charges trapped in a charge storage layer of a memory cell may be suppressed from being released in a program operation of the semiconductor memory device, so that the threshold voltage distribution of memory cells may be improved. While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments but should be determined by only the appended claims and the equivalents thereof. In the above-described embodiments, all steps may be selectively performed or part of the steps and may be omitted. In each embodiment, the steps are not necessarily performed in accordance with the described order and may be rearranged. The embodiments disclosed in this specification and drawings are only examples to facilitate an understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made on the basis of the technological scope of the present disclosure. Meanwhile, the exemplary embodiments of the present disclosure have been described in the drawings and specification. Although specific terminologies are used here, those are only to explain the embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications may be made on the basis of the technological scope of the present disclosure in addition to the embodiments disclosed herein. | 30,468 |
11943931 | DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS There is a constant requirement for reducing the sizes of the components of integrated circuits, and particularly of providing non-volatile memory devices of the type for trapping charges in a dielectric interface that are even more compact. The embodiments of the invention relate to non-volatile memory devices, particularly devices of the type for trapping charges in a dielectric interface and having a vertical structure embedded in a semiconductor well. According to one aspect, a non-volatile memory device is proposed comprising memory cells of the type for trapping charges in a dielectric interface embedded in a semiconductor well. Each memory cell is advantageously of the “split gate” type, each comprising a state transistor that can be selected by a selection transistor. Moreover, according to one embodiment, the selection transistor is a vertical selection transistor advantageously embedded in the well and located under the state transistor, i.e. at a distance from the upper face of the well that is greater than the distance separating the state transistor from this upper face. This selection transistor-state transistor stack renders the memory cell even more compact. According to one embodiment, each memory cell comprises a state transistor having a control gate and a dielectric area located between the control gate and the well and forming said charge trapping dielectric interface. According to one embodiment, the selection transistor comprises a selection gate, with the control gate superposing the selection gate. According to a particular embodiment, a non-volatile memory device is proposed comprising a memory plane comprising rows and columns of memory cells of the type for trapping charges in a dielectric interface, each memory cell comprising a vertical state transistor embedded in a well and comprising an embedded control gate, each memory cell being able to be selected by a vertical selection transistor embedded in the well and comprising an embedded selection gate, the columns of memory cells comprising pairs of twin memory cells, the two selection transistors of a pair of twin memory cells having a common selection gate, the two state transistors of a pair of twin memory cells having a common control gate superposing the common selection gate, the device further comprising, for each pair of twin memory cells, two dielectric areas, located between the common control gate and the well, forming, on either side of the control gate, two charge trapping dielectric interfaces respectively dedicated to the two twin memory cells. In other words, the control gate and the selection gate of the twin memory cells are superposed and are fully embedded in the well, for example, in a structure of the trench type. Such an embodiment, comprising a pair of vertically structured memory cells, is advantageous in terms of the surface footprint and allows easier integration, for example, in CMOS technology. Furthermore, each memory cell of the pair of twin memory cells is capable of storing digital information by means of the respective charge trapping dielectric interface, which is advantageous in terms of the density of the memory. According to one embodiment, each state transistor of a pair of twin memory cells comprises a respective drain area located in the vicinity of a front face delimiting an upper surface of the well. Thus, each memory cell of the pair of memory cells can be accessed independently of the other memory cell, for example, by means of dedicated control voltages applied to said drain areas. According to one embodiment, each selection transistor of a pair of twin memory cells comprises a source area belonging to an embedded semi-conductive area located in the well in the vicinity of the bottom of the common selection gate. Such a memory cell, provided with such a selection transistor and a source area belonging to an embedded semi-conductive area, also denoted “source plane”, particularly provides an NOR type memory configuration, advantageously allowing page erasures and advantageously using hot-carrier injection programming. According to one embodiment, the memory plane comprises two bit lines per column of memory cells, with the two memory cells of a pair of twin memory cells being respectively connected to the two bit lines. For example, it is the drain area of each memory cell of the pair of twin memory cells that is connected to the respective bit line, the bit line being able to route dedicated control voltages, for example. According to one embodiment, in which the well comprises lateral isolation areas, the control gate extends less deeply in the well than the lateral isolation areas. The lateral isolation areas typically can be of the Shallow Trench Isolation (STI) type. This embodiment particularly allows the appearance of a parasitic current between two adjacent memory cells in a row to be avoided, particularly during a writing operation. According to one embodiment, said charge trapping dielectric interfaces are located on a local part of the sides of the common control gate, in the vicinity of the common selection gate and at a distance from a front face delimiting an upper surface of the well. In other words, the charge trapping dielectric interfaces are located in the vicinity of the bottom of the control gate area, laterally between said control gate and the well. This allows trapped charges to be located while reducing the available storage volume, which allows a phenomenon of spreading the location of the trapped charges to be avoided, which phenomenon can degrade the performance of the device. According to one embodiment, said charge trapping dielectric interfaces comprise semiconductor nanocrystals that are made of silicon, for example. The term nanocrystal is understood to be a nanometric sized isolated crystalline structure, such as an isolated grain of a polycrystalline material. Such nanocrystals can be obtained by means of short growth by Chemical Vapor Deposition (CVD). The use of such nanocrystals also allows the location of the trapped charges to be constrained and thus avoids potential degradation of the performance of the device. According to one embodiment, the device comprises a connection area providing electrical continuity between the selection gate and a contact zone located in the vicinity of a front face delimiting an upper surface of the well. According to one embodiment, said dielectric area forming said charge trapping dielectric interfaces has a first dielectric layer intended to trap electric charges, surrounded by two second dielectric layers. According to one embodiment, the control gate comprises polycrystalline silicon, the first dielectric layer comprises silicon nitride and the second dielectric layers comprise silicon oxide. According to another aspect, a method is proposed for manufacturing a pair of twin memory cells comprising: forming a trench extending vertically in a semiconductor well; forming, in said trench, an embedded selection gate common to two vertical selection transistors embedded in the well and respectively belonging to each memory cell of said pair of twin memory cells. The method further comprises forming a dielectric area comprising, on the sides of the trench above the embedded selection gate, two charge trapping dielectric interfaces respectively belonging to each memory cell of said pair of twin memory cells; and forming, above said selection gate in said trench. An embedded control gate common to two vertical state transistors is embedded in the well and respectively belonging to each memory cell of said pair of twin memory cells. The common embedded control gate being at least partially laterally surrounded by said two charge trapping dielectric interfaces. According to one embodiment, said formation of said common embedded selection gate comprises: depositing an excessive amount of a selection gate conductor material overflowing said trench above a front face delimiting an upper surface of the well; flattening this excessive amount to the level of the front face; selectively etching a thickness below the depth of the trench of the selection gate conductor material remaining in said trench. The selective etching is anisotropic and hidden facing a connection area located at a longitudinal end of the trench, the non-etched connection area providing electrical continuity between the selection gate and a contact area located in the vicinity of the front face of the well. According to one embodiment, the method comprises forming two drain areas adjoining the trench, on either side of the trench and in the vicinity of a front face delimiting an upper surface of the well, respectively belonging to each memory cell of said pair of twin memory cells. According to one embodiment, the method comprises forming an embedded semiconductor area located in the vicinity of the bottom of the trench, forming a source area common to the memory cells of said pair of twin memory cells. The embodiments of the method according to this aspect have the particular advantage of being dissociated (i.e. implemented separately) from the manufacture of other conventional elements of integrated circuits, such as, for example, the logic elements belonging to the control parts of a memory integrated circuit. Indeed, such a dissociated implementation allows the interactions between the method according to this aspect and the manufacturing steps of the other elements of the same integrated circuit to be limited. Furthermore, such a dissociated implementation is adapted to technologies on a carrier substrate of the Fully-Depleted Silicon On Insulator (FDSOI) type. The memory cells are of the type for trapping charges in a dielectric interface, for example, of the SONOS type. The columns COL of memory cells comprise pairs of twin memory cells CEL1, CEL2. The non-volatile memory device IC, which is produced in an integrated manner, is intended, for example, to equip an electronic device APP, such as a mobile telephone or a hearing aid. Any known electronic device that is not mentioned herein also can be equipped with such a device IC. FIG.1shows an embodiment of a pair of memory cells CEL1, CEL2of the SONOS type for trapping charges in a dielectric interface having a vertical structure. FIG.1is a section view in the I-I plane ofFIG.4. The pair of memory cells can be produced in a semiconductor well IPW, incorporated in a carrier substrate PSUB, capable of being biased to high value voltages (of approximately 5 to 15 volts) and being of opposite sign. According to one embodiment, the semiconductor well IPW in which said pair of memory cells CEL1, CEL2is formed is an isolated well, of the “triple well” type, electrically isolated from the remainder of the carrier substrate PSUB by isolation areas. Typically, the isolation areas of a triple well comprise an embedded layer NISO and lateral wells with a conductivity type that is opposite the conductivity type of the carrier substrate PSUB and of the triple well semiconductor IPW. According to another embodiment, the carrier substrate PSUB is of the Fully-Depleted Silicon On Insulator (FDSOI) hybrid type, i.e. an FDSOI well comprising a part in which the depleted silicon and the insulation have been removed, exposing the underlying carrier well in a “conventional” configuration that can receive the well IPW in which the pair of memory cells CEL1, CEL2is formed. In this type of hybrid FDSOI structure, a topological demarcation exists between the part in which the depleted silicon and insulation layers have been removed and the part in which the depleted silicon and insulation layers have not been removed, with the respective surfaces of these parts not being at the same height, making a “step” between them. This height difference can introduce constraints in the design and manufacturing steps, particularly in the manufacturing steps carried out concomitantly in the two parts, such as the steps requiring polishing to be carried out from the upper surfaces of layers deposited in the two parts. However, as will be seen hereafter, manufacturing pairs of memory cells CEL1, CEL2can be implemented separately from the steps of manufacturing other parts of the integrated circuit IC, for example, a logic part using CMOS technology. Thus, the manufacture of the pair of memory cells CEL1, CEL2is not necessarily subject to the constraints introduced by the topological demarcation of a hybrid FDSOI well structure. Each memory cell CEL1, CEL2comprises a vertical state transistor T1, T2, which is embedded in a semiconductor well IPW and which particularly can be selected by a vertical selection transistor ST1, ST2embedded in the well IPW. The vertical state transistor T1, T2embedded in the well IPW comprises an embedded control gate CG and the vertical selection transistor ST1, ST2embedded in the well IPW also comprises an embedded selection gate SG. The pair of memory cells CEL1, CEL2is formed in a trench vertically extending in the semiconductor well IPW. The selection gate SG is common to the two selection transistors ST1, ST2of the pair of twin memory cells CEL1, CEL2and, similarly, the control gate CG is common to the two state transistors T1, T2of the pair of twin memory cells CEL1, CEL2. The common control gate CG is located above the common selection gate SG and both are thus “embedded” in the well IPW. The common selection gate SG can comprise a conductive area such as a doped polycrystalline silicon, metal or silicide area. Similarly, the common control gate CG can comprise a conductive area such as a polycrystalline silicon, metal or silicide area. The selection gate SG and the control gate CG are mutually electrically isolated by a gate isolation area GI. The gate isolation area GI can be formed, for example, by growing a thick silicon oxide (such as silicon dioxide SiO2), after depositing and etching the conductive area of the selection gate SG. The selection gate SG area is also surrounded by a gate dielectric layer GO. The gate dielectric layer GO, for example, made of silicon oxide, electrically isolates the selection gate SG area laterally with the well IPW, and also in the bottom of the trench with an embedded layer NISO forming a source area S. In the example of an isolated well IPW of the triple well type, the layer NISO forming the source area S advantageously can simultaneously form the embedded layer of the aforementioned isolation areas. Such a source area S belonging to the embedded semi-conductive area NISO located in the vicinity of the bottom of the trench is commonly denoted using the term “source plane”. This structure provided with a source plane NISO corresponds, according to one embodiment, to a memory configuration of the NOR type, advantageously allowing page erasures and advantageously using hot-carrier injection programming (see below with reference toFIG.7). Furthermore, each state transistor T1, T2of a pair of twin memory cells CEL1, CEL2comprises a respective drain area D1, D2located in the vicinity of a front face FA delimiting an upper surface of the well IPW. The drain areas D1and D2are located either side of the common control gate CG. The gate dielectric layer GO is configured to allow the formation of a vertical channel area along the trench, between the source area S and the drain area D1or D2, in the case of biasing as described hereafter with reference toFIG.7. The control gate area CG is also laterally surrounded by two dielectric areas QDi forming, on the sides of the common control gate area CG, two charge trapping dielectric interfaces QTI1, QTI2between the control gate CG and the well IPW. The charge trapping dielectric interfaces QTI1and QTI2are capable of permanently (or in a non-volatile manner, i.e. including in the absence of a power supply) and reversibly (i.e. the digital data can be modified by means of erasures and/or programming) storing a charge representing one or more item(s) of digital data. Indeed, the dielectric areas QDi are configured to allow injections and extractions of electric charges in “traps” belonging to the charge trapping dielectric interfaces QTI1, QTI2, in the case of biasing as described hereafter with reference toFIG.7. Charge extractions can involve injecting charges of the opposite sign. The dielectric areas QDi forming said charge trapping dielectric interfaces QTI1, QTI2have a first dielectric layer Di10intended to trap electric charges, surrounded by two second dielectric layers Di21, Di22. The first dielectric layer Di10can comprise silicon nitride and the second dielectric layers Di21, Di22can comprise silicon oxide. For example, the second outer dielectric layer Di21(on the well IPW side) can comprise or be formed by the gate dielectric layer GO that surrounds the selection gate area SG and is previously deposited on the sides and the bottom of the exposed trench. In other words, the gate dielectric layer GO can surround the trench on its bottom and over the full height of its sides and the second outer dielectric layer Di21comprises the part of the gate dielectric layer GO located facing the control gate area CG. An additional formation of oxide can fulfil the requirement of completing the gate dielectric layer GO for forming the second outer dielectric layer Di21of the charge trapping interfaces QTI1, QTI2. Furthermore, the gate isolation area GI can comprise part of a dielectric area QDi at the bottom of the conductive area of the control gate CG. Indeed, the first dielectric layer Di10and the second dielectric layer Di22can be formed following the growth of the silicon oxide on the conductive area of the selection gate SG and form the gate isolation area GI in combination with the oxide thus grown. In any event, the first dielectric layer Di10, the second dielectric layers Di21, Di22, the gate dielectric layer GO and the gate isolation area GI can be produced according to formations that are common to at least some of them, as well as according to formations that are independent and are respectively dedicated to each of them. For example, in order to form the second dielectric layer Di21, removing the gate dielectric layer GO after the formation of the selection gate SG and distributing the exposed silicon present on the sides of the trench also can be contemplated. The formation of the second dielectric layer Di21thus can also contribute to the formation of the gate isolation area GI. The twin memory cells CEL1, CEL2are thus denoted “twins” since they have said selection gate SG, said control gate CG and said source area S in the source plane NISO in common. FIG.2shows a section view in the II-II plane ofFIG.4of the pair of memory cells CEL1, CEL2, i.e. a vertical section view in the length of the trench, whereasFIG.1shows a vertical section in the width of the trench. The common control gate CG is located above the common selection gate SG and below a front face FA delimiting an upper surface of the well IPW. The conductive area of the selection gate SG further comprises a connection area CR providing electrical continuity between the common selection gate SG, located under the common control gate CG, and a contact zone CZ located in the vicinity of the front face FA of the well IPW. In this example, the connection area CR is located at a longitudinal end of the trench, between the control gate CG and the well IPW. The connection area CR is electrically isolated from the common control gate CG by the gate isolation layer GI extending vertically along said connection area CR. The gate oxide GO surrounding the common selection gate SG electrically isolates the connection area CR from the well IPW. Optionally, a dielectric spacer can be formed between the common control gate CG and the connection area CR in the vicinity of the front face FA in order to avoid electrical coupling or electrical short-circuits. The structure comprising the selection gate SG (in the bottom of the trench) and the connection area CR (vertical) can be formed, for example, by depositing an excessive amount of a selection gate conductor material overflowing the trench on the front face FA; by Chemical-Mechanical Planarization (CMP) of this excessive amount to the level of the front face FA; by selective etching of the selection gate conductor material to the desired depth, with the selective etching being anisotropic and hidden in the vicinity of the surface of the connection column CR. The contact zone CZ conventionally originates, for example, from silicification (in the case of a selection gate conductor material of the doped polycrystalline silicon type), in order to allow, for example, connection to a metal track routing biasing voltages of the selection gate SG. FIG.3shows a section view in the III-III plane ofFIG.4, i.e. a vertical section in the width of the trench, longitudinally offset relative to the I-I plane. Indeed, while the I-I plane is located in part, called “active area”, of the pair of memory cells CEL1, CEL2in which the front face FA of the semiconductor well IPW is exposed and typically comprises integrated areas, the III-III plane is located outside the “active area”, between two pairs of memory cells CEL1, CEL2in a row, the semiconductor well IPW being covered at this location by lateral isolation areas STI. The lateral isolation areas STI located on the surface of the well IPW, for example, of the “shallow isolation trench” type, conventionally allow lateral isolation of two “active areas” of neighbouring devices formed along the same trench. The trench of the pair of memory cells CEL1, CEL2extends perpendicular to said lateral isolation areas STI of the well IPW. In this embodiment, the control gate CG extends less deeply in the well IPW than the lateral isolation areas STI. Indeed, as will become apparent hereafter with reference toFIG.4, such a configuration, in which the charge trapping dielectric interfaces are only adjacent to the semiconductor well IPW at the active areas, allows any diffusion of a parasitic current to be avoided between a line of selected bits and a neighbouring line of non-selected bits, along a selected line of words. FIG.4shows a top view of the pair of memory cells CEL1, CEL2in the memory plane PM in the vicinity of the front face FA delimiting an upper surface of the well IPW in the IV-IV plane ofFIGS.1,2and3. The memory plane PM comprises numerous memory cells that are arranged matrix-wise in rows RG and columns COL and are accessible via conductive lines, particularly word lines WL and control gate lines CGL, in the direction of the rows RG, and bit lines BL1, BL2, in the direction of the columns COL. Given that the columns COL of memory cells comprise pairs of twin memory cells CEL1, CEL2, the memory plane PM comprises two bit lines BL1, BL2per column COL of memory cells. The two memory cells CEL1, CEL2of a pair of twin memory cells are also respectively connected to the two bit lines BL1, BL2of the column COL. FIG.4shows only one pair of memory cells CEL1, CEL2, the two bit lines BL1, BL2of the respective column, as well as the respective word lines WL and control gate lines CGL. The trench containing the common control gate CG and the common selection gate SG extends longitudinally in the direction of the rows RG of the memory plane PM. Even though they are not shown, other similar trenches are formed in parallel in the memory plane PM and other “active areas” are formed in parallel in the memory plane PM, along bit lines BL1, BL2. The pairs of memory cells CEL1, CEL2are thus arranged matrix-wise at each “intersection” between a row RG and a column COL. The word lines WL are advantageously formed by the conductive areas of the selection gate SG in the respective trenches and the control gate lines CGL are formed by the conductive areas of the control gate CG in the respective trenches. The bit lines BL1, BL2can, for their part, be formed by metal tracks extending above the memory plane PM in the direction of the columns COL and can be connected to the areas of respective drains D1, D2of the two twin memory cells CEL1, CEL2. Typically, vertical conducting vias allow the drain area D1, D2to be electrically connected to the respective bit line BL1, BL2. An example of the configuration of the memory plane PM, particularly in that it comprises two bit lines per column of memory cells, is disclosed in the patent application filed in the U.S. of America under Ser. No. 15/810,979, in particular with reference to appendedFIGS.2and4of said patent application, the entire content of which is incorporated. FIG.5shows variations of the previously described embodiment. In these variations, said charge trapping dielectric interfaces QTI1, QTI2are located on a local part of the sides of the control gate CG. According to one embodiment, the first dielectric layer Di10and the second inner dielectric layer Di22(on the control gate CG side) are formed in like manner to a conventional formation of gate spacers, i.e. by isotropic growth or deposition and anisotropic etching leaving a residue of the grown or deposited material on the vertical walls. Of course, in this case this etching would have been taken into account during the formation of the gate isolation area GI, which in this case is exposed to the anisotropic etching. Thus, said charge trapping dielectric interfaces QTI1, QTI2are located on a local part of the sides of the common control gate CG, in the vicinity of the common selection gate SG, for example, adjoining the gate isolation area GI and at a distance from a front face FA delimiting an upper surface of the well IPW. Thus, the trapped charges will remain close to their initial injection zone, avoiding a phenomenon of spreading the location of the trapped charges, which can result from multiple writing operations and can degrade the performance of the device. According to another embodiment, said charge trapping dielectric interfaces QTI1, QTI2comprise silicon nanocrystals. The charge trapping dielectric interfaces QTI1, QTI2comprising silicon nanocrystals also can be located on the sides of the common control gate CG, in the vicinity of the common selection gate SG, for example, adjoining the gate isolation area GI and at a distance from a front face FA delimiting an upper surface of the well IPW. For example, the silicon nanocrystals are obtained by means of partial chemical vapor deposition (CVD) of a polycrystalline silicon layer. Thus, a silicon nanocrystal is, for example, a nanometric sized isolated silicon crystalline structure, such as a grain of polycrystalline silicon. The nanocrystals thus act like a floating gate of a typical floating gate transistor, but with nanometric dimensions forming highly localized charge traps. The use of such nanocrystals also allows the location of the trapped charges to be enhanced and also increases the amount of trappable charges. FIG.7shows a table of examples of voltage values in volts (V) to be applied to the control gate CG, the selection gate SG, the drain area D, the source area S and the well IPW, in order to implement programming Wr, erasing Er and reading Rd of data in a memory cell. It is to be noted that the well IPW is of the well type that is electrically isolated from the remainder of the carrier well. The term “drain area D” relates to the drain area D1, D2of the state transistor T1, T2of the respective memory cell CEL1, CEL2of a pair of twin memory cells as previously described. Similarly, the term “charge trapping dielectric interface QTI” refers to the charge trapping dielectric interface QTI1, QTI2of the respective memory cell CEL1, CEL2of the pair of twin memory cells. During programming Wr, electric charges are injected into the first dielectric layer Di10of the charge trapping dielectric interface QTI through the second outer dielectric layer (on the well IPW side) Di21. The charges originate from a channel area formed in the well IPW along the trench between the source area S and the drain area D and are transmitted by an effect called source-side hot-carrier injection (or commonly called “SSI” (Source Side Injection)). For example, the voltages that allow such hot-carrier injection are from 5 V to 10 V on the control gate CG; the sufficient selection gate voltage Vsg for forming a channel area in the well IPW along the selection gate SG (from 0.5 V to 3 V) is applied to the selection gate SG; from 3 V to 4.5 V on the drain area D; and 0 V on the source area S and in the well IPW. This type of source side hot-carrier injection programming particularly offers the advantages of not requiring biasing of opposite signs, of having the physical granularity of one bit (one memory cell) and of being quick to execute. During erasing, the charges previously injected and trapped in the charge trapping dielectric interface QTI can be extracted therefrom through the Fowler-Nordheim effect. An electric field of approximately 15 MVcm−1between the control gate CG and the well IPW is sufficient to obtain the Fowler-Nordheim effect. For example, voltages allowing the Fowler-Nordheim effect to be implemented that extracts the trapped charges are approximately −10 V on the control gate CG; and from 5 V to 10 V on the well IPW. Similarly, voltages of 5 V to 10 V possibly can be applied to the selection gate SG, the drain area D and the source area S. However, it is possible, particularly relative to the desired operation or reliability constraints, to leave some floating nodes (particularly the selection gate SG) or to apply different voltages to each of the nodes. According to an alternative, extraction of the trapped charges can be implemented by opposite charge hot-carrier injection (denoted “hot-hole injection”). Given the configurations of the selection gate SG and control gate CG areas that circulate in the direction of the rows RG of the memory plane PM and the source areas S adjoining a common source plane NISO, the erasure voltages advantageously can be applied to a group of memory cells belonging to the same row RG, generally a page. This corresponds to advantageous memory technology called NOR memory. When reading, a control gate voltage Vcg, which allows a channel area to be formed in the well IPW along the control gate CG, is applied to the control gate CG; a sufficient selection gate voltage Vsg rd for forming a channel area in the well IPW along the selection gate SG is applied to the selection gate SG; a low potential difference is applied between the drain area D and the source area S, meeting the requirements relating to the aforementioned voltages, for example, from 0.4 V to 0.7 V on the drain area D and 0 V on the source area S; and 0 V in the well IPW. When charges are trapped in the charge trapping dielectric interface, they form a screen for the control gate potential (at the reading voltage Vcg) and disrupt the formation of the channel area. A lack of trapped charges in the charge trapping dielectric interface does not form a control gate potential screen (at the reading voltage Vcg), allowing the channel area to be formed without any disruption. Thus, a measurement of a source-drain current, which is intended to flow in a formed channel area, allows the digital information stored by the read memory cell to be obtained. Such voltages can be generated, for example, by charge pumps and can be distributed to said gate CG, SG and drain D and source S areas by control and distribution means and can be routed via the aforementioned control gate CGL, word WL and bit BL1, BL2lines. Of course, the values of the voltages have been provided by way of an example of an order of magnitude and are by no means limiting. Furthermore, the invention is not limited to the previously described embodiments but includes all variations and combinations. FIGS.8A-8F and9A-9Fillustrate a semiconductor memory during various stages of fabrication in accordance with embodiments of the present invention.FIGS.8A-8Fcorrespond to the section view in the I-I plane ofFIG.4whileFIGS.9A-9Fillustrate the corresponding semiconductor memory along the section view in the II-II plane ofFIG.4. Referring toFIGS.8A and9A, a pair of memory cells can be produced in a semiconductor well IPW, incorporated in a carrier substrate PSUB. According to one embodiment, the semiconductor well IPW is an isolated well, of the “triple well” type, electrically isolated from the remainder of the carrier substrate PSUB by isolation areas. The isolation areas of a triple well may comprise an embedded layer NISO and lateral wells with a conductivity type that is opposite the conductivity type of the carrier substrate PSUB and of the triple well semiconductor well IPW. Referring toFIGS.8B and9B, a trench etch is performed to form trenches10. As illustrated inFIGS.8C and9C, a source implant may be implanted through the trenches10to form source regions15thereby the source plane discussed above. After depositing a gate dielectric layer GO, a first conductive material20such as polysilicon, metal, or silicide, is deposited into the trenches10, which eventually forms the selection gate. The first conductive material20is overfilled. Referring toFIGS.8D and9D, the exposed first conductive material20is etched to form a partially filled trench30and a contact area25. In another embodiment, the exposed first conductive material20is planarized with a chemical mechanical polishing process followed by an etching process. In some embodiments, the partially filled trench30may be formed directly with the deposition of the first conductive material20. Referring toFIGS.8E and9E, a gate isolation area GI is deposited into the partially filled trench30. As described earlier, the gate isolation area GI can be formed, for example, by growing a thick silicon oxide (such as silicon dioxide SiO2) over the first conductive material20. Dielectric areas QDi are formed along the sidewalls of the partially filled trench30. The dielectric areas QDi include a first dielectric layer Di10intended to trap electric charges, and is surrounded by two second dielectric layers Di21, Di22. In one embodiment, the first dielectric layer Di10can comprise silicon nitride and the second dielectric layers Di21, Di22can comprise silicon oxide. For example, the second outer dielectric layer Di21(on the well IPW side) can comprise or be formed by the gate dielectric layer GO that surrounds the selection gate area SG and is previously deposited on the sides and the bottom of the exposed trench10. A second conductive material40such as polysilicon, metal, or silicide, is deposited into the partially filled trench30over the dielectric areas QDi. The second conductive material40may be overfilled to ensure that the partially filled trench30is completely filled. As next illustrated inFIGS.8F and9F, a planarization followed by etching process is used to remove the overfilled second conductive material40thereby forming a control gate CG. Alternately, a direct etching process may be sufficient in some embodiments. In some embodiments, a spacer may be added to the have reliable separation between the contact area25and the control gate CG. Further processing may continue as in conventional processing, for example, to form drain regions and contacts. The structures illustrated inFIGS.8F and9Fcorrespond toFIGS.1and2respectfully. | 35,636 |
11943933 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Elements with the same reference numerals refer to the same element, and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise. A ferroelectric material is a material that may have spontaneous nonzero electrical polarization (i.e., non-zero total electrical dipole moment) when the external electrical field is zero. The spontaneous electrical polarization may be reversed by a strong external electric field applied in the opposite direction. The electrical polarization is dependent not only on the external electrical field at the time of measurement, but also on the history of the external electrical field, and thus, has a hysteresis loop. The maximum of the electrical polarization is referred to as saturation polarization. The electrical polarization that remains after an external electrical field that induces saturation polarization is no longer applied (i.e., turned off) is referred to as remnant polarization. The magnitude of the electrical field that needs to be applied in the opposite direction of the remnant polarization in order to achieve zero polarization is referred to as coercive electrical field. For the purposes of forming memory devices, it is generally desirable to have high remnant polarization and high coercive field. High remnant polarization may increase the magnitude of an electrical signal. High coercive field makes the memory devices more stable against perturbations caused by noise-level electrical field and interferences. Generally, the structures and methods of the present disclosure may be used to form a ferroelectric memory device including at least one ferroelectric memory cell connected to at least one thin film transistor embedded in a back-end-of-line (BEOL) metal interconnect level. A field effect transistor including a single crystalline semiconductor channel may be provided on a semiconductor material layer in a substrate that underlies the at least one ferroelectric memory cell and the at least one thin film transistor. Each ferroelectric memory cell may include a first electrode which is a first node, a ferroelectric dielectric material layer, and a second electrode which is a second node. A thin film transistor may be connected to a node of a ferroelectric memory cell, and a field effect transistor located on the semiconductor material layer may be connected to another node of the ferroelectric memory cell. Generally, the field effect transistor may provide a larger per-area current density than thin film transistors, and thus, may be used as a programming transistor for the ferroelectric memory cell. Alternatively, a thin film transistor may be used as a programming transistor. A series connection including a field effect transistor, a ferroelectric memory cell, and a thin film transistor may be used to program the ferroelectric memory cell into a first ferroelectric state in which the electrical polarization of the ferroelectric dielectric material layer points toward the first electrode, and to program the ferroelectric memory cell into a second ferroelectric state in which the electrical polarization of the ferroelectric dielectric material layer points toward the second electrode. The asymmetry in the material composition of the first electrode and the second electrode may cause the ferroelectric memory cell to provide different capacitances or different tunneling resistances so that encoding of a data bit in the ferroelectric memory cell is possible. A two-dimensional array of ferroelectric memory cells and an array of thin film transistors may be provided. Field effect transistors on the semiconductor material layer may be configured to drive a respective row or column of ferroelectric memory cells. Each of the thin film transistor may be configured to access a respective one of the ferroelectric memory cells. Alternatively, thin film transistors may be configured to drive a respective column or row of ferroelectric memory cells. Each field effect transistor on the semiconductor material layer may be configured to access a respective one of the ferroelectric memory cells. As a further alternative, field effect transistors on the semiconductor material layer may be configured to drive a respective row or column of ferroelectric memory cells. Each thin film transistor may be configured to drive a respective column or row of the ferroelectric memory cells. Still alternatively, field effect transistors on the semiconductor material layer may be configured to drive a respective one of ferroelectric memory cells, and each thin film transistor may be configured to drive a respective one of the ferroelectric memory cells. The various aspects of the present disclosure are now described in detail with reference to accompanying drawings. Referring toFIG.1, an exemplary structure according to an embodiment of the present disclosure is illustrated. The exemplary structure includes a substrate8, which may be a semiconductor substrate such as a commercially available silicon substrate. The substrate8may include a semiconductor material layer9at least at an upper portion thereof. The semiconductor material layer9may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon. Shallow trench isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures720. Field effect transistors701may be formed over the top surface of the semiconductor material layer9. For example, each field effect transistor701may include a source region732, a drain region738, a semiconductor channel735that includes a surface portion of the substrate8extending between the source region732and the drain region738, and a gate structure750. The semiconductor channel735may include a single crystalline semiconductor material. Each gate structure750may include a gate dielectric layer752, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal-semiconductor alloy region742may be formed on each source region732, and a drain-side metal-semiconductor alloy region748may be formed on each drain region738. The exemplary structure may include a memory array region100in which an array of ferroelectric memory cells may be subsequently formed. The exemplary structure may further include a peripheral region200in which metal wiring for the array of ferroelectric memory devices is provided. Generally, the field effect transistors701in the CMOS circuitry700may be electrically connected to an electrode of a respective ferroelectric memory cell by a respective set of metal interconnect structures. Devices (such as field effect transistors701) in the peripheral region200may provide functions that operate the array of ferroelectric memory cells to be subsequently formed. Specifically, devices in the peripheral region may be configured to control the programming operation, the erase operation, and the sensing (read) operation of the array of ferroelectric memory cells. For example, the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer9may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry700. One or more of the field effect transistors701in the CMOS circuitry700may include a semiconductor channel735that contains a portion of the semiconductor material layer9in the substrate8. If the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel735of each field effect transistor701in the CMOS circuitry700may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a plurality of field effect transistors701in the CMOS circuitry700may include a respective node that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed. For example, a plurality of field effect transistors701in the CMOS circuitry700may include a respective source region732or a respective drain region738that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed. In one embodiment, the CMOS circuitry700may include a programming control circuit configured to control gate voltages of a set of field effect transistors701that are used for programming a respective ferroelectric memory cell and to control gate voltages of thin film transistors to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a respective ferroelectric dielectric material layer in a selected ferroelectric memory cell into a first polarization state in which electrical polarization in the ferroelectric dielectric material layer points toward a first electrode of the selected ferroelectric memory cell, and to provide a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state in which the electrical polarization in the ferroelectric dielectric material layer points toward a second electrode of the selected ferroelectric memory cell. Various metal interconnect structures embedded in dielectric material layers may be subsequently formed over the substrate8and the semiconductor devices thereupon (such as field effect transistors701). In an illustrative example, the dielectric material layers may include, for example, a contact-level dielectric material layer601, a first metal-line-level dielectric material layer610, and a second line-and-via-level dielectric material layer620. The metal interconnect structures may include device contact via structures612formed in the contact-level dielectric material layer601and contacting a respective component of the CMOS circuitry700, first metal line structures618formed in the first metal-line-level dielectric material layer610, first metal via structures622formed in a lower portion of the second line-and-via-level dielectric material layer620, and second metal line structures628formed in an upper portion of the second line-and-via-level dielectric material layer620. Each of the dielectric material layers (601,610,620) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612,618,622,628) may include at least one conductive material, which may be a combination of a metallic liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures622and the second metal line structures628may be formed as integrated line and via structures by a dual damascene process. While the present disclosure is described using an embodiment in which an array of memory cells formed over the second line-and-via-level dielectric material layer620, embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level. An array of thin film transistors and an array of ferroelectric memory cells may be subsequently deposited over the dielectric material layers (601,610,620) that embed the metal interconnect structures (612,618,622,628). The set of all dielectric material layer that are formed prior to formation of an array of thin film transistors or an array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (601,610,620). The set of all metal interconnect structures that is embedded in the lower-level dielectric material layers (601,610,620) is herein referred to as first metal interconnect structures (612,618,622,628). Generally, first metal interconnect structures (612,618,622,628) embedded within at least one lower-level dielectric material layer (601,610,620) may be formed over the semiconductor material layer9that is located in the substrate8. In one embodiment, thin film transistors (TFTs) may be formed in a metal interconnect level that overlies that metal interconnect levels that contain the lower-level dielectric material layers (601,610,620) and the first metal interconnect structures (612,618,622,628). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower-level dielectric material layers (601,610,620). The planar dielectric material layer is herein referred to as a planar insulating spacer layer630A. The planar insulating spacer layer630A includes a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the planar insulating spacer layer630A may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be used. Referring toFIG.2, at least one metallic material may be deposited on the top surface of the planar insulating spacer layer630A. The deposited metallic material may be lithographically patterned into discrete metallic strips to form at least one thin film transistor (TFT) gate electrode854, which may be an array of TFT gate electrodes854. A one-dimensional array or a two-dimensional array of TFT gate electrodes854may be formed over the at least one lower-level dielectric material layer (601,610,620). In embodiments in which a one-dimensional array of TFT gate electrodes854is used, each TFT gate electrode854may be used as a common TFT gate electrode854for a row of field effect transistors701. In one embodiment, the TFT gate electrodes854may be laterally spaced apart along a first horizontal direction hd1(which is referred to as a column direction) and may laterally extend along a second horizontal direction hd2(which is herein referred to as a row direction) that is perpendicular to the first horizontal direction hd1. The first horizontal direction hd1is within the plane of the vertical cross-sectional view ofFIG.2, and the second horizontal direction hd2is perpendicular to the plane of the vertical cross-sectional view ofFIG.2. Each TFT gate electrode854may have a uniform width along the first horizontal direction hd1, which is the gate length of a respective thin film transistor to be subsequently formed. For example, the gate length of thin film transistors to be subsequently formed may be in a range from 20 nm to 200 nm, although lesser and greater gate lengths may also be used. The at least one metallic material of the TFT gate electrodes854may include at least one conductive metallic nitride material (such as TiN, TaN, and/or WN), an elemental metal (such as W, Cu, Ru, Co, Mo, Ni, Al, etc.), and/or an intermetallic alloy of at least two elemental metals. The at least one metallic material of the TFT gate electrodes854may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating. The thickness of the TFT gate electrodes854may be in a range from 10 m, to 50 nm, although lesser and greater thicknesses may also be used. The at least one metallic material may be patterned into the TFT gate electrodes854, for example, by application and patterning of a photoresist layer over the at least one metallic material, and by transfer of the pattern in the photoresist layer through the at least one metallic material using an etch process such as an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing. Referring toFIG.3, a thin film transistor (TFT) gate dielectric layer852may be formed over the TFT gate electrodes854by conformal deposition of a gate dielectric material. The gate dielectric material that may be used for the TFT gate dielectric layer852include, but are not limited to, silicon oxide, silicon oxynitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or a stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. The TFT gate dielectric layer852may be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the TFT gate dielectric layer852may be in a range from 1 nm to 12 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses may also be used. Referring toFIG.4, a semiconducting metal oxide material layer may be deposited over the TFT gate dielectric layer852. The semiconducting metal oxide material layer may be patterned into at least one semiconducting metal oxide layer835, such as a two-dimensional array of semiconducting metal oxide layers835. The semiconducting metal oxide material layer includes a semiconducting metal oxide material, i.e., a metal oxide material that is capable of providing electrical conductivity in a range from 1.0 S/m to 1.0×105S/m upon suitable doping with electrical dopants (which may be p-type dopants or n-type dopants). In an intrinsic state or under a condition of a low-level electrical doping, a semiconducting metal oxide material may be semiconducting or insulating, and may have electrical conductivity generally in a range from 1.0×10−10S/m to 1.0×105S/m. Exemplary semiconducting metal oxide materials that may be used for the semiconducting metal oxide material layer include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconducting metal oxide materials are within the contemplated scope of disclosure. In one embodiment, the semiconducting metal oxide material layer may include indium gallium zinc oxide. The semiconducting metal oxide material layer may include a polycrystalline semiconducting metal oxide material, or an amorphous semiconducting metal oxide material that may be subsequently annealed into a polycrystalline semiconducting metal oxide material having a greater average grain size. The semiconducting metal oxide material layer may be deposited by physical vapor deposition. The thickness of the semiconducting metal oxide material layer may be in a range from 1 nm to 100 nm, such as from 2 nm to 50 nm and/or from 4 nm to 15 nm, although lesser and greater thicknesses may also be used. A photoresist layer (not shown) may be applied over the semiconducting metal oxide material layer, and may be lithographically patterned into at least one discrete photoresist material portion. In one embodiment, the photoresist layer may be patterned into a two-dimensional array of photoresist material portions such that each patterned photoresist material portion overlies a respective one of the TFT gate electrodes854. In one embodiment, a row of patterned photoresist material portions that are arranged along the second horizontal direction hd2may overlie a TFT gate electrode854having a strip shape that extends along the second horizontal direction. Unmasked portions of the semiconducting metal oxide material layer may be etched, for example, by an anisotropic etch process using the photoresist material portions of the photoresist layer as an etch mask. Remaining portions of the semiconducting metal oxide material layer comprise at least one semiconducting metal oxide layer835, which may be a two-dimensional array of semiconducting metal oxide layers835. The photoresist layer may be subsequently removed, for example, by ashing. Each semiconducting metal oxide layer835may have a rectangular horizontal cross-sectional shape or a rounded rectangular horizontal cross-sectional shape. Each semiconducting metal oxide layer835may have a pair of lengthwise edges that laterally extend along the first horizontal direction hd1. Each semiconducting metal oxide layers835may also have a pair of widthwise edges that laterally extend along the second horizontal direction hd2. A portion of a TFT gate electrode854underlies a middle portion of a semiconducting metal oxide layer835such that the TFT gate electrode854crosses the two lengthwise edges of the semiconducting metal oxide layer835in a plan view. Optionally, electrical dopants (such as p-type dopants or n-type dopants) may be implanted into portions of the semiconducting metal oxide layers835that do not overlie the TFT gate electrodes854. In this embodiment, a masked ion implantation process may be used. Referring toFIG.5, at least one conductive material may be deposited over the at least one semiconducting metal oxide layer835(such as a two-dimensional array of semiconducting metal oxide layers835). The at least one conductive material may include a conductive metallic nitride material (such as TiN, TaN, and/or WN), an elemental metal (such as W, Ti, Ta, Mo, Ru, Co, Ni, Cu, Al, etc.), and/or an intermetallic alloy. Other suitable conductive materials are within the contemplated scope of disclosure. The at least one conductive material may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, and/or electroless plating. The thickness of the at least one conductive material may be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater thicknesses may also be used. The at least one conductive material may be patterned into source contact structures832and drain contact structures838. For example, a photoresist layer (not shown) may be applied over the at least one conductive material, and may be lithographically patterned into discrete material portions that cover end portions of each semiconducting metal oxide layer835. The portions of the semiconducting metal oxide layers835that are covered by the photoresist layer may be laterally offset from areas that overlap with the TFT gate electrodes854along the first horizontal direction hd1, i.e., the lengthwise direction of each semiconducting metal oxide layer835. Unmasked portions of the at least one conductive material may be removed, for example, by performing an anisotropic etch process using the photoresist layer as an etch mask. Remaining portions of the at least one conductive material include source contact structures832and drain contact structures838. A pair of a source contact structure832and a drain contact structure838may be formed on each semiconducting metal oxide layer835. Each source contact structure832may be formed on a source region of a respective semiconducting metal oxide layer835. Each drain contact structure838may be formed on a drain region of a respective semiconducting metal oxide layer835. A portion of each semiconducting metal oxide layer835that overlies a TFT gate electrode854and located between a pair of a source region and a drain region constitutes a channel region of a thin film transistor801. At least one thin film transistor801may be formed over the at least one lower-level dielectric material layer (601,610,620). In one embodiment, the semiconducting metal oxide layers835may be polycrystalline. Each thin film transistor801may comprise a polycrystalline semiconducting metal oxide material as a channel material. In one embodiment, a two-dimensional array of thin film transistors801may be formed over the at least one lower-level dielectric material layer (601,610,620). In one embodiment, the two-dimensional array of thin film transistors801may be formed as a two-dimensional periodic rectangular array in which a set of TFT gate electrodes854that laterally extend along the second horizontal direction hd1are repeated along the first horizontal direction with a first pitch, which is the pitch of the two-dimensional periodic rectangular array along the first horizontal direction hd1. The two-dimensional periodic rectangular array may have a second pitch along the second horizontal direction hd2. Each TFT801may include a respective TFT gate electrode854, a respective portion of the TFT gate dielectric layer852that overlies the TFT gate electrode854, a respective semiconducting metal oxide layer835that overlies the respective TFT gate electrode854, a respective source contact structure832that contacts a top surface of a source region which is a first end portion of the respective semiconducting metal oxide layer835, and a respective drain contact structure838that contacts a top surface of a drain region which is a second end portion of the respective semiconducting metal oxide layer835. Referring toFIG.6, a TFT-level dielectric matrix layer630B may be deposited over the planar insulating spacer layer630A and the thin film transistors801, and may be planarized to provide a flat top surface. The TFT-level dielectric matrix layer630B may include a self-planarizing dielectric material such as a flowable oxide (FOX) or a planarizable dielectric material such as undoped silicate glass or a doped silicate glass. The planar insulating spacer layer630A and the TFT-level dielectric matrix layer630B are collectively referred to as a TFT-level dielectric material layer (630A,630B). In embodiments in which the TFT-level dielectric material layer (630A,630B) is formed directly above the level of the second line-and-via-level dielectric material layer620, the TFT-level dielectric material layer (630A,630B) may be a third line-and-via-level dielectric material layer630. In this embodiment, the thin film transistors801may be embedded within the third line-and-via-level dielectric material layer630. In this embodiment, the third line-and-via-level dielectric material layer630may include the planar insulating spacer layer630A that is formed over the second line-and-via-level dielectric material layer prior to formation of the thin film transistors801, and a TFT-level dielectric matrix layer630B that is formed over the thin film transistors801. Second metal via structures632and third metal line structures638may be formed within the third line-and-via-level dielectric material layer630. For example, a first photoresist layer (not shown) may be applied over the third line-and-via-level dielectric material layer630, and may be lithographically patterned to form a pattern of line-shaped trenches or pad-shaped trenches. A first anisotropic etch process may be performed to form line trenches and/or pad trenches in an upper portion of the third line-and-via-level dielectric material layer630. The line trenches and/or the pad trenches may overlie a respective set of at least one node of the thin film transistors801. The first photoresist layer may be removed, and a second photoresist layer may be applied over the third line-and-via-level dielectric material layer630. The second photoresist layer may be lithographically patterned to form discrete openings located within the areas of the line trenches and/or pad trenches. A second anisotropic etch process may be performed to form via cavities in areas that underlie the openings in the second photoresist layer. Each of the via cavities may vertically extend to a respective node of the thin film transistors801. For example, a first subset of the via cavities may vertically extend to a top surface of a respective one of the source contact structures832. A second subset of the via cavities may vertically extend to a top surface of a respective one of the drain contact structures838. A third subset of the via cavities may vertically extend to a top surface of a respective one of the TFT gate electrodes854. The second photoresist layer may be subsequently removed, for example, by ashing. Integrated line and via cavities and optional pad cavities may be formed in the third line-and-via-level dielectric material layer630. Each integrated line and via cavity may include a line cavity and at least one via cavity. Each pad cavity may include a void configured to form a metal pad therein. At least one conductive material such as a combination of a conductive metallic nitride liner and a conductive metallic fill material layer may be deposited in each of the cavities in the third line-and-via-level dielectric material layer630. For example, the conductive metallic nitride liner may include a conductive metallic material such as TiN, TaN, and/or WN. The conductive metallic fill material layer may include a metallic fill material such as W, Ti, Ta, Mo, Ru, Co, Cu, another elemental metal, or an intermetallic alloy. Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the third line-and-via-level dielectric material layer630. Remaining portions of the at least one conductive material comprise second metal via structures632and third metal line structures638. Each contiguous combination of a third metal line structure638and at least one second metal via structure632forms an integrated line and via structure (632,638). A subset of the second metal via structures632may contact a respective one of the TFT gate electrodes854, the source contact structures832, and the drain contact structures838. The thin film transistors801may function as access transistors that control access to a respective single ferroelectric memory cell, a respective row of ferroelectric memory cells to be subsequently formed, or a respective column of ferroelectric memory cells to be subsequently formed. A dielectric cap layer108and a connection-via-level dielectric material layer110may be sequentially formed over the metal interconnect structures and the dielectric material layers. For example, the dielectric cap layer108may be formed on the top surfaces of the third metal line structures638and on the top surface of the third line-and-via-level dielectric material layer630. The dielectric cap layer108includes a dielectric capping material that may protect underlying metal interconnect structures such as the third metal line structures638. In one embodiment, the dielectric cap layer108may include a material that may provide high etch resistance, i.e., a dielectric material and also may function as an etch stop material during a subsequent anisotropic etch process that etches the connection-via-level dielectric material layer110. For example, the dielectric cap layer108may include silicon carbide or silicon nitride, and may have a thickness in a range from 5 nm to 30 nm, although lesser and greater thicknesses may also be used. The connection-via-level dielectric material layer110may include any material that may be used for the dielectric material layers (601,610,620,630). For example, the connection-via-level dielectric material layer110may include undoped silicate glass or a doped silicate glass deposited by decomposition of tetraethylorthosilicate (TEOS). The thickness of the connection-via-level dielectric material layer110may be in a range from 50 nm to 200 nm, although lesser and greater thicknesses may also be used. The dielectric cap layer108and the connection-via-level dielectric material layer110may be formed as planar blanket (unpatterned) layers having a respective planar top surface and a respective planar bottom surface that extends throughout the memory array region100and the peripheral region200. Referring toFIG.7, via cavities may be formed through the connection-via-level dielectric material layer110and the dielectric cap layer108. For example, a photoresist layer (not shown) may be applied over the connection-via-level dielectric material layer110and may be patterned to form opening within areas of the memory array region100that overlie a respective one of the third metal interconnect structures638. An anisotropic etch may be performed to transfer the pattern in the photoresist layer through the connection-via-level dielectric material layer110and the dielectric cap layer108. The via cavities formed by the anisotropic etch process are herein referred to as lower-electrode-contact via cavities because bottom electrode connection via structures are subsequently formed in the lower-electrode-contact via cavities. The lower-electrode-contact via cavities may have tapered sidewalls having a taper angle (within respective to a vertical direction) in a range from 1 degree to 10 degrees. A top surface of a third metal interconnect structure638may be physically exposed at the bottom of each lower-electrode-contact via cavity. The photoresist layer may be subsequently removed, for example, by ashing. A metallic barrier layer may be formed as a material layer. The metallic barrier layer may cover physically exposed top surfaces of the third metal interconnect structures638, tapered sidewalls of the lower-electrode-contact via cavities, and the top surface of the connection-via-level dielectric material layer110without any hole therethrough. The metallic barrier layer may include a conductive metallic nitride such as TiN, TaN, and/or WN. Other suitable materials within the contemplated scope of disclosure may also be used. The thickness of the metallic barrier layer may be in a range from 3 nm to 20 nm, although lesser and greater thicknesses may also be used. A metallic fill material such as tungsten or copper may be deposited in remaining volumes of the lower-electrode-contact via cavities. Portions of the metallic fill material and the metallic barrier layer that overlie the horizontal plane including the topmost surface of the connection-via-level dielectric material layer110may be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the metallic fill material located in a respective via cavity comprises a metallic via fill material portion124. Each remaining portion of the metallic barrier layer in a respective via cavity comprises a metallic barrier layer122. Each combination of a metallic barrier layer122and a metallic via fill material portion124that fills a via cavity constitutes a connection via structure (122,124). An array of connection via structures (122,124) may be formed in the connection-via-level dielectric material layer110on underlying metal interconnect structures. Referring toFIG.8, a layer stack including a first electrode material layer130L, a ferroelectric dielectric material layer140L, and a second electrode material layer160L may be sequentially deposited over the third line-and-via-level dielectric material layer630. The layers within the layer stack may be deposited by a respective chemical vapor deposition process or a respective physical vapor deposition process. Each layer within the layer stack may be deposited as planar blanket material layers having a respective uniform thickness throughout. The first electrode material layer130L may include, and/or may consist essentially of, at least one of a transition metal, a conductive metallic nitride, and a conductive metallic carbide. In one embodiment, the first electrode material layer130L includes at least one metallic material such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and/or a combination thereof. Other suitable materials within the contemplated scope of disclosure may also be used. For example, the first electrode material layer130L may include, and/or may consist essentially of, an elemental metal such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the first electrode material layer130L may be in a range from 10 nm to 100 nm, although lesser and greater thicknesses may also be used. The ferroelectric dielectric material layer140L includes a ferroelectric material having two stable directions for electrical polarization. The two stable directions may be the upward direction and the downward direction. The ferroelectric material of the ferroelectric dielectric material layer140L may include at least one material selected from barium titanate, colemanite, bismuth titanate, europium barium titanate, ferroelectric polymer, germanium telluride, langbeinite, lead smaydium tantalate, lead titanate, lead zirconate titanate, lithium niobate, polyvinylidene fluoride, potassium niobate, potassium sodium tartrate, potassium titanyl phosphate, sodium bismuth titanate, lithium tantalate, lead lanthanum titanate, lead lanthanum zirconate titanate, ammonium dihydrogen phosphate, and potassium dihydrogen phosphate. The ferroelectric dielectric material layer140L may be deposited, for example, by physical vapor deposition. The thickness of the ferroelectric dielectric material layer140L may be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses may also be used. The second electrode material layer160L includes a top electrode material, which may include any metallic material that may be used for the first electrode material layer130L. The second electrode material layer160L may include, and/or may consist essentially of, at least one of a transition metal, a conductive metallic nitride, and a conductive metallic carbide. Exemplary metallic materials that may be used for the second electrode material layer160L include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, an alloy thereof, and/or a combination thereof. Other suitable materials within the contemplated scope of disclosure may also be used. For example, the second electrode material layer160L may include, and/or may consist essentially of, an elemental metal such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the second electrode material layer160L may be in a range from 10 nm to 100 nm, although lesser and greater thicknesses may also be used. In an embodiment in which ferroelectric memory cells to be subsequently formed include a respective ferroelectric tunnel junction, a dielectric tunneling barrier layer such as a magnesium oxide layer may be optionally formed between the first electrode material layer130L and the ferroelectric dielectric material layer140L, or between the ferroelectric dielectric material layer140L and the second electrode material layer160L. In such embodiments, the thickness of the dielectric tunneling barrier layer may be in a range from 0.6 nm to 3.0 nm, although lesser and greater thicknesses may also be used. Referring toFIG.9, at least one patterned etch mask material portion177may be formed over the second electrode material layer160L. For example, the at least one patterned etch mask material portion177may include a two-dimensional array of patterned photoresist material portions that are formed by applying and lithographically patterning a photoresist material layer. In one embodiment, the at least one patterned etch mask material portion177may include a two-dimensional periodic array (such as a two-dimensional rectangular array) of patterned photoresist material portions. Each patterned photoresist material portion may have a horizontal cross-sectional shape of a circle, a rectangle, a rounded rectangle, an ellipse, or any other closed curvilinear shape. In embodiments in which the at least one patterned etch mask material portion177includes a two-dimensional array of at least one patterned etch mask material portions (such as photoresist material portions), the pitch of the at least one patterned etch mask material portion177along each horizontal direction of periodicity may be in a range from 20 nm to 400 nm, such as from 40 nm to 200 nm, although lesser and greater pitches may also be used. An anisotropic etch process may be performed to transfer the pattern in the at least one patterned etch mask material portion177through the layer stack (160L,140L,130L). The anisotropic etch process etches unmasked portions of the layer stack (160L,140L,130L), and forms at least one ferroelectric memory cell101, which may include a two-dimensional array of ferroelectric memory cells101. Each ferroelectric memory cell101includes a vertical stack including a first electrode130, a ferroelectric dielectric material layer140, and a second electrode160. Each second electrode160is a patterned portion of the second electrode material layer160L. Each ferroelectric dielectric material layer140is a patterned portion of the ferroelectric dielectric material layer140L. Each first electrode130is a patterned portion of the first electrode material layer130L. The sidewalls of the layers within each ferroelectric memory cell101may be vertically coincident, i.e., may be located within a vertical plane including sidewalls of at least one overlying layer and/or at least one underlying layer. The sidewalls of the layers within each ferroelectric memory cell101may be vertical, or may have a taper angle in a range from 0.1 degree to 30 degrees. The at least one patterned etch mask material portion177may be subsequently removed, for example, by ashing. Optionally, dielectric spacers (not shown) may be formed around the array of ferroelectric memory cells101. An array of ferroelectric memory cells101may be formed. Each ferroelectric memory cell101may include a first electrode130, a second electrode160overlying the first electrode130, and a ferroelectric dielectric material layer140located between the first electrode130and the second electrode160. In an embodiment in which the ferroelectric memory cells101include a respective ferroelectric tunnel junction, a dielectric tunneling barrier layer (not expressly shown) such as a magnesium oxide layer may be located as an interfacial layer between a first electrode130and a ferroelectric dielectric material layer140, or between the ferroelectric dielectric material layer140and a second electrode160. Referring toFIG.10, a memory-level dielectric material layer170may be formed around, and over, the array of ferroelectric memory cells101and the connection-via-level dielectric material layer110. The memory-level dielectric material layer170includes a planarizable dielectric material such as undoped silicate glass or a doped silicate glass. The dielectric material of the memory-level dielectric material layer170may be deposited by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating). At least one lithographic patterning step and at least one anisotropic etch process may be used for form interconnect cavities in the memory-level dielectric material layer170. For example, a first photoresist layer (not shown) may be applied over the memory-level dielectric material layer170and may be lithographically patterned to form discrete openings in the first photoresist layer. A first anisotropic etch process may be performed to form via cavities in the memory-level dielectric material layer170. After removal of the first photoresist layer, a second photoresist layer (not shown) may be applied over the memory-level dielectric material layer170and may be lithographically patterned to form line-shaped openings in the second photoresist layer. A second anisotropic etch process may be performed to form line cavities in the memory-level dielectric material layer170. The second photoresist layer may be subsequently removed. Interconnect via cavities may be formed through the memory-level dielectric material layer170. In one embodiment, the interconnect cavities may be formed as integrated line and via cavities. In this embodiment, each integrated line and via cavity may include a line cavity and at least one via cavity. A top surface of a second electrode160may be physically exposed at the bottom of each via cavity that is formed in the memory array region100, and a top surface of a metal line structure (such as a third metal line structure638) may be physically exposed at the bottom of each via cavity that is formed in the peripheral region200. At least one metallic material may be deposited in the interconnect cavities. The at least one metallic material is herein referred to as at least one memory-level metallic material. In one embodiment, a metallic barrier material layer (such as a TiN layer, TaN layer, and/or a WN layer) and a metallic fill material (such as W, Cu, Co, Ru, Mo, or an intermetallic alloy) may be deposited in the interconnect cavities and over the memory-level dielectric material layer170. Other suitable metallic barrier and fill materials are within the contemplated scope of disclosure. A planarization process such as a chemical mechanical planarization process may be performed to remove the at least one memory-level metallic material from above the memory-level dielectric material layer170. The chemical mechanical planarization process may remove material portions from above the horizontal plane including the top surface of the memory-level dielectric material layer170. Remaining portions of the at least one memory-level metallic material filling the interconnect cavities comprise memory-level metal interconnect structures (180,190,280,290). The memory-level metal interconnect structures (180,190,280,290) may include first memory-level line and via structures (180,190) formed in the memory array region100and second memory-level line and via structures (280,290) formed in the peripheral region200. Each first memory-level line and via structures (180,190) may include a respective metal via portion180that contacts a top surface of a second electrode160, and a respective metal line portion190overlying, and adjoined to, the respective metal via portion180. Each second memory-level line and via structures (280,290) may include a respective metal via portion280that contacts a top surface of a metal line structure (such as a third metal line structure638), and a respective metal line portion290overlying, and adjoined to, the respective metal via portion280. Top surfaces of the memory-level metal interconnect structures (180,190,280,290) may be located within the horizontal plane including the top surface of the memory-level dielectric material layer170. In embodiments in which the dielectric cap layer108, the connection-via-level dielectric material layer110, and the memory-level dielectric material layer170are formed above the third line-and-via-level dielectric material layer630, the combination of the dielectric cap layer108, the connection-via-level dielectric material layer110, and the memory-level dielectric material layer170constitutes a fourth line-and-via-level dielectric material layer630. Generally, the memory-level dielectric material layer170embeds, and laterally surrounds, the array of ferroelectric memory cells101. Metal interconnect structures (such as the first memory-level metal interconnect structures (180,190)) including a metal via portion may be formed through the memory-level dielectric material layer170. The set of all metal interconnect structures that are formed above the first metal interconnect structures (612,618,622,628) is herein collectively referred to as second metal interconnect structures (632,638,180,190,280,290). The second metal interconnect structures (632,638,180,190,280,290) may be formed over the thin film transistors801and the ferroelectric memory cells101. A subset of the second metal interconnect structures (632,638,180,190,280,290) electrically connects a first node of a respective ferroelectric memory cell101to a respective node of the thin film transistor801. Generally, the first node of each ferroelectric memory cell101may be the first electrode130or the second electrode160. The node of a thin film transistor801that is electrically connected to the first node of a respective ferroelectric memory cell101may be a source region that is connected to a source contact structure832, a drain region that is connected to a drain contact structure838, or a TFT gate electrode854. WhileFIG.10illustrates an embodiment in which a source region of each thin film transistor801is electrically connected to a first electrode130of a respective ferroelectric memory cell101, embodiments are expressly contemplated herein in which any electrical node of a thin film transistor801is electrically connected to a first electrode130or a second electrode160of a respective ferroelectric memory cell101through a respective subset of the second metal interconnect structures (632,638,180,190,280,290). In one embodiment, field effect transistors701including a respective semiconductor channel735that contains a portion of the semiconductor material layer9in the substrate8may be formed as described above. In one embodiment, a second node of each ferroelectric memory cell101may be electrically connected to a node of a respective field effect transistor701through a respective subset of the first metal interconnect structures (612,618,622,628) and a respective subset of the second metal interconnect structures (632,638,180,190,280,290). For example, if the first node of a ferroelectric memory cell101is a first electrode130, the second node of the ferroelectric memory cell101is a second electrode160, and vice versa. While the various embodiments herein are described using field effect transistors including planar semiconductor channels located within the semiconductor material layer9, embodiments are expressly contemplated herein in which fin field effect transistors and/or gate-all-around field effect transistors are used in lieu of, or in addition to, the planar field effect transistors. Generally, the thin film transistors801may be embedded in a first dielectric material layer (such as the TFT-level dielectric matrix layer630B), and the ferroelectric memory cells101may be embedded within a second dielectric material layer (such as the memory-level dielectric material layer170) selected from dielectric material layers that are located above, or below, the first dielectric material layer. In the illustrated example ofFIG.9, the second dielectric material layer comprising the memory-level dielectric material layer170is located above the first dielectric material layer comprising the TFT-level dielectric material layer630B. Each subset of the second metal interconnect structures (632,638,180,190,280,290) that provides electrical connection between a pair of a thin film transistor801and a ferroelectric memory cell101may extend between the first dielectric material layer and the second dielectric material layer. In one embodiment, at least one, and/or each, of the ferroelectric memory cells101may comprise a ferroelectric tunnel junction providing two tunneling resistance values depending on a polarization direction of a ferroelectric material within a respective ferroelectric dielectric material layer140, and a combination of a thin film transistor801and a field effect transistor701may be configured to provide electrical current that tunnels through the ferroelectric tunnel junction. In one embodiment, the ferroelectric memory cell101comprises a programmable ferroelectric capacitor providing two different capacitive states having two different capacitance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140, and a combination of a thin film transistor801and a field effect transistor701may be configured to provide a charging current for the programmable ferroelectric capacitor. Generally, each ferroelectric memory cell101may comprise a vertical stack of a first electrode130, a ferroelectric dielectric material layer140, and a second electrode160. The ferroelectric memory cell101may comprise one of a ferroelectric tunnel junction and a programmable ferroelectric capacitor. Each ferroelectric tunnel junction may provide two tunneling resistance values depending on a polarization direction of a ferroelectric material within the ferroelectric dielectric material layer140. Each programmable ferroelectric capacitor may provide two different capacitive states having two different capacitance values depending on a polarization direction of a ferroelectric material within the ferroelectric dielectric material layer140. In one embodiment, the field effect transistors701and the thin film transistors801may be configured such that a field effect transistor701may access a row of ferroelectric memory cells101. In one embodiment, a set of field effect transistors701may be configured to access a respective row of ferroelectric memory cells101. The thin film transistors801may be configured to access a respective one of the ferroelectric memory cells101. In one embodiment, a two-dimensional array of ferroelectric memory cells101may be arranged in M rows and N columns. A total of M×N ferroelectric memory cells101may be present within the two-dimensional array of ferroelectric memory cells101. Each row of ferroelectric memory cells101may laterally extend along the second horizontal direction hd2, and may be repeated M times along the first horizontal direction hd1. Each column of ferroelectric memory cells101may laterally extend along the first horizontal direction hd1, and may be repeated N times along the second horizontal direction hd2. M field effect transistors701may be configured to access a respective row of N ferroelectric memory cells101. An M×N array of thin films transistors801that are arranged in M rows and N columns may be provided, and each of the thin film transistors801may be electrically connected to a respective one of the ferroelectric memory cells. Referring toFIG.11, a first alternative configuration of the exemplary structure is illustrated according to an embodiment of the present disclosure. A fourth line-and-via-level dielectric material layer640embedding third metal via structures642and fourth metal line structures648may be formed between the third line-and-via-level dielectric material layer630that includes the TFT-level dielectric material layer (630A,630B) and the interconnect level that includes the ferroelectric memory cells101. A combination of the dielectric cap layer108, the connection-via-level dielectric material layer110, and the memory-level dielectric material layer170is formed in the fifth metal interconnect level, and constitutes a fifth line-and-via-level dielectric material layer650. In one embodiment, the field effect transistors701and the thin film transistors801may be configured such that a thin film transistor801may access a column of ferroelectric memory cells101. In one embodiment, a set of thin film transistors801may be configured to access a respective column of ferroelectric memory cells101. The field effect transistors701may be configured to access a respective one of the ferroelectric memory cells101. In one embodiment, a two-dimensional array of ferroelectric memory cells101may be arranged in M rows and N columns. A total of M×N ferroelectric memory cells101may be present within the two-dimensional array of ferroelectric memory cells101. Each row of ferroelectric memory cells101may laterally extend along the second horizontal direction hd2, and may be repeated M times along the first horizontal direction hd1. Each column of ferroelectric memory cells101may laterally extend along the first horizontal direction hd1, and may be repeated N times along the second horizontal direction hd2. N thin film transistors801may be configured to access a respective column of M ferroelectric memory cells101. An M×N array of field effect transistors701that are arranged in M rows and N columns may be provided, and each of the field effect transistors701may be electrically connected to a respective one of the ferroelectric memory cells. In one embodiment, the field effect transistors701and the thin film transistors801may be configured such that each thin film transistor801accesses a single ferroelectric memory cell101and each field effect transistor701accesses a single ferroelectric memory cell101. Referring toFIG.12, a second alternative configuration of the exemplary structure is illustrated according to an embodiment of the present disclosure is illustrated. A combination of the dielectric cap layer108, the connection-via-level dielectric material layer110, and the memory-level dielectric material layer170is formed in the fourth metal interconnect level, and constitutes a fourth line-and-via-level dielectric material layer640. A column of ferroelectric memory cells101may be accessed by a thin film transistor801in this configuration. In one embodiment, a two-dimensional array of ferroelectric memory cells101may be arranged in M rows and N columns. A total of M×N ferroelectric memory cells101may be present within the two-dimensional array of ferroelectric memory cells101. Each row of ferroelectric memory cells101may laterally extend along the second horizontal direction hd2, and may be repeated M times along the first horizontal direction hd1. Each column of ferroelectric memory cells101may laterally extend along the first horizontal direction hd1, and may be repeated N times along the second horizontal direction hd2. An M×N array of thin film transistors801that are arranged in M rows and N columns may be provided, and each of the thin film transistors801may be configured to access a respective one of the M×N ferroelectric memory cells101. An M×N array of field effect transistors701that are arranged in M rows and N columns may be provided, and each of the field effect transistors701may be electrically connected to a respective one of the M×N ferroelectric memory cells101. In an alternative configuration, a two-dimensional array of ferroelectric memory cells101may be arranged in M rows and N columns. A total of M×N ferroelectric memory cells101may be present within the two-dimensional array of ferroelectric memory cells101. M field effect transistors701and N thin film transistors801may be configured such that each field effect transistor701accesses a respective set of N ferroelectric memory cells101located within a respective column, and each thin film transistor801accesses a respective set of M ferroelectric memory cells101located within a row. Thus, a single ferroelectric memory cell101may be selected by activating a field effect transistor701and a thin film transistor801. In another alternative configuration, a two-dimensional array of ferroelectric memory cells101may be arranged in M rows and N columns. A total of M×N ferroelectric memory cells101may be present within the two-dimensional array of ferroelectric memory cells101. N field effect transistors701and M thin film transistors801may be configured such that each field effect transistor701accesses a respective set of M ferroelectric memory cells101located within a respective column, and each thin film transistor801accesses a respective set of N ferroelectric memory cells101located within a respective row. Thus, a single ferroelectric memory cell101may be selected by activating a field effect transistor701and a thin film transistor801. Referring toFIG.13, a third alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from any of the configurations illustrated inFIGS.10-12by altering the levels in which the array of ferroelectric memory cells101and the array of thin film transistors801are formed. Specifically, the thin film transistors801may be embedded within a first dielectric material layer such as a fifth line-and-via-level dielectric material layer650. In this embodiment, the fifth line-and-via-level dielectric material layer650may include a vertical stack of a planar insulating spacer layer650A (which provided the same function as a planar insulating spacer layer630A that is described above) and a TFT-level dielectric matrix layer650B (which provides the same function as the TFT-level dielectric matrix layer630B that is described above). Fourth-level metal via structures652and fifth-level metal line structures658may be used to provide electrical wiring to the thin film transistors801. The ferroelectric memory cells101may be embedded within a second dielectric material layer selected from dielectric material layers such as third line-and-vie-level dielectric material layer630. In this embodiment, the third line-and-vie-level dielectric material layer630may include the dielectric cap layer108, the connection-via-level dielectric material layer110, and the memory-level dielectric material layer170. The memory-level metal interconnect structures (180,190,280,290) may be used as second metal via structures and third metal line structures that are embedded within the third line-and-via-level dielectric material layer630. In this embodiment, each of the first dielectric material layer that embeds the thin film transistors801and the second dielectric material layer that embeds the ferroelectric memory cells101may be located above the at least one lower-level dielectric material layer (601,610,620). The second dielectric layer may be located below the first dielectric material layer. Second metal interconnect structures (180,190,280,290,642,648,652,658) are embedded within the dielectric material layers (630,640,650) that overlie the lower-level dielectric material layers (601,610,620). Metal interconnect structures that provide electrical connection between the thin film transistors801and the ferroelectric memory cells101extend between the first dielectric material layer and the second dielectric material layer. Referring toFIG.14, a fourth alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from any of the configurations illustrated inFIGS.10-12by forming an array of ferroelectric memory cells101and the array of thin film transistors801at a same level. In the illustrated example, a planar insulating spacer layer630A may be used in lieu of a combination of a dielectric cap layer108and a connection-via-level dielectric material layer110. In one embodiment, the array of ferroelectric memory cells101may be formed prior to formation of the array of thin film transistors801. In another embodiment, the array of ferroelectric memory cells101may be formed after formation of the array of thin film transistors801. In one embodiment, the array of ferroelectric memory cells101may be interlaced with the array of thin film transistors801in order to reduce the lateral distance of electrical wiring between each connected pair of a thin film transistor801and a ferroelectric memory cell101. An array of series connections of a ferroelectric memory cell101and a thin film transistor801may be provided. In this configuration, a row of a ferroelectric memory cell101and a thin film transistor801may be accessed by a field effect transistor701, or a column of a ferroelectric memory cell101and a thin film transistor801may be accessed by a field effect transistor701. For example, a M×N array of series connections of a ferroelectric memory cell101and a thin film transistor801may be provided, and M field effect transistors701may access a respective row including N series connections of a ferroelectric memory cell101and a thin film transistor801located within a same row. Alternatively, N field effect transistors701may access a respective row including M series connections of a ferroelectric memory cell101and a thin film transistor801located within a same column. In this configuration, the first dielectric material layer that laterally surrounds the array of thin film transistors801and the second dielectric material layer that laterally surrounds the array of ferroelectric memory cells101may be the same. Thus, the TFT-level dielectric matrix layer630B may be the memory-level dielectric material layer170. In one embodiment, each set of metal interconnect structures that provides electrical connection between a ferroelectric memory cell101and a thin film transistor801may be embedded within the common dielectric material layer (such as the TFT-level dielectric matrix layer630B), which is the first dielectric material layer and the second dielectric material layer. Referring toFIG.15, a fifth alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from any of the configurations illustrated inFIGS.10-14by duplicating a combination of an array of thin film transistors801and an array of ferroelectric memory cells101along a vertical direction at least once. Multiple combinations of an array of thin film transistors801and an array of ferroelectric memory cells101may be formed along the vertical direction. In the illustrated example, a combination of a first array of thin film transistors801and a first array of ferroelectric memory cells101may be formed over the levels of a third line-and-via-level dielectric material layer630and a fourth line-and-via-level dielectric material layer640. A combination of a second array of thin film transistors801and a second array of ferroelectric memory cells101may be formed over the levels of a fifth line-and-via-level dielectric material layer650and a sixth line-and-via-level dielectric material layer660. Any of the wiring schemes for addressing a selected ferroelectric memory cell101may be individually used at each combination of an array of thin film transistors801and an array of ferroelectric memory cells101. In one embodiment, a field effect transistor701may address multiple levels of ferroelectric memory cells101located at different metal interconnect levels. For example, a field effect transistor701may address a row of ferroelectric memory cells101located within the combination of a first array of thin film transistors801and a second array of ferroelectric memory cells101and another row of ferroelectric memory cells located within the combination of a second array of thin film transistors801and a second array of ferroelectric memory cells101simultaneously. Referring toFIG.16, a sixth alternative configuration of the exemplary structure according to an embodiment of the present disclosure may be derived from any of the configurations illustrated inFIGS.10-15by forming different types of ferroelectric memory cells101at a same level. For example, at least one first-type ferroelectric memory cell101A and at least one second-type ferroelectric memory cell101B may be formed by patterning a layer stack including a first electrode material layer130L, a ferroelectric dielectric material layer140L, and a second electrode material layer160L at a processing step corresponding to the processing step ofFIG.9. In an illustrative example, a first-type ferroelectric memory cell101A may include a ferroelectric tunnel junction providing two tunneling resistance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140, and a first thin film transistor801and a first field effect transistor701may be configured to provide electrical current that tunnels through the ferroelectric tunnel junction. A second-type ferroelectric memory cell101B may comprise a programmable ferroelectric capacitor providing two different capacitive states having two different capacitance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140, and a second thin film transistor801and a second field effect transistor701may be configured to provide a charging current for the programmable ferroelectric capacitor. Referring toFIG.17, a flowchart illustrates the general processing steps for manufacturing the semiconductor device of the various embodiments of the present disclosure. Referring to step1710andFIG.1, first metal interconnect structures (612,618,622,628) embedded within at least one lower-level dielectric material layer (601,610,620) may be formed over a substrate8. Referring to step1720andFIGS.2-5, a thin film transistor801may be formed over the lower-level dielectric material layer (601,610,620). Referring to step1730andFIGS.6-9and11-16, a ferroelectric memory cell101may be formed over the at least one lower-level dielectric material layer (601,610,620) prior to, or after, formation of the thin film transistor801, wherein the ferroelectric memory cell101is formed underneath, above, or at a same level as, a level of the thin film transistor801. Referring to step1740andFIGS.6-16, second metal interconnect structures (632,638,642,648,652,658,180,190,280,290) may be formed over the thin film transistor801or the ferroelectric memory cell101. A subset of the second metal interconnect structures (632,638,642,648,652,658,180,190,280,290) electrically connects a first node of the ferroelectric memory cell101to a node of the thin film transistor801. Referring to all drawings and according to various embodiments of the present disclosure, a memory device is provided, which comprises: metal interconnect structures (612,618,622,628,632,638,642,648,642,658,180,190,280,290) embedded within dielectric material layers (601,610,620,630,640,650,660) that overlie a top surface of a substrate8; a thin film transistor801embedded in a first dielectric material layer (e.g., a third line-and-via-level dielectric material layer630, a fourth line-and-via-level dielectric material layer640, or a fifth line-and-via-level dielectric material layer650) selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate8; and a ferroelectric memory cell101embedded within the dielectric material layers, wherein a first node (130or160) of the ferroelectric memory cell101is electrically connected to a node (835,832,838) of the thin film transistor801through a subset of the metal interconnect structures (632,638,642,648,642,658,180,190,280,290) that is located above, and vertically spaced from, the top surface of the substrate8. In one embodiment, the memory device comprises a field effect transistor701including a semiconductor channel that contains a portion of the substrate8, wherein a second node (160or130) of the ferroelectric memory cell101is electrically connected to a node of the field effect transistor701. In one embodiment, the substrate8comprises a single crystalline semiconductor material; and the thin film transistor801comprises a polycrystalline semiconducting metal oxide material as a channel material. In one embodiment, the ferroelectric memory cell101comprises a layer stack including a first electrode130, a ferroelectric dielectric material layer140, and a second electrode160; one of the first electrode130and the second electrode160comprises the first node of the ferroelectric memory cell101that is electrically connected to the node of the thin film transistor801; and another of the first electrode130and the second electrode160comprises the second node of the ferroelectric memory cell101that is electrically connected to the node of the field effect transistor701. In one embodiment, the memory device comprises a programming control circuit comprising a portion of a CMOS circuitry700that includes additional field effect transistors701configured to control gate voltages of the thin film transistor801and the field effect transistor701. The CMOS circuitry700may be configured to provide: a first programming pulse that programs the ferroelectric dielectric material layer140into a first polarization state in which electrical polarization in the ferroelectric dielectric material layer points toward the first electrode130; and a second programming pulse that programs the ferroelectric dielectric material layer into a second polarization state in which the electrical polarization in the ferroelectric dielectric material layer points toward the second electrode160. Generally, each ferroelectric memory cell101may have a built-in structural and electrical asymmetry between the first electrode130and the second electrode160. The asymmetry may be provided, for example, by providing different materials between the first electrode130and the second electrode160, and/or by inserting a suitable interfacial layer (such as a ferroelectric tunneling barrier layer including magnesium oxide). The asymmetry between the first electrode130and the second electrode160causes differences in the tunneling resistance or in the capacitance of the ferroelectric memory cell101between the two ferroelectric states of the ferroelectric memory cell101, and may be sensed by a sensing circuit that may be provided within the CMOS circuitry700. The sensing circuit may be configured to detect the tunneling current or the capacitance of a selected ferroelectric memory cell101, which may be activated through selection of a field effect transistor701and a thin film transistor801. In one embodiment, the node of the thin film transistor801that is electrically connected to the first node or the second node of the ferroelectric memory cell101comprises a source region (and the source contact structure832) or a drain region (and the drain contact structure838) of the thin film transistor801; and the node of the field effect transistor701comprises a source region732or a drain region738of the field effect transistor701. In one embodiment, the ferroelectric memory cell101comprises a ferroelectric tunnel junction providing two tunneling resistance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140; and the thin film transistor801and the field effect transistor701are configured to provide electrical current that tunnels through the ferroelectric tunnel junction. In one embodiment, the ferroelectric memory cell101comprises a programmable ferroelectric capacitor providing two different capacitive states having two different capacitance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140; and the thin film transistor801and the field effect transistor701are configured to provide a charging current for the programmable ferroelectric capacitor. In one embodiment, the ferroelectric memory cell101is embedded within a second dielectric material layer (e.g., a third line-and-via-level dielectric material layer630, a fourth line-and-via-level dielectric material layer640, or a fifth line-and-via-level dielectric material layer650) selected from dielectric material layers that are located above, or below, the first dielectric material layer; and the subset of the metal interconnect structures (632,638,642,648,642,658,180,190,280,290) extends between the first dielectric material layer and the second dielectric material layer. In one embodiment, the ferroelectric memory cell101is located at a same level as the thin film transistor801and laterally surrounded by the first dielectric material layer; and the subset of the metal interconnect structures (180,190,280,290) is embedded within the first dielectric material layer as illustrated inFIG.14. According to another aspect of the present disclosure, a memory device is provided, which comprises: metal interconnect structures (612,618,622,628,632,638,642,648,642,658,180,190,280,290) embedded within dielectric material layers that overlie a substrate8; an array of thin film transistors801embedded within a first dielectric material layer selected from dielectric material layers (601,610,620,630,640,650,660); and an array of ferroelectric memory cells101embedded within a second dielectric material layer selected from the dielectric material layers (601,610,620,630,640,650,660), the second dielectric material layer being the same or different from the first dielectric material layer, wherein each ferroelectric memory cell101within the array of ferroelectric memory cells101comprises a pillar structure containing a layer stack that includes a first electrode130, a ferroelectric dielectric material layer140contacting a top surface of the first electrode130, and a second electrode160contacting a top surface of the ferroelectric dielectric material layer140; and wherein each ferroelectric memory cell101comprise a first node that is electrically connected to a node of a respective thin film transistor801which functions as an access transistor through a respective subset of the metal interconnect structures (632,638,642,648,642,658,180,190,280,290). In one embodiment, the memory device comprises at least one field effect transistor701including a semiconductor channel that contains a portion of the substrate8(such as a portion of the semiconductor material layer9), wherein a node of the field effect transistor701is electrically connected to a second node of at least one ferroelectric memory cell101within the array of ferroelectric memory cells101through an additional subset of the metal interconnect structures (612,618,622,628,632,638,642,648,642,658,180,190,280,290). In one embodiment, each field effect transistor701within the at least one field effect transistor701is electrically connected to second nodes of a respective plurality of ferroelectric memory cells101selected from the array of ferroelectric memory cells101(which may be a row of ferroelectric memory cells101or a column of ferroelectric memory cells101). In one embodiment, each ferroelectric memory cell101within the array of ferroelectric memory cells101comprises a ferroelectric tunnel junction providing two tunneling resistance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140; and the array of thin film transistors801and the at least one field effect transistor701are configured to provide electrical current that tunnels through a selected ferroelectric tunnel junction within the array of ferroelectric memory cells101. In one embodiment, each ferroelectric memory cell101within the array of ferroelectric memory cells101comprises a programmable ferroelectric capacitor providing two different capacitive states having two different capacitance values depending on a polarization direction of a ferroelectric material within a ferroelectric dielectric material layer140; and the array of thin film transistors801and the at least one field effect transistor701are configured to provide a charging current for a selected programmable ferroelectric capacitor within the array of ferroelectric memory cells101. The various embodiments of the present disclosure may be used to provide a ferroelectric memory device including at least one ferroelectric memory cell101, such as a two-dimensional array of ferroelectric memory cells101, that may be accessed through a combination of at least one thin film transistor801and at least one field effect transistor701located on a semiconductor material layer9in a substrate8. By using a vertical stack of at least two levels of transistors (which may be three or more levels of transistors in embodiments in which two or more levels of thin film transistors801are used), the total device area occupied by the transistors in a plan view may be reduced, and a semiconductor chip with a higher ferroelectric device density may be provided. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 82,355 |
11943934 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A magnetoresistive random-access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack arranged between top and bottom electrodes. The MTJ stack comprises a thin insulating layer arranged between two magnetic layers. Many MTJs make up an MRAM device that reads, writes, and stores data using magnetic orientations. As technology is developed to be smaller and more efficient, manufacturing methods often need to be adjusted to accommodate for the smaller dimensions. Typically, an MRAM device may be formed by depositing MTJ layers over a bottom electrode layer, and depositing a top electrode layer over the MTJ layers. A hard mask structure is then deposited over the top electrode layer. The top electrode layer undergoes a first etch according to the hard mask structure. Then, a remaining portion of the hard mask structure and the top electrode layer are used as a mask for a second etch of the MTJ layers to form the MTJ stack. Oftentimes the first etch may etch different parts of the top electrode layer at different lateral etch rates, causing a resulting top electrode to have deformities, especially when the top electrode is made of more than one layer of material. For example, a top electrode layer with a higher lateral etch rate will have a small width after the first etch than other top electrode layers with lower lateral etch rates. Thus, a top electrode with more than one layer of material will not have a smooth sidewall after the first etch. When the first etch results in a non-uniform width of the top electrode, control of a critical the second etch results in a non-uniform width of the MTJ stack. A non-uniform width of the MTJ stack causes problems with control over magnetic properties in the MTJ, which impacts the reliability of the MRAM to read, write, and store data. In the present disclosure, a new method of manufacturing MTJ stacks is presented to produce reliable MRAM devices. The new manufacturing method eliminates a top electrode etch such that there is improved control over critical dimensions of the top electrode structure and subsequently the MTJ stack. FIG.1illustrates a cross-sectional view of some embodiments of an integrated chip100comprising an MRAM cell. The integrated chip100includes an MRAM cell101arranged over a substrate102. The MRAM cell101comprises an MTJ stack116, which is separated from the substrate102by one or more lower interconnect layers109embedded within a dielectric structure106. The dielectric structure106may comprise one or more stacked inter-level dielectric (ILD) layers. The one or more lower interconnect layers109comprise, in many embodiments, interconnect vias108and interconnect wires110configured to connect a bottom electrode114to a first access transistor104. The MRAM cell101comprises a top electrode122and the bottom electrode114, which are separated from one another by the MTJ stack116. In some embodiments, the dielectric structure106comprises an etch stop structure112arranged between a lower dielectric structure106asurrounding the one or more lower interconnect layers109and an upper dielectric structure106bsurrounding the MRAM cell101. In such embodiments, the bottom electrode114protrudes through the etch stop structure112to electrically connect to the one or more lower interconnect layers109. An upper interconnect structure126is coupled to the top electrode122. A capping layer118, in some embodiments, may be arranged over the MTJ stack116and below the top electrode122to enforce structural properties and thus, protect magnetic properties of the MTJ stack116. The capping layer118has outer sidewalls that are aligned to outer sidewalls of the MTJ stack116. In many embodiments, the top electrode122has rounded upper corners that are coupled to sidewalls of the top electrode122. The sidewalls of the top electrode122meet a bottom surface of the top electrode122at an angle A. The MTJ stack116has smooth sidewalls that meet a bottom surface of the MTJ stack116at an angle B, which is less than or equal to angle A. For example, angle A may be in the range of between approximately 80° and approximately 90°. Angle B may be in the range of between approximately 70° and approximately 90°. Angle A is larger than angle B because the top electrode122is subjected to a single etch, which occurs during patterning of the underlying MTJ stack116. By subjecting the top electrode122to a single etch (rather than to a first etch during patterning of the top electrode122and a second etch during patterning of the MTJ stack116), a critical dimension of the top electrode122is able to be more accurately controlled. The critical dimension of the top electrode122may be, for example, in the range of between approximately 15 nanometers and approximately 150 nanometers. By more accurately controlling the critical dimension of the top electrode122, a critical dimension of the MTJ stack116is able to be more accurately controlled resulting in an MRAM device having good reliability to read and write data. FIG.2illustrates an additional embodiment of a cross-sectional view of an integrated chip200comprising an MRAM cell. The integrated chip200includes an MRAM cell101arranged over a substrate102. The MRAM cell101comprises a top electrode122and a bottom electrode114, which are separated from one another by an MTJ stack116. The MTJ stack116comprises a lower ferromagnetic electrode116cseparated from an upper ferromagnetic electrode116aby a thin tunneling barrier layer116b.The lower ferromagnetic electrode116cis coupled to the bottom electrode114. In some embodiments, a width of the bottom electrode114is larger than a width of the lower ferromagnetic electrode116c.The upper ferromagnetic electrode116ais electrically coupled to the top electrode122. Electron tunneling occurs between the upper ferromagnetic electrode116aand the lower ferromagnetic electrode116cthrough the thin tunneling barrier layer116b.The relationship of the magnetic orientations of the lower and upper ferromagnetic electrodes116c,116adetermines if the MRAM cell will read, write or store data. Outer sidewalls of the lower ferromagnetic electrode116c,the thin tunneling barrier layer116b,the upper ferromagnetic electrode116a,and the capping layer118, are aligned and together, have a continuous, smooth surface. A capping layer118, in some embodiments, may be arranged over the MTJ stack116and below the top electrode122. The capping layer118may have a thickness in the range of between approximately 0.5 nanometers and approximately 15 nanometers. The capping layer118may be made of, for example, tantalum, titanium, tantalum nitride, titanium nitride, or combinations thereof, and the top electrode122may be made of one or more conductive materials, for example, tantalum, titanium, tantalum nitride, titanium nitride, tungsten, ruthenium, or layered combinations thereof. The capping layer118may have a thickness in the range of between approximately 0.5 nanometers and approximately 15 nanometers. Oftentimes, there is poor adhesion at the interface of the capping layer118and the top electrode122. Thus, in some embodiments, a glue layer120between the top electrode122and the capping layer118to improve adhesion between the top electrode122and the capping layer118. In some embodiments, the glue layer120may comprise or be a diffusion barrier layer. In some embodiments, the glue layer120may have a lower surface directly contacting the capping layer118and an upper surface directly contacting the top electrode122. The capping layer118has a lower surface having a width that is approximately equal to a width of an upper surface of the upper ferromagnetic electrode116a.The glue layer120may comprise, for example, tantalum, titanium, tantalum nitride, titanium nitride, or combinations thereof. The glue layer120, in some embodiments, is continuous and along a sidewall of the top electrode122and a bottom surface of the top electrode122. In such embodiments, the top electrode122has a first maximum height h1measured from a bottom surface of the top electrode122. The first maximum height h1may measure to be in the range of between approximately 10 nanometers and approximately 100 nanometers. The glue layer120has an inner sidewall that has a second maximum height h2measured from the bottom surface of the top electrode122. The second maximum height h2measures to be less than the first maximum height h1by a range of between approximately 2 nanometers and approximately 6 nanometers, due to difference in etching rates during patterning steps. The glue layer120has an outer sidewall that has a third maximum height h3measured from the bottom surface of the top electrode122. The third maximum height h3measures to be less than the second maximum height h2by a range of between approximately 1 nanometer and approximately 5 nanometers, due to etching effects. In some embodiments, the inner sidewall of the glue layer120is connected to the outer sidewall of the glue layer by a rounded corner. FIG.3Aillustrates an additional embodiment of a cross-sectional view of an integrated chip300comprising an MRAM cell. FIG.3Acomprises the same features as the integrated chip200ofFIG.2in addition to sidewall spacers124. The sidewall spacers124are made of a dielectric material. In some embodiments, outer sidewalls of the sidewall spacers124are aligned with outer sidewalls of a bottom electrode114. An upper interconnect structure126protrudes through the sidewall spacers124such that the upper interconnect structure126is coupled to a top electrode122. As shown in top-view302ofFIG.3B, the sidewall spacers124surround the top electrode122such that the top electrode122is separated from dielectric structure106. In some embodiments, a glue layer120(e.g., a diffusion barrier layer) is separates the top electrode122from the sidewall spacers124. In some embodiments, the top electrode122and the sidewall spacers124have a top-view that resemble concentric circle. In other embodiments, the top-view of the top electrode122and the sidewall spacers124may, for example, have a top-view that resembles an oval, a quadrilateral, or a polygon. FIG.4Aillustrates an additional embodiment of a cross-sectional view of an integrated chip400comprising an MRAM cell. FIG.4Acomprises sidewall spacers124with a different shape than the sidewall spacers124illustrated inFIG.3A. InFIG.4, the sidewall spacers124have curved outer sidewalls such that the sidewall spacers124have sidewalls that decrease in thickness from a bottom surface of the sidewall spacers124to a top surface of the sidewall spacers124. The sidewall spacers124, in some embodiments, does not cover top surfaces of the top electrode122, as illustrated inFIG.4. FIG.4Brepresents a zoomed in illustration outlined by box402inFIG.4Aof integrated chip400. In some embodiments, as illustrated byFIG.4B, a capping layer118has an upper surface that is not planar. For example, in some embodiments, the capping layer118has a thickness t that increases from a center of the capping layer118to outer sidewalls of the capping layer118, thereby giving the capping layer118a concave upper surface. In such embodiments, lower surfaces of the glue layer120and/or the top electrode122are also not planar. FIG.5illustrates an additional embodiment of a cross-sectional view of an integrated chip500comprising an MRAM cell. FIG.5comprises an integrated chip500with similar features as the integrated chip300illustrated inFIG.3A. In some embodiments, the bottom electrode114has outer sidewalls that are aligned with outer sidewalls of the MTJ stack116. Additionally, in other embodiments, the sidewall spacers124cover the outer sidewalls of the bottom electrode114, as illustrated inFIG.5. In some embodiments, the sidewall spacers124has substantially planar sidewalls, as illustrated inFIG.5. In other embodiments, the sidewall spacers124has outer sidewalls that are continuous and curved, similar to the sidewall spacers124inFIG.4A. FIG.6illustrates a cross-sectional view of some additional embodiments of an integrated chip600having an MRAM device. The integrated chip600comprises a substrate102including an embedded memory region602and a logic region604. Isolation structures606separate the embedded memory region602from the logic region604. The isolation structures606comprise a dielectric material and may be, for example, shallow isolation trenches (STI). A dielectric structure106is arranged over the substrate102and includes interconnect vias108, interconnect wires110. The logic region604comprises a transistor device609arranged within the substrate102and coupled to interconnect vias610and interconnect wires612. The embedded memory region602comprises a first access transistor104and a second access transistor608arranged within a substrate102. In some embodiments, the first access transistor104has a first gate electrode104cover a first gate oxide layer104dand arranged between a first drain region104band a common source region104a.Similarly, the second access transistor608has a second gate electrode608bover a second gate oxide layer608cand arranged between a second drain region608aand a common source region104a.The common source region104ais coupled to a source-line SL and the first gate electrode104cand the second gate electrode608bare coupled to word-lines WL1-WL2. The interconnect vias108and interconnect wires110couple the first drain region104bto MTJ stack116. Similarly, the second drain region608ais coupled to a second MTJ stack616. The MTJ stack116and the second MTJ stack616are coupled to bit-lines BL1-BL2by upper interconnect structures126,626. Although integrated chip600illustrates the word-lines WL1-WL2, the source-line SL, the bit-lines BL1-BL2, and the MTJ stacks116,616as being located at certain levels within a BEOL (back-end-of-the-line) stack, it will be appreciated that the position of these elements is not limited to those illustrated positions. Rather, the elements may be at different locations within a BEOL stack. For example, in some alternative embodiments, the MTJ stack116and the second MTJ stack616may be located between a second and third metal interconnect wire. FIGS.7-19illustrate cross-sectional views700-1900of some embodiments of a method of forming an integrated chip having an embedded MRAM cell. AlthoughFIGS.7-19are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.7-19are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in cross-sectional view700ofFIG.7, a substrate102is provided. In various embodiments, the substrate102may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. A first access transistor104is formed over the substrate102. In some embodiments, the first access transistor104may be formed by forming a first gate oxide layer104dover the substrate102and forming a layer of the first gate electrode104cover the gate oxide. The first gate oxide layer104dand the layer of first gate electrode104cmay be formed by way of vapor deposition processes (e.g., CVD, PE-CVD, PVD, or ALD). In some embodiments, the first gate electrode104cmay comprise doped polysilicon. In some embodiments, the first gate electrode104cmay comprise a sacrificial gate material that is subsequently replaced with a metal gate material, such as aluminum, cobalt, ruthenium, or the like. The first gate oxide layer104dand the first gate electrode104care patterned to define a gate structure having a first gate oxide layer104dand a first gate electrode104cover the first gate oxide layer104d.In some embodiments, the first gate oxide layer104dand the layer of the first gate electrode104cmay be selectively patterned according to a masking layer (not shown) formed over the gate material. In some embodiments, the masking layer may comprise a photosensitive material (e.g., photoresist) formed by a spin coating process. In such embodiments, the layer of photosensitive material is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies a solubility of exposed regions within the photosensitive material to define soluble regions. The photosensitive material is subsequently developed to define openings within the photosensitive material by removing the soluble regions. In other embodiments, the masking layer may comprise a mask layer (e.g., a silicon nitride layer, a silicon carbide layer, or the like). The first source region104aand the first drain region104bare then formed by, in many embodiments, ion implantation using the first gate electrode104cas a mask. One or more lower interconnect layers109are formed within a lower dielectric structure106aarranged over the substrate102and are coupled to the first access transistor104. In some embodiments, one or more of the one or more lower interconnect layers109may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming an ILD layer over the substrate102, etching the ILD layer to form a via hole and/or a metal trench, and filling the via hole and/or metal trench with a conductive material. In some embodiments, the ILD layer may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.) and the conductive material may be formed using a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.). In various embodiments, the one or more lower interconnect layers109may comprise tungsten, copper, or aluminum copper, or the like. An etch stop layer112′ is formed over interconnect wire110and the lower dielectric structure106a.In some embodiments, the etch stop layer112′ may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.) In some embodiments, the etch stop layer112′ may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. As shown in cross-sectional view800ofFIG.8, the etch stop layer112′ is patterned to expose a portion of interconnect wire110, forming an etch stop structure112. In many embodiments, the etch stop layer112′ is patterned through photolithography using a mask over the etch stop layer112′. As shown in cross-sectional view900ofFIG.9, a bottom electrode layer114′ is deposited over the etch stop structure112and interconnect wire110. The bottom electrode layer114′ is a conductive material, for example, Ta, Ti, W or Ru. In some embodiments, a planarization process (e.g., a chemical mechanical planarization process) may be conducted to remove excess metal such that an upper surface of the bottom electrode layer114′ is substantially planar. A lower ferromagnetic electrode layer116c′ is deposited over the bottom electrode layer114′. A thin tunneling barrier layer116b′ is deposited over the lower ferromagnetic electrode layer116c′, and an upper ferromagnetic electrode layer116a′ is deposited over the thin tunneling barrier layer116b′. The upper ferromagnetic electrode layer116a′, the thin tunneling barrier layer116b′, and the lower ferromagnetic electrode layer116c′ make up MTJ stack layers116′. In some embodiments, a capping film118′ is deposited on top of MTJ stack layers116′. The capping film118′ may comprise, for example, tantalum, titanium, tantalum nitride, titanium nitride, or combinations thereof. In some embodiments, the capping film118′ may be formed by a deposition technique (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in a range of between approximately 0.5 nanometer and approximately 5 nanometers. A sacrificial dielectric layer902′ (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric) is deposited over the MTJ stack layers116′ and/or the capping film118′. As shown in cross-sectional view1000ofFIG.10, the sacrificial dielectric layer902′ is selectively patterned to define a patterned sacrificial dielectric902having sidewalls defining an opening1002that extends through the patterned sacrificial dielectric902. The opening1002exposes the capping film118′. In many embodiments, the sacrificial dielectric902′ is patterned by photolithography to form the opening1002. In some embodiments, a width w of the opening1002in the patterned sacrificial dielectric902is in the range of between approximately 15 nanometers and approximately 150 nanometers. In many embodiments, the opening1002has sidewalls arranged at an obtuse angle A, with respect to an exposed upper surface of the capping film118′. As shown in the cross-sectional view1100ofFIG.11A, in some embodiments, a glue material120″ (e.g., a diffusion barrier material) is deposited over the patterned sacrificial dielectric902and within the opening1002of the patterned sacrificial dielectric902. In some embodiments, the glue material120″ may be formed by a deposition technique (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in a range of between approximately 1 nanometer and approximately 15 nanometers and may comprise tantalum, titanium, tantalum nitride, titanium nitride, or combinations thereof. In some embodiments, illustrated inFIG.11A, a plurality of top electrode materials are deposited over the glue material120″. For example, a first top electrode material122a″ may be deposited within the opening1002, and a second top electrode material122b″ may be deposited within the opening1002over the first top electrode material122a″. The first top electrode material122a″ is a different material than the second top electrode material122b″. The first top electrode material122a″ and the second top electrode material122b″are conductive materials, such as, for example, tantalum, titanium, tantalum nitride, titanium nitride, tungsten, or ruthenium. In some embodiments, the second top electrode material122b″ is used as a mask for patterning in future steps. Thus, in some embodiments, the first top electrode material122a″ has a higher etch rate than the second top electrode material122b″. In some alternative embodiments, shown in the cross-sectional view1102ofFIG.11B, a first top electrode material122a″ is deposited over the patterned sacrificial dielectric902and within the opening1002to completely fill the opening1002. The second top electrode material122b″ is not necessary in some embodiments that have different future patterning steps than embodiments as inFIG.11A. As shown in the cross-sectional view1200ofFIG.12, a planarization process is performed along line1202. The planarization process removes excess of the glue material120″, the first top electrode material122a″, and the second top electrode material122b′ that are above a topmost surface of the patterned sacrificial dielectric902to form a planar glue layer120′ (e.g., a planar diffusion barrier layer), a planar first top electrode122a′, and a planar second top electrode122b.In some embodiments, the planarization process may comprise a chemical mechanical planarization (CMP) process, wherein the CMP process is conducted until a top surface of the patterned sacrificial dielectric902is exposed. As shown in the cross-sectional view1300ofFIG.13, the patterned sacrificial dielectric902is removed such that the planar glue layer120′, planar first top electrode122a′, and planar second top electrode122bare arranged overlying the MTJ stack layers116′. The patterned sacrificial dielectric902may be removed using an etchant. As shown in the cross-sectional view1400ofFIG.14, a first etching process may use one or more etchants1402to pattern the MTJ stack layers116′ and the capping film118′ to form a capping layer118over the MTJ stack116. The one or more etchants1402may comprise a dry etchant or a wet etchant. The planar second top electrode122bis used in this embodiment to act as a hard mask for the one or more etchants1402. A top portion of the planar second top electrode122bmay be removed by the one or more etchants1402, such that after the first etching process, the planar second top electrode122bis thinner than before the first etching process. The MTJ stack116has sidewalls that meet a bottom surface at angle B as illustrated inFIG.14, such that angle B is equal to or less than angle A. During the first etching process, portions of the planar first top electrode122a′ uncovered by the planar second top electrode122bmay be removed, but a substantial portion of the planar first top electrode122a′ remains. Upper portions of the planar glue layer120′ also may be removed during the first etching process. The glue layer120and the planar top electrode122a′ may have slanted upper sidewalls as a result of the first etching process, such that the glue layer120has a second maximum height h2measured from a bottom surface of the planar first top electrode122a′ to an inner sidewall of the glue layer120and a third maximum height h3measured from the bottom surface of the planar first top electrode122a′ to an outer sidewall of the glue layer120. The third maximum height h3measures to be less than the second maximum height h2by a range of between approximately 1 nanometer and approximately 5 nanometers due to effects from the one or more etchants1402. A fourth maximum height h4is measured after the first etching process from a bottom of the planar first top electrode122a′ to a top of the planar second top electrode122b,as shown inFIG.14. In some embodiments (not shown), an additional etching processes may be used after the first etching process to pattern the bottom electrode layer114′, again using the planar second top electrode122bas the hard mask for the additional etch. As shown in the cross-sectional view1500ofFIG.15, a sidewall spacer layer124′ is conformally deposited over the embodiment in cross-sectional view1400. In some embodiments, the sidewall spacer layer124′ may be deposited by a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). The sidewall spacer layer124′ may comprise a dielectric material such as a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), a carbide (e.g., silicon carbide), or the like. As shown in the cross-sectional view1600ofFIG.16, a second etching process may use one or more etchants1602(e.g., a dry etchant) to etch the sidewall spacer layer124′ to form sidewall spacers124. The sidewall spacers124typically have a curved outer sidewall because of vertical etching effects. The second etching process removes portions of the sidewall spacer layer124′ over the bottom electrode layer114′ and over the planar second top electrode122b.After the second etching process, the planar first top electrode122a′ has a fifth maximum height h5measured from a bottom surface of the planar first top electrode122a′ to a top surface of the planar first top electrode122a′. As shown in the cross-sectional view1700ofFIG.17, a third etching process may use one or more etchants1702(e.g., a dry etchant) to pattern the bottom electrode layer114′ to form the bottom electrode114. The planar second top electrode122bmay act as a hard mask, as well as the sidewall spacers124. The sidewall spacers124may reduce in height due to etching effects from the third etching process. For example, in the cross-sectional view1700, the sidewall spacers124have a top surface that is below a top surface of the glue layer120after the third etching process is used. During the third etching process, in some embodiments, the planar second top electrode122bis removed, and part of the planar first top electrode122a′ is removed resulting in a first top electrode122a.A sixth maximum height h6is measured from a bottom surface of the first top electrode122ato a top surface of the first top electrode122aafter the third etching process. The sixth maximum height h6in cross-sectional view1700is less than the fifth maximum height h5in cross-sectional view1600due to effects of the third etching process. The sixth maximum height h6may measure to be in the range of between approximately 10 nanometers to approximately 100 nanometers. Although the bottom electrode114is patterned in the method illustrated by cross-sectional view1700inFIG.17, it will be appreciated that the bottom electrode114may be patterned during other steps in the method, such as with an additional etch after patterning of the MTJ stack116or even prior to the deposition of the MTJ stack layers116′ by using an etch process. As shown in cross-sectional view1800ofFIG.18, an upper dielectric structure106bis deposited over the etch stop structure112. The upper dielectric structure106bcovers top surfaces of the first top electrode122a. As shown in cross-sectional view1900ofFIG.19, the upper dielectric structure106bis patterned to define an opening over the first top electrode122a.An upper interconnect structure126is subsequently formed within the opening and over the first top electrode122a.The first top electrode122ais electrically coupled to the upper interconnect structure126. FIG.20illustrates a flow diagram of some embodiments of a method2000of forming an integrated chip having an MRAM device. While method2000is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At2002, a first access transistor is formed within a substrate.FIG.7illustrates a cross-sectional view700of some embodiments corresponding to act2002. At2004, one or more interconnect layers are formed within a lower dielectric structure formed over the substrate.FIG.7illustrates a cross-sectional view700of some embodiments corresponding to act2004. At2006, an etch stop layer is formed over the one or more interconnect layers.FIG.7illustrates a cross-sectional view700of some embodiments corresponding to act2006. At2008, the etch stop layer is selectively patterned to expose an interconnect wire.FIG.8illustrates a cross-sectional view800of some embodiments corresponding to act2008. At2010, a bottom electrode layer is formed over the interconnect wire and etch stop layer. At2012, MTJ layers are formed over the bottom electrode layer. At2014, a capping film is formed over the MTJ layers. At2016, a sacrificial dielectric layer is deposited over the capping film.FIG.9illustrates a cross-sectional view900of some embodiments corresponding to acts2010-2016. At2018, the sacrificial dielectric layer is patterned to form an opening that exposes the capping film. A glue material and one or more top electrode materials are deposited within the opening.FIGS.10,11A and11Billustrate cross-sectional views1000,1100and1102of some embodiments corresponding to act2018. At2020, the one or more top electrode materials and glue layer are planarized to the top of the patterned sacrificial dielectric layer.FIG.12illustrates a cross-sectional view1200of some embodiments corresponding to act2020. At2022, the patterned sacrificial dielectric is removed.FIG.13illustrates a cross-sectional view1300of some embodiments corresponding to act2022. At2024, the capping film and MTJ layers are etched using the top electrode as the hard mask to form a capping layer over an MTJ stack.FIG.14illustrates a cross-sectional view1400of some embodiments corresponding to act2024. At2026, a sidewall spacer layer is deposited and etched to form sidewall spacers.FIGS.15and16illustrate cross-sectional views1500and1600of some embodiments corresponding to act2026. At2028, the bottom electrode layer is patterned to from a bottom electrode, using the top electrode and the sidewall spacers as a mask.FIG.17illustrates a cross-sectional view1700of some embodiments corresponding to act2028. At2030, additional interconnect layers are formed within an upper dielectric structure over the top electrode.FIGS.18and19illustrate cross-sectional views1800and1900of some embodiments corresponding to act2030. Therefore, the present disclosure relates to a new method of manufacturing MTJ stacks that eliminates a top electrode etch to provide for improved control over critical dimensions of the top electrode structure and an underlying MTJ stack. Accordingly, in some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer; forming a sacrificial dielectric layer over the MTJ layers; patterning the sacrificial dielectric layer to define a cavity; forming a top electrode material within the cavity; removing the sacrificial dielectric layer; and patterning the MTJ layers according to the top electrode material to define an MTJ stack after removing the sacrificial dielectric layer. In some embodiments, the method further includes depositing a glue layer onto surfaces of the sacrificial layer defining the cavity; and depositing the top electrode material onto the glue layer to fill the cavity. In some embodiments, after patterning the MTJ layers according to the top electrode material, the glue layer has a first height measured from a bottom surface of the top electrode material to a top surface of the glue layer and the top electrode material has a second height measured from a bottom surface of the top electrode material to a top surface of the top electrode material, the second height greater than the first height. In some embodiments, an etching process used to pattern the MTJ layers according to the top electrode material removes a part of the glue layer and causes an outermost sidewall of the glue layer facing away from the top electrode material to be curved. In some embodiments, a height of the top electrode material decreases during the patterning of the MTJ layers. In some embodiments, the method further includes forming a capping film over the MTJ layers and below the sacrificial dielectric layer, so that patterning the sacrificial dielectric layer exposes a top surface of the capping film. In some embodiments, the method further includes patterning the capping film to define a capping layer over the MTJ layers, the capping layer having a thickness that increases from a center of the capping layer to an outermost sidewall of the capping layer. In other embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer; depositing a sacrificial layer over the MTJ layers; etching the sacrificial layer to form a cavity defined by sidewalls of the sacrificial layer; depositing a glue layer onto and between the sidewalls of the sacrificial layer defining the cavity; forming a conductive material over the glue layer and within the cavity, wherein the glue layer contacts sidewalls and a bottom surface of the conductive material; removing the sacrificial layer; and patterning the MTJ layers according to the conductive material and the glue layer to define a magnetic tunnel junction (MTJ). In some embodiments, the method further includes forming a capping film over the MTJ layers prior to depositing the sacrificial layer; and patterning the capping film to define a capping layer. In some embodiments, after removing the sacrificial layer, the glue layer has a first height measured from the bottom surface of the conductive material to a top surface of the glue layer that is substantially equal to a second height of the conductive material. In some embodiments, after patterning the MTJ layers, the glue layer has a third height measured from the bottom surface of the conductive material to the top surface of the glue layer that is less than the second height. In some embodiments, the conductive material has sidewalls arranged at a first angle with respect to the bottom surface of the conductive material and the MTJ has sidewalls arranged at a second angle with respect to a bottom surface of the MTJ, the second angle less than the first angle. In some embodiments, the method further includes depositing a sidewall spacer layer over the conductive material; patterning the sidewall spacer layer to form a sidewall spacer surrounding the MT, wherein patterning the sidewall spacer layer exposes a top surface of the conductive material and top surfaces of the bottom electrode layer; and etching the bottom electrode layer using the conductive material and the sidewall spacer as a mask. In some embodiments, after forming the conductive material within the cavity, a top surface of the conductive material meets a sidewall of the conductive material at an angled corner; and after patterning of the MTJ layers according to the conductive material, the top surface of the conductive material meets the sidewall of the conductive material at a rounded corner. In yet other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within one or more stacked inter-level dielectric (ILD) layers over a substrate; an etch stop structure disposed over the one or more lower interconnect layers; a bottom electrode disposed over the etch stop structure, the bottom electrode electrically contacts the one or more lower interconnect layers; a magnetic tunnel junction (MTJ) stack disposed over the bottom electrode, the MTJ stack has sidewalls arranged at a first angle with respect to a bottom surface of the MTJ stack; and a top electrode disposed over the MTJ stack, the top electrode has sidewalls arranged at a second angle with respect to a bottom surface of the top electrode, the second angle greater than the first angle. In some embodiments, the integrated chip further includes a capping layer above the MTJ stack and below the top electrode. In some embodiments, the capping layer has a curved upper surface and a thickness that increases from a center of the capping layer to an outermost sidewall of the capping layer. In some embodiments, the integrated chip further includes a diffusion barrier layer continuously extending from between the top electrode and the MTJ stack to contact sidewalls of the top electrode. In some embodiments, the diffusion barrier layer has a curved upper surface that increases in height as a distance from the sidewalls of the top electrode decreases. In some embodiments, a first height is measured from the bottom surface of the top electrode to a topmost surface of the top electrode, a second height is measured from the bottom surface of the top electrode to a topmost surface of the diffusion barrier layer, and the first height is greater than the second height. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 41,698 |
11943935 | DETAILED DESCRIPTION Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “connect”, “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. Referring toFIGS.1-5,FIGS.1-5illustrate a layout pattern of a MRAM device with elements in different levels according to an embodiment of the present invention. As shown inFIG.1, a substrate12made of semiconductor material is provided, in which the substrate12could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). Next, a first cell region14, a second cell region16, a third cell region18, and a fourth cell region20are defined on the substrate12, in which each of the cell region or memory cell region preferably includes two sets of transistors and a MTJ for constituting a 2T1MTJ cell structure. The substrate12preferably includes a diffusion region22extending through the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20, in which the diffusion region22includes a H-shape according to a top view perspective. Specifically, the diffusion region22further includes a first portion24extending from the first cell region14to the third cell region18along a first direction (such as Y-direction), a second portion26extending from the second cell region16to the fourth cell region20along the first direction, a third portion28extending from the first cell region14to the second cell region16along a second direction (X-direction) for connecting the first portion24and the second portion26, a fourth portion30extending from the third cell region18to the fourth cell region20along the second direction for connecting the first portion24and the second portion26, and a fifth portion32extending between the third portion28and the fourth portion30along the second direction for connecting the first portion24and the second portion26. Viewing from an overall perspective the third portion28, the fourth portion30, and the fifth portion32are all disposed extending along the X-direction and parallel to each other, and the fifth portion32is disposed between the third portion28and the fourth portion30while overlapping the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20. A plurality of gate patterns or word lines (WLs) including a first gate pattern34, a second gate pattern36, a third gate pattern38, and a fourth pattern40are disposed on the diffusion region22, in which the first gate pattern34is extending from the first cell region14to the second cell region16along the second direction, the second gate pattern36is extending from the first cell region14to the second cell region16along the second direction, the third gate pattern38is extending from the third cell region18to the fourth cell region20along the second direction, and the fourth gate pattern40is extending from the third cell region18to the fourth cell region20along the second direction. The MRAM device further includes a first source region S1disposed on the third portion28, a second source region S2disposed on the fourth portion30, a third source region S3disposed on the fifth portion32, a first drain region D1disposed on the first cell region14between the first gate pattern34and the second gate pattern36, a second drain region D2disposed on the second cell region16between the first gate pattern34and the second gate pattern36, a third drain region D3disposed on the third cell region18between the third gate pattern38and the fourth gate pattern40, and a fourth drain region D4disposed on the fourth cell region20between the third gate pattern38and the fourth gate pattern40. It should be noted that a contact plug (not shown) having rectangular profile is disposed on each of the first source region S1, second source region S2, third source region S3, first drain region D1, second drain region D2, third drain region D3, and fourth drain region D4for connecting the source and drain regions to the first level metal patterns formed afterwards while the source and drain regions are essentially disposed adjacent to two sides of the gate patterns and not limited in the rectangular blocks. As shown inFIG.2, the MRAM device further includes a plurality of first level metal patterns M1disposed on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20while overlapping each of the gate patterns, in which the first level metal patterns include a first metal pattern42extending along the first direction such as Y-direction overlapping and connecting the first source region S1, the second source region S2, and the third source region S3, a second metal pattern44extending along the first direction overlapping and connecting the first drain region D1, a third metal pattern46extending along the first direction overlapping and connecting the second drain region D2, a fourth metal pattern48extending along the first direction overlapping and connecting the third drain region D3, and a fifth metal pattern50extending along the first direction overlapping and connecting the fourth drain region D4. Viewing from a top view perspective, each of the first metal pattern42, second metal pattern44, third metal pattern46, fourth metal pattern48, and fifth metal pattern50include a rectangular shape extending along the Y-direction and overlapping the source regions and drain regions in the cell regions. It should be noted that the first metal pattern42from the first level metal patterns is coupled to or directly connecting to a source line (SL) so that signals could be transmitted on the same level. MRAM device also includes a plurality of first level via patterns (also referred to as V1) disposed on the first level metal patterns on the first cell region14, second cell region16, third cell region18, and fourth cell region20, in which the first level via patterns include a via pattern52disposed on the second metal pattern44, a via pattern54disposed on the third metal pattern46, a via pattern56disposed on the fourth metal pattern48, and a via pattern58disposed on the fifth metal pattern50. Next, as shown inFIG.3, the MRAM device further includes a plurality of second level metal patterns M2disposed on and overlapping each of the first level metal patterns and first level via patterns on the first cell region14, second cell region16, third cell region18, and fourth cell region20, in which the second level metal patterns includes a metal pattern62overlapping the second metal pattern44on the first cell region14, a metal pattern64overlapping the third metal pattern46on the second cell region16, a metal pattern66overlapping the fourth metal pattern48on the third cell region18, and a metal pattern68overlapping the fifth metal pattern50on the fourth cell region20. Viewing from a top view perspective, each of the metal patterns from the second level metal patterns include a substantially square shape overlapping the drain regions disposed on each of the cell regions. Next, as shown inFIG.4, the MRAM device includes a plurality of MTJs disposed on the second level metal patterns and coupled to the lower level second level metal interconnections and even lower level drain regions, in which the MTJs include a first MTJ72disposed on the metal pattern62on the first cell region14and connected to the first drain region D1, a second MTJ74disposed on the metal pattern64on the second cell region16and connected to the second drain region D2, a third MTJ76disposed on the metal pattern66on the third cell region18and connected to the third drain region D3, and a fourth MTJ78disposed on the metal pattern68on the fourth cell region20and connected to the fourth drain region D4. Since the MTJs are disposed on the second level metal patterns, the MTJs could be understood as third level metal patterns M3. In this embodiment, each of the MTJs preferably includes a bottom electrode, a pinned layer, a barrier layer, a free layer, and a top electrode disposed on the second level metal patterns. Preferably, the bottom electrode layer and the top electrode layer are made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Moreover, the pinned layer could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field. Overall, each of the cell regions includes a 2T1MTJ cell structure that preferably includes two transistors accompanying a single MTJ. For instance, a first source region S1, a first gate pattern34, a first drain region D1, a second gate pattern36, a third source region D3, and a first MTJ72disposed on the first cell region14preferably constitute a 2T1MTJ cell structure in the first cell region14. Next, as shown inFIG.5, the MRAM device includes a plurality of fourth level metal patterns M4disposed on the first cell region14, second cell region16, third cell region18, and fourth cell region20to overlap the MTJs, in which the fourth level metal patterns include a metal pattern82extending from the first cell region14to the third cell region18along the first direction such as Y-direction to overlap the first MTJ72and the third MTJ76and a metal pattern84extending from the second cell region16to the fourth cell region20along the same first direction to overlap the second MTJ74and the fourth MTJ78. Viewing from a top view perspective, each of the metal patterns from the fourth level metal patterns include rectangular shape extending along the Y-direction and overlapping the drain region and MTJ disposed in each cell region. It should also be noted that each of the metal patterns82,84from the fourth level metal patterns are also coupled to or directly connected to a bit line (BL) for passing the signals. Referring toFIGS.6-10,FIGS.6-10illustrate a layout pattern of a MRAM device according to an embodiment of the present invention. For simplicity purpose, elements from the aforementioned embodiments are labeled with same numberings. As shown inFIG.6, a substrate112made of semiconductor material is provided, in which the substrate112could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). Next, a first cell region114and a second cell region116are defined on the substrate112, in which each of the cell region or memory cell region preferably includes three sets of transistors and two MTJs for constituting a 3T2MTJ cell structure. The substrate112preferably includes a diffusion region122extending through the first cell region114and the second cell region116, in which the diffusion region122includes a first H-shape and a second H-shape according to a top view perspective. Specifically, the diffusion region122further includes a first portion124extending in the first cell region114along a first direction (such as Y-direction), a second portion126extending in the second cell region116along the first direction, a third portion128extending from the first cell region114to the second cell region116along a second direction (X-direction) for connecting the first portion124and the second portion126, and a fourth portion130extending from the first cell region114to the second cell region116along the second direction for connecting the first portion124and the second portion126. It should be noted that viewing from a top view perspective, the third portion128and the fourth portion130preferably overlaps the boundaries of the first cell region114and second cell region116and part of the first portion124, second portion126, third portion128, and fourth portion130exceed the boundaries of the first cell region114and second cell region116. Nevertheless, according to other embodiment of the present invention it would also be desirable to contain all the outer boundary of the first portion124, second portion126, third portion128, and fourth portion130within the first cell region114and second cell region116so that all the four portions of the diffusion region122do not cross over the boundaries of the two cell regions, which is also within the scope of the present invention. The MRAM device further includes a plurality of gate patterns such as a first gate pattern134, a second gate pattern136, and a third gate pattern138disposed on the diffusion region22, in which the first gate pattern134is extending from the first cell region114to the second cell region116along the second direction, the second gate pattern136is extending from the first cell region114to the second cell region116along the second direction, and the third gate pattern138is extending from the first cell region114to the second cell region116along the second direction. The MRAM device further includes a first source region S1disposed on the third portion128, a second source region S2disposed on the fourth portion130, a first drain region D1disposed on the first cell region114between the first gate pattern134and the second gate pattern136, a second drain region D2disposed on the second cell region116between the first gate pattern134and the second gate pattern136, a third drain region D3disposed on the first cell region114between the second gate pattern136and the third gate pattern138, and a fourth drain region D4disposed on the second cell region116between the second gate pattern136and the third gate pattern138. Similar to the aforementioned embodiment, a contact plug (not labeled) having rectangular shape is disposed on each of the first source region S1, second source region S2, first drain region D1, second drain region D2, third drain region D3, and fourth drain region D4for connecting the source and drain regions to the first level metal patterns formed afterwards while the source and drain regions are essentially disposed adjacent to two sides of the gate patterns and not limited in the rectangular blocks. As shown inFIG.7, the MRAM device further includes a plurality of first level metal patterns M1disposed on the first cell region114and the second cell region116while overlapping each of the gate patterns, in which the first level metal patterns include a first metal pattern142extending along the first direction such as Y-direction overlapping and connecting the first source region S1and the second source region S2, a second metal pattern144extending along the first direction overlapping and connecting the first drain region D1, a third metal pattern146extending along the first direction overlapping and connecting the second drain region D2, a fourth metal pattern148extending along the first direction overlapping and connecting the third drain region D3, and a fifth metal pattern150extending along the first direction overlapping and connecting the fourth drain region D4. Viewing from a top view perspective, each of the first metal pattern142, second metal pattern144, third metal pattern146, fourth metal pattern148, and fifth metal pattern150include a rectangular shape extending along the Y-direction and overlapping the source regions and drain regions in the cell regions. Similar to the aforementioned embodiment, the first metal pattern142from the first level metal patterns is coupled to or directly connecting to a source line (SL) so that signals could be transmitted on the same level. MRAM device also includes a plurality of first level via patterns (also referred to as V1) disposed on the first level metal patterns on the first cell region114and second cell region116, in which the first level via patterns include a via pattern152disposed on the second metal pattern144, a via pattern154disposed on the third metal pattern146, a via pattern156disposed on the fourth metal pattern148, and a via pattern158disposed on the fifth metal pattern150. Next, as shown inFIG.8, the MRAM device further includes a plurality of second level metal patterns M2disposed on and overlapping each of the first level metal patterns and first level via patterns on the first cell region114and second cell region116, in which the second level metal patterns includes a metal pattern162overlapping the second metal pattern144on the first cell region114, a metal pattern164overlapping the third metal pattern146on the second cell region116, a metal pattern166overlapping the fourth metal pattern148on the first cell region114, and a metal pattern168overlapping the fifth metal pattern150on the second cell region116. Viewing from a top view perspective, each of the metal patterns from the second level metal patterns include a substantially square shape overlapping the drain regions disposed on each of the cell regions. Next, as shown inFIG.9, the MRAM device includes a plurality of MTJs disposed on the second level metal patterns and coupled to the lower level second level metal patterns and even lower level drain regions, in which the MTJs include a first MTJ172disposed on the metal pattern162on the first cell region114and connected to the first drain region D1, a second MTJ174disposed on the metal pattern164on the second cell region116and connected to the second drain region D2, a third MTJ176disposed on the metal pattern166on the first cell region114and connected to the third drain region D3, and a fourth MTJ178disposed on the metal pattern168on the second cell region116and connected to the fourth drain region D4. Similar to the aforementioned embodiment, each of the MTJs preferably includes a bottom electrode, a pinned layer, a barrier layer, a free layer, and a top electrode disposed on the second level metal patterns. Overall, each of the cell regions includes a 3T2MTJ cell structure that preferably includes three transistors accompanying two MTJs. For instance, a first source region S1, a first gate pattern134, a first drain region D1, a second gate pattern136, a third drain region D3, a third gate pattern138, a second source region S2, a first MTJ172, and a third MTJ176disposed on the first cell region114preferably constitute a 3T2MTJ cell structure in the first cell region114. Next, as shown inFIG.10, the MRAM device includes a plurality of fourth level metal patterns M4disposed on the first cell region114and second cell region116to overlap the MTJs, in which the fourth level metal patterns include metal patterns182,184extending along the first direction such as Y-direction in the first cell region114to overlap the first MTJ172and the third MTJ176and metal patterns186,188extending along the same first direction in the second cell region116to overlap the second MTJ174and the fourth MTJ178. Viewing from a top view perspective, each of the metal patterns from the fourth level metal patterns include rectangular shape extending along the Y-direction and overlapping the drain region and MTJ disposed in each cell region. It should also be noted that each of the metal patterns from the fourth level metal patterns is also coupled to or directly connected to a bit line (BL) for passing the signals. Overall, in contrast to using the second level metal patterns to couple to source line (SL) for transmitting signals in conventional MRAM device, the present invention preferably adjusts the layout of the diffusion region and first level metal patterns so that the first level metal patterns could be coupled to the source line SL directly. By using this design it would be desirable to save significantly more space in the memory cell regions and also adjust the position of the MTJs to prevent misalignment between MTJs and metal interconnections underneath. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 21,433 |
11943936 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another, Terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies, Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. FIG.1illustrates a schematic view of a layout of a semiconductor device1a, in accordance with some embodiments of the present disclosure. The semiconductor device1acan include devices10,20, and30. In some embodiments, the device10can include an active region120-1, a gate130-1, a conductive feature170-1, a conductive feature170-2, a conductive via180-1, a conductive via180-2, a conductive feature190-1, and a conductive feature190-2. The device20can include an active region a gate130-2, a conductive feature172-2, a resistive material layer174-2, and a conductive via180-3. The device30can include an active region120-3, a gate130-3, a conductive feature172-3, a resistive material layer174-3, and the conductive via180-3. It should be noted that some elements of the semiconductor device1aare not shown inFIG.1for clarity. The numbers of the active regions, the gates, and the metal features are given for illustrative purposes. Various numbers of the active regions, the gates, and the conductive features and other features are within the contemplated scope of the present disclosure. The terms “comprise” or “comprising,” “include” or “including,” “have” or “having,” and the like used in this application are to be understood to be open-ended, i.e., to mean including but not limited to. Accordingly, various elements and/or structures, which are not shown inFIG.1and formed in the semiconductor device1a, are within the contemplated scope of the present disclosure. In some embodiments, the device10can include a transistor. In some embodiments, the device10can include, but is not limited to, a fin field-effect transistor (FinFET), a planar metal-oxide-semiconductor field-effect transistor (MOSFET), or other types of transistors. In some embodiments, the device20can include, but is not limited to, a resistive random access memory (RRAM) resistor. In some embodiments, the device30can include, but is not limited to, a RRAM resistor. The RRAM resistor has two or more states with different electric resistance values that correspond to a different digital value. The RRAM resistor switches from one state to another in response to application of a predetermined voltage or current to the RRAM resistor. For example, the RRAM resistor has a state of relatively high resistance, referred to as “a high resistance state”, and a state of relatively low resistance, referred to as “a low resistance state”. The RRAM resistor may be switched from the high resistance state to the low resistance state, or from the low resistance state to high resistance state by applying a predetermined voltage or current to its electrodes. In some embodiments, as shown inFIG.1, the active region120-1can extend along the X direction. In some embodiments, the active regions120-2and120-3can extend along the Y direction. In some embodiments, each one of the active regions120-1,120-2, and120-3can include one or more fin structures. In various embodiments, at least one fin structure is formed on, or formed with, each one of the active regions120-1,120-2, and120-3. In some embodiments, the term “active region” discussed in the present disclosure may be also referred to as “OD” (oxide dimensioned area). In some embodiments, the gate130-1can extend along the Y direction. In some embodiments, the gates130-2and130-3can extend along the X direction. In some embodiments, the gate130-1can overlap the active region120-1, the gate130-2can overlap the active region120-2, and the gate130-3can overlap the active region120-3, respectively. In some embodiments, the gates130-1,130-2, and130-3can be substantially perpendicular to the active regions120-1,120-2, and120-3in a plain view, or in the Z direction, respectively. In some embodiments, the term “gate” discussed in the present disclosure is also referred to as “PO.” The terms “overlap” and “overlapping” in this disclosure are used to describe that two elements and/or features are at least partially vertically, or along the Z direction, aligned to each other. In some embodiments, the conductive features170-1,1713-2,172-2, and172-3may be located at a first horizontal level higher than the horizontal level of the gate130-1. The conductive features170-1and170-2can overlap the active region120-1. In some embodiments, the conductive features170-1and170-2can be spaced apart from each other. The conductive features170-1and170-2can be located, for example, at two opposite sides of the gate130-1. The conductive feature172-2can overlap the active region120-2. The conductive feature172-2can be located, for example, at a side of the gate130-2. The conductive feature172-3can overlap the active region120-3. The conductive feature172-3can be located, for example, at a side of the gate130-3. In some embodiments, the conductive features172-2and172-3can be located at two opposite sides of the conductive via180-3. In some embodiments, the term “conductive feature” located at the first horizontal level discussed in the present disclosure is also referred to as “first metal layer (M1).” The conductive via180-1can be located over and electrically coupled to the conductive feature170-1. The conductive via180-2can be located over and electrically coupled to the conductive feature170-2. In some embodiments, the term “conductive via” discussed in the present disclosure is also referred to as “V1.” The conductive features190-1and190-2may be located at a second horizontal level higher than the first horizontal level. The conductive features190-1and190-2can be spaced apart from each other. The conductive feature190-1can be located over and electrically coupled to the conductive feature170-1through the conductive via180-1. The conductive feature190-2can be located over and electrically coupled to the conductive feature170-2through the conductive via180-2, In some embodiments, the conductive feature190-2can extend into between the active regions120-2and120-3. In some embodiments, the conductive feature190-2can extend into between the conductive features172-2and172-3. In some embodiments, the term “conductive feature” located at the second horizontal level discussed in the present disclosure is also referred to as “second metal layer (M2).” The conductive via180-3can be electrically coupled to the conductive feature190-2. In some embodiments, the conductive via180-3can be located between the active regions120-2and120-3. In some embodiments, the conductive via180-3can be located between the conductive features172-2and172-3. In some embodiments, the conductive via180-3is free from vertically overlapping the active region120-1. In some embodiments, the conductive via180-3is free from vertically overlapping the conductive feature170-2. In some embodiments, the semiconductor device1afurther includes a resistive material structure174including the resistive material layers174-2and174-3. In some embodiments, the resistive material structure174can surround the conductive via180-3, In some embodiments, the resistive material structure174can be in contact with the conductive via180-3. In some embodiments, the resistive material layers174-2and174-3can be located at two opposite sidewalls of the conductive via180-3. In some embodiments, the device20can include, but is not limited to, a RRAM resistor. In some embodiments, the device20can include a resistor structure including the conductive feature172-2, the resistive material layer174-2, and the conductive via180-3. The conductive feature172-2can serve as a portion of the bottom electrode of the RRAM resistor, and the conductive via180-3can serve as a portion of the top electrode of the RRAM resistor. In some embodiments, the device30can include, but is not limited to, a RRAM resistor. In some embodiments, the device30can include a resistor structure including the conductive feature172-3, the resistive material layer174-3, and the conductive via180-3. The conductive feature172-3can serve as a portion of the bottom electrode of the RRAM resistor, and the conductive via180-3can serve as a portion of the top electrode of the RRAM resistor. In some embodiments, the conductive via180-3is electrically coupled to the device10. In some embodiments, the conductive via180-3can serve as a common electrode shared by the devices20and30. In some embodiments, the devices20and30can collaboratively define a twin bit RRAM resistor device. FIG.2illustrates a schematic view of a cross-sectional view along line A-A′ of the semiconductor device1ashown inFIG.1, in accordance with some embodiments of the present disclosure. In some embodiments, the device10can further includes a substrate100, a fin110-1, sidewalls140-1, source and drain structures (S/D features)152-1and154-1, an electrical conductor162-1, and an electrical conductor164-1. It should be noted that some elements are not illustrated inFIG.2for brevity. In some embodiments, the device10can include other elements or features, such as dielectric layers, etching stop layers, interlayer dielectric (ILD), doped regions and other elements or features. The substrate100can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate100may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate100may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonids; an alloy semiconductor including Sire, GaAsP, AlinAs, AlGaAs, GalnAs, GaInP, and/or GainAsP; or combinations thereof. The substrate100may include a plurality of regions (not shown) for forming p-type devices and/or n-type devices, such as PMOS and/or transistors, e.g., p-type FinFETs and/or n-type FinFETs. The fin110-1can be disposed on the substrate100. The fin110-1can include a semiconductor strip. In some embodiments, the fin110-1may protrude from the substrate100by etching the substrate100. In some embodiments, the fin110-1can correspond to the active region120-1ofFIG.1. In some embodiments, the gate130-1can include a gate dielectric layer (not shown) and a gate electrode layer (not shown). The gate dielectric layer can be disposed on the fin110-1. The gate dielectric layer may be a single layer or multiple layers. In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy) silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include dielectric material(s), such as high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. The high-k material may include hafnium oxide (HFO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3) yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material. Other suitable materials are within the contemplated scope of the disclosure. The gate electrode layer can be disposed on the gate dielectric layer. The gate electrode layer is made of conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the gate electrode layer includes a work function layer. The work function layer is made of metal material, and the metal material may include N-work-function metal or P-work-function metal. The N-work-function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof. The P-work-function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof. Other suitable materials are within the contemplated scope of the disclosure. The sidewalls140-1can be disposed on two opposite sides of the gate130-1. The sidewall140-1can be a single layer structure or a multi-layer structure. In some embodiments, the sidewall140-1can include SiO2, SiN, SiCN, SiOCN, SiC, SiOC, SiON, or the like, or combinations thereof. In some embodiments, the S/D features152-1and154-1can be formed on the fin110-1. The S/D features152-1and154-1can be formed on opposite sides of the gate130-1. In some embodiments, the S/D features152-1and154-1are doped regions configured for a PMOS device or P-type FinFET and include p-type dopants, such as boron, BF2+, and/or a combination thereof. In alternative embodiments, the S/D features152-1and154-1are doped regions configured for an NMOS device or N-type FinFET, and include n-type dopants, such as phosphorus, arsenic, and/or a combination thereof. In some other embodiments, the S/D features152-1and154-1are strained layers formed by an epitaxial growing process such as a selective epitaxial growing process. In some embodiments, recesses are formed in the fins on sides of the gate130-1, and the strained layers are formed by selectively growing epitaxy layers from the fins exposed in the recesses. In some embodiments, the strained layers include silicon germanium (SiGe), SiGeB, Ge, InSb, GaSb, InGaSb or combinations thereof for a P-type MOS or FinFET device. In alternative embodiments, the strained layers include silicon carbon (SiC), silicon phosphate (Silo), SiCP, InP, GaAs, AlAs, InAs, InAlAs, InGaAs or a SiC/SiP multi-layer structure, or combinations thereof for an N-type MOS or FinFET device. In some embodiments, the strained layers may be optionally implanted with an N-type dopant or a P-type dopant as needed. The electrical conductor162-1can be disposed on and electrically coupled to the S/D feature152-1. The electrical conductor164-1can be disposed on and electrically coupled to the S/I) feature154-1. The electrical conductor162-1and the electrical conductor164-1may include conductive materials, such as metal, metal nitride, alloy or other suitable materials. In some embodiments, the term “electrical conductor” discussed in the present disclosure is also referred to as “MD.” The conductive feature170-1can be disposed on and electrically coupled to the S/D feature152-1through the electrical conductor162-1. The conductive feature170-2can be disposed on and electrically coupled to the S/D feature154-1through the electrical conductor164-1. The conductive features170-1and170-2may include conductive materials, such as metal, metal nitride, alloy or other suitable materials. The conductive via180-1can be disposed on and electrically coupled to the conductive feature170-1. The conductive via180-2can be disposed on and electrically coupled to the conductive feature170-2. The conductive via180-1and the conductive via180-2may include conductive materials, such as metal, metal nitride, alloy or other suitable materials. In some embodiments, the conductive via180-1and the conductive via180-2can further include a barrier layer (not shown), such as metal nitride or other suitable materials. The conductive feature190-1can be disposed on and electrically coupled to the conductive via180-1. The conductive feature190-2can be disposed on and electrically coupled to the conductive via180-2. The material of the conductive features190-1and190-2can be the same as or similar to that of the conductive feature170-1. The resistive material structure174can surround the conductive via180-3. The resistive material structure174include oxide, nitride, oxynitride of metal, such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr. The conductive via180-3can be electrically coupled to the S/D feature154-1, The conductive via180-3can protrude from a bottom surface of the conductive feature190-2. The conductive via180-3can have a vertical length L1, and the conductive via180-2can have a vertical length L2. In some embodiments, L1 is greater than L2. In some embodiments, the conductive via180-3can extend to a horizontal level at which the conductive feature170-2is located. In some embodiments, a portion of the conductive via180-3is located at the first horizontal level. FIG.3illustrates a schematic view of a cross-sectional view along line B-B′ of the semiconductor device1ashown inFIG.1, in accordance with some embodiments of the present disclosure. In some embodiments, the device20can further includes a fin110-2, sidewalls140-2, S/D features152-2and154-2, an electrical conductor162-2, and an electrical conductor164-2, In some embodiments, the device30can further includes a fin110-3, sidewalls140-3, S/D features152-3and154-3, an electrical conductor162-3, and an electrical conductor164-3. The fins110-2and110-3can be disposed on the substrate100. The fin110-2can be separated from the fin110-3by an isolation structure102. The material and the structure of the fins110-2and110-3can be the same as or similar to those of the fin110-1. In some embodiments, the fins110-2and110-3can correspond to the active regions120-2and120-3ofFIG.1, respectively. The sidewalls140-2can be disposed on two opposite sides of the gate130-2, The sidewalls140-3can be disposed on two opposite sides of the gate130-3. The material and the structure of the sidewalls140-2and140-3can be the same as or similar to those of the sidewall140-1. The S/D features152-2and154-2can be formed on opposite sides of the gate130-2. The S/D features152-3and154-3can be formed on opposite sides of the gate130-3. The material and the structure of the S/D features152-2,152-3,154-2and154-3can be the same as or similar to those of the S/D feature152-1. The electrical conductor162-2can be disposed on and electrically coupled to the S/D feature152-2. The electrical conductor164-2can be disposed on and electrically coupled to the S/D feature154-2. The electrical conductor162-3can be disposed on and electrically coupled to the S/D feature152-3. The electrical conductor164-3can be disposed on and electrically coupled to the S/D feature154-3. The material and the structure of the electrical conductors162-2,162-3,164-2, and164-3can be the same as or similar to those of the electrical conductor162-1. The conductive feature172-2can be disposed on and electrically coupled to the S/D feature154-2through the electrical conductor164-2. The conductive feature172-3can be disposed on and electrically coupled to the S/D feature154-3through the electrical conductor164-3. The material and the structure of the conductive features172-2and172-3can be the same as or similar to those of conductive feature170-1. The conductive via180-3can be disposed between the conductive features172-2and172-3. The resistive material layer174-2can be disposed between the conductive feature172-2and the conductive via180-3, and therefore the conductive feature172-2, the resistive material layer174-2, and the conductive via180-3collaboratively define a RRAM resistor. The resistive material layer174-3can be disposed between the conductive feature172-3and the conductive via180-3, and therefore the conductive feature172-3, the resistive material layer174-3, and the conductive via180-3collaboratively define a RRAM resistor. In the embodiments of the disclosure, the structure and the manufacturing method of the RRAM resistor can be integrated with those of a FinFET transistor. Further, the conductive feature172-2, the resistive material layer174-2, the conductive feature172-3, the resistive material layer174-3, and the conductive via180-3can collaboratively define a twin bit RRAM resistor device, which can be applicable to various circuits. FIG.4illustrates a schematic view of a circuit2aof the semiconductor device1ashown inFIG.1, in accordance with some embodiments of the present disclosure. The circuit2acan be configured to perform a data access operation. The data access operation includes a read operation, a write operation, and a clear operation. Thus, the data access operation in this disclosure is not limited herein. The data can include, for example, a logic high value (for example, “1”) and a logic low value (for example, “0”). In some embodiments, the circuit2acan include device10,20and30. In some embodiments, the device10can have terminals T1, T2, and T3. The terminal T1 can be electrically coupled to a supply voltage V1and can serve as an input data terminal. The terminal T2 can be electrically coupled to a supply voltage V2and can serve as a set terminal. The terminal T3 can be electrically coupled to the devices20and30. The device20can be electrically coupled to a supply voltage V3. The device30can be electrically coupled to ground. The circuit2acan control a logic output node Y. During the clear operation, the supply voltage V2can have a voltage higher than those of the power supplies V1and V3, and the supply voltage V3can have a voltage greater than that of the supply voltage Vt. Both the devices20and30can be switched into the high resistance state. As a result, a current can flow from the supply voltage V3to ground. During the “write 0” operation, the device10is turned on, and the supply voltage V3can have a voltage substantially equal to that of the supply voltage V1. The device20is switched into the high resistance state, and the device30is switched into the low resistance state. As a result, a current can flow from the device10to ground. During the “read 0” operation, the device10is turned off, the device20is at the high resistance state, and the device30is at the low resistance state. As a result, a current can flow from ground to the logic output node Y. During the “write 1” operation, the device10is turned on, and the supply voltage V3can have a voltage greater than that of the supply voltage V1. The device20is switched into the low resistance state, and the device30is switched into the high resistance state. As a result, a current can flow from the supply voltage V3to the device10. During the “read 1” operation, the device10is turned off, the device20is at the low resistance state, and the device30is at the high resistance state. As a result, a current can flow from the supply voltage V3to the logic output node Y. FIG.5illustrates a schematic view of a circuit diagram of a logic gate3, in accordance with some embodiments of the present disclosure. In some embodiments, the circuit2ashown inFIG.4can be utilized as a logic gate. The logical operations of the logic gate3can follow the truth table (Table 1) shown below. The circuit2acan use the signal received from the input data terminal “D” of the logic gate3, and use the signal received from the set terminal “S” of the logic gate3. Further, “Q” is defined as logical “0” when the device20is at the high resistance state, and the device30is at the low resistance state. “Q” is defined as logical “1” when the device20is at the low resistance state, and the device30is at the high resistance state. The signal outputted by the output node “Y” can be obtained in accordance with the equation: Y=S×D+Q. TABLE 1SDQY00000011010001111000101011011111 In some embodiments, a logical state of Y can be determined by the truth table and a combination of logical states of S, D, and Q. For example, when the logical states of S, D, and Q are at a logical “1”, a logical “0” and a logical “1” respectively, according to the truth table, Y is at a logical state “0”. in some embodiments, the twin bit RRAM resistor device can also be applicable to a one-time programmable (OTP) device. For example, the conductive features172-2and the conductive feature172-3are electrically coupled to SID features154-2and154-3, respectively. The gates130-2and130-3can be electrically coupled to word lines, the S/D features152-2and152-3can be electrically coupled to bit lines. The node between the devices20and30can be electrically coupled to a source line. The gates130-2and130-3can perform a set and a reset operations, and further perform the read of selected operation. FIG.6illustrates a schematic view of a layout of a semiconductor device1b, in accordance with some embodiments of the present disclosure. The semiconductor device1bcan be similar to the semiconductor device1a, except that the semiconductor device1bcan further include devices40,50, and60. The device40can be the same as or similar to the device10. The device50can include, but is not limited to, a RRAM resistor. In some embodiments, the device50can include a resistor structure including a conductive feature172-5, a resistive material layer174-5, and a conductive via180-6. The conductive feature172-5can serve as a portion of the bottom electrode of the RRAM resistor, and the conductive via180-6can serve as a portion of the top electrode of the RRAM resistor. The device60can include, but is not limited to, a RRAM resistor. In some embodiments, the device60can include a resistor structure including the conductive feature172-6, the resistive material layer174-6, and the conductive via180-6. The conductive feature172-6can serve as a portion of the bottom electrode of the RRAM resistor, and the conductive via180-6can serve as a portion of the top electrode of the IMAM resistor. In some embodiments, the conductive via180-6is electrically coupled to the device40. In some embodiments, the conductive via180-6can serve as a common electrode shared by the devices50and60. In some embodiments, the devices50and the60can collaboratively define a twin bit RRAM resistor device. The conductive via180-3can be electrically coupled to the conductive via180-6through a conductive feature190-3. In some embodiments, the conductive feature190-3can be located at the second horizontal level. In some embodiments, the conductive feature190-3can be in contact with the conductive feature190-2and electrically connected to the device10. In some embodiments, the devices20,30,50, and60can be aligned to each other along the X direction. In some embodiments, conductive features172-2,172-3,172-5, and172-6can be aligned to each other along the X direction. The conductive feature172-2and the conductive via180-3can be spaced apart by a distance D1, The conductive feature172-3and the conductive via180-3can be spaced apart by a distance D2. The conductive feature172-5and the conductive via180-6can be spaced apart by a distance D3. The conductive feature172-6and the conductive via180-6can be spaced apart by a distance D4. In some embodiments, D2 can be different from D1. In some embodiments, D2 can be greater than D1. In some embodiments, D4 can be different from D3. In some embodiments, D4 can be greater than D3. In some embodiments, a sum of the D1 and D4 is substantially equal to that of the D2 and D3. FIG.7illustrates a schematic view of a circuit2bof the semiconductor device1bshown inFIG.6, in accordance with some embodiments of the present disclosure. In some embodiments, the device40can have terminals T4, T5, and 16. The terminal T4 can be electrically coupled to a supply voltage V4and can serve as an input data terminal. The terminal T5 can be electrically coupled to a supply voltage V5and can serve as a set terminal. The terminal T6 can be electrically coupled to the devices50and60. In some embodiments, the device20can be electrically coupled to supply voltage V3, the device30can be electrically coupled to supply voltage V6, the device50can be electrically coupled to ground, and the device60can be electrically coupled to ground. The circuit2bcan control a logic output node Y. As shown inFIG.6, when the formation of the conductive via180-3has a misalignment, D1 will be different from D2, causing the resistance of the devices20and30to be different/mismatched. This issue can be levitated by having the devices50and60. In this embodiment, the circuit2bincludes the two twin bit RRAM resistor devices aligned to each other. In some embodiments, when the conductive via180-3and conductive via180-6have misalignments, the conductive via180-3and conductive via180-6may tend to shift in the same direction, causing D3 to have a shift the same as that of D1, and causing134to have a shift the same as that of D2. As shown inFIG.7, when the resistances of the devices20becomes relatively smaller and the device30becomes relatively greater due to misalignment, the resistances of the devices50and60can become relatively smaller and relatively greater correspondingly. The devices20and50that have a relatively smaller resistance can be configured to be a twin bit RRAM resistor device. The devices30and60that have a relatively greater resistance can be configured to be a twin bit RRAM resistor device. Therefore, the resistance matching of all RRAM resistors of the circuit2bcan be improved, even if the locations of the conductive vias180-3and180-6are shifted. FIG.8is a flow chart illustrating a method300for manufacturing a semiconductor device, in accordance with various aspects of the present disclosure. The method300begins with operation302in which a first active region, a second active region and a third active region are formed on a substrate. For example, the operation302can include forming the active regions120-1,120-2, and120-3as shown inFIGS.1-3. The method300continues with operation304in which a first gate, a second gate, and a third gate are formed on the first active region, the second active region and the third active region, respectively. For example, the operation304can include forming the gate130-1, the gate130-2, and the gate130-3as shown inFIGS.1-3. The method300continues with operation306in which a first SID feature, a second S/D feature, and a third S/D feature are formed beside the first gate, the second gate and the third gate, respectively. For example, the operation306can include forming the S/D feature152-1, the S/D feature154-1, the S/D feature152-2, the S/D feature154-2, the S/D feature152-3, and the S/D feature154-3as shown inFIGS.1-3. The method300continues with operation308in which a first conductive feature, a second conductive feature, and a third conductive feature are formed. The first conductive feature, the second conductive feature, and the third conductive feature are located at a first horizontal level and electrically coupled to the first S/D feature, the second S/D feature, and the third S/D feature, respectively. For example, the operation308can include forming the conductive features170-2,172-2, and172-3as shown inFIGS.1-3. The method300continues with operation310in which a first conductive via and a second conductive via are formed. The first conductive via is located on the first conductive feature. The second conductive via is located between the second conductive feature and the third conductive feature. For example, the operation310can include forming the conductive via180-2and the conductive via180-3as shown inFIGS.1-3. The method300continues with operation312in which a fourth conductive feature is formed at a second horizontal level and electrically connecting the first conductive via and the second conductive via. For example, the operation312can include forming the conductive feature190-2as shown inFIGS.1-3. The method300is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method300, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor. Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first device, a second device, and a third device. The first device includes a first conductive feature at a first horizontal level, a second conductive feature at a second horizontal level different from the first horizontal level and electrically coupled to the first conductive feature, and an electrode protrudes from the second conductive feature. The second device includes a third conductive feature at the first horizontal level. The third device includes a fourth conductive feature at the first horizontal level. The electrode is located between the third conductive feature and the fourth conductive feature. Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a first source/drain feature beside the first gate structure and a second SID feature beside the second gate structure; forming a first conductive feature at a first horizontal level and electrically coupled to the first S/D feature and a second conductive feature at the first horizontal level and electrically coupled to the second S/D feature; forming a first conductive via on the first conductive feature; forming a second conductive via beside the second conductive feature and a resistive material layer around the second conductive via; and forming a third conductive feature at a second horizontal level different from the first horizontal level and electrically connecting the first conductive via and the second conductive via, wherein the second conductive via and the second conductive feature collaboratively define a first resistive random access memory (RRAM) resistor. The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 38,851 |
11943937 | DETAILED DESCRIPTION OF THE INVENTION Before the present MOSFETS, transistors, memory select transistors, memory elements, memory cells and arrays are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims. Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited. It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the region” includes reference to one or more regions and equivalents thereof known to those skilled in the art, and so forth. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. The dates of publication provided may be different from the actual publication dates which may need to be independently confirmed. FIG.1illustrates a prior art metal-oxide semiconductor field effect transistor (MOSFET)1in which both n-channel and p-channel MOSFETs are fabricated on the same chip having a substrate12. A BJT is inherently formed during manufacture of the MOSFET. The intrinsic BJT is connected in parallel to the MOSFET, where emitter, base, and collector of the intrinsic BJT are formed from the source16, channel24, and drain18of the MOSFET1, respectively. The MOSFET1further includes a gate60, gate insulator62and insulators26. The intrinsic BJT of MOSFET1rarely contributes to the drain current. Currently, the manufacturing process and operation scheme for conventional MOSFETs are designed to nullify the effect of the inherent BJT. Referring toFIG.2A, a semiconductor device50according to an embodiment of the present invention is shown. Semiconductor device50may function as a memory select transistor with increased on-state drain current, but with no change in the off-state drain current, depending on the bias applied to the semiconductor device50. Semiconductor device50includes a substrate12of a first conductivity type such as p-type, for example. Substrate12is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, and/or other semiconductor materials. In some embodiments of the invention, substrate12can be the bulk material of the semiconductor wafer. In another embodiment shown inFIG.3, substrate12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well29of the second conductivity type, such as n-type. The well29in turn can be another well inside substrate12B of the first conductivity type (for example, p-type). In another embodiment, well12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal (not shown inFIG.3), which is connected to12A. To simplify the description, the substrate12will usually be drawn as the semiconductor bulk material as it is inFIG.2A. Semiconductor device50also includes a buried layer22of a second conductivity type, such as n-type, for example; a body24of the first conductivity type, such as p-type, for example; and source/drain regions16and18of the second conductivity type, such as n-type, for example. Buried layer22may be formed by an ion implantation process on the material of substrate12. Alternatively, buried layer22can be grown epitaxially on top of substrate12or formed through a solid-state diffusion process. The body24of the first conductivity type is bounded on top by source16, drain18, and insulating layer62(or by surface14in general), on the sides by insulating layers26, and on the bottom by buried layer22. Body24may be the portion of the original substrate12above buried layer22if buried layer22is implanted. Alternatively, body24may be epitaxially grown on top of the buried layer22through a solid-state diffusion process. A source16and drain18having a second conductivity type, such as n-type, for example, are provided in body24, so as to bound a portion of the top of the body24in a manner discussed above, and are exposed at surface14. Source16and drain18may be formed by an implantation process on the material making up substrate12, according to any implantation process known and typically used in the art. Alternatively, a solid-state diffusion or a selective epitaxial growth process could be used to form source16and drain18. A gate60is positioned in between the source16and the drain18, above body24. The gate60is insulated from the body24by an insulating layer62. Insulating layer62may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate60may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. Insulating layers26(like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers26insulate semiconductor device50from adjacent semiconductor devices50. The bottom of insulating layer26may reside inside the buried layer22allowing buried layer22to be continuous as shown inFIGS.2A and3. Alternatively, the bottom of insulating layer26may reside below the buried layer22(seeFIG.2B). This requires a shallower insulating layer26B (where the bottom of insulating layer26B resides inside the buried layer22), which insulates the body24, but allows the buried layer22to be continuous in the perpendicular direction of the cross-sectional view shown inFIG.2AandFIG.3. For simplicity, only semiconductor device50with continuous buried layer22in all directions will be shown from hereon. FIG.4illustrates a cross-sectional illustration of a semiconductor device50A that includes semiconductor50shown inFIG.2Awith buried layer22connected to buried layer tap36according to an embodiment of the present invention. The buried layer tap36having a second conductivity type, such as n-type, for example, is connected to the buried layer22through the buried tap body44having a second conductivity type, such as n-type. The buried tap body44may be formed by an implantation process following the same process step of the well formation of complementary type of MOS transistor such as p-channel device. The buried tap36may be formed by an implantation process or selective epitaxial growth process following the same process step of the source and drain formation of complementary type of MOS transistor such as p-channel device. For example, if buried tap body44and buried tap36are formed by an ion implantation process, the implant energy (which determines the depth of the implant) for buried tap body44is higher than the implant energy for buried layer tap36. FIG.5Aillustrates a schematic three-dimensional view of semiconductor device50F. Fin type semiconductor device50F includes substrate12of a first conductivity type, such as p-type for example, and a buried layer22of a second conductivity type, such as n-type, for example; a fin type body24of the first conductivity type, such as p-type, for example; and source/drain regions16and18of the second conductivity type, such as n-type, for example. Buried layer22may be formed by an ion implantation process on the material of substrate12. Alternatively, buried layer22can be grown epitaxially on top of substrate12or formed through a solid-state diffusion process. FIGS.5B-5Dillustrate a top view and cross-sectional views of semiconductor device50F comprising a fin structure52as shown inFIG.5A. Fin structure52extends perpendicularly from the substrate12to form a three-dimensional structure and comprises body24having a first conductivity type with buried layer region22having a second conductivity type and located below the body24. Substrate12is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, and/or other semiconductor materials. In some embodiments of the invention, substrate12can be the bulk material of the semiconductor wafer. The fin type body24of the first conductivity type is bounded on top by source16, drain18, and insulating layer62, on the sides by insulating layer26, and on the bottom by buried layer22. Fin type body24may be the portion of the original substrate12above buried layer22if buried layer22is implanted. Alternatively, fin type body24may be epitaxially grown on top of the buried layer22through a solid-state diffusion process. A source16and drain18having a second conductivity type, such as n-type, for example, are provided in body24, so as to bound a portion of the top of the fin type body24in a manner discussed above. Source16and drain18may be formed by an implantation process on the material making up substrate12, according to any implantation process known and typically used in the art. Alternatively, a solid-state diffusion or a selective epitaxial growth process could be used to form source16and drain18. A gate60is positioned in between the source16and the drain18, above body24. The gate60is insulated from the fin type body24by an insulating layer62. Insulating layer62may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate60may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. Insulating layers26(like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers26insulate semiconductor device50F from adjacent fin type MOS devices50F. The bottom of insulating layer26may reside inside the buried layer22allowing buried layer22to be continuous as shown inFIGS.5A-5D. Alternatively, the bottom of insulating layer26may reside below the buried layer22(seeFIG.2Bfor illustration of insulating layers26and26B having different depths). This requires a shallower insulating layer26B, which insulates the body24, but allows the buried layer22to be continuous in direction of the I-I′ cross-sectional view shown inFIG.5C. For simplicity, only semiconductor device50F with continuous buried layer22in all directions will be shown from hereon. FIGS.6A and6Billustrate top view and cross-sectional view of a fin type semiconductor device450F that includes fin type semiconductor device50F shown inFIGS.5A-5D, but with buried layer22connected to buried layer tap36according to an embodiment of the present invention. The buried layer tap36having a second conductivity type, such as n-type, for example, is connected to the buried layer22through the buried tap body44having a second conductivity type, such as n-type. The buried tap body44may be formed by an implantation process following the same process step of the well formation of complementary fin type of MOS transistor such as p-channel device. The buried tap36may be formed by an implantation process or selective epitaxial growth process following the same process step of the source and drain formation of complementary type of MOS transistor such as p-channel device. In one embodiment, the bottom of the gate60is extended down to align to the junction between the body24and the buried layer22(seeFIG.6C). This increases the capacitive coupling efficiency between the gate60voltage and the body24potential. FIG.6Dillustrates a cross-sectional view of a fin type semiconductor device50F according to another embodiment of the present invention. In order to increase the capacitive coupling efficiency between the gate60voltage and the fin type body24potential, the fin type body24is tapered. The gate60voltage controllability to the junction potential between the fin type body24and the buried layer22may be increased due to the wider fin width near the junction and the angle between the gate60and the junction angle23between the fin type body24and the buried layer22becomes less than 90°. It is noted that this type of semiconductor50F as shown inFIG.6Dcould also be combined with buried layer22connected to buried layer tap36to form a device450F having a tapered fin type body24. The transient time for the transistor having increased on-state drain current but with no change in the off-state drain, from the on-state (with increased drain current) to the off-state (with low off-state drain current), may be improved by limiting excess majority carrier lifetime. During the on-state, the semiconductor device50(or50A,50F,150,350,450,450F,550,602,650or1750) requires that the body24has a large lifetime for body region excess majority carriers to boost the drive current. When the electrons are injected from the source16(emitter) to the body24(base), most of these electrons are swept in to the buried layer22(collector) with some recombining with the base region majority carriers. A small amount of recombination may occur, but a continuous supply of body24region majority-carriers is sustained to boost the on-state drive current. Therefore, the transient time for the transistor50(or50A,50F,150.350,450,450F,550,602,650or1750and any other embodiments of MOS device described as embodiments of the invention herein) from the on-state to the off-state may be improved by providing a recombination region made by several means that will be described below. However, if the population of these majority carriers is too limited, the operation of vertical BJT30a(seeFIG.8) is inhibited and subsequently no current boosting will occur. All of the described methods will only alter the majority carrier lifetime while the conductivity type and channel mobility may remain substantially unchanged. FIG.7Ais a schematic, cross-sectional illustration of a semiconductor device50with charge trap layer27such as silicon nitride lined in the trench isolation region26according to an embodiment of the present invention. Unless noted otherwise features that are described here with regard to device50can also be applied to devices50A,50F,150,350,450,450F,550,602,650,1750and any other embodiments of MOS device described as embodiments of the invention herein. The charge trap layer27is either directly contacted to the sidewall of the body24region or indirectly contacted through the very thin interfacial oxide in between (not shown). The charge trap layer27such as silicon nitride contains substantial number of charge trap centers that may absorb the excess majority carrier. FIG.7Bis a schematic, cross-sectional illustration of a semiconductor device50with metal silicided junction partially contacting to body24region according to an embodiment of the present invention. The metal silicide regions16A and18A may contact the body24region near the sides of the source16and drain18region, respectively. Alternatively, the metal silicide16A is formed only on the source side16, with no metal silicide region18A (not shown). The Schottky junction formed by metal silicide region16A and the body24may facilitate the majority carrier recombination. FIG.7Cis a schematic, cross-sectional illustration of a semiconductor device50with junction with energy band offset compared to body region according to an embodiment of the present invention. The energy band offset regions16B and18B may contact the body24region near the bottoms of the source16and drain18regions. Alternatively, the energy band offset region16B may be formed only at the source16side, with no energy band offset region18B being formed (not shown). For an n-type channel MOS, the valence band offset material is embedded in the source16and the drain18for the excess majority carrier (holes) to be preferentially evacuated through the source16. For a p-type channel MOS, the conduction band offset material is embedded in the source16and the drain18for the excess majority carrier (electrons) to be preferentially evacuated through the source16. FIG.7Dis a schematic, cross-sectional illustration of a semiconductor device50with recombination centers17disposed near the junction between source16and body24and, optionally, between drain18and body24according to an embodiment of the present invention. One general approach is by doping with deep level impurities, such as gold or platinum. Another general approach is to introduce crystallinity damage through ion implantation through such as Si, Ge, or Ar implantation. Another general approach is by using radiation damage to produce defects in the silicon crystal lattice structure. The charge recombination regions explained inFIG.7AtoFIG.7Dcan be symmetrically formed at both the source16and the drain18for process convenience. However, these charge recombination regions may also be formed only at the source side region in order to inhibit drive current degradation and junction leakage occurring near the drain side. The operation of the semiconductor device50will be described using an n-channel device as an example. The operation of a p-channel device follows the same principle, but the polarity of the applied voltages will be opposite that of the n-channel device (using the source voltage as the reference). Likewise, the operation of semiconductor devices50A,50F,150,350,450,450F,550,602,650and1750operate like that described with regard to p-channel or n-channel devices50. FIG.8illustrates an equivalent circuit representation of semiconductor device50. Inherent in semiconductor device50are metal-oxide-semiconductor (MOS) transistor20, formed by source16, gate60, drain18, and body24, and vertical BJTs30aand30b, formed by buried layer22, body24, and source16or drain18, respectively. Also inherent in semiconductor device50is lateral BJT30c, formed by source16, body24, and drain18. FIG.9schematically illustrates an equivalent capacitor circuit representation of semiconductor device50shown inFIGS.1-8. It is noted that this equivalent capacitor circuit would also represent other embodiments of devices described herein according to the present invention, as would be readily apparent to those of ordinary skill in the art after viewingFIG.9and reading its description. The body24potential (VB) is capacitively coupled with gate oxide capacitance, source side junction capacitance, drain side junction capacitance, and buried layer junction capacitance. Therefore, the body24potential (VB) can be perturbed by the gate60voltage (VG), source16voltage (VS), drain18voltage (VD), and buried layer22voltage (VBNLfor buried n-layer and VBPLfor buried p-layer voltage). FIG.10schematically illustrates drain18current versus gate60voltage characteristics for various buried layer22voltage. In this plot, it is important to note that the applied drain18voltage is assumed to be a voltage that does not exceed that which would cause an impact ionization process near the junction between the body24and the drain18. If the voltage applied to the drain region18is sufficiently high to cause an impact ionization process near the junction between the body24and the drain18, an increase in the current flow (from the drain region18to the source region16) may also be observed, as described for example in “Hysteresis I-V Effects in Short-Channel Silicon MOSFETs”, Boudou, A. and Doyle, B. S., IEEE Electron Device Letters, vol. EDL-8, no. 7, July 1987, or the kink effect observed in the silicon-on-insulator (SOI) wafer as described for example in “Single-Transistor Latch in SOI MOSFETs”, Chen, C.-E. D., et al, IEEE Electron Device Letters, vol. 9, no. 12, December 1988, which are hereby incorporated herein, in their entireties, by reference thereto. Because the voltage applied to the drain region18to cause an impact ionization process is typically higher than the operating voltage of the transistor, this may result in degradation of the transistor performance and reliability over time. If the buried layer22is biased at low voltage such as zero volts, the drain18current versus the gate60voltage characteristic100ashows ordinary MOSFET characteristics. At high voltage VBNL2applied to the buried layer22, the semiconductor device50will function as a memory device having at least two stable states. If the constant voltage applied to the buried layer22is sufficiently high that if body24potential is greater than the potential required to turn-on vertical BJT30a, regardless of the gate60and the drain18voltages, electron hole pairs are generated near a junction between the body24and the buried layer22even at the gate voltage of zero. The resulting hot electrons flow into the buried layer22while the resulting hot holes will subsequently flow into the body region24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of the bipolar transistors30aor30band M is the impact ionization coefficient—the amount of holes injected into the body region24compensates for the charge lost due to p-n junction forward bias current between the body region24and the source line region16or bit line region18and due to holes recombination. This process maintains the majority charge (i.e. holes) stored in the body region24which will keep the n-p-n bipolar transistors30aand30bon for as long as a positive bias is applied to the buried well region22. The state where the body potential is sufficiently high and is maintained by the hole current generated at the junction of body24and buried layer22is referred to as the latch state of the semiconductor device50. As shown in the drain18current versus gate60voltage characteristics for high buried layer22voltage100cofFIG.10, the lateral BJT30ccurrent flows even at the zero gate voltage, when the semiconductor device50is in latch-state. If the buried layer22is biased at a positive voltage (but less positive than the positive voltage which results in the drain18current versus gate60voltage characteristics100c), gate60and drain18voltages can elevate body24potential to be greater than a potential required to turn-on vertical BJT30aby capacitive coupling. When the vertical BJT30ais turned on, electrons from source18(emitter) flow to the buried layer22(collector) of the vertical BJT30a. The constant voltage applied to the buried layer22is enough to cause impact ionization process, and electron hole pairs are generated near a junction between the body24and the buried layer22. The generated electrons are collected by the positively biased buried layer22, while the generated holes flow into the body24. These generated holes act as a base current of the lateral BJT30c, which turns on the lateral BJT30c. As a result, the on-state drain current becomes the sum of MOS transistor20current and lateral BJT30ccurrent. As shown in the drain18current versus gate60voltage characteristics for high buried layer22voltage100bofFIG.10, the on-state drain current is boosted compared to the on-state drain current with the buried layer22biased at zero. If desired, the on-state drain current can be further boosted by increasing the voltage applied to the buried layer22. However, the off-state drain current can be the same as the off-state drain current with the buried layer22biased at zero, because the body24potential at the gate voltage of zero becomes smaller than the threshold voltage for turning on the vertical BJT30c. Therefore, at a positive bias VBNL1(less positive than the positive voltage VBNL2which results in a latch state at zero gate voltage), semiconductor device50functions as a boosted transistor with increased on-state drain current, but with no change in the off-state drain current. Also notice that the drain18current versus gate60voltage characteristics of100bexhibits a steep slope (<60 mV/dec) when at the gate60voltage when the lateral BJT30cis first activated. When the constant voltage applied to the buried layer22is less than a voltage to cause an impact ionization process near the junction between the buried layer22and the body24, no lateral BJT30caction takes place at any body24potentials. For a constant voltage applied to the buried layer22that is greater than or equal to that required to cause an impact ionization process,FIG.11represents the drain18voltage and gate60voltage that start to form body24potential to turn on the lateral BJT30c. In other words, the lines (102a,102b, and102c) indicate the minimum gate60and drain18voltages to activate the lateral BJT30cat a given buried layer22voltage. The voltages at upper and right region of the line causes the lateral BJT30cto be turned on. A line may locate above power supply voltage Vdd for a low voltage applied to the buried layer22(for example, line102a). In this case, no lateral BJT would be activated within the normal operation voltage ranging from 0V to Vdd. For a very high voltage applied to the buried layer22, a line may locate inside Vdd (for example, line102c). In this case, the lateral BJT30cis activated even at gate60voltage of zero. For some high voltage applied to the buried layer22, a line (for example, line102b) may intersect to the Vdd lines (dotted lines). In this case, the lateral BJT30cis activated even at gate60voltage of Vdd, but the lateral BJT30ccan be turned off at gate60voltage of zero. Therefore, various operations can be attained according to the desired characteristics. Particularly, when the semiconductor device50is biased to exhibit the drain18current versus gate60voltage characteristics showing a boosted on-state drain current as shown in100bofFIG.10, the semiconductor device50is hereinafter referred as boosted transistor50. Likewise semiconductor devices50A,50F,150,350,450,450F,550,602,650and1750having a boosted on-state drain current can be referred to as boosted transistors50A,50F,150,350,450,450F,550,602,650and1750. Several operations can be performed by semiconductor device50having increased on-state drain current, but with no change in the off-state drain current. When a supply voltage (Vdd) such as 1.0 volt is applied to the gate60and the drain18, depending on the voltage applied to the buried layer22, both MOS transistor20and lateral BJT30ccan be turned on, which results in higher on-state drain current than the conventional MOSFET, or MOS transistor20can be turned on while the lateral BJT30cis turned off, which results in the same on-state drain current compared to the conventional MOSFET. When zero volts is applied to the gate60and Vdd such as 1.0 volt is applied to the drain18, MOS transistor20can be turned off while the lateral BJT30cis turned on, which results in a high off-state drain leakage current, or both MOS transistor20and lateral BJT30ccan be turned off, which results in lowest off-state drain current. According to an embodiment of the present invention, aforementioned various operational states can be determined by different levels of voltage applied to the buried layer22. The switching between on and off of MOS transistor20is associated with a voltage applied to gate60. The switching between on and off of lateral BJT30cis associated with voltages applied to gate60and buried layer22. In one particular non-limiting embodiment, VBNL2is about +2.0 volts, VBNL1is about +1.5 volts, and low VBNLis a positive voltage lower than VBNL1. However, these voltage levels may vary, while maintaining the relationship that VBNL2is more positive than VBNL1. These voltage levels may depend for example on the doping profile and the depth of the buried layer region22. FIGS.12A and12Billustrate a schematic cross-sectional view of a semiconductor memory device1750and an equivalent circuit, respectively, according to another embodiment of the present invention. The semiconductor memory device1750is a volatile or non-volatile memory cell comprising a boosted transistor50and a two terminal memory element41. The semiconductor memory device1750includes five terminals: word line (WL) terminal70, source line (SL) terminal72, bit line (BL) terminal74, buried layer (BW) terminal76, and substrate terminal (SUB)78. WL terminal70is connected to gate60. SL terminal72is connected to the source16and BL terminal74is connected to drain18. BW terminal76is connected to buried layer22. Substrate terminal78is connected to substrate12below buried layer22. For simplicity, the substrate terminal is not drawn inFIG.12B. The memory element41has two terminals where one terminal is connected to the drain18of the boosted transistor50and another terminal is connected to BL terminal74. The memory element41is shown as a variable resistor which resistance value is controlled by previously applied bias condition, and may be formed from resistive switching memory (known as resistive random access memory (RRAM or ReRAM), memristor, conductive bridge memory (CBRAM), phase change memory (also known as PCM, PCRAM), chalcogenide memory (CRAM)), magnetoresistive memory (MRAM). The memory element41material may take the form of metal-insulator-metal structure, in which transition metal oxide or perovskite metal oxide is used in conjunction with any reasonably good conductors, for example as described in “Overview of Phase-Change Chalcogenide Non-volatile Memory Technology”, S. Hudgens and B. Johnson, MRS Bulletin, vol. 29, issue 11, November 2004, p. 829-832, “Phase Change Memory”, Wong, H.-S. P. et al., Proceedings of the IEEE, vol. 98, no. 12, December 2010, pp. 2201-2227, “Nanoionics-based resistive switching memories”, R. Waser and M. Aono, Nature Materials, vol. 6, November 2007, pp. 833-840, and “Metal-Oxide RRAM”, Wong, H.-S. P. et al., Proceedings of the IEEE, vol. 100, no. 6, June 2012, pp. 1951-1970, all of which are hereby incorporated herein, in their entireties, by reference thereto. The state of the semiconductor memory device1750is determined by the resistivity of the memory element41. The memory element41is written (from a low resistivity state to a high resistivity state and vice versa) by flowing an electrical current through the memory element41. In the case of phase change materials, this involves the change of the crystallinity of the chalcogenide materials from crystalline state to amorphous state, while in metal oxide materials, this typically involves the annihilation of conductive filaments. Alternatively, the memory element41material may take the form of magnetic storage elements formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulator layer, known as magnetic tunnel junction (MTJ) as descripted in “A 4-Mb toggle MRAM based on a novel bit and switching method”, Engel, B. N., Akerman, J., Butcher, B., Dave, R. W., DeHerrera, M., Durlam, M., Grynkewich, G., Janesky, J., Pietambaram, S. V., Rizzo, N. D. and Slaughter, J. M., 2005 IEEE Transactions on Magnetics, 41(1), pp. 132-136, “Progress and outlook for MRAM technology, Tehrani, S., Slaughter, J. M., Chen, E., Durlam, M., Shi, J. and DeHerren, M., 1999 Progress and outlook for MRAM technology. IEEE Transactions on Magnetics, 35(5), pp. 2814-2819, “Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects”, Huai, Y., 2008 AAPPS bulletin, 18(6), pp. 33-40, “Recent developments in magnetic tunnel junction MRAM”, Tehrani, S., Engel, B., Slaughter, J. M., Chen, E., DeHerrera, M., Durlam, M., Naji, P., Whig, R., Janesky, J. and Calder, J., 2000. IEEE Transactions on magnetics, 36(5), pp. 2752-2757, “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement”, Dong, X., Wu, X., Sun, G., Xie, Y., Li, H. and Chen, Y., Design Automation Conference 2008, 2008 45th ACM/IEEE (pp. 554-559). IEEE, all of which are hereby incorporated herein, in their entireties, by reference thereto. The boosted transistor50is used as a select device for the memory element41. The memory element41may be connected directly on the drain18region of the boosted transistor50. Alternatively, the memory element41may be formed on a number of metal layers interposed by inter-layer-dielectric (ILD) on top of the boosted transistor50. Application of back bias to buried layer22of the boosted transistor50may turn on the vertical bipolar devices formed by source region16or drain region18, body region24, and buried layer22, and enhance the current flow through the semiconductor device50. As a result, the write operations of the boosted transistor1750may be enhanced. The increased efficiency of the write operations may be used to increase the operating speed, or to lower the voltage applied for the write operations, reducing the transistor channel width, or reducing the operating power of the semiconductor memory device1750. In one embodiment, if one set of voltage pulses is applied to the memory element41through the boosted transistor50, the resistance of memory element41is increased or the memory element41is written to high resistance state (HRS). If another set of voltage pulses is applied to the memory element41through the boosted transistor50, the resistance of memory element41is decreased or the memory element is written to low resistance state (LRS). The voltage pulses for the writing logic ‘1’ and logic ‘0’ may have opposite polarity. Alternatively, the voltage pulses for the writing logic ‘1’ and logic ‘0’ may have the same polarity but different pulse amplitude or pulse width. The voltage pulse for each writing operation may be optimized by changing pulse amplitude and pulse width. The HRS may range from 50 kilo-ohm to 100 mega-ohm and the LRS may range from 1 ohm to 10 kilo-ohm. The amount of current required to switch the resistance of the memory element41depends on the material, the memory element thickness, and the area of the memory element. Application of back bias to buried layer22of the semiconductor device50enhances the current flow through the boosted transistor50and therefore increases the efficiency of the write operation, thereby relatively reducing the amount of voltage or current that would otherwise be necessary to perform the write operation. In one embodiment, the back bias may be applied during the write operation and then removed after the completion of the write operation. In one embodiment, a memory element41may require a forming process to be performed prior to an initial operation. The forming operation requires a higher voltage or current than that which is used during normal operations for setting the resistance states. It is desirable to reduce the voltage or current necessary for the forming process to as low a level as possible. Application of back bias to buried layer22of the semiconductor device50enhances the current flow through the boosted transistor50and therefore increases the efficiency of the forming process, thereby relatively reducing the amount of voltage or current that would otherwise be necessary to perform the forming operation. In one embodiment, the back bias may be applied during the forming operation and then removed after the completion of the forming operation. FIG.13is a schematic illustration of an array1850comprising a plurality of semiconductor memory devices1750. The unit cell1750of the memory array utilizes a 1-boosted transistor50and 1-memory element41configuration (1T1M). The memory array1850includes columns of bit lines BL1-BLn, columns of source lines SL1-SLn, and rows of word lines WL1-WLn. Additionally, the memory array1850may include rows of buried well layer lines BW1-BWn, or the buried well layer may also be common for all of the memory array1850or for a sub-array of the array1850. In another embodiment, the SL1-SLn may also be running in the same direction of WL1-WLn. It should be understood that the memory array is shown as 3×3 sub-array chain, but may be sized as desired such as 128×128 sub-array, or other configuration. FIG.14is a schematic illustration of a semiconductor memory device array1950comprising 1-boosted transistor50and n-memory elements41(1TnM, wherein “n” is a positive integer, typically greater than 1) configuration according to an embodiment of the present invention. Referring toFIG.14, the memory array1950comprises a plurality of memory elements41, each associated with one of word line select (WLS) transistor and one of bit line select (BLS) transistor. The memory array includes columns of bit lines BL1-BLn supplied through BLS1-BLSn and rows of word lines WL1-WLn supplied through WLS1-WLSn. The boosted transistor50herein is assigned for WLS transistor and BLS transistor. The WL voltage and BL voltage are supplied to the memory element41by activating WLS and BLS transistors respectively. According to another embodiment of the present invention, only BL voltages are supplied through the boosted BLS transistors50or only WL voltages are supplied through the boosted WLS transistors50(not drawn). FIG.15is a semiconductor memory device array2050comprising three-dimensionally stacked 1-boosted transistor and n-memory element (1TnM) configuration according to an embodiment of the present invention. Referring toFIG.15, the memory array2050comprises a plurality of memory elements41formed in a portion of back-end-of-line (BEOL) layers, each associated with one of word line select transistors (not drawn) and one of bit line select transistors formed in a portion of front-end-of-line (FEOL) layers. The WL voltage and BL voltages are supplied to the memory element41by activating WLS and BLS transistors respectively. At least one of WLS and BLS transistors are boosted transistor50. The WLS and BLS boosted transistors are included in the substrate (XY plane). FIG.16is a three-dimensionally stacked 1-boosted transistor and n-memory element (1TnM) configuration according to an embodiment of the present invention. Referring toFIG.16, the bit lines BL1, BL2, BL3are horizontally extending in the X-direction and the word line is vertically extending in the Z-direction, where the vertical word line is wrapping around the sidewall of horizontally arranged bit line with memory element therebetween. The vertical word lines are arranged in a grid pattern. The memory elements are formed in regions where the vertical and horizontal lines cross. FIG.17is a three-dimensionally stacked 1-boosted transistor and n-memory element (1TnM) configuration according to an embodiment of the present invention. ReferringFIG.17, the bit lines are horizontally extending in the X-direction and the word line is vertically extending in the Z-direction such as pillar electrode, where the vertical word line is punching through the horizontally arranged bit line with memory element therebetween. The vertical word lines are arranged in a grid pattern. The memory elements are formed in regions where the vertical and horizontal lines cross. FIG.18is a three-dimensionally stacked 1-boosted transistor and n-memory element (1TnM) configuration according to an embodiment of the present invention. ReferringFIG.18, the bit lines are horizontally extending in the X-direction and the word line is also horizontally extending in Y-direction, perpendicular to bit line direction. The memory elements are formed in cross-point regions where the bit lines and word lines cross. Therefore, the cross-point regions are arranged in a grid pattern in XY plane. The cross-points arrangement in XY plane is repeated at least twice along Z-direction. FIG.19is an equivalent circuit representing a semiconductor memory device having two select boosted transistors50,50′ with one memory element41allowing dual-port memory according to an embodiment of the present invention. In some memory usage, the read and write operation to the same column can be accomplished at the same time via different ports. FIG.20illustrates a semiconductor device150according to another embodiment of the present invention. Similar to semiconductor device50, semiconductor device150may operate as a boosted transistor or a memory cell. The buried layer region22of semiconductor device150is located below the insulating region26. The floating body region24of semiconductor device150is also bounded by adjacent well region20of a second conductivity type, such as n-type, for example. The floating body region24of the semiconductor device150may be bounded by adjacent well region20of the second conductivity type by four sides of the floating body region24or two sides along channel length direction or two sides along channel width direction of the floating body region24. The operation of boosted transistor150is similar to that of boosted transistor50. The back bias applied to the buried layer region22(through BW terminal76) may be higher for boosted transistor150than that of boosted transistor as the base region of the vertical bipolar device formed by source/drain regions16and18, floating body region24, and buried layer22is wider for boosted transistor150than that of boosted transistor50. FIGS.21A-21Billustrate semiconductor device350(with illustrations cut along the gate length and the gate width, respectively) according to another embodiment of the present invention. Similar to semiconductor device50, semiconductor device350may operate as a boosted transistor or a memory cell. The body region24of semiconductor device350is also bounded by well region20of a second conductivity type, such as n-type, for example. The well region20may be formed at only two sides along gate width direction. However, the body region24of semiconductor device350is not physically bounded at the bottom by a buried layer region. As illustrated inFIG.21, in the absence of voltage bias applied to the semiconductor device350, the body region24of semiconductor device350is electrically connected to the substrate region12. FIGS.22A-22Billustrate semiconductor device350(with illustrations cut along the gate length and the gate width, respectively) according to another embodiment of the present invention. The body region24of semiconductor device350is also bounded by well region20of a second conductivity type, such as n-type, for example. The well region20may be formed at only two sides along gate width direction. However, the body region24of semiconductor device350is not physically bounded at the bottom by a buried layer region. As illustrated inFIGS.22A-22B, in the absence of voltage bias applied to the semiconductor device350, the body region24of semiconductor device350is electrically connected to the substrate region12. As illustrated inFIGS.23A-23B and24A-24B, upon application of a back bias to the well region20(through terminal76), a depletion region23(enclosed in dashed lines) is formed in the junction of the body region24and the well region20. It should be understood that the shape of depletion region boundary shown inFIGS.23-23B and24A-24Bare for illustration purpose only. Rather, it should be understood that it conceptually illustrates the depletion boundaries from left and right well regions20merge and result in the body24to be floating. Depletion region23may extend into the body region24due to the reverse biased p-n junctions, and form an isolation for the body region24. Therefore, the body region24of the boosted transistor350is now floating and is now isolated from that of adjacent boosted transistors350. The body region24now forms a potential well which can store charge. FIG.25illustrates a top plane view of an array2150of memory cells550according to another embodiment of the present invention.FIG.26illustrates a cross-section view of the array2150ofFIG.25cut along line A-A′.FIG.27illustrates a cross-section view of the array2150cut along line B-B′ inFIG.25.FIGS.25to27illustrate a 3×3 memory array2150, but the memory array size is not limited to 3×3. Semiconductor memory cell550includes a substrate12of a first conductivity type such as p-type, for example. Substrate12is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, and/or other semiconductor materials. Memory cell550also includes a buried layer22of a second conductivity type, such as n-type, for example; a body24of the first conductivity type, such as p-type, for example; and source/drain regions16and18of the first or the second conductivity type. Alternatively, memory cell550may optionally not include source/drain region16and18, in which as the regions16and18that would otherwise make up the source and drain regions are made of the same material, conductivity type and conductivity as the body24and therefore the source and drain regions16and18are left out of the body24and do not exist in such an embodiment. Buried layer22may be formed by an ion implantation process on the material of substrate12with bit line implant mask4. The bitline implant mask4may be a non-critical mask that opens only the memory cell550region. Alternatively, buried layer22can be grown epitaxially on top of substrate12or formed through a solid-state diffusion process. The body24of the first conductivity type is bounded on top by source16, drain18, and insulating layer62(or by surface14in general), on the sides by insulating layers26along A-A′ direction, on the side by insulating layer28along B-B′ direction, and on the bottom by buried layer22. Body24may be the portion of the original substrate12above buried layer22if buried layer22is implanted. Alternatively, body24may be epitaxially grown on top of the buried layer22through a solid-state diffusion process. The body24may also be referred to as a fin in a FinFET technology. A source16and drain18having a first or second conductivity type, such as n-type or p-type, for example, are provided in body24, so as to bound a portion of the top of the body24in a manner discussed above, and is exposed at surface14. If desired, the source16and drain18are not ion-implantation processed, so that they are left with the same material and conductivity type as that of the body24. If desired, the source16and drain18may have, but not be limited to, the same conductivity type with the body24. Source16and drain18may be formed by an implantation process on the material making up substrate12, according to any implantation process known and typically used in the art. Alternatively, a solid-state diffusion or a selective epitaxial growth process could be used to form source16and drain18. A gate60is positioned in between the source16and the drain18, above body24. The gate60is insulated from the body24by an insulating layer62. Insulating layer62may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate60may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. The gates60may be patterned continuous along vertical direction (B-B′ direction) as shown inFIGS.25and27. Insulating layers26(like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layer26may be patterned by single diffusion break layer8, given as a foundry's baseline process. Insulating layers26insulate memory cell550from adjacent memory cells550along the A-A′ direction. The bottom of insulating layer26may reside inside the buried layer22allowing buried layer22to be continuous along horizontal direction (A-A′ direction) as shown inFIG.26. Insulating layer28(like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers28, perpendicular to insulating layer26, insulate memory cell550from adjacent memory cells550along the B-B′ direction. The bottom of insulating layer28may reside below the buried layer22allowing buried layer22to isolate the buried layer22per body24along the B-B′ direction as shown inFIG.27. Consequently, the buried layer22formed through non-critical mask is self-aligned by insulating layers26and28and continuous along the horizontal direction. Therefore, the depth of the isolation layer28is deeper than the depth of the isolation layer26, allowing the buried layer22to be continuous in the perpendicular direction of gate60. In one embodiment of this invention, the gate60in the vertical direction becomes wordline (WL) and the buried layer22in the horizontal direction becomes bitline (BL), forming a cross-point memory cell at each grid point, intersecting WL and BL. The orientation and terminology of WL and BL may be switched or the different terminology such as row and column can be used for WL and BL, interchangeably. The memory cell550includes terminals: word line (WL) terminal70, bit line (BL) terminal74, and substrate terminal (SUB)78. WL terminal70is connected to gate60. BL terminal72is connected to the buried layer22. Substrate terminal78is connected to substrate12below buried layer22. However, no physical connection to source/drain16and18is made to any terminals. At each grid point, the metal-insulator-semiconductor (MIS) dielectric capacitor is formed by gate60, gate dielectric62, and body24. The term “metal” may include all conductive structure such as highly doped polysilicon. The doping concentration of n-type buried layer22could range from 1×1018/cm3to 5×1018/cm3. The doping concentration of p-type body24could range from 1×1016/cm3to 5×1018/cm3, and may be the same as the body doping concentration used in the n-type transistor on the same substrate. As a result, each cross-section of WL and BL or each memory cell includes pn junction diode formed by the p-type body24and the n-type buried layer22. The per-memory cell550diode serves as a select device of the cross-point memory structure preventing the flow of parasitic leakage current. ReferringFIG.28, an equivalent layout of the array2150of memory cells550ofFIGS.25-27is shown. Memory cell550include gate dielectric antifuse52and pn junction diode54.FIG.29shows example bias conditions for programming and read operations. The programing operation bias causes MIS oxide breakdown to the selected cells550but not to the unselected cells550. The read operation bias senses the resistance or conductance of the selected cell550while minimizing the parasitic leakage current through unselected cells550. In this example, the program voltage (Vp) and the read voltage (Vread) are selected by 3 V and 1 V, respectively. But those voltages are only example and their actual voltages depend on the technology and process. When the Vp and 0 V are applied across the selected wordline and selected bitline, respectively, its gate dielectric breaks down and the cell takes on a conductive state. For unselected cell550, both unselected wordlines and bitlines are floating. The unselected cells are not disturbed. Alternatively, 0V and Vp are applied to unselected wordlines and bitlines, respectively. The half-selected cells (i.e. where only one of the WL or BL terminals is biased at a selected voltage while the other WL or BL terminals is biased at an unselected voltage) are at the same bias conditions across its wordline and bitline and no current flows. The unselected cells at the programmed states are under reverse biased condition and the leakage will be negligible. The read operation is similar to the write operation except that the read voltage is greater than the threshold voltage of pn junction diode such as 0.6 V and lower than the breakdown voltage used for the program operation. The leakage current across BL to BL is minimized as the neighboring BLs form back-to-back pn diodes. The breakdown voltage of such parasitic npn structure (BL-substrate-BL) may be greater than 6 V. FIGS.30A-30C and31illustrate memory cell650having insulating layers26and28having different depths. Memory cell650is a bi-stable floating body device, for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”), U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), U.S. Patent Application Publication No. 2012/0217549, “Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor” (“Widjaja-3”), and U.S. patent application Ser. No. 13/746,523, “Memory Device Having Electrically Floating Body” (“Widjaja-4”), which are all hereby incorporated herein, in their entireties, by reference thereto. As illustrated inFIGS.30A and30B(shown better inFIG.30A), the bottom of insulating layer26resides below the buried region22. A shallower insulating layer28is provided which insulates the floating body region24, but allows the buried layer22to be continuous in one direction, for example the perpendicular direction of the cross-sectional view shown inFIG.30A. As a result, different bias conditions may be applied to different buried layer regions22isolated by the insulating layer26.FIG.30Cillustrates two buried layer regions22aand22bisolated by insulating layer26, which can be connected to different terminals and biased independently. Memory cell650may also comprise a fin structure as illustrated inFIG.31. FIG.32illustrates memory cell602comprises memory device40and access device42, which are connected in series, and has been described for example in U.S. application Ser. No. 14/380,779, “Memory Cell Comprising First and Second Transistors and Methods of Operating” (“Widjaja-5”), which is hereby incorporated herein, in its entirety, by reference thereto. Memory cell602comprises a floating body region24of a first conductivity type, such as p-type, for example; buried layer region30aof a second conductivity type, such as n-type, for example. Insulating layers26(like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers26insulate floating body transistor40from adjacent floating body transistor40and adjacent access transistor42. The bottom of insulating layer26may reside inside the buried region30a,30ballowing buried region30a,30bto be continuous. Alternatively, the bottom of insulating layer26may reside below the buried region30a,30bas shown inFIG.32. A shallower insulating layer28can be provided which insulates the floating body region24, but allows the buried layer30a,30bto be continuous in one direction. As a result, different bias conditions may be applied to different buried layer regions30a,30bisolated by the insulating layer26.FIG.32illustrates two buried layer regions30aand30bisolated by insulating layer26, which can be connected to different terminals and biased independently. For example, about 0.0V may be applied to the buried layer region30bof the access transistor42, while about +1.2V may be applied to the buried layer region30aof the floating body transistor40. From the foregoing it can also be seen that a memory cell having reduced operating voltage through the application of a back bias has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope of the invention as claimed. | 57,549 |
11943938 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be disclosed and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. The present disclosure relates to a method method for manufacturing an electronic memory device and to a memory device manufactured using the method. The memory device of the present disclosure is a non-volatile memory device. For instance 3D vertical memory array, that has been realized as an independent die with a specific lithography process. In some examples, a 3D memory array may include a substrate with a plurality of contacts arranged in a pattern (e.g., a geometric pattern) and a first insulative material (e.g., a dielectric material) formed on the substrate. A plurality of planes of a conductive material may be separated from one another by a second insulative material (e.g., a dielectric material) and formed on the substrate material. The planes of conductive material may be examples of word lines. A cross-point memory array is a 3D vertical memory array having memory cells formed at a topological cross-point between a first conductive access line (e.g., word line) and a second conductive access line (e.g., digit line). This 3D architecture allows to advantageously increase the number of memory cells that may be placed or created on a single die or substrate as compared with 2D architectures. This 3D architecture may thus reduce production costs, or increase the performance of the memory device, or both. Cross-point memory arrays may be manufactured by forming a stack of alternating layers of conductive materials (e.g., tungsten or molybdenum) and dielectric, insulating materials (e.g., silicon dioxide) on a substrate with a plurality of contacts. A plurality of vertically stacked 2D memory arrays is formed in which each 2D memory array is associated with a corresponding conductive material layer. For each 2D memory array, first access lines (e.g., word lines) are formed from the associated conductive material layer, and memory cell data storage elements (e.g., phase-change material elements) are formed contacting said first access lines. Second access lines (e.g., digit lines) in the form of conductive pillars are formed that vertically cross the alternating layers of conductive materials and dielectric materials until contacting the contacts on the substrate. Therefore, a (storage element of a) memory cell of a 2D memory array can be accessed (e.g., for programming or reading the logic state thereof) through a first access line (word line) obtained from the associated conductive material layer, and through a second access line (e.g., digit line) corresponding to a conductive pillar. In order to form the first access lines, the storage elements and the conductive pillars of this 3D vertical arrangement, the manufacturing process thereof requires the formation of trenches crossing the stack of alternating layers of conductive materials and dielectric materials until reaching the substrate. In order to form these trenches, selective etching operations are performed to selectively remove portions of the stack of alternating layers of conductive materials and dielectric materials until reaching the substrate. However, as the number of vertically stacked layers of conductive materials and dielectric materials is increased (e.g., above 64), the abovementioned selective etching operations become more difficult to be carried out. Indeed, etching a portion of a layer of a conductive material such as tungsten or molybdenum requires the application of an etching agent for a non negligible amount of time. When the number of vertically stacked layers is too high, the mask used for the selective etching operation can be consumed before the complete formation of the trench. Other conductive materials which can be etched in an easier way, such as the polysilicon used in the floating gate NAND memory technology, could be used as conductive layers for forming the 3D vertical memory arrays of the cross-point type. However, their higher resistivity causes the memory device to be affected by a disadvantageous latency increase. Solutions used for manufacturing vertical 3D NAND memory devices based on the so-called Replacement Gate architecture, try to solve this drawback by forming on the substrate a stack of alternating layers of two different dielectric (insulating) materials (e.g., silicon dioxide layers and silicon nitride layers) instead of forming a stack of alternating layers of conductive materials and dielectric materials. According to this solution, the layers made in one of the two dielectric materials (e.g., the silicon nitride layers) are sacrificial layers, adapted to be replaced by layers of a conductive material in a subsequent time. Then, trenches are generated in the stacked layers of the two dielectric materials by means of etching, and memory cells and conductive pillars are formed. A plurality of slits are then etched through the stacked layers of the two dielectric materials, for example a slit every four lines of conductive pillars, and etchant is applied through the opened slits for selectively removing the sacrificial layers. The slits are then exploited for filling the empty spaces left by the removed sacrificial layers with a conductive material (such as tungsten) to be used for forming word lines. The abovementioned method for manufacturing vertical 3D NAND memory devices based on the Replacement Gate architecture is affected by the drawback of requiring the formation of dedicated slits for the removal of the sacrificial layers, which negatively increase the area occupation of the resulting memory device. Moreover, this method is not suitable for being used for manufacturing 3D vertical memory arrays of the cross-point type, since it provides for the replacement of the sacrificial layers with conductive material only after the formation of the conductive pillars and of the memory cells. In view of the above, the applicant has devised a solution for manufacturing a memory device comprising a 3D vertical memory array, particularly a 3D vertical memory array of the cross-point type which is not affected by the drawbacks of the solutions known in the art. With particular reference to the figures, which all share the same reference system identified by the three orthogonal directions x, y and z,FIG.1illustrates an example of a portion of a 3D vertical memory array100in accordance with embodiments of the present disclosure. The 3D vertical memory array100comprises one or more, preferably a plurality, 2D arrays (or decks)105(i) (i=1, 2, . . . ) of memory cells stacked to each other along a direction parallel to direction z above a substrate104(e.g., made of or comprising dielectric material) extending parallel to direction x and y. In the exemplary 3D vertical memory array100portion illustrated inFIG.1, portions of only three decks of memory cells are visible, namely a generic deck105(i) and the two adjacent decks105(i−1) and105(i+1), wherein the deck105(i−1) is below the deck105(i) and the deck105(i+1) is above the deck105(i). The 3D vertical memory array100includes for each deck105(i) associated word lines110(i), extending substantially parallel to the substrate104at a corresponding distance (along direction z) with respect to the substrate104. The 3D vertical memory array100include also digit lines115in the form of conductive pillars, only one being depicted in the figure, extending substantially perpendicular to the substrate104(i.e., extending along direction z). Memory cells of the decks105(i) may comprise self-selecting memory cells. Each memory cell of each deck105(i) comprises a data storage element125(i), made in, or comprising, a storage element material, such as a chalcogenide material, for example a chalcogenide alloy and/or glass, that may serve as a self-selecting data storage element material, i.e., a material that may serve as both a select device and a data storage element. The architecture of 3D vertical memory array100may be referred to as a cross-point architecture, in which a memory cell is formed at a topological cross-point between a word line110(i) and a digit line115, with the generic data storage element125(i) that contacts a corresponding word line110(i) associated to the deck105(i) and a corresponding digit line115. Such a cross-point architecture may offer relatively high-density data storage with lower production costs compared to other memory architectures. For example, the cross-point architecture may have memory cells with a reduced area and, resultantly, an increased memory cell density compared to other architectures. According to this architecture, memory cells belonging to a generic deck105(i) are vertically stacked (along direction z) above the memory cells of the underlying deck105(i−1), with the data storage elements125(i) that are located above the data storage elements125(i−1) and are electrically insulated from the latter by means of a dielectric (insulating) material portion128(i) located between the data storage elements125(i) and125(i−1). The substrate104may comprise a plurality of contacts (not visible inFIG.1) arranged in a grid or staggered pattern. For example, the plurality of contacts may extend through the substrate104and couple with access lines of the memory array100, such as the digit lines115. Memory cells may be accessed through selected word line(s)110(i) and selected digit line(s)115for receiving program and/or read pulses. The generic data storage element125(i) may be responsive to an applied voltage, such as a program pulse. For an applied voltage that is less than a threshold voltage, the data storage element125(i) may remain in an electrically nonconductive state, corresponding for example to a “RESET” state (or logic “0”). Responsive to an applied voltage that is greater than the threshold voltage, the data storage element125(i) may enter an electrically conductive state, corresponding for example to a “SET” state (or logic “1”). The data storage element125(i) may be programmed to a target logic state by applying a pulse (e.g., a program pulse) that satisfies a programming threshold. The amplitude, shape, or other characteristics of the program pulse may be configured to cause the data storage element125(i) to exhibit the target logic state. For example, after applying the program pulse, the ions of the data storage element125(i) may be redistributed throughout the data storage element125(i), thereby altering a resistance of the memory cell detected when a read pulse is applied. In some cases, the threshold voltage of the data storage element125(i) may vary based on applying the program pulse. In other embodiments, the data storage element125(i) may be programmed to a target logic state by one or more pulses of a positive or a negative polarity applied to the selected word line110(i) and bit line (115), The logic state stored by the data storage element125(i) may be sensed, detected, or read by applying read pulse to the storage element125(i). The amplitude, shape, or other characteristics of the read pulse may be configured to allow a sense component to determine what logic state is stored in the data storage element125(i). For example, in some cases, the amplitude of the read pulse is configured to be at a level that the data storage element125(i) will conduct (e.g., current is conducted through the material) for a first logic state such as the “SET” state (or logic “1”), but will be not conductive (e.g., little to no current is conducted through the material) for a second logic state such as the “RESET” state (or logic “0”). In some cases, the polarity of the pulse (whether program pulse or read pulse) applied to the data storage element125(i) may affect the outcomes of the operation being performed. For example, a read pulse of a first polarity may result in the data storage element125(i) exhibiting a first logic state while a read pulse of a second polarity may result in the data storage element125(i) exhibiting a second, different logic state. This may occur because of the asymmetrical distributions of ions or other material in the data storage element125. Similar principles apply to program pulses and other pulses or voltages. Examples of chalcogenide materials that may serve as the data storage element125(i) include indium(In)-antimony(Sb)-tellurium(Te) (IST) materials, such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., and germanium(Ge)-antimony(Sb)-tellurium(Te) (GST) materials, such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, or etc., among other chalcogenide materials, including, for instance, alloys that do not change phase during the operation (e.g., selenium-based chalcogenide alloys). Further, the chalcogenide material may include minor concentrations of other dopant materials. Other examples of chalcogenide materials may include tellurium-arsenic (As)-germanium (OTS) materials, Ge, Sb, Te, silicon (Si), nickel (Ni), gallium (Ga), As, silver (Ag), tin (Sn), gold (Au), lead (Pb), bismuth (Bi), indium (In), selenium (Se), oxygen (O), Sulphur (S), nitrogen (N), carbon (C), yttrium (Y), and scandium (Sc) materials, and combinations thereof. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. In some examples, the chalcogenide material may be a chalcogenide glass or amorphous chalcogenide material. In some example, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium(Ge) may be referred to as SAG-alloy. In some examples, SAG-alloy may include silicon (Si) and such chalcogenide material may be referred to as SiSAG-alloy. In some examples, the chalcogenide glass may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms. In some examples, conductivity may be controlled through doping using various chemical species. For example, doping may include incorporating a Group 3 (e.g., boron (B), gallium (Ga), indium (In), aluminum (Al), etc.) or Group 4 (tin (Sn), carbon (C), silicon (Si), etc.) element into the composition. A method according to embodiments of the present disclosure for manufacturing a 3D vertical memory array corresponding to the 3D vertical memory array100ofFIG.1will be now described by making reference toFIGS.2A,2B,3A,3B,4A,4B,5A-5C,6A,6B,7A-7C,8A-8C,9A,9B,10A,10B,11A,11B and12. The first phase of the manufacturing method according to embodiments is illustrated inFIGS.2A and2B, whereinFIG.2Ais a bottom view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from a plane parallel to directions x and y, andFIG.2Bis a side view of the same array taken from a plane parallel to directions x and z. The phase of the method illustrated inFIGS.2A and2Bcomprises providing the substrate104made of or comprising dielectric material, and forming a plurality of conductive contacts202which extend through the substrate104. According to an embodiment, each conductive contact202is configured to contact a corresponding digit line (seeFIG.1), for example through a selector transistor (not illustrated). The plurality of conductive contacts202may be arranged according to a grid pattern. For example, a conductive contact202may be surrounded by up to eight other conductive contacts202. According to other embodiments, not illustrated, the plurality of conductive contacts202may be arranged in a staggered pattern or a hexagonal pattern. According to an embodiment, this phase of the method further comprises forming on the substrate104a stack of alternating layers of two different dielectric (insulating) materials, comprising first dielectric material layers204and second dielectric material layers206. According to an embodiment, the first dielectric material layers204comprise silicon dioxide layers and the second dielectric material layers206comprise silicon nitride layers. Each first and second dielectric material layer204,206are at a different level (i.e., at a different distance along direction z) with respect to the substrate104. According to an embodiment of the present disclosure, the first dielectric material layers204and the second dielectric material layers206are formed by means of a sequence of deposition operations. Although seven first dielectric material layers204and six second dielectric material layers206are illustrated in the figures, it has to be appreciated that concepts according to embodiments of the present disclosure can be applied to a different (e.g., higher) number of layers, such as for example 64. As will be described in greater detail in the following, according to an embodiment of the present disclosure, the first dielectric material layers204will be used for the generation of the dielectric material portions128(i) between the data storage elements125(i) and125(i−1) of memory cells belonging to adjacent decks105(i),105(i−1) of the finished 3D vertical memory array100(seeFIG.1). As will be described in greater detail in the following, according to an embodiment, the second dielectric layers206are sacrificial layers adapted to be replaced in a subsequent method phase by layers of a conductive material to be used for the formation of the word lines110(i) associated to the decks105(i) of the finished 3D vertical memory array100. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.3A and3B, whereinFIG.3Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from a section plane A-A′ plane parallel to directions x and y and crossing a second dielectric material layer206, andFIG.3Bis a section view of a portion of the same array taken from a section plane B-B′ parallel to directions y and z and crossing three conductive contacts202. The phase of the method illustrated inFIGS.3A and3Bcomprises forming a trench305through the alternating first and second dielectric material layers204,206until exposing the underlying substrate104and the conductive contacts202. According to an embodiment of the present disclosure, the trench305is formed by means of a selective etching operation exploiting a suitable patterned mask (not illustrated). Since both the first dielectric material layers204and the second dielectric material layers206are made of or comprise dielectric materials such as silicon dioxide and silicon nitride, which can be etched more easily compared to conductive materials such as tungsten or molybdenum, the selective etching operation can be expediently carried out even if the number of first and second dielectric material layers204,206is large. Indeed, the etching operation can be carried out in a relatively fast and efficient way, and the underlying substrate104can be advantageously exposed before the mask used for the selective etching operation is consumed. As already mentioned above, if instead a large number of conductive material (e.g., molybdenum or tungsten) layers had to be etched, the mask used for the etching operation would consume itself before the etching reached the underlying substrate104. According to an embodiment of the disclosure, the trench305has a serpentine-like shape view from above. According to an embodiment of the disclosure, the trench305may pass over a row of the conductive contacts202in a first direction (e.g., parallel to direction x, going from left to right), and then pass over an adjacent row of the conductive contacts202in a second direction that is opposite to the first direction (e.g., parallel to direction x, going from right to left). With reference toFIG.3A, the trench305passes over a first row of conductive contacts202parallel to direction x from left to right, then “turns” and passes over a next (second) row of conductive contacts202(adjacent to the first row of conductive contacts202along direction y) parallel to direction x from right to left. The trench305then “turns” again and passes over a next (third) row of conductive contacts202(adjacent to the second row of conductive contacts202along direction y) parallel to direction x from left to right, and so on. The trench305is arranged to bifurcate each first and second dielectric material layers204,206in at least two portions: a first portion204(a),206(a) and a second portion204(b),206(b)(only the portions206(a) and206(b) being visible inFIG.3A). As will be described in detail the following, according to embodiments of the present disclosure, the (separate) portions206(a) and206(b) of each second dielectric material layer206will be replaced by corresponding conductive material portions having the same shape, and forming interleaved word lines110(i) associated to the corresponding deck105(i) of the finished 3D vertical memory array100(e.g., even word lines110(i) and odd word lines110(i)). The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.4A and4B, whereinFIG.4Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane parallel to directions x and y and crossing a second dielectric material layer206, andFIG.4Bis a section view of a portion of the same array taken from the section plane B-B′ parallel to directions y and z and crossing three conductive contacts202. The phase of the method illustrated inFIGS.4A and4Bcomprises entirely filling (e.g., through a deposition process) the trench305with a dielectric material405, such as the same dielectric material of the substrate104, until reaching the top dielectric material layer204and forming a cap layer410covering said top dielectric material layer204. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.5A,5B and5CwhereinFIG.5Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane,FIG.5Bis a section view of a portion of the same array taken from the section plane B-B′, andFIG.5Cis a section view of a portion of the same array taken from a section plane C-C′ parallel the section plane B-B′ and displaced from the latter along direction x so as to be located between pairs of adjacent conductive contacts202. The phase of the method illustrated inFIGS.5A-5Ccomprises forming for each conductive contact202a respective hole-like trench505that crosses—along direction z—the cap layer410and the dielectric material405inside the serpentine-like trench305until exposing the conductive contact202. These hole-like trenches505will be used to define the conductive pillars forming the digit lines115. According to an embodiment of the present disclosure, the formation of the hole-like trenches505is carried out by means of a selective vertical etching operation directed to etch (portions of) the dielectric material405inside the serpentine-like trench and the cap layer410only, without attacking the dielectric materials forming the first and second dielectric material layers204,206. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.6A and6B, whereinFIG.6Ais a section view of a portion of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane B-B′ andFIG.6Bis a section view of a portion of the same array taken from the section plane C-C′. The phase of the method illustrated inFIGS.6A and6Bprovides for exploiting the previously generated hole-like trenches505—which will be used later on for the generation of the conductive pillars corresponding to the digit lines115—for providing access to all the stacked first and second dielectric material layers204,206from a large number of different points across the array. According to an embodiment of the present disclosure, the hole-like trenches505are exploited for removing the dielectric material of the second dielectric material layers206. According to an embodiment of the present disclosure, an isotropic etching operation is performed for selectively removing the dielectric material of the second dielectric material layers206. According to an embodiment of the present disclosure, an etching agent is provided through the hole-like trenches505, configured to selectively remove the dielectric material of the second dielectric material layers206(e.g., silicon nitride), without attacking the dielectric material of the first dielectric material layers204. Since the hole-like trenches505are distributed across the 3D array structure in a high number and with a high density—such as for example every 60 nm—the etching agent can easily reach all (i.e., at any depth along direction z) the second dielectric material layers206and propagate along directions x and y between adjacent first dielectric material layers204while the second dielectric material layers206are being etched and removed. In this way, according to this embodiment of the disclosure, the second dielectric material layers206can be efficiently removed. The resulting layered arrangement, in which empty cavities605are formed between adjacent first dielectric material layers204, is mechanically supported by the dielectric material structure comprising the dielectric material405of the serpentine-like trench305, the cap layer410, and the substrate104. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.7A,7B and7CwhereinFIG.7Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane,FIG.7Bis a section view of a portion of the same array taken from the section plane B-B′, andFIG.7Cis a section view of a portion of the same array taken from the section plane C-C′. The phase of the method illustrated inFIGS.7A,7B and7Cprovides for exploiting again the hole-like trenches505, this time for accessing the cavities605and filling it (e.g., by means of a deposition process) with a conductive material, such as tungsten or molybdenum, in order to form corresponding conductive material layers705between the first dielectric material layers204. During this phase, also the bottom of each hole like trench505, as well as the side thereof will be covered by conductive material. The conductive material layers705will be used for the formation of the word lines110(i) associated to the decks105(i) of the finished 3D vertical memory array100. Again, since the hole-like trenches505are distributed across the 3D array structure in a high number and with a high density, the conductive material can easily reach all (i.e., at any depth along direction z) the cavities605and propagate along directions x and y. In this way, according to this embodiment of the disclosure, the cavities605can be effectively filled and the conductive material layers705are generated in a very efficient way. Because of the dielectric material405of the serpentine-like trench305, each conductive material layer705is bifurcated into a first conductive material portion705(a) and a second conductive material portion705(b). According to an embodiment of the present disclosure, the (separate) portions705(a) and705(b) of each conductive material layer705will form interleaved word lines110(i) associated to the corresponding deck105(i) of the finished 3D vertical memory array100(e.g., the portions705(a) for odd word lines110(i) and the portions705(b) for even word lines110(i)). The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.8A,8B and8CwhereinFIG.8Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane,FIG.8Bis a section view of a portion of the same array taken from the section plane B-B′, andFIG.8Cis a section view of a portion of the same array taken from the section plane C-C′. The phase of the manufacturing method illustrated inFIGS.8A,8B,8C, provides for forming a plurality of recesses805in each conductive material layer705at the hole-like trenches505. For example, each recess805is formed in such a way to face toward a respective hole-like trench505. According to an embodiment of the present disclosure, the recesses805are formed by means of an etching operation in sidewalls of the hole-like trenches505in an isotropic way. The recesses805are formed in such a way that the sidewalls of a generic hole-like trench505are spaced apart to each other along direction x from a first distance d1(between portions of the first dielectric material layers204facing to each other in said hole-like trench505), while pairs of recesses805facing to each other at said hole-like trench505comprises side walls spaced apart to each other along direction x from a second distance d2higher than the first distance d1(seeFIG.8B). As will be described in the following, the recesses805will be used for the formation of the data storage elements125(i) of the memory cells of the finished 3D vertical memory array100. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.9A and9BwhereinFIG.9Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane, andFIG.9Bis a section view of a portion of the same array taken from the section plane B-B′. The phase of the manufacturing method illustrated inFIGS.9A and9Bprovides for the conformal deposition of a chalcogenide material905, for example a chalcogenide alloy and/or glass, into the hole-like trenches505(for example, a sidewall direction conformal deposition). The chalcogenide material905is deposited in such a way to cover the bottom and side walls of the hole-like trenches505, filling the recesses805formed in the conductive material layers705. In this way, the chalcogenide material905contacts the conductive material layers705(the portions705(a) and705(b) thereof). The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.10A and10BwhereinFIG.10Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane, andFIG.10Bis a section view of a portion of the same array taken from the section plane B-B′. The phase of the manufacturing method illustrated inFIGS.10A and10Bprovides for carrying out a selective etching operation directed to remove excess portions of the chalcogenide material905deposed in the hole-like trenches505in such a way that the remaining portions of the chalcogenide material905form the data storage elements125(i) of the memory cells of the finished 3D vertical memory array100. According to an embodiment of the present disclosure, said etching operation is carried out in such a way that side surfaces of the data storage elements125(i) (i.e., the surfaces thereof facing toward the hole-like trenches505) are substantially co-planar with surfaces of the portions of the first dielectric material layers204facing toward the hole-like trenches505, and are spaced apart to each other along direction y by the same distance d1(seeFIG.10B). In each recess805, a corresponding storage element125(i) is thus formed, which contacts (seeFIG.10B):along direction y, a corresponding portion705(a) or705(b) of a conductive material layer705, andalong direction z, two corresponding portions of two first dielectric material layers204. Making reference toFIG.10Btogether withFIG.1(the latter illustrating a portion of the finished 3D vertical memory array100), the portion705(a) or705(b) of conductive material layer705contacting the generic storage element125(i) of the deck105(i) correspond to the corresponding world line110(i) for accessing the storage element125(i), while the two portions of two first dielectric material layers204contacting the generic storage element125(i) correspond to the dielectric material portions128(i) and128(i+1) that allow electric insulation of the storage element125(i) from the storage elements125(i+1) and125(i−1) belonging to the adjacent decks105(i+1),105(i−1). The etching operation of this phase is also carried out in such a way to remove chalcogenide material905from the bottom of the hole-like trenches505to expose the conductive contacts202. The next phase of the manufacturing method according to embodiments of the present disclosure is illustrated inFIGS.11A and11BwhereinFIG.11Ais a section view of an intermediate (i.e., partially manufactured) 3D vertical memory array taken from the section plane A-A′ plane, andFIG.11Bis a section view of a portion of the same array taken from the section plane B-B′. The phase of the manufacturing method illustrated inFIGS.11A and11Bprovides for filling the hole-like trenches505with conductive material in order to form conductive pillars1005extending along direction z and contacting the storage elements125(i). According to an embodiment of the present disclosure, the conductive material of the conductive pillars1005is deposed according to a sidewall direction conformal deposition operation. In this specific case, the conductive material has to be compatible with a sidewall direction conformal deposition operation According to this embodiment, the conductive material of the conductive pillars1005may be the same used for the generation of the conductive material layers705, provided that such conductive material is compatible with a sidewall direction conformal deposition operation. The finished 3D vertical memory array100according to embodiments of the present disclosure is then obtained by covering the trench305opening in the cap layer410with the same dielectric material in order to cover also the conductive pillars1005, as shown in the section view illustrated inFIG.12taken from the section plane B-B′. Compared to the 3D vertical memory arrays obtained with known methods, the 3D vertical memory array that can be manufactured with the herein described manufacturing method according to embodiments of the present disclosure is more compact, requiring less area occupation. Compared in particular to the above mentioned known methods for manufacturing vertical 3D NAND memory devices based on the Replacement Gate architecture, a higher memory cell density is obtained. Indeed, while the known methods for manufacturing vertical 3D NAND memory devices based on the Replacement Gate architecture cause a waste of space because of the mandatory presence of a high number of dedicated slits (e.g., every four conductive pillars), for removing the sacrificial layers, the manufacturing method according to embodiments of the present disclosure advantageously exploit the hole-like trenches (used for the generation of the conductive pillars) also for the replacement of the sacrificial layers with the conductive layers corresponding to the word lines. Moreover, the herein described manufacturing method according to embodiments of the present disclosure is particularly suited for manufacturing 3D vertical memory arrays of the cross-point type, since it provides for the replacement of the sacrificial layers with conductive material layers before the formations of the storage elements and of the conductive pillars. According to an embodiment of the present disclosure illustrated inFIG.13, in case of compatibility issues between the chalcogenide material of the storage elements125(i) and the conductive material of the conductive material layers705and/or of the conductive pillars1005, barriers (identified inFIG.13with reference1305) could be interposed between the conductive material layers705and the storage elements125(i), and/or barriers (identified inFIG.13with reference1310) could be interposed between the conductive pillars1005and the storage elements125(i) to avoid cross-contamination between the materials. As already mentioned above, the herein described manufacturing method according to embodiments of the present disclosure is based on the replacement of sacrificial dielectric layers (the first dielectric material layers204) with conductive material layers (the conductive material layer705) exploiting the hole-like trenches505, which are necessary for the formation of the conductive pillars1005corresponding to the digit lines115in the active portion of the memory array, i.e., the portion wherein the memory cells are located. However, in order to access the (vertically stacked) word lines110(i) of the 3D vertical memory array (e.g., for the providing program and/or read pulses), one or more access portions, for example located at one or more of the edges of the one or more active portions, in which the conductive material layers705have staggered lengths so as to form “steps” on one or more edges of the one or more active portions, as illustrated in the side view ofFIG.14. Each respective “step” of the access portion corresponds to a respective layer of the 3D vertical memory array, and comprises a conductive access contact1405contacting a corresponding conductive material layer705. In some embodiments, the staircase depicted inFIG.14may be formed according to a trim and etch technique. Since the access portion does not comprise memory cells, the presence of hole-like trenches505for the formation of conductive pillars1005corresponding to digit lines115is not required. Moreover, the access portion has a non-negligible length (e.g., along direction x) in order to be sufficiently long to accommodate a large number of steps depending in turn on the number of stacked conductive material layers705(for example, 3-4 μm). The absence of hole-like trenches505together with the non-negligible length of the access portion could make it not suitable to be directly manufactured with the previously described method (replacement of sacrificial dielectric layers with conductive material layers). Indeed, in order to access the various layers of the access portion for removing the sacrificial dielectric layers therefrom, the closest hole-like trenches505through which etchant agent can be provided (i.e., in the active portion of the array) could be too far for allowing an efficient removal of the sacrificial dielectric layers. Similarly, the same closest hole-like trenches505through which conductive material can be provided for substituting the sacrificial dielectric layers could be too far for allowing an efficient formation of the conductive material layers. Moreover, even if the sacrificial dielectric layers were actually removed from the access portion, the remaining dielectric material layers would collapse because of the too large size of the access portion. For this reason, according to an embodiment of the present disclosure illustrated inFIG.15, dedicated (e.g., linear) trenches1505(functionally similar to the trench305described with reference toFIGS.3A,3B) are formed, and filled with dielectric material (like the filling of the trench305with dielectric material405described with reference toFIGS.4A,4B), and hole-like trenches1510are formed in said dedicated trenches1505. According to an embodiment of the present disclosure, the hole-like trenches1510are advantageously exploited for the removal of sacrificial dielectric layers and the replacement thereof with conductive material layers, like the previously described hole-like trenches505. Moreover, the dedicated trenches1505filled with dielectric material work as support structure that advantageously avoid the collapse of the remaining dielectric material layers of the access portion after the removal of the sacrificial layers. FIG.16illustrates a diagram showing the steps of a method of the present disclosure. Several steps of a method1600for manufacturing a 3D vertical array of memory cells are depicted. Steps1610-1680may be carried out according to the description above with reference toFIGS.2-13and14-15. Some details have been omitted in the diagram of method1600to avoid obfuscating the method flow. Method1600may comprise, at step1610, forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each other; at step1620, forming holes through the stack of dielectric material layers, said holes exposing the substrate; at step1630, selectively removing the second material layers through said holes to form cavities between adjacent first dielectric material layers; at step1640, filling said cavities with a conductive material through said holes to form corresponding conductive material layers; at step1650, forming first memory cell access lines from said conductive material layers; at step1660, carrying out a conformal deposition of a chalcogenide material through said holes; at step1670, forming memory cell storage elements from said deposed chalcogenide material; and, at step1680, filling said holes with conductive material to form corresponding second memory cell access lines. The previous description presents and discusses in detail several embodiments; nevertheless, several changes to the described embodiments, as well as different embodiments are possible, without departing from the scope defined by the appended claims. | 41,986 |
11943939 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Integration of various modules built by different designers into an IC device is potentially a challenging task, due to different metal schemes used by different designers. A metal scheme includes various specifications including, but not limited to, a direction of metal patterns in a metal layer, a pitch between adjacent metal patterns, or the like. Horizontal and vertical metal schemes with correspondingly horizontal and vertical metal directions of metal patterns are often used for integrating or coupling different modules. In some embodiments, a module (also referred to as “circuit region”) has IO pins (also referred to as “IO patterns”) which are oblique to both the horizontal metal direction and the vertical metal direction. As a result, it is easier in at least one embodiment to integrate modules, and/or to reuse modules for various metal schemes. FIG.1is a schematic view of an IC device100, in accordance with some embodiments. The IC device100comprises a substrate102, and at least one circuit region over the substrate102. In the example configuration inFIG.1, the IC device100comprises circuit regions110,112,114,116,118over the substrate102. The number of five circuit regions110,112,114,116,118is an example. Other numbers of circuit regions over a substrate are within the scopes of various embodiments. In some embodiments, the substrate102is a semiconductor material (e.g., silicon, doped silicon, GaAs, or another semiconductor material). In some embodiments, the substrate102is a P-doped substrate. In some embodiments, the substrate102is an N-doped substrate. In some embodiments, the substrate102is a rigid crystalline material other than a semiconductor material (e.g., diamond, sapphire, aluminum oxide (Al2O3), or the like) on which an IC is manufactured. In some embodiments, N-type and P-type dopants are added to the substrate102to form one or more circuit elements as described herein. Each of the circuit regions110,112,114,116,118comprises at least one cell. Each cell represents one or more semiconductor structures configured to perform a specific function. Cells having pre-designed layout diagrams, sometimes known as standard cells, are stored in standard cell libraries (hereinafter “libraries” or “cell libraries” for simplicity) and accessible by various tools, such as electronic design automation (EDA) tools, to generate, optimize and verify designs for IC devices. Each cell includes one or more circuit elements and/or one or more nets. A circuit element is an active element or a passive element. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or the like. Examples of nets include, but are not limited to, vias, conductive pads, conductive traces (also referred to herein as “patterns”), and conductive redistribution layers, or the like. In some embodiments, each of the circuit regions110,112,114,116,118comprises a combination of cells electrically coupled together to perform at least one corresponding function of the IC device100. The circuit regions110,112,114,116,118are electrically coupled together to perform various functions of the IC device100. In some embodiments, at least one of the circuit regions110,112,114,116,118comprises an intellectual property (IP) block. An IP block comprises a cell or a combination of cells developed by an IC designer (also referred to as “IP provider”). In some situations, an IP designer is a fabless design house or design company which designs, but does not manufacture, IC devices. In some situations, an IP designer is a foundry that designs and manufactures IC devices. An IP designer develops various IP blocks with corresponding different functions, and stores the developed IP blocks in an IP library. Different IC designers develop different IP libraries. It is possible that the same component with the same function is developed by different IC designers and corresponds to different IP blocks. IP blocks are reusable and selectable by a user to integrate the selected IP blocks into an IC device. It is possible that a user selects IP blocks from different IP designers or IP libraries to be integrated into an IC device. In some embodiments, at least one of the circuit regions110,112,114,116,118comprises a non-IP block. A non-IP block comprises a cell or a combination of cells, but is not retrieved from an IP library. For example, a non-IP block is built from standard cells retrieved from a standard library, and/or developed specifically for a particular IC device. In some embodiments, at least one of the circuit regions110,112,114,116,118comprises a core. A core comprises one or more IP blocks and/or one or more non-IP blocks integrated together. A core built from IP blocks of the same IP designer is sometimes referred to as an IP core. In at least one embodiment, multiple cores are arranged side-by-side on the same substrate, as described herein. In one or more embodiments, multiple cores are stacked one on top another, as also described herein. Examples of cells include, but are not limited to, inverters, adders, multipliers, logic gates (such as NAND, XOR, NOR or the like), phase lock loops (PLLs), flip-flops, multiplexers, or the like. Examples of IP blocks and/or cores include, but are not limited to, memories, memory control logics, caches, resistor arrays, capacitor arrays, communications interfaces, application programming interfaces (APIs), analog to digital (A/D) converters, radio frequency tuners, digital signal processors (DSPs), graphics processing units (GPUs), arithmetic logic units (ALUs), floating-point units (FPUs), central processing units (CPUs), system-on-chips (SoCs), or the like. In some embodiments, each circuit region comprises one or more IO pins (or IO patterns) to electrically couple circuitry in the circuit region to external circuitry, such as another circuit region in the same IC device or an external device outside the IC device. An EDA tool, such as an Automatic Placement and Routing (APR) tool, generates an IC layout diagram from a design of the IC device by placing various circuit regions of the IC device in a floor plan, and routing various nets to interconnect the IO patterns of the placed circuit regions. In other words, the APR tool integrates various circuit regions into the IC device. Some embodiments provide an IO pin layout structure that, in at least one embodiment, makes it easier for an APR tool to integrate various circuit regions than other approaches. FIG.2is a schematic view of an IC layout diagram of a circuit region200, in accordance with some embodiments. In at least one embodiment, the circuit region200corresponds to one or more of the circuit regions110,112,114,116,118. In at least one embodiment, an IC device manufactured according to the IC layout diagram of the circuit region200comprises physical and electrical configurations of the circuit region200as described herein. The circuit region200comprises a boundary210within which various circuit elements and/or nets of the circuit region200are arranged. In the example configuration inFIG.2, the boundary210is rectangular and comprises sides211-214. The described shape and number of sides of the boundary210are examples. Other configurations are within the scopes of various embodiments. The circuit region200comprises at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. For example, as shown in the enlarged view of a section220of the circuit region200inFIG.2, the circuit region200comprises active regions201,202and gate regions203,204. The active regions201,202extend, or are elongated, along an X-X′ direction, which is the first direction. The gate regions203,204extend, or are elongated, across the active regions201,202and along a Y-Y′ direction, which is the second direction. The Y-Y′ direction is transverse to the X-X′ direction. In at least one embodiment, the Y-Y′ direction is perpendicular to the X-X′ direction. Active regions are sometimes referred to as oxide-definition (OD) regions, and are schematically illustrated in the drawings with the label “OD.” The X-X′ direction is sometimes referred to as the OD direction. The active regions201,202include P-type dopants and/or N-type dopants. The gate regions203,204include a conductive material, such as, polysilicon, and is schematically illustrated in the drawings with the label “PO.” The Y-Y′ direction is sometimes referred to as the Poly direction. Other conductive materials for the gate regions, such as metals, are within the scope of various embodiments. The active regions201,202and the gate regions203,204together form one or more circuit elements (not shown). Although in the example configuration inFIG.2, the active regions201,202and gate regions203,204are shown inside the section220, this is for illustrative purposes. In some embodiments, active regions and/or gate regions are arranged in other sections of the circuit region200. In at least one embodiment, active regions and gate regions, and therefore corresponding circuit elements of the circuit region200, are arranged over substantially an entirety of the circuit region200as defined by the boundary210. The circuit elements of the circuit region200are interconnected by nets (not shown) to form internal circuitry of the circuit region200. The internal circuitry of the circuit region200is configured to perform at least one function of the circuit region200. The nets of the circuit region200comprise metal patterns in various metal layers arranged one on top another. For example, the lowermost metal layer immediately over the active regions is sometimes referred to as the metal-zero (M0) layer, the subsequent metal layer immediately over the M0layer is sometimes referred to as the metal-one (M1) layer, and so on. The circuit region200comprises at least one input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. In the example configuration inFIG.2, the circuit region200comprises IO patterns221-229. Each of the IO patterns221-229is electrically coupled by one or more nets to one or more circuit elements in the internal circuitry of the circuit region200. Therefore, when external circuitry is electrically coupled to the IO patterns221-229, the external circuitry is electrically coupled to the internal circuitry of the circuit region200to integrate the circuit region200with other circuit regions in the IC device. Examples of IO patterns include, but are not limited to, signal IO patterns configured to communicate data signals to or from the circuit region200, power IO patterns configured to supply power supply voltages to the circuit region200, or the like. In the example configuration inFIG.2, the IO patterns221-224,228-229are signal IO patterns, whereas IO patterns225-227are power IO patterns and are schematically illustrated in the drawings with the label “PG” (power-ground). Power supply voltages carried by the power IO patterns include one or more positive power supply voltages, and the ground voltage. Power IO patterns are wider than signal IO patterns. For example, as illustrated inFIG.2, the power IO pattern225has a width d1greater than a width d2of the signal IO pattern224. Further, power IO patterns are longer than signal IO patterns. For example, as illustrated inFIG.2, the signal IO patterns221-224,228-229are shorter and arranged each adjacent one corresponding side of the boundary210. Specifically, the signal IO patterns221-224are arranged adjacent the side214, whereas the signal IO patterns228-229are arranged adjacent the side213of the boundary210. In contrast, each of the power IO patterns225-227is longer and extends from one side of the boundary210to another. Specifically, the power IO pattern225extends from the side214to the adjacent side211, whereas the power IO patterns226-227extend from the side213to the adjacent side212. The described types, numbers, and/or sizes of the IO patterns are examples. Other configurations are within the scopes of various embodiments. Each of the IO patterns221-229of the circuit region200extends, or is elongated, along a direction oblique to both the X-X′ direction and the Y-Y′ direction. For example, the IO patterns221-227are arranged in metal layer M4, and extend along a U-U′ direction which is oblique to both the X-X′ direction and the Y-Y′ direction. Further, the IO patterns228-229are arranged in metal layer M3, and extend along a V-V′ direction which is oblique to both the X-X′ direction and the Y-Y′ direction. The U-U′ direction is transverse to the V-V′ direction. In one or more embodiments, the U-U′ direction is perpendicular to the V-V′ direction. In at least one embodiment, the U-U′ direction is oblique, i.e., not perpendicular, to the V-V′ direction. The U-U′ direction of the IO patterns221-227in the metal layer M4forms with either of the X-X′ direction or the Y-Y′ direction an acute angle. For example, as illustrated inFIG.2, an angle230between the U-U′ direction and the Y-Y′ direction is an acute angle. The acute angle may be between any one of orientations U, U′ and any one of orientations Y, Y′. Similarly, the U-U′ direction and the X-X′ direction form therebetween an acute angle which may be between any one of orientations U, U′ and any one of orientations X, X′. The V-V′ direction of the IO patterns228-229in the metal layer M3forms with either of the X-X′ direction or the Y-Y′ direction an acute angle. For example, the V-V′ direction and the X-X′ direction form therebetween an acute angle which may be between any one of orientations V, V′ and any one of orientations X, X′. Similarly, the U-U′ direction and the Y-Y′ direction form therebetween an acute angle which may be between any one of orientations U, U′ and any one of orientations Y, Y′. Any of the described acute angles, e.g., the angle230, is greater than 0 degrees, and is smaller than 90 degrees. In some embodiments, the acute angle230is between 10 degrees and 80 degrees, or between 20 degrees and 70 degrees, or between 30 degrees and 60 degrees, or between 40 degrees and 50 degrees. In at least one embodiment, the acute angle230is 45 degrees. In the example configuration inFIG.2, the sides211,213of the boundary210extend along the X-X′ direction, and the sides212,214of the boundary210extend along the Y-Y′ direction. Accordingly, the IO patterns221-229are also oblique to the sides211-214of the boundary210. The oblique directions of the IO patterns221-229with respect to the X-X′ direction and the Y-Y′ direction facilitate integration of the circuit region200with other circuit regions, as described herein. In some embodiments, all metal patterns in the metal layer M4of an IC device including the circuit region200, are linear and parallel to the U-U′ direction. In other words, metal patterns in the metal layer M4of the IC device but outside the boundary210of the circuit region200are linear and parallel to the U-U′ direction. In some embodiments, all metal patterns in the metal layer M3of the IC device including the circuit region200, are linear and parallel to the V-V′ direction. In other words, metal patterns in the metal layer M3of the IC device but outside the boundary210of the circuit region200are linear and parallel to the V-V′ direction. In some embodiments, all metal patterns in each metal layer below the metal layers containing the IO patterns extend along the X-X′ direction or in the Y-Y′ direction. For example, for the metal layers M2, M1, M0below the metal layer M3, the metal layers M0and M2have metal patterns extending along the X-X′ direction (sometimes referred to as the “horizontal metal direction”), whereas the metal layer M1has metal patterns extending along the Y-Y′ direction (sometimes referred to as the “vertical metal direction”). In some embodiments, metal patterns in one or more or all metal layers above the metal layers containing the IO patterns extend along the X-X′ direction or in the Y-Y′ direction. For example, metal patterns in the metal layer M5extend along the X-X′ direction in one or more embodiments, or extend along the Y-Y′ direction in one or more further embodiments, as described herein. In some embodiments, each of the IO patterns221-229is completely arranged within the boundary210of the circuit region200. In some embodiments, the metal layers containing the IO patterns are the topmost metal layers of the circuit region200. For example, the circuit region200is an IP block read from an IP library, and placed by an APR tool into the IC layout diagram of an IC device. The IP block includes no information about layers above the metal layer M4, making the metal layer M3and the metal layer M4the two topmost metal layers of the IP block. The described configurations of the IO patterns221-229are examples. Other configurations are within the scopes of various embodiments. For example, in at least one embodiment, IO patterns of the circuit region200are arranged in one or more metal layers other than the metal layer M3and/or the metal layer M4. In one or more embodiments, IO patterns of the circuit region200are arranged in non-consecutive metal layers. In at least one embodiment, the IO patterns221-227are tilted to the other side of the Y-Y′ direction, i.e., the U-U′ direction is arranged such that the orientation U is in the quarter between the orientation Y and the orientation X′. In one or more embodiments, IO patterns of the circuit region200are arranged in one metal layer. For example, the IO patterns228-229are omitted and all IO patterns of the circuit region200are arranged in the metal layer M4. In one or more embodiments, IO patterns of the circuit region200are arranged in more than two metal layers. For example, IO patterns of the circuit region200are arranged in three metal layers M3, M4, M5. In at least one embodiment, the IO patterns in the three metal layers have three different metal directions. For example, metal patterns in the metal layer M5extend along a direction (not shown) that is oblique to all of the X-X′ direction, Y-Y′ direction, U-U′ direction and V-V′ direction. FIGS.3A-3Dare schematic views showing various routing arrangements for the circuit region200in an IC device, in accordance with some embodiments. InFIG.3A, an IO pattern is accessed from a metal layer different from the metal layer in which the IO pattern is arranged, in accordance with some embodiments. For example, to access, or electrically couple, to the IO pattern221, an APR tool generates or routes, in the metal layer M5over the metal layer M4in which the IO pattern221is arranged, an access pattern311. The access pattern311extends along the X-X′ direction from outside the boundary210of the circuit region200to inside the boundary210to overlap the IO pattern221. The APR tool further generates, in a via layer VIA4between the metal layer M4and the metal layer M5, a via313electrically coupling the access pattern311to the IO pattern221. Other circuitry electrically coupled to the access pattern311is electrically coupled to the IO pattern221and, hence, to the internal circuitry of the circuit region200. Because the access pattern311extends along the X-X′ direction and the IO pattern221extends along the U-U′ direction, an angle315between the access pattern311and the IO pattern221is an acute angle. As illustrated inFIG.3A, the angle315is formed between longitudinal center lines of the access pattern311and the IO pattern221. In some embodiments, another arrangement for accessing an IO pattern is from the same metal layer in which the IO pattern is arrangement. For example, to access, or electrically couple, to the IO pattern222, the APR tool generates, or routes, in the same metal layer M4where the IO pattern222is arranged, an extension pattern322. The extension pattern322is contiguous to the IO pattern222and extends from inside the boundary210of the circuit region200to outside the boundary210. In one or more embodiments, the extension pattern322is linear and aligned with the IO pattern222, i.e., a longitudinal center line of the extension pattern322coincides with a longitudinal center line of the IO pattern222. In at least one embodiment, the extension pattern322has the same width as the IO pattern222. The extension pattern322extends to overlap a further pattern324in the metal layer M3. The further pattern324extends along the V-V′ direction like the IO patterns228-229in the same metal layer M3. The APR tool further generates, in a via layer VIA3between the metal layer M3and the metal layer M4, a via326electrically coupling the extension pattern322to the further pattern324. FIG.3Bshows a further routing arrangement for the circuit region200, in accordance with some embodiments. A difference between the routing arrangements inFIGS.3A and3Bis that an access pattern331inFIG.3Bcorresponds to the access pattern311inFIG.3A, but extends instead along the Y-Y′ direction. The routing arrangement inFIG.3Ais applicable when the metal layer M5has the horizontal metal direction, and the routing arrangement inFIG.3Bis applicable when the metal layer M5has the vertical metal direction. A further difference between the routing arrangements inFIGS.3A and3Bis that the further pattern324is an IO pattern of a further circuit region350, in accordance with some embodiments. The further circuit region350is placed by the APR tool to be adjacent to the circuit region200. In some embodiments, the APR tool places the further circuit region350in abutment with the circuit region200. The APR tool integrates the circuit region200and the further circuit region350by extending the IO pattern222of the circuit region200with the extension pattern322until the extension pattern322overlaps the IO pattern324of the further circuit region350. FIG.3Cshows a further routing arrangement for the circuit region200, in accordance with some embodiments. InFIG.3C, to access, or electrically couple, to the power IO patterns225-227, the APR tool generates or routes, in the metal layer M5over the metal layer M4in which the power IO patterns225-227are arranged, an access pattern333. The access pattern333extends along the X-X′ direction, across an entire width of the circuit region200to overlap the power IO patterns225-227. The APR tool further generates, in the via layer VIA4, a plurality of vias335-337electrically coupling the access pattern333correspondingly to the power IO patterns225-227. As a result, the internal circuitry of the circuit region200is configured to receive power supply through the access pattern333and the power IO patterns225-227. FIG.3Dshows a further routing arrangement for the circuit region200, in accordance with some embodiments. A difference between the routing arrangements inFIGS.3C and3Dis that an access pattern343inFIG.3Dcorresponds to the access pattern333inFIG.3C, but extends instead along the Y-Y′ direction. The access pattern343extends across an entire height of the circuit region200in the Y-Y′ direction to overlap the power IO patterns225-227, and is electrically coupled to the power IO patterns225-227correspondingly by vias345-347. The routing arrangement inFIG.3Cis applicable when the metal layer M5has the horizontal metal direction, and the routing arrangement inFIG.3Dis applicable when the metal layer M5has the vertical metal direction. In at least one embodiment, the routing arrangements inFIGS.3A and3Care usable together, whereas the routing arrangements inFIGS.3B and3Dare usable together. The described routing arrangements are examples. Other routing arrangements are within the scopes of various embodiments. For example, in one or more embodiments, at least one of the access patterns311,331,333,343is arranged in a metal layer other than the metal layer M5, or in a metal layer not immediately adjacent to the metal layer of the IO pattern to be accessed. In some embodiments, an APR tool has at least two options for accessing an IO pattern. For example, as described with respect toFIG.3A, a first option is to access the IO pattern221by the access pattern311from an adjacent metal layer, e.g., the metal layer M5. A second option is to access the IO pattern221by an extension pattern on the same metal layer, e.g., the metal layer M4, in a manner similar to that described with respect to the IO pattern222. In at least one embodiment, multiple options for accessing an IO pattern provide routing flexibility and/or make it easier to integrate the circuit region200with other circuit regions in the IC device. One or more of these advantages are not observable or are difficult to achieve in other approaches that do not include oblique IO patterns. In some embodiments, regardless of the metal direction in a metal layer of the IC device that is to be used for integrating circuit regions, there is always an available option for the APR tool to perform integration. For example, in one or more embodiments where the metal layer (e.g., the metal layer M5) to be used for integration of circuit regions has the horizontal metal direction, the APR tool is configured to apply the routing arrangements described with respect toFIGS.3A and3C. In one or more embodiments where the metal layer (e.g., the metal layer M5) to be used for integration of circuit regions has the vertical metal direction, the APR tool is configured to apply the routing arrangements described with respect toFIGS.3B and3D. As a result, it is possible in at least one embodiment to use a circuit region, e.g., an IP block, with different metal schemes without having to revise the layout of the IP block to be compatible with a specific metal scheme the IP block is to be used with. It is also possible in one or more embodiments to integrate circuit regions with different built-in metal schemes. One or more of these advantages are not observable or are difficult to achieve in other approaches that do not include oblique IO patterns. In some embodiments, integration of adjacently placed circuit regions is possible simply by extending an IO pattern of one circuit region by an extension pattern until the extension pattern overlaps a corresponding IO pattern of another circuit region, and then arranging a via at the overlapping section to electrically couple the corresponding IO patterns. For example, as described with respect toFIG.3B, by simply extending the IO pattern222of the circuit region200by an extension pattern322until the extension pattern322overlaps a corresponding IO pattern324of another circuit region350, and then arranging a via326at the overlapping section, it is possible to electrically couple the corresponding IO patterns222and324and, hence, integrate the circuit region200and the further circuit region350. As a result, in at least one embodiment, it is easier to integrate circuit regions than in other approaches that do not include oblique IO patterns. FIG.3Eis a schematic cross-sectional view, taken along line E1-E2-E3-E4inFIG.3A, of an IC device300in accordance with some embodiments. The IC device300comprises a circuit region corresponding to the circuit region200described with respect toFIG.3A. The cross-section line E1-E2inFIG.3Aextends along the longitudinal center line of the access pattern311, and then along the longitudinal center line of the IO pattern221. The cross-section line E3-E4inFIG.3Aextends along the longitudinal center line of the IO pattern222and the extension pattern322, and then along the longitudinal center line of the further pattern324. Corresponding components inFIG.3AandFIG.3Eare indicated by the same reference numerals. In at least one embodiment, the IC device300corresponds to the IC device100. As shown inFIG.3E, the IC device300comprises a substrate302over which the circuit region200is formed. In at least one embodiment, the substrate302corresponds to the substrate102. N-type and P-type dopants are added to the substrate302to correspondingly form N wells351,352, and P wells (not shown). In some embodiments, isolation structures are formed between adjacent P wells and N wells. For simplicity, several features such as P wells and isolation structures are omitted fromFIG.3E. In at least one embodiment, the N wells351,352correspond to the active region201,202. The N wells351,352define source/drain regions of a transistor T. The N wells351,352are referred to herein as source/drain regions351,352. A gate region of the transistor T comprises a stack of gate dielectric layers353,354, and a gate electrode355. In at least one embodiment, the transistor T comprises a gate dielectric layer instead of multiple gate dielectrics. Example materials of the gate dielectric layer or layers include HfO2, ZrO2, or the like. Example materials of the gate electrode355include polysilicon, metal, or the like. In at least one embodiment, the gate electrode355of the transistor T corresponds to the gate region203,204. The transistor T is an example of a circuit element in the internal circuitry of the circuit region200. Contact structures for electrically coupling the transistor T to other circuit elements in the circuitry of the IC device300comprise metal-to-device (MD) regions356,357correspondingly over and in electrical contact with the source/drain regions351,352, and a via structure (not shown) over and in electrical contact with the gate electrode355. Further via-to-device (VD) via structures358,359are correspondingly over and in electrical contact with the MD regions356,357. An interconnect structure360is over the VD via structures358,359, and comprises a plurality of metal layers M0, M1, . . . and a plurality of via layers V0, V1, . . . arranged alternatingly in a thickness direction of the substrate302, i.e., along a Z-Z′ direction. The interconnect structure360further comprises various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The metal layers and via layers of the interconnect structure360are configured to electrically couple various elements or circuits of the IC device300with each other, and with external circuitry. In the example configuration inFIG.3E, the source/drain region351of the transistor T is electrically coupled to the IO pattern221in the metal layer M4through a via361in a via layer V2, a conductive pattern362in the metal layer M3, and a via363in a via layer V3. The access pattern311in the metal layer M5extends along the X-X′ direction from outside the boundary210of the circuit region200to inside the boundary210to overlap the IO pattern221. The IO pattern221is electrically coupled to the access pattern311through the via313, as described with respect toFIG.3A. The IO pattern222is electrically coupled to the internal circuitry of the circuit region200through one or more vias and/or conductive patterns in corresponding metal layers. For simplicity, the one or more vias and/or conductive patterns electrically coupled to the IO pattern222are omitted inFIG.3E. Further, although the IO patterns221,222have about the same position along the X-X′ direction inFIG.3A, the IO patterns221,222inFIG.3Eare shifted along the X-X′ direction for illustrative purposes. The extension pattern322is contiguous to the IO pattern222and extends from inside the boundary210of the circuit region200to outside the boundary210. The extension pattern322overlaps the further pattern324in the metal layer M3, and is electrically coupled by the via326to the further pattern324, as described with respect toFIG.3A. Other configurations are within the scopes of various embodiments. FIG.4Ais a schematic view of a core400, in accordance with some embodiments. In at least one embodiment, the core400comprises a circuit region, or a combination of circuit regions, over a substrate as described with respect toFIG.1. In at least one embodiment, the core400comprises an IP core. In at least one embodiment, the core400comprises a whole individual IC device. The core400comprises a core region410and a ring region412over the substrate (not shown), and at least one IO pattern arranged in the ring region412and configured to electrically couple the core region410to external circuitry outside the core400. The core region410comprises at least one active region extending along the X-X′ direction, and at least one gate region extending across the at least one active region and along the Y-Y′ direction, as described with respect toFIG.1. In at least one embodiment, the core region410comprises various active regions and gate regions coupled into one or more logics which configure internal circuitry of the core region410to perform intended functions of the core400. The ring region412extends around, or surrounds, the core region410. In at least one embodiment, the ring region412is free of logics, and comprises various nets that electrically couple the internal circuitry of the core region410to the at least one IO pattern. In at least one embodiment, in addition to the various nets that electrically couple the internal circuitry of the core region410to the at least one IO pattern, the ring region412further comprises IO circuits configured for data input/output, but not for data processing. For example, some IO circuits are configured to change signal voltages to levels suitable for the external circuitry and/or the internal circuitry of the core region410. In the example configuration inFIG.4A, the at least one IO pattern arranged in the ring region412comprises a plurality of first IO patterns413,414in a first metal layer Mj and a plurality of second IO patterns415,416in a second metal layer Mi, where i and j are natural numbers, and i<j corresponding to the metal layer Mj being higher or above the metal layer Mi. In at least one embodiment, the metal layer Mj and the metal layer Mi are consecutive metal layers, i.e., the metal layer Mj is immediately above the metal layer Mi. In at least one embodiment, the metal layer Mj and the metal layer Mi are not consecutive metal layers, i.e., the metal layer Mj is higher than the metal layer Mi with at least one further metal layer in between. In at least one embodiment, the metal layer Mj and the metal layer Mi are topmost metal layers of the core400. An IC device comprising the core400comprises higher metal layers over the topmost metal layers of the core400for integrating the core400with other circuit regions of the IC device. The first IO patterns413,414extend in the U-U′ direction that is oblique to both the X-X′ direction and the Y-Y′ direction. The second IO patterns415,416extend in the V-V′ direction that is also oblique to both the X-X′ direction and the Y-Y′ direction. The first IO patterns413,414and second IO patterns415,416are electrically coupled to the core region410by various nets (not shown). The core region410, first IO patterns413,414, and second IO patterns415,416are all arranged within a boundary422of the ring region412. The boundary422comprises sides423-426, among which sides424,426extend along the X-X′ direction, and sides423,425extend along the Y-Y′ direction. In at least one embodiment, the boundary422is a virtual periphery of the core400where the core400is arranged together with one or more other circuit regions over a substrate to form an IC device. In at least one embodiment, the boundary422is a physical periphery or edge of the core400where the core400is the whole IC device itself. Each of the first IO patterns413,414and the second IO patterns415,416extends toward a corresponding adjacent side of the boundary422at an acute angle. In the example configuration inFIG.4A, the first IO patterns413extend from the core region410outwardly toward the adjacent side423at an acute angle, the first IO patterns414extend from the core region410outwardly toward the adjacent side424at an acute angle, the second IO patterns415extend from the core region410outwardly toward the adjacent side425at an acute angle, and the second IO patterns416extend from the core region410outwardly toward the adjacent side426at an acute angle. The described configuration of the core400is an example. Other configurations are within the scopes of various embodiments. For example, in at least one embodiment, all IO patterns of the core400are arranged in one metal layer, or the IO patterns of the core400are arranged in more than two metal layers. In some embodiments where the IO patterns of the core400are arranged in three or more metal layers, the IO patterns have correspondingly three or more different metal directions. In at least one embodiment, IO patterns are not necessarily arranged along all sides of the ring region412. In one or more embodiments, one or more of the routing arrangements described with respect toFIGS.3A-3Dis/are applicable to route metal patterns to electrically couple to the IO patterns413-416for accessing internal circuitry of the core region410. In at least one embodiment, one or more advantages described with respect toFIGS.2and3A-3Dis/are achievable with the core400. FIG.4Bis a schematic view of a core430, in accordance with some embodiments. In at least one embodiment, the core430comprises a circuit region, or a combination of circuit regions, over a substrate as described with respect toFIG.1. In at least one embodiment, the core430comprises an IP core. In at least one embodiment, the core430comprises a whole individual IC device. A difference between the core400and the core430is that, in the core400, there is one layer of IO patterns along each side of the ring region412, whereas in the core430, there are two layers of IO patterns along each side of the ring region412. Compared to the core400, the core430additionally comprises first IO patterns435,436and second IO patterns433,434. The first IO patterns435,436are arranged in the metal layer Mj, and the second IO patterns433,434are arranged in the metal layer Mi. The second IO patterns433are arranged along the side423of the ring region412, overlap and are electrically coupled to the corresponding first IO patterns413by vias443. The second IO patterns434are arranged along the side424of the ring region412, overlap and are electrically coupled to the corresponding first IO patterns414by vias444. The first IO patterns435are arranged along the side425of the ring region412, overlap and are electrically coupled to the corresponding second IO patterns415by vias445. The first IO patterns436are arranged along the side426of the ring region412, overlap and are electrically coupled to the corresponding second IO patterns416by vias446. The vias443-446are in a via layer VIAi between the metal layer Mj and the metal layer Mi. In one or more embodiments, one or more of the routing arrangements described with respect toFIGS.3A-3Dis/are applicable to route metal patterns to electrically couple to the IO patterns413-416,433-436for accessing internal circuitry of the core region410in the core430. In at least one embodiment, one or more advantages described with respect toFIGS.2and3A-3Dis/are achievable with the core430. By arranging multiple layers of IO patterns along at least one side of the ring region412in accordance with some embodiments, there are more choices for accessing the IO patterns resulting in routing flexibility and/or making it easier to integrate the core430with other circuit regions in the IC device. FIGS.5A-5Eare schematic views showing various arrangements for integrating cores, in accordance with some embodiments. InFIG.5A, the core400and a core400′ are integrated in an overlapping manner into an integrated core500A, in accordance with some embodiments. In the example configuration inFIG.5A, the core400′ includes components corresponding to those of the core400. For simplicity, a component of the core400′ is indicated in the drawings by the same reference numeral of the corresponding component in the core400but with the prime symbol. In at least one embodiment, an APR tool is configured to integrate the core400and core400′ by placing the core400and core400′ so that the ring region412of the core400and the corresponding ring region412′ of the core400′ partially overlap each other in the Y-Y′ direction at an overlapped section542. The overlapped section542is defined between the side426′ of the core400′ and the side424of the core400after the overlapping placement of the cores400,400′. In the overlapped section542, the first IO patterns414of the core400are in the metal layer Mj and overlap the second IO patterns416′ of the core400′ which are in the metal layer Mi. The APR tool is configured to generate vias540in the via layer VIAi to electrically couple the corresponding and overlapping IO patterns414,416′. In at least one embodiment, the overlapping placement of the cores400,400′ makes it possible to quickly and easily integrate the cores400,400′ without using metal patterns in an additional metal layer. Further, the chip area occupied by the integrated core500A is advantageously reduced compared to a sum of the wafer areas occupied by the cores400,400′ individually. InFIG.5B, the core400and the core400′ are integrated in an abutment manner into an integrated core500B, in accordance with some embodiments. A difference from the arrangement inFIG.5Ais that, inFIG.5B, the APR tool places the cores400,400′ not in an overlapping manner, but in abutment. For example, the side424of the core400is placed by the APR tool to abut the side426′ of the core400′. The first IO patterns414of the core400and the second IO patterns416′ of the core400′ do not overlap, and are electrically coupled by corresponding access patterns545in a metal layer Mk and vias546,547in a via layer VIAj between the metal layer Mk and the metal layer Mj, where k is a natural number, and j<k corresponding to the metal layer Mk being higher or above the metal layer Mj. For simplicity, one access pattern545, one via546, and one via547are indicated inFIG.5Bfor one pair of corresponding IO patterns414,416′. The electrically coupling between each access pattern545and the corresponding IO patterns414,416′ is similar to the IO pattern access described with respect toFIG.3B. In at least one embodiment, one or more advantages described herein is/are achievable with the integrated core500B. The arrangements described with respect toFIGS.5A,5Bare examples of vertical core integration in which the cores400,400′ are integrated in the Y-Y′ direction. Other configurations are within the scopes of various embodiments. For example, in at least one embodiment, core integration includes extending an IO pattern of one of the cores400,400′, by an extension pattern, to extend into the ring region of the other core to a position where the extension pattern overlaps, and is electrically coupled by a via to, a corresponding IO pattern of the other core, as described with respect toFIGS.3A-3B. Other types of core integration, i.e., horizontal, diagonal, and three-dimensional core integration, are described herein. InFIG.5C, the core400and the core400′ are integrated in an overlapping manner into an integrated core500C, in accordance with some embodiments. A difference from the vertical core integration inFIG.5Ais that, inFIG.5C, the core integration is horizontal, i.e., in the X-X′ direction. In at least one embodiment, an APR tool is configured to integrate the core400and core400′ by placing the core400and core400′ so that the ring region412of the core400and the corresponding ring region412′ of the core400′ partially overlap each other in the X-X′ direction at an overlapped section552. The overlapped section552is defined between the side425′ of the core400′ and the side423of the core400after the overlapping placement of the cores400,400′. In the overlapped section552, the first IO patterns413of the core400are in the metal layer Mj and overlap the second IO patterns415′ of the core400′ which are in the metal layer Mi. The APR tool is configured to generate vias560in the via layer VIAi to electrically couple the corresponding and overlapping IO patterns413,415′. In at least one embodiment, one or more advantages described with respect toFIG.5Ais/are achievable with the integrated core500C. In at least one embodiment, the cores400,400′ are placed in abutment in the X-X′ direction, and are integrated using horizontal access patterns in an additional metal layer in a manner similar to that described with respect toFIG.5B. InFIG.5D, the core400and the core400′ are integrated in a diagonal core integration into an integrated core500D, in accordance with some embodiments. An APR tool is configured to place the cores400,400′ such that the first IO patterns413of the core400and the corresponding first IO patterns414′ of the core400′, which are in the same metal layer Mj, are aligned with each other. In at least one embodiment, this alignment is possible where the core400and the core400′ include the same metal scheme for the metal layer Mj, i.e., the same metal direction and the same pitch between adjacent metal patterns. A first IO patterns413of the core400and a corresponding first IO pattern414′ of the core400′ are aligned when their longitudinal center lines coincide. In the example configuration inFIG.5D, the alignment of the first IO patterns413and the corresponding first IO patterns414′ is achieved with the ring region412of the core400and the ring region412′ of the core400′ touch each other at a corner. Other arrangements are within the scopes of various embodiments. The APR tool generates one or more extension patterns563each extending along the same U-U′ direction as a corresponding pair of one first IO pattern413and one first IO pattern414′, contiguous to both the corresponding first IO pattern413and first IO pattern414′, to electrically couple the core region410to the core region410′. The APR tool is further configured to generate, in the metal layer Mj, one or more access patterns565each overlapping a corresponding pair of one second IO pattern416of the core400and one second IO pattern415′ of the core400′, which are in a different metal layer Mi. Each access pattern565is electrically coupled to the corresponding overlapped second IO pattern416and second IO pattern415′ at vias566,567in the via layer VIAi. InFIG.5D, for illustrative purposes, the extension patterns563and the access patterns565are illustrated differently from the first IO patterns413,414′ even though they are all arranged in the same metal layer Mj. In at least one embodiment, one or more advantages described herein is/are achievable with the integrated core500D. InFIG.5E, the core400and the core400′ are integrated in a three dimensional core integration into an integrated core500E, in accordance with some embodiments. The core400′ is rotated 180 degrees compared to the core400′ in the other drawings. For illustrative purposes, inFIG.5E, the core region410is referred to as Core1, the core region410′ is referred to as Core2, and the IO patterns of the core400′ are illustrated differently from the other drawings. The metal layers Mj, Mi corresponding to each of Core1, Core2are indicated with additional labels “Core1_,” “Core2_” inFIG.5E. When the cores400,400′ are three dimensionally integrated, the core400is arranged at the bottom and the core400′ is stacked on top of the core400. The stacking of the core400′ on top of the core400results in the IO patterns of the core400′ overlapping the IO patterns of the core400. For example, the second IO patterns415′ of the core400′ which, in the other arrangements described with respect toFIGS.5A-5D, are arranged at a metal layer below the first IO patterns413of the core400are now on top of the first IO patterns413. The overlapping second IO patterns415′ and first IO patterns413are electrically coupled by through substrate vias (TSVs)573. For another example, the first IO patterns413′ of the core400′ overlap the second IO patterns415of the core400, and are electrically coupled thereto by TSVs575. In at least one embodiment, the described three dimensional core integration is performed by an APR tool which generates an IC layout diagram for the integrated core500E based on which one or more physical IC devices are manufactured. In at least one embodiment, one or more advantages described herein is/are achievable with the integrated core500E. Further, the chip area is saved compared to when the cores400,400′ are arranged side-by-side or with partial overlapping, resulting in denser floorplan. FIG.6is a schematic sectional view of a 3D IC device600, in accordance with some embodiments. In at least one embodiment, the 3D IC device600corresponds to the integrated core500E described with respect toFIG.5E. The 3D IC device600comprises a substrate610over which Core1is formed. In at least one embodiment, the substrate610corresponds to the semiconductor substrate102and Core2comprises logics. The 3D IC device600further comprises a metallization layer612, which includes one or more metal layers starting from the M0layer and one or more via layers, and which is formed over Core1to electrically couple Core1to various corresponding IO patterns, for example, a first IO patterns413and a second IO pattern415as schematically illustrated inFIG.6. The first IO patterns413and a second IO pattern415are arranged in the ring region412. The 3D IC device600further comprises a substrate620over which Core2is formed. In at least one embodiment, the substrate620corresponds to the semiconductor substrate102, for example, when Core2comprises logics and the 3D IC device600comprises a logic-on-logic 3D IC structure. In one or more embodiments, the substrate620comprises an insulation layer, for example, when Core2comprises a metal-insulator-metal (MIM) capacitor arrays. The 3D IC device600further comprises a metallization layer622, which includes one or more metal layers and one or more via layers, and which is formed over Core2to electrically couple Core2to various corresponding IO patterns, for example, a first IO patterns413′ and a second IO pattern415′ as schematically illustrated inFIG.6. The first IO patterns413′ and a second IO pattern415′ are arranged in the ring region412′. The 3D IC device600further comprises TSVs573,575extending through the substrate620to electrically couple the corresponding IO patterns of Core1and Core2, as described with respect toFIG.5E. In at least one embodiment, one or more advantages described herein is/are achievable with the 3D IC device600. FIG.7Ais a flow chart of a method700A, in accordance with some embodiments. In at least one embodiment, method700A is performed in whole or in part by a processor as described herein. In at least one embodiment, the method700A is a method for accessing an IO pattern of an IP block in an IC layout diagram. At operation705, an intellectual property (IP) block is placed in an integrated circuit (IC) layout diagram. For example, as described with respect toFIGS.3A,3B, a circuit region200, which in one or more embodiments comprises an IP block, is placed by an APR tool into an IC layout diagram, in a placement operation. At operation715, an access pattern is generated in a first metal layer over the IP block. The access pattern extends from outside a boundary of the IP block to inside the boundary to overlap a first input/output (IO) pattern among a plurality of IO patterns of the IP block. For example, as described with respect toFIGS.3A,3B, an access pattern311or331is generated by the APR tool in a routing operation. The access pattern311or331is in a metal layer, e.g., the metal layer M5, over the IP block which has the metal layer M4as the topmost metal layer. The access pattern311or331extends from outside a boundary210of the IP block to inside the boundary210to overlap a first input/output (IO) pattern221among a plurality of IO patterns221-229of the IP block. The access pattern311,331and the first IO pattern221form an acute angle therebetween, as described and/or illustrated inFIGS.3A-3B. At operation725, a via is generated to electrically couple the overlapping access pattern and first IO pattern. For example, the APR tool generates a via313to electrically couple the access pattern311,331to the first IO pattern221. As a result the IO pattern221is electrically couplable, through the access pattern311,331, to external circuitry outside the IP block. In at least one embodiment, all operations705,715,725are automatically performed without user input or intervention. FIG.7Bis a flow chart of a method700B, in accordance with some embodiments. In at least one embodiment, the method700B is a method of manufacturing an IC device corresponding to an IC layout diagram in which an IO pattern of an IP block is accessed as described with respect toFIG.7A. At operation755, a circuit region is formed over a substrate, the circuit region corresponding to an intellectual property (IP) block. The circuit region comprises a boundary, and a plurality of input/output (IO) patterns inside the boundary. For example, as described with respect toFIG.3E, a circuit region200(with a representative transistor T) is formed over a substrate302. The circuit region200corresponds to an IP block in one or more embodiments, as described herein. Further, as described with respect toFIG.2, the circuit region comprises a boundary210, and a plurality of IO patterns221-227inside the boundary210. At operation765, a first via is formed over and electrically coupled to a first IO pattern among the plurality of IO patterns of the circuit region. For example, as described with respect toFIG.3E, a via313is formed over and electrically coupled to a first IO pattern221. At operation775, in a first metal layer over the first via, an access pattern is formed to extend from outside the boundary of the circuit region to inside the boundary to overlap and electrically contact the first via, and the access pattern and the first IO pattern form an acute angle therebetween. For example, as described with respect toFIG.3E, in a metal layer M5over the first via313, an access pattern311is formed to extend from outside the boundary210of the circuit region200to inside the boundary210to overlap and electrically contact the first via313which electrically couples the access pattern311to the first IO pattern221of the circuit region200. As described with respect toFIG.3Athe access pattern311and the first IO pattern221form an acute angle therebetween. In some embodiments, as described with respect toFIG.3E, before forming the first via313, a further pattern324is formed in a second metal layer, e.g., the metal layer M3, over the substrate302. The further pattern324is outside the boundary210of the circuit region200. A second via326is formed over and electrically coupled to the further pattern324. In a third metal layer, e.g., the metal layer M4, over the second via326, the plurality of IO patterns221-227are formed and an extension pattern322is also formed. The extension pattern322is contiguous to a second IO pattern222among the plurality of IO patterns221-227, and extends from inside the boundary210of the circuit region200to outside the boundary210where the extension pattern322overlaps and is electrically coupled to the second via326. As described with respect toFIG.3A, the extension pattern322extends transversely to and overlaps the further pattern324, and the access pattern311and the further pattern324form an acute angle therebetween. In at least one embodiment, one or more advantages described herein are achievable in the IC device manufactured in accordance with the method700B. FIG.8is a flow chart of a method800, in accordance with some embodiments. In at least one embodiment, method800is performed in whole or in part by a processor as described herein. In at least one embodiment, the method800is a method for integrating cores in an IC layout diagram. At operation805, a first core is placed in an integrated circuit (IC) layout diagram. The first core has at least one first IO pattern in a first ring region, which extends around the first core in a first direction and a second direction. The first IO pattern is oblique to both the first direction and the second direction. For example, the APR tool is configured to place a core400in an IC layout diagram. As described with respect toFIG.4A, the core400has one or more IO patterns413-416in a ring region412, which extends around the core400in the X-X′ direction and Y-Y′ direction. The IO patterns413-416are oblique to both the X-X′ direction and the Y-Y′ direction. At operation815, a second core is placed in the IC layout diagram. The second core has at least one second IO pattern in a second ring region, and the second IO pattern is oblique to both the first direction and the second direction. For example, the APR tool is configured to place a core400′ in an IC layout diagram. As described with respect toFIG.5A, the core400′ has one or more IO patterns413′-416′ in a ring region412′, and the IO patterns413′-416′ are oblique to both the X-X′ direction and the Y-Y′ direction. At operation825, the first core and the second core are integrated in any of several arrangements. In a first arrangement, the first core and the second core are integrated by overlapping the first IO pattern and the second IO pattern, and electrically coupling them by a via. For example, as described with respect toFIGS.5A,5C,5E, the cores400,400′ are integrated by overlapping, and electrically coupling using a via, one or more of the first IO patterns413-416of the core400and corresponding one or more of the second IO patterns413′-416′ of the core400′. In a second arrangement, the first core and the second core are integrated by generating a linear extension pattern contiguous to both the first IO pattern and the second IO pattern. For example, as described with respect toFIG.5D, the APR tool is configured to generate linear extension patterns563each contiguous to a first IO pattern413and the corresponding second IO pattern414′. As a result, the first IO pattern413and the corresponding second IO pattern414′ are electrically coupled, which corresponds to integrating the cores400,400′. In a third arrangement, the first core and the second core are integrated by generating a linear access pattern overlapping and electrically coupled by vias to both the first IO pattern and the second IO pattern. For example, as described with respect toFIG.5D, the APR tool is configured to generate linear access patterns565each overlapping and electrically coupled by vias566,567to a first IO pattern416and the corresponding second IO pattern415′. As a result, the first IO pattern416and the corresponding second IO pattern415′ are electrically coupled, which corresponds to integrating the cores400,400′. In at least one embodiment, all operations805,815,825are automatically performed without user input or intervention. The described methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure. In some embodiments, at least one method(s) discussed above is performed in whole or in part by at least one EDA system. In some embodiments, an EDA system is usable as part of a design house of an IC manufacturing system discussed below. FIG.9is a block diagram of an electronic design automation (EDA) system900in accordance with some embodiments. In some embodiments, EDA system900includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system900, in accordance with some embodiments. In some embodiments, EDA system900is a general purpose computing device including a hardware processor902and a non-transitory, computer-readable storage medium904. Storage medium904, amongst other things, is encoded with, i.e., stores, computer program code906, i.e., a set of executable instructions. Execution of instructions906by hardware processor902represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Processor902is electrically coupled to computer-readable storage medium904via a bus908. Processor902is also electrically coupled to an I/O interface910by bus908. A network interface912is also electrically connected to processor902via bus908. Network interface912is connected to a network914, so that processor902and computer-readable storage medium904are capable of connecting to external elements via network914. Processor902is configured to execute computer program code906encoded in computer-readable storage medium904in order to cause system900to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor902is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium904is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium904includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium904includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium904stores computer program code906configured to cause system900(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium904stores library907of standard cells including such standard cells as disclosed herein. EDA system900includes I/O interface910. I/O interface910is coupled to external circuitry. In one or more embodiments, I/O interface910includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor902. EDA system900also includes network interface912coupled to processor902. Network interface912allows system900to communicate with network914, to which one or more other computer systems are connected. Network interface912includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems900. System900is configured to receive information through I/O interface910. The information received through I/O interface910includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor902. The information is transferred to processor902via bus908. EDA system900is configured to receive information related to a UI through I/O interface910. The information is stored in computer-readable medium904as user interface (UI)942. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system900. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.10is a block diagram of an integrated circuit (IC) manufacturing system1000, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1000. InFIG.10, IC manufacturing system1000includes entities, such as a design house1020, a mask house1030, and an IC manufacturer/fabricator (“fab”)1050, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1060. The entities in system1000are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050is owned by a single larger company. In some embodiments, two or more of design house1020, mask house1030, and IC fab1050coexist in a common facility and use common resources. Design house (or design team)1020generates an IC design layout diagram1022. IC design layout diagram1022includes various geometrical patterns designed for an IC device1060. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1060to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1022includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1020implements a proper design procedure to form IC design layout diagram1022. The design procedure includes one or more of logic design, physical design or place-and-route operation. IC design layout diagram1022is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1022can be expressed in a GDSII file format or DFII file format. Mask house1030includes data preparation1032and mask fabrication1044. Mask house1030uses IC design layout diagram1022to manufacture one or more masks1045to be used for fabricating the various layers of IC device1060according to IC design layout diagram1022. Mask house1030performs mask data preparation1032, where IC design layout diagram1022is translated into a representative data file (“RDF”). Mask data preparation1032provides the RDF to mask fabrication1044. Mask fabrication1044includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1045or a semiconductor wafer1053. The design layout diagram1022is manipulated by mask data preparation1032to comply with particular characteristics of the mask writer and/or requirements of IC fab1050. InFIG.10, mask data preparation1032and mask fabrication1044are illustrated as separate elements. In some embodiments, mask data preparation1032and mask fabrication1044can be collectively referred to as mask data preparation. In some embodiments, mask data preparation1032includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1022. In some embodiments, mask data preparation1032includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, mask data preparation1032includes a mask rule checker (MRC) that checks the IC design layout diagram1022that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1022to compensate for limitations during mask fabrication1044, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, mask data preparation1032includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1050to fabricate IC device1060. LPC simulates this processing based on IC design layout diagram1022to create a simulated manufactured device, such as IC device1060. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1022. It should be understood that the above description of mask data preparation1032has been simplified for the purposes of clarity. In some embodiments, data preparation1032includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1022according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1022during data preparation1032may be executed in a variety of different orders. After mask data preparation1032and during mask fabrication1044, a mask1045or a group of masks1045are fabricated based on the modified IC design layout diagram1022. In some embodiments, mask fabrication1044includes performing one or more lithographic exposures based on IC design layout diagram1022. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1045based on the modified IC design layout diagram1022. Mask1045can be formed in various technologies. In some embodiments, mask1045is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1045includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1045is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1045, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1044is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1053, in an etching process to form various etching regions in semiconductor wafer1053, and/or in other suitable processes. IC fab1050is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1050is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. IC fab1050includes fabrication tools1052configured to execute various manufacturing operations on semiconductor wafer1053such that IC device1060is fabricated in accordance with the mask(s), e.g., mask1045. In various embodiments, fabrication tools1052include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein. IC fab1050uses mask(s)1045fabricated by mask house1030to fabricate IC device1060. Thus, IC fab1050at least indirectly uses IC design layout diagram1022to fabricate IC device1060. In some embodiments, semiconductor wafer1053is fabricated by IC fab1050using mask(s)1045to form IC device1060. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1022. Semiconductor wafer1053includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1053further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Details regarding an integrated circuit (IC) manufacturing system (e.g., system1000ofFIG.10), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. In some embodiments, an integrated circuit (IC) device comprises a substrate and a circuit region over the substrate. The circuit region comprises at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction. In some embodiments, an integrated circuit (IC) device comprises a substrate, a first core region over the substrate, a first ring region over the substrate and surrounding the first core region, and at least one first input/output (IO) pattern in the first ring region. The first core region comprises at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. The first IO pattern is configured to electrically couple the first core region to external circuitry outside the first core region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction. In some embodiments, a method comprises forming a circuit region over a substrate, the circuit region corresponding to an intellectual property (IP) block. The circuit region comprises a boundary, and a plurality of input/output (IO) patterns inside the boundary. The method further comprises forming a first via over and electrically coupled to a first IO pattern among the plurality of IO patterns of the circuit region. The method further comprises forming, in a first metal layer over the first via, an access pattern which extends from outside the boundary of the circuit region to inside the boundary to overlap and electrically contact the first via. The access pattern and the first IO pattern form an acute angle therebetween. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 81,137 |
11943940 | DETAILED DESCRIPTION Referring more specifically to the drawings, for illustrative purposes, embodiments of apparatus, system and methods for nucleic acid based cross-wire memory structures are generally shown. Several embodiments of the technology are described generally inFIG.1AtoFIG.4to illustrate the characteristics and functionality of the devices, methods and systems. It will be appreciated that the methods may vary as to the specific steps and sequence and the systems and apparatus may vary as to structural details without departing from the basic concepts as disclosed herein. The method steps are merely exemplary of the order that these steps may occur. The steps may occur in any order that is desired, such that it still performs the goals of the claimed technology. To effectively implement a high-density, cross-wire system from DNA there are two primary capabilities: a) it must be possible to encode and read specific digital values from the conductance to create memory elements, and b) it must be possible to interconnect these elements with highly conductive, small width interconnects. These interconnects would be “wires” that display a large conductance over long distances to ensure that i) the conductance of the memory elements dominate the conductance of the system, and ii) that the readout can be sufficiently fast to allow these systems to be introduced as Random Access Memories (RAMs) that can be implemented near or within the overall CPU architecture to improve computation. These capabilities are met with a simple memory element design with bit elements with controllable conductance characteristics. Turning now toFIG.1AandFIG.1B, one embodiment of an electrically readable, 4×4 element, 32-bit, nucleic acid X-wire ROM (Read Only Memory) platform 10 is shown schematically and is used to illustrate the technology. The platform 10 can be useful in a variety of systems such as for long-term storage or look-up-tables for time consuming calculations such as logarithms. For simplicity, the platform ofFIG.1Adepicts four lower wires 12 and four upper wires 16 oriented cross ways at right angles to each other. However, the upper and lower nanowires or structures can be can be different shapes, non-uniform sizes and may be oriented at oblique angles to each other. In this illustration, each of the lower nanowires 12 are electrically coupled to an electrode 14. Each of the upper overlapping nanowires 16 are also mounted to their own electrodes 18 that are supported by a substrate 20. The electrodes 14, 20 are in contact with appropriate circuits (not shown) for memory read-out. The nucleic acid-based memory technology is interfaced with conventional semiconductor technologies and the information can be directly accessed electrically. Memory elements 22 are formed at the junctions between overlapping nanowires or nanostructures. In the side view of the memory element 22 shown inFIG.1B, it can be seen that the lower nanowire 12 and the overlapping upper nanowire 16 are interconnected together at the junction by one or more memory DNA or RNA based nanostructures 24 that encodes bits. The number of connections, length and sequence of the memory nanostructures 24 dictates conductance and memory value. Different bit-values can be encoded into the memory elements 22 by controlling the physical properties of the nucleic acid nanostructure 24 by selection of sequence, length, conformation, doping, and number of pathways. FIG.2shows an idealized version of the structure ofFIG.1AandFIG.1Bthat has a set of 2-bit encoded memory elements interconnected with nucleic acid-based nanowires. Here, specific sequences are identified that can be used to encode a 2-bit (4-level) architecture that covers 4 orders of magnitude of conductance. This is feasible because nucleic acids such as DNA are conductors in which carriers are often delocalized over several bases at a time. To set these bit values modulating the conductance values between approximately 1×10−6G0and approximately 0.01 G0is preferred. By controlling the electronic structure of DNA memory nanostructures and nanowires, for example, 4 DNA duplexes of similar lengths (˜20 bp to 200 bp) that have conductance values that are each separated by 1 order of magnitude can be organized. In the scheme ofFIG.2, it is possible to read multi-level logic states (i.e. conductance values related to 00, 01, 10, and 11) from the combined system. To achieve this, in one embodiment, contact is made with the electrodes of all four legs of the X-wire device using standard lithography and substrates 20. For example, post-deposition electron beam lithography can be used to make contact after the X-wires have been deposited. In another embodiment, thiolated single-strand linkers are used on each of the 4-electrodes. Each of the electrodes can be programmed with a different sequence by controlling the potentials on the electrodes during assembly. In the preferred embodiment, each of the DNA-nanowires at the end of the X-wire junction will have a sticky end that is complementary to a single electrode. The nanowires are then allowed to self-assemble on the surface in the presence of the functionalized electrodes. Employing a large number of electrode sets on the surface will ensure successful measurements and will allow for a statistical analysis of the variability of the structures. Obviously, for a memory system to be functional, the position of the bit-values cannot be randomly determined during the self-assembly process. These systems must be addressable. Fortunately, DNA is an ideal tool for structural programming, even using short 10 bp sticky-ends to link memory elements to DNA-nanowires would allow for 410unique combinations (addresses). In fact, a variety of lengths can be used, along with parallel sticky-ends at the interface, opening up an extremely large design space for controlling the location of specific bit-values. Referring back toFIG.2, the control of the characteristics of the 2-bit memory elements connected with nucleic acid nanowires with 4 orders of magnitude of conductance provide an encoding scheme. In principle, Element j and Element k shown in the illustration ofFIG.2are identical as each encodes a 00-bit. However, each of these bits have unique nearest-neighbors, and in order to ensure that each address encodes the proper bit-value in the final structure, these two elements must actually be different physically even though they encode the same digital value.FIG.2illustrates all of the possible values for the 00-bit, which result in 256 different memory elements that all encode the same digital value. Also, since there are 4 possible digital values (00, 01, 10, and 11), 1024 unique memory elements are needed to encode all possible linkages for a 2-bit logic system. In addition, each of the nanowires that interconnects the memory elements should also be specific, resulting in another 16 elements. Thus, a complete design will require at least 1040 unique nucleic acid structures for implementation. In one embodiment, each element may need to be completely unique to limit the growth process to ensure that each element only attaches at the desired locations i.e. at a unique address. This would require optimal sequence design algorithms that minimize unwanted interactions. Therefore, for a given ROM pattern, the system will encode each memory element not only with a bit-value, but with an address as well to allow them to self-assemble into the correct structure. The crossed nanostructured platform is preferably formed on an arbitrarily sized, recessed, electrode arrays on a SiO2or Si3N4insulated substrate to ensure that the memory elements can be properly read in an electrical architecture. In this embodiment, the nanostructured materials are deposited on a planar surface that provides better electrical contact and reduces shearing forces at the electrode/nanostructure interface that often causes materials to rupture or inhibits transport. It is also possible to direct the assembly of the memory elements or array using either electrically-assisted methods (e.g. dielectrophoresis), or chemical direction (modifying surface interactions using thiols, hydroxyls, carboxylic acids, etc. on the surfaces. For example, these surface modifications can be controlled lithographically for precision placement. Using these structures, preliminary electrical measurements on nucleic acid nanowires indicated that even over distances of −10 μm currents in the pA range can be obtained. Moreover, these devices increase in conductance when conductivity is enhanced or optimized with intercalators or metals are used to dope the devices. This indicates that these structures have inherent long-range transport properties at room temperature. The preferred approaches for constructing nucleic acid nanostructures fall into two categories: the folding of a long strand (often called “DNA origami”) and the assembly of modular units called DNA tiles. Nucleic acid origami folding can create arbitrary two-dimensional nanoscale objects. A long scaffold strand (typically a M13 viral genomic DNA, ˜7 k bases) is folded into a prescribed shape by interacting with approximately 100 to 200 synthetic “staple” strands. Each staple strand is programmed with unique sequences and occupies a specific position in the final shape. In order to generate a custom-shaped nanostructure, one simply needs to raster-fill the shape with scaffold strands and then generate complementary staple sequences accordingly. The origami method was later extended for making 3D nanostructures. DNA origami is the first DNA self-assembly approach that allowed the building of arbitrarily-shaped, large (seven thousand base-pairs), addressable (each staple is unique) nanostructures. Another example is a modular strategy that can efficiently assemble large DNA-origami monomers into larger polyhedral structures. DNA-brick and DNA-origami modular assembly approaches can be extended for constructing microscale two-dimensional DNA crystalline structures and DNA nanowires. The 1D DNA nanowire design is based on discrete three-dimensional DNA brick structures, by implementing “connecting bricks” between discrete DNA brick structures. The nucleic acid nanowire can typically grow to several micrometers in length. In comparison, DNA-tile self-assembly is typically a two-step hierarchical process. The first step involves the formation of DNA tiles, which normally consists of a few to dozens of short synthetic DNA strands. Individual DNA tiles then connect to others through hybridization between complementary single stranded overhangs (“sticky ends”). A special type of DNA tile called a “single-stranded-tile (SST)” or “DNA brick” have been successfully used for assembling large 2D structures and 3D structures. The successes of the complex self-assembly that uses only short strands (as in DNA bricks) and those that includes a long scaffold (as in DNA origami) together suggest a full spectrum of motif possibilities with strands of diverse lengths: longer strands may provide better structural support, and shorter strands have finer modularity and features are available for use with controlled wire and memory bit conductivity. There are two general methods for creating conductive nanowires from DNA. The first involves using nucleic acids as a template to grow either inorganic or conducting polymer-based nanowires. These techniques typically involve binding to a catalyst for wire growth or a sticky end that can attach to an appropriately functionalized nanoparticle. These approaches have had success in creating conducting channels with a shape defined by the underlying nucleic acid nanostructure. However, they can suffer from low overall conductivity if the grains in the wire are not well coupled. Thus, the growth process must be carefully controlled to result in high conductivity. The second approach is to dope the nucleic acid using either intercalators or metal ions to improve the native conductivity of the material. While the second approach maintains the size of the nucleic acid nanostructures, it allows for a more straightforward implementation of the cross-wire architecture without needing to assemble around inorganic wires. Either approach can be implemented to ensure higher conductance wires. Another aspect of optimization and control over conduction is the enhancement of conductivity of the nucleic acid structures with one of three approaches: 1) metal ion doping; 2) doping with metal nanoparticles; and 3) doping with intercalators. One approach to doping the nucleic acids focuses on inserting metal ions at specific locations within the nucleic acid stack by using either modified bases to bind metal ions, or by using mismatches to ligate a metal ion to improve stability. For instance, in one embodiment, the use of a salicylic aldehyde-salicylic aldehyde pair in place of two complementary bases (one base on each strand), allows the DNA duplex to bind a range of metal ions including Cu2+, Fe3+, and Ag+. Alternatively, a T-T mismatch is known to bind Hg2+. These alternative pairing schemes may be used at specific locations in the DNA nanostructures by including these bases (and base substitutes) in the design of the DNA bricks described above. Conductance can be modulated when ions are spaced by every 3, 5, 7, or 9 base pairs, or quasi-randomly spaced. Another enhancement to conductivity of nucleic acids may be with the association of metal nanoparticles with the DNA, RNA or hybrid nanowire. For example, in one embodiment, gold nanoparticles, including spherical nanoparticles and nanorods, can be incorporated into DNA nanostructures to optimize the conductance. It is possible to attach controlled numbers of gold nanoparticles to DNA nanowires in a tight one-dimensional arrangement. The alignment of gold nanorods can be accomplished via a facile and robust hybridization between free DNA “sticky-ends” exposed on the DNA nanowires and complimentary DNA strands bound to the gold nanoparticles. The alignment of gold nanoparticles can be optimized by tuning the reaction conditions (e.g. concentrations, reaction time), and the design (e.g. DNA lengths and sequences). Similarly, the nucleic acid nanowires can be modified using conductive carbon dopants such as carbon nanotubes, carbon nanorods, carbon black, graphene sheets, graphene nanoribbons, and carbon nanofibers. Conductive carbon dopants can be used alone or with other dopants such as metal nanoparticles. Alternatively, conductivity can be enhanced and controlled through improving the inherent transport properties of DNA using DNA intercalators and groove-binding molecules to dope the nucleic acid nanostructures. Intercalators are molecules that insert into the DNA Tr-stack. An example of the conductance of a DNA sequence without an intercalator is shown inFIG.3Aand the same sequence with an intercalator is shown inFIG.3B. These demonstrate that adding an anthraquinone-based intercalator to DNA changes the energy gap between the Highest Occupied Molecular Orbital (HOMO) and Lowest Unoccupied Molecular Orbital (LUMO) from approximately 3.7 eV to approximately 1.5 eV. In addition to this significant decrease in the energy gap, the energy levels are more delocalized over the entire length of the nucleic acid. These changes to the electronic structure result in an experimentally determined conductance value that is 3 orders of magnitude higher for a 15-basepair (bp) sequence with the intercalator present over the sequence alone as shown inFIG.3AandFIG.3B. Given this substantial change in the transport properties, and, the relative ease of introducing these molecules into DNA-nanostructures, the use of intercalators are suitable for controlling or optimizing the transport properties of the DNA-nanowires. Several different intercalators can be selected to control conductance. Molecules with low redox potentials, such as anthraquinone and methylene blue, are preferred as these add energy levels near the Fermi potential of the Au electrodes. Additionally, the selection of intercalators can include classes of molecules aimed at lowering the LUMO level (such as anthraquinone), and classes of molecules aimed at increasing the HOMO level (such as methylene blue). After an initial examination of both classes, the best performers in each class can be used in tandem to further reduce the HOMO-LUMO energy gap of the system. The overall goal is to introduce enough additional states, with sufficient proximity to one another (both spatially and energetically) to approach long-range quasi-ballistic transport in the DNA nanowires. In another embodiment, a Programmable ROM (PROM) is provided. The metal ion or intercalator dopants are chosen, in-part, because of their redox or electroactive switching properties. Dopants that can be reduced or oxidized by the applied current will change the charge state. Changing the charge states of these systems changes the conductance, and thereby provides a mechanism for writing a digital value. Preferred redox or electroactive switching molecules or nanoparticles include Au, PbS, PbSe, Ge, and Ag. The charge state of the nanoparticle can change the resistance. One phenomenon that causes this is Coulomb Blockade. Preferred electroactive switching molecules include Methylene Blue, Ferrocene, Anthraquinone, Norbornadiene, and various fluorophores. A combination of these approaches will allow the identification of specific sequences that can be used to encode a 2-bit (4-level) architecture that covers 4 orders of magnitude of conductance, for example. Distinct conductance or resistance states can be engineered by designing specific DNA sequences, structures and enhances structures. Single-molecule break-junction (SMBJ) and lithographically-based conductance measurements reveal that the conductance is sensitive to the sequence, length and conformation. The results show that increasing the number of G:C (guanine:cytosine) base pairs in the stack causes a systematic increase in the resistance regardless of the conformation (A-form or B-form). The DNA can be switched between these conformations in situ by controlling the environment, and the A-form is consistently about 8 times lower in resistance than the B-form. This surprising result is due to increased delocalization of the HOMO levels in the A-form. It has also been established that the conductance is sensitive to a single-base mismatch in both double stranded DNA and DNA:RNA hybrids, for example. It is also interesting to note that some mismatches have a conductance that is too small to measure, giving it a very distinctive resistance value to use as a potential memory element. Overall, the results on different DNA and DNA:RNA systems demonstrate approximately 3 orders of magnitude change in conductance depending on both length and sequence. This implies that it is possible to directly identify two sequences with very different conductance values that could be used to encode a single bit (0 and 1) directly. For instance, the sequence 5′-GCGCGCGC-3′ (plus complement) has a conductance of about 1×10−3G0, where SEQ ID NO: 1 (plus complement) has a conductance of about 7×10−6G0(G0is the conductance quantum). The significant difference between these two sequences can be used for initial single bit memory element designs. One intriguing feature of DNA from an electronics standpoint is its 1D, quantum transport properties. While there have been differences of opinion about whether individual bases in DNA behave as independent hopping sites, it has recently become clear that charge carriers are often delocalized over several bases within the stack, as can be seen from the observed distributed HOMO levels. Studies on short DNA duplexes have indicated that in GC systems, transport occurs via delocalized states on the oligonucleotide chain while short AT base pairs provide a tunneling barrier. Taking advantage of the quantum transport properties of DNA or other nucleic acids or hybrids will provide additional control over simply modifying only the length of DNA or number of interlinking strands and allow the design of sequences where the resistances can be controlled at various values (beyond two) for multi-bit storage. Manipulation of the effects of the quantum mechanical nature of charge transport in DNA will also allow the development of multi-bit memory elements capable of overcoming the sneak-path problem noted below. In order to clearly distinguish between two conductance-encoded digital values, their conductance values must be significantly separated. As noted above, one important issue to developing a cross-wire based resistive memory array is ensuring that the resistances can be properly read. The concern is that if a voltage is applied to one horizontal line and the current is measured from one vertical line to read a single element, then there are other possible pathways that can contribute to the overall current that is read. If the memory element has a high resistance, then these other pathways with lower resistance can dominate the current and misread the value as a result. From an architectural perspective, this issue can be circumvented by connecting a diode in series with the memory element lying between the vertical and horizontal nanowires. In the nanoscale memories proposed so far, these diodes lead to two difficulties. First, they lower the memory density because of the area occupied by the diode, and second, they increase fabrication complexity because the memory elements are based on a new technology while the diode are based on silicon. The advantage of the DNA technology proposed here is that it is possible to program the self-assembly process to include a DNA based diode element in series with the DNA-based memory element between the vertical and horizontal nanowires. Modeling by MPA shows that the sequence SEQ ID NO: 2 will serve as a diode (as a result of the ionization potential difference between the G's and T's). It has also been demonstrated that coralyne intercalators or alternative bases can provide this rectification. In the embodiment shown inFIG.4, one DNA memory element 24 has a combination of DNA sequences 26 capable of encoding digital values with a DNA diode-resistive sequence 28 in a system with multiple, parallel paths. The memory elements can be functionalized with gold nanoparticles 30 or nanorods. The technology described herein may be better understood with reference to the accompanying examples, which are intended for purposes of illustration only and should not be construed as in any sense limiting the scope of the technology described herein as defined in the claims appended hereto. Example 1 To demonstrate the functionality of DNA-origami nanowire fabrication methods, an approximately 1.25 μm long DNA-origami nanowire was designed and fabricated by an end-to-end hierarchical assembly of five 10HB bundles of DNA nanorods. The 10HB DNA nanorod monomer was selected as the building block because of its increased rigidity and longer persistence length compared to nanorod designs with fewer helix bundles. The 10HB nanorod monomer was designed in caDNAno and verified by transmission electron microscopy (TEM). Selected staple strands were modified with a handle domain extension complimentary to a fluorescence-dye-labelled DNA strand to incorporate multiple fluorescence dyes for fluorescence microscopy imaging. To create the 1.25 μm DNA-origami nanowire, five 10HB nanorod monomers were connected together by outfitting five identical nanorod samples with a pair of unique sticky ends. With each nanorod bearing 24 handle extensions, a total of 120 fluorophores could be incorporated into each nanowire. Additionally, five capture handles for a thiol modified DNA strand extend from either end of the pentamer nanowire (the first 10HB nanorod monomer and the last 10HB nanorod monomer) to enable immobilization of the wires onto gold substrates. The five 10HB nanorod monomers were assembled separately in buffer and then mixed together at equal concentration to create the 1.25 μm DNA-origami nanowire, which was then purified by native agarose gel electrophoresis. Purified DNA nanowire was imaged by TEM (under dry conditions) and fluorescence imaging in aqueous solution. The overall morphology of the DNA nanowire was clearly confirmed in the TEM images. Fluorescence microscopy, including total internal reflection fluorescence (TIRF) microscopy and epifluorescent microscopy, also verified the successful assembly of the DNA nanowire under native condition in aqueous solution. After creating the DNA origami-based nanowire structures they were placed on a surface of a substrate and in contact with electrodes. The nanowires were placed on a substrate for initial electrical characterization, and on a second substrate for precision placement using Dielectrophoresis. First, the thiol- and fluorescent-modified DNA origami structures described above were placed on an electrode array chip for electrical characterization. This structure allowed testing of the initial conductance values of the DNA and to test conductance modification schemes (doping, intercalation, etc.). The electrodes were recessed into the substrate (oxide or nitride insulating layer) to create a planar structure for the DNA Nanowire to sit across. The DNA nanowires were placed on the surface by incubating the surface in a solution of nanowires after carefully cleaning the surface. Because of the fluorescent modifications to the DNA nanowires, they were able to be imaged via fluorescence microscopy to determine which sets of electrodes are bridged by DNA nanowires for electrical characterization. The resistance of the DNA nanowire was shown to decrease by incubating the system with an intercalator with favorable electrical properties (an anthraquinone based intercalator was used here). This demonstrated that the DNA nanowire conductance can be tuned over a large range. Example 2 To further demonstrate the operational principles of the apparatus and methods, modified and unmodified DNA nanowires of different sequences and lengths were evaluated. DNA conductance values can span a large range to allow multiple bits to be stored within each X-wire junction was demonstrated. The effects of intercalation, metal ion doping and metal nanoparticles on the conductance of the DNA nanowires was determined by comparing the conductance of native and modified nanowires. Conductance values of two examples of DNA nanowires differed by nearly 3 orders of magnitude are shown inFIG.3AandFIG.3B. In this case the sequence is the same, but an intercalator was used in the higher-conductance case to change the resistance. These measurements directly demonstrate sufficient separation of conductance values of short DNA systems to serve as memory elements. For example, these two elements could be used as a 0 and 1 respectively, but other modifications and various changes in sequence could be used to allow the coding of multiple bits per junction (e.g. 4-values 00, 01, 10, 11). Example 3 To further demonstrate the operational principles of the apparatus and methods, precision placement of the DNA nanowires on a substrate was demonstrated with a variety of schemes. Dielectrophoretic trapping was used to illustrate one preferred approach to positioning of DNA nanowires. In this approach, a high frequency (MHz range) AC field was applied between two electrodes. Because the DNA+counterion system is polarizable, the AC field induces a polarization which creates a force on the DNA that is parallel to the field gradient. Consequently, the DNA origami element is driven toward the source of the driving field. A chip for performing dielectrophoresis was used that concentrates the field gradient in the area of interest. A 6 MHz AC field, amplitude between 0.7 V and 1.0 V, was applied for 6 to 11 minutes to the junctions to trap and orient DNA-origami based nanowires. Fluorescent images of dielectrophoretically trapped DNA-origami based nanowires were observed. The optimum electrical conditions to trap DNA (and recognize the binding due to the change in the dielectric response of the junction) was identified. It was possible to concentrate the DNA in the junction between the two electrodes and to obtain only a small number of DNA-origami between the electrodes. Continued optimization allowed trapping of a single DNA nanowire. From the description herein, it will be appreciated that that the present disclosure encompasses multiple embodiments which include, but are not limited to, the following: 1. A cross-wire memory apparatus, comprising: (a) a first plurality of nucleic acid-based nanowires; (b) a second plurality of nucleic acid-based nanowires; wherein each nanowire in the first plurality of nucleic acid-based nanowires crossing over a nanowire in the second plurality of nucleic acid-based nanowires; and (c) a plurality of conductive memory elements, each the memory element connecting a first nanowire with a second nanowire; wherein each the memory element having a controlled conductance to encode a data bit. 2. The apparatus of any preceding or following embodiment, further comprising: a substrate; and a plurality of electrodes mounted to the substrate; wherein a first end of the nucleic acid-based nanowire is mounted to one electrode and a second end of the nucleic acid-based nanowire is mounted to a separate electrode. 3. The apparatus of any preceding or following embodiment, wherein the nucleic acid-based nanowires are assembled from a nucleic acid selected from the group of nucleic acids consisting of DNA, RNA, threose nucleic acid (TNA), peptide nucleic acid (PNA) Glycol nucleic acid (GNA), locked nucleic acid (LNA), bridged nucleic acid (BNA) and phosphorodiamidate morpholino oligomer (PMO). 4. The apparatus of any preceding or following embodiment, the nucleic acid-based nanowires further comprising conductive metal nanoparticles coupled to the nanowires. 5. The apparatus of any preceding or following embodiment, the nucleic acid-based nanowires further comprising conductive carbon coupled to the nanowires selected from the group consisting of carbon nanotubes, carbon nanorods, carbon black, graphene sheets, graphene nanoribbons, and carbon nanofibers. 6. The apparatus of any preceding or following embodiment, wherein the nucleic acid-based nanowires are modified with metal ion doping with ions selected from the group of ions consisting of Cu2+, Fe3+, Cu2+and Ag+. 7. The apparatus of any preceding or following embodiment, the nucleic acid-based nanowires further comprising molecular doping with intercalators selected from the group of intercalators consisting of anthraquinone, ferrocene, norbornadiene, methylene blue, ethidium, coralyne and cryptolepin. 8. The apparatus of any preceding or following embodiment, wherein the memory elements comprise: one or more nucleic acid strands linking the first and second nanowires, the nucleic acid strands producing a characteristic conductance. 9. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is controlled by sequence, length and number of linking nucleic acid strands. 10. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is further controlled by metal ion doping of the nucleic acid strands with ions selected from the group of ions consisting of Cu2+, Fe3+, Cu2+and Ag+. 11. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is further controlled by doping the nucleic acid strands with conductive metal nanoparticles. 12. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is further controlled by doping the nucleic acid strands with a conductive carbon dopant selected from the group consisting of carbon nanotubes, carbon nanorods, carbon black, graphene sheets, graphene nanoribbons, and carbon nanofibers. 13. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is further controlled by molecular doping of the nucleic acid strands with intercalators selected from the group of intercalators consisting of anthraquinone, methylene blue, ethidium, coralyne and cryptolepin. 14. The apparatus of any preceding or following embodiment, wherein the nucleic acid strands of the memory elements are nucleic acids selected from the group of nucleic acids consisting of DNA, RNA, DNA:RNA hybrids, threose nucleic acid (TNA), peptide nucleic acid (PNA) Glycol nucleic acid (GNA), locked nucleic acid (LNA), bridged nucleic acid (BNA) and phosphorodiamidate morpholino oligomer (PMO). 15. The apparatus of any preceding or following embodiment, wherein the memory elements comprise: a plurality of nucleic acid strands with sequences capable of encoding digital values combined with diode sequences linking the first and second nanowires, the combined nucleic acid-diode strands configured as a memory element with multiple, parallel paths producing a characteristic conductance. 16. The apparatus of any preceding or following embodiment, wherein the diode is formed from an end of a nucleic acid strand with a sequence comprising SEQ ID NO: 2. 17. The apparatus of any preceding or following embodiment, wherein the diode is formed from an end of a nucleic acid strand incorporating coralyne intercalators. 18. The apparatus of any preceding or following embodiment, wherein the plurality of nucleic acid strands has sequences that are not identical. 19. A memory apparatus, comprising: (a) a substrate; (b) a plurality of electrodes mounted to the substrate; and (c) an array of cross-wire memory units, each unit comprising: (1) a first plurality of conductive nanowires, each nanowire having two ends with each end coupled to an electrode; (2) a second plurality of conductive nanowires, each nanowire having two ends with each end coupled to an electrode; wherein each nanowire in the first plurality of conductive nanowires crossing over a nanowire in the second plurality of nucleic acid-based nanowires; and (3) a plurality of nucleic acid-based memory elements, each said memory element connecting a first nanowire with a second nanowire; wherein each said memory element having a controlled conductance to encode a data bit. 20. The apparatus of any preceding or following embodiment, wherein nanowires of the first plurality of nanowires are oriented at a right angle to the second plurality of nanowires. 21. The apparatus of any preceding or following embodiment, wherein said first plurality of conductive nanowires and the second plurality of conductive nanowires are nucleic acid-based nanowires. 22. The apparatus of any preceding or following embodiment, wherein the nucleic acid-based nanowires are assembled from a nucleic acid selected from the group of nucleic acids consisting of DNA, RNA, threose nucleic acid (TNA), peptide nucleic acid (PNA) Glycol nucleic acid (GNA), locked nucleic acid (LNA), bridged nucleic acid (BNA) and phosphorodiamidate morpholino oligomer (PMO). 23. The apparatus of any preceding or following embodiment, wherein the memory elements comprise: one or more nucleic acid strands linking the first and second nanowires, the nucleic acid strands producing a characteristic conductance. 24. The apparatus of any preceding or following embodiment, wherein the characteristic conductance is controlled by sequence, length and number of linking nucleic acid strands. 25. The apparatus of any preceding or following embodiment, wherein the nucleic acid strands are modified by metal ion doping of the nucleic acid strands with ions selected from the group of ions consisting of Cu2+, Fe3+, Cu2+and Ag+. 26. The apparatus of any preceding or following embodiment, wherein the nucleic acid strands are modified by doping with conductive metal nanoparticles. 27. The apparatus of any preceding or following embodiment, wherein the conductive metal nanoparticles are metals selected from the group of metals consisting of Au, PbS, PbSe, Ge, and Ag. 28. The apparatus of any preceding or following embodiment, wherein the nucleic acid strands are modified by doping with a conductive carbon dopant selected from the group consisting of carbon nanotubes, carbon nanorods, carbon black, graphene sheets, graphene nanoribbons, and carbon nanofibers. 29. The apparatus of any preceding or following embodiment, wherein the nucleic acid strands are modified by molecular doping with intercalators selected from the group of intercalators consisting of anthraquinone, ferrocene, norbornadiene, methylene blue, ethidium, coralyne and cryptolepin. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” As used herein, the term “set” refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects. As used herein, the terms “substantially” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200 should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth. Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments which may become obvious to those skilled in the art. All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed as a “means plus function” element unless the element is expressly recited using the phrase “means for”. No claim element herein is to be construed as a “step plus function” element unless the element is expressly recited using the phrase “step for”. | 40,334 |
11943941 | DETAILED DESCRIPTION <Underlying Knowledge Forming Basis of the Present Disclosure> Underlying knowledge forming the basis of the present disclosure is as follows. Tandem solar cells include two-terminal tandem solar cells and four-terminal tandem solar cells. In a two-terminal tandem solar cell, a negative electrode of a top cell and an n-type semiconductor layer thereof are stacked on a p-type semiconductor layer of a bottom cell. Terminals are attached to a positive electrode of the bottom cell and a negative electrode of the top cell. In a four-terminal tandem solar cell, a bottom cell and a top cell have respective substrates. The top cell and the bottom cell are electrically insulated from each other. In the four-terminal tandem solar cell, terminals are connected to positive and negative electrodes of each cell, and a total of four terminals are provided. The properties required for the four-terminal tandem solar cell that include the value of the band gap of the top cell, the value of the band gap of the bottom cell, and the theoretical efficiency of the four-terminal tandem solar cell are shown in “Alexis De Vos, J. Phys. D: Appl. Phys., 1980, 13, 839-846.” When a light source used emits black body radiation, an efficiency of 40% to 42% is obtained when a silicon solar cell with a band gap of 1.1 eV is disposed as the bottom cell and a perovskite solar cell with a band gap of 1.9 eV is disposed as the top cell. A perovskite solar cell can be used also as the bottom cell. In this case, when the band gap of the perovskite solar cell is 1.0 eV, the maximum efficiency can be estimated to be 42.3%. Japanese Patent No. 4953562 discloses a solar cell module including electrodes disposed on its front surface. The electrodes include front-side finger electrodes and busbar electrodes orthogonal to the front-side finger electrodes. It is stated that the front-side finger electrodes have a width equal to or more than 0.05 mm and equal to or less than 0.1 mm and that the busbar electrodes have a width equal to or more than 0.5 mm and equal to or less than 2 mm. It is also stated that three busbar electrodes are disposed on single crystal silicon having a side length of 100 mm to 150 mm. Japanese Unexamined Patent Application Publication No. 2010-80887 discloses back-contact electrodes. The use of the back-contact electrodes allows the utilization of the power generation area to be maximized because the electrodes are disposed only on the back side. “Qingfeng Dong et al., Science, 2015, 347, 6225, 967-970” reports a perovskite light absorption material with a carrier diffusion length of 175±25 μm. In the conventional tandem solar cell structures, transparent electrodes are disposed on the light-receiving surfaces. The solar cell requires the transparent electrodes in order to allow light to pass through to photoelectric conversion layers. However, the use of the transparent electrodes causes a reduction in light transmittance and an increase in electrical resistance. This leads to a reduction in the power generation efficiency of the solar cell. The details of the reduction in the light transmittance will be described in “(Optical simulations of tandem solar cell having three transparent electrodes)” described later. In view of the above findings, the inventors have found a structure of a four-terminal tandem solar cell that allows the use of transparent electrodes to be avoided. SUMMARY OF ASPECTS OF PRESENT DISCLOSURE A solar cell according to a first aspect of the present disclosure includes:a first substrate;a second substrate;a third substrate;a first photoelectric conversion layer;a second photoelectric conversion layer; anda pair of electrodes,wherein the first substrate and the second substrate have light-transmitting properties,wherein the second substrate is disposed between the first substrate and the third substrate,wherein the first photoelectric conversion layer is disposed between the first substrate and the second substrate,wherein the second photoelectric conversion layer is disposed between the second substrate and the third substrate, andwherein the pair of electrodes are disposed so as to sandwich the first photoelectric conversion layer therebetween in a direction perpendicular to an arrangement direction of the first substrate, the second substrate, and the third substrate. In other words, the solar cell according to the first aspect of the present disclosure includes:the light-transmitting first substrate;the light-transmitting second substrate;the third substrate disposed such that the second substrate is disposed between the first substrate and the second substrate;the first photoelectric conversion layer disposed between the first substrate and the second substrate and containing a perovskite material;the second photoelectric conversion layer disposed between the second substrate and the third substrate; andthe pair of electrodes disposed so as to sandwich the first photoelectric conversion layer therebetween in the direction perpendicular to the arrangement direction of the first substrate, the second substrate, and the third substrate. In the first aspect, the use of the transparent electrodes can be avoided. When the electrodes are excluded from the light-receiving surfaces, incident light is not absorbed by the electrodes, so that the power generation efficiency of the solar cell can be improved. The “arrangement direction of the first substrate, the second substrate, and the third substrate” means the direction normal to the first substrate. According to a second aspect of the present disclosure, in the solar cell according to the first aspect, for example, the pair of electrodes may include a first negative electrode and a first positive electrode. The solar cell may further include a first electron transport layer disposed between the first negative electrode and the first photoelectric conversion layer and a first hole transport layer disposed between the first positive electrode and the first photoelectric conversion layer. With this structure, the power generation efficiency of the solar cell can be improved. According to a third aspect, in the solar cell according to the second aspect, for example, at least one selected from the group consisting of the first negative electrode and the first positive electrode may be a non-transparent electrode formed of a metal material. With this structure, the electrical resistance of the at least one of the electrodes can be reduced. Therefore, the power generation efficiency of the solar cell can be improved. According to a fourth aspect of the present disclosure, the solar cell according to any one of the first to third aspects may further include, for example, an additional pair of electrodes disposed so as to sandwich the second photoelectric conversion layer therebetween in the direction perpendicular to the arrangement direction of the first substrate, the second substrate, and the third substrate. With this structure, the use of the transparent electrodes can be avoided. When the electrodes are excluded from the light-receiving surfaces, the power generation efficiency of the solar cell can also be improved. According to a fifth aspect of the present disclosure, in the solar cell according to the fourth aspect, for example, the additional pair of electrodes may include a second negative electrode and a second positive electrode. The solar cell may further include a second electron transport layer disposed between the second negative electrode and the second photoelectric conversion layer and a second hole transport layer disposed between the second positive electrode and the second photoelectric conversion layer. With this structure, the power generation efficiency of the solar cell can be improved. According to a sixth aspect of the present disclosure, in the solar cell according to the fifth aspect, for example, at least one selected from the group consisting of the second negative electrode and the second positive electrode may be a non-transparent electrode formed of a metal material. With this structure, the power generation efficiency of the solar cell can be improved. According to a seventh aspect of the present disclosure, the solar cell according to any one of the first to third aspects may further include, for example, a second positive electrode having light-transmitting properties and disposed between the second substrate and the second photoelectric conversion layer and a second negative electrode disposed between the third substrate and the second photoelectric conversion layer. The second positive electrode may include a plurality of busbar electrodes and a plurality of finger electrodes, and the plurality of busbar electrodes may be electrically connected to each other through the plurality of finger electrodes. Although the positive electrodes are disposed on the light-receiving surface of the bottom cell, light is allowed to pass through to the photoelectric conversion layer efficiently. According to an eighth aspect of the present disclosure, the solar cell according to any one of the first of third aspects may further include, for example, second negative electrodes disposed between the third substrate and the second photoelectric conversion layer and second positive electrodes disposed between the third substrate and the second photoelectric conversion layer. The second negative electrodes and the second positive electrodes may be arranged alternately in the direction perpendicular to the arrangement direction of the first substrate, the second substrate, and the third substrate and may be electrically insulated from each other with gaps therebetween. With this structure, the electric power generation area of the bottom cell can be increased. According to a ninth aspect of the present disclosure, in the solar cell according to the second aspect, for example, the first electron transport layer and the first hole transport layer may be formed of respective inorganic materials. According to a tenth aspect of the present disclosure, in the solar cell according to the fifth aspect, for example, the second electron transport layer and the second hole transport layer may be formed of respective inorganic materials. In each of the ninth and tenth aspects, the photoelectric conversion layer is unlikely to be damaged during the production of the electron transport layer and the hole transport layer. Therefore, the tandem solar cell provided can have high thermal durability and high light durability. According to an eleventh aspect of the present disclosure, in the solar cell according to any one of the first to tenth aspects, for example, the first photoelectric conversion layer may contain a perovskite material. Embodiments of Present Disclosure Embodiments of the present disclosure will be described with reference to the drawings. Solar cells shown in embodiments 1 to 10 are four-terminal tandem solar cells. The following embodiments are merely examples, and the present disclosure are not limited to the following embodiments. Embodiment 1 [Overview of Solar Cell] FIG.1Ais a cross-sectional view of a solar cell100according to embodiment 1.FIG.1Bis a top view of the solar cell100according to embodiment 1. The solar cell100includes a top cell110and a bottom cell120. Light40is incident on the solar cell100from a prescribed direction. The top cell110is located on the light incident side. The bottom cell120is located downstream of the top cell110in the traveling direction of the light. The top cell110includes a first substrate1, a second substrate5, and a first photoelectric conversion layer3. The first photoelectric conversion layer3is disposed between the first substrate1and the second substrate5. The first substrate1, the first photoelectric conversion layer3, and the second substrate5are arranged in this order. The plane of the first substrate1and the plane of the second substrate5are parallel to each other. The first photoelectric conversion layer3may or may not be in contact with each of the first substrate1and the second substrate5. The top cell110further includes a pair of electrodes2and4. The pair of electrodes2and4are disposed so as to sandwich the first photoelectric conversion layer3therebetween in a direction perpendicular to the arrangement direction of the first substrate1and the second substrate5. In other words, the pair of electrodes2and4are disposed so as to sandwich the first photoelectric conversion layer3therebetween in a direction perpendicular to the direction normal to the first substrate1. The first photoelectric conversion layer3has two principal surfaces and at least one side surface. The pair of electrodes2and4are attached to the at least one side surface in a direction perpendicular to the thickness direction of the first photoelectric conversion layer3. In the present embodiment, the first photoelectric conversion layer3has a rectangular shape in plan view and has four side surfaces. For example, when the first photoelectric conversion layer3has a circular shape, the number of side surfaces is 1. The “principal surfaces” mean the surfaces having the largest area. A “side surface” of the first photoelectric conversion layer3means its surface extending in a direction perpendicular to the arrangement direction of the first substrate1and the second substrate5. The pair of electrodes2and4include a first negative electrode2and a first positive electrode4. In the present specification, “the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4” may be referred to as “top cell components.” The first negative electrode2has, for example, a rectangular shape in plan view. The first negative electrode2is attached to a side surface of the first photoelectric conversion layer3. The first negative electrode2is disposed between the first substrate1and the second substrate5. When the first substrate1and the first negative electrode2are projected onto a plane perpendicular to the thickness direction of the first photoelectric conversion layer3, part or all of the projection image of the first negative electrode2is located inside the projection image of the first substrate1. In this case, the first negative electrode2may or may not be in contact with each of the first substrate1and the second substrate5. The first negative electrode2may be in contact with the first photoelectric conversion layer3. More specifically, the first negative electrode2may be in contact with the entire side surface of the first photoelectric conversion layer3. The first negative electrode2may be in contact with the first photoelectric conversion layer3only at its side surface. The first negative electrode2may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first negative electrode may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. With this structure, the top cell110produced can have high strength. The first positive electrode4has, for example, a rectangular shape in plan view. The first positive electrode4is attached to a side surface of the first photoelectric conversion layer3. The first positive electrode4is disposed between the first substrate1and the second substrate5. When the first substrate1and the first positive electrode4are projected onto a plane perpendicular to the thickness direction of the first photoelectric conversion layer3, part or all of the projection image of the first positive electrode4is located inside the projection image of the first substrate1. In this case, the first positive electrode4may or may not be in contact with each of the first substrate1and the second substrate5. The first positive electrode4may be in contact with the first photoelectric conversion layer3. More specifically, the first positive electrode4may be in contact with the entire side surface of the first photoelectric conversion layer3. The first positive electrode4may be in contact with the first photoelectric conversion layer3only at its side surface. The first positive electrode4may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first positive electrode4may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. The first negative electrode2and the first positive electrode4face each other in the direction perpendicular to the arrangement direction of the first substrate1and the second substrate5. The first negative electrode2and the first positive electrode4are attached to the first photoelectric conversion layer3. Since the first negative electrode2and the first positive electrode4are positioned so as not to block the incident light, they do not need to be transparent electrodes. Specifically, with the structure of the present embodiment, the use of transparent electrodes can be avoided. However, the first negative electrode2and/or the first positive electrode4may be a transparent electrode. In the present embodiment, the electrodes are positioned so as not to block the incident light. Therefore, the incident light is not absorbed by the electrodes, so that the solar cell100in the present embodiment has high photoelectric conversion efficiency. The top cell110further includes terminals11aand11b. The terminal11ais electrically connected to the first negative electrode2. The terminal11bis electrically connected to the first positive electrode4. The top cell110further includes a sealing portion12. The sealing portion12surrounds the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4. The sealing portion12may be in contact with each of the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4. The sealing portion12may be in contact with each of the first substrate1and the second substrate5. With the above structure, the top cell components can be isolated from the external environment. Therefore, deterioration of the solar cell due to intrusion of water or oxygen into the top cell components can be prevented. The distance between the first negative electrode2and the first positive electrode4can be determined from the carrier diffusion length in the first photoelectric conversion layer3. Since the first photoelectric conversion layer3contains a perovskite material, the carrier diffusion length in the first photoelectric conversion layer3is longer than that in a photoelectric conversion material used for conventional silicon solar cells. The carrier diffusion length in the photoelectric conversion layer containing the perovskite material is about 200 μm. The distance between the first negative electrode2and the first positive electrode4is set to be about 10 times the carrier diffusion length in the first photoelectric conversion layer3. The distance between the first negative electrode2and the first positive electrode4is, for example, equal to or more than 0.2 mm and equal to or less than 2 mm. The bottom cell120includes a second substrate6, a third substrate7, and a second photoelectric conversion layer9. The third substrate7supports the first substrate1, the second substrate5, and the second substrate6in this order. The second substrates5and6are located between the third substrate7and the first substrate1. The second photoelectric conversion layer9is disposed between the second substrate6and the third substrate7. The second substrate6, the second photoelectric conversion layer9, and the third substrate7are disposed in this order. The plane of the second substrate6and the plane of the third substrate7are parallel to each other. The second photoelectric conversion layer9may or may not be in contact with each of the second substrate6and the third substrate7. The bottom cell120further includes a pair of electrodes8and10. The pair of electrodes8and10are disposed so as to sandwich the second photoelectric conversion layer9therebetween in a direction perpendicular to the arrangement direction of the second substrate6and the third substrate7. The second photoelectric conversion layer9has two principal surfaces and at least one side surface. The pair of electrodes8and10are attached to the at least one side surface in a direction perpendicular to the thickness direction of the second photoelectric conversion layer9. In the present embodiment, the second photoelectric conversion layer9has a rectangular shape in plan view and has four side surfaces. For example, when the second photoelectric conversion layer9has a circular shape, the number of side surfaces is one. The pair of electrodes8and10include a second negative electrode8and a second positive electrode10. In the present specification, “the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10” may be referred to as “bottom cell components.” The second negative electrode8has, for example, a rectangular shape in plan view. The second negative electrode8is attached to a side surface of the second photoelectric conversion layer9. The second negative electrode8is disposed between the second substrate6and the third substrate7. When the second substrate6and the second negative electrode8are projected onto a plane perpendicular to the thickness direction of the second photoelectric conversion layer9, part or all of the projection image of the second negative electrode8is located inside the projection image of the second substrate6. In this case, the second negative electrode8may or may not be in contact with each of the second substrate6and the third substrate7. The second negative electrode8may be in contact with the second photoelectric conversion layer9. More specifically, the second negative electrode8may be in contact with the entire side surface of the second photoelectric conversion layer9. The second negative electrode8may be disposed, for example, between the second substrate6and the second photoelectric conversion layer9. The second negative electrode8may be disposed, for example, between the second photoelectric conversion layer9and the third substrate7. The second positive electrode10has, for example, a rectangular shape in plan view. The second positive electrode10is attached to a side surface of the second photoelectric conversion layer9. The second positive electrode10is disposed between the second substrate6and the third substrate7. When the second substrate6and the second positive electrode10are projected onto a plane perpendicular to the thickness direction of the second photoelectric conversion layer9, part or all of the projection image of the second positive electrode10is located inside the projection image of the second substrate6. In this case, the second positive electrode10may or may not be in contact with each of the second substrate6and the third substrate7. The second positive electrode10may be in contact with the second photoelectric conversion layer9. More specifically, the second positive electrode10may be in contact with the entire side surface of the second photoelectric conversion layer9. The second positive electrode10may be disposed, for example, between the second substrate6and the second photoelectric conversion layer9. The second positive electrode10may be disposed, for example, between the second photoelectric conversion layer9and the third substrate7. The second negative electrode8and the second positive electrode10face each other in the direction perpendicular to the arrangement direction of the second substrate6and the third substrate7. The second negative electrode8and the second positive electrode10are attached to the second photoelectric conversion layer9. Since the second negative electrode8and the second positive electrode10are positioned so as not to block the incident light, they do not need to be transparent electrodes. Specifically, with the structure of the present embodiment, the use of transparent electrodes can be avoided. Since the incident light is not absorbed by the electrodes, the solar cell100in the present embodiment can have high photoelectric conversion efficiency. The bottom cell120further includes terminals11cand11d. The terminal11cis electrically connected to the second negative electrode8. The terminal11dis electrically connected to the second positive electrode10. The bottom cell120further includes a sealing portion12. The sealing portion12surrounds the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10. The sealing portion12may be in contact with each of the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10. The sealing portion12may be in contact with each of the second substrate6and the third substrate7. With the above structure, the bottom cell components can be isolated from the external environment. Therefore, deterioration of the solar cell due to intrusion of water or oxygen into the bottom cell components can be prevented. The distance between the second negative electrode8and the second positive electrode10can be determined from the carrier diffusion length in the second photoelectric conversion layer9. Since the second photoelectric conversion layer9contains a perovskite material, the carrier diffusion length in the second photoelectric conversion layer9is longer than that of a photoelectric conversion material used for conventional silicon solar cells. The carrier diffusion length of the photoelectric conversion layer containing the perovskite material is about 200 μm. The distance between the second negative electrode8and the second positive electrode10is set to be about 10 times the carrier diffusion length in the second photoelectric conversion layer9. The distance between the second negative electrode8and the second positive electrode10is, for example, equal to or more than 0.2 mm and equal to or less than 2 mm. When the second photoelectric conversion layer9is an n-type silicon layer, the carrier diffusion length in the second photoelectric conversion layer9is about 100 μm. The distance between the electrodes is set to be about 10 times the carrier diffusion length. Therefore, he distance between the second negative electrode8and the second positive electrode10is, for example, equal to or more than 0.1 mm and equal to or less than 1 mm. Next, the basic operation principle of the solar cell100will be described. When the solar cell100is irradiated with light, the first photoelectric conversion layer3in the top cell110absorbs the light, and electrons and holes are generated. The electrons move to the first negative electrode2. The holes move to the first positive electrode4. In the solar cell100, an electric current can thereby be drawn from the first negative electrode2serving as a negative electrode and the first positive electrode4serving as a positive electrode. In the bottom cell120, the second photoelectric conversion layer9absorbs the light, and electrons and holes are generated. The electrons move to the second negative electrode8. The holes move to the second positive electrode10. In the solar cell100, an electric current can be drawn from the second negative electrode8serving as a negative electrode and the second positive electrode10serving as a positive electrode. The conventional four-terminal tandem solar cell requires three transparent electrodes. The “transparent electrodes” mean electrodes formed of an inorganic oxide doped with a metal. Examples of the inorganic oxide doped with a metal include FTO and ITO. The use of the transparent electrodes causes a reduction in light transmittance and an increase in electrical resistance. This leads to a reduction in the power generation efficiency of the solar cells. In the solar cell100according to the present embodiment, the electrodes are disposed on side surfaces of the photoelectric conversion layers. Since the incident light is not absorbed by the electrodes, the solar cell100can have high photoelectric conversion efficiency. Moreover, the use of the transparent electrodes can be avoided. [Specific Structure of Solar Cell] The components of the solar cell100will be described specifically. (First Substrate1) The first substrate1has light-transmitting properties. No particular limitation is imposed on the material forming the first substrate so long as the material has light-transmitting properties. The first substrate1plays a role in holding the layers included in the top cell110. The first substrate1used may be a glass substrate or a plastic substrate. The plastic substrate may be a plastic film. The first substrate1may be formed by stacking an inorganic or organic sealing layer on a surface of the solar cell100. The first substrate1transmits light, for example, in the ultraviolet to near infrared region. The wavelength of the light allowed to pass through the first substrate1depends on the absorption wavelength of the first photoelectric conversion layer3. The wavelength of the light allowed to pass through the first substrate1is, for example, equal to or longer than 380 nm and equal to or shorter than 2000 nm. The light transmittance of the first substrate1may be equal to or higher than 90% and may be equal to or higher than 95%. The term “light-transmitting properties” means that 90% or more of light having a wavelength equal to or longer than 380 nm and equal to shorter than 2000 nm passes through the substrate. The light transmittance can be measured using, for example, an ultraviolet-visible-near infrared spectrophotometer. The thickness of the first substrate1is, for example, equal to or more than 0.3 mm and equal to or less than 0.7 mm. By appropriately setting the thickness of the first substrate1, the first substrate1can hold the layers included in the top cell100of the solar cell110and can efficiently transmit light. (Second Substrates5and6) The second substrate5has light-transmitting properties. No particular limitation is imposed on the material forming the second substrate5so long as the material has light-transmitting properties. The second substrate5holds the layers included in the top cell110of the solar cell100. The second substrate6has light-transmitting properties. No particular limitation is imposed on the material forming the second substrate6so long as the material has light-transmitting properties. The second substrate6plays a role in holding the layers included in the bottom cell120of the solar cell100. The second substrates5and6used may each be a glass substrate or a plastic substrate. The plastic substrate may be a plastic film. The material forming the second substrate5and the material forming the second substrate6may be the same or different. No particular limitation is imposed on the material forming the second substrate5and the material forming the second substrate6so long as they can electrically insulate the top cell110and the bottom cell120from each other. The second substrates5and6may be formed by stacking inorganic or organic sealing layers. Light in the ultraviolet to near infrared region passes through the second substrates5and6. The wavelength of the light allowed to pass through the second substrates5and6depends on the absorption wavelength of the second photoelectric conversion layer9. The wavelength of the light allowed to pass through the second substrate5is, for example, equal to or longer than 380 nm and equal to or shorter than 2000 nm. The wavelength of the light allowed to pass through the second substrate6may be the same as or different from the wavelength of the light allowed to pass through the second substrate5. The light transmittance of the second substrate5may be equal to or higher than 90%. The light transmittance of the second substrate6may be the same as or different from the light transmittance of the second substrate5. The light transmittance may be measured using, for example, an ultraviolet-visible-near infrared spectrophotometer. The thickness of the second substrate5is, for example, equal to or more than 0.3 mm and equal to or less than 0.7 mm. The thickness of the second substrate6may be the same as or different from the thickness of the second substrate5. By appropriately setting the thickness of the second substrate5and the thickness of the second substrate6, the second substrates5and6can hold the layers included in the top cell110and the bottom cell120and can transmit light efficiently. The solar cell100includes the second substrates5and6. However, the solar cell100may include only the second substrate5or6. By reducing the number of second substrates, the solar cell can transmit light more sufficiently. Therefore, the photoelectric conversion efficiency of the bottom cell120of the solar cell100can be improved. (First Photoelectric Conversion Layer3) The first photoelectric conversion layer3contains a perovskite material. Examples of the perovskite material include perovskite crystals and structures similar thereto. Examples of the perovskite crystals include compounds having a composition formula of ABX3. Here, A is a monovalent cation, B is a divalent cation, and X is a halogen anion. Examples of the similar structures include: perovskite compounds having halogen anion defects; and perovskite compounds in which the monovalent cation or the halogen anion includes a plurality of types of elements. It is only necessary that the first photoelectric conversion layer3contain the perovskite material, and the first photoelectric conversion layer3may contain impurities. The first photoelectric conversion layer3may further contain an additional compound different from the perovskite material. The band gap of the first photoelectric conversion layer3is larger than the band gap of the second photoelectric conversion layer9described later. The band gap of the first photoelectric conversion layer3may be about 1.9 eV. Examples of the perovskite material that can be used for the first photoelectric conversion layer3include CsPbI3and CsPbBr3. The band gap of CsPbI3is 1.7 eV, and the band gap of CsPbBr3is 2.0 eV. Other examples of the perovskite material that can be used for the first photoelectric conversion layer3include CsPbBrxI3-x. Here, x is 0≤x≤3. The band gap of CsPbBrxI3-xis appropriately controlled in the range of 1.7 eV to 2.0 eV. The thickness of the first photoelectric conversion layer3is, for example, equal to or more than 100 nm and equal to or less than 10 μm. By appropriately set the thickness of the first photoelectric conversion layer3, the first photoelectric conversion layer3can absorb visible light sufficiently. Therefore, the solar cell100provided can have high photoelectric conversion efficiency. (First Negative Electrode2) The first negative electrode2has electrical conductivity. The first negative electrode2is not in ohmic contact with the first photoelectric conversion layer3. Moreover, the first negative electrode2has the ability to block holes from the first photoelectric conversion layer3. The ability to block holes from the first photoelectric conversion layer3means the ability to allow only electrons generated in the first photoelectric conversion layer3to pass through and to block holes generated in the first photoelectric conversion layer3. A material with such an ability is a material whose work function is smaller than the difference between the vacuum level and the energy level of the upper edge of the valence band of the first photoelectric conversion layer3. A material whose work function is smaller than the difference between the vacuum level and the Fermi level of the first photoelectric conversion layer3may also be used. Specific examples of such a material include aluminum. The first negative electrode2may not have transparency. The first negative electrode2may be a non-transparent electrode. The non-transparent electrode contains a metal material or a carbon material as a main component. The term “main component” means a component whose weight ratio in the non-transparent electrode is largest. The non-transparent electrode contains substantially no oxides. The phrase “contains substantially no oxides” means that no oxides are intentionally added to the non-transparent electrode. The first negative electrode2may be formed of a metal material. The thickness of the first negative electrode2may be in the range of from 1 nm to 1000 nm. The thickness of the first negative electrode2may be equal to or more than 100 nm in order to reduce its sheet resistance. (First Positive Electrode4) The first positive electrode4has electrical conductivity. The first positive electrode4is not in ohmic contact with the first photoelectric conversion layer3. The first positive electrode4has the ability to block electrons from the first photoelectric conversion layer3. The ability to block electrons from the first photoelectric conversion layer3means the ability to allow only holes generated in the first photoelectric conversion layer3to pass through and to block electrons generated in the first photoelectric conversion layer3. A material with such an ability is a material whose Fermi energy is lower than the energy level of the lower edge of the conduction band of the first photoelectric conversion layer3. The above material may be a material whose work function is smaller than the difference between the vacuum level and the Fermi energy of the first photoelectric conversion layer3. Specific examples of such a material include platinum, gold, and carbon materials such as graphene. The first positive electrode4may not have transparency. The first positive electrode4may be a non-transparent electrode. The non-transparent electrode contains a metal material or a carbon material as a main component. The non-transparent electrode contains substantially no oxides. The first positive electrode4may be formed of a metal material. The thickness of the first positive electrode4may be in the range of from 1 nm to 1000 nm. The thickness of the first positive electrode4may be equal to or more than 100 nm in order to reduce its sheet resistance. (Third Substrate7) The third substrate7is an optional component. The third substrate7used may be, for example, a glass substrate or a plastic substrate. The plastic substrate may be a plastic film. (Second Photoelectric Conversion Layer9) The second photoelectric conversion layer9contains, for example, a perovskite material. Examples of the perovskite material include perovskite crystals and structures similar thereto. Examples of the perovskite crystals include compounds having a composition formula of ABX3. Here, A is a monovalent cation, B is a divalent cation, and X is a halogen anion. Examples of the similar structures include: perovskite compounds having halogen anion defects; and perovskite compounds in which the monovalent cation or the halogen anion includes a plurality of types of elements. It is only necessary that the second photoelectric conversion layer9contain the perovskite material, and the first photoelectric conversion layer3may contain impurities. The second photoelectric conversion layer9may further contain an additional compound different from the perovskite material. The band gap of the second photoelectric conversion layer9is smaller than the band gap of the first photoelectric conversion layer3. The band gap of the second photoelectric conversion layer9may be about 1.0 eV. Examples of the perovskite material that can be used for the second photoelectric conversion layer9include CH3NH3SnI3. The band gap of CH3NH3SnI3is 1.25 eV. Other examples of the material that can be used for the second photoelectric conversion layer9include silicon. An n-type silicon single crystal may be used for the second photoelectric conversion layer9. The band gap of silicon is about 1.1 eV and is smaller than the band gap of the first photoelectric conversion layer3. When silicon is used for the second photoelectric conversion layer9, a silicon substrate doped with phosphorus (P) may be used as the n-type silicon layer. When silicon is used for the second photoelectric conversion layer9, the thickness of the second photoelectric conversion layer9is equal to or more than 200 μm and equal to or less than 300 μm. (Second Negative Electrode8) The second negative electrode8has electrical conductivity. The second negative electrode8is not in ohmic contact with the second photoelectric conversion layer9. The second negative electrode8has the ability to block holes from the second photoelectric conversion layer9. The ability to block holes from the second photoelectric conversion layer9means the ability to allow only electron generated in the second photoelectric conversion layer9to pass through and to block holes generated in the second photoelectric conversion layer9. A material with such an ability is a material whose work function is smaller than the difference between the vacuum level and the energy level of the upper edge of the valence band of the second photoelectric conversion layer9. A material whose work function is smaller than the difference between the vacuum level and the Fermi level of the second photoelectric conversion layer9may also be used. Specific examples of such a material include aluminum. The second negative electrode8may not have transparency. The second negative electrode8may be a non-transparent electrode formed of a metal material. The non-transparent electrode contains a metal material or a carbon material as a main component. The non-transparent electrode contains substantially no oxides. The thickness of the second negative electrode8may be equal to or more than 1 nm and equal to or less than 1000 nm. The thickness of the second negative electrode8may be 100 nm or more in order to reduce its sheet resistance. (Second Positive Electrode10) The second positive electrode10has electrical conductivity. The second positive electrode10is not in ohmic contact with the second photoelectric conversion layer9. The second positive electrode10has the ability to block electrons from the second photoelectric conversion layer9. The ability to block electrons from the second photoelectric conversion layer9means the ability to allow only holes generated in the second photoelectric conversion layer9to pass through and to block electrons generated in the second photoelectric conversion layer9. A material with such an ability is a material whose Fermi energy is lower than the energy level of the lower edge of the conduction band of the second photoelectric conversion layer9. The above material may be a material whose work function is smaller than the difference between the vacuum level and the Fermi energy of the second photoelectric conversion layer9. Specific examples of such a material include platinum, gold, and carbon materials such as graphene. The second positive electrode10may not have transparency. The second positive electrode10may be a non-transparent electrode formed of a metal material. The non-transparent electrode contains a metal material or a carbon material as a main component. The non-transparent electrode contains substantially no oxides. The thickness of the second positive electrode10may be in the range of from 1 nm to 1000 nm. The thickness of the second positive electrode10may be 100 nm or more in order to reduce its sheet resistance. (Terminals11) The terminals11connect the top cell110to the bottom cell120in series. Examples of the material that can be used for the terminals11include silver and copper. (Sealing Portions12) One of the sealing portions12bonds the first substrate1to the second substrate5. The other sealing portion12bonds the second substrate6to the third substrate7. Examples of the material that can be used for the sealing portions12include epoxy resins and ethylene-vinyl acetate copolymers (EVA). [Method for Producing Solar Cell] Next, an example of a method for producing the solar cell100according to the present embodiment will be described. First, the top cell110of the solar cell100is produced. To form the first photoelectric conversion layer3, a spin coating method or vacuum deposition can be used. The spin coating method will next be described as an example. First, PbI2and CsI in a molar amount equal to the molar amount of PbI2are added to an organic solvent to prepare a perovskite precursor solution. The organic solvent used is, for example, a solvent mixture of dimethyl sulfoxide (DMSO):N,N-dimethylformamide (DMF)=1:1. The second substrate5used is a glass substrate. The perovskite precursor solution is applied to the glass substrate using the spin coating method under the condition of a rotation speed of 6000 rpm. To facilitate nucleation, 600 μL of toluene, which is a poor solvent, may be added dropwise to the perovskite precursor solution. The glass substrate with the perovskite precursor solution applied thereto is fired on a hot plate at 100° C. for 30 minutes to thereby obtain a CsPbI3film having the perovskite structure. Then a solvent such as DMF is used to remove part of the CsPbI3film, and the first photoelectric conversion layer3is thereby formed. Next, the first negative electrode2and the first positive electrode4are formed on the glass substrate by vacuum deposition. Any of the first negative electrode2and the first positive electrode4may be formed first. Specifically, aluminum (Al) used for the first negative electrode2is evaporated onto the second substrate5. Gold (Au) used for the first positive electrode4is evaporated onto the second substrate5. A glass substrate used as the first substrate1is placed on the second substrate5with the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4formed thereon. The first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4disposed between the first substrate1and the second substrate5are sealed with an epoxy resin. Then the epoxy resin is cured with ultraviolet (UV) light to thereby produce the top cell110. Next, the bottom cell120of the solar cell100is produced. When the second photoelectric conversion layer9contains a perovskite material, the second photoelectric conversion layer9may be formed by the same method as the method for producing the first photoelectric conversion layer3. When the second photoelectric conversion layer9contains the perovskite material, the second photoelectric conversion layer9may further contain, for example, CH3NH3SnI3in consideration of the band gap. First, SnI2and CH3NH3I in a molar amount equal to the molar amount of SnI2are added to an organic solvent to prepare a perovskite precursor solution. The organic solvent used is, for example, a solvent mixture of dimethyl sulfoxide (DMSO): N,N-dimethylformamide (DMF)=1:1. The third substrate7used is a glass substrate. The perovskite precursor solution is applied to the glass substrate using the spin coating method under the condition of a rotation speed of 6000 rpm. To facilitate nucleation, 600 μL of toluene, which is a poor solvent, may be added dropwise to the perovskite precursor solution. The glass substrate with the perovskite precursor solution applied thereto is fired on a hot plate at 100° C. for 30 minutes to thereby obtain a CH3NH3SnI3film having the perovskite structure. Then a solvent such as DMF is used to remove part of the CH3NH3SnI3film, and the second photoelectric conversion layer9is thereby formed. Next, the second negative electrode8and the second positive electrode10are formed on the glass substrate by vacuum deposition. Any of the second negative electrode8and the second positive electrode10may be formed first. Specifically, aluminum (Al) used for the second negative electrode8is evaporated onto the third substrate7. Gold (Au) used for the second positive electrode10is evaporated onto the third substrate7. A glass substrate used as the second substrate6is placed on the third substrate7with the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10formed thereon. The second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10disposed between the second substrate6and the third substrate7are sealed with an epoxy resin. Then the epoxy resin is cured with UV light, and the bottom cell120is thereby produced. Then the top cell110is placed on the bottom cell120. Terminals are connected to the negative electrode and the positive electrode of each cell, and the solar cell100is thereby obtained. When n-type single crystal silicon doped with phosphorus (P) is used for the second photoelectric conversion layer9, the bottom cell components may be produced by vapor deposition, a sputtering method, a chemical vapor deposition (CVD) method, etc. For example, a multilayer body in which the components of the bottom cell120are stacked is produced. The multilayer body formed includes the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10in this order. Specifically, Al used as the second negative electrode8is vapor-deposited on the second photoelectric conversion layer9, and Ag used as the second positive electrode10is vapor-deposited. Then the multilayer body obtained is cut, for example, at 1 mm intervals, and the bottom cell components are thereby obtained. Some other embodiments will next be described. Components common to the solar cell100in embodiment 1 and solar cells in other embodiments are denoted by the same reference numerals, and the description thereof may be omitted. The descriptions of the embodiments can be interchangeably applied so long as no technical conflicts occur. The embodiments may be combined with one another so long as no technical conflicts occur. Embodiment 2 FIG.2Ais a cross-sectional view of a solar cell200according to embodiment 2.FIG.2Bis a top view of the solar cell200according to embodiment 2. In a direction perpendicular to the thickness direction of the first photoelectric conversion layer3, the size of the first photoelectric conversion layer3may be the same as the size of the first substrate1. In the direction perpendicular to the thickness direction of the first photoelectric conversion layer3, the size of the first photoelectric conversion layer3may be larger than the size of the first substrate1. In this case, when the first substrate1and the first photoelectric conversion layer3are projected onto a plane perpendicular to the thickness direction of the first photoelectric conversion layer3, part of the projection image of the first photoelectric conversion layer3is located outside the projection image of the first substrate1. With this structure, the area of the principal surfaces of the first photoelectric conversion layer3can be further increased. Therefore, the photoelectric conversion efficiency can be improved. The first negative electrode2is attached to a side surface of the first photoelectric conversion layer3. The first negative electrode2may be in contact with the first photoelectric conversion layer3. More specifically, the first negative electrode2may be in contact with the entire side surface of the first photoelectric conversion layer3. The first negative electrode2may be in contact with a side surface of the first substrate1and/or a side surface of the second substrate5. In this case, the thickness of the first negative electrode2may be larger than the thickness of the first photoelectric conversion layer3. The first negative electrode2may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first negative electrode2may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. Part of the first photoelectric conversion layer3may be embedded in the first negative electrode2. Part of the first negative electrode2may be embedded in the first photoelectric conversion layer3. The first positive electrode4is attached to a side surface of the first photoelectric conversion layer3. The first positive electrode4may be in contact with the first photoelectric conversion layer3. More specifically, the first positive electrode4may be in contact with the entire side surface of the first photoelectric conversion layer3. The first positive electrode4may be in contact with a side surface of the first substrate1and/or a side surface of the second substrate5. In this case, the thickness of the first positive electrode4may be larger than the thickness of the first photoelectric conversion layer3. The first positive electrode4may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first positive electrode4may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. Part of the first photoelectric conversion layer3may be embedded in the first positive electrode4. Part of the first positive electrode4may be embedded in the first photoelectric conversion layer3. The top cell210further includes a sealing portion12. The sealing portion12surrounds the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4. The sealing portion12may be in contact with each of the first negative electrode2, the first photoelectric conversion layer3, and the first positive electrode4. The sealing portion12may be in contact with each of the first substrate1and the second substrate5. More specifically, the sealing portion12may be in contact with each of a side surface of the first substrate1and a side surface of the second substrate5. With the above structure, the top cell components can be isolated from the external environment. Therefore, deterioration of the solar cell due to intrusion of water or oxygen into the top cell components can be prevented. In a direction perpendicular to the thickness direction of the second photoelectric conversion layer9, the size of the second photoelectric conversion layer9may be the same as the size of the second substrate6. In the direction perpendicular to the thickness direction of the second photoelectric conversion layer9, the size of the second photoelectric conversion layer9may be larger than the size of the second substrate6. In this case, when the second substrate6and the second photoelectric conversion layer9are projected onto a plane perpendicular to the thickness direction of the second photoelectric conversion layer9, part of the projection image of the second photoelectric conversion layer9is located outside the projection image of the second substrate6. With this structure, the area of the principal surfaces of the second photoelectric conversion layer9can be further increased. Therefore, the photoelectric conversion efficiency can be improved. The second negative electrode8is attached to a side surface of the second photoelectric conversion layer9. The second negative electrode8may be in contact with the second photoelectric conversion layer9. More specifically, the second negative electrode8may be in contact with the entire side surface of the second photoelectric conversion layer9. The second negative electrode8may be in contact with a side surface of the second substrate6and/or a side surface of the third substrate7. In this case, the thickness of the second negative electrode8may be larger than the thickness of the second photoelectric conversion layer9. The second negative electrode8may be disposed, for example, between the second substrate6and the second photoelectric conversion layer9. The second negative electrode8may be disposed, for example, between the second photoelectric conversion layer9and the third substrate7. Part of the second photoelectric conversion layer9may be embedded in the second negative electrode8. Part of the second negative electrode8may be embedded in the second photoelectric conversion layer9. The second positive electrode10is attached to a side surface of the second photoelectric conversion layer9. The second positive electrode10may be in contact with the second photoelectric conversion layer9. More specifically, the second positive electrode10may be in contact with the entire side surface of the second photoelectric conversion layer9. The second positive electrode10may be in contact with a side surface of the second substrate6and/or a side surface of the third substrate7. In this case, the thickness of the second positive electrode10may be larger than the thickness of the second photoelectric conversion layer9. The second positive electrode10may be disposed, for example, between the second substrate6and the second photoelectric conversion layer9. The second positive electrode10may be disposed, for example, between the second photoelectric conversion layer9and the third substrate7. Part of the second photoelectric conversion layer9may be embedded in the second positive electrode10. Part of the second positive electrode10may be embedded in the second photoelectric conversion layer9. The bottom cell220further includes a sealing portion12. The sealing portion12surrounds the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10. The sealing portion12may be in contact with each of the second negative electrode8, the second photoelectric conversion layer9, and the second positive electrode10. The sealing portion12may be in contact with each of the second substrate6and the third substrate7. More specifically, the sealing portion12may be in contact with each of a side surface of the second substrate6and a side surface of the third substrate7. With the above structure, the bottom cell components can be isolated from the external environment. Therefore, deterioration of the solar cell due to intrusion of water or oxygen into the bottom cell components can be prevented. Embodiment 3 FIG.3Ais a cross-sectional view of a solar cell300according to embodiment 3.FIG.3Bis a top view of the solar cell300according to embodiment 3. As shown inFIG.3A, in the solar cell300, a top cell310further includes a first electron transport layer13and a first hole transport layer14. The first electron transport layer13has, for example, a rectangular shape in plan view. The first electron transport layer13is attached to a side surface of the first photoelectric conversion layer3. More specifically, the first electron transport layer13may be in contact with the entire side surface of the first photoelectric conversion layer3. The first electron transport layer13is disposed between the first negative electrode2and the first photoelectric conversion layer3. The first electron transport layer13is in contact with the first negative electrode2. The first electron transport layer13may or may not be in contact with each of the first substrate1and the second substrate5. The first electron transport layer13may be in contact with the first photoelectric conversion layer3only at its side surface. The first electron transport layer13may be in contact with the first negative electrode2only at its side surface. The first electron transport layer13may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first electron transport layer13may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. The first hole transport layer14has, for example, a rectangular shape in plan view. The first hole transport layer14is attached to a side surface of the first photoelectric conversion layer3. More specifically, the first hole transport layer14may be in contact with the entire side surface of the first photoelectric conversion layer3. The first hole transport layer14is disposed between the first positive electrode4and the first photoelectric conversion layer3. The first hole transport layer14is in contact with the first positive electrode4. The first hole transport layer14may or may not be in contact with each of the first substrate1and the second substrate5. The first hole transport layer14may be in contact with the first photoelectric conversion layer3only at its side surface. The first hole transport layer14may be in contact with the first positive electrode4only at its side surface. The first hole transport layer14may be disposed, for example, between the first substrate1and the first photoelectric conversion layer3. The first hole transport layer14may be disposed, for example, between the first photoelectric conversion layer3and the second substrate5. With the above structure, the photoelectric conversion efficiency can be improved. In the top cell310, the first electron transport layer13and the first hole transport layer14face each other in the direction perpendicular to the arrangement direction of the first substrate1and the second substrate5. The first electron transport layer13and the first hole transport layer14are attached to the first photoelectric conversion layer3. Since the first electron transport layer13and the first hole transport layer14are positioned so as not to block incident light, they do not need to transmit visible light and infrared light. The bottom cell320further includes a second electron transport layer15and a second hole transport layer16. The second electron transport layer15has, for example, a rectangular shape in plan view. The second electron transport layer15is attached to a side surface of the second photoelectric conversion layer9. More specifically, the second electron transport layer15may be in contact with the entire side surface of the second photoelectric conversion layer9. The second electron transport layer15is disposed between the second negative electrode8and the second photoelectric conversion layer9. The second electron transport layer15is in contact with the second negative electrode8. The second electron transport layer15may or may not be in contact with each of the second substrate6and the third substrate7. The second electron transport layer15may be in contact with the second photoelectric conversion layer9only at its side surface. The second electron transport layer15may be in contact with the second negative electrode8only at its side surface. The second electron transport layer15may be disposed, for example, between the second substrate6and the second photoelectric conversion layer9. The second electron transport layer15may be disposed, for example, between the second photoelectric conversion layer9and the third substrate7. The second hole transport layer16has, for example, a rectangular shape in plan view. The second hole transport layer16is attached to a side surface of the second photoelectric conversion layer9. More specifically, the second hole transport layer16may be in contact with the entire side surface of the second photoelectric conversion layer9. The second hole transport layer16is disposed between the second positive electrode10and the second photoelectric conversion layer9. The second hole transport layer16is in contact with the second positive electrode10. The second hole transport layer16may or may not be in contact with each of the second substrate6and the third substrate7. The second hole transport layer16may be in contact with the second photoelectric conversion layer9only at its side surface. The second hole transport layer16may be in contact with the second positive electrode10only at its side surface. With the above structure, the photoelectric conversion efficiency can be improved. In the bottom cell320, the second electron transport layer15and the second hole transport layer16face each other in the direction perpendicular to the arrangement direction of the second substrate6and the third substrate7. The second electron transport layer15and the second hole transport layer16are attached to the second photoelectric conversion layer9. Since the second electron transport layer15and the second hole transport layer16are positioned so as not to block incident light, they do not need to transmit visible light and infrared light. While the solar cell300includes the first electron transport layer13and the first hole transport layer14, the second electron transport layer15and the second hole transport layer16may be omitted. Alternatively, while the solar cell300includes the second electron transport layer15and the second hole transport layer16, the first electron transport layer13and the first hole transport layer14may be omitted. While the first electron transport layer13is provided, the first hole transport layer14may be omitted. While the first hole transport layer14is provided, the first electron transport layer13may be omitted. While the second electron transport layer15is provided, the second hole transport layer16may be omitted. While the second hole transport layer16is provided, the second electron transport layer15may be omitted. (First Electron Transport Layer13) The first electron transport layer13contains a semiconductor. Examples of the semiconductor include organic and inorganic n-type semiconductors. The first electron transport layer13is formed of, for example, an inorganic material. Examples of the organic n-type semiconductors include imide compounds, quinone compounds, fullerenes, and fullerene derivatives. Examples of the inorganic n-type semiconductors include metal oxides, metal nitrides, and perovskite compounds. Examples of the metal element oxide that can be used include oxides of Cd, Zn, In, Pb, Mo, W, Sb, Bi, Cu, Hg, Ti, Ag, Mn, Fe, V, Sn, Zr, Sr, Ga, Si, and Cr. More specific examples include TiO2. Examples of the metal element nitride include GaN. Examples of the perovskite oxide include SrTiO3and CaTiO3. The first electron transport layer13may be formed of a material having a band gap larger than 6.0 eV. Examples of the material having a band gap larger than 6.0 eV include alkali metal halides, alkaline earth metal halides, alkali metal oxides, and silicon dioxide. Examples of the alkali metal halides include lithium fluoride. Examples of the alkaline earth metal halides include calcium fluoride. Examples of the alkaline earth metal oxides include magnesium oxide. To facilitate the formation of the first photoelectric conversion layer3, the thickness of the first electron transport layer13may be slightly larger than the thickness of the first photoelectric conversion layer3. The thickness of the first electron transport layer13may be equal to or more than 150 nm and equal to or less than 1000 nm. (First Hole Transport Layer14) The first hole transport layer14contains a semiconductor. Examples of the semiconductor include organic and inorganic p-type semiconductors. The first hole transport layer14is formed of, for example, an inorganic material. The first hole transport layer14may contain a plurality of organic or inorganic p-type semiconductors. The band gap of the first hole transport layer14is larger than 3.0 eV. When the first photoelectric conversion layer3contains a perovskite material, the p-type inorganic semiconductor usable for the first hole transport layer14is, for example, Ni oxide or W oxide. Specifically, Ni2O3may be used. Specific examples of the p-type organic semiconductor include N2,N2,N2′,N2′,N7,N7,N7′,N7′-octakis(4-methoxyphenyl)-9,9′-spirobi[9H-fluorene]-2,2′,7,7′-tetramine (Spiro-OMeTAD) and poly(triallylamine) (PTAA). By doping the organic semiconductor with 4-tert-butylpyridine or lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), the electrical conductivity of the organic semiconductor can be increased. To facilitate the formation of the first photoelectric conversion layer3, the thickness of the first hole transport layer14may be slightly larger than the thickness of the first photoelectric conversion layer3. The thickness of the first hole transport layer14may be equal to or more than 150 nm and equal to or less than 1000 nm. (Second Electron Transport Layer15) When the second photoelectric conversion layer9contains a perovskite material, the structure of the second electron transport layer15may be the same as or different from the structure of the first electron transport layer13. The second electron transport layer15is formed of, for example, an inorganic material. To facilitate the formation of the second photoelectric conversion layer9, the thickness of the second electron transport layer15may be slightly larger than the thickness of the second photoelectric conversion layer9. The thickness of the second electron transport layer15may be equal to or more than 150 nm and equal to or less than 1000 nm. When the second photoelectric conversion layer9contains an n-type silicon single crystal, the second electron transport layer15used may be a silicon layer doped with phosphorus (P). When such a silicon layer is used for the second electron transport layer15, the second electron transport layer15can be formed by a CDV method. (Second Hole Transport Layer16) When the second photoelectric conversion layer9contains a perovskite material, the structure of the second hole transport layer16may be the same as or different from the structure of the first hole transport layer14. The second hole transport layer16is formed of, for example, an inorganic material. To facilitate the formation of the second photoelectric conversion layer9, the thickness of the second hole transport layer16may be slightly larger than the thickness of the second photoelectric conversion layer9. The thickness of the second hole transport layer16may be equal to or more than 150 nm and equal to or less than 1000 nm. When the second photoelectric conversion layer9contains an n-type silicon single crystal, a silicon layer doped with boron (B) may be used for the second hole transport layer16. When such a silicon layer is used for the second hole transport layer16, the second hole transport layer16can be formed by a CVD method. The solar cell300can be produced by, for example, the following method. First, the top cell310of the solar cell300is produced. An inorganic particle paste for the first electron transport layer13is applied to the second substrate5. Examples of the application method include screen printing, inkjet printing, a doctor blade method, a bar coating method, and a spraying method. The second substrate5coated with the first electron transport layer13is fired in an electric furnace at about 500° C. Next, an inorganic particle paste for the first hole transport layer14is applied to the second substrate5. Examples of the application method include screen printing, ink jet printing, a doctor blade method, a bar coating method, and a spraying method. The second substrate5coated with the first hole transport layer14is fired in an electric furnace at about 500° C. No particular limitation is imposed on the order of forming the first electron transport layer13and the first hole transport layer14. Among the first electron transport layer13and the first hole transport layer14, one having a higher firing temperature may be first formed. Next, the first photoelectric conversion layer3is formed on the second substrate5. First, PbI2and CH3NH3I (methylammonium Iodide: MAI) in a molar amount equal to the molar amount of PbI2are added to an organic solvent to prepare a perovskite precursor solution. The organic solvent used is, for example, a solvent mixture of dimethyl sulfoxide (DMSO): N,N-dimethylformamide (DMF)=1:1. The first photoelectric conversion layer3can be formed, for example, by applying the perovskite precursor solution. The perovskite precursor solution is applied between the first electron transport layer13and the first hole transport layer14. Examples of the application method include screen printing, inkjet printing, a doctor blade method, a bar coating method, and a spraying method. To form the first photoelectric conversion layer3, toluene may be added dropwise to the perovskite precursor solution in order to facilitate nucleation. The glass substrate coated with the perovskite precursor solution is fired on a hot plate at 100° C. for 30 minutes, and a CH3NH3PbI3film having the perovskite structure is thereby obtained. Next, the first negative electrode2and the first positive electrode4are deposited on the second substrate5by vacuum deposition. Any of the first negative electrode2and the first positive electrode4may be deposited first. Specifically, aluminum (Al) is evaporated onto the second substrate5to form the first negative electrode2. Gold (Au) is evaporated onto the second substrate5to form the first positive electrode4. A glass substrate serving as the first substrate1is stacked on the second substrate5with the first negative electrode2, the first photoelectric conversion layer3, the first positive electrode4, the first electron transport layer13, and the first hole transport layer14formed thereon. The first negative electrode2, the first photoelectric conversion layer3, the first positive electrode4, the first electron transport layer13, and the first hole transport layer14disposed between the first substrate1and the second substrate5are sealed with an epoxy resin. Then the epoxy resin is cured with UV light to produce the top cell310. Next, the bottom cell320of the solar cell300is produced. When the second photoelectric conversion layer9contains a perovskite material, the second photoelectric conversion layer9may be formed by the same method as that for the first photoelectric conversion layer3. When the second photoelectric conversion layer9contains an n-type silicon single crystal, the bottom cell components can be produced by vapor deposition, a sputtering method, a CVD method, etc. For example, a multilayer body in which the components of the bottom cell320are stacked is produced. Specifically, the second negative electrode8, the second electron transport layer15, the second photoelectric conversion layer9, the second hole transport layer16, and the second positive electrode10are formed in this order. Then the multilayer body is cut, for example, at 1 mm intervals, and the bottom cell components are thereby produced. The method for forming the second electron transport layer15may be the same as the method for forming the first electron transport layer13. The method for forming the second hole transport layer16may be the same as the method for forming the first hole transport layer14. In the present embodiment, the electron transport layers and the hole transport layers are formed of, for example, inorganic materials. Each of the electron transport layers and the hole transport layers may be formed by applying an inorganic particle paste to a substrate. Therefore, when the electron transport layers and the hole transport layers are produced, the photoelectric conversion layers containing the respective perovskite materials are unlikely to be damaged. Moreover, the electron transport layers and the hole transport layers are produced by firing at a high temperature of about 500° C. Therefore, the tandem solar cell provided has high heat resistance and high light resistance. Embodiment 4 FIG.4Ais a cross-sectional view of a solar cell400according to embodiment 4.FIG.4Bis a top view of the solar cell400according to embodiment 4. As shown inFIG.4A, the solar cell400includes a top cell410and a bottom cell420, and the top cell410and the bottom cell420each include two elements. In the top cell410, a first positive electrode4of a first one of the elements and a first negative electrode2of a second one of the elements are electrically connected through a terminal17. In the bottom cell420, a second positive electrode10of a first one of the elements and a second negative electrode8of a second one of the elements are electrically connected through a terminal17. With the above structure, the solar cell produced can have a large area. In the solar cell400, the top cell410and the bottom cell420include the same number of elements. The number of elements included in the top cell410may be the same as or different from the number of elements included in the bottom cell420. An insulating layer may be disposed between the first one and second one of the elements in the top cell410, for the purpose of preventing a short circuit and improving the accuracy of patterning. Moreover, an insulating layer may be disposed between the first one and second one of the elements in the bottom cell420, for the purpose of preventing a short circuit and improving the accuracy of patterning. In the solar cell400, each of the elements in the top cell410may further include a first electron transport layer13and a first hole transport layer14. Each of the elements in the bottom cell420may further include a second electron transport layer15and a second hole transport layer16. With the above structure, the photoelectric conversion efficiency can be improved. Embodiment 5 FIG.5Ais a cross-sectional view of a solar cell500according to embodiment 5.FIG.5Bis a top view of a top cell510of the solar cell500according to embodiment 5.FIG.5Cis a top view of a bottom cell520of the solar cell500according to embodiment 5. As shown inFIG.5A, in the solar cell500, a top cell510has the same structure as the structure of the top cell110. However, the top cell510may further include a first electron transport layer13and a first hole transport layer14. With the above structure, the photoelectric conversion efficiency can be improved. The bottom cell520is a silicon solar cell having surface electrodes. The bottom cell520includes a second substrate6, a third substrate7, a protective film18, second positive electrodes19, second positive electrodes26, a second hole transport layer20, a second hole transport layer21, a second photoelectric conversion layer22, a second electron transport layer23, a second electron transport layer24, and a second negative electrode25. The second positive electrodes19and the second positive electrodes26are disposed between the second substrate6and the second photoelectric conversion layer22. More specifically, the second hole transport layer22is disposed on the second photoelectric conversion layer21. The second hole transport layer20is disposed on the second hole transport layer21. The second positive electrodes19, the second positive electrodes26, and the protective film18are disposed on the second hole transport layer20. The second substrate6is disposed on the second positive electrodes19and26. The second negative electrode25is disposed between the third substrate7and the second photoelectric conversion layer22. More specifically, the second negative electrode25is disposed on the third substrate7. The second electron transport layer24is disposed on the second negative electrode25. The second electron transport layer23is disposed on the second electron transport layer24. The second photoelectric conversion layer22is disposed on the second electron transport layer23. A plurality of busbar electrodes19and a plurality of finger electrodes26used as the second positive electrodes are disposed on the front surface of the bottom cell520. In this structure, although the positive electrodes are disposed on the front surface of the bottom cell520, light is allowed to pass through to the photoelectric conversion layer efficiently. In the bottom cell520, for the purpose of reducing the sheet resistance on the negative electrode side, busbar electrodes and finger electrodes may be disposed between the second negative electrode25and the third substrate7. In the present specification, “the protective film18, the second positive electrodes19, the second positive electrodes26, the second hole transport layer20, the second hole transport layer21, the second photoelectric conversion layer22, the second electron transport layer23, the second electron transport layer24, and the second negative electrode25” may be referred to as a “front surface electrode-type element.” (Second Photoelectric Conversion Layer22) The second photoelectric conversion layer22is an n-type silicon layer. The second photoelectric conversion layer22used may be an n-type single crystal silicon substrate doped with phosphorus (P). (Second Hole Transport Layer21) The second hole transport layer21is an i-type amorphous silicon layer. The second hole transport layer21can be produced by forming a silicon layer on the second photoelectric conversion layer22using a CVD method. (Second Hole Transport Layer20) The second hole transport layer20is a p-type amorphous silicon layer. The second hole transport layer20is produced by forming a silicon layer doped with boron (B: boron) on the second hole transport layer21using a CVD method. (Second Positive Electrodes19and26) The second electrodes are disposed on the front surface of the bottom cell520. The second electrodes include the plurality of busbar electrodes19and the plurality of finger electrodes26. The plurality of busbar electrodes19extending parallel to each other and the plurality of finger electrodes26orthogonal to the busbar electrodes19are disposed on the front surface of the bottom cell520. The plurality of busbar electrodes19are electrically connected to each of the plurality of finger electrodes26. The plurality of busbar electrodes19are electrically connected to each other through the plurality of finger electrodes26. The busbar electrodes19each have, for example, a rectangular shape in plan view. No particular limitation is imposed on the number of busbar electrodes19disposed for one front surface electrode-type element, and the number of busbar electrodes19is, for example, 4. No particular limitation is imposed on the width of the busbar electrodes19, and the width may be from 0.5 mm to 2 mm. No particular limitation is imposed on the separation distance between the plurality of busbar electrodes19, and the separation distance may be from 25 mm to 50 mm. The finger electrodes26each have, for example, a rectangular shape in plan view. No particular limitation is imposed on the width of the finger electrodes26, and the width may be from 0.05 mm to 0.1 mm. No particular limitation is imposed on the separation distance between the plurality of finger electrodes26, and the separation distance may be from 0.3 mm to 0.6 mm. In the solar cell400in the present embodiment, the busbar electrodes19and the finger electrodes26are disposed on the front surface, i.e., the light-receiving surface, of the bottom cell520. The busbar electrodes19and the finger electrodes26are produced by applying a Ag paste. The busbar electrodes19and the finger electrodes26may also be produced by vapor deposition of Ag. The busbar electrodes19and the finger electrodes26may have light-transmitting properties. The busbar electrodes19and the finger electrodes26may be produced by forming transparent electrodes made of, for example, ITO instead of Ag by sputtering. By using the transparent electrodes made of, for example, ITO, the power generation area can be increased. (Protective Film18) The protective film18protects the front surface of the bottom cell520. The protective film18may serve also as an antireflective film. The protective film18is, for example, a silicon nitride film. The protective film18is produced by forming a SiN3layer by a CVD method. (Second Electron Transport Layer23) The second electron transport layer23is an i-type amorphous silicon layer. The second electron transport layer23is disposed on a surface of the second photoelectric conversion layer22that is opposite to the second hole transport layer21. The second electron transport layer23is produced by forming a silicon layer by a CVD method. (Second Electron Transport Layer24) The second electron transport layer24is an n-type amorphous silicon layer. The second electron transport layer24is produced by forming a silicon layer doped with phosphorus (P) on the second electron transport layer23by a CVD method. (Second Negative Electrode25) The second negative electrode25is produced by applying an Al paste. The second negative electrode25may also be produced by vapor deposition of Al. The second negative electrode25may be produced by forming a transparent electrode made of ITO instead of Al by sputtering. Embodiment 6 FIG.6Ais a cross-sectional view of a solar cell600according to embodiment 6.FIG.6Bis a top view of the solar cell600according to embodiment 6. As shown inFIG.6A, a top cell610has the same structure as the structure of the top cell410. A bottom cell620has the same structure as the structure of the bottom cell520. As shown inFIG.6A, the top cell610includes 2 elements. However, no particular limitation is imposed on the number of elements included in the top cell610. By appropriately setting the number of elements included in the top cell610, the moving distance of carriers in the first photoelectric conversion layer3of each element can be shortened. Therefore, the occurrence of recombination of the carriers in the first photoelectric conversion layer3of each element can be reduced. Moreover, since the top cell610includes the plurality of elements, a large area solar cell having, for example, a square shape with a side length of about 10 cm can be produced. Each of the elements in the top cell610may further include a first electron transport layer13and a first hole transport layer14. With this structure, the photoelectric conversion efficiency can be improved. Embodiment 7 FIG.7Ais a cross-sectional view of a solar cell700according to embodiment 7.FIG.7Bis a top view of the solar cell700. As shown inFIG.7A, a top cell710has the same structure as the structure of the top cell610. A bottom cell720includes two front surface electrode-type elements. In the front surface electrode-type elements provided in the bottom cell720, the second positive electrodes19and26included in a first one of the front surface electrode-type elements are electrically connected to the second negative electrode25included in a second one of the front surface electrode-type elements through a terminal17. With the above structure, a large area solar cell having, for example, a square shape with a side length equal to or more than 10 cm can be produced. In the solar cell700, the top cell710and the bottom cell720include the same number of elements. However, the number of elements included in the top cell710may be the same as or different from the number of elements included in the bottom cell720. An insulating layer may be disposed between the first one of the elements in the top cell710and the second one of the elements, for the purpose of preventing a short circuit and improving the accuracy of patterning. An insulating layer may be disposed between the first one of the elements in the bottom cell720and the second one of the elements, for the purpose of preventing a short circuit and improving the accuracy of patterning. Each of the elements in the top cell710may further include a first electron transport layer13and a first hole transport layer14. With this structure, the photoelectric conversion efficiency can be improved. Embodiment 8 FIG.8Ais a cross-sectional view of a solar cell800according to embodiment 8.FIG.8Bis a top view of the solar cell800according to embodiment 8. As shown inFIG.8A, a top cell810of the solar cell800has the same structure as the structure of the top cell110. However, the top cell810may further include a first electron transport layer13and a first hole transport layer14. With this structure, the photoelectric conversion efficiency can be improved. A bottom cell820is a silicon solar cell of the back contact type having back side electrodes. The bottom cell820include a second substrate6, a third substrate7, a second photoelectric conversion layer33, a second hole transport layer27, a second hole transport layer28, a second electron transport layer29, a second electron transport layer30, second positive electrodes31, and second negative electrodes32. The second positive electrodes31are disposed between the third substrate7and the second photoelectric conversion layer33. The second negative electrodes32are disposed between the third substrate7and the second photoelectric conversion layer33. More specifically, the second positive electrodes31and the second negative electrodes32are disposed on the third substrate7. The second positive electrodes31and the second negative electrodes32are arranged alternately in a direction perpendicular to the arrangement direction of the first substrate1, the second substrate5, the second substrate6, and the third substrate7. The second positive electrodes31and the second negative electrodes32are electrically isolated from each other with gaps therebetween. The second electron transport layer30, the second electron transport layer29, the second photoelectric conversion layer33, and the second substrate6are stacked in this order on the second negative electrodes32. The second hole transport layers27and28are disposed on the second positive electrodes31. In the present specification, “the second photoelectric conversion layer33, the second hole transport layer27, the second hole transport layer28, the second electron transport layer29, the second electron transport layer30, the second positive electrodes31, and the second negative electrodes32” may be referred to as a “back contact-type element.” The distance between the second positive electrodes31and the second negative electrodes32can be determined from the carrier diffusion length in the second photoelectric conversion layer33. When the second photoelectric conversion layer33contains an n-type silicon single crystal, the carrier diffusion length in the second photoelectric conversion layer33is about 100 μm. The distance between the electrodes can be set to be about 10 times the carrier diffusion length. Therefore, the distance between the second positive electrodes31and the second negative electrodes32may be equal to or more than 0.1 mm and equal to or less than 1 mm. The back contact-type silicon solar cell has no electrodes on its light-receiving surface. Therefore, the power generation area of the bottom cell820is larger than those of the front surface electrode-type solar cells. In the above structure, the light transmittance of the bottom cell820is unlikely to decrease, so that the photoelectric conversion efficiency can be improved. (Second Photoelectric Conversion Layer33) The second photoelectric conversion layer33is an n-type silicon layer. The second photoelectric conversion layer33used may be an n-type single crystal silicon substrate doped with phosphorus (P). (Second Electron Transport Layer29) The second electron transport layer29is an i-type intrinsic amorphous silicon layer. The second electron transport layer29is produced by forming a silicon layer on the second photoelectric conversion layer33by a CVD method. (Second Electron Transport Layer30) The second electron transport layer30is an n-type amorphous silicon layer. The second electron transport layer30is produced by forming a silicon layer doped with phosphorus (P) on the second electron transport layer29by a CVD method. (Second Hole Transport Layer27) The second hole transport layer27is an i-type intrinsic amorphous silicon layer. To form the second hole transport layer27, first, grooves separated from each other by a distance of about 2 mm are formed by removing part of the second electron transport layer29and part of the second electron transport layer30by etching. Then a silicon layer is formed in the grooves by a CVD method to thereby form the second hole transport layer27. (Second Hole Transport Layer28) The second hole transport layer28is a p-type amorphous silicon layer. The second hole transport layer28can be produced by forming a silicon layer doped with boron (B) on the second hole transport layer27by a CVD method. (Second Positive Electrodes31) The second positive electrodes31are formed by applying a Ag paste on the second hole transport layer28. To form the second positive electrodes31, a mask may be formed on the second electron transport layer30in advance, and Ag may be evaporated thereonto. (Second Negative Electrodes32) The second negative electrodes32are formed by forming a mask on the second positive electrodes31in advance and then evaporating Al thereonto. Embodiment 9 FIG.9Ais a cross-sectional view of a solar cell900according to embodiment 9.FIG.9Bis a top view of the solar cell900. As shown inFIG.9A, a top cell910has the same structure as the structure of the top cell410. A bottom cell920has the same structure as the structure of the bottom cell820. As shown inFIG.9A, the top cell910includes two elements. However, no particular limitation is imposed on the number of elements included in the top cell910. By appropriately setting the number of elements included in the top cell910, the moving distance of carriers in the first photoelectric conversion layer3of each element can be shortened. Therefore, the occurrence of recombination of the carriers in the first photoelectric conversion layer3of each element can be reduced. Moreover, since the top cell910includes the plurality of elements, a large area solar cell having, for example, a square shape with a side length of about 10 cm can be produced. Each of the elements in the top cell910may further include a first electron transport layer13and a first hole transport layer14. With this structure, the photoelectric conversion efficiency can be improved. Embodiment 10 FIG.10Ais a cross-sectional view of a solar cell1000according to embodiment 10.FIG.10Bis a top view of the solar cell1000according to embodiment 10. As shown inFIG.10A, a top cell1100has the same structure as the structure of the top cell910. A bottom cell1200includes two back contact-type elements. In the back contact-type elements in the bottom cell1200, a second positive electrode31of a first one of the back contact-type elements is electrically connected to a second negative electrode32of a second one of the back contact-type elements through a terminal17. With this structure, the solar cell produced can have a large area. With the above structure, while a reduction in light transmittance is prevented, the occurrence of recombination of carriers can be reduced. Since the bottom cell1200includes the plurality of elements, a large area solar cell having, for example, a square shape with a side length equal to or more than 10 cm can be produced. In the solar cell1000, the top cell1100and the bottom cell1200include the same number of elements. However, the number of elements included in the top cell1110may be the same as or different from the number of elements included in the bottom cell1200. An insulating layer may be disposed between the first one of the elements of the top cell1100and the second one of the elements, for the purpose of preventing a short circuit and improving the accuracy of patterning. An insulating layer may be disposed between the first one of the elements of the bottom cell1200and the second one of the elements, for the purpose of preventing a short circuit and improving the accuracy of patterning. Each of the elements of the top cell1100may further include a first electron transport layer13and a first hole transport layer14. With this structure, the photoelectric conversion efficiency can be improved. The structures of the four-terminal tandem solar cells in embodiments 1 to 10 are shown in Table 1. The “non-transparent electrodes” in Table 1 mean electrode that do not use a metal-doped inorganic oxide. Examples of the non-transparent electrodes include electrodes formed of metals and layered carbon materials. Examples of the layered carbon materials include graphene with no band gap. The cell structure in the “present disclosure” means a structure in which a pair of electrodes are disposed so as to sandwich a photoelectric conversion layer therebetween in a direction perpendicular to the arrangement direction of the first substrate, the second substrate, and the third substrate. (Optical Simulations of Tandem Solar Cell Having Three Transparent Electrodes) A solar cell simulator e-ARC (provided by National Research and Development Agency National Institute of Advanced Industrial Science and Technology) was used to compute the optical characteristics of a tandem solar cell having three transparent electrodes (i.e., a conventional four-terminal tandem solar cell, seeFIG.11A). First, the thicknesses of the following layers and the quality parameters of light absorption layers were inputted to the solar cell simulator e-ARC. The quality parameters of each light absorption layer include the refractive indexes n at different wavelengths and the extinction coefficients k at different wavelengths. 1. Thicknesses or Layers [Top Cell] First ITO: 500 nmMoO3: 20 nmSpiro-OMeTAD: 100 nmFAPbI3: 500 nmTiO2: 15 nmSecond ITO: 100 nmGlass: 500000 nm [Bottom Cell]Third ITO: 100 nmPEDOT/PSS: 50 nm(MAFA)(PbSn)I3: 500 nmPCBM: 30 nmAg: 100 nm 2. Quality Parameters of Light Absorption Layers The following three documents were referenced to determine the values of the refractive indexes n and extinction coefficients k per 1 nm of each layer.[1] H. Fujiwara, R. W. Collins, editors, Spectroscopic Ellipsometry for Photovoltaics: Vol. 2 Springer (2018)[2] J. Werner et al., ACS Energy Lett. 3, 742 (2018)[3] Maximilian T. Hoerantner et al., ACS Energy Lett. 2, 2506 (2017) Then the amount of reflection and the amount of absorption by each layer were outputted from the solar cell simulator e-ARC. Then the amount of reflection and the amount of absorption by each layer were used to compute external quantum efficiency (i.e., EQE) and the amount of absorption. Table 2 shows the layers and the amount of absorption by each layer (i.e., the value of current loss).FIG.11Bshows wavelength (the horizontal axis) versus the external quantum efficiency (i.e., EQE: the vertical axis). TABLE 1Materials usable forPhotoelectricelectron transportNumber ofType ofCellconversionlayers and holetransparentEmbodimentelectrodesstructurematerialtransport layerselectrodes1-4Top cellNon-transparentPresentPerovskiteNo limitation or0electrodesdisclosurematerialinorganic materialsBottomNon-transparentPresentSilicon materialNo limitation orcellelectrodesdisclosureor perovskiteinorganic materialsmaterial5-7Top cellNon-transparentPresentPerovskiteNo limitation or0 or 1electrodesdisclosurematerialinorganic materialsBottomNegative electrodeFront surfaceSilicon materialNo limitation orcellis non-transparentelectrodeor perovskiteinorganic materialselectrodematerial8-10Top cellNon-transparentPresentPerovskiteNo limitation or0electrodesdisclosurematerialinorganic materialsBottomNon-transparentBack contactSilicon—cellelectrodesmaterial TABLE 2Amount ofabsorptionLayer(mA/cm2)ITO7.646(total of threeincluding two intop cell and onein bottom cell)Spiro-OMeTAD2.825PCBM0.007Ag0.306 As shown in Table 1, the four-terminal tandem solar cells according to embodiments 1 to 10 use no or one transparent electrode. However, the conventional four-terminal tandem solar cell requires three transparent electrodes. In the four-terminal tandem solar cells having the structure of the present disclosure, the use of the transparent electrodes can be avoided. When the electrodes are eliminated from the light-receiving surfaces, the light transmittance is unlikely to decrease. Moreover, since the electrodes used can each be a non-transparent electrode formed of a metal material, the electrical resistance is unlikely to increase. Therefore, the power generation efficiency of the solar cells can also be improved. As shown inFIG.11Band Table 2, the amount of absorption by ITO, which is one type of transparent electrode, is higher than those of other layers. This amount of absorption is the value of current loss by the ITO. In the above embodiments, the number of transparent electrodes is smaller than that in the conventional four-terminal tandem solar cell. It is therefore expected to reduce the value of current loss in the solar cells. The technique of the present disclosure is useful for four-terminal tandem solar cells. | 100,666 |
11943942 | DETAILED DESCRIPTION Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. It should be noted that the present invention is not limited to the embodiments described below. The numerals and materials cited in Embodiments are only illustrative. The embodiments of the present disclosure will be described in the following order.1. Electronic Device, Solid State Imaging Apparatus, and Method of Producing Electrode for Electronic Device according to First or Second Embodiment of Present Disclosure, General Description2. First Embodiment (Electronic Device and Method of Producing Electrode for Electronic Device according to First Embodiment of Present Disclosure)3. Second Embodiment (Electronic Device and Method of Producing Electrode for Electronic Device according to Second Embodiment of Present Disclosure)4. Third Embodiment (Solid State Imaging Apparatus according to First or Second Embodiment of Present Disclosure), Others [Electronic Device, Solid State Imaging Apparatus, and Method of Producing Electrode for Electronic Device according to First or Second Embodiment of Present Disclosure, General Description] An electronic device according to a first embodiment of the present disclosure, an electronic device configuring the solid state imaging apparatus according to a first embodiment of the present disclosure, and an electronic device provided by the method of producing the electrode for the electronic device according to a first embodiment of the present disclosure may be hereinafter referred collectively to as “electronic devices according to a first embodiment of the present disclosure”). An electronic device according to a second embodiment of the present disclosure, an electronic device configuring the solid state imaging apparatus according to a second embodiment of the present disclosure, and an electronic device provided by the method of producing the electrode for the electronic device according to a second embodiment of the present disclosure may be hereinafter referred collectively to as “electronic devices according to a second embodiment of the present disclosure”). A method of producing an electrode for the electronic device according to a first embodiment of the present disclosure and a method of producing an electrode for the electronic device according to a second embodiment of the present disclosure may be hereinafter referred collectively to as “methods of producing the electrodes in the electronic devices according to the present disclosure”). In the electronic devices according to a first embodiment of the present disclosure or in the method of producing an electrode for the electronic device according to a first embodiment of the present disclosure, a difference between a work function value of the second electrode and a work function value of the first electrode being 0.4 eV or more, thereby, based on the difference between the work function values, generating an internal electric field in the photoelectric conversion layer to improve an internal quantum efficiency. In the electronic devices according to a second embodiment of the present disclosure or in the method of producing an electrode for the electronic device according to a second embodiment of the present disclosure, a difference between the work function value of the first A layer of the first electrode and the work function of the first B layer of the first electrode is desirably 0.1 eV to 0.2 eV, and a difference between a work function value of the second electrode and a work function value of the first electrode being 0.4 eV or more. In the electronic devices according to the second embodiment of the present disclosure or in the method of producing an electrode for the electronic device according to the second embodiment of the present disclosure, the first electrode has a thickness of 1×10−8 m to 1×10−7 m. A ratio between the thickness of the first A layer of the first electrode and the thickness of the first B layer of the first electrode can be 9/1 to 1/9. In order to diminish effects of oxygen atoms or oxygen molecules on the photoelectric conversion layer, the first B layer of the first electrode is more desirably thinner than the first A layer of the first electrode. In the electronic devices according to the first embodiment of the present disclosure including the above-described embodiments or in the method of producing an electrode for the electronic device according to the first embodiment of the present disclosure, the first electrode has a thickness of 1×10−8 m to 1×10−7 m. In the electronic devices according to the second embodiment of the present disclosure including the above-described embodiments or in the method of producing an electrode for the electronic device according to the second embodiment of the present disclosure, a difference between a work function value of the second electrode and a work function value of the first A layer of the first electrode being 0.4 eV or more, thereby, based on the difference between the work function values, generating an internal electric field in the photoelectric conversion layer to desirably improve an internal quantum efficiency. In the electronic devices according to the first to the second embodiments of the present disclosure including a variety of the above-described embodiments and the methods of producing the electrodes in the electronic devices according to the present disclosure, the work function value of the first electrode is not limited, but can be 4.1 eV to 4.5 eV, for example. In the electronic devices according to the first to the second embodiments of the present disclosure including a variety of the above-described embodiments and the methods of producing the electrodes in the electronic devices according to the present disclosure, the first electrode is composed of a transparent conductive material such as indium gallium complex oxide (IGO), indium-doped gallium zinc complex oxide (IGZO, In—GaZnO4), aluminum oxide-doped zinc oxide (AZO), indium zinc complex oxide (IZO) and gallium-doped zinc oxide (GZO). The first electrode composed of the transparent conductive material has the work function value of 4.1 eV to 4.5 eV, for example. In the electronic devices according to the first to the second embodiments of the present disclosure or in the methods of producing the electrodes in the electronic devices according to the present disclosure, the second electrode is composed of indium tin complex oxide (ITO), indium zinc complex oxide (IZO) and tin oxide (SnO2). The second electrode composed of the transparent conductive material has the work function value of 4.8 eV to 5.0 eV, for example. In the electronic devices according to the first to the second embodiments of the present disclosure or in the methods of producing the electrodes in the electronic devices according to the present disclosure, the first electrode has desirably light transmittance of 80% or more at wavelengths of 400 nm to 660 nm. Also, the second electrode has desirably light transmittance of 80% or more at wavelengths of 400 nm to 660 nm. Furthermore, in the electronic devices according to the first to the second embodiments of the present disclosure or in the methods of producing the electrodes in the electronic devices according to the present disclosure including the above-described embodiments and configurations, the first electrode has desirably a sheet resistance value of 3×10 Ω/square to 1×103 Ω/square. In the electronic devices according to the first to the second embodiments of the present disclosure including the above-described embodiments and configurations, the oxygen gas introduction amount (the oxygen gas partial pressure) is controlled when the first electrode is formed by a sputtering method, thereby controlling the work function value of the first electrode. Also, the oxygen gas introduction amount (the oxygen gas partial pressure) is controlled when the first electrode is formed by a sputtering method, thereby controlling the work function values of the first A layer and the first B layer of the first electrode. Moreover, in the electronic devices according to the first to the second embodiments of the present disclosure including the above-described embodiments and configurations, an oxygen content rate of the first electrode is less than an oxygen content rate of a stoichiometric composition. Based on the oxygen content rate, the work function value of the first electrode can be controlled. The lower the oxygen content rate of the first electrode than the oxygen content rate of the stoichiometric composition is, i.e., the higher oxygen defects are, the lower the work function value is. The oxygen content of the first A layer of the first electrode is lower than that of the first B layer of the first electrode. In the electronic devices according to the first to the second embodiments of the present disclosure including the above-described embodiments and configurations, the electronic device is a photoelectric conversion element. In the methods of producing the electrodes in the electronic devices according to the present disclosure, the electrode can be used for the photoelectric conversion element. In the methods of producing the electrodes in the electronic devices according to the present disclosure including a variety of the embodiments, an oxygen content rate of the first electrode is less than an oxygen content rate of a stoichiometric composition. In the method of producing the electrode for the electronic device according to the second embodiment of the present disclosure, the oxygen content of the first A layer of the first electrode is lower than that of the first B layer of the first electrode. In the electronic devices according to the first to the second embodiments of the present disclosure (hereinafter may be referred collectively to as “electronic devices according to the present disclosure) including the above-described embodiments and configurations, the first electrode is formed on the substrate, the photoelectric conversion layer is formed on the first electrode, and the second electrode is formed on the photoelectric conversion layer, or the second electrode is formed on the substrate, the photoelectric conversion layer is formed on the second electrode, and the first electrode is formed on the photoelectric conversion layer. In other words, the present electronic devices have a two-terminal electronic device structure including the first electrode and the second electrode. However, the present electronic devices are not limited thereto, and may have a three-terminal electronic device structure further including a control electrode. When a voltage is applied to the control electrode, a flowing current can be modulated. Examples of the three-terminal electronic device structure include the same structure or configuration as a so-called bottom gate/bottom contact type, bottom gate/top contact type, top gate/bottom contact type, or top gate/top contact type field effect transistor (FET). The first electrode can function as a cathode (negative) electrode (in other words, an electrode for taking out electrons), and the second electrode can function as an anode (positive) electrode (in other words, an electrode for taking out holes). A plurality of electronic devices including the photoelectric conversion layers having different light absorption spectra may be laminated. For example, the substrate may be a silicon semiconductor substrate. On the silicon semiconductor substrate, a driving circuit and a photoelectric conversion layer for the electronic device may be disposed. The electronic devices may be laminated on the silicon semiconductor substrate. The photoelectric conversion layer may be amorphous or crystal. As an organic material of the photoelectric conversion layer, an organic semiconductor material, an organic metal compound, an organic semiconductor microparticle, a metal oxide semiconductor, an inorganic semiconductor microparticle, a material including a core member covered with a shell member, and an organic-inorganic hybrid compound can be used. Examples of the organic semiconductor material include an organic dye such as quinacridone and a derivative thereof, a dye where a preceding cycle (metal left side periodic table) ion is chelated with an organic material such as Alq3 [tris(8-quinolinolato)aluminum (III)], an organic metal dye complex formed by a transition metal ion and an organic material such as phthalocyanine zinc (II), dinaphthothienothiophene (DNTT) and the like. As the organic metal compound, the dye where the preceding cycle ion is chelated with the organic material or the organic metal dye complex formed by the transition metal ion and the organic material can be used. Examples of the organic semiconductor microparticle include an organic dye aggregate such as the above-described quinacridone and the derivative thereof, a dye aggregate where the preceding cycle ion is chelated with the organic material, an organic metal dye aggregate complex formed by the transition metal ion and the organic material, Prussian blue where a metal ion is cross-linked with cyano groups or a complex aggregate thereof. Examples of the metal oxide semiconductor and the inorganic semiconductor microparticle include ITO, IGZO, ZnO, IZO, IrO2, TiO2, SnO2, SiOx, a metal chalcogen semiconductor containing chalcogen [for example, sulfur (S), selenium (Se), tellurium (Te)] (specifically, CdS, CdSe, ZnS, CdSe/CdS, CdSe/ZnS, PbSe), ZnO, CdTe, GaAs and Si. Examples of the material including the core member covered with the shell member, i.e., a combination of the core member and the shell member, include an organic material such as polystyrene and polyaniline and a metal material that is difficult or easy to be ionized. Examples of the organic-inorganic hybrid compound include Prussian blue where a metal ion is cross-linked with cyano groups or a derivative thereof, metal ions endlessly cross-linked with pipyridines, and a coordination polymer that is a collective term of metal ions cross-linked with multivalent ion acid such as oxalic acid and rubeanic acid. The photoelectric conversion layer is formed by a coating method, a physical vapor deposition (PVD) method or a variety of chemical vapor deposition (CVD) method including a MOCVD method, depending on the material used. Examples of the coating method include a variety of printing methods such as a spin coating method, an immersion method, a cast method, a screen printing method, an inkjet printing method, an offset printing method and a gravure printing method; a stamp method; a spray method; a variety of coating method such as an air doctor coater method, a blade coater method, a rod coater method, a knife coater method, a squeeze coater method, a reverse roll coater method, a transfer roll coater method, a gravure coater method, a kiss coater method, a cast coater method, a spray coater method, a slit orifice coater method and a calendar coater method. In the coating method, a non-polar or low polar organic solvent such as toluene, chloroform, hexane and ethanol can be used. Examples of the PVD method include a variety of vacuum vapor deposition methods such as an electron beam heating method, a resistive heating method and a flash vapor deposition; a plasma vapor deposition method; a variety of sputtering methods such as a diode sputtering method, a DC (direct current) sputtering method, a DC magnetron sputtering method, a high frequency sputtering method, a magnetron sputtering method, an ion beam sputtering method and a bias sputtering method; and a variety of ion plating methods such as a DC method, an RF method, a multicathode method, an activation reaction method, an electric field vapor deposition method, a high frequency ion plating method, and a reactive ion plating method. The photoelectric conversion layer has a non-limiting thickness of 1×10−10 m to 5×10−7 m. The first electrode is formed by the sputtering method. Specifically, the sputtering method includes a magnetron sputtering method, a parallel flat plate sputtering method, and a plasma generation method using DC discharge or RF discharge. According to the present disclosure, the work function can be advantageously controlled by an oxygen flow rate (the oxygen gas introduction amount, the oxygen gas partial pressure). The second electrode is formed by the PVD method such as a vacuum vapor deposition method, a reactive vapor deposition method, a variety of sputtering methods, an electron beam vapor deposition method and an ion plating method, a pyrosol method, a method of thermally decomposing an organic metal compound, a spray method, a dipping method, a variety of CVD methods including a MOCVD method, a electroless plating method and an electrolytic plating method. Examples of the material of the substrate include an organic polymer (having a configuration of a polymer material such as a plastic film, a plastic sheet and a plastic substrate having a flexibility composed of the polymeric material) including polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN). When the substrate composed of the flexible polymer material is used, the electronic device can be incorporated into or integrated with the electronic apparatus having a curved shape, for example. Also, examples of the substrate include a variety of glass substrates, a variety of glass substrates each having an insulation film formed on each surface, a quartz substrate, a quartz substrate having an insulation film formed on the surface, a silicon semiconductor substrate, a silicon semiconductor substrate having an insulation film formed on the surface, and a metal substrate composed of an alloy or a metal including stainless steel. Examples of the insulation film include an silicon oxide material (SiOx and spin-on glass(SOG)); silicon nitride (SiNY); silicon oxynitride (SiON); aluminum oxide (Al2O3); a metal oxide and a metal salt. Also, a conductive substrate having the insulation film formed on the surface (a metal substrate including gold, aluminum etc., or a highly oriented graphite substrate) can be used. The surface of the substrate is desirably smooth, but may have roughness as long as the properties of the photoelectric conversion layer are not adversely affected. On the surface of the substrate, a silanol derivative is formed by a silane coupling method, a thin film composed of a thiol derivative, a carboxylic acid derivative, a phosphoric acid derivative etc. is formed by a SAM method, or a thin film composed of an insulated metal salt or metal complex is formed by a CVD method, thereby improving adhesion between the first electrode or the second electrode and the substrate. In some cases, the first electrode or the second electrode may be coated with a coating layer. Examples of the coating layer include an inorganic insulation material, e.g., a high dielectric insulation film of a metal oxide including a silicon oxide material, silicon nitride (SiNY) and aluminum oxide (Al2O3); an organic insulation material (an organic polymer) such as polymethyl methacrylate (PMMA), polyvinyl phenol (PVP), polyvinyl alcohol (PVA), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polystyrene, a silanol derivative including N-2(aminoethyl)3-aminopropyl trimethoxysilane (AEAPTMS), 3-mercaptopropyl trimethoxysilane (MPTMS) and octadecyl trichlorosilane (OTS), straight chain hydrocarbons having a functional group being capable of bonding to the control electrode at one end including octadecane thiol and dodecyl isocyanate; and a combination thereof. Examples of the silicon oxide material include silicon oxide (SiOX), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on glass) and a low dielectric material (for example, polyarylether, cycloperfluorocarbon polymer, benzocyclobutene, cyclic fluoro resin, polytetrafluoroethylene, fluorinated arylether, fluorinated polyimide, amorphous carbon and organic SOG). The insulation layer can be formed by a variety of the PVD methods described above, a variety of the CVD methods described above, a spin coat method, a variety of the coating method described above, a sol-gel method, an electrodeposition method, a shadow mask method or a spray method. The electronic device according to an embodiment of the present disclosure can be used for an optical sensor and an image sensor as well as an imaging apparatus (a solid state imaging apparatus) such as a television camera. First Embodiment The first embodiment refers to an electronic device according to a first embodiment of the present disclosure and a method of producing an electrode for the electronic device according to a first embodiment of the present disclosure.FIG.1Bshows a schematic partial sectional view of the electronic device. Specifically, the electronic device according to the first embodiment or the second embodiment described below includes the photoelectric conversion element, and has a first electrode21, a second electrode22and a photoelectric conversion layer23sandwiched between the first electrode21and the second electrode22. The first electrode21includes an amorphous oxide composed of at least a quaternary compound [Ina(Ga, Al)bZncOd] of indium (In), gallium (Ga) and/or aluminum (Al), zinc (Zn) and oxygen (O). Here, “a”, “b”, “c” and “d” can have a variety of values. More specifically, in the electronic device according to the first embodiment, the second electrode22is formed on a substrate10composed of a silicon semiconductor substrate, the photoelectric conversion layer23is formed on the second electrode22, and the first electrode21is formed on the photoelectric conversion layer23. Thus, the electronic device according to the first embodiment or the second embodiment described below has a two-terminal electronic device structure including the first electrode21and the second electrode22. In the electronic device according to the first embodiment or the second embodiment described below a difference between a work function value of the second electrode22and a work function value of the first electrode21is 0.4 eV or more. By setting the difference between the work function value of the second electrode22and the work function value of the first electrode21to 0.4 eV or more, based on the difference between the work function values, an internal electric field is generated in the photoelectric conversion layer23to improve an internal quantum efficiency. The first electrode21can function as a cathode (negative) electrode. In other words, the first electrode21can function as an electrode for taking out electrons. On the other hand, the second electrode22can function as an anode (positive) electrode. In other words, the second electrode22can function as an electrode for taking out holes. The photoelectric conversion layer23is composed of quinacridone having a thickness of 100 μm. More specifically, according to the first embodiment, the first electrode21is composed of a transparent conductive material such as indium-doped gallium zinc complex oxide (IGZO). The second electrode22is composed of a transparent conductive material such as indium tin complex oxide (ITO). IGZO has the work function value of 4.1 eV to 4.2 eV depending on the film formation conditions. ITO has the work function value of 4.8 eV to 5.0 eV depending on the film formation conditions. Other materials of the first electrode21include indium gallium complex oxide (IGO), aluminum oxide-doped zinc oxide (AZO), indium zinc complex oxide (IZO) and gallium-doped zinc oxide (GZO). Other materials of the second electrode22include indium zinc complex oxide (IZO) and tin oxide (SnO2). The above-described description is also applicable to the second embodiment as described below. In the electronic device according to the first embodiment or the second embodiment described below, the first electrode21has light transmittance of 80% or more at wavelengths of 400 nm to 660 nm. Also, the second electrode22has light transmittance of 80% or more at wavelengths of 400 nm to 660 nm. The light transmittances of the first electrode21and the second electrode22can be measured by forming the first electrode21and the second electrode22on a transparent glass plate. The first electrode21has a sheet resistance value of 3×10 Ω/square to 1×103 Ω/square. More specifically, the first electrode21composed of IGZO having a thickness of 100 μm has a sheet resistance value of 800 Ω/square. Hereinafter, a method of producing an electrode for the electronic device according to the first embodiment, specifically, a method of producing the first electrode, will be described referring toFIGS.1A and1B. The electrode provided by the method of producing the electrode for the electronic device according to the first embodiment is an electrode for a photoelectric conversion element. [Process100] The substrate10composed of a silicon semiconductor substrate is prepared. The substrate10includes a driving circuit (not shown) and a photoelectric conversion layer (not shown) for the electronic device, and wiring11. On the surface of the substrate10, an insulation layer12is formed. The insulation layer12has an opening13where the wiring11is exposed on a bottom. On the insulation layer12and within the opening13, the second electrode22composed of ITO is formed (film-formed) by a sputtering method (seeFIG.1A). [Process110] Next, the second electrode22is patterned. Thereafter, on an entire surface, the photoelectric conversion layer23composed of quinacridone is formed (film-formed) by a vacuum vapor deposition method. In addition, on the photoelectric conversion layer23, the first electrode21composed of IGZO is formed (film-formed) by a sputtering method. In this way, the electronic device having the structure shown inFIG.1Baccording to the first embodiment can be provided. An oxygen gas introduction amount (an oxygen gas partial pressure) is controlled when the first electrode21is formed by a sputtering method to control the work function value of the first electrode21.FIG.2Ais a graph showing a relationship between the oxygen gas partial pressure and the work function value of the first electrode21. The higher the value of the oxygen gas partial pressure is, i.e., the lower the oxygen defects are, the higher the work function value of the first electrode21is. The lower the value of the oxygen gas partial pressure is, i.e., the higher the work function value of the first electrode21is, the lower the work function value of the first electrode21is. As the sputtering apparatus, a parallel flat plate sputtering apparatus or a DC magnetron sputtering apparatus is used. As the process gas, an argon (Ar) gas is used. As the target, an InGaZnO4 sintered body is used. In this way, in the electronic device according to the first embodiment, the oxygen gas introduction amount (the oxygen gas partial pressure) is controlled when the first electrode21is formed by a sputtering method to control the work function value of the first electrode21. The oxygen content rate of the first electrode21is less than the oxygen content rate of the stoichiometric composition. FIG.2Bis a graph showing an I-V curve of the electronic devices (the photoelectric conversion elements) according to the first embodiment and the first comparative embodiment. InFIG.2B, “A” represents a measured result of the electronic device according to the first embodiment, “B” represents a measured results of the electronic device according to the second embodiment as described below and “C” represents a measure result of the electronic device according to the first comparative embodiment. The electronic device according to the first comparative embodiment is similar to that according to the first embodiment except that the first electrode21is composed of ITO instead of IGZO.FIG.2Breveals that in the electronic device according to the first embodiment or the second embodiment described below, a current value is steeply increased at a reverse bias voltage of little less than 1 volt (at a bias voltage of little less than −1 volt). Table 1 shows values of internal quantum efficiency and values of on/off ratios of the electronic devices according to the first embodiment and the first comparative embodiment. The internal quantum efficiency η is a ratio of incident photon numbers to generated electron numbers, and can be represented by the following equation.η={(h·c)/(q·λ)}(I/P)=(1.24/λ)(I/P)whereh: Planck's constantc: light speedq: electron chargeλ: wavelength (μm) of incident lightI: light current; a current value (ampere/cm2) at the reverse bias voltage of 1 volt measured in the first embodimentP: power of incident light (ampere/cm2) TABLE 1Internal quantumOn/offefficiency (%)ratioFirst Embodiment392.6Second Embodiment553.4First Comparative5.41.4Embodiment In the electronic device according to the first comparative embodiment where both of the first and second electrodes are composed of ITO, there is no difference between the work function value of the second electrode and the work function value of the first electrode as shown in a conceptual view of an energy diagram inFIG.3B. Therefore, the holes are easily flowed from the second electrode to the first electrode, which results in an increased dark current. In addition, as there is no difference between the work function value of the second electrode and the work function value of the first electrode, no potential gradient is present (in other words, no internal electric field is generated in the photoelectric conversion layer) when the electrons and the holes are taken out, which makes difficult to take out the electrons and the holes smoothly (see a conceptual view inFIG.3D). On the other hand, in the electronic device according to the first embodiment where the first electrode is composed of IGZO and second electrode is composed of ITO, a difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more.FIG.3Ashows a conceptual view of an energy diagram. Therefore, the holes are prevented from flowing from the second electrode to the first electrode, which results in a prevention of a dark current. In addition, as there is a difference between the work function value of the second electrode and the work function value of the first electrode of 0.4 eV or more, a potential gradient is generated (in other words, an internal electric field is generated in the photoelectric conversion layer) when the electrons and the holes are taken out. By utilizing the potential gradient, the electrons and the holes can be taken out smoothly (see a conceptual view inFIG.3C). In addition,FIG.4Ais a graph showing a correlation of a difference between the internal quantum efficiency and the work function value.FIG.4Bis a graph showing a correlation of a difference between the dark current (the current value provided when no light is irradiated at the reverse bias voltage of 1 volt measured in the first embodiment) and the work function value. A horizontal axis in each ofFIGS.4A and4Brepresents the difference between the work function value of the second electrode22and the work function value of the first electrode21. A horizontal axis in each ofFIGS.5A and5Bas described below represents the difference between the work function value of a first B layer21B of the first electrode21and the work function value of a first A layer21A of the first electrode21.FIGS.4A and4Breveal that the internal quantum efficiency is obviously increased and the dark current is obviously decreased at around 0.4 eV of the difference between the work function values. As described above, as the difference between the work function value of the second electrode and the difference between the work function value of the first electrode in the electronic device according to the first embodiment is specified, a large internal electric field can be generated in the photoelectric conversion layer based on the difference between the work function values, when the bias voltage (specifically, the reverse bias voltage) is applied between the first electrode and the second electrode. As a result, the internal quantum efficiency can be improved, i.e., the photocurrent can be increased. In addition, the dark current can be suppressed. In the method of producing an electrode for the electronic device according to the first embodiment, the oxygen gas introduction amount (the oxygen gas partial pressure) is controlled when the first electrode is formed by a sputtering method to control the work function value of the first electrode. As a result, a large internal electric field can be generated in the photoelectric conversion layer based on the difference between the work function values, thereby improving the internal quantum efficiency, i.e., the photocurrent can be increased. In addition, an electronic device being capable of suppressing a dark current can be generated simply. Second Embodiment The second embodiment refers to an electronic device and a method of producing an electrode for the electronic device according to a second embodiment of the present disclosure.FIG.1Cis a schematic partial sectional view of the electronic device according to the second embodiment. In the electronic device according to the second embodiment, the first electrode21has a laminated structure including the first B layer21B and the first A layer21A from the photoelectric conversion layer side. A work function value of the first A layer21A of the first electrode21is lower than a work function of the first B layer21B of the first electrode21. Specifically, a difference between the work function value of the first A layer21A of the first electrode21and the work function of the first B layer21B of the first electrode21is 0.1 eV to 0.2 eV, more specifically, 0.15 eV. A difference between the work function value of the second electrode22and the work function of the first A layer21A of the first electrode21is 0.4 eV or more. The first electrode21has a thickness of 1×10−8 m to 1×10−7 m, specifically 50 nm. A ratio between the thickness of the first A layer21A of the first electrode21and the thickness of the first B layer21B of the first electrode21is 9/1 to 1/9, specifically 9/1. Also, according to the second embodiment of the present disclosure, a difference between the work function value of the second electrode22and the work function value of the first A layer21A of the first electrode21is set to 0.4 eV or more, thereby, based on the difference between the work function values, generating an internal electric field in the photoelectric conversion layer to improve an internal quantum efficiency. When the composition of the first A layer21A is [Ina(Ga, Al)bZncOd] and the composition of the first B layer21bis [Ina′(Ga, Al)b′Znc′Od′], a=a′, b=b′, c=c′ and d<d′. Table 1 shows values of internal quantum efficiency and values of on/off ratios of the electronic devices according to the second embodiment.FIG.2Bshows an I-V curve of the electronic device (the photoelectric conversion element) according to the second embodiment.FIG.5Ais a graph showing a correlation of a difference between the internal quantum efficiency and the work function value.FIG.5Bis a graph showing a correlation of a difference between a dark current (the current value provided when no light is irradiated at the reverse bias voltage of 1 volt measured also in the second embodiment) and the work function value.FIGS.5A and5Breveal that the internal quantum efficiency is obviously increased and the dark current is obviously decreased as the difference between the work function value of the first A layer of the first electrode and the work function value of the first B layer of the first electrode is increased to around 0.2 eV. In the method of producing the electrode for the electronic device according to the second embodiment, the oxygen gas introduction amount is controlled when the first electrode is formed by a sputtering method in a process similar to [Process-110] in the first embodiment, thereby controlling the work function values of the first A layer21A and the first B layer21B of the first electrode2, as shown in the graph inFIG.2A. In the electronic device according to the second embodiment, the first electrode has the first A layer and the first B layer, and the difference between the work function values of the first A layer and the first B layer is specified. Therefore, the work function of the first electrode can be optimized, thereby exchanging (migrating) carriers more easily.[Third Embodiment] The third embodiment refers to a solid state imaging apparatus according to an embodiment of the present disclosure. The solid state imaging apparatus according to the third embodiment include the electronic device (specifically, the photoelectric conversion element) according to the first embodiment or second embodiment. FIG.6is a conceptual view of the solid state imaging apparatus (the solid state imaging element) according to the third embodiment. A solid state imaging apparatus40according to the third embodiment is composed of an imaging area41where the electronic devices (the photoelectric conversion elements)30described in the first embodiment or the second embodiment are arranged in a two dimensional array on the semiconductor substrate (for example, the silicon semiconductor substrate), a vertical driving circuit42, column signal processing circuits43, a horizontal driving circuit44, an output circuit45and a control circuit46, etc. all of which are peripheral circuits. These circuits can be configured of well-known circuits. It will be appreciated that other circuit configurations (for example, a variety of circuits used in a CCD imaging apparatus and a CMOS imaging apparatus in the related art) can be used. The control circuit46generates clock signals and control signals for operating the vertical driving circuit42, the column signal processing circuits43and the horizontal driving circuit44based on vertical synchronizing signals, horizontal synchronizing signals and a master clock. The clock signals and the control signals generated are inputted to the vertical driving circuit42, the column signal processing circuits43and the horizontal driving circuit44. The vertical driving circuit42is composed of shift resistors, for example, and selects and scans sequentially the respective electronic devices30in the imaging area41per row in a vertical direction. Pixel signals based on a current (signals) generated depending on the amount of light received in the respective electronic devices30are sent to the column signal processing circuits43via vertical signal lines47. The column signal processing circuits43are arranged per column of the electronic devices30, for example, and perform signal processings such as noise removal and signal amplification of signals outputted from the electronic devices30in a row by signals from black reference pixels (not shown, formed around effective pixel regions) per electronic device. Horizontal selection switches (not shown) are disposed and connected between the output stages of the column signal processing circuits43and a horizontal signal line48. The horizontal driving circuit44is configured of shift resistors, for example, and sequentially outputs a horizontal scan pulse to sequentially select the respective column signal processing circuits43and to output signals from the respective column signal processing circuits43to the horizontal signal line48. The output circuit45performs signal processing to the signals sequentially supplied from the respective column signal processing circuits43via the horizontal signal line48and outputs them. Although it depends on the materials of the photoelectric conversion layer, the photoelectric conversion layer itself can function as a color filter. Therefore, when no color filter is disposed, a color separation is possible. However, as the case may be, a well-known color filter that transmits a specific wavelength such as red, green, blue, cyan, magenta, yellow or the like may be disposed above the electronic devices30at a light incident side. The solid state imaging apparatus may be a surface irradiation type or a rear surface irradiation type. In addition, a shutter may be disposed in order to control light incident on the electronic devices30, as necessary. While the present disclosure is described herein with reference to illustrative embodiments, it should be understood that the present disclosure is not limited thereto. The structure, the configuration, the production conditions, the production method, and the materials used for the electronic devices (the photoelectric conversion element) and the solid state imaging apparatus described in Embodiment are illustrative and can be changed as necessary. When the electronic device according to the embodiment of the present disclosure is used as a solar cell, the photoelectric conversion layer may be irradiated with light while no voltage is applied between the first electrode and the second electrode. The electronic device according to the embodiment of the present disclosure can be used for an optical sensor and an image sensor as well as the imaging apparatus (the solid state imaging apparatus) such as a television camera. The present disclosure may have the following configurations.[A01]<<Electronic Device: First Embodiment>> An electronic device, including:a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode,the first electrode including an amorphous oxide composed of at least a quaternary compound of indium, gallium and/or aluminum, zinc and oxygen, anda difference between a work function value of the second electrode and a work function value of the first electrode being 0.4 eV or more.[A02] The electronic device according to [A01] above, in whicha difference between a work function value of the second electrode and a work function value of the first electrode is set to 0.4 eV or more, andbased on the difference between the work function values, an internal electric field is generated in the photoelectric conversion layer to improve an internal quantum efficiency.[BO1]<<Electronic Device: Second Embodiment>> An electronic device, including:a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode,the first electrode including an amorphous oxide composed of at least a quaternary compound of indium, gallium and/or aluminum, zinc and oxygen,the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side, anda work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode.[B02] The electronic device according to [BO1] above, in which a difference between the work function value of the first A layer21A of the first electrode21and the work function of the first B layer21B of the first electrode21is 0.1 eV to 0.2 eV.[B03] The electronic device according to [B01] or [B02] above, in whicha difference between a work function value of the second electrode and a work function value of the first A layer of the first electrode is 0.4 eV or more.[B04] The electronic device according to any one of [B01] to [B03] above, in whichthe first electrode has a thickness of 1×10−8 m to 1×10−7 m, anda ratio between the thickness of the first A layer of the first electrode and the thickness of the first B layer of the first electrode is 9/1 to 1/9.[B05] The electronic device according to any one of [B01] to [B04] above, in whicha difference between a work function value of the second electrode and a work function value of the first electrode is set to 0.4 eV or more, andbased on the difference between the work function values, an internal electric field is generated in the photoelectric conversion layer to improve an internal quantum efficiency.[C01] The electronic device according to any one of [A01] to [B05] above, in which the work function value of the first electrode is 4.1 eV to 4.5 eV.[C02] The electronic device according to any one of [A01] to [C01] above, in whichthe first electrode is composed of indium gallium complex oxide, indium-doped gallium zinc complex oxide, aluminum oxide-doped zinc oxide indium zinc complex oxide or gallium-doped zinc oxide.[C03] The electronic device according to any one of [A01] to [c02] above, in whichthe second electrode is composed of indium tin complex oxide, indium zinc complex oxide or tin oxide.[C04] The electronic device according to any one of [A01] to [C03] above, in whichthe first electrode has light transmittance of 80% or more at wavelengths of 400 nm to 660 nm.[C05] The electronic device according to any one of [A01] to [C04] above, in whichthe first electrode has a sheet resistance value of 3×10 Ω/square to 1×103 Ω/square.[C06] The electronic device according to any one of [A01] to [C05] above, in whichan oxygen gas introduction amount is controlled when the first electrode is formed by a sputtering method to control the work function value of the first electrode.[C07] The electronic device according to any one of [A01] to [C06] above, in whichan oxygen content rate of the first electrode is less than an oxygen content rate of a stoichiometric composition.[C08] The electronic device according to any one of [A01] to [C07] above, which is a photoelectric conversion element.[D01] A solid state imaging apparatus including the electronic device according to any one of [A01] to [C08] above.[E01]<<Method of Producing Electrode for Electronic Device: First Embodiment>> A method of producing an electrode for an electronic device including a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode,the first electrode including an amorphous oxide composed of at least a quaternary compound of indium, gallium and/or aluminum, zinc and oxygen,a difference between a work function value of the second electrode and a work function value of the first electrode being 0.4 eV or more,an oxygen gas introduction amount being controlled when the first electrode is formed by a sputtering method to control the work function value of the first electrode.[E02] The method of producing an electrode for the electronic device according to [E01], in whicha difference between a work function value of the second electrode and a work function value of the first electrode is set to 0.4 eV or more, andbased on the difference between the work function values, an internal electric field is generated in the photoelectric conversion layer to improve an internal quantum efficiency.[E03]<<Method of Producing Electrode for Electronic Device: Second Embodiment>> A method of producing an electrode for an electronic device including a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode,the first electrode including an amorphous oxide composed of at least a quaternary compound of indium, gallium and/or aluminum, zinc and oxygen,the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side,a work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode, andan oxygen gas introduction amount being controlled when the first electrode is formed by a sputtering method to control the work function value of the first electrode.[E04] The method of producing an electrode for the electronic device according to [E03] in which,a difference between a work function value of the second electrode and a work function value of the first A layer of the first electrode is 0.4 eV or more.[E05] The method of producing an electrode for the electronic device according to [E03] or [E04] in which,the first electrode has a thickness of 1×10−8 m to 1×10−7 m, anda ratio between the thickness of the first A layer of the first electrode and the thickness of the first B layer of the first electrode is 9/1 to 1/9.[E06] The method of producing an electrode for the electronic device according to any one of [E03] to [E05 in which,a difference between a work function value of the second electrode and a work function value of the first electrode is set to 0.4 eV or more, andbased on the difference between the work function values, an internal electric field is generated in the photoelectric conversion layer to improve an internal quantum efficiency.[E07] The method of producing an electrode for the electronic device according to any one of [E01] to [E06], in whichan oxygen content rate of the first electrode is less than an oxygen content rate of a stoichiometric composition.[E08] The method of producing an electrode for the electronic device according to any one of [E01] to [E07] in which,the work function value of the first electrode is 4.1 eV to 4.5 eV.[E09] The method of producing an electrode for the electronic device according to any one of [E01] to [E07] in which,the first electrode is composed of indium gallium complex oxide, indium-doped gallium zinc complex oxide, aluminum oxide-doped zinc oxide indium zinc complex oxide or gallium-doped zinc oxide.[E10] The method of producing an electrode for the electronic device according to any one of [E01] to [E09] in which,the second electrode is composed of indium tin complex oxide, indium zinc complex oxide or tin oxide.[E11] The method of producing an electrode for the electronic device according to any one of [E01] to [E10] in which,the first electrode has light transmittance of 80% or more at wavelengths of 400 nm to 660 nm.[E12] The method of producing an electrode for the electronic device according to any one of [E01] to [E11] in which,the first electrode has a sheet resistance value of 3×10 Ω/square to 1×103 Ω/square.[E13] The method of producing an electrode for the electronic device according to any one of [E01] to [E12] which is a photoelectric conversion element. It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims. | 51,115 |
11943943 | DETAILED DESCRIPTION The following describes aspects (embodiments) for carrying out the present disclosure in detail with reference to the drawings. The present disclosure is not limited to the description of the embodiments given below. Components to be described below include those easily conceivable by those skilled in the art or those substantially identical thereto. Moreover, the components to be described below can be appropriately combined. What is disclosed herein is merely an example, and the present disclosure naturally encompasses appropriate modifications easily conceivable by those skilled in the art while maintaining the gist of the disclosure. To further clarify the description, the drawings schematically illustrate, for example, widths, thicknesses, and shapes of various parts as compared with actual aspects thereof, in some cases. However, they are merely examples, and interpretation of the present disclosure is not limited thereto. The same element as that illustrated in a drawing that has already been discussed is denoted by the same reference numeral through the description and the drawings, and detailed description thereof will not be repeated in some cases where appropriate. First Embodiment FIG.1is a plan view illustrating a detection device according to a first embodiment of the present disclosure.FIG.2is a block diagram illustrating a configuration example of the detection device according to the first embodiment. As illustrated inFIG.1, a detection device1includes an insulating substrate21, a sensor10, a gate line drive circuit15, a signal line selection circuit16, a detection circuit48, a control circuit102, and a power supply circuit103. As illustrated inFIG.1, a control board101is electrically coupled to the insulating substrate21through a flexible printed circuit board71. The flexible printed circuit board71is provided with the detection circuit48. The control board101is provided with the control circuit102and the power supply circuit103. The control circuit102is, for example, a field programmable gate array (FPGA). The control circuit102supplies control signals to the sensor10, the gate line drive circuit15, and the signal line selection circuit16to control a detection operation of the sensor10. The power supply circuit103supplies voltage signals including, for example, a power supply signal SVS (refer toFIG.4), to the sensor10and the gate line drive circuit15. The insulating substrate21has a detection area AA and a peripheral area GA. The detection area AA is an area overlapping a plurality of detection electrodes35, a counter electrode36, and an organic semiconductor layer31included in the sensor10. The peripheral area GA is an area outside the detection area AA, and is an area not overlapping the detection electrodes35. The gate line drive circuit15and the signal line selection circuit16are provided in the peripheral area GA. The sensor10includes the organic semiconductor layer31, the detection electrodes35, and the counter electrode36. The detection electrodes35are arranged in the detection area AA of the insulating substrate21. The organic semiconductor layer31is continuously provided in the entire detection area AA so as to cover the detection electrodes35. The counter electrode36is provided above the organic semiconductor layer31. The organic semiconductor layer31, each of the detection electrodes35, and the counter electrode36constitute a photoelectric conversion element PD (photodiode) in an area overlapping a corresponding one of the detection electrodes35. In other words, the photoelectric conversion elements PD are provided corresponding to the respective detection electrodes35, and are arranged in the detection area AA. As illustrated inFIG.2, the detection device1further includes a detection controller11and a detector40. The control circuit102includes some or all functions of the detection controller11. The control circuit102also includes some or all functions of the detector40. InFIG.1, the detection circuit48is provided on the flexible printed circuit board71. However, the detection circuit48may be incorporated in the control circuit102. The sensor10is an optical sensor including the photoelectric conversion elements PD. Each of the photoelectric conversion elements PD included in the sensor10outputs an electrical signal corresponding to light emitted thereto as a detection signal Vdet to the signal line selection circuit16. The sensor10performs the detection in response to a gate drive signal VGCL supplied from the gate line drive circuit15. The detection controller11is a circuit that supplies respective control signals to the gate line drive circuit15, the signal line selection circuit16, and the detector40to control operations thereof. The detection controller11supplies various control signals including, for example, a start signal STV, a clock signal CK, and a reset signal RST1to the gate line drive circuit15. The detection controller11also supplies various control signals including, for example, a selection signal SEL to the signal line selection circuit16. The gate line drive circuit15is a circuit that drives a plurality of gate lines GCL (refer toFIG.3) based on the various control signals. The gate line drive circuit15sequentially or simultaneously selects the gate lines GCL, and supplies the gate drive signals VGCL to the selected gate lines GCL. Through this operation, the gate line drive circuit15selects the photoelectric conversion elements PD coupled to the gate lines GCL. The signal line selection circuit16is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (refer toFIG.3). The signal line selection circuit16couples the selected signal lines SGL to the detection circuit48based on the selection signal SEL supplied from the detection controller11. Through this operation, the signal line selection circuit16outputs the detection signal Vdet of each of the photoelectric conversion elements PD to the detector40. The detector40includes the detection circuit48, a signal processor44, a coordinate extractor45, a storage46, and a detection timing controller47. The detection timing controller47controls, based on a control signal supplied from the detection controller11, the detection circuit48, the signal processor44, and the coordinate extractor45so as to operate in synchronization with one another. The detection circuit48is, for example, an analog front-end circuit (AFE). The detection circuit48is a signal processing circuit having functions of at least a detection signal amplifier42and an analog-to-digital (A/D) converter43. The detection signal amplifier42amplifies the detection signal Vdet. The A/D converter43converts an analog signal output from the detection signal amplifier42into a digital signal. The signal processor44is a logic circuit that detects a predetermined physical quantity input to the sensor10based on an output signal of the detection circuit48. When a finger Fg is in contact with or in proximity to a detection surface, the signal processor44can detect asperities of a surface of the finger Fg or a palm based on the signal from the detection circuit48. The signal processor44can also detect biological information based on the signal from the detection circuit48. Examples of the biological information include a blood vessel image of the finger Fg or the palm, a pulse wave, pulsation, and a blood oxygen concentration. The storage46temporarily stores a signal calculated by the signal processor44. The storage46may be, for example, a random-access memory (RAM) or a register circuit. The coordinate extractor45is a logic circuit that obtains detected coordinates of the asperities of the surface of, for example, the finger Fg when the contact or the proximity of the finger Fg is detected by the signal processor44. The coordinate extractor45combines the detection signals Vdet output from the photoelectric conversion elements PD of the sensor10to generate two-dimensional information representing a shape of the asperities of the surface of, for example, the finger Fg and two-dimensional information representing shapes of blood vessels of the finger Fg and the palm. The coordinate extractor45may output the detection signals Vdet as sensor outputs Vo, without calculating the detected coordinates. The following describes a circuit configuration example and an operation example of the detection device1.FIG.3is a circuit diagram illustrating the detection device.FIG.4is a circuit diagram illustrating a partial detection area. As illustrated inFIG.3, the sensor10has a plurality of partial detection areas PAA arranged in a matrix having a row-column configuration. As illustrated inFIG.4, each of the partial detection areas PAA includes the photoelectric conversion element PD, a capacitive element Ca, and a first switching element Tr. The first switching element Tr is provided corresponding to each of the detection electrodes35included in the photoelectric conversion element PD. The first switching element Tr is constituted by a thin-film transistor, and in this example, constituted by an n-channel metal oxide semiconductor (MOS) thin-film transistor (TFT). The gate of the first switching element Tr is coupled to each of the gate lines GCL. The source of the first switching element Tr is coupled to each of the signal lines SGL. The drain of the first switching element Tr is coupled to the anode of the photoelectric conversion element PD and the capacitive element Ca. The cathode of the photoelectric conversion element PD is supplied with the power supply signal SVS from the power supply circuit103. The photoelectric conversion element PD is driven in a reverse bias state. The capacitive element Ca is supplied with a reference signal VR1serving as an initial potential of the capacitive element Ca from the power supply circuit103. When the partial detection area PAA is irradiated with light, a current corresponding to an amount of the light flows through the photoelectric conversion element PD. As a result, an electrical charge is stored in the capacitive element Ca. After the first switching element Tr is turned on, a current corresponding to the electrical charge stored in the capacitive element Ca flows through the signal line SGL. The signal line SGL is coupled to the detection circuit48through the signal line selection circuit16. Thus, the detection device1can detect a signal corresponding to the amount of the light emitted to the photoelectric conversion element PD for each of the partial detection areas PAA. As illustrated inFIG.3, the gate lines GCL extend in a first direction Dx, and are coupled to the partial detection areas PAA arranged in the first direction Dx. A plurality of gate lines GCL1, GCL2, . . . , GCL8are arranged in a second direction Dy, and are each coupled to the gate line drive circuit15. In the following description, the gate lines GCL1, GCL2, . . . , GCL8will each be simply referred to as the gate line GCL when need not be distinguished from one another. Although the number of the gate lines GCL is eight, this is merely an example. Eight or more, such as 256, of the gate lines GCL may be arranged. The first direction Dx is a direction in a plane parallel to the insulating substrate21, and is, for example, a direction parallel to the gate lines GCL. The second direction Dy is a direction in a plane parallel to the insulating substrate21, and is a direction orthogonal to the first direction Dx. The second direction Dy may intersect the first direction Dx without being orthogonal thereto. The signal lines SGL extend in the second direction Dy, and are coupled to the partial detection areas PAA arranged in the second direction Dy. A plurality of signal lines SGL1, SGL2, . . . , SGL12are arranged in the first direction Dx, and are each coupled to the signal line selection circuit16and a reset circuit17. Although the number of the signal lines SGL is 12, this is merely an example. Twelve or more, such as 252, of the signal lines SGL may be arranged. InFIG.3, the sensor10is provided between the signal line selection circuit16and the reset circuit17. The present disclosure is not limited thereto. The signal line selection circuit16and the reset circuit17may be coupled to the same ends of the signal lines SGL. The gate line drive circuit15receives the various control signals such as the start signal STV, the clock signal CK, and the reset signal RST1through a level shifter151. The gate line drive circuit15includes a plurality of second switching elements TrG (refer to FIG.6), and sequentially selects the gate lines GCL1, GCL2, . . . , GCL8in a time-division manner through operations of the second switching elements TrG. The gate line drive circuit15supplies the gate drive signals VGCL to the first switching elements Tr through the selected gate lines GCL. This operation selects the partial detection areas PAA arranged in the first direction Dx as detection targets. The signal line selection circuit16includes a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and third switching elements TrS. The third switching elements TrS are provided corresponding to the respective signal lines SGL. Six of the signal lines SGL1, SGL2, . . . , SGL6are coupled to a common output signal line Lout1. Six of the signal lines SGL7, SGL8, . . . , SGL12are coupled to a common output signal line Lout2. The output signal lines Lout1and Lout2are each coupled to the detection circuit48. The signal lines SGL1, SGL2, . . . , SGL6are grouped into a first signal line block, and the signal lines SGL7, SGL8, . . . , SGL12are grouped into a second signal line block. The selection signal lines Lsel are coupled to the gates of the respective third switching elements TrS included in one of the signal line blocks. One of the selection signal lines Lsel is coupled to the gates of the third switching elements TrS in the signal line blocks. Specifically, selection signal lines Lsel1, Lsel2, . . . , Lsel6are coupled to the third switching elements TrS corresponding to the signal lines SGL1, SGL2, . . . , SGL6. One of the selection signal lines Lsel1is coupled to one of the third switching elements TrS corresponding to the signal line SGL1and one of the third switching elements TrS corresponding to the signal line SGL7. In the same manner, the selection signal line Lsel2is coupled to one of the third switching elements TrS corresponding to the signal line SGL2and one of the third switching elements TrS corresponding to the signal line SGL8. The control circuit102(refer toFIG.1) sequentially supplies the selection signals SEL to the selection signal lines Lsel through level shifters161. This operation causes the signal line selection circuit16to operate the third switching elements TrS to sequentially select the signal lines SGL in one of the signal line blocks in a time-division manner. The signal line selection circuit16simultaneously selects one of the signal lines SGL in each of the signal line blocks. With the above-described configuration, the detection device1can reduce the number of integrated circuits (ICs) including the detection circuit48or the number of terminals of the ICs. As illustrated inFIG.3, the reset circuit17includes a reference signal line Lvr, a reset signal line Lrst, and fourth switching elements TrR. The fourth switching elements TrR are provided corresponding to the signal lines SGL. The reference signal line Lvr is coupled to either the sources or the drains of the fourth switching elements TrR. The reset signal line Lrst is coupled to the gates of the fourth switching elements TrR. The control circuit102supplies a reset signal RST2to the reset signal line Lrst through a level shifter171. This operation turns on the fourth switching elements TrR to electrically couple the signal lines SGL to the reference signal line Lvr. The power supply circuit103supplies the reference signal VR1to the reference signal line Lvr. This operation supplies the reference signal VR1to the capacitive elements Ca included in the partial detection areas PAA. The detection device1includes a reset period, an exposure period, and a reading period. The power supply circuit103supplies the power supply signal SVS to the cathode of the photoelectric conversion element PD through the reset period, the exposure period, and the reading period. During the reset period, the gate line drive circuit15sequentially selects the gate lines GCL, and sequentially supplies the gate drive signals VGCL to the gate lines GCL. Thus, during the reset period, the capacitive elements Ca of all the partial detection areas PAA are sequentially electrically coupled to the signal lines SGL, and are supplied with the reference signal VR1. As a result, capacities of the capacitive elements Ca are reset. During the exposure period, the respective first switching elements Tr are turned off, and the current corresponding to the light irradiating the photoelectric conversion element PD flows in each of the partial detection areas PAA. As a result, the electrical charge is stored in each of the capacitive elements Ca. During the reading period, the gate line drive circuit15sequentially supplies the gate drive signals VGCL to the gate lines GCL. This operation turns on the respective first switching elements Tr. The control circuit102sequentially supplies selection signals SEL1, . . . , SEL6to the signal line selection circuit16. This operation sequentially or simultaneously couples the signal lines SGL of the partial detection areas PAA selected by the gate drive signals VGCL to the detection circuit48. As a result, the detection signals Vdet are supplied to the detection circuit48on a per partial detection area PAA basis. The detection device1may perform the detection by repeatedly performing the processing during the reset period, the exposure period, and the reading period. Alternatively, the detection device1may start the detection operation when having detected that the finger Fg, for example, is in contact with or in proximity to the detection surface. When the partial detection areas PAA have a configuration not including the capacitive elements Ca, the processing during the exposure period and the reading period may be performed during the same period. In this case, the first switching element Tr couples the photoelectric conversion element PD to the signal line SGL during the exposure period. As a result, the current corresponding to the irradiating light flows from the photoelectric conversion element PD to each of the signal lines SGL. The following describes a detailed configuration of the detection device1.FIG.5is a plan view schematically illustrating the partial detection areas of the detection device according to the first embodiment.FIG.6is a VI-VI′ sectional view ofFIG.5. For ease of viewing,FIG.5illustrates the detection electrodes35and third conductive layers67with long dashed double-short dashed lines. To illustrate a relation between a layered structure of the detection area AA and a layered structure of the peripheral area GA,FIG.6illustrates the section taken along line VI-VI′ and a section of a portion of the peripheral area GA including one of the second switching elements TrG in a schematically connected manner.FIG.6also illustrates a section of a portion of the peripheral area GA including a terminal portion72in a schematically connected manner. In the description of the detection device1, in a direction orthogonal to a surface of the insulating substrate21, a direction from the insulating substrate21toward the counter electrode36of the photoelectric conversion element PD will be referred to as the “upper side” or simply as “above”, and a direction from the counter electrode36toward the insulating substrate21will be referred to as the “lower side” or simply as “below”. The term “plan view” refers to an arrangement relation as viewed from the direction orthogonal to the surface of the insulating substrate21. As illustrated inFIG.5, the partial detection area PAA is an area surrounded by the gate lines GCL and the signal lines SGL. In the present embodiment, each of the gate lines GCL includes a first gate line GCLA and a second gate line GCLB. The second gate line GCLB is provided so as to overlap the first gate line GCLA. The first gate line GCLA and the second gate line GCLB are provided in different layers with insulating layers (a third inorganic insulating layer22cand a fourth inorganic insulating layer22d(refer toFIG.6)) interposed therebetween. The first gate line GCLA and the second gate line GCLB are electrically coupled to each other at any place, and are supplied with the gate drive signals VGCL having the same potential. At least one of the first gate line GCLA and the second gate line GCLB is coupled to the gate line drive circuit15. InFIG.5andFIG.6, the first gate line GCLA has a different width from that of the second gate line GCLB. However, the first gate line GCLA may have the same width as that of the second gate line GCLB. Each of the detection electrodes35is provided in the area surrounded by the gate lines GCL and the signal lines SGL. The organic semiconductor layer31and the counter electrode36are continuously provided so as to cover the detection electrodes35, the gate lines GCL, the signal lines SGL, and the first switching elements Tr. Each of the third conductive layers67is provided in an area overlapping a corresponding one of the detection electrodes35, and is provided so as to cover a portion of the first switching element Tr. A metal material such as aluminum (Al), copper (Cu), silver (Ag), or molybdenum (Mo), or an alloy of these materials is used as the third conductive layer67. The third conductive layer67serves as a reflective layer for reflecting externally incident light. The third conductive layer67also serves as a protection layer for protecting the first switching element Tr. The first switching element Tr is provided near an intersecting portion between the gate line GCL and the signal line SGL. The first switching element Tr includes a first semiconductor61, a source electrode62, a drain electrode63, a first gate electrode64A, and a second gate electrode64B. One end of the first semiconductor61is coupled to the source electrode62through a contact hole H1. The other end of the first semiconductor61is coupled to the drain electrode63through a contact hole H2. A portion of the signal line SGL overlapping the first semiconductor61serves as the source electrode62. A portion of the third conductive layer67overlapping the first semiconductor61serves as the drain electrode63. The third conductive layer67is coupled to the detection electrode35through a contact hole H3. The above-described configuration allows the first switching element Tr to switch between coupling and decoupling of the photoelectric conversion element PD to and from the signal line SGL. The first semiconductor61is an oxide semiconductor. The first semiconductor61is more preferably a transparent amorphous oxide semiconductor (TAOS) among types of the oxide semiconductor. Using the oxide semiconductor as the first switching element Tr can reduce a leakage current of the first switching element Tr. As a result, the detection device1can restrain reduction in sensitivity in a case of trying to achieve high resolution of the detection. The first semiconductor61is provided along the first direction Dx, and intersects the first gate electrode64A and the second gate electrode64B. The first gate electrode64A and the second gate electrode64B are provided so as to branch from the first gate line GCLA and the second gate line GCLB, respectively. In other words, portions of the first gate line GCLA and the second gate line GCLB overlapping the first semiconductor61serve as the first gate electrode64A and the second gate electrode64B, respectively. Aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy of these materials is used as the first gate electrode64A and the second gate electrode64B. A channel area is formed at a portion of the first semiconductor61overlapping the first gate electrode64A and the second gate electrode64B. The following describes a layer configuration of the detection device1. As illustrated inFIG.6, an array substrate2includes, the insulating substrate21, the first switching element Tr, the second switching element TrG, a first conductive layer65, a second conductive layer66, the third conductive layer67, a fourth conductive layer68, a first inorganic insulating layer22ato a fifth inorganic insulating layer22e, an organic insulating layer23a, various types of wiring, and the like. The first switching element Tr is provided above the insulating substrate21. The insulating substrate21is, for example, a glass substrate. Alternatively, the insulating substrate21may be a resin substrate or a resin film formed of a resin such as polyimide. When the resin film is used as the insulating substrate21, the array substrate2can be formed to have a curved surface, and thus, the detection device1is configured as a sensor having a curved surface corresponding to the shape of the finger Fg or the palm. In the detection device1, the first switching element Tr including the oxide semiconductor is formed above the insulating substrate21. As a result, the detection device1can easily have an area of the detection area AA larger than that in a case of using a semiconductor substrate such as a silicon substrate. The first gate electrode64A is provided above the insulating substrate21with a first inorganic insulating layer22aand a second inorganic insulating layer22binterposed therebetween. For example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon oxynitride (SiON) film is used as each of the first inorganic insulating layers22ato the fifth inorganic insulating layers22e. Each of the inorganic insulating layers is not limited to a single layer, but may be a laminated film. The third inorganic insulating layer22cis provided above the second inorganic insulating layer22bso as to cover the first gate electrode64A. The first semiconductor61, a first conductive layer65, and a second conductive layer66are provided above the third inorganic insulating layer22c. The first conductive layer65is provided so as to cover an end of the first semiconductor61coupled to the source electrode62. The second conductive layer66is provided so as to cover an end of the first semiconductor61coupled to the drain electrode63. The fourth inorganic insulating layer22dis provided above the third inorganic insulating layer22cso as to cover the first semiconductor61, the first conductive layer65, and the second conductive layer66. The second gate electrode64B is provided above the fourth inorganic insulating layer22d. The first semiconductor61is provided between the first gate electrode64A and the second gate electrode64B in a direction orthogonal to the insulating substrate21. That is, the first switching element Tr has what is called a dual-gate structure. However, the first switching element Tr may have a bottom-gate structure in which the first gate electrode64A is provided while the second gate electrode64B is not provided, or a top-gate structure in which only the second gate electrode64B is provided without the first gate electrode64A being provided. The fifth inorganic insulating layer22eis provided above the fourth inorganic insulating layer22dso as to cover the second gate electrode64B. The source electrode62(signal line SGL) and the drain electrode63(third conductive layer67) are provided above the fifth inorganic insulating layer22e. In the present embodiment, the drain electrode63is the third conductive layer67provided above the first semiconductor61with the fourth inorganic insulating layer22dand the fifth inorganic insulating layer22einterposed therebetween. The fourth inorganic insulating layer22dand the fifth inorganic insulating layer22eare provided with the contact hole H1and the contact hole H2. The first conductive layer65is exposed at the bottom of the contact hole H1. The source electrode62is electrically coupled to the first semiconductor61through the contact hole H1and the first conductive layer65. In the same manner, the second conductive layer66is exposed at the bottom of the contact hole H2. The drain electrode63is electrically coupled to the first semiconductor61through the contact hole H2and the second conductive layer66. The first conductive layer65is provided at a portion overlapping at least the bottom of the contact hole H1between the source electrode62and the first semiconductor61, and contacts the first semiconductor61. The second conductive layer66is provided at a portion overlapping at least the bottom of the contact hole H2between the drain electrode63and the first semiconductor61, and contacts the first semiconductor61. Since the detection device1is provided with the first conductive layer65and the second conductive layer66, the first semiconductor61can be restrained from being removed by an etching solution when the contact holes H1and H2are formed by etching. That is, in the detection device1, the first switching elements Tr in the detection area AA and the second switching elements TrG in the peripheral area GA can be formed in the same process, so that the manufacturing cost can be reduced. A metal material such as aluminum (Al), copper (Cu), silver (Ag), or molybdenum (Mo), or an alloy of these materials is used as the first conductive layer65and the second conductive layer66same as the third conductive layer67. The first conductive layer65and the second conductive layer66only need to be made of a conductive material that restrains the etching from progressing when the contact holes H1and H2are formed. The third conductive layer67is provided in an area overlapping the photoelectric conversion element PD in the plan view. The third conductive layer67is also provided above the first semiconductor61, the first gate electrode64A, and the second gate electrode64B. That is, the third conductive layer67is provided between the first switching element Tr and the photoelectric conversion element PD in the direction orthogonal to the insulating substrate21. This configuration causes the third conductive layer67to have a function as a protection layer for protecting the first switching element Tr when the photoelectric conversion element PD is formed on the array substrate2. The second conductive layer66extends so as to face the third conductive layer67in an area not overlapping the first semiconductor61. A fourth conductive layer68is provided above the fourth inorganic insulating layer22din an area not overlapping the first semiconductor61. The fourth conductive layer68is provided between the second conductive layer66and the third conductive layer67. This configuration forms a capacity between the second conductive layer66and the fourth conductive layer68, and a capacity between the third conductive layer67and the fourth conductive layer68. The capacities formed by the second conductive layer66, the third conductive layer67, and the fourth conductive layer68serve as a capacity of the capacitive element Ca illustrated inFIG.4. The organic insulating layer23ais provided above the fifth inorganic insulating layer22eso as to cover the source electrode62(signal line SGL) and the drain electrode63(third conductive layer67). The organic insulating layer23ais a planarization layer that planarizes asperities formed by the first switching elements Tr and various types of conductive layers. The photoelectric conversion element PD includes the organic semiconductor layer31, the detection electrode35, and the counter electrode36. The photoelectric conversion element PD is provided above the organic insulating layer23aof the array substrate2, and is stacked in the order of the detection electrode35, the organic semiconductor layer31, and the counter electrode36in the direction orthogonal to the insulating substrate21. The detection electrode35is the anode of the photoelectric conversion element PD, and is an electrode for reading the detection signal Vdet. The detection electrode35is electrically coupled to the third conductive layer67through the contact hole H3provided in the organic insulating layer23a. For example, a metal material such as molybdenum (Mo) or aluminum (Al) is used as the detection electrode35. Alternatively, the detection electrode35may be a laminated film having a plurality of stacked layers of these metal materials. The detection electrode35may be of a light-transmitting conductive material such as indium tin oxide (ITO). The organic semiconductor layer31is continuously provided over the detection electrodes35. For example, a low-molecular organic material such as C60 (fullerene), phenyl-C61-butyric acid methyl ester (PCBM), copper phthalocyanine (CuPc), fluorinated phthalocyanine (F16CuPc), rubrene (5,6,11,12-tetraphenyltetracene), or PDI (derivative of perylene) can be used as a material of the organic semiconductor layer31. A material obtained by combining any of the above-listed low-molecular organic materials with a polymeric organic material is used as the organic semiconductor layer31. For example, poly(3-hexylthiophene) (P3HT) or F8-alt-benzothiadiazole (F8BT) can be used as the polymeric organic material. The organic semiconductor layer31can be a film in a state of a mixture (having a sea-island structure) of P3HT and PCBM, or a film in a state of a mixture of F8BT and PDI. A detailed configuration of the organic semiconductor layer31will be described later. The counter electrode36is provided above the organic semiconductor layer31. That is, the single counter electrode36faces the detection electrodes35. The counter electrode36is the cathode of the photoelectric conversion element PD, and is an electrode for applying a common potential to the photoelectric conversion elements PD by being supplied with the power supply signal SVS. The counter electrode36is a light-transmitting conductive layer of, for example, ITO. Light L2reflected by the finger Fg or the palm (refer toFIG.10) passes through the counter electrode36, and enters the organic semiconductor layer31. In the present embodiment, the detection electrode35serves as the anode and the counter electrode36serves as the cathode. However, the configuration may be reversed. That is, the detection electrode35may serve as the cathode, and the counter electrode36may serve as the anode. The peripheral area GA is provided with the second switching elements TrG included in the gate line drive circuit15. Each of the second switching elements TrG is provided on the same insulating substrate21as that of the first switching element Tr. The second switching element TrG includes a second semiconductor81, a source electrode82, a drain electrode83, and a gate electrode84. The second semiconductor81is of polysilicon. The second semiconductor81is more preferably of low-temperature polysilicon (hereinafter, referred to as low-temperature polycrystalline silicon (LTPS)). The second switching element TrG using LIPS can be produced at a process temperature of 600 degrees Celsius or lower. Therefore, circuits such as the gate line drive circuit15and the signal line selection circuit16can be formed on the same substrate as that for the first switching element Tr. Polysilicon has higher carrier mobility than that of a-Si. Therefore, the detection device1can reduce the size of the gate line drive circuit15as compared with a case of using a-Si as the second switching element TrG. As a result, the detection device1can reduce the area of the peripheral area GA. The second switching element TrG using polysilicon has higher reliability than that obtained using a-Si. The second semiconductor81is provided above the first inorganic insulating layer22a. That is, the first semiconductor61of the first switching element Tr is provided in a position farther away from the insulating substrate21than the second semiconductor81of the second switching element TrG in the direction orthogonal to the insulating substrate21. This configuration allows the second semiconductor81formed of polysilicon and the first semiconductor61formed of the oxide semiconductor to be formed on the same insulating substrate21. The gate electrode84is provided above the second semiconductor81with the second inorganic insulating layer22binterposed therebetween. The gate electrode84is provided in the same layer as that of the second gate electrode64B. The second switching element TrG has what is called the top-gate structure. However, the second switching element TrG may have the dual-gate structure or the bottom-gate structure. The source electrode82and the drain electrode83are provided above the fifth inorganic insulating layer22e. The source electrode82and the drain electrode83are provided in the same layer as that of the source electrode62and the drain electrode63of the first switching element Tr. Contact holes H4and H5are provided through from the second inorganic insulating layer22bto the fifth inorganic insulating layer22e. The source electrode82is electrically coupled to the second semiconductor81through the contact hole H4. The drain electrode83is electrically coupled to the second semiconductor81through the contact hole H5. The contact holes H1and H2and the contact holes H4and H5of the detection device1can be formed in the same process because the first switching element Tr is provided with the first conductive layer65and the second conductive layer66. Each of the third switching elements TrS included in the signal line selection circuit16and each of the fourth switching elements TrR included in the reset circuit17illustrated inFIG.3may have the same configuration as that of the second switching element TrG. That is, the semiconductor of each of the third switching elements TrS and the fourth switching elements TrR is of polysilicon, and is more preferably of LTPS. In this case, the detection device1can reduce the circuit scale of the signal line selection circuit16and the reset circuit17. The semiconductor of each of the third switching elements TrS and the fourth switching elements TrR is not limited to such materials, but may be an oxide semiconductor, including a TAOS. The terminal portion72is provided in a position of the peripheral area GA different from the area provided with the gate line drive circuit15. The terminal portion72includes a first terminal conductive layer73, a second terminal conductive layer74, and a third terminal conductive layer75. The first terminal conductive layer73is provided in the same layer as that of the second gate electrode64B and on the second inorganic insulating layer22b. A contact hole H6is provided so as to extend through the third inorganic insulating layer22cto the fifth inorganic insulating layer22e, and the organic insulating layer23a. The second terminal conductive layer74and the third terminal conductive layer75are stacked in this order in the contact hole H6, and are electrically coupled to the first terminal conductive layer73. The second terminal conductive layer74can be formed using the same material as and in the same process as those of the third conductive layer67and the like. The third terminal conductive layer75can be formed using the same material as and in the same process as those of the detection electrode35. The counter electrode36extends to the peripheral area GA, and is electrically coupled to the terminal portion72. AlthoughFIG.6illustrates one terminal portion72, a plurality of such terminal portions72may be arranged with gaps interposed therebetween. The terminal portions72may be provided as coupling terminals to the flexible printed circuit board71(refer toFIG.1) or coupling terminals to a drive IC. The detection device1may be provided with a protection layer or a cover glass above the counter electrode36as needed. The following describes a configuration of the organic semiconductor layer31.FIG.7is a VII-VII′ sectional view ofFIG.5.FIG.7is a sectional view obtained by cutting the partial detection areas PAA illustrated inFIG.5along the first direction Dx. The same sectional view asFIG.7can also be obtained by cutting the partial detection areas PAA along the second direction Dy. WhileFIG.7illustrates the array substrate2in a simplified manner, the detection electrodes35are provided on the organic insulating layer23aof the array substrate2(refer toFIG.6). The detection electrodes35are disposed so as to be separated from one another. Herein, an overlapping area R1denotes an area overlapping each of the detection electrodes35. A non-overlapping area R2denotes an area not overlapping each of the detection electrodes35, that is, an area between the adjacent detection electrodes35. The photoelectric conversion element PD is constituted by the detection electrode35, the organic semiconductor layer31, and the counter electrode36stacked in each of the overlapping areas R1. The organic semiconductor layer31and the counter electrode36are provided over the overlapping areas R1and the non-overlapping areas R2so as to cover the detection electrodes35. The organic semiconductor layer31includes a p-type semiconductor layer32and an active layer34that is formed by mixing a p-type semiconductor34awith an n-type semiconductor34b. The organic semiconductor layer31has different configurations in the overlapping area R1and the non-overlapping area R2. Specifically, in the overlapping area R1, the organic semiconductor layer31includes a buffer layer37(first buffer layer), the p-type semiconductor layer32(second p-type semiconductor layer), the active layer34, and a buffer layer38(second buffer layer). The active layer34is provided between the p-type semiconductor layer32and the buffer layer37in the direction orthogonal to the insulating substrate21. The p-type semiconductor layer32(second p-type semiconductor layer32b) and the buffer layer38are provided between the active layer34and the counter electrode36. The p-type semiconductor layer32(second p-type semiconductor layer32b) and the buffer layer38are disposed over the overlapping areas R1and the non-overlapping areas R2. A plurality of the buffer layers37are provided. The buffer layers37are provided between the active layers34and the detection electrodes35, and are provided so as to be separated from one another on a per detection electrode35basis. In the present embodiment, the detection electrodes35, the buffer layers37, the active layer34, the p-type semiconductor layer32, the buffer layer38, and the counter electrode36are stacked in this order in the direction orthogonal to the insulating substrate21. The active layer34has a bulk hetero structure in which the p-type semiconductor34aand the n-type semiconductor34bare mixed and coexist. The active layer34has a configuration in which the p-type semiconductor34aand the n-type semiconductor34bare distributed at a desired ratio (for example, at a ratio of 1:2), and the density distribution is graded in the vertical direction such that the ratio between the p-type semiconductor34aand the n-type semiconductor34bis such that p-type semiconductor34a>n-type semiconductor34band n-type semiconductor34b>p-type semiconductor34anear the detection electrode35and the counter electrode36. When the active layer34is irradiated with light, electron-hole pairs are generated in each of the p-type semiconductor34aand the n-type semiconductor34b. Each of the holes and the electrons generated in the active layer34moves in the active layer34, and moves toward the detection electrode35(anode) or the counter electrode36(cathode). The buffer layers37and38are provided for facilitating the holes and the electrons generated in the active layer34to reach the detection electrode35or the counter electrode36. The buffer layer37serves as an electron transport layer (or a hole blocking layer), and the buffer layer38serves as a hole transport layer (electron blocking layer). For example, ZnO or polyethylenimine can be used as a material of the buffer layer37. For example, WO3, MoO3, or polyethylenedioxythiophene (PEDOT)/polystyrene sulfonic acid (PSS) can be used as a material of the buffer layer38. The p-type semiconductor layer32is in contact with the p-type semiconductor34aand the n-type semiconductor34bincluded in the active layer34. For example, P3HT among the above-listed organic materials is used as the p-type semiconductor layer32and the p-type semiconductor34aof the active layer34. For example, PCBM among the above-listed organic materials is used as an n-type semiconductor layer33(refer toFIG.8) and the n-type semiconductor34bof the active layer34. In the overlapping area R1, the ratio of the p-type semiconductor (including the p-type semiconductor layer32and the p-type semiconductor34aof the active layer34) to the n-type semiconductor (including the n-type semiconductor34bof the active layer34) in the organic semiconductor layer31varies in the direction orthogonal to the insulating substrate21. When the ratio per unit volume of the p-type semiconductor to the n-type semiconductor is denoted as a ratio RT (=volume of p-type semiconductor/volume of n-type semiconductor), the ratio RT decreases in the order of the p-type semiconductor layer32and the active layer34in the direction orthogonal to the insulating substrate21. In the non-overlapping area R2, the organic semiconductor layer31is configured by including at least either of the p-type semiconductor layer32constituted by the p-type semiconductor and the n-type semiconductor layer33constituted by the n-type semiconductor. In the present embodiment, in the non-overlapping area R2, a first p-type semiconductor layer32a, the second p-type semiconductor layer32b, the buffer layer38, and the counter electrode36are stacked in this order in the direction orthogonal to the insulating substrate21. That is, in the non-overlapping area R2, the active layer34having the bulk hetero structure is not provided, and the first p-type semiconductor layer32aand the second p-type semiconductor layer32bare stacked so as to contact each other in the direction orthogonal to the insulating substrate21. The first p-type semiconductor layer32aof the non-overlapping area R2is provided above the organic insulating layer23aof the array substrate2(refer toFIG.6). The first p-type semiconductor layer32ais continuously provided over a gap between the adjacent detection electrodes35. The first p-type semiconductor layer32ais continuously provided over a gap between the adjacent active layers34. The second p-type semiconductor layer32bin the non-overlapping area R2is provided so as to be continuous to the p-type semiconductor layer32provided in the overlapping area R1. The p-type semiconductor layer32is continuously provided over the overlapping areas R1and the non-overlapping areas R2, and is provided above the active layer34and the first p-type semiconductor layer32a. As described above, in the organic semiconductor layer31, the active layer34is provided in each of the overlapping areas R1. In the non-overlapping area R2, the first p-type semiconductor layer32ais continuously provided between the active layers34and between the detection electrodes35. This configuration can more effectively restrain the holes or the electrons generated in the active layers34from moving between the detection electrodes35than in a case where the active layer34is continuously provided over the overlapping areas R1and the non-overlapping areas R2. For example, even when one of the detection electrodes35and the other of the detection electrodes35adjacent to each other are set to different potentials by being irradiated with light, the holes or the electrons generated in the active layers34can be restrained from moving from one of the detection electrodes35to the other of the detection electrodes35. Accordingly, the detection device1can reduce the leakage current between the detection electrodes35. As a result, the detection device1can achieve high resolution of the detection. The configuration of the organic semiconductor layer31, the detection electrode35, and the counter electrode36illustrated inFIG.5toFIG.7is merely an example, and can be modified as appropriate. For example, the shape in the plan view of the detection electrode35is not limited to the rectangle, and may be another shape such as a polygon or an irregular shape. FIG.8is an explanatory diagram for explaining an exemplary method for manufacturing the detection device according to the first embodiment. As illustrated inFIG.8, a film forming device forms the n-type semiconductor layer33above the array substrate2so as to cover the detection electrodes35and the buffer layers37(Step ST11). The n-type semiconductor layer33is formed using an application method, such as a spin coating method, a screen printing method, or an ink-jet printing method. Then, the film forming device forms a resist layer201above the n-type semiconductor layer33(Step ST12). The resist layer201is formed in the overlapping areas R1, and is not formed in the non-overlapping areas R2. That is, in the non-overlapping areas R2, the n-type semiconductor layer33is formed so as to be exposed from the resist layer201. The resist layer201is formed using an application method or a photolithography method. Then, the film forming device performs dry etching to remove the resist layer201and the n-type semiconductor layer33in the non-overlapping areas R2(Step ST13). Reactive ion etching (hereinafter, referred to as “RIE”) can be employed as the dry etching. The RIE uses an oxygen gas containing oxygen (O2) molecules210. The film forming device further performs the RIE to remove the resist layer201and remove the n-type semiconductor layer33exposed in the overlapping areas R1(Step ST14). Since the polymeric organic material is used, the RIE removes portions of the n-type semiconductor layer33in the overlapping areas R1, but does not remove the other portions thereof. Thus, a porous structure33phaving many fine pores is formed. Since the resist layer201is present, the etching in the non-overlapping areas R2progresses more than in the overlapping areas R1. As a result, the n-type semiconductor layer33is removed to expose a surface of the array substrate2in the non-overlapping areas R2, and the porous structure33pis formed in the n-type semiconductor layer33in the overlapping areas R1(Step ST15). The film forming device forms the p-type semiconductor layer32over the overlapping areas R1and the non-overlapping areas R2(Step ST16). The p-type semiconductor layer32is formed to fill the pores of the porous structure33p, and thus, the active layers34in which the p-type semiconductor34aand the n-type semiconductor34bare mixed and coexist are formed in the overlapping areas R1. In the non-overlapping areas R2, the p-type semiconductor layer32is formed as a single layer above the array substrate2. The film forming device forms the counter electrode36and the buffer layer38above the p-type semiconductor layer32(Step ST17). The counter electrode36and the buffer layer38are continuously formed over the overlapping areas R1and the non-overlapping areas R2. The counter electrode36and the buffer layer38are formed using a thin film method such as sputtering or vapor deposition. The above-described process can form the organic semiconductor layer31having the different configurations in the overlapping areas R1and the non-overlapping areas R2. Specifically, the active layer34is separately patterned in each of the overlapping areas R1, and in the non-overlapping area R2, the p-type semiconductor layer32(first p-type semiconductor layer32a) is provided between the active layers34and between the detection electrodes35. The process illustrated inFIG.8is merely an example. The method for manufacturing the detection device1can be modified as appropriate. For example, a metal mask may be used instead of the resist layer201. Second Embodiment FIG.9is a sectional view illustrating a schematic sectional configuration of a detection device according to a second embodiment of the present disclosure. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and the description thereof will not be repeated. As illustrated inFIG.9, a detection device1A of the second embodiment is provided with the n-type semiconductor layer33instead of the p-type semiconductor layer32, as compared with the first embodiment. Specifically, in the non-overlapping area R2, the n-type semiconductor layer33is provided as a single layer, and is continuously provided from the surface of the array substrate2between the adjacent detection electrodes35to the counter electrode36. In the non-overlapping area R2, a first n-type semiconductor layer33a, a second n-type semiconductor layer33b, the buffer layer38, and the counter electrode36are stacked in this order above the array substrate2, and the p-type semiconductor layer32is not provided. Similar to the first embodiment, the layered structure of the overlapping area R1is stacked in the order of the detection electrodes35, the buffer layers37, the active layer34, the n-type semiconductor layer33, the buffer layer38, and the counter electrode36in the direction orthogonal to the insulating substrate21. That is, the n-type semiconductor layer33(second n-type semiconductor layer) and the buffer layer38are included between the active layer34and the counter electrode36, and the n-type semiconductor layer33and the buffer layer38are disposed over the overlapping areas R1and the non-overlapping areas R2. In the non-overlapping area R2, the first n-type semiconductor layer33aand the second n-type semiconductor layer33bare stacked so as to contact each other in the direction orthogonal to the insulating substrate21. The second n-type semiconductor layer33bin the non-overlapping area R2is provided so as to be continuous to the n-type semiconductor layer33in the overlapping area R1. The first n-type semiconductor layer33ain the non-overlapping area R2is provided between the adjacent detection electrodes35, and is also provided between the adjacent active layers34. Also in the second embodiment, the active layer34is provided in each of the overlapping areas R1. In the non-overlapping area R2, the first n-type semiconductor layer33ais continuously provided between the active layers34and between the detection electrodes35. With this configuration, the detection device1A can reduce the leakage current between the detection electrodes35. Third Embodiment FIG.10is a sectional view illustrating a schematic sectional configuration of a display device according to a third embodiment of the present disclosure. As illustrated inFIG.10, a display device120includes the detection device1, a display panel121, a touchscreen panel122, and a cover glass123. The display panel121may be, for example, an organic electroluminescent (EL) (organic light-emitting diode (OLED)) display panel or an inorganic EL (micro-LED or mini-LED) display using light-emitting elements as the display elements. Alternatively, a display panel121may be a liquid crystal display (LCD) panel that uses liquid crystal elements as the display elements, or an electrophoretic display (EPD) panel that uses electrophoretic elements as the display elements. The display panel121has a first principal surface121aand a second principal surface121bthat is the opposite side of the first principal surface121a. The first principal surface121ais a surface that emits light L1from display elements toward the cover glass123to display an image. The first principal surface121ahas a display area DA in which the image is displayed. The touchscreen panel122uses, for example, a capacitance method to detect the finger Fg in contact with or in proximity to a surface of the cover glass123. The touchscreen panel122is transmissive of light, and can transmit the light L1and light L2that has been reflected on an interface between the cover glass123and air. The display device120may have a configuration not including the touchscreen panel122. The display panel121may be integrated with the touchscreen panel122, or may incorporate functions of the touchscreen panel122. The cover glass123is a member for protecting, for example, the display panel121, and covers, for example, the display panel121. The cover glass123is, for example, a glass substrate. The present disclosure is not limited to using the cover glass123. For example, a resin substrate may be provided above the touchscreen panel122. The detection device1is provided so as to face the second principal surface121bof the display panel121. The detection device1can detect the asperities of the surface of the finger Fg by detecting the light L2reflected by the finger Fg. Alternatively, the detection device1can detect the biological information such as a vain pattern, the pulse wave, and the pulsation by detecting the light L2reflected in the finger Fg. Since the detection device1can be easily increased in area, the detection area AA of the detection device1is provided so as to face the entire display area DA of the display panel121. The detection area AA is not limited to this configuration, and may face a portion of the display area DA of the display panel121. The detection device1is not limited to the configuration of being provided as the display device120, and may be configured as a biometric authentication device including the detection device1and a light source. In this case, the detection device1is not limited to the configuration of detecting the light L2reflected by, for example, the finger Fg, and can employ a configuration of detecting the light L2having passed through, for example, the finger Fg. Fourth Embodiment FIG.11is a sectional view schematically illustrating the buffer layer of a detection device according to a fourth embodiment of the present disclosure. As illustrated inFIG.11, in a detection device1B of the fourth embodiment, the buffer layer37(first buffer layer) includes zinc oxide (ZnO) nanoparticles37aand a zinc acetate layer37b. The zinc oxide nanoparticles37aare dispersed between the active layer34and the detection electrode35. The zinc acetate layer37bis provided in a space among the zinc oxide nanoparticles37abetween the active layer34and the detection electrode35. The zinc acetate layer37bis provided so as to fill the space among the zinc oxide nanoparticles37a, and contacts the active layer34and the detection electrode35. The buffer layer37can be formed by using and applying ink obtained by mixing the zinc oxide nanoparticles37awith the zinc acetate layer37b. The zinc oxide nanoparticles37aare provided for facilitating the electrons generated in the active layer34to reach the detection electrode35, and serve as an electron transport layer. At the same time, the zinc acetate layer37bserves as a hole blocking layer for restricting the movement of the holes. With this configuration, the buffer layer37can reduce the movement of the holes passing through the space among the zinc oxide nanoparticles37a, for example, as compared with a case where the buffer layer37is formed as a single film of the zinc oxide nanoparticles37awithout including the zinc acetate layer37b. As a result, a dark current can be reduced when the photoelectric conversion element PD is driven in the reverse bias state. The level of the dark current can be controlled by the concentration of the zinc acetate layer37b, that is, the ratio between the zinc oxide nanoparticles37aand the zinc acetate layer37b. For example, the dark current varies with the zinc acetate concentration of a zinc acetate mixed solution used in the buffer layer37. The concentration of the zinc acetate layer37bis more preferably from 0.3 mol/L to 0.4 mol/L. In the present embodiment, the dark current can be reduced to approximately one hundredth to one tenth that in the case where the buffer layer37is formed as a single film of the zinc oxide nanoparticles37a. While the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. The content disclosed in the embodiments is merely an example, and can be variously modified within the scope not departing from the gist of the present disclosure. Modifications appropriately made within the scope not departing from the gist of the present disclosure naturally belong to the technical scope of the present disclosure. | 60,889 |
11943944 | BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments. Embodiment 1 In an organic EL device, in order to facilitate carrier injection from an anode, a hole-injection layer is often provided in contact with the anode. The hole-injection layer contains a material having a high capability to accept electrons from an organic compound (an acceptor material). Although the acceptor material can be either an organic compound or an inorganic compound, an organic compound is widely used as the acceptor material because it is easy to evaporate and handle. On the other hand, it is known that the acceptor property of an organic compound used as the acceptor material is not as high as that of an inorganic compound. For this reason, as a material that is used for the hole-injection layer in combination with the acceptor material and a material used for the hole-transport layer that is stacked to be adjacent to the hole-injection layer, a hole-transport material with a shallow HOMO level is selected in order to facilitate the extraction of electrons. Therefore, a hole-transport material with a shallow HOMO level tends to be used also in the adjacent hole-transport layer, in relation to a driving voltage and the like. Here, in a blue fluorescent light-emitting device, a host material with a deep HOMO level is usually used in order to efficiently excite an emission center substance that exhibits blue fluorescence. Accordingly, in the light-emitting device in which an organic compound is used as the acceptor material, there is a big difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer or an electron-blocking layer that is in contact with a light-emitting layer. The present inventors have found that this difference largely affects the driving lifetime at high temperature. FIG.21Bshows a change in luminance over driving time, at room temperature, of a light-emitting device in which a difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer (or an electron-blocking layer) that is in contact with the light-emitting layer is greater than 0.24 eV (a comparative light-emitting device1) and a light-emitting device in which the difference is less than or equal to 0.24 eV (a light-emitting device1).FIG.21Ashows a change in luminance over driving time, at 85° C., of a light-emitting devices having the same device structures as the above light-emitting devices. Note that in these graphs, luminance is normalized with the initial luminance. Example 1 is referred to for the details of the device structure. InFIG.21Bshowing the results of driving at room temperature, the lifetime of the comparative light-emitting device1is longer than that of the light-emitting device1, whereas inFIG.21Ashowing the results of driving at high temperature, the lifetime of the comparative light-emitting device1is much shorter than that of the light-emitting device1. Furthermore, the degradation curve of the light-emitting device1almost follows the single exponential function both at room temperature and at high temperature, whereas the degradation curve of the comparative light-emitting device1deviates from the single exponential function at high temperature. This indicates a possibility that the comparative light-emitting device1degrades in a different mechanism in high-temperature driving. FIGS.1A1and1A2illustrate a light-emitting device of one embodiment of the present invention. The light-emitting device of one embodiment of the present invention includes an anode101, a cathode102, and an EL layer103. The EL layer includes a hole-injection layer111, a hole-transport layer112, and a light-emitting layer113. Although FIGS.1A1and1A2additionally illustrate an electron-transport layer114and an electron-injection layer115in the EL layer103, the structure of the light-emitting device is not limited thereto. As long as the above-described components are included, a layer having another function may be included. The hole-injection layer111includes a first organic compound and a second organic compound. The first organic compound exhibits an electron-accepting property with respect to the second organic compound. As the first organic compound, organic compounds having an electron-withdrawing group (in particular, a cyano group or a halogen group such as a fluoro group) can be used, for example. A substance that exhibits an electron-accepting property with respect to the second organic compound is selected from such organic compounds as appropriate. Examples of such an organic compound include 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviation: F4-TCNQ), chloranil, 2,3,6,7,10,11-hexacyano-1,4,5,8,9,12-hexaazatriphenylene (abbreviation: HAT-CN), 1,3,4,5,7,8-hexafluorotetracyano-naphthoquinodimethane (abbreviation: F6-TCNNQ), and 2-(7-dicyanomethylene-1,3,4,5,6,8,9,10-octafluoro-7H-pyrene-2-ylidene)malononitrile. A compound in which electron-withdrawing groups are bonded to a condensed aromatic ring having a plurality of heteroatoms, such as HAT-CN, is preferred because it is thermally stable. A [3]radialene derivative having an electron-withdrawing group (in particular, a cyano group or a halogen group such as a fluoro group) has a very high electron-accepting property and thus is preferred. Specific examples include α,α′,α″-1,2,3-cyclopropanetriylidenetris[4-cyano-2,3,5,6-tetrafluorobenzeneacetonitrile], α,α′,α″-1,2,3-cyclopropanetriylidenetris[2,6-dichloro-3,5-difluoro-4-(trifluoromethyl)benzeneacetonitrile], and α,α′,α″-1,2,3-cyclopropanetriylidenetris[2,3,4,5,6-pentafluorobenzeneacetonitrile]. The second organic compound is preferably an organic compound having a hole-transport property and any of a carbazole skeleton, a dibenzofuran skeleton, a dibenzothiophene skeleton, and an anthracene skeleton. In particular, an aromatic amine having a substituent that includes a dibenzofuran ring or a dibenzothiophene ring, an aromatic monoamine that includes a naphthalene ring, or an aromatic monoamine in which a 9-fluorenyl group is bonded to nitrogen of amine through an arylene group may be used. Note that the second organic compound having an N,N-bis(4-biphenyl)amino group is preferred because a light-emitting device having a long lifetime can be fabricated. Specific examples of the second organic compound include N-(4-biphenyl)-6,N-diphenylbenzo[b]naphtho[1,2-d]furan-8-amine (abbreviation: BnfABP), N,N-bis(4-biphenyl)-6-phenylbenzo[b]naphtho[1,2-d]furan-8-amine (abbreviation: BBABnf), 4,4′-bis(6-phenylbenzo[b]naphtho[1,2-d]furan-8-yl)-4″-phenyltriphenylamine (abbreviation: BnfBB1BP), N,N-bis(4-biphenyl)benzo[b]naphtho[1,2-d]furan-6-amine (abbreviation: BBABnf(6)), NN-bis(4-biphenyl)benzo[b]naphtho[1,2-d]furan-8-amine (abbreviation: BBABnf(8)), NN-bis(4-biphenyl)benzo[b]naphtho[2,3-d]furan-4-amine (abbreviation: BBABnf(II)(4)), N,N-bis[4-(dibenzofuran-4-yl)phenyl]-4-amino-p-terphenyl (abbreviation: DBfBB1TP), N-[4-(dibenzothiophen-4-yl)phenyl]-N-phenyl-4-biphenylamine (abbreviation: ThBA1BP), 4-(2-naphthyl)-4′,4″-diphenyltriphenylamine (abbreviation: BBAβNB), 4-[4-(2-naphthyl)phenyl]-4′,4″-diphenyltriphenylamine (abbreviation: BBAβNBi), 4-(2;1′-binaphthyl-6-yl)-4′,4″-diphenyltriphenylamine (abbreviation: BBAαNβNB), 4,4′-diphenyl-4″-(7;1′-binaphthyl-2-yl)triphenylamine (abbreviation: BBAαNβNB-03), 4,4′-diphenyl-4″-(7-phenyl)naphthyl-2-yltriphenylamine (abbreviation: BBAPβNB-03), 4-(6;2′-binaphthyl-2-yl)-4′,4″-diphenyltriphenylamine (abbreviation: BBA(βN2)B), 4-(2;2′-binaphthyl-7-yl)-4′,4″-diphenyltriphenylamine (abbreviation: BBA(βN2)B-03), 4-(1;2′-binaphthyl-4-yl)-4′,4″-diphenyltriphenylamine (abbreviation: BBAβNαNB), 4-(1;2′-binaphthyl-5-yl)-4′,4″-diphenyltriphenylamine (abbreviation: BBAβNαNB-02), 4-(4-biphenylyl)-4′-(2-naphthyl)-4″-phenyltriphenylamine (abbreviation: TPBiAβNB), 4-(3-biphenylyl)-4′-[4-(2-naphthyl)phenyl]-4″-phenyltriphenylamine (abbreviation: mTPBiAβNBi), 4-(4-biphenylyl)-4′-[4-(2-naphthyl)phenyl]-4″-phenyltriphenylamine (abbreviation: TPBiAβNBi), 4-(1-naphthyl)-4′-phenyltriphenylamine (abbreviation: αNBA1BP), 4,4′-bis(1-naphthyl)triphenylamine (abbreviation: αNBB1BP), 4,4′-diphenyl-4″-[4′-(carbazol-9-yl)biphenyl-4-yl]triphenylamine (abbreviation: YGTBi1BP), 4′-[4-(3-phenyl-9H-carbazol-9-yl)phenyl]tris(1,1′-biphenyl-4-yl)amine (abbreviation: YGTBi1BP-02), 4-[4′-(carbazol-9-yl)biphenyl-4-yl]-4′-(2-naphthyl)-4″-phenyltriphenylamine (abbreviation: YGTBiβNB), N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-N-[4-(1-naphthyl)phenyl]-9,9′-spirobi[9H-fluoren]-2-amine (abbreviation: PCBNBSF), N,N-bis([1,1′-biphenyl]-4-yl)-9,9′-spirobi[9H-fluoren]-2-amine (abbreviation: BBASF), N,N-bis([1,1′-biphenyl]-4-yl)-9,9′-spirobi[9H-fluoren]-4-amine (abbreviation: BBASF(4)), N-(1,1′-biphenyl-2-yl)-N-(9,9-dimethyl-9H-fluoren-2-yl)-9,9′-spirobi[9H-fluoren]-4-amine (abbreviation: oFBiSF), N-(4-biphenyl)-N-(9,9-dimethyl-9H-fluoren-2-yl)dibenzofuran-4-amine (abbreviation: FrBiF), N-[4-(1-naphthyl)phenyl]-N-[3-(6-phenyldibenzofuran-4-yl)phenyl]-1-naphthylamine (abbreviation: mPDBfBNBN), 4-phenyl-4′-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: BPAFLP), 4-phenyl-3′-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: mBPAFLP), 4-phenyl-4′-[4-(9-phenylfluoren-9-yl)phenyl]triphenylamine (abbreviation: BPAFLBi), 4-phenyl-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBA1BP), 4,4′-diphenyl-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBBi1BP), 4-(1-naphthyl)-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBANB), 4,4′-di(1-naphthyl)-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBNBB), N-phenyl-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9,9′-spirobi[9H-fluoren]-2-amine (abbreviation: PCBASF), and N-(1,1′-biphenyl-4-yl)-9,9-dimethyl-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9H-fluoren-2-amine (abbreviation: PCBBiF). The second organic compound preferably has a relatively deep HOMO level of greater than or equal to −5.7 eV and less than or equal to −5.4 eV, like the above-described material. In addition, the HOMO level of the second organic compound is preferably less than a LUMO level of the first organic compound for easy hole induction, and the difference therebetween is preferably greater than or equal to 0.15 eV, more preferably greater than or equal to 0.20 eV. The hole-transport layer112includes a first hole-transport layer112-1and a second hole-transport layer112-2. The first hole-transport layer112-1is closer to the anode101than the second hole-transport layer112-2is. The first hole-transport layer112-1includes a third organic compound, and the second hole-transport layer112-2includes a fourth organic compound. The third organic compound and the fourth organic compound preferably have a hole-transport property. As the third organic compound and the fourth organic compound, the organic compound that can be used as the second organic compound can be similarly used. In this case, it is preferable that the HOMO level of the third organic compound be deeper than or equal to that of the second organic compound, and the HOMO level of the fourth organic compound be deeper than or equal to that of the third organic compound. Note that a difference between HOMO levels of the second organic compound and the third organic compound and a difference between HOMO levels of the third organic compound and the fourth organic compound are each preferably less than or equal to 0.2 eV. Preferably, the second organic compound to the fourth organic compound each have a hole-transport skeleton. A carbazole skeleton, a dibenzofuran skeleton, a dibenzothiophene skeleton, and an anthracene skeleton, with which the HOMO levels of the organic compounds do not become too shallow, are preferably used as the hole-transport skeleton. Materials of adjacent layers (e.g., the second organic compound and the third organic compound or the third organic compound and the fourth organic compound) preferably have the same hole-transport skeleton, in which case holes can be injected smoothly. In particular, a dibenzofuran skeleton is preferably used as the hole-transport skeleton. Furthermore, materials contained in adjacent layers (e.g., the second organic compound and the third organic compound or the third organic compound and the fourth organic compound) are preferably the same, in which case holes can be injected smoothly. In particular, the second organic compound and the third organic compound are preferably the same material. When the second organic compound has a relatively deep HOMO level of greater than or equal to −5.7 eV and less than or equal to −5.4 eV, the light-emitting device can have favorable characteristics even when the hole-transport layer112is formed of one layer as illustrated in FIG.1A2, instead of two layers as illustrated in FIG.1A1. That is, the first hole-transport layer112-1is not provided and the second hole-transport layer112-2is provided in contact with the hole-injection layer111. When the second organic compound has a deep HOMO level, a difference between HOMO levels of the second organic compound and the host material is small and thus the light-emitting device of one embodiment of the present invention can be achieved even when the hole-transport layer112has a single-layer structure. It is preferable that the second hole-transport layer112-2also function as an electron-blocking layer. The light emitting layer113includes a fifth organic compound and the emission center substance. The fifth organic compound is a host material in which the emission center substance is dispersed. As the emission center substance, fluorescent substances, phosphorescent substances, substances exhibiting thermally activated delayed fluorescence (TADF), or other light-emitting materials may be used. Furthermore, the light-emitting layer113may be a single layer or include a plurality of layers including different light-emitting materials. Note that one embodiment of the present invention is more preferable in the case where the light-emitting layer113exhibits fluorescence, specifically, blue fluorescence. Examples of the material that can be used as a fluorescent substance in the light-emitting layer113are as follows. Fluorescent substances other than those can also be used. The examples include 5,6-bis[4-(10-phenyl-9-anthryl)phenyl]-2,2′-bipyridine (abbreviation: PAP2BPy), 5,6-bis[4′-(10-phenyl-9-anthryl)biphenyl-4-yl]-2,2′-bipyridine (abbreviation: PAPP2BPy), N,N-diphenyl-N,N-bis[4-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6-diamine (abbreviation: 1,6FLPAPrn), N,N-bis(3-methylphenyl)-N,N-bis[3-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6-diamine (abbreviation: 1,6mMemFLPAPrn), N,N-bis[4-(9H-carbazol-9-yl)phenyl]-N,N-diphenylstilbene-4,4′-diamine (abbreviation: YGA2S), 4-(9H-carbazol-9-yl)-4′-(10-phenyl-9-anthryl)triphenylamine (abbreviation: YGAPA), 4-(9H-carbazol-9-yl)-4′-(9,10-diphenyl-2-anthryl)triphenylamine (abbreviation: 2YGAPPA), N,9-diphenyl-N-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: PCAPA), perylene, 2,5,8,11-tetra(tert-butyl)perylene (abbreviation: TBP), 4-(10-phenyl-9-anthryl)-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBAPA), N,N′-(2-tert-butylanthracene-9,10-diyldi-4,1-phenylene)bis[N,N,N-triphenyl-1,4-phenylenediamine] (abbreviation: DPABPA), N,9-diphenyl-N-[4-(9,10-diphenyl-2-anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: 2PCAPPA), N-[4-(9,10-diphenyl-2-anthryl)phenyl]-N,N,N-triphenyl-1,4-phenylenediamine (abbreviation: 2DPAPPA), N,N,N′,N′,N″,N″,N′″,N′″-octaphenyldibenzo[g,p]chrysene-2,7,10,15-tetraamine (abbreviation: DBC1), coumarin 30, N-(9,10-diphenyl-2-anthryl)-N,9-diphenyl-9H-carbazol-3-amine (abbreviation: 2PCAPA), N-[9,10-bis(1,1′-biphenyl-2-yl)-2-anthryl]-N,9-diphenyl-9H-carbazol-3-amine (abbreviation: 2PCABPhA), N-(9,10-diphenyl-2-anthryl)-N,N,N-triphenyl-1,4-phenylenediamine (abbreviation: 2DPAPA), N-[9,10-bis(1,1′-biphenyl-2-yl)-2-anthryl]-N,N,N-triphenyl-1,4-phenylenediamine (abbreviation: 2DPABPhA), 9,10-bis(1,1′-biphenyl-2-yl)-N-[4-(9H-carbazol-9-yl)phenyl]-N-phenylanthracen-2-amine (abbreviation: 2YGABPhA), N,N,9-triphenylanthracen-9-amine (abbreviation: DPhAPhA), coumarin 545T, N,N-diphenylquinacridone (abbreviation: DPQd), rubrene, 5,12-bis(1,1′-biphenyl-4-yl)-6,11-diphenyltetracene (abbreviation: BPT), 2-(2-{2-[4-(dimethylamino)phenyl]ethenyl}-6-methyl-4H-pyran-4-ylidene)propanedinitrile (abbreviation: DCM1), 2-{2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizin-9-yl)ethenyl]-4H-pyran-4-ylide ne}propanedinitrile (abbreviation: DCM2), N,N,N′,N′-tetrakis(4-methylphenyl)tetracene-5,11-diamine (abbreviation: p-mPhTD), 7,14-diphenyl-N,N,N,N-tetrakis(4-methylphenyl)acenaphtho[1,2-a]fluoranthene-3,10-diamine (abbreviation: p-mPhAFD), 2-{2-isopropyl-6-[2-(1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizin-9-yl)ethenyl]-4H-pyran-4-ylidene}propanedinitrile (abbreviation: DCJTI), 2-{2-tert-butyl-6-[2-(1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizin-9-yl)ethenyl]-4H-pyran-4-ylidene}propanedinitrile (abbreviation: DCJTB), 2-(2,6-bis{2-[4-(dimethylamino)phenyl]ethenyl}-4H-pyran-4-ylidene)propanedinitrile (abbreviation: BisDCM), 2-{2,6-bis[2-(8-methoxy-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizin-9-yl) ethenyl]-4H-pyran-4-ylidene}propanedinitrile (abbreviation: BisDCJTM), N,N′-(pyrene-1,6-diyl)bis[(6,N-diphenylbenzo[b]naphtho[1,2-d]furan)-8-amine](abbreviation:1,6BnfAPrn-03), 3,10-bis[N-(9-phenyl-9H-carbazol-2-yl)-N-phenylamino]naphtho[2,3-b;6,7-b′]bisbenzofuran (abbreviation: 3,10PCA2Nbf(IV)-02), 3,10-bis[N-(dibenzofuran-3-yl)-N-phenylamino]naphtho[2,3-b;6,7-b′]bisbenzofuran (abbreviation: 3,10FrA2Nbf(IV)-02). Condensed aromatic diamine compounds typified by pyrenediamine compounds such as 1,6FLPAPrn, 1,6mMemFLPAPrn, and 1,6BnfAPrn-03 are particularly preferred because of their high hole-trapping properties, high emission efficiency, and high reliability. Examples of the material that can be used when a phosphorescent substance is used as the emission center substance in the light-emitting layer113are as follows. The examples include: an organometallic iridium complex having a 4H-triazole skeleton, such as tris{2-[5-(2-methylphenyl)-4-(2,6-dimethylphenyl)-4H-1,2,4-triazol-3-yl-κN2]phenyl-κC}iridium(III) (abbreviation: [Ir(mpptz-dmp)3]), tris(5-methyl-3,4-diphenyl-4H-1,2,4-triazolato)iridium(III) (abbreviation: [Ir(Mptz)3]), and tris[4-(3-biphenyl)-5-isopropyl-3-phenyl-4H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(iPrptz-3b)3]); an organometallic iridium complex having a 1H-triazole skeleton, such as tris[3-methyl-1-(2-methylphenyl)-5-phenyl-1H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(Mptz1-mp)3]) and tris(1-methyl-5-phenyl-3-propyl-1H-1,2,4-triazolato)iridium(III) (abbreviation: [Ir(Prptz1-Me)3]); an organometallic iridium complex having an imidazole skeleton, such as fac-tris[1-(2,6-diisopropylphenyl)-2-phenyl-1H-imidazole]iridium(III) (abbreviation: [Ir(iPrpmi)3]) and tris[3-(2,6-dimethylphenyl)-7-methylimidazo[1,2-f]phenanthridinato]iridium(III) (abbreviation: [Ir(dmpimpt-Me)3]); and an organometallic iridium complex in which a phenylpyridine derivative having an electron-withdrawing group is a ligand, such as bis[2-(4′,6′-difluorophenyl)pyridinato-N,C2′]iridium(III) tetrakis(1-pyrazolyl)borate (abbreviation: FIr6), bis[2-(4′,6′-difluorophenyl)pyridinato-N,C2′]iridium(III) picolinate (abbreviation: Firpic), bis{2-[3′,5′-bis(trifluoromethyl)phenyl]pyridinato-N,C2′}iridium(III) picolinate (abbreviation: [Ir(CF3ppy)2(pic)]), and bis[2-(4′,6′-difluorophenyl)pyridinato-N,C2′]iridium(III) acetylacetonate (abbreviation: FIr(acac)). These compounds emit blue phosphorescence and have a peak of the emission spectrum at 440 nm to 520 nm. Other examples include organometallic iridium complexes having a pyrimidine skeleton, such as tris(4-methyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(mppm)3]), tris(4-t-butyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm)3]), (acetylacetonato)bis(6-methyl-4-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(mppm)2(acac)]), (acetylacetonato)bis(6-tert-butyl-4-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm)2(acac)]), (acetylacetonato)bis[6-(2-norbornyl)-4-phenylpyrimidinato]iridium(III) (abbreviation: [[Ir(nbppm)2(acac)]), (acetylacetonato)bis[5-methyl-6-(2-methylphenyl)-4-phenylpyrimidinato]iridium(III) (abbreviation: [Ir(mpmppm)2(acac)]), and (acetylacetonato)bis(4,6-diphenylpyrimidinato)iridium(III) (abbreviation: [Ir(dppm)2(acac)]); organometallic iridium complexes having a pyrazine skeleton, such as (acetylacetonato)bis(3,5-dimethyl-2-phenylpyrazinato)iridium(III) (abbreviation: [Ir(mppr-Me)2(acac)]) and (acetylacetonato)bis(5-isopropyl-3-methyl-2-phenylpyrazinato)iridium(III) (abbreviation: [Ir(mppr-iPr)2(acac)]); organometallic iridium complexes having a pyridine skeleton, such as tris(2-phenylpyridinato-N,C2′)iridium(III) (abbreviation: [Ir(ppy)3]), bis(2-phenylpyridinato-N,C2′)iridium(III) acetylacetonate (abbreviation: [Ir(ppy)2(acac)]), bis(benzo[h]quinolinato)iridium(III) acetylacetonate (abbreviation: [Ir(bzq)2(acac)]), tris(benzo[h]quinolinato)iridium(III) (abbreviation: [Ir(bzq)3]), tris(2-phenylquinolinato-N,C2′)iridium(III) (abbreviation: [Ir(pq)3]), and bis(2-phenylquinolinato-N,C2′)iridium(III) acetylacetonate (abbreviation: [Ir(pq)2(acac)]); and a rare earth metal complex such as tris(acetylacetonato)(monophenanthroline)terbium(III) (abbreviation: [Tb(acac)3(Phen)]). These are mainly compounds that emit green phosphorescence and have a peak of the emission spectrum at 500 nm to 600 nm. Note that organometallic iridium complexes having a pyrimidine skeleton have distinctively high reliability and emission efficiency and thus are especially preferable. Other examples include organometallic iridium complexes having a pyrimidine skeleton, such as (diisobutyrylmethanato)bis[4,6-bis(3-methylphenyl)pyrimidinatoiridium(III) (abbreviation: [Ir(5mdppm)2(dibm)]), bis[4,6-bis(3-methylphenyl)pyrimidinato](dipivaloylmethanato)iridium(III) (abbreviation: [Ir(5mdppm)2(dpm)]), and bis[4,6-di(naphthalen-1-yl)pyrimidinato(dipivaloylmethanato)iridium(III) (abbreviation: [Ir(dlnpm)2(dpm)]); organometallic iridium complexes having a pyrazine skeleton, such as (acetylacetonato)bis(2,3,5-triphenylpyrazinato)iridium(III) (abbreviation: [Ir(tppr)2(acac)]), bis(2,3,5-triphenylpyrazinato)(dipivaloylmethanato)iridium(III) (abbreviation: [Ir(tppr)2(dpm)]), and (acetylacetonato)bis[2,3-bis(4-fluorophenyl)quinoxalinatoiridium(III) (abbreviation: [Ir(Fdpq)2(acac)]); organometallic iridium complexes having a pyridine skeleton, such as tris(1-phenylisoquinolinato-N,C2′)iridium(III) (abbreviation: [Ir(piq)3]) and bis(1-phenylisoquinolinato-N,C2′)iridium(III) acetylacetonate (abbreviation: [Ir(piq)2(acac)]); platinum complexes such as 2,3,7,8,12,13,17,18-octaethyl-21H,23H-porphyrinplatinum(II) (abbreviation: [PtOEP]); and rare earth metal complexes such as tris(1,3-diphenyl-1,3-propanedionato) (monophenanthroline)europium(III) (abbreviation: [Eu(DBM)3(Phen)]) and tris[1-(2-thenoyl)-3,3,3-trifluoroacetonato (monophenanthroline)europium(III) (abbreviation: [Eu(TTA)3(Phen)]). These compounds emit red phosphorescence having a peak of the emission spectrum at 600 nm to 700 nm. Furthermore, the organometallic iridium complexes having a pyrazine skeleton can provide red light emission with favorable chromaticity. Besides the above phosphorescent compounds, known phosphorescent materials may be selected and used. Examples of the TADF material include a fullerene, a derivative thereof, an acridine, a derivative thereof, and an eosin derivative. Furthermore, a metal-containing porphyrin, such as a porphyrin containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), or palladium (Pd), can be given. Examples of the metal-containing porphyrin include a protoporphyrin-tin fluoride complex (SnF2(Proto IX)), a mesoporphyrin-tin fluoride complex (SnF2(Meso IX)), a hematoporphyrin-tin fluoride complex (SnF2(Hemato IX)), a coproporphyrin tetramethyl ester-tin fluoride complex (SnF2(Copro III-4Me)), an octaethylporphyrin-tin fluoride complex (SnF2(OEP)), an etioporphyrin-tin fluoride complex (SnF2(Etio I)), and an octaethylporphyrin-platinum chloride complex (PtCl2OEP), which are represented by the following structural formulae. Alternatively, a heterocyclic compound having one or both of a π-electron rich heteroaromatic ring and a π-electron deficient heteroaromatic ring that is represented by the following structural formulae, such as 2-(biphenyl-4-yl)-4,6-bis(12-phenylindolo[2,3-a]carbazol-11-yl)-1,3,5-triazine (abbreviation: PIC-TRZ), 9-(4,6-diphenyl-1,3,5-triazin-2-yl)-9′-phenyl-9H,9′H-3,3′-bicarbazole (abbreviation: PCCzTzn), 2-{4-[3-(N-phenyl-9H-carbazol-3-yl)-9H-carbazol-9-yl]phenyl}-4,6-diphenyl-1,3,5-triazine (abbreviation: PCCzPTzn), 2-[4-(10H-phenoxazine-10-yl)phenyl]-4,6-diphenyl-1,3,5-triazine (abbreviation: PXZ-TRZ), 3-[4-(5-phenyl-5,10-dihydrophenazin-10-yl)phenyl]-4,5-diphenyl-1,2,4-triazole (abbreviation: PPZ-3TPT), 3-(9,9-dimethyl-9H-acridin-10-yl)-9H-xanthen-9-one (abbreviation: ACRXTN), bis[4-(9,9-dimethyl-9,10-dihydroacridine)phenyl]sulfone (abbreviation: DMAC-DPS), or 10-phenyl-10H,10′H-spiro[acridin-9,9′-anthracen]-10′-one (abbreviation: ACRSA) can be used. Such a heterocyclic compound is preferred because of having excellent electron-transport and hole-transport properties owing to a π-electron rich heteroaromatic ring and a π-electron deficient heteroaromatic ring. Among skeletons having the π-electron deficient heteroaromatic ring, a pyridine skeleton, a diazine skeleton (a pyrimidine skeleton, a pyrazine skeleton, and a pyridazine skeleton), and a triazine skeleton are preferred because of their high stability and reliability. In particular, a benzofuropyrimidine skeleton, a benzothienopyrimidine skeleton, a benzofuropyrazine skeleton, and a benzothienopyrazine skeleton are preferred because of their high accepting properties and reliability. Among skeletons having the π-electron rich heteroaromatic ring, an acridine skeleton, a phenoxazine skeleton, a phenothiazine skeleton, a furan skeleton, a thiophene skeleton, and a pyrrole skeleton have high stability and reliability; therefore, at least one of these skeletons is preferably included. As a furan skeleton, a dibenzofuran skeleton is preferable. As a thiophene skeleton, a dibenzothiophene skeleton is preferable. As a pyrrole skeleton, an indole skeleton, a carbazole skeleton, an indolocarbazole skeleton, a bicarbazole skeleton, and a 3-(9-phenyl-9H-carbazol-3-yl)-9H-carbazole skeleton are particularly preferable. Note that a substance in which the π-electron rich heteroaromatic ring is directly bonded to the π-electron deficient heteroaromatic ring is particularly preferred because the electron-donating property of the π-electron rich heteroaromatic ring and the electron-accepting property of the π-electron deficient heteroaromatic ring are both improved, the energy difference between the S1 level and the T1 level becomes small, and thus thermally activated delayed fluorescence can be obtained with high efficiency. Note that an aromatic ring to which an electron-withdrawing group such as a cyano group is bonded may be used instead of the π-electron deficient heteroaromatic ring. As a π-electron rich skeleton, an aromatic amine skeleton, a phenazine skeleton, or the like can be used. As a π-electron deficient skeleton, a xanthene skeleton, a thioxanthene dioxide skeleton, an oxadiazole skeleton, a triazole skeleton, an imidazole skeleton, an anthraquinone skeleton, a skeleton containing boron such as phenylborane or boranthrene, an aromatic ring or a heteroaromatic ring having a cyano group or a nitrile group such as benzonitrile or cyanobenzene, a carbonyl skeleton such as benzophenone, a phosphine oxide skeleton, a sulfone skeleton, or the like can be used. As described above, a π-electron deficient skeleton and a π-electron rich skeleton can be used instead of at least one of the π-electron deficient heteroaromatic ring and the π-electron rich heteroaromatic ring. Note that a TADF material is a material having a small difference between the S1 level and the T1 level and a function of converting triplet excitation energy into singlet excitation energy by reverse intersystem crossing. Thus, a TADF material can upconvert triplet excitation energy into singlet excitation energy (i.e., reverse intersystem crossing) using a small amount of thermal energy and efficiently generate a singlet excited state. In addition, the triplet excitation energy can be converted into luminescence. An exciplex whose excited state is formed of two kinds of substances has an extremely small difference between the S1 level and the T1 level and functions as a TADF material capable of converting triplet excitation energy into singlet excitation energy. A phosphorescent spectrum observed at a low temperature (e.g., 77 K to 10 K) is used for an index of the T1 level. When the level of energy with a wavelength of the line obtained by extrapolating a tangent to the fluorescent spectrum at a tail on the short wavelength side is the S1 level and the level of energy with a wavelength of the line obtained by extrapolating a tangent to the phosphorescent spectrum at a tail on the short wavelength side is the T1 level, the difference between the S1 level and the T1 level of the TADF material is preferably smaller than or equal to 0.3 eV, further preferably smaller than or equal to 0.2 eV. When the TADF material is used as an emission center substance, the S1 level and the T1 level of the host material are preferably higher than those of the TADF material. As the host material in the light-emitting layer113, various carrier-transport materials such as materials having an electron-transport property, materials having a hole-transport property, and the TADF materials can be used. The material having a hole-transport property is preferably an organic compound having an aromatic amine skeleton or a π-electron rich heteroaromatic ring skeleton. Examples of such a compound is as follows: 4,4′-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (abbreviation: NPB), N,N-bis(3-methylphenyl)-N,N-diphenyl-[1,1′-biphenyl]-4,4′-diamine (abbreviation: TPD), 4,4′-bis[N-(spiro-9,9′-bifluoren-2-yl)-N-phenylamino]biphenyl (abbreviation: BSPB), 4-phenyl-4′-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: BPAFLP), 4-phenyl-3′-(9-phenylfluoren-9-yl)triphenylamine (abbreviation: mBPAFLP), 4-phenyl-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBA1BP), 4,4′-diphenyl-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBBi1BP), 4-(1-naphthyl)-4′-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBANB), 4,4′-di(1-naphthyl)-4″-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBNBB), 9,9-dimethyl-N-phenyl-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]fluoren-2-amine (abbreviation: PCBAF), and N-phenyl-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9,9′-spirobi[9H-fluoren]-2-amine (abbreviation: PCBASF); compounds having a carbazole skeleton such as 1,3-bis(N-carbazolyl)benzene (abbreviation: mCP), 4,4′-di(N-carbazolyl)biphenyl (abbreviation: CBP), 3,6-bis(3,5-diphenylphenyl)-9-phenylcarbazole (abbreviation: CzTP), and 3,3′-bis(9-phenyl-9H-carbazole) (abbreviation: PCCP); compounds having a thiophene skeleton such as 4,4′,4″-(benzene-1,3,5-triyl)tri(dibenzothiophene) (abbreviation: DBT3P-II), 2,8-diphenyl-4-[4-(9-phenyl-9H-fluoren-9-yl)phenyl]dibenzothiophene (abbreviation: DBTFLP-III), and 4-[4-(9-phenyl-9H-fluoren-9-yl)phenyl]-6-phenyldibenzothiophene (abbreviation: DBTFLP-IV); and compounds having a furan skeleton such as 4,4′,4″-(benzene-1,3,5-triyl)tri(dibenzofuran) (abbreviation: DBF3P-II) and 4-{3-[3-(9-phenyl-9H-fluoren-9-yl)phenyl]phenyl}dibenzofuran (abbreviation: mmDBFFLBi-II). Among the above materials, the compound having an aromatic amine skeleton and the compound having a carbazole skeleton are preferred because these compounds are highly reliable and have high hole-transport properties to contribute to a reduction in driving voltage. In addition, the organic compounds given as examples of the above second organic compound can also be used. As the material having an electron-transport property, metal complexes such as bis(10-hydroxybenzo[h]quinolinato)beryllium(II) (abbreviation: BeBq2), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum(III) (abbreviation: BAlq), bis(8-quinolinolato)zinc(II) (abbreviation: Znq), bis[2-(2-benzoxazolyl)phenolato]zinc(II) (abbreviation: ZnPBO), and bis[2-(2-benzothiazolyl)phenolato]zinc(II) (abbreviation: ZnBTZ); or an organic compound having a π-electron deficient heteroaromatic ring skeleton is preferable. Examples of the organic compound having a π-electron deficient heteroaromatic ring skeleton include 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butylphenyl)-1,2,4-triazole (abbreviation: TAZ), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD-7), 9-[4-(5-phenyl-1,3,4-oxadiazol-2-yl)phenyl]-9H-carbazole (abbreviation: CO11), 2,2′,2″-(1,3,5-benzenetriyl)tris(1-phenyl-1H-benzimidazole) (abbreviation: TPBI), and02-[3-(dibenzothiophen-4-yl)phenyl]-1-phenyl-1H-benzimidazole (abbreviation: mDBTBIm-II); heterocyclic compounds having a diazine skeleton, such as 2-[3-(dibenzothiophen-4-yl)phenyl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTPDBq-II), 2-[3′-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II), 2-[3′-(9H-carbazol-9-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mCzBPDBq), 4,6-bis[3-(phenanthren-9-yl)phenyl]pyrimidine (abbreviation: 4,6mPnP2Pm), and 4,6-bis[3-(4-dibenzothienyl)phenyl]pyrimidine (abbreviation: 4,6mDBTP2Pm-II); and heterocyclic compounds having a pyridine skeleton, such as 3,5-bis[3-(9H-carbazol-9-yl)phenyl]pyridine (abbreviation: 35DCzPPy) and 1,3,5-tri[3-(3-pyridyl)phenyl]benzene (abbreviation: TmPyPB). Among the above materials, the heterocyclic compound having a diazine skeleton and the heterocyclic compound having a pyridine skeleton have high reliability and thus are preferable. In particular, the heterocyclic compound having a diazine (pyrimidine or pyrazine) skeleton has an excellent electron-transport property to contribute to a reduction in driving voltage. As the TADF material that can be used as the host material, the above materials mentioned as the TADF material can also be used. When the TADF material is used as the host material, triplet excitation energy generated in the TADF material is converted into singlet excitation energy by reverse intersystem crossing and transferred to the emission center substance, whereby the emission efficiency of the light-emitting device can be increased. Here, the TADF material functions as an energy donor, and the emission center substance functions as an energy acceptor. This is very effective in the case where the emission center substance is a fluorescent substance. In that case, it is preferable that the S1 level of the TADF material be higher than the S1 level of the fluorescent substance in order that high emission efficiency be achieved. Furthermore, the T1 level of the TADF material is preferably higher than the S1 level of the fluorescent substance. Therefore, the T1 level of the TADF material is preferably higher than the T1 level of the fluorescent substance. A TADF material that emits light whose wavelength overlaps with the wavelength on a lowest-energy-side absorption band of the fluorescent substance is preferably used, in which case excitation energy is transferred smoothly from the TADF material to the fluorescent substance and light emission can be obtained efficiently. In addition, in order to efficiently generate singlet excitation energy from the triplet excitation energy by reverse intersystem crossing, carrier recombination preferably occurs in the TADF material. It is also preferable that the triplet excitation energy generated in the TADF material not be transferred to the triplet excitation energy of the fluorescent substance. For that reason, the fluorescent substance preferably has a protective group around a luminophore (a skeleton which causes light emission) of the fluorescent substance. As the protective group, a substituent having no π bond and a saturated hydrocarbon are preferably used. Specific examples include an alkyl group having 3 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, and a trialkylsilyl group having 3 to 10 carbon atoms. It is further preferable that the fluorescent substance have a plurality of protective groups. The substituents having no π bond are poor in carrier transport performance, whereby the TADF material and the luminophore of the fluorescent substance can be made away from each other with little influence on carrier transportation or carrier recombination. Here, the luminophore refers to an atomic group (skeleton) that causes light emission in a fluorescent substance. The luminophore is preferably a skeleton having a π bond, further preferably includes an aromatic ring, and still further preferably includes a condensed aromatic ring or a condensed heteroaromatic ring. Examples of the condensed aromatic ring or the condensed heteroaromatic ring include a phenanthrene skeleton, a stilbene skeleton, an acridone skeleton, a phenoxazine skeleton, and a phenothiazine skeleton. Specifically, a fluorescent substance having any of a naphthalene skeleton, an anthracene skeleton, a fluorene skeleton, a chrysene skeleton, a triphenylene skeleton, a tetracene skeleton, a pyrene skeleton, a perylene skeleton, a coumarin skeleton, a quinacridone skeleton, and a naphthobisbenzofuran skeleton is preferred because of its high fluorescence quantum yield. In the case where a fluorescent substance is used as the emission center substance, a material having an anthracene skeleton is favorably used as the host material. The use of a substance having an anthracene skeleton as the host material for the fluorescent substance makes it possible to obtain a light-emitting layer with high emission efficiency and high durability. Among the substances having an anthracene skeleton, a substance having a diphenylanthracene skeleton, in particular, a substance having a 9,10-diphenylanthracene skeleton, is chemically stable and thus is preferably used as the host material. The host material preferably has a carbazole skeleton because the hole-injection and hole-transport properties are improved; further preferably, the host material has a benzocarbazole skeleton in which a benzene ring is further condensed to carbazole because the HOMO level thereof is shallower than that of carbazole by approximately 0.1 eV and thus holes enter the host material easily. In particular, the host material preferably has a dibenzocarbazole skeleton because the HOMO level thereof is shallower than that of carbazole by approximately 0.1 eV so that holes enter the host material easily, the hole-transport property is improved, and the heat resistance is increased. Accordingly, a substance that has both a 9,10-diphenylanthracene skeleton and a carbazole skeleton (or a benzocarbazole or dibenzocarbazole skeleton) is further preferable as the host material. Note that in terms of the hole-injection and hole-transport properties described above, instead of a carbazole skeleton, a benzofluorene skeleton or a dibenzo fluorene skeleton may be used. Examples of such a substance include 9-phenyl-3-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: PCzPA), 3-[4-(1-naphthyl)-phenyl]-9-phenyl-9H-carbazole (abbreviation: PCPN), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA), 6-[3-(9,10-diphenyl-2-anthryl)phenyl]-benzo[b]naphtho[1,2-d]furan (abbreviation: 2mBnfPPA), 9-phenyl-10-{4-(9-phenyl-9H-fluoren-9-yl)biphenyl-4′-yl}anthracene (abbreviation: FLPPA), and 9-(1-naphthyl)-10-[4-(2-naphthyl)phenyl]anthracene (abbreviation: αN-βNPAnth). Note that CzPA, cgDBCzPA, 2mBnfPPA, and PCzPA have excellent characteristics and thus are preferably selected. Note that the host material (the fifth organic compound) may be a mixture of a plurality of kinds of substances; in the case of using a mixed host material, it is preferable to mix a material having an electron-transport property with a material having a hole-transport property. By mixing the material having an electron-transport property with the material having a hole-transport property, the transport property of the light-emitting layer113can be easily adjusted and a recombination region can be easily controlled. The weight ratio of the content of the material having a hole-transport property to the content of the material having an electron-transport property may be 1:19 to 19:1. In the case of using the mixed host material as the fifth organic compound, the HOMO level of the fifth organic compound is regarded as a HOMO level of the material having a hole-transport property. Note that a phosphorescent substance can be used as part of the mixed material. When a fluorescent substance is used as the emission center substance, a phosphorescent substance can be used as an energy donor for supplying excitation energy to the fluorescent substance. An exciplex may be formed of these mixed materials. When these mixed materials are selected so as to form an exciplex that exhibits light emission whose wavelength overlaps with the wavelength on a lowest-energy-side absorption band of the light-emitting material, energy can be transferred smoothly and light emission can be obtained efficiently. The use of such a structure is preferred because the driving voltage can also be reduced. Note that at least one of the materials forming an exciplex may be a phosphorescent substance. In this case, triplet excitation energy can be efficiently converted into singlet excitation energy by reverse intersystem crossing. Combination of a material having an electron-transport property and a material having a hole-transport property whose HOMO level is higher than or equal to that of the material having an electron-transport property is preferable for forming an exciplex efficiently. In addition, the LUMO level of the material having a hole-transport property is preferably higher than or equal to the LUMO level of the material having an electron-transport property. Note that the LUMO levels and the HOMO levels of the materials can be derived from the electrochemical characteristics (the reduction potentials and the oxidation potentials) of the materials that are measured by cyclic voltammetry (CV). The formation of an exciplex can be confirmed by a phenomenon in which the emission spectrum of the mixed film in which the material having a hole-transport property and the material having an electron-transport property are mixed is shifted to the longer wavelength side than the emission spectra of each of the materials (or has another peak on the longer wavelength side) observed by comparison of the emission spectra of the material having a hole-transport property, the material having an electron-transport property, and the mixed film of these materials, for example. Alternatively, the formation of an exciplex can be confirmed by a difference in transient response, such as a phenomenon in which the transient PL lifetime of the mixed film has more long lifetime components or has a larger proportion of delayed components than that of each of the materials, observed by comparison of transient photoluminescence (PL) of the material having a hole-transport property, the material having an electron-transport property, and the mixed film of the materials. The transient PL can be rephrased as transient electroluminescence (EL). That is, the formation of an exciplex can also be confirmed by a difference in transient response observed by comparison of the transient EL of the material having a hole-transport property, the material having an electron-transport property, and the mixed film of the materials. The light-emitting device of one embodiment of the present invention having the above-described structure can have a long lifetime. Embodiment 2 Next, examples of specific structures and materials of the aforementioned light-emitting device will be described. As described above, the light-emitting device of one embodiment of the present invention includes the EL layer103that is positioned between the pair of electrodes (the anode101and the cathode102) and has a plurality of layers. In the EL layer103, the hole-injection layer111, the first hole-transport layer112-1, the second hole-transport layer112-2, the light-emitting layer113, and the electron-transport layer are provided from the anode101side. There is no particular limitation on the other layers included in the EL layer103, and various layers such as a hole-injection layer, a hole-transport layer, an electron-transport layer, an electron-injection layer, a carrier-blocking layer, an exciton-blocking layer, and a charge generation layer can be employed. The anode101is preferably formed using any of metals, alloys, conductive compounds with a high work function (specifically, higher than or equal to 4.0 eV), mixtures thereof, and the like. Specific examples include indium oxide-tin oxide (ITO: indium tin oxide), indium oxide-tin oxide containing silicon or silicon oxide, indium oxide-zinc oxide, and indium oxide containing tungsten oxide and zinc oxide (IWZO). Such conductive metal oxide films are usually formed by a sputtering method, but may be formed by application of a sol-gel method or the like. In an example of the formation method, indium oxide-zinc oxide is deposited by a sputtering method using a target obtained by adding 1 wt % to 20 wt % of zinc oxide to indium oxide. Furthermore, a film of indium oxide containing tungsten oxide and zinc oxide (IWZO) can be formed by a sputtering method using a target in which tungsten oxide and zinc oxide are added to indium oxide at 0.5 wt % to 5 wt % and 0.1 wt % to 1 wt %, respectively. Alternatively, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), nitride of a metal material (e.g., titanium nitride), or the like can be used. Graphene can also be used. Note that although the typical materials for forming the anode are listed above, a composite material of an organic compound having a hole-transport property and a substance exhibiting an electron-accepting property with respect to the organic compound is used for the hole-injection layer111of one embodiment of the present invention; thus, an electrode material can be selected regardless of its work function. Two kinds of stacked layer structure of the EL layer103are described: a structure illustrated in FIGS.1A1and1A2, which includes the electron-injection layer115in addition to the hole-injection layer111, the hole-transport layer112(the first hole-transport layer112-1and the second hole-transport layer112-2), the light-emitting layer113, and the electron-transport layer114; and a structure illustrated inFIG.1B, which includes a charge generation layer116in addition to the hole-injection layer111, the first hole-transport layer112-1, the second hole-transport layer112-2, the light-emitting layer113, and the electron-transport layer114. Materials for forming each layer will be specifically described below. Since the hole-injection layer111, the hole-transport layer112(the first hole-transport layer112-1and the second hole-transport layer112-2), and the light-emitting layer113are described in detail in Embodiment 1, the description thereof is not repeated. Refer to the description in Embodiment 1. The electron-transport layer114is provided between the light-emitting layer113and the cathode102. The electron-transport layer114contains an organic compound having an electron-transport property. As the organic compound having an electron-transport property, any of the above-mentioned electron-transport organic compounds that can be used as the host material, and the above-mentioned organic compounds that can be used as the host material for the fluorescent substance can be used. It is preferable to use an organic compound whose electron mobility in the case where the square root of the electric field strength [V/cm] is 600 is higher than or equal to 1×10−7cm2/Vs and lower than or equal to 5×10−5cm2/Vs. A layer containing an alkali metal, an alkaline earth metal, or a compound thereof such as lithium fluoride (LiF), cesium fluoride (CsF), or calcium fluoride (CaF2) may be provided as the electron-injection layer115between the electron-transport layer114and the cathode102. For example, an electride or a layer that is formed using a substance having an electron-transport property and that includes an alkali metal, an alkaline earth metal, or a compound thereof can be used as the electron-injection layer115. Examples of the electride include a substance in which electrons are added at high concentration to calcium oxide-aluminum oxide. Instead of the electron-injection layer115, the charge generation layer116may be provided between the electron-transport layer114and the cathode102(FIG.1). The charge generation layer116refers to a layer capable of injecting holes into a layer in contact with the cathode side of the charge generation layer116and electrons into a layer in contact with the anode side thereof when a potential is applied. The charge generation layer116includes at least a p-type layer117. The p-type layer117is preferably formed using any of the composite materials given above as examples of materials that can be used for the hole-injection layer111. The p-type layer117may be formed by stacking a film containing the above-described acceptor material as a material included in the composite material and a film containing a hole-transport material. When a potential is applied to the p-type layer117, electrons are injected into the electron-transport layer114and holes are injected into the cathode102serving as a cathode; thus, the light-emitting device operates. Note that the charge generation layer116preferably includes an electron-relay layer118and/or an electron-injection buffer layer119in addition to the p-type layer117. The electron-relay layer118includes at least the substance having an electron-transport property and has a function of preventing an interaction between the electron-injection buffer layer119and the p-type layer117and smoothly transferring electrons. The LUMO level of the substance having an electron-transport property contained in the electron-relay layer118is preferably between the LUMO level of the electron-accepting substance in the p-type layer117and the LUMO level of a substance contained in a layer of the electron-transport layer114that is in contact with the charge generation layer116. As a specific value of the energy level, the LUMO level of the substance having an electron-transport property in the electron-relay layer118is preferably higher than or equal to −5.0 eV, more preferably higher than or equal to −5.0 eV and lower than or equal to −3.0 eV. Note that as the substance having an electron-transport property in the electron-relay layer118, a phthalocyanine-based material or a metal complex having a metal-oxygen bond and an aromatic ligand is preferably used. A substance having an excellent electron-injection property can be used for the electron-injection buffer layer119. For example, an alkali metal, an alkaline earth metal, a rare earth metal, or a compound thereof (an alkali metal compound (including an oxide such as lithium oxide, a halide, and a carbonate such as lithium carbonate and cesium carbonate), an alkaline earth metal compound (including an oxide, a halide, and a carbonate), or a rare earth metal compound (including an oxide, a halide, and a carbonate)) can be used. In the case where the electron-injection buffer layer119includes the substance having an electron-transport property and a substance having an electron-donating property, an organic compound such as tetrathianaphthacene (abbreviation: TTN), nickelocene, or decamethylnickelocene can be used as the substance having an electron-donating property, as well as an alkali metal, an alkaline earth metal, a rare earth metal, a compound thereof (an alkali metal compound (including an oxide such as lithium oxide, a halide, and a carbonate such as lithium carbonate and cesium carbonate), an alkaline earth metal compound (including an oxide, a halide, and a carbonate), or a rare earth metal compound (including an oxide, a halide, and a carbonate)). As the substance having an electron-transport property, a material similar to the above-described material for the electron-transport layer114can be used. For the cathode102, a metal, an alloy, an electrically conductive compound, or a mixture thereof each having a low work function (specifically, lower than or equal to 3.8 eV) or the like can be used. Specific examples of such a cathode material are elements belonging to Groups 1 and 2 of the periodic table, such as alkali metals (e.g., lithium (Li) and cesium (Cs)), magnesium (Mg), calcium (Ca), and strontium (Sr), alloys containing these elements (e.g., MgAg and AlLi), rare earth metals such as europium (Eu) and ytterbium (Yb), and alloys containing these rare earth metals. However, when the electron-injection layer is provided between the cathode102and the electron-transport layer, for the cathode102, a variety of conductive materials such as Al, Ag, ITO, or indium oxide-tin oxide containing silicon or silicon oxide can be used regardless of the work function. Films of these conductive materials can be formed by a dry process such as a vacuum evaporation method or a sputtering method, an inkjet method, a spin coating method, or the like. Alternatively, a wet process using a sol-gel method or a wet process using a paste of a metal material may be employed. Furthermore, any of a variety of methods can be used for forming the EL layer103, regardless of a dry method or a wet method. For example, a vacuum evaporation method, a gravure printing method, an offset printing method, a screen printing method, an inkjet method, a spin coating method, or the like may be used. Different methods may be used to form the electrodes or the layers described above. The structure of the layers provided between the anode101and the cathode102is not limited to the above-described structure. Preferably, a light-emitting region where holes and electrons recombine is positioned away from the anode101and the cathode102so as to prevent quenching due to the proximity of the light-emitting region and a metal used for electrodes and carrier-injection layers. Furthermore, in order that transfer of energy from an exciton generated in the light-emitting layer can be suppressed, preferably, the hole-transport layer and the electron-transport layer which are in contact with the light-emitting layer113, particularly a carrier-transport layer closer to the recombination region in the light-emitting layer113, are formed using a substance having a wider band gap than the light-emitting material of the light-emitting layer or the light-emitting material included in the light-emitting layer. Next, an embodiment of a light-emitting device with a structure in which a plurality of light-emitting units are stacked (this type of light-emitting device is also referred to as a stacked or tandem light-emitting device) is described with reference toFIG.1C. This light-emitting device includes a plurality of light-emitting units between an anode and a cathode. One light-emitting unit has substantially the same structure as the EL layer103illustrated in FIG.1A1or1A2. In other words, the light-emitting device illustrated in FIG.1A1,1A2, or1B includes a single light-emitting unit, and the light-emitting device illustrated inFIG.1Cincludes a plurality of light-emitting units. InFIG.1C, a first light-emitting unit511and a second light-emitting unit512are stacked between an anode501and a cathode502, and a charge generation layer513is provided between the first light-emitting unit511and the second light-emitting unit512. The anode501and the cathode502correspond, respectively, to the anode101and the cathode102illustrated in FIGS.1A1and1A2, and the materials given in the description for FIGS.1A1and1A2can be used. Furthermore, the first light-emitting unit511and the second light-emitting unit512may have the same structure or different structures. The charge generation layer513has a function of injecting electrons into one of the light-emitting units and injecting holes into the other of the light-emitting units when a voltage is applied between the anode501and the cathode502. That is, inFIG.1C, the charge generation layer513injects electrons into the first light-emitting unit511and holes into the second light-emitting unit512when a voltage is applied so that the potential of the anode becomes higher than the potential of the cathode. The charge generation layer513preferably has a structure similar to that of the charge generation layer116described with reference toFIG.1B. A composite material of an organic compound and a metal oxide has an excellent carrier-injection property and an excellent carrier-transport property; thus, low-voltage driving and low-current driving can be achieved. In the case where the anode-side surface of a light-emitting unit is in contact with the charge generation layer513, the charge generation layer513can also function as a hole-injection layer of the light-emitting unit; therefore, a hole-injection layer is not necessarily provided in the light-emitting unit. In the case where the charge generation layer513includes the electron-injection buffer layer119, the electron-injection buffer layer119functions as the electron-injection layer in the light-emitting unit on the anode side and thus, an electron-injection layer is not necessarily formed in the light-emitting unit on the anode side. The light-emitting device having two light-emitting units is described with reference toFIG.1C; however, one embodiment of the present invention can also be applied to a light-emitting device in which three or more light-emitting units are stacked. With a plurality of light-emitting units partitioned by the charge generation layer513between a pair of electrodes as in the light-emitting device of this embodiment, it is possible to provide a long-life element which can emit light with high luminance at a low current density. A light-emitting apparatus which can be driven at a low voltage and has low power consumption can be provided. When the emission colors of the light-emitting units are different, light emission of a desired color can be obtained from the light-emitting device as a whole. For example, in a light-emitting device having two light-emitting units, the emission colors of the first light-emitting unit may be red and green and the emission color of the second light-emitting unit may be blue, so that the light-emitting device can emit white light as the whole. The light-emitting device in which three or more light-emitting units are stacked can be, for example, a tandem device in which a first light-emitting unit includes a first blue light-emitting layer, a second light-emitting unit includes a yellow or yellow-green light-emitting layer and a red light-emitting layer, and a third light-emitting unit includes a second blue light-emitting layer. The tandem device can provide white light emission like the above light-emitting device. The above-described layers and electrodes such as the EL layer103, the first light-emitting unit511, the second light-emitting unit512, and the charge generation layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a droplet discharge method (also referred to as an ink-jet method), a coating method, or a gravure printing method. A low molecular material, a middle molecular material (including an oligomer and a dendrimer), or a high molecular material may be included in the layers and electrodes. Embodiment 3 In this embodiment, a light-emitting apparatus including the light-emitting device described in Embodiments 1 and 2 will be described. In this embodiment, the light-emitting apparatus manufactured using the light-emitting device described in Embodiments 1 and 2 is described with reference toFIGS.2A and2B. Note thatFIG.2Ais a top view of the light-emitting apparatus andFIG.2Bis a cross-sectional view taken along the lines A-B and C-D inFIG.2A. This light-emitting apparatus includes a driver circuit portion (source line driver circuit)601, a pixel portion602, and a driver circuit portion (gate line driver circuit)603, which are to control the light emission of a light-emitting device and illustrated with dotted lines. A reference numeral604denotes a sealing substrate;605, a sealing material; and607, a space surrounded by the sealing material605. A lead wiring608is a wiring for transmitting signals to be input to the source line driver circuit601and the gate line driver circuit603and receiving signals such as a video signal, a clock signal, a start signal, and a reset signal from a flexible printed circuit (FPC)609serving as an external input terminal. Although only the FPC is illustrated here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting apparatus in the present specification includes, in its category, not only the light-emitting apparatus itself but also the light-emitting apparatus provided with the FPC or the PWB. Next, a cross-sectional structure is described with reference toFIG.2B. The driver circuit portions and the pixel portion are formed over an element substrate610. Here, the source line driver circuit601, which is a driver circuit portion, and one pixel in the pixel portion602are illustrated. The element substrate610may be a substrate containing glass, quartz, an organic resin, a metal, an alloy, or a semiconductor or a plastic substrate formed of fiber reinforced plastic (FRP), polyvinyl fluoride (PVF), polyester, or acrylic. The structure of transistors used in pixels and driver circuits is not particularly limited. For example, inverted staggered transistors may be used, or staggered transistors may be used. Furthermore, top-gate transistors or bottom-gate transistors may be used. A semiconductor material used for the transistors is not particularly limited, and for example, silicon, germanium, silicon carbide, gallium nitride, or the like can be used. Alternatively, an oxide semiconductor containing at least one of indium, gallium, and zinc, such as an In—Ga—Zn-based metal oxide, may be used. There is no particular limitation on the crystallinity of a semiconductor material used for the transistors, and an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partly including crystal regions) may be used. It is preferable that a semiconductor having crystallinity be used, in which case degradation of the transistor characteristics can be suppressed. Here, an oxide semiconductor is preferably used for semiconductor devices such as the transistors provided in the pixels and driver circuits and transistors used for touch sensors described later, and the like. In particular, an oxide semiconductor having a wider band gap than silicon is preferably used. When an oxide semiconductor having a wider band gap than silicon is used, the off-state current of the transistors can be reduced. The oxide semiconductor preferably includes at least indium (In) or zinc (Zn). Further preferably, the oxide semiconductor includes an oxide represented by an In-M-Zn-based oxide (M represents a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). An oxide semiconductor that can be used in one embodiment of the present invention is described below. An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. The CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where the nanocrystals are connected. The shape of the nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that it is difficult to observe a clear grain boundary even in the vicinity of distortion in the CAAC-OS. That is, a lattice arrangement is distorted and thus formation of a grain boundary is inhibited. This is because the CAAC-OS can tolerate distortion owing to a low density of oxygen atom arrangement in the a-b plane direction, a change in interatomic bond distance by substitution of a metal element, and the like. The CAAC-OS tends to have a layered crystal structure (also referred to as a stacked-layer structure) in which a layer containing indium and oxygen (hereinafter an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter an (M, Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, the layer can be referred to as an (In, M, Zn) layer. When indium of the In layer is replaced with the element M, the layer can be referred to as an (In, M) layer. The CAAC-OS is an oxide semiconductor with high crystallinity. By contrast, in the CAAC-OS, a reduction in electron mobility due to a grain boundary is less likely to occur because it is difficult to observe a clear grain boundary. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS is an oxide semiconductor having small amounts of impurities and defects (e.g., oxygen vacancies (also referred to as Vo)). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Accordingly, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. Note that an indium-gallium-zinc oxide (hereinafter IGZO) that is an oxide semiconductor containing indium, gallium, and zinc has a stable structure in some cases by being formed of the above-described nanocrystals. In particular, IGZO crystals tend not to grow in the air and thus, a stable structure is obtained when IGZO is formed of smaller crystals (e.g., the above-described nanocrystals) rather than larger crystals (here, crystals with a size of several millimeters or several centimeters). The a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS. An oxide semiconductor can have any of various structures that show various different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention. A cloud-aligned composite OS (CAC-OS) may be used as an oxide semiconductor other than the above. A CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Note that in the case where the CAC-OS is used in a semiconductor layer of a transistor, the conducting function is to allow electrons (or holes) serving as carriers to flow, and the insulating function is to not allow electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, a switching function (On/Off function) can be given to the CAC-OS. In the CAC-OS, separation of the functions can maximize each function. Furthermore, the CAC-OS includes conductive regions and insulating regions. The conductive regions have the above-described conducting function, and the insulating regions have the above-described insulating function. Furthermore, in some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. Furthermore, in some cases, the conductive regions and the insulating regions are unevenly distributed in the material. Furthermore, the conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred, in some cases. Furthermore, in the CAC-OS, the conductive regions and the insulating regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm, and are dispersed in the material, in some cases. Furthermore, the CAC-OS includes components having different bandgaps. For example, the CAC-OS includes a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of the structure, when carriers flow, carriers mainly flow in the component having a narrow gap. Furthermore, the component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, high current driving capability in an on state of the transistor, that is, a high on-state current and high field-effect mobility can be obtained. In other words, the CAC-OS can also be referred to as a matrix composite or a metal matrix composite. The use of the above-described oxide semiconductor materials for the semiconductor layer makes it possible to provide a highly reliable transistor in which a change in the electrical characteristics is suppressed. Charge accumulated in a capacitor through a transistor including the above-described semiconductor layer can be held for a long time because of the low off-state current of the transistor. When such a transistor is used in a pixel, operation of a driver circuit can be stopped while a gray scale of an image displayed in each display region is maintained. As a result, an electronic device with extremely low power consumption can be obtained. For stable characteristics or the like of the transistor, a base film is preferably provided. The base film can be formed with a single-layer structure or a stacked-layer structure using an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. The base film can be formed by a sputtering method, a chemical vapor deposition (CVD) method (e.g., a plasma CVD method, a thermal CVD method, or a metal organic CVD (MOCVD) method), an atomic layer deposition (ALD) method, a coating method, a printing method, or the like. Note that the base film is not necessarily provided. Note that an FET623is illustrated as a transistor formed in the driver circuit portion601. In addition, the driver circuit may be formed with any of a variety of circuits such as a CMOS circuit, a PMOS circuit, or an NMOS circuit. Although a driver integrated type in which the driver circuit is formed over the substrate is illustrated in this embodiment, the driver circuit is not necessarily formed over the substrate, and the driver circuit can be formed outside the substrate. The pixel portion602includes a plurality of pixels including a switching FET611, a current controlling FET612, and an anode613electrically connected to a drain of the current controlling FET612. One embodiment of the present invention is not limited to the structure. The pixel portion602may include three or more FETs and a capacitor in combination. Note that to cover an end portion of the anode613, an insulator614is formed. Here, the insulator614can be formed using positive photosensitive acrylic here. In order to improve the coverage with an EL layer or the like which is formed later, the insulator614is formed to have a curved surface with curvature at its upper or lower end portion. For example, in the case where positive photosensitive acrylic is used as a material of the insulator614, only the upper end portion of the insulator614preferably has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator614, either a negative photosensitive resin or a positive photosensitive resin can be used. An EL layer616and a cathode617are formed over the anode613. Here, as a material used for the anode613, a material having a high work function is desirably used. For example, a single-layer film of an ITO film, an indium tin oxide film containing silicon, an indium oxide film containing zinc oxide at 2 wt % to 20 wt %, a titanium nitride film, a chromium film, a tungsten film, a Zn film, a Pt film, or the like, a stack of a titanium nitride film and a film containing aluminum as its main component, a stack of three layers of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film, or the like can be used. The stacked-layer structure enables low wiring resistance and favorable ohmic contact, and can function as an anode. The EL layer616is formed by any of a variety of methods such as an evaporation method using an evaporation mask, an inkjet method, and a spin coating method. The EL layer616has the structure described in Embodiments 1 and 2. As another material included in the EL layer616, a low molecular compound or a high molecular compound (including an oligomer or a dendrimer) may be used. As a material used for the cathode617, which is formed over the EL layer616, a material having a low work function (e.g., Al, Mg, Li, and Ca, or an alloy or a compound thereof, such as MgAg, MgIn, or AlLi) is preferably used. In the case where light generated in the EL layer616is transmitted through the cathode617, a stack of a thin metal film and a transparent conductive film (e.g., ITO, indium oxide containing zinc oxide at 2 wt % to 20 wt %, indium tin oxide containing silicon, or zinc oxide (ZnO)) is preferably used for the cathode617. Note that the light-emitting device is formed with the anode613, the EL layer616, and the cathode617. The light-emitting device is the light-emitting device described in Embodiments 1 and 2. In the light-emitting apparatus of this embodiment, the pixel portion, which includes a plurality of light-emitting devices, may include both the light-emitting device described in Embodiments 1 and 2 and a light-emitting device having a different structure. The sealing substrate604is attached to the element substrate610with the sealing material605, so that a light-emitting device618is provided in the space607surrounded by the element substrate610, the sealing substrate604, and the sealing material605. The space607may be filled with a filler, or may be filled with an inert gas (such as nitrogen or argon), or the sealing material. It is preferable that the sealing substrate be provided with a recessed portion and a drying agent be provided in the recessed portion, in which case degradation due to influence of moisture can be suppressed. An epoxy-based resin or glass frit is preferably used for the sealing material605. It is desirable that such a material not be permeable to moisture or oxygen as much as possible. As the sealing substrate604, a glass substrate, a quartz substrate, or a plastic substrate formed of fiber reinforced plastic (FRP), polyvinyl fluoride (PVF), polyester, or acrylic can be used. Although not illustrated inFIGS.2A and2B, a protective film may be provided over the cathode. As the protective film, an organic resin film or an inorganic insulating film may be formed. The protective film may be formed so as to cover an exposed portion of the sealing material605. The protective film may be provided so as to cover surfaces and side surfaces of the pair of substrates and exposed side surfaces of a sealing layer, an insulating layer, and the like. The protective film can be formed using a material through which an impurity such as water does not permeate easily. Thus, diffusion of an impurity such as water from the outside into the inside can be effectively suppressed. As a material of the protective film, an oxide, a nitride, a fluoride, a sulfide, a ternary compound, a metal, a polymer, or the like can be used. For example, the material may contain aluminum oxide, hafnium oxide, hafnium silicate, lanthanum oxide, silicon oxide, strontium titanate, tantalum oxide, titanium oxide, zinc oxide, niobium oxide, zirconium oxide, tin oxide, yttrium oxide, cerium oxide, scandium oxide, erbium oxide, vanadium oxide, indium oxide, aluminum nitride, hafnium nitride, silicon nitride, tantalum nitride, titanium nitride, niobium nitride, molybdenum nitride, zirconium nitride, gallium nitride, a nitride containing titanium and aluminum, an oxide containing titanium and aluminum, an oxide containing aluminum and zinc, a sulfide containing manganese and zinc, a sulfide containing cerium and strontium, an oxide containing erbium and aluminum, an oxide containing yttrium and zirconium, or the like. The protective film is preferably formed using a deposition method with favorable step coverage. One such method is an atomic layer deposition (ALD) method. A material that can be deposited by an ALD method is preferably used for the protective film. A dense protective film having reduced defects such as cracks or pinholes or a uniform thickness can be formed by an ALD method. Furthermore, damage caused to a process member in forming the protective film can be reduced. By an ALD method, a uniform protective film with few defects can be formed even on a surface with a complex uneven shape or upper, side, and lower surfaces of a touch panel. As described above, the light-emitting apparatus manufactured using the light-emitting device described in Embodiments 1 and 2 can be obtained. The light-emitting apparatus in this embodiment is manufactured using the light-emitting device described in Embodiments 1 and 2 and thus can have favorable characteristics. Specifically, since the light-emitting device described in Embodiments 1 and 2 has a long lifetime, the light-emitting apparatus can have high reliability. Since the light-emitting apparatus using the light-emitting device described in Embodiments 1 and 2 has high emission efficiency, the light-emitting apparatus can achieve low power consumption. FIGS.3A and3Beach illustrate an example of a light-emitting apparatus in which full color display is achieved by formation of a light-emitting device exhibiting white light emission and with the use of coloring layers (color filters) and the like.FIG.3Aillustrates a substrate1001, a base insulating film1002, a gate insulating film1003, gate electrodes1006,1007, and1008, a first interlayer insulating film1020, a second interlayer insulating film1021, a peripheral portion1042, a pixel portion1040, a driver circuit portion1041, anodes1024W,1024R,1024G, and1024B of light-emitting devices, a partition1025, an EL layer1028, a cathode1029of the light-emitting devices, a sealing substrate1031, a sealing material1032, and the like. InFIG.3A, coloring layers (a red coloring layer1034R, a green coloring layer1034G, and a blue coloring layer1034B) are provided on a transparent base material1033. A black matrix1035may be additionally provided. The transparent base material1033provided with the coloring layers and the black matrix is aligned and fixed to the substrate1001. Note that the coloring layers and the black matrix1035are covered with an overcoat layer1036. InFIG.3A, light emitted from part of the light-emitting layer does not pass through the coloring layers, while light emitted from the other part of the light-emitting layer passes through the coloring layers. The light that does not pass through the coloring layers is white and the light that passes through any one of the coloring layers is red, green, or blue; thus, an image can be displayed using pixels of the four colors. FIG.3Billustrates an example in which the coloring layers (the red coloring layer1034R, the green coloring layer1034G, and the blue coloring layer1034B) are provided between the gate insulating film1003and the first interlayer insulating film1020. As in the structure, the coloring layers may be provided between the substrate1001and the sealing substrate1031. The above-described light-emitting apparatus is a light-emitting apparatus having a structure in which light is extracted from the substrate1001side where FETs are formed (a bottom emission structure), but may be a light-emitting apparatus having a structure in which light is extracted from the sealing substrate1031side (a top emission structure).FIG.4is a cross-sectional view of a light-emitting apparatus having a top emission structure. In this case, a substrate that does not transmit light can be used as the substrate1001. The process up to the step of forming a connection electrode which connects the FET and the anode of the light-emitting device is performed in a manner similar to that of the light-emitting apparatus having a bottom emission structure. Then, a third interlayer insulating film1037is formed to cover an electrode1022. This insulating film may have a planarization function. The third interlayer insulating film1037can be formed using a material similar to that of the second interlayer insulating film, and can alternatively be formed using any of other known materials. The anodes1024W,1024R,1024G, and1024B of the light-emitting devices are each an anode here, but may be formed as a cathode. Furthermore, in the case of a light-emitting apparatus having a top emission structure as illustrated inFIG.4, the anodes are preferably reflective electrodes. The EL layer1028is formed to have a structure similar to the structure of the EL layer103described in Embodiments 1 and 2, with which white light emission can be obtained. In the case of a top emission structure as illustrated inFIG.4, sealing can be performed with the sealing substrate1031on which the coloring layers (the red coloring layer1034R, the green coloring layer1034G, and the blue coloring layer1034B) are provided. The sealing substrate1031may be provided with the black matrix1035which is positioned between pixels. The coloring layers (the red coloring layer1034R, the green coloring layer1034G, and the blue coloring layer1034B) and the black matrix may be covered with the overcoat layer1036. Note that a light-transmitting substrate is used as the sealing substrate1031. Although an example in which full color display is performed using four colors of red, green, blue, and white is shown here, there is no particular limitation and full color display using four colors of red, yellow, green, and blue or three colors of red, green, and blue may be performed. In the light-emitting apparatus having a top emission structure, a microcavity structure can be favorably employed. A light-emitting device with a microcavity structure is formed with the use of a reflective electrode as the anode and a semi-transmissive and semi-reflective electrode as the cathode. The light-emitting device with a microcavity structure includes at least an EL layer between the reflective electrode and the semi-transmissive and semi-reflective electrode, which includes at least a light-emitting layer serving as a light-emitting region. Note that the reflective electrode has a visible light reflectivity of 40% to 100%, preferably 70% to 100%, and a resistivity of 1×10−2Ωcm or lower. In addition, the semi-transmissive and semi-reflective electrode has a visible light reflectivity of 20% to 80%, preferably 40% to 70%, and a resistivity of 1×10−2Ωcm or lower. Light emitted from the light-emitting layer included in the EL layer is reflected and resonated by the reflective electrode and the semi-transmissive and semi-reflective electrode. In the light-emitting device, by changing thicknesses of the transparent conductive film, the composite material, the carrier-transport material, and the like, the optical path length between the reflective electrode and the semi-transmissive and semi-reflective electrode can be changed. Thus, light with a wavelength that is resonated between the reflective electrode and the semi-transmissive and semi-reflective electrode can be intensified while light with a wavelength that is not resonated therebetween can be attenuated. Note that light that is reflected back by the reflective electrode (first reflected light) considerably interferes with light that directly enters the semi-transmissive and semi-reflective electrode from the light-emitting layer (first incident light). For this reason, the optical path length between the reflective electrode and the light-emitting layer is preferably adjusted to (2n−1)λ/4 (n is a natural number of 1 or larger and λ is a wavelength of color to be amplified). By adjusting the optical path length, the phases of the first reflected light and the first incident light can be aligned with each other and the light emitted from the light-emitting layer can be further amplified. Note that in the above structure, the EL layer may include a plurality of light-emitting layers or may include a single light-emitting layer. The tandem light-emitting device described above may be combined with a plurality of EL layers; for example, a light-emitting device may have a structure in which a plurality of EL layers are provided, a charge generation layer is provided between the EL layers, and each EL layer includes a plurality of light-emitting layers or a single light-emitting layer. With the microcavity structure, emission intensity with a specific wavelength in the front direction can be increased, whereby power consumption can be reduced. Note that in the case of a light-emitting apparatus which displays images with subpixels of four colors, red, yellow, green, and blue, the light-emitting apparatus can have favorable characteristics because the luminance can be increased owing to yellow light emission and each subpixel can employ a microcavity structure suitable for wavelengths of the corresponding color. The light-emitting apparatus in this embodiment is manufactured using the light-emitting device described in Embodiments 1 and 2 and thus can have favorable characteristics. Specifically, since the light-emitting device described in Embodiments 1 and 2 has a long lifetime, the light-emitting apparatus can have high reliability. Since the light-emitting apparatus using the light-emitting device described in Embodiments 1 and 2 has high emission efficiency, the light-emitting apparatus can achieve low power consumption. The active matrix light-emitting apparatus is described above, whereas a passive matrix light-emitting apparatus is described below.FIGS.5A and5Billustrate a passive matrix light-emitting apparatus manufactured using the present invention. Note thatFIG.5Ais a perspective view of the light-emitting apparatus, andFIG.5Bis a cross-sectional view taken along the line X-Y inFIG.5A. InFIGS.5A and5B, over a substrate951, an EL layer955is provided between an electrode952and an electrode956. An end portion of the electrode952is covered with an insulating layer953. A partition layer954is provided over the insulating layer953. The sidewalls of the partition layer954are aslope such that the distance between both sidewalls is gradually narrowed toward the surface of the substrate. In other words, a cross section taken along the direction of the short side of the partition layer954is trapezoidal, and the lower side (a side of the trapezoid that is parallel to the surface of the insulating layer953and is in contact with the insulating layer953) is shorter than the upper side (a side of the trapezoid that is parallel to the surface of the insulating layer953and is not in contact with the insulating layer953). The partition layer954thus provided can prevent defects in the light-emitting device due to static electricity or others. The passive-matrix light-emitting apparatus also includes the light-emitting device described in Embodiments 1 and 2; thus, the light-emitting apparatus can have high reliability or low power consumption. Since many minute light-emitting devices arranged in a matrix in the light-emitting apparatus described above can each be controlled, the light-emitting apparatus can be suitably used as a display device for displaying images. This embodiment can be freely combined with any of the other embodiments. Embodiment 4 In this embodiment, an example in which the light-emitting device described in Embodiments 1 and 2 is used for a lighting device will be described with reference toFIGS.6A and6B.FIG.6Bis a top view of the lighting device, andFIG.6Ais a cross-sectional view taken along the line e-f inFIG.6B. In the lighting device in this embodiment, an anode401is formed over a substrate400which is a support and has a light-transmitting property. The anode401corresponds to the anode101in Embodiment 2. When light is extracted through the anode401side, the anode401is formed using a material having a light-transmitting property. A pad412for applying voltage to a cathode404is formed over the substrate400. An EL layer403is formed over the anode401. The structure of the EL layer403corresponds to, for example, the structure of the EL layer103in Embodiments 1 and 2, or the structure in which the light-emitting units511and512and the charge generation layer513are combined. Refer to the descriptions for the structure. The cathode404is formed to cover the EL layer403. The cathode404corresponds to the cathode102in Embodiment 2. The cathode404is formed using a material having high reflectance when light is extracted through the anode401side. The cathode404is connected to the pad412, whereby voltage is applied. As described above, the lighting device described in this embodiment includes a light-emitting device including the anode401, the EL layer403, and the cathode404. Since the light-emitting device is a light-emitting device with high emission efficiency, the lighting device in this embodiment can be a lighting device having low power consumption. The substrate400provided with a light-emitting device having the above structure is fixed to a sealing substrate407with sealing materials405and406and sealing is performed, whereby the lighting device is completed. It is possible to use only either the sealing material405or the sealing material406. The inner sealing material406(not shown inFIG.6B) can be mixed with a desiccant which enables moisture to be adsorbed, increasing reliability. When parts of the pad412and the anode401are extended to the outside of the sealing materials405and406, the extended parts can function as external input terminals. An IC chip420mounted with a converter or the like may be provided over the external input terminals. The lighting device described in this embodiment includes as an EL element the light-emitting device described in Embodiments 1 and 2; thus, the light-emitting apparatus can have high reliability at high temperature. In addition, the light-emitting apparatus can consume less power. Embodiment 5 In this embodiment, examples of electronic devices each including the light-emitting device described in Embodiments 1 and 2 will be described. The light-emitting device described in Embodiments 1 and 2 has a long lifetime and high reliability at high temperature. As a result, the electronic devices described in this embodiment can each include a light-emitting portion having high reliability at high temperature. Examples of the electronic device including the above light-emitting device include television devices (also referred to as TV or television receivers), monitors for computers and the like, digital cameras, digital video cameras, digital photo frames, cellular phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. Specific examples of these electronic devices are shown below. FIG.7Aillustrates an example of a television device. In the television device, a display portion7103is incorporated in a housing7101. Here, the housing7101is supported by a stand7105. Images can be displayed on the display portion7103, and in the display portion7103, the light-emitting devices described in Embodiments 1 and 2 are arranged in a matrix. The television device can be operated with an operation switch of the housing7101or a separate remote controller7110. With operation keys7109of the remote controller7110, channels and volume can be controlled and images displayed on the display portion7103can be controlled. Furthermore, the remote controller7110may be provided with a display portion7107for displaying data output from the remote controller7110. Note that the television device is provided with a receiver, a modem, and the like. With the use of the receiver, a general television broadcast can be received. Moreover, when the television device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) data communication can be performed. FIG.7B1illustrates a computer, which includes a main body7201, a housing7202, a display portion7203, a keyboard7204, an external connection port7205, a pointing device7206, and the like. Note that this computer is manufactured using the light-emitting devices described in Embodiments 1 and 2 and arranged in a matrix in the display portion7203. The computer illustrated in FIG.7B1may have a structure illustrated in FIG.7B2. A computer illustrated in FIG.7B2is provided with a second display portion7210instead of the keyboard7204and the pointing device7206. The second display portion7210is a touch panel, and input operation can be performed by touching display for input on the second display portion7210with a finger or a dedicated pen. The second display portion7210can also display images other than the display for input. The display portion7203may also be a touch panel. Connecting the two screens with a hinge can prevent troubles; for example, the screens can be prevented from being cracked or broken while the computer is being stored or carried. FIG.7Cillustrates an example of a portable terminal. A cellular phone is provided with a display portion7402incorporated in a housing7401, operation buttons7403, an external connection port7404, a speaker7405, a microphone7406, and the like. Note that the cellular phone has the display portion7402including the light-emitting devices described in Embodiments 1 and 2 and arranged in a matrix. When the display portion7402of the portable terminal illustrated inFIG.7Cis touched with a finger or the like, data can be input into the portable terminal. In this case, operations such as making a call and creating an e-mail can be performed by touching the display portion7402with a finger or the like. The display portion7402has mainly three screen modes. The first mode is a display mode mainly for displaying images. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which the two modes, the display mode and the input mode, are combined. For example, in the case of making a call or creating an e-mail, a text input mode mainly for inputting text is selected for the display portion7402so that text displayed on the screen can be input. In this case, it is preferable to display a keyboard or number buttons on almost the entire screen of the display portion7402. When a sensing device including a sensor such as a gyroscope or an acceleration sensor for detecting inclination is provided inside the portable terminal, display on the screen of the display portion7402can be automatically changed in direction by determining the orientation of the portable terminal (whether the portable terminal is placed horizontally or vertically). The screen modes are switched by touching the display portion7402or operating the operation buttons7403of the housing7401. Alternatively, the screen modes can be switched depending on the kind of images displayed on the display portion7402. For example, when a signal of an image displayed on the display portion is a signal of moving image data, the screen mode is switched to the display mode. When the signal is a signal of text data, the screen mode is switched to the input mode. Moreover, in the input mode, when input by touching the display portion7402is not performed for a certain period while a signal sensed by an optical sensor in the display portion7402is sensed, the screen mode may be controlled so as to be switched from the input mode to the display mode. The display portion7402may also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when the display portion7402is touched with the palm or the finger, whereby personal authentication can be performed. Furthermore, by providing a backlight or a sensing light source which emits near-infrared light in the display portion, an image of a finger vein, a palm vein, or the like can be taken. Note that the structure described in this embodiment can be combined with any of the structures described in Embodiments 1 to 4 as appropriate. As described above, the application range of the light-emitting apparatus having the light-emitting device described in Embodiments 1 and 2 is wide so that this light-emitting apparatus can be applied to electronic devices in a variety of fields. By using the light-emitting device described in Embodiments 1 and 2, an electronic device with high reliability at high temperature can be obtained. FIG.8Ais a schematic view illustrating an example of a cleaning robot. A cleaning robot5100includes a display5101on its top surface, a plurality of cameras5102on its side surface, a brush5103, and operation buttons5104. Although not illustrated, the bottom surface of the cleaning robot5100is provided with a tire, an inlet, and the like. Furthermore, the cleaning robot5100includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezoelectric sensor, an optical sensor, and a gyroscope sensor. The cleaning robot5100has a wireless communication means. The cleaning robot5100is self-propelled, detects dust5120, and sucks up the dust through the inlet provided on the bottom surface. The cleaning robot5100can determine whether there is an obstacle such as a wall, furniture, or a step by analyzing images taken by the cameras5102. When the cleaning robot5100detects an object that is likely to be caught in the brush5103(e.g., a wire) by image analysis, the rotation of the brush5103can be stopped. The display5101can display the remaining capacity of a battery, the amount of collected dust, and the like. The display5101may display a path on which the cleaning robot5100has run. The display5101may be a touch panel, and the operation buttons5104may be provided on the display5101. The cleaning robot5100can communicate with a portable electronic device5140such as a smartphone. The portable electronic device5140can display images taken by the cameras5102. Accordingly, an owner of the cleaning robot5100can monitor his/her room even when the owner is not at home. The owner can also check the display on the display5101by the portable electronic device5140such as a smartphone. The light-emitting apparatus of one embodiment of the present invention can be used for the display5101. A robot2100illustrated inFIG.8Bincludes an arithmetic device2110, an illuminance sensor2101, a microphone2102, an upper camera2103, a speaker2104, a display2105, a lower camera2106, an obstacle sensor2107, and a moving mechanism2108. The microphone2102has a function of detecting a speaking voice of a user, an environmental sound, and the like. The speaker2104also has a function of outputting sound. The robot2100can communicate with a user using the microphone2102and the speaker2104. The display2105has a function of displaying various kinds of information. The robot2100can display information desired by a user on the display2105. The display2105may be provided with a touch panel. Moreover, the display2105may be a detachable information terminal, in which case charging and data communication can be performed when the display2105is set at the home position of the robot2100. The upper camera2103and the lower camera2106each have a function of taking an image of the surroundings of the robot2100. The obstacle sensor2107can detect an obstacle in the direction where the robot2100advances with the moving mechanism2108. The robot2100can move safely by recognizing the surroundings with the upper camera2103, the lower camera2106, and the obstacle sensor2107. The light-emitting apparatus of one embodiment of the present invention can be used for the display2105. FIG.8Cillustrates an example of a goggle-type display. The goggle-type display includes, for example, a housing5000, a display portion5001, a speaker5003, an LED lamp5004, a connection terminal5006, a sensor5007(a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared ray), a microphone5008, a display portion5002, a support5012, and an earphone5013. The light-emitting apparatus of one embodiment of the present invention can be used for the display portion5001and the display portion5002. FIG.9illustrates an example in which the light-emitting device described in Embodiments 1 and 2 is used for a table lamp which is a lighting device. The table lamp illustrated inFIG.9includes a housing2001and a light source2002, and the lighting device described in Embodiment 3 may be used for the light source2002. FIG.10illustrates an example in which the light-emitting device described in Embodiments 1 and 2 is used for an indoor lighting device3001. Since the light-emitting device described in Embodiments 1 and 2 has high reliability at high temperature, the lighting device can have high reliability at high temperature. Furthermore, since the light-emitting device described in Embodiments 1 and 2 can have a large area, the light-emitting device can be used for a large-area lighting device. Furthermore, since the light-emitting device described in Embodiments 1 and 2 is thin, the light-emitting device can be used for a lighting device having a reduced thickness. The light-emitting device described in Embodiments 1 and 2 can also be used for an automobile windshield or an automobile dashboard.FIG.11illustrates one mode in which the light-emitting devices described in Embodiments 1 and 2 are used for an automobile windshield and an automobile dashboard. Display regions5200to5203each include the light-emitting device described in Embodiments 1 and 2. The display regions5200and5201are display devices which are provided in the automobile windshield and in which light-emitting devices each of which is described in Embodiments 1 and 2 are incorporated. The light-emitting devices described in Embodiments 1 and 2 can be formed into what is called a see-through light-emitting device, through which the opposite side can be seen, by including an anode and a cathode formed of electrodes having a light-transmitting property. Such see-through display devices can be provided even in the automobile windshield without hindering the view. In the case where a driving transistor or the like is provided, a transistor having a light-transmitting property, such as an organic transistor including an organic semiconductor material or a transistor including an oxide semiconductor, is preferably used. A display device incorporating the light-emitting device described in Embodiments 1 and 2 is provided in the display region5202in a pillar portion. The display region5202can compensate for the view hindered by the pillar by displaying an image taken by an imaging unit provided in the car body. Similarly, the display region5203provided in the dashboard portion can compensate for the view hindered by the car body by displaying an image taken by an imaging unit provided on the outside of the automobile. Thus, blind areas can be eliminated to enhance the safety. Images that compensate for the areas which a driver cannot see enable the driver to ensure safety easily and comfortably. The display region5203can provide various kinds of information by displaying navigation data, a speedometer, a tachometer, and other various kinds of information. The content or layout of the display can be changed freely by a user as appropriate. Note that such information can also be displayed on the display regions5200to5202. The display regions5200to5203can also be used as lighting devices. FIGS.12A and12Billustrate a foldable portable information terminal5150. The foldable portable information terminal5150includes a housing5151, a display region5152, and a bend portion5153.FIG.12Aillustrates the portable information terminal5150that is opened.FIG.12Billustrates the portable information terminal5150that is folded. Despite its large display region5152, the portable information terminal5150is compact in size and has excellent portability when folded. The display region5152can be folded in half with the bend portion5153. The bend portion5153includes a flexible member and a plurality of supporting members. When the display region is folded, the flexible member expands and the bend portion5153has a radius of curvature of greater than or equal to 2 mm, preferably greater than or equal to 3 mm. Note that the display region5152may be a touch panel (an input/output device) including a touch sensor (an input device). The light-emitting apparatus of one embodiment of the present invention can be used for the display region5152. FIGS.13A to13Cillustrate a foldable portable information terminal9310.FIG.13Aillustrates the portable information terminal9310that is opened.FIG.13Billustrates the portable information terminal9310that is being opened or being folded.FIG.13Cillustrates the portable information terminal9310that is folded. The portable information terminal9310is highly browsable when opened because of a seamless large display region. A display panel9311is supported by three housings9315joined together by hinges9313. Note that the display panel9311may be a touch panel (an input/output device) including a touch sensor (an input device). By folding the display panel9311at the hinges9313between two housings9315, the portable information terminal9310can be reversibly changed in shape from the opened state to the folded state. The light-emitting apparatus of one embodiment of the present invention can be used for the display panel9311. Example 1 In this example, a light-emitting device1of one embodiment of the present invention and a comparative light-emitting device1are described. Structural formulae of organic compounds used for the light-emitting device1and the comparative light-emitting device1are shown below. (Method of Fabricating Light-Emitting Device1) First, indium tin oxide containing silicon oxide (ITSO) was deposited over a glass substrate by a sputtering method to form the anode101. The thickness of the anode101was 70 nm and the electrode area was 2 mm×2 mm. Next, in pretreatment for forming the light-emitting device over a substrate, a surface of the substrate was washed with water and baked at 200° C. for 1 hour, and then UV ozone treatment was performed for 370 seconds. After that, the substrate was transferred into a vacuum evaporation apparatus where the pressure was reduced to approximately 10−4Pa, vacuum baking was performed at 170° C. for 30 minutes in a heating chamber of the vacuum evaporation apparatus, and then the substrate was cooled down for approximately 30 minutes. Next, the substrate provided with the anode101was fixed to a substrate holder provided in the vacuum evaporation apparatus such that the surface on which the anode101was formed faced downward. Then, N-(1,1′-biphenyl-4-yl)-N-[4-(9-phenyl-9H-carbazol-3-yl)phenyl]-9,9-dimethyl-9H-fluoren-2-amine (abbreviation: PCBBiF) represented by Structural Formula (i) and ALD-MP001Q (produced by Analysis Atelier Corporation, material serial No. 1S20170124) were co-evaporated to a thickness of 10 nm on the anode101using a resistance-heating method such that the weight ratio of PCBBiF to ALD-MP001Q was 1:0.1, whereby the hole-injection layer111was formed. Subsequently, over the hole-injection layer111, PCBBiF was evaporated to a thickness of 20 nm to form the first hole-transport layer112-1, and then N,N-bis[4-(dibenzofuran-4-yl)phenyl]-4-amino-p-terphenyl (abbreviation: DBfBB1TP) represented by Structural Formula (ii) was evaporated to a thickness of 10 nm to form the second hole-transport layer112-2, whereby the hole-transport layer112was formed. Note that the second hole-transport layer112-2also functions as an electron-blocking layer. Then, 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA) represented by Structural Formula (iii) and 3,10-bis[N-(9-phenyl-9H-carbazol-2-yl)-N-phenylamino]naphtho[2,3-b;6,7-b′]bisbenzofuran (abbreviation: 3,10PCA2Nbf(IV)-02) represented by Structural Formula (iv) were co-evaporated to a thickness of 25 nm such that the weight ratio of cgDBCzPA to 3,10PCA2Nbf(IV)-02 was 1:0.015, whereby the light-emitting layer113was formed. Then, over the light-emitting layer113, 2-[3′-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II) represented by Structural Formula (v) was evaporated to a thickness of 15 nm, and subsequently 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen) represented by Structural Formula (vi) was evaporated to a thickness of 10 nm, whereby the electron-transport layer114was formed. After the formation of the electron-transport layer114, lithium fluoride (LiF) was evaporated to a thickness of 1 nm to form the electron-injection layer115. Then, aluminum was evaporated to a thickness of 200 nm to form the cathode102. Thus, the light-emitting device1of this example was fabricated. (Method of Fabricating Comparative Light-Emitting Device1) The comparative light-emitting device1was fabricated in a manner similar to that for the light-emitting device1except that 9-(1-naphthyl)-10-[4-(2-naphthyl)phenyl]anthracene (abbreviation: αN-βNPAnth) represented by Structural Formula (vii) was used instead of cgDBCzPA of the light-emitting device1. The device structures of the light-emitting device1and the comparative light-emitting device1are listed in the following table. TABLE 1Hole-Hole-transportLight-Electron-injectionlayeremittinginjectionlayer12layerElectron-transport layerlayer10 nm20 nm10 nm25 nm15 nm10 nm1 nmLight-emittingPCBBiF:PCBBiFDBfBB1TP*12mDBTBPDBq-IINBPhenLiFdevice 1ALD-ComparativeMP001Q*2light-emitting(1:0.1)device 1*1 cgDBCzPA: 3, 10PCA2Nbf(IV)-02 (1:0.015)*2 αN-βNPAnth: 3, 10PCA2Nbf(IV)-02 (1:0.015) The HOMO levels of the organic compounds used in this example are listed in the following table. TABLE 2HOMO level (eV)PCBBiF−5.36DBfBB1TP−5.50cgDBCzPA−5.69αN-βNPAnth−5.85 The light-emitting device was sealed using a glass substrate in a glove box containing a nitrogen atmosphere so as not to be exposed to the air (a sealing material was applied to surround the element and UV treatment and heat treatment at 80° C. for 1 hour were performed at the time of sealing). Then, the initial characteristics and reliability of the light-emitting device were measured. Note that the measurement was performed at room temperature. FIG.14shows the luminance-current density characteristics of the light-emitting device1.FIG.15shows the current efficiency-luminance characteristics thereof.FIG.16shows the luminance-voltage characteristics thereof.FIG.17shows the current-voltage characteristics thereof.FIG.18shows the power efficiency-luminance characteristics thereof.FIG.19shows the external quantum efficiency-luminance characteristics thereof.FIG.20shows the emission spectrum thereof. Table 3 shows the main characteristics of the light-emitting device1at a luminance of about 1000 cd/m2. TABLE 3CurrentPowerExternalVoltageCurrentdensityChromaticityChromaticityefficiencyquantum(V)(mA)(mA/cm2)xy(lm/W)efficiency (%)Light-emitting3.10.297.10.140.1412.011.0device 1Comparative3.90.4110.30.140.118.811.7light-emittingdevice 1 FIG.14toFIG.20and Table 3 show that the light-emitting device1and the comparative light-emitting device1of one embodiment of the present invention are blue-light-emitting devices with favorable characteristics. FIG.21Ais a graph showing a change in luminance over driving time at a current density of 50 mA/cm2at a high temperature of 85° C. As shown inFIG.21A, the luminance of the light-emitting device1decreased substantially in accordance with the single exponential function, whereas the luminance of the comparative light-emitting device1decreased at high speed not in accordance with the function. FIG.21Bis a graph showing a change in luminance over driving time at a current density of 50 mA/cm2at room temperature. At room temperature, the luminances of the light-emitting device1and the comparative light-emitting device1both decreased substantially in accordance with the single exponential function with small gradients of the degradation curves. Furthermore, the luminance of the comparative light-emitting device1decreased more slowly than the light-emitting device1at room temperature, which is opposite to the results at a high temperature of 85° C. The host material in the light-emitting layer of the light-emitting device1of one embodiment of the present invention is cgDBCzPA with a HOMO level of −5.69 eV, and the material in the second hole-transport layer in contact with the light-emitting layer is DBfBB1TP with a HOMO level of −5.50 eV; thus, a difference of HOMO levels therebetween is 0.19 eV On the other hand, the host material in the light-emitting layer of the comparative light-emitting device1is αN-βNPAnth with a HOMO level of −5.85 eV, and thus a difference between HOMO levels of this material and the material in the second hole-transport layer is 0.35 eV. Here, the temperature acceleration coefficients of the light-emitting devices were compared. The temperature acceleration coefficient was calculated by dividing the elapsed time taken for the luminance to decrease to 90% of the initial luminance at room temperature (LT90(R.T.)) by the elapsed time taken for the luminance to decrease to 90% of the initial luminance at 85° C. (LT90(85 deg.)). Thus, a smaller temperature acceleration coefficient indicates smaller degradation due to high temperature during the high-temperature driving. LT90(R.T.) and LT90(85 deg.) read from inFIGS.21A and21Band the temperature acceleration coefficients of the light-emitting devices are listed in the following table. TABLE 4LT90Temperature accelerationR.T.85 deg.coefficientLight-emitting device 1288417Comparative light-emitting6084115device 1 In the case where DBfBB1TP with a shallow HOMO level was used for the second hole-transport layer112-2, the light-emitting device1using cgDBCzPA with a shallow HOMO level as a host material had a smaller temperature acceleration coefficient than the comparative light-emitting device1using αN-βNPAnth with a deep HOMO level as a host material, and was less affected by the high-temperature driving. This result shows that as the difference between HOMO levels of the host material and the material used for the second hole-transport layer is smaller, the degradation due to high temperature during the high-temperature driving is smaller. In the comparative light-emitting device1in which the difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer in contact with the light-emitting layer was greater than 0.24 eV, the luminance largely decreased at high temperature with a change in the shape of the degradation curve, which showed a possibility of degradation in a different mechanism. On the other hand, in the light-emitting device1in which the difference was less than or equal to 0.24 eV, favorable results were obtained without such an irregularity. Note that the difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer that is in contact with the light-emitting layer is further preferably less than or equal to 0.20 eV. Example 2 In this example, a light-emitting device2of one embodiment of the present invention and a comparative light-emitting device2are described. Structural formulae of organic compounds used for the light-emitting device2and the comparative light-emitting device2are shown below. (Method of Fabricating Light-Emitting Device2) First, indium tin oxide containing silicon oxide (ITSO) was deposited over a glass substrate by a sputtering method to form the anode101. The thickness of the anode101was 70 nm and the electrode area was 2 mm×2 mm. Next, in pretreatment for forming the light-emitting device over a substrate, a surface of the substrate was washed with water and baked at 200° C. for 1 hour, and then UV ozone treatment was performed for 370 seconds. After that, the substrate was transferred into a vacuum evaporation apparatus where the pressure was reduced to approximately 10−4Pa, vacuum baking was performed at 170° C. for 30 minutes in a heating chamber of the vacuum evaporation apparatus, and then the substrate was cooled down for approximately 30 minutes. Next, the substrate provided with the anode101was fixed to a substrate holder provided in the vacuum evaporation apparatus such that the side on which the anode101was formed faced downward. Then, N,N-bis(4-biphenyl)-6-phenylbenzo[b]naphtho[1,2-d]furan-8-amine (abbreviation: BBABnf) represented by Structural Formula (Viii) and ALD-MP001Q (produced by Analysis Atelier Corporation, material serial No. 1S20170124) were co-evaporated to a thickness of 10 nm on the anode101using a resistance-heating method such that the weight ratio of BBABnf to ALD-MP001Q was 1:0.1, whereby the hole-injection layer111was formed. Subsequently, over the hole-injection layer111, BBABnf was evaporated to a thickness of 30 nm to form the hole-transport layer112. Note that the hole-transport layer112also functions as an electron-blocking layer. Then, 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA) represented by Structural Formula (iii) and 3,10-bis[N-(9-phenyl-9H-carbazol-2-yl)-N-phenylamino]naphtho[2,3-b;6,7-b′]bisbenzofuran (abbreviation: 3,1PCA2Nbf(IV)-02) represented by Structural Formula (iv) were co-evaporated to a thickness of 25 nm such that the weight ratio of cgDBCzPA to 3,10PCA2Nbf(IV)-02 was 1:0.015, whereby the light-emitting layer113was formed. Then, over the light-emitting layer113, 2-[3′-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II) represented by Structural Formula (v) was evaporated to a thickness of 15 nm, and subsequently 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen) represented by Structural Formula (vi) was evaporated to a thickness of 10 nm, whereby the electron-transport layer114was formed. After the formation of the electron-transport layer114, lithium fluoride (LiF) was evaporated to a thickness of 1 nm to form the electron-injection layer115. Then, aluminum was evaporated to a thickness of 200 nm to form the cathode102. Thus, the light-emitting device2of this example was fabricated. (Method of Fabricating Comparative Light-Emitting Device2) The comparative light-emitting device2was fabricated in a manner similar to that for the light-emitting device2except that 9-(1-naphthyl)-10-[4-(2-naphthyl)phenyl]anthracene (abbreviation: αN-βNPAnth) represented by Structural Formula (vii) was used instead of cgDBCzPA of the light-emitting device2. The device structures of the light-emitting device2and the comparative light-emitting device2are listed in the following table. TABLE 5Hole-Light-Electron-Hole-injectiontransportemittinginjecionlayerlayerlayerElectron-transport layerlayer10 nm30 nm25 nm15 nm10 nm1 nmLight-emittingBBABnf:BBABnf*32mDBTBPDBq-IINBPhenLifdevice 2ALD-MP001QComparative(1:0.1)*4light-emittingdevice 2*3 cgDBCzPA: 3, 10PCA2Nbf(IV)-02 (1:0.015)*4 αN-βNPAnth: 3,10PCA2Nbf(IV)-02 (1:0.015) The HOMO levels of the organic compounds used in this example are listed in the following table. TABLE 6HOMO level (eV)BBABnf−5.56cgDBCzPA−5.69αN-βNPAnth−5.85 The light-emitting device was sealed using a glass substrate in a glove box containing a nitrogen atmosphere so as not to be exposed to the air (a sealing material was applied to surround the element and UV treatment and heat treatment at 80° C. for 1 hour were performed at the time of sealing). Then, the initial characteristics and reliability of the light-emitting device were measured. Note that the measurement was performed at room temperature. FIG.22shows the luminance-current density characteristics of the light-emitting device2.FIG.23shows the current efficiency-luminance characteristics thereof.FIG.24shows the luminance-voltage characteristics thereof.FIG.25shows the current-voltage characteristics thereof.FIG.26shows the power efficiency-luminance characteristics thereof.FIG.27shows the external quantum efficiency-luminance characteristics thereof.FIG.28shows the emission spectrum thereof. Table 7 shows the main characteristics of the light-emitting device2at a luminance of about 1000 cd/m2. TABLE 7CurentPowerExternalVoltageCurrentdensityChromaticityChromaticityefficiencyquantum(V)(mA)(mA/cm2)xy(lm/W)efficiency (%)Light-emitting3.30.4010.00.140.149.79.6device 2Comparative4.00.4711.90.14.0.117.19.7light-emittingdevice 2 FIG.22toFIG.28and Table 7 show that the light-emitting device2of one embodiment of the present invention and the comparative light-emitting device2are blue-light-emitting devices with favorable characteristics. FIG.29Ais a graph showing a change in luminance over driving time at a current density of 50 mA/cm2at the high temperature of 85° C. As shown inFIG.29A, the luminance of the light-emitting device2decreased substantially in accordance with the single exponential function, whereas the luminance of the comparative light-emitting device2decreased at high speed not in accordance with the function. FIG.29Bis a graph showing a change in luminance over driving time at a current density of 50 mA/cm2at room temperature. At room temperature, the luminance of the light-emitting device2and the comparative light-emitting device2both decreased substantially in accordance with the single exponential function with small gradients of the degradation curves. Furthermore, the luminance of the comparative light-emitting device2decreased more slowly than the light-emitting device2at room temperature, which is opposite to the results at a high temperature of 85° C. The host material in the light-emitting layer of the light-emitting device2of one embodiment of the present invention is cgDBCzPA with a HOMO level of −5.69 eV, and the material in the hole-transport layer that is in contact with the light-emitting layer is BBABnf with a HOMO level of −5.56 eV; thus, a difference therebetween is 0.13 eV On the other hand, the host material in the light-emitting layer of the comparative light-emitting device2is αN-βNPAnth with a HOMO level: −5.85 eV), and thus a difference between HOMO levels of this material and the material in the second hole-transport layer is 0.29 eV. Here, the temperature acceleration coefficients of the light-emitting devices were compared. The temperature acceleration coefficient was calculated by dividing the elapsed time taken for the luminance to decrease to 90% of the initial luminance at room temperature (LT90(R.T.)) by the elapsed time taken for the luminance to decrease to 90% of the initial luminance at 85° C. (LT90(85 deg.)). Thus, a smaller temperature acceleration coefficient indicates smaller degradation due to high temperature during the high-temperature driving. LT90(R.T.) and LT90(85 deg.) read from inFIGS.29A and29Band the temperature acceleration coefficients of the light-emitting devices are listed in the following table. TABLE 8LT90Temperature accelerationR.T.85 deg.coefficientLight-emitting device 2512678Comparative light-emitting820*16113device 2*1an extrapolated value In this example, BBABnf with a HOMO level slightly deeper than that of DBfBB1TP used in Example 1 was used as the material for the hole-transport layer in contact with the light-emitting layer. As a result, the difference between HOMO levels of the host material and the material used for the hole-transport layer in contact with the light-emitting layer was smaller than that in Example 1. Also in Example 2, the light-emitting device2, in which the difference was smaller than that in the comparative light-emitting device2, showed more favorable results than that in the high-temperature driving test. Furthermore, a difference in temperature acceleration coefficient between the light-emitting device2and the comparative light-emitting device2was smaller than that between the light-emitting device1and the comparative light-emitting device1in Example 1. Thus, in the comparative light-emitting device2in which the difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer in contact with the light-emitting layer was greater than 0.24 eV, the luminance largely decreased at high temperature with a change in the shape of the degradation curve, which showed a possibility of degradation in a different mechanism. On the other hand, in the light-emitting device2in which the difference was less than or equal to 0.24 eV, favorable results were obtained without such an irregularity. It was found that the difference of HOMO levels in the light-emitting device2was 0.13 eV, which was smaller than 0.19 eV of the light-emitting device1in Example 1, and the driving lifetime at 85° C. was increased accordingly in the light-emitting device2. Thus, in one embodiment of the present invention, the difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer in contact with the light-emitting layer is further preferably less than or equal to 0.16 eV. Example 3 In this example, light-emitting devices3and4of one embodiment of the present invention are described. Structural formulae of organic compounds used for the light-emitting devices3and4are shown below. (Method of Fabricating Light-Emitting Device3) First, indium tin oxide containing silicon oxide (ITSO) was deposited over a glass substrate by a sputtering method to form the anode101. The thickness of the anode101was 70 nm and the electrode area was 2 mm×2 mm. Next, in pretreatment for forming the light-emitting device over a substrate, a surface of the substrate was washed with water and baked at 200° C. for 1 hour, and then UV ozone treatment was performed for 370 seconds. After that, the substrate was transferred into a vacuum evaporation apparatus where the pressure was reduced to approximately 10−4Pa, vacuum baking was performed at 170° C. for 30 minutes in a heating chamber of the vacuum evaporation apparatus, and then the substrate was cooled down for approximately 30 minutes. Next, the substrate provided with the anode101was fixed to a substrate holder provided in the vacuum evaporation apparatus such that the side on which the anode101was formed faced downward. Then, N,N-bis(4-biphenyl)-6-phenylbenzo[b]naphtho[1,2-d]furan-8-amine (abbreviation: BBABnf) represented by Structural Formula (viii) and ALD-MP001Q (produced by Analysis Atelier Corporation, material serial No. 1S20170124) were co-evaporated to a thickness of 10 nm on the anode101using a resistance-heating method such that the weight ratio of BBABnf to ALD-MP001Q was 1:0.1, whereby the hole-injection layer111was formed. Subsequently, over the hole-injection layer111, BBABnf was evaporated to a thickness of 20 nm to form the first hole-transport layer112-1, and then 3,3′-(naphthalene-1,4-diyl)bis(9-phenyl-9H-carbazole) (abbreviation: PCzN2) represented by Structural Formula (ix) was evaporated to a thickness of 10 nm to form the second hole-transport layer112-2, whereby the hole-transport layer112was formed. Note that the second hole-transport layer112-2also functions as an electron-blocking layer. Then, 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA) represented by Structural Formula (iii) and 3,10-bis[N-(9-phenyl-9H-carbazol-2-yl)-N-phenylamino]naphtho[2,3-b;6,7-b′]bisbenzofuran (abbreviation: 3,10PCA2Nbf(IV)-02) represented by Structural Formula (iv) were co-evaporated to a thickness of 25 nm such that the weight ratio of cgDBCzPA to 3,10PCA2Nbf(IV)-02 was 1:0.015, whereby the light-emitting layer113was formed. Then, over the light-emitting layer113, 2-[3′-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenzo[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II) represented by Structural Formula (v) was evaporated to a thickness of 15 nm, and subsequently 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen) represented by Structural Formula (vi) was evaporated to a thickness of 10 nm, whereby the electron-transport layer114was formed. After the formation of the electron-transport layer114, lithium fluoride (LiF) was evaporated to a thickness of 1 nm to form the electron-injection layer115. Then, aluminum was evaporated to a thickness of 200 nm to form the cathode102. Thus, the light-emitting device3of this example was fabricated. (Method of Fabricating Light-Emitting Device4) The light-emitting device4was fabricated in a manner similar to that for the light-emitting device3except that 9-(1-naphthyl)-10-[4-(2-naphthyl)phenyl]anthracene (abbreviation: αN-NPAnth) represented by Structural Formula (vii) was used instead of cgDBCzPA of the light-emitting device3. The device structures of the light-emitting devices3and4are listed in the following table. TABLE 9Hole-Hole-transportLight-Electron-injectionlayeremittinginjectionlayer12layerElectron-transport layerlayer10 nm20 nm10 nm25 nm15 nm10 nm1 nmLight-emittingBBABnf:BBABnfPCzN2*52mDBTBPDBq-IINBPhenLiFdevice 3ALD-light-emittingMP001Q*6device 4(1:0.1)*5 cgDBCzPA: 3, 10PCA2Nbf(IV)-02 (1:0.015)*6 αN-βNPAnth: 3, 10PCA2Nbf(IV)-02 (1:0.015) The HOMO levels of the organic compounds used in this example are listed in the following table. TABLE 10HOMO level (eV)BBABnf−5.56PCzN2−5.71cgDBCzPA−5.69αN-βNPAnth−5.85 These light-emitting devices were sealed using a glass substrate in a glove box containing a nitrogen atmosphere so as not to be exposed to the air (a sealing material was applied to surround the element and UV treatment and heat treatment at 80° C. for 1 hour were performed at the time of sealing). Then, the initial characteristics and reliability of the light-emitting devices were measured. Note that the measurement was performed at room temperature. FIG.30shows the luminance-current density characteristics of the light-emitting devices3and4.FIG.31shows the current efficiency-luminance characteristics thereof.FIG.32shows the luminance-voltage characteristics thereof.FIG.33shows the current-voltage characteristics thereof.FIG.34shows the power efficiency-luminance characteristics thereof.FIG.35shows the external quantum efficiency-luminance characteristics thereof.FIG.36shows the emission spectra thereof. Table 11 shows the main characteristics of the light-emitting devices3and4at a luminance of about 1000 cd/m2. TABLE 11CurrentPowerExternalVoltageCurrentdensityChromaticityChromaticityefficiencyquantum(V)(mA)(mA/cm2)xy(lm/W)efficiency (%)Light-emitting3.20.369.00.140.1411.811.0device 3Light-emitting3.90.358.60.140.119.012.1device 4 FIG.30toFIG.36and Table 11 show that the light-emitting devices3and4of one embodiment of the present invention are blue light-emitting devices with favorable characteristics. FIG.37Ais a graph showing a change in luminance over driving time at a high temperature of 85° C. and a current density of 50 mA/cm2. As shown inFIG.37A, the luminances of the light-emitting devices3and4both decrease with time substantially in accordance with the single exponential function. FIG.37Bis a graph showing a change in luminance over driving time at a current density of 50 mA/cm2at room temperature. At room temperature, the luminances of the light-emitting devices3and4both decreased with time substantially in accordance with the single exponential function with small gradients of the degradation curves. The host material in the light-emitting layer of the light-emitting device3of one embodiment of the present invention is cgDBCzPA with a HOMO level of −5.69 eV, and the material in the hole-transport layer that is in contact with the light-emitting layer is PCzN2 with a HOMO level of −5.71 eV; thus, a difference of HOMO levels therebetween is 0.02 eV. On the other hand, the host material in the light-emitting layer of the light-emitting device4is αN-βNPAnth with a HOMO level of −5.85 eV, and thus a difference between HOMO levels of this material and the material in the second hole-transport layer is 0.14 eV. Here, the temperature acceleration coefficients of the light-emitting devices were compared. The temperature acceleration coefficient was calculated by dividing the elapsed time taken for the luminance to decrease to 90% of the initial luminance at room temperature (LT90(R.T.)) by the elapsed time taken for the luminance to decrease to 90% of the initial luminance at 85° C. (LT90(85 deg.)). Thus, a smaller temperature acceleration coefficient indicates smaller degradation due to high temperature during the high-temperature driving. LT90(R.T.) and LT90(85 deg.) read fromFIGS.37A and37Band the temperature acceleration coefficients of the light-emitting devices are listed in the following table. TABLE 12LT90Temperature accelerationR.T.85 deg.coefficientLight-emitting device 3363448Light-emitting device 4640*25911*2an extrapolated value In this example, PCzN2 with a deep HOMO level is used as the material for the hole-transport layer that is in contact with the light-emitting layer, and thus the difference between HOMO levels of the host material and PCzN2 is sufficiently small. When the comparative light-emitting device1of Example 1, the comparative light-emitting device2of Example 2, and the light-emitting device4of this example, in each of which the same host material was used, were compared, it was found that smaller decrease in luminance and longer driving lifetime were obtained at high temperature as the HOMO level of the material for the hole-transport layer in contact with the light-emitting layer was deeper, i.e., as the difference between HOMO levels of the host material and the material for the hole-transport layer was smaller. As described above, it was found that the light-emitting devices3and4, in which the difference between HOMO levels of the host material and the hole-transport material used for the hole-transport layer in contact with the light-emitting layer was less than or equal to 0.24 eV, had a small temperature acceleration coefficient and a favorable driving lifetime at high temperature. Note that the light-emitting devices3and4had a smaller difference in HOMO levels than that of the light-emitting device1in Example 1, which is 0.20 eV, and accordingly had an improved driving lifetime at 85° C. Reference Example In this reference example, methods of calculating the HOMO levels and the LUMO levels of the organic compounds used in the examples are described. The HOMO level and the LUMO level can be calculated through a cyclic voltammetry (CV) measurement. An electrochemical analyzer (ALS model600A or600C, manufactured by BAS Inc.) was used as the measurement apparatus. A solution for the CV measurement was prepared in the following manner: tetra-n-butylammonium perchlorate (n-Bu4NClO4, produced by Tokyo Chemical Industry Co., Ltd., catalog No. T0836) as a supporting electrolyte was dissolved in dehydrated dimethylformamide (DMF, produced by Sigma-Aldrich Co. LLC., 99.8%, catalog No. 22705-6) as a solvent at a concentration of 100 mmol/L, and the object to be measured was dissolved therein at a concentration of 2 mmol/L. A platinum electrode (PTE platinum electrode, manufactured by BAS Inc.) was used as a working electrode, another platinum electrode (Pt counter electrode for VC-3 (5 cm), manufactured by BAS Inc.) was used as an auxiliary electrode, and an Ag/Ag+electrode (RE7 reference electrode for nonaqueous solvent, manufactured by BAS Inc.) was used as a reference electrode. Note that the measurement was conducted at room temperature (20° C. to 25° C.). In addition, the scan speed in the CV measurement was fixed to 0.1 V/sec, and an oxidation potential Ea [V] and a reduction potential Ec [V] with respect to the reference electrode were measured. The potential Ea is an intermediate potential of an oxidation-reduction wave, and the potential Ec is an intermediate potential of a reduction-oxidation wave. Here, since the potential energy of the reference electrode used in this example with respect to the vacuum level is known to be −4.94 [eV], the HOMO level and the LUMO level can be calculated by the following formulae: HOMO level [eV]−4.94−Ea and LUMO level [eV]−4.94−Ec. REFERENCE NUMERALS 101: anode,102: cathode,103: EL layer,111: hole-injection layer,112: hole-transport layer,112-1: first hole-transport layer,112-2: second hole-transport layer,113: light-emitting layer,114: electron-transport layer,115: electron-injection layer,116: charge generation layer,117: p-type layer,118: electron-relay layer,119: electron-injection buffer layer,400: substrate,401: anode,403: EL layer,404: cathode,405: sealing material,406: sealing material,407: sealing substrate,412: pad,420: IC chip,501: anode,502: cathode,511: first light-emitting unit,512: second light-emitting unit,513: charge generation layer,601: driver circuit portion (source line driver circuit),602: pixel portion,603: driver circuit portion (gate line driver circuit),604: sealing substrate,605: sealing material,607: space,608: wiring,609: FPC (flexible printed circuit),610: element substrate,611: switching FET,612: current controlling FET,613: anode,614: insulator,616: EL layer,617: cathode,618: light-emitting device,951: substrate,952: electrode,953: insulating layer,954: partition layer,955: EL layer,956: electrode,1001: substrate,1002: base insulating film,1003: gate insulating film,1006: gate electrode,1007: gate electrode,1008: gate electrode,1020: first interlayer insulating film,1021: second interlayer insulating film,1022: electrode,1024W: anode,1024R: anode,1024G: anode,1024B: anode,1025: partition,1028: EL layer,1029: cathode,1031: sealing substrate,1032: sealing material,1033: transparent base material,1034R: red coloring layer,1034G: green coloring layer,1034B: blue coloring layer,1035: black matrix,1036: overcoat layer,1037: third interlayer insulating film,1040: pixel portion,1041: driver circuit portion,1042: peripheral portion,2001: housing,2002: light source,2100: robot,2110: arithmetic device,2101: illuminance sensor,2102: microphone,2103: upper camera,2104: speaker,2105: display,2106: lower camera,2107: obstacle sensor,2108: moving mechanism,3001: lighting device,5000: housing,5001: display portion,5002: second display portion,5003: speaker,5004: LED lamp,5005: control key,5006: connection terminal,5007: sensor,5008: microphone,5012: support,5013: earphone,5100: cleaning robot,5101: display,5102: camera,5103: brush,5104: operation button,5150: personal digital assistant,5151: housing,5152: display region,5153: bend portion,5120: dust,5200: display region,5201: display region,5202: display region,5203: display region,7101: housing,7103: display portion,7105: stand,7107: display portion,7109: operation key,7110: remote controller,7201: main body,7202: housing,7203: display portion,7204: keyboard,7205: external connection port,7206: pointing device,7210: second display portion,7401: housing,7402: display portion,7403: operation button,7404: external connection port,7405: speaker,7406: microphone,9310: personal digital assistant,9311: display panel,9313: hinge, and9315: housing. This application is based on Japanese Patent Application Serial No. 2019-008234 filed with Japan Patent Office on Jan. 22, 2019, the entire contents of which are hereby incorporated by reference. | 143,711 |
11943945 | DETAILED DESCRIPTION FIG.1is a cross-sectional view schematically illustrating the structure of an organic light-emitting diode (“OLED”)10according to an exemplary embodiment of the present disclosure. The OLED10according to an exemplary embodiment of the present disclosure includes a bottom electrode11, a top electrode19disposed opposite to the bottom electrode11, and an organic layer15that is interposed between the bottom electrode11and the top electrode19, wherein the organic layer15includes an exciplex-forming co-host consisting of a hole-transporting host and an electron-transporting host and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex. The bottom electrode11of the OLED10may be an anode to which a positive voltage is applied, and the top electrode19of the OLED10may be a cathode to which a negative voltage is applied. Alternatively, the bottom electrode11may be the cathode, and the top electrode19may be the anode. A case of the OLED10including the bottom electrode11as the anode and the top electrode19as the cathode is described for convenience. When a voltage is applied to the bottom electrode11and the top electrode19of the OLED10, holes in the organic layer15are transported by a hole-transporting host, and electrons in the organic layer15are transported by an electron-transporting host such that an exciton is formed in a light emitting layer16. Since a mixture of a hole-transporting host having hole transport characteristics and an electron-transporting host having electron transport characteristics is used as a host of the light emitting layer16, a driving voltage is lowered as there is no energy barrier when holes and electrons are injected into the light emitting layer16. However, the exciton is not easily formed since the holes and the electrons are not present in the same host material when a hole-transporting host having holes and an electron-transporting host having electrons are brought into contact with each other in the light emitting layer16. Since the OLED10uses as a co-host a hole-transporting host and an electron-transporting host that are capable of being brought into contact with each other to form an exciplex upon excitation, holes on the hole-transporting host and electrons on the electron-transporting host are only physically brought into contact with each other to form the exciplex and the exciplex energy may be transferred to the dopant through energy transfer. Energy is transferred from the exciplex which is formed between a hole-transporting host and an electron-transporting host in the organic layer15to a phosphorescent dopant. Therefore, the triplet energy of the phosphorescent dopant should be lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex in order for the energy transfer to take place. As a result, when a hole-transporting host having holes and an electron-transporting host having electrons are brought into contact with each other in the organic layer15, the OLED10forms the exciplex, wherein an energy of the formed exciplex is transferred to a phosphorescent dopant such that an exciton may be formed in the phosphorescent dopant, and then recombination of the exciton occurs in the light emitting layer16such that light emission may occur. There are no energy barriers to inject holes and electrons into the emitting layer16using a co-host, and the hole-transporting host and the electron-transporting host are brought into contact with each other to form the exciplex in a state that the hole-transporting host and the electron-transporting host do not transfer holes or electrons over an energy barrier there between, or the hole-transporting host and the electron-transporting host do not transfer the holes or electrons to a dopant. Therefore, the OLED10has low driving voltage and high luminous efficiency characteristics. When a phosphorescent dopant is used, the OLED10may display a high efficiency value with low efficiency roll-off at a high luminance value. The hole-transporting host and the electron-transporting host may satisfy the following relational expressions 1 and 2: Lowest unoccupied molecular orbital (“LUMO”) energy of the hole-transporting host−LUMO energy of the electron-transporting host>0.2 eV and (1) Highest occupied molecular orbital (“HOMO”) energy of the hole-transporting host−HOMO energy of the electron-transporting host>0.2 eV. (2) When a difference between the LUMO energy of the hole-transporting host and the LUMO energy of the electron-transporting host is higher than 0.2 eV, an exciplex may be smoothly formed without a process of directly transferring electrons from the electron-transporting host to the hole-transporting host. Further, when a difference between the HOMO energy of the hole-transporting host and the HOMO energy of the electron-transporting host is higher than 0.2 eV, the exciplex may be smoothly formed without a process of directly transferring holes from the hole-transporting host to the electron-transporting host. The organic layer15of the OLED10may include the light emitting layer16. The organic layer15includes a hole-transporting host and an electron-transporting host, and the light emitting layer16includes a hole-transporting host, an electron-transporting host and a phosphorescent dopant. The hole-transporting host, the electron-transporting host and the phosphorescent dopant may have a mixing molar ratio range of 100:30-300:1-100 in the organic layer15of the OLED10. When the mixing molar ratio range of the hole-transporting host, the electron-transporting host and the phosphorescent dopant satisfies the above range, satisfactory levels of energy transfer and light emission may occur. For example, the hole-transporting host and the electron-transporting host may be mixed in a combination selected from TCTA:B3PYMPM, TCTA:TPBi, TCTA:3TPYMB, TCTA:BmPyPB, TCTA:BSFM, CBP:B3PYMPM, and NPB:BSFM. FIG.2is a cross-sectional view schematically illustrating the structure of an OLED20according to another exemplary embodiment of the present disclosure. The OLED20according to the another exemplary embodiment of the present disclosure includes: a bottom electrode21; a top electrode29disposed opposite to the bottom electrode21; and an organic layer25that is interposed between the bottom electrode21and the top electrode29, wherein the organic layer25includes a light emitting layer26, a hole transport layer23interposed between the light emitting layer26and the bottom electrode21, a hole injection layer22interposed between the hole transport layer23and the bottom electrode21, an electron transport layer27interposed between the light emitting layer26and the top electrode29, and an electron injection layer28interposed between the electron transport layer27and the top electrode29. At least one of the hole injection layer22and the electron injection layer28may be omitted. The hole transport layer23of the OLED20may be formed using a hole-transporting host, the light emitting layer26includes a hole-transporting host, an electron-transporting host and a phosphorescent dopant, and the electron transport layer27may be formed using an electron-transporting host. The hole-transporting host and the electron-transporting host are a co-host forming an exciplex upon excitation. That is, the hole transport layer23includes a hole-transporting material, wherein the hole-transporting material is the same material as the hole-transporting host, and an electron-transporting material included in the electron transport layer27is the same material as the electron-transporting host. In the OLED20, the holes are present within the hole-transporting host in the hole transport layer23as holes are transported from the bottom electrode21to the hole transport layer23via the hole injection layer22, and the electrons are present within the electron-transporting host in the electron transport layer27as electrons are transported from the top electrode29to the electron transport layer27via the electron injection layer28. When the holes and electrons are transferred to the light emitting layer26, the holes are moved from the hole-transporting host of the hole transport layer23to the hole-transporting host of the light emitting layer26such that the holes are transferred to the light emitting layer26, and the electrons are moved from the electron-transporting host of the electron transport layer27to the electron-transporting host of the light emitting layer26such that the electrons are transferred to the light emitting layer26. Therefore, an energy barrier between the hole transport layer23and the light emitting layer26and an energy barrier between the electron transport layer27and the light emitting layer26are removed and absent such that a driving voltage is greatly reduced. After the hole-transporting host and the electron-transporting host are physically brought into contact with each other to form an exciplex in the light emitting layer26, the exciplex energy is transferred to a phosphorescent dopant to form an exciton. A triplet energy of the phosphorescent dopant may be less than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host and the triplet energy of the exciplex in order for the energy transfer to take place efficiently. The hole-transporting host, the electron-transporting host and the phosphorescent dopant may have a mixing molar ratio range of 100:30-300:1-100 in the light emitting layer26of the OLED20. When the mixing molar ratio range of the hole-transporting host, the electron-transporting host and the phosphorescent dopant satisfies the above range, energy transfer and light emission may occur efficiently. An OLED according to another exemplary embodiment of the present disclosure may include: a bottom electrode; a top electrode disposed opposite to the bottom electrode; and an organic layer that is interposed between the bottom electrode and the top electrode, the organic layer including a hole-transporting host and an electron-transporting host which form an exciplex upon excitation and in which a difference between a singlet energy of the exciplex and a triplet energy of the exciplex is lower than 0.3 eV, and a fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex. The bottom electrode of the OLED may be an anode to which a positive voltage is applied, and the top electrode of the OLED may be a cathode to which a negative voltage is applied. Alternatively, the bottom electrode may be the cathode, and the top electrode may be the anode. A case of the OLED including the bottom electrode as the anode and the top electrode as the cathode is described for convenience. When a voltage is applied to the bottom electrode and the top electrode of the OLED, holes in the organic layer are transported by a hole-transporting host, and electrons in the organic layer are transported by an electron-transporting host such that an exciton is formed in a light emitting layer. Since a mixture of a hole-transporting host having hole transport characteristics and an electron-transporting host having electron transport characteristics is used as a host of the light emitting layer, a driving voltage is lowered as there is no energy barrier when holes and electrons are injected into the light emitting layer. The OLED uses as a co-host a hole-transporting host and an electron-transporting host that are capable of being brought into contact with each other to form an exciplex upon excitation. The exciplex in the organic layer are present in the singlet and in the triplet states with a ratio of 1:3. Since the difference between the singlet energy of the exciplex and the triplet energy of the exciplex is less than 0.3 eV in the OLED, reversible intersystem crossing is possible such that the triplet state can be reversed into the singlet state. Therefore, most exciplexes in the organic layer may be present in a state that they are crossed into the singlet state. Furthermore, since a singlet energy of a fluorescent dopant is lower than the singlet energy of the exciplex, the exciplexes of the singlet state that are present in the organic layer smoothly transfer energy to the dopant such that an exciton may be formed. As a result, an internal quantum efficiency of the OLED may be very high using a fluorescent dopant. There are no energy barriers to inject holes and electrons into emitting layer using co-host, and the hole-transporting host and the electron-transporting host are brought into contact with each other to form an exciplex such that an energy of singlet exciplex is transferred to the fluorescent dopant. Therefore, such an OLED may have a low driving voltage, a high luminous efficiency and a very high internal quantum efficiency. The hole-transporting host and the electron-transporting host may satisfy the following relational expressions 1 and 2: LUMO energy of the hole-transporting host−LUMO energy of the electron-transporting host>0.2 eV and (1) HOMO energy of the hole-transporting host−HOMO energy of the electron-transporting host>0.2 eV. (2) When a difference between the LUMO energy of the hole-transporting host and the LUMO energy of the electron-transporting host is higher than 0.2 eV, an exciplex may be formed without a process of directly transferring electrons from the electron-transporting host to the hole-transporting host. Further, when a difference between the HOMO energy of the hole-transporting host and the HOMO energy of the electron-transporting host is higher than 0.2 eV, the exciplex may be formed without a process of directly transferring holes from the hole-transporting host to the electron-transporting host. An organic layer of the OLED may include a light emitting layer. The organic layer includes a hole-transporting host and an electron-transporting host, and the light emitting layer includes a hole-transporting host, an electron-transporting host and a fluorescent dopant. The hole-transporting host, the electron-transporting host and the fluorescent dopant may have a mixing molar ratio range of 100:30-300:1-100 in the organic layer of the OLED. When the mixing molar ratio range of the hole-transporting host, the electron-transporting host and the fluorescent dopant satisfies the above range, efficient energy transfer and light emission may occur. For example, the hole-transporting host and the electron-transporting host may be mixed in a combination selected from TCTA:B3PYMPM, TCTA:TPBi, TCTA:3TPYMB, TCTA:BmPyPB, TCTA:BSFM, CBP:B3PYMPM, and NPB:BSFM. An OLED according to another exemplary embodiment of the present disclosure includes: a bottom electrode; a top electrode disposed opposite to the bottom electrode; and an organic layer that is interposed between the bottom electrode and the top electrode, wherein the organic layer includes a light emitting layer, a hole transport layer interposed between the light emitting layer and the bottom electrode, a hole injection layer interposed between the hole transport layer and the bottom electrode, an electron transport layer interposed between the light emitting layer and the top electrode, and an electron injection layer interposed between the electron transport layer and the top electrode. At least one of the hole injection layer and the electron injection layer may be omitted. The hole transport layer of the OLED may be formed using a hole-transporting material, wherein the hole-transporting material is the same material as the hole-transporting host, and an electron-transporting material in the electron transport layer may be the same material as the electron-transporting host. In the OLED, the holes are present within the hole-transporting host in the hole transport layer as holes are transported from the bottom electrode to the hole transport layer via the hole injection layer, and the electrons are present within the electron-transporting host in the electron transport layer as electrons are transported from the top electrode to the electron transport layer via the electron injection layer. When transferring the holes and electrons to the light emitting layer, the holes are moved from the hole transport layer to the hole-transporting host of the light emitting layer such that the holes are transferred to the light emitting layer, and the electrons are moved from the electron transport layer to the electron-transporting host of the light emitting layer such that the electrons are transferred to the light emitting layer. Therefore, an energy barrier between the hole transport layer and the light emitting layer and an energy barrier between the electron transport layer and the light emitting layer are removed such that a driving voltage is greatly reduced. A hole-transporting host and an electron-transporting host are physically brought into contact with each other in a light emitting layer to form an exciplex and transfer the exciplex energy to a fluorescent dopant. The exciplex is present in a singlet state since a difference between the singlet energy of the exciplex and the triplet energy of the exciplex is less than 0.3 eV, and the energy of singlet exciplex is transferred to the fluorescent dopant since a singlet energy of the fluorescent dopant is less than the singlet energy of the exciplex. The hole-transporting host, the electron-transporting host and the fluorescent dopant may have a mixing molar ratio range of 100:30-300:1-100 in the light emitting layer of the OLED. When the mixing molar ratio range of the hole-transporting host, the electron-transporting host and the fluorescent dopant satisfies the above range, efficient energy transfer and light emission may occur. Hereinafter, a method of manufacturing an OLED according to an exemplary embodiment of the present disclosure is described in detail by referring toFIG.2. However, the exemplary embodiment of the present disclosure is not limited thereto. Examples of a substrate (which is not drawn in the drawing) may include substrates used in OLEDs of the related art, and a glass substrate or a transparent plastic substrate that is excellent in terms of mechanical strength, thermal stability, transparency, surface flatness, handling ability, and waterproofing property. For example, a substrate may be formed of a transparent glass material including SiO2as a principle component. A bottom electrode21is formed on the substrate. The bottom electrode21may be formed as a transparent electrode or a reflection electrode, and the bottom electrode21may be formed as the transparent electrode if an OLED is a bottom emitting type. When forming the bottom electrode21as the transparent electrode, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), graphene, etc may be used. When forming the bottom electrode21as the reflection electrode, after a reflection film is formed of silver (Ag), magnesium (Mg), aluminium (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof, a film is formed on the reflection film using ITO, IZO, ZnO, graphene, etc. such that the reflection electrode may be formed. The bottom electrode21may be formed by various well-known methods such as deposition, sputtering, spin-coating, etc. A hole injection layer22is formed on the bottom electrode21. The hole injection layer22may be formed on the top of the bottom electrode21by various methods such as vacuum deposition, spin-coating, casting, a Langmuir-Blodgett (LB) method, etc. Well-known hole injection materials may be used as material used in the hole injection layer22. Examples of the material used in the hole injection layer22may include: a phthalocyanine compound such as copper phthalocyanine; m-MTDATA; TDATA; TAPC, 2-TNATA; Pani/DBSA (polyaniline/dodecylbenzenesulfonic acid), PEDOT/PSS (poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate)), Pani/CSA (polyaniline/camphorsulfonic acid), Pani/PSS (polyaniline/poly(4-styrenesulfonate)), etc. However, the material used in the hole injection layer22is not limited to the examples. A hole transport layer23is formed on the hole injection layer22. The hole transport layer23may be formed by various methods such as vacuum deposition, spin-coating, casting, a LB method, etc. The above-described hole-transporting host may be used as the material that forms the hole transport layer23. A light emitting layer26is formed on the hole transport layer23. The light emitting layer26may be formed by various methods such as vacuum deposition, spin-coating, casting, a LB method, etc. The light emitting layer26includes a hole-transporting host, an electron-transporting host, and a phosphorescent or fluorescent dopant. For example, the hole-transporting host and the electron-transporting host may be mixed in a combination selected from TCTA:B3PYMPM, TCTA:TPBi, TCTA:3TPYMB, TCTA:BmPyPB, TCTA:BSFM, CBP:B3PYMPM, and NPB:BSFM. Examples of the phosphorescent dopant may include Ir(ppy), Ir(ppy)2(acac) or PtOEP, but is not limited thereto. Examples of the fluorescent dopant may include a fused-ring aromatic compound such as rubrene, coumarin such as DMQA or 0545T, or di-pyran such as DCJTB or DCM, but is not limited thereto. The hole-transporting host, the electron-transporting host and the phosphorescent dopant (or fluorescent dopant) may be contained in the light emitting layer26in amounts selected from a mixing molar ratio range of 100:30-300:1-100. An electron transport layer27is formed on the light emitting layer26. The electron transport layer27may be formed by various methods such as vacuum deposition, spin-coating, casting, a LB method, etc. The above-described electron-transporting host may be used as the material that forms the electron transport layer27. An electron injection layer28having a function of facilitating injection of electrons from the top electrode29is formed on the electron transport layer27. The electron injection layer28may be formed by various methods such as vacuum deposition, spin-coating, casting, a LB method, etc. Materials such as LiF, NaCl, CsF, Li2O, BaO, etc. may be used as a material that forms the electron injection layer28. A top electrode29is formed on the electron injection layer28. The top electrode29may be formed in a structure including: an alkali metal such as lithium, sodium, potassium, rubidium, cesium, etc.; an alkali earth metal such as beryllium, magnesium, calcium, strontium, barium, etc.; a metal such as aluminum, scandium, vanadium, zinc, yttrium, indium, cerium, samarium, europium, terbium, ytterbium, etc.; an alloy of two or more thereof; or alloy of one or more thereof and one or more of gold, silver, platinum, copper, manganese, titanium, cobalt, nickel, tungsten and tin; and one or more thereof. The structure may be a single layer or a stacked layer. If it is necessary, ITO treated by ultraviolet rays and ozone may be used. Also, the top electrode29may use IZO, ZnO, or graphene. If the OLED is a top-emission OLED, the top electrode29may be formed of a transparent oxide such as ITO, IZO, ZnO, or graphene. The top electrode29may be formed by various well-known methods such as deposition, sputtering, spin-coating, etc. A lighting device including the OLED according to another exemplary embodiment of the present disclosure is provided. The lighting device includes an OLED including a hole-transporting host and an electron-transporting host that form an exciplex, and a phosphorescent or fluorescent dopant. A display apparatus including the OLED according to another exemplary embodiment of the present disclosure is provided. The display apparatus includes: a transistor including a source, a drain, a gate and an activation layer; and an OLED including a hole-transporting host and an electron-transporting host that form an exciplex upon excitation, and a phosphorescent or fluorescent dopant. A bottom electrode of the OLED may be electrically connected to the source or the drain. Hereinafter, an OLED according to an exemplary embodiment of the present disclosure is described in more detail through unlimited Reference Examples and Examples. However, the following Reference Examples and Examples are only for exemplifying the present disclosure, and a scope of the present disclosure is not limited by the following Reference Examples and Examples. Reference Example 1 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a 4,6-bis(3,5-di(pyridin-3-yl)phenyl)-2-methylpyrimidine (B3PYMPM) thin film, and a thin film in which TCTA and B3PYMPM were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.3A. Comparative Reference Example 1 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a 1,1′-biphenyl-4′-oxy)-bis(8-hydroxy-2-methylquinolinato)aluminum (BAlq) thin film, and a thin film in which TCTA and BAlq were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.3B. Reference Example 2 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a 1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene (TPBi) thin film, and a thin film in which TCTA and TPBi were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4A. Reference Example 3 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a tris(2,4,6-trimethyl-3-(pyridin-3-yl)phenyl)borane (3TPYMB) thin film, and a thin film in which TCTA and 3TPYMB were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4B. Reference Example 4 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a 1,3-bis(3,5-dipyrid-3-yl-phenyl)benzene (BmPyPB) thin film, and a thin film in which TCTA and BmPyPB were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4C. Reference Example 5 A 4,4′,4″-tris(carbazol-9-yl)-triphenylamine (TCTA) thin film, a bis-9,9′-spirobi[fluoren-2-yl]-methanone (BSFM) thin film, and a thin film in which TCTA and BSFM were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4D. Reference Example 6 A 4-4′-bis(carbazol-9-yl)biphenyl (CBP) thin film, a 4,6-bis(3,5-di(pyridin-3-yl)phenyl)-2-methylpyrimidine (B3PYMPM) thin film, and a thin film in which CBP and B3PYMPM were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4E. Reference Example 7 A N,N′-diphenyl-N,N′-bis(1-naphthylphenyl)-1,1′-biphenyl-4,4′-diamine (NPB) thin film, a bis-9,9′-spirobi[fluoren-2-yl]-methanone (BSFM) thin film, and a thin film in which NPB and BSFM were mixed at a molar ratio of 1:1 were manufactured. Photoluminescence spectra of the three thin films were measured using a He:Cd laser and a photomultiplier tube (Acton Research Corporation; PD-471) to which a monochromator (Acton Research Corporation; SpectraPro 300i) was attached. The measured photoluminescence spectra are illustrated inFIG.4F. Evaluation Example Referring toFIG.3A, it can be seen from the thin films according to the Reference Example 1 that a photoluminescence spectrum of TCTA:B3PYMPM co-host thin film shows light emission of a long wavelength range that is not shown in the photoluminescence spectra of pristine TCTA and B3PYMPM thin films. It may be seen from this that TCTA and B3PYMPM are brought into contact with each other to form an exciplex upon photo-excitation in the thin film in which TCTA and B3PYMPM were mixed. Referring toFIG.3B, it can be seen from the thin films according to the Comparative Reference Example 1 that a photoluminescence spectrum of TCTA:BaIq co-host thin film was similar with a photoluminescence spectrum of a BAlq thin film. It may be seen from this that an exciplex is not formed in the TCTA:BAlq co-host thin film in which TCTA and BAlq were mixed although TCTA and BAlq are brought into contact with each other. Referring toFIGS.4A to4F, it can be seen from the photoluminescence spectra of the co-host thin films according to the Reference Examples 2 to 7 that the light emission of a long wavelength range that is not shown in a photoluminescence spectrum of a single host thin film which is component of co-host thin film. It may be seen from this that a hole-transporting host material and an electron-transporting host material are mixed to form an exciplex upon photo-excitation in the thin films in which components according to the respective Reference Examples 2 to 7 were mixed. Example 1 An OLED having the following composition was manufactured: ITO/TAPC/TCTA/TCTA:B3PYMPM:Ir(ppy)2(acac)/B3PYMPM/LiF/Al A 1,500 Å thick ITO glass substrate in which an ITO film was formed on a glass substrate was used as a bottom electrode, TAPC was deposited on the top of the ITO glass substrate to form a 200 Å thick hole injection layer. TCTA was deposited on the top of the hole injection layer to form a 100 Å thick hole transport layer. TCTA, B3PYMPM and Ir(ppy)2(acac) were simultaneously deposited on the top of the hole transport layer at a molar ratio of 100:100:21 to form a 300 Å thick light emitting layer. B3PYMPM was deposited on the top of the light emitting layer to form a 400 Å thick electron transport layer. After LiF was deposited on the top of the electron transport layer to form a 10 Å thick electron injection layer, Al was deposited on the electron injection layer to form a 1,000 Å thick top electrode such that an OLED was manufactured. Example 2 An OLED having the following composition was manufactured using the same method as in the Example 1 except that a 700 Å thick ITO glass substrate was used as the bottom electrode, and TAPC was deposited on the top of the ITO glass substrate to form a 60 Å thick hole injection layer: ITO/TAPC/TCTA/TCTA:B3PYMPM:Ir(ppy)2(acac)/B3PYMPM/LiF/Al Comparative Example 1 An OLED having the following composition was manufactured using the same method as in the Example 1 except that TCTA, BAlq and Ir(ppy)2(acac) were simultaneously deposited on the top of the hole transport layer at a molar ratio of 100:100:21 to form a 300 Å thick light emitting layer, and BAlq was deposited on the top of the light emitting layer to form a 400 Å thick electron transport layer: ITO/TAPC/TCTA/TCTA:BAlq:Ir(ppy)2(acac)/BAlq/LiF/Al Comparative Example 2 An OLED having the following composition was manufactured using the same method as in the Example 1 except that TCTA, BAlq and Ir(dmpq)2(acac) were simultaneously deposited on the top of the hole transport layer at a molar ratio of 100:100:6 to form a 300 Å thick light emitting layer, and BAlq was deposited on the top of the light emitting layer to form a 400 Å thick electron transport layer: ITO/TAPC/TCTA/TCTA:BAld:Ir(dmpd)2(acac)/BAlq/LiF/Al Evaluation Example Highest occupied molecular orbital (“HOMO”) energies and lowest unoccupied molecular orbital (“LUMO”) energies for respective layers composing an OLED according to the Example 1 were shown inFIG.5. Referring toFIG.5, it can be seen that the LUMO energy of TCTA, a hole-transporting host, is about 0.77 eV higher than that of B3PYMPM, an electron-transporting host, and the HOMO energy of TCTA is about 0.94 eV higher than that of B3PYMPM. This shows that an exciplex may be efficiently formed without a process of directly transferring electrons from the electron-transporting host to the hole-transporting host, or directly transferring holes from the hole-transporting host to the electron-transporting host. On the other hand, the LUMO energy and the HOMO energy of BAlq are known to be 2.9 eV and 5.9 eV respectively. This shows that it is difficult to form an exciplex since an HOMO energy difference between TCTA and BAlq is about 0.07 eV in the light emitting layer of the OLED of the Comparative Example 1. Triplet energies of hole-transporting hosts, electron-transporting hosts, exciplexes and dopant materials respectively composing the light emitting layers of the OLEDs according to the Example 1 and Comparative Examples 1 and 2 are represented in the following Table 1, wherein the exciplexes were formed by mixing hole-transporting hosts and electron-transporting hosts with each other, and the triplet energies were obtained by calculating energies of lights having wavelengths corresponding to the photoluminescence spectra after measuring photoluminescence spectra using a charge-coupled device (Princeton Instruments; 7393-0005) to which an ND:YAG laser and a spectroscope (Acton Research Corporation; SpectraPro 2300i) were attached in a state that respective thin films were put into a cryostat and maintained at a temperature of 35K. TABLE 1Triplet energies of hole-transporting hosts, electron-transporting hosts, exciplexes and dopant materialsHole-Electron-transportingtransportingClassificationhosthostExciplexDopantExample 1TAPCB3PYMPMTAPC-Ir(ppy)2(acac)2.8 eV2.75 eVB3PYMPM2.37 eV2.51 eVComparativeTCTABAlq—Ir(ppy)2(acac)Example 12.8 eV2.2 eV—2.37 eVComparativeTCTABAlq—Ir(dmpq)2(acac)Example 22.8 eV2.2 eV—2.01 eV Referring to the Table 1, it can be seen that the triplet energy of the dopants are lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting hosts, and the triplet energy of the exciplex in the OLED according to the Example 1. It indicates that energy transfer from an exciplex formed in the light emitting layer to a phosphorescent dopant is possible in an OLED of Example 1. Meanwhile, it can be seen that the OLED of the Comparative Example 1 does not form an exciplex, the triplet energy of the dopant is higher than the triplet energy of the electron-transporting host, and the OLED of the Comparative Example 2 does not form an exciplex. FIGS.6A and6Bshowed the current density-voltage-luminance characteristics of the OLEDs according to the Examples 1 to 2 and the Comparative Examples 1 to 2 which were measured using a spectrophotometer (Photo research spectrophotometer; PR-650) and a power supplier (Keithley 2400). Referring toFIG.6A, it can be seen that the OLEDs according to the Examples 1 to 2 exhibit the lowest theoretical driving voltages by showing an turn-on voltage of about 2.4 V, a voltage corresponding to an energy gap that is almost the same as the photon energy of emitted green light divided by the elementary charge. Meanwhile, it can be seen that the OLEDs according to the Comparative Examples 1 to 2 respectively exhibit the turn-on voltages of about 4.5 V and about 3.6 V, respectively. This shows that the OLEDs according to the Examples 1 to 2 which form the exciplexes have lower driving voltages than the OLEDs according to the Comparative Examples 1 to 2 which do not form the exciplexes. Referring toFIG.6B, it can be seen that the OLEDs according to the Examples 1 to 2 have higher luminance values than the OLEDs according to the Comparative Examples 1 to 2. External quantum efficiencies and power efficiencies based on the measured current density-voltage-luminance data with respect to the OLEDs according to the Examples 1 to 2 and the Comparative Examples 1 to 2 were calculated, and the calculation results are illustrated inFIGS.7A and7B. Referring toFIG.7A, the OLED according to the Examples 1 and 2 exhibit very high external quantum efficiencies of about 27% to about 29%, and having external quantum efficiencies of about more than 27% at 10,000 cd/m2, the OLEDs according to the Examples 1 to 2 have very low efficiency roll-off characteristics. Meanwhile, the OLED according to the Comparative Example 1 exhibited a very low external quantum efficiency of about 1.1%, and the OLED according to the Comparative Example 2 exhibited an external quantum efficiency of about 20.5%. It may be predicted that the OLED according to the Comparative Example 1 exhibited a very low external quantum efficiency since the triplet energy of the dopant was higher than the triplet energy of the electron-transporting host. It can be seen from this that the OLEDs according to the Examples 1 to 2 have higher external quantum efficiencies than the OLEDs according to the Comparative Examples 1 to 2. Referring toFIG.7B, it can be seen that the OLEDs according to the Examples 1 to 2 have far higher power efficiencies than the OLEDs according to the Comparative Examples 1 to 2, and the OLEDs according to the Examples 1 to 2 have very high power efficiencies even at high luminance values. After integrating the results, voltages, external quantum efficiencies, and power efficiencies with respect to the OLEDs according to the Examples 1 to 2 and the Comparative Examples 1 to 2 are exhibited in the following Table 2. TABLE 2ExternalPowerquantumefficiencyVoltage (V)efficiency (%)(lm/W)@1000@1000@1000ClassificationDrivingcd/m2Maximumcd/m2Maximumcd/m2Example 12.43.227.126.8113.797.9Example 22.43.329.129.0119.1101.4Comparative4.510.51.10.52.50.4Example 1Comparative3.68.420.519.820.69.4Example 2 Referring to the Table 2, it can be seen that the OLEDs according to the Examples 1 to 2 have lower driving voltages, higher luminous efficiencies, and higher power efficiencies than the OLEDs according to the Comparative Examples 1 to 2, and the OLEDs according to the Examples 1 to 2 have very high power efficiencies at high luminance values. An OLED according to an aspect of the present disclosure has a low driving voltage and a high luminous efficiency and exhibits high efficiency characteristics at a high luminance value by using a hole-transporting host and an electron-transporting host that form an exciplex upon excitation. A display apparatus or a lighting device according to another aspect of the present disclosure may be used in a field requiring low voltage and high efficiency characteristics by including an OLED using a hole-transporting host and an electron-transporting host that form an exciplex upon excitation. It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more exemplary embodiments of the present disclosure have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims. | 40,674 |
11943946 | DETAILED DESCRIPTION Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description of the embodiments and the drawings, the same or similar elements are denoted by the same reference numerals throughout the specification. In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Further, the names of elements used in the following description of the embodiments of the present invention are selected in consideration of ease of preparation of the specification, and may thus differ from the names of parts of an actual product. Shapes, sizes, rates, angles and numbers disclosed in the drawings to describe the embodiments of the present invention are only exemplary and do not limit the present invention. In the following description of the embodiments, the terms “including”, “comprising” and “having” are to be interpreted as indicating the presence of one or more other characteristics, numbers, steps, operations, elements or parts stated in the specification or combinations thereof, and do not exclude the presence of characteristics, numbers, steps, operations, elements, parts or combinations thereof, or the possibility of adding the same, unless the term “only” is used. It will be understood that a singular expression encompasses a plural expression unless stated otherwise. In the interpretation of elements included in the various embodiments of the present invention, it is to be interpreted that the elements include error ranges unless stated otherwise. In the following description of the embodiments, it will be understood that, when positional relationships are expressed, for example, when an element is “on”, “above”, “under” or “beside” another element, the two elements may directly contact each other, or one or more other elements may be interposed between the two elements, unless the term “just” or “directly” is used. In the following description of the embodiments, it will be understood that, when temporal relationships are expressed, for example, when terms expressing a sequence of events, such as “after”, “subsequent to”, “next” and “before” are used, the terms encompass both a continuous relationship between the events and a discontinuous relationship between the events, unless the term “just” or “directly” is used. In the following description of the embodiments, it will be understood that, when the terms “first”, “second”, etc. are used to describe various elements, these terms are used merely to discriminate the same or similar elements. Therefore, a first element described hereinafter may be a second element without departing from the technical scope of the invention. Respective features of the various embodiments of the present invention may be partially or wholly coupled to or combined with each other and be technically variously interlocked or driven, and the respective embodiments may be implemented independently of each other or be implemented together through connection therebetween. In the following description of the embodiments, the “Lowest Unoccupied Molecular Orbital (LUMO) energy level” and the “Highest Occupied Molecular Orbital (HOMO) energy level” of a layer means a LUMO energy level and a HOMO energy level of a material occupying the majority of the weight of the corresponding layer, for example, a host material, unless they refer to the LUMO energy level and the HOMO energy level of a dopant material with which the corresponding layer is doped. In the following description of the embodiments, it will be understood that “the HOMO energy level” means an energy level measured through cyclic voltammetry (CV) in which an energy level is determined from a potential value relative to that of a reference electrode having a known electrode potential value. For example, the HOMO energy level of any material may be measured using ferrocene having a known oxidation potential value and reduction potential value, as a reference electrode. In the following description of the embodiments, the term “doped” means that the content of a material having properties different from a material occupying the majority of the weight of a corresponding layer (for example, materials having different properties being N-type and P-type materials or an organic material and an inorganic material), which is added to the material occupying the majority of the weight of the corresponding layer, is less than 20 wt %. In other words, a “doped” layer means a layer in which a host material and a dopant material may be discriminated from each other based on a ratio of the weight percents thereof. In addition, the term “undoped” means all cases other than the case corresponding to the term “doped”. For example, if a layer is formed of a single material or is formed of a mixture of materials having the same or similar properties, the layer may be an “undoped” layer. For example, if at least one of materials forming a layer is P-type and none of the materials forming the layer are N-type, the layer is an “undoped” layer. For example, if at least one of materials forming a layer is an organic material and none of of the materials forming the layer are inorganic materials, the layer is an “undoped” layer. For example, if all of the materials forming a layer are organic materials and at least one of the materials forming the layer is N-type and at least another of the other materials is P-type, when the content of the N-type material is less than 20 wt % or the content of the P-type material is less than 20 wt %, the layer is a “doped” layer. In the following description of the embodiments, an electroluminescence (EL) spectrum is calculated by multiplying (1) a photoluminescence (PL) spectrum, in which the intrinsic properties of a light emitting material, such as a dopant material or a host material included in an organic light emitting layer, are reflected, by (2) an out-coupling emittance spectrum curve which is determined by the structure and optical properties of an organic light emitting element including the thickness of organic layers, such as an electron transport layer. FIG.1is a cross-sectional view illustrating a white organic light emitting element according to a first embodiment of the present disclosure, andFIG.2is an energy band diagram between a hole transport layer and a red light emitting layer of a phosphorescent light emitting stack ofFIG.1according to an embodiment of the present disclosure. As shown inFIG.1, the white organic light emitting element according to the first embodiment of the present disclosure includes a first electrode110and a second electrode240arranged opposite each other on a substrate100, and an organic stack OS provided between the first electrode110and the second electrode240. The organic stack OS includes a plurality of light emitting stacks BS1, RGS, and BS2, and charge generation layers150and190provided between the light emitting stacks BS1, RGS, and BS2. Respective layers in the organic stack OS in the present disclosure may be layers including organic components as main components, and may further include inorganic matter, such as metal, as necessary so as to improve transfer of carriers or luminescence. Further, light emitted from respective light emitting layers of the light emitting stacks BS1, RGS, and BS2provided in the organic stack OS is combined and emitted towards any one of the first electrode110and/or the second electrode240, thus expressing white. When the first electrode110is a reflective electrode and the second electrode240is a transparent electrode, light is emitted towards the second electrode240, and when the first electrode110is a transparent electrode and the second electrode240is a reflective electrode, light is emitted towards the first electrode110. As circumstances require, when both the first and second electrodes110and240are transparent electrodes, light may be emitted in both directions. AlthoughFIG.1illustrates that a first blue light emitting stack BS1, a phosphorescent light emitting stack RGS, and a second blue light emitting stack BS2are sequentially stacked in a direction from the first electrode110to the second electrode240, the order thereof may be changed. Further, in order to express white, only two stacks, i.e., a blue light emitting stack and a phosphorescent light emitting stack, may be provided between the first and second electrodes110and240, or as circumstances require, four or more light emitting stacks may be provided. By varying the number of light emitting stacks depending on a required color temperature, color coordinate values may be changed to correspond to the color temperature for expressing a white color of the white organic light emitting element to be implemented. When the light emitting stacks are under constant conditions, the color temperature may be raised as the number of the light emitting stacks is increased. When three or more light emitting stacks are provided between the first and second electrodes110and240, two or more blue light emitting stacks BS may be provided. The blue light emitting stacks BS1and BS2have emission peaks at wavelengths of 440 nm to 480 nm, and the phosphorescent light emitting stack RGS has an emission peak at longer wavelengths than those of the blue light emitting stacks BS1and BS2and, for example, may include different kinds of light emitting layers having emission peaks at different green wavelengths and red wavelengths. The green wavelengths may have an emission peak at wavelengths of 500 nm to 540 nm and thus be emitted as pure green light, or have an emission peak at wavelengths of 540 nm to 580 nm and thus be emitted as yellowish green light, depending on the luminescence property of a green dopant. Further, the red wavelengths have an emission peak at wavelengths of 600 nm to 640 nm. Therefore, blue light emitted from the blue light emitting stacks BS1and BS2and green and red light emitted from the phosphorescent light emitting stack RGS are combined and emitted towards any one of the first electrode110and/or the second electrode240, thus implementing white light. The light emitting stacks BS1, RGS, and BS2include hole transport units120,160, and210, light emitting layers130,173/175, and220, and electron transport units140,180, and230, respectively. InFIG.1, the hole transport unit120of the first blue light emitting stack BS1includes a hole injection layer121, a first hole transport layer122, and a second hole transport layer123. The hole injection layer121is a layer of the organic stack OS which directly contacts the first electrode110formed of inorganic matter, which is a component of a transparent electrode or a reflective electrode, and lowers interfacial stress and an energy barrier when holes are injected from an interface with the first electrode110, so that the holes are smoothly injected into the organic stack OS. When the layer contacting the first electrode110belongs to another light emitting stack, for example, a phosphorescent light emitting stack RGS, the phosphorescent light emitting stack RGS may include a hole injection layer. Here, the first electrode110functions as an anode. The reason why the hole transport unit120of the first blue light emitting stack BS1includes the first and second hole transport layers122and123is to form a first optimal distance of blue light from the first electrode110, i.e., to generate resonance in which reflection and re-reflection are optimally repeated within the distance between the first electrode110and the second electrode240, and the configuration of these first and second hole transport layers122and123may be changed by the position of a reflective electrode selected from the first electrode110and the second electrode240and the thickness of a transparent electrode selected from the first electrode110and the second electrode240. In the hole transport unit120, the thicknesses of the first and second hole transport layers122and123may be changed, or any one of the first and second hole transport layers122and123may be omitted. Further, the first blue light emitting stack BS1includes a first blue light emitting layer130and a first electron transport layer140on the hole transport unit120. The first blue light emitting layer130, which is a light emitting layer provided on the first blue light emitting stack BS1, includes a host and a blue dopant which emits light by receiving energy through excitons generated in the host. The blue dopant may be a phosphorescent dopant or a fluorescent dopant, or include both thereof. In the following test examples, when the color coordinates of white were determined, the first and second blue light emitting layers130and220of the first and second blue light emitting stacks BS1and BS2, each of which includes a fluorescent blue dopant, were tested. However, the reason for this is that it was confirmed that, among blue dopants which have been developed, fluorescent blue dopants have a lifespan and efficiency of a designated level or more, and any phosphorescent blue dopant may be substituted for fluorescent blue dopant as long as the phosphorescent blue dopant has the same or similar lifespan and efficiency as the fluorescent blue dopant. In the white organic light emitting element of the present disclosure, the reason why the blue light emitting stacks BS1and BS2are provided separately from the phosphorescent light emitting stack RGS which emits light of longer wavelengths than blue light is to sufficiently implement blue light when a display device requires uniform color expression because the visual recognition efficiency of blue light is lower than those of other colors of light. The phosphorescent light emitting stack RGS located on the first blue light emitting stack BS1includes different kinds of light emitting layers. The phosphorescent light emitting stack RGS includes a third hole transport layer160, a red light emitting layer173, a green light emitting layer175, and a second electron transport layer180. In the phosphorescent light emitting stack RGS, the red light emitting layer173and the green light emitting layer175contact each other, the red light emitting layer173contacts the third hole transport layer160, and the green light emitting layer175contacts the second electron transport layer180. Each of the red light emitting layer173and the green light emitting layer175is a phosphorescent light emitting layer, and in order to maximize efficiency of excitons used to emit red and green light in the phosphorescent light emitting stack RGS, the excitons and carrier, such as holes and electrons, may be concentrated at the interface between the red light emitting layer173and the green light emitting layer175without biasing the carriers or the excitons (including singlet and triplet excitons) towards the first electrode110or the second electrode240. For this purpose, the white organic light emitting element of the present disclosure suggests the configuration of the red light emitting layer173and the green light emitting layer175, and the red light emitting layer173includes, as shown inFIG.2, a red dopant rd3having a HOMO energy level HOMO2lower than or equal to the HOMO energy level HOMO1of the adjacent third hole transport layer160. Further, the red dopant r3has the low HOMO energy level HOMO2and thus serves as electron acceptor and aids in a function of transporting electrons, and may be, for example, a compound of thienopyrimidine and a heavy metal, such as iridium or the like. However, the compound of thienopyrimidine and the heavy metal is only exemplary, and may be substituted with any dopant material which emits red light, has a HOMO energy level lower than the HOMO energy level HOMO1of the adjacent third hole transport layer160shown inFIG.2, and performs a function of smoothly transferring electrons to the inside of a light emitting layer without trapping the electrons. If the HOMO energy level HOMO2of the red dopant rd3is equal to or lower than the HOMO energy level HOMO1of the third hole transport layer160, transport of holes from the third hole transport layer160to the red light emitting layer173may be carried out normally without trapping the electrons, and thus, the holes may be transferred to the interface between the red light emitting layer173and the green light emitting layer175(inFIG.5) without accumulation of electrons at the interface between the third hole transport layer160and the red light emitting layer173, and concentration of excitons at the interface in the red light emitting layer173and the green light emitting layer175may be reinforced. Thereby, the excitons may be used to effectively emit light from the red light emitting layer173and the green light emitting layer175, and thus efficiency may be improved. Further, in the organic light emitting element of the present disclosure, trapping of holes in a low-current condition (at a low grayscale) is solved because the HOMO energy level HOMO2of the red dopant rd3is lower than the HOMO energy level HOMO1of the third hole transport layer160, excitons are concentrated at the same position or a similar position both at the low grayscale and the high grayscale, and thus, a change in the color coordinates of white, occurring due to a color property variation according to a current condition, may be prevented. Further, when there is a difference ΔHOMO between the HOMO energy level HOMO1of the third hole transport layer160and the HOMO energy level HOMO2of the red dopant rd3, the difference ΔHOMO may be 0.01 eV to 0.5 eV so as to reduce an interfacial barrier and acquire a stabilized material of the red dopant rd3. In addition, equality between the HOMO energy level HOMO1of the third hole transport layer160and the HOMO energy level HOMO2of the red dopant rd3may mean not only that the HOMO energy level HOMO1of the third hole transport layer160and the HOMO energy level HOMO2of the red dopant rd3are numerically completely equal to each other, but also that different materials of the third hole transport layer160and the red dopant rd3meet and influence each other at the interface therebetween and thus fluctuates within about ±0.2 eV from the intrinsic HOMO energy levels thereof. The red light emitting layer173includes electron transporting hosts reh1and reh2as hosts in addition to the red dopant rd3. Here, the red light emitting layer173prevents trapping of holes, is involved in the function of transporting electrons and thus does not require any separate hole transporting host, and may perform a function of transferring carriers including the holes and the electrons in the different kinds of light emitting layers173and175using only the electron transporting hosts reh1and reh2. As circumstances require, the red light emitting layer173may include a small amount of a hole transporting host. Further, the HOMO energy level HOMO2of the red dopant rd3may be higher that the HOMO energy levels HOMO3of the electron transporting hosts reh1and reh2, such that the red dopant rd3functions to aid in transport of holes. That is, the organic light emitting element of the present disclosure includes the phosphorescent light emitting stack RGS including the different kinds of light emitting layers173and175, in which the red light emitting layer173contacting the third hole transport layer160includes the red dopant rd3having the HOMO energy level HOMO2lower than or equal to the HOMO energy level HOMO1of the hole transport layer160, thereby allowing carriers, particularly, holes from the third hole transport layer160adjacent to the red light emitting layer173to be smoothly transported to the interface between the red light emitting layer173and the green light emitting layer175, without trapping the carriers by the red dopant rd3in the area of the red light emitting layer173adjacent to the hole transport layer160. Further, the red light emitting layer173of the phosphorescent light emitting stack RGS includes only the electron transporting hosts reh1and reh2, and one of the electron transporting hosts reh1and reh2may be the same as an electron transporting host in the green light emitting layer175. Consequently, a common material, i.e., the electron transporting host reh1or reh2, is distributed in both the red light emitting layer173and the green light emitting layer175of the phosphorescent light emitting stack RGS, and holes supplied from the third hole transport layer160are not stagnant in the red light emitting layer173but maintain a constant transfer rate. Particularly, in order to prevent an emission zone from being changed due to holes being pushed to the rear end of the heterogeneous light emitting layer configuration, i.e., a part thereof far away from the first electrode110, at the low grayscale (at the low current density) due to a difference in electric field dependencies between holes and electrons, when the red light emitting layer173includes only the electron transporting hosts reh1and reh2, the emission zone may be maintained at the interface between the red light emitting layer173and the green light emitting layer175. Therefore, even when a display device has a difference between the low grayscale and the high grayscale or displays the low grayscale or the high grayscale at different times, the display device may secure uniformity in the color coordinates of white and thus facilitate stable display. The second blue light emitting stack BS2includes the hole transport unit210, formed by stacking fourth and fifth hole transport layers213and215, the second blue light emitting layer220, and a third electron transport layer230. InFIG.1, the second electrode240may include inorganic compound components, i.e., LiF and Al, LiF may function as an electron injection layer, and Al may function as the second electrode240, i.e., a cathode. The electron injection layer is formed of a compound of alkali metal or alkali earth metal and a halogen element, and LiF may be substituted with any of various other materials. Alternatively, the electron injection layer may be omitted as circumstances require. Further, Al used to form the second electrode240is only exemplary, and may be substituted with any of various other metals into which electrons are easily injected. In some cases, the second electrode240may be formed by stacking a plurality of metal layers, only one of these metal layer may be formed of a reflective metal and the remainder may be formed of transparent metals, and in this case, the second electrode240may be formed by stacking a reflective metal layer and transparent metal layers. The charge generation layers150and190may be respectively formed by stacking n-type charge generation layers151and191contacting lower light emitting stacks adjacent thereto and p-type charge generation layers153and193contacting upper light emitting stacks adjacent thereto, as shown in these figures. However, this is only exemplary, and charge generation layers, in which electrons and holes are generated by doping one or more hosts with an n-type dopant and a p-type dopant, and are then supplied to adjacent stacks, may be provided. Although, in the embodiment shown inFIG.1, the first and second blue light emitting stacks BS1and BS2are located on the upper and lower surfaces of the phosphorescent light emitting stack RGS, the first and second blue light emitting stacks BS1and BS2are limited thereto, and the positions thereof may be changed as circumstances require. FIGS.3A and3Bare schematic cross-sectional views illustrating white organic light emitting elements according to other embodiments of the present disclosure. FIG.3Aillustrates a white organic light emitting element according to a second embodiment, and the white organic light emitting element includes a first blue light emitting stack BS1, a second blue light emitting stack BS2and a phosphorescent light emitting stack RGS, which are sequentially arranged between a first electrode110and a second electrode240. In this case, the phosphorescent light emitting stack RGS includes different kinds of light emitting layers, i.e., the red light emitting layer173and the green light emitting layer175, as shown inFIG.1, and may thus concentrate light emission at the interface between the red light emitting layer173and the green light emitting layer175regardless of current density and exhibit the uniform color coordinates of white. The above-described charge generation layers may be provided between the light emitting stacks BS1, BS2, and RGS. Further, a white organic light emitting element according to a third embodiment of the present disclosure, as shown inFIG.3B, includes a phosphorescent light emitting stack RGS, a first blue light emitting stack BS1, and a second blue light emitting stack BS2, which are sequentially arranged between a first electrode110and a second electrode240. In the white organic light emitting element according to the third embodiment, the phosphorescent light emitting stack RGS also includes different kinds of light emitting layers, i.e., the red light emitting layer173and the green light emitting layer175, as shown inFIG.1, and may thus concentrate light emission at the interface between the red light emitting layer173and the green light emitting layer175regardless of current density and exhibit uniform the color coordinates of white. The above-described charge generation layers may be provided between the light emitting stacks RGS, BS1, and BS2. In the white organic light emitting elements according to the second and third embodiments, the position of the light emitting layer in each light emitting stack may be set to a position where optimal resonance of the wavelength of light emitted by the light emitting layer occurs, and when the blue light emitting layers and other colored light emitting layers are located in the stacks arranged in an order different from the order shown inFIG.1between the first and second electrodes110and240, the distances between the respective light emitting layers and the first electrode110may be adjusted by changing the thickness of the adjacent charge generation layer150or190or the thicknesses of the hole transport units120and210. AlthoughFIGS.1,3A, and3Billustrate that the triple light emitting stack structure is provided between the first electrode110and the second electrode240, other blue light emitting stacks and/or other phosphorescent light emitting stacks may be further added in order to further improve luminous efficacy. Hereinafter, the functions and effects of the white organic light emitting element according to the present disclosure will be verified through various tests. In test examples other than third test examples, the triple light emitting stack structure shown inFIG.1was used, and elements other than the red light emitting layer and the green light emitting layer of the phosphorescent light emitting stack had the same structure. FIGS.4A and4Bare a cross-sectional view illustrating a heterogeneous light emitting layer configuration according to a first test example and an energy band diagram between a hole transport layer and a red light emitting layer therein, respectively. Further,FIG.5is a graph showing emission zones occurring at a low grayscale and a high grayscale in the heterogeneous light emitting layer configuration according to the first test example. In the first test example shown inFIG.4A, a red light emitting layer273and a green light emitting layer275brespectively included hole transporting hosts rhh and ghh and electron transporting hosts reh and geh. In the red light emitting layer273, the ratio of the hole transporting host rhh to the electron transporting host reh was 4:6, and the hole transporting host rhh and the electron transporting host reh were doped with a first red dopant rd1at a concentration of 3.5 wt %. Further, in the green light emitting layer275b, the ratio of the hole transporting host ghh to the electron transporting host geh was 6:4, and the hole transporting host ghh and the electron transporting host geh were doped with a green dopant gd at a concentration of 15 wt %. Here, the first red dopant rd1is a triphenylamine compound, as shown in Chemical Formula 1. Among the hole transporting host rhh, the electron transporting host reh and the first red dopant rd1included in the red light emitting layer273, the first red dopant rd1has a HOMO energy level HOMO4higher than that of a hole transport layer260by 0.3 eV or more, as shown inFIG.4B, and thus, when holes are transferred from the interface between the adjacent hole transport layer260and the red light emitting layer273, the holes introduced into the red light emitting layer273are no longer transferred and are trapped in the HOMO energy level HOMO4of the first red dopant rd1and are thus stagnant. Therefore, a higher driving voltage is required to push the stagnant holes towards the green light emitting layer275bso as to increase luminous efficacy of the green light emitting layer275b. Further, in the structure of the first test example, the holes trapped around the HOMO energy level HOMO4of the first red dopant rd1are difficult to be combined with electrons and may thus not be used for recombination with excitons, thereby deteriorating luminous efficacy of red light. Since such trapping of some holes is greatly influenced by an electric field density, there is a large difference in trapping of holes according to a difference in densities of current applied at the low grayscale and the high grayscale, thereby causing inversion of color coordinates between the low grayscale and the high grayscale. Therefore, as shown inFIG.5, excitons in the red light emitting layer273and the green light emitting layer275bare differently distributed at the low grayscale and the high grayscale, and emission zones at the low grayscale and the high grayscale are different. This means that the first test example cannot maintain uniform color coordinates according to a change in current density, and the white organic light emitting element according to the present disclosure aims to solve this problem through various changes in the configuration of different kinds of light emitting layers. FIGS.6A to6Care cross-sectional views illustrating a heterogeneous light emitting layer configuration according to second test examples, andFIG.7is an energy band diagram of the second test examples. In the second test examples, a red light emitting layer273having the same structure as in the first test example was used, i.e., a ratio of a hole transporting host rhh to an electron transporting host reh was 4:6, and the hole transporting host rhh and the electron transporting host reh were doped with a red dopant rd1at a concentration of 3.5 wt %, and green light emitting layers275a,275b, and275cin which a ratio of a hole transporting host ghh to an electron transporting host geh was varied (the second test example_A, the second test example_B and the second test example_C) were used. In the second test example_A, the second test example_B, and the second test example_C, the ratio of the hole transporting host ghh to the electron transporting host geh was set to 5:5, 6:4, and 7:3, respectively, and in each of the second test examples, the hole transporting host ghh and the electron transporting host geh were doped with a green dopant gd at a concentration of 15 wt %, in the same manner as in the first test example. In this case, in all the second test examples (the second test example_A, the second test example_B, and the second test example_C), the red dopant rd1has a higher HOMO energy level than the HOMO energy level of an adjacent hole transport layer260, and thus, holes tends to be trapped, similar to the above-described first test example. In the second test examples, a triphenylamine compound having a HOMO energy level of −5.0 eV was used as the red dopant rd1, and an amine-based material having a HOMO energy level of −5.2 eV was used as the adjacent hole transport layer260. In order to eliminate a hole-trapping tendency due to a HOMO energy level difference between the hole transport layer and the red dopant rd1used in in the red light emitting layer in the first and second test examples, the inventors of the present disclosure applied red dopants rd2and rd3formed of different materials to the red light emitting layer and observed a change in characteristics. FIG.8is a cross-sectional view illustrating a hole-only device (HOD) used in third test examples.FIG.9is an energy band diagram between a hole transport layer and a red light emitting layer in a third test example in which a third red dopant is applied to the red light emitting layer among the third test examples. Further,FIGS.10A to10Care graphs showing J-V characteristics according to a dopant concentration in the third test examples. In addition, Table shows driving voltage (V) measured by varying a current density to 0.1 mA/cm2, 1 mA/cm2, 5 mA/cm2, 10 mA/cm2, 15 mA/cm2, 20 mA/cm2, 30 mA/cm2, 40 mA/cm2and 50 mA/cm2, and varying the contents of first to third red dopants in the third test examples (the third test example_A, the third test example_B, and the third test example_C). In the third test examples, a hole-only device (HOD) shown inFIG.8was manufactured so as to observe J-V characteristics (a change in current density in response to driving voltage) according to a change in the red dopant. As shown inFIG.8, the HOD is an element in which a first electrode310formed of ITO, a hole injection layer320, a hole transport layer330, a red light emitting layer353, and a second electrode380formed of Al are stacked such that only a change in transport of holes is observed. In the third test examples, hole transferring characteristics between the hole transport layer330and the red light emitting layer353depending on application of current were examined by applying a voltage to the first electrode310and the second electrode380of the HOD ofFIG.8. The J-V characteristics were examined, as shown inFIGS.10A to10C, under the condition that the red light emitting layer353includes a hole transporting host rhh formed of the same material as the hole transport layer330and an electron transporting host reh having high electron mobility at a ratio of 4:6, different dopants, i.e., the first to third red dopants rd1, rd2, and rd3, are used, and the amount of each dopant is varied. The first red dopant rd1used inFIG.10Ais the compound shown in Chemical Formula 1, and the second red dopant rd2used inFIG.10Bis a compound which has a different methyl group at a terminal of a triphenylamine monomer combined with iridium, unlike the compound shown in Chemical Formula 1, as shown in Chemical Formula 2, and shows properties almost similar to those of the compound shown in Chemical Formula 1. Therefore, the second red dopant rd2has a HOMO energy level higher than the HOMO energy level of the hole transport layer330adjacent thereto in the phosphorescent light emitting stack, similar toFIG.7, and thus the second red dopant rd2has a hole-trapping tendency. Further, the third red dopant rd3used inFIG.10Cis a compound of thienopyrimidine and iridium, unlike the triphenylamine monomer and influences the phenyl group affecting the HOMO energy level due to thienopyrimidine functioning as a strong acceptor, and thereby, has a low HOMO energy level. Therefore, holes transferred from the hole transport layer330adjacent to the red light emitting layer353are not trapped by the third red dopant rd and may pass through the red light emitting layer353. In the first and second red dopants rd1and rd2having HOMO energy levels higher than that of the hole transport layer adjacent thereto, as shown inFIGS.10A and10Band Table 1, when the content of each dopant is increased to 2 wt %, 3 wt %, and 4 wt %, the hole-trapping tendency becomes severe, and thereby, hole mobility is reduced and a driving voltage (V) at the same current density tends to be gradually increased. Here, the HOMO energy levels of the first and second red dopants rd1and rd2are −5.0 eV. On the other hand, in the third red dopant rd3having the HOMO energy level of about −5.3 eV, as shown inFIG.10Cand Table 1, even when the content of the third red dopant rd3is varied to 2 wt %, 3 wt % and 4 wt %, a driving voltage (V) at the same current density tends to be almost uniform. This means that holes are not trapped in a specific area of the red light emitting layer353and thus the holes may be transferred normally when the third red dopant rd3is used, and thus means that the element may be stably driven at a low driving voltage. TABLE 13rdtest3rdtest3rdtestCurrentexample_Aexample_Bexample_Cdensity(rd1) [wt %](rd2) [wt %](rd3) [wt %][mA/cm2]2342342340.15.45.55.73.23.53.521.8216.36.56.94.34.44.62.32.32.457.47.88.35.45.96.62.82.82.91078.4966.87.33.13.13.2158.38.89.46.47.27.83.33.33.4208.69.19.76.77.58.23.43.43.53099.5107.188.63.73.73.8409.39.9107.48.38.63.83.93.9509.510107.78.68.6444.1 From Table 1 andFIGS.10A to10C, it may be confirmed that, even when the third red dopant rd3is applied to the red light emitting layer including the hole transporting host and the electron transporting host, the third red dopant rd3does not restrict mobility of holes supplied from the hole transport layer, and particularly, the content of the third red dopant rd3in the red light emitting layer does not greatly contribute to an increase in driving voltage. FIGS.11A to11Care cross-sectional views illustrating heterogeneous light emitting layer configurations according to fourth test examples, andFIGS.12A to12Care graphs showing white color coordinate characteristics depending on a change in current density in the fourth test examples. Further,FIGS.13A to13Care graphs showing white spectra according to wavelength, depending on the change in current density in the fourth test examples. As shown inFIGS.11A to11C, a red light emitting layer273having the same structure as in the second test examples was used, and exhibits the same energy band diagram characteristics between a hole transport layer260and the red light emitting layer273as inFIG.7. That is, in the red light emitting layer273, the ratio of a hole transporting host rhh to an electron transporting host reh was 4:6, and the hole transporting host rhh and the electron transporting host reh were doped with a red dopant rd1at a concentration of 3.5 wt %. Further, in green light emitting layers275a,275band275c, the ratio of a hole transporting host ghh to an electron transporting host geh was set to 7:3, and the content of a green dopant in each of the green light emitting layers275a,275band275cwas varied to 15 wt %, 10 wt %, and 5 wt %. In this case, in all the fourth test examples (the fourth test example_A, the fourth test example_B, and the fourth test example_C), the red dopant rd1has a higher HOMO energy level than the HOMO energy level of an adjacent hole transport layer260, as shown inFIG.7, and thus, holes tend to be trapped in the HOMO energy level of the red dopant rd1, similar to the above-described first test example. Further, in the fourth test example_A, as shown inFIG.12A, as the current density increases, the CIEy value is greatly changed but the CIEx value is insignificantly changed. This means that the color coordinates of white at a low current density and a high current density are different, and it may be expected that when a display is implemented, a white color will be expressed non-uniformly in different areas. As shown inFIG.13A, when the white spectrum is observed while increasing the current density in the fourth test example_A, particularly, when an emission peak at red wavelengths is examined, a peak intensity at a current density of 5 mA/cm2is increased by 40% from a peak intensity at an initial current density of 0.25 mA/cm2, and thus, it may be confirmed that a change in red light relative to green light greatly influences the color coordinates of white. Further, in the fourth test example_B, as shown inFIG.12B, it may be confirmed that the CIEy value and the CIEx value are similarly changed at a current density of 10 mA/cm2of higher, as shown inFIG.13B, unlike the fourth test example_A. However, a color coordinate change in the CIEy value becomes great at a low current density of less than 10 mA/cm2, and thus, it may be expected that that the color coordinates of white at a low current density and a high current density are different. In this case, as shown inFIG.13B, when the white spectrum is observed while varying the current density to 0.25 mA/cm2, 1.25 mA/cm2, 2.25 mA/cm2, 3.25 mA/cm2, 4.25 mA/cm2and 5 mA/cm2in the fourth test example_B, particularly, when an emission peak at red wavelengths is examined, a peak intensity at a current density of 5 mA/cm2is increased by 24% from a peak intensity at an initial current density of 0.25 mA/cm2, and thus, it may be confirmed that a change in red light relative to green light influences the color coordinates of white to a certain extent even if less than in the fourth test example_A. Further, in the fourth test example_C, as shown inFIG.11C, it may be confirmed that the CIEy value and the CIEx value are changed similarly at a low current density and a high current density, i.e., at a current density of 10 mA/cm2or higher, as shown inFIG.12C, unlike the fourth test example_A and the fourth test example_B. In this case, as shown inFIG.13C, when the white spectrum is observed while varying the current density to 0.25 mA/cm2, 1.25 mA/cm2, 2.25 mA/cm2, 3.25 mA/cm2, 4.25 mA/cm2, 5 mA/cm2in the fourth test example_C, particularly, when an emission peak at red wavelengths is examined, a peak intensity at a current density of 5 mA/cm2is increased from a peak intensity at an initial current density of 0.25 mA/cm2by 9%, and thus, it may be confirmed that a change in red light according to a current density is reduced even in the low-current density condition, compared to the fourth test example_A and the fourth test example_B. Thereby, it may be expected that green light and red light are changed similarly even at the low current density and thus more stable white color coordinate characteristics may be acquired. This means that, under the condition that the same host in the red light emitting layer is doped with the same red dopant, when the content of the green dopant in the green light emitting layer provided on the red light emitting layer is reduced, a change in green light and a change in red light according to a change in the current density in the the color coordinates of white may be relatively reduced. Further, in the above-described fourth test examples, for example, when the the color coordinates of white of the fourth test example_C, in which a change in red light in the white spectrum according to a change in current density is small, is examined, the color coordinates of white at a current density of about 20 mA/cm are (0.275, 0.245), indicating a reddish tendency, and thus, it may be confirmed that it is difficult to satisfy the color temperature of white required by a display device. Therefore, test examples, in which uniformity in the color coordinates of white according to a change in current density may be secured and a cool color temperature required by the display device may be expressed, are considered. FIG.14is an energy band diagram between a hole transport layer and a red light emitting layer in fifth and sixth test examples. That is, in the fifth and sixth test examples, as shown inFIG.14, as considered in the white organic light emitting element according to the present disclosure, a red light emitting layer of a phosphorescent light emitting stack uses a third red dopant rd3having a HOMO energy level lower than or equal to the HOMO energy level of a hole transport layer adjacent to the red light emitting layer so as to obtain a hole trapping prevention effect, and uses only electron transporting hosts reh1and reh2so as to concentrate generation of excitons at the interface between the red light emitting layer and a green light emitting layer by adjusting a hole moving speed when holes are transported. That is, in the fifth and sixth test examples, the red light emitting layer273is configured such that a mixture of a first-type electron transporting host reh1and a second-type electron transporting host reh2is doped with the third red dopant rd3. Here, the HOMO energy levels HOMO3of the first and second-type electron transporting hosts reh1and reh2are lower than the HOMO energy level HOMO2of the third red dopant rd3, and the LUMO energy levels of the first and second-type electron transporting hosts reh1and reh2are lower than the LUMO energy level of the adjacent hole transport layer160so as to restrict transfer of electrons to the inside of the red light emitting layer373. Both the first and second-type electron transporting hosts reh1and reh2are compounds having a triazine core, as shown in Chemical Formula 4, i.e., materials having electron mobility higher than hole mobility. The first-type electron transporting host reh1has electron mobility of 2.3×10−6cm2V−1s−1, the second-type electron transporting host reh2has electron mobility of 1.0×10−5cm2V−1s−1, and the electron mobility of the second-type electron transporting host reh2is five times greater than the electron mobility of the first-type electron transporting host reh1. However, this is only exemplary, electron transporting hosts having different electron mobilities may be used in the red light emitting layer373. Further, the number of electron transporting hosts used in the red light emitting layer373is not limited to two, and a larger number of electron transporting hosts may be included in the red light emitting layer373. The suggested examples are only examples, and besides triazine core compounds, any other compounds, which have HOMO energy levels lower than the HOMO energy levels of the adjacent hole transport layer160and the red dopant rd3and have electron transporting properties, may be used as hosts. FIGS.15A to15Fare graphs showing white color coordinate characteristics depending on a change in current density in the fifth test examples (Ex_A, Ex_B, Ex_C, Ex_D, Ex_E and Ex_F). Further,FIG.16is a graph showing luminous efficacies of red, green, and blue in the fifth test examples, andFIG.17is a graph showing lifespans of emission of red, green, and blue in the fifth test examples.FIG.18is a graph showing driving voltages in the fifth test examples. FIGS.15A to15Fillustrate the fifth test examples_A, B, C, D, E, and F, in which the ratio of the first-type electron transporting host reh1to the second-type electron transporting host reh2was set to 1:0, 8:2, 6:4, 4:6, 2:8 and 0:1, respectively, in the relationship between the hole transport layer160and the red light emitting layer373having the energy band diagram shown inFIG.14. In the direction from the fifth test example_D to the fifth test example_E and the fifth test example_F, the current density at which a CIEy value and a CIEx value are equal is gradually reduced. As the content of the first-type electron transporting host reh1is decreased, the luminous efficacy of green is partially reduced but stability is maintained, as shown inFIG.16, and thus, the lifespan of emission of green is gradually increased, as shown inFIG.17. Particularly, the lifespans of both the red light emitting layer and the green light emitting layer, forming the heterogeneous light emitting layer configuration, are improved. Further, as shown inFIG.18, it may be confirmed that when the red light emitting layer273adjacent to the hole transport layer160includes only the electron transporting hosts reh1and reh2, driving voltage is less than 15V (in the same manner in the white organic light emitting element shown inFIG.1) in all the fifth test examples. It may be confirmed that, when the red light emitting layer arranged adjacent to the hole transport layer includes only electron transporting hosts and a red dopant having a HOMO energy level lower than that of the hole transport layer in the heterogeneous light emitting layer configuration, all of efficacy, lifespan, driving voltage, and stability may be improved. FIG.19is a cross-sectional view illustrating a heterogeneous light emitting layer configuration according to the sixth test example, andFIG.20is a graph showing emission zones occurring at a low grayscale and a high grayscale in the heterogeneous light emitting layer configuration according to the sixth test example.FIG.21is a graph showing white color coordinate characteristics depending on a change in current density in the sixth test example. As shown inFIG.19, considering that in the fifth test examples, when the ratio of the first-type electron transporting host reh1to the second-type electron transporting host reh2is 6:4 and 4:6, the CIEx and CIEy values satisfy the cool color coordinates of white and inversion between the CIEx and CIEy is not caused as the current density increases, in the heterogeneous light emitting layer configuration according to the sixth test example, the ratio of the first-type electron transporting host reh1to the second-type electron transporting host reh2in a red light emitting layer373was set to 5:5, as the optimal configuration. In this case, as shown inFIG.11C, the ratio of a hole transporting host ghh to an electron transporting host geh in a green light emitting layer375was set to 7:3, and the content of a green dopant in the green light emitting layer375was set to 5 wt %. In this case, in the sixth test example, as shown inFIG.20, excitons are mainly concentrated at the interface between the red light emitting layer173and the green light emitting layer175, an emission zone occurs at the interface, and the emission zone may be maintained at the center of the red light emitting layer or the green light emitting layer without moving therefrom regardless of a change in the current density, and thus, it may be confirmed that the color coordinates of white are uniformly expressed. Further, from the graph ofFIG.21showing the white color coordinate characteristics according to the change in current density in the sixth test example, it may be confirmed that the CIEx and CIEy values are uniformly changed and thus uniform and stable expression of white is facilitated. Hereinafter, in the above-described first to second test examples and fourth to sixth test examples to which the white organic light emitting element is applied, except for the third test examples to which the HOD is applied, luminous efficacies of red and green, color coordinates, driving voltage, and lifespans of emission of red and green when luminance is reduced to 95% of the luminance at an initial state will be described. In the first test example, it may be confirmed from Table 2 that luminous efficacy of green is excellent but driving voltage is high, a change in the emission zone at the low grayscale and the high grayscale is great, as shown inFIG.5, and the great change in the emission zone means a change in the color coordinates of white according to a change in current density and thus causes difficulty stably expressing white. In the second test examples and the fourth test examples having the same red light emitting layer as in the first test example, the contents of the hosts in each green light emitting layer were varied or the content of the green dopant in each green light emitting layer was varied. In the second test examples, as the content of the hole transporting host in the green light emitting layer is increased, luminous efficacy of green is raised, but driving voltage is also raised, and thus the lifespan of emission of green light is gradually reduced. In the fourth test examples, as the content of the green dopant is deceased, the luminous efficacy of red is raised and the lifespan of emission of red light is improved. Particularly, in the fourth test example_C in which the content of the green dopant is 5 wt %, roll-off of green and red light is greatly improved. However, in this case, the color coordinates of white are (0.275, 0.245), indicating a reddish tendency, and thus, it may be confirmed that it is difficult to express cool white. In the fifth examples, different electron transporting hosts reh1and reh2and the third red dopant are used, there is not much change in roll-off in an initial stage, but there is a difference between luminous efficacy of red and luminous efficacy of green and there is a difference between the lifespan of emission of red and the lifespan of emission of green. It may be confirmed that, as the content of the first-type electron transporting host reh1is decreased, luminous efficacy of green is reduced but the lifespan of emission of green is improved. The sixth test example, which is the most improved example, and, in which the ratio of the first-type electron transporting host reh1to the second-type electron transporting host reh2(reh1:reh2) was set to 1:1 and the first-type and second-type electron transporting hosts reh1and reh2were doped with the third red dopant rd3, is applied to the white organic light emitting element ofFIG.1. In this case, it may be confirmed that driving voltage is reduced to 14.9 V which is 94% of the driving voltage in the first test example, the color coordinates (CIEx, CIEy) of white are (0.267, 0.280) and thus more cool white may be expressed, and luminous efficacy of red is relatively improved. Particularly, it may be confirmed that, when the sixth test example is applied, the color coordinates of white are uniform regardless of a change in current density, as shown inFIG.21. TABLE 2EfficacyDrivingLifespan(Cd/A)voltage(T95)Test examplerdRGCIExCIEy(V)RG1stexamplerd16.824.70.2710.29915.81402102ndexample Ard17.817.50.2760.26014.81802002ndexample Brd17.319.70.2750.27615.31402002ndexample Crd16.323.70.2690.29915.9851603rdexample Ard16.227.20.2660.30815.9751003rdexample Brd17.621.60.2710.27715.71402103rdexample Crd18.616.60.2750.24515.51402605thexample Ard36.126.50.2680.30814.9981165thexample Brd36.126.60.2660.30614.91161225thexample Crd36.226.30.2660.30314.9981225thexample Drd36.425.00.2670.29714.81071425thexample Erd36.424.00.2660.29214.81261515thexample Frd36.522.60.2670.28514.91281606thexamplerd37.322.40.2670.28014.9123170 Hereinafter, an example in which the above-described white organic light emitting element is applied to a display device will be described. FIG.22is a cross-sectional view illustrating a display device including a white organic light emitting element according to the present disclosure. As shown inFIG.22, the display device according to the present disclosure may include a substrate100having a plurality of subpixels R_SP, G_SP, B_SP, and W_SP, the white organic light emitting element OLED shown inFIG.1which is provided in common in the subpixels R_SP, G_SP, B_SP, and W_SP of the substrate100, a thin film transistor TFT provided in each of the subpixels R_SP, G_SP, B_SP, and W_SP and connected to the first electrode110of the white organic light emitting element OLED, and a color filter layer109R,109G, and109B which is provided under the first electrode110of at least one of the subpixels R_SP, G_SP, B_SP, and W_SP. Although this example illustrates that the display device includes the white subpixel W_SP, the disclosure is not limited thereto, and the display device may have a structure including only the red, green, and blue subpixels R_SP, G_SP, and B_SP without the white subpixel W_SP. As circumstances require, a combination of a cyan subpixel, a magenta subpixel, and a yellow subpixel, which are combined to express white, may be used as a substitute for the red, green and blue subpixels R_SP, G_SP, and B_SP. The thin film transistor TFT includes, for example, a gate electrode102, a semiconductor layer104, and a source electrode106aand a drain electrode106bconnected to both sides of the semiconductor layer104. A gate insulating film103is provided between the gate electrode102and the semiconductor layer104. The semiconductor layer104may be formed of, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, or a combination of two or more thereof. For example, if the semiconductor layer104is formed of an oxide semiconductor, an edge stopper105directly contacting the upper surface of the semiconductor layer104may be further provided so as to prevent damage to a channel region of the semiconductor layer104. Further, the drain electrode106bof the thin film transistor TFT may be connected to the first electrode110by a contact hole CT formed through first and second protective films107and108. The first protective film107is provided so as to primarily protect the thin film transistor TFT, and color filters109R,109G, and19B may be provided on the upper surface of the first protective film107. When the subpixels include the red subpixel R_SP, the green subpixel G_SP, the blue subpixel B_SP, and the white subpixel W_SP, first and third color filters109R,109G and109B divided from the color filter layer are provided in the remaining subpixels R_SP, G_SP, and B_SP, except for the white subpixel W_SP, and transmit respective wavelengths of white light emitted via the first electrode110. Further, the second protective film108is provided on the lower surface of the first electrode110so as to cover the first to third color filters109R,109G, and109B. The first electrode110is formed on the surface of the second protective film108except for the contact holes CT. Here, the white organic light emitting element OLED may include the first electrode110which is a transparent electrode, the second electrode120which is a reflective electrode arranged opposite the first electrode110, and a two-stack structure including a blue light emitting stack S1and a long-wavelength (R/G or YG) (phosphorescent) light emitting stack S2, or a three-stack structure including the first blue light emitting stack BS1, the phosphorescent light emitting stack RGS and the second blue light emitting stack BS2, as shown inFIGS.1,3A, and3B. Otherwise, at least one of the above-described blue light emitting stack or phosphorescent light emitting stack may be provided in plural as an organic stack OS, and a charge generation layer may be provided between the respective light emitting stacks. In this case, the plurality of light emitting stacks may have the same structure. Here, reference numeral119which is not described indicates banks, and BH between the banks119indicates bank holes. Light is emitted through an open area in the bank hole BH, and the bank hole BH defines an emission area of each subpixel. For example, the display device shown inFIG.22may be a bottom emission-type display device. However, the display device according to the present disclosure is not limited thereto, and may be implemented as a top emission-type display device by locating the color filter layer on the upper surface of the second electrode240, forming the first electrode110of a reflective metal and forming the second electrode110of a transparent metal or a transflective metal in the structure of the display device shown inFIG.22. Otherwise, a transparent organic light emitting element may be implemented by providing or omitting the color filter layer and embodying the first and second electrodes110and240as transparent electrodes. In the white organic light emitting element and the display device using the same according to the present disclosure, the phosphorescent light emitting stack including different kinds of light emitting layers contacting each other is changed so as to compensate for different mobility tendencies of holes and electrons in response to an electric field change. If the white organic light emitting element is driven under the condition that higher dependency of electrons than dependency of holes on an electric field change is not compensated for, an emission zone is reversed according to a current density, and consequently, a uniform white spectrum or uniform color coordinates according to the current density may not be acquired, thus causing a panel defect. In the present disclosure, in order to compensate for this, the red dopant included in the red light emitting layer has a HOMO energy level lower than the HOMO energy level of the hole transport layer adjacent to the red light emitting layer so that holes are not trapped in a specific area in the red light emitting layer, thus maintaining a consistent emission zone at the interface between the red light emitting layer and the green light emitting layer of the heterogeneous light emitting layer configuration. Therefore, carriers are not trapped by the red dopant in the area of the red light emitting layer adjacent to the hole transport layer, and the carriers may be smoothly transported to the interface between the red light emitting layer and the green light layer. Further, since electron transporting hosts are used as hosts included in the red light emitting layer, a change in the transfer rate of carriers, such as holes and electrons, in the red light emitting layer is effectively reduced, and thus, the emission zone may be uniformly maintained regardless of a change in current density. Therefore, the emission zone may be maintained without change at the interface between the red light emitting layer and the green light emitting layer, and thus, uniformity in the color coordinates of white may be ensured despite the change in current density. A white organic light emitting element according to one embodiment of the present disclosure may include a first electrode and a second electrode arranged opposite each other, and at least one blue light emitting stack and a phosphorescent light emitting stack, provided between the first electrode and the second electrode and separated from each other by a charge generation layer, the phosphorescent light emitting stack may include a hole transport layer, a red light emitting layer, a green light emitting layer, and an electron transport layer, and the red light emitting layer may include a red dopant having a HOMO energy level lower than or equal to a HOMO energy level of the hole transport layer, and a red host. The red host may include an electron transport host. Also, in some cases, the red host may exclusively include electron transporting hosts. The electron transporting hosts may be compounds having a triazine core. The electron transporting hosts in the red light emitting layer may include a first-type host and a second-type host having different electron mobilities, and HOMO energy levels of the first-type host and the second-type host may be lower than the HOMO energy level of the red dopant. The red dopant may be a compound of thienopyrimidine and iridium. A content of the red dopant in the red light emitting layer may be 1 wt % to 10 wt %, and a content of a green dopant in the green light emitting layer may be 3 wt % to 10 wt %. The red light emitting layer and the green light emitting may contact each other, the green light emitting layer may include a hole transporting host, an electron transporting host and the green dopant, and a content of the hole transporting host in the green light emitting layer may be higher than a content of the electron transporting host in the green light emitting layer. Any one of the electron transporting hosts in the red light emitting layer may be equal to the electron transporting host in the green light emitting layer. The at least one blue light emitting stack may be provided in plural between the first electrode and the second electrode. Each of the blue light emitting stacks may be provided on or under the phosphorescent light emitting stack, or be provided adjacent to the first electrode or the second electrode with the charge generation layer interposed between each of the blue light emitting layers and the phosphorescent light emitting layer. The red light emitting layer may have an emission peak at wavelengths of 600 nm to 640 nm, and the green light emitting layer may have an emission peak at wavelengths of 500 nm to 540 nm. Otherwise, the red light emitting layer may have an emission peak at wavelengths of 600 nm to 640 nm, and the green light emitting layer may have an emission peak at wavelengths of 540 nm to 580 nm. A display device according to the present disclosure so as to achieve the same objects may include a substrate including a thin film transistor provided in each of a plurality of subpixels, a first electrode connected to the thin film transistor in each subpixel, and a second electrode spaced apart from the first electrode and provided throughout the subpixels, and at least one blue light emitting stack and a phosphorescent light emitting stack, provided between the first electrode and the second electrode and separated from each other by a charge generation layer, the phosphorescent light emitting stack may include a hole transport layer, a red light emitting layer, a green light emitting layer and an electron transport layer, and the red light emitting layer may include a red dopant having a HOMO energy level lower than or equal to a HOMO energy level of the hole transport layer, and red hosts. The red hosts may include electron transporting hosts. The display device may further include color filters separated by the subpixels and provided under the first electrodes or on the second electrode so as to transmit light having passed through the first electrodes or the second electrode to produce different colored light between adjacent subpixels. As is apparent from the above description, a white organic light emitting element and a display device using the same according to the present disclosure have the following effects. In a phosphorescent light emitting stack including different kinds of light emitting layers, a red light emitting layer contacting a hole transport layer includes a red dopant having a HOMO energy level lower than or equal to the HOMO energy level of the hole transport layer, thereby preventing carriers from being trapped by the red dopant in the area of the red light emitting layer adjacent to the hole transport layer and thus allowing the carriers to be smoothly transported to the interface between the red light emitting layer and a green light layer. Further, because electron transporting hosts are used as hosts included in the red light emitting layer in addition to the red dopant, a change in the transfer rate of the carriers, such as holes and electrons, in the red light emitting layer is effectively reduced, and thus, an emission zone may be uniformly maintained regardless of a change in current density Therefore, the emission zone may be maintained without change at the interface between the red light emitting layer and the green light emitting layer, and thus, uniformity in the color coordinates of white may be ensured despite the change in current density. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. | 67,856 |
11943947 | DESCRIPTION OF EMBODIMENTS The following will describe embodiments of the disclosure with reference to drawings. The disclosure may be implemented in various forms without departing from its spirit and main features. Therefore, the following embodiments and examples are for illustrative purposes only in every respect and should not be subjected to any restrictive interpretations. EMBODIMENTS FIG.1is a schematic diagram of an exemplary cross-sectional structure of a light-emitting device in accordance with an embodiment of the disclosure. Referring toFIG.1, a light-emitting device1includes a substrate10, an anode11, a hole transport layer12, a light-emitting layer13, an electron transport layer14, and a cathode15in this sequence when viewed from the lower layer. The anode11resides on the substrate10and is electrically connected to a TFT (not shown) on the substrate10. Throughout the following description, the direction from the substrate10toward the light-emitting layer13will be referred to as the upward direction whereas the direction from the light-emitting layer13toward the substrate10will be referred to as the downward direction. The present embodiment assumes that the light-emitting device1is a bottom-emission type where the light-emitting layer13emits light that exits the light-emitting device1downward. The light-emitting layer13is composed of quantum dots and may alternatively be composed of an organic light-emitting material. The substrate10is made of, for example, glass or flexible resin such as polyimide and is highly transparent. When the light-emitting device1is a top-emission type where the light-emitting layer13emits light that exits the light-emitting device1upward, the substrate10may be made of, for example, plastics and poorly transparent. The anode11is composed of a conductive material that has a large work function (e.g., roughly equivalent to the valence band of the hole transport layer12) such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony-doped tin oxide (ATO), or fluorine-doped tin oxide (FTO). The anode11is transparent. The anode11is formed by, for example, sputtering, vapor deposition, or printing. The hole transport layer12transports holes fed from the anode11to the light-emitting layer13. The hole transport layer12contains a metal oxide and carbon atoms in a prescribed, adjusted ratio. The term, “metal oxide,” in the present specification is used in a broad sense of the term, referring to oxides of metals including insulating oxides, conductive oxides (including transparent conductive oxides), and semiconducting oxides. The term, “ratio” or “content ratio,” in the present specification refers to the ratio of the carbon atom content of the hole transport layer12to the metal atom content of the hole transport layer12(carbon atoms/metal atoms) and is expressed in percent. The metal oxide in the hole transport layer12is produced by dissolving, for example, a metal oxide precursor such as an organic acid salt of a metal or a metal complex of an organic compound in a solvent to prepare a coating solution, applying the coating solution to the anode11, and then baking the solution in an atmosphere of oxygen, nitrogen, argon, or a mixture thereof. In this example, the carbon atoms in the hole transport layer12are contained, for example, in the metal oxide precursor that remains after the baking. The solvent in which the metal oxide precursor is dissolved in the example is, for example, an ethanol-based organic solvent. The coating solution can be applied by any method and may be applied by, for example, spin-coating. The hole transport layer12has a thickness of, for example, 5 to 100 nm. The metal oxide in the hole transport layer12may be produced by preparing a dispersion solution containing metal oxide nanoparticles dispersed in a solvent such as ethanol, applying the dispersion solution to the anode11by spin-coating, and evaporating and drying out the solvent. The metal oxide nanoparticles are synthesized in advance from, for example, a metal oxide precursor such as an organic acid salt of a metal or a metal complex of an organic compound in such a manner that the resultant metal oxide nanoparticles contain carbon atoms in a prescribed, adjusted ratio. The metal oxide in the example is composed primarily of, for example, NiO, LaNiO3, Cr2O3, Ni1-xMgxO (0.0<x≤0.9), or Cu2O. The metal oxide may additionally contain an oxide of, for example, Li, Ni, Cu, Mg, Al, or Ti in 20% or less, to increase the hole transport efficiency from the hole transport layer12to the light-emitting layer13. The metal oxide precursor in the example is, for example, a substance capable of producing, for example, an amorphous or crystalline thin film of metal oxide. Specifically, as an example, when the metal oxide is NiO, the metal oxide precursor is, for example, nickel acetate or nickel acetylacetonate. The prescribed carbon content ratio of the hole transport layer12is preferably 1.2% or higher as achieved, for example, by the common 400° C. baking described in WO2016/136729. If the carbon content ratio is 1.2% or lower, for example, many excitons are quenched by the hole transport layer12, possibly leading to low luminance and luminous efficiency. The prescribed carbon content ratio is preferably less than 23.8% as achieved by 180° C. baking. If the carbon content ratio is 23.8% or higher, for example, no metal oxide may be produced, possibly leading to no current flow in the light-emitting device1. Furthermore, to obtain the light-emitting device1that achieves high luminance and high luminous efficiency at low voltage, the prescribed carbon content ratio is more preferably from 1.5% to 6.0%, both inclusive, as achieved by 330° C. baking and 200° C. baking respectively and even more preferably from 2.1% to 4.2%, both inclusive, as achieved by 280° C. baking and 230° C. baking respectively, as will be demonstrated later in examples. The hole transport layer12may have a carbon concentration that is constant in a thickness direction thereof. This particular structure, for example, enables the hole transport layer12to achieve a good balance across the thickness thereof between the N O's function of increasing hole transport efficiency and the carbon's function of restraining exciton quenching. The structure hence further improves the luminance and luminous efficiency of the light-emitting device1. The hole transport layer12may have a carbon concentration that increases toward the light-emitting layer13. This particular structure, for example, imparts, to the hole transport layer12, a carbon content that increases toward the light-emitting layer13, thereby increasingly better restraining exciton quenching as moving toward the light-emitting layer13where excitons are likely to be quenched and also imparts, to the hole transport layer12, a NiO content that increases farther from the light-emitting layer13, thereby achieving increasingly higher hole transport efficiency as moving away from the light-emitting layer13. The structure hence more effectively improves the luminance and luminous efficiency of the light-emitting device1. This particular hole transport layer12in the example can be formed by, for example, repeating the film-forming process from the application of a solution through the baking with the baking temperature being lowered toward the upper layer (as moving toward the light-emitting layer13). The light-emitting layer13is where the holes transported from the anode11recombine with the electrons transported from the cathode15to emit light. The light-emitting layer13can be composed of quantum dots and contain, for example, from one to several layers of quantum dots. The light-emitting layer13may be formed from a dispersion solution, for example, by spin-coating or inkjet printing. The dispersion solution contains quantum dots dispersed, for example, in a solvent such as hexane or toluene. The dispersion solution may additionally contain thiol or amine dispersed in the solvent. The light-emitting layer13has a thickness of, for example, 5 to 80 nm. The quantum dots may be made of, for example, semiconducting nanoparticles with a core/shell structure, such as CdSe/ZnS, CdSe/CdS, InP/ZnS, ZnSe/ZnS, or CIGS/ZnS nanoparticles. The quantum dots have a particle diameter of, for example, 3 to 15 nm. The emission wavelength of the quantum dots can be controlled by way of the particle diameter of the quantum dots. Therefore, the wavelength of the light emitted by the light-emitting device1can be controlled through the control of the particle diameter of the quantum dots. The electron transport layer14transports the electrons fed from the cathode15to the light-emitting layer13. The electron transport layer14may be made of a material such as ZnO, Zn1-xMgxO (0.0<x≤0.5), TiO2, SnO2, Ta2O3, or SrTiO3. The electron transport layer14may be formed by applying a dispersion solution containing nanoparticles dispersed in a solvent such as ethanol to the light-emitting layer13by, for example, spin-coating or sputtering and then evaporating and drying out the solvent. The electron transport layer14has a thickness of, for example, 10 to 100 nm. Each of the hole transport layer12and the electron transport layer14may be nanoparticulate, crystalline, polycrystalline, or amorphous. The hole transport layer12may have a function of disrupting electron transport, whereas the electron transport layer14may have a function of disrupting hole transport. The hole transport layer12and the electron transport layer14preferably have an absorption coefficient of 10 cm−1or less for the light emitted by the light-emitting layer13, so as not to disrupt the emission of light by the light-emitting device1. The cathode15is composed of a conductive metal that has a small work function (e.g., roughly equivalent to the conduction band of the electron transport layer14) such as Al, Ag, Ba, Yb, Ca, a Li—Al alloy, a Mg—Al alloy, a Mg—Ag alloy, a Mg—In alloy, or an Al—Al2O3alloy. The cathode15is reflective. The cathode15is formed by, for example, sputtering, vapor deposition, or printing. The present embodiment, for example, restrains exciton quenching in a light-emitting device including a hole transport layer containing a metal oxide, thereby improving the luminance and luminous efficiency of the light-emitting device. The disclosure is not limited to the embodiments described above and may be implemented in various other forms. The disclosure may further include, for example, a configuration that is practically the same as the configuration detailed above, a configuration that achieves the same effect and function as the configuration detailed above, or a configuration that achieves the same purpose as the configuration detailed above. For example, the hole transport layer12has been described as containing a metal oxide and carbon atoms as an example. The disclosure may be applied to the electron transport layer14. Specifically, the metal oxide may be any of ZnO, Zn1-xMgxO(0.0<x≤0.5), TiO2, SnO2, Ta2O3, and SrTiO3. In such cases, the electron transport layer14can achieve the same effects as the hole transport layer12in the relation to the carbon/metal atomic ratio. In these cases, the substrate10, the cathode15, the electron transport layer14, the light-emitting layer13, the hole transport layer12, and the anode11are preferably stacked in this sequence. The metal oxide in the electron transport layer14may be produced, for example, by dissolving a metal oxide precursor such as an organic acid salt of a metal or a metal complex of an organic compound in a solvent to prepare a coating solution, applying the coating solution to the cathode15, and then baking the solution in an atmosphere of oxygen, nitrogen, argon, or a mixture thereof. The light-emitting layer13is protected from damage in the baking because the light-emitting layer13is formed after the electron transport layer14is formed. The metal oxide in the electron transport layer14may be produced by preparing a dispersion solution containing metal oxide nanoparticles dispersed in a solvent such as ethanol, applying the dispersion solution to the cathode15by spin-coating, and evaporating and drying out the solvent. The metal oxide nanoparticles are synthesized in advance from, for example, a metal oxide precursor such as an organic acid salt of a metal or a metal complex of an organic compound in such a manner that the resultant metal oxide nanoparticles contain carbon atoms in a prescribed, adjusted ratio. Similarly to the hole transport layer12, the electron transport layer14may have a carbon concentration that is constant in a thickness direction thereof and may have a carbon concentration that increases toward the light-emitting layer13. These particular structures improve the luminance and luminous efficiency of the light-emitting device1, similarly to the hole transport layer12. The light-emitting device1may further include an electrical insulation film16between the hole transport layer12and the light-emitting layer13and another electrical insulation film16between the light-emitting layer13and the electron transport layer14, as shown inFIG.2. The electrical insulation film16may be made of a material such as Al2O3, SiO2, MgO, or ZrO2. Al2O3is particularly preferred because Al2O3can be easily processed, and can be uniformly formed at low temperature by sputtering or another conventional method. The two electrical insulation films16may not be made of the same material. The electrical insulation film16has a thickness of, for example, 1 nm to 3 nm. The electrical insulation film16may be provided only either between the hole transport layer12and the light-emitting layer13or between the light-emitting layer13and the electron transport layer14. The disclosure, involving use of a metal oxide and carbon atoms, may be applied to the electrical insulation film16. The use of the electrical insulation film16, for example, restrains quenching when holes and electrons are recombined, thereby further improving luminance. FIGS.1and2show, as an example, a structure where the lower electrode serves as the anode and the upper electrode serves as the cathode. The disclosure may alternatively be applied to a structure where the lower electrode serves as the cathode and the upper electrode serves as the anode, in which case the substrate10, the cathode15, the electron transport layer14, the light-emitting layer13, the hole transport layer12, and the anode11are stacked in this sequence. EXAMPLES OF THE INVENTION DISCLOSURE The following will describe the disclosure in more detail by way of examples and with reference to drawings. The disclosure is not limited to these examples. Manufacture of Light-Emitting Device The present example assumes that the lower electrode serves as the anode and the upper electrode serves as a cathode, in which structure the substrate10, the anode11, the hole transport layer12, the light-emitting layer13, the electron transport layer14, and the cathode15are stacked in this sequence. This structure includes no electrical insulation films and may alternatively include an electrical insulation film. The present example may alternatively assume that the lower electrode serves as the cathode and the upper electrode serves as the anode, in which structure the substrate10, the cathode15, the electron transport layer14, the light-emitting layer13, the hole transport layer12, and the anode11are stacked in this sequence. The light-emitting devices in accordance with Examples 1 and 2 and Comparative Examples 1 and 2 all detailed below differ only in the structure of the hole transport layer12and are otherwise identical. The substrate10was a glass substrate. The anode11was formed of IZO by sputtering to a thickness of 100 nm. The light-emitting layer13contained Cd (Se, S) quantum dots and had a thickness of 40 nm. The electron transport layer14was formed by applying ZnO nanoparticles to a thickness of 40 nm. The cathode15was formed of Al by vacuum vapor deposition to a thickness of 100 nm. Each layer was sealed in a nitrogen atmosphere after being formed. The hole transport layer12was made of NiO for desirable properties thereof such as atmospheric stability and light transmission. In Example 1, the hole transport layer12was formed by dissolving nickel acetate in ethanol to prepare a coating solution, applying the coating solution to the anode11by spin-coating, and then baking the coating solution at 230° C. for 1 hour in an oxygen atmosphere. The hole transport layers12of Example 2 and Comparative Examples 1 and 2 differed from Example 1 only in the baking temperature and were otherwise formed under the same conditions as Example 1. The baking temperature was 280° C., 180° C., and 400° C. in Example 2 and Comparative Examples 1 and 2 respectively. The baking temperature in Comparative Example 2 was 400° C. which is, as described earlier, a baking temperature commonly used in baking NiO paste to obtain a NiO layer. XSPXPS ANALYSIS The hole transport layers12thus obtained were analyzed by X-ray photoelectron spectroscopy (XPS). Specifically, the elements in the hole transport layers12were analyzed using an X-ray photoelectron spectrometer (Kratos AXIS NOVA, manufactured by Shimadzu Corporation) (X-ray: AlK alpha beam, output: 10 mA×15 kV). Specifically, the ratio (C/Ni) of element concentrations (atom %) of nickel atoms and carbon atoms was calculated from the detection sensitivity factor and the area of each peak in the spectrum obtained by the XPS measurement. The background for the quantification calculation was determined by the Shirley method. The analysis shows that the hole transport layer12had a carbon/nickel (C/Ni) composition ratio (atomic ratio) of 4.2% in Example 1, 2.1% in Example 2, 23.8% in Comparative Example 1, and 1.2% in Comparative Example 2. Table 1 represents results of the analysis of the composition of the hole transport layers12of Examples 1 and 2 and Comparative Examples 1 and 2.FIG.3represents the C/Ni element ratio plotted against the baking temperature. TABLE 1XPS Composition AnalysisBakingC/NiTemperatureRatio(° C.)(%)Comparative18023.8Example 1*********2055.9Example 12304.2Example 22802.1Comparative4001.2Example 2 The graph inFIG.3, obtained by linking the plots with a generally arc-like curve, indicates that the C/Ni element ratio increases abruptly below 200° C. and is constant above 330° C. These results suggest that the light-emitting device including the hole transport layer formed at a baking temperature in a range from 200° C. (C/Ni element ratio: approximately 6.0%) to 330° C. (C/Ni element ratio: approximately 1.5%), which encompasses both the baking temperatures in Example 1 and Example 2, has substantially the same effects as the light-emitting devices1of Examples 1 and 2. Evaluation The current density-luminance characteristics, current density-external quantum efficiency (EQE) characteristics, voltage-luminance characteristics, and voltage-current density characteristics of the light-emitting devices of Examples 1 and 2 and Comparative Examples 1 and 2 were measured.FIG.4represents the current density-luminance characteristics.FIG.5represents the current density-external quantum efficiency (EQE) characteristics.FIG.6represents the voltage-luminance characteristics.FIG.7represents the voltage-current density characteristics. FIG.4shows the current density (mA/cm2) on the horizontal axis and the luminance (cd/m2) on the vertical axis.FIG.4indicates that, for example, the luminance at a current density near 400 mA/cm2is approximately 1,800 cd/m2in the light-emitting device of Example 1 and approximately 1,550 cd/m2in the light-emitting device of Example 2. These values are very high in comparison with the luminance of approximately 900 cd/m2in the light-emitting device of Comparative Example 2. The graph does not show the results obtained from the light-emitting device of Comparative Example 1 because no current flowed in the light-emitting device of Comparative Example 1 and no points except for (0,0) could be plotted. The results obtained from the light-emitting device of Comparative Example 1 were treated in the same manner inFIG.5described next. No current flowed in the light-emitting device of Comparative Example 1 presumably because no NiO could be produced in the baking at 180° C. FIG.5shows the current density (mA/cm2) on the horizontal axis and the EQE (%) on the vertical axis.FIG.5indicates that, for example, the EQE at a current density near 400 mA/cm2is approximately 0.39% in the light-emitting device of Example 1 and approximately 0.32% in the light-emitting device of Example 2. These values represent very high luminous efficiency in comparison with the EQE of approximately 0.19% in the light-emitting device of Comparative Example 2. FIG.6shows the applied voltage (V) on the horizontal axis and the luminance (cd/m2) on the vertical axis.FIG.6indicates that the light-emitting devices of Examples 1 and 2 exhibit a luminance of, for example, close to 1,000 cd/m2when driven at 4 to 5 V. These values show that the light-emitting devices of Examples 1 and 2 are able to be driven at low voltage in comparison with the light-emitting device of Comparative Example 2 exhibiting a luminance of close to 1,000 cd/m2when driven at approximately 15 V.FIG.6also indicates that the light-emitting device of Example 1 exhibits a luminance as high as 3,243 cd/m2when driven at 6.2 V and exhibits a very high luminance of no less than 2,500 cd/m2, which is equivalent to 5 to 10 times the luminance of the light-emitting device of Comparative Example 2, when driven at 5.2 to 7.6 V, a voltage range that encompasses 6.2 V. FIG.7shows the applied voltage (V) on the horizontal axis and the current density (mA/cm2) on the vertical axis.FIG.7indicates that the light-emitting devices of Examples 1 and 2 exhibit a very large rate of increase of current density with respect to voltage in comparison with the light-emitting device of Comparative Example 2. FIGS.4to7clearly demonstrate that the light-emitting devices of Examples 1 and 2 exhibit high luminance and high luminous efficiency in comparison with the light-emitting devices of Comparative Examples 1 and 2 when driven at approximately the same voltage. Various characteristics have been evaluated as an indicator in the examples of the present embodiment in view of C/Ni element ratio. When the metal oxide in the hole transport layer includes a plurality of metal compounds, the ratio of carbon atoms with respect to the sum of metal atoms in each metal oxide is used. While there have been described what are at present considered to be certain embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention. | 23,125 |
11943948 | DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of the present invention will be described using the drawings. In all of the drawings, the same configuration elements will be given the same reference sign and will not be repeated. An expression “A is positioned over B” in the present specification may mean that A is directly positioned on B with no different element (for example, a layer) positioned between A and B or may mean that a different element (for example, a layer) is partially or fully positioned between A and B. Furthermore, expressions indicating orientations, such as “up”, “down”, “left”, “right”, “front”, and “back” are basically used in accordance with orientations in the drawings and are not interpreted to be limited to, for example, orientations in which an invented product described in the present specification is used. An anode in the present specification refers to an electrode from which a hole is injected into a layer containing a light emitting material (for example, an organic layer) and a cathode refers to an electrode from which an electron is injected into the layer containing the light emitting material. In addition, expressions “anode” and “cathode” may also mean different terms such as “hole injection electrode” and “electron injection electrode” or “positive electrode” and “negative electrode”. “Light emitting device” in the present specification includes devices having a light emitting element such as a display, lighting, or the like. In addition, “light emitting device” may include wires, integrated circuits (ICs), casing, or the like that are directly, indirectly, or electrically connected to the light emitting element. In the present specification, unless otherwise noted, expressions such as “first, second, A, B, (a), and (b)” and the like are expressions for differentiating elements, and the essence, sequence, order, number, or the like of the corresponding element is not limited by the expression. In the present specification, each member and each element may be singular or plural, unless the context clarifies whether a member or element is “singular” or “plural”. In the present specification, unless otherwise noted, the expression “A includes B” does not necessarily mean that A consists of B and possibly means that A may consist of element other than B. Unless otherwise noted, “cross section” in the present specification means a surface that appears at the time of cutting the light emitting device in a direction in which pixels, light emitting materials, or the like are laminated. In the present specification, expressions that describe anteroposterior relations in time such as “after”, “subsequent to”, “next”, and “before” indicate relative time relations, and individual elements for which an anteroposterior relation in time is used are not necessarily continuous from each other. In the case of expressing individual elements that are continuous from each other, an expression “immediately”, “directly”, or the like may be used. An expression “A is heated” in the present specification means that heat is applied to A and does not necessarily mean that only A is heated. The corresponding expression may mean that, for example, an element including A is heated. In addition, “A is heated” means that heat is applied to A intentionally or artificially, but does not include a simple change in the temperature of the atmosphere around A. FIG.1is a cross-sectional view of a light emitting device10according to an embodiment.FIG.2is a view showing an example of a secondary ion mass spectrometry (SIMS) profile in a first layer120ashown inFIG.1. The outline of the light emitting device10will be described usingFIG.1andFIG.2. The light emitting device10includes a first electrode110, an organic layer120, and a second electrode130. The organic layer120is positioned over the first electrode110. The organic layer120includes a first layer120a. The second electrode130is positioned over the organic layer120. The first layer120aincludes a first region RG1and a second region RG2. The first region RG1contains a first organic material and a metal compound (a compound containing a metal element). The first region RG1is in contact with the first electrode110. The second region RG2contains the first organic material and the metal compound. The second region RG2is positioned farther away from the first electrode110than the first region RG1. The SIMS profile shown inFIG.2shows signals derived from the metal element in the metal compound. Specifically, the SIMS profile shown inFIG.2shows the signals of a molybdenum element in a molybdenum oxide. The SIMS profile shown inFIG.2has a correlation with a profile of the proportion of the metal compound in the total of the volume of the first organic material and the volume of the metal compound. In the present embodiment, the average intensity of the SIMS profile of the metal element in the second region RG2can be lower than the average intensity of the SIMS profile of the metal element in the first region RG1. Specifically, as shown inFIG.2, the average intensity of the SIMS profile of the metal element in the second region RG2can be lower than 10%, preferably lower than 1.0%, of the average intensity of the SIMS profile of the metal element in the first region RG1. In the present embodiment, the maximum intensity of the SIMS profile of the metal element in the second region RG2can be lower than the maximum intensity of the SIMS profile of the metal element in the first region RG1. Specifically, as shown inFIG.2, the maximum intensity of the SIMS profile of the metal element in the second region RG2can be lower than 10%, preferably lower than 1.0%, of the maximum intensity of the SIMS profile of the metal element in the first region RG1. The first layer120acan be formed by heating the first organic material and the metal compound at a temperature equal to or higher than the glass transition temperature Tg1of the first organic material. The present inventors studied a process for forming the first layer120aand, as a result, newly found that, in the case of heating the first layer120aat a temperature equal to or higher than the glass transition temperature Tg1of the first organic material, the concentration of the metal compound can be lower at a position away from the first electrode110by a certain distance than at a position near the first electrode110. That is, the concentration distribution of the metal compound in the first layer120acan be controlled by a simple process of heating the first layer120a. The above-described concentration distribution of the metal compound is preferred for the light emitting device10. The concentration of the metal compound at the position near the first electrode110is desirably high due to a variety of requests (for example, an improvement in the current injection efficiency or an improvement in the adhesion to the first electrode110). However, an excess increase in the amount of the metal compound may cause a variety of adverse effects (for example, the degradation of the rectifying property). Therefore, the concentration of the metal compound at the position away from the first electrode110by a certain distance is desirably not too high. In the above-described concentration distribution, the concentration of the metal compound at the position away from the first electrode110by a certain distance can be lower than the concentration of the metal compound at the position near the first electrode110. The detail of the light emitting device10will be described usingFIG.1. The light emitting device10includes a substrate100, the first electrode110, the organic layer120, and the second electrode130. The substrate100has a first surface102and a second surface104. The first electrode110, the organic layer120, and the second electrode130are positioned on the first surface102side of the substrate100. The second surface104is present opposite to the first surface102. The substrate100is capable of functioning as a support for forming the first electrode110, the organic layer120, and the second electrode130. The substrate100may be translucent and flexible. The substrate100may be a single layer or as a plurality of layers. In one example, the substrate100may be a glass substrate. In another example, the substrate100may be a resin substrate and may contain an organic material (for example, polyethylene naphthalate (PEN), polyethersulfone (PES), polyethylene terephthalate (PET), or polyimide). Ina case where the substrate100is the resin substrate, at least one of the first surface102and the second surface104of the substrate100may have an inorganic barrier layer (for example, SiN or SiON). A layer containing one or more layers of an organic material may be provided between the substrate100and the first electrode110in a region that is wider than at least the first electrode110for the purpose of flattening or improvement in adhesion. The first electrode110is capable of function as an anode. In one example, the first electrode110may include a metal or an alloy. The metal or the alloy is, for example, silver or a silver alloy. In this example, the thickness of the first electrode110may be, for example, equal to or larger than 5 nm and equal to or smaller than 50 nm. In a case where the thickness of the first electrode110is equal to or larger than the above-described lower limit, it is possible to decrease the electrical resistance of the first electrode110, and, in a case where the thickness of the first electrode110is equal to or smaller than the above-described upper limit, it is possible to increase the transmission of the first electrode110. In another example, the first electrode110may include an oxide semiconductor. Examples of the oxide semiconductor include indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten zinc oxide (IWZO), zinc oxide (ZnO), and indium gallium zinc oxide (IGZO). The organic layer120includes the first layer120a, a hole transport layer (HTL)120b, a light emitting layer (EML)120c, an electron transport layer (ETL)120d, and an electron injection layer (EIL)120e. Each of the first layer120a, the HTL120b, the EML120c, the ETL120d, and the EIL120emay be a single layer or a plurality of layers. In the organic layer120, holes are injected from the first electrode110into the EML120cthrough the first layer120aand the HTL120b, and electrons are injected from the second electrode130into the EML120cthrough the EIL120eand the ETL120d. The organic layer120may not include the HTL120b, the ETL120d, and the EIL120e. The first layer120ais capable of functioning as a functional layer having a specific characteristic. The first layer120amay have, for example, at least one of a hole injection characteristic and a hole transport characteristic and is capable of functioning as, for example, at least one of a hole injection layer (HIL) and a hole transport layer (HTL). The first layer120ais positioned over the first electrode110and is in contact with the first electrode110. The first layer120acontains a first organic material and a metal compound. The first organic material may be, for example, an electron-accepting organic semiconductor material having a glass transition temperature. Examples of the first organic material include triphenylamine derivatives, specifically, 4,4′-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (α-NPD). In addition, it is also possible to appropriately use a well-known organic material that has been used for the production of organic EL elements in the related art such as an aromatic amine compound such as 4,4′,4″-tris(carbazole-9-yl)-triphenylamine (TCTA); a carbazole derivative such as 1,3-bis(N-carbazolyl)benzene; or a spiro compound such as N,N′-bis(naphthalen-1-yl)-N,N′-bis(phenyl)-9,9′-spirobisfluorene (Spiro-NPB). The metal compound may be a metal compound having an acceptor property, such as a metal oxide. The metal oxide may be, for example, a transition metal oxide. The transition metal oxide may be, for example, a molybdenum oxide, a titanium oxide, a zirconium oxide, a hafnium oxide, a vanadium oxide, a niobium oxide, a tantalum oxide, a chromium oxide, a tungsten oxide, a manganese oxide, or a rhenium oxide. The metal compound may be a molybdenum oxide. The molybdenum oxide has a composition represented by MoOx, (2≤x≤3) and is at least one of molybdenum trioxide (MoO3) and molybdenum dioxide (MoO2) and preferably molybdenum trioxide (MoO3). In the first layer120a, the concentration of the metal compound is lower at a position away from the first electrode110(the interface between the first electrode110and the first layer120a) by a certain distance than at a position near the first electrode110(an interface between the first electrode110and the first layer120a). The first layer120amay contain, for example, equal to or more than 1% by volume and equal to or less than 20% by volume of the metal compound with respect to the total volume of the first layer120a. In a case where the volume percentage of the metal compound is equal to or higher than the above-described lower limit, it is possible to improve the characteristics (for example, the conductive property) of the light emitting device10. In a case where the volume percentage of the metal compound is equal to or lower than the above-described upper limit, the concentration of the metal compound can be sufficiently lower at the position away from the first electrode110by a certain distance than at the position near the first electrode110, by heating the first layer120a. The concentration of the metal compound in the first layer120acan be regarded as the signal intensity of the metal element that configures the metal compound (for example, the molybdenum (Mo) element that configures the molybdenum oxide) in a secondary ion mass spectrometry (SIMS) depth profile (vertical direction inFIG.1). After the heating of the first layer120a, the first layer120amay have a thickness T of, for example, equal to or larger than 5 nm and equal to or smaller than 200 nm. The second electrode130is capable of functioning as a cathode. In one example, the second electrode130may contain a metal or alloy. The metal or alloy is, for example, at least one metal selected from a group consisting of Al, Au, Ag, Pt, Mg, Sn, Zn, and In or an alloy of metals selected from the above-described group. The first electrode110, the organic layer120, and the second electrode130are arranged in order from the first surface102of the substrate100to form a light emitting portion140. The light emitting device10may be bottom emission or top emission. In a case where the light emitting device10is bottom emission, light emitted from the organic layer120transmits through the first electrode110and the substrate100(that is, in a case where the light emitting device10is bottom emission, the substrate100and the first electrode110are translucent), and the light is emitted from the second surface104of the substrate100. In a case where the light emitting device10is top emission, light emitted from the organic layer120transmits through the second electrode130(that is, in a case where the light emitting device10is top emission, the second electrode130is translucent), and the light is emitted from a side opposite to the second surface104of the substrate100. The detail of the first layer120awill be described usingFIG.2. The first layer120aincludes the first region RG1, the second region RG2, and a third region RG3. The first region RG1, the second region RG2, and the third region RG3contain a first organic material and a metal compound (a compound containing a metal element). The first region RG1, the third region RG3, and the second region RG2are arranged in order from the first electrode110side (the deep side in the horizontal axis ofFIG.2). The first region RG1is in contact with the first electrode110. The range of the first region RG1can be determined by a variety of guidelines. In one example, the range of the first region RG1may be determined based on the distance from the boundary between the first electrode110and the first layer120a. For example, the first region RG1may be positioned up to 10 nm from the boundary between the first electrode110and the first layer120a. In another example, the range of the first region RG1may be determined such that the maximum intensity of the SIMS profile of the metal element in the third region RG3(the detail will be described below) is 90% of the average concentration of the SIMS profile of the metal element in the first region RG1. The first region RG1has a certain thickness. For example, the first region RG1has a thickness of equal to or larger than 5 nm and preferably has a thickness of equal to or larger than 10 nm. In this case, it is possible to increase the conductivity of the first layer120aand to improve the adhesion between the first electrode110and the first layer120a. The thickness of the first region RG1may be thicker than the thickness of the second region RG2(the detail will be described below). In this case, it is possible to increase the conductivity of the first layer120a. The second region RG2is positioned farther away from the first electrode110than the first region RG1. The second region RG2may be in contact with a layer over the first layer120a(the HTL120bin the example shown inFIG.1). The range of the second region RG2can be determined by a variety of guidelines. In one example, the range of the second region RG2may be determined such that the average intensity of the SIMS profile of the metal element in the second region RG2is equal to or lower than a certain proportion of the average intensity of the SIMS profile of the metal element in the first region RG1. The second region RG2has a certain thickness. For example, the second region RG2has a thickness of equal to or larger than 5 nm and preferably has a thickness of equal to or larger than 10 nm. In this case, it is possible to improve the reliability of the light emitting device10(for example, to suppress the current value at the time of applying a reverse bias current). The intensity of the SIMS profile of the metal element in the second region RG2can be equal to or lower than 10%, preferably equal to or lower than 1.0%, of the intensity of the SIMS profile of the metal element in the first region RG1. In this case, it is possible to improve the reliability of the light emitting device10. The intensity of the SIMS profile of the metal element in the second region RG2can be equal to or higher than 0.1%, preferably equal to or higher than 0.2%, of the intensity of the SIMS profile of the metal element in the first region RG1. In this case, it is possible to reduce the electrical resistance in the second region RG2. The third region RG3is positioned between the first region RG1and the second region RG2. The third region RG3may be in contact with the first region RG1and the second region RG2. The intensity of the SIMS profile of the metal element in the third region RG3decreases from the first region RG1to the second region RG2. The intensity of the SIMS profile of the metal element in the third region RG3may not strictly decrease monotonously, but may partially increase. For example, even in a case where the intensity of the SIMS profile of the metal element in the third region RG3partially increases, when the fitting curve of plots throughout the entire SIMS profile of the metal element in the third region RG3monotonically decreases, the intensity of the SIMS profile of the metal element in the third region RG3may be regarded as being decreased. The third region RG3has a certain thickness. For example, the third region RG3has a thickness of equal to or larger than 5 nm and preferably has a thickness of equal to or larger than 10 nm. In a case where the thickness in the third region RG3is thick, it is possible to make the concentration gradient in the third region RG3shallow. For example, the slope of the SIMS profile in the third region RG3is equal to or more than 0.5%/nm and equal to or less than 20%/nm when the average intensity of the SIMS profile in the first region RG1is 100%. When the concentration gradient is shallow (the concentration distribution does not change stepwise), it is possible to reduce the injection barrier of charges and to reduce a voltage increase caused by the injection barrier. Furthermore, when the concentration gradient is shallow (the concentration distribution does not change stepwise), it is possible to reduce the refractive index step and to reduce a decrease in the light extraction efficiency caused by the refractive index step. The coefficient of variation of the intensity of the SIMS profile of the metal element in the first region RG1may be larger than the coefficient of variation of the intensity of the SIMS profile of the metal element in the second region RG2. The coefficient of variation is the ratio of the standard deviation to the mean value. In a manufacturing process according to the present embodiment, the variation (coefficient of variation) in the intensity of the SIMS profile of the metal element in the first region RG1may be larger than the variation (coefficient of variation) in the intensity of the SIMS profile of the metal element in the second region RG2. FIG.3is a view for describing an example of a method of manufacturing the light emitting device10shown inFIG.1. The light emitting device10can be manufactured as follows. First, the first electrode110is formed over the first surface102of the substrate100. For example, the first electrode110may be formed by evaporating a metal or alloy (for example, silver or a silver alloy) using a mask or may be formed by patterning an oxide semiconductor. Next, as shown inFIG.3, the first layer120ais formed over the first electrode110. The first layer120acan be formed by co-evaporating the first organic material and the metal compound. The volume percentage of the metal compound with respect to the total volume of the first layer120acan be adjusted by controlling a condition for the co-evaporation. The first organic material and the metal compound may be co-evaporated without heating the substrate100or may be co-evaporated while the substrate100is heated at a specific temperature (for example, a temperature lower than the glass transition temperature Tg1of the first organic material). Next, the first layer120ais heated at a temperature (heating temperature T1) equal to or higher than the glass transition temperature Tg1of the first organic material. In the case of heating the first layer120aat a temperature equal to or higher than the glass transition temperature Tg1of the first organic material, the concentration of the metal compound can be lower at the position away from the first electrode110by a certain distance than at the position near the first electrode110. The reason for the generation of the above-described concentration distribution of the metal compound is assumed as follows. Before the heating of the first layer120a, the metal compound is distributed almost uniformly regardless of the depth in the first layer120a. When the first layer120ais heated at a temperature equal to or higher than the glass transition temperature Tg1of the first organic material, the first organic material exhibits fluidity. When the first organic material exhibits fluidity, some of the metal compound is precipitated toward the first electrode110. The above-described concentration distribution of the metal compound is assumed to be generated as described above. In addition, in the formation of the concentration distribution, the density of the metal compound is preferably higher than the density of the first organic material. Here, the density represents the mass per unit volume (g/cm3). The method of heating the first layer120ais not limited to a specific method. For example, the first layer120acan be heated by placing the substrate100under an environment of the heating temperature T1of the first layer120a(for example, the substrate100is placed on a hot plate or the substrate100is disposed in a vacuum heating oven) or by electromagnetic wave irradiation (for example, flash lamp annealing). The heating temperature T1may be, for example, a temperature of not less than 10° C. above the glass transition temperature Tg1of the first organic material and a temperature of not more than 70° C. above the glass transition temperature Tg1of the first organic material (Tg1+10≤T1≤Tg1+70) or a temperature of not less than 30° C. above the glass transition temperature Tg1of the first organic material and a temperature of not more than 40° C. above the glass transition temperature Tg1of the first organic material (Tg1+30≤T1≤Tg1+40). The time for heating the first layer120aat the heating temperature T1may be, for example, equal to or longer than one minute and equal to or shorter than 60 minutes in the case of heating with a hot plate or an oven or equal to or longer than 1 μs and equal to or shorter than 1 s in the case of heating by flash lamp annealing. Next, the HTL120b(FIG.1) is formed over the first layer120a. In other words, the method according to this example includes a step of forming a second layer (the HTL120bin the example shown inFIG.1) in contact with the first layer120aafter heating the first layer120a. In still other words, the first layer120ais heated before the first layer120ais covered with the second layer (the HTL120bin the example shown inFIG.1). The method of forming the HTL120bis not limited to a specific method. For example, the HTL120bcan be formed by an evaporation or application process (for example, inkjet). Next, the EML120c, the ETL120d, and the EIL120eare formed. The method of forming the EML120c, the ETL120d, and the EIL120eis not limited to a specific method. For example, the EML120c, the ETL120d, and the EIL120ecan be formed by an evaporation or application process (for example, inkjet). Next, the second electrode130is formed. The method of forming the second electrode130is not limited to a specific method. For example, the second electrode130can be formed by evaporation. The light emitting device10is manufactured as described above. FIG.4andFIG.5are views for describing an example of the reason for heating the first layer120a. The reason for heating the first layer120amay include not only the formation of the above-described concentration distribution of the metal compound but also the reason described usingFIG.4andFIG.5. In the example shown inFIG.4, a foreign matter P is attached to the surface of the first electrode110. In the example shown inFIG.4, since the substrate100(for example,FIG.1orFIG.2) is moved from a chamber for forming the first electrode110to a chamber for forming the first layer120aafter the formation of the first electrode110, the substrate100(for example,FIG.1orFIG.2) is exposed to the atmosphere. During the movement of the substrate100, a foreign matter in the atmosphere (the foreign matter Pin the example shown inFIG.4) may be attached to the surface of the first electrode110. In the example shown inFIG.4, the first layer120ais an evaporated layer and is formed by co-evaporating the first organic material and the metal compound. Layers formed by evaporation are inferior to layers formed by different deposition (for example, atomic layer deposition (ALD)) in terms of step coverage. Therefore, the first layer120amay break around the foreign matter P. Formation of an element (for example, the second electrode130shown inFIG.1) over the first layer120awith the first layer120abroken may cause a short circuit between the first electrode110and the second electrode130(for example,FIG.1). As shown inFIG.5, the first layer120ais heated in order to bury the foreign matter P with the first layer120a. The first layer120ais heated at a temperature that is equal to or higher than the glass transition temperature Tg1of the first organic material and thereby exhibits fluidity. As shown inFIG.4, the first layer120acan be deformed by heating so as to bury the foreign matter P. The burying of the foreign matter P with the first layer120amakes it possible to prevent a short circuit between the first electrode110and the second electrode130(for example,FIG.1). Modification Example The light emitting device10according to a modification example is the same as the light emitting device10according to the embodiment except the following points. The first electrode110functions as a cathode, and the first layer120afunctions as at least one of an electron injection layer and an electron transport layer. The first layer120acontains a first organic material and a metal compound. The concentration of the metal compound in the first layer120acan be made the same as the concentration in the embodiment by the method described in the embodiment. The metal compound may be a metal compound having a donor property, such as lithium fluoride (LiF), lithium oxide (Li2O), cesium fluoride (CsF), or calcium carbonate (CaCO3). Hitherto, the embodiment and the example have been described with reference to the drawings, but the embodiment and the example are examples of the present invention, and it is also possible to adopt a variety of configurations other than the above-described configurations. This application claims priority based on Japanese Patent Application No. 2018-247736 filed Dec. 28, 2018, the disclosure of which is incorporated herein in its entirety. REFERENCE SIGNS LIST 10: Light emitting device100: Substrate102: First surface104: Second surface110: First electrode120: Organic layer120a: First layer120b: HTL120c: EML120d: ETL120e: EIL130: Second electrode140: Light emitting portionRG1: First regionRG2: Second regionRG3: Third region | 29,894 |
11943949 | Figure numerals: display panel10, light-emitting region101, non-light-emitting region102, first substrate110, second substrate120, base substrate111, light-shielding metal layer112, buffer layer113, active layer114, first insulating layer115, first metal layer116, second insulating layer117, second metal layer118, first metal segment1181, second metal segment1192, third insulating layer119, first active layer1141, second active layer1142, through-hole1191, first leading line130, cover plate121, first electrode122, light-emitting layer123, retaining wall structure124, second electrode126, second leading line126, packaging layer127. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with accompanying drawings in the embodiments of the present disclosure. Obviously, the embodiments described are merely a part of the present disclosure, rather than all the embodiments. All other embodiments obtained by the person having ordinary skill in the art based on embodiments of the disclosure, without making creative efforts, are within the scope of the present disclosure. The following disclosure provides many different embodiments or examples for achieving different structures of the present disclosure. To simplify the present disclosure, components and settings of specific examples are described below. They are only examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and/or reference letters in different examples, this repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between various embodiments and/or settings discussed. In addition, the present disclosure provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the present disclosure of other processes and/or the use of other materials. Embodiment 1 In the present embodiment, a display panel10of the present disclosure comprises a light-emitting region101and a non-light-emitting region102surrounding the light-emitting region101. The display panel10further comprises a first substrate110and a second substrate120, which are opposite to each other. As shown inFIG.1, the first substrate110is an array substrate and comprises a base substrate111, a light-shielding metal layer112, a buffer layer113, an active layer114, a first insulating layer115, a first metal layer116, a second insulating layer117, a second metal layer118, and a third insulating layer119. The base substrate111is a glass substrate, and the glass is transparent glass, which has a certain carrying capacity and can support various functional layers on the array substrate. Meanwhile, it can also effectively prevent outside water vapor from entering the array substrate, causing loss of function of the array substrate, thereby affecting service life of the display panel10. The light-shielding metal layer112is disposed on the base substrate111. Specifically, the light-shielding metal layer112is disposed in the non-light-emitting region102, and is used to reflect light directed in a direction of the base substrate111to prevent light leakage from one side of the base substrate111of the first substrate110, which causes display abnormality. The active layer114is disposed on the buffer layer113. Specifically, the active layer114comprises a first active layer1141and a second active layer1142, wherein a position of the first active layer1141corresponds to the light-shielding metal layer112. In order for the light-shielding metal layer112to achieve the best light-shielding effect, generally speaking, an area of the light-shielding metal layer112is greater than an area of the first active layer1141, that is, a projection of the first active layer1141on the base substrate111completely falls within a projection of the light-shielding metal layer112on the base substrate111. The second active layer1142is disposed in the light-emitting region101and is used to provide electrical signals required by the display panel10to emit light. The first insulating layer115is disposed on the active layer114. Specifically, the first insulating layer115is disposed on the first active layer1141and the second active layer1142, and an orthographic projection of the first insulating layer115completely falls within a region of the first active layer1141and the second active layer1142. The first metal layer116is disposed on the first insulating layer115. The first insulating layer115is used to prevent the first metal layer116and the active layer114from directly contacting each other, causing short-circuiting. The second insulating layer117is disposed on the buffer layer113and covers the active layer114, the first insulating layer115, and the first metal layer116to prevent external water vapor from entering and improve service life of the first substrate110. The second metal layer118is disposed on the second insulating layer117. Specifically, the second metal layer comprises a first metal segment1181and a second metal segment1182, the first metal segment1181is correspondingly disposed on the first active layer1141in the non-light-emitting region102, the first metal segment1181comprises at least two pins. One of the pins is connected to the first active layer1141through the second insulating layer117, and another pin is connected to the corresponding light-shielding metal layer112through the second insulating layer117and the buffer layer113. The second metal segment1182is correspondingly disposed on the second active layer1142in the light-emitting region101. The second metal segment1182comprises at least two pins, the least two pins are connected to the second active layer1142through the second insulating layer117to form a source/drain electrode circuit. The second metal layer118is disposed on the second insulating layer117, wherein the first metal segment1181of the second metal layer118disposed in the non-light-emitting region102is connected to the first active layer1141and the light-shielding metal layer112through at least two connecting holes1171in the non-light-emitting region102, and the second metal segment1182of the second metal layer118disposed in the light-emitting region101is connected to the second active layer1142through at least two connecting holes1172in the light-emitting region101. The third insulating layer119is disposed on the second insulating layer117and covers the second metal layer118to prevent intrusion of external water vapor from causing the second metal layer118to fail due to water vapor corrosion. Meanwhile, the third insulating layer119covering the second metal layer118also prevents short-circuiting caused by contact between the second metal layer118and other metal layers. A via hole1191is defined in the third insulating layer119corresponding to the second metal layer118, a portion of the second metal layer118is exposed outside of from the through-hole1191, and a first leading line130is disposed in the via hole1191, wherein the first leading line130is disposed on the inner surface of the via hole1191and is connected to the exposed second metal layer118. As shown inFIG.2, the second substrate120comprises a cover plate121, a first electrode122, a light-emitting layer123, a retaining wall structure124, a second electrode125, a second leading line126, and a packaging layer127. The cover plate121is a glass substrate, and the glass is transparent glass, which has a certain carrying capacity and can support various functional layers on the array substrate. Meanwhile, it can also effectively prevent outside water vapor from entering the array substrate, and affecting service life of the display panel10. The first electrode122is an anode, and the first electrode122is directly disposed on the cover plate121. Since the cover plate121is a flat and smooth plate-structure, the anode may have a higher integrity and improve the uniformity of film thickness, thereby improving luminescent efficiency and service life of the display panel10. The retaining wall structure124is disposed on the first electrode122and corresponds to the non-light-emitting region102. Specifically, the retaining wall structure124comprises a plurality of retaining wall units, and an interval surrounded by adjacent retaining wall units is the light-emitting region101, and the light-emitting layer123is disposed in the interval. The light-emitting layer123comprises a plurality of light-emitting units, and colors of the light-emitting units are red, blue, and green. Each of the light-emitting units is correspondingly disposed in the interval surrounded by the retaining wall units, and the colors of adjacent light-emitting units are different, which ensures that the display panel10can display a colored image. The second electrode125is a cathode, which is disposed on the light-emitting layer123and extends to an adjacent retaining wall unit. The first electrode122and the second electrode125have a voltage difference, so that the light emitting layer123can emit light, and the display panel10can normally display. The second lead-out line126is disposed on the first electrode122and corresponds to the non-light-emitting region102. Specifically, the second leading line126is a circular frustum or a prismatic frustum, and one terminal thereof penetrates through the retaining wall structure124from the first electrode122. In order to prevent the second electrode125and the first electrode122disposed on the retaining wall structure124from being connected through the second leading line126and causing short-circuiting, an interval is defined between the second electrode125and the second leading line126which are disposed on a surface of the retaining wall structure124. The packaging layer127is disposed on the first electrode122and covers the retaining wall structure124, the light-emitting layer123, and the second electrode125to prevent the second electrode125and the first electrode122from being corroded by external water vapor, affecting service life. A portion of the packaging layer127covers the second lead-through126to facilitate subsequent connection of the second lead-through126to the first lead-through130. As shown inFIG.3, the first substrate110and the second substrate120are oppositely arranged to form the display panel10, and the first leading line130is correspondingly connected to the second leading line126, that is, the second metal layer is connected to the first electrode122through the first leading line130and the second leading line126. In order to better describe the present disclosure, an embodiment further provides a manufacturing method of the display panel, comprising forming a first substrate and a second substrate, and specific steps are as follows: The method of forming the second substrate is as follows: providing a cover plate; forming a first electrode on the cover plate; forming a retaining wall structure in the non-light-emitting region of the first electrode, and defining a through-hole on the light-emitting region corresponding to the retaining wall structure; forming a light-emitting layer in the through-hole of the retaining wall structure, wherein the light-emitting layer comprises light-emitting units comprising at least two colors, and the colors of adjacent light-emitting units are different; forming a second electrode on the light-emitting units, wherein the second electrode extends from a corresponding surface of the light-emitting units to the adjacent retaining wall structure; forming a penetrating hole in the retaining wall structure of the non-light-emitting region, wherein an interval is defined between the penetrating hole and the second electrode of the non-light-emitting region; filling a conductive material in the penetrating hole to form a second leading line; forming a packaging layer above the first electrode, wherein the packaging layer covers the retaining wall structure, the light-emitting layer, and the second electrode, and a portion of the second leading line is exposed outside of the packaging layer; forming a first leading line on the first substrate corresponding to the second leading line; and combining the first substrate and the second substrate, wherein the second leading line is correspondingly connected to the first leading line. The method of forming the first substrate is as follows: providing a base substrate; preparing a shielding metal material on the base substrate, and patterning to form a light-shielding metal layer; forming a buffer layer on the second substrate, and the buffer layer covers the light-shielding metal layer; forming a layer of indium gallium zinc oxide (IGZO), and patterning to form an active layer, wherein the active layer comprises a first active layer corresponding to the light-shielding metal layer and a second active layer disposed in the light-emitting region; forming a first insulating layer on the active layer; forming a first metal layer on the first insulating layer; forming a second insulating layer on the buffer layer, wherein the second insulating layer covers the active layer, the first insulating layer, and first metal layer; and forming a second metal layer on the second insulating layer, wherein the second metal layer disposed in the non-light-emitting region is connected to the first active layer and the light-shielding metal layer through the connecting holes, and the second metal layer disposed in the light-emitting region is connected to the second active layer through the connecting holes; combining the first substrate and the second substrate, wherein the second leading line is connected to the first leading line. The above embodiments are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure, and any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure. | 14,170 |
11943950 | DESCRIPTION OF EMBODIMENT Embodiments of the present invention will be described below by referring to the drawings. Moreover, in all the drawings, the same constituent elements are given the same reference numerals, and descriptions thereof will not be repeated. FIG.1is a diagram showing a light-emitting module according to an embodiment. A light-emitting module includes a plurality of light-emitting devices10and a reflecting member20. The plurality of light-emitting devices10include a plurality of light-emitting devices10a, a plurality of light-emitting devices10b, and a plurality of light-emitting devices10c. The plurality of light-emitting devices10are aligned on the reflecting member20. Light emitted from each light-emitting device10is reflected on the reflecting member20, thereby generating a sense of beauty different from that of a light-emitting module without any reflecting member20. In the example shown inFIG.1, six light-emitting devices10care aligned in a straight line along one direction, four light-emitting devices10bare aligned surrounding a region facing one end of the six light-emitting devices10c, and each of four light-emitting devices10ais aligned with each of the four light-emitting devices10boutside the four light-emitting devices10b. The color of light emitted from the light-emitting devices10aand the light-emitting devices10bmay be made different from the color of light emitted from the light-emitting devices10c. In one example, each of the light-emitting devices10aand the light-emitting devices10bmay emit red light and the light-emitting devices10cmay emit yellow light. In this example, the difference between the light-emitting devices10cand the set of the light-emitting devices10aand the light-emitting devices10bcan be made conspicuous. The light-emitting module shown inFIG.1can be applied to various uses. For example, the light-emitting module may be used as an automobile tail lamp. FIG.2is a plan view showing the light-emitting devices10ashown inFIG.1.FIG.3is a diagram in which the second electrodes130are removed fromFIG.2.FIG.4is a cross-sectional view taken along line A-A ofFIG.2. InFIGS.2and3, the light-emitting device10is viewed from a first surface102(FIG.4) side of a substrate100. An organic layer120, a layer211, a covering layer212, an intermediate layer213, a layer214, a covering layer215, and a protective layer216shown inFIG.4are not shown inFIG.2for ease of explanation. In addition, the width of the second electrode130shown inFIG.2does not imply the relative size of the width of the second electrode130with respect to the width of the substrate100. (InFIG.2, for ease of explanation, the relative size of the width of the second electrode130with respect to the width of the substrate100is shown bigger than that of the light-emitting device10awhich can be actually manufactured.) A summary of the light-emitting device10a(light-emitting device) is explained usingFIGS.2-4. The light-emitting device10aincludes a first electrode110, the organic layer120, a plurality of second electrodes130a(second electrodes130of a first group), and a plurality of second electrodes130b(second electrodes130of a second group). The first electrode110is located on the first surface102of the substrate100. The organic layer120is located on the first electrode110. The plurality of second electrodes130aare located on the organic layer120and extend in a first direction (X direction ofFIG.2). The second electrodes130bare located on the organic layer120and extend in a second direction (Y direction ofFIG.2) orthogonal to the first direction. As shown inFIG.2, the first surface102of the substrate100includes a first region102a, a second region102b, and a third region102c. The plurality of second electrodes130aare located in the first region102a. The plurality of second electrodes130bare located in the second region102b. The third region102cis located between the first region102aand the second region102b, and the second electrode130is not located in the third region102c. Particularly in the example shown inFIG.2, none of the plurality of second electrodes130aintersect any of the plurality of second electrodes130b. According to the above-mentioned configuration, the plurality of second electrodes130(the plurality of second electrodes130aand the plurality of second electrodes130b) can be favorably deposited. Specifically, assuming that each of the plurality of second electrodes130aintersects each of the plurality of second electrodes130b, as described later usingFIG.6, an opening including a bending portion (a bending portion322shown inFIG.6) is formed in a mask used for deposition of the plurality of second electrodes130. When gravity acts on such a mask, there is a possibility of the mask being greatly deformed in the bending portion and the surroundings thereof, that is, there is a possibility that the second electrodes130cannot be favorably deposited. In contrast, in the above-mentioned configuration, as described later usingFIG.5, the second electrode130can be deposited without forming the opening including the bending portion in the mask. There is low possibility of such a mask being deformed by gravity. Therefore, the plurality of second electrodes130(the plurality of second electrodes130aand the plurality of second electrodes130b) can be favorably deposited. Meanwhile, some of the plurality of second electrodes130amay intersect any of the plurality of second electrodes130b. In other words, at least one of the plurality of second electrodes130aneed not intersect any of the plurality of second electrodes130b. In this example, the opening including the bending portion is formed in the mask. However, the number of bending portions can be reduced in comparison to the later described the example shown inFIG.6(that is, an example of all of the plurality of second electrodes130aintersecting any of the plurality of second electrodes130b). Therefore, even in a case where at least one of the plurality of second electrodes130adoes not intersect any of the plurality of second electrodes130b, it is possible to inhibit the mask from being deformed, and the plurality of second electrodes130can be favorably deposited to a certain degree. Details of the plan layout of the light-emitting device10ais explained usingFIGS.2-3. The light-emitting device10aincludes the substrate100, the first electrode110, a conductive portion112, a terminal114, a plurality of second electrodes130, a conductive portion132, and a terminal134. The substrate100is L-shaped. Specifically, the substrate100includes a side100a, a side100b, a side100c, a side100d, a side100e, and a side100f. The substrate100extends from the side100ato the side100b. The side100cand the side100dextend from the side100aand the side100b, respectively, and intersect each other. The side100eand the side100fare on the opposite sides of the side100cand the side100d, respectively, and extend from the side100aand the side100b, respectively, intersecting each other. The side100eand the side100fare longer than the side100cand the side100d, respectively. The substrate100is formed of a flexible material. Therefore, as shown inFIG.1, the light-emitting device10a(that is, the substrate100) can be curved. The first electrode110includes a plurality of segments which are separated from each other, and in the example shown inFIG.3, the first electrode110includes a first segment110aand a second segment110b. The first segment110aand the second segment110bcontinuously extend from the side100ato the side100b, that is, from the first region102ato the second region102bvia the third region102c. The first segment110aand the second segment110bare aligned in a direction intersecting the extending direction of the substrate100, that is, in a direction from the side100cand the side100dtoward the side100eand the side100f. The first segment110ais located nearer to the side100cand the side100dthan the second segment110b, and the second segment110bis located nearer to the side100eand the side100fthan the first segment110a. By aligning the plurality of segments (the first segment110aand the second segment110b) in a direction intersecting the extending direction of the plurality of second electrodes130, a light-emitting unit142configured of the first segment110a(for example,FIG.4) and a light-emitting unit142configured of the second segment110b(for example,FIG.4) can be controlled independently of each other. The first electrode110can be formed without performing deposition using a mask. Therefore, unlike the second electrode130, the first electrode110need not be discontinued in the third region102c. Therefore, the first electrode110(the first segment110aand the second segment110b) continuously extends from the first region102ato the second region102bvia the third region102c. In another example, the first electrode110may be formed by deposition using a mask. In this case, the first electrode110may be discontinued in the third region102c. The first electrode110can be favorably deposited as is the case with the second electrode130. The conductive portion112functions as an auxiliary electrode of the first electrode110. Specifically, two conductive portions112extend from the side100ato the side100b, that is, from the first region102ato the second region102bvia the third region102c. The sheet resistance of each conductive portion112is lower than that of the first electrode110. Each conductive portion112is formed of a material (for example, metal, and more specifically, Mo/Al/Mo (MAM)) having higher conductivity than that of a conductive material included in the first electrode110. In the example shown inFIG.3, one conductive portion112extends along the side100cand the side100dand is covered by the first segment110a. The other conductive portion112extends along the side100eand the side100fand is covered by the second segment110b. The first electrode110can be supplied with electrical potential from the outside of the light-emitting device10via the terminal114. Specifically, the terminal114disposed along the side100ais connected to one end of the conductive portion112extending along the side100c, and the terminal114disposed along the side100bis connected to the other end of the conductive portion112extending along the side100d. Similarly, the terminal114disposed along the side100ais connected to one end of the conductive portion112extending along the side100e, and the terminal114disposed along the side100bis connected to the other end of the conductive portion112extending along the side100f. It is possible to inhibit voltage of the conductive portion112from dropping in the extending direction of the conductive portion112by connecting the terminals114to both ends of the conductive portion112. Variation in the brightness distribution of the light-emitting units142(for example,FIG.4) may be inhibited by inhibiting a voltage drop in the conductive portion112. The plurality of second electrodes130include the plurality of second electrodes130aand the plurality of second electrodes130b. The plurality of second electrodes130aextend in a striped pattern in the first direction (X direction ofFIG.2) from the side100atoward the third region102c. In the example shown inFIG.2, the plurality of second electrodes130aare aligned at substantially constant intervals along the second direction (Y direction ofFIG.2) from the side100ctoward the side100e. In another example, the interval between second electrodes130aadjacent to each other may vary depending on the set of second electrodes130aadjacent to each other. The plurality of second electrodes130bextend in a striped pattern in the second direction (Y direction ofFIG.2) from the side100btoward the third region102c. In the example shown inFIG.2, the plurality of second electrodes130bare aligned at substantially constant intervals along the first direction (X direction ofFIG.2) from the side100dtoward the side100f. In another example, the interval between second electrodes130badjacent to each other may vary depending on the set of second electrodes130badjacent to each other. The plurality of second electrodes130aand the plurality of second electrodes130bare substantially symmetrically arranged with respect to the third region102c. Specifically, the plurality of second electrodes130aand the plurality of second electrodes130binclude a pair of second electrodes130substantially symmetrically arranged with respect to the third region102c. Of the pair, the length and the width of one second electrode130are substantially equal to the length and the width of the other second electrode130. In more detail, the third region102cis linear, and the plurality of second electrodes130aand the plurality of second electrodes130bare axisymmetrically arranged with respect to the straight line. Therefore, the brightness distribution of the light-emitting unit142configured by the one second electrode130(FIG.4) and the brightness distribution of the light-emitting unit142configured by the other second electrodes130(FIG.4) can be made substantially symmetric with respect to the third region102c. The plurality of second electrodes130acan be supplied with electrical potential from the outside of the light-emitting device10via the terminal134. Specifically, the terminal134(first terminal) is located on the opposite side of the third region102cwith the plurality of second electrodes130atherebetween, and is disposed along the side100ain the examples shown inFIGS.2-3. The terminal134is connected to the plurality of second electrodes130avia the conductive portion132between the terminal134and the plurality of second electrodes130a. The plurality of second electrodes130bcan be supplied with electrical potential from the outside of the light-emitting device10via the terminal134. Specifically, the terminal134(second terminal) is located on the opposite side of the third region102cwith the plurality of second electrodes130btherebetween, and arranged along the side100bin the example shown inFIGS.2-3. The terminal134is connected to the plurality of second electrodes130bvia the conductive portion132between the terminal134and the plurality of second electrodes130b. The terminal134connected to the plurality of second electrodes130aand the terminal134connected to the plurality of second electrodes130bare substantially symmetrically arranged with respect to the third region102c. In more detail, the third region102cis linear, and the terminal134connected to the plurality of second electrodes130aand the terminal134connected to the plurality of second electrodes130bare axisymmetrically arranged with respect to the straight line. Specifically, the distance from the terminal134connected to the plurality of second electrodes130bto the third region102cis substantially equal to the distance from the terminal134connected to the plurality of second electrodes130ato the third region102c. Therefore, the brightness distribution of the light-emitting unit142(FIG.4) from the terminal134connected to the plurality of second electrodes130ato the third region102cand the brightness distribution of the light-emitting unit142(FIG.4) from the terminal134connected to the plurality of second electrodes130bto the third region102ccan be made substantially symmetric with respect to the third region102c. Details of the cross-sectional structure of the light-emitting device10ais explained usingFIG.4. The light-emitting device10aincludes the substrate100, the first electrode110, the organic layer120, the second electrode130, an insulating layer150, the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216. The light-emitting device10aincludes the plurality of light-emitting units142and a plurality of light-transmitting units144. Each light-emitting unit142is formed of a laminated structure of the first electrode110, the organic layer120, and the second electrode130. Each light-transmitting unit144is located between the light-emitting units142adjacent to each other. The light-emitting device10ahas light-transmitting properties due to the plurality of light-transmitting units144. The substrate100includes the first surface102and the second surface104. The first electrode110, the organic layer120, the second electrode130, the insulating layer150, the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216are located on the first surface102side of the substrate100. The second surface104is located on the opposite side of the first surface102. The substrate100is composed of a material having light-transmitting properties. Therefore, light can be transmitted through the substrate100. The substrate100is composed of, for example, glass or a resin. The resin may be, for example, polyethylene naphthalate (PEN), polyether sulphone (PES), polyethylene terephthalate (PET), or polyimide. In a case where the substrate100is composed a resin, at least one of the first surface102and the second surface104of the substrate100may be covered by an inorganic barrier layer (for example, SiNx or SiON). It is possible to inhibit a substance which can deteriorate the organic layer120(for example, vapor) from permeating the substrate100by the inorganic barrier film. The first electrode110includes a light-transmitting conductive material and has light-transmitting properties. The light-transmitting conductive material may be, for example, a metal oxide (for example, an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium tungsten zinc oxide (IWZO), a zinc oxide (ZnO)) or an indium gallium zinc oxide (IGZO), a carbon nanotube, an electroconductive polymer (for example, PEDOT/PSS), or a metal film (for example, Ag) having light-transmitting properties, or an alloy film (for example, AgMg). In the example shown inFIG.4, the first segment110aand the second segment110bof the first electrode110extend across the plurality of light-emitting units142. The plurality of light-emitting units142include a common first electrode110except an area between the first segment110aand the second segment110b. The organic layer120includes a light-emitting layer (EML) which emits light by organic electroluminescence, and may appropriately include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). A hole is injected from the first electrode110to the EML, an electron is injected from the second electrode130to the EML, and the hole and the electron are recombined in the EML to emit light. In the example shown inFIG.4, the organic layer120extends across the plurality of light-emitting units142. In the example shown inFIG.4, the colors of light emitted from the plurality of light-emitting units142are the same, and for example, may be red. In this case, the organic layer120configuring each light-emitting unit142need not be separated from another organic layer120, and the organic layers120can be extended across the plurality of light-emitting units142. In another example, the organic layer120configuring each light-emitting unit142may be separated from another organic layer120. The second electrode130includes a light-shielding conductive material, and has light shielding properties, particularly light reflectivity. The light-shielding conductive material may be a metal, particularly, a metal selected from a group consisting of Al, Au, Ag, Pt, Mg, Sn, Zn, and In, or an alloy of metals selected from this group. The insulating layer150includes two openings152. One opening152exposes a portion of the first segment110a, and the other opening152exposes a portion of the second segment110b. The plurality of light-emitting units142are located in each opening152. In each light-emitting unit142, the first electrode110, the organic layer120, and the second electrode130configure a laminated structure. The insulating layer150covers an end of the first segment110aon the opposite side of the second segment110b, and covers an end of the second segment110bon the opposite side of the first segment110a. Thus, contact between the first electrode110and the second electrode130, that is, a short circuit is prevented between the first electrode110and the second electrode130. In the example shown inFIG.4, the end of the first segment110aon the opposite side of the second segment110bcovers one conductive portion112, and the end of the second segment110bon the opposite side of the first segment110acovers the other conductive portion112. As is clear from the explanation of the present embodiment, the location at which the conductive portion112is provided is not limited to the example shown inFIG.4. In one example, the conductive portion112may be covered with the insulating layer150on the first electrode110. The insulating layer150may be, for example, an organic insulating layer (for example, polyimide) or an inorganic insulating layer (for example, SiO2). The layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216are laminated in order from the first surface102of the substrate100. The layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216function as a sealing portion to seal the light-emitting unit142, particularly, the organic layer120. The layer211is provided in order to prevent the covering layer212(as described later, the covering layer212is formed by Atomic Layer Deposition (ALD)) from peeling off. The layer211is formed by Chemical Vapor Deposition (CVD), and includes an inorganic material (for example, SiN). When the covering layer212is formed directly on an organic layer (for example, organic layer120), there is a risk of the covering layer212peeling off. The covering layer212can be prevented from peeling off by the layer211. The covering layer212is provided to shield the light-emitting unit142, particularly, the organic layer120from substances (for example, vapor or oxygen) which can deteriorate the light-emitting unit142and the organic layer120. The covering layer212is formed by ALD, and includes an inorganic material having insulating properties. The intermediate layer213is provided in order to relieve stress of the covering layer215(as described later, the covering layer215is formed by ALD). In one example, the intermediate layer213may be a resin layer. The layer214is provided in order to prevent the covering layer215from peeling off. The layer211is formed by sputtering, and includes an inorganic material (for example, SiON). When the covering layer215is formed directly on an organic layer (for example, the intermediate layer213), there is a risk of the covering layer215peeling off. The covering layer215can be prevented from peeling off by the layer214. The covering layer215is provided to shield the light-emitting unit142, particularly, the organic layer120, from substances (for example, vapor or oxygen) which can deteriorate the light-emitting unit142and the organic layer120. The covering layer215is formed by ALD, and includes an inorganic material having insulating properties. The protective layer216is provided in order to protect the light-emitting unit142, the layer211, the covering layer212, the intermediate layer213, the layer214, and the covering layer215. In one example, the protective layer216may be a resin layer. In the example shown inFIG.4, the covering layer212(inorganic layer) and the layer214(inorganic layer) are in contact with each other on the outside of an end of the intermediate layer213. That is, the end of the intermediate layer213is prevented from being exposed by the covering layer212and the layer214. Therefore, it is possible to prevent substances (for example, vapor or oxygen) which can deteriorate the light-emitting unit142, particularly, the organic layer120, from entering from the end of the intermediate layer213. Meanwhile, when the layer211is formed by CVD and includes silicon oxynitride, and the layer214is formed by sputtering and includes silicon oxynitride, the composition ratio of oxygen atoms in the layer214is preferably greater than the composition ratio of oxygen atoms in the covering layer212. By adopting such a configuration, high moisture-proof properties can be obtained by the layer211which is near the organic layer120, and a greater effect of stress relaxation can be obtained by the layer214. In addition, sealing failure such as cracks in the sealing portion or the like can be reduced. The structure to seal the organic layer120is not limited to the example shown inFIG.4(the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216). As is clear from the explanation of the present embodiment, the organic layer120may be sealed by a structure which is different from the structure shown inFIG.4. As shown with a black arrow inFIG.4, in the light-emitting unit142, light emitted from the organic layer120is reflected by the second electrode130, the light hardly transmitted through the second electrode130. The light is then transmitted through the first electrode110and the substrate100, and is emitted from the second surface104of the substrate100. As shown with a white arrow inFIG.4, in the light-transmitting unit144, light from outside the light-emitting device10is transmitted through the substrate100, the first electrode110, the organic layer120, the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216. Therefore, in the example shown inFIG.2, the light-emitting device10aincludes a light-transmitting unit144(FIG.4) between adjacent second electrodes130aout of the plurality of second electrodes130a, and a transmitting unit144(FIG.4) between adjacent second electrodes130bout of the plurality of second electrodes130b. FIG.5is a plan view showing a mask300used in formation of the second electrode130of the light-emitting devices10ashown inFIGS.2-4. The mask300includes a shielding member310and a plurality of openings320. The plurality of openings320are formed in the shielding member310. The plurality of openings320include a plurality of openings320aand a plurality of openings320b. The plurality of openings320aextend in the X direction in the drawing. The plurality of openings320bextend in the Y direction in the drawing. The shielding member310includes a portion in which the opening320is not formed (a portion312in the drawing) between the plurality of openings320aand the plurality of openings320b. That is, the plurality of openings320aand the plurality of openings320bare separated by the portion312. Each of the plurality of second electrodes130a(FIG.2) is formed by each of the plurality of openings320a, each of the plurality of second electrodes130b(FIG.2) is formed by each of the plurality of openings320b, and a third region102c(that is, a region in which the second electrode130is not formed) is formed by the portion312. FIG.6is a plan view showing the mask300according to a comparative example. The mask300according to the comparative example is the same as the mask300shown inFIG.5except the following. In the comparative example, all of the plurality of openings320aintersect all of the plurality of openings320bin a region corresponding to the portion312shown inFIG.5. Therefore, the bending portion322is formed in all of the openings320. The mask300shown inFIG.5and the mask300shown inFIG.6are compared. There is a high possibility of the mask300being deformed when gravity acts on the mask300, since many bending portions322are formed in the mask300shown inFIG.6. In contrast, in the mask300shown inFIG.5, there is a low possibility of the mask300being deformed even when gravity acts on the mask300, since the bending portions322shown inFIG.6are not formed in the mask300. Therefore, the plurality of second electrodes130(FIG.2) can be more favorably deposited by using the mask300shown inFIG.5than the mask300shown inFIG.6. Meanwhile, in an example which is different from the one shown inFIG.5, some of the plurality of openings320amay intersect any of the plurality of openings320b. In other words, at least one of the plurality of second electrodes130aneed not intersect any of the plurality of second electrodes130b. In this example, the bending portion322is formed in some of the plurality of openings320. However, the number of the bending portions322can be reduced compared to the example shown inFIG.6. Therefore, even when at least one of the plurality of second electrodes130adoes not intersect any of the plurality of second electrodes130b, it is possible to inhibit the mask300from being deformed, and the plurality of second electrodes130(FIG.2) can be favorably deposited to a certain degree. Next, an example of a method of manufacturing the light-emitting device10ais explained usingFIGS.4-5. First, the first electrode110is formed on the first surface102of the substrate100. In one example, the first electrode110can be formed by patterning a conductive material. Then, the insulating layer150is formed on the first surface102of the substrate100. In one example, the insulating layer150can be formed by patterning an insulating material. Thereafter, the organic layer120is formed over the first surface102of the substrate100. In one example, at least one layer of the organic layer120can be formed by a coating process. Next, the second electrode130is formed over the first surface102of the substrate100. The second electrode130can be formed by deposition using the mask300shown inFIG.5. Next, the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216are formed in an order over the first surface102of the substrate100. The light-emitting device10ais manufactured in the above manner. FIG.7is a diagram showing a modification example ofFIG.2. The plurality of second electrodes130aand the plurality of second electrodes130bare not symmetrically arranged with respect to the third region102c. Specifically, the plurality of second electrodes130aextend in a first direction (X direction ofFIG.7) from the side100atoward the side100fin a striped pattern. The plurality of second electrodes130bextend from the side100bin a second direction (Y direction ofFIG.7) in a striped pattern. The plurality of second electrodes130bdo not reach the side100e, but face the side100ewith the plurality of second electrodes130atherebetween. The second electrodes130bare shorter than the second electrodes130a. In the example shown inFIG.7, the plurality of second electrodes130ahave substantially equivalent lengths in the first direction (X direction ofFIG.7). Therefore, voltage drops between both ends of the second electrodes130acan be inhibited from varying between the plurality of second electrodes130a. Therefore, luminescence of the light-emitting units142(FIG.4) in the extending direction of the second electrode130a(X direction ofFIG.7) can be inhibited from varying between the plurality of second electrodes130a. Similarly, in the example shown inFIG.7, the plurality of second electrodes130bhave substantially equivalent lengths in the second direction (Y direction ofFIG.7). Therefore, voltage drops between both ends of the second electrode130bcan be inhibited from varying between the plurality of second electrodes130b. Therefore, the luminescence of the light-emitting units142(FIG.4) in the extending direction of the second electrodes130b(Y direction ofFIG.7) can be inhibited from varying between the plurality of second electrodes130b. FIG.8is a plan view showing the mask300used in formation of the second electrode130of the light-emitting device10ashown inFIG.7. The plurality of openings320aand the plurality of openings320bare separated by the portion312. Therefore, a bending portion corresponding to the bending portion322shown inFIG.6is not formed in the opening320. In the example shown inFIG.8also, it is possible to inhibit the mask300from being deformed, and the plurality of second electrodes130(FIG.7) can be favorably deposited. FIG.9is a diagram to explain Example 1 of the arrangement of the light-emitting device10aand the light-emitting device10b(light-emitting module) shown inFIG.1. A summary of the light-emitting module is explained usingFIG.9. The light-emitting module includes the light-emitting device10a(first light-emitting device), the light-emitting device10b(second light-emitting device), and the reflecting member20. As explained usingFIG.4, the light-emitting device10aincludes the light-emitting unit142and the light-transmitting unit144. At least a portion of light (light L3inFIG.9) emitted from the light-emitting device10band reflected by the reflecting member20is transmitted through the light-transmitting unit144of the light-emitting device10a. According to the above-mentioned configuration, it is possible to combine light emitted from the light-emitting device10aand light emitted from the light-emitting device10bby a novel method. Specifically, in the above-mentioned configuration, light emitted from the light-emitting device10band reflected by the reflecting member20(light L3inFIG.9) is transmitted through the light-transmitting unit144of the light-emitting device10a. Therefore, it is possible to combine light emitted from the light-emitting device10aand light emitted from the light-emitting device10bby the light-transmitting unit144of the light-emitting device10a. In one example, the wavelength of light emitted from the light-emitting device10bcan be made substantially equal to the wavelength of light emitted from the light-emitting device10a. In this example, luminescence of light emitted from the light-emitting device10acan be enhanced compared to an example in which the light-emitting device10bis not provided. In another example, the wavelength of light emitted from the light-emitting device10bcan be made different from the wavelength of light emitted from the light-emitting device10a. In this example, by combining light emitted from the light-emitting device10aand light emitted from the light-emitting device10b, light of a color can be generated that is different from either the color of light emitted from the light-emitting device10aor the color of light emitted from the light-emitting device10b, without separately coloring a light-emitting layer so that a different color is emitted or providing a complicated circuit system. Details of the light-emitting module is explained usingFIG.9. The substrate100of the light-emitting device10aincludes the first surface102and the second surface104. The light-emitting device10ais arranged so that the first surface102of the substrate100faces a reflecting surface22of the reflecting member20. As explained usingFIG.4, most of light emitted from the organic layer120(FIG.4) is emitted from the second surface104of the substrate100, and is not emitted from the first surface102of the substrate100. In the example shown inFIG.9, light emitted from the second surface104of the substrate100(light L1) is emitted toward a direction away from the reflecting surface22of the reflecting member20without being reflected by the reflecting surface22of the reflecting member20. The light-emitting device10bincludes a first surface12and a second surface14. The second surface14is located on the opposite side of the first surface12. The light-emitting device10bcan emit light from both of the first surface12and the second surface14. The light-emitting device10bis arranged so that the second surface14faces the reflecting surface22of the reflecting member20. In the example shown inFIG.9, light emitted from the first surface12of the light-emitting device10b(light L2) is emitted toward a direction away from the reflecting surface22of the reflecting member20without being reflected by the reflecting surface22of the reflecting member20. At least a portion of light emitted from the second surface14of the light-emitting device10b(light L3) is reflected by the reflecting surface22of the reflecting member20and is transmitted through the light-transmitting unit144of the light-emitting device10a. Meanwhile, all of the light emitted from the second surface14of the light-emitting device10bneed not be reflected by the reflecting surface22of the reflecting member20and transmitted through the light-transmitting unit144of the light-emitting device10a. For example, a portion of the light emitted from the second surface14of the light-emitting device10bmay be reflected by the reflecting surface22of the reflecting member20and emitted toward a direction away from the reflecting surface22of the reflecting member20without being transmitted through the light-emitting device10a. The orientation of at least a portion of light emitted from the second surface14of the light-emitting device10b(light L3) may be set to be different from the orientation of light from the second surface104of the substrate100(light L1) by appropriately adjusting the angle formed between the portion of light and the reflecting surface22of the reflecting member20. Thus, light having an orientation of one of the light L1and the light L3or light having both orientations of the light L1and the light L3can be generated from the second surface104of the substrate100. In the example shown inFIG.9, the light-emitting device10aand the light-emitting device10bare in proximity of each other. Specifically, a portion of the light-emitting device10ais overlapped by a portion of the light-emitting device10bin the direction orthogonal to the first surface12or the second surface14of the light-emitting device10b. In the example shown inFIG.9, the light-emitting device10ais located closer to the reflecting surface22of the reflecting member20than the light-emitting device10b. FIG.10is a diagram showing Modification Example 1 ofFIG.9. As shown inFIG.10, the light-emitting device10bmay be located closer to the reflecting surface22of the reflecting member20than the light-emitting device10a. In the example shown inFIG.10also, the light-emitting device10aand the light-emitting device10bare in proximity of each other. Specifically, a portion of the light-emitting device10aoverlaps a portion of the light-emitting device10bin the direction orthogonal to the first surface12or the second surface14of the light-emitting device10b. FIG.11is a diagram showing Modification Example 2 ofFIG.9. In the example shown inFIG.11, the light-emitting device10ais arranged so that the second surface104of the substrate100faces the reflecting surface22of the reflecting member20. Similarly to the example shown inFIG.9, most of the light emitted from the organic layer120(FIG.4) is emitted from the second surface104of the substrate100, and is not emitted from the first surface102of the substrate100. In the example shown inFIG.11, light emitted from the second surface104of the substrate100(light L1) is reflected by the reflecting surface22of the reflecting member20and is transmitted through the light-emitting device10a. In the example shown inFIG.11, it is possible to make light emitted from the light-emitting device10band transmitted through the light-emitting device10a(light L3) easier to see. Specifically, in the example shown inFIG.11, light emitted from the light-emitting device10acannot be directly seen from the first surface102side of the substrate100. Therefore, the light emitted from the light-emitting device10band transmitted through the light-emitting device10a(light L3) becomes easier to see. FIG.12is a diagram to explain Example 1 of the light-emitting device10bshown inFIG.9. The light-emitting device10bincludes a light-emitting member10b1(first light-emitting member) and a light-emitting member10b2(second light-emitting member). Each of the light-emitting member10b1and the light-emitting member10b2is provided with the substrate100and the light-emitting unit142. The substrate100includes the first surface102and the second surface104. The light-emitting unit142is located on the first surface102side of the substrate100. The second surface104is located on the opposite side of the first surface102. The light-emitting device10bcan emit light from both of the first surface12and the second surface14. Specifically, each of the light-emitting member10b1and the light-emitting member10b2can emit light from the second surface104. In the example shown inFIG.12, as shown with a black arrow, light emitted from the light-emitting unit142is transmitted through the substrate100and emitted from the second surface104of the substrate100. The light-emitting member10b1and the light-emitting member10b2are joined to a supporting member410(details of the supporting member410to be described later usingFIGS.22-25) through an adhesive layer16so that the first surface102of the light-emitting member10b2faces the first surface102of the light-emitting member10b1. In this manner, the light-emitting device10bcan emit light from both of the first surface12and the second surface14. That is, the second surface104of the light-emitting member10b1serves as the first surface12of the light-emitting device10b, and the second surface104of the light-emitting member10b2serves as the second surface14of the light-emitting device10b. FIG.13is a plan view showing the light-emitting member10b1shown inFIG.12.FIG.14is a diagram in which the second electrode130is removed fromFIG.13.FIG.15is a cross-sectional view taken along line B-B ofFIG.13. The light-emitting member10b1is the same as the light-emitting device10ashown inFIGS.2-4except the following. Details of the plan layout of the light-emitting member10b1is explained usingFIGS.13-14. The second electrode130continuously extends from the side100ato the side100b, along the side100c, the side100d, the side100e, and the side100f. Further, the second electrode130continuously extends from the side100cand the side100dto the side100eand the side100f. That is, the second electrode130shown inFIG.13, unlike the plurality of second electrodes130shown inFIG.2, is not arranged in a striped pattern. Therefore, the light-emitting member10b1, unlike the light-emitting device10a, does not include the light-transmitting unit144(FIG.4) and does not have light-transmitting properties. Details of the cross-sectional structure of the light-emitting member10b1is explained usingFIG.15. The insulating layer150defines each of two light-emitting units142by each of two openings152. The first segment110aof the first electrode110configures one of the two light-emitting units142, and the second segment110bof the first electrode110configures the other of the two light-emitting units142. The organic layer120extends across the two light-emitting units142. The second electrode130also extends across the two light-emitting units142. The light-emitting member10b1includes a covering layer221, an adhesive layer222, a desiccant223, and a layer224. The covering layer221, the adhesive layer222, the desiccant223, and the layer224are laminated in order over the first surface102of the substrate100. The covering layer221is provided to shield a substance (for example, vapor or oxygen) which can deteriorates the light-emitting unit142, particularly the organic layer120. The covering layer221is formed by ALD, and includes an inorganic material having insulating properties. The adhesive layer222is provided to adhere the desiccant223. The desiccant223is provided to protect the organic layer120from vapor. The desiccant223is adhered to the first surface102of the substrate100through the adhesive layer222. The layer224covers the desiccant223. In one example, the layer224may be a metal layer (for example, an Al layer). The structure to seal the light-emitting unit142of the light-emitting member10b1is not limited to the example shown inFIG.15. As is clear from the explanations of the present embodiment, the light-emitting unit142may be sealed by a structure different from the structure shown inFIG.15. As shown inFIG.15with a black arrow, most of the light emitted from the organic layer120is emitted from the second surface104of the substrate100, and is not emitted to the first surface102side of the substrate100. Specifically, the substrate100and the first electrode110have light-transmitting properties, and the second electrode130has light shielding properties, particularly, light reflectivity. Therefore, light emitted from the organic layer120is reflected by the second electrode130, transmitted through the first electrode110and the substrate100, and emitted from the second surface104of the substrate100, the light hardly transmitted through the second electrode130. The light-emitting member10b2(FIG.12) also includes a configuration which is the same as the light-emitting member10b1shown inFIGS.13-15. FIG.16is a diagram to explain Example 2 of the light-emitting device10bshown inFIG.9. The light-emitting device10bshown inFIG.16is the same as the light-emitting member10b1shown inFIG.15except the following. As shown inFIG.16with a black arrow, approximately half of the light emitted from the organic layer120is emitted from the second surface104of the substrate100, and approximately the other half of the light emitted from the organic layer120is emitted from the protective layer216(that is, the first surface102side of the substrate100). Specifically, the substrate100and the first electrode110have light-transmitting properties, and the second electrode130also has light-transmitting properties. Therefore, light emitted from the organic layer120can be transmitted through not only the first electrode110and the substrate100, but also through the second electrode130. Therefore, approximately half of the light emitted from the organic layer120is emitted from the second surface104of the substrate100, and approximately the other half of the light emitted from the organic layer120is emitted from the protective layer216(that is, the first surface102side of the substrate100). That is, the second surface104of the substrate100serves as one of the first surface12and the second surface14of the light-emitting device10b(FIG.9), and the surface of the protective layer216is the other of the first surface12and the second surface14of the light-emitting device10b(FIG.9). Similarly to the first electrode110, the second electrode130includes a light-transmitting conductive material, and has light-transmitting properties. The light-transmitting conductive material is, for example, a metal oxide (for example, ITO, IZO, IWZO, ZnO) or IGZO, a carbon nanotube, an electroconductive polymer (for example, PEDOT/PSS) or a metal film having light-transmitting properties (for example, Ag), or an alloy film (for example, AgMg). The light-transmitting conductive material contained in the second electrode130may be the same as the light-transmitting conductive material contained in the first electrode110, or may be different therefrom. In the example shown inFIG.16, the light-emitting device10bincludes a sealing structure (the layer211, the covering layer212, the intermediate layer213, the layer214, the covering layer215, and the protective layer216) which is the same as the sealing structure of the light-emitting device10ashown inFIG.4. Therefore, light emitted from the organic layer120can be transmitted through the sealing structure. FIG.17is a diagram to explain Example 3 of the light-emitting device10bshown inFIG.9. In the example shown inFIG.17, the light-emitting device10bincludes two first electrodes110, two organic layers120, and one second electrode130. The first electrode110has light-transmitting properties, and the second electrode130has light shielding properties, specifically, light reflectivity. The two organic layers120are located on the opposite side of each other with the second electrode130therebetween. The two first electrodes110are located on the opposite side of each other with the second electrode130and the two organic layers120therebetween. That is, the second electrode130configures one light-emitting unit with a first electrode110and an organic layer120on one side of the second electrode130, and configures another light-emitting unit with a first electrode110and an organic layer120on the other side of the second electrode130. In other words, these two light-emitting units share the second electrode130. As shown with a black arrow inFIG.17, light emitted from one organic layer120is transmitted through the first electrode110and emitted toward the opposite side of the second electrode130, and light emitted from the other organic layer120is transmitted through the first electrode110and emitted toward the opposite side of the second electrode130. In this manner, as shown inFIG.9, the light-emitting device10bcan emit light from both surfaces of the light-emitting device10b(first surface12and second surface14ofFIG.9). FIG.18is a diagram to explain an example of the arrangement of a plurality of the light-emitting devices10c(light-emitting module) shown inFIG.1.FIG.19is a diagram of the plurality of light-emitting devices10cshown inFIG.18when viewed from the second surface104side of the substrate100.FIG.20is a cross-sectional view taken along line C-C ofFIG.19. A summary of the light-emitting module is explained usingFIG.20. The light-emitting module includes the plurality of light-emitting devices10c. The plurality of light-emitting devices10care aligned in the first direction (X direction ofFIG.20). The plurality of light-emitting devices10cemit light toward a region RG (that is, a region located on one side of the plurality of light-emitting devices10c). The plurality of light-emitting devices10chave peaks (the peaks are shown with arrows inFIG.20) in directions which are different from each other in a light distribution D (that is, a light distribution on a cross-section (surface ZX ofFIG.20) along both of the first direction (X direction ofFIG.20) and the second direction (Z direction ofFIG.20: the light emission direction of the plurality of light-emitting devices10c)). According to the above-mentioned configuration, light with a high luminous intensity can be emitted toward a region facing the plurality of light-emitting devices10c(particularly, the region RG inFIG.20) over a wide angle. Specifically, in the above-mentioned configuration, the plurality of light-emitting devices10chave peaks in directions which are different from each other in the light distribution D. Therefore, the peak in the light distribution D in each light-emitting device10cis not localized only in a specific direction, and the peaks can be dispersed over a wide angle. Therefore, light with a high luminous intensity can be emitted toward a region facing the plurality of light-emitting devices10cover a wide angle. Each light-emitting device10cincludes a light-emitting region140(light-emitting unit142). The light-emitting device10cincludes a configuration which is the same as, for example, the light-emitting member10b1as shown inFIGS.12-15. The wavelength of light emitted from the light-emitting device10cmay be different from or substantially the same as the wavelength of light emitted from the light-emitting member10b1. Details of the light-emitting module is explained usingFIG.18. The plurality of light-emitting devices10care convexly curved toward the region RG (FIG.20) when viewed from a direction along the above-mentioned cross section (surface ZX ofFIG.20). The plurality of light-emitting devices10chave substantially the same shape, and specifically, are curved at a substantially equivalent curvature. As is clear from the explanation of the present embodiment, the plurality of light-emitting devices10cmay be curved at curvatures which are different from each other. Details of the light-emitting module is explained usingFIG.19. The plurality of light-emitting devices10chave substantially the same shape. Therefore, the area of the light-emitting region140(light-emitting unit142) of each of the plurality of light-emitting devices10cis substantially the same. Details of the light-emitting device10cis explained usingFIG.20. In the example shown inFIG.20, the light distribution D of each light-emitting device10cis a Lambertian distribution. In this example, the direction of the peak of the light distribution D is the normal direction of the second surface104of the light-emitting device10c. In another example, the light distribution D of each light-emitting device10cmay be different from the Lambertian distribution. In the example shown inFIG.20, angles (θ1, θ2, θ3, θ4, θ5, and θ6) in directions (directions of black arrows inFIG.20) of peaks with respect to the first direction (X direction ofFIG.20) vary depending on the light-emitting device10c. Specifically, inFIG.20, the angles become larger (θ1<θ2<θ3<θ4<θ5<θ6) from the light-emitting device10cat the left side toward the light-emitting device10cat the right side. That is, the plurality of light-emitting devices10cinclude a first light-emitting device (light-emitting device10c), a second light-emitting device (light-emitting device10c), and a third light-emitting device (light-emitting device10c) in order along the first direction (X direction ofFIG.20), and the above-mentioned angles become larger or smaller in the order of the first light-emitting device, the second light-emitting device, and the third light-emitting device. According to such a configuration, the light distribution of light emitted toward the region (region RG inFIG.20) facing the plurality of light-emitting devices10ccan be inhibited from varying. The direction of the peak of the light distribution D in each light-emitting device10can be adjusted by various methods. In the example shown inFIG.20, the direction of the peak of the light distribution D is adjusted by the normal direction of the second surface104of the light-emitting device10c, that is, by the installation angle of the light-emitting device10c. In more detail, the inclination of the end of each light-emitting device10c(φ1-φ6inFIG.20) with respect to the first direction (X direction ofFIG.20) varies depending on the light-emitting device10c, and in the example shown inFIG.20, φ1<φ2<φ3<φ4<φ5<φ6. FIG.21is a diagram showing a modification example ofFIG.20. In the example shown inFIG.21, the inclination of the end of each light-emitting device10cwith respect to the first direction (X direction ofFIG.20) is constant (φ). Meanwhile, each light-emitting device10ccurves at a curvature different from another light-emitting device10cso that the direction of the peak of the light distribution D varies depending on the light-emitting device10c. In the example shown inFIG.21also, the direction of the peak of the light distribution D in each light-emitting device10can be adjusted. FIG.22is a diagram to explain a method to install the light-emitting device10on the supporting member410.FIG.23is a cross-sectional view taken along line D-D ofFIG.22.FIG.24is a diagram to explain a method to install the supporting member410(light-emitting module) shown inFIG.22. A summary of the light-emitting module is explained usingFIG.24. The light-emitting module includes the light-emitting device10, the supporting member410, and a shielding member420. The supporting member410includes a first region410aand a second region410b. The second region410bis different from the first region410a. The light-emitting device10is installed in the first region410aof the supporting member410. The shielding member420includes a first opening422a. The first region410aand the second region410bof the supporting member410are located on the opposite side of each other with the first opening422atherebetween. Specifically, the first region410aand the second region410bof the supporting member410pass through the first opening422afrom the first region410ato the second region410bto be located on the opposite side of each other with the shielding member420therebetween. The second region410bof the supporting member410is fixed to a member424a(that is, a member which is located on the same side as the second region410bwith respect to the shielding member420). According to the above-mentioned configuration, it is possible to make the structure on which the light-emitting device10is installed less noticeable. Specifically, in the above-mentioned configuration, the supporting member410passes through the first opening422afrom the first region410ato the second region410bso that the first region410aand the second region410bare located on the opposite side of each other with the shielding member420therebetween, and the second region410bof the supporting member410is fixed to the member424a. The structure on which the light-emitting device10is installed (for example, the member424aand surroundings thereof) can be provided on the opposite side of the light-emitting device10with the shielding member420therebetween, and is hardly noticeable from the side of the light-emitting device10due to the shielding member420. Therefore, it is possible to make the structure on which the light-emitting device10is installed less noticeable. In the example shown inFIG.24, the light-emitting module includes a first wiring member430a. The first wiring member430ais connected to the light-emitting device10, and extends from the first region410ato the outside of the supporting member410via the second region410b. The first wiring member430apasses through the first opening422aof the shielding member420. According to the above-mentioned configuration, it is possible to make the structure to supply electrical power to the light-emitting device10less noticeable. Specifically, in the above-mentioned configuration, the first wiring member430apasses through the first opening422aof the shielding member420. Electrical power can be supplied to the light-emitting device10via the first wiring member430a. The structure to supply electrical power (for example, a circuit connected to the first wiring member430a) can be provided on the opposite side of the light-emitting device10with the shielding member420therebetween, and is hardly noticeable from the side of the light-emitting device10due to the shielding member420. Therefore, it is possible to make the structure to supply electrical power to the light-emitting device10less noticeable. In addition, according to the above-mentioned configuration, the supporting member410and the first wiring member430acan pass through the shielding member420via a common opening (that is, the first opening422a). Therefore, the number of the openings formed in the shielding member420can be reduced. In another example, the supporting member410and the first wiring member430amay pass through the shielding member420via different openings. In this example also, it is possible to make less noticeable the structure on which the light-emitting device10is installed and the structure to supply electrical power to the light-emitting device10. In the example shown inFIG.24, the supporting member410includes a third region410c. The third region410cis on the opposite side of the second region410bwith the first region410atherebetween. The shielding member420includes a second opening422b. The first region410aand the third region410cof the supporting member410are located on the opposite side of each other with the second opening422btherebetween. Specifically, the first region410aand the third region410cof the supporting member410pass through the second opening422bfrom the first region410ato the third region410cto be located on the opposite side of each other with the shielding member420therebetween. The third region410cof the supporting member410is fixed to a member424b(that is, a member which is located on the same side as the third region410cwith respect to the shielding member420). According to the above-mentioned configuration, as is the case with the above-mentioned reasons, it is possible to make the structure (for example, the member424band surroundings thereof) on which the light-emitting device10to be installed less noticeable. In addition, according to the above-mentioned configuration, both sides of the supporting member410can be fixed. Therefore, the supporting member410can be stably installed. Particularly as shown inFIG.24, the first region410aof the supporting member410can be curved from the first opening422ato the second opening422b. In the example shown inFIG.24, the light-emitting module includes a second wiring member430b. The second wiring member430bis connected to the light-emitting device10, and extends from the first region410ato the outside of the supporting member410via the third region410c. The second wiring member430bpasses through the second opening422bof the shielding member420. According to the above-mentioned configuration, as is the case with the above-mentioned reason, it is possible to make the structure (for example, a circuit connected to the second wiring member430b) to supply electrical power to the light-emitting device10less noticeable. In addition, according to the above-mentioned configuration, the supporting member410and the second wiring member430bcan pass through the shielding member420via a common opening (that is, the second opening422b). Therefore, the number of the openings formed in the shielding member420can be reduced. In another example, the supporting member410and the second wiring member430bmay pass through the shielding member420via different openings. In this example also, it is possible to make less noticeable the structure on which the light-emitting device10is installed and the structure to supply electrical power to the light-emitting device10. Details of the light-emitting module is explained usingFIG.22. The light-emitting device10shown inFIG.22includes a configuration which is the same as the light-emitting device10ashown inFIGS.2-4or the light-emitting member10b1shown inFIGS.13-15. The supporting member410is L-shaped. Specifically, the supporting member410includes a portion extending from the first region410ato the second region410bin the first direction (Y direction ofFIG.22), and a portion extending from the first region410ato the third region410cin the second direction (X direction ofFIG.22) which intersects the first direction. The second region410bprotrudes further outward than the side100aof the light-emitting device10, and the third region410cprotrudes further outward than the side100bof the light-emitting device10. A plurality of wiring members430are connected to the light-emitting device10. The wiring members430may be, for example, flexible printed circuits (FPC). In the example shown inFIG.22, the first wiring member430a(wiring member430) is connected to the side100aof the light-emitting device10, and the second wiring member430b(wiring member430) is connected to the side100bof the light-emitting device10. The wiring member430is connected to the terminal114and the terminal134(for example,FIG.2,FIG.3,FIG.13, andFIG.14). Therefore, the wiring member430can be electrically connected to the first electrode110and the second electrode130(for example,FIG.4andFIG.15). In the example shown inFIG.22, openings416are formed in both sides of the supporting member410with a portion of the first wiring member430atherebetween, and the openings416are formed in both sides of the supporting member410with a portion of the second wiring member430btherebetween. The openings416are provided so as to fix the supporting member410. Particularly in the later described example shown inFIG.24, the supporting member410is fixed by screwing a screw in the member424a(member424b) via the openings416. Details of the light-emitting module is explained usingFIG.23. The supporting member410includes a first surface412and a second surface414. The second surface414is on the opposite side of the first surface412. The light-emitting device10is installed on the supporting member410via an adhesive layer440so that the first surface102of the substrate100faces the first surface412of the supporting member410. A portion of the wiring member430is embedded in the adhesive layer440. The supporting member410is formed of a metal (for example, Al). In this case, the supporting member410functions as a soaking plate. In another example, the supporting member410may be formed of a light-transmitting resin (for example, acrylic) and may fix the light-emitting device10outside the light-emitting region. In this case, by making the adhesive layer440a light-transmitting material, even when the light-emitting device10ais supported, it is possible to inhibit light-transmitting properties from becoming impaired. Details of the light-emitting module is explained usingFIG.24. In the example shown inFIG.24, the second region410bof the supporting member410is fixed to the member424ain a direction from the second region410bside to the third region410cside of the supporting member410by a fixing member (specifically, a screw), and the third region410cof the supporting member410is fixed to the member424bin a direction from the third region410cside to the second region410bside of the supporting member410by a fixing member (specifically, a screw). Due to the curve of the first region410aof the supporting member410, an internal stress (restoring force) is generated to deform the supporting member410in a direction separating the second region410band the third region410cfrom each other on the supporting member410. By the above-mentioned fixing member, deformation of the supporting member410by an internal stress can be inhibited. FIG.25is a diagram showing a modification example ofFIG.22. The light-emitting module includes a plurality of shielding films450(first shielding film450aand second shielding film450b). The first shielding film450acovers a portion of the first wiring member430a. This portion is located on the same side as the first region410awith respect to the shielding member420inFIG.24. Therefore, even when the portion of the first wiring member430ais exposed on the light-emitting device10side inFIG.24, the portion can be hidden by the first shielding film450a. The second shielding film450bcovers a portion of the second wiring member430b. This portion is located on the same side as the first region410awith respect to the shielding member420inFIG.24. Therefore, even when the portion of second wiring member430bis exposed on the light-emitting device10side inFIG.24, the portion can be hidden by the second shielding film450b. The shielding film450favorably has an appearance (for example, color or glossiness) which is similar to the appearance (for example, color or glossiness) of a member in the surroundings of the shielding film450to hide the wiring member430. For example, in a case where the second electrode130of the light-emitting device10(for example,FIG.4andFIG.15) is conspicuous, the shielding film450may have an appearance which is similar to appearance (for example, silver) of the second electrode130of the light-emitting device10. As described above, according to the present embodiment, a light-emitting device and the light-emitting module having a new structure are provided. As described above, although the embodiment and examples of the present invention have been set forth with reference to the accompanying drawings, they are merely illustrative of the present invention, and various configurations other than those stated above can be adopted. This application claims priority from Japanese Patent Application No. 2017-203218, filed Oct. 20, 2017, the disclosure of which is incorporated by reference in its entirety. | 67,919 |
11943951 | DETAILED DESCRIPTION The advantages and features of the present disclosure and methods of achieving the same will be apparent by referring to embodiments of the present disclosure as described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments set forth below, but may be implemented in various different forms. The following embodiments are provided only to completely disclose the present disclosure and inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the appended claims. In addition, the shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally denote like elements throughout the present specification. Further, in the following description of the present disclosure, detailed description of well-known functions and configurations incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure rather unclear. The terms such as “including”, “having”, “containing”, “comprising of”, and “consist of” used herein are generally intended to allow other components to be added unless the terms are used with the term “only”. Singular forms used herein are intended to include plural forms unless the context clearly indicates otherwise. In interpreting any elements or features of the embodiments of the present disclosure, it should be considered that any dimensions and relative sizes of layers, areas and regions include a tolerance or error range even when a specific description is not conducted. Spatially relative terms, such as” “on”, “over”, “above”, “below”, “under”, “beneath”, “lower”, “upper”, “near”, “close”, “adjacent”, and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures, and it should be interpreted that one or more elements may be further “interposed” between the elements unless the terms such as ‘directly’, “only” are used. Time relative terms, such as “after”, “subsequent to”, “next to”, “before”, or the like, used herein to describe a temporal relationship between events, operations, or the like are generally intended to include events, situations, cases, operations, or the like that do not occur consecutively unless the terms, such as ‘immediately’, or the like, are used. When embodiments related to signal flows are discussed, for example, an embodiment where a signal is transmitted from node A to node B may include the transmission of the signal from node A to node B by way of another node unless the terms such as “directly”, “only” are used. When the terms, such as “first”, “second”, or the like, are used herein to describe various elements or components, it should be considered that these elements or components are not limited thereto. These terms are merely used herein for distinguishing an element from other elements. Therefore, a first element mentioned below may be a second element in a technical concept of the present disclosure. The elements or features of various exemplary embodiments of the present disclosure can be partially or entirely bonded to or combined with each other and can be interlocked and operated in technically various ways as can be fully understood by a person having ordinary skill in the art, and the various exemplary embodiments can be carried out independently of or in association with each other. A display device according to one aspect of the present disclosure includes a substrate including an active area and a non-active area, a planarization film disposed over the substrate, an anode electrode disposed on the planarization film and including a first hole in the non-active area, a bank disposed on the anode electrode, a cathode electrode disposed on the bank, an encapsulation layer disposed on the cathode electrode, and a touch sensor disposed on the encapsulation layer and including a touch line in the non-active area. Here, the first hole may be disposed not to overlap with the touch line. In the display device, the anode electrode may include a second hole having a size smaller than the first hole, in the non-active area, and the second hole may be disposed to overlap with the touch line. The touch line of the display device may include a plurality of touch signal lines, and the first hole may be disposed between the plurality of touch signal lines. A gate signal generation circuit may be disposed below the planarization film in the non-active area of the substrate of the display device, and the cathode and anode electrodes may be disposed to overlap with the gate signal generation circuit. The first hole of the display device may be disposed to overlap with the gate signal generation circuit. The encapsulation layer of the display device may include a first inorganic film, a second inorganic film, and an organic film disposed between the first and second inorganic layers. The first hole of the display device may be disposed at a region in which the planarization film and the bank contact with each other. In accordance with another aspect of the present disclosure, a method of manufacturing a display device is provided that includes disposing a planarization film over a substrate including an active area and a non-active area, disposing an anode electrode including a first hole in the non-active area, on the planarization film, disposing a bank on the anode electrode, disposing a cathode electrode on the bank, disposing an encapsulation layer on the cathode electrode, and disposing a touch sensor including a touch line in the non-active area, on the encapsulation layer. Here, the first hole may be disposed not to overlap with the touch line. In the manufacturing method of the display device, the anode electrode may include a second hole having a size smaller than the first hole, in the non-active area, and the second hole may be disposed to overlap with the touch line. In the manufacturing method of the display device, the touch line may include a plurality of touch signal lines, and the first hole may be disposed between the plurality of touch signal lines. In the manufacturing method of the display device, a gate signal generation circuit may be disposed in the non-active area of the substrate before disposing the planarization film, and the cathode and anode electrodes may be disposed to overlap with the gate signal generation circuit. In the manufacturing method of the display device, the first region may be disposed to overlap with the gate signal generation circuit. In the manufacturing method of the display device, the encapsulation layer may include a first inorganic film, a second inorganic film, and an organic film disposed between the first and second inorganic layers. In the manufacturing method of the display device, the first hole may be disposed at a region in which the planarization film and the bank contact with each other. Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail. FIG.1illustrates a system configuration of a display device according to aspects of the present disclosure. Referring toFIG.1, the display device100includes a display panel110, a data driver120, a gate driver130, and a timing controller140. The display device100can includes one or more touch sensors disposed to overlap with the display panel100. The display panel110can include a plurality of pixels101that are arranged in a matrix form. The plurality of pixels101each may emit a red color light, a green color light, a blue color light, or the like. However, light emitted by each pixel according to embodiments herein is not limited thereto. For example, the pixel may emit a white color light. Further, the display panel110may have a rectangular shape. The display panel110can include a plurality of gate lines (GL1to GLn), a plurality of data lines (DL1to DLm), and a plurality of pixels101each connected with each of the plurality gate lines (GL1to GLn) and each of the plurality lines (DL1to DLm). Each pixel101can receive a data signal through each of the plurality lines (DL1to DLm) according to a gate signal delivered through each of the plurality gate lines (GL1to GLn) However, lines arranged in the display panel110according to embodiments herein are not limited thereto. The data driver120is connected to the plurality of data lines (DL1to DLm), and can transfer data signals to the pixels101through the plurality of data lines (DL1to DLm). Here, althoughFIG.1shows a single data driver120, embodiments of the present disclosure are not limited thereto. For example, the display device includes a plurality of data drivers when desired. The gate driver130is connected to the plurality of gate lines (GL1to GLn), and can supply gate signals to the pixels101through the plurality of gate lines (GL1to GLn). Here, althoughFIG.1shows that the gate driver130is located in one side of the display panel110, embodiments of the present disclosure are not limited thereto. For example, gate drivers130may be disposed in two sides of display panel110. Further, one of two or more gate drivers may be connected to odd-numbered gate lines, and another, or the other, of the gate drivers may be connected to even-numbered gate lines. Further, the display device100may include a gate signal generation circuit for supplying gate signals to the display panel110without including a separate gate driver. The timing controller140can control the data driver120and the gate driver130. The timing controller140can supply image signals (RGB) and data control signals (DCS) to the data driver120, and supply gate control signals GCS to the gate driver130. The touch sensor150may be disposed to overlap with at least a portion of the display panel110and can detect a touch performed on the display panel110by a user. The touch sensor150may include one or more touch electrodes, and one or more touch lines for delivering one or more touch signals to one or more touch electrodes. FIG.2is a circuit diagram of a pixel used in the display device according to aspects of the present disclosure. Referring toFIG.2, the pixel101can include a pixel circuit for supplying a driving current, and a light emitting element ED, such as a light emitting diode including an organic light emitting diode, which emits light by the driving current. The pixel circuit may include a first transistor M1, a second transistor M2, and a storage capacitor Cst. First and second electrodes of the first transistor M1may be connected to a first power line VL1carrying a first power supply voltage EVDD and a first node N1, respectively. Further, a gate electrode of the first transistor M1may be connected to a second node N2. The first transistor M1can allow a driving current to flow through the first node N1according to a voltage applied to the second node N2. First and second electrodes of the second transistor M2may be connected to a data line DL and the second node N2, respectively. Further, a gate electrode of the second transistor M2may be connected to a gate line GL. The second transistor M2can allow a data signal Vdata delivered through the data line DL to be transferred to the second node N2according to a gate signal GATE delivered through the gate line GL. First and second electrodes of the storage capacitor Cst may be connected to the first node N1and the second node N2, respectively. The storage capacitor Cst may allow a voltage applied to the second node N2to be maintained. The light emitting element ED can include an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode and emitting light when a current flows. The emissive layer may include at least one of an organic material, an inorganic material, and a quantum dot material. The light emitting element ED, such as a light emitting diode including an organic light emitting diode, can receive a driving current flowing through the first node N1, and then, emit light. The first and second transistors M1and M2of the pixel101may be NMOS transistors. However, embodiments of the present disclosure are not limited thereto. Further, the first electrodes and the second electrodes of the first and second transformers (M1and M2) may be drain electrodes and source electrodes, respectively. However, embodiments of the present disclosure are not limited thereto. FIG.3illustrates that a gate signal generation circuit is disposed on a display panel in a display device according to aspects of the present disclosure. Referring toFIG.3, the display panel110may include the gate signal generation circuit130adisposed on or over a substrate111. The substrate111may include an active area110ain which one or more pixels101are disposed, and a non-active area110bin which one or more signal lines for carrying a signal and/or a voltage to the active area110aare disposed. The gate signal generation circuit130amay be disposed in the non-active area110b. The gate signal generation circuit130amay be disposed together with the pixel101in a process of disposing the pixel101in the active area110a. One or more touch sensors150may be disposed on or over the substrate111. The touch sensor150may include one or more touch electrodes, and one or more touch lines for delivering one or more touch signals to one or more touch electrodes. The touch electrode may be disposed to overlap with the active area110a, and the touch line may be disposed to overlap with the non-active area110b. The touch line and the signal line may be disposed on different layers in the non-active area110b. When the touch line is disposed on or over the signal line, a capacitor may be formed between the touch line and the signal line, and a signal flowing through the signal line may act as a noise in the touch line due to such a capacitor. Here, althoughFIG.3shows that the gate signal generation circuit130ais located on one side of the substrate111and disposed to overlap with the substrate111, embodiments of the present disclosure are not limited thereto. For example, gate signal generation circuits130amay be located in respective sides, such as left and right sides, top and bottom sides, or the like, of the substrate111and disposed to overlap with the substrate111. FIG.4is a cross-sectional view taken along with line I-I′ ofFIG.3according to a first embodiment. Referring toFIG.4, a gate insulating film112may be disposed on the substrate111, and the gate signal generation circuit130amay be disposed on the gate insulating film112. AlthoughFIG.4shows the gate signal generation circuit130aincluding a single metal layer; however, it should be noted that this is merely for ease of description. For example, the gate signal generation circuit130amay include a plurality of stacked insulating films and a plurality of metal layers. The gate signal generation circuit130amay include a plurality of transistors. A planarization film113may be disposed on the gate signal generation circuit130a. An anode electrode114may be disposed on the planarization film113. The planarization film113may include photo acryl or polyimide. However, materials or substances that may be included in the planarization film113according to embodiments herein are not limited thereto. When the planarization film113is exposed to the atmosphere, the planarization film113may absorb moisture. The anode electrode114disposed on the planarization film113may include a first hole H1. A portion of the planarization film113may be exposed through the first hole H1. Due to this, the first hole H1may serve as a path for outgas through which gas generated by moisture in the planarization film113can be discharged. A bank115may be disposed on the anode electrode114. The first hole H1may be disposed at a region in which the planarization film113and the bank114contact with each other. A cathode electrode116may be disposed on the bank115. A first inorganic film117, an organic film118, and a second inorganic film119may be sequentially stacked on the cathode electrode116. All or each of the first inorganic film117, the organic film118, and the second inorganic film119may be an encapsulation layer. A thickness of the organic film118may be greater than that of each of the first and second inorganic films117and119. A touch line151may be disposed on the second inorganic film119. The second inorganic film119can prevent the organic film118from being damaged when the touch line151is disposed. The touch line151may be shielded from the gate signal generation circuit130aby the cathode electrode116disposed under the touch line151. However, since the cathode electrode116generally has a large process deviation, the cathode electrode116may not completely cover the gate signal generation circuit130a. Due to this, as the cathode electrode116does not completely shield the gate signal generation circuit130a, noises may be transferred to the touch line151by the gate signal generation circuit130a. FIG.5illustrates a layout of an X-region ofFIG.3according to aspects of the present disclosure. Referring toFIG.5, one or more signal lines132included in the gate signal generation circuit130amay be disposed on or over the substrate111. The signal line132may be a clock signal line for delivering a clock signal supplied to the gate signal generation circuit130a. However, embodiments of the present disclosure are not limited thereto. The anode electrode114may be disposed on one or more signal lines132. A touch line151may be disposed on the anode electrode114. The anode electrode114may include a plurality of first holes HL The plurality of first holes H1may be disposed in three columns each including some of the plurality of first holes H1. However, embodiments of the present disclosure are not limited thereto. The plurality of first holes H1may be disposed not to overlap with the touch sensor150. One of the three columns of the first holes H1is disposed in a first region A in which the touch line151and the signal line132do not overlap with each other, and the other two columns of the first holes H1may be disposed in a second region B in which the touch line151and the signal line132overlap with each other. As the first hole H1is disposed in the anode electrode114, thus, a path for outgas through which gas generated from the planarization film113can travel can be provided, and as a result, it is possible to prevent defects in the display device100from being caused. Although the cathode electrode116is not shown inFIG.5, the cathode electrode116may cover at least a portion or all of one or more signal lines132. The plurality of first holes H1may be disposed in the first region A in which the touch line151and the signal line132do not overlap with each other, and disposed in the second region B in which the touch line151and the signal line132overlap with each other. The anode electrode114may cause the signal line132and the touch line151not to be shielded due to at least one first hole H1disposed in the second region B. FIG.6is a cross-sectional view taken along with line I-I′ ofFIG.3according to a second embodiment. Referring toFIG.6, a gate insulating film112may be disposed on the substrate111, and the gate signal generation circuit130amay be disposed on the gate insulating film112and disposed in a region corresponding to at least a portion of the non-active area110b. AlthoughFIG.6shows the gate signal generation circuit130aincluding a single metal layer; however, it should be noted that this is merely for ease of description. For example, the gate signal generation circuit130amay include a plurality of insulating films and a plurality of metal layers. The gate signal generation circuit130amay include a plurality of transistors. A planarization film113may be disposed on the gate signal generation circuit130a. An anode electrode114may be disposed on the planarization film113, and a cathode electrode116may be disposed on the anode electrode114. The planarization film113may include photo acryl or polyimide. When the planarization film113is exposed to the atmosphere, the planarization film113may absorb moisture. A bank115may be disposed on the anode electrode114. A cathode electrode116may be disposed on the bank115. A first inorganic film117, an organic film118, and a second inorganic film119may be sequentially stacked on the cathode electrode116. All or each of the first inorganic film117, the organic film118, and the second inorganic film119may be an encapsulation layer. A thickness of the organic film118may be greater than that of each of the first and second inorganic films117and119. A touch line151may be disposed on the second inorganic film119. The second inorganic film119can prevent the organic film118from being damaged when the touch line151is disposed. The touch line151may be shielded from a signal line132by the cathode electrode116disposed under the touch line151. The touch line151may be shielded from the signal line132by the anode electrode114disposed under the cathode electrode116. Even when the cathode electrode116generally has a large process deviation, and thus, the cathode electrode116does not completely cover the touch line151, as the touch line151can be shielded by the anode electrode114, it is possible prevent noises from being transferred to the touch line151. FIGS.7A to7Cillustrate layouts of the X-region ofFIG.3according to aspects of the present disclosure. Referring toFIGS.7A to7C, one or more signal lines132included in the gate signal generation circuit130amay be disposed on or over the substrate111. The signal line132may be a clock signal line for delivering a clock signal supplied to the gate signal generation circuit130a. However, embodiments of the present disclosure are not limited thereto. An anode electrode114may be disposed on one or more signal lines132. A touch line151may be disposed on the anode electrode114. The anode electrode114may include a plurality of first holes H1. Although the cathode electrode116is not shown inFIGS.7A to7C, the cathode electrode116may cover at least a portion or all of one or more signal lines132. Referring toFIG.7A, the plurality of first holes H1may be disposed in a first region A among the first region A in which a touch line151and one or more signal lines132do not overlap with each other and a second region B in which the touch line151and the signal line132overlap with each other. Further, the first hole H1may be disposed at a region in which the planarization film113and the bank115contact with each other. Table 1 below shows a comparison between noises in Sample 1, for example, a display device employing the anode electrode shown inFIG.5and noises in Sample 2, for example, a display device employing the anode electrode shown inFIG.7A. TABLE 1Sample 1Sample 2GclkCathodeRxGclkCathodeRx(mV)(mV)(mV)(mV)(mV)(mV)115.6923.0055.9615.7121.4551.55215.7024.7261.1615.6922.0056.77315.7023.0361.0715.7323.6164.54415.7121.5967.7715.7124.6453.38515.7121.1951.8415.7321.1265.19Min15.6921.1951.8415.6921.1251.55Max15.7124.7267.7715.7324.6465.19Avg15.7022.7159.5915.7122.5658.29 In above Table 1, Gclk represents voltages of clock signals output from gate signal generation circuits, and Cathode represents voltages of cathode electrodes. Further, Rx represents voltages of touch signals output from touch lines. Five display devices were used to measure voltages of the clock signals, voltages of the cathode electrodes and voltages of the touch signals. Referring to Table 1 above, minimum, maximum, and average values of each of the voltage of the cathode electrode and the voltage of the touch signal which are measured in Sample 1 (e.g. the display device employing the anode electrode shown inFIG.5) are larger than respective minimum, maximum, and average values of each of the voltage of the cathode electrode and the voltage of the touch signal which are measured in Sample 2 (e.g. the display device employing the anode electrode shown inFIG.7A). It can be seen that noise shielding of the touch sensor150is improved when the first hole H1is removed from a region of the anode electrode114overlapping with the gate signal generation circuit130a. Referring toFIG.7B, the plurality of first holes H1may be disposed in a first region A among the first region A in which a touch line151and one or more signal lines132do not overlap with each other and a second region B in which the touch line151and the signal line132overlap with each other. The touch line151may include a plurality of touch signal lines, and the first region A may be a region disposed between the plurality of touch signal lines. The plurality of first holes H1may not be disposed in the second region B where the touch line151and the signal line132overlap with each other. Accordingly, the anode electrode114may shield the touch line151from the signal line132in the second region B where the touch line151and the signal line132overlap with each other. Referring toFIG.7C, the plurality of first holes H1may be disposed in a first region A among the first region A in which a touch line151and one or more signal lines132do not overlap with each other and a second region B in which the touch line151and the signal line132overlap with each other. Further, one or more second holes H2with a size smaller than the first hole H1may be disposed in the second region B in which the touch line151and the signal line132overlap with each other. Even though the size of the second hole H2formed in the anode electrode114in the second region B is small, the noise shielding of the touch sensor150can be improved. A sum of sizes of the second holes H2corresponding to one first hole H1may be determined to be smaller than half of the size of the first hole H1. InFIG.7C, the sum of respective sizes of four second holes H2may be smaller than half of a size of one first hole H1. As shown inFIGS.7A to7C, at least one of the first hole H1and the second hole H2is disposed on the planarization film113, and provide a path through which outgas can be discharged, and thereby, it is possible to prevent defects in the display device100from occurring. FIG.8is a flow diagram illustrating a method of manufacturing a display device including a touch sensor according to aspects of the present disclosure. Referring toFIG.8, a planarization film113may be disposed on or over a substrate111, at step S810. The substrate111may be formed of glass or polyamide. The planarization film113may be formed of photo acryl or polyimide. When the planarization film113is exposed to the atmosphere, the planarization film113may absorb moisture. A gate signal generation circuit130amay be disposed on the substrate111before the planarization film113is disposed on the substrate111, at step S800. The gate signal generation circuit130amay be disposed in a non-active area110bon or over the substrate111. The gate signal generation circuit130amay be disposed on a side of the substrate111. Gate signal generation circuits130amay be disposed on both sides of the substrate111, for example, left and right sides, top and bottom sides, and the like. The gate signal generation circuit130amay be formed by patterning a conductive layer and may include a signal line132. The signal line132may include a clock signal line for delivering a clock signal to the gate signal generation circuit130a. The gate signal generation circuit130amay include a plurality of transistors. A gate signal generation circuit130amay be disposed in a non-active area110bon or over the substrate111together with the pixels101when one or more pixels101are disposed on or over the substrate111. An anode electrode114may be disposed on the planarization film113, at step S820. The anode electrode114may include one or more first hole H1. As the first hole H1formed in the anode electrode114provides a path of outgas through which gas generated from the planarization film113can travel can be provided, as a result, it is possible to prevent defects in the display device100from being caused. The first hole H1may be disposed to overlap with the gate signal generation circuit130ain the non-active area110b. A bank115may be disposed on the anode electrode114, and the bank115may be disposed to overlap with the first hole H1, at step S830. A cathode electrode116may be disposed on the bank115, at step S840. The cathode electrode116may cover an upper portion of the substrate111. The cathode electrode116may cover an upper portion of the gate signal generation circuit130a. The cathode electrode116may shield the gate signal generation circuit130a. However, in a corresponding manufacturing process, since the cathode electrode116generally has a large process deviation, and thus, may cover only a part of the upper portion of the gate signal generation circuit130a, there is a probability that an effect of using the cathode electrode116for shielding the gate signal generation circuit130amay be degraded. An encapsulation layer may be disposed on the cathode electrode116, at step S850. The encapsulation layer may include a first inorganic film117, a second inorganic film119, and an organic film118disposed between the first and second inorganic films117and119. A thickness of the organic film118may be greater than that of each of the first and second inorganic films117and119. The encapsulation layer can serve to prevent the penetration of foreign substances including moisture and air. A touch sensor150may be disposed on the encapsulation layer. The touch sensor150may include a touch electrodes and a touch line151. Further, the second inorganic film119can prevent the organic film118from being damaged when the touch sensor150is disposed. The first hole H1may be disposed not to overlap with the touch line151. The first holes H1may be disposed in a first region A among the first region A in which the touch line151and one or more signal lines132do not overlap with each other and a second region B in which the touch line151and the signal line132overlap with each other. Since the first hole H1included in the anode electrode114is disposed not to overlap with the touch line151, the touch line151and the signal line132can be shielded by the anode electrode114. Accordingly, as double shielding for the gate signal generation circuit130acan be performed, the shielding of the gate signal generation circuit130acan be improved. The touch line151may include a plurality of touch signal lines, and the first hole H1may be disposed between the plurality of touch signal lines. Further, one or more second holes H2with a size smaller than the first hole H1may be disposed in the second region B in which the touch line151and the signal line132overlap with each other. It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the technical idea or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents. | 31,568 |
11943952 | DETAILED DESCRIPTION Reference will now be made in detail to example embodiments of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Hereinafter, a light-emitting device and a display apparatus including the same will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements throughout, and in the drawings, sizes of elements may be exaggerated for clarity and convenience of explanation. Also, the example embodiments described below are merely examples, and various modifications may be made from the example embodiments. When an element is referred to as being “on” another element, it may be directly on the other element, or intervening elements may be present therebetween. The singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. When a portion “includes” an element, another element may be further included, rather than excluding the existence of the other element, unless otherwise described. The use of the terms “a” and “an,” and “the” and similar referents in the context of describing the present disclosure is to be construed to cover both the singular and the plural. The steps of all methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context, and are not limited to the described order. The terms such as “unit” or “module” refer to units that perform at least one function or operation, and the units may be implemented as hardware or software or as a combination of hardware and software. Also, lines or members connecting elements illustrated in the drawings are merely illustrative of functional connections and/or physical or circuit connections. In an actual device, the connections between components may be represented by various functional connections, physical connections, or circuit connections that are replaceable or added. The use of any and all examples, or language provided herein, is intended merely to better describe the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. FIG.1is a cross-sectional view illustrating a structure of a light-emitting device according to an example embodiment. Referring toFIG.1, a light-emitting device100according to an example embodiment may include a reflective layer110including a plurality of nano-structures112that are two-dimensionally arranged, a first electrode121disposed on the reflective layer110, an organic emission layer130disposed on the first electrode121, and a second electrode122disposed on the organic emission layer130. The light-emitting device100may further include a passivation layer140that is transparent and is disposed on the second electrode122opposite to the organic emission layer130and protects the second electrode122. The light-emitting device100may be an organic light-emitting diode (OLED). For example,FIG.2is a detailed cross-sectional view illustrating a structure of the organic emission layer130ofFIG.1according to an example embodiment. Referring toFIG.2, the organic emission layer130may include a hole injection layer132disposed on a top surface of the first electrode121, an organic emission material layer131disposed on a top surface of the hole injection layer132, and an electron injection layer133disposed on a top surface of the organic emission material layer131. In this structure, holes injected by the hole injection layer132and electrons injected by the electron injection layer133may combine with each other in the organic emission material layer131to generate light. A wavelength of the generated light may be determined by an energy band gap of a light-emitting material of the organic emission material layer131. The organic emission layer130may further include a hole transfer layer134disposed between the hole injection layer132and the organic emission material layer131to more smoothly transfer holes. The organic emission layer130may further include an electron transfer layer135disposed between the electron injection layer133and the organic emission material layer131to more smoothly transfer electrons. The organic emission layer130may include various additional layers when necessary. For example, the organic emission layer130may further include an electron block layer between the hole transfer layer134and the organic emission material layer131, and may further include a hole block layer between the organic emission material layer131and the electron transfer layer135. The organic emission material layer131may be configured to emit visible light. For example, the organic emission material layer131may be configured to emit light in any one of a wavelength band corresponding to red light, a wavelength band corresponding to green light, and a wavelength band corresponding to blue light. However, embodiments are not limited thereto. For example, the organic emission material layer131may be configured to emit white visible light including all of red light, green light, and blue light. For example,FIG.3is a detailed cross-sectional view illustrating a structure of the organic emission layer130ofFIG.1according to another example embodiment. Referring toFIG.3, the organic emission material layer131may include a first organic emission material layer131athat emits red light, a second organic emission material layer131bthat emits green light, and a third organic emission material layer131cthat emits blue light. Also, an exciton blocking layer136may be disposed between the first organic emission material layer131aand the second organic emission material layer131band between the second organic emission material layer131band the third organic emission material layer131c. In this case, the organic emission layer130may emit white light. However, a structure of the organic emission layer130that emits white light is not limited thereto. Instead of including three organic emission material layers, that is, the first through third organic emission material layers131a,131b, and131c, the organic emission layer130may include two organic emission material layers that are complementary to each other. The first electrode121disposed on a bottom surface of the organic emission layer130may function as an anode that provides holes. The second electrode122disposed on the top surface of the organic emission layer130may function as a cathode that provides electrons. To this end, the first electrode121may be formed of a material having a relatively high work function, and the second electrode122may be formed of a material having a relatively low work function. Also, the first electrode121may be a transparent electrode through which light (e.g., visible light) is transmitted. For example, the first electrode121may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum zinc oxide (AZO). The second electrode122may be a semi-transmissive electrode that reflects part of light and transmits the remaining part of the light. To this end, the second electrode122may include a very thin reflective metal. For example, the second electrode122may be formed of silver (Ag), aluminum (Al), gold (Au), nickel (Ni), or an alloy thereof, or may have a two-layer structure including silver (Ag) and magnesium (Mg) or a two-layer structure including aluminum (Al) and lithium (Li). A total thickness of the second electrode122may range from about 10 nm to about 50 nm. Because the second electrode122is very thin, part of light may pass through the reflective metal. The reflective layer110may be configured to reflect light generated by the organic emission layer130and transmitted through the first electrode121. For example, the reflective layer110may be configured to selectively reflect only light of a specific wavelength band and transmit or absorb light of another wavelength band. The reflective layer110and the second electrode122may constitute a micro-cavity. For example, the micro-cavity may be formed between the reflective layer110and the second electrode122of the light-emitting device100. For example, light generated by the organic emission layer130may reciprocate and resonate between the reflective layer110and the second electrode122, and then light corresponding to a resonance wavelength of the micro-cavity may be emitted to the outside through the second electrode122. The resonance wavelength of the micro-cavity formed between the reflective layer110and the second electrode122may be determined by an optical length L of the micro-cavity. For example, when the resonance wavelength of the micro-cavity is λ, the optical length L of the micro-cavity may be nλ/2, where n is a natural number. The optical length L of the micro-cavity may be determined by a sum of an optical thickness of layers constituting the micro-cavity between the reflective layer110and the second electrode122, a phase retardation by the second electrode122, and a phase shift (e.g., a phase retardation) by the reflective layer110. Here, the optical thickness of the layers constituting the micro-cavity between the reflective layer110and the second electrode122is not a simple physical thickness, but is a thickness considering refractive indexes of materials of the layers constituting the micro-cavity. For example, the optical thickness of the layers constituting the micro-cavity may be a sum of an optical thickness of the first electrode121and an optical thickness of the organic emission layer130. According to the example embodiment, the optical length L or the resonance wavelength of the micro-cavity may be adjusted by adjusting only the phase shift by the reflective layer110while fixing the optical thickness of the layers constituting the micro-cavity and the phase retardation by the second electrode122. In order to adjust a wavelength selectivity of the reflective layer110and the phase shift by the reflective layer110, a phase modulation surface may be formed on a reflective surface of the reflective layer110contacting the first electrode121. The phase modulation surface may include very small nano-scale patterns. For example, the phase modulation surface of the reflective layer110may have a meta-structure in which nano-structures having a size smaller than a wavelength of visible light are periodically arranged. Referring toFIG.1, the reflective layer110may include the plurality of nano-structures112two-dimensionally arranged in a regular periodic structure and a low-refractive-index layer111surrounding the plurality of nano-structures112. The low-refractive-index layer111may completely surround a bottom surface, a side surface, and a top surface of each of the nano-structures112. The plurality of nano-structures112may be completely buried and encapsulated in the low-refractive-index layer111. Accordingly, the top surfaces of the plurality of nano-structures112may not contact the first electrode121, and only the top surface of the low-refractive-index layer111may directly contact the first electrode121. The plurality of nano-structures112included in the low-refractive-index layer111may be horizontally arranged on the same plane. Each of the nano-structures112may include a non-metallic material having a first refractive index, and the low-refractive-index layer111may include a dielectric material having a second refractive index lower than the first refractive index. For example, the non-metallic material of each of the nano-structures112may include a dielectric material or a semiconductor material having a high refractive index and a low light absorption in a visible light region. For example, the dielectric material may include at least one of titanium dioxide (TiO2), barium titanate (BaTiO3), chromium oxide (Cr2O3), hafnium dioxide (HfO2), and silicon nitride (SiNx), and the semiconductor material may include at least one of silicon (Si), zinc sulfide (ZnS), zinc selenide (ZnSe), gallium phosphide (GaP), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), and aminolevulinate synthase (AlAs2) Also, the low-refractive-index layer111may be formed of e a dielectric material having a low refractive index and a low absorption in a visible light band such as silicon dioxide (SiO2) or siloxane-based spin on glass (SOG). Although each of the nano-structures112and the low-refractive-index layer111includes a material having a low reflectance, a guide mode resonance is formed by periodically arranging the plurality of nano-structures112having a size smaller than a wavelength of visible light, and thus the reflective layer110may have a high reflectance for light of a specific wavelength. For example, when each nano-structure112has a cylindrical shape, a wavelength of light reflected by the reflective layer110may be determined by a diameter W of each nano-structure112, a thickness T of each nano-structure112, and a pitch or period P of the plurality of nano-structures112. When each nano-structure112has a polygonal column shape, a wavelength of light reflected by the reflective layer110may be determined by a maximum width W of each nano-structure112, the thickness T of each nano-structure112, and the pitch or period P of the plurality of nano-structures112. In particular, when the thickness T of the nano-structure112is relatively small, a full width at half-maximum of a reflectance peak may be small, and thus a reflectance at a wavelength other than the specific wavelength may be relatively low, and when the thickness T of the nano-structure112increases, the full width at half-maximum of the reflectance peak increases. For example, the thickness T of the nano-structure112may range from about 20 nm to about 200 nm. Also, when the thickness T of the nano-structure112is fixed, a reflectance at the specific wavelength may be controlled by adjusting the diameter or width W of each nano-structure112or the pitch or period P of the plurality of nano-structures112. For example, when the light-emitting device100is used in a visible light region, the diameter or width W of each nano-structure112may range from about 100 nm to about 250 nm, and the pitch or period P of the plurality of nano-structures112may range from about 200 nm to about 500 nm. The phase retardation of reflected light by the reflective layer110may be determined by the diameter or width W of each nano-structure112, the pitch or period P of the plurality of nano-structures112, and the thickness T of each nano-structure112. Accordingly, the resonance wavelength of the micro-cavity may be determined by the diameter W of each nano-structure112, the thickness T of each nano-structure112, and the period P of the plurality of nano-structures112. For example, when the resonance wavelength of the micro-cavity is λ, the diameter W of each nano-structure112, the thickness T of each nano-structure112, and the period P of the plurality of nano-structures112may be selected so that the optical length L of the micro-cavity satisfies nλ/2, where n is a natural number. The diameter W of each nano-structure112, the thickness T of each nano-structure112, and the period P of the plurality of nano-structures112may be selected such that the reflective layer110has a highest reflectance for light having a wavelength corresponding to the resonance wavelength of the micro-cavity. Accordingly, the resonance wavelength of the micro-cavity may be more easily matched to an emission wavelength or an emission color of the light-emitting device100. For example, when the light-emitting device100is a red light-emitting device, the diameter W of each nano-structure112, the thickness T of each nano-structure112, and the period P of the plurality of nano-structures112may be selected such that the resonance wavelength of the micro-cavity corresponds to a red wavelength band and the reflective layer110has a highest reflectance for light of the red wavelength band. In this way, the emission wavelength of the light-emitting device100may be determined only by using a structure of the phase modulation surface of the reflective layer110. In order to prevent the micro-cavity from having polarization dependence, the plurality of nano-structures112may be regularly and periodically arranged to have 4-fold symmetry. When the micro-cavity has the polarization dependence, only light of a specific polarization component may resonate, thereby reducing the luminous efficiency of the light-emitting device100. For example,FIG.4is a perspective view illustrating a structure of the reflective layer110ofFIG.1. Referring toFIG.4, the plurality of nano-structures112each having a cylindrical shape may be two-dimensionally arranged in a regular square array. Although the nano-structure112has a cylindrical shape inFIG.4, a shape of the nano-structure112is not limited thereto. For example, the nano-structure112may have an elliptical column shape, a polygonal column shape such as a rectangular column shape, a pentagonal column shape, or the like, or a cross-like column shape. FIGS.5and6are plan views illustrating an arrangement of the plurality of nano-structures112of the reflective layer110ofFIG.1according to example embodiments. The plurality of nano-structures112may have any arrangement other than a square array arrangement as long as the plurality of nano-structures have 4-fold symmetry. For example, as shown inFIG.5, the plurality of nano-structures112may be two-dimensionally arranged in a hexagonal array or, as shown inFIG.6, the plurality of nano-structures112may be two-dimensionally arranged in a body-centered square array. Referring toFIGS.4and5, the plurality of nano-structures112are arranged in a regular two-dimensional array pattern. However, embodiments are not limited thereto, and when the plurality of nano-structures112has 4-fold symmetry, the plurality of nano-structures112may be arranged in any other array. For example, the plurality of nano-structures112may be irregularly arranged. In another example embodiment, the arrangement of the plurality of nano-structures112may be designed to be different from 4-fold symmetry such that the light-emitting device100emits only light of a specific polarization component. For example, the plurality of nano-structures112may be arranged in a one-dimensional array pattern. A reflection characteristics of the reflective layer110including the plurality of nano-structures112formed of a non-metallic material will now be described. FIGS.7A through7Dare graphs illustrating a change in a reflectance of the reflective layer110according to a thickness and a period of each nano-structure112according to example embodiments. Each nano-structure112has a cylindrical shape and is formed of Si, and the low-refractive-index layer111is formed of SiO2.FIGS.7A through7Dare graphs when a thickness T of each nano-structure112is 30 nm, 40 nm, 50 nm, and 120 nm. A hatched area in the graphs ofFIGS.7A through7Dindicates a case where a reflectance of the reflective layer110is equal to or greater than 80%. As illustrated in the graphs ofFIGS.7A through7D, when a thickness of each nano-structure112is fixed, a wavelength band in which a reflectance of the reflective layer110is equal to or greater than 80% may increase as a period of the plurality of nano-structures112increases. The period of the plurality of nano-structures112is smaller than a wavelength in which a reflectance of the reflective layer110is equal to or greater than 80%. Accordingly, the period of the plurality of nano-structures112may be selected to be smaller than a resonance wavelength of a micro-cavity. As a thickness of each nano-structure112increases, a width of a wavelength band in which a reflectance of the reflective layer110is equal to or greater than 80% for the same period increases which indicates that a full width at half-maximum of a reflectance peak increases. For example, a width of a wavelength band in which a reflectance is equal to or greater than 80% when a thickness of each nano-structure112is 120 nm is greater than a width of a wavelength band in which a reflectance is equal to or greater than 80% when a thickness of each nano-structure112is 30 nm. When the full width at half-maximum of the reflectance peak increases, the color purity of light emitted by the light emitting device100may decrease. Accordingly, reflectance characteristics of the reflective layer110may vary according to a material of the nano-structure112and a material of the low-refractive-index layer111, but a thickness of each nano-structure112may be selected to be equal to or less than 200 nm. FIGS.8A through8Care cross-sectional views illustrating the reflective layer110having a selectively high reflectance respectively for blue light, green light, and red light according to an example embodiment. The nano-structure112has a cylindrical shape and is formed of Si, and the low-refractive-index layer111is formed for SiO2. InFIGS.8A through8C, a thickness of the nano-structure112is fixed to 60 nm. A period of the plurality of nano-structures112of the reflective layer110ofFIG.8Awhich reflects blue light may be 236 nm, a period of the plurality of nano-structures112of the reflective layer110ofFIG.8Bwhich reflects green light may be 337 nm, and a period of the plurality of nano-structures112of the reflective layer110ofFIG.8Cwhich reflects red light may be 412 nm. InFIGS.8A through8C, a diameter of each nano-structure112is selected to be ½ of the period. FIG.9is a graph illustrating a relationship between a reflectance of the reflective layer110and a wavelength for a period of the plurality of nano-structures112. Referring to the graph ofFIG.9, the reflective layer110ofFIG.8Ahas a highest reflectance of 61.5% for blue light having a wavelength of about 450 nm, the reflective layer110ofFIG.8Bhas a highest reflectance of 92.6% for green light having a wavelength of about 550 nm, and the reflective layer110ofFIG.8Chas a highest reflectance of 91.9% for red light having a wavelength of about 650 nm. Accordingly, when the reflective layer110including the plurality of nano-structures112formed of a non-metallic material is used, an emission wavelength of the light-emitting device100may be selected by increasing a reflectance only for a specific wavelength in a visible light region. A top-emission type micro-cavity having high efficiency may be formed by filling the organic emission layer130between the reflective layer110including the plurality of nano-structures112formed of the non-metallic material and the second electrode122that is thin and flat.FIG.10is a cross-sectional view illustrating a structure for simulating characteristics of the light-emitting device100according to an optical length of a micro-cavity. In the structure ofFIG.10, SiO2that is the same as a material of the low-refractive-index layer111, instead of an organic emission layer, is filled between the reflective layer110and the second electrode122. The reflective layers ofFIGS.8A through8Care each used as the reflective layer110. Silver (Ag) having a thickness of 30 nm was used for the second electrode122. By emitting white light to the second electrode122from the outside a spectrum of reflected light is measured, and the optical length L of the micro-cavity is changed. In this case, because light having a wavelength corresponding to the resonance wavelength of the micro-cavity is absorbed by SiO2while resonating between the reflective layer110and the second electrode122, a reflectance with respect to the light having the wavelength corresponding to the resonance wavelength of the micro-cavity is reduced. FIG.11is a graph illustrating reflectances of blue light, green light, and red light according to the optical length L of the micro-cavity ofFIG.10. As the optical length L of the micro-cavity changes, a wavelength of light absorbed by the structure ofFIG.10changes. As marked by a dashed circle, there exists the optical length L of the micro-cavity for absorbing all of blue light, green light, and red light. For example, all of blue light, green light, and red light may be absorbed at an optical length corresponding to a common multiple of an optical length for absorbing the blue light, an optical length for absorbing the green light, and an optical length for absorbing the red light. Considering this point, when the optical length L of the micro-cavity of the light-emitting device100is appropriately selected, an emission color of the light-emitting device100may be determined only with dimensions of the nano-structure112of the reflective layer110. Accordingly, physical thicknesses of a light-emitting device for emitting blue light, a light-emitting device for emitting green light, and a light-emitting device for emitting red light may be set to be the same. For example, the light-emitting device for emitting the blue light, the light-emitting device for emitting the green light, and the light-emitting device for emitting the red light may be manufactured by fixing the optical length L of the micro-cavity and changing dimensions of the nano-structure112. Physical thicknesses of the manufactured light-emitting devices for respectively emitting the blue light, the green light, and the red light may be set to be the same. FIGS.12and13are graphs illustrating emission spectra of green light and red light according to the optical length L of the micro-cavity ofFIG.10. InFIGS.12and13, a white light source is disposed in SiO2between the reflective layer110and the second electrode122, and an intensity of light emitted by the second electrode122was calculated. FIG.12illustrates a result when the reflective layer ofFIG.8Bis used as the reflective layer110. Referring to the graph ofFIG.12, when the optical length L of the micro-cavity is 320 nm, a resonance peak that is amplified by about 2.5 times an intensity of light generated by a light source inside the micro-cavity may be obtained. Also, a full width at half-maximum of the resonance peak is about 10 nm which is very narrow.FIG.13illustrates a result when the reflective layer ofFIG.8Cis used as the reflective layer110. Referring to the graph ofFIG.13, when the optical length L of the micro-cavity is 380 nm, a resonance peak that is amplified by about 4.5 times an intensity of light generated by a light source inside the micro-cavity may be obtained, and a full width at half-maximum of the resonance peak is about 7 nm which is very narrow. Accordingly, because light having a wavelength other than a target wavelength is hardly emitted, very high color purity may be obtained. Although the nano-structure112is formed of Si inFIGS.8A through13, the nano-structure112may be formed of a material other than Si, and characteristics of the reflective layer110may be accordingly changed.FIGS.14A through14Care cross-sectional views illustrating the reflective layer110having a selectively high reflectance respectively for blue light, green light, and red light according to another example embodiment. Each nano-structure112has a cylindrical shape and is formed of TiO2, and the low-refractive-index layer111is formed of SiO2. InFIGS.14A through14C, a thickness of the nano-structure112is fixed to 60 nm. A period of the plurality of nano-structures112is selected to be smaller than an emission wavelength. For example, a period of the plurality of nano-structures112of the reflective layer110ofFIG.14Awhich reflects blue light may be 291 nm, a period of the plurality of nano-structures112of the reflective layer110ofFIG.14Bwhich reflects green light may be 364 nm, and a period of the plurality of nano-structures112of the reflective layer110ofFIG.14Cwhich reflects red light may be 435 nm. InFIGS.14A through14C, a diameter of each nano-structure112is selected to be ½ of the period. FIG.15is a graph illustrating a relationship between a period of the plurality of nano-structures112and a reflectance of the reflective layer110for blue light, green light, and red light. For blue light, a reflectance of about 99% may be obtained when a period of the plurality of nano-structures112is 291 nm, and a reflectance is rapidly reduced when the period of the plurality of nano-structures112is changed. For green light, a reflectance of about 99% may be obtained when a period of the plurality of nano-structures112is 364 nm, and a reflectance is rapidly reduced when the period of the plurality of nano-structures112is changed. For red light, a reflectance of about 99% may be obtained when a period of the plurality of nano-structures112is 435 nm, and a reflectance is rapidly reduced as the period of the plurality of nano-structures112is changed. FIG.16is a graph illustrating a relationship between a reflectance of the reflective layer110and a wavelength for a period of the plurality of nano-structures112. Referring to the graph ofFIG.16, the reflective layer110ofFIG.14Ahas a highest reflectance of 99% for blue light having a wavelength of about 450 nm, the reflective layer110ofFIG.14Bhas a highest reflectance of 99% for green light having a wavelength of about 550 nm, and the reflective layer110ofFIG.14Chas a highest reflectance of 99% for red light having a wavelength of about 650 nm.FIG.16also illustrates that crosstalk noise of a wavelength other than a target wavelength is less than about 20%, and thus a wavelength selectivity of the reflective layer110is relatively good. Also,FIGS.17through19are graphs illustrating emission spectra of blue light, green light, and red light according to an optical length of a micro-cavity.FIGS.17through19are obtained by applying the reflective layers110ofFIGS.14A through14Cto the structure ofFIG.10. InFIGS.17through19, a white light source is disposed in SiO2between the reflective layer110and the second electrode122, and an intensity of light emitted by the second electrode122is calculated. FIG.17illustrates a result when the reflective layer ofFIG.14Ais used as the reflective layer110. Referring to the graph ofFIG.17, when the optical length L of the micro-cavity is 240 nm, a resonance peak that is amplified by about 3.5 times an intensity of light generated by a light source inside the micro-cavity may be obtained.FIG.18illustrates a result when the reflective layer ofFIG.14Bis used as the reflective layer110. Referring to the graph ofFIG.18, when the optical length L of the micro-cavity ranges from about 300 nm to about 320 nm, a resonance peak that is amplified by about 4.2 times an intensity of light generated by a light source inside the micro-cavity may be obtained.FIG.19illustrates a result when the reflective layer ofFIG.14Cis used as the reflective layer110. Referring to the graph ofFIG.19, when the optical length L of the micro-cavity is 380 nm, a resonance peak that is amplified by about 4.5 times an intensity of light generated by a light source inside the micro-cavity may be obtained. Also, a full width at half-maximum of each of the resonance peaks in the graphs ofFIGS.17through19is about 3 nm which is very narrow, thereby significantly reducing crosstalk noise. Accordingly, because light having a wavelength other than a target wavelength is hardly emitted, very high color purity may be obtained. Although each nano-structure112has a cylindrical shape inFIGS.8A through19, the nano-structure112may have any of various other shapes. For example,FIGS.20and21are plan views illustrating shapes of a plurality of nano-structures of a reflective layer according to other example embodiments. As shown inFIG.20, each nano-structure112may have a rectangular column shape, or as shown inFIG.21, each nano-structure112may have a cross-like column shape. However embodiments are not limited thereto. For example, each nano-structure112may have an elliptical column shape, or a polygonal column shape such as a pentagonal column shape or the like. Reflection characteristics of the reflective layer110may vary according to a shape of the nano-structure112. For example,FIG.22is a graph illustrating reflection characteristics of the reflective layer110, which is configured to reflect blue light, according to a shape of the nano-structure112.FIG.23is a graph illustrating reflection characteristics of the reflective layer110, which is configured to reflect green light, according to a shape of the nano-structure112.FIG.24is a graph illustrating reflection characteristics of the reflective layer110, which is configured to reflect red light, according to a shape of the nano-structure112. Each nano-structure112is formed of Si, and the low-refractive-index layer111is formed of SiO2. A solid line in each ofFIGS.22through24indicates a case where the nano-structure112has a cylindrical shape, a dashed line indicates a case where the nano-structure112has a cross-like column shape, and a dash-dotted line indicates a case where the nano-structure112has a square column shape. In all of the examples, a thickness of the nano-structure112is fixed to 100 nm. In the reflective layer110for reflecting blue light, a width of the nano-structure112is 150 nm and a period of the plurality of nano-structures112is 290 nm. In the reflective layer110for reflecting green light, a width of the nano-structure112is 180 nm and a period of the plurality of nano-structures112is 330 nm. In the reflective layer110for reflecting red light, a width of the nano-structure112is 180 nm and a period of the plurality of nano-structures112is 410 nm. Referring toFIGS.22through24, when the nano-structure112has a cylindrical shape, a reflectance peak was formed at 450 nm, 550 nm, and 650 nm. When the nano-structure112has a cross-like column shape, a reflectance peak was formed at wavelengths slightly shorter than 450 nm, 550 nm, and 650 nm. When the nano-structure112has a square column shape, a reflectance peak was formed at wavelengths slightly longer than 450 nm, 550 nm, and 650 nm. In the reflective layers110for reflecting blue light and green light, a reflectance of each of the nano-structures112having a cross-like column shape and a square column shape was higher than a reflectance of the nano-structure112having a cylindrical shape. In the reflective layer110for reflecting red light, a reflectance of the nano-structure having a square column shape was similar to a reflectance of the nano-structure112having a cylindrical shape. Accordingly, even when the nano-structure112has a shape other than a cylindrical shape, the reflective layer110having a selectively high reflectance may be designed, and a desired wavelength of reflected light may be controlled by changing dimensions of the nano-structure112. FIG.25is a cross-sectional view illustrating a structure of a light-emitting device according to another example embodiment. In the light-emitting device100ofFIG.1, the low-refractive-index layer111completely covers a top surface of the nano-structure112. However, in a light-emitting device100aofFIG.25, the low-refractive-index layer111does not cover top surfaces of the nano-structures112, and the top surfaces of the plurality of nano-structures112and a top surface of the low-refractive-index layer111are disposed on the same plane. The top surfaces of the plurality of nano-structures112and the top surface of the low-refractive-index layer111may directly contact the first electrode121. Side surfaces and bottom surfaces of the plurality of nano-structures112may be completely surrounded and encapsulated by the low-refractive-index layer111. FIG.26is a cross-sectional view illustrating a structure of a light-emitting device according to another example embodiment. Referring toFIG.26, the reflective layer110of a light-emitting device100bmay further include a metal reflective film113that is flat and has a high reflectance. For example, the metal reflective film113may include silver (Ag), aluminum (Al), gold (Au), nickel (Ni), or a combination thereof. The metal reflective film113may directly contact a bottom surface of the nano-structure112. The low-refractive-index layer111may surround a bottom surface of the metal reflective film113and a top surface of the metal reflective film113which does not contact the nano-structure112. FIG.27is a cross-sectional view illustrating a structure of a light-emitting device according to another example embodiment. Although the metal reflective film113directly contacts the bottom surface of the nano-structure112inFIG.26, embodiments are not limited thereto. In a light-emitting device100cofFIG.27, the metal reflective film113may be disposed on a bottom surface of the low-refractive-index layer111. In this case, the metal reflective film113does not directly contact the nano-structure112. FIG.28is a cross-sectional view illustrating a structure of a light-emitting device according to another example embodiment. Referring toFIG.28, a light-emitting device100dmay further include a substrate101. Examples of the substrate101may include a semiconductor substrate such as a silicon (Si) substrate, a transparent glass substrate, and a transparent polymer substrate. The reflective layer110, the first electrode121, the organic emission layer130, the second electrode122, and the passivation layer140may be sequentially stacked on the substrate101. Also, the low-refractive-index layer111may be formed of two different dielectric materials. For example, the low-refractive-index layer111may include a first low-refractive-index layer111adisposed under the nano-structure112and a second low-refractive-index layer111bdisposed to cover side surfaces and a top surface of the nano-structure112. The first low-refractive-index layer111aand the second low-refractive-index layer111bmay have different refractive indexes, and may each be formed of a transparent dielectric material having a refractive index lower than a refractive index of the nano-structure112. A wavelength of reflected light reflected by the reflective layer110may be controlled by the first low-refractive-index layer111aand the second low-refractive-index layer111b. As described above, blue light, green light, and red light may be emitted with high efficiency and a narrow full width at half-maximum according to the optical length L of the micro-cavity, by using the reflective layer110including the plurality of nano-structures112formed of a non-metallic material. An emission wavelength of the light-emitting device100may be more easily determined only by changing widths and/or periods of the nano-structures112while fixing heights of the nano-structures112of the reflective layer110and the optical length L of the micro-cavity. Accordingly, when the light-emitting device100according to an example embodiment is applied to red, green, blue (RGB) sub-pixels of a display apparatus, a process of manufacturing the display apparatus may be facilitated. For example,FIG.29is a cross-sectional view illustrating a structure of a display apparatus according to an example embodiment. Referring toFIG.29, a display apparatus200according to an example embodiment may include a display substrate201and a first pixel100B, a second pixel100G, and a third pixel100R aligned on the display substrate201. InFIG.29, although each of the first through third pixels100B,100G, and100R has the same structure as that of the light-emitting device100ofFIG.1, each of the first through third pixels100B,100G, and100R may have a structure of any of the light-emitting devices100a,100b,100c, and100dofFIGS.25through28. Also, although only one first pixel100B, one second pixel100G, and one third pixel100R are illustrated for convenience of explanation inFIG.29, a large number of first through third pixels100B,100G, and100R may be repeatedly arranged. The first through third pixels100B,100G, and100R may include reflective layers110B,110G, and110R respectively including a plurality of nano-structures112B,112G, and112R that are two-dimensionally arranged, the first electrode121disposed on the reflective layers110B,110G, and110R, the organic emission layer130disposed on the first electrode121, and the second electrode122disposed on the organic emission layer130. Also, the first through third pixels100B,100G, and100R may each further include the passivation layer140that is transparent and is disposed on the second electrode122to protect the second electrode122. The first through third pixels100B,100G, and100R may be configured to emit light having different wavelengths. For example, the first pixel100B may be configured to emit light B of a blue wavelength band, the second pixel100G may be configured to emit light G of a green wavelength band, and the third pixel100R may be configured to emit light R of a red wavelength band. To this end, the reflective layers110B,110G, and110R of the first through third pixels100B,100G, and100R may respectively include the nano-structures112B,112G, and112R having different dimensions. For example, a diameter of each nano-structure112B, a height of each nano-structure112B, and a period of the plurality of nano-structures112B may be determined such that the reflective layer110B of the first pixel100B has a highest reflectance for the light B of the blue wavelength band and transmits or absorbs the light R and G of the remaining wavelength bands. Also, a diameter of each nano-structure112G, a height of each nano-structure112G, and a period of the plurality of nano-structures112G may be determined so that the reflective layer110G of the second pixel100G has a highest reflectance for the light G of the green wavelength band and transmits or absorbs the light B and R of the remaining wavelength bands. Likewise, a diameter of each nano-structure112R, a height of each nano-structure112R, and a period of the plurality of nano-structures112R may be determined so that the reflective layer110R of the third pixel100R has a highest reflectance for the light R of the red wavelength band and transmits or absorbs the light B and G of the remaining wavelength bands. In particular, the first through third pixels100B,100G, and100R may be configured such that heights of the plurality of nano-structures112B,112G, and112R are fixed to be the same and diameters and periods of the plurality of nano-structures112B,112G, and112R are different from one another. For example, a period of the nano-structure112B of the first pixel100B may be smaller than a blue wavelength, and may be smaller than a period of the nano-structure112G of the second pixel100G. A period of the nano-structure112G of the second pixel100G may be smaller than a green wavelength, and may be smaller than a period of the nano-structure112R of the third pixel100R. Also, a period of the nano-structure112R of the third pixel100R may be smaller than a red wavelength. Optical lengths of micro-cavities in the first through third pixels100B,110G, and100R may be the same. As described with reference toFIGS.10and11, the optical lengths of the micro-cavities of the first through third pixels100B,100G, and100R may correspond to a common multiple of an optical length for resonating blue light, an optical length for resonating green light, and an optical for resonating red light. Accordingly, emission wavelengths of the first through third pixels100B,100G, and100R may be determined only with dimensions of the nano-structures112B,112G, and112R of the reflective layers110B,110G, and110R. In the first through third pixels100B,100G, and100R, elements other than the reflective layers110B,110G, and110R, for example, the first electrodes121, the organic emission layers130, and the second electrodes122may have the same composition and the same thickness. As a result, physical thicknesses of the first through third pixels100B,100G, and100R may be the same. Accordingly, a process of manufacturing the display apparatus200may be more simplified and manufacturing costs may be reduced. FIG.30is a cross-sectional view illustrating a structure of a display apparatus according to another example embodiment. In a display apparatus300ofFIG.30, the reflective layers110G and110R of the second pixel100G and the third pixel100R may respectively include the nano-structures112G and112R, but the reflective layer110B of the first pixel100B may not include nano-structures. Each of the reflective layers110B,110G, and110R of the display apparatus300ofFIG.30may further include the metal reflective film113. The metal reflective film113may directly contact a bottom surface of each of the nano-structures112G and112R. However, as shown inFIG.27, the metal reflective film113may contact a bottom surface of the low-refractive-index layer111. The metal reflective films113of the reflective layers110B,110G, and110R may be disposed on the same plane. An optical length of a micro-cavity of the first pixel100B may be determined such that a resonance wavelength matches a blue wavelength. For example, the optical length of the micro-cavity of the first pixel100B may be determined by a sum of optical lengths of materials disposed between the metal reflective film113and the second electrode122. Accordingly, the first pixel100B may emit light B of blue wavelength band. In the second pixel100G and the third pixel100R, resonance wavelengths of micro-cavities may be adjusted through a phase retardation of reflected light by using the nano-structures112G and112R. For example, the nano-structure112G of the second pixel100G may be configured such that the resonance wavelength of the micro-cavity of the second pixel100G matches a green wavelength to delay a phase of reflected light and has a highest reflectance for light G of a green wavelength band. The nano-structure112R of the third pixel100R may be configured such that the resonance wavelength of the micro-cavity of the third pixel100R matches a red wavelength to delay a phase of reflected light and has a highest reflectance for light R of a red wavelength band. It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other embodiments. While example embodiments have been described with reference to the figures, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 47,371 |
11943953 | Components in figures are represented as follows:organic light emitting diode100;substrate layer1; first electrode layer2;hole injection layer3; hole transport layer4;electron blocking layer5; blended active layer6;light emitting layer6A; first packaging layer6B;hole blocking layer7; electron transport layer8;electron injection layer9; second electrode layer10;second packaging layer11. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Preferred embodiments of the present disclosure are described in the following with reference to accompanying drawings, which demonstrate that the present disclosure can be implemented, and the embodiments of the present disclosure can be fully described for those skilled in the art to make the technical content clearer and easier to understand. The present disclosure may be embodied in many different forms of embodiments, and scope of the present disclosure is not limited to the embodiments disclosed herein. In the drawings, structurally identical components are denoted by same reference numerals, and structural or functionally similar components are denoted by like reference numerals. Dimensions and thickness of each component shown in the drawings are arbitrarily shown, and the disclosure does not limit the size and thickness of each component. In order to make the illustration clearer, some parts of the drawing appropriately exaggerate the thickness of the parts. In addition, the description of each of the following embodiments of the disclosure is provided to illustrate specific embodiments of the disclosure in which the disclosure may be practiced. The directional terms mentioned in the present disclosure, for example, “upper”, “lower”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are merely directions referring to the adding drawings. Therefore, the directional terminology used is for the purpose of illustration and understanding of the disclosure, rather than indicating or implying that the device or component referred to has a particular orientation, construction, and operation in a particular orientation. Therefore, it is not to be construed as limiting the disclosure. Moreover, the terms “first”, “second”, “third”, and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. When some components are described as “on” another component, the components may be placed directly on the another component; or may also be an intermediate component in which the component is placed on the intermediate component, and the intermediate component is placed on the another component. When a component is described as “mounted to” or “connected to” another component, both of them may be understood to be “mounted” or “connected” directly, or a component is “mounted to” or “connected” to another component through an intermediate component. Embodiment 1 An embodiment of the present disclosure discloses an organic light emitting diode100. As shown inFIG.1, the organic light emitting diode100includes a substrate layer1, a first electrode layer2, a hole injection layer3, a hole transport layer4, an electron blocking layer5, a blended active layer6, a hole blocking layer7, an electron transport layer8, an electron injection layer9, and a second electrode layer10. Material of the substrate layer1is polyimide (PI), which is a flexible substrate layer1and which protects a structure of the organic light emitting diode100while promoting the organic light emitting diode100to achieve flexible display. The first electrode layer2is disposed on the substrate layer1. Material of the first electrode layer2is indium tin oxide (ITO), which is used to provide a current and voltage for the organic light emitting diode100to promote holes to migrate to the light emitting layer6A. The first electrode layer2is an anode layer. The hole injection layer3is disposed on a surface of the first electrode layer2facing away from the substrate layer1, which is used to reduce a potential barrier for injecting holes from the first electrode layer2, so that the holes can be efficiently injected into the light emitting layer6A. The hole transport layer4is disposed on a surface of the hole injection layer3facing away from the first electrode layer2and is used to transport holes in the hole-injection layer3into the light emitting layer6A. The electron blocking layer5is disposed on a surface of the hole transport layer4facing away from the hole injection layer3and is used to prevent electrons in the light emitting layer6A from entering the hole injection layer3. The blended active layer6includes a light emitting layer6A and a first packaging layer6B. The light emitting layer6A is disposed on a surface of the electron blocking layer5facing away from the hole transport layer4, and material of the light blocking layer6A includes a light emitting material. The holes and the electrons are condensed and combined in the light emitting layer6A under a driving of the electric field and voltage of the first electrode layer2and the second electrode layer10, thereby converting electric energy into light energy, and realizing electroluminescence. The first packaging layer6B covers a surface of the light emitting layer6A. A light transmittance of the first packaging layer6B is greater than or equal to 50%. Material used for fabricating the first packaging layer6B is a polymer material with high light transmittance, such as polyacrylonitrile, for protecting the light emitting layer6A, blocking water and oxygen, and avoiding inactivation of carriers by traps during exciton formation. The hole blocking layer7is disposed on a surface of the blended active layer6facing away from the electron blocking layer5and is used to prevent holes in the light emitting layer6A from entering the electron injection layer9. The electron transporting layer8is disposed on a surface of the hole blocking layer7facing away from the blended active layer6and is used to transport electrons in the electron injection layer9into the light emitting layer6A. The electron injection layer9is disposed on a surface of the electron transport layer8facing away from the hole blocking layer7and is used to reduce barrier of electron injection from the second electrode layer10, so that the electrons can be efficiently injected into the light emitting layer6A. The second electrode layer10is disposed on a surface of the electron injection layer9facing away from the electron transport layer8. The second electrode layer10is used to provide a current and voltage to the electron injection layer9to promote electron movement toward the light emitting layer6A. The second electrode layer10is a cathode layer. Driven by the voltage of the first electron layer2and the second electrode layer10, the injected holes and electrons migrate from the hole transport layer4and the electron transport layer8to the light emitting layer6A, respectively. And in the light emitting layer6A, they are bound together by the Coulomb force to form an electron-hole pair, that is, an exciton, thereby exciting chemical molecules in the light-emitting layer6A to produce light and realize self-luminescence. An embodiment of the present disclosure further discloses a fabricating method of an organic light emitting diode100. The fabricating process is shown inFIG.2. The specific fabricating steps include: In step S10, a substrate layer1is provided. A substrate layer1is provided. The substrate layer1is a flexible substrate layer1and material thereof is polyimide. In step S20, a first electrode layer2, a hole injection layer3, and a hole transport layer4are sequentially formed on the substrate layer1. A layer of indium tin oxide material is formed on the substrate layer1by plating processes such as sputtering and evaporation to form the first electrode layer2. A hole injection material and a hole transport material are sequentially plated on a surface of the first electrode layer2facing away from the substrate layer1by a process such as evaporation to form the hole injection layer3and the hole transport layer4. In step S30, a blended active layer6is formed on the hole transport layer4. Polymer material polyacrylonitrile is incorporated into the light emitting material to form a blended active solution, and the blended active solution is coated on the hole transport layer4in a roll-to-roll manner, and the blended active layer6is formed after drying. The blended active layer6includes a light emitting layer6A and a first packaging layer6B covering the surface of the light emitting layer6A. The polymer materials in the blended active solution are uniformly dispersed in the surface of the light emitting layer6A to form the first packaging layer6B. In step S40, An electron transport layer8, an electron injection layer9, and a second electrode layer10are sequentially formed on the blended active layer6. Through processes such as evaporation, an electron transport material, an electron injection material, and a second electrode layer material are sequentially plated on the surface of the blended active layer6facing away from the first electrode layer2, so as to form the electron transport layer8, the electron injection layer9, and the second electrode layer10. Material of the second electrode layer10is a conductive metal. An embodiment of the present disclosure further provides a display device, which includes the organic light emitting diode100fabricated by the fabricating method described above. The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, and a notebook computer. An organic light emitting diode100is provided in this embodiment, and a surface of the light emitting layer6A is covered with a first packaging layer6B for protecting the light emitting layer6A and preventing the light emitting layer6A from being corroded by water and oxygen to affect an activity of the material of the light emitting layer6A, thereby improving a service life of the organic light emitting diode100. In addition, the first packaging layer6B has high light transmittance, and its light transmittance is identical to or greater than 50%, and does not block light emitted from the light emitting layer6A. Simultaneously, material of the first packaging layer6B has a certain carrier transmission capability, and does not affect the carrier transmission. The fabricating method of an organic light emitting diode100provided in the present embodiment has a simple manufacturing process and can achieve packaging effects without adding a packaging process or a packaging device, thereby saving resources and costs. Embodiment 2 An embodiment of the present disclosure discloses an organic light emitting diode100. As shown inFIG.3, the organic light emitting diode100includes a substrate layer1, a first electrode layer2, a hole injection layer3, a hole transport layer4, an electron blocking layer5, a blended active layer6, a hole blocking layer7, an electron transport layer8, an electron injection layer9, a second electrode layer10, and a second packaging layer. Material of the substrate layer1is polyimide (PI), which is a flexible substrate layer1and which protects a structure of the organic light emitting diode100while promoting the organic light emitting diode100to achieve flexible display. The first electrode layer2is disposed on the substrate layer1. Material of the first electrode layer2is indium tin oxide (ITO), which is used to provide a current and voltage for the organic light emitting diode100to promote holes to migrate to the light emitting layer6A. The first electrode layer2is an anode layer. The hole injection layer3is disposed on a surface of the first electrode layer2facing away from the substrate layer1, which is used to reduce a potential barrier for injecting holes from the first electrode layer2, so that the holes can be efficiently injected into the light emitting layer6A. The hole transport layer4is disposed on a surface of the hole injection layer3facing away from the first electrode layer2and is used to transport holes in the hole-injection layer3into the light emitting layer6A. The electron blocking layer5is disposed on a surface of the hole transport layer4facing away from the hole injection layer3and is used to prevent electrons in the light emitting layer6A from entering the hole injection layer3. The blended active layer6includes a light emitting layer6A and a first packaging layer6B. The light emitting layer6A is disposed on a surface of the electron blocking layer5facing away from the hole transport layer4, and material of the light blocking layer6A includes a light emitting material. The holes and the electrons are condensed and combined in the light emitting layer6A under a driving of the electric field and voltage of the first electrode layer2and the second electrode layer10, thereby converting electric energy into light energy, and realizing electroluminescence. The first packaging layer6B covers a surface of the light emitting layer6A. A light transmittance of the first packaging layer6B is greater than or equal to 50%. Material used for fabricating the first packaging layer6B is a polymer material with high light transmittance, such as polyacrylonitrile, for protecting the light emitting layer6A, blocking water and oxygen, and avoiding inactivation of carriers by traps during exciton formation. The hole blocking layer7is disposed on a surface of the blended active layer6facing away from the electron blocking layer5and is used to prevent holes in the light emitting layer6A from entering the electron injection layer9. The electron transporting layer8is disposed on a surface of the hole blocking layer7facing away from the blended active layer6and is used to transport electrons in the electron injection layer9into the light emitting layer6A. The electron injection layer9is disposed on a surface of the electron transport layer8facing away from the hole blocking layer7and is used to reduce barrier of electron injection from the second electrode layer10, so that the electrons can be efficiently injected into the light emitting layer6A. The second electrode layer10is disposed on a surface of the electron injection layer9facing away from the electron transport layer8. The second electrode layer10is used to provide a current and voltage to the electron injection layer9to promote electron movement toward the light emitting layer6A. Driven by the voltage of the first electron layer2and the second electrode layer10, the injected holes and electrons migrate from the hole transport layer4and the electron transport layer8to the light emitting layer6A, respectively. And in the light emitting layer6A, they are bound together by the Coulomb force to form an electron-hole pair, that is, an exciton, thereby exciting chemical molecules in the light-emitting layer6A to produce light and realize self-luminescence. The second packaging layer11is disposed on a surface of the second electrode layer10facing away from the electron injection layer9. Material of the second packaging layer11is an organic adhesive, which is used to isolate water and oxygen, protect the organic light emitting diode100from corrosion, and improve a service life of the organic light emitting diode100. An embodiment of the present disclosure further discloses a fabricating method of an organic light emitting diode100. The fabricating process is shown inFIG.4. The specific fabricating steps include: In step S10, a substrate layer1is provided. A substrate layer1is provided. The substrate layer1is a flexible substrate layer1and material thereof is polyimide. In step S20, a first electrode layer2, a hole injection layer3, and a hole transport layer4are sequentially formed on the substrate layer1. A layer of indium tin oxide material is formed on the substrate layer1by plating processes such as sputtering and evaporation to form the first electrode layer2. A hole injection material and a hole transport material are sequentially plated on a surface of the first electrode layer2facing away from the substrate layer1by a process such as evaporation to form the hole injection layer3and the hole transport layer4. In step S30, a blended active layer6is formed on the hole transport layer4. Polymer material polyacrylonitrile is incorporated into the light emitting material to form a blended active solution, and the blended active solution is coated on the hole transport layer4in a roll-to-roll manner, and the blended active layer6is formed after drying. The blended active layer6includes a light emitting layer6A and a first packaging layer6B covering the surface of the light emitting layer6A. The polymer materials in the blended active solution are uniformly dispersed in the surface of the light emitting layer6A to form the first packaging layer6B. In step S40, An electron transport layer8, an electron injection layer9, and a second electrode layer10are sequentially formed on the blended active layer6. Through processes such as evaporation, an electron transport material, an electron injection material, and a second electrode layer material are sequentially plated on the surface of the blended active layer6facing away from the first electrode layer2, so as to form the electron transport layer8, the electron injection layer9, and the second electrode layer10. Material of the second electrode layer10is a conductive metal. In step S50, a second packaging layer11is formed on the second electrode layer10. An organic adhesive is coated on a surface of the second electrode layer10facing away from the blended active layer6, and the organic adhesive is cured to form the second packaging layer11. An embodiment of the present disclosure further provides a display device, which includes the organic light emitting diode100fabricated by the fabricating method described above. The display device may be any product or component having a display function, such as a mobile phone, a tablet computer, and a notebook computer. An organic light emitting diode100provided in this embodiment adopts a double-layer package. A surface of the light-emitting layer6A is covered with a first packaging layer6B. Simultaneously, a second packaging layer11is disposed on the second electrode layer10. The double-layer package can further prevent the light emitting layer6A from being corroded by water and oxygen to affect an activity of the material of the light emitting layer6A, and further prevent other devices in the organic light emitting diode100from being corroded. The organic light emitting diode100is protected to the maximum extent, and a service life of the organic light emitting diode100is improved. The first packaging layer6B has high light transmittance, and its light transmittance is identical to or greater than 50%, and it will not block light emitted from the light emitting layer6A. Simultaneously, material of the first packaging layer6B has a certain carrier transmission capability, and does not affect the carrier transmission. The fabricating method of the organic light emitting diode100provided in this embodiment has a simple manufacturing process, and can achieve better packaging effects without adding new processes, saving resources and costs. Although the disclosure is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the disclosure. It should therefore be understood that many modifications can be made to the exemplary embodiments and that other arrangements can be devised without departing from the spirit and scope of the disclosure as defined by the appended claims. It should be understood that different dependent claims and features described herein may be combined in a manner different from that described in the original claims. It can also be understood that features described in connection with separate embodiments may be used in other described embodiments. | 20,160 |
11943954 | DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION Specific embodiments of the present invention will be further described in detail below with reference to accompanying drawings and examples. The following examples are used to illustrate the present invention, but not to limit scope of the present invention. In a field of organic light-emitting diode (OLED) flexible displays, organic materials of OLED devices are easily eroded by moisture and oxygen, which will affect service lives of the OLED devices. Preventing the OLED devices from contacting with moisture and oxygen by an encapsulation process can extend the service lives of the OLED devices. In current mainstream thin-film encapsulation structures, an organic/inorganic thin-film stack structure is commonly used to simultaneously block moisture and oxygen and achieve flexible bending. As shown inFIG.1, an outermost layer of a thin-film encapsulation (TFE) structure is a dense inorganic layer152, which can block moisture and oxygen. An inner layer of the TFE structure is an organic polymer layer151, which can planarize and encapsulate impurity particles, and also help to release stress between layers. However, it should be noted that, in such encapsulation structure ofFIG.1, when an OLED display screen is bent outward, tensile stress of the outermost inorganic layer cannot be completely released, and thus the outermost inorganic layer is easily peeled, separated or even broken. From a mechanical point of view, disposing an additional organic layer on an outside of the inorganic layer can solve the problem. However, most organic polymers easily absorb and hold moisture. If the outermost layer of the TFE structure is an organic layer, it is easy to cause erosion of the TFE structure. Furthermore, a surface of an organic matter has a small hardness, and thus is prone to damage such as scratches in subsequent module manufacturing processes. Therefore, in general, an organic layer is not suitable to be disposed on an outermost side of a TFE structure. Plasma process is a common surface treatment process. Studies have shown that O2, CO2, and air plasma can oxidize organic polymers, thereby modifying surfaces of the organic polymers. O2plasma can effectively increase a Si-to-O ratio of a surface of a polydimethylsiloxane (PDMS) thin-film and reduce a corresponding Si-to-C ratio, thereby increasing a hardness of the surface of the PDMS thin-film. Similar related studies have shown that a surface of a PDMS thin-film will become a thin SiOX-rich modified layer after O2plasma treatment. The modified layer is confirmed to reduce gas permeability of the surface of the PDMS thin-film and block moisture and oxygen. Based on the above theoretical knowledge, in order to not only prevent an OLED device from being eroded by moisture and oxygen but also reduce a risk of degradation of a TFE structure during bending, an embodiment of the present invention provides an encapsulation structure for a flexible OLED device, which can enhance bending performance. Please refer toFIG.2toFIG.6, the encapsulation structure comprises an organic matter protective layer30, one or more continuous organic flat layers40, one or more inorganic barrier layers50, and one or more organic layers60sequentially disposed on the OLED device20. An outermost surface of each of the organic layers60is treated with plasma to become a surface hardened layer602, and the surface hardened layer602and an unhardened portion601of the organic layer60form an organic barrier layer. The one or more organic layers60are made of an organic silicone-based material. An outer surface of each of the organic layers60is treated with plasma to become a thin hardened layer on a surface of an organic silicone-based thin-film, which is hereinafter referred to as a surface hardened layer602for convenience of description. The plasma is O2plasma or CO2plasma. The component of the surface hardened layer602is between organic silicon and inorganic silicon. The surface hardened layer602and the remaining unhardened portion601form the organic barrier layer. The outermost organic barrier layer of the TFE structure can improve moisture and oxygen blocking performance and simultaneously reduce the risk of the degradation of the TFE structure during bending thereby extending a service life of the OLED device. In an embodiment of the present invention, each of the organic layers may be a continuous thin-film or a discontinuous thin-film. When each of the organic layers is a continuous thin-film, the thin-film has a thickness of 3 μm to 6 μm, and the surface hardened layer has a thickness of 100 nm to 200 nm. When each organic layer is a discontinuous thin-film, each organic layer may comprise a plurality of independent block unit thin-films, and each of the block unit thin-films covers a single pixel or a plurality of pixels adjacent to each other in the OLED device. Each organic layer may also comprise a plurality of independent strip unit thin-films, and each of the strip unit thin-films covers a single row of pixels or a plurality of rows of pixels adjacent to each other in the OLED device. An embodiment of the present disclosure further provides a method for encapsulating a flexible OLED device. The method mainly comprises: sequentially disposing an organic matter protective layer, one or more continuous organic flat layers, one or more inorganic barrier layers, and one or more organic layers on the OLED device; and treating an outermost surface of each of the organic layers with plasma to form a surface hardened layer, wherein the surface hardened layer and an unhardened portion of the organic layer form an organic barrier layer. In an embodiment of the present invention, a specific process of an encapsulation structure for a flexible OLED device comprises: (1) Depositing a layer of fluorine-containing organic matter as a protective layer on the OLED device by thermal evaporation, pulsed laser deposition (PLD), or the like, which covers an entire display area of the OLED device and has a thickness between 10 nm and 100 nm. The organic matter protective layer may be composed of, but is not limited to, polytetrafluoroethylene (PTFE), polyvinylidene fluoride (PVDF), or polyvinyl fluoride (PVF). (2) Forming one or more continuous organic flat layers on the organic matter protective layer by ink-jet printing (IJP), coating, or the like. An edge portion of each organic flat layer is located in a coverage area of the organic matter protective layer. Each organic flat layer has a thickness between 1 μm and 10 μm and is composed of, but is not limited to, acrylic resin, epoxy resin, silicone resin, polydimethylsiloxane (PDMS), or hexamethyldisiloxane (HMDSO). (3) Forming one or more inorganic barrier layers on the one or more organic flat layers by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), PLD, Sputter, or the like. Each inorganic barrier layer is a continuous thin-film covering the entire display area of the OLED device. An edge portion of each inorganic barrier layer extends to a non-display area of the OLED device. Each inorganic barrier layer has a thickness between 500 nm and 1.5 μm and is composed of, but is not limited to, Al2O3, TiO2, CrO2, SiNX, SiONX, or SiOX. (4) Forming one or more organic layers on the one or more inorganic barrier layers by IJP, coating, or the like. Each organic layer has a thickness between 1 μm and 10 μm and is composed of, but is not limited to, silicone resin, polydimethylsiloxane (PDMS), or hexamethyldisiloxane (HMDSO). (5) Treating an outer surface of each organic layer with plasma by a plasma treatment process, so that the outer surface of each organic layer becomes a surface hardened layer, that is, a surface hardened layer. The surface hardened layer has a thickness between 50 nm and 500 nm. The surface hardened layer and a remaining unhardened portion of the organic layer form an organic barrier layer. The plasma for the plasma treatment process comprises, but is not limited to, O2plasma and CO2plasma. A method for encapsulating an OLED device is described in detail below with a specific embodiment. First step: as shown inFIG.2, disposing an OLED device20on a back plate10, and disposing an organic matter protective layer30having a thickness between 10 nm and 100 nm on the OLED device20by thermal evaporation, PLD, or the like. The organic matter protective layer30may be composed of, but is not limited to, polytetrafluoroethylene (PTFE), polyvinylidene fluoride (PVDF), or polyvinyl fluoride (PVF). The organic matter protective layer30covers an entire display area of the OLED device20. Second step: as shown inFIG.3, forming a continuous organic flat layer40on the organic matter protective layer30by ink-jet printing (IJP), coating, or the like. An opening of the organic flat layer40is smaller than an opening of the organic matter protective layer30. The organic flat layer40preferably has a thickness between 3 μm and 6 μm and is composed of, but is not limited to, acrylic resin, epoxy resin, silicone resin, polydimethylsiloxane (PDMS), or hexamethyldisiloxane (HMDSO). Third step: as shown inFIG.4, forming an inorganic barrier layer50on the organic flat layer40by PECVD, ALD, PLD, Sputter, or the like. The inorganic barrier layer50is a continuous thin-film covering the entire display area of the OLED device20. An opening of the inorganic barrier layer50is larger than the opening of the organic flat layer40. The inorganic barrier layer50preferably has a thickness between 500 nm and 1 μm and is composed of, but is not limited to, Al2O3, TiO2, CrO2, SiNX, SiONX, or SiOX. Fourth step: as shown inFIG.5, forming one or more organic layers on the one or more inorganic barrier layers by IJP, coating, or the like. Each organic layer has a thickness between 1 μm and 10 μm and is composed of, but is not limited to, silicone resin, polydimethylsiloxane (PDMS), or hexamethyldisiloxane (HMDSO). Fifth step: as shown inFIG.6, treating a surface of the cured organic layer60by a plasma treatment process so that the surface of the organic layer60becomes a thin surface hardened layer602. The surface hardened layer602and an unhardened portion601of the organic layer60finally form an organic barrier layer. Preferably, the plasma treatment process is performed on the surface of the organic layer60with O2plasma. During the plasma treatment process, adjusting a ratio of O2plasma and time of treating the surface of the organic layer60by the plasma treatment process so that the generated surface hardened layer602preferably has a thickness between 100 nm and 200 nm. A method for encapsulating an OLED device is described in detail below with another specific embodiment. As shown inFIG.7, a flow of the method of this embodiment is similar to that of the above embodiment, and differs from that of the above embodiment in that the organic barrier layer of the above embodiment is a continuous thin-film, but an organic barrier layer of this embodiment is preferably a discontinuous thin-film. In an embodiment of the present invention, as shown inFIG.8, when an organic barrier layer is a discontinuous thin-film, the organic layer comprises a plurality of independent block unit thin-films, and each of the block unit thin-films may cover a single pixel or a plurality of pixels adjacent to each other in an OLED device20thin-film. In another embodiment of the present invention, as shown inFIG.9, when an organic barrier layer is a discontinuous thin-film, the organic layer may also comprise a plurality of independent strip unit thin-films, and each of the strip unit thin-films may cover a single row of pixels or a plurality of rows of pixels adjacent to each other in an OLED device thin-film. The above description of various embodiments of the present disclosure with reference to the accompanying drawings is used to illustrate specific embodiments that can be practiced. Directional terms mentioned in the present disclosure, such as “above”, “below”, “front”, “rear”, “left”, “right”, “inside”, “outside”, “side”, are merely used to indicate the direction of the accompanying drawings. Therefore, the directional terms are used for illustrating and understanding the present disclosure rather than limiting the present disclosure. In the figures, elements with similar structures are indicated by the same reference numerals. It should be noted that a thickness and shape of each layer in the accompanying drawings of the present invention do not reflect true proportions, and are only intended to schematically illustrate embodiments of the present application. The present disclosure provides an encapsulation structure and an encapsulation method for a flexible OLED device, in which an organic layer is disposed on an outermost layer of the OLED device and is treated by a plasma surface treatment process, so that an outermost surface of the organic layer becomes a thin surface hardened layer. The surface hardened layer and a remaining unhardened portion of the organic layer form an organic barrier layer. The surface hardened layer can prevent moisture invasion and erosion, thereby extending a service life of the OLED device. The unhardened portion of the organic barrier layer can help to completely release tensile stress of an inorganic layer. An encapsulation structure for a flexible OLED device of the present invention can improve moisture and oxygen blocking performance and simultaneously reduce a risk of degradation of a thin-film encapsulation structure during bending. In the above, the present application has been described in the above preferred embodiments, but the preferred embodiments are not intended to limit the scope of the present application, and those skilled in the art may make various modifications without departing from the scope of the present application. The scope of the present application is determined by claims. | 14,016 |
11943955 | DESCRIPTION OF EMBODIMENTS First Embodiment In the descriptions below, the term “same layer” means that constituent features are formed in the same process. The term “lower layer (or layer below)” means that a constituent feature is formed in a previous process before a comparative layer is formed. The term “upper layer (or layer above)” means that a constituent feature is formed in a successive process after a comparative layer is formed. An illustration (a) ofFIG.1is a top view of a display device2according to this embodiment. An illustration (b) ofFIG.1is a back view of the display device2according to this embodiment.FIG.2illustrates a cross-sectional view taken along arrows A-A in the illustration (a) ofFIG.1.FIG.3illustrates an enlarged top view of a region B in the illustration (a) ofFIG.1; that is, a region including a third-inorganic-insulating-film second slit20B to be described later. Note that the display device2inFIG.1is illustrated on a substantial plane and not folded along a fold portion FD to be described later. Note that directions of the illustration (a) inFIG.1are defined as follows: A direction on the observer's right is a positive direction along an X-axis. An upward direction is a positive direction along a Y-axis. A direction toward the observer is a positive direction along a Z-axis. Moreover, X-axes, Y-axes, and Z-axes in the drawings of DESCRIPTION correspond to respective axes throughout the drawings. That is, as seen in the illustration (a) ofFIG.1, DESCRIPTION defines that the X-axis direction, the Y-axis direction, and the Z-axis direction respectively indicate a longitudinal direction of a display region DA of the display device2, a transverse direction of the display region DA of the display device2, and a thickness direction of the display device2. As seen in the illustration (a) ofFIG.1, the display device2according to this embodiment includes the display region DA and a frame region NA adjacent to, and surrounding, the display region DA. With reference toFIG.2, described below in detail are configurations of the layers included in the display region DA of the display device2according to this embodiment. As illustrated inFIG.2, the display device2according to this embodiment includes: a film layer10; a bonding layer11; a resin layer12; a TFT layer4; a light-emitting element layer5; a sealing layer6; and a functional film29in the stated order from below. Note that the functional film29may have such functions as optical compensation, touch sensing, and protection. The film layer10serving as a base-material film of the display device2may contain, for example, an organic resin material. The bonding layer11, bonding the film layer10and the resin layer12together, may be formed of a conventionally known adhesive. The resin layer12is made of, for example, polyimide. The TFT layer4includes: a barrier layer3; a semiconductor film15; a first inorganic insulating film16(a gate insulating film); a gate electrode GE; a second inorganic insulating film18: a capacitance electrode CE; a third inorganic insulating film20; a source wire SH (a metal wire layer); and a planarization film21(an interlayer insulating film) in the stated order from below. A TFT Tr is formed to include the semiconductor film15, the first inorganic insulating film16, and the gate electrode GE. When the display device2is in use, the barrier layer3keeps water and impurities from reaching the TFT layer4and the light-emitting element layer5. An example of the barrier layer3includes a silicon oxide film, a silicon nitride film, or a silicon oxide nitride film formed by the CVD, or a multilayer film including those films. The semiconductor film15is formed of, for example, low-temperature polysilicon (LTPS) or an oxide semiconductor. Note that, inFIG.2, the TFT including the semiconductor film15as a channel is of a top gate structure. Alternatively, the TFT may be of a bottom gate structure (when the channel of the TFT is, for example, an oxide semiconductor). The gate electrode GE, the capacitance electrode CE, or the source wire SH may include at least one of such metals as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu). That is, the gate electrode GE, the capacitance electrode CE, or the source wire SH is a monolayer film or a multilayer film made of these metals. The first inorganic insulating film16, the second inorganic insulating film18, and the third inorganic insulating film20can be, for example, a silicon oxide (SiOx) film, or a silicon nitride (SiNx) film formed by the CVD, or a multilayer film including these films. In this embodiment, the barrier layer3, the first inorganic insulating film16, the second inorganic insulating film18, and the third inorganic insulating film20are included in an inorganic insulating film4A. The planarization film21may be made of an applicable photosensitive organic material such as polyimide and acrylic. The light-emitting element layer5(e.g. an organic light-emitting diode layer) includes: a pixel electrode22(a first electrode, for example, an anode); a cover film (an edge cover)23covering an edge of the pixel electrode22; a light-emitting layer24; and an upper electrode (a second electrode, for example, a cathode)25in the stated order from below. For each of the sub-pixels SP, the light-emitting element layer5includes: a light-emitting element (e.g. an organic light-emitting diode or OLED) including the pixel electrode22shaped into an island, the light-emitting layer24shaped into an island, and the upper electrode25; and a sub-pixel circuit driving the light-emitting element. Moreover, in the TFT layer4, a transistor Tr is formed for each sub-pixel circuit, and the sub-pixel circuit is controlled through the control of the transistor Tr. In plan view, the pixel electrode22is positioned to overlap the planarization film21and a contact hole that is an opening in the planarization film21. The pixel electrode22is electrically connected through the contact hole to the source wire SH. Hence, the pixel electrode22is supplied with a signal of the TFT layer4through the source wire SH. Note that the pixel electrode22may have a thickness of, for example, 100 nm. The pixel electrode22is shaped into an island for each of the sub-pixels SP. The pixel electrode22includes, for example, indium tin oxide (ITO) and an alloy containing Ag stacked on top of another, and reflects light. The upper electrode25is shaped into a monolithic form as a common layer for the sub-pixels. The upper electrode25can be formed of a light-transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). The cover film23, an organic insulating film, is formed in a position for covering the edge of the pixel electrode22. The cover film23includes an opening23cfor each of the sub-pixels SP to partially expose the pixel electrode22. The light-emitting layer24includes, for example, a hole-transport layer, a light-emitting layer, and an electron-transport layer stacked on top of an other in the stated order from below. In this embodiment, at least one layer of the light-emitting layer24is formed by vapor deposition. Furthermore, in this embodiment, each of the layers of the light-emitting layer24may be shaped into an island for a corresponding one of the sub-pixels SP, or may be shaped into a monolithic form as a common layer for the sup-pixels SP. If the light-emitting element layer5is an OLED layer, holes and electrons recombine together in the light-emitting layer24by a drive current between the pixel electrode22and the upper electrode25, which forms an exciton. While the exciton transforms to the ground state, light is released. Since the upper electrode25is translucent and the pixel electrode22is light-reflective, the light emitted from the light-emitting layer24travels upward. This is how the display device2is of a top emission type. The sealing layer6includes: a first inorganic sealing film26above the upper electrode25; an organic sealing film27above the first inorganic sealing film26; and a second inorganic sealing film28above the organic sealing film27. The sealing layer6prevents such foreign objects as water and oxygen from penetrating into the light-emitting element layer5. An example of the first and second inorganic sealing films26and28includes a silicon oxide film, a silicon nitride film, or a silicon oxide nitride film formed by the CVD, or a multilayer film including these films. The organic sealing film27may be made of an applicable photosensitive organic material such as polyimide and acrylic. In this embodiment, the frame region NA includes the film layer10to the TFT layer4from among the layers inFIG.2. The frame region NA further includes a terminal T and the fold portion FD. The terminal T is formed at an end of the frame region NA. Mounted on the terminal T is a not-shown component such as a driver. The driver supplies a signal, through a connection wire CL from the display region DA, for driving each of the light-emitting elements in the display region DA. In this embodiment, the terminal T may be shaped into any given shape. The fold portion FD is formed, between the terminal T and the display region, along a side of the frame region NA. The display device2bends along the fold portion FD so that a portion of the frame region NA can be folded back against a back face of the display device2. The display device2is bent along the fold portion FD, and a portion of the frame region NA is folded back. Hence, the terminal T is disposed against the back face of the display device2. Such a feature makes it possible to reduce an area of the frame region NA when the display device2is observed in a top view. Described in detail with reference toFIGS.3to5is a structure around the fold portion FD.FIG.3is an enlarged top view of the region B in the illustration (a) ofFIG.1. An illustration (a) ofFIG.4is a cross-sectional view taken along arrows X1-X1inFIG.3. An illustration (b) ofFIG.4is a cross-sectional view taken along arrows X2-X2inFIG.3. An illustration (c) ofFIG.4is a cross-sectional view taken along arrows X3-X3inFIG.3. An illustration (a) ofFIG.5is a cross-sectional view taken along arrows Y1-Y1inFIG.3. An illustration (b) ofFIG.5is a cross-sectional view taken along arrows Y2-Y2inFIG.3. As seen inFIG.3and the illustrations (a) and (b) ofFIG.4, the frame region NA includes a barrier-layer first slit3A formed in a position to overlap the fold portion FD, and serving as a slit of the barrier layer3. The frame region NA further includes: a first-inorganic-insulating-film first slit16A; a second-inorganic-insulating-film first slit18A; and a third-inorganic-insulating-film first slit20A formed in a position to overlap the fold portion FD and the barrier-layer first slit3A, and each serving as a slit of a corresponding one of the first inorganic insulating film16, the second inorganic insulating film18, and the third inorganic insulating film20. That is, the frame region NA includes an inorganic-insulating-film first slit SA formed in a position to overlap the fold portion FD, and serving as a slit of the inorganic insulating film4A.FIG.3and the illustrations (a) and (b) inFIG.4show the barrier-layer first slit3A and the third-inorganic-insulating-film first slit20A respectively serve as a lower end slit and an upper end slit of the inorganic-insulating-film first slit SA. The inorganic-insulating-film first slit SA is formed to extend in a direction to intersect with an edge of the frame region NA. That is, the inorganic-insulating-film first slit SA is formed along the Y-axis across opposing ends of the frame region NA. In addition, the frame region NA includes an inorganic-insulating-film second slit SB formed to partially overlap the fold portion FD, and branching from the inorganic-insulating-film first slit SA.FIG.3and the illustration (c) inFIG.4show a barrier-layer second slit3B and a third-inorganic-insulating-film second slit20B respectively serving as a lower end slit and an upper end slit of the inorganic-insulating-film second slit SB. The inorganic-insulating-film second slit SB is formed between pluralities of the connection wires CL adjacent to each other. Hence, the connection wires CL do not overlap the inorganic-insulating-film second slit SB. In the frame region NA, the TFT layer4includes, as shown in the illustration (a) ofFIG.4, a first gate-electrode-layer frame wire GE1led from the display region DA, and a second gate-electrode-layer frame wire GE2led from the terminal T. The first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2are formed in the same layer as the gate electrode GE, and are formed above the first inorganic insulating film16. The first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2may be formed together with the gate electrode GE. Moreover, in the frame region NA, the TFT layer4in the illustration (b) ofFIG.4includes: a first capacitance-electrode-layer frame wire CE1led from the display region DA; and a second capacitance-electrode-layer frame wire CE2led from the terminal T. The first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2are formed in the same layer as the capacitance electrode CE, and are formed above the second inorganic insulating film18. The first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2may be formed together with the capacitance electrode CE. Note that, in this embodiment, the first gate-electrode-layer frame wire GE1and the first capacitance-electrode-layer frame wire CE1are alternately formed. Furthermore, in this embodiment, the second gate-electrode layer frame wire GE2and the second capacitance-electrode-layer frame wire CE2are alternately formed. Hence, in the frame region NA, the neighboring wires are formed in different metal layers. Such a feature makes it possible to reduce short-circuit of the wires. Moreover, in the frame region NA, the TFT layer4illustrated inFIG.4includes a fold-portion resin layer19serving as a first resin film provided to fill the inorganic-insulating-film first slit SA and the inorganic-insulating-film second slit SB. The fold-portion resin layer19may be made of the same material as that of the planarization film21or the resin layer12, or may be made of an organic resin material that is different from the materials of the planarization film21and the resin layer12. Furthermore, as illustrated inFIG.4, the fold-portion resin layer19may be provided to fill the inorganic-insulating-film first slit SA and the inorganic-insulating-film second slit SB. In addition, a source-wire-layer frame wire SC is formed above the fold-portion resin layer19and the third inorganic insulating film20. The source-wire-layer frame wire SC may be formed in the same layer as the source wire SH is, and may be formed together with the source wire SH. The source-wire-layer frame wire SC is electrically connected to the first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2. Moreover, the source-wire-layer frame wire SC is electrically connected to the first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2. As shown inFIG.3and the illustrations (a) and (b) inFIG.4, the electric connection is established through a contact CH included in the source-wire-layer frame wire SC and formed inside a contact hole in each of the second inorganic insulating film18and the third inorganic insulating film20. The source-wire-layer frame wire SC, the first gate-electrode-layer frame wire GE1, and the second gate-electrode-layer frame wire GE2constitute the connection wires CL electrically connecting the terminal T to a wire in the display region DA. Moreover, the source-wire-layer frame wire SC, the first capacitance-electrode-layer frame wire CE1, and the second capacitance-electrode-layer frame wire CE2also constitute the connection wires CL. The planarization film21serving as a second resin film is formed above the fold-portion resin layer19and the source-wire-layer frame wire SC. The source-wire-layer frame wire SC is included in the connection wire CL and exposed from the fold-portion resin layer19. Furthermore, as shown in the illustration (b) ofFIG.1andFIGS.3and4, a film-layer first slit10A is formed, to serve as a slit of the film layer10, in a position to overlap the fold portion FD and the inorganic-insulating-film first slit SA. The film-layer first slit10A is also formed to extend in a direction to intersect with an edge of the frame region NA. Hence, as can be clearly seen from the illustration (a) ofFIG.5, the film layer10is not formed in a position to overlap the fold portion FD. Here, since the resin layer12is more flexible than the film layer10, a portion of the frame region NA can be folded back along the fold portion FD against the back face of the display device2. Note that if a bending width of the fold portion FD is as wide as, or narrower than, a width of the film-layer first slit10A, the fold portion FD can bend. Note that, inFIGS.4and5, the bonding layer11is formed in a position including no film layer10. However, forming the bonding layer may be determined in any given manner. The bonding layer11inside the film-layer first slit10A may be either omitted or partially left. Moreover, a film-layer second slit108branching from the film-layer first slit10A is formed in a position to overlap the fold portion FD. The film-layer second slit10B is formed between pluralities of the connection wires CL adjacent to each other. Hence, as clearly seen in the illustration (b) ofFIG.5, the connection wires CL do not overlap the film-layer second slit10B. The bonding layer11inside the film-layer second slit10B may also be either omitted or partially left. As illustrated inFIG.3, the barrier-layer second slit3B is formed to lie out of opposing ends, of the barrier-layer first slit3A, each toward one of the display region DA and the terminal T. Likewise, the third-inorganic-insulating-film second slit20B is formed to lie out of opposing ends, of the third-inorganic-insulating-film first slit20A, each toward one of the display region DA and the terminal T. In a still similar manner, the film-layer second slit10B is formed to lie out of opposing ends, of the film-layer first slit10A, each toward one of the display region DA and the terminal T. Note that, as illustrated inFIG.3, the fold-portion resin layer19includes: an end19A formed to lie out of the inorganic-insulating-film first slit SA; and an end19B formed to lie out of the inorganic-insulating-film second slit SB. In a still similar manner, the end19B is formed to lie out of the end19A toward both the display region DA and the terminal T. Hence, the inorganic-insulating-film second slit SB lies closer to the display region and the terminal than the inorganic-insulating-film first slit SA lies. In a similar manner, the film-layer second slit10B lies closer to the display region and the terminal than the inorganic-insulating-film first slit SA and the film-layer first slit10A lie. Here, as shown in the illustrations (a) and (b) ofFIG.4, the end19A is formed to lie out of the third-inorganic-insulating-film first slit20A. Moreover, the third-inorganic-insulating-film first slit20A is wider than the barrier-layer first slit3A. Furthermore, the barrier-layer first slit3A is wider than the film-layer first slit10A. Hence, the inorganic-insulating-film first slit SA and the fold-portion resin layer19above the inorganic-insulating-film first slit SA are wider than the film-layer first slit10A. In a similar manner, as shown in the illustration (c) ofFIG.4, the end19B is formed to lie out of the third-inorganic-insulating-film second slit20B. Moreover, the third-inorganic-insulating-film second slit20B is wider than the barrier-layer second slit3B. Furthermore, the barrier-layer second slit3B is wider than the film-layer second slit10B. Hence, the inorganic-insulating-film second slit SB and the fold-portion resin layer19above the inorganic-insulating-film second slit SB are wider than the film-layer second slit10B. A method for manufacturing a display device according to this embodiment is described in detail with reference to flowchart inFIG.6. First, at Step S1, the resin layer12is formed on a transparent support substrate (e.g. a mother glass). At Step S2, the barrier layer3is formed above the resin layer12. At Step S2, the barrier-layer first slit3A and the barrier-layer second slit3B may be formed; whereas, the barrier layer3may be deposited but does not have to be patterned. At Step S3, the layers of the TFT layer4except the barrier layer3are formed above the barrier layer3. Step S3is described more specifically, with reference to a flowchart inFIG.7. Note that the term “depositing” hereinafter means deposition of a thin film of a corresponding member, but not subsequent patterning of the thin film. Moreover, the term “forming” means a treatment to include deposition of a thin film of a corresponding member, followed by patterning the thin film. First, at Step S21, the semiconductor film15is formed. At Step22, the first inorganic insulating film16is deposited. At Step S23, the gate electrode GE and a gate wire connected to the gate electrode GE are formed. Here, at Step S23, the first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2are also formed together. At Step S24, the semiconductor film15is doped with an impurity. Step S24can be carried out by a technique to dope a channel of a conventional TFT with various kinds of impurities. At Step25, the second inorganic insulating film18is deposited. At Step S26, the capacitance electrode CE is formed. At Step S26, the first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2may also be formed together. At Step27, the third inorganic insulating film20is deposited. At Step28, deposited films; namely, the first inorganic insulating film16, the second inorganic insulating film18, and the third inorganic insulating film20, are patterned by, for example, photolithography. Here, at Step28, the contact hole in which the contact CH of the source-wire-layer frame wire SC is formed is also formed in the second inorganic insulating film18and the third inorganic insulating film20. At Step S29, the inorganic-insulating-film first slit SA and the inorganic-insulating-film second slit SB are formed. Step S29involves patterning the inorganic-insulating-film first slit SA and the inorganic-insulating-film second slit SB by photolithography. Furthermore, if the barrier layer3is only deposited but not patterned at Step S2, the barrier layer3may be patterned at Step S29. That is, at Step S29, the barrier-layer first slit3A and the barrier-layer second slit3B may be formed. At Step S29, the inorganic insulating film4A is etched all at once up to the resin layer12such that the slits included in the inorganic-insulating-film first slit SA are formed to overlap one an other. Moreover, at Step S29, the inorganic insulating film4A is etched all at once up to the resin layer12such that the slits included in the inorganic-insulating-film second slit SB are also formed to overlap one another. In this description, Step S28and Step S29are carried out separately. Alternatively, Step S28and Step S29may be carried out simultaneously. At Step S30, the fold-portion resin layer19is formed to fill the inorganic-insulating-film first slit SA and the inorganic-insulating-film second slit SB. At Step S31, the source wire SH is formed. Here, at Step S31, the source-wire-layer frame wire SC and the contact CH are also formed together. At Step S32, the planarization film21is formed, and the formation of the TFT layer4is completed. Here, in forming members in Steps S21, S23, S26, and S28to S32, the members may be deposited first, and, after that, processed by photolithography. Next, at Step S4, the light-emitting device layer (e.g. an OLED element layer)5of a top emission type is formed. At Step S4, the layers of the light-emitting element layer5may be formed by a conventionally known technique. In particular, the light-emitting layer24may be formed by, for example, vapor deposition. At Step S5, the sealing layer6is formed. At Step S6, an upper-face film is attached. At Step S7, the support substrate is removed from the stack. An example technique for removing the support substrate may involve emitting a laser beam to a lower face of the resin layer12through the support substrate to reduce bonding strength between the support substrate and the resin layer12, and removing the support substrate from the resin layer12. At Step S8, the film layer10serving as a lower-face film is attached to the resin layer12through the bonding layer11. At Step S8, the film-layer first slit10A and the film-layer second slit10B may also be formed. At Step S9, the stack from the film layer10to the upper-face film is separated into a plurality of pieces, using for example, a laser beam. At Step S10, a laser beam is emitted on the film layer10of each of the pieces to partially remove the film layer10, so that the film-layer first slit10A and the film-layer second slit10B are formed. In this embodiment, the film layer10is partially removed by the emission of the laser beam. Alternately, the film layer10may be removed by any given technique. At Step S8, for example, the lower-face film to be attached may be provided with notches, using a die. The notches may be conformable with the shapes of the film-layer first slit10A and the film-layer second slit10B. In such a case, the portions of the notches are removed at Step S10so that the film-layer first slit10A and the film-layer second slit10B can be formed. At Step S11, an electronic circuit board (e.g. an IC chip, an FPC, or a chip on film (COF)) is mounted on the terminal T. At Step S12, the upper-face film is removed from each of the pieces. At Step S13, the functional film29is attached to an upper face of each piece. Finally, at Step S14, the display device2is folded at an end, of the fold portion FD, toward the display region DA. This is how a portion, of the frame region NA, including the terminal T is folded back against the back face of the display device2. Hence, the terminal T is positioned against the back face of the display device2. After the electronic circuit board is mounted on the terminal T, the portion, of the frame region, including the terminal T is folded back against the back face of the display device2. Such a feature makes it possible to reduce an area of the frame region NA in planner view, and to provide the display device2with a narrow frame region. An illustration (a) inFIG.8is a schematic top view of the display device2. In the illustration (a), a portion, of the frame region NA, including the terminal T is folded back against the back face of the display device2. An illustration (b) ofFIG.8is a schematic back view of the display device2in the illustration (a) ofFIG.8. As illustrated inFIG.8, the display device2is folded along the fold portion FD. Hence, a fold-back region FL, which is the portion, of the frame region NA, including the terminal T, is folded back against the back face of the display device2. A structure around the fold-back region FL of the display device2is described below, with reference toFIGS.9and10. An illustration (a) ofFIG.9is a cross-sectional view taken along arrows C-C in the illustration (a) ofFIG.8. An illustration (b) ofFIG.9is a cross-sectional view taken along arrows D-D in the illustration (a) ofFIG.8. Moreover, an illustration (a) ofFIG.10is a cross-sectional view taken along arrows E-E in the illustration (a) ofFIG.8. That is, the illustrations (a) and (b) ofFIG.9are cross-sectional views of positions in which the connection wire CL and the third-inorganic-insulating-film second slit20B overlap in the X-axis direction. Moreover, the illustration (a) ofFIG.10is a cross-sectional view of a plane orthogonal to the X-axis. The plane does not overlap the film-layer first slit10A, and intersects with the film-layer second slit10B. The illustration (a) ofFIG.10corresponds to a cross-sectional view taken along arrows F-F in an illustration (b) ofFIG.9. As shown in the illustrations (a) and (b) inFIG.9, the display device2bends along the fold portion FD in an R-shape in an enlarged view. The size of the R-shape may be determined, depending on a thickness of the film layer10. Here, the film layer10in the position to overlap the fold portion FD is removed with the film-layer first slit10A or the film-layer second slit10B. Hence, even if the display device2is folded along the fold portion FD, the film layer10is free from great stress. Furthermore, each of the barrier layer3, the first inorganic insulating film16, the second inorganic insulating film18, and the third inorganic insulating film20, which are high in bending stiffness, is removed with a slit of the corresponding member. Hence, in the position to overlap the fold portion FD in the frame region NA, the layers above the resin layer12include only the fold-portion resin layer19, the planarization film21, and the source-wire-layer frame wire SC all of which are low in bending stiffness. Such a feature makes it possible to reduce stress on the layers of the display device2when the display device2is folded along the fold portion FD. As shown in the illustration (a) ofFIG.10, the source-wire-layer frame wire SC overlaps the film layer10also when the fold-back region FL is folded back against the back face of the display device2. That is, the film-layer second slit10B does not overlap the connection wire CL in the fold-back region FL, either. Likewise, the inorganic-insulating-film second slit SB does not overlap the connection wire CL in the fold-back region FL, either. Here, an illustration (b) ofFIG.10shows the display device2in the illustration (a) ofFIG.10. The display device2is bent in a direction orthogonal to the folding direction of the fold portion FD such that a crease is formed on the display device2along the X-axis. As shown in the illustration (b) ofFIG.10, the display device2bends greater in a bend portion R, in which the film layer10and the inorganic insulating films are removed such that bending stiffness is relatively low, than in a stiff portion S, in which the film layer10and the inorganic insulating films are formed such that bending stiffness is relatively high. Hence, the connection wire CL, positioned to overlap the stiff portion S bending little, is less likely to receive stress even if bending. Such a feature makes it possible to reduce the risk of breaking the connection wire CL due to the bend of the display device2. Moreover, compared with a case where no bend portion R is provided, the display device2is more likely to bend in the direction orthogonal to the folding direction of the fold portion FD; that is, a direction in which a crease is formed on the display device2along the X-axis. Such a feature allows the fold portion FD to be bent in a direction different from the folding direction, while reducing the risk of breaking the connection line CL in the fold portion FD. In this embodiment, the display device2includes, but not limited to, both the film-layer second slit10B and the inorganic-insulating-film second slit SB. Alternatively, the display device2including either the film-layer second slit10B or the inorganic-insulating-film second slit SB may also achieve advantageous effects described above. Note that, the display device2including both the film-layer second slit10B and the inorganic-insulating-film second slit SB can further reduce the risk of breaking the connection wire CL and facilitate bending of the fold portion FD in a direction different from the folding direction. Moreover, in this embodiment, each of the film-layer second slit10B and the inorganic-insulating-film second slit SB is respectively branched from the film layer first slit10A and the inorganic-insulating-film first slit SA, and is shaped substantially semicircularly. However, the shape of the film-layer second slit10B and the inorganic-insulating-film second slit SB shall not be limited to the semicircle in particular, as long as the shape includes a curve in a portion where stress concentrates. Furthermore, in the above description, the connection wire CL in the fold-back region FL is of two types including: the first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2; and the first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2. However, the connection wire CL shall not be limited to the two types. If the wires have a sufficient width and spacing between the neighboring wires, the connection wire CL may be of either one type. Moreover, in a case where more kinds of signals are to be applied to wires; that is, a case where wires receiving a function signal including a touch panel signal and a plurality of signals for video signal lines are to be routed in the same region, the wires may include two or more kinds of wires. Although not shown in this embodiment, the end19B, formed to lie out of the inorganic-insulating-film second slit SB, may be formed in a position to overlap the end19A as long as the wire CL is free from break and is resistant to adverse environmental conditions. Although not shown in this embodiment, a protective resin layer may further be formed on the planarization film21in the fold portion, to enhance the structure of the display device2against the external environment. The protective resin layer may be formed in any given stage; that is, either before or after the fold portion FD is folded. Although not shown in this embodiment, a protective resin is further applied in a space created between the film layer10and the resin layer12after the fold portion FD is folded, to further enhance the structure of the display device2against the external environment. Modification A structure of the display device2according to a modification of this embodiment is described with reference toFIG.11.FIG.11is a cross-sectional view of the display device2according to this modification, corresponding to the illustration (a) ofFIG.4. In this modification, the display device2includes a capacitance-electrode-layer frame wire CC provided in a position to overlap the inorganic-insulating-film first slit SA, and electrically connecting the first gate-electrode-layer frame wire GE1and the second gate-electrode-layer frame wire GE2together. The capacitance-electrode-layer frame wire CC is formed in the same layer, and of the same material, as the capacitance electrode CE is formed. Hence, the capacitance-electrode-layer frame wire CC electrically connects to the first gate-electrode-layer frame wire GE1and to the second gate-electrode-layer frame wire GE2through the contact CH in the contact hole formed in the second inorganic insulating film18. Moreover, the capacitance-electrode-layer frame wire CC is formed below the fold-portion resin layer19. Note that, as shown in the illustration (b) ofFIG.4, the source-wire-layer frame wire SC in this modification is formed in a position where the first capacitance-electrode-layer frame wire CE1and the second capacitance-electrode-layer frame wire CE2are led out. Hence, in this modification, the capacitance-electrode-layer frame wire CC and the source-wire-layer frame wire SC are alternatively formed adjacently to each other in a position to overlap the inorganic-insulating-film first slit SA. In this modification, the capacitance-electrode-layer frame wire CC and the source-wire-layer frame wire SC, each of which is a different frame wire, are formed in a position to overlap the inorganic-insulating-film first slit SA. Hence, the layers to be formed are different from each other, making it possible to further reduce short circuit of the neighboring frame wires. Second Embodiment FIG.12illustrates an enlarged top view of the display device2according to this embodiment, corresponding toFIG.3. Comparing the display device2according to this embodiment with the one according to the previous embodiment, the fold-portion resin layer19serving as the first resin film includes a fold-portion-resin-layer recess19C serving as a first resin film recess. The fold-portion-resin-layer recess19C includes a bottom19D. Furthermore, comparing the display device2according to this embodiment with the one according to the previous embodiment, the planarization film21serving as the second resin film includes a planarization-film slit21B formed in the frame region NA and serving as a second-resin-film slit. Other than those points, the display device2according to this embodiment has the same features as the display device2according to the previous embodiment has. The fold-portion-resin-layer recess19C and the planarization-film slit21B according to this embodiment are described in detail, with reference toFIGS.13and14. An illustration (a) ofFIG.13is a cross-sectional view taken along arrows X1-X1inFIG.12. An illustration (b) ofFIG.13is a cross-sectional view taken along arrows X2-X2inFIG.12. An illustration (c) ofFIG.13is a cross-sectional view taken along arrows X3-X3inFIG.12. An illustration (a) ofFIG.14is a cross-sectional view taken along arrows Y1-Y1inFIG.12. An illustration (b) ofFIG.14is a cross-sectional view taken along arrows Y2-Y2inFIG.12. As shown in the illustrations (a) and (b) ofFIG.13, the display device2does not include either the fold-portion-resin-layer recess19C or the planarization-film slit21B in a position to overlap the connection wire CL. Hence, in a position where the connection wire CL is formed, the display device2according to this embodiment has the same in layer structure as the display device2according to the previous embodiment has. Meanwhile, as shown inFIG.12and the illustration (c) ofFIG.13, the display device2includes the planarization-film slit21B in a position to overlap the third-inorganic-insulating-film second slit20B, the barrier-layer second slit3B, and the film-layer second slit10B. Moreover, as shown inFIG.12and the illustration (c) ofFIG.13, the display device2includes the fold-portion-resin-layer recess19C in a position to overlap the planarization film slit21B. Furthermore, as shown in the illustrations (a) and (b) ofFIG.14, the fold-portion-resin-layer recess19C and the planarization-film slit21B are formed between pluralities of the connection wires CL adjacent to each other, and do not overlap the connection wires CL. A method for manufacturing the display device2according to this embodiment is described, with reference to a flowchart inFIG.15. The method for manufacturing the display device2according to this embodiment is the same as that according to the previous embodiment up to Step S32, and the descriptions thereof shall be omitted. In this embodiment, at Step S33following Step S32, the planarization film slit21B and the fold-portion-resin-layer recess19C are formed. At Step S33, the planarization film21and the fold-portion resin layer19are patterned by, for example, photolithography. In forming the fold-portion-resin-layer recess19C, the bottom19D is formed to have a thickness from the resin layer12. The display device2according to this embodiment is also folded at an end, of the fold portion FD, toward the display region DA, so that a portion, of the frame region NA, including the terminal T can be folded back against the back face of the display device2. Described below in detail with reference toFIGS.16and17is a structure around the fold portion FD when a portion, of the frame region NA, including the terminal T is folded back against the back face of the display device2. Note that an illustration (a) ofFIG.16, an illustration (b) ofFIG.16, and an illustration (a) ofFIG.17are cross-sectional views respectively corresponding to the illustration (a) ofFIG.9, the illustration (b) ofFIG.9, and the illustration (a) ofFIG.10. In this embodiment, as shown in the illustrations (a) and (b) ofFIG.16, the film layer10in the position to overlap the fold portion FD is removed with the film-layer first slit10A or the film-layer second slit10B. Hence, even if the display device2is folded along the fold portion FD, the film layer10is free from great stress. Moreover, as shown in the illustration (b) ofFIG.16, only the bonding layer11, the resin layer12, and the fold-portion resin layer19of the fold portion FD overlap one another in a position where the fold-portion-resin-layer recess19C and the planarization film slit21B are formed. Hence, the display device2according to this embodiment can be bent more readily along the fold portion FD. As shown in an illustration (a) ofFIG.17in this embodiment, neither the film-layer second slit10B nor the inorganic-insulating-film second slit SB overlaps the connection wire CL in the fold-back region FL. In addition, as shown in the illustration (a) ofFIG.17, neither the fold-portion-resin-layer recess19C nor the planarization-film slit21B overlaps the connection wire CL in the fold-back region FL. Here, an illustration (b) ofFIG.17shows the display device2in the illustration (a) ofFIG.17. The display device2is bent in a direction orthogonal to the folding direction of the fold portion FD. Here, the illustration (b) ofFIG.17shows that, in the bend portion R of the display device2, not only the film layer10and the inorganic insulating films but also a portion of the fold-portion resin layer19and the planarization film21are also removed. Compared with the previous embodiment, the bend portion R is further lower in bending stiffness than the stiff portion S, so that the display device2is likely to bend further at the bend portion R. Hence, the stiff portion S is less likely to bend, and that is why the risk of breaking the connection wire CL, formed in a position to overlap the stiff portion S, is further reduced when the display device2is bent. In addition, the lower bending stiffness of the bend portion R allows the display device2to be bent more readily in a direction different from the folding direction of the fold portion FD. In this embodiment, the planarization film21, formed in a position where the film layer10and the connection line CL do not overlap, is entirely removed along the thickness of the display device2. Hence, the planarization-film slit21B is formed. Moreover, in this embodiment, a portion of the fold-portion resin layer19, formed in a position where the film layer10and the connection line CL do not overlap, is removed along the thickness of the display device2. Hence, the fold-portion-resin-layer recess19C is formed. However, the slit and the recess may be formed in any given manner. In this embodiment, removed may be only a portion of the planarization film21in a position where the film layer10and the connection wire CL do not overlap. Hence, a recess may be formed on the planarization film instead of the fold-portion-resin-layer recess19C and the planarization-film slit21B. In this case, too, the display device2can be bent more readily in a direction different from the folding direction of the fold portion FD. Third Embodiment An illustration (a) ofFIG.18is a top view of the display device2according to this embodiment. An illustration (b) ofFIG.18is a back view of the display device2according to this embodiment.FIG.19is an enlarged top view of a region F in the illustration (a) ofFIG.18; that is, a view around the third-inorganic-insulating-film second slit20B. Note that, as seen inFIG.1,FIG.18also illustrates the display device2on a substantial plane and not folded along the fold portion FD. As shown inFIGS.18and19, in the display device2according to this embodiment, at least one inorganic-insulating-film second slit SB obliquely intersects with an end, of the inorganic-insulating-film first slit SA, toward the display region DA. Moreover, in the display device2according to this embodiment, at least one film-layer second slit10B obliquely intersects with an end, of the film-layer first slit10A, toward the display region DA. In addition, at least one inorganic-insulating-film second slit SB and at least one film-layer second slit10B overlap. Furthermore, in the display device2according to this embodiment, the connection wire CL obliquely intersects with the end, of the inorganic-insulating-film first slit SA, toward the display region DA to run along the inorganic-insulating-film second slit SB. Likewise, in the display device2according to this embodiment, the connection wire CL obliquely intersects with the end, of the film-layer first slit10A, toward the display region DA, to run along the film-layer second slit10B. Meanwhile, the connection wire CL extends from the terminal T and orthogonally intersects with ends, of the inorganic-insulating-film first slit SA and the film-layer first slit10A, toward the terminal T. Because the connection wire CL obliquely intersects with the ends, of the inorganic-insulating-film first slit SA and the film-layer first slit10A, toward the display region DA, the connection wire CL includes a bend point P at which the connection wire CL obliquely bends above the inorganic-insulating-film first slit SA and the film-layer first slit10A. Here, as illustrated inFIG.19of this embodiment, the fold-portion-resin-layer recess19C and the planarization-film slit21B are formed to run along the inorganic-insulating-film second slit SB and the film-layer second slit10B. That is, the fold-portion-resin-layer recess19C and the planarization-film slit21B obliquely intersect with the ends, of the inorganic-insulating-film first slit SA and the film-layer first slit10A, toward the display region DA. Other than those points, the display device2according to this embodiment has the same features as the display device2according to the previous embodiments has. Moreover, the display device2according to this embodiment may be manufactured by the same method for manufacturing the display device2according to the previous embodiments. In the display device2according to this embodiment, at least one inorganic-insulating-film second slit SB and at least one film-layer second slit10B obliquely intersect with the ends, of the inorganic-insulating-film first slit SA and the film-layer first slit10A, toward the display region DA. Such a feature makes it possible to decrease a distance from the display region DA to the ends of the inorganic-insulating-film first slit SA and the film-layer first slit10A. As a result, the area of the frame region NA can be reduced. In this embodiment, as illustrated inFIG.18, the inorganic-insulating-film second slits SB include an inorganic-insulating-film second slit SB positioned in a center of the fold portion FD, and orthogonally intersecting with opposing ends of the inorganic-insulating-film first slit SA. Meanwhile, the inorganic-insulating-film second slits SB include an inorganic-insulating-film second slit SB positioned closer to an end than to the center of the fold portion FD, and obliquely intersecting with an end, of the inorganic-insulating-film first slit SA, toward the display region DA. Any inorganic-insulating-film second slit SB obliquely intersecting with an end of the inorganic-insulating-film first slit SA is angled at the display region DA to run from the center toward an end of the fold portion FD. Here, to the display region DA of the fold portion FD, an angle θ is formed at an intersection of a center axis of an inorganic-insulating-film second slit SB with a line in parallel with the Y-axis. In such a case, as shown in the illustration (a) ofFIG.18, the angle θ is a right angle θA if the inorganic-insulating-film second slit SB is in the center of the fold portion FD. Moreover, as shown in the illustration (a) ofFIG.18, the angle θ is an obtuse angle θB if the inorganic-insulating-film second slit SB is formed in the positive direction along the Y-axis in relation to the center of the fold portion FD. Next, to the terminal T of the fold portion FD, an angle θ is formed at the intersection of the center axis of an inorganic-insulating-film second slit SB with the line in parallel with the Y-axis. In such a case, as shown in the illustration (a) ofFIG.18, the angle θ is a right angle θC regardless of the position of the inorganic-insulating-film second slit SB. That is, in this embodiment, all the inorganic-insulating-film second slits SB intersect, at a right angle, with the ends, of the inorganic-insulating-film first slit SA, toward the terminal T. As shown in the illustration (a) ofFIG.18, the inorganic-insulating-film second slits SB are provided to shorten the length of the connection wires CL, as well as to decrease the distance between the terminals T, contributing to reduce the size of the mounting area. Note that, as shown in the illustration (b) ofFIG.18, a film-layer second slit10B, positioned closer to an end than to the center of the fold portion FD, may also be obliquely intersect with an end, of the film-layer first slit10A, toward the display region DA. In this embodiment, the bend point P at which the connection wire CL bends is disposed to overlap the inorganic-insulating-film first slit SA and the film-layer first slit10A at a subsequent center of the film-layer first slit10A. However, the position of the bend point P shall not be limited to such a position. Each of the bend points P may be shifted in a different position toward the terminals T or toward the display region DA, as long as the bend points P overlap the inorganic-insulating-film first slit SA. Furthermore, the inorganic-insulating-film second slit SB, the film-layer second slit10B, the fold-portion-resin-layer recess19C, and the planarization-film slit21B may also shift toward the terminals T or toward the display region DA in accordance with the shift of the bend point P. Moreover, in this embodiment, the connection wire CL led out from a terminal T extends orthogonally to the film-layer first slit10A and intersects obliquely with the connection wire CL led out from the display region DA. However, the connection line CL may be formed in any given direction. The connection line CL led out from the terminal T may extend in a different oblique direction, in relation to the film-layer first slit10A, from the oblique direction of the connection line CL led out from the display region DA. In this case, too, the inorganic-insulating-film second slit SB, the film-layer second slit10B, the fold-portion-resin-layer recess19C, and the planarization-film slit21B may be shaped conformably to the connection wire CL led out from the display region DA. The display device2in the above embodiments may include a flexible display panel including a bendable display element. The display element includes two kinds of display elements: one of which has brightness and transmittance controlled by current, and an other one of which by voltage. The display device2according to the above embodiments may include, for example, an OLED as a display element controlled by current. In this case, the display device according to this embodiment may be an organic electroluminescence (EL) display. The display device2according to the above embodiments may include an inorganic light-emitting diode as a display element controlled by current. In such a case, the display device according to this embodiment may include an EL display such as an inorganic EL display, and a quantum dot light-emitting diode (QLED) display including a QLED. Moreover, the display elements controlled by voltage include liquid crystal display elements. SUMMARY A display device according to a first aspect includes: a display region including a plurality of display elements, and a frame region surrounding the display region; a film layer and a TFT layer stacked on top of an other in a stated order, the TFT layer including at least one inorganic insulating film; and a terminal and a fold portion in the frame region, the fold portion being formed between the terminal and the display region. The display device includes: an inorganic-insulating-film first slit provided to the inorganic insulating film, and a film-layer first slit provided to the film layer, the inorganic-insulating-film first slit and the film-layer first slit overlapping at least the fold portion, and extending in a direction to intersect with an edge of the frame region; a first resin film included in the TFT layer and provided to fill the inorganic-insulating-film first slit; a plurality of connection wires provided above the inorganic insulating film and the first resin film to overlap, and to intersect with, the fold portion, the connection wires electrically connecting the terminal to a wire in the display region; and either an inorganic-insulating-film second slit overlapping the fold portion and intersecting with the inorganic-insulating-film first slit, or a film-layer second slit overlapping the fold portion and intersecting with the film-layer first slit, either the inorganic-insulating-film second slit or the film-layer second slit being provided between pluralities of the connection wires adjacent to each other. In a second aspect, the inorganic-insulating-film second slit may be wider than the film-layer second slit. In a third aspect, the first resin film may be provided to further fill the inorganic-insulating-film second slit. In a fourth aspect, the first resin film may include a first resin film recess to overlap either the inorganic-insulating-film second slit or the film-layer second slit. In a fifth aspect, the display device may further include a second resin film formed on the first resin film and the connection wires, wherein the second resin film may include either a second resin film slit or a second resin film recess to overlap either the inorganic-insulating-film second slit or the film-layer second slit. In a sixth aspect, (i) the inorganic-insulating-film second slit may lie closer to the display region and the terminal than the inorganic-insulating-film first slit lies, or (ii) the film-layer second slit may lie closer to the display region and the terminal than the film-layer first slit lies. In a seventh aspect, (i) at least one of a plurality of the inorganic-insulating-film second slits may obliquely intersect with an end, of the inorganic-insulating-film first slit, toward the display region, or (ii) at least one of a plurality of the film-layer second slits may obliquely intersect with an end, of the film-layer first slit, toward the display region. In an eighth aspect, the connection wires may obliquely intersect with either: at least the end, of the inorganic-insulating-film first slit, toward the display region to run along the inorganic-insulating-film second slit; or at least the end, of the film-layer first slit, toward the display region to run along the film-layer second slit. In a ninth aspect, a plurality of the inorganic-insulating-film second slits may include: an inorganic-insulating-film second slit positioned in a center of the fold portion, and orthogonally intersecting with opposing ends of the inorganic-insulating-film first slit; and an inorganic-insulating-film second slit positioned closer to an end than to a center of the fold portion, and obliquely intersecting with an end of the inorganic-insulating-film first slit. In a tenth aspect, the connection wires may extend from the terminal and orthogonally intersect with an end, of either the inorganic-insulating-film first slit or the film-layer first slit, toward the terminal, and each of the connection wires may include a bend point at which the connection wire obliquely bends above either the inorganic-insulating-film first slit or the film-layer first slit. In an eleventh aspect, the first resin film may include a first resin film recess formed: to run along either the inorganic-insulating-film second slit obliquely intersecting with an end of the inorganic-insulating-film first slit, or the film-layer second slit obliquely intersecting with an end of the film-layer first slit; and to overlap either the inorganic-insulating-film second slit, or the film-layer second slit. In a twelfth aspect, the display device may further include a second resin film formed on the first resin film and the connection wires, wherein the second resin film may include either a second resin film slit or a second resin film recess formed: to run along either the inorganic-insulating-film second slit obliquely intersecting with an end of the inorganic-insulating-film first slit, or the film-layer second slit obliquely intersecting with an end of the film-layer first slit; and to overlap either the inorganic-insulating-film second slit, or the film-layer second slit. In a thirteenth aspect, the display device may include both the inorganic-insulating-film second slit and the film-layer second slit. In a fourteenth aspect, the inorganic-insulating-film second slit may be wider than the film-layer second slit. A fifteenth aspect is directed to a method for manufacturing a display device. The display device includes: a display region including a plurality of display elements, and a frame region surrounding the display region; a film layer and a TFT layer stacked on top of an other in a stated order, the TFT layer including at least one inorganic insulating film; and a terminal and a fold portion in the frame region, the fold portion being formed between the terminal and the display region. The method includes forming the film layer, and forming the TFT layer. The forming of the TFT layer includes forming an inorganic-insulating-film first slit in the fold portion, and the forming of the film layer includes a film-layer first slit in the fold portion. The inorganic-insulating-film first slit is provided to the inorganic insulating film. The film-layer first slit is provided to the film layer. The inorganic-insulating-film first slit and the film-layer first slit extend in a direction to intersect with an edge of the frame region. The forming of the TFT layer further includes: forming a first resin film provided to fill the inorganic-insulating-film first slit; and forming a plurality of connection wires provided above the inorganic insulating film and the first resin film to overlap, and to intersect with, the fold portion, the connection wires electrically connecting the terminal to a wire in the display region. The forming of the TFT layer involves forming an inorganic-insulating-film second slit intersecting with the inorganic-insulating-film first slit in the fold portion, and the forming of the film layer involves forming a film-layer second slit intersecting with the film-layer first slit in the fold portion. Either the inorganic-insulating-film second slit or the film-layer second slit is provided between pluralities of the connection wires adjacent to each other. The disclosure shall not be limited to the embodiments described above, and can be modified in various manners within the scope of claims. The technical aspects disclosed in different embodiments are to be appropriately combined together to implement another embodiment. Such an embodiment shall be included within the technical scope of the disclosure. Moreover, the technical aspects disclosed in each embodiment may be combined to achieve a new technical feature. | 59,898 |
11943956 | DETAILED DESCRIPTION Aspects of some embodiments of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects of the present disclosure may not be described. Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Further, parts not related to the description of the embodiments might not be shown to make the description clear. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Various embodiments are described herein with reference to sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Further, specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. In the detailed description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this indicates that the first part is arranged at an upper side or a lower side of the second part without the limitation to the upper side thereof on the basis of the gravity direction. Further, in this specification, the phrase “on a plane,” or “plan view,” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side. It will be understood that when an element, layer, region, or component is referred to as being “formed on,” “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component or intervening layers, regions, or components may be present. However, “directly connected/directly coupled” refers to one component directly connecting or coupling another component without an intermediate component. Similarly, the expression “A component X is arranged directly on a component Y” means that there are no adhesion layers/adhesion members arranged between the components X and Y (e.g., the component X is formed on a base surface of the component Y via a consecutive process after the component Y is formed). Meanwhile, other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present. For the purposes of this disclosure, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expression such as “at least one of A and B” may include A, B, or A and B. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression such as “A and/or B” may include A, B, or A and B. In the examples, the x-axis, the y-axis, and/or the z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. The same applies for first, second, and/or third directions. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, any numerical range disclosed and/or recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein. All such ranges are intended to be inherently described in this specification such that amending to expressly recite any such subranges would comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 132(a). The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. FIG.1is a schematic plan view of a portion of a display apparatus1according to some embodiments. Referring toFIG.1, the display apparatus1includes a display area DA, and a peripheral area NDA outside the display area DA. A plurality of pixels P including a display element are arranged in the display area DA, and the display apparatus1may provide an image by using light that is emitted by the plurality of pixels P arranged in the display area DA. The peripheral area NDA is a non-display area where no display elements are arranged, and the display area DA may be entirely surrounded by the peripheral area NDA. AlthoughFIG.1illustrates the display apparatus1including a flat display surface, embodiments of the disclosure are not limited thereto. According to other embodiments, the display apparatus1may include a three-dimensional display surface or a curved display surface. When the display apparatus1includes a three-dimensional display surface, the display apparatus1may include a plurality of display areas pointing in different directions, and, for example, may include a display surface in the form of a polyprism. According to other embodiments, when the display apparatus1includes a curved display surface, the display apparatus1may be implemented in various types, such as flexible, foldable, and rollable display apparatuses. According to some embodiments,FIG.1illustrates a display apparatus1applicable to mobile phones. For example, electronic modules, a camera module, a power supply module, and the like mounted on a main board may be arranged in a bracket/case or the like together with the display apparatus1, thereby constituting a mobile phone. The display apparatus1according to some embodiments is applicable to not only large-sized electronic apparatuses, such as televisions and monitors, but also small- and medium-sized electronic apparatuses, such as tablets, automobile navigation devices, game players, and smart watches. FIG.1illustrates a case where the display area DA of the display apparatus1has a shape of an edge-rounded rectangle. However, according to other embodiments, the shape of the display area DA may be a circle, an oval, or a polygon such as a triangle or a pentagon. Although an organic light-emitting display apparatus will now be illustrated and described as the display apparatus1according to some embodiments of the disclosure, other embodiments are not limited thereto. According to other embodiments, the display apparatus1may be an inorganic light-emitting display, a quantum dot light-emitting display, or the like. For example, an emission layer of a display element included in the display apparatus1may include an organic material, include an inorganic material, include quantum dots, include an organic material and quantum dots, or include an inorganic material and quantum dots. FIGS.2A and2Bare schematic cross-sectional views of the display apparatus1ofFIG.1taken along the line A-A′, andFIG.3is a schematic plan view of a portion of the display apparatus1according to some embodiments.FIGS.2A,2B, and3are simplified cross-sectional views for explaining a stacking relationship between a functional panel and/or functional layers that constitute the display apparatus1. Referring toFIG.2A, the display apparatus1according to some embodiments may include a display layer DU, an input-sensing layer TU, an optical functional layer OU, an anti-reflection layer PU, and a window layer WU. At least some components from among the display layer DU, the input-sensing layer TU, the optical functional layer OU, the anti-reflection layer PU, and the window layer WU may be formed by consecutive processes, or may be combined with each other via an adhesion member.FIG.2Aillustrates an optically clear adhesion member OCA as the adhesion member. An adhesion member to be described hereinafter may include a typical adhesive. According to some embodiments, the anti-reflection layer PU and the window layer WU may be replaced by other components or may be omitted. According to some embodiments, the input-sensing layer TU is arranged directly on the display layer DU. The combination of the display layer DU, the input-sensing layer TU arranged directly on the display layer DU, and the optical functional layer OU may be defined as a display panel DP. According to some embodiments, as shown inFIG.2A, optically clear adhesion members OCA may be arranged between the display panel DP and the anti-reflection layer PU and between the anti-reflection layer PU and the window layer WU, respectively. According to other embodiments, as shown inFIG.2B, the display panel DP may include a color filter layer CU. The color filter layer CU may be arranged between the input-sensing layer TU and the optical functional layer OU. The color filter layer CU may include a color filter included to correspond to a light-emission region of each pixel P, and a light-shielding layer included to correspond to a non-light-emission region between pixels P. According to some embodiments, optically clear adhesion members OCA may be omitted between the color filter layer CU and the display panel DP, and the color filter layer CU may be directly on the display panel DP. The display layer DU generates an image, and the input-sensing layer TU obtains coordinate information of an external input (for example, a touch event). The display panel DP according to some embodiments may further include a protection member arranged on a lower surface of the display layer DU. The protection member and the display layer DU may be combined with each other via an adhesion member. The optical functional layer OU may improve light efficiency. The optical functional layer OU may improve, for example, front light efficiency and/or side visibility of light that is emitted by the organic light-emitting diode OLED. The anti-reflection layer PU reduces reflectivity of external light that is incident thereon from the top of the window layer WU. The anti-reflection layer PU according to some embodiments may include a phase retarder and a polarizer. The phase retarder may be of a film type or liquid-coating type, and may include a λ/2 phase retarder and/or a λ/4 phase retarder. The polarizer may also be of a film type or liquid-coating type. The film type may include a stretchable synthetic resin film, and the liquid-coating type may include liquid crystals arranged (e.g., arranged in a predetermined arrangement). The phase retarder and the polarizer may further include protective films, respectively. The phase retarder and the polarizer, or the protection film may be defined as a base layer of the anti-reflection layer PU. The display layer DU, the input-sensing layer TU, and the optical functional layer OU will now be described in detail with reference toFIG.3. Referring toFIG.3, the display panel DP includes the display layer DU and the input-sensing layer TU. The display layer DU is simply illustrated to explain a stacking structure of the input-sensing layer TU. The anti-reflection layer PU ofFIG.2Aand the window layer WU ofFIG.2Amay be arranged on the input-sensing layer TU in some embodiments. The display layer DU may be obtained by sequentially arranging a circuit layer CL, an organic light-emitting diode OLED, and a thin-film encapsulation layer TFE on a substrate100. The input-sensing layer TU may be arranged directly on the thin-film encapsulation layer TFE. The thin-film encapsulation layer TFE includes at least one organic encapsulation layer320, as shown inFIG.8A(described later), and thus may provide a flatter base surface. Accordingly, even when the components of the input-sensing layer TU are formed by consecutive processes, a defect rate may be reduced. The input-sensing layer TU may have a multi-layered structure. The input-sensing layer TU includes a detection electrode, a signal line (or trace line) connected to the detection electrode, and at least one insulating layer. The input-sensing layer TU may detect an external input according to, for example, an electrostatic capacitive method. An operation method of the input-sensing layer TU is not particularly limited in the disclosure. According to some embodiments, the input-sensing layer TU may sense an external input according to an electromagnetic induction method or a pressure detection method. As shown inFIG.3, the input-sensing layer TU according to some embodiments may include a first insulating layer IL1, a first conductive layer CL1, a second insulating layer IL2, and a second conductive layer CL2. For example, each of the first conductive layer CL1and the second conductive layer CL2may have a single-layered structure or a stacked multi-layered structure. A conductive layer having a single-layered structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). Alternatively, the transparent conductive layer may include a conductive polymer (e.g., PEDOT), metal nano wires, graphene, or the like. A conductive layer having a multi-layered structure may include a plurality of metal layers. The plurality of metal layers may have, for example, a three-layered structure of titanium/aluminum/titanium (Ti/Al/Ti). The conductive layer having a multi-layered structure may include at least one metal layer and at least one transparent conductive layer. Each of the first conductive layer CL1and the second conductive layer CL2includes a plurality of patterns. It may be hereinafter understood that the first conductive layer CL1includes first conductive patterns, and that the second conductive layer CL2includes second conductive patterns. The first conductive patterns and the second conductive patterns may form a detection electrode shown inFIG.6. According to some embodiments, the detection electrode may have a mesh shape, as will be described later with reference toFIG.6, which reduces or prevents visual recognition of the detection electrode by a user. Each of the first insulating layer IL1and the second insulating layer IL2may have a single-layered or multi-layered structure. Each of the first insulating layer IL1and the second insulating layer IL2may include an inorganic material or a composite material. For example, at least one of the first insulating layer IL1and the second insulating layer IL2may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. According to other embodiments, the first inorganic insulating layer IL1and/or the second inorganic insulating layer IL2may be replaced by an organic insulating layer. The optical functional layer OU may be directly on the input-sensing layer TU. The optical functional layer OU may include a first layer410, and a second layer420on the first layer410. The first layer410and the second layer420may include an organic insulative material, and may be included to have different refractive indexes. According to some embodiments, the refractive index of the second layer420(e.g., as a high refractive index layer) may be greater than that of the first layer410. FIG.4is a schematic plan view of the display panel DP of the display apparatus1ofFIG.1. Referring toFIG.4, the display panel DP includes a display10, first and second scan driving circuits20and30, a terminal portion40, a data driving circuit50, a driving voltage supply line60, and a common voltage supply line (e.g., common power supply line)70arranged on the substrate100. In other embodiments, an emission-control driving circuit may be further arranged on one side of the first scan driving circuit20. The substrate100may include a material, such as a glass material, metal, or an organic material. According to some embodiments, the substrate100may be formed of a flexible material. For example, the substrate100may include polymer resin, such as polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The display10includes a scan line SL extending in a first direction (e.g., an x direction), a data line DL extending in a second direction (e.g., a y direction), which crosses the first direction (e.g., the x direction), and pixels P connected to a driving voltage line PL. Each of the pixels P may emit, for example, red, green, blue, and/or white light, and may include, for example, an organic light-emitting diode. The display10provides a certain image via light emitted from the pixels P, and a display area DA is defined by the pixels P. The display10may have a shape of an approximate rectangle. However, according to various embodiments, the display10may have a shape of a polygon, a circle, or an oval, or a shape corresponding to some of them. The display10may include a corner portion that corresponds to a generally rectangular shape but has rounded edges. The substrate100on which the display10is located may have outer edges of which at least portions are curved. The first and second scan driving circuits20and30are arranged on the peripheral area NDA of the substrate100, and generate and transmit scan signals to each of the pixels P via the scan line SL. For example, the first scan driving circuit20may be located on the left side of the display10, and the second scan driving circuit30may be located on the right side of the display10. The first and second scan driving circuits20and30are arranged on both sides of the display10, respectively. However, according to other embodiments, a scan driving circuit may be arranged on one side of the display10. The terminal portion40is located on one end of the substrate100and includes a plurality of terminals41,42,43, and44. The terminal portion40may be exposed without being covered with an insulating layer, and may be electrically connected to a controller such as a flexible printed circuit board or a driver integrated circuit (IC) chip. The controller changes a plurality of image signals received from an external source into a plurality of image data signals, and transmits the plurality of image data signals to the data driving circuit50via the terminal41. The data driving circuit50may generate a data signal, and the generated data signal may be transmitted to the display area DA via fanout wires FW. The controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal to generate a control signal for controlling driving of the first and second scan driving circuits20and30, and may transmit the generated control signal to the first and second scan driving circuits20and30via the terminal(s)43. The controller transmits a driving voltage ELVDD and a common voltage ELVSS to the driving voltage supply line60and the common voltage supply line70via the terminals42and44, respectively. The data driving circuit50is on the peripheral area NDA of the substrate100, and generates and transmits a data signal to each of the pixels P via the data line DL. The data driving circuit50may be on one side of the display10, for example, between the terminal portion40and the display10. The driving voltage supply line60may be on the peripheral area NDA. For example, the driving voltage supply line60may be between the data driving circuit50and the display10. The driving voltage supply line60provides the driving voltage ELVDD to the pixels P. The driving voltage supply line60may extend in the first direction (e.g., the x direction), and may be connected to the plurality of driving voltage lines PL each extending in the second direction (e.g., the y direction). The common voltage supply line70is arranged on the peripheral area NDA, and provides the common voltage ELVSS to an opposite electrode230ofFIG.8Aof an organic light-emitting diode of each pixel P. For example, the common voltage supply line70has a loop shape of which one side is open, and accordingly, may extend along an edge of the substrate100with the exception of the terminal portion40. The optical functional layer OU may be on the display area DA. The optical functional layer OU may be over the entire surface of the display area DA, and may partially extend to the peripheral area NDA. Substantially, the optical functional layer OU is arranged on the input-sensing layer TU ofFIGS.2A and3, and may improve luminescent efficiency and side visibility of the pixel P on the display area DA. The optical functional layer OU may include the first layer410, and the second layer420on the first layer410. The first layer410may extend more toward the peripheral area NDA than the second layer420extends, and thus may be closer to the edge of the substrate100. A valley portion VP to be described later may be on the first layer410located on the peripheral area NDA. The second layer420is arranged on the first layer410to extend toward the peripheral area NDA, and may be controlled by, or have a shape corresponding to, the valley portion VP. In other words, the second layer420may be arranged on the peripheral area NDA to not extend beyond the valley portion VP. For example, the second layer420may be formed using an inkjet method. Because the second layer420includes an organic insulative material having good spreadability, the display apparatus1needs a structure capable of controlling spreading of the second layer420in the edge of the substrate100. The valley portion VP may be on the peripheral area NDA to surround the display area DA. The valley portion VP may be on the outside of the common voltage supply line70. According to some embodiments, the first layer410ofFIG.3may extend toward the peripheral area NDA, and the valley portion VP may be defined by removing a portion of the first layer410. The valley portion VP may effectively control spreading of the second layer420included in the display area DA toward the edge of the substrate100. According to some embodiments, the valley portion VP may have a shape of a closed loop to surround the organic layer OL. A structure of the valley portion VP will be described later in detail with reference toFIG.9and its subsequent drawings. FIG.5is an equivalent circuit diagram of a pixel P that may be included in the display apparatus1, according to some embodiments of the disclosure. Referring toFIG.5, each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC includes a driving thin-film transistor Td, a switching thin-film transistor Ts, and a storage capacitor Cst. The switching thin-film transistor Ts is connected to the scan line SL and the data line DL, and transmits, to the driving thin-film transistor Td, a data signal Dm received via the data line DL according to a scan signal Sn received via the scan line SL. The storage capacitor Cst is connected to the switching thin-film transistor Ts and a driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching thin-film transistor Ts and the driving voltage ELVDD supplied to the driving voltage line PL. The driving thin-film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED in accordance with a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a certain brightness by the driving current Id. Although a case where the pixel circuit PC includes two thin-film transistors and one storage capacitor is illustrated inFIG.5, the disclosure is not limited thereto. According to other embodiments, the pixel circuit PC may include seven thin-film transistors one storage capacitor. According to other embodiments, the pixel circuit PC may include two or more storage capacitors. FIG.6is a schematic plan view of an input-sensing layer TU of the display apparatus1according to some embodiments of the disclosure, andFIG.7is a schematic magnified view of a portion B ofFIG.6. Referring toFIG.6, the input-sensing layer TU may include first detection electrodes IE1-1through IE1-5, first signal lines SL1-1through SL1-5respectively connected to the first detection electrodes IE1-1through IE1-5, second detection electrodes IE2-1through IE2-4, and second signal lines SL2-1through SL2-4respectively connected to the second detection electrodes IE2-1through IE2-4. In other embodiments, the input-sensing layer TU may further include optical dummy electrodes arranged on boundary areas between the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4. The thin-film encapsulation layer TFE ofFIG.3includes at least one organic encapsulation layer320ofFIG.8A, and thus provides a flatter base surface. Accordingly, even when the components of the input-sensing layer TU are formed by consecutive processes, a defect rate may be reduced. Because the first signal lines SL1-1through SL1-5and the second signal lines SL2-1through SL2-4are arranged in the peripheral area NDA having a reduced step difference, they may have uniform thicknesses. Accordingly, stress of the first signal lines SL1-1through SL1-5and the second signal lines SL2-1through SL2-4, which may be otherwise caused by a step difference of a lower layer, may decrease. The first detection electrodes IE1-1through IE1-5cross the second detection electrodes IE2-1through IE2-4. The first detection electrodes IE1-1through IE1-5may be arranged in the second direction (e.g., they direction), and each of the first detection electrodes IE1-1through IE1-5may extend in the first direction (e.g., the x direction). The second detection electrodes IE2-1through IE2-4may be arranged in the first direction (e.g., the x direction), and each of the second detection electrodes IE2-1through IE2-4may extend in the second direction (e.g., the y direction). The first detection electrodes IE1-1through IE1-5include first sensors SP1, respectively, and first sensor connectors CP1, respectively. The second detection electrodes IE2-1through IE1-4include second sensors SP2, respectively, and second sensor connectors CP2, respectively. Two first sensors SP1on both ends of a first detection electrode from among the first sensors SP1may have a smaller size than a first sensor SP1of the first detection electrode (e.g., a size that is about ½ of the size of the first sensor SP1of the first detection electrode). Two second sensors SP2on both ends of a second detection electrode from among the second sensors SP2may have a smaller size than a second sensor SP2of the second detection electrode (e.g., a size that is about ½ of the size of the second sensor SP2of the second detection electrode). FIG.6illustrates the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4according to some embodiments, but the shape thereof is not limited. According to some embodiments, each of the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4may have a shape (e.g., a bar shape) in which a sensor and a sensor connector are not distinguished from each other.FIG.6illustrates the first sensors SP1and the second sensors SP2each having a diamond shape, but the disclosure is not limited thereto. Each of the first sensors SP1and the second sensors SP2may have any of other polygonal shapes. The first sensors SP1within one first detection electrode are arranged in the first direction (e.g., the x direction), and the second sensors SP2within one second detection electrode are arranged in the second direction (e.g., the y direction). Each of the first sensor connectors CP1connects respective adjacent ones of the first sensors SP1to each other, and each of the second sensor connectors CP2connects respective adjacent ones of the second sensors SP2to each other. The first signal lines SL1-1through SL1-5are respectively connected to one respective end of the first detection electrodes IE1-1through IE1-5. The second signal lines SL2-1through SL2-4are connected to both ends of the second detection electrodes IE2-1through IE2-4, respectively. According to other embodiments, the first signal lines SL1-1through SL1-5may be respectively connected to both ends of the first detection electrodes IE1-1through IE1-5. According to other embodiments, the second signal lines SL2-1through SL2-4may be connected to a single respective end of the second detection electrodes IE2-1through IE2-4, respectively. The first signal lines SL1-1through SL1-5and the second signal lines SL2-1through SL2-4may be connected to pads PD. The pads PD may be arranged in a pad area PDA. According to some embodiments, locations of the first signal lines SL1-1through SL1-5may be interchanged with those of the second signal lines SL2-1through SL2-4. For example, in contrast withFIG.6, the first signal lines SL1-1through SL1-5may be arranged on the left side, and the second signal lines SL2-1through SL2-4may be arranged on the right side. Referring toFIGS.6and7, each of the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4may have a mesh shape. Because each of the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4has a mesh shape, parasitic capacitance between the first and second detection electrodes IE1-1through IE1-5and IE2-1through IE2-4and electrodes (for example, an opposite electrode) of the display DU ofFIG.4may be reduced. As will be described later, the first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4do not overlap light-emission areas PA-R, PA-G, and PA-B, and thus are not visually recognized by a user of the display apparatus1. The first detection electrodes IE1-1through IE1-5and the second detection electrodes IE2-1through IE2-4each having a mesh shape may include metal on which a low-temperature process may be executed, for example, silver, aluminum, copper, chromium, nickel, and titanium. Accordingly, even when the input-sensing layer TU is formed via a consecutive process, damage to an organic light-emitting diode OLED ofFIG.8Amay be reduced or prevented. Referring toFIG.7, a portion of a first sensor SP1is magnified and illustrated. The first sensor SP1does not overlap the light-emission areas PA-R, PA-G, and PA-B, and instead overlaps a non-light-emission area NPA. Each of the light-emission areas PA-R, PA-G, and PA-B may be defined the same as a light-emission area PA ofFIG.7. Mesh lines of the first sensor SP1may define a plurality of mesh holes OPR, OPG, and OPB. The mesh lines may have a three-layered structure of Ti/Al/Ti. The mesh holes OPR, OPG, and OPB may have one-to-one correspondence with the light-emission areas PA-R, PA-G, and PA-B. The light-emission areas PA-R, PA-G, and PA-B may be classified according to the colors of light beams generated by organic light-emitting diodes OLEDs.FIG.7illustrates the three light-emission areas PA-R, PA-G, and PA-B that are distinguished by the colors of light respectively emitted thereby. According to some embodiments, the light-emission areas PA-R, PA-G, and PA-B may emit red light, green light, and blue light, respectively. FIG.7illustrates the mesh holes OPR, OPG, and OPB having one-to-one correspondence with the light-emission areas PA-R, PA-G, and PA-B, but the embodiments of the present disclosure are not limited thereto. Each of the mesh holes OPR, OPG, and OPB may correspond to two or more of the light-emission areas PA-R, PA-G, and PA-B. InFIG.7, planar shapes of the mesh holes OPR, OPG, and OPB correspond to the shapes of the light-emission areas PA-R, PA-G, and PA-B and are thus illustrated as diamond shapes. However, embodiments are not limited thereto. The mesh holes OPR, OPG, and OPB may have, as their planar shapes, polygonal shapes other than the diamond shapes. For example, the mesh holes OPR, OPG, and OPB may have polygonal shapes having rounded corners. The first layer410may be arranged to cover the first sensor SP1. In other words, the first layer410may be arranged to cover a second conductive layer CL2ofFIG.8Athat forms the first sensor SP1. In the first layer410, opening patterns OPR-H, OPG-H, and OPB-H corresponding to respective display elements of the pixels Pr, Pg, and Pb, namely, to the light-emission areas PA-R, PA-G, and PA-B, may be formed. On a plane (e.g., an x-y plane), the area of the opening patterns OPR-H, OPG-H, and OPB-H may be greater than that of the light-emission areas PA-R, PA-G, and PA-B. The opening patterns OPR-H, OPG-H, and OPB-H are located in light extraction directions of the pixels Pr, Pg, and Pb, respectively, to thereby reinforce the straightness of light beams emitted by the light-emission areas PA-R, PA-G, and PA-B, and thus light extraction efficiency may be improved. FIG.7illustrates a first sensor SP1, but each of the second sensors SP2has substantially the same structure as the first sensor SP1illustrated inFIG.7. FIGS.8A through8Dare cross-sectional views taken along the line C-C′ ofFIG.7of a portion of a display area of a display apparatus according to some embodiments. Referring toFIG.8A, the substrate100may include glass or polymer resin. Examples of the polymer resin may include polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate100including polymer resin may have flexible, rollable, or bendable characteristics. The substrate100may have a multi-layered structure including a layer including the aforementioned polymer resin and an inorganic layer. The buffer layer101may be positioned on the substrate100and may reduce or prevent infiltration of a foreign material, moisture, or ambient air from below the substrate100and may provide a flat surface on the substrate100. The buffer layer101may include an inorganic material (such as oxide or nitride), an organic material, or an organic and inorganic compound, and may be a single layer or multiple layers of an inorganic material and an organic material. According to some embodiments, the buffer layer101may include silicon oxide (SiOx), silicon nitride (SiNx), or/and silicon oxynitride (SiON). A thin-film transistor TFT and a storage capacitor included at a position corresponding to the display area DA, and an organic light-emitting diode OLED electrically connected to the thin-film transistor TFT and the storage capacitor may be located on the substrate100. The thin-film transistor TFT may be on the buffer layer101. The thin film transistor TFT may include a semiconductor layer134, a gate electrode136, a source electrode138s, and a drain electrode138d. The semiconductor layer134may include at least one of amorphous silicon (a-Si), polysilicon, an oxide semiconductor, and an organic semiconductor material. According to some embodiments, the semiconductor layer134may include low temperature poly-silicon (LTPS). Because a polysilicon material has a high electron mobility (100 cm2/Vs or greater), energy consumption power is low and reliability is high, and thus may be used as a semiconductor layer of a thin-film transistor of a display apparatus. The semiconductor layer134may include a channel region131that is overlapped by the gate electrode136, and a source region132and a drain region133located on respective sides of the channel region131, and including a higher concentration of impurities than the channel region131. The impurities may include N-type impurities or P-type impurities. The source region132and the drain region133may be understood as a source electrode and a drain electrode of the thin-film transistor TFT. A gate insulating layer103may be between the semiconductor layer134and the gate electrode136. The gate insulating layer103may include silicon oxide (SiOx), silicon nitride (SiNx), or/and silicon oxynitride (SiON), and may be a single layer or multiple layers. An interlayer insulating layer107may be on the gate electrode136. The interlayer insulating layer107may include silicon oxide (SiOx), silicon nitride (SiNx), or/and silicon oxynitride (SiON), and may be a single layer or multiple layers. The thin film transistor TFT may include the source electrode138sand the drain electrode138drespectively connected to the source region132and the drain region133of the semiconductor layer134. The source electrode138sand the drain electrode138dmay be electrically connected to the source region132and the drain region133of the semiconductor layer134, respectively, via a contact hole that penetrates through the gate insulating layer103and the interlayer insulating layer107. The source electrode138sand the drain electrode138dmay include aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a single layer or as a multi-layer. According to some embodiments, the source electrode138sand the drain electrode138dmay have a multi-layer structure, such as Ti/Al/Ti or TiN/Al/Ti. In other embodiments, the data line DL ofFIG.4and the driving voltage line PL ofFIG.4may be formed on the same layer as the source electrode138sand the drain electrode138d, and may include the same material as the source electrode138sand the drain electrode138d. According to some embodiments, the thin-film transistor TFT may be covered by a protection layer109. The protection layer109may reduce or prevent exposure of a wire including metal that may be damaged by an etchant, like aluminum, to an etching environment occurring during the manufacture of the display apparatus. The protection layer109may extend to the peripheral area NDA. In some cases, the protection layer109may be omitted. A planarization layer111that planarizes an upper surface of the thin-film transistor TFT may be arranged on the protection layer109. An upper surface on which a pixel electrode210is to be arranged may be planarized by the planarization layer111. The planarization layer111may include an organic insulative material and may be a single layer or multiple layers. The pixel electrode210is on the planarization layer111. The pixel electrode210may be a (semi) light-transmissive electrode or a reflective electrode. According to some embodiments, the pixel electrode210may include a reflection layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflection layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). According to some embodiments, the pixel electrode210may have a stack structure of ITO/Ag/ITO. The pixel-defining layer112may be on the pixel electrode210, and the pixel-defining layer112may have an opening corresponding to each (sub)pixel. The pixel-defining layer112may define a light-emission area PA-G by including an opening pattern OPG-H via which at least a center portion of the pixel electrode210is exposed. The pixel-defining layer112may reduce or prevent the likelihood of an arc or the like occurring between an edge of the pixel electrode210and the opposite electrode230by increasing a distance between the edge of the pixel electrode210and the opposite electrode230. The pixel-defining layer112may include an organic material, for example, polyimide or hexamethyldisiloxane (HMDSO). According to some embodiments, a spacer113may be on the pixel-defining layer112. According to some embodiments, the spacer113may be located at the peripheral area NDA. In other embodiments, the spacer113may be located at the display area DA. The spacer113may reduce or prevent the likelihood of damage to the organic light-emitting diode OLED due to sagging of a mask in a manufacturing process of using the mask. The spacer113may include an organic insulative material and may be a single layer or multiple layers. The planarization layer111, the pixel-defining layer112, and the spacer113may include an organic insulative material. The organic insulative material may include an imide-based polymer, a commercial polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, a blend thereof, or the like. According to some embodiments, the planarization layer111may include polyimide. An intermediate layer220is between the pixel electrode210and the opposite electrode230. The intermediate layer220may include a low-molecular weight or high-molecular weight material. When the intermediate layer220includes a low-molecular weight material, the intermediate layer220may be formed by stacking a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) in a single structure or in a composite structure, and may include any of various materials, such as copper phthalocyanine (CuPc), N, N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), or tris-8-hydroxyquinoline aluminum (Alq3). These layers may be formed via vacuum deposition. When the intermediate layer220includes a high-molecular weight material, the intermediate layer220may generally have a structure including an HTL and an EML. In this case, the HTL may include poly(ethylenedioxythiophene) (PEDOT), and the EML may include a high-molecular weight material such as a polyphenylene vinylene (PPV)-based material or a polyfluorene-based material. The intermediate layer220is not limited to the above-described structure, and may have any of various other structures. For example, at least one of the layers that constitute the intermediate layer220may be integrally formed with the opposite electrode230. According to other embodiments, the intermediate layer220may include a layer that is patterned to correspond to each of a plurality of pixel electrodes210. The opposite electrode230may be arranged on the display area DA and may cover the entire display area DA. In other words, the opposite electrode230may be formed as a single body covering the entire display area DA. A portion of the opposite electrode230may extend to the peripheral area NDA. As shown inFIG.10, the opposite electrode230may extend to a partition wall (for example, a first partition wall PW1) arranged in the peripheral area NDA, and thus may electrically contact the common voltage supply line70. The thin-film encapsulation layer TFE may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. According to some embodiments, the thin-film encapsulation layer TFE may include a first inorganic encapsulation layer310, a second inorganic encapsulation layer330, and an organic encapsulation layer320therebetween. Each of the first and second inorganic encapsulation layers310and330may include one or more inorganic insulative materials. The inorganic insulative materials may include, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride. The first and second inorganic encapsulation layers310and330may be formed by chemical vapor deposition. The organic encapsulation layer320may include a polymer-based material. Examples of the polymer-based material may include an acrylic resin, an epoxy-based resin, polyimide, and polyethylene. For example, the organic encapsulation layer320may include an acrylic resin, for example, polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer320may be formed by curing a monomer or by coating a polymer. The thin-film encapsulation layer TFE may cover the entirety of the display area DA, and may extend toward the peripheral area NDA to cover a portion of the peripheral area NDA. The thin-film encapsulation layer TFE may extend to the outside of, or to be beyond, the common voltage supply line70. The input-sensing layer TU includes a first inorganic insulating layer IL1, a first conductive layer CL1on the first inorganic insulating layer IL1, a second inorganic insulating layer IL2on the first conductive layer CL1, and a second conductive layer CL2on the second inorganic insulating layer IL2. The first conductive layer CL1and the second conductive layer CL2may correspond to the first sensor SP1ofFIG.7. As described above, the first sensor SP1might not overlap the light-emission area PA-G, and instead may overlap the non-light-emission area NPA. In other embodiments, the first conductive layer CL1and the second conductive layer CL2may be electrically connected to each other via a contact hole defined in the second inorganic insulating layer IL2, in some areas. The optical functional layer OU may be on the input-sensing layer TU. The optical functional layer OU may include a first layer410that covers the second conductive layer CL2, and that is arranged on the second inorganic insulating layer IL2, and a second layer420that is arranged on the first layer410. The opening pattern OPG-H may be arranged on the first layer410to correspond to the light-emission area PA-G. A width W-H of the opening pattern OPG-H may be greater than that of the light-emission area PA-G in the same direction. This may mean that, as described above with reference toFIG.7, the area of the opening pattern OPG-H is greater than that of the light-emission area PA-G on a plane (e.g., the x-y plane, or in a plan view). The opening pattern OPR-H is located in the light extraction direction of the pixel Pg to thereby reinforce the straightness of light emitted by the light-emission area PA-G, and thus light extraction efficiency may be improved. To further improve the above-described light extraction efficiency, the second layer420having a higher refractive index than the refractive index of the first layer410may be further arranged on the first layer410. The first layer410may include an organic insulative material having a first refractive index, and the second layer420may include an organic insulative material having a second refractive index. The first refractive index of the first layer410may be in the range of about 1.3 to about 1.6. According to some embodiments, the first refractive index of the first layer410may be in the range of about 1.4 to about 1.55. The first layer410may include, for example, (ethyl)hexyl acrylate, pentafluoropropyl acrylate, poly(ethylene glycol) dimethacrylate, ethylene glycol dimethacrylate, or the like. According to some embodiments, the first layer410may include an acrylic organic material having a refractive index of about 1.5. Alternatively, the first layer410may include a material included in the organic encapsulation layer320of the thin-film encapsulation layer TFE. According to some embodiments, the first layer410may include an epoxy-based organic material, and in some cases, may also include a photocurable material. The second layer420may be a planarization layer having a second refractive index. The second refractive index of the second layer420may be in the range of about 1.65 to about 1.85. The second layer420may include, for example, polydiarylsiloxane, methyltrimethoxysilane, tetramethoxysilane, or the like. According to some embodiments, the second layer420may include an acrylic and/or siloxane-based organic material having a refractive index of about 1.6. According to other embodiments, the second layer420may include dispersed particles to have a high refractive index. In the second layer420, metal oxide particles, for example, zinc oxide (ZnOx), titanium oxide (TiO2), zirconium oxide (ZrO2), or barium titanate (BaTiO3), may be dispersed therein. The anti-reflection layer PU may be arranged on the optical functional layer OU, as shown inFIG.8B. The anti-reflection layer PU may be attached onto the optical functional layer OU by an optically clear adhesion member OCA. According to other embodiments, the color filter layer CU may be arranged on the input-sensing layer TU as shown inFIG.8C, and the optical functional layer OU may be arranged on the color filter layer CU. The color filter layer CU may include a base layer510, a light-shielding layer520, color filters530, and an overcoat layer540. According to some embodiments, the base layer510may be omitted. The color filters530may be arranged by taking into account the colors of light beams respectively emitted by the pixels of the display panel DP. For example, each color filter530may have a red, green, or blue color according to the color of light emitted by the organic light-emitting diode OLED. The light-shielding layer520may include a pigment or dye having a black color in an insulating material (e.g., an organic insulating material). The light-shielding layer520may be, for example, a black matrix. The overcoat layer540may be between the color filters530and the input-sensing layer TU, may include an organic material, such as resin, and may have a light transmission property. According to other embodiments, to maximize an effect of the color filter layer CU, the pixel-defining layer112and/or the spacer113may include a black light-shielding material, as shown inFIG.8D. In this case, the pixel-defining layer112and/or the spacer113may be included as, for example, a back matrix. The light-shielding layer520may be arranged to correspond to the non-light-emission area NPA, thereby reducing or preventing color mixture due to light leakage between pixels P. Furthermore, the pixel-defining layer112and/or the spacer113may further perform a light-shielding function along with the light-shielding layer520, thereby increasing or maximizing an effect of the color filter layer CU. The anti-reflection layer PU ofFIG.8Amay be omitted in some embodiments. According to other embodiments, a color filter layer CU′ may be arranged on the input-sensing layer TU, as shown inFIG.8E, and the color filter layer CU′ may include a light-shielding layer520′ and color filters530′. The light-shielding layer520′ may be located in the non-light-emission area NPA, and may surround the light-emission area PA-G. According to some embodiments, the light-shielding layer520′ may passivate a touch electrode of the input-sensing layer TU. For example, as shown inFIG.8E, the second conductive layer CL2of the input-sensing layer TU including the touch electrode may be overlapped by the light-shielding layer520′ and may be covered by the light-shielding layer520′. FIG.9is a magnified plan view of a portion D ofFIG.6,FIG.10is a magnified plan view of a portion E ofFIG.4, andFIG.11Ais a cross-sectional view of the portion E taken along the line F-F′ ofFIG.10.FIGS.11B,11C, and12are modifications ofFIG.10. FIG.9illustrates a structure corresponding to the location of the portion D of the input-sensing layer TU, but also illustrates the display layer DU below the input-sensing layer TU in addition to the input-sensing layer TU. Referring toFIG.9, as described above, detection electrodes may be located in the display area DA.FIG.9illustrates some detection electrodes located at a right-lower corner of the display area DA, for example, the first detection electrode IE1-5and the second detection electrode IE2-1. Signal lines may be located outside the display area DA, namely, in the peripheral area NDA.FIG.9illustrates some signal lines located at the right-lower corner of the display area DA, for example, the first signal lines SL1-1through SL1-5. An electrostatic prevention line ESL may be located outside the first signal lines SL1-1through SL1-5. The electrostatic prevention line ESL may be arranged outside the first signal lines SL1-1through SL1-5and the second signal lines SL2-1through SL2-4, namely, on the outermost edge of the input-sensing layer TU. The electrostatic prevention line ESL may be included such that no signals are applied thereto, but instead a uniform constant voltage flows. A shield layer90may be located outside the electrostatic prevention line ESL. The shield layer90may be arranged on the same layer as the pixel electrode210ofFIG.8A, and may include the same material as the material included in the pixel electrode210. A driving circuit, for example, the second scan driving circuit30, may be below the shield layer90. The shield layer90may include a plurality of through holes90H. The planarization layer111ofFIG.8Amay be between the second scan driving circuit30and the shield layer90, and outgas generated by the planarization layer111during the manufacture of the display apparatus may be exhausted via the plurality of through holes90H. An anti-reflection layer92may be arranged above the shield layer90. In other embodiments, the planarization layer111located below the shield layer90may include a valley structure obtained by removing a portion of the planarization layer111. The valley structure may block introduction of impurities into the display area DA by blocking external moisture permeation via the planarization layer111corresponding to an organic insulating material. The valley structure may also reduce or prevent overflow of the organic encapsulation layer320ofFIG.8Aof the thin-film encapsulation layer TFE ofFIG.8A. The anti-reflection layer92may overlap the valley structure, and may reflect external light to reduce or prevent visibility of the valley structure from the outside. For example, the anti-reflection layer92may include the same material as the material included in the detection electrodes of the input-sensing layer TU. According to some embodiments, a crack-sensing line80may be outside the shield layer90. According to some embodiments, when the display apparatus1includes a transmission unit that penetrates through the substrate100in the display area DA and/or the peripheral area NDA, the crack-sensing line80may sense a crack of the layers around the transmission unit. According to other embodiments, when the display apparatus1includes no transmission units, the crack-sensing line80may be omitted. A first partition wall PW1and a second partition wall PW2may be located outside the crack-sensing line80. A first valley portion VP1and a second valley portion VP2may be located outside the first partition wall PW1and the second partition wall PW2. The first partition wall PW1, the second partition wall PW2, the first valley portion VP1, and the second valley portion VP2will be described in detail with reference toFIG.10and other figures to be described later. Referring toFIGS.10and11A, the peripheral area NDA is on one side of (e.g., outside of) the display area DA. In the peripheral area NDA, an auxiliary partition wall PW0, the first partition wall PW1, and the second partition wall PW2may be arranged in order adjacent to the display area DA. The auxiliary partition wall PW0, the first partition wall PW1, and the second partition wall PW2may be spaced apart from one another (e.g., by a predetermined distance). InFIG.11A, the first partition wall PW1and the second partition wall PW2may include portions111P1and111P2of the planarization layer111, portions112P1and112P2of the pixel-defining layer112, and portions113P1and113P2of the spacer113, respectively. However, the embodiments of the present disclosure are not limited thereto. The auxiliary partition wall PW0may be a single layer and may be located on the planarization layer111. In this case, the auxiliary partition wall PW0may include the same material as the pixel-defining layer112or the spacer113. According to other embodiments, the auxiliary partition wall PW0may be on the interlayer insulating layer107. In this case, the auxiliary partition wall PW0may include the same material as the planarization layer111. The first partition wall PW1and the second partition wall PW2are arranged to surround the display area DA, and may reduce or prevent overflow of the organic encapsulation layer320of the thin-film encapsulation layer TFE to the outside of the substrate100. Accordingly, the organic encapsulation layer320may contact, or may be near, an inner surface of the first partition wall PW1that faces the display area DA. In this case, the organic encapsulation layer320being near the inner surface of the first partition wall PW1may be understood as the first inorganic encapsulation layer310being between the organic encapsulation layer320and the first partition wall PW1, the organic encapsulation layer320being in direct contact with the first inorganic encapsulation layer310. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may be on the first and second partition walls PW1and PW2and may extend toward an edge of the substrate100. The valley portion VP may be located outside the second partition wall PW2. According to some embodiments, the valley portion VP may include the first valley portion VP1and the second valley portion VP2. The first valley portion VP1and the second valley portion VP2may be formed by removing at least a portion of the first layer410. The first valley portion VP1and the second valley portion VP2may be included by forming a hole (or a groove) that penetrates through at least a portion of the first layer410, or may be included by forming a recess that does not completely penetrate through the first layer410, but is formed in the first layer410in a direction toward the substrate100. The first valley portion VP1may be closer to the display area DA than the second valley portion VP2. The first valley portion VP1and the second valley portion VP2may control spreading of the second layer420having mobility upon film formation. According to some embodiments, the first valley portion VP1may include a plurality of first holes H1. In other words, it may be understood that the plurality of first holes H1form at least one row and at least one column, and that this matrix of the plurality of first holes H1forms the first valley portion VP1. InFIG.10, the second valley portion VP2has an integrally connected shape in contrast with the first valley portion VP1. However, embodiments of the present disclosure are not limited thereto. Various embodiments regarding the shapes of the first valley portion VP1and the second valley portion VP2will be described in detail later with reference toFIGS.14through21. The second layer420may be included to cover the entirety of the display area DA, and may partially extend to the peripheral area NDA. The second layer420may extend to the second partition wall PW2to cover the auxiliary partition wall PW0, the first partition wall PW1, and the second partition wall PW2, and might not overlap the first valley portion VP1. Accordingly, an end420eof the second layer420may be spaced apart from the first valley portion VP1(e.g., by a predetermined distance), and may be located between the second partition wall PW2and the first valley portion VP1. InFIG.10and its subsequent drawings, the end420eof the second layer420is spaced apart from the first valley portion VP1(e.g., by a predetermined distance). However, in some cases, at least a portion of the second layer420may fill at least some of the plurality of first holes H1of the first valley portion VP1and/or at least some of the second valley portion VP2. Even in this case, the second layer420may be controlled by the first valley portion VP1(or the second valley portion VP2). This may mean that a portion of, or the entirety of, the second layer420may fill a portion of, or the entirety of, the first valley portion VP1(or the second valley portion VP2), but, as a result, does not overflow (e.g., does not extend past) the first valley portion VP1(or the second valley portion VP2). An end TFEe of the thin-film encapsulation layer TFE may be between an end100eof the substrate100and the end410eof the first layer410. The end TFEe of the thin-film encapsulation layer TFE may mean, or may correspond to, an end of the first inorganic encapsulation layer310and/or the second inorganic encapsulation layer330. Referring toFIG.11A, the first valley portion VP1and the second valley portion VP2may penetrate through the first layer410, and the first valley portion VP1may include the plurality of first holes H1. The first valley portion VP1and the second valley portion VP2may expose at least a portion of the second inorganic encapsulation layer330located below the first layer410. A width W-VP1of the first valley portion VP1in one direction (e.g., the x direction) may be greater than a width W-VP2of the second valley portion VP2in the same direction (e.g., the x direction). The first valley portion VP1may be a main valley portion for controlling spreading of the second layer420, and the second valley portion VP2may be an auxiliary valley portion prepared for a case when the second layer420spreads over the first valley portion VP1. Accordingly, due to the width W-VP1of the first valley portion VP1being greater than the width W-VP2of the second valley portion VP2, a function as a main valley portion may be effectively achieved. According to some embodiments, a depth dt of each of the plurality of first holes H1may be, for example, about 2 μm or more (e.g., the first layer410may have a thickness of about 2 μm or more). However, when the thickness of the first layer410is less than or equal to about 2 μm, the depth dt of each of the plurality of first holes H1may be adjusted by forming a hole or a recess in the first inorganic encapsulation layer310and/or the second inorganic encapsulation layer330located below the first layer410. Substantially, for the first valley portion VP1to control spreading of the second layer420, each of the plurality of first holes H1may have a depth (e.g., a predetermined depth, or a depth that is greater than the predetermined depth). When the depth dt of each of the plurality of first holes H1is less than about 2 μm, it is difficult for the first valley portion VP1to effectively control spreading of the second layer420. As shown inFIG.11B, the anti-reflection layer PU may be arranged over the display panel DP ofFIG.11A. The anti-reflection layer PU may be attached to the display panel DP therebelow by the optically clear adhesion member OCA. The anti-reflection layer PU may be, for example, a polarizer, and may extend to the second valley portion VP2. As described above with reference toFIG.10, an end PUe of the anti-reflection layer PU may overlap the second valley portion VP2. However, embodiments are not limited thereto, and, for example, the anti-reflection layer PU may overlap the display area DA while the end PUe of the anti-reflection layer PU does not extend to the second valley portion VP2. In this case, it is enough for the end PUe of the anti-reflection layer PU to be located at a boundary between the display area DA and the peripheral area NDA, or on the peripheral area NDA, and various modifications are possible. According to some embodiments, the end PUe of the anti-reflection layer PU may be between the display area DA and the second valley portion VP2. According to other embodiments, as described above with reference toFIG.8D, the color filter layer CU may be over the display panel DP ofFIG.11A.FIG.11Cmay correspond to the peripheral area NDA extending from the display area DA ofFIG.8D. When the pixel-defining layer112and/or the spacer113are included as black matrices, as described above with reference toFIG.8D, the auxiliary partition wall PW0, the first partition wall PW1, and the second partition wall PW2arranged in the peripheral area NDA may be included as black matrices. In this case, a light-shielding material included in the pixel-defining layer112may flow to the lower planarization layer111, and thus, at least a portion of the planarization layer111may become a black matrix, as shown inFIG.11C. As shown inFIG.12, the display apparatus1according to some embodiments may include only the first valley portion VP1. In other words, as shown inFIG.12, the second valley portion VP2may be omitted, and spreading of the second layer420may be controlled by only the first valley portion VP1. The shape of the first valley portion VP1inFIG.12is the same as the shape of the first valley portion VP1described above with reference toFIG.10. However, inFIG.12, an arrangement of the plurality of first holes H1may be changed. Referring toFIGS.11A through12, the second layer420does not overlap the first valley portion VP1. A surface of the first layer410having the plurality of first holes H1thereon has a hydrophobic property due to a low surface energy (surface tension). This phenomenon is referred to as a lotus effect. Because the surface of the first layer410has a hydrophobic property due to the lotus effect, the second layer420may be controlled to stop spreading in an area before reaching the first valley portion VP1, and without overflowing to the first valley portion VP1. To increase or maximize the lotus effect, the sizes and a configuration of the plurality of first holes H1constituting the first valley portion VP1act as important factors. The size of each of the plurality of first holes H1may suitably be a relatively minute size that is less than or equal to a given size (e.g., a predetermined size), and the plurality of first holes H1may be arranged to have regularity. Various embodiments regarding the sizes and a configuration of the plurality of first holes H1will now be described with reference toFIGS.13through21. FIG.13is a magnified plan view of a portion of the display area and the first valley portion ofFIG.10,FIG.14is a cross-sectional view of a portion of a manufacturing process corresponding to a cross-section taken along the line G-G′ ofFIG.13, andFIG.15is a magnified plan view of a portion ofFIG.13. Referring toFIG.13, the pixels Pr, Pg, and Pb may be arranged on the display area DA, and the first layer410may be arranged over the pixels Pr, Pg, and Pb. The first layer410may be arranged on the entire surface of the display area DA, and may extend to the peripheral area NDA. The first layer410may include opening patterns OPR-H, OPG-H, and OPB-H in correspondence to the display area DA, and may include the first valley portion VP1defined as the plurality of first holes H1in correspondence to the peripheral area NDA. As described above, the opening patterns OPR-H, OPG-H, and OPB-H may correspond to the pixels Pr, Pg, and Pb, respectively. In the display area DA, the second layer420may cover the first layer410, and a portion of the second layer420may extend to the peripheral area NDA. The end420eof the second layer420may be spaced apart from the first valley portion VP1(e.g., by a predetermined distance). In other words, the second layer420might not overlap the first valley portion VP1. The plurality of first holes H1may be arranged to form at least one row in one direction (e.g., they direction), and at least one column in another direction (e.g., the x direction) that crosses the one direction (e.g., the y direction). Referring toFIG.15, the plurality of first holes H1may include a plurality of first sub-holes SH1, a plurality of second sub-holes SH2, and a plurality of third sub-holes SH3arranged in the one direction (e.g., they direction). The plurality of first sub-holes SH1, the plurality of second sub-holes SH2, and the plurality of third sub-holes SH3may be arranged to form a first row L1, a second row L2, and a third row L3, respectively. The plurality of first sub-holes SH1of the first row L1, the plurality of second sub-holes SH2of the second row L2, and the plurality of third sub-holes SH3of the third row L3may be spaced apart from one another in the other direction (e.g., the x direction). According to some embodiments, the plurality of first sub-holes SH1may be spaced apart from one another at intervals of a first distance d1in a first direction (e.g., the y direction), and the plurality of second sub-holes SH2(e.g., respective top corners thereof) may be shifted from the plurality of first sub-holes SH1(e.g., respective side corners thereof) by half of the first distance d1in the first direction (e.g., the y direction). That is, the second sub-holes SH2may be centered between respective adjacent ones of the first sub-holes SH1with respect to the first direction while being offset from the first sub-holes SH1in a second direction (e.g., the x direction). The plurality of second sub-holes SH2may correspond to areas corresponding to the distances by which the plurality of first sub-holes SH1are spaced apart from one another (e.g., the second sub-holes SH2may be spaced apart from one another at intervals of the first distance d1in the first direction). The plurality of third sub-holes SH3may be arranged in the same manner as the plurality of first sub-holes SH1. In other words, given that the first direction (e.g., the y direction) is a row direction and the second direction (e.g., the x direction) is a column direction, the plurality of first sub-holes SH1and the plurality of third sub-holes SH3are arranged in the same columns (for example, a first column R1and a second column R2), but the plurality of second sub-holes SH2may be located between the columns (for example, between the first column R1and the second column R2). As the plurality of second sub-holes SH2is located by being shifted by ½ of the first distance d1between the plurality of first sub-holes SH1as described above, a control area of the second layer420, which spreads with mobility toward the plurality of first sub-holes SH1, may increase, and thus spreading of the second layer420may be more effectively controlled. The second layer420may spread in a direction toward the first valley portion VP1(e.g., a −x direction), may be primarily controlled by the plurality of first sub-holes SH1, and may be secondarily controlled by the plurality of second sub-holes SH2. According to some embodiments, the end420eof the second layer420may be curved in accordance with the shape in which the plurality of first sub-holes SH1and the plurality of second sub-holes SH2are arranged as inFIG.15. Each of the plurality of first holes H1may have any of various shapes. Each of the plurality of first holes H1may have various shapes, for example, a circle, an oval, a polygon, and a corner-rounded polygon. According to some embodiments, each of the plurality of first holes H1may have a diamond shape. In other words, the plurality of first holes H1may have a rectangular shape, but also may have a diamond shape. The diamond shape refers to at least one vertex of each of the plurality of first holes H1facing the end420eof the second layer420. Accordingly, because portions of the plurality of first holes H1corresponding to vertexes (instead of edges corresponding to sides) are arranged to face the end420eof the second layer420, a pressure at the end420eof the second layer420may be dispersed, and thus spreading of the second layer420may be more effectively controlled. When the size of each of the plurality of first holes H1increases (e.g., to a predetermined size or greater), the lotus effect may degrade, and thus spreading of the second layer420may be less effectively controlled and may overflow to the first valley portion VP1. Thus, according to some embodiments, given that each of the plurality of first holes H1has a diamond shape, two sides facing each other may have a first width w1therebetween. For example, the first width w1may be about 1 μm to about 10 μm. In each of the plurality of first holes H1, a second width w2between two vertexes facing each other may be about 1 μm to about 15 μm. For example, if the first width w1is about 10 μm, the second width w2may be about 14.14 μm. When a distance between the plurality of first holes H1is widened (e.g., to a predetermined distance or greater) the lotus effect may degrade. Thus, according to some embodiments, the plurality of first holes H1may be spaced apart from one another at intervals of the first distance d1in the first direction (e.g., the y direction). For example, the first distance d1may be about 1 μm to about 15 μm. According to some embodiments, the first width w1of each of the plurality of first holes H1may be less than the first distance d1between the plurality of first holes H1. The plurality of first holes H1may be spaced apart from one another by a second distance d2in a second direction (e.g., the x direction). In detail, a first sub-hole SH1and a third sub-hole SH3aligned in the first row R1may be spaced apart from each other by the second distance d2. For example, the second distance d2may be about 1 μm to about 15 μm. The plurality of first holes H1may be spaced apart from one another by a third distance d3in a third direction (e.g., a w direction). The third direction (e.g., the w direction) may cross the first direction (e.g., the y direction) and the second direction (e.g., the x direction) at the same time, and may be, for example, a diagonal direction. For example, the third distance d3may be about 1 μm to about 10 μm. FIG.14illustrates both the display area DA and the peripheral area NDA with reference toFIG.12. To focus on and describe the opening patterns OPG-H and the plurality of first holes H1formed in the first layer410and the second layer420arranged on the first layer410,FIG.14omits illustrating the other components. To correspond to the display area DA, a display element, namely, an organic light-emitting diode OLED, is arranged on the substrate100. Organic light-emitting diodes OLED each including a pixel Pg that emits green light are illustrated. The first layer410is over the organic light-emitting diodes OLED, and the first layer410may include opening patterns OPG-H in correspondence to the organic light-emitting diodes OLED, respectively. The first layer410may extend to the peripheral area NDA, and may include the first valley portion VP1having the plurality of first holes H1in the peripheral area NDA. According to some embodiments, a width W-H1of each of the plurality of first holes H1may be less than or equal to a width W-IL2of each of the opening patterns OPG-H. Referring toFIG.7or13described above, the pixels Pr, Pg, and Pb may include first pixels Pr emitting red light, second pixels Pg emitting green light, and third pixels Pb emitting blue light. The area of each second pixel Pg emitting green light may be less than that of each first pixel Pr or each third pixel Pb. Accordingly, the opening patterns OPR-H, OPG-H, and OPB-H have sizes to correspond to the sizes of the pixels Pr, Pg, and Pb, respectively, and the opening pattern OPG-H corresponding to the second pixel Pg emitting green light may have the smallest size. The width W-H1of each of the plurality of first holes H1may be less than or equal to the width W-IL2of the opening pattern OPG-H corresponding to the second pixel Pg from among the opening patterns OPR-H, OPG-H, and OPB-H. The second layer420may be on the first layer410, and may be formed using the inkjet method as inFIG.14. In other words, the second layer420may be formed by depositing an ink jet material I-J directly onto the first layer410. In the display apparatus1according to some embodiments, the first valley portion VP1controls spreading of the second layer420, thereby reducing or preventing overflow of the second layer420to the edge of the substrate100, and thus a defect rate when an inkjet process is used may be reduced or minimized. FIGS.16through21are plan views schematically illustrating a portion of a display apparatus according to some embodiments.FIGS.16through21illustrate modifications of the example shown inFIG.13. Referring toFIG.16, the first layer410may further include the second valley portion VP2outside the first valley portion VP1.FIG.16may correspond toFIGS.10and11A. The structure ofFIG.16is the same as that ofFIGS.10and11A, and thus a redundant description thereof will be omitted. FIG.17is similar toFIG.16, but is different therefrom in that the second valley portion VP2includes the plurality of second holes H2in the same manner as the first valley portion VP1. A configuration of, and respective shapes of, the plurality of second holes H2constituting the second valley portion VP2may be the same as those of the first valley portion VP1, and thus a redundant description thereof will be omitted. Referring toFIG.18, the first layer410includes the first valley portion VP1, and the first valley portion VP1may include the plurality of first holes H1and a first auxiliary valley SV1. The first auxiliary valley SV1may be continuously formed along a first direction (e.g., they direction) that is substantially parallel to the end420eof the second layer420, with the plurality of first holes H1being between the first auxiliary valley SV1and the end420eof the second layer420. A width W-VP11of a plurality of first holes H1in a second direction (e.g., the x direction) may be equal to or greater than a width (e.g., average width, maximum width, or minimum width) W-VP12of the first auxiliary valley SV1in the second direction (e.g., the x direction). Because the first auxiliary valley SV1substantially plays an auxiliary role in controlling spreading of the second layer420, the plurality of first holes H1playing a main role, or lead role, of controlling spreading of the second layer420may have a wider area than the first auxiliary valley SV1. In the first auxiliary valley SV1, a first end SV1athereof, which is adjacent to the plurality of first holes H1, may be curved, or may have a sawtooth shape, along the configuration of the plurality of first holes H1.FIG.17illustrates the first end SV1ahaving an irregular shape in accordance with the shape of the plurality of first holes H1, but embodiments are not limited thereto. A second end SV1bof the first auxiliary valley SV1, which is opposite to the first end SV1a, may be included as a straight line. Because the first end SV1ais in a direction toward the second layer420, if the second layer420overflows to the plurality of first holes H1, the shape of the first end SV1aof the first auxiliary valley SV1may distribute the pressure of the end420eof the second layer420. According to other embodiments, as inFIG.19, both the first end SV1aand the second end SV1bof the first auxiliary valley SV1may be included as straight lines. FIGS.19and20are similar toFIG.18, but are different therefrom in that the second valley portion VP2is further included outside the first valley portion VP1. A configuration and a shape of the second valley portion VP2are the same as the above-described configuration, and the above-described shape of the second valley portion VP2, and thus a redundant description thereof will be omitted. FIG.20is similar toFIG.18, but is different therefrom in that a second valley portion VP2having the same shape as the first valley portion VP1is further included. A configuration and a shape of the second valley portion VP2are the same as the above-described configuration, and the above-described shape of the second valley portion VP2, and thus a redundant description thereof will be omitted. Although only a display apparatus has been described above, embodiments are not limited thereto. For example, a method of manufacturing a display apparatus by using such a display apparatus also belongs to the scope of the disclosure. According to some embodiments as described above, a display apparatus having an improved reliability by effectively controlling spreading of an organic layer may be realized. Of course, the scope of the disclosure is not limited thereto. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of aspects of the disclosed embodiments should typically be considered as available for other similar aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, with functional equivalent thereof to be include therein. | 91,318 |
11943957 | DETAILED DESCRIPTION OF THE EMBODIMENTS Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, some embodiments are merely described below, by referring to the figures, to explain aspects of the description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” Because the disclosure may have diverse modified embodiments, some embodiments are illustrated in the drawings and are described in the detailed description. Effects and characteristics of the disclosure, and a method of accomplishing these will be apparent when referring to embodiments described with reference to the drawings. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. One or more embodiments of the disclosure will be described below in more detail with reference to the accompanying drawings. Those components that are the same are rendered the same reference numeral regardless of the figure number, and redundant explanations may be omitted. It will be understood that although the terms “first,” “second,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. An expression used in the singular form encompasses the expression of the plural form, unless it has a clearly different meaning in the context. It will be further understood that the terms “comprises,” “comprising,” “include,” and “including” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements. It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, area, or element, it may be directly or indirectly formed on the other layer, region, or element. For example, for example, intervening layers, regions, or elements may be present. It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, it may be directly or indirectly connected to the other layer, region, or component. For example, for example, intervening layers, regions, or components may be present. In the following embodiments, it will be understood that when a layer, region, or element is referred to as being “electrically connected to” or “electrically coupled to” another layer, region, and element, it may be directly or indirectly electrically connected or coupled to the other layer, region, or element. For example, for example, intervening layers, regions, or elements may be present. The x-axis, the y-axis, and the z-axis are not limited to three axes of the rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto. Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and should not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification. Hereinafter, although an organic light-emitting display apparatus is described as an example of a display apparatus1according to an embodiment, a display apparatus according to the disclosure is not limited thereto. In another embodiment, the display apparatus1according to the disclosure may include an inorganic light-emitting display apparatus, an inorganic electroluminescence (EL) display apparatus, or a quantum dot light-emitting display apparatus. For example, an emission layer of a display element provided in the display apparatus1may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot. FIG.1is a plan view schematically illustrating a display apparatus1according to an embodiment. Referring toFIG.1, the display apparatus1may include a display area DA, and a peripheral area NDA outside the display area DA. The display area DA may include a first area DA1defined as an auxiliary display area or a component area, and a second area DA2defined as a main display area at least partially surrounding the first area DA1. For example, the first area DA1and the second area DA2may display images individually or together. The peripheral area NDA may be a non-display area in which no display elements are arranged. The display area DA may be entirely surrounded by the peripheral area NDA. FIG.1illustrates that one first area DA1is located in the second area DA2. In another embodiment, the display apparatus1may include at least two first areas DA1, and the at least two first areas DA1may have different shapes and sizes. When seen in a direction substantially perpendicular to the upper surface of the display apparatus1(or in a plan view), the first area DA1may have various shapes. For example, the first area DA1may have a polygonal shape such as a quadrangular, hexagonal, or octagonal shape, a circular shape, an oval shape, a stellate shape, or a diamond shape. When seen in a direction substantially perpendicular to the upper surface of the display apparatus1,FIG.1illustrates that the first area DA1is arranged in the upper center (+y direction) of the display area DA including corners each having a substantially rounded rectangular shape, but the first area DA1may also be arranged at a side of the display area DA, for example, the upper right or upper left of the display area DA. The first area DA1may include a pixel area PA and a transmission area TA. Pixel areas PA and transmission areas TA may be provided. The pixel areas PA and the transmission areas TA may be alternately arranged. Pixels may be arranged in the pixel area PA, and pixels are not arranged in the transmission area TA. The transmission area TA may be an area in which the arrangement of elements constituting a display layer DSL (seeFIG.2) is minimized. The transmission area TA may transmit light through a substrate100. First pixels P1may be arranged in the pixel area PA of the first area DA1. Each of the first pixels P1refers to a sub-pixel and may be implemented by a display element such as an organic light-emitting diode OLED. The first pixel P1may emit, for example, red, green, blue, or white light. The transmission area TA may surround the first pixels P1. As another example, the transmission areas TA may be alternatively arranged with the first pixels P1. The first area DA1may include the transmission area TA, and thus the resolution of the first area DA1may be lower than that of the second area DA2. For example, the resolution of the first area DA1may be about ½, ⅜, ⅓, ¼, 2/9, ⅛, 1/9, or 1/16 of that of the second area DA2. For example, the resolution of the first area DA1may be about 200 ppi or about 100 ppi, and the resolution of the second area DA2may be about 400 ppi or greater. Second pixels P2may be arranged in the second area DA2. Each of the second pixels P2refers to a sub-pixel and may be implemented by a display element such as an organic light-emitting diode OLED. The second pixel P2may emit, for example, red, green, blue, or white light. The display apparatus1may provide images through the first area DA1and the second area DA2. As described below with reference toFIG.2, a component20, which is an electronic element, may be arranged below a display panel10in correspondence with the first area DA1. In case that light is transmitted through the first area DA1, the display apparatus1according to an embodiment may have a light transmittance of about 10% or greater. Specifically, the light transmittance may be about 40% or greater, about 25% or greater, about 50% or greater, about 85% or greater, or about 90% or greater. FIG.2is a cross-sectional view schematically illustrating a portion of the display apparatus1, according to an embodiment. Referring toFIG.2, the display apparatus1may include the display panel10, and the component20overlapping the display panel10. A cover window (not illustrated) may be further arranged above the display panel10to protect the display panel10. The display panel10may include the substrate100, the display layer DSL, a thin-film encapsulation layer300, and a panel protection layer PPL arranged below the substrate100. Although not illustrated, a touch sensing layer and/or a polarization layer may be further located on the thin-film encapsulation layer300. The substrate100may include an insulating material such as glass, quartz, and a polymer resin. The substrate100may be a rigid or flexible substrate that is bendable, foldable, or rollable. In an embodiment, the substrate100may have a multilayer structure and may include at least one organic layer and at least one inorganic layer. The display layer DSL may include a pixel circuit layer PCL including a thin-film transistor TFT, a display element layer DEL including an organic light-emitting diode OLED as a display element, and a sealing member such as the thin-film encapsulation layer300or a sealing substrate (not illustrated). The first and second pixels P1and P2including the thin-film transistor TFT and the organic light-emitting diode OLED electrically connected thereto may be arranged in the display layer DSL corresponding to the display area DA. The first pixel P1including the thin-film transistor TFT and the organic light-emitting diode OLED electrically connected thereto may be arranged in the first area DA1. AlthoughFIG.2illustrates that a single first pixel P1is included in the pixel area PA, the first pixels P1may be included in each pixel area PA. The transmission area TA including no display elements may be located between the pixel areas PA of the first area DA1. The transmission area TA may be an area through which light or a signal emitted from the component20or light or a signal incident onto the component20is transmitted. At least a portion of an insulating layer IL corresponding to the transmission area TA may be removed, and other portions thereof may be arranged on the transmission area TA. As described above, the light transmittance of the transmission area TA may be improved by removing a portion of the insulating layer IL corresponding to the transmission area TA. The component20may be located in correspondence with the first area DA1. The component20may be an electronic element that uses light or sound. For example, the component20may include a sensor (e.g., an infrared sensor) configured to receive and use light, a sensor configured to output and detect light or sound to measure a distance, a sensor configured to recognize a fingerprint, a small lamp configured to output light, a speaker configured to output sound, a camera including an imaging device, and the like. In case that the component20is an electronic element that uses light, the component20may use light of various wavelength bands, such as visible light, infrared light, and ultraviolet light. For example, the component20may include a solar cell, a flash, an illumination sensor, a proximity sensor, an iris sensor, or a camera. To reduce the limiting of the function of the component20, the transmission area TA may be arranged in the first area DA1. The transmission area TA may transmit light and/or sound output from the component20to the outside or traveling from the outside toward the component20. In an embodiment, components20may be arranged in the first area DA1. The components20may have different functions. For example, the components20may include at least two components selected from a camera (or imaging device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor. A back metal layer BML may be arranged in the first area DA1. The back metal layer BML may be arranged to correspond to the pixel area PA. The back metal layer BML may prevent external light, for example, light emitted from the component20, from reaching the first pixel P1. The back metal layer BML may prevent light from being reflected or diffracted while the external light passes between lines CL. Therefore, image distortion (e.g., flare, haze, etc.) in the first area DA1may be prevented. In an embodiment, a constant voltage or a signal may be applied to the back metal layer BML to prevent damage to a pixel circuit PC (seeFIG.3) due to electrostatic discharge. In another embodiment, different voltages may be applied to back metal layers BML arranged to correspond to different pixel areas PA. The thin-film encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The thin-film encapsulation layer300may be arranged on the transmission area TA. In the embodiment, the thin-film encapsulation layer300may be used as the encapsulation member for sealing the display element layer DEL, but the disclosure is not limited thereto. For example, a sealing substrate bonded to the substrate100by a sealant or frit may be used as a member for sealing the display element layer DEL. The panel protection layer PPL may be attached to a lower portion of the substrate100to support and protect the substrate100. The panel protection layer PPL may include an opening PPL-OP corresponding to the first area DA1. The panel protection layer PPL may include the opening PPL-OP, and thus the light transmittance of the first area DA1may be improved. The panel protection layer PPL may include polyethylene terephthalate or polyimide. For example, an area of the opening PPL-OP may be less than that of the first area DA1. The cover window (not illustrated) may be arranged above the display panel10to protect the display panel10. FIG.3is an equivalent circuit diagram of the first pixel P1in the display apparatus1, according to an embodiment. Referring toFIG.3, the first pixel P1may include the pixel circuit PC connected to a driving voltage line PL, a scan line SL, and a data line DL, and the organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor Td, a switching thin-film transistor Ts, and a storage capacitor Cst. The switching thin-film transistor Ts may be electrically connected to the scan line SL and the data line DL and may be configured to transmit, to the driving thin-film transistor Td, a data signal Dm input through the data line DL according to a scan signal Sn input through the scan line SL. The storage capacitor Cst may be electrically connected to the switching thin-film transistor Ts and the driving voltage line PL and may be configured to store a voltage corresponding to a difference between a voltage received from the switching thin-film transistor Ts and a first power supply voltage (e.g., a driving voltage) ELVDD supplied to the driving voltage line PL. The driving thin-film transistor Td may be electrically connected to the driving voltage line PL and the storage capacitor Cst and may be configured to control a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a predetermined luminance according to a second power supply voltage (e.g., a common voltage) ELVSS and the driving current. FIG.3illustrates a case in which the pixel circuit PC includes two thin-film transistors and a storage capacitor, but the disclosure is not limited thereto. In another embodiment, the pixel circuit PC may include seven thin-film transistors and a storage capacitor. In another embodiment, the pixel circuit PC may include two or more storage capacitors. In an embodiment, the second pixel P2and the first pixel P1may have the same or different pixel circuit structure(s). For example, the first pixel P1may include a pixel circuit PC including two thin-film transistors and a storage capacitor, and the second pixel P2may include a pixel circuit PC including seven thin-film transistors and a storage capacitor. FIG.4is a schematic cross-sectional view schematically illustrating the portion of the first area DA1in the display apparatus1, according to an embodiment, andFIG.5is a schematic enlarged cross-sectional view of portion B ofFIG.4.FIGS.7and8are schematic cross sectional views of modifications ofFIG.4. Referring toFIG.4, a substrate100may include a polymer resin. Examples of the polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. In an embodiment, the substrate100may include at least one organic base layer including an organic material, and at least one inorganic base layer. A barrier layer111amay be arranged on the substrate100. In an embodiment, as illustrated inFIG.4, the barrier layer111amay be arranged on the entire surface of the first area DA1over the pixel area PA and the transmission area TA. In another embodiment, the barrier layer111amay not be arranged in the transmission area TA. The barrier layer111amay reduce or block penetration of foreign matter, moisture, or external air from the bottom of the substrate100and may provide a flat surface on the substrate100. The barrier layer111amay include an inorganic material such as oxide or nitride, or an organic or inorganic composite material and may have a single or multilayer structure. For example, the barrier layer111amay include silicon nitride (SiNx), silicon oxide (SiOx), and/or silicon oxynitride (SiON). The first pixel P1may correspond to the pixel area PA. AlthoughFIG.4illustrates only the stacked structure of the first pixel P1in the first area DA1, the stacked structure of the second pixel P2in the second area DA2may also be substantially identical to the stacked structure illustrated inFIG.4. However, in an embodiment, the back metal layer BML may not be arranged below the second pixel P2in the second area DA2. The pixel area PA may include insulating layers, a thin-film transistor TFT, a storage capacitor Cst, and an organic light-emitting diode OLED. The transmission area TA may include a transmission hole HT that is an opening formed by removing some of the insulating layers to secure transmittance. The back metal layer BML may be arranged below or under the thin-film transistor TFT of the first pixel P1and may overlap the thin-film transistor TFT. As illustrated inFIG.4, after the barrier layer111ais formed on the substrate100, the back metal layer BML may be arranged on the barrier layer111aor may be directly arranged on the substrate100. In another embodiment, the back metal layer BML overlapping the thin-film transistor TFT may be omitted. In another embodiment, multiple back metal layers BML may be provided in the first area DA1, and some of the back metal layers BML may be arranged on different layers. The back metal layer BML may be arranged below the first pixel P1to prevent the thin-film transistor TFT, arranged in the first pixel P1, from being damaged or deteriorated by the component20. The back metal layer BML may be connected through a contact hole to a conductive layer ML arranged on another layer. The back metal layer BML may receive a constant voltage or a signal from the conductive layer ML. For example, the back metal layer BML may receive a driving voltage ELVDD, an initialization voltage, or a scan signal. Because the back metal layer BML receives a constant voltage or a signal, the probability of occurrence of electrostatic discharge may be significantly reduced. In another embodiment, all the back metal layers BML may not receive an electrical signal. In another embodiment, in case that the back metal layers BML are provided, various modifications may be made. For example, at least one of the back metal layers BML may be electrically isolated, and the others thereof may receive an electrical signal. The back metal layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). The back metal layer BML may include a single layer or multiple layers including the above-described material. A buffer layer111bmay be arranged on the back metal layer BML. The thin-film transistor TFT may be arranged above the buffer layer111b. The thin-film transistor TFT may include a semiconductor layer AL, a gate electrode GE, and a source electrode SE and a drain electrode DE that are electrode layers. The thin-film transistor TFT may be electrically connected to the organic light-emitting diode OLED and may drive the organic light-emitting diode OLED. The semiconductor layer AL may be arranged on the buffer layer111band may include polysilicon. In another embodiment, the semiconductor layer AL may include amorphous silicon. In another embodiment, the semiconductor layer AL may include oxide of at least one selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer AL may include a channel region, and a source region and a drain region doped with impurities. The semiconductor layer AL may overlap the back metal layer BML with the buffer layer111btherebetween. In an embodiment, a width of the semiconductor layer AL may be less than that of the back metal layer BML. Therefore, when projected in a direction perpendicular to the substrate100(or in a plan view), the entire semiconductor layer AL may overlap the back metal layer BML. In another embodiment, the back metal layer BML may correspond to the pixel area PA. In this case, multiple semiconductor layers AL may overlap the back metal layer BML. A first gate insulating layer112may cover or overlap the semiconductor layer AL. The first gate insulating layer112may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The first gate insulating layer112may be a single layer or multiple layers including the above-described inorganic insulating material. The gate electrode GE may be arranged on the first gate insulating layer112and overlap the semiconductor layer AL. The gate electrode GE may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like and may include a single layer or multiple layers. For example, the gate electrode GE may be a single Mo layer. A second gate insulating layer113may cover or overlap the gate electrode GE. The second gate insulating layer113may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate insulating layer113may be a single layer or multiple layers including the above-described inorganic insulating material. A second electrode CE2of the storage capacitor Cst may be arranged above or on the second gate insulating layer113. In the pixel circuit PC according to the embodiment, the second electrode CE2may overlap the gate electrode GE arranged therebelow. The gate electrode GE and the second electrode CE2overlapping each other with the second gate insulating layer113therebetween may form (or constitute) the storage capacitor Cst. The gate electrode GE may be a first electrode CE1of the storage capacitor Cst. The second electrode CE2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu) and may include a single layer or multiple layers including the above-described material. An interlayer insulating layer115may cover or overlap the second electrode CE2. The interlayer insulating layer115may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). In the embodiment, the buffer layer111b, the first gate insulating layer112, the second gate insulating layer113, the interlayer insulating layer115, which are arranged on the barrier layer111a, may be collectively defined as an inorganic insulating layer IL. The source electrode SE and the drain electrode DE may be arranged on the interlayer insulating layer115. The source electrode SE and the drain electrode DE may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like and may each include a single layer or multiple layers including the above-described material. For example, the source electrode SE and the drain electrode DE may each have a multilayer structure of Ti/Al/Ti. A first organic insulating layer117may cover or overlap the source electrode SE and the drain electrode DE. The first organic insulating layer117may include a flat upper surface so that a pixel electrode210arranged thereabove may be flat. A second organic insulating layer118may be arranged on the first organic insulating layer117. A contact metal CM may be between the first organic insulating layer117and the second organic insulating layer118. The contact metal CM may electrically connect the drain electrode DE to the pixel electrode210through contact holes formed in the first organic insulating layer117and the second organic insulating layer118. The first and second organic insulating layers117and118may include a single layer or multiple layers including an organic or inorganic material. The first and second organic insulating layers117and118may each include a general-purpose polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS)), a polymer derivative including a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and any blend thereof. The first and second organic insulating layers117and118may each include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The organic light-emitting diode OLED may be arranged on the second organic insulating layer118. The organic light-emitting diode OLED may include the pixel electrode210, an intermediate layer220including an emission layer222, and an opposite electrode230. The pixel electrode210may include conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode210may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In another embodiment, the pixel electrode210may further include a layer including ITO, IZO, ZnO, or In2O3above and/or below the reflective layer. For example, the pixel electrode210may have a stacked structure of ITO/Ag/ITO. A third organic insulating layer119corresponding to a pixel defining layer may cover or overlap each edge of the pixel electrode210. The third organic insulating layer119may include an opening OP overlapping the pixel electrode210and defining an emission area of the pixel (e.g., the first pixel P1). The opening OP may be defined as an emission area in the first pixel P1. The third organic insulating layer119may increase a distance between the edge of the pixel electrode210and the opposite electrode230disposed above the pixel electrode210, thereby preventing arcs or the like from occurring at the edge of the pixel electrode210. The third organic insulating layer119may include an organic insulating material such as polyimide, polyamide, an acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and a phenol resin and may be formed by spin coating or the like. The third organic insulating layer119may include a third hole H3corresponding to the transmission area TA. The third hole H3may overlap at least a part of the transmission hole HT. The first to third holes H1, H2, and H3may correspond to the transmission area TA, and thus the light transmittance of the transmission area TA may be improved. The intermediate layer220and the opposite electrode230, which will be described below, may be arranged on inner walls of the first to third holes H1, H2, and H3. A first common layer221may overlap the third organic insulating layer119. The first common layer221may be a single layer or multiple layers. The first common layer221may include a hole transport layer (hereinafter “HTL”) having a single layer structure. For example, the first common layer221may include a hole injection layer (hereinafter “HIL”) and an HTL. An emission layer222formed to correspond to the pixel electrode210may be arranged on the first common layer221. The emission layer222may include a high or low molecular weight material and may emit red, green, blue, or white light. A second common layer223may be arranged on the emission layer222. The second common layer223may be a single layer or multiple layers. The second common layer223may include an electron transport layer (hereinafter “ETL”) and/or an electron injection layer (hereinafter “EIL”). In an embodiment, the ETL may be arranged on the emission layer222, and the EIL may be arranged on the ETL. The first common layer221and the second common layer223may be integral with each other to commonly correspond to the first and second pixels P1and P2(seeFIG.2) included in the first area DA1and the second area DA2. In another embodiment, the first common layer221and/or the second common layer223may be omitted. The opposite electrode230may be arranged above the second common layer223. The opposite electrode230may include a conductive material having a low work function. For example, the opposite electrode230may include a transparent (or semi-transparent) layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. As another example, the opposite electrode230may further include a layer such as an ITO, IZO, ZnO, or In2O3layer on the transparent or semi-transparent layer including the above-described material. The opposite electrode230may be integrally formed in the display area DA. In an embodiment, the opposite electrode230is not provided in the transmission area TA. The opposite electrode230will be described below in detail. A capping layer240may be formed on the opposite electrode230so as to improve the light extraction rate of light emitted from the organic light emitting diode OLED. In an embodiment, the capping layer240may have a refractive index of about 1.7 to about 1.99 and may have a thickness of about 300 Å to about 1,000 Å. The capping layer240may include a metal material, for example, lithium fluoride (LiF). For example, the capping layer240may include an inorganic insulating material such as silicon nitride and/or an organic insulating material. In an embodiment, the capping layer240may be omitted. The organic light-emitting diode OLED may be sealed by the thin-film encapsulation layer300. The thin-film encapsulation layer300may be arranged on the opposite electrode230. In case that the capping layer240is formed on the opposite electrode230, the thin-film encapsulation layer300may be arranged on the capping layer240. The thin-film encapsulation layer300may prevent external moisture or foreign matter from penetrating into the organic light-emitting diode OLED. The thin-film encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard,FIG.4illustrates the thin-film encapsulation layer300having a structure in which a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330are stacked. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be changed. The first inorganic encapsulation layer310, the organic encapsulation layer320, and the second inorganic encapsulation layer330may be arranged in the entire display area DA and may be integral with each other to cover or overlap the first area DA1and the second area DA2. Therefore, the first inorganic encapsulation layer310, the organic encapsulation layer320, and the second inorganic encapsulation layer330may also be arranged in the transmission area TA. In another embodiment, the organic encapsulation layer320may be integrally formed to cover or overlap the first area DA1and the second area DA2but may not be present in the transmission area TA. For example, the organic encapsulation layer320may include an opening corresponding to the transmission area TA. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may contact each other in the transmission hole HT. In another embodiment, as illustrated inFIG.7, the display apparatus1according to an embodiment may not include a thin-film encapsulation layer, but instead may include an encapsulation substrate400as an encapsulation member. The encapsulation substrate400may include an insulating material such as glass, quartz, or a polymer resin. Although not illustrated, the encapsulation substrate400may be bonded to the substrate100through a sealant (e.g., a frit, etc.) arranged in the peripheral area NDA. Such a structure may prevent external moisture or foreign matter from penetrating into the organic light-emitting diode OLED. A transmission window TW may be provided in the transmission area TA. The transmission window TW may transmit light and/or sound output from the component20to the outside or traveling toward the component20. The transmission window TW may be implemented or formed through the transmission hole HT and the first to third holes H1, H2, and H3formed in the inorganic insulating layer IL and the first to third organic insulating layers117,118, and119. At least a portion of the barrier layer111amay be arranged in the transmission area TA. The barrier layer111aarranged in the transmission area TA may prevent outgas, generated during a process of manufacturing the substrate100including an organic material, from penetrating into the display layer DSL. In another embodiment, the barrier layer111amay not be arranged in the transmission area TA. In this case, the transmission hole HT, which will be described below, may extend to the barrier layer111a, and the substrate100may be exposed through the transmission hole HT. The inorganic insulating layer IL may include a transmission hole HT that is an opening corresponding to the transmission area TA. InFIG.4, the transmission hole HT may expose the barrier layer111a. The transmission hole HT may be formed by overlapping openings of the buffer layer111b, the first gate insulating layer112, the second gate insulating layer113, and the interlayer insulating layer115, which correspond to the transmission area TA. The openings may be separately formed through separate processes or may be simultaneously formed through the same process. In case that the openings are formed through the separate processes, a staircase-shaped stepped surface may be formed on the inner surface of the transmission hole HT. The first and second organic insulating layers117and118may respectively include a first hole H1and a second hole H2in correspondence with the transmission area TA. The first hole H1and the second hole H2may overlap at least a part of the transmission hole HT. The third organic insulating layer119may include the third hole H3in correspondence with the transmission area TA. The third hole H3may correspond to the transmission hole HT. The width of the third hole H3in a direction (e.g., the x-direction) may be greater than that of the second hole H2, the width of the second hole H2may be greater than that of the first hole H1, and the width of the first hole H1may be greater than that of the transmission hole HT. However, the disclosure is not limited thereto, and at least one of the first to third organic insulating layers117,118, and119may cover or overlap the inner surface of the transmission hole HT. The width of at least one of the first to third holes H1, H2, and H3may be less than that of the transmission hole HT. The emission layer222of the intermediate layer220may be formed only in the pixel area PA in correspondence with each pixel (e.g., the first pixel), but the first common layer221and the second common layer223may be arranged in the transmission area TA. The first common layer221and the second common layer223may be integral with each other over the entire display area DA. A hydrophobic layer250may be arranged on the second common layer223of the transmission area TA. In an embodiment, the hydrophobic layer250may be arranged on the EIL of the second common layer223(see the EIL223aofFIG.9). In another embodiment, the hydrophobic layer250may be arranged on the ETL (see the ETL223bofFIG.9), as illustrated inFIG.9or10, which will be described below. The hydrophobic layer250may include a fluorine-based organic material. For example, the hydrophobic layer250may include a perfluorine-based material such as perfluorooctyl-trichlorosilane or perfluorodecyltrichlorosilane (FDTS), a highly fluorinated monomer or oligomeric material, and a polymer material such as polytetrafluoroethylene (PTFE). In an embodiment, the hydrophobic layer250may include a fluorine-based molecule including at least one —CF3group at an end thereof. In the case of a —CF2 functional group in which two fluorine atoms are bonded to a carbon atom, surface energy is about 18 mJ/m2, which is relatively lower than the surface energy of most inorganic materials including metals. Furthermore, in the case of a —CF3functional group in which three fluorine atoms are bonded to a carbon atom, the surface energy is very low (e.g., about 6 mJ/m2). Thus, the hydrophobic layer250including the fluorine-based molecule including the —CF3group may prevent a metal layer (e.g., an opposite electrode) from being formed in the transmission area TA. The opposite electrode230may include an opening230OP corresponding to the transmission area TA. As described above, the opposite electrode230is not formed on the hydrophobic layer250because of the difference in surface energy. For example, in the manufacturing process, the opposite electrode230may be deposited on or applied onto the entire surface of the display area DA but may not be selectively formed in the transmission area TA in which the hydrophobic layer250is arranged. Fine particles230P may be arranged on the hydrophobic layer250of the transmission area TA. The fine particles230P and the opposite electrode230may include the same material. The material for forming the opposite electrode230deposited on or applied onto the transmission area TA may have very low spreadability on the hydrophobic layer250, and thus may not have a layer shape like the pixel area PA and may be agglomerated in the form of particles on the hydrophobic layer250to form the fine particles230P. Referring toFIG.5, the fine particles230P may be spaced apart from each other on the hydrophobic layer250, and some of the fine particles230P may contact each other. The fine particles230P may not be provided on the entire surface of the hydrophobic layer250. The fine particles230P may be selectively present in a portion of the hydrophobic layer250. With this structure, the opposite electrode230is not present on the transmission area TA, so that the transmittance of the transmission area TA may be improved. FIGS.6A to6Cillustrates transmission electron microscope (TEM) images of the opposite electrode230and the fine particles230P. Referring toFIGS.5and6, a diameter D of each of the fine particles230P may be in a range of about 1 nm to about 10 nm. A thickness H of the opposite electrode230in the pixel area PA may be in a range of about 7 nm to about 10 nm. Therefore, the diameter D of each of the fine particles230P may be 10 nm or less and about 1 nm or greater. As illustrated inFIG.6A, the opposite electrode230may be arranged in the pixel area PA, or the display area DA excluding the transmission area TA, and the EIL (see the EIL223bofFIG.9) may be arranged below the opposite electrode230. InFIG.6A, the EIL223bmay have a thickness of about 2.23 nm, and the opposite electrode230may have a thickness of about 7.09 nm. FIGS.6B and6Cillustrate that the fine particles230P are formed in the transmission area TA. As described above, because of the hydrophobic layer250, the fine particles230P may not form a layer as illustrated inFIG.6Aand may be formed in the form of particles.FIGS.6B and6Cillustrate the fine particles230P formed to have a diameter less than the thickness of the opposite electrode230. In an embodiment, in the same area, the volume ratio of the fine particles230P may be about 30% or less of that of the opposite electrode230. This means that, as the volume ratio of the fine particles230P decreases, the transmittance of the transmission area TA is improved. Therefore, the volume ratio of the fine particles230P may be about 30% or less of that of the opposite electrode230, but the transmittance of the transmission area TA may be advantageously secured as the volume ratio of the fine particles230P decreases. The capping layer240may be arranged on the fine particles230P of the transmission area TA.FIG.4illustrates that the capping layer240is also arranged in the transmission area TA, and thus may be provided on the entire surface of the display area DA, but the disclosure is not limited thereto. In case that the capping layer240is arranged in the transmission area TA, at least a portion of the capping layer240may contact the hydrophobic layer250. The fine particles230P may be spaced apart from each other in some areas, and the capping layer240may contact the hydrophobic layer250in an area between the fine particles230P spaced apart from each other. In another embodiment, as illustrated inFIG.8, the capping layer240may be patterned to include an opening240OP corresponding to the transmission area TA. Similar to the opposite electrode230, in case that the capping layer240is arranged in the transmission area TA, the capping layer240may act as a factor of impairing the transmittance of the transmission area TA. Therefore, the capping layer240may be patterned to include the opening240OP corresponding to the transmission area TA, thereby improving the transmittance of the transmission area TA. In an embodiment, the opening240OP of the capping layer240may be formed by using a shadow mask. FIG.8illustrates that an end of the capping layer240, forming the opening240OP is located above the third organic insulating layer119, but the disclosure is not limited thereto. The width of the opening240OP of the capping layer240in a direction (e.g., the x-direction) may be equal to or greater than the width of the transmission area TA. The thin-film encapsulation layer300may be arranged on the capping layer240. As described above, the thin-film encapsulation layer300may also be arranged in the transmission area TA. FIGS.9and10are cross-sectional views schematically illustrating a portion of a display apparatus, according to an embodiment. The embodiments ofFIGS.9and10are similar to the embodiment ofFIG.4described above, but differ from the embodiment ofFIG.4at least in that a second common layer223may include an ETL223aand an EIL223b, and a hydrophobic layer250may be arranged directly on the ETL223a. Hereinafter, differences will be mainly described. The second common layer223may be provided over the entire surface of the display area DA and may include the ETL223aand the EIL223b. As illustrated inFIG.9, the ETL223aand the EIL223bmay be sequentially stacked on the emission layer222in correspondence with the pixel area PA, and the opposite electrode230may be arranged on the EIL223b. In the transmission area TA, the hydrophobic layer250may be arranged directly on the ETL223a. In other words, in a manufacturing process, the hydrophobic layer250is formed after the ETL223ais formed and before the EIL223bis formed. The EIL223bis not provided on the hydrophobic layer250, and the fine particles230P described above may be partially provided. The capping layer240and the thin-film encapsulation layer300may be arranged on the fine particles230P. In the embodiment, the EIL223bmay include a metal material, for example, ytterbium (Yb). The EIL223bmay include the metal material, and the EIL223bmay act as a factor of impairing the transmittance of the transmission area TA, similar to the opposite electrode230. Therefore, in an embodiment, the hydrophobic layer250may be arranged before the EIL223bis formed. For example, the hydrophobic layer250is arranged directly on the ETL223a, so that the EIL223bis not formed in the transmission area TA because of the hydrophobic layer250. In another embodiment, as illustrated inFIG.10, a capping layer240may be patterned to include an opening240OP corresponding to the transmission area TA. Similar to the opposite electrode230, in case that the capping layer240is arranged in the transmission area TA, the capping layer240may act as a factor of impairing the transmittance of the transmission area TA. Therefore, the capping layer240may be patterned to include the opening240OP corresponding to the transmission area TA, thereby improving the transmittance of the transmission area TA. FIGS.11and12are cross-sectional views schematically illustrating a portion of a display apparatus, according to an embodiment. The embodiments ofFIGS.11and12are similar to the embodiment ofFIG.4described above but differ from the embodiment ofFIG.4at least in that an optical functional layer260is further provided on a hydrophobic layer250. Hereinafter, differences will be mainly described. The optical functional layer260may be arranged on the hydrophobic layer250, in correspondence with the transmission area TA. The optical functional layer260may have a refractive index less than that of the capping layer240. The optical functional layer260may concentrate light in the transmission area TA to improve light emission efficiency. In an embodiment, the optical functional layer260may have a refractive index of about 1.3 to about 1.6 and may have a thickness of about 100 Å to about 1,000 Å. The optical functional layer260may include an organic material and/or an inorganic material satisfying the above-described refractive index. The capping layer240may be arranged on the optical functional layer260. For example, in the embodiment, the capping layer240may also be arranged in the transmission area TA, in correspondence with the entire surface of the display area DA. In another embodiment, as illustrated inFIG.12, the capping layer240may not be arranged on the optical functional layer260. The capping layer240may be patterned to include an opening240OP corresponding to the transmission area TA. Similar to the opposite electrode230, in case that the capping layer240is arranged in the transmission area TA, the capping layer240may act as a factor of lowering the transmittance of the transmission area TA. Therefore, the capping layer240may be patterned to include the opening240OP corresponding to the transmission area TA, thereby improving the transmittance of the transmission area TA. In this case, a first inorganic encapsulation layer310may be directly arranged on the optical functional layer260in the transmission area TA. FIGS.13and14are cross-sectional views schematically illustrating a portion of a display apparatus, according to an embodiment. The embodiments ofFIGS.13and14are similar to the embodiment ofFIG.4described above, but differ from the embodiment ofFIG.4at least in that a second common layer223includes an ETL223aand an EIL223b, and an optical functional layer260is arranged on a hydrophobic layer250. Hereinafter, differences will be mainly described. Referring toFIG.13, the second common layer223may include the ETL223aand the EIL223b. The ETL223aand the EIL223bmay be sequentially stacked on an emission layer222, in correspondence with the pixel area PA, and an opposite electrode230may be arranged on the EIL223b. In the embodiment, the EIL223bmay include a metal material, for example, ytterbium (Yb). Because the EIL223bincludes the metal material, the EIL223bmay act as a factor of lowering the transmittance of the transmission area TA, similar to the opposite electrode230. Therefore, in an embodiment, the hydrophobic layer250may be arranged directly on the ETL223a, so that the EIL223bis not formed in the transmission area TA because of the hydrophobic layer250. In the transmission area TA, the optical functional layer260may be arranged on the hydrophobic layer250. The optical functional layer260may have a refractive index less than that of a capping layer240. The optical functional layer260may concentrate light in the transmission area TA to improve light emission efficiency. In an embodiment, the optical functional layer260may have a refractive index of about 1.3 to about 1.6 and may have a thickness of about 100 Å to about 1,000 Å. The optical functional layer260may include an organic material and/or an inorganic material satisfying the above-described refractive index. The capping layer240may be arranged on the optical functional layer260. For example, in the embodiment, the capping layer240may also be arranged in the transmission area TA, in correspondence with the entire surface of the display area DA. In another embodiment, as illustrated inFIG.14, the capping layer240may not be arranged on the optical functional layer260. The capping layer240may be patterned to include an opening240OP corresponding to the transmission area TA. Similar to the opposite electrode230, in case that the capping layer240is arranged in the transmission area TA, the capping layer240may act as a factor of lowering the transmittance of the transmission area TA. Therefore, the capping layer240may be patterned to include the opening240OP corresponding to the transmission area TA, thereby improving the transmittance of the transmission area TA. In this case, a first inorganic encapsulation layer310may be directly arranged on the optical functional layer260in the transmission area TA. FIG.15is an experimental graph showing a change in the transmittance of the transmission area TA according to the presence or absence of the hydrophobic layer250. Referring toFIG.15together with the above-described embodiments, to form identical conditions to the above-described transmission area TA, in the case of Example A, first and second common layers221and223(e.g., including an HIL/HTL/ETL structure having a thickness of about 1,520 Å) were deposited on a glass substrate, a hydrophobic layer250was formed on the first and second common layers221and223, and an opposite electrode230(e.g., an AgMg layer having a thickness of about 100 Å) was formed thereon. In the case of Comparative Example B, first and second common layers221and223(e.g., including an HIL/HTL/ETL structure having a thickness of about 1,520 Å), were deposited on a glass substrate, and an opposite electrode230(e.g., an AgMg layer having a thickness of about 90 Å) was formed directly on the first and second common layers221and223. As illustrated inFIG.15, it can be seen that a change in the transmittance is 10% or greater in a wavelength range of about 450 nm or greater according to the presence or absence of the hydrophobic layer250. For example, it was found that the transmittance of Example A including the hydrophobic layer250is 10% or more superior to that of Comparative Example B. In the case of Example A, in forming the opposite electrode230, the transmittance of the transmission area TA may be easily secured by the hydrophobic layer250without a separate patterning process corresponding to the transmission area TA. Although the display apparatus has been described, the disclosure is not limited thereto. For example, methods of manufacturing the display apparatus will also fall within the scope of the disclosure. FIGS.16A to16Dare cross-sectional views schematically illustrating part of a process of manufacturing a display apparatus, according to an embodiment. Referring toFIG.16A, after a pixel electrode210is formed on a pixel area PA, a third organic insulating layer119may be formed to include the opening OP overlapping the edge of the pixel electrode210and exposing a central portion thereof. The pixel electrode210and the third organic insulating layer119may not be formed on a transmission area TA. For convenience of description,FIGS.16A to16Dillustrate that the pixel electrode210is formed directly on a substrate100. However, in practice, it may be understood that, after various elements including a thin-film transistor, wirings, and insulating layers are formed on the substrate100as illustrated inFIG.4, the pixel electrode210is formed thereon. Subsequently, as illustrated inFIG.16B, an intermediate layer220may be formed on the pixel electrode210. More specifically, a first common layer221may be formed on the pixel electrode210, an emission layer222may be formed on the first common layer221, and a second common layer223may be formed on the emission layer222. The emission layer222may be patterned for each pixel and formed only on the pixel electrode210, whereas the first and second common layers221and223are formed on both the pixel area PA and the transmission area PA. Next, as illustrated inFIG.16C, a hydrophobic layer250may be formed on the transmission area TA. The hydrophobic layer250may include a fluorine-based organic material and may have liquid-repellent properties. The basic characteristics of the hydrophobic layer250may be the same as described above. The hydrophobic layer250may be formed by using a process of a deposition method such as dry film formation, wet coating, screen printing, inkjet printing, or the like. The hydrophobic layer250according to the embodiment may include a fluorine-based molecule including at least one —CF3group at an end thereof, and thus the surface energy of the hydrophobic layer250may be very low, as compared with that of most inorganic materials including metals. In case that a layer having a relatively high surface energy is formed on a layer having very low surface energy, an upper layer is not normally formed because of poor spreadability. Next, as illustrated inFIG.16D, an electrode material may be applied onto the entire surfaces of the pixel area PA and the transmission area TA. The electrode material applied onto the pixel area PA may form an opposite electrode230. The electrode material applied onto the transmission area TA may form fine particles230P. For example, the electrode material on the pixel area PA may be formed on the second common layer223as a layer having a thickness equal to that of the opposite electrode230, and the electrode material on the transmission area TA may not be formed on the hydrophobic layer250as a layer, but may be formed as fine particles230P including material(s) identical to that of the opposite electrode230. As described above, it means that, because of the surface energy of the hydrophobic layer250, the electrode material does not form a layer as in the pixel area PA, but is agglomerated in the form of particles on the hydrophobic layer250to form the fine particles230P. In an embodiment, in the same area, the volume ratio of the fine particles230P may be about 30% or less of that of the opposite electrode230. As described above, in the display apparatus1according to the embodiment, the hydrophobic layer250may be provided in the transmission area TA so that the opposite electrode230is selectively formed only in the pixel area PA. Therefore, the display apparatus1may prevent the opposite electrode230from being formed in the transmission area TA without a process of patterning the opposite electrode230, thereby improving the transmittance of the transmission area TA. According to one or more embodiments, a display apparatus including an expanded display area enabling images to be displayed even in an area in which a component is arranged and a method of manufacturing the display apparatus are provided. The scope of the disclosure is not limited by these effects. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 59,544 |
11943958 | MODES FOR CARRYING OUT THE INVENTION In the following, some embodiments of the disclosure are described in detail with reference to the accompanying drawings. Note that the embodiments described below are preferred specific examples of the disclosure. Thus, factors including, without limitation, numerical values, shapes, materials, components, positions of the components, and how the components are coupled to each other are illustrative only and not to be construed as limiting to the disclosure. Further, elements in the following embodiments which are not recited in a most-generic independent claim of the disclosure are optional and may be provided on an as-needed basis. The drawings are schematic and are not intended to be drawn to scale and not necessarily strictly illustrated. Note that the like elements are denoted with the same reference numerals, and any redundant description thereof is omitted or simplified. Note that the description is given in the following order:1. Embodiments (Display Apparatus)2. Modification Examples (Display Apparatus) 1. EMBODIMENTS [Configuration] FIG.1illustrates a schematic configuration example of a display apparatus1according to one embodiment of the disclosure. The display apparatus1includes a display panel10, a controller20, and a driver30, for example.FIG.2illustrates an exemplary connection between the display panel10, the controller20, and the driver30.FIG.3illustrates an exemplary circuit configuration of each pixel11provided in the display apparatus1. The display panel10includes a plurality of pixels11arranged in matrix. The plurality of pixels11are provided in a display region10A of the display panel10. The display region10A corresponds to an image display surface of the display panel10. The display panel10has a frame region10B surrounding the display region10A. The frame region10B has a frame shape surrounding the display region10A. A plurality of mounting terminals are provided at one side of the frame region10B. The plurality of mounting terminals53are electrically connected to the plurality of pixels11and flexible printed circuits (FPCs)52. The controller20and the driver30are mounted on a control base51and electrically connected to the display panel10(the plurality of pixels11) via the FPCs52. The controller20and the driver30drive the display panel10(the plurality of pixels11) on the basis of an image signal Din received from an external device. [Display Panel10] In response to active-matrix driving of the pixels11performed by the controller20and the driver30, the display panel10displays an image on the display region10A on the basis of the image signal Din received from the external device. The display panel10includes multiple scanning lines WSL extending in a row direction, multiple signal lines DTL and multiple power lines DSL extending in a column direction, and the plurality of pixels11arranged in matrix. The scanning line WSL is used to select the pixels11. For example, the scanning line WSL supplies a selection pulse to any of the pixels11to select the pixels11on a predetermined unit basis (e.g., a pixel-row basis). The signal line DTL is used to supply a signal voltage corresponding to the image signal Din to each pixel11. For example, the signal line DTL supplies a data pulse including a signal voltage to each pixel11. The power line DSL supplies electric power to each pixel11. The pixels11in the display panel10include ones emitting red right, ones emitting green light, and ones emitting blue light. The pixel11emitting red light, the pixel11emitting green light, and the pixel11emitting blue light constitute a display pixel, which is a unit of display of a color image. Each display pixel may further include a pixel11emitting light of another color (e.g., white or yellow). Alternatively, each display pixel may include a plurality of pixels11emitting light of the same color (e.g., two pixels11emitting blue light). Each of the signal lines DTL is coupled to an output terminal of a horizontal selector31to be described later. Each of the signal lines DTL is allocated to its corresponding pixel column, for example. Each of the scanning lines WSL is coupled to an output terminal of a write scanner32to be described later. Each of the scanning lines WSL is allocated to its corresponding pixel row, for example. Each of the power lines DSL is coupled to an output terminal of a power source. Each of the power lines DSL is allocated to its corresponding pixel row, for example. Each pixel11includes a pixel circuit11-1and an organic electroluminescent element11-2. The configuration of the organic electroluminescent element11-2will be described later. The pixel circuit11-1controls light emission and light extinction of the organic electroluminescent element11-2. The pixel circuit11-1has a function of holding a voltage written in each pixel11through write scanning. The pixel circuit11-1includes a driving transistor Tr1, a write transistor Tr2, and a storage capacitor Cs, for example. The write transistor Tr2controls an application of the signal voltage corresponding to the image signal Din to a gate of the driving transistor Tr1. For example, the write transistor Tr2samples the voltage of the signal line DTL and write the sampled voltage into the gate of the driving transistor Tr1. The driving transistor Tr1is coupled in series to the organic electroluminescent element11-2. The driving transistor Tr1drives the organic electroluminescent element11-2. The driving transistor Tr1controls an electric current flowing in the organic electroluminescent element11-2on the basis of the magnitude of the voltage sampled at the write transistor Tr2. The storage capacitor Cs holds a predetermined voltage between the gate and the source of the driving transistor Tr1. The storage capacitor Cs holds a constant voltage between the gate and the source of the driving transistor Tr1for a predetermined period of time. Note that the pixel circuit11-1may have the 2Tr1C circuit configuration described above and additional capacitors and transistors. Alternatively, the pixel circuit11-1may have a circuit configuration different from the 2Tr1C circuit configuration described above. Each of the signal lines DTL is coupled to the output terminal of the horizontal selector31to be described later and the source or drain of the write transistor Tr2. Each of the scanning lines WSL is coupled to the output terminal of the write scanner32to be described later and the gate of the write transistor Tr2. Each of the power lines DSL is coupled to a power supply circuit and the source or drain of the driving transistor Tr1. The gate of the write transistor Tr2is coupled to the scanning line WSL. One of the source and drain of the write transistor Tr2is coupled to the signal line DTL. The other of the source and drain of the write transistor Tr2, which is not coupled to the signal line DTL, is coupled to the gate of the driving transistor Tr1. One of the source and drain of the driving transistor Tr1is coupled to the power line DSL. The other of the source and drain of the driving transistor Tr1, which is not coupled to the power line DSL, is coupled to an anode21of the organic electroluminescent element11-2. One end of the storage capacitor Cs is coupled to the gate of the driving transistor Tr1The other end of the storage capacitor Cs is coupled to the source or drain of the driving transistor Tr1whichever is adjacent to the organic electroluminescent element11-2. The driving transistor Tr1and the write transistor Tr2are general thin-film transistors (TFTs) and may have a reverse staggered structure (a so-called bottom gate type) or a staggered structure (top gate type). The structure of the driving transistor Tr1and the write transistor Tr2should not limited to a particular structure. [Driver30] The driver30includes the horizontal selector31and the write scanner32, for example. The horizontal selector31applies an analog signal voltage received from the controller20to each of the signal lines DTL in response to (in synchronization with) a control signal, for example. The write scanner32scans the pixels11on a predetermined unit basis. [Controller20] The controller20will now be described. The controller20performs a predetermined correction on the digital image signal Din received from an external device, for example, and generates a signal voltage based on the image signal generated as a result of the correction. The controller20outputs the generated signal voltage to the horizontal selector31, for example. For example, the controller20outputs a control signal to each circuit in the driver30in response to (in synchronization with) the control signal obtained from the image signal Din. Next, with reference toFIGS.4and5, a cross-sectional configuration of the display panel10is described.FIG.4illustrates an exemplary cross-sectional configuration taken along a line A-A inFIG.3.FIG.5illustrates an exemplary cross-sectional configuration taken along a line B-B inFIG.3. The display panel10includes a flexible substrate41and a plurality of organic electroluminescent elements44A provided on a surface41A (first main face) of the flexible substrate41. The flexible substrate41is a film or sheet made of resin, for example. The flexible substrate41includes a methacrylic resin, such as polyimide (PI) or polymethylmethacrylate (PMMA), a polyester, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polybutylene naphthalate (PBN), or a polycarbonate resin. The organic electroluminescent elements44A correspond to the organic electroluminescent elements11-2described above. The display panel10includes TFT circuits43A provided between the surface41A of the flexible substrate41and the organic electroluminescent elements44A. The TFT circuits43A drive the organic electroluminescent elements44A. The TFT circuits43A corresponds to the pixel circuits11-1described above. The display panel10includes an inorganic insulating film43B (first inorganic film) provided between the TFT circuits43A and the organic electroluminescent elements44A. The inorganic insulating film43B covers the TFT circuits43A. The inorganic insulating film43B includes an inorganic material having low moisture absorbency, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), titanium oxide (TiOx), or aluminum oxide (AlxOy). The inorganic insulating film43B has a step portion43C. The step portion43C is a thinned portion of the inorganic insulating film43B opposed to an end portion of the flexible substrate41. The portion of the inorganic insulating film43B opposed to the end portion of the flexible substrate41is thinner than the other portion of the inorganic insulating film43B opposed to the organic electroluminescent elements44A. The difference in thickness between the portion opposed to the end portion of the flexible substrate41and the portion opposed to the organic electroluminescent elements44A forms the step portion43C. The step portion43C is formed in the frame region10B. The step portion43C is formed so as not to be opposed to at least the mounting terminals53. For example, the step portion43C is formed along three sides of the frame region10B other than the side along which the mounting terminals53are formed. The mounting terminals53are formed in a flat region of the surface of the inorganic insulating film43B in which the step portion43C is not formed, and are exposed on the surface of the inorganic insulating film43B. Alternatively, the step portion43C is formed on two sides of the frame region10B perpendicular to the side along which the mounting terminals53are formed. In such a case, the display panel10is foldable only in the direction perpendicular to the side of the frame region10B along which the mounting terminals53are formed. The display panel10includes an inorganic insulating film45(second inorganic film) covering the organic electroluminescent elements44A, and a resin layer46covering the inorganic insulating film45and covering at least a portion of the inorganic insulating film43B in contact with an end portion of the inorganic insulating film45. For example, the inorganic insulating film45includes an inorganic material having low moisture absorbency, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), titanium oxide (TiOx), or aluminum oxide (AlxOy). An end portion of the resin layer46may be formed on the step portion43C. In such a case, the resin layer46is in contact with the entire surface of the inorganic insulating film45and also in contact with from a portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45to the step portion43C. The resin layer46also serves as an adhesive layer, and includes an epoxy resin or an acrylic resin, for example. The resin layer46may include a thermosetting resin or an ultraviolet curing resin, for example. In the display panel10, the organic electroluminescent elements44A are separated from each other by opening definition insulating portions44B. Each of the organic electroluminescent elements44A defined in outline is provided in each pixel11. The opening definition insulating portions44B and the organic electroluminescent elements44A are formed on the same plane, forming an EL element layer44. The display panel10includes a UC barrier layer42between the flexible substrate41and the TFT circuits43A. The UC barrier layer42entirely covers the surface41A of the flexible substrate41. The UC barrier layer42is an inorganic insulating film including an inorganic material having low moisture absorbency, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), titanium oxide (TiOx), or aluminum oxide (AlxOy). The UC barrier layer42may be a single layer or a laminated layer including layers made of different materials. The display panel10includes a sealing layer47provided so as to be opposed to the flexible substrate41and being in contact with the resin layer46. The sealing layer47includes a resin material, such as an epoxy resin or a vinyl resin. The sealing layer47may have an optical function. The sealing layer47may be a polarization plate, for example. The display panel10includes, in order, a resin layer48and a reinforcement layer49on a rear surface41B of the flexible substrate41. The resin layer48entirely covers the rear surface41B of the flexible substrate41. For example, the resin layer48serves as an adhesive layer that adheres the flexible substrate41to the reinforcement layer49. The resin layer48includes an epoxy resin or an acrylic resin, for example. The reinforcement layer49serves as a reinforcing member that maintains the strength of the display panel10, and a protective member that protects the back face of the display panel10. For example, the reinforcement layer49includes a resin material, such as PET or PI, or a metal material, such as Al, Cu, or SUS. FIG.6illustrates the step portion43C in an enlarged manner. The portion of the inorganic insulating film43B opposed to the end portion of the flexible substrate41has a thickness tb. The portion of the inorganic insulating film43B opposed to the organic electroluminescent elements44A has a thickness ta. The length between the portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45and the end portion of the inorganic insulating film43B is indicated by Wa, and the length between the step portion43C and the end portion of the inorganic insulating film43B is indicated by Wb. In this case, it is preferable that the thickness tb be 3% or greater and 50% or less of the thickness ta. The length Wa is within a practical range of a narrow frame panel, for example, 1 mm or greater and 10 mm or less. The lower limit of the length Wb is a minimum length that prevents an initially-generated crack from reaching the step portion43C, and may be, for example, 0.1 mm. The upper limit of the length Wb is a half of a maximum possible length of the length Wa, and may be, for example, 5 mm. FIG.7illustrates a design model of the step portion43C. As illustrated inFIG.7(A), when a plate object is stretched from both sides with a force F, a stress σ0exerted on a cross-section perpendicular to the stretching direction is represented by F/(Bt), where “B” denotes the width of the object, and “t” denotes the thickness of the object. Further, as illustrated inFIG.7(B), when an object in which an initial crack in the form of an oval hole is formed, is stretched from both sides with the force F, a stress σmaxexerted on an end portion of the oval hole is represented by σ0×(1+2(a/ρ)1/2), where “2a” denotes the longitudinal length of the oval hole, “2b” denotes the lateral length of the oval hole, and “ρ(=b2/a)” denotes the radius of curvature of an end portion of the oval hole. Here, the stress σmaxis in proportion to “1/t”. Thus, a relationship represented by σmax1/σmax2=t2/t1is hold between the stress σmax1exerted on the end portion of the oval hole formed in the inorganic insulating film43B at a position opposed to the end portion of the flexible substrate41and the stress σmax2exerted on the end portion of the oval hole formed at a position opposed to the organic electroluminescent elements44A. Accordingly, assuming that a crack is generated in a film by a stress greater than a predetermined level, it is possible to make the portion of the inorganic insulating film43B opposed to the organic electroluminescent elements44A twice as resistant to a crack as the portion of the inorganic insulating film43B opposed to the end of the flexible substrate41by setting the thickness ta to be twice of the thickness tb, for example. [Manufacturing Method] An exemplary method of manufacturing the display panel10will now be described.FIGS.8A to8Fare cross-sectional views of the display panel10illustrating exemplary steps for manufacturing the display panel10. First, the flexible substrate41, the UC barrier layer42, and the TFT layer43are formed on a large supporting glass100(FIG.8A). Thereafter, the EL element layer44and the inorganic insulating film45are formed in each section corresponding to the size of the display panel10(FIG.8A). Thereafter, the sealing layer47is attached to the inorganic insulating film45with the resin layer46provided therebetween in each section corresponding to the size of the display panel10(FIG.8B). Thereafter, the large supporting glass100is separated into the sections each corresponding to the size of the display panel10(FIGS.8C(a) and8C(b)).FIG.8C(a) illustrates an exemplary cross-sectional configuration taken along the line A-A inFIG.2, andFIG.8C(b) illustrates an exemplary cross-sectional configuration taken along the line B-B inFIG.2. Next, the inorganic insulating film43B of the TFT layer43is selectively etched using the sealing layer47as a mask (FIGS.8D(a) and8D(b)). The step portion43C is thereby formed in the inorganic insulating film43B. While the step portion43C is being formed (i.e., while the inorganic insulating film43B is being selectively etched using the sealing layer47as a mask), the inorganic insulating film43B is etched into a desired thickness tb for a predetermined etching time that is calculated based on a preliminarily calculated etching rate of the inorganic insulating film43B, for example. The front surfaces of the mounting terminals53are thereby exposed. Thereafter, the FPCs52are mounted on the respective mounting terminals53(FIGS.8E(a) and8E(b)). Lastly, the supporting glass100is removed, and the reinforcement layer49is attached to the rear surface of the flexible substrate41with the resin layer48provided therebetween (FIGS.8F(a) and8F(b)). The display panel10according to the present embodiment is manufactured as described above. The display panel10may be produced by a method other than the method described above.FIGS.9A to9Hare cross-sectional views illustrating exemplary steps for manufacturing the display panel10. First, the flexible substrate41, the UC barrier layer42, and the TFT layer43are formed on the large supporting glass100(FIG.9A). Thereafter, the EL element layer44and the inorganic insulating film45are formed in each section corresponding to the size of the display panel10(FIG.9A). Thereafter, a supporting film120is attached to the entire surface including the inorganic insulating film45with the resin layer130provided therebetween, and then the supporting glass100is removed (FIG.9B). Thereafter, the reinforcement layer49is attached to the rear surface of the flexible substrate41with the resin layer48provided therebetween (FIG.9C). Next, the supporting film120and the resin layer130are removed (FIG.9D), and the sealing layer47is attached to the inorganic insulating film45with the resin layer46provided therebetween in each section corresponding to the size of the display panel10(FIG.9E). Thereafter, the inorganic insulating film43B of the TFT layer43is selectively etched using the sealing layer47as a mask (FIG.9F). The step portion43C is thereby formed in the inorganic insulating film43B. The front surfaces of the mounting terminals53are thereby exposed. Thereafter, the flexible substrate41is separated into the sections each corresponding to the size of the display panel10(FIGS.9G(a) and9G(b)).FIG.9G(a) illustrates an exemplary cross-sectional configuration taken along the line A-A inFIG.2, andFIG.9G(b) illustrates an exemplary cross-sectional configuration taken along the line B-B inFIG.2. Lastly, the FPCs52are mounted on the respective mounting terminals53(FIGS.9H(a) and9H(b)). The display panel10of the present embodiment is manufactured as described above. The display panel10may be produced by a method other than the methods described above.FIGS.10A to10Care cross-sectional views illustrating exemplary steps for manufacturing the display panel10. First, the same processes as those illustrated inFIGS.9A to9Care performed. Thereafter, the flexible substrate41is separated into sections each corresponding to the size of the display panel10(FIGS.10A(a) and10A(b)).FIG.10A(a) illustrates an exemplary cross-sectional configuration taken along the line A-A inFIG.2, andFIG.10A(b) illustrates an exemplary cross-sectional configuration taken along the line B-B inFIG.2. Thereafter, the supporting film120and the resin layer130are removed (FIGS.10B(a) and10B(b)), and the sealing layer47is attached to the inorganic insulating film45with the resin layer46provided therebetween in each section corresponding to the size of the display panel10(FIGS.10C(a) and10C(b)). Next, the inorganic insulating film43B of the TFT layer43is selectively etched using the sealing layer47as a mask (FIGS.9G(a) and9G(b)). The step portion43C is thereby formed in the inorganic insulating film43B. The front surfaces of the mounting terminals53are thereby exposed. Lastly, the FPCs52are mounted on the respective mounting terminals53(FIGS.9H(a) and9H(b)). The display panel10according to the present embodiment is manufactured as described above. [Effects] Some effects of the display panel10and the display apparatus1according to the present embodiment will now be described. In the display panel including the self-luminescent element such as an organic electroluminescent element, the self-luminescent element is driven by the TFT. In the frame region of the display panel, the inorganic film of the TFT is provided. Meanwhile, it is possible to make the display panel flexible by using a flexible substrate in the display panel. However, such a flexible display panel is likely to cause a crack in the inorganic film in the frame portion of the display panel while being carried or intentionally bent. Once a crack is formed in the inorganic film, external moisture can enter through the crack to cause display failures, such as a dark spot. However, in the present embodiment, the inorganic insulating film43B covering the TFT circuit43A has the step portion43C, which is the thinned portion of the inorganic insulating film43B opposed to the end portion of the flexible substrate41. If a crack is generated at the end portion of the inorganic insulating film43B while the display panel10is being carried or intentionally bent, the step portion43C helps prevent the crack from expanding. Further, in the present embodiment, the inorganic insulating film45covering each organic electroluminescent element44A is covered with the resin layer46. The resin layer46also covers at least a portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45. Accordingly, even if a crack generated in the end portion of the inorganic insulating film43B expands over the step portion43C, the resin layer46helps prevent the crack from expanding through the portions of the inorganic insulating film43B and the inorganic insulating film45covered with the resin layer46. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Further, in the present embodiment, the end portion of the resin layer46is formed on the step portion43C. In this case, the resin layer46is in contact with the entire surface of the inorganic insulating film45and also in contact with from the portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45to the step portion43C. Accordingly, even if a crack generated in the end portion of the inorganic insulating film43B expands over the step portion43C, the resin layer46helps prevent the crack from expanding through the portions of the inorganic insulating film43B and the inorganic insulating film45covered with the resin layer46. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Further, in the present embodiment, the step portion43C is formed so as not to be opposed to at least the mounting terminals53. That is, the step portion43C does not reach the region of the display panel10not to be intentionally bent. Thus, it is possible to provide the mounting terminals53in flat portions. As a result, the FPCs52are easily coupled to the mounting terminals53. 2. MODIFICATION EXAMPLES Modification examples of the display panel10according to the foregoing embodiment will now be described. Modification Example A FIG.11illustrates a cross-sectional configuration taken along the line A-A inFIG.4according to one modification example. In the foregoing embodiment, the step portion43C of the inorganic insulating film43B and the vicinity thereof may be exposed without being covered with the resin layer46. Even in such a case, the resin layer46covers at least the portion of inorganic insulating film43B in contract with the end portion of the inorganic insulating film45. The end portion of the resin layer46is in contact with the surface of the inorganic insulating film43B in a region between the end portion of the inorganic insulating film45and the step portion43C. A step portion43D is formed in the portion where the end portion of the resin layer46is in contact with the surface of the inorganic insulating film43B. Accordingly, even if a crack generated in the end portion of the inorganic insulating film43B expands over the step portion43C, the resin layer46and the step portion43D help prevent the crack from expanding through the portions of the inorganic insulating films43B and45covered with the resin layer. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Modification Example B FIGS.12and13illustrate a cross-sectional configuration taken along the line A-A inFIG.4according to one modification example. In the foregoing embodiment and Modification Example A, the display panel10may include a resin layer54and a UC barrier layer57between the UC barrier layer42and the TFT layer43. The resin layer54includes an epoxy resin or an acrylic resin, for example. The UC barrier layer57is an inorganic insulating film including an inorganic material having low moisture absorbency, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), titanium oxide (TiOx), or aluminum oxide (AlxOy). The UC barrier layer57may be a single layer or a laminated layer including layers made of different materials. Accordingly, if a crack is generated at the UC barrier layers42or57while the display panel10is being carried or intentionally bent, for example, the resin layer54provided between the inorganic insulating film43B or45and the UC barrier layer42helps prevent the crack from expanding through the inorganic insulating film43B or45. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Modification Example C FIG.14illustrates a cross-sectional configuration taken along the line A-A inFIG.4according to one modification example.FIG.14illustrates an modification example of the cross-sectional configuration illustrated inFIG.12. In Modification Example B described above, the step portion43C is formed in the inorganic insulating film43B. However, in Modification Example B described above, the inorganic insulating film43B does not include the step portion43C, and the UC barrier layer42may include the step portion42A instead, as illustrated inFIG.14, for example. In this modification example, the surface of the end portion of the inorganic insulating film43B does not include step portion43C and is substantially flat. In contrast, the UC barrier layer42has the step portion42A, which is a thinned portion of the UC barrier layer42opposed to the end portion of the flexible substrate41. The portion of the UC barrier layer42opposed to the end portion of the flexible substrate41is thinner than the other portion of the UC barrier layer42opposed to the organic electroluminescent elements44A. The difference in thickness between the portion opposed to the end portion of the flexible substrate41and the portion opposed to the organic electroluminescent elements44A forms the step portion42A. The step portion42A is formed in the frame region10B. The step portion42A is formed so as not to be opposed to at least the mounting terminals53. For example, the step portion42A is formed along three sides of the frame region10B other than the side along which the mounting terminals53are formed. The mounting terminals53are formed in a region of the surface of the UC barrier layer42opposed to the flat region in which step portion42A is not formed. Alternatively, the step portion42A is formed on two sides of the frame region10B perpendicular to the side along which the mounting terminals53are formed. In such a case, the display panel10is foldable only in the direction perpendicular to the side of the frame region10B along which the mounting terminals53are formed. In this modification example, the resin layer54covers the portion of the UC barrier layer42other than the thinned portion of the UC barrier layer42. The end portion of the resin layer54may be formed on the step portion42A. In this case, the resin layer54is in contact with from a portion of the UC barrier layer42opposed to the TFT circuits43A to the step portion42A. The resin layer54may include polyimide, an epoxy resin, or an acrylic resin, for example. Accordingly, even if a crack generated in the end portion of the UC barrier layer42expands over the step portion42A, the resin layer54helps prevent the crack from expanding through the portion of the UC barrier layer42covered with the resin layer54. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the UC barrier layer42. Further, in this modification example, the end portion of the TFT layer43provided in the vicinity of the step portion42A may be exposed without being covered with the resin layer46, as illustrated inFIG.15, for example. Even in such a case, the resin layer46covers at least the portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45. Here, the end portion of the resin layer46is in contact with the surface of the inorganic insulating film43B in the region between the end portion of the inorganic insulating film45and the end portion of the inorganic insulating film43B. The step portion43D is formed at a portion where the end portion of the resin layer46is in contact with the surface of the inorganic insulating film43B. Accordingly, even if a crack is generated in the end portion of the inorganic insulating film43B, the resin layer46and the step portion43D help prevent the crack from expanding through the portions of the inorganic insulating films43B and45covered with the resin layer46. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Although the disclosure is described hereinabove with reference to the embodiments and modification examples, the disclosure is not limited thereto and may be modified in various ways. It should be appreciated that the effects described herein are mere examples, and the effects of the disclosure should not be limited to the effects described herein. The disclosure may provide effects other than those described herein. Modification Example D FIG.16illustrates the step portion42A in the UC barrier layer42or the step portion43C in the inorganic insulating film43B in an enlarged manner. In the foregoing embodiments and Modification Examples A, B, and C, the UC barrier layer42and the inorganic insulating film43B may have a configuration in which an insulating material constituting the bottom surfaces of the step portions42A and43C and an insulating material constituting the side surfaces of the step portions42A and43C are different from each other. In the foregoing embodiments and Modification Examples A, B, and C, the UC barrier layer42and the inorganic insulating film43B may each include the insulating film55constituting the bottom surface of the step portion42A or43C and the insulating film56constituting the side face of the step portion42A or43C, as illustrated inFIG.16, for example. In this case, the insulating film55may include an inorganic material of which etching rate is lower than that of the insulating film56in terms of a predetermined etching gas or a predetermined etchant. For example, in the case of dry etching using a fluorine-containing gas, a silicon nitride film has a larger etching rate than a silicon oxide film. Thus, for example, the insulating film56includes silicon nitride (SiNx), and the insulating film55includes silicon oxide (SiOx). In such a case, according to the foregoing embodiments and Modification Examples A, B, and C, the insulating film55serve as an etching stop layer when the UC barrier layer42and the inorganic insulating film43B are selectively etched. As a result, it is possible to precisely control the height of the step portions42A and43C in the manufacturing process. Modification Example E FIG.17illustrates a modification example of the cross-sectional configuration illustrated inFIG.4.FIG.18illustrates a modification example of the cross-sectional configuration illustrated inFIG.12. In the foregoing embodiments and Modification Example B, the resin layer46may be formed so as to be in contact with the entire surface of the inorganic insulating film45, to be in contact with from a portion of the inorganic insulating film43B in contact with the end portion of the inorganic insulating film45to the step portion43C, and to cover the step portion43C, as illustrated inFIGS.17and18, for example. In this case, the end portion of the resin layer46is formed so as to be in contact with the portion of the inorganic insulating film43B in the region between the end portion of the inorganic insulating film43B and the step portion43C. The step portion43D is formed in the portion where the end portion of the resin layer46is in contact with the surface of the inorganic insulating film43B. Such a structure is formed by, for example, selectively etching the TFT layer43using a film different from the polarization plate47as a mask to form the step portion43C, and then selectively etching the resin layer46using the polarization plate47having a size enough to cover the step portion43C as a mask to form the step portion43D. Accordingly, even if a crack generated in the end portion of the inorganic insulating film43B expands over the step portion43D, the resin layer46helps prevent the crack from expanding through the portions of the inorganic insulating films43B and45covered with the resin layer46. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the inorganic insulating film43B. Modification Example F FIG.19illustrates a modification example of the cross-sectional configuration illustrated inFIG.14. In Modification Example C described above, the resin layer54may be formed so as to cover the entire surface of the region of the UC barrier layer42opposed to the organic electroluminescent elements44A and to cover the step portion42A of the UC barrier layer42, as illustrated inFIG.19, for example. In this case, the end portion of the resin layer54is formed so as to be in contact with the portion of the UC barrier layer42in the region between the end portion of the UC barrier layer42and the step portion42A. The step42B is formed in the portion where the end portion of the resin layer54is in contact with the surface of the UC barrier layer42. Such a structure is formed by, for example, selectively etching the UC barrier layer42using a layer different from the polarization plate47to form the step portion42A, and then selectively etching the resin layer54using the polarization plate47having a size enough to cover the step portion42A as a mask to form the step42B. Accordingly, even if a crack generated in the end portion of the UC barrier layer42expands over the step portion42A, the resin layer54helps prevent the crack from expanding through the portion of the UC barrier layer42covered with the resin layer54. As a result, it is possible to suppress the occurrence of a display failure, such as a dark spot, due to the crack generated in the UC barrier layer42. Further, the disclosure may take the following configurations, for example.(1) A display panel including:a flexible substrate;a plurality of self-luminescent elements provided on a first main face of the flexible substrate;a plurality of thin film transistor (TFT) circuits provided between the first main face and the plurality of self-luminescent elements and driving the self-luminescent elements;a first inorganic film provided between the plurality of TFT circuits and the plurality of self-luminescent elements, covering the TFT circuits, and having a step portion, the step portion being a thinned portion of the first inorganic film opposed to an end portion of the flexible substrate;a second inorganic film covering the self-luminescent elements; anda resin layer covering the second inorganic film and covering at least a portion of the first inorganic film in contact with an end portion of the second inorganic film.(2) The display panel according to (1), in which an end portion of the resin layer is formed on the step portion.(3) The display panel according to (1), in which the resin layer is formed so as to cover the step portion.(4) The display panel according to any one of (1) to (3), further including:a plurality of mounting terminals electrically coupled to the plurality of TFT circuits; andflexible printed circuits (FPC) joined to the plurality of mounting terminals, in which,the step portion is formed in the first inorganic film at a position not opposed to the mounting terminals.(5) A display panel including:a flexible substrate;a plurality of self-luminescent elements provided on a first main face of the flexible substrate;a plurality of thin film transistor (TFT) circuits provided between the first main face and the plurality of self-luminescent elements and driving the self-luminescent elements;an inorganic film provided between the flexible substrate and the plurality of TFT circuits, covering the first main face, and having a step portion, the step portion being a thinned portion of the inorganic film opposed to an end portion of the flexible substrate; anda resin layer covering a portion of the inorganic film other than the thinned portion.(6) The display panel according to (5), in which an end portion of the resin layer is formed on the step portion.(7) The display panel according to (5), in which the resin layer is formed so as to cover the step portion.(8) The display panel according to any one of (5) to (7), further including:a plurality of mounting terminals electrically coupled to the plurality of TFT circuits; andflexible printed circuits joined to the plurality of mounting terminals, in which the step portion is formed in the inorganic film at a position not opposed to the mounting terminals.(9) A display apparatus including:a display panel; anda driver that drives the display panel, in whichthe display panel includesa flexible substrate,a plurality of self-luminescent elements provided on a first main face of the flexible substrate;a plurality of thin film transistor (TFT) circuits provided between the first main face and the plurality of self-luminescent elements and driving the self-luminescent elements,a first inorganic film provided between the plurality of TFT circuits and the plurality of self-luminescent elements, covering the TFT circuits, and having a step portion, the step portion being a thinned portion of the first inorganic film opposed to an end portion of the flexible substrate;a second inorganic film covering the self-luminescent elements; anda resin layer covering the second inorganic film and covering at least a portion of the first inorganic film in contact with an end portion of the second inorganic film.(10) The display apparatus according to (9), further including:a plurality of mounting terminals electrically coupled to the plurality of TFT circuits; andflexible printed circuits (FPC) joined to the plurality of mounting terminals and the driver, in whichthe step portion is formed in the first inorganic film at a position not opposed to the mounting terminals.(11) A display apparatus including:a display panel; anda driver that drives the display panel, in whichthe display panel includesa flexible substrate,a plurality of self-luminescent elements provided on a first main face of the flexible substrate,a plurality of thin film transistor (TFT) circuits provided between the first main face and the plurality of self-luminescent elements and driving the self-luminescent elements,an inorganic film provided between the flexible substrate and the plurality of TFT circuits, covering the first main face, and having a step portion, the step portion being a thinned portion of the inorganic film opposed to an end portion of the flexible substrate, anda resin layer covering a portion of the inorganic film other than the thinned portion.(12) The display apparatus according to (11), further including:a plurality of mounting terminals electrically coupled to the plurality of TFT circuits; andflexible printed circuits (FPC) joined to the plurality of mounting terminals and the driver, in whichthe step portion is formed in the inorganic film at a position not opposed to each of the mounting terminals. The present application claims priority based on Japanese Patent Application No. 2019-001931 filed with the Japan Patent Office on Jan. 9, 2019, the entire contents of which are incorporated herein by reference. It should be understood that those skilled in the art would make various modifications, combinations, sub-combinations, and alterations depending on design requirements and other factors, and they are within the scope of the attached claims or the equivalents thereof. | 44,441 |
11943959 | DETAILED DESCRIPTION In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology is employed for sake of clarity. However, the present disclosure is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents which operate in a similar manner. Like reference numerals in the drawings and specification may denote like or corresponding elements, and to the extent that repeated description has been omitted, it may be assumed that the omitted description is at least similar to that of corresponding elements that are described elsewhere in the specification. It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. It will be further understood that the terms “comprises/includes” and/or “comprising/including” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. However, the phrase, “consisting of” are used herein to preclude the presence or addition of other features or components. It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of elements in the drawings may be exaggerated for convenience of explanation. While the lengths, angles, thicknesses, and relative dispositions of the various elements shown in the figures may be interpreted as details pertaining to a particular example, it may be understood that changes may be made to these values without departing from the spirit or scope of the present disclosure. It is to be understood that the elements described herein with respect to particular embodiments may be re-combined to form different embodiments and the steps described herein may be rearranged to be performed in a different order and one or more of the described steps may be performed substantially simultaneously. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component or may be “indirectly connected” to the other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component or may be “indirectly electrically connected” to other layer, region, or component with other layer, region, or component interposed therebetween. In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. FIG.1is a plan view illustrating a display device10according to an exemplary embodiment of the present disclosure. Referring toFIG.1, the display device10may include a display area DA and a non-display area NDA that at least partially surrounds the display area DA. The display device10includes a plurality of pixel areas P arranged therein. A display element emitting light of a predetermined color may be arranged in each of the pixel areas P. The display element may be connected to a scan line SL and a data line DL. The display area DA and the non-display area NDA may each be a portion of a substrate100of the display device10. For example, it may be understood that the substrate100includes the display area DA and the non-display area NDA. A scan driver1100, a data driver1200, and a main power line may be arranged in the non-display area NDA. The scan driver1100provides a scan signal to each pixel area P through a scan line SL. The data driver1200provides a data signal to each pixel area P through a data line DL. The main power line provides a first power voltage and a second power voltage. Though it is shown inFIG.1that the data driver1200is arranged on the substrate100, the data driver1200may be arranged on a flexible printed circuit board (FPCB) electrically connected to a pad arranged on one side of the display device10. The display device10, according to an exemplary embodiment of the present disclosure, may include an organic light-emitting display, an inorganic light-emitting display, and a quantum dot display. Though a display device, according to an exemplary embodiment of the present disclosure, is described as being an organic light-emitting display device as an example, a display device according to the present disclosure is not limited thereto and characteristics described below are applicable to various types of display devices. FIG.2is a schematic diagram illustrating a display element and a pixel circuit PC connected thereto, the pixel circuit PC being arranged in one of the pixel areas of a display device according to an exemplary embodiment of the present disclosure. Referring toFIG.2, an organic light-emitting diode OLED, which is a display element, is connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. The organic light-emitting diode OLED may emit red, green, and blue light, or may emit red, green, blue, and white light. The second thin film transistor T2includes a switching thin film transistor and is connected to a scan line SL and a data line DL. The second thin film transistor T2transfers a data voltage input through the data line DL to the first thin film transistor T1in response to a switching voltage input through the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2and a driving voltage line PL and may carry a voltage corresponding to a difference between a voltage transferred from the second thin film transistor T2and a first power voltage ELVDD supplied through the driving voltage line PL. The first thin film transistor T1may be a driving thin film transistor, be connected to the driving voltage line PL and the storage capacitor Cst and may control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a predetermined brightness according to the driving current. An opposite electrode (e.g. a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS. Though it is described inFIG.2that the pixel circuit PC includes two thin film transistors and one storage capacitor, the number of thin film transistors and the number of storage capacitors may be variously changed depending on a design of the pixel circuit PC. FIGS.3and4are cross-sectional views illustrating a portion of a display device according to an exemplary embodiment of the present disclosure. Referring toFIGS.3and4, a pixel circuit layer PCL is arranged on the substrate100, and the organic light-emitting diode OLED, which is a display element, is arranged on the pixel circuit layer PCL and is covered by a thin-film encapsulation layer300. The pixel circuit layer PCL includes the pixel circuit PC. The substrate100may include a glass material or a polymer resin. The substrate100including a polymer resin may be flexible, rollable, and/or bendable. In an exemplary embodiment of the present disclosure, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104as shown inFIG.3. The first base layer101and the second base layer103may include a polymer resin. For example, the first base layer101and the second base layer103may include a polymer resin including polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose tri acetate (TAC) and/or cellulose acetate propionate (CAP). The first barrier layer102and the second barrier layer104are barrier layers preventing the penetration of external foreign substances and may include a single layer or a multi-layer structure including an inorganic material such as silicon nitride and silicon oxide. According to an exemplary embodiment of the present disclosure, the substrate100may include a single layer including a glass material as shown inFIG.4. For example, the substrate100may include a glass substrate including SiO2as a main component thereof. The pixel circuit layer PCL on the substrate100may include a thin film transistor TFT. The pixel circuit layer PCL may include a storage capacitor connected to the thin film transistor TFT. The transistor TFT may have the same structure for each pixel. Each thin film transistor TFT may be connected to a display element provided to each pixel. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The semiconductor layer Act includes amorphous silicon, polycrystalline silicon, and/or an organic semiconductor material. To secure insulation between the semiconductor layer Act and the gate electrode GE, a gate insulating layer121may be arranged between the semiconductor layer Act and the gate electrode GE. The gate insulating layer121includes an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride. An interlayer insulating layer131may be arranged on the gate electrode GE. The interlayer insulating layer131includes an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride. The source electrode SE and the drain electrode DE may each be arranged on the interlayer insulating layer131. The insulating layer includes an inorganic material that may be formed by chemical vapor deposition (CVD) and/or atomic layer deposition (ALD). The gate electrode GE, the source electrode SE, and the drain electrode DE may include various conductive materials. The gate electrode GE may include molybdenum or aluminum and may have a single-layered or multi-layered structure. For example, the gate electrode GE may include a single molybdenum layer, or may have a three-layered structure including a molybdenum layer, an aluminum layer, and a molybdenum layer. The source electrode SE and the drain electrode DE may each include titanium or aluminum and may each have a single-layered or multi-layered structure. In an exemplary embodiment of the present disclosure, the source electrode SE and the drain electrode DE may each have a three-layered structure including a titanium layer, an aluminum layer, and a titanium layer. A buffer layer110may be arranged between the thin film transistor TFT having the above-described structure and the substrate100. The buffer layer110includes an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride. The buffer layer110may increase flatness of a top surface of the substrate100or may prevent or minimize the penetration of impurities into the semiconductor layer Act of the thin film transistor TFT from the substrate100. A planarization insulating layer140may be arranged on the thin film transistor TFT. The planarization insulating layer140may include an organic material such as acryl, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The planarization insulating layer140may be a single layer or the planarization insulating layer140may be a multi-layer structure. The organic light-emitting diode OLED includes a pixel electrode221, an intermediate layer222, and an opposite electrode223. The pixel electrode221may be arranged on the planarization insulating layer140and may be arranged one-by-one for every pixel. The pixel electrode221may include a reflective electrode. In an exemplary embodiment of the present disclosure, the pixel electrode221may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Jr, and/or Cr. In an exemplary embodiment of the present disclosure, the pixel electrode221may include a transparent or semi-transparent electrode layer arranged on/under the reflective layer. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and/or aluminum zinc oxide (AZO). In an exemplary embodiment of the present disclosure, a pixel electrode221may have a three-layered structure of an ITO layer, an Ag layer, and an ITO layer. A pixel-defining layer150is arranged on the pixel electrode221. The pixel-defining layer150includes an opening150OP exposing a central portion of each pixel electrode221. The pixel-defining layer150may prevent an arc, etc. from occurring at the edges of the pixel electrode221by increasing a distance between the opposite electrode223and the edges of the pixel electrode221. The pixel-defining layer150may include an organic insulating material such as polyimide, polyamide, an acrylic resin, BCB, HMDSO, and a phenolic resin, and may be formed by a method such as spin coating. An emission layer222bmay be arranged on a portion of the pixel electrode221that is exposed through the opening150OP of the pixel-defining layer150. The emission layer222bmay include an organic material including a fluorescent or phosphorous material that may emit red, green, or blue light. The organic material may include a low molecular weight organic material or a polymer organic material. A first functional layer222aand a second functional layer222cmay be respectively arranged under and on the emission layer222b. The first functional layer222amay include, for example, a hole transport layer (HTL), or include an HTL as well as a hole injection layer. The second functional layer222cis an element arranged on the emission layer222band may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The second functional layer222cis optional and may be omitted. In an exemplary embodiment of the present inventive concept, the second functional layer222cmay be omitted. The emission layers222bare arranged so as to respectively correspond to openings of the pixel-defining layer150. In contrast, like the opposite electrode223described below, the first functional layer222aand the second functional layer222cmay be common layers each formed as one body so as to entirely cover the substrate100, for example, so as to entirely cover the display area DA of the substrate100. The opposite electrode223may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Jr, Cr, Li, and/or Ca. Alternatively, the opposite electrode223may further include a layer including ITO, IZO, ZnO, and/or In2O3on the (semi) transparent layer including the above materials. In an exemplary embodiment of the present disclosure, the opposite electrode223may include Ag, Mg, or an alloy of Ag and Mg. A capping layer230may be located on the opposite electrode223. For example, the capping layer230may include LiF, an inorganic insulating material, or an organic insulating material. In an exemplary embodiment of the present disclosure, the capping layer230may be omitted. The thin-film encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin-film encapsulation layer300includes a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330, and includes an auxiliary layer315between the first inorganic encapsulation layer310and the organic encapsulation layer320, as shown inFIG.4. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may include an inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride. In an exemplary embodiment of the present disclosure, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may each include an inorganic insulating layer including a non-metal element, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. The number and a kind of non-metal elements included in the first inorganic encapsulation layer310may be different from the number and a kind of non-metal elements included in the second inorganic encapsulation layer330. For example, the first inorganic encapsulation layer310may include silicon oxynitride, and the second inorganic encapsulation layer330may include silicon nitride. The first inorganic encapsulation layer310may have a thickness T ranging from about 600 nm to about 2200 nm (600 nm≤T≤2200 nm). In the case where the thickness of the first inorganic encapsulation layer310deviates from the lower limit (for example, less than 600 nm), moisture transmission may occur. In the case where the thickness of the first inorganic encapsulation layer310deviates from the upper limit, the first inorganic encapsulation layer310may exfoliate or separate. A thickness of the second inorganic encapsulation layer330may be the same as, less than, or greater than the thickness of the first inorganic encapsulation layer310. The organic encapsulation layer320may alleviate inner stress of the first inorganic encapsulation layer310and/or the second inorganic encapsulation layer330. The organic encapsulation layer320may include a polymer-based material. The polymer-based material may include PET, PEN, PC, PI, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, an acrylic-based resin (for example, polymethylmethacrylate, poly acrylic acid, etc.), or an arbitrary combination thereof. The organic encapsulation layer320may be formed by coating with a monomer having fluidity and then hardening a monomer layer by using heat or light such as an ultraviolet ray. Alternatively, the organic encapsulation layer320may be formed by coating with a polymer-based material. The auxiliary layer315is arranged between the first inorganic encapsulation layer310and the organic encapsulation layer320. The auxiliary layer315may directly contact the first inorganic encapsulation layer310and the organic encapsulation layer320. For example, a bottom surface of the auxiliary layer315may directly contact a top surface of the first inorganic encapsulation layer310, and a top surface of the auxiliary layer315may directly contact a bottom surface of the organic encapsulation layer320. The auxiliary layer315may include an inorganic insulating layer including a non-metal element. In an exemplary embodiment of the present disclosure, a non-metal element included in the auxiliary layer315may be the same non-metal element as that of the first inorganic encapsulation layer310. The non-metal element may include, for example, Si, O, and/or N. Light emitted from an organic light-emitting diode OLED arranged for each pixel passes through the thin-film encapsulation layer300and progresses to the outside. In this case, due to a thin-film interference phenomenon of the thin-film encapsulation layer300, an image viewed by the user may seem reddish (e.g. each color may look more red than it should) when the image is viewed in an oblique direction with respect to a direction (e.g. a z-direction) perpendicular to the substrate100(e.g. when viewed from a side angle as opposed to straight on). However, since the thin-film encapsulation layer300includes the auxiliary layer315, the reddish image issue may be prevented. A specific characteristic of the thin-film encapsulation layer300is described below with reference toFIG.5. FIG.5is a cross-sectional view illustrating the display device10according to an exemplary embodiment of the present disclosure. Referring toFIG.5, the display device10includes the substrate100, the pixel circuit layer PCL, a display layer200, and the thin-film encapsulation layer300that are sequentially stacked. The display layer200includes the pixel electrode221, the intermediate layer222, the opposite electrode223, and the capping layer230. The thin-film encapsulation layer300may include the first inorganic encapsulation layer310and the auxiliary layer315that are sequentially stacked in a progressing direction of light (or a direction facing the thin-film encapsulation layer300from the display layer200). The organic encapsulation layer320and the second inorganic encapsulation layer330may be arranged on the auxiliary layer315. Though a method of adjusting a thickness of the first inorganic encapsulation layer310may be considered as a method of resolving the above-mentioned reddish issue, it might not be easy to control the thickness thereof due to the limitations of the manufacturing equipment being used (e.g. CVD equipment) for forming the first inorganic encapsulation layer310. For example, the first inorganic encapsulation layer310may have a thickness ranging from about 600 nm to about 2200 nm, as described above, so as to protect the display layer200from moisture, etc. and to prevent the separation of the first inorganic encapsulation layer310. In the case where a margin for error of equipment for forming an inorganic insulating layer is about 10%, since a thickness deviation of the first inorganic encapsulation layer310that is actually formed corresponds to the range from tens of nm to hundreds of nm, it is practically difficult to control the thickness of the first inorganic encapsulation layer310and thus there is a limit in resolving the above-described reddish issue. The thin-film encapsulation layer300, according to an exemplary embodiment of the present disclosure, has an advantage of easily solving the reddish issue without being limited by the thickness of the first inorganic encapsulation layer310, by arranging the auxiliary layer315on the first inorganic encapsulation layer310. The auxiliary layer315may include an inorganic insulating material. To minimize or prevent the reddish issue, a thickness t of the auxiliary layer315may be less than about 100 nm. For example, the thickness t of the auxiliary layer315may be equal to or greater than 30 nm and less than 100 nm (30 nm≤t<100 nm). FIG.6is a graph illustrating a minimum perception color difference (MPCD) depending on a thickness change of the first inorganic encapsulation layer310and a thickness change of the auxiliary layer315. InFIG.6, the MPCD is shown as a contour by dividing a predetermined section. When an MPCD has a (−) value in a direction away from zero, the MPCD represents reddish. When MPCD has a (+) value in a direction away from zero, the MPCD represents greenish.FIG.6shows simulation results in the case where the first inorganic encapsulation layer310and the auxiliary layer315respectively include silicon oxynitride layers having different refractive indexes. The contour of the MPCD is shown based on MPCD values when the display device10is viewed in an oblique direction with respect to a direction perpendicular to the substrate100, for example, when viewed at an oblique angle of about 30° (θ=30°) with respect to a z-direction, as shown inFIG.5. Referring toFIG.6, it is found that a change in the MPCD is small when the thickness t of the auxiliary layer315is in the range of 30 nm≤t<100 nm. When the thickness of the auxiliary layer315meets the above-described range, the reddish issue may be minimized or prevented without being limited by the thickness T of the first inorganic encapsulation layer310. The auxiliary layer315may include an inorganic insulating material. In the inorganic insulating material formed by CVD equipment, a thickness of the inorganic insulating material that is actually formed may have an error of about 10% compared to a target thickness as described above. Since, like the first inorganic encapsulation layer310, the auxiliary layer315may be formed by using CVD equipment, a thickness of the auxiliary layer315that is actually formed may be different from a target thickness. However, since a thickness of the auxiliary layer315is one tenth of the thickness of the first inorganic encapsulation layer310, or smaller, controlling a thickness of the auxiliary layer315is much easier even though a thickness error (e.g. an error of about 10%) of the CVD equipment is taken into account. In the case where the auxiliary layer315deviates from the above-described thickness range, for example, deviates from the lower limit, a change in an MPCD increases. In the case where the auxiliary layer315deviates from the upper limit, a change in an MPCD increases and/or it is difficult to control the thickness of the auxiliary layer315. Therefore, it is difficult to expect the auxiliary layer315to prevent the reddish issue without being limited by the thickness of the first inorganic encapsulation layer310. As described above, the auxiliary layer315may include an inorganic insulating material including a non-metal element. In an exemplary embodiment of the present disclosure, the auxiliary layer315may include the same non-metal element as that of the first inorganic encapsulation layer310. For example, the auxiliary layer315and the first inorganic encapsulation layer310may each include Si, O, and N. Therefore, the first inorganic encapsulation layer310and the auxiliary layer315may be formed by changing composition of a gas in the same CVD equipment (or the same chamber). For example, the auxiliary layer315and the first inorganic encapsulation layer310may include silicon nitride layers having different Si, O, and N contents/concentrations. A gas composition during a process of forming the first inorganic encapsulation layer310may be different from a gas composition during a process of forming the auxiliary layer315. Therefore, there may be an interface between them, as shown inFIG.5. The first inorganic encapsulation layer310and the auxiliary layer315may have different refractive indexes. For example, a refractive index n3 of the auxiliary layer315may meet the condition below. min(n1,n2)+n2-n1×0.25<n3<min(n1,n2)+n2-n1×0.75 Here, n1 is a refractive index of the first inorganic encapsulation layer310, n2 is a refractive index of the organic encapsulation layer320, and min (n1, n2) is a minimum value of n1 and n2, and |n2−n1| is an absolute value of a difference between n2 and n1. In the case where the refractive index n3 of the auxiliary layer315deviates from the above range, the MPCD may change substantially and thus it is difficult to prevent the reddish issue. FIG.7is a graph illustrating an MPCD depending on a thickness change of the first inorganic encapsulation layer310and a refractive index change of the auxiliary layer315. Like inFIG.6, the MPCD is simulation results in the case where the first inorganic encapsulation layer310and the auxiliary layer315respectively include silicon oxynitride layers and the display device10is viewed at a location that is oblique with respect to a direction perpendicular to the substrate100, for example, when viewed at an oblique angle of about 30° (θ=30°) with respect to a z-direction ofFIG.5. Referring toFIG.7, in the case where a refractive index of the auxiliary layer315is in the range from about 1.57 to about 1.70, a change in the MPCD is relatively small. A refractive index of the auxiliary layer315may be less than a refractive index of the first inorganic encapsulation layer310. FIG.8is a block diagram of the display device10according to an exemplary embodiment of the present disclosure. Referring toFIG.8, the display device10may include the substrate100, the pixel circuit layer PCL, the display layer200, and a thin-film encapsulation layer300′. The thin-film encapsulation layer300′ may further include a bottom layer325arranged under the organic encapsulation layer320. Since the rest of the elements except for the bottom layer325are the same as those of the embodiment described with reference toFIGS.5to7, the bottom layer325is mainly described below. The bottom layer325need not function as a thin-film encapsulation layer, for example, it might transmit moisture. The bottom layer325may control a material constituting the organic encapsulation layer320during a process of forming the organic encapsulation layer320by coating and hardening a monomer. As described above, the bottom layer325does not only have a moisture transmission characteristic but also has a separate optical function. A refractive index of the bottom layer325may be substantially the same as a refractive index of the organic encapsulation layer320. Because the refractive index of the bottom layer325may be substantially the same as the refractive index of the organic encapsulation layer320, a difference Δn between the refractive index of the bottom layer325and the refractive index of the organic encapsulation layer320is less than 0.05. In an exemplary embodiment of the present disclosure, the refractive index of the bottom layer325may be about 1.52. A thickness of the bottom layer325may be in the range from about 500 Å to about 1000 Å. For example, the thickness of the bottom layer325may be within a range from about 550 Å to about 900 Å, or from about 600 Å to about 850 Å. Because a refractive index of the bottom layer325is substantially the same as a refractive index of the organic encapsulation layer320, with the bottom layer325including a different material from that of the organic encapsulation layer320, there is an interface between the bottom layer325and the organic encapsulation layer320. The bottom layer325may include an inorganic insulating layer. In an exemplary embodiment of the present disclosure, the bottom layer325may include the same non-metal element as those of the first inorganic encapsulation layer310and the auxiliary layer315, or may include a non-metal element different from a non-metal element included in the first inorganic encapsulation layer310and the auxiliary layer315. For example, the bottom layer325may include an inorganic insulating layer having relatively high oxygen content, for example, the bottom layer325may include an oxygen rich silicon oxynitride layer. In an exemplary embodiment of the present disclosure, each of the first inorganic encapsulation layer310, the auxiliary layer315, and the bottom layer325may include the same non-metal element, for example, Si, O, and N. A first silicon oxynitride layer as the first inorganic encapsulation layer310, a second silicon oxynitride layer as the auxiliary layer315, and a third silicon oxynitride layer as the bottom layer325, may respectively include different Si, O, and No content ratios and/or concentrations. Therefore, there may be interfaces between the first silicon oxynitride layer and the second silicon oxynitride layer, and between the second silicon oxynitride layer and the third silicon oxynitride layer. FIG.9is a cross-sectional view illustrating a portion of the display device10according to an exemplary embodiment of the present disclosure. Referring toFIG.9, an organic light-emitting diode OLED, as a display element, is arranged in each pixel of the substrate100. Each organic light-emitting diode OLED may be electrically connected to a thin film transistor TFT provided to the pixel circuit layer PCL. The substrate100, the pixel circuit layer PCL, and the organic light-emitting diode OLED may be the same as those described above with reference toFIG.3. The organic light-emitting diode OLED for each pixel may be covered by the thin-film encapsulation layer300′. The thin-film encapsulation layer300′ may include the first inorganic encapsulation layer310, the auxiliary layer315, the bottom layer325, the organic encapsulation layer320, and the second inorganic encapsulation layer330that are sequentially stacked in a direction (e.g. the z-direction) away from the substrate100, for example, in the recited order. The first inorganic encapsulation layer310, the auxiliary layer315, the bottom layer325, the organic encapsulation layer320, and the second inorganic encapsulation layer330may be the same as those described with reference toFIGS.3to8. The first inorganic encapsulation layer310, the auxiliary layer315, and the bottom layer325may include different non-metal elements or the same non-metal elements. The non-metal element may include, for example, Si, O, and N. In an exemplary embodiment of the present disclosure, the first inorganic encapsulation layer310, the auxiliary layer315, and the bottom layer325may each include a silicon oxynitride layer including Si, O, and N. However, characteristics, for example, refractive indexes of the first inorganic encapsulation layer310, the auxiliary layer315, and the bottom layer325may be different from one another. The third silicon oxynitride layer as the bottom layer325has a relatively high oxygen content (e.g. is oxygen rich), and a refractive index of the third silicon oxynitride layer may be less than refractive indexes of the first silicon oxynitride layer as the first inorganic encapsulation layer310and the second silicon oxynitride layer as the auxiliary layer315. Even though the first inorganic encapsulation layer310, the auxiliary layer315, and the bottom layer325each include the same non-metal elements, they are formed during separate processes. A process of forming the first inorganic encapsulation layer310, a process of forming the auxiliary layer315, and a process of forming the bottom layer325are sequentially performed in separate processes (e.g. with different ratios of a reaction gas or with different kinds of a reaction gas in the same chamber). The auxiliary layer315is arranged right on the first inorganic encapsulation layer310, and the bottom layer325is arranged right on the auxiliary layer315. There are interfaces between the first inorganic encapsulation layer310and the auxiliary layer315and between the auxiliary layer315and the bottom layer325. These interfaces may be visible to an observer, in a cross-sectional view. A process of forming the organic encapsulation layer320may be performed after the process of forming the bottom layer325. A process of forming the second inorganic encapsulation layer330may be performed after the process of forming the organic encapsulation layer320. Therefore, the bottom layer325and the organic encapsulation layer320contact each other and a contact surface therebetween is visible to an observer on a cross-sectional view. Likewise, the organic encapsulation layer320and the second inorganic encapsulation layer330contact each other, and a contact surface therebetween is visible to an observer on a cross-sectional view. Though it is described inFIG.9that the substrate100includes a polymer resin, the substrate100shown inFIG.9may alternatively include a glass material described with reference toFIG.4. FIGS.10A to10Dare graphs showing MPCD depending on a viewing angle θ in accordance with exemplary embodiments of the present disclosure.FIGS.10E and10Fare graphs showing MPCD depending on a viewing angle θ in accordance with comparative examples. FIG.10Ashows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 1100 nm, and the auxiliary layer315includes a silicon oxynitride layer having a refractive index of about 1.62 and a thickness of about 70 nm. FIG.10Bshows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 1170 nm, and the auxiliary layer315includes a silicon oxynitride layer having a refractive index of about 1.62 and a thickness of about 70 nm. FIG.10Cshows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 900 nm, and the auxiliary layer315includes a silicon oxynitride layer having a refractive index of about 1.62 and a thickness of about 70 nm. FIG.10Dshows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 1100 nm, and the auxiliary layer315includes a silicon oxynitride layer having a refractive index of about 1.62 and a thickness of about 40 nm. FIG.10Eshows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 1100 nm, and the auxiliary layer315includes a silicon oxynitride layer having a refractive index of about 1.62 and a thickness of about 100 nm. FIG.10Fshows results of an MPCD depending on a viewing angle θ after manufacturing two hundred samples in which the first inorganic encapsulation layer310includes a silicon oxynitride layer having a refractive index of about 1.77 and a thickness of about 1200 nm, and the auxiliary layer315is absent. Information for each sample is summarized in Table 1 below. TABLE 1Thin-film encapsulation layerFirst inorganicencapsulation layerAuxiliary layerEmbodiment #1SiON (n1: 1.77,SiON (n3: 1.62,T: 1100 nm)t: 70 nm)Embodiment #2SiON (n1: 1.77,SiON (n3: 1.62,T: 1170 nm)t: 70 nm)Embodiment #3SiON (n1: 1.77,SiON (n3: 1.62,T: 900 nm)t: 70 nm)Embodiment #4SiON (n1: 1.77,SiON (n3: 1.62,T: 1100 nm)t: 40 nm)ComparativeSiON (n1: 1.77,SiON (n3: 1.62,example #1T: 1100 nm)t: 100 nm)ComparativeSiON (n1: 1.77,Not availableexample #2T: 1200 nm) Referring toFIGS.10A to10D and10E and10F, it is found that a reddish image is viewed at a viewing angle of 30° from the surface of the display in the case where a thickness of the auxiliary layer315is 100 nm or there is no auxiliary layer315. It is found that the reddish issue is resolved in all of the embodiments in which the thickness range of the auxiliary layer315meets the above-described condition. A display device according to exemplary embodiments of the present disclosure may prevent a color deviation of light emitted from display elements and encapsulate the display elements from external impurities while minimizing a thickness of the display device. However, the scope of the present disclosure is not limited by these effects. It should be understood that embodiments described herein should be considered in a descriptive sense and various changes may be possible within the spirit and scope of the present disclosure. It is to be understood that the features and properties shown and described with respect to any one figure may be mixed and matched with the features and properties shown and described with respect to any other figure. | 39,975 |
11943960 | DESCRIPTION OF THE PREFERRED EMBODIMENTS As used herein, spatial or directional terms, such as “left”, “right”, “inner”, “outer”, “above”, “below”, and the like, relate to the invention as it is shown in the drawing FIGURE. However, it is to be understood that the invention can assume various alternative orientations and, accordingly, such terms are not to be considered as limiting. Further, as used herein, all numbers expressing dimensions, physical characteristics, processing parameters, quantities of ingredients, reaction conditions, and the like, used in the specification and claims are to be understood as being modified in all instances by the term “about”. Accordingly, unless indicated to the contrary, the numerical values set forth in the following specification and claims may vary depending upon the desired properties sought to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical value should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Moreover, all ranges disclosed herein are to be understood to encompass the beginning and ending range values and any and all subranges subsumed therein. For example, a stated range of “1 to 10” should be considered to include any and all subranges between (and inclusive of) the minimum value of 1 and the maximum value of 10; that is, all subranges beginning with a minimum value of 1 or more and ending with a maximum value of 10 or less, e.g., 1 to 3.3, 4.7 to 7.5, 5.5 to 10, and the like. Additionally, all documents, such as but not limited to, issued patents and patent applications, referred to herein are to be considered to be “incorporated by reference” in their entirety. Any reference to amounts, unless otherwise specified, is “by weight percent”. For purposes of the following discussion, the invention will be discussed with reference to a conventional OLED device. However, it is to be understood that the invention is not restricted to use with OLED devices but could be practiced in other fields, such as, but not limited to, photovoltaic thin film solar cells. For other uses, such as thin film solar cells, the glass architecture described later in this application might have to be modified. An OLED device10incorporating features of the invention is shown inFIG.1. The OLED device10includes a cathode12, an emissive layer14, and an anode18. However, unlike conventional OLED devices, the OLED device10includes a substrate20incorporating features of the invention. The structure and operation of a conventional OLED device will be well understood by one of ordinary skill in the art and, therefore, will not be described in detail. An exemplary OLED device is described in U.S. Pat. No. 7,663,300. The cathode12can be any conventional OLED cathode. Examples of suitable cathodes include metals, such as but not limited to, barium and calcium. The cathode typically has a low work function. The emissive layer14can be a conventional organic electroluminescent layer as known in the art. Examples of such materials include, but are not limited to, small molecules such as organometallic chelates (e.g., Alq3), fluorescent and phosphorescent dyes, and conjugated dendrimers. Examples of suitable materials include triphenylamine, perylene, rubrene, and quinacridone. Alternatively, electroluminescent polymeric materials are also known. Examples of such conductive polymers include poly(p-phenylene vinylene) and polyfluorene. Phosphorescent materials could also be used. Examples of such materials include polymers such as poly(n-vinylcarbazole) in which an organometallic complex, such as an iridium complex, is added as a dopant. The anode18can be a conductive, transparent material, such as a metal oxide material, such as, but not limited to, indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO). The anode typically has a high work function. Unlike conventional OLED devices, the OLED device10is carried on a substrate20incorporating features of the invention. The substrate20is a transparent substrate having a first surface24and a second surface26. Examples of suitable materials for the substrate20include, but are not limited to, glass, such as conventional soda-lime silicate glass, for example, float glass. The substrate20has a high visible light transmission at a reference wavelength of 550 nanometers (nm) and a reference thickness of 3.2 mm. By “high visible light transmission” it is meant visible light transmission at 550 nm of greater than or equal to 85%, such as greater than or equal to 87%, such as greater than or equal to 90%, such as greater than or equal to 91%, such as greater than or equal to 92%, such as greater than or equal to 93%, such as greater than or equal to 95%, at a 3.2 mm reference thickness. Non-limiting examples of glass that can be used for the practice of the invention include, but are not limited to, Starphire®, Solarphire®, Solarphire® PV, and CLEAR™ glass, all commercially available from PPG Industries, Inc. of Pittsburgh, Pennsylvania. The substrate20can have any desired thickness, such as in the range of 0.5 mm to 10 mm, such as 1 mm to 10 mm, such as 1 mm to 4 mm, such as 2 mm to 3.2 mm. The substrate20incorporates at least one of: (1) a first (e.g., an internal) light extraction layer or region30; and/or (2) a second (e.g., an external) light extraction layer or region32. Adding light extraction regions in the substrate reduces the waveguide effect described above so that less light is reflected back from the various interfaces, and less light is trapped inside the device. This allows more light to be emitted from the device. The first extraction region30is formed by nanoparticles34incorporated on the first surface24of the substrate20or embedded in or incorporated into a region of the glass adjacent the first surface24. Examples of suitable nanoparticles34include, but are not limited to, oxide nanoparticles, such as but not limited to alumina, titania, cerium oxide, zinc oxide, tin oxide, silica, and zirconia. These oxide nanoparticles can be incorporated into the substrate20at a depth in the range of 0 microns to 50 microns, such as 0 microns to 10 microns, such as 0 micron to 5 microns, such as 0 microns to 3 microns. The first surface24incorporating the first extraction region30can be smoother than the second surface26. For example, the first surface24can have an average surface roughness (Ra) up to 100 nm, such as up to 50 nm, such as up to 20 nm, such as up to 10 nm, such as up to 5 nm, such as in the range of 1 nm to 100 nm, such as in the range of 1 nm to 50 nm, such as 1 nm to 20 nm, such as 1 nm to 10 nm, such as 1 nm to 5 nm. The external extraction region32can be formed by a coating, such as a metal oxide coating having a roughened exterior surface. Examples of oxides useful for the external extraction layer32include, but are not limited to, silica, alumina, zinc oxide, titania, zirconia, tin oxide, and mixtures thereof. The external extraction layer32can have an average surface roughness (Ra) in the range of 5 nm to 500 nm, such as 5 nm to 500 nm, such as 50 nm to 500 nm, such as 50 nm to 200 nm, such as 100 nm to 200 nm and/or a root mean square roughness (Rq) in the range of 100 nm to 250 nm, such as 150 nm to 200 nm. The coating can have a thickness in the range of 10 nm to 500 nm, such as 50 nm to 500 nm, such as 100 nm to 500 nm. The external extraction layer32can be a single layer or optionally a multilayer coating. Alternatively, the external extraction region32can be formed by texturing the second surface26of the glass rather than applying a separate coating layer. For example, the second surface26can be scored or cut to form a textured surface. The first extraction region30and second extraction region32can provide the substrate20with haze in the range of 1% to 100%, such as 1% to 90%, such as 1% to 80%, such as 1% to 60%, such as 1% to 50%, such as 10% to 80%, such as 10% to 40%, as measured by a conventional Haze-Gard Plus hazemeter, commercially available from BYK-Gardner. Operation of the OLED device10will now be described with particular reference toFIG.1. During operation, a voltage is applied across the anode18and the cathode12. A current of electrons flows from the cathode12to the anode18through the emissive layer14. This electric current causes the emissive layer14to emit light. The substrate20of the invention provides for increased light extraction as compared to an OLED device without the substrate20. Electromagnetic radiation in the form of light waves emitted by the emissive layer14travels through the anode18into the substrate20. These light waves encounter the internal extraction layer30and become more scattered, causing the light waves to travel more randomly through the substrate20. When the light waves exit the substrate20at the second surface26, the roughened surface of the external extraction layer32causes further scattering of the light waves. The combination of the internal extraction layer30scattering and external extraction layer32scattering increases the overall light extraction for the OLED device10by decreasing the wave guide effect. While the above embodiment contemplates the presence of both the internal extraction layer30and the external extraction layer32, in other embodiments only one or the other of these layers need be present. An exemplary method of forming a substrate of the invention will now be described. In a float glass process, glass batch materials are melted in a furnace to form a glass melt. The glass melt is poured into a float chamber having a bath of molten metal, such as a molten tin bath. The molten glass spreads across the surface of the molten metal to form a glass ribbon. In one practice of the invention, a flame spray device or combustion deposition device is mounted in the float chamber above the glass ribbon. A suitable flame spray device is commercially available from Beneq-Oy Vantaa, Finland. Another flame spray device is described in WO 01/28941. In the flame spray device, coating materials are atomized, combusted, and then sprayed directly onto the hot float glass ribbon. The particles34are formed on and/or diffused into the surface of the ribbon or penetrate the surface and are incorporated into the upper portion of the float glass ribbon. These particles34, such as metal oxide nanoparticles, are present on the surface of the glass or are diffused into the glass and react with the glass matrix. This process can be practiced at any suitable place in the float chamber but is believed to be more practical at locations where the temperature of the float glass ribbon is in the range of 400° C. to 1,000° C., such as 500° C. to 900° C., such as 500° C. to 800° C., such as 600° C. to 800° C., such as 700° C. to 800° C. As the float ribbon exits the float chamber, the glass has nanoparticles34embedded in the surface of the glass sheet or incorporated into a region of the glass adjacent the upper surface of the glass. These nanoparticles34define the first extraction region30. During the incorporation process of nanoparticles34in the glass surface at an elevated temperature, the glass surface smoothes out by softening at high temperature. The glass can be heat treated or annealed in a conventional manner. In a non-float process, the substrate can be heated, such as in a furnace, by a flame, or by another heat source, until the glass surface has softened. The nanoparticles can then be directed or propelled at the softened surface, such as by a carrier gas. As will be appreciated, the temperature of the substrate is one factor in determining how far the nanoparticles penetrate into the substrate. As will be appreciated, the lower the viscosity of the substrate, the farther the nanoparticles should penetrate. A suitable deposition process is described in U.S. Pat. No. 7,851,016. After the internal extraction layer30has been formed (e.g., after the glass has left the float chamber in a float glass process), the external extraction layer32can be provided. For example, the external extraction layer32can be formed by applying a coating, such as a metal oxide coating, onto the surface of the glass opposite the surface having the nanoparticles34incorporated therein. This can be accomplished in any conventional manner, such as by conventional sol-gel or spray pyrolysis methods, inside an annealing lehr, or at the exit of the annealing lehr, where the temperature is in the range of 50° C. to 600° C., such as 100° C. to 400° C., such as 150° C. to 350° C., such as 200° C. to 300° C. The resultant substrate thus incorporates both the first (i.e., internal) extraction layer30and the second (i.e., external) extraction layer32. However, in the broad practice of the invention, only one of these extraction regions need be present. As an additional step (either on-line or off-line), a conductive metal oxide layer to form the anode18can be applied in any conventional manner over the first surface24of the glass substrate20. For example, a layer of indium tin oxide or aluminum doped zinc oxide can be applied by magnetron sputter vapor deposition, chemical vapor deposition, or any other suitable method to form the anode. The anode18can be deposited before or after the deposition of the first extraction region30by an on-line process, or after the deposition of both the first extraction region30and the second extraction layer32. In addition, an optional underlayer coating stack (such as described in U.S. Publication Nos. 2010/0285290, 2010/0124642, or 2010/0124643) can be incorporated under the anode18(i.e., between the anode18and the substrate20) to increase the transmittance of the substrate20with the underlayer coating stack and the anode18and at least one of the internal extraction region30or the external extraction region32. The substrate20with the conductive anode18and at least one of the internal extraction region30or the external extraction region32can then be supplied to an OLED manufacturer who can subsequently apply the emissive layer14and the cathode12to form an OLED incorporating the light extraction substrate20. Examples of the invention will now be described. However, it is to be understood that the invention is not limited to these specific examples. EXAMPLES In the following Examples, the substrate (unless indicated to the contrary) is Solarphire® glass commercially available from PPG Industries Ohio, Inc. having a thickness of 2 millimeters (mm). The haze and transmittance values are percentage values and were measured using a Haze-Gard Plus hazemeter commercially available from BYK-Gardner USA. The temperature values are in degrees Fahrenheit (° F.) and the pressure values are in pounds per square inch (psi). Example 1 This Example illustrates a substrate with an external extraction layer on one side. TEOS means tetraethyl orthosilicate; TPT means titanium isopropoxide; DI water means deionized water; and IPA means isopropyl alcohol. A first solution (as set forth in Table 1) and a second solution (as set forth in Table 2) were prepared. The TPT was added to adjust the refractive index of the coating. TABLE 1(SOLUTION 1)MATERIALAMT. (g)PERCENT(%)TPT5024IPA5024HNO3105DI Water10048Total210100 TABLE 2(SOLUTION 2)MATERIALAMT. (g)PERCENT(%)TEOS8021Ethanol28072DI Water287Total388100 These solutions were mixed in the proportions shown in Table 3 and Table 4 to form coating composition1(Table 3) and coating composition2(Table 4). TABLE 3(COATING 1)MATERIALAMT. (g)PERCENT(%)Solution 1105Solution 219095Total200100 TABLE 4(COATING 2)MATERIALAMT. (g)PERCENT(%)Solution 12010Solution 218090Total200100 The coating compositions were spray applied onto a surface of oven heated glass substrates using a conventional spray coating device to form an external extraction layer. As set forth in Table 5, the resultant coatings provided the substrate with haze greater than 10 while still maintaining transmittance greater than 90 percent. TABLE 5SPRAYOVENAIRSAMPLECOATINGTIMETEMPPRESSUREHAZETRANSMITTANCE#COMPOSITION(min.)° F.(psi)(Post-Spray)(Post-Spray)1154505011.894.421104505021.194.23254505010.394.142104505023.194.0 Example 2 This Example illustrates a coated substrate with an external extraction layer on one surface and an indium tin oxide coating on an opposite surface. A coating of indium tin oxide (ITO) was sputter deposited onto a first major surface of a glass substrate from an indium/tin cathode using a conventional magnetic sputter vapor deposition (MSVD) device. The ITO coating had a thickness of 300 nm. An external extraction layer was applied by conventional spray pyrolysis onto the second major surface of the glass substrate (opposite the first major surface) using the coating compositions described above. The spray parameters and optical results are shown in Table 6. TABLE 6SPRAYOVENAIRSAMPLECOATINGTIMETEMPPRESSUREHAZETRANSMITTANCEHAZETRANSMITTANCE#COMPOSITION(min.)° F.(psi)(Pre-Spray)(Pre-Spray)(Post-Spray)(Post-Spray)515450500.1486.911.887.26210450500.1287.519.787.6 Example 3 (A) This Example illustrates a substrate with a silane based external extraction layer. Hi-Gard® HC 1080 coating composition (commercially available from PPG Industries Ohio, Inc.) was spray applied onto a surface of oven heated glass substrates using a conventional spray coating device to form an external extraction layer. The spray parameters and optical measurements are disclosed in Table 7. The coated substrate had haze greater than 50 percent while still maintaining transmittance greater than 87 percent. TABLE 7FactorsSprayAirOvenSampleTimePressureTempPost Spraynumber(sec.)(psi)° F.HazeTransmittance754050066928104050071.290.1954050064.9871054055059.792.31174055070.691.61254060071.488.1135755506492145605506991.81557550071.791.71657545072.891.71756045074.591.61854045063.892.2 (B) A Hi-Gard® HC 1080 coating was spray applied to one side of a glass substrate as described above. An indium tin oxide coating of 300 nm was sputter deposited on the opposite side of the substrate using a conventional MSVD coater. The spray deposition parameters and measured optical data are set forth in Table 8. The coated substrate had haze greater than 50 percent while still maintaining transmittance greater than 81 percent. TABLE 8FactorsPre-sprayPost-spraySprayAirOvenReadingsReadingsSampleTimePressureTempTrans-Trans-number(sec.)(psi)° F.HazemittanceHazemittance195404000.0986.157.584.62010404000.1285.968.784.12110404000.1385.276.883.1225404000.1287.566.285.6234404000.1387.556.286.12410504000.1184.365.882.9253404000.1484.25682.8265.5754000.1283.677.781.2275.5754000.1185.774.583.4 Example 4 This example illustrates a substrate having an internal extraction layer (region). The internal extraction layer was formed using a conventional flame spray device, such as an nHalo flame spray coating device commercially available from Beneq Oy. The coating compositions were selected to form either alumina or titania nanoparticles. Samples 28 to 31 below contain alumina nanoparticles. Samples 32 to 39 contain titania nanoparticles. The nanoparticles were present at a depth in the range of 0 nm to 10 nm from the surface of the glass. As a general rule, as the concentration of nanoparticles increases, the haze increases and the transmittance decreases. Haze and transmittance values were measured on these samples as listed in Table 9. TABLE 9SamplenumberHazeTransmittance285.2293.02914.991.73030.289.53135.889.93282.769.43363.369.93444.078.03568.671.03655.574.63773.674.13878.069.53962.974.1 Example 5 This Example relates to a coated substrate having both an internal extraction layer and an external extraction layer. An internal extraction region was formed by softening the first surface by heating and then directing titania nanoparticles at the first surface such that at least a portion of the nanoparticles penetrated below the first surface. This was done using a flame spray device such as described above. The resultant substrate with the internal extraction layer had a haze value (percent) of 55.6 and a transmittance of 74.4 percent. An external extraction layer was formed on the second surface of the substrate by heating the substrate in an oven for eight minutes at 450° F. and then spray applying a Hi-Gard® HC 1080 coating composition (commercially available from PPG Industries Ohio, Inc.) onto the second surface using a conventional spray coating device as described above (40 psi for 10 seconds) to form the external extraction layer on the second surface. The substrate with both the internal extraction layer and the external extraction layer had a haze of 94.4 percent and a transmittance of 74.6 percent. It will be readily appreciated by one of ordinary skill in the art that modifications may be made to the invention without departing from the concepts disclosed in the foregoing description. Accordingly, the particular embodiments described in detail herein are illustrative only and are not limiting to the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalents thereof. | 21,321 |
11943961 | DETAILED DESCRIPTION The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. Also, in the figures, the thickness, ratio, and dimensions of components are exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. The term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that although the terms such as ‘first’ and ‘second’ are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one component from other components. For example, a first element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims. The terms of a singular form may include plural forms unless referred to the contrary. Also, ““under”, “below”, “above’, “upper”, and the like are used for explaining relation association of components illustrated in the drawings. The terms may be a relative concept and described based on directions expressed in the drawings. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art. Terms as defined in a commonly used dictionary should be construed as having the same meaning as in an associated technical context, and unless defined apparently in the description, the terms are not ideally or excessively construed as having formal meaning. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims. Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings. FIG.1is a perspective view illustrating an electronic device according to an embodiment of the invention. Referring toFIG.1, an embodiment of an electronic device ED may include a display device DD and a screen SC. The display device DD may project an image IM toward the screen SC substantially in a first direction DR1. The screen SC may be parallel to a plane defined by a second direction DR2crossing the first direction DR1and a third direction DR3crossing the first direction DR1and the second direction DR2. The first direction DR1, the second direction DR2, and the third direction DR3may be perpendicular to each other. Herein, a surface defined by the first direction DR1and the second direction DR2may be defined as a plane, and an expression “when viewed on a plane” may mean “when viewed from a plan view in the third direction DR3”. The third direction DR3may be a thickness direction of the display device DD. In an embodiment, as shown inFIG.1, the screen SC may have a thin rectangular plate shape, but the embodiment of the invention is not limited thereto. In one alternative embodiment, for example, the screen SC may be a curved screen, which is curved inside or outside, or a wall surface. In an alternative embodiment, the electronic device ED may not include the screen SC. FIG.2is a cross-sectional view illustrating a portion of the electronic device according to an embodiment of the invention. Referring toFIG.2, an embodiment of the display device DD may include a display panel DP, a first optical part L1, a second optical part L2, and a light shielding part BM. In an embodiment, the display panel DP may be a light emitting display panel or a light receiving display panel, but the embodiment of the invention is not particularly limited thereto. In one alternative embodiment, for example, the light receiving display panel may be a liquid crystal display panel. The light emitting display panel may be an organic light emitting display panel, a micro light emitting diode (“LED”) display panel, or a quantum dot light emitting display panel. The organic light emitting display panel may include a light emitting layer containing an organic light emitting material. The quantum dot light emitting display panel may include a light emitting layer containing a quantum dot or a quantum rod. Hereinafter, for convenience of description, embodiments where the display panel DP is an organic light emitting display panel will be described in detail. An embodiment of the display panel DP may include a base layer BS, a circuit element layer DP-CL, a display element layer DP-EL, and a thin-film encapsulation layer TFE. The display panel DP may emit first light LS1. The first light LS1may include first display light LS1a, second display light LS1b, and third display light LS1c. The display panel DP may include a first display area AR-DP1, a second display area AR-DP2, and a third display area AR-DP3. The first display area AR-DP1may emit the first display light LS1ato realize a first image IM-1having a first color. The second display area AR-DP2may be disposed adjacent to the first display area AR-DP1. The second display area AR-DP2may emit the second display light LS1bto realize a second image IM-2having a second color different from the first color. The third display area AR-DP3may be disposed adjacent to the second display area AR-DP2. The third display area AR-DP3may emit the third display light LS1cto realize a third image IM-3having a third color different from the first color and the second color. The second display area AR-DP2may be disposed between the first display area AR-DP1and the third display area AR-DP3. According to an embodiment of the invention, the first image IM-1may have only the first color, the second image IM-2may have only the second color, and the third image IM-3may have only the third color. The first image IM-1, the second image IM-2, and the third image IM-3may be images that are different from each other only in color. According to an embodiment of the invention, the display panel DP may provide the first image IM-1, the second image IM-2, and the third image IM-3, each of which has high resolution and high brightness. The first image IM-1, the second image IM-2, and the third image IM-3may be synthesized or combined and viewed as a single image IM (refer toFIG.1) on the screen SC. Thus, the electronic device ED (refer toFIG.1) having improved visibility may be provided. The first color, the second color, and the third color may have different wavelengths from each other. In one embodiment, for example, the first color may be a red color, the second color may be a green color, and the third color may be a blue color. However, the embodiment of the invention is not limited thereto. In one alternative embodiment, for example, each of the first color, the second color, and the third color may be one of various colors. The first display area AR-DP1, the second display area AR-DP2, and the third display area AR-DP3may not overlap each other when viewed on a plane. The first optical part L1may be disposed on the display panel DP. The first optical part L1may be disposed between the display panel DP and the second optical part L2. The first optical part L1may change a path and a luminance (or intensity) of the first light LS1provided from the display panel DP. The changed first light LS1may be second light LS2. The second light LS2may be parallel light incident in parallel to the second optical part L2. The second light LS2may travel in a direction parallel to the third direction DR3. The second optical part L2may be disposed on the first optical part L1. The second optical part L2may include a diffraction optical element having a diffraction grating. In an embodiment, the second light LS2may be incident to the second optical part L2in a direction parallel to the third direction DR3to improve a diffraction efficiency. The first image IM-1, the second image IM-2, and the third image IM-3may be diffracted by the second optical part L2and provided to the screen SC. A first area AR1, a second area AR2, and a third area AR3may be defined on the second optical part L2. The first area AR1may be disposed on the first display area AR-DP1. The first area AR1may overlap the first display area AR-DP1when viewed on a plane. A portion of the second light LS2realizing or corresponding to the first image IM-1may be transmitted through the first area AR1. The second area AR2may be disposed on the second display area AR-DP2. The second area AR2may overlap the second display area AR-DP2on the plane. A portion of the second light LS2realizing or corresponding to the second image IM-2may be transmitted through the second area AR2. The third area AR3may be disposed on the third display area AR-DP3. The third area AR3may overlap the third display area AR-DP3on the plane. A portion of the second light LS2realizing or corresponding to the third image IM-3may be transmitted through the third area AR3. A light shielding part BM may be disposed above the second optical part L2. The light shielding part BM may block the first image IM-1, the second image IM-2, and the third image IM-3, which are not diffracted toward the screen, of the first image IM-1, the second image IM-2, and the third image IM-3, which are diffracted by the second optical part L2. The screen SC may be spaced apart from the display device DD in the first direction DR1. The first image IM-1, the second image IM-2, and the third image IM-3may be synthesized or combined at the screen SC and provided as a single image. FIG.3is a cross-sectional view illustrating a display panel according to an embodiment of the invention. Referring toFIG.3, an embodiment of the display panel DP may include a base layer BS, a circuit element layer DP-CL, a display element layer DP-EL, and a thin-film encapsulation layer TFE. The base layer BS may include a synthetic resin film. In an embodiment, a synthetic resin layer may be provided on a working substrate that is used when the display panel DP is manufactured. Thereafter, a conductive layer and an insulation layer may be provided on the synthetic resin layer. When the working substrate is removed, the synthetic resin layer may correspond to the base layer BS. The synthetic resin layer may include or contain a thermosetting resin. In an embodiment, the synthetic resin layer may include a polyimide-based resin layer, but the embodiment of the invention is not limited to the material of the synthetic resin layer. Alternatively, the base layer BS may include an organic/inorganic composite substrate. The circuit element layer DP-CL may include a buffer layer BFL that is an inorganic layer, a first intermediate inorganic layer10, a second intermediate inorganic layer20, and an intermediate organic layer30that is an organic layer. The embodiment of the invention is not limited to particular material of each of the inorganic layer and the organic layer. The buffer layer BFL may provide a flat surface on the base layer BS and block impurity elements from being permeated into the base layer BS. In an embodiment of the invention, the buffer layer BFL may be selectively provided or omitted. A semiconductor pattern OSP of a transistor TR may be disposed on the buffer layer BFL. The semiconductor pattern OSP may include or contain a polysilicon or an amorphous silicon. In an embodiment, the semiconductor pattern OSP may include a metal oxide semiconductor. The first intermediate inorganic layer10may be disposed on the semiconductor pattern OSP. A control electrode GE of the transistor TR may be disposed on the first intermediate inorganic layer10. The second intermediate inorganic layer20covering the control electrode GE may be disposed on the first intermediate inorganic layer10. A first electrode E1and a second electrode E2of the transistor TR may be disposed on the second intermediate inorganic layer20. The first electrode E1may be may be connected to the semiconductor pattern OSP through a first through-hole CH1defined through the first intermediate inorganic layer10and the second intermediate inorganic layer20. The second electrode E2may be connected to the semiconductor pattern OSP through a second through-hole CH2defined through the first intermediate inorganic layer10and the second intermediate inorganic layer20. In an embodiment of the invention, the transistor TR may be modified to have a bottom gate structure. The intermediate organic layer30covering the first electrode E1and the second electrode E2may be disposed on the second intermediate inorganic layer20. The intermediate organic layer30may provide a flat surface. The display element layer DP-EL may be disposed on the intermediate organic layer30. The display element layer DP-EL may include a pixel defining layer PDL and a light emitting element OLED. In one embodiment, for example, the light emitting element OLED may include an organic light emitting diode. The pixel defining layer PDL may include an organic material. A first electrode AE may be disposed on the intermediate organic layer30. The first electrode AE may be electrically connected to the second electrode E2through a third through-hole CH3defined through the intermediate organic layer30. An opening OP may be defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL may expose at least a portion of the first electrode AE. A hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. A light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in an area corresponding to the opening OP. The light emitting layer EML may include an organic material and/or an inorganic material. The light emitting layer EML may emit light having a predetermined color. An electron control layer ECL may be disposed on the light emitting layer EML. A second electrode CE may be disposed on the electron control layer ECL. A thin-film encapsulation layer TFE may be disposed on the second electrode CE. The thin-film encapsulation layer TFE may cover the second electrode CE. In an embodiment, a capping layer covering the second electrode CE may be further disposed between the thin-film encapsulation layer TFE and the second electrode CE. In such an embodiment, the thin-film encapsulation layer TFE may directly cover or be disposed directly on the capping layer. FIG.4is a cross-sectional view illustrating a portion of the display device according to an embodiment of the invention. The same or like elements shown inFIG.4have been labeled with the same reference characters as used above to describe the embodiments of the display device shown inFIG.2, and any repetitive detailed description thereof will hereinafter be omitted or simplified. Referring toFIGS.2and4, the first display area AR-DP1of an embodiment of the display panel DP is illustrated inFIG.4. However, this is merely exemplary. Features of the first display area AR-DP1, which will be described below, may be applied in the same manner to the second display area AR-DP2and the third display area AR-DP3. The display panel DP may provide the first display light LS1a. The first display light LS1amay be transmitted through the first optical part L1. The first optical part L1may include a first lens TL1and a second lens TL2. The first lens TL1may be disposed between the display panel DP and the second optical part L2. The first lens TL1may disperse the first display light LS1a. The first display light LS1atransmitted through the first lens TL1may be dispersed to have various directionalities. The first lens TL1may include a concave lens or a convex lens. The first lens TL1may include a spherical lens or an aspheric lens. However, this is merely exemplary. In an embodiment of the invention, the first lens TL1may include at least one of various lenses. In one embodiment, for example, the first lens TL1may include an achromatic lens. The second lens TL2may be disposed between the first lens TL1and the second optical part L2. The second lens TL2may convert the first display light LS1atransmitted through the first lens TL1into the second light LS2having a constant directionality. The second lens TL2may include a concave lens or a convex lens. The second lens TL2may include a spherical lens or an aspheric lens. However, this is merely one example. In an embodiment of the invention, the second lens TL2may include at least one of various lenses. In one embodiment, for example, the second lens TL2may include an achromatic lens. However, the embodiment of the invention is not limited to the first optical part L1described above. In one alternative embodiment, for example, the first optical part L1may include only one lens or a single lens to convert the first light LS1into the second light LS2 The second light LS2may be provided to the second optical part L2in a direction parallel to the third direction DR3. The second optical part L2may provide the first image IM-1to the screen SC by diffracting the second light LS2. The second optical part L2may include a diffraction optical element having a diffraction grating. The diffraction grating may have a predetermined pitch. The diffraction grating may have pitches D1and D2that are expressed by the following equation: D*sin(AG)=m*λ. The above equation may be a grating equation. The above symbol D denotes the pitches D1and D2of the diffraction grating. The above symbol AG denotes an angle between each light IM-1aand IM-1btransmitted through the second optical part L2and an arbitrary line defined in a thickness direction of the second optical part L2. The light IM-1aand IM-1bmay realize the image IM on the screen SC. The thickness direction of the second optical part L2may be parallel to the third direction DR3. The above symbol m may be an integer, e.g., 1. The above symbol λ denotes a wavelength of each of the first color of the first display light LS1a, the second color of the second display light LS1b, and the third color of the third display light LS1c. Light IM-la may have a first angle AG1so that the light IM-1ais projected to a lower portion of the screen SC. A first pitch D1of the diffraction grating may be designed through or determined based on the above equation. Light IM-1bmay have a second angle AG2so that the light IM-1bis projected to an upper portion of the screen SC. A second pitch D2of the diffraction grating may be designed through or determined based on the above equation. In the first area AR1, the pitch of the diffraction grating may gradually increase in the first direction DR1. The pitch of the diffraction grating may be different in each of the first area AR1through which the first display light LS1ahaving the first color is transmitted, the second area AR2through which the second display light LS1bhaving the second color is transmitted, and the third area AR3through which the third display light LS1chaving the third color is transmitted. According to an embodiment of the invention, the electronic device ED may include the first optical part L1and the second optical part L2. The second optical part L2may have a reduced size or a thin thickness by using the diffraction optical element. The image IM provided from the display panel DP may pass through the first optical part L1and the second optical part L2and be projected to the screen SC. The display device DD may provide the optical part having a reduced size in comparison with a conventional display device having a typical projection method. Thus, the electronic device ED having a reduced size may be provided. Also, a projected direction of the image IM may be adjusted by determining the pitch of the diffraction grating of the second optical part L2based on the above equation. A focal distance by which the image is provided on the screen SC may be adjusted. Thus, the electronic device ED allowing the image IM to be projected in a close range may be provided. FIG.5is a side view illustrating a screen according to an embodiment of the invention. Referring toFIGS.2and5, an embodiment of the electronic device ED may further include a first diffraction element DO1, a second diffraction element DO2, and a third diffraction element DO3. The first diffraction element DO1may be disposed on one surface SC-1S of a screen SC-1. The second diffraction element DO2may be disposed on the first diffraction element DO1. The third diffraction element DO3may be disposed on the second diffraction element DO2. The first diffraction element DO1may reflect the first image IM-1having the first color in a predetermined direction. The second diffraction element DO2may reflect the second image IM-2having the second color in the predetermined direction. The third diffraction element DO3may reflect the third image IM-3having the third color in the predetermined direction. The predetermined direction may be parallel to the first direction DR1. However, this is merely exemplary. The predetermined direction may be variously modified to be in one of various directions in which the image IM is desired to be displayed. According to an embodiment of the invention, the first image IM-1, the second image IM-2, and the third image IM-3may be synthesized or combined to provide the image IM. The image IM may be provided in a predetermined direction by the first diffraction element DO1, the second diffraction element DO2, and the third diffraction element DO3. The image IM may have a viewing angle that is restricted in the predetermined direction. Thus, a personal electronic device ED for a single user or viewer may be provided. FIG.6is a side view illustrating a screen according to an alternative embodiment of the invention. Referring toFIGS.2and6, the electronic device ED may further include a scattering element SO. The scattering element SO may be disposed on one surface SC-2S of a screen SC-2. The first image IM-1, the second image IM-2, and the third image IM-3may be synthesized or combined at the screen SC-2to provide the image IM. The image IM may be scattered by the scattering element SO and reflected in all directions. The screen SC-2may include a transparent screen or an opaque screen. According to an embodiment of the invention, the scattering element SO may scatter the image IM. The scattered image IM may be provided in various directions. Thus, a shareable electronic device ED for multiple users or viewers may be provided. FIG.7is a side view illustrating a screen according to an embodiment of the invention. Referring toFIGS.2and7, the electronic device ED may further include a first lens part LN1. The first lens part LN1may be disposed on one surface SC-3S of a screen SC-3. The screen SC-3may include a transparent screen. The screen SC-3may transmit light BL therethrough. The first lens part LN1may reflect the first image IM-1, the second image IM-2, and the third image IM-3. The first image IM-1, the second image IM-2, and the third image IM-3, which are reflected, may be synthesized or combined to provide the image IM. The first lens part LN1may transmit the light BL incident toward the screen SC-3. According to an embodiment of the invention, the light BL incident toward the screen SC-3may represent an external environment. The image IM reflected by the first lens part LN1may be recognized in conjunction with the external environment. Thus, the electronic device ED capable of realizing an augmented reality may be provided. FIG.8is a plan view illustrating a screen according to an embodiment of the invention. Referring toFIGS.2and8, the electronic device ED may further include a second lens part LN2. The second lens part LN2may be disposed on one surface SC-4S of a screen SC-4. Each of the first image IM-1, the second image IM-2, and the third image IM-3may include a left eye image and a right eye image. The image IM obtained by synthesizing or combining the first image IM-1, the second image IM-2, and the third image IM-3may include a left eye image IM-L obtained by synthesizing or combining the left eye images of the first image IM-1, the second image IM-2, and the third image IM-3and a right eye image IM-R obtained by synthesizing or combining the right eye images of the first image IM-1, the second image IM-2, and the third image IM-3. The second lens part LN2may refract the left eye image IM-L in a left eye direction. The left eye direction may be a direction heading toward a left eye LE. The second lens part LN2may refract the right eye image IM-R in a right eye direction. The right eye direction may be a direction heading toward a right eye RE. According to an embodiment of the invention, the second lens part LN2may refract the left eye image IM-L and the right eye image IM-R in different directions from each other. The second lens part LN2may allow only the left eye image IM-L to be shown in the left eye LE and only the right eye image IM-R to be shown in the right eye RE. The second lens part LN2may allow different images from each other to be shown in the left eye LE and the right eye RE, respectively, for a three-dimensional effect. The different images from each other may represent images having a binocular parallax. Thus, the electronic device ED capable of regenerating a three-dimensional image may be provided. According to embodiments of the invention, the electronic device may include the first optical part and the second optical part. The second optical part may have a reduced size by including the diffraction optical element. The image provided from the display panel may be projected to the screen through the first optical part and the second optical part. The display device may provide the optical part having a reduced size in comparison with a conventional projector-type display device. Thus, the electronic device ED having a reduced size may be provided. The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims. | 29,221 |
11943962 | DESCRIPTION OF EMBODIMENTS In order to make the above-mentioned objects, features and advantages of the present disclosure more understandable, the present disclosure will be further described below with reference to the accompanying drawings and embodiments. It should be noted that specific details are set forth in the following description in order to fully understand the present disclosure. However, the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present disclosure. Therefore, the present disclosure is not limited by the specific embodiments disclosed below. In addition, in the following description, the same reference numerals in the figures denote the same or similar structures, and thus will not be described repeatedly. FIG.1is a schematic cross-sectional view of a display panel in the related art, andFIG.2is a partial enlarged view of an area A inFIG.1. As shown inFIGS.1-2, the display panel includes a substrate01, a light-emitting device layer02, a thin film encapsulation layer03and a color filter that are sequentially stacked in a first direction X. The color filter includes a light-shielding layer04, a color resist layer05, and a color resist planarization layer06that are sequentially stacked in the first direction X. The first direction X is a direction in which light exits from the display panel. In the related art, the technology of directly fabricating the color filter on the thin film encapsulation layer03can improve the anti-reflection ability of the display panel while reducing the overall thickness of the display panel. However, as shown inFIGS.1-2, in the related art, when a color filter is fabricated on the thin film encapsulation layer03, the light-shielding layer04needs to be fabricated first, and then the color resist layer05is fabricated by coating a color resist material. In this process, the light-shielding layer04is made of a black light-shielding material, and the light-shielding layer04itself has a certain thickness, so that the color resist material is likely to pile up at a position where the color resist material overlaps with the light-shielding layer04, forming a horn defect, and the color resist unit has a thickness h2 in a center area that is smaller than a thickness h1 in an edge area. FIG.3is a schematic diagram of brightness attenuation of light emitted by a light-emitting device at different viewing angles in the related art. As shown inFIG.3, the normal-viewing-angle light Aa and the large-viewing-angle light Bb emitted by the light-emitting device have different paths when passing through the color resist unit. It can be seen from the figure that the normal-viewing-angle light Aa emitted by the light-emitting device021travels a distance of m1 in the color resist layer05; a surface of the color resist layer05close to the substrate01is a surface05A, and a surface of the color resist layer05facing away from the substrate01is a surface05B; and the large-viewing-angle light Bb emitted by the light-emitting device021travels a distance of m2 in the color resist layer05, where m2>m1. Therefore, the large-viewing-angle light Bb travels a longer distance in the color resist unit, and its brightness attenuates more. Therefore, the brightness of the large-viewing-angle light Bb is smaller than the brightness of the normal-viewing-angle light Aa, and therefore color deviation between viewing angles occurs. The horn defect will further increase the distance that the large-viewing-angle light Bb travels in the color resist unit. It can be seen from the figure that, due to the presence of the horn defect, the surface of the color resist layer05facing away from the substrate01becomes a surface05B′, and the distance that the normal-viewing-angle light Aa emitted by the light-emitting device021travels in the color resist layer05is reduced to m1′, while the distance that the large-viewing-angle light Bb emitted by the light-emitting device021travels in the color resist layer05is increased to m2′, that is, m2′−m1′>m2−m1, which further aggravates the color deviation between viewing angles. On this basis, the applicant of the present disclosure proposes a display panel, which can improve the display uniformity of the display panel and reduce the color deviation between viewing angles, and which, in combination with the microstructure of the display panel and the reduced color deviation between viewing angles, increases the light exited at the large-viewing angle and improves light-exiting efficiency of the display panel. FIG.4is a schematic diagram of an implementation of a display panel provided by an embodiment of the present disclosure, andFIG.5is a partial enlarged schematic diagram ofFIG.4. As shown inFIG.4, the display panel includes a substrate100, a light-emitting device layer200, a light-shielding layer300, and a color resist layer400that are sequentially stacked in a first direction X. The light-emitting device layer200is located at a side of the substrate100. The light-emitting device layer200includes pixel apertures210arranged in an array, and light-emitting devices220one-to-one corresponding to the pixel apertures210and located in the pixel apertures210. The light-emitting devices220may be organic light-emitting devices or inorganic light-emitting devices, which will not be specifically limited herein. Illustratively, the light-emitting devices220described below are organic light-emitting devices. Each light-emitting device220includes an anode221, an organic light-emitting layer222, and a cathode223. A material of the anode221may be ITO/Al/ITO, and a material of the cathode223may be Mg/Ag. In an embodiment, as shown inFIG.5, the display panel further includes a pixel definition layer230. A size of the pixel aperture210generally refers to a size of an aperture of the pixel definition layer230. The light-emitting device220is disposed in the aperture of the pixel definition layer230, so as to limit a boundary of the light-emitting device220. The light-shielding layer300is located at a side of the light-emitting device layer200facing away from the substrate100, and a projection of the light-shielding layer300on the light-emitting device layer200is located between adjacent pixel apertures210. The light-shielding layer300may be made of a black material. The color resist layer400is located at a side of the light-shielding layer300facing away from the substrate100. The color resist layer400includes color resist units410arranged in an array. Each color resist unit410includes a first portion411and a second portion412. A projection of the second portion412on the substrate100is located outside a projection of the first portion411on the substrate100, that is, in each color resist unit410, the first portion411is located in a center area, and the second portion412is located in a peripheral area of the first portion411. As shown inFIG.4, the projection of the first portion411on the light-emitting device layer200is located in the pixel aperture210. In an embodiment, the color resist layer400further includes a color resist planarization layer420located at a side of the color resist unit410facing away from the substrate100. The color resist planarization layer420makes a surface of the color resist layer400facing away from the substrate100tend to be flat. In addition, the color resist planarization layer420can also serve as a protective layer located above the color resist layer400to prevent the color resist unit410from being scratched during subsequent manufacturing or bonding processes to cause new display issues. An auxiliary layer500is located between the light-shielding layer300and the color resist layer400, and a projection of the auxiliary layer500on the substrate100covers a projection of at least one of the color resist units410on the substrate100. As shown inFIG.4, the auxiliary layer500has a planarization function between the light-shielding layer300and the color resist unit410. This configuration can allow lower surfaces of the color resist units410to lie in a same plane. The fluidity of the color resist unit410on the surface of the auxiliary layer500during coating allows a better flatness of the color resist unit410. Therefore, with the auxiliary layer500, the thickness of the first portion411of the color resist unit410in the first direction X is equal to the thickness of the second portion412in the first direction X, where the first direction X is a direction in which light exits from the display panel. It should be noted that, the thickness of the first portion411of the color resist unit410in the first direction X being equal to the thickness of the second portion412of the color resist unit410in the first direction X herein does not mean that the thickness of the first portion411in the first direction X is absolutely equal to the thickness of the second portion412in the first direction X, but means that within a tolerance range of process errors, the thickness of the first portion411in the first direction X is substantially equal to the thickness of the second portion412in the first direction X. By arranging the auxiliary layer between at least one of the color resist units and the light-shielding layer, a center thickness of the color resist unit can be more easily and controllably adjusted to be larger than or equal to an edge thickness of the color resist unit, thereby reducing aggravation of the color deviation between viewing angles caused by the horn defect. Thereby, the brightness attenuation at a large viewing angle is alleviated, and color deviation between viewing angles of the display panel is reduced. In an embodiment, the auxiliary layer500includes a first auxiliary unit510. The light-emitting device220includes first-color light-emitting units220R, second-color light-emitting units220G, and third-color light-emitting units220B. A center wavelength of first-color light emitted by the first-color light-emitting unit is 1, a center wavelength of second-color light emitted by the second-color light-emitting unit is λ2, and a center wavelength of third-color light emitted by the third-color light-emitting unit is λ3, where λ1>λ2>λ3. In an embodiment, the center wavelength of the first-color light is within a range of 620-630 nm, the center wavelength of the second-color light is within a range of 555-585 nm, and the center wavelength of the third-color light is within a range of 440-480 nm. The color resist units410include first-color resist units410R, and along the first direction, the first-color resist units410R one-to-one correspond to the first-color light-emitting units220R. The projection of the first auxiliary unit510on the substrate100covers the projection of the first-color resist unit410R on the substrate. FIG.6is a schematic diagram of brightness attenuation of the first-color light-emitting unit220R at different viewing angles.FIG.7is a schematic diagram of brightness attenuation of the second-color light-emitting unit220G at different viewing angles.FIG.8is a schematic diagram of brightness attenuation of the third-color light-emitting unit220B at different viewing angles. The applicant of the present disclosure has found through research that, referring toFIGS.6-8, the first-color light-emitting unit220R has the largest attenuation degree, while the second-color light-emitting unit220G and the third-color light-emitting unit220B each have smaller attenuation under a same viewing angle. Since the attenuation degrees of the light-emitting units of different colors are inconsistent, when viewing from a certain direction of the display panel, the phenomenon of color separation is likely to occur to affect the display effect. Therefore, in an embodiment, the applicant adds a first auxiliary unit510above the first-color light-emitting unit220R to reduce the large-viewing-angle brightness attenuation of the first-color light-emitting unit220R when passing through the first-color resist unit410R while balancing the viewing-angle brightness attenuation degrees between the first-color light-emitting unit220R, the second-color light-emitting unit220G, and the third-color light-emitting unit220B, thereby reducing color dispersion. FIG.9is a partially enlarged schematic diagram of another implementation of a display panel provided by an embodiment of the present disclosure.FIG.10is a partial enlarged schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, as shown inFIGS.9-10, a first groove511is formed at a surface of the first auxiliary unit510facing away from the substrate100; an opening of the first groove511faces a light-exiting surface of the display panel, and the first groove511has a maximum depth din the first direction X. The presence of the first groove511allows the first portion411of the color resist unit410to fill the first groove511to increase the maximum thickness of the first portion411in the first direction X, thereby increasing the distance that the normal-viewing-angle light Aa travels in the color resist unit410, and further balancing the brightness of the normal-viewing-angle light Aa and the brightness of the large-viewing-angle light Bb, thus further reducing the color deviation between viewing angles. In an embodiment, as shown inFIGS.9-10, a bottom surface of the first groove511is a smooth curved surface or a multi-step surface, which is used to further adjust the thickness of the first portion411of the color resist unit410in the first direction X and to make the thickness change as smooth as possible, thereby preventing a large step difference from being formed to result in other optical effects. The maximum depth d of the first groove511in the first direction X may be smaller than or equal to the thickness of the first auxiliary unit510in the first direction X. In an embodiment, the maximum depth d is larger than or equal to a thickness difference (h1−h2) of the color resist unit caused by the horn defect. The light-shielding layer300includes first apertures310arranged in an array, the first apertures310one-to-one correspond to the pixel apertures, and the number of the first apertures310is equal to the number of the pixel apertures. The projection of the first groove511on the light-shielding layer300overlaps with the projection of the first-color resist units410R on the light-shielding layer300. In an embodiment, a projection of the first groove511on the light-shielding layer300covers the projection of the first portion411of the first-color resist unit410R on the light-shielding layer300, so that the first portion411of the first-color resist unit410R fills the first groove511to increase the maximum thickness of the first portion411in the first direction X and increase a propagation direction of the normal-viewing-angle light in the color resist unit410, thereby further balancing the brightness of the normal-viewing-angle light Aa and the brightness of the large-viewing-angle light Bb, thus further reducing the color deviation between viewing angles. FIG.11is a partial enlarged schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, the projection of the first groove511on the light-shielding layer300at least covers the first aperture310, as shown inFIG.11, the projection of the first groove511on the substrate has a maximum width w2 in the second direction Y, and the first aperture310has a maximum width w1 in the second direction Y, where w2 width w2 in the second direction Y, and the vided by an exiting surface of the display panel and perpendicular to the first direction X. By increasing the maximum width of the projection of the first groove511on the substrate100in the second direction Y, the overlapping area of the first groove511and the color resist unit410can be increased to further adjust the thickness of the color resist unit410in the first direction X, so that the adjustable range of color deviation between viewing angles enlarged, that is, an angle θ between the large-viewing-angle light Bb and the normal-viewing-angle light Aa increases. In an embodiment, a center of a projection of the first groove511on the light-shielding layer300coincides with a center of a projection of the first-color resist unit410R on the light-shielding layer300. That is, in the first direction X, a position on the first groove511with the largest change in the depth coincides with a position of a center of the first-color resist unit410R, and the center may be a geometric center or a center of gravity of the first-color resist unit410R, which is not specifically limited herein. It can be understood that within a certain process error, the position on the first groove511with the largest change in the depth coincides with the position of the center of the first-color resist unit410R to a more extent, the better effect of reducing the color deviation between viewing angles can be obtained. FIG.12is a partial enlarged schematic diagram of another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, the display panel includes a touch function layer600, the touch function layer600is located between the light-shielding layer300and the light-emitting device layer200, and the touch function layer600includes touch electrodes610and a touch insulation layer620between the touch electrodes610. The projection of the light-shielding layer300on the substrate100covers a projection of the touch electrodes610on the substrate100. The touch electrodes610include sensing touch electrodes and driving touch electrodes (not marked in the figures), which together realize the touch function of the display panel. The touch insulation layer620is configured to make the sensing touch electrodes be insulated from the driving touch electrodes. In an embodiment, the touch function layer600further includes a touch buffer layer630at a side close to the light-emitting device layer200for supporting the touch electrodes610, which provides a preparation environment for the touch electrodes610to be directly integrated with the display panel. In an embodiment, the touch buffer layer630is an inorganic layer. Due to the presence of the touch electrodes610, the thickness of the light-shielding layer300will increase. Accordingly, in an embodiment, in a direction perpendicular to the substrate, the maximum thickness of the first auxiliary unit510is larger than or equal to the thickness of the light-shielding layer300. As shown inFIG.12, if the maximum thickness of the first auxiliary unit510is equal to the thickness of the light-shielding layer300, the first auxiliary unit510is completely located in the first aperture310of the light-shielding layer300, so that the thickness of the first portion411at a side of the first auxiliary unit510facing away from the substrate in the first direction X is larger than or equal to the thickness of the second portion412in the first direction X, and at the same time, the thickness of the film layers on the display panel in the first direction X is reduced, which ensures that the final thickness of the entire display panel will not be affected after adding the auxiliary layer500, in order to meet the design requirements of a thinner and lighter display panel. In an embodiment, a refractive index of the first auxiliary unit510is smaller than a refractive index of the first-color resist unit410R. By setting a difference between the refractive index of the first-color resist unit410R and the refractive index of the first auxiliary unit510, a structure with a refractive index change at a contact interface between the first-color resist unit410R and the first auxiliary unit510can be formed to improve the light-exiting efficiency of the first-color light-emitting unit220R. In an embodiment, a surface of the first auxiliary unit510facing the color resist layer400includes a first region and a second region. Along the first direction X, the first region corresponds to the first portion411, and the second region corresponds to the second portion412. The first region has greater hydrophilicity than the second region. FIG.13is a partial enlarged schematic diagram of another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, as shown inFIG.13, a hydrophilic material layer512can be coated on the first region. Due to the function of the hydrophilic material layer512, the color resist material at the first portion411will be more likely to aggregate to form a convex structure such that the thickness of the first portion411in the first direction X is larger than or equal to the thickness of the second portion412in the first direction X. In an embodiment, the hydrophilic material layer512can also be coated on the surface of the first groove511to further adjust the thickness of the color resist unit410in the first direction X, and a principle thereof is the same as that described above and will not be repeated herein. FIG.14is a partial enlarged schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, as shown inFIG.14, the first auxiliary unit510includes at least a hydrophilic portion513, and in the first direction X, the hydrophilic portion513overlaps the first portion411. The hydrophilic portion513has a hydrophilic surface513aat a side facing away from the substrate100. Due to the hydrophilic surface513a, the color resist material at the first portion411is more likely to aggregate to form a convex structure such that the thickness of the first portion411in the first direction X is not larger than or equal to the thickness of the second portion412in the first direction X. In an embodiment, the first groove511may be formed in the hydrophilic portion513, and a principle thereof is similar to that of the foregoing embodiments and will not be repeated herein. FIG.15is a partial enlarged schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, as shown inFIG.15, the first auxiliary unit510is doped with scattering particles514, and a particle size of each of the scattering particles514is preferably within a range of 600±100 μm, and the material of the scattering particles can be selected from a metal oxide and an organic material with a high refractive index. The refractive index of the scattering particles514is n, where n>1.5, in order to improve the light-exiting efficiency of the first-color light-emitting unit220R. In an embodiment, projections of the scattering particles514on the light-shielding layer300completely fall into the first aperture310, so that the scattering efficiency is high and the transmittance loss is small in this range. FIG.16is a schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure. Based on the same inventive concept, a display panel is provided, as shown inFIG.16, the display panel including: a substrate100, a light-emitting device layer200, a light-shielding layer300, and a color resist layer400stacked in sequence along a first direction X. The light-emitting device layer200is located at a side of the substrate100. The light-emitting device layer200includes pixel apertures210arranged in an array, and light-emitting devices220one-to-one corresponding to the pixel apertures210. The light-emitting device220is located in the pixel aperture210. The light-emitting device220may be an organic light-emitting device or an inorganic light-emitting device, which is not specifically limited herein. In the following, taking the light-emitting device220being an organic light-emitting device as an example, the light-emitting device220includes an anode221, an organic light-emitting layer222, and a cathode223. The material of the anode221may be ITO/Al/ITO, and the material of the cathode223may be Mg/Ag. In an embodiment, the display panel further includes a pixel definition layer230, a size of the pixel aperture210generally refers to a size of an aperture of the pixel definition layer230, and the light-emitting device220is disposed in the aperture of the pixel definition layer230, in order to define a boundary of the light-emitting device220. The light-shielding layer300is located at a side of the light-emitting device layer200facing away from the substrate100, and a projection of the light-shielding layer300on the light-emitting device layer200is located between adjacent pixel apertures210. The light-shielding layer300can be made of a black material. The color resist layer400is located at a side of the light-shielding layer300facing away from the substrate100. The color resist layer400includes color resist units410arranged in an array. The color resist unit410includes a first portion411and a second portion412, and a projection of the second portion412on the substrate100is located outside a projection of the first portion411on the substrate100, that is, in a color resist unit410, the first portion411is located in the center area, and the second portion412is located in the peripheral area of the first portion411, as shown inFIG.4, the projection of the first portion411on the light-emitting device layer200is located in the pixel aperture210. In an embodiment, the color resist layer400further includes a color resist planarization layer420located at a side of the color resist units410facing away from the substrate100, and configured to make a surface of the color resist layer400facing away from the substrate100tend to be flat. In addition, the color resist planarization layer420can also serve as a protective layer above the color resist layer400to prevent the color resist units410from being scratched during subsequent manufacturing or bonding processes to cause new display issues. An auxiliary layer500is located between the light-shielding layer300and the color resist layer400. As shown inFIG.16, a projection of the auxiliary layer500on the substrate100completely covers a projection of the color resist layer400on the substrate100, the auxiliary layer500has a planarization function between the light-shielding layer300and the color resist units410. This configuration can allow lower surfaces of the color resist units410lie in a same plane. During coating, the fluidity of the color resist unit410on the surface of the auxiliary layer500provides better flatness of the color resist unit410, such that the thickness of the first portion411of the color resist unit410in the first direction X is equal to the thickness of the second portion412in the first direction X, where the first direction X is a direction in which light exits from the display panel. It should be noted that, due to process errors, the thickness of the first portion411in the first direction X being equal to the thickness of the second portion412in the first direction X herein does not mean that the thickness of the first portion411in the first direction X is absolutely equal to the thickness of the second portion412in the first direction X, but means that within a tolerance range of process errors, the thickness of the first portion411in the first direction X is approximately equal to the thickness of the second portion412in the first direction X. By arranging the auxiliary layer500between the color resist units and the light-shielding layer, the center thickness of the color resist unit can be more easily and controllably adjusted to be larger than or equal to an edge thickness of the color resist unit, thereby alleviating the aggravation of the color deviation between viewing angles caused by the horn defect. Thereby, the brightness attenuation at a large viewing angle is alleviated, and color deviation between viewing angles of the display panel is reduced. Referring toFIGS.6-8, at a same viewing angle, the first-color light-emitting unit220R has the largest attenuation degree, and the second-color light-emitting unit220G and the third-color light-emitting unit220B have smaller attenuation degrees. Although the applicant of the present disclosure preferably adds the auxiliary layer500above the first-color light-emitting unit220R, it can be seen fromFIGS.7-8that each of the second-color light-emitting unit220G and the third-color light-emitting unit220B also has a certain attenuation but with a less significant attenuation degree than that of the first-color light-emitting unit220R. Thus, the color resist units above the second-color light-emitting unit220G and the third-color light-emitting unit220B can also be modified. It can be understood that, since the second-color light-emitting unit220G and the third-color light-emitting unit220B have relatively small attenuation degrees, even if the color resist units above the second-color light-emitting unit220G and the third-color light-emitting unit220B are modified, the resulted color deviation reduction between viewing angles is far less significant than that when the color resist unit above the first-color light-emitting unit220R is modified. However, by modifying the color resist units above the second-color light-emitting unit220G and the third-color light-emitting unit220B while modifying the color resist unit above the first-color light-emitting unit220R, the process can be simplified and the cost can be reduced without affecting the effect of reducing the color deviation between viewing angles. FIG.17is a schematic diagram of another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, as shown inFIG.17, a first groove511is formed at a surface of the auxiliary layer500facing away from the substrate100; The light-emitting device220includes a first-color light-emitting unit220R, a second-color light-emitting unit220G, and a third-color light-emitting unit220B. A center wavelength of first-color light emitted from the first-color light-emitting unit is λ1, a center wavelength of second-color light emitted from the second-color light-emitting unit is λ2, and a center wavelength of third-color light emitted from the third-color light-emitting unit is λ3, where λ1>λ2>λ3; In an embodiment, the center wavelength of the first-color light is within a range of 620-630 nm, the center wavelength of the second-color light is within a range of 555-585 nm, and the center wavelength of the third-color light is within a range of 440-480 nm. The color resist units410include first-color resist units410R, and along the first direction, the first-color resist units410R one-to-one correspond to the first-color light-emitting units220R. The light-shielding layer300includes first apertures310arranged in an array, the first apertures310one-to-one correspond to the pixel apertures210, and the number of the first apertures310is equal to the number of the pixel apertures210. Generally, in the first direction X, in order to obtain the desired light-exiting efficiency, the size of the first aperture310is larger than the size of the pixel aperture210, and the first aperture310does not overlap with the pixel aperture210. The projection of the first groove511on the light-shielding layer300overlaps with the projection of the first-color resist unit410R on the light-shielding layer300. The first groove511has a maximum depth d1 in the first direction X, and the presence of the first groove511allows the first portion411of the color resist unit410fill the first groove511, which increases the maximum thickness of the first portion411in the first direction X, thereby increasing the distance that the normal-viewing-angle light Aa travels in the color resist unit410, further balancing the brightness of the normal-viewing-angle light Aa and the brightness of the large-viewing-angle light Bb, and thus further reducing the color deviation between viewing angles. In an embodiment, the bottom surface of the first groove511is a smooth curved surface or a multi-step surface, which is configured to further adjust the thickness of the first portion411of the color resist unit410in the first direction X and to make the thickness change as smooth as possible, thereby preventing a large step difference from being formed to result in other optical effects. The maximum depth d1 of the first groove511in the first direction X may be smaller than or equal to the thickness of the first auxiliary unit510in the first direction X. In an embodiment, the maximum depth d1 is larger than or equal to a thickness difference (h1−h2) of the color resist unit caused by the horn defect. In an embodiment, the projection of the first groove511on the light-shielding layer300covers the projection of the first portion411of the first-color resist unit410R on the light-shielding layer300, so that the first portion411of the first-color resist unit410R fills the first groove511to increase the maximum thickness of the first portion411in the first direction X, and increase the distance that the normal-viewing-angle light Aa travels in the color resist unit410, thereby balancing the brightness of the normal-viewing-angle light Aa and the brightness of the large-viewing-angle light Bb, and thus further reducing the color deviation between viewing angles. In an embodiment, the projection of the first groove511on the light-shielding layer300covers at least the first aperture310, the projection of the first groove511on the substrate has a maximum width w2 in the second direction Y, and the first aperture310has a maximum width w1 in the second direction Y, where w2th w2 in the second direction Yn between vie a light-exiting surface of the display panel and perpendicular to the first direction X. By increasing the maximum width of the projection of the first groove511on the substrate100in the second direction Y, the overlapping area of the first groove511and the color resist unit410can be increased to further adjust the thickness of the color resist unit410in the first direction X, so that the adjustable range of the color deviation between viewing angles becomes larger, that is, the angle θ between the large-viewing-angle light Bb and the normal-viewing-angle light Aa increases. In an embodiment, a center of a projection of the first groove511on the light-shielding layer300coincides with a center of a projection of the first-color resist unit410R on the light-shielding layer300. That is, in the first direction X, a position on the first groove511with the largest change in the depth coincides with a position of a center of the first-color resist unit410R, and the center may be a geometric center or a center of gravity of the first-color resist unit410R, which is not specifically limited herein. It can be understood that within a certain process error, the position on the first groove511with the largest change in the depth coincides with the position of the center of the first-color resist unit410R to a more extent, the better effect of reducing the color deviation between viewing angles can be obtained. Continuing to refer toFIG.17, a second groove515and a third groove516are further formed at the surface of the auxiliary layer500facing away from the substrate100. The color resist units410further include second-color resist units410G and third-color resist units410B. Along the first direction X, the second-color resist units410G one-to-one correspond to the second-color light-emitting units220G, and the third-color resist units410B one-to-one correspond to the third-color light-emitting units220B. The projection of the second groove515on the light-shielding layer300overlaps with the projection of the second-color resist unit410G on the light-shielding layer300. The projection of the third groove516on the light-shielding layer300overlaps with the projection of the third-color resist unit410B on the light-shielding layer300. The second groove515has a maximum depth d2 in the first direction X, and the third groove516has a maximum depth d3 in the first direction X, for increasing the maximum thickness of the first portion411in the first direction X, and thus increasing the distance that the normal-viewing-angle light Aa travels in the color resist unit410, further balancing the brightness of the normal-viewing-angle light Aa and the brightness of the large-viewing-angle light Bb, thereby further reducing the color deviation between viewing angles. Referring toFIGS.6-8, at a same viewing angle, the first-color light-emitting unit220R has the largest attenuation degree, and the second-color light-emitting unit220G and the third-color light-emitting unit220B have smaller attenuation degrees. Therefore, it can be configured such that the maximum depths of the first groove511, the second groove515, and the third groove516in the first direction X satisfy h1>h2 or h1>h3. Referring toFIGS.7-8, since the second-color light-emitting unit220G and the third-color light-emitting unit220B have similar attenuation degrees, in order to further simplify the process, the maximum depths of the first groove511, the second groove515, and the third groove516in the first direction X may further satisfy h1>h2=h3. In an embodiment, the bottom surface of each of the second groove515and the third groove516may also be a smooth curved surface or a multi-step surface, in order to further adjust the thickness of the first portion411of the color resist unit410in the first direction X and to make the thickness change as smooth as possible, thereby preventing a large step difference from being formed to result in other optical effects. In an embodiment, other optional implementations of the first groove511can also be used to improve the second groove515and the third groove516, and a principle and effect thereof is similar to that of the foregoing embodiments and will not be repeated herein. FIG.18is a schematic diagram of another implementation of a display panel provided by an embodiment of the present disclosure. In an embodiment, the display panel includes a touch function layer600, the touch function layer600is located between the light-shielding layer300and the light-emitting device layer200, and the touch function layer600includes touch electrodes610and a touch insulation layer620between the touch electrodes610. The projection of the light-shielding layer300on the substrate100covers a projection of the touch electrodes610on the substrate100. The touch electrodes610include sensing touch electrodes and driving touch electrodes (not marked in the figures), which together realize the touch function of the display panel. The touch insulation layer620is configured to make the sensing touch electrodes be insulated from the driving touch electrodes. In an embodiment, the touch function layer600includes a touch buffer layer630at a side close to the light-emitting device layer200for supporting the touch electrodes610, which provides a preparation environment for the touch electrodes610to be directly integrated with the display panel. In an embodiment, the touch buffer layer630is an inorganic layer. Due to the presence of the touch electrodes610, the thickness of the light-shielding layer300will increase. Accordingly, in an embodiment, in a direction perpendicular to the substrate, the maximum thickness of the first auxiliary unit510is larger than or equal to the thickness of the light-shielding layer300. As shown inFIG.18, if the maximum thickness of the auxiliary layer500is equal to the thickness of the light-shielding layer300, the auxiliary layer500is completely located in the first aperture310of the light-shielding layer300, so that the thickness of the first portion411at the side of the auxiliary unit500facing away from the substrate in the first direction X is larger than or equal to the thickness of the second portion412in the first direction X, and at the same time, the thickness of the film layers on the display panel in the first direction X is reduced, which ensures that the final thickness of the entire display panel will not be affected after adding the auxiliary layer500, in order to meet the design requirements of a thinner and lighter display panel. In an embodiment, the refractive index of the auxiliary layer500is smaller than the refractive index of the color resist layer400. If the refractive indexes of the first-color resist unit410R, the second-color resist unit410G, and the third-color resist unit410B in the color resist layer400are different, then the refractive index of the auxiliary layer500is smaller than that of the one with the smallest refractive index among the first-color resist unit410R, the second-color resist unit410G, and the third-color resist unit410B. In an embodiment, the light-emitting devices220include a first-color light-emitting unit220R, a second-color light-emitting unit220G, and a third-color light-emitting unit220B, a center wavelength of first-color light emitted from the first-color light-emitting unit is λ1, a center wavelength of second-color light emitted from the second-color light-emitting unit is λ2, and a center wavelength of third-color light emitted from the third-color light-emitting unit is λ3, where λ1>λ2>λ3. In an embodiment, the center wavelength of the first-color light is within a range of 620-630 nm, the center wavelength of the second-color light is within a range of 555-585 nm, and the center wavelength of the third-color light is within a range of 440-480 nm. The color resist units410includes first-color resist units410R, and along the first direction, the first-color resist units410R one-to-one correspond to the first-color light-emitting units220R. A surface of the auxiliary layer500facing away from the substrate includes a first region and a second region, the second region is located outside the first region, and along the first direction, the first region corresponds to the first portion411. The hydrophilicity of the first region is greater than that of the second region. In an embodiment, a hydrophilic material layer may be coated on the first region, or the auxiliary layer500includes a hydrophilic portion corresponding to the first portion411, and a principle and effect thereof is similar to that of the foregoing embodiments and will not be repeated herein. In an embodiment, the auxiliary layer500is doped with scattering particles inside, and the projection of the scattering particles on the substrate100overlaps with the projection of the first-color resist unit410R on the substrate100, the principle and effect of which are similar to the foregoing embodiments, and will not be repeated here. FIG.19is a schematic diagram of yet another implementation of a display panel provided by an embodiment of the present disclosure; andFIG.20is a partial enlarged schematic view of an optional implementation of an area B inFIG.19. In an embodiment, referring toFIGS.19-20, a fourth groove517is formed at a surface of the auxiliary layer500facing away from the substrate100. The projection of the light-shielding layer300on the auxiliary layer500covers the fourth groove517, and the projection of the color resist unit410on the auxiliary layer500at least partially overlaps with the fourth groove517. The fourth groove517can accommodate redundant color resist material in the edge area of the color resist unit410, thereby preventing the color resist material from accumulating at the edge of the color resist unit410, and thus reducing or even completely eliminating the horn defect in the edge area of the color resist unit410, thereby further ensuring that the center thickness of the color resist unit is larger than or equal to the edge thickness of the color resist unit, to reduce the aggravation of color deviation between viewing angles caused by the horn defect, thereby alleviating the brightness attenuation at the large viewing angle, and reducing the color deviation between viewing angles of the display panel. FIG.21is a partial enlarged schematic diagram of yet another embodiment of the area B inFIG.19. In an embodiment, referring toFIG.21, a fifth groove518is formed at a surface of the light-shielding layer300facing away from the substrate100; and along the first direction X, the fifth groove518at least partially overlaps with the fourth groove517. Providing the fifth groove518on the light-shielding layer300can increase the redundant position of the edge area of the color resist unit410, thereby further preventing the color resist material from accumulating at the edge of the color resist unit410; and due to the presence of the fourth groove517and the fifth groove518, the horn defects in the edge area of the color resist unit410can be reduced or even completely eliminated, thereby further ensuring that the center thickness of the color resist unit is larger than or equal to the edge thickness of the color resist unit and reducing the aggravation of the color deviation between viewing angles caused by the horn defects, and thus alleviating the brightness attenuation at the large viewing angle, and reducing the color deviation between viewing angles of the display panel. The present disclosure also provides a display device.FIG.22is a schematic diagram of a display device provided by an embodiment of the present disclosure. The display device includes the display panel provided by any embodiment of the present disclosure. The display devices provided by the present disclosure include but are not limited to the following categories: televisions, notebook computers, desktop displays, tablet computers, digital cameras, mobile phones, smart bracelets, smart glasses, car monitors, medical equipment, industrial control equipment, touch interaction terminal, etc. The above description is a further detailed description of the present disclosure in conjunction with specific preferred embodiments, but the specific implementations of the present disclosure is limited thereto. Those skilled in the art can make a number of simple deductions or substitutions without departing from the inventive concept of the present disclosure, all of which shall fall into a scope of the present disclosure. | 46,512 |
11943964 | DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In all the drawings, like elements are referenced by like reference numerals and the descriptions thereof will not be repeated. In addition, in the following description, having a light-transmitting property, being light-transmitting, or transmitting light means transmitting at least visible light. FIG.1is a plan view illustrating a configuration of a light-emitting device10according to an embodiment.FIG.2is a diagram in which a partition wall170, an insulating layer150, and a second electrode130are removed fromFIG.1.FIG.3is a cross-sectional view taken along line A-A ofFIG.1,FIG.4is a cross-sectional view taken along line B-B ofFIG.1, andFIG.5is a cross-sectional view taken along line C-C ofFIG.1. The light-emitting device10according to the embodiment includes a substrate100, a first electrode110, an insulating layer150, an organic layer120, a second electrode130, and an intermediate layer200. The substrate100is light-transmitting. The first electrode110is formed on the substrate100and has a light-transmitting property. The insulating layer150is formed over the substrate100and the first electrode110and includes an opening152overlapping the first electrode110. The organic layer120is located within at least the opening152. The second electrode130is formed over the organic layer120and has a light-transmitting property. The intermediate layer200is formed in at least a portion of a region of the lateral side of the first electrode110which overlaps the insulating layer150. The refractive index of the intermediate layer200is between the refractive index of the first electrode110and the refractive index of the insulating layer150. In addition, the light-emitting device10includes an interconnect116. The interconnect116is formed on the substrate100and has a light-transmitting property. The insulating layer150is formed also on the interconnect116. The intermediate layer200is formed in at least a portion of a region of the lateral side of the interconnect116which overlaps the insulating layer150. The refractive index of the intermediate layer200is between the refractive index of the interconnect116and the refractive index of the insulating layer150. Hereinafter, a detailed description will be given. The light-emitting device10according to the embodiment is a display device, and includes the substrate100, the first electrode110, plural first terminals112, plural second terminals132, a light-emitting unit140, the insulating layer150, plural openings152, plural openings154, plural lead-out interconnections114, the organic layer120, the second electrode130, plural lead-out interconnections134, and plural partition walls170. The substrate100is formed of a light-transmitting material such as, for example, a glass or a light-transmitting resin. The substrate100is polygonal such as, for example, rectangular. The substrate100may have flexibility. In a case where the substrate100has flexibility, the thickness of the substrate100is, for example, equal to or greater than 10 μm and equal to or less than 1,000 μm. Particularly, in a case where the substrate100is formed of glass, the thickness of the substrate100is, for example, equal to or less than 200 μm. In a case where the substrate100is a resin, the substrate100is formed using, for example, polyethylene naphthalate (PEN), polyether sulphone (PES), polyethylene terephthalate (PET), or polyimide. In addition, in a case where the substrate100is a resin, an inorganic barrier film of SiNx, SiON or the like is formed on at least one surface (preferably, both surfaces) of the substrate100in order to prevent moisture from permeating the substrate100. In a case where the substrate100is a glass substrate, the refractive index n1of the substrate100is, for example, equal to or greater than 1.4 and equal to or less than 1.6. The light-emitting unit140is formed on the substrate100and includes an organic EL element. The organic EL element has a configuration in which the first electrode110, the organic layer120, and the second electrode130are laminated in this order. The first electrode110is a transparent electrode which is formed on the substrate100and has a light-transmitting property. A transparent conductive material constituting the transparent electrode is a material including a metal, for example, a metal oxide such as an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium tungsten zinc oxide (IWZO), or a zinc oxide (ZnO). The thickness of the first electrode110is, for example, equal to or greater than 10 nm and equal to or less than 500 nm. The first electrode110is formed using, for example, sputtering or vapor deposition using a mask. Meanwhile, the first electrode110may be a thin metal material (for example, Ag or an Ag alloy), carbon nanotubes, or a conductive organic material such as PEDOT/PSS. The refractive index n2of the first electrode110is greater than the refractive index n1of the substrate100, and is, for example, equal to or greater than 1.8 and equal to or less than 2.2. The first electrode110linearly extends in a first direction (Y direction inFIGS.1and2). An end of the first electrode110is electrically and physically connected to the lead-out interconnection114. The lead-out interconnection114is formed using the same material as that of the first electrode110. Therefore, the lead-out interconnection114is light-transmitting. In the present example, the lead-out interconnection114is formed integrally with the first electrode110. The lead-out interconnection114is connected to the first terminal112. In the example shown in the drawing, the end of the lead-out interconnection114serves as the first terminal112. The insulating layer150is formed over conductor patterns serving as plural first electrodes110and over the substrate100between the first electrodes100. The insulating layer150partially covers the upper surfaces of the conductor patterns serving as the first electrodes110. The insulating layer150is formed using a photosensitive resin material, such as, for example, a light-transmitting polyimide-based resin. The insulating layer150may be formed using resins other than the polyimide-based resin, for example, an epoxy-based resin or an acrylic-based resin. The refractive index n3of the insulating layer150exists between the refractive index n1of the substrate100and the refractive index n2of the first electrode110, and is, for example, equal to or greater than 1.6 and equal to or less than 1.8. The second electrode130is formed on the organic layer120. Similarly to the first electrode110, the second electrode130is a transparent electrode having a light-transmitting property. A material exemplified as the material constituting the first electrode110may be used in a material constituting the second electrode130. However, the first electrode110and the second electrode130may be formed using different materials or may be formed using the same material. In addition, the film thickness of the second electrode130and a method of forming the second electrode130are the same as the film thickness of the first electrode110and a method of forming the second electrode130. However, the film thickness of the second electrode130may be different from the film thickness of the first electrode110. The second electrode130extends in a second direction (X direction inFIG.1) intersecting the first direction. The partition wall170is formed between the second electrodes130next to each other. The partition wall170extends parallel to the second electrode130, that is, in the second direction, and is provided in order to separate the second electrodes130from each other. Specifically, the partition wall170is formed in a shape which is trapezoidal in cross-section and is turned upside down (inverted trapezoid). That is, the width of the upper surface of the partition wall170is larger than the width of the lower surface of the partition wall170. For this reason, when the partition wall170is formed prior to the second electrode130, plural second electrodes130may be collectively formed by forming the second electrodes130on one surface side of the substrate100by vapor deposition or sputtering. In addition, the partition wall170also has a function of partitioning the organic layer120. The foundation of the partition wall170is, for example, the insulating layer150. The partition wall170is, for example, a photosensitive resin such as a polyimide-based resin, and is formed in a desired pattern by exposure and development. Meanwhile, the partition wall170may be formed of a resin other than a polyimide-based resin, for example, an epoxy-based resin or an acrylic-based resin, or an inorganic material such as silicon dioxide. Meanwhile, the light-emitting device10is not required to include the partition wall170. In this case, the second electrode130is formed in a predetermined pattern by using a mask during sputtering or vapor deposition. In addition, plural openings152and plural openings154are formed in the insulating layer150. The opening152is located at the point of intersection of the first electrode110and the second electrode130, on a surface parallel to the substrate100. Specifically, the plural openings152are aligned in the extending direction of the first electrode110(Y direction inFIG.1). In addition, the plural openings152are also aligned in the extending direction of the second electrode130(X direction inFIG.1). For this reason, the plural openings152are arranged to constitute a matrix. The organic layer120is formed in a region overlapping the opening152. The organic layer120includes a light-emitting layer. Therefore, the light-emitting unit140is located in each region overlapping the opening152. Specifically, the organic layer120has a configuration in which, for example, a hole injection layer, a light-emitting layer, and an electron injection layer are laminated. A hole transport layer may be formed between the hole injection layer and the light-emitting layer. In addition, an electron transport layer may be formed between the light-emitting layer and the electron injection layer. The organic layer120may be formed by vapor deposition. In addition, at least one layer of the organic layer120, for example, a layer in contact with the first electrode110, may be formed by a coating method such as an ink jetting, printing, or spraying. Meanwhile, in this case, the remaining layers of the organic layer120are formed by vapor deposition. In addition, all layers of the organic layer120may be formed by coating. The hole injection layer of the organic layer120is in contact with the first electrode110, and the electron injection layer of the organic layer120is in contact with the second electrode130. Meanwhile, in the examples shown inFIGS.3and4, a case is shown in which each of layers constituting the organic layer120all protrude to the outside of the opening152. As shown inFIG.4, the organic layer120may or may not be continuously formed between the openings152next to each other in the extending direction of the partition wall170. However, as shown inFIG.5, the organic layer120is not formed in the opening154. In addition, as described above, the light-emitting unit140is located in each region overlapping the opening152. Therefore, to be exact, as shown inFIG.3, the first electrode110may be defined as a region of the conductor pattern serving as the first electrode110which overlaps the opening152, in the extending direction of the conductor pattern serving as the first electrode110. In the first electrode110according to this definition, the edges of the upper surface of the first electrode110in a width direction (both ends of the first electrode110inFIG.4) are covered by the insulating layer150. A portion of the conductor pattern serving as the first electrode110which is located between the first electrodes110next to each other may be defined as the interconnect116. The interconnect116is covered by the insulating layer150. The opening154is located in a region overlapping one end side of each of the plurality of second electrodes130when seen in a plan view. In addition, the opening154is disposed along one side of the matrix constituted by the openings152. When seen in a direction along the one side (for example, Y direction inFIG.1, that is, the direction along the first electrode110), the openings154are disposed at a predetermined interval. A portion of the lead-out interconnection134is exposed from the opening154. The lead-out interconnection134is connected to the second electrode130through the opening154. The lead-out interconnection134is for electrically connecting the second electrode130to a second terminal132, and includes a layer constituted of the same material as that of the first electrode110. One end side of the lead-out interconnection134is located below the opening154, and the other end side of the lead-out interconnection134is extracted to the outside of the insulating layer150. In the examples shown in the drawings, the other end side of the lead-out interconnection134serves as the second terminal132. A conductive member such as a flexible printed circuit (FPC) is connected to the first terminal112and the second terminal132. In the example shown in the drawings, the first terminal112and the second terminal132are disposed along the same side of the substrate100. Therefore, in a case where the FPC is used as a conductive member, the first terminal112and the second terminal132can be connected to one FPC. In addition, the light-emitting device10includes the intermediate layer200. The intermediate layer200is formed in at least a portion (preferably, the entirety) of a region of the lateral side of the first electrode110which overlaps the insulating layer150, and at least a portion (preferably, the entirety) of a region of the lateral side of the interconnect116which overlaps the insulating layer150. In the example shown in the drawings, the intermediate layer200is also formed on the lateral side of the first terminal112, the lateral side of the lead-out interconnection114, the lateral side of the second terminal132, and the lateral side of the lead-out interconnection134. The thickness of the intermediate layer200is, for example, equal to or greater than 50 nm and equal to or less than 500 nm. The refractive index n4of the intermediate layer200is between the refractive index n2of the first electrode110and the refractive index n3of the insulating layer150. In order to achieve such a configuration, the intermediate layer200may be formed using, for example, both a material constituting the first electrode110and a material constituting the insulating layer150. In this case, the volume content of the material same as that of the first electrode110in the intermediate layer200is, for example, equal to or greater than 30% and equal to or less than 70%. Meanwhile, the volume content of the material same as that of the first electrode110may be replaced with, for example, the area ratio of the material same as that of the first electrode110in a cross-sectional photograph of the intermediate layer200. In addition, the intermediate layer200may be formed using a material containing silicon, oxygen, and nitrogen, such as a silicon oxynitride. In this case, the ratio of the nitrogen content of the intermediate layer200to the oxygen content of the intermediate layer200is, for example, equal to or greater than 2 and equal to or less than 9. Meanwhile, the ratio can also be replaced with, for example, the ratio of peak heights in X-ray fluorescence (XRF) or energy dispersive X-ray spectroscopy (EDX). Next, a method of manufacturing the light-emitting device10in the present embodiment will be described. First, the first electrode110, the interconnect116, the first terminal112, the second terminal132, and the lead-out interconnections114and134are formed over the substrate100. These components are formed by, for example, sputtering or vapor deposition using a mask. However, these components may be formed using other methods. Next, the intermediate layer200is formed on the lateral side of the first electrode110, the lateral side of the first terminal112, the lateral side of the second terminal132, the lateral side of the interconnect116, and the lateral sides of the lead-out interconnections114and134. In a case where the intermediate layer200is formed using a material constituting the first electrode110and a material constituting the insulating layer150, the intermediate layer200is formed by, for example, coating a material constituting the first electrode110, coating a material constituting the insulating layer150, and then heat-treating the materials. Meanwhile, the intermediate layer200may alternatively be formed by mixing the coating material including the material constituting the first electrode110and the coating material constituting the insulating layer150in advance, and coating and heat treating the mixed material. In addition, in a case where the intermediate layer200is formed using a material containing silicon, oxygen, and nitrogen, the intermediate layer200is formed using a gas phase method such as CVD or a lithographic method. Next, a photosensitive insulating film serving as the insulating layer150is formed over the substrate100and the first electrode110using, for example, a coating method. Thereafter, the insulating film is exposed and developed, thereby forming the insulating layer150. In this process, the openings152and154are also formed. Thereafter, the partition wall170, the organic layer120, and the second electrode130are formed in this order. In the present embodiment, the substrate100, the first electrode110, and the second electrode130are light-transmitting. Therefore, the light-emitting device10serves as a transparent display. However, since the refractive index n2of the first electrode110and the refractive index n3of the insulating layer150are different from each other, light is scattered on the interface between the lateral side of the first electrode110and the insulating layer150. As a result, there is the possibility of a user noticing the edge of the first electrode110. On the other hand, in the present embodiment, at least a portion (preferably, the entirety) of a region of the lateral side of the first electrode110which faces the insulating layer150is covered by the intermediate layer200. The refractive index n4of the intermediate layer200exists between the refractive index n2of the first electrode110and the refractive index n3of the insulating layer150. For this reason, light is less likely to be scattered between the lateral side of the first electrode110and the insulating layer150than in a case where the intermediate layer200is not provided, and thus a user is less likely to notice the edge of the first electrode110. In addition, the intermediate layer200is also formed on the lateral side of the interconnect116, the lateral side of a portion of the lead-out interconnection114which is covered by the insulating layer150, and the lateral side of a portion of the lead-out interconnection134which is covered by the insulating layer150. Therefore, light is also less likely to be scattered between each of these lateral sides and the insulating layer150. Therefore, a user is less likely to notice the edge of the interconnect116, the edge of the lead-out interconnection114, and the edge of the lead-out interconnection134. Second Embodiment FIGS.6,7, and8are cross-sectional views of a light-emitting device10according to a second embodiment, and correspond toFIGS.3,4, and5in the first embodiment, respectively. The light-emitting device10according to the present embodiment has the same configuration as that of the light-emitting device10according to the first embodiment, except for the layout of the intermediate layer200. In the present embodiment, similarly to the first embodiment, the insulating layer150covers the edges of the upper surface of the first electrode110in a width direction (both ends of the first electrode110inFIG.7). As shown inFIGS.6and7, the intermediate layer200is formed on at least a portion (preferably, the entirety) of a region of the upper surface of the first electrode110which is covered by the insulating layer150. In addition, as shown inFIG.6, the intermediate layer200is formed in at least a portion of a region of the upper surface of the interconnect116which is covered by the insulating layer150. In the examples shown inFIGS.6and7, on a cross-section in a direction (Y direction ofFIG.1) orthogonal to the extending direction of the interconnect116, the insulating layer150and the intermediate layer200are formed on the entirety of the interconnect116. In other words, the intermediate layer200is formed on the entirety of a region of the interconnect116which is covered by the insulating layer150. In addition, as shown inFIG.8, the intermediate layer200is formed on the entirety of a region of the lead-out interconnection134covered by the insulating layer150. Similarly, the intermediate layer200is formed on the entirety of a region of the lead-out interconnection114covered by the insulating layer150. In the present embodiment, a user is also less likely to notice the edge of the first electrode110, the edge of the interconnect116, the edge of the lead-out interconnection114, and the edge of the lead-out interconnection134. In addition, since the intermediate layer200is also formed on the upper surfaces of the first electrode110, the interconnect116, the lead-out interconnection114, and the lead-out interconnection134, the degree of accuracy required for the position of the intermediate layer200is reduced, allowing the manufacturing cost of the light-emitting device10to be reduced. Meanwhile, in the first and second embodiments, the intermediate layer200may be formed over portions of the substrate100, including a portion of the substrate100located in the vicinity of the first electrode110, a portion thereof located in the vicinity of the first terminal112, a portion thereof located in the vicinity of the lead-out interconnection114, a portion thereof located in the vicinity of the interconnect116, a portion thereof located in the vicinity of the second terminal132, and a portion located in the vicinity of the lead-out interconnection134. Third Embodiment FIGS.9and10are plan views illustrating a configuration of a light-emitting device10according to a third embodiment.FIGS.11,12, and13are cross-sectional views illustrating a configuration of the light-emitting device10.FIGS.9to13correspond toFIGS.1to5in the embodiment. The light-emitting device10according to the present embodiment has the same configuration as that of the light-emitting device10according to the first embodiment, except that the intermediate layer200is also provided on a surface of the substrate100where the light-emitting unit140is formed. Therefore, the intermediate layer200is formed in at least a portion (the entirety in the example shown in the drawing) between the substrate100and the first electrode110, at least a portion (the entirety in the example shown in the drawing) between the substrate100and the interconnect116, at least a portion (the entirety in the example shown in the drawing) between the insulating layer150located next to the first electrode110and the substrate100, at least a portion (the entirety in the example shown in the drawing) between the insulating layer150located next to the interconnect116and the substrate100, at least a portion (the entirety in the example shown in the drawing) between the substrate100and the lead-out interconnection114, and at least a portion (the entirety in the example shown in the drawing) between the substrate100and the lead-out interconnection134. The refractive index n4of the intermediate layer200formed on the substrate100exists between the refractive index n1of the substrate100and the refractive index n2of the first electrode110. More specifically, the refractive index n3of the insulating layer150is preferably between the refractive index n2of the first electrode110and the refractive index n1of the substrate100, and the refractive index n4of the intermediate layer200is preferably between the refractive index n2of the first electrode110and the refractive index n3of the insulating layer150. In addition, n4is preferably between √(n1×n2) and (n2+n3)/2. Further, when the wavelength of a maximum peak of an emission spectrum of the organic layer120is λ, and the thickness of the intermediate layer200is d, 0.9λ/4≤n4×d≤1.1λ/4 and √(n1×n2)≤n4≤(n2+n3)/2 are preferably true. Meanwhile, a material of the intermediate layer200formed on the substrate100is the same as a material of the intermediate layer200shown in the first embodiment. However, the intermediate layer200formed on the substrate100may be different from that of the intermediate layer200covering the lateral side of the first electrode110. In addition, the thickness of the intermediate layer200formed on the substrate100is, for example, equal to or greater than 50 nm and equal to or less than 500 nm. According to the present embodiment, the intermediate layer200is formed between the first electrode110and the substrate100. The refractive index n4of the intermediate layer200exists between the refractive index n1of the substrate100and the refractive index n2of the first electrode110. Therefore, extraction efficiency of light from the organic layer120is further improved than in a case where no intermediate layer200is provided. In a case where n4is √(n1×n2), the extraction efficiency of light from the organic layer120is further improved. In addition, in a case where 0.9λ/4≤n4×d≤1.1λ/4 is true and n4is √(n1×n2), extraction efficiency of light from the organic layer120is further improved. In addition, since the refractive index n4of the intermediate layer200is between the refractive index n2of the first electrode110and the refractive index n3of the insulating layer150, a user is less likely to visually recognize a portion of the lateral side of the first electrode110in contact with the insulating layer150. In a case where n4is (n2+n3)/2, the aforementioned portion of the lateral side of the first electrode110is the most less likely to be visually recognized. Therefore, √(n1×n2)≤n4≤(n2+n3)/2 indicates a condition for achieving superior extraction efficiency of light from the organic layer120and less visibility of a portion of the lateral side of the first electrode110in contact with the insulating layer150. As described above, although the embodiments and examples of the present invention have been set forth with reference to the accompanying drawings, they are merely illustrative of the present invention, and various configurations other than those stated above can be adopted. | 26,965 |
11943965 | DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, exemplary embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings. FIG.1is a diagram illustrating a display device according to an exemplary embodiment of the present inventive concept. Referring toFIG.1, the display device1000may be divided into a display area DA and a non-display area NDA. A first pixel structure PXL_1, a second pixel structure PXL_2, and a third pixel structure PXL_3are spaced apart from each other and may be disposed in the display area DA. For example, as shown inFIG.1, the first to third pixel structures PXL_1, PXL_2and PXL_3may be arranged in a pentile manner. For example, the second pixel structure PXL_2may be smaller than each of the first and third pixel structures PXL_1and PXL_3. In addition, wirings for providing a power and a signal to the first to third pixel structures PXL_1, PXL_2and PXL_3may be disposed in the display area DA. The first to third pixel structures PXL_1, PXL_2and PXL_3may emit lights having first to third colors that are different from each other, respectively. For example, the first to third colors may be a red color, a green color, and a blue color, respectively. Each of the first to third pixel structures PXL_1, PXL_2and PXL_3may be connected to a thin film transistor disposed on a substrate through a contact hole. For example, the first pixel structure PXL_1may be connected to a thin film transistor through a first contact hole CNT_1. The power and the signal may be provided to the first pixel structure PXL_1through the thin film transistor so that the first pixel structure PXL_1emits a light having the first color. In addition, the second pixel structure PXL_2may be connected to a thin film transistor through a second contact hole CNT_2. The power and the signal may be provided to the second pixel structure PXL_2through a thin film transistor so that the second pixel structure PXL_2emits a light having the second color. In an exemplary embodiment of the present inventive concept, the first contact hole CNT_1may be located at one side of the first pixel structure PXL_1, and the second contact hole CNT_2may be located at one side of the second pixel structure PXL_2. For example, when viewed in a plan view, the first contact hole CNT_1may be located below the first pixel structure PXL_1, and the second contact hole CNT_2may be located above the second pixel structure PXL_2. However, the present inventive concept is not limited thereto. In the display area DA of the display device1000, an image may be displayed through the first to third pixel structures PXL_1, PXL_2and PXL_3. A power supply, a gate driver, and a data driver may be disposed in the non-display area NDA. The power supply may provide the power to the first to third pixel structures PXL_1, PXL_2and PXL_3through some of the wirings provided in the display area DA and connected to the first to third pixel structures PXL_1, PXL_2and PXL_3. The gate driver and the data driver may provide a scan signal and a data signal, respectively, to the first to third pixel structures PXL_1, PXL_2and PXL_3through other wirings provided in the display area DA. In addition, the display device1000may further include a flexible printed circuit board disposed in the non-display area NDA, and the data driver may be disposed on the flexible printed circuit board. FIG.2is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.2is a cross-sectional view taken along line I-I′ of the display device ofFIG.1. Referring toFIGS.1and2, the display device1000may include a substrate110, a first thin film transistor117, a second thin film transistor127, a gate insulating layer112, an interlayer insulating layer114, a via insulating layer130, a first lower electrode140, a second lower electrode150, a first emission layer161, a second emission layer162, an upper electrode170, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure180, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. The first thin film transistor117may include a first active pattern111, a first gate electrode113, a first source electrode115, and a first drain electrode116. The second thin film transistor127may include a second active pattern121, a second gate electrode123, a second source electrode125, and a second drain electrode126. The first lower electrode140may include a first transparent electrode141, a first reflective electrode143, and a second transparent electrode145. The second lower electrode150may include a third transparent electrode151, a second reflective electrode153, and a fourth transparent electrode155. The substrate110may include a transparent material or an opaque material. For example, the substrate110may include a quartz substrate, a glass substrate, a plastic substrate, and the like. The plastic substrate may be a polyimide substrate having a ductility. For example, the substrate110may have a structure including at least one polyimide layer and at least one barrier layer alternately stacked with each other. The first active pattern111and the second active pattern121may be disposed on the substrate110. The first and second active patterns111and121may be formed by patterning an active layer after the active layer is deposited on the substrate110. Each of the first and second active patterns111and121may include a source region doped with impurities, a drain region doped with impurities, and a channel region disposed between the source region and the drain region. For example, each of the first and second active patterns111and121may include an amorphous silicon, a polycrystalline silicon, or the like. A buffer layer may be disposed between the substrate110and the first and second active patterns111and121. The buffer layer may prevent a phenomenon in which metal atoms or impurities are diffused from the substrate110to the first and second thin film transistors117and127. In addition, the buffer layer may control a heat transfer rate during a crystallization process to form the first and second active patterns111and121, so that the first and second active patterns111and121may be uniformly formed. The gate insulating layer112may be disposed on the substrate110and the first and second active patterns111and121. For example, the gate insulating layer112may be disposed on the substrate110, and may cover the first and second active patterns111and121. The gate insulating layer112may include an insulating material. The first gate electrode113and the second gate electrode123may be disposed on the gate insulating layer112. The first and second gate electrodes113and123may be formed by patterning a metal layer after the metal layer is deposited on the entire gate insulating layer112. Each of the first and second gate electrodes113and123may respectively overlap each of the channel regions of the first and second active patterns111and121. For example, each of the first and second gate electrodes113and123may include a metal, an alloy, a conductive metal oxide, a transparent conductive material and the like. The interlayer insulating layer114may be disposed on the gate insulating layer112and the first and second gate electrodes113and123. For example, the interlayer insulating layer114may be disposed on the gate insulating layer112, and may cover the first and second gate electrodes113and123. The interlayer insulating layer114may include an insulating material. The first source electrode115and the first drain electrode116may be disposed on the interlayer insulating layer114. The first source electrode115may be connected to the source region of the first active pattern111through a contact hole formed in the gate insulating layer112and the interlayer insulating layer114. The first drain electrode116may be connected to the drain region of the first active pattern111through another contact hole formed in the gate insulating layer112and the interlayer insulating layer114. For example, the first source electrode115and the first drain electrode116may be formed by depositing and patterning a metal material (e.g., aluminum (Al)), after the contact holes are formed in the gate insulating layer112and the interlayer insulating layer114. The second source electrode125and the second drain electrode126may be formed in a substantially same process as the first source electrode115and the first drain electrode116. For example, the second source electrode125and the second drain electrode126may be formed of substantially the same material as the first source electrode115and the first drain electrode116. The via insulating layer130may be disposed on the interlayer insulating layer114and the first and second thin film transistors117and127. For example, the via insulating layer130may be disposed on the interlayer insulating layer114, and may cover the first and second thin film transistors117and127. The via insulating layer130may be include the first contact hole CNT_1and the second contact hole CNT_2. The first contact hole CNT_1exposes a portion of the first drain electrode116, and the second contact hole CNT_2exposes a portion of the second drain electrode126. The via insulating layer130may be disposed between the substrate110and the first and second lower electrodes140and150to insulate wirings formed on the substrate110from the first and second lower electrodes140and150. For example, the via insulating layer130may include an insulating material. The via insulating layer130may include an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), and the like, or an organic material such as a photoresist, a polyimide resin, a polyamide resin, and the like. In addition, the via insulating layer130may be formed in a multi-layer structure so that the first and second lower electrodes140and150are arranged on a flat surface. For example, the via insulating layer130may include a first via insulating layer a second via insulating layer. For example, the first via insulating layer may include siloxane, and the second via insulating layer may include the polyamide resin. The first pixel structure PXL_1may include the first lower electrode140and the first emission layer161. The first pixel structure PXL_1may overlap the first thin film transistor117. The first lower electrode140may include the first transparent electrode141, the first reflective electrode143and the second transparent electrode145. The first transparent electrode141may be disposed on the via insulating layer130. The first transparent electrode141may be formed by patterning a metal layer to contact the first contact hole CNT_1after the metal layer is deposited on the via insulating layer130including the first and second contact holes CNT_1and CNT_2. Accordingly, the first transparent electrode141may be formed to have a same thickness along a profile of the via insulating layer130. In an exemplary embodiment of the present inventive concept, the first transparent electrode141may overlap a first region10, a second region20and a third region30. The first region10overlaps the first emission layer161. The second region20is located in one side of the first region10, and overlaps the first contact hole CNT_1. The third region30is located in the other side of the first region10. For example, from a plan view, the second region20is located below the first region10. In an exemplary embodiment of the present inventive concept, the first transparent electrode141may contact the first drain electrode116exposed by the first contact hole CNT_1. For example, the entirety of the portion of the first drain electrode116that is exposed by the first contact hole CNT_1may be in contact with the first transparent electrode141. In an exemplary embodiment of the present inventive concept, the first transparent electrode141may contact a portion of the first drain electrode116exposed by the first contact hole CNT_1, and may not contact a remaining portion of the first drain electrode116exposed by the first contact hole CNT_1. The first transparent electrode141may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the first transparent electrode141may include, for example, nickel (Ni), chromium (Cr), titanium (Ti), indium tin oxide (ITO), indium zinc oxide (IZO), and the like. The first reflective electrode143may be disposed on the first transparent electrode141. The first reflective electrode143may be formed by patterning a metal layer to overlap the first transparent electrode141after the metal layer is deposited on the via insulating layer130and the first transparent electrode141. In addition, a thickness of the first reflective electrode143may be larger than a thickness of the first transparent electrode141. The first reflective electrode143may include a reflective electrode. In an exemplary embodiment of the present inventive concept, the first reflective electrode143may include, for example, silver (Ag), an alloy including Ag, Al, copper (Cu), platinum (Pt), and the like. In an exemplary embodiment of the present inventive concept, the first reflective electrode143may overlap only the first region10. For example, the first reflective electrode143may be formed by patterning a metal layer to overlap only the first region10after the metal layer is deposited on the via insulating layer130and the first transparent electrode141. Accordingly, the first reflective electrode143may not overlap the second and third regions20and30. In addition, portions of the first transparent electrode141may be exposed in the second and third regions20and30. When a general pixel structure includes a reflective electrode, a light incident from an outside (e.g., an external light) may be reflected from the reflective electrode disposed in the second and third regions20and30. The reflected light may generate a color band described above, so that the color band blurs a color of a light emitted from the pixel structure. However, since the first reflective electrode143overlaps only the first region10, the external light incident to the second and third regions20and30may not be reflected. Therefore, the color band may not be generated, and the color of the light emitted from the first pixel structure PXL_1may be clearly recognized. The second transparent electrode145may be disposed on the first reflective electrode143. In an exemplary embodiment of the present inventive concept, the first reflective electrode143and the second transparent electrode145may be formed by simultaneously patterning metal layers after the metal layers are sequentially deposited on the via insulating layer130and the first transparent electrode141. The second transparent electrode145may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the second transparent electrode145may include, for example, Ni, Cr, Ti, ITO, IZO, and the like. In an exemplary embodiment of the present inventive concept, the second transparent electrode145may include a substantially same material as the first transparent electrode141. The pixel defining layer PDL may be disposed between the first and second pixel structure PXL_1and PXL_2on the via insulating layer130and may be disposed on at least a portion of the first transparent electrode141and at least a portion of the third transparent electrode151. In an exemplary embodiment of the present inventive concept, the pixel defining layer PDL may overlap the first and second contact holes CNT_1and CNT_2. The pixel defining layer PDL may include openings. Emission materials included in the first and second emission layers161and162may be disposed in the openings, respectively. Accordingly, the pixel defining layer PDL may provide regions in which the first and second emission layers161and162are formed. In an exemplary embodiment of the present inventive concept, the pixel defining layer PDL may function as a light blocking member. For example, the pixel defining layer PDL may include a black pigment or a black dye. The first emission layer161may be disposed on the second transparent electrode145exposed by the opening of the pixel defining layer PDL. In an exemplary embodiment of the present inventive concept, the first emission layer161may overlap the first region10. The second pixel structure PXL_2may include the second lower electrode150and the second emission layer162. The second pixel structure PXL_2may overlap the second thin film transistor127. In addition, the second pixel structure PXL_2may be spaced apart from the first pixel structure PXL_1. The second lower electrode150may include the third transparent electrode151, the second reflective electrode153, and the fourth transparent electrode155. In addition, the second lower electrode150may have a shape different from a shape of the first lower electrode140. This will be described in detail below. For example, the second lower electrode150may have a different configuration of elements than that of the first lower electrode140. The third transparent electrode151may be disposed on the via insulating layer130. The third transparent electrode151may be formed by patterning a metal layer to contact the second contact hole CNT_2after the metal layer is deposited on the via insulating layer130including the first and second contact holes CNT_1and CNT_2. Accordingly, the third transparent electrode151may be formed to have a substantially constant thickness along a profile of the via insulating layer130. In addition, as described above, the third transparent electrode151may be simultaneously formed with the first transparent electrode141. For example, the third transparent electrode151may have a thickness that is substantially the same as that of the first transparent electrode141. In an exemplary embodiment of the present inventive concept, the third transparent electrode151may overlap a fourth region40, a fifth region50, and a sixth region60. The fourth region40may overlap the second emission layer162. The fifth region50is located in one side of the fourth region40and overlaps the second contact hole CNT_2. The sixth region60is located in the other side of the fourth region40. For example, from a plan view, the fifth region50is located above the fourth region40. In an exemplary embodiment of the present inventive concept, the third transparent electrode151may contact the second drain electrode126exposed by the second contact hole CNT_2. For example, the entirety of the portion of the second drain electrode126that is exposed by the second contact hole CNT_2may be in contact with the third transparent electrode151. In an exemplary embodiment, the third transparent electrode151may contact a portion of the second drain electrode126exposed by the second contact hole CNT_2and may not contact a remaining portion of the second drain electrode126exposed by the second contact hole CNT_2. The third transparent electrode151may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the third transparent electrode151may include, for example, Ni, Cr, Ti, ITO, IZO, and the like. The second reflective electrode153may be disposed on the third transparent electrode151. The second reflective electrode153may be formed by patterning a metal layer to overlap the third transparent electrode151after the metal layer is deposited on the via insulating layer130and the third transparent electrode151. In addition, a thickness of the second reflective electrode153may be larger than a thickness of the third transparent electrode151. In addition, the second reflective electrode153may be simultaneously formed with the first reflective electrode143. For example, the second reflective electrode153may be formed of substantially the same material as the first reflective electrode143, and the second reflective electrode153may have substantially the same thickness as the first reflective electrode143. However, the present inventive concept is not limited thereto. The second reflective electrode153may include a reflective electrode. In an exemplary embodiment of the present inventive concept, the second reflective electrode153may include, for example, Ag, Al, Cu, Pt, an alloy including Ag, and the like. In an exemplary embodiment of the present inventive concept, the second reflective electrode153may overlap the fourth region40and the fifth region50. For example, the second reflective electrode153may be formed by patterning a metal layer to overlap the fourth region40and the fifth region50after the metal layer is deposited on the via insulating layer130and the third transparent electrode151. Accordingly, the second reflective electrode153may not overlap the sixth region60. The fourth transparent electrode155may be disposed on the second reflective electrode153. In an exemplary embodiment of the present inventive concept, the second reflective electrode153and the fourth transparent electrode155may be formed by simultaneously patterning metal layers after the metal layers are sequentially deposited on the via insulating layer130and the third transparent electrode151. In addition, the second reflective electrode153and the fourth transparent electrode155may be simultaneously formed with the first reflective electrode143and the second transparent electrode145. The fourth transparent electrode155may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the fourth transparent electrode155may include, for example, Ni, Cr, Ti, ITO, IZO, and the like. In an exemplary embodiment of the present inventive concept, the fourth transparent electrode155may include a substantially same material as the third transparent electrode151. The second emission layer162may be disposed on the fourth transparent electrode155exposed by the opening of the pixel defining layer PDL. In an exemplary embodiment of the present inventive concept, the second emission layer162may overlap the fourth region40. For example, each of the first and second emission layers161and162may have a multi-layer structure including an organic light emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In an exemplary embodiment of the present inventive concept, the first emission layer161may emit a light having a first color, and the second emission layer162may emit a light having a second color different from the first color. Accordingly, the first color filter CF_1corresponding to the first emission layer161may transmit the first color, and the second color filter CF_2corresponding to the second emission layer162may transmit the second color. The upper electrode170may be disposed on the pixel defining layer PDL, the first emission layer161, and the second emission layer162. The upper electrode170may be formed in a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and/or a transparent conductive material film. For example, the upper electrode170may include Ag, an alloy including Ag, Al, an alloy including Al, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), Cu, Ni, Cr, chromium nitride (CrN), molybdenum (Mo), an alloy including Mo, Ti, tantalum (Ta), Pt, scandium (Sc), ITO, IZO, and the like. In an exemplary embodiment of the present inventive concept, the upper electrode170may include a transparent electrode. For example, the upper electrode170may include Ni, Cr, Ti, ITO, IZO, and the like. When the upper electrode170includes the transparent electrode, lights emitted by the first and second emission layers161and162may transmit through the upper electrode170. The thin film encapsulation layer TFE may be disposed on the upper electrode170. The thin film encapsulation layer TFE may prevent a penetration of moisture and oxygen from an outside (e.g., an external environment). In an exemplary embodiment of the present inventive concept, the thin film encapsulation layer TFE may include a first inorganic layer, a second inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer. For example, the first and second inorganic layers may include inorganic materials, and the organic layer may include an organic material. The sensing structure180may be disposed on the thin film encapsulation layer TFE. In an exemplary embodiment of the present inventive concept, some components (e.g., sensing electrodes) of the sensing structure180may overlap the thin film encapsulation layer TFE, but the structure in which the sensing structure180is disposed in the display device1000is not limited thereto. The sensing structure180may detect a user's touch or a user's approach (e.g., a user's gesture that does not touch the display device1000). In an exemplary embodiment of the present inventive concept, the sensing structure180may have a structure in which a plurality of sensing electrodes are formed as a multi-layer structure. For example, a capacitance may be generated by the sensing electrodes, and the sensing structure180may detect the user's touch or the user's approach through a capacitive method for sensing a change of the capacitance. In an exemplary embodiment of the present inventive concept, the sensing structure180may detect the user's touch or the user's approach through an electromagnetic induction method, a pressure detection method, an infrared method, and the like. The black matrix BM may be disposed on the sensing structure180. In an exemplary embodiment of the present inventive concept, the black matrix BM may overlap the pixel defining layer PDL. For example, the black matrix may not overlap the first and third transparent electrodes141and151. As a width of the black matrix BM is reduced, an emission efficiency of the display device1000may be increased. The black matrix BM may absorb and/or block a light. For example, the black matrix BM may include Cr, such as, chromium oxide (CrO). As the black matrix BM absorbs and/or blocks the light, a stain caused by wirings arranged in a non-emission area may not be recognized by the user. The first and second color filters CF_1and CF_2may be disposed on the sensing structure180and the black matrix BM. Each of the first and second color filters CF_1and CF_2may partially overlap the black matrix BM. Colors of lights emitted by the first and second emission layers161and162may be more clearly recognized as the lights pass through the first and second color filters CF_1and CF_2. The display device1000may further include a planarization layer and a cover window disposed on the first and second color filters CF_1and CF_2. For example, the planarization layer may be formed of a polyimide, an acrylic, or an inorganic insulating layer. The planarization layer may be disposed to compensate for an overall height of the display device1000, and accordingly, an upper surface of the planarization layer may be a flat surface. For example, the cover window may include a glass or a plastic. In addition, the cover window may be formed of a single layer or a laminate in which a plurality of functional layers are stacked so that the cover window may protect components of the display device1000from an external impact. In addition, since the display device1000does not include a polarizer, a weight and a thickness of the display device may be reduced, and lights emitted from the first and second emission layers161and162may be recognized more brightly. In the display device1000according to an exemplary embodiment of the present inventive concept, the first reflective electrode143may be disposed in the first region10, and the second reflective electrode153may be disposed in the fourth and fifth regions40and50, so that an external light is not reflected at distal ends of the first and second lower electrodes140and150. Accordingly, a reflected light emitted along a path different from a path of a light emitted from the first and second emission layer161and162may not occur, and a color band may not be generated. Since the display device1000does not generate the color band, a user may more clearly recognize a color of a light emitted from a pixel structure. FIG.3is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.3is a cross-sectional view taken along a line I-I′ ofFIG.1. Referring toFIGS.1and3, the display device1000may include a substrate210, a first thin film transistor217, a second thin film transistor227, a gate insulating layer212, an interlayer insulating layer214, a via insulating layer230, a first lower electrode240, a second lower electrode250, a first emission layer261, a second emission layer262, an upper electrode270, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure280, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. However, since the components except the second lower electrode250of the display device1000are a substantially same as the substrate110, the first thin film transistor117, the second thin film transistor127, the gate insulating layer112, the interlayer insulating layer114, the via insulating layer130, the first lower electrode140, the first emission layer161, the second emission layer162, the upper electrode170, the pixel defining layer PDL, the thin film encapsulation layer TFE, the sensing structure180, the first color filter CF_1, the second color filter CF_2, and the black matrix BM described above with reference toFIG.2, the second lower electrode250will be described in detail below. The second pixel structure PXL_2may include the second lower electrode250and the second emission layer262. The second pixel structure PXL_2may overlap the second thin film transistor227. In addition, the second pixel structure PXL_2may be spaced apart from the first pixel structure PXL_1. The second lower electrode250may include the third transparent electrode251, the second reflective electrode253, and the fourth transparent electrode255. In addition, the second lower electrode250may have a shape different from a shape of the first lower electrode240. The third transparent electrode251may be disposed on the via insulating layer230. The third transparent electrode251may be formed by patterning a metal layer to be disposed in the second contact hole CNT_2after the metal layer is deposited on the via insulating layer230including the first and second contact holes CNT_1and CNT_2. Accordingly, the third transparent electrode251may be formed to have a substantially constant thickness along a profile of the via insulating layer130. In addition, the third transparent electrode251may be formed simultaneously with the first transparent electrode241. In an exemplary embodiment of the present inventive concept, the third transparent electrode251may be formed in the second contact hole CNT_2. In an exemplary embodiment of the present inventive concept, the third transparent electrode251may overlap the fourth region40, the fifth region50, and the sixth region60. The fourth region40overlaps the second emission layer262. The fifth region50is located in one side of the fourth region40and overlaps the second contact hole CNT_2. The sixth region60is located in the other side of the fourth region40. In an exemplary embodiment of the present inventive concept, the third transparent electrode251may contact the entire second drain electrode226exposed by the second contact hole CNT_2. In an exemplary embodiment of the present inventive concept, the third transparent electrode251may contact a portion of the second drain electrode226exposed by the second contact hole CNT_2, and may not contact a remaining portion of the second drain electrode226exposed by the second contact hole CNT_2. For example, when the third transparent electrode251does not contact the remaining portion, the second reflective electrode253and/or the fourth transparent electrode255may contact the remaining portion of the second drain electrode226. The third transparent electrode251may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the third transparent electrode251may include Ni, Cr, Ti, ITO, IZO, and the like. The second reflective electrode253may be disposed on the third transparent electrode251. The second reflective electrode253may be formed by patterning a metal layer to overlap the third transparent electrode251after the metal layer is deposited on the via insulating layer230and the third transparent electrode251. In addition, a thickness of the second reflective electrode253may be larger than a thickness of the third transparent electrode251. In addition, the second reflective electrode253may be formed simultaneously with the first reflective electrode243. The second reflective electrode253may include a reflective electrode. In an exemplary embodiment of the present inventive concept, the second reflective electrode253may include Ag, Al, Cu, Pt, an alloy including Ag, and the like. In an exemplary embodiment of the present inventive concept, the second reflective electrode253may overlap the fourth region40and the sixth region60. For example, the second reflective electrode253may be formed by patterning a metal layer to overlap the fourth region40and the sixth region60after the metal layer is deposited on the via insulating layer230and the third transparent electrode251. Accordingly, the second reflective electrode253may not overlap the fifth region50. The fourth transparent electrode255may be disposed on the second reflective electrode253. In an exemplary embodiment of the present inventive concept, the second reflective electrode253and the fourth transparent electrode255may be formed by simultaneously patterning metal layers after the metal layers are deposited on the via insulating layer230and the third transparent electrode251. In addition, the second reflective electrode253and the fourth transparent electrode255may be formed simultaneously with the first reflective electrode243and the second transparent electrode245. The fourth transparent electrode255may include a transparent electrode. In an exemplary embodiment of the present inventive concept, the fourth transparent electrode255may include, for example, Ni, Cr, Ti, ITO, IZO, and the like. In an exemplary embodiment of the present inventive concept, the fourth transparent electrode255may include a substantially same material as the third transparent electrode251. FIG.4is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.4is a cross-sectional view taken along a line I-I′ ofFIG.1. Referring toFIGS.1and4, the display device1000may include a substrate310, a first thin film transistor317, a second thin film transistor327, a gate insulating layer312, an interlayer insulating layer314, a via insulating layer330, a first lower electrode340, a second lower electrode350, a first emission layer361, a second emission layer362, an upper electrode370, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure380, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. However, since the components except the first and second lower electrodes340and350of the display device1000are a substantially same as the substrate110, the first thin film transistor117, the second thin film transistor127, the gate insulating layer112, the interlayer insulating layer114, the via insulating layer130, the first emission layer161, the second emission layer162, the upper electrode170, the pixel defining layer PDL, the thin film encapsulation layer TFE, the sensing structure180, the first color filter CF_1, the second color filter CF_2, and the black matrix BM described above with reference toFIG.2, the first and second lower electrodes340and350will be described in detail below. The first pixel structure PXL_1may include the first lower electrode340and the first emission layer361. The first pixel structure PXL_1may overlap the first thin film transistor317. The first lower electrode340may include a first transparent electrode341, a first reflective electrode343, and a second transparent electrode345. Since the first transparent electrode341is a substantially same as the first transparent electrode141described above with reference toFIG.2, the first reflective electrode343and the second transparent electrode345will be described in detail below. The first reflective electrode343may be disposed on the first transparent electrode341. The first reflective electrode343may be formed by patterning a metal layer to overlap the first transparent electrode341after the metal layer is deposited on the via insulating layer330and the first transparent electrode341. In addition, a thickness of the first reflective electrode343may be larger than a thickness of the first transparent electrode341. In an exemplary embodiment of the present inventive concept, the first reflective electrode343may overlap the first region10and the second region20. For example, the first reflective electrode343may be formed by patterning a metal layer to overlap the first region10and the second region20after the metal layer is deposited on the via insulating layer330and the first transparent electrode341. Accordingly, the first reflective electrode343may not overlap the third region30. The second transparent electrode345may be disposed on the first reflective electrode343. In an exemplary embodiment of the present inventive concept, the first reflective electrode343and the second transparent electrode345may be formed by simultaneously patterning metal layers after the metal layers are deposited on the via insulating layer330and the first transparent electrode341. The second pixel structure PXL_2may include the second lower electrode350and the second emission layer362. The second pixel structure PXL_2may overlap the second thin film transistor327. In addition, the second pixel structure PXL_2may be spaced apart from the first pixel structure PXL_1. The second lower electrode350may include a third transparent electrode351, a second reflective electrode353, and a fourth transparent electrode355. In addition, the second lower electrode350may have a shape different from a shape of the first lower electrode340. This will be described in detail below. Since the third transparent electrode351is a substantially same as the third transparent electrode151described above with reference toFIG.2, the second reflective electrode353and the fourth transparent electrode355will be described in detail below. The second reflective electrode353may be disposed on the third transparent electrode351. The second reflective electrode353may be formed by patterning a metal layer to overlap the third transparent electrode351after the metal layer is deposited on the via insulating layer330and the third transparent electrode351. In addition, a thickness of the second reflective electrode353may be larger than a thickness of the third transparent electrode351. In addition, the second reflective electrode353may be formed simultaneously with the first reflective electrode343. In an exemplary embodiment of the present inventive concept, the second reflective electrode353may overlap only the fourth region40. For example, the second reflective electrode353may be formed by patterning a metal layer to overlap only the fourth region40after the metal layer is deposited on the via insulating layer330and the third transparent electrode351. Accordingly, the second reflective electrode353may not overlap the fifth and sixth regions50and60. The fourth transparent electrode355may be disposed on the second reflective electrode353. In an exemplary embodiment of the present inventive concept, the second reflective electrode353and the fourth transparent electrode355may be formed by simultaneously patterning metal layers after the metal layers are sequentially deposited on the via insulating layer330and the third transparent electrode351. FIG.5is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.5is a cross-sectional view taken along a line I-I′ ofFIG.1. Referring toFIGS.1and5, the display device1000may include a substrate410, a first thin film transistor417, a second thin film transistor427, a gate insulating layer412, an interlayer insulating layer414, a via insulating layer430, a first lower electrode440, a second lower electrode450, a first emission layer461, a second emission layer462, an upper electrode470, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure480, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. The components ofFIG.5except the first lower electrode440of the display device1000are a substantially same as the substrate210, the first thin film transistor217, the second thin film transistor227, the gate insulating layer212, the interlayer insulating layer214, the via insulating layer230, the second lower electrode250, the first emission layer261, the second emission layer262, the upper electrode270, the pixel defining layer PDL, the thin film encapsulation layer TFE, the sensing structure280, the first color filter CF_1, the second color filter CF_2, and the black matrix BM described above with reference toFIG.3. In addition, the first lower electrode440may be a substantially same as the first lower electrode340described above with reference toFIG.4. FIG.6is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.6is a cross-sectional view taken along a line I-I′ ofFIG.1. Referring toFIGS.1and6, the display device1000may include a substrate510, a first thin film transistor517, a second thin film transistor527, a gate insulating layer512, an interlayer insulating layer514, a via insulating layer530, a first lower electrode540, a second lower electrode550, a first emission layer561, a second emission layer562, an upper electrode570, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure580, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. However, since the components except the first lower electrode540of the display device1000are a substantially same as the substrate310, the first thin film transistor317, the second thin film transistor327, the gate insulating layer312, the interlayer insulating layer314, the via insulating layer330, the second lower electrode350, the first emission layer361, the second emission layer362, the upper electrode370, the pixel defining layer PDL, the thin film encapsulation layer TFE, the sensing structure380, the first color filter CF_1, the second color filter CF_2, and the black matrix BM described above with reference toFIG.4, the first lower electrode540will be described in detail below. The first pixel structure PXL_1may include the first lower electrode540and the first emission layer561. The first pixel structure PXL_1may overlap the first thin film transistor517. The first lower electrode140may include a first transparent electrode541, a first reflective electrode543, and a second transparent electrode545. Since the first transparent electrode541may be a same as the first transparent electrode341described above with reference toFIG.4, the first reflective electrode543and the second transparent electrode545will be described in detail below. The first reflective electrode543may be disposed on the first transparent electrode541. The first reflective electrode543may be formed by patterning a metal layer to overlap the first transparent541after the metal layer is deposited on the via insulating layer530and the first transparent electrode541. In addition, a thickness of the first reflective electrode543may be larger than a thickness of the first transparent electrode541. In an exemplary embodiment of the present inventive concept, the first reflective electrode543may overlap the first region10and the third region30. For example, the first reflective electrode543may be formed by patterning a metal layer to overlap the first region10and the third region30after the metal layer is deposited on the via insulating layer530and the first transparent electrode541. Accordingly, the first reflective electrode543may not overlap the second region20. The second transparent electrode545may be disposed on the first reflective electrode543. In an exemplary embodiment of the present inventive concept, the first reflective electrode543and the second transparent electrode545may be formed by simultaneously patterning metal layers after the metal layers are deposited on the via insulating layer530and the first transparent electrode541. FIG.7is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.7is a cross-sectional view taken along a line I-I′ ofFIG.1. Referring toFIGS.1and7, the display device1000may include a substrate610, a first thin film transistor617, a second thin film transistor627, a gate insulating layer612, an interlayer insulating layer614, a via insulating layer630, a first lower electrode640, a second lower electrode650, a first emission layer661, a second emission layer662, an upper electrode670, a pixel defining layer PDL, a thin film encapsulation layer TFE, a sensing structure680, a first color filter CF_1, a second color filter CF_2, and a black matrix BM. The components except the first lower electrode640of the display device1000are a substantially same as the substrate110, the first thin film transistor117, the second thin film transistor127, the gate insulating layer112, the interlayer insulating layer114, the via insulating layer130, the second lower electrode150, the first emission layer161, the second emission layer162, the upper electrode170, the pixel defining layer PDL, the thin film encapsulation layer TFE, the sensing structure180, the first color filter CF_1, the second color filter CF_2, and the black matrix BM described above with reference toFIG.2. In addition, the first lower electrode640may be a substantially same as the first lower electrode540described above with reference toFIG.6. FIG.8is a cross-sectional view illustrating the display device according to an exemplary embodiment of the present inventive concept. For example,FIG.8is an enlarged view of an area A ofFIG.1. Referring toFIGS.1and8, the first pixel structure PXL_1and the second pixel structure PXL_2may be arranged in a pentile manner in the display area DA of the display device1000. The first pixel structure PXL_1may be divided into a first central region710and a first peripheral region730. The first central region710may be provided by the opening of the pixel defining layer PDL described above with reference toFIGS.2to7. The first peripheral region730may surround the first central region710, and may overlap the pixel defining layer PDL The first pixel structure PXL_1may include a first lower electrode, and the first lower electrode may include a first transparent electrode, a first reflective electrode disposed on the first transparent electrode, and a second transparent electrode disposed on the first reflective electrode. The first transparent electrode may overlap the first central region710and the first peripheral region730. In an exemplary embodiment of the present inventive concept, the first reflective electrode and the second transparent electrode may overlap only the first central region710. In an exemplary embodiment of the present inventive concept, the first reflective electrode and the second transparent electrode may extend to overlap the first central region710and at least a region of the first peripheral region730. The second pixel structure PXL_2may be divided into a second central region810and a second peripheral region830. The second central region810may be provided by the opening of the pixel defining layer PDL described above with reference toFIGS.2to7. The second peripheral region830may surround the first central region810, and may overlap the pixel defining layer PDL. The second pixel structure PXL_2may include a second lower electrode, and the second lower electrode may include a third transparent electrode, a second reflective electrode disposed on the third transparent electrode, and a fourth transparent electrode disposed on the second reflective electrode. The third transparent electrode may overlap the second central region810and the second peripheral region830. In an exemplary embodiment of the present inventive concept, the second reflective electrode and the fourth transparent electrode may overlap only the second central region810. In an exemplary embodiment of the present inventive concept, the second reflective electrode and the fourth transparent electrode may extend to overlap the second central region810and at least a region of the second peripheral region830. The present inventive concept may be applied to a display device and an electronic device using the display device. For example, the present inventive concept may be applied to a cellular phone, a smart phone, a video phone, a smart pad, a smart watch, a tablet personal computer (PC), a car navigation system, a television, a computer monitor, a laptop, etc. While the present inventive concept has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present inventive concept. | 50,190 |
11943966 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises/includes” and/or “comprising/including” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto. It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component or may be “indirectly connected” to the other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “connected to or electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component or may be “indirectly connected or electrically connected” to other layer, region, or component with other layer, region, or component interposed therebetween. A display device is an apparatus for displaying an image and may include an organic light-emitting display, an inorganic light-emitting display, a quantum dot light-emitting display, a field emission display, a surface-conduction electron-emitter display, and a plasma display. Hereinafter, although a display device according to an embodiment is described by using an organic light-emitting display device as an example, a display device according to an embodiment is not limited thereto and various types of display devices may be used. FIG.1is a plan view of a display device according to an exemplary embodiment. Referring toFIG.1, the display device may be formed by attaching a first substrate100and a second substrate200through a sealing member600. The sealing member600may surround the outer periphery of the first substrate100and the second substrate200and attach the first substrate100to the second substrate200. The display device includes a display area DA and a peripheral area PA outside the display area DA. The display device may display a predetermined image by using light emitted from a plurality of pixels arranged in the display area DA. The display area DA includes pixels P connected to a data line DL and a scan line SL, the data line extending in a first direction, and the scan line SL extending in a second direction intersecting with the first direction. Each pixel P is also connected to a driving voltage line PL extending in the first direction. Each of the pixels P may include a display element such as an organic light-emitting diode OLED. Each pixel P may emit, for example, red, green, blue, or white light through the organic light-emitting diode OLED. In the present specification, a pixel P may be understood as a pixel that emits red, green, blue, or white light as described above. Each pixel P may be electrically connected to built-in circuits arranged in the peripheral area PA. A built-in driving circuit unit40, a wiring unit50, a terminal unit30, a first power supply line10, and a second power supply line20may be arranged in the peripheral area PA. The built-in driving circuit unit40may include a plurality of thin film transistors and provide a scan signal to each pixel P through a scan line SL. The built-in driving circuit units40may be arranged on two opposite sides with the display area DA therebetween. Some of the pixels P arranged in the display area DA may be electrically connected to the built-in driving circuit unit40arranged on the left, and the rest of the pixels P may be electrically connected to the built-in driving circuit unit40arranged on the right. The present invention is not limited thereto. In an exemplary embodiment, the built-in driving circuit unit40may be arranged on only one side of the display area DA. The wiring unit50is arranged on one side of the built-in driving circuit unit40. The wiring unit50denotes a region in which wirings transferring a signal for driving the built-in driving circuit unit40are arranged. The terminal unit30may be arranged on one side of the first substrate100. The terminal unit30may be exposed without being covered by an insulating layer and electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal unit30. The printed circuit board PCB transfers a signal or power of a controller (not shown) to the terminal unit30. The controller may respectively provide a driving voltage ELVDD and a common ELVSS (seeFIGS.2A and2Bbelow) to the first power supply line10and the second power supply line20through a first connection line11and a second connection line21. The driving voltage ELVDD may be provided to each pixel P through the driving voltage line PL connected to the first power supply line10, and the common voltage ELVSS may be provided to the opposite electrode of a pixel P connected to the second power supply line20. The second power supply line20may have a loop shape having one open side and partially surround the display area DA. The second power supply line20may be arranged between the built-in driving circuit unit40and the display area DA. Since the second power supply line20provides the common voltage ELVSS, it may be called a common voltage supply line. A control signal generated by the controller may be transferred to the built-in driving circuit unit40and the wiring unit50through the printed circuit board PCB and a third connection line41and a fourth connection line51. Also, a signal transferred to the wiring unit50may be transferred to the built-in driving circuit unit40. A data driving circuit60is electrically connected to a data line DL. A data signal of the data driving circuit60may be provided to each pixel P through a data connection line61and the data line DL, the data connection line61being connected to the terminal unit30, and the data line DL being connected to the data connection line61. Though it is shown inFIG.1that the data driving circuit60is arranged in the printed circuit board PCB, the data driving circuit60may be arranged on the first substrate100. For example, the data driving circuit60may be arranged between the terminal unit30and the first power supply line10. A dam unit120may be arranged in the peripheral area PA. The dam unit120may prevent an edge tail of an organic encapsulation layer420(seeFIG.4) from being formed by blocking flowing of an organic material in an edge direction of the first substrate100while the organic encapsulation layer420of a thin-film encapsulation layer400is formed. The dam unit120in the peripheral area PA may surround at least a portion of the display area DA. The dam unit120may include a plurality of dams. In the case where the plurality of dams are arranged, the dams may be spaced apart from each other. The dam unit120may be arranged closer to the display area DA than the sealing member600in the peripheral area PA. At least a portion of the dam unit120overlaps the built-in driving circuit unit40. The present invention is not limited thereto. In an exemplary embodiment, a portion of the dam unit120may overlap the wiring unit50. Since the dam unit120overlaps the built-in driving circuit unit40and/or the wiring unit50, the dam unit120may be arranged without occupying a separate region for the dam unit120. Therefore, a size of the peripheral area PA may be reduced. However, the present embodiment is not limited thereto. The dam unit120may not overlap the built-in driving circuit unit40and the wiring unit50. FIGS.2A and2Bare equivalent circuit diagrams of one of the pixels of the display device ofFIG.1according to an exemplary embodiment. Referring toFIG.2A, a pixel P includes a pixel circuit PC and an organic light-emitting diode OLED, the pixel circuit PC being connected to a scan line SL and a data line DL, and the organic light-emitting diode OLED being connected to the pixel circuit PC. The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2is connected to the scan line SL and the data line DL and transfers a data signal Dm input through the data line DL to the driving thin film transistor T1in response to a scan signal Sn input through the scan line SL. The storage capacitor Cst is connected to the switching thin film transistor T2and the driving voltage line PL and stores a voltage corresponding to a voltage difference between a voltage transferred from the switching thin film transistor T2and the first power voltage ELVDD (or a driving voltage) supplied to the driving voltage line PL. The driving thin film transistor T1is connected to the driving voltage line PL and the storage capacitor Cst and may control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having predetermined brightness by using the driving current. Though it is shown inFIG.2Athat the pixel circuit PC includes two thin film transistors and one storage capacitor, the present invention is not limited thereto. Referring toFIG.2B, a pixel PX includes the organic light-emitting diode OLED and the pixel circuit PC including a plurality of thin film transistors driving the organic light-emitting diode OLED. The pixel circuit PC includes the driving thin film transistor T1, the switching thin film transistor T2, a sensing thin film transistor T3, and the storage capacitor Cst. The scan line SL is connected to a gate electrode G2of the switching thin film transistor T2, the data line DL is connected to a source electrode S2, and a first electrode CE1of the storage capacitor Cst may be connected to a drain electrode D2. Therefore, the switching thin film transistor T2supplies a data voltage of the data line DL to a first node N in response to a scan signal Sn from the scan line SL of the pixel P. A gate electrode G1of the driving thin film transistor T1is connected to the first node N, a source electrode S1is connected to a first power line PL1transferring the driving power voltage ELVDD, and a drain electrode D1is connected to an anode electrode of the organic light-emitting diode OLED. Therefore, the driving thin film transistor T1may adjust a current amount flowing through the organic light-emitting diode OLED depending on a source-gate voltage Vgs of the driving thin film transistor T1, that is, a voltage applied between the driving power voltage ELVDD and the first node N. A gate electrode G3of the sensing thin film transistor T3is connected to a sensing control line SSL, a source electrode S3is connected to a second node S, and a drain electrode D3is connected to a reference voltage line RL. The present invention is not limited thereto. In an exemplary embodiment, the sensing thin film transistor T3may be controlled by the scan line SL instead of the sensing control line SSL. The sensing thin film transistor T3may sense an electric potential of the anode electrode of the organic light-emitting diode OLED. The sensing thin film transistor T3supplies a pre-charging voltage from the reference voltage line RL to the second node S in response to a sensing signal SSn from the sensing control line SSL or supplies a voltage of the anode electrode AD of the organic light-emitting diode OLED to the reference voltage line RL for a sensing period. The first electrode CE1of the storage capacitor Cst is connected to the first node N, and a second electrode CE2of the storage capacitor Cst is connected to the second node S. The storage capacitor Cst is charged with a voltage difference between a voltage supplied to the first node N and a voltage supplied to the second node S and supplies the charged voltage difference as a driving voltage of the driving thin film transistor T1. For example, the storage capacitor Cst may be charged with a voltage difference between a voltage of the data signal Dm supplied to the first node and the driving power voltage ELVDD supplied to the second node S. A bias electrode BSM is formed to correspond to the driving thin film transistor T1and connected to the source electrode S3of the sensing thin film transistor T3. Since the bias electrode BSM is supplied with a voltage in cooperation with an electric potential of the source electrode S3of the sensing thin film transistor T3, the driving thin film transistor T1may be stabilized. The present invention is not limited thereto. In an exemplary embodiment, the bias electrode BSM may not be connected to the source electrode S3of the sensing thin film transistor T3and may be connected to a separate bias line. The opposite electrode (e.g. a cathode) of the organic light-emitting diode OLED receives the common power voltage ELVSS. The organic light-emitting diode OLED emits light by receiving the driving current from the driving thin film transistor T1. Though it is shown inFIG.2Bthat the pixel P includes the signal lines SL, SSL, and DL, the reference voltage line RL, the first power line PL1, and a second power line PL2, the present invention is not limited thereto. For example, at least one of the signal lines SL, SSL, and DL, and/or the reference voltage line RL, the first power line PL1, and the second power line PL2may be shared by neighboring pixels. The pixel circuit PC is not limited to the number of thin film transistors, the number of storage capacitors, and the circuit design described with reference toFIGS.2A and2B, and the number and the circuit design may be variously modified. FIG.3is a plan view of a portion of a display device according to an exemplary embodiment and corresponds to a region A ofFIG.1.FIG.4is a cross-sectional view of a portion of a display device according to an exemplary embodiment and corresponds to line I-I′ ofFIG.1and line II-II′ ofFIG.3.FIG.5is a cross-sectional view of a comparative example for comparison with an exemplary embodiment. Referring toFIGS.3and4, the display device according to an exemplary embodiment includes the display area DA and the peripheral area PA outside the display area DA. In an exemplary embodiment, the peripheral area PA may surround the display area DA. At least one thin film transistor T1and a display element connected to the thin film transistor T1may be arranged in the display area DA. The dam unit120, a support130, and the sealing member600are arranged in the peripheral area PA. In an exemplary embodiment of the present invention, the display area DA of the display device includes a plurality of pixels, that is, a first pixel P1, a second pixel P2, and a third pixel P3, each pixel including a corresponding emission area of a plurality of emission areas EA. Each of the emission areas EA may include an area in which light is generated and emitted to the outside. A non-emission area NEA may be arranged between the emission areas EA. For example, the emission areas EA of the pixels P1, P2, and P3may be separately defined by the non-emission area NEA. In an exemplary embodiment, the display area DA may include the plurality of emission areas EA and the non-emission area NEA. The non-emission area NEA may surround each of the plurality of emission areas EA. Each of the plurality of pixels may be disposed in a corresponding emission area of the plurality of emission areas EA. InFIG.3, the first pixel P1, the second pixel P2, and the third pixel P3may respectively produce different lights. For example, the first pixel P1may produce red light, the second pixel P2may produce green light, and the third pixel P3may produce blue light. In the drawing, though the emission areas of the first pixel P1, the second pixel P2, and the third pixel P3have a rounded rectangular shape and are arranged in a stripe, the present invention is not limited thereto. The emission area EA of each pixel may have various polygonal shapes or a circular shape and may be arranged in various configurations such as a pentile arrangement. The display device according to an exemplary embodiment of the present invention includes a pattern layer500including a first opening OP1and a first light-blocking pattern510, the first opening OP1exposing the emission area EA, and the first light-blocking pattern510shielding the non-emission area NEA. For example, the first opening OP1is vertically aligned with the emission area EA such that the first opening OP1and the emission area EA, when viewed in a plan view, overlap each other, and the first light-blocking pattern510and the non-emission area NEA, when viewed in a plan view, overlap each other. Also, the display device according to an exemplary embodiment of the present embodiment includes the second substrate200on which a second opening OP2and a second light-blocking pattern210are formed, the second opening OP2corresponding to the first opening OP1, and the second light-blocking pattern210corresponding to the non-emission area NEA. For example, the second opening OP2is vertically aligned with the first opening OP1such that the first opening OP1and the second opening OP2, when viewed in a plan view, overlap each other, and the second light-blocking pattern210and the first light-blocking pattern510, when viewed in a plan view, overlap each other. In an exemplary embodiment, the first opening OP1and the second opening OP2are vertically aligned with the emission area EA such that light emitted therefrom may travel through the first opening OP1and the second opening OP2. The first light-blocking pattern510and the second light-blocking pattern210are vertically aligned with the non-emission area NEA such that some light emitted from the emission area EA is blocked. Hereinafter, the display device of an exemplary embodiment is described in detail according to a stacking sequence shown inFIG.4. The display area DA ofFIG.4shows the driving thin film transistor T1and the storage capacitor Cst of the pixel circuit PC of the pixel P described with reference toFIGS.2A and2B. For convenience of description, a configuration arranged in the display area DA ofFIG.4is described according to a stacking sequence. The first substrate100may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. In the case where the first substrate100includes a flexible or bendable material, the first substrate100may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyacrylate, polyimide, polycarbonate, or cellulose acetate propionate. The first substrate100may have a single-layered or multi-layered structure including the above materials. In the case where the first substrate100has a multi-layered structure, the first substrate100may further include an inorganic layer. In an exemplary embodiment, the first substrate100may have a structure including an organic material/inorganic material/organic material. A barrier layer (not shown) may be further arranged between the first substrate100and a first buffer layer111. The barrier layer may prevent or minimize penetration of impurities into a semiconductor layer A1from the first substrate100. The barrier layer may include an inorganic material such as an oxide or a nitride, or an organic material, or an organic/inorganic composite material and have a single-layered or multi-layered structure including an inorganic material and an organic material. The bias electrode BSM is arranged on the first buffer layer111to correspond to the driving thin film transistor T1. For example, the bias electrode BSM is disposed under the driving thin film transistor T1. A voltage may be applied to the bias electrode BSM. For example, the source electrode S3(seeFIG.2B) of the sensing thin film transistor T3(seeFIG.2B) may be connected to the bias electrode BSM and thus a voltage of the source electrode S3may be applied to the bias electrode BSM. Also, the bias electrode BSM may prevent external light from reaching the semiconductor layer A1. Therefore, a characteristic of the driving thin film transistor T1may be stabilized. The bias electrode BSM may be omitted depending on a case. A second buffer layer112covers the bias electrode BSM. The second buffer layer112may be formed on an entire surface of the first substrate100. The second buffer layer112may include SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. The semiconductor layer A1is arranged on the second buffer layer112. The semiconductor layer A1may include amorphous silicon or polycrystalline silicon. The present invention is not limited thereto. In an exemplary embodiment, the semiconductor layer A1may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. For example, the semiconductor layer A1may include, as a Zn oxide-based material, Zn oxide, In—Zn oxide, and Ga—In—Zn oxide. For another example, the semiconductor layers A1may include a semiconductor including IGZO (In—Ga—Zn—O), ITZO (In—Sn—Zn—O), or IGTZO (In—Ga—Sn—Zn—O) in which ZnO contains metal such as In, Ga, or Sn. The semiconductor layer A1may include a channel region, and a source region and a drain region respectively arranged on two opposite sides of the channel region. The semiconductor layer A1may include a single layer or a multi-layer. The gate electrode G1is arranged over the semiconductor layer A1with a gate insulating layer113therebetween such that the gate electrode G1overlaps at least a portion of the semiconductor layer A1. The gate electrode G1may include at least one of Mo, Al, Cu, and Ti and may include a single layer or a multi-layer. For example, the gate electrode G1may include a single layer including Mo. The first electrode CE1of the storage capacitor Cst may be arranged on the same layer on which the gate electrode G1is arranged. The first electrode CE1may include the same material as that of the gate electrode G1. An interlayer insulating layer115covers the gate electrode G1and the first electrode CE1of the storage capacitor Cst. The interlayer insulating layer115may include SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. The second electrode CE2of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL are arranged on the interlayer insulating layer115. The second electrode CE2of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL may include a conductive material including Mo, Al, Cu, or Ti and include a single layer or a multi-layer including the above materials. For example, the second electrode CE2, the source electrode S1, the drain electrode D, and the data line DL may include a multi-layered structure of Ti/Al/Ti. The source electrode S1and the drain electrode D1may be connected to a source region and a drain region of the semiconductor layer A1through a contact hole, respectively. The second electrode CE2of the storage capacitor Cst overlaps the first electrode CE1with the interlayer insulating layer115therebetween and forms a capacitance in cooperation with the first electrode CE1. In this case, the interlayer insulating layer115may serve as a dielectric layer of the storage capacitor Cst. The second electrode CE2of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the data line DL are covered by an inorganic protective layer PVX. The inorganic protective layer PVX may include a single layer or a multi-layer including SiNxand SiOx. The inorganic protective layer PVX may cover and protect some of wirings arranged on the interlayer insulating layer115. Wirings (not shown) simultaneously formed with the data line DL during the same process of forming the data line DL may be exposed to a partial area (e.g. a portion of the peripheral area PA) of the first substrate100. An exposed portion of the wirings may be damaged by etchant used while the pixel electrode310is patterned. Since the inorganic protective layer PVX covers the data line DL and at least some of the wirings simultaneously formed with the data line DL as in an exemplary embodiment of the present invention, the damage of the wirings may be prevented during a patterning operation of the pixel electrode310. A planarization layer118is arranged on the inorganic protective layer PVX, and the organic light-emitting diode OLED is arranged on the planarization layer118. The planarization layer118may include a single layer or a multi-layer including an organic material and provide a flat top surface. The planarization layer118may include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), or polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof. The organic light-emitting diode OLED is arranged on the planarization layer118in the display area DA of the first substrate100. The organic light-emitting diode OLED includes the pixel electrode310, an intermediate layer320, and an opposite electrode330, the intermediate layer320including an organic emission layer. The pixel electrode310may include a transparent electrode, a semi-transparent electrode or a reflective electrode. In an exemplary embodiment, the pixel electrode310may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, the reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode310may have a structure of ITO/Ag/ITO. A pixel-defining layer119is arranged on the planarization layer118. The pixel-defining layer119defines an emission area of the pixel P by including an opening corresponding to each of sub-pixels in the display area DA, that is, a third opening OP3that exposes at least a central portion of the pixel electrode310. Also, the pixel-defining layer119may prevent an arc, etc. from occurring at an edge of the pixel electrode310by increasing a distance between the edge of the pixel electrode310and the opposite electrode330over the pixel electrode310. The pixel-defining layer119may include at least one of organic insulating materials including polyimide, polyamide, an acrylic resin, BCB, or a phenolic resin and may be formed by spin coating, etc. The intermediate layer320of the organic light-emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material which emits red, green, blue, or white light. The organic emission layer may include a low molecular weight or polymer organic material. A functional layer such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively further arranged under and on the organic emission layer. The intermediate layer320may correspond to each of the plurality of pixel electrodes310. For example, the intermediate layer320may be separately formed on a corresponding pixel electrode of the plurality of pixel electrodes310. However, the present invention is not limited thereto. In an exemplary embodiment, the intermediate layer320may include a single layer provided as one body over the plurality of pixel electrodes310. Various modifications may be made. The opposite electrode330may include a light-transmissive electrode or a reflective electrode. In an exemplary embodiment, the opposite electrode330may include a transparent or semi-transparent electrode and may include a metal thin film having a small work function and including at least one of Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and a compound thereof. Also, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In2O3may be further arranged on the metal thin film. The opposite electrode330may be arranged over the display area DA and the peripheral area PA and arranged over the intermediate layer320and the pixel-defining layer119. The opposite electrode330may be provided as one body over a plurality of organic light-emitting diodes OLED and may correspond to the plurality of pixel electrodes310. A spacer119S for preventing mask chopping may be further provided on the pixel-defining layer119. The spacer119S may be provided as one body with the pixel-defining layer119. For example, the spacer119S and the pixel-defining layer119may be simultaneously formed by a half-tone mask process during the same process. Since the organic light-emitting diode OLED may be easily damaged by external moisture, oxygen, etc., the organic light-emitting diode OLED may be covered and protected by the thin-film encapsulation layer400. The thin-film encapsulation layer400may cover the display area DA and extend to the outside of the display area DA. The thin-film encapsulation layer400may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin-film encapsulation layer400includes a first inorganic encapsulation layer410, an organic encapsulation layer420, and a second inorganic encapsulation layer430. The first inorganic encapsulation layer410may cover the opposite electrode330and include silicon oxide, silicon nitride, or tri-silicon oxynitride. Though not shown, when needed, other layers such as a capping layer may be arranged between the first inorganic encapsulation layer410and the opposite electrode330. Since the first inorganic encapsulation layer410is formed along a structure thereunder, a top surface thereof is not flat. The organic encapsulation layer420covers the first inorganic encapsulation layer410. Unlike the first inorganic encapsulation layer410, a top surface of the organic encapsulation layer420may be approximately flat. Specifically, the top surface of the organic encapsulation layer420that corresponds to the display area DA may be approximately flat. The organic encapsulation layer420may include at least one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonates (PC), polyimide (PI), polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane (HMDSO). The second inorganic encapsulation layer430may cover the organic encapsulation layer420and include silicon oxide, silicon nitride and/or silicon tri-oxynitride. Even when a crack occurs inside the thin-film encapsulation layer400, the thin-film encapsulation layer400may prevent cracks from propagating to be connected to each other through such a multi-layered structure, the cracks occurring between the first inorganic encapsulation layer410and the organic encapsulation layer420or between the organic encapsulation layer420and the second inorganic encapsulation layer430. In other words, forming of a path through which external moisture or oxygen may penetrate the display area DA may be prevented or minimized. The pattern layer500is arranged on the thin-film encapsulation layer400. The pattern layer500may include an element preventing light generated from an emission area EA of the first pixel P1from being emitted to an emission area EA of the second pixel P2that is adjacent thereto. The pattern layer500includes the first light-blocking pattern510configured to shield at least a portion of the non-emission area NEA arranged between the emission areas EA of the first pixel P1, the second pixel P2, and the third pixel P3. Also, the pattern layer500further includes the first opening OP1exposing an emission area EA. Lights generated from the emission areas EA of the first pixel P1, the second pixel P2, and the third pixel P3may be emitted through the openings OP1. The first light-blocking pattern510may include metal. For example, the first light-blocking pattern510may include a conductive material including Mo, Al, Cu, or Ti and include a single layer or a multi-layer including the above materials. For example, the first light-blocking pattern510may have a multi-layered structure of Ti/Al/Ti. However, the present invention is not limited thereto. For example, the first light-blocking pattern510may include a black matrix including at least one of black pigment, black dye, and black particle. In an exemplary embodiment, the second light-blocking pattern210is arranged on the second substrate200facing the first substrate100. The second light-blocking pattern210may include a black matrix and include a member for increasing color saturation and contrast. The second light-blocking pattern210may include the second opening OP2exposing the emission area EA. For example, the second opening OP2vertically overlaps the emission area EA. The second light-blocking pattern210may include a material that absorbs a visible light. The second light-blocking pattern210may include at least one of black pigment, black dye, and black particle. In an exemplary embodiment, the second light-blocking pattern210may include materials such as Cr or CrOx, Cr/CrOx, Cr/CrOx/CrNy, a resin (carbon pigment, RGB mixed pigment), graphite, or non-Cr-based materials. A protective layer220is arranged on the second substrate200to cover the second light-blocking pattern210. The protective layer220may include an inorganic material such as SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. The protective layer220may include an organic material such as PI or epoxy. The second light-blocking pattern210may also block light coming from an emission area of a neighboring pixel. However, in the display device according to the present embodiment, since a member such as the thin-film encapsulation layer400is employed on the organic light-emitting diode OLED, an interval between the intermediate layer320and the second light-blocking pattern210may be large, the intermediate layer320emitting light. Accordingly, in the case where there is no first light-blocking pattern510as inFIG.5, which is a comparative example of the present invention, even though the second light-blocking pattern210is arranged on the second substrate200, light LP′ coming from the first pixel P1may not be prevented from being emitted to the emission area EA of the second pixel P2that is adjacent thereto. In contrast, according to the present embodiment, light LP that is emitted in a direction of the second pixel P2among lights generated from the organic light-emitting diode OLED of the first pixel P1may be blocked by the first light-blocking pattern510arranged closer to the intermediate layer320than the second light-blocking pattern210and thus not be emitted to the emission area EA of the second pixel P2. The built-in driving circuit unit40(seeFIG.1), the wiring unit50, the dam unit120, the support130, and the sealing member600may be arranged in the peripheral area PA outside the display area DA. The wiring unit50may include a first wiring W1, a second wiring W2, and a third wiring W3that are arranged on the first substrate100. The first wiring W1and the second wiring W2may be connected to the terminal unit30(seeFIG.1) to transfer a control signal supplied from the controller, and the third wiring W3may transfer the control signal to the built-in driving circuit unit40(seeFIG.1). The first wiring W1may be arranged on the same layer as a layer on which the gate electrode G1is arranged and may be simultaneously formed with the gate electrode G1by using the same material as that of the gate electrode G1. For example, the first wiring W1and the gate electrode G1may be simultaneously formed on the gate insulating layer113. In this case, the first wiring W1and the gate electrode G1may be formed using the same material. The second wiring W2may be arranged on the same layer as a layer on which the bias electrode BSM is arranged and may be simultaneously formed with the bias electrode BSM by using the same material as that of the bias electrode BSM. For example, the second wiring W2and the bias electrode BSM may be simultaneously formed on the first buffer layer111. In this case, the second wiring W2and the bias electrode BSM may be formed using the same material. The third wiring W3may be arranged on the same layer as a layer on which the source electrode S1or the drain electrode D1is arranged and may be simultaneously formed with the source electrode S1or the drain electrode D1by using the same material as that of the source electrode S1or the drain electrode D1. For example, the third wiring W3, the source electrode S1and the drain electrode D1may be formed on the interlayer insulating layer115. In this case, the third wiring W3, the source electrode S1and the drain electrode D1may be formed using the same material. The dam unit120is arranged outside the planarization layer118and the pixel-defining layer119, each extending from the display area DA. The dam unit120is spaced apart from the planarization layer118and the pixel-defining layer119. The dam unit120may prevent an organic material from flowing to an edge of the first substrate100while the organic encapsulation layer420of the thin-film encapsulation layer400is formed. In the case where the dam unit120is provided as a plurality of dam units, the plurality of dam units may be spaced apart from each other. The dam unit120may have a single-layered or multi-layered structure. The dam unit120may have a structure in which a first layer120a, a second layer120b, and a third layer120care stacked. In this case, the first layer120amay be simultaneously formed with the planarization layer118by using the same material as that of the planarization layer118. The second layer120bmay be simultaneously formed with the pixel-defining layer119by using the same material as that of the pixel-defining layer119. The third layer120cmay be simultaneously formed with the spacer119S by using the same material as that of the spacer119S. Since the first inorganic encapsulation layer410and the second inorganic encapsulation layer430of the thin-film encapsulation layer400directly contact each other outside the dam unit120, the organic encapsulation layer420may not be exposed to the outside. That is, penetration of external air or moisture through the organic material may be prevented. The inorganic protective layer PVX directly contacts the first inorganic encapsulation layer410in an inner region inside the dam unit120, that is, a region adjacent to the display area DA. Since both the first inorganic encapsulation layer410and the inorganic protective layer PVX include an inorganic material, adhesive force may be reinforced. Also, since an organic material is not arranged in a region between the dam unit120and the support130, moisture transmission of external air may be effectively prevented. The support130is arranged outside the dam unit120. The support130may include a member for supporting a mask used during a mask process. That is, a mask support may be provided to one side of the mask and may be engaged with the support130of the display device to support the mask. Since the support130may include an organic material, the support130may perform a buffering function in supporting the mask. The support130may not only support the mask but also suppress transfer of a crack onto the display area DA. The support130has a structure protruding from a top surface of the first substrate100and may be called a protrusion. The support130may be simultaneously formed with the planarization layer118by using the same material as that of the planarization layer118. The height of the support130may be less than that of the dam unit120. The support130may overlap at least a portion of the wiring unit50. Therefore, a size of the peripheral area PA may be reduced. The sealing member600is arranged outside the support130to attach the first substrate100to the second substrate200. The sealing member600may surround the outer side of the peripheral area PA in the outside of the support130. The sealing member600may include sealant and frit. A filling material610is arranged between the first substrate100and the second substrate200. The filling material610may perform a buffering function against external pressure, etc. The filling material610may include an organic material such as methyl silicon, phenyl silicon, or P1. However, the filling material610is not limited thereto and may include a urethane-based resin, an epoxy-based resin, an acrylic-based resin, which are organic sealants, or silicon, which is an inorganic sealant. A polarization plate, a touchscreen panel, etc. may be further arranged on a top surface of the second substrate200which is opposite to a surface on which the second light-blocking pattern210is arranged. FIG.6is an enlarged cross-sectional view of a portion B ofFIG.4and shows arrangement relation of the pixel-defining layer119, the pattern layer500, and the second light-blocking pattern210. Referring toFIG.6, the pixel-defining layer119includes the third opening OP3that exposes a central portion of the pixel electrode310. The emission area EA of the pixel P is defined by a lower end of the pixel-defining layer119where a lateral side of the third opening OP3and the pixel electrode310meet each other. Since the lateral side of the third opening OP3may have an oblique inclination, a bottom surface and a top surface of the third opening OP3may have different areas. In the present embodiment, an area of the third opening OP3may be defined as an area of the bottom surface which is a boundary where the lateral side of the third opening OP3and the pixel electrode310meet each other. The second opening OP2is arranged in the second light-blocking pattern210on the second substrate200to correspond to the emission area EA. For example, the second opening OP2is vertically aligned with the emission area EA such that the second opening OP2overlaps the emission area EA. An area of the second opening OP2may be substantially the same as an area of the third opening OP3. Since a final emission area EA through which light is emitted to the outside of the display device may be defined by the second opening OP2, it may be advantageous that the area of the second opening OP2coincides with an emission area that emits light in the intermediate layer320in aspects of an aperture ratio and contrast. To express this, it is shown inFIG.6that a width a2of the second opening OP2and a width a3of the third opening OP3are the same. The pattern layer500includes the first opening OP1corresponding to the third opening OP3. For example, the first opening OP1is vertically aligned with the third opening OP3such that the first opening OP1overlaps the third opening OP3. The area of the first opening OP1may be greater than the area of the third opening OP3. That is, since the first light-blocking pattern510is arranged to correspond to a top surface of the pixel-defining layer119, the area of the first opening OP1may be greater than the area of the third opening OP3. The first light-blocking pattern510prevents light leakage and does not need to be equal to the emission area EA. In the case where the first light-blocking pattern510is designed to be equal to the emission area EA, when an error occurs due to a process variation, the emission area EA may be rather reduced. That is, to secure a process margin, the first opening OP1may be greater than the third opening OP3and the second opening OP2. To express this, it is shown inFIG.6that a width a1of the first opening OP1is greater than the width a2of the second opening OP2and the width a3of the third opening OP3. FIG.7is a cross-sectional view of an exemplary embodiment. InFIG.7, since the same reference numerals as those ofFIG.4denote the same elements, repeated description thereof is omitted. The display device according to an exemplary embodiment of the present invention includes the first pixel P1, the second pixel P2, and the third pixel P3that are arranged in the display area DA, the thin-film encapsulation layer400covering the first pixel P1, the second pixel P2, and the third pixel P3, the pattern layer500arranged on the thin-film encapsulation layer400, and the second substrate200on which the second light-blocking pattern210is formed. In an exemplary embodiment, the second substrate200of the display device may include quantum emission layers QD1and QD2, that is, a first quantum emission layer QD1and a second quantum emission layer QD2, each including a quantum dot. A quantum dot may include a semiconductor particle having a diameter ranging from about 2 nm to about 10 nm and include a particle having a peculiar electrical optical property. When a quantum dot is exposed to light, the quantum dot may emit light in a specific frequency depending on a size of the particle and a kind of a material. For example, when a quantum dot is exposed to light, the quantum dot may emit red, green, or blue light depending on a size of the particle and/or a kind of a material. A core of a quantum dot may include a II-VI Group compound, a III-V Group compound, a IV-VI Group compound, a IV Group element, a IV Group compound, and a combination thereof. The II-VI Group compound may include: a two-element compound including CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, or a mixture thereof; a three-element compound including AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, or a mixture thereof; or a four-element compound including HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, or a mixture thereof. The III-V compound may include: a two-element compound including GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, or a mixture thereof; a three-element compound including GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, or a mixture thereof; or a four-element compound including GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, or a mixture thereof. The IV-VI Group compound may include: a two-element compound including SnS, SnSe, SnTe, PbS, PbSe, PbTe, or a mixture thereof; a three-element compound including SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, or a mixture thereof; or a four-element compound including SnPbSSe, SnPbSeTe, SnPbSTe, or a mixture thereof. The IV Group element may include Si, Ge, or a mixture thereof. The IV compound may include a two-element compound including SiC, SiGe, or a mixture thereof. In this case, the two-element compound, the three-element compound, or the four-element compound may exist inside a particle with uniform concentration or exist inside the same particle with partially different concentration distribution. The compound may have a core/shell structure in which one quantum dot surrounds another quantum dot. An interface between the core and the shell may have concentration gradient in which concentration of an element existing in the shell reduces toward a center thereof. In an exemplary embodiment, a quantum dot may have a core-shell structure including a core including a nano crystal, and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer for maintaining a semiconductor characteristic by preventing chemical denaturalization of the core, and/or serve as a charging layer for giving an electrophoretic characteristic to the quantum dot. The shell may have a single layer or a multi-layer. An interface between the core and the shell may have concentration gradient in which concentration of an element existing in the shell reduces toward a center thereof. Examples of the quantum dot include an oxide of metal or nonmetal, a semiconductor compound, or a combination thereof. For example, the oxide of metal or nonmetal may include a two-element compound including SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO, or a three-element compound including MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4. The present invention, however, is not limited thereto. The semiconductor compound may include CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb. The present invention, however, is not limited thereto. The quantum dot may have a full width of half maximum (FWHM) of an emission wavelength spectrum of 45 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and color saturation or color reproduction may be improved in this range. Since emitted light is discharged in all directions through the quantum dot, a light viewing angle may be improved. The quantum dot has a shape generally used in a relevant field and is not particularly limited. More specifically, a spherical dot, a pyramid dot, a multi-arm dot, or a cubic nano particle, a nano tube, a nano wire, a nano fiber, a nano plate-shaped particle, etc. may be used. The first quantum emission layer QD1and the second quantum emission layer QD2may be arranged to correspond to at least a portion of the emission area EA. For example, the first quantum emissions layer QD1may correspond to the emission area EA of the first pixel P1, and the second quantum emission layer QD2may correspond to the emission area EA of the second pixel P2. Instead of a quantum emission layer, a transmission window TW may be arranged in the emission area EA of the third pixel P3. The transmission window TW may include a material that may transmit light without wavelength conversion, the light being emitted from the organic light-emitting diode OLED of the third pixel P3. However, the transmission window is not limited thereto. A quantum emission layer may be arranged in the emission area EA of the third pixel P3. In an exemplary embodiment, all of the plurality of organic light-emitting diodes OLED may emit blue light. In this case, the first quantum emission layer QD1may include a quantum dot that emits red light, and the second quantum emission layer QD2may include a quantum dot that emits green light. Therefore, light emitted to the outside of the display device may include red, green, and blue lights, and various color expressions may be made through a combination of these colors. It may be understood that the first quantum emission layer QD1, the second quantum emission layer QD2, and the transmission window TW are arranged in the second opening OP2of the second light-blocking pattern210. Since the second light-blocking pattern210may include a black matrix that absorbs a visible light, color mixing of lights emitted from emission areas of neighbor pixels may be prevented, and visibility and contrast may be increased. In an exemplary embodiment, since the pattern layer500includes the first light-blocking pattern510arranged on the thin-film encapsulation layer400and corresponding to the non-emission area NEA, the first light-blocking pattern510may block lights emitted from the emission areas of neighboring pixels that, if the first light-blocking pattern510does not exist, cannot be blocked by the second light-blocking pattern210. FIG.8is a cross-sectional view of an exemplary embodiment. InFIG.8, since the same reference numerals as those ofFIG.4denote the same elements, repeated description thereof is omitted. The display device according to an exemplary embodiment of the present invention includes the first pixel P1, the second pixel P2, and the third pixel P3that are arranged in the display area DA, the thin-film encapsulation layer400covering the first pixel P1, the second pixel P2, and the third pixel P3, the pattern layer500arranged on the thin-film encapsulation layer400, and the second substrate200including the second light-blocking pattern210. In an exemplary embodiment, the first quantum emission layer QD1and the second quantum emission layer QD2may be formed on the second substrate200, each including a quantum dot, and color filters including a first color filter CF1, a second color filter CF2, and a third color filter CF3may be formed on the second substrate200. With the first color filter CF1, the second color filter CF2, and the third color filter CF3, a full-color image may be implemented and color saturation and outside visibility are increased. The first color filter CF1, the second color filter CF2, and the third color filter CF3may be arranged on the second substrate200to correspond to the second openings OP2of the second light-blocking pattern210. The protective layer220covers the second light-blocking pattern210, and the first color filter CF1, the second color filter CF2, and the third color filter CF3. Specifically, the first color filter CF1may correspond to the emission area EA of the first pixel P1, the second color filter CF2may correspond to the emission area EA of the second pixel P2, and the third color filter CF3may correspond to the emission area EA of the third pixel P3. The first quantum emission layer QD1, the second quantum emission layer QD2, and the transmission window TW overlap the first color filter CF1, the second color filter CF2, and the third color filter CF3respectively with the protective layer220therebetween. An additional protective layer230is further arranged over the second substrate200to cover the first quantum emission layer QD1, the second quantum emission layer QD2, and the transmission window TW. The additional protective layer230may include an organic material or an inorganic material. The first quantum emission layer QD1and the second quantum emission layer QD2may include quantum dots that emit different colors. For example, the first quantum emission layer QD1may emit red light, and the second quantum emission layer QD2may emit green light. The transmission window TW may transmit blue light emitted from the organic light-emitting diode OLED of the third pixel P3. In this case, the first color filter CF1may include a red color filter, the second color filter CF2may include a green color filter, and the third color filter CF3may include a blue color filter. Since the display device according to the present embodiment increases a distance between the intermediate layer320of the organic light-emitting diode OLED and the second light-blocking pattern210due to the thin-film encapsulation layer400and/or the first quantum emission layer QD1and the second quantum emission layer QD2, etc., color mixing of neighboring pixels may be prevented by introducing the first light-blocking pattern510therebetween. FIG.9is a cross-sectional view of an exemplary embodiment. InFIG.9, since the same reference numerals as those ofFIG.4denote the same elements, repeated description thereof is omitted. The display device according to an exemplary embodiment of the present invention includes the first pixel P1, the second pixel P2, and the third pixel P3that are arranged in the display area DA, the thin-film encapsulation layer400covering the first pixel P1, the second pixel P2, and the third pixel P3, the pattern layer500arranged on the thin-film encapsulation layer400, and the second substrate200including the second light-blocking pattern210. A third buffer layer520is further arranged between the pattern layer500and the thin-film encapsulation layer400. The third buffer layer520may be introduced to efficiently form the first light-blocking pattern510of the pattern layer500. The third buffer layer520is formed on the thin-film encapsulation layer400over the entire surface of the first substrate100. In the case where the first light-blocking pattern510includes metal, a metal layer constituting the first light-blocking pattern510is entirely formed on the third buffer layer520, and then the metal layer may be patterned through etching. In this case, the third buffer layer520may serve to prevent the metal layer from being lifted in the process of forming the metal layer. The third buffer layer520may include SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. The third buffer layer520extends to not only the display area DA but also the peripheral area PA. In this case, a contact hole may be formed in the third buffer layer520to expose a terminal31of the terminal unit30. An additional terminal layer33is arranged inside the contact hole, the additional terminal layer33being simultaneously formed with the first light-blocking pattern510by using the same material as that of the first light-blocking pattern510. The terminal31is connected to a connection wiring CW through a contact hole, the connection wiring CW being arranged on a different layer and transferring an electrical signal to the display area DA. The connection wiring CW may be formed on the same layer as a layer on which the gate electrode G1is arranged and may include the same material as that of the gate electrode G1. The terminal31may be arranged on the same layer as a layer on which the source electrode/drain electrode S1/D1are arranged and may include the same material as that of the source electrode/drain electrode S1/D1. A touchscreen panel700is further arranged on a surface of the second substrate200that is opposite to a surface of the second substrate200on which the second light-blocking pattern210is arranged. The touchscreen panel700may include a touch electrode and measure a position coordinate of a contact portion on a surface of the touchscreen panel700. A window may be further arranged on the touchscreen panel700. FIG.10is a cross-sectional view of an exemplary embodiment. InFIG.10, since the same reference numerals as those ofFIG.9denote the same elements, repeated description thereof is omitted.FIG.10is a cross-section taken along line III-III′ and shows a portion of the terminal unit30. The terminal unit30of the display device according to an exemplary embodiment of the present invention includes the terminal31and the additional terminal layer33, the terminal31being connected to the connection wiring CW through a first contact hole CNT1, and the additional terminal layer33being connected to the terminal31through a second contact hole CNT′. The connection wiring CW is arranged on the gate insulating layer113. The connection wiring CW is arranged on the same layer as a layer on which the gate electrode G1(seeFIG.9) is arranged and may include the same material as that of the gate electrode G1. The terminal31is arranged on the interlayer insulating layer115. The terminal31is arranged on the same layer as a layer on which the source electrode S1(seeFIG.9) is arranged and may include the same material as that of the source electrode S1. The additional terminal layer33is arranged on the third buffer layer520and may include the same material as that of the first light-blocking pattern510(seeFIG.9). The first contact hole CNT1passes through the interlayer insulating layer115to expose a portion of the connection wiring CW arranged thereunder. The second contact hole CNT′ passes through the third buffer layer520to expose a portion of the terminal31arranged thereunder. The additional terminal layer33is connected to the terminal31through the second contact hole CNT′, and the terminal31is connected to the connection wiring CW through the first contact hole CNT1. A width Wf of the connection wiring CW in one direction may be less than a width Wp of the terminal31in one direction. Edges of the terminal31are covered by the planarization layer118. The planarization layer118includes an opening P_OP exposing a central portion of the terminal31. The third buffer layer520is arranged on the planarization layer118and covers the terminal31. The second contact hole CNT′ of the third buffer layer520is disposed in the opening P_OP. The additional terminal layer33may be simultaneously formed while the first light-blocking pattern510including a metal layer is formed. As described above, since the terminal unit30further includes the additional terminal layer33over the terminal31, the additional terminal layer33being connected to the terminal31, an electrical resistance of the terminal unit30may be reduced. Up to now, embodiments applicable to the present disclosure have been described. The embodiments may be implemented as separate embodiments and implemented as a combined embodiment. As described above, since the display device according to embodiments includes the pattern layer500, a high-quality image may be displayed. These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. | 63,602 |
11943967 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. FIG.1is a perspective view showing an organic light-emitting display panel having a touch sensor according to the present disclosure, andFIG.2is a plan view of the organic light-emitting display panel having the touch sensor according to the present disclosure. The organic light-emitting display panel having the touch sensor shown inFIGS.1and2includes a plurality of subpixels PXL arranged on a substrate111in a matrix fashion, an encapsulation unit140disposed on the subpixels PXL, and mutual capacitance Cm disposed on the encapsulation unit140. The organic light-emitting display panel having the touch sensor displays an image through the subpixels PXL, each of which includes a light-emitting element120, during a display period. In addition, the organic light-emitting display panel having the touch sensor detects variation in mutual capacitance Cm (the touch sensor) due to a user's touch during a touch period to sense whether a touch has been performed and the touched position. Each of the subpixels PXL, which are disposed in an active area of the organic light-emitting display panel having the touch sensor, includes a pixel-driving circuit and a light-emitting element120connected to the pixel-driving circuit. As shown inFIG.1, the pixel-driving circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cst. Meanwhile, in the present disclosure, the pixel-driving circuit has been described as including two transistors T and one capacitor C (2T1C) by way of example. However, the present disclosure is not limited thereto. That is, a 3T1C or 3T2C type pixel-driving circuit having three or more transistors T and one or more capacitors C may be used. When a scan pulse is supplied to a scan line SL, the switching transistor T1is turned on to supply a data signal, which is supplied to a data line DL, to the storage capacitor Cst and to a gate electrode of the driving transistor T2. In response to the data signal supplied to the gate electrode of the driving transistor T2, the driving transistor T2controls the current that is supplied from a high-voltage (VDD) supply line to the light-emitting element120to adjust the amount of light emitted by the light-emitting element120. Even when the switching transistor T1is turned off, the driving transistor T2supplies uniform current to the light-emitting element120using the voltage charged in the storage capacitor Cst such that the light-emitting element120keeps emitting light until a data signal of the next frame is supplied. To this end, as shown inFIG.3, the driving transistor T2includes a semiconductor layer134disposed on a buffer layer112, a gate electrode132overlapping the semiconductor layer134in the state in which a gate dielectric film102is disposed therebetween, and source electrode136and drain electrode138formed on an interlayer dielectric film114so as to contact the semiconductor layer134. The semiconductor layer134is made of at least one of an amorphous semiconductor material, a polycrystalline semiconductor material, or an oxide semiconductor material. The semiconductor layer134includes a channel area, a source area, and a drain area. The channel area overlaps the gate electrode132in the state in which the gate dielectric film102is disposed therebetween so as to be formed between the source and drain electrodes136and138. The source area is electrically connected to the source electrode136via a source contact hole, which is formed through the interlayer dielectric film114. The drain area is electrically connected to the drain electrode138via a drain contact hole, which is formed through the interlayer dielectric film114. The gate electrode132may be made of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu) or an alloy thereof, and may have a single-layered structure or a multi-layered structure. However, the present disclosure is not limited thereto. The gate electrode132overlaps the channel area of the semiconductor layer134in the state in which the gate dielectric film102is disposed therebetween. At this time, as shown inFIG.3, the gate dielectric film102may be formed so as to have the same line width as the gate electrode132in order to expose the side surface of the semiconductor layer134, or may be formed so as to have a larger line width than the gate electrode132in order to cover the side surface of the semiconductor layer134. Each of the source and drain electrodes136and138may be made of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu) or an alloy thereof, and may have a single-layered structure or a multi-layered structure. However, the present disclosure is not limited thereto. The source electrode136is connected to the source area of the semiconductor layer134, which is exposed through the source contact hole formed through both the gate dielectric film102and the interlayer dielectric film114or only through the interlayer dielectric film114. The drain electrode138faces the source electrode, and is connected to the drain area of the semiconductor layer134via the drain contact hole, which is formed through both the gate dielectric film102and the interlayer dielectric film114or only through the interlayer dielectric film114. The light-emitting element120includes an anode electrode122, at least one light-emitting stack124formed on the anode electrode122, and a cathode electrode126formed on the light-emitting stack124. The anode electrode122is electrically connected to the drain electrode138of the driving transistor T2, which is exposed through a pixel contact hole116formed through a passivation film108and a planarization layer118disposed on the driving transistor T2. The anode electrode122of each subpixel is formed so as to be exposed by a bank128. The bank128is formed so as to expose the anode132. The bank128may be made of an opaque material (e.g. black) in order to reduce optical interference between neighboring subpixels. In this case, the bank128includes a light-blocking material made of at least one of a color pigment, organic black, or carbon. The at least one light-emitting stack124is formed on the anode electrode122in a light-emitting area defined by the bank128. The at least one light-emitting stack124is formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer on the anode electrode122in that order or in the reverse order. In addition, the light-emitting stack124may include first and second light-emitting stacks that are opposite each other in the state in which a charge generation layer is disposed therebetween. In this case, the organic light-emitting layer of one of the first and second light-emitting stacks generates blue light, and the organic light-emitting layer of the other of the first and second light-emitting stacks generates yellowish-green light. Consequently, white light is generated by the first and second light-emitting stacks. The white light generated by the light-emitting stack124is incident on a color filter, which is located above or under the light-emitting stack124, to realize a color image. Alternatively, each light-emitting stack124may generate colored light corresponding to a respective subpixel without a separate color filter to realize a color image. That is, the light-emitting stack124of the red (R) subpixel may generate red light, the light-emitting stack124of the green (G) subpixel may generate green light, and the light-emitting stack124of the blue (B) subpixel may generate blue light. The cathode electrode126is formed to be opposite the anode electrode122in the state in which the light-emitting stack124is disposed therebetween, and is connected to a low-voltage (VSS) supply line. The encapsulation unit140reduces external moisture or oxygen from permeating into the light-emitting element120, which has low resistance to external moisture or oxygen. To this end, the encapsulation unit140includes at least one of inorganic encapsulation layer142and inorganic encapsulation layer146and at least one organic encapsulation layer144. In the present disclosure, an encapsulation unit140having a structure in which a first inorganic encapsulation layer142, an organic encapsulation layer144, and a second inorganic encapsulation layer146are sequentially stacked will be described by way of example. The first inorganic encapsulation layer142is formed on the substrate111, on which the cathode electrode126is formed. The second inorganic encapsulation layer146is formed on the substrate111, on which the organic encapsulation layer144is formed, and is formed to surround the upper surface, the lower surface, and the side surface of the organic encapsulation layer144together with the first inorganic encapsulation layer142. The first and second inorganic encapsulation layers142and146reduce or prevent external moisture or oxygen from permeating into the light-emitting stack124. Each of the first and second inorganic encapsulation layers142and146is made of an inorganic dielectric material that can be deposited at a low temperature, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), or aluminum oxide (Al2O3). Consequently, each of the first and second inorganic encapsulation layers142and146is deposited in a low-temperature atmosphere, whereby it is possible to reduce damage to the light-emitting stack124, which has low resistance to a high-temperature atmosphere, when each of the first and second inorganic encapsulation layers142and146is deposited. Each of the first and second inorganic encapsulation layers142and146is formed to have a larger thickness than the passivation film108, whereby each of the first and second inorganic encapsulation layers142and146has low resistance to external impact. For this reason, each of the first and second inorganic encapsulation layers142and146is formed so as not to be disposed in a bending area BA. The organic encapsulation layer144reduces stress between the layers due to bending of the organic light-emitting device and improves planarization. The organic encapsulation layer144is formed on the substrate111, on which the first inorganic encapsulation layer142is formed, and is made of a non-photosensitive organic dielectric material, such as a particle cover layer (PCL), an acrylic resin, an epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC), or a photosensitive organic dielectric material, such as photo acrylic. The organic encapsulation layer144is disposed in an active area AA, excluding a non-active area NA. At this time, a dam106is disposed on the substrate111or the passivation film108in order to prevent the organic encapsulation layer144from spreading to the non-active area NA. A touch-sensing line154and a touch-driving line152are disposed in the active area AA of the encapsulation unit140to intersect each other in the state in which a touch dielectric film156is disposed therebetween. Mutual capacitance Cm is formed at the intersection of the touch-sensing line154and the touch-driving line152. Consequently, the mutual capacitance Cm charges an electric charge by a touch-driving pulse supplied to the touch-driving line152and discharges the charged electric charge to the touch-sensing line154, thereby serving as a touch sensor. The touch-driving line152includes a plurality of first touch electrodes152eand first bridges152bfor electrically interconnecting together the first touch electrodes152e. The first touch electrodes152eare spaced apart from each other on the touch dielectric film156by a predetermined distance in a Y direction, which is a first direction. Each of the first touch electrodes152eis electrically connected to an adjacent first touch electrode152evia a corresponding one of the first bridges152b. The first bridges152bare disposed on the touch dielectric film156, which is disposed in the same plane as the first touch electrodes152e, so as to be electrically connected to the first touch electrodes152ewithout separate contact holes. The first bridges152bare disposed to overlap the bank128, whereby it is possible to reduce the reduction of an aperture ratio due to the first bridges152b. The touch-sensing line154includes a plurality of second touch electrodes154eand second bridges154bfor electrically interconnecting the second touch electrodes154e. The second touch electrodes154eare spaced apart from each other on the touch dielectric film156by a predetermined distance in an X direction, which is a second direction. Each of the second touch electrodes154eis electrically connected to an adjacent second touch electrode154evia a corresponding one of the second bridges154b. The second bridges154bare formed on a touch buffer layer148, and are electrically connected to the second touch electrodes154evia touch contact holes150, which are formed through the touch dielectric film156. In the same manner as the first bridges152b, the second bridges154bare disposed to overlap the bank128, whereby it is possible to reduce the reduction of an aperture ratio due to the second bridges154b. Meanwhile, the structure in which the second bridges154bare disposed on the touch buffer layer148to contact the touch buffer layer148has been described by way of example with reference toFIG.3. Alternatively, at least one of the first and second touch electrodes152eand154eor the first bridges152bmay be disposed on the touch buffer layer148to contact the touch buffer layer148, and the second bridges154bmay be disposed on the touch dielectric film156. In addition, each of the first bridges152b, the second bridges154b, the first touch electrodes152e, and the second touch electrodes154ehas been described by way of example as being formed in a plate shape, as shown inFIG.2. Alternatively, at least one of the first bridges152b, the second bridges154b, the first touch electrodes152e, or the second touch electrodes154emay be formed in a mesh shape. In the present disclosure, the structure in which the first touch electrodes152eand the second touch electrodes154eare formed in a mesh shape will be described by way of example with reference toFIGS.4and5. The mesh-shaped touch electrodes152eand154ecorrespond to the bank128disposed in a non-emission area NEA of each subpixel, and an opening area between the mesh-shaped touch electrodes152eand154ecorresponds to an emission area EA of each subpixel. Each of the touch electrodes152eand154eincludes a transparent conductive film, such as ITO or IZO, and a mesh metal film disposed above or under the transparent conductive film, the mesh metal film being formed in a mesh shape. Alternatively, each of the touch electrodes152eand154emay include only a mesh metal film. Here, the mesh metal film has a structure having at least one layer made of at least one of Ti, Al, Mo, MoTi, Cu, Ta, or ITO, which exhibits higher conductivity than the transparent conductive film, and is formed in a mesh shape. For example, the mesh metal film is formed to have a three-layer stack structure, such as Ti/Al/Ti, MoTi/Cu/MoTi, or Ti/Al/Mo. Consequently, the resistance and capacitance of each of the first and second touch electrodes152eand154eand the first and second bridges152band154bare reduced, whereby an RC time constant is reduced and thus touch sensitivity is improved. In addition, the line width of the mesh metal film of each of the first and second touch electrodes152eand154eis very small, whereby it is possible to prevent the reduction of an aperture ratio and transmittance due to the mesh metal film. Meanwhile, a display pad168, which is connected to at least one of the data line DL, the scan line SL, the low-voltage (VSS) supply line, or the high-voltage (VDD) supply line, and a touch pad160are disposed in the non-active area NA. The display pad168and the touch pad160may be disposed in the portion of the non-active area NA corresponding to at least one of a one-side portion or an other-side portion of the substrate111, or may be disposed in different portions of the non-active area NA. Meanwhile, the disposition of the touch pad160and the display pad168is not limited to the structure shown inFIG.2. The disposition of the touch pad160and the display pad168may be variously changed depending on the design of the display panel. The touch pad160and the display pad168are disposed on a dielectric film disposed under the light-emitting element120. For example, the touch pad160is disposed on the substrate111together with the display pad168. The touch pad160and the display pad168are formed to be exposed by a touch passivation film158. Consequently, the touch pad160is connected to a signal transmission film having a touch-driving circuit (not shown) mounted thereon, and the display pad168is connected to a signal transmission film having at least one of a scan-driving unit or a data-driving unit mounted thereon. Meanwhile, the touch-driving circuit may be mounted in one of the data-driving unit and a timing controller. The touch pad160includes first pad electrode162and second pad electrode164, which are electrically connected to each other. The first pad electrode162is made of the same material as the source and drain electrodes136and138, and is disposed on the substrate111. Meanwhile, the first pad electrode162may be made of the same material as the source and drain electrodes136and138, and may be disposed in the same plane as the source and drain electrodes136and138. The second pad electrode164is made of the same material as a routing line170, and is disposed on the touch dielectric film156. The second pad electrode164is connected to the first pad electrode162, which is exposed through a pad contact hole166formed through the touch dielectric film156and the touch buffer layer148. Meanwhile, the routing line170, which is connected to the second pad electrode164, extends from each of the touch electrodes152eand154e, and is formed along the side surface of the encapsulation unit140. At this time, the routing line170is disposed so as to cross at least one dam106. The routing line170is made of the same material as the touch electrodes152eand154e, and is formed on the touch dielectric film156. The routing line170overlaps a black layer184and a white layer182, which are disposed on the touch passivation film158, so as to reduce external light from being reflected by the routing line170. The touch passivation film158are formed to cover the touch sensor, which includes the touch electrodes152eand154eand the bridges152band154b, in order to reduce the touch sensor from being corroded by external moisture. In addition, the touch passivation film158is made of an organic dielectric material, such as epoxy or acrylic, and is formed in the form of a thin film or a general film, or is made of an inorganic dielectric material, such as SiNx or SiOx. As shown inFIGS.5and6, an antireflective film180including a white layer182and a black layer184is disposed on the touch passivation film158. The black layer184reduces mixing of internal light generated by the light-emitting element120and absorbs external light incident from the outside. The black layer184is formed in a mesh (matrix) shape so as to overlap the mesh-shaped first and second touch electrodes152eand154eand the bank128. That is, the black layer184is formed in the emission area EA, but is not formed in the non-emission area NEA. The black layer184may be formed on the white layer182so as to have the same line width as the white layer182in order to expose the side surface of the white layer182, as shown inFIG.5, or may be formed on the white layer182so as to have a larger line width than the white layer182in order to cover opposite side surfaces of the white layer182, as shown inFIG.6. The black layer184includes black nanoparticles, a binder, and a sensitive emulsion. The black nanoparticles include at least one of carbon-black-based black nanoparticles, metal-oxide-based black nanoparticles, or organic-based black nanoparticles. TiNxOy or CuMnFeOx is used as the metal-oxide-based black nanoparticles, and lactam black or perylene black is used as the organic-based black nanoparticles. The white layer182is formed so as to overlap the black layer184while contacting the black layer184between the black layer184and the touch sensor. The white layer182is formed on the touch passivation film158in a mesh (matrix) shape so as to overlap the mesh-shaped first and second touch electrodes152eand154eand the bank128. That is, the white layer182is formed in the emission area EA, but is not formed in the non-emission area NEA. The white layer182includes white nanoparticles, a binder, and a sensitive emulsion. The white nanoparticles include at least one of Ti-based white nanoparticles, silica-based white nanoparticles, metal-oxide-based white nanoparticles, or core-shell-based white nanoparticles. TiO2is used as the Ti-based white nanoparticles, spherical SiO2, hollow SiO2, fumed SiO2, or colloidal SiO2is used as the silica-based white nanoparticles, ZrO2, Al2O3, or CeO2is used as the metal-oxide-based white nanoparticles, and a silica-based core and a Ti-based shell are used as the core-shell-based white nanoparticles. As shown inFIG.7, the higher the content of the white nanoparticles included in the white layer182, the higher the reflectance. Consequently, the white nanoparticles may be included in the white layer182at a content of 90% to 97%. As shown inFIG.8, the white layer182changes the path of the internal light IL, generated by the light-emitting stack124and directed toward the non-emission area NEA, to the emission area EA. That is, the white layer182may reflect the internal light IL advancing to the non-emission area NEA to the emission area EA, whereby it is possible to improve the efficiency of the light that exits through the emission area EA. A process of reducing the reflection of external light using the black layer184and the white layer182according to the present disclosure will be described with reference toFIG.8. Most external light OL is absorbed and extinguished by the black layer184. However, some of the external light OL is not absorbed by the black layer184but is reflected from the black layer184as a first reflection light beam L1. In addition, some of the external light absorbed by the black layer184is transmitted through the black layer184and is reflected from the black layer184as a second reflection light beam L2. At this time, the first and second reflection light beams L1and L2have opposite phases, whereby the first and second reflection light beams L1and L2destructively interfere with each other and thus are extinguished. In the present disclosure, as described above, the external light is absorbed using the black layer184, and the external light is extinguished through destructive interference using the black layer184and the white layer182, whereby it is possible to prevent the reflection of the external light. In particular, as shown in Table 1, the reflectance of external light is 6.5% according to Comparative Example 1, in which a low-reflective metal is used, and the reflectance of external light is 5.3% according to Comparative Example 2, in which a black layer is used, whereas the reflectance of external light is less than 5.0%, i.e. 1.6%, according to Example, in which the black layer184and the white layer182are used. Consequently, i the reflectance of external light according to Example is lower than the reflectance of external light according to each of Comparative Examples 1 and 2. TABLE 1ComparativeComparativeExample 1Example 2ExampleReflectance6.5%5.3%1.6% In the present disclosure, as described above, it is possible to reduce external light from being incident on the touch sensor and the routing line170using the black layer184and the white layer182, whereby it is possible to reduce the reflectance of the external light. In the present disclosure, therefore, it is possible to reduce a reduction in external visibility, and therefore it is possible to obviate a polarizing plate, which is expensive. Also, in the present disclosure, because the expensive polarizing plate is obviated, it is possible to improve transmittance and luminance. Consequently, the power consumption thereof is reduced, and the lifespan thereof is increased. Meanwhile, the substrate111, on which the black layer184and the white layer182according to the present disclosure are formed, is laminated with a cover substrate101via an adhesive film186, as shown inFIGS.9Aand9B. The adhesive film186is formed between the black layer184and the cover substrate101in the form of an optical clear adhesive (OCA) or an optical clear resin (OCR). The adhesive film186and the black layer184may contact each other, as shown inFIG.9A, or an optical film188may be disposed between the adhesive film186and the black layer184, as shown inFIG.9B. A semi-transmissive film or an OLED transmittance controllable film (OTF) is used as the optical film188. A display device comprising a display panel with touch sensors shown inFIG.1andFIG.2is further disclosed according to another embodiment of the present invention. And the same description for the display panel with touch sensors in the display device will be omitted here. As is apparent from the above description, in the present invention, it is possible to reduce external light from being incident on the touch sensor and the cathode electrode using the antireflective film (for example, the black layer and the white layer), whereby it is possible to reduce the reflectance of external light. In the present disclosure, therefore, it is possible to reduce a reduction in external visibility without using a separate optical film (e.g. a polarizing plate). Also, in the present disclosure, it is possible to improve the transmittance, luminance, and lifespan of the display panel and the display device. Consequently, it is possible to reduce the thickness and the power consumption of the display panel and the display device. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers such modifications and variations to this invention provided they come within the scope of the appended claims and their equivalents. | 26,828 |
11943968 | DETAILED DESCRIPTION The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of various embodiments of the present disclosure as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the various embodiments described herein can be made without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness. When an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, this indicates that the element may further include another component instead of excluding another component unless there is different disclosure. FIG.1illustrates an embodiment of a display device1000, andFIG.2is a cross-sectional view taken along lines I-I′ and II-II′ inFIG.1. Referring toFIG.1, the display device1000includes a display area DA and a non-display area NA distinguished from the display area DA when viewed in a plan view. The display area DA displays an image, while the non-display area NA does not display an image. The non-display area NA may be adjacent to one side of the display area DA. In another embodiment, the non-display area NA may be adjacent to at least one of the other sides of the display area DA and/or more than one side of the display area. The non-display area NA includes a pad area PDA which may be connected to a flexible printed circuit board. The display device1000may receive signals to drive the display device1000through the pad area PDA. A haze area HA is at an edge of the display area DA. In the present exemplary embodiment, the haze area HA is at one or more sides different from the side adjacent to the non display area NA. When the non-display area NA is adjacent to another side, the position of the haze area HA may be changed accordingly. Referring toFIG.2, the display device1000includes a display panel100, a first film200, and a second film300stacked along a first direction DR1. The display panel100includes a display element emitting light including display information. The display element may be, but is not limited to, an organic light emitting element, a liquid crystal display element, a plasma display element, an electrophoretic display element, a microelectromechanical system display element, or an electrowetting display element. An organic light emitting element will be described below as a representative example. The display panel100includes a second surface102opposite to a first surface101. The display panel100outputs light emitted by the display element through the second surface102. The first film200is on the first surface101of the display panel100. The second film300is on the second surface102of the display panel100. The display device1000may further include a first pressure sensitive adhesive400between the first film200and the display panel100. The first film200may be, but is not limited to, a support film to support and protect the display panel100. The first film200may include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), polycarbonate oxide (PCO), or modified polythenylene oxide (MPPO). In the present exemplary embodiment, the first film200includes polyethylene terephthalate (PET). The second film300may include a polarizing film to block external light incident thereto. The polarizing film may include a linear polarizing layer and a λ/4 retardation layer. The linear polarizing layer may be on, for example, the λ/4 retardation layer. External light sequentially passing through the linear polarizing layer and the λ/4 retardation layer is reflected by a lower portion (e.g., a cathode of the display panel100) of the polarizing film. Then, the external light is suppressed since the external light does not pass through the linear polarizing layer after passing through the λ/4 retardation layer. The first pressure sensitive adhesive400adheres the first film200to the first surface101. The first pressure sensitive adhesive400includes, for example, an urethane-based material, an acrylic-based material, or a silicon-based material. The display panel100further includes a side surface103connecting the first surface101and the second surface102. A side surface303of the second film300may protrude outwardly along a second direction DR2than a side surface203of the first film200and the side surface103of the display panel100. In addition, the side surface103of the display panel100may protrude outwardly along the second direction DR2more than the side surface203of the first film200. Accordingly, each of the side surface203of the first film200, the side surface103of the display panel100, and the side surface303of the second film300may be inclined at a predetermined angle and, for example, aligned to form a continuous slanted side surface. The angle between the side surface303of the second film300and the second surface102may be referred to as a first inclination angle θ1. The first inclination angle θ1may be greater than a predetermined angle, e.g., about 90 degrees. An angle between the side surface103of the display panel100and the second surface102may be referred to as a second inclination angle θ1. An angle between an extension line of the side surface203of the first film200and the second surface102may be referred to as a third inclination angle θ3. In one embodiment, the second and third inclination angles θ1and θ3may be less than a predetermined angle (e.g., less than about 90 degrees). The second and third inclination angles θ1and θ3may be equal or different. A first burr BU1is on a lower surface201of the first film200and adjacent to the side surface203of the first film200. A second burr BU2is on an upper surface301of the second film300and adjacent to the side surface303of the second film300. In one embodiment, the first and second burrs BU1and BU2may have different sizes, e.g., the second burr BU2may be smaller than the first burr BU1. A yellow area YA may be in the lower surface201of the first film200and the upper surface301of the second film300and adjacent to the first and second burrs BU1and BU2.FIG.2shows only the yellow area YA in the upper surface301of the second film300for illustrative purposes. The haze area HA may correspond to an area which includes the area in which the second burr BU2is formed and the yellow area YA. As an example, the haze area HA has a width of from about 1 micrometers to about 100 micrometers. When a direction vertical to the first and second surfaces101and102of the display panel100and toward the second surface102from the first surface101is a first direction DR1, a direction vertical to the first direction DR1may be a second direction DR2. The width of the haze area HA may correspond to a width in the second direction DR2of the haze area HA when the display panel100is cut along a direction vertical to two parallel sides. FIG.3is a cross-sectional view of another embodiment of a display device1001which further includes a second pressure sensitive adhesive500. The second pressure sensitive adhesive500is between the second surface102of the display panel100and the second film300to adhere the second film300to the second surface102. The second pressure sensitive adhesive500includes, for example, an urethane-based material, an acryl-based material, or a silicon-based material. The side surface203of the first film200, the side surface103of the display panel100, and the side surface303of the second film300may correspond to a cross-section ST of the display device100. The cross-section ST may be inclined with respect to a normal line direction, e.g., the first direction DR1, of the second surface102, which sequentially penetrates through the first film200, the display panel100, and the second film300. The cross-section ST is inclined outwardly away from a center of the display device1001with respect to the first direction DR1.FIG.3shows only a left cross-section ST of the display device1001, but a right cross-section may be symmetrical with the left cross-section ST relative to the first direction DR1. For example, when the inclined direction of the left cross-section ST relative to the first direction DR1is a third direction DR3, the right cross-section is inclined in a direction symmetrical with the third direction DR3relative to the first direction DR1. FIG.4is a cross-sectional view of another embodiment of a display device1002which includes a first cross-section ST1and a second cross-section ST2having a slope different from a slope of the first-cross-section ST1. The first cross-section ST1corresponds to the side surface203of the first film200and the side surface103of the display panel100L. The second cross-section ST2corresponds to the side surface303of the second film300. For example, the first and second cross-sections ST1and ST2are inclined outwardly to be far away from the center of the display device1002with respect to the first direction DR1. The first cross-section ST1inclined with respect to the first direction DR1may be referred to as a fourth direction DR4. The second cross-section ST2inclined with respect to the first direction DR1may be referred to as a fifth direction DR5. In the present exemplary embodiment, the angle between the first direction DR1and the fourth direction DR4may referred to as a fourth inclination angle θ4. The angle between the first direction DR1and the fifth direction DR5may be referred to as a fifth inclination angle θ5. The fourth and fifth angles θ4and θ5may be different from each other. For example, the fourth inclination angle θ4may be greater than the fifth inclination angle θ5. FIG.4shows only left first and second cross-sections ST1and ST2of the display device1002, but right first and second cross-sections may be symmetrical with the left first and second cross-sections ST1and ST2relative to the first direction DR1. For example, the right first and second cross-sections are inclined to directions respectively symmetrical with the fourth and fifth directions DR4and DR5with respect to the first direction DR1. FIG.5is a cross-sectional view of another embodiment of a display device1003which further includes a protective film600protecting the second film300, a lower support film700disposed under the first film200, and a third pressure sensitive adhesive800disposed between the lower support film700and the first film200. The protective film600is on the second film200to protect the second film300. The protective film600includes, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), polycarbonate oxide (PCO), or modified polythenylene oxide (MPPO). The lower support film700is under the first film200to protect and support internal components of the display device103at an outermost position of the display device103. The lower support film700includes, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), polycarbonate oxide (PCO), or modified polythenylene oxide (MPPO). The third pressure sensitive adhesive800adheres the lower support film700to the first film200. A cross-section ST3of the display device1003corresponds to a side surface of the lower support film700, a side surface203of the first film200, a side surface103of the display panel100, a side surface303of the second film, and a side surface603of the protective film600. The cross-section ST3is inclined with respect to a normal line direction, e.g., the first direction DR1, of the second surface102, which sequentially penetrates through the first film200, the display panel100, and the second film300. The cross-section ST3is inclined outwardly away from a center of the display device1003with respect to the first direction DR1. For example, the cross-section ST3is inclined in the third direction DR3outwardly inclined with respect to the first direction DR1. Accordingly, the side surface303of the second film300and the side surface603of the protective film600protrude outwardly more than the side surface203of the first film200with respect to the side surface103of the display panel100. In addition, the side surface103of the display panel100protrudes outwardly more than the side surface203of the first film200and a side surface703of the lower support film700. A first burr BU1may be on a lower surface701of the lower support film700and adjacent to the side surface703of the lower support film700. A second burr BU2may be on an upper surface601of the protective film600and adjacent to the side surface603of the protective film600. The first and second burrs BU1and BU2may have different sizes, e.g., the second burr BU2may be smaller than the first burr BU1. FIG.6is a cross-sectional view of an other embodiment of a display device1004which includes a first cross-section ST4and a second cross-section ST5having a slope different from a slope of the first cross-section ST4. The first cross-section ST4corresponds to the side surface703of the lower support film700, the side surface203of the first film200, and the side surface103of the display panel100. The second cross-section ST5corresponds to the side surface303of the second film300and the side surface603of the protective film600. The first and second cross-sections ST4and ST5are inclined outwardly to be far away from a center of the display device1004with respect to the first direction DR1. A direction in which the first cross-section ST4is inclined relative to the first direction DR1may be referred to as a fourth direction DR4. A direction in which the second cross-section ST5is inclined with respect to the first direction DR1may be referred to as a fifth direction DR5. The angle between the first direction DR1and the fourth direction DR4is a fourth inclination angle θ4. The angle between the first direction DR1and the fifth direction DR5is a fifth inclination angle θ5. The fourth and fifth inclination angles θ4and θ5may be different, e.g., the fourth inclination angles θ4may be greater than the fifth inclination angle θ5. FIG.7is a cross-sectional view of another embodiment of a display device1005which may include a first cross-section ST6and a second cross-section ST7having a curvature different from a curvature of the first cross-section ST6. The first and second cross-sections ST6and ST7may be connected to each other. The first cross-section ST6may include the side surface703of the lower support film700, the side surface204of the first film200, and the side surface103of the display panel100. The second cross-section ST7may include the side surface303of the second film300and the side surface603of the protective film600. Each of the first and second cross-sections ST6and ST7may have a half-parabolic shape. The curvature of the first cross-section ST6may be different from the curvature of the second cross-section ST7in another embodiment. In one embodiment, the first cross-section ST6may have a tangent slope decreasing as the distance from the display panel100decreases from the lower support film700. The second cross-section ST7may have a tangent slope decreasing as a distance from the protective film600decreases from the second film300. The side surface703of the lower support film700, the side surface204of the first film200, and the side surface103of the display panel100, which correspond to the first cross-section ST6, may have different tangent slopes from each other. For example, a tangent slope of the side surface703of the lower support film700may be greater than a tangent slope of the side surface204of the first film200, and the side surface103of the display panel100, and a tangent slope of the side surface203of the first film200may be greater than a tangent slope of the side surface103of the display panel100. The side surface303of the second film300and the side surface603of the protective film600, which corresponds to the second cross-section ST7, may have different tangent slopes from each other. For example, the tangent slope of the side surface303of the second film300may be greater than the tangent slope of the side surface603of the protective film600. The variation in the tangent slope of the first cross-section ST6may be greater than the variation in the tangent slope of the second cross-section ST7, e.g., the curvature of the first cross-section ST6may be greater than the curvature of the second cross-section ST7. FIG.8is a cross-sectional view of another embodiment of a display device1006which may include at least three cross-sections having different slopes from each other. Referring toFIG.8, the display device1006may include first, second, third, and fourth cross-sections ST8, ST9, ST10, and ST11. The first cross-section ST8includes the side surface703of the lower support film700. The second cross-section ST9includes the side surface203of the first film200and the side surface103of the display panel100. The first cross-section ST8further includes a side surface803of the third pressure sensitive adhesive800. The second cross-section ST9further includes a side surface403of the first pressure sensitive adhesive400. The third cross-section ST10includes a side surface503of the second pressure sensitive adhesive500. The fourth cross-section ST11includes the side surface303of second film300and the side surface603of protective film600. The angle between an extension line of the first cross-section ST8and the second surface102may be a sixth inclination angle θ6. The angle between the second cross-section ST9and the second surface102may be a seventh inclination angle θ7. The sixth and seventh inclination angles θ6and θ7may be less than a predetermined angle, e.g., about 90 degrees. The sixth inclination angle θ6may be less than the seventh inclination angle θ7. The angle between the third cross-section ST10and the second surface102may be an eighth inclination angle θ8. The angle between an extension line of the fourth cross-section ST11and the second surface102may be a ninth inclination angle θ9. The eighth and ninth inclination angles θ8and θ9may be less than a predetermined angle, e.g., about 90 degrees. The eighth inclination angle θ8may be less than the ninth inclination angle θ9. In another example, each of the first, second, third, and fourth cross-sections ST8, ST9, ST10, and ST11may include portions of side surfaces of two layers adjacent to each other. FIGS.2to8illustrate cross-sectional structures of various embodiments of display devices. The cross-sectional structure may be changed in various ways as long as the side surface303of the second film300protrudes outwardly more than the side surface303of the first film200and the side surface303of the second film300is inclined at an angle greater than a predetermined angle (e.g., about 90 degrees) with respect to the second surface102. FIG.9is a cross-sectional view of an embodiment of a display panel100inFIGS.1to8. Referring toFIG.9, the display panel100includes a base substrate110, a driving layer120, an organic light emitting element layer130, and a sealing layer140. The base substrate110provides the first surface101of the display panel100, may be a flexible substrate, and may include a plastic material having superior thermal resistance and durability, e.g., polyethylene etherphthalate, polyethylene naphthalate, polycarbonate, polyarylate, poly etherimide, polyether sulfone, polyimide, etc. Hereinafter, the base substrate110includes polyimide as an illustrative case. The driving layer120includes various signal lines, e.g., a scan line, a data line, a power source line, and a light emitting line. The driving layer120includes a plurality of transistors and a one or more capacitors. The transistors include a switching transistor and a driving transistor which are arranged in every pixel. FIG.9illustrates a driving transistor Qd of the driving layer120as a representative example. The driving transistor Qd includes an active layer211, a gate electrode213, a source electrode215, and a drain electrode217. The active layer211is on the base substrate110. The driving layer120further includes a first insulating layer221between the active layer211and the gate electrode213. The first insulating layer221insulates the active layer211and the gate electrode213. The source electrode215and the drain electrode217are on the gate electrode213. The driving layer120further includes a second insulating layer223between the gate electrode213and the source electrode215and between the gate electrode213and the drain electrode217. The source electrode215and the drain electrode217are connected to the active layer211respectively through contact holes CH1and CH2through the first and second insulating layers221and223. The driving layer120may further include a protective layer230disposed on the source electrode215and the drain electrode217. The structure of the driving transistor Qd may be different fromFIG.9in another embodiment. Also, the positions of the active layer211, the gate electrode213, the source electrode215, and the drain electrode217may be different in other embodiments, e.g., the gate electrode213may be on the active layer211inFIG.9but the gate electrode213may be under the active layer211. The switching transistor may have substantially the same structure as the driving transistor Qd. In an other embodiment, the switching and driving transistors may have different structures. For instance, an active layer of the switching transistor may be on a layer different from a layer on which the active layer211of the driving transistor Qd is disposed. The organic light emitting element layer130includes an organic light emitting diode LD. In the present exemplary embodiment, the organic light emitting diode LD may be a front-surface light-emitting type to emit a light to an upper direction DR3. The organic light emitting diode LD includes a first electrode AE, an organic layer OL, and a second electrode CE. The first electrode AE is on the protective layer230. The first electrode AE is connected to the drain electrode217through a contact hole CH3through the protective layer230. The first electrode AE is a pixel electrode or a positive electrode. The first electrode AE may be a transflective electrode or a reflective electrode. When the first electrode AE is a transflective electrode or a reflective electrode, the first electrode AE may include, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture of metal. The first electrode AE may have a single-layer structure of a metal oxide or a metal or a multi-layer structure. For example, the first electrode AE may have a single-layer structure of ITO, Ag, or a mixture of metal (e.g., a mixture of Ag and Mg), a double-layer structure of ITO/Mg or ITO/MgF, or a triple-layer structure of ITO/Ag/ITO, but it should not be limited thereto or thereby. The organic layer OL includes an organic light emitting layer which includes a low molecular weight or high molecular weight organic material. The organic light emitting layer emits light. The organic layer OL selectively includes a hole transport layer, a hole injection layer, an electron transport layer, and/or an electron injection layer. Holes and electrons are injected into the organic light emitting layer from the first and second electrodes AE and CE, respectively. The electrons are recombined with the holes in the organic light emitting layer to generate excitons, and the organic light emitting layer emits light when the excitons transition from an excited state to a ground state. The second electrode CE is on the organic light OL. The second electrode CE is a common electrode or a negative electrode. The second electrode may be, for example, a transmissive electrode or a transflective electrode. When the second electrode E2is a transmissive electrode or a transflective electrode, the second electrode E2may include, for example, Li, Liq, Ca, LiF/Ca, LiF/Al, Al, Mg, BaF, Ba, Ag, a compound thereof, or a mixture thereof, e.g., a mixture of Ag and Mg. The second electrode CE may include an auxiliary electrode, which may include a layer formed by depositing the material to face the organic light emitting layer and a transparent metal oxide material, e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc., Mo, Ti, or Ag. The organic light emitting element layer130further includes a pixel definition layer PDL on the protective layer230. The pixel definition layer PDL overlaps a boundary of the pixel area PA, for example, from a plan view perspective. The sealing layer is on the organic light emitting element layer130. The sealing layer140provides the upper surface102of the display panel100. The sealing layer143blocks the organic light emitting element layer130from external moisture and air. The sealing layer140includes a sealing substrate141and a sealing member. The sealing member is disposed along an edge of the sealing substrate141and seals the organic light emitting diode LD in cooperation with the sealing substrate141. An inner space143defined by the sealing substrate141and the sealing member is maintained in a vacuum state, but this arrangement may be different in another embodiment. The inner space143may be filled with nitrogen (N2) or a filling member including an insulating material. Different from the embodiment inFIG.9, the sealing layer140may have a structure in which an organic layer and an inorganic layer are stacked several times. The sealing layer140may provide the second surface102of the display panel100. FIG.10illustrates an embodiment of a mother substrate2000including a display unit.FIGS.11A to11Dare cross-sectional views corresponding to an embodiment of a method for manufacturing a display device. Referring toFIGS.10and11A, the mother substrate2000is formed to include a plurality of display units DU. The mother substrate2000further includes a dummy area DM between the display units DU or surrounding each display unit DU. Each of the display units DU includes display elements formed therein to display an image based on a signal applied thereto. The display elements may include various types of display elements. The display units DU may include, for example, the organic light emitting display element inFIG.9. The display elements are not in the dummy area DM. In one embodiment, the display units1000may be formed to share one substrate. The dummy area DM may be removed, for example, at the last stage in the manufacturing process. FIG.10shows six display units DU in one mother substrate, but the mother substrate may include a different number of display units DU in another embodiment depending, for example, on the size of the display unit DU. When the display units DU are to be flexible, the mother substrate2000may be formed using a flexible material. FIG.11Ais a cross-sectional view of an embodiment taken along a line III-III′ inFIG.10. Referring toFIG.11A, three display units DU are arranged in a second direction DR2spaced apart from each other. The dummy area DM is between two adjacent display units DU. The display units DU are cut along a dotted line to form the display panel100(e.g., refer toFIGS.2to8), and the dummy area DM is removed after the cutting process. Each of the display units DU emits light including display information. The mother substrate2000includes first and second surfaces2001and2002facing each other. The second surface2002corresponds to a surface from which light exits. Referring toFIG.11B, before the mother substrate2000is cut, first and second mother films2100and2200may be respectively attached to the first and second surfaces2001and2002of the mother substrate2000. The first mother film2100is adhered to the first surface2001of the mother substrate2000by a first mother pressure sensitive adhesive2300. The second mother film2200is adhered to the second surface2002of the mother substrate2000by a second mother pressure sensitive adhesive2400. Accordingly, a display mother substrate2010is completed or ready for additional processes. The display mother substrate2010may further include a mother protective film and a mother support film in addition to the first and second mother films2100and2200. The first mother film2100may include, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), polycarbonate oxide (PCO), or modified polythenylene oxide (MPPO). The second mother film2200includes a polarizing film to block external light incident thereto. The polarizing film includes a linear polarizing layer and a λ/4 retardation layer. The linear polarizing layer may be on the λ/4 retardation layer. The external light sequentially passes through the linear polarizing layer and the λ/4 retardation layer and is reflected by a lower portion (e.g., a cathode of the display panel100) of the polarizing film. Then, the external light is suppressed since the external light does not pass through the linear polarizing layer after passing through the λ/4 retardation layer. Then, as shown inFIG.11C, a laser beam LZ is irradiated to the display mother substrate2010from the first mother film2100. The laser beam LZ cuts the display mother substrate2010. InFIGS.11A to11C, an area cut by the laser beam LZ is indicated by a dotted line. When the laser beam LZ is irradiated on the dotted line, the display mother substrate2010may be cut into the display units DU. The laser beam LZ may be, for example, at least one of a UV laser beam or a CO2laser beam. In addition, the laser beam LZ may be irradiated in a direction from the first surface2001to the second surface2002, e.g., the first direction DR1, at the side of the first mother film2100of the mother substrate2000. Accordingly, as shown inFIG.11D, the display mother substrate2010is cut into the display units DU to form a plurality of display devices1000. Each of the display devices1000includes the cross-section ST defining the side surface203of the first film200, the side surface103of the display panel100, and the side surface303of the second film300. The cross-section ST is inclined and spaced apart from the center of the display device1000with respect to a normal line direction of the second surface102, e.g., the first direction DR1, which sequentially passes through the first film200, the display panel100, and the second film300. When the display mother substrate2010is cut, the first and second mother films2100and2200and the first and second mother pressure sensitive adhesives2300and2400are cut into display units DU. Due to the irradiating process of the laser beam, the first burr BU1is formed on the lower surface201of the first film200adjacent to the side surface203of the first film200. The second burr BU2is formed on the upper surface301of the second film300adjacent to the side surface303of the second film300. The sizes of the first and second burrs BU1and BU2are changed based on the intensity of laser beam LZ while the irradiating process of the laser beam LZ is performed. The haze area HA is in the upper surface301of the second film300adjacent to the second burr BU2. The haze area HA has a width depending on the intensity of the laser beam LZ while the irradiating process of the laser beam LZ is performed. When the display mother substrate2010is cut, the distance between the dummy area DM and the display unit DU increases as the display mother substrate2010is cut. Since the laser beam LZ is irradiated to the first direction DR1from the first surface2001, the distance between the dummy area DM and the display unit DU is gradually reduced toward the first direction DR1. As described above, when the display mother substrate2010is cut by irradiating the laser beam from the first mother film2100side, the width of the haze area HA in the upper surface301of the second film300is reduced. For example, when the laser beam is irradiated from the first mother film2100side, the width of the haze area HA is reduced to a greater extent than when the laser beam is irradiated from the second mother film2200side. FIGS.12A to12Dare cross-sectional views corresponding to an embodiment of a cutting method when a laser beam LZ1with an intensity of about 5 W is irradiated six times and a width of haze area. Referring toFIGS.12A to12D, the display mother substrate2010is not completely cut when the laser beam LZ1with the intensity of about 5 W is irradiated once, twice, or three times. The display mother substrate2010is completely cut after irradiating the laser beam LZ1six times. When the display mother substrate2010is completely cut by irradiating the laser beam LZ1six times, a width of a first haze area HA1in the upper surface301of the second film300is about 27 micrometers. The process of irradiating the laser beam several times may be referred to as a multi-pass process. FIGS.13A to13Care cross-sectional views corresponding to an embodiment of a cutting process when a laser beam LZ2with an intensity of about 10 W is irradiated three times and a width of haze area. Referring toFIGS.13A to13C, the display mother substrate2010is not completely cut when the laser beam LZ2with the intensity of about 10 W is irradiated once or twice. The display mother substrate2010is completely cut after irradiating the laser beam LZ2three times. When the display mother substrate2010is completely cut by irradiating the laser beam LZ2three times, the width of a second haze area HA2in the upper surface301of the second film300is about 45 micrometers. FIGS.14A and14Bare cross-sectional views corresponding to an embodiment of a cutting process when a laser beam LZ3with an intensity of about 20 W is irradiated two times and a width of haze area. Referring toFIGS.14A and14B, the display mother substrate2010is not completely cut when the laser beam LZ3with the intensity of about 20 W is irradiated once. The display mother substrate2010is completely cut after irradiating the laser beam LZ3twice. When the display mother substrate2010is completely cut by irradiating the laser beam LZ3twice, the width of a third haze area HA3in the upper surface301of the second film300is about 63 micrometers. FIGS.15A and15Bare cross-sectional views corresponding to an embodiment of a cutting process when a laser beam LZ4with an intensity of about 30 W is irradiated two times and a width of haze area. Referring toFIGS.15A and15B, the display mother substrate2010is not completely cut when the laser beam LZ4with the intensity of about 30 W is irradiated once. The display mother substrate2010is completely cut after irradiating the laser beam LZ4twice. When the display mother substrate2010is completely cut by irradiating the laser beam LZ4twice, the width of a fourth haze area HA4in the upper surface301of the second film300is about 68 micrometers. As illustrated inFIGS.12A to15B, the number of irradiation times of the laser beam increases when the intensity of the laser beam reduces. However, the width of the first haze area HA1in the upper surface301of the second film300after the display mother substrate2010is cut is less than the second, third, and fourth haze areas HA2, HA3, and HA4. The size of the first and second burrs BU1and BU2reduces as the intensity of the laser beam reduces. The increased distances d1, d2, d3, and d4between the dummy area DM and the display unit DU reduces as the intensity of the laser beam reduces. FIGS.16A and16Bare cross-sectional views of an embodiment of a cross-sectional structure obtained by irradiating the laser beam two times. In this embodiment, the process of cutting the display mother substrate2010by irradiating the laser beam inFIG.11Cmay include irradiating the laser beam with a first intensity and irradiating the laser beam with a second intensity as illustrated inFIGS.16A and16B. The second intensity may be less than the first intensity, e.g., the second intensity may be about 5 W when the first intensity is about 30 W. In one embodiment, irradiating the laser beam with the first intensity may be performed in a first multi-pass process. Irradiating of the laser beam with the second intensity may be performed in a second multi-pass process. The second multi-pass process may be greater than the first multi-pass process. For instance, when the first multi-pass process involves irradiating the laser beam twice, the second multi-pass process may involve irradiating the laser beam five times. As illustrated inFIG.16A, the first mother film2100and the mother substrate2000may be cut when the laser beam is irradiated at the first intensity. Accordingly, the first cross-section ST6may be formed to have a half-parabolic shape in the display device. Then, when the laser beam is irradiated to the second mother film2200at the second intensity to cut the second mother film2200, the display mother substrate2010is completely cut. Thus, the second cross-section ST7may be formed to have a half-parabolic shape in the display device connected to the first cross-section ST6. Due to the difference in intensity of the laser beam, the curvature of the first cross-section ST6may be different from the curvature of the second cross-section ST7. FIGS.17A and17Bare cross-sectional views corresponding to another embodiment of a cross-sectional structure obtained by irradiating the laser beam two times. In this embodiment, cutting the display mother substrate2010by irradiating the laser beam inFIG.11Cmay include irradiating the laser beam at the first intensity and irradiating the laser beam at the second intensity as inFIGS.17A and17B. The second intensity may be less than the first intensity, e.g., the second intensity may be about 10 W when the first intensity is about 30 W. Irradiating the laser beam with the first intensity may be performed in a first multi-pass process. Irradiating the laser beam with the second intensity may be performed in a second multi-pass process. The second multi-pass process may be greater than the first multi-pass process. For instance, when the first multi-pass process involves irradiating the laser beam twice, the second multi-pass process may involve irradiating the laser beam four times. As shown inFIG.17A, the first mother film2100and the mother substrate2000may be cut when the laser beam is irradiated at the first intensity. Accordingly, first and second cross-sections ST8and ST9may be formed in the display device. Then, when the laser beam is irradiated to the second mother film2200at the second intensity to cut the second mother film2200, the display mother substrate2010is completely cut. Thus, the third and fourth cross-sections ST10and ST11may be formed in the display device. Due to the difference in intensity of the laser beam, the slope of the first cross-section ST8may be more gentle than the slope of the third cross-section ST10. Also, the slope of the second cross-section ST9may be more gentle than the slope of the fourth cross-section ST11. In accordance with one or more of the aforementioned embodiments, when the display mother substrate is cut by a laser beam irradiated from a first mother film side, the width of a haze area in an upper surface of the second film is reduced. For example, the width of the haze area in the image display surface of the display device may be greatly reduced compared to the case where the laser beam irradiated from the second mother film side. As a result, the bezel width of the display device may be reduced. In accordance with at least one embodiment, a display device is formed to have a haze area with a reduced width. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. The embodiments (or portions thereof) may be combined to form additional embodiments. In some instances, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, various changes in form and details may be made without departing from the spirit and scope of the embodiments set forth in the claims. | 41,422 |
11943969 | DETAILED DESCRIPTION Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As the present description allows for various suitable changes and numerous embodiments, certain embodiments will be illustrated in the drawings and described in the written description. Effects and features of the disclosure, and methods of achieving them will be clarified with reference to embodiments described below in more detail with reference to the drawings. However, the disclosure is not limited to the following embodiments and may be embodied in various suitable forms. One or more embodiments of the disclosure will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence with each other are rendered the same reference numeral regardless of the figure number, and redundant explanations may not be repeated. It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. The singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “including,” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure”. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “bottom,” “top,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “over” the other elements or features. Thus, the term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. It will be further understood that, when a layer, region, or component is referred to as being “on” another layer, region, or component, it can be directly or indirectly on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of elements in the drawings may be exaggerated or reduced for convenience of explanation. For example, because sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the disclosure is not limited thereto. When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. In the following embodiments, it will be understood that when a layer, region, or component is referred to as being “connected to” or “coupled to” another layer, region, or component, it may be directly or indirectly connected or coupled to the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. For example, when layers, areas, components, or the like are referred to as being “electrically connected,” the layers, areas, or components may be directly electrically connected, or the layers, areas, or components may be indirectly electrically connected and an intervening portion may be present. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. A display device displays an image and may include a game console, a multimedia device, or a portable mobile device such as an ultra-small personal computer (PC). A display device may include a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conduction electron-emitter display, a quantum dot display, a plasma display, a cathode ray display, and/or the like. Hereinafter, an organic light-emitting display device is described as an example of a display device according to an embodiment, but the various types of display devices described above may be used in embodiments. FIG.1is a schematic perspective view of a display device1according to an embodiment.FIG.2is a schematic cross-sectional view of the display device1according to an embodiment. Referring toFIGS.1and2, the display device1may include a display area DA, a non-display area NDA, and an opening area OA. The display area DA may emit light. A plurality of pixels may be arranged in the display area DA, and the display device1may provide a certain image by using light emitted from the pixels. The non-display area NDA does not emit light. The non-display area NDA may be arranged adjacent to the display area DA. The opening area OA may be at least partially surrounded by the display area DA. According to an embodiment, the opening area OA may be completely surrounded by the display area DA. The display device1may include a display panel10, a cover window20, a display driver30, a display circuit board40, a touch sensor driver50, and a component60. The display panel10may display an image. The display panel10may include pixels arranged in the display area DA. The pixels may include a display element and a pixel circuit connected thereto. The display element may include an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot light-emitting diode. Hereinafter, a detailed description will be given focusing on a case in which the display element includes an organic light-emitting diode. The display panel10may include a substrate100and multiple layers over the substrate100. In this case, the display area DA, the non-display area NDA, and the opening area OA may be defined in the substrate100and/or the multiple layers. For example, the substrate100may include the display area DA, the non-display area NDA, and the opening area OA. Hereinafter, a detailed description will be given focusing on a case in which the display area DA, the non-display area NDA, and the opening area OA are defined in the substrate100. The non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. The first non-display area NDA1may surround the opening area OA. The second non-display area NDA2may at least partially surround the display area DA. According to an embodiment, the first non-display area NDA1may completely surround the opening area OA. The display area DA may completely surround the first non-display area NDA1. The second non-display area NDA2may completely surround the display area DA. The third non-display area NDA3may be connected to the second non-display area NDA2and the fourth non-display area NDA4. The third non-display area NDA3may be a bending area, and the substrate100may be bent in the third non-display area NDA3. In this case, at least some portions of the lower surface of the substrate100may face each other. The fourth non-display area NDA4may be a pad area in which the display driver30and/or the display circuit board40are arranged. According to an embodiment, the display panel10may include the substrate100, a display layer DSL, an encapsulation layer ENL, a touch sensor layer TSL, and an optical functional layer OFL. The substrate100may include glass or a polymer resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. According to an embodiment, the substrate100may have a multiple layer structure including a base layer including the above-described polymer resin and a barrier layer. The substrate100including the polymer resin may be flexible, rollable, or bendable. The display layer DSL may be on the substrate100. The display layer DSL may include a pixel circuit layer including a plurality of pixel circuits and a display element layer including a plurality of display elements. In this case, the pixel circuits may be connected to the display elements, respectively. The pixel circuit may include a thin-film transistor and a storage capacitor. Also, the display layer DSL may further include insulating layers. The encapsulation layer ENL may be on the display layer DSL. The encapsulation layer ENL may be on the display element and may cover the display element. According to an embodiment, the encapsulation layer ENL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The at least one inorganic encapsulation layer may include at least one inorganic material selected from aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), zinc oxide (ZnO), silicon oxide (SiO2), silicon nitride (SiNx), or silicon oxynitride (SiON). The at least one organic encapsulation layer may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, polyimide, polyethylene, and/or the like. According to an embodiment, the at least one organic encapsulation layer may include acrylate. The touch sensor layer TSL may be on the encapsulation layer ENL. The touch sensor layer TSL may sense coordinate information according to an external input, for example, a touch event. The touch sensor layer TSL may include a sensor electrode and touch lines connected to the sensor electrode. The touch sensor layer TSL may sense an external input by using a self-capacitance method or a mutual-capacitance method. The touch sensor layer TSL may be formed on the encapsulation layer ENL. Alternatively, the touch sensor layer TSL may be separately formed on a touch substrate and then bonded to the encapsulation layer ENL through an adhesive layer such as an optically clear adhesive. According to an embodiment, the touch sensor layer TSL may be formed directly on the encapsulation layer ENL. In this case, the adhesive layer may not be between the touch sensor layer TSL and the encapsulation layer ENL. The optical functional layer OFL may be on the touch sensor layer TSL. The optical functional layer OFL may reduce reflectance of light (external light) incident on the display device1(e.g., the optical functional layer OFL of the display device1) from the outside, and/or may improve color purity of light emitted from the display device1. According to an embodiment, the optical functional layer OFL may include a retarder and/or a polarizer. The retarder may be a film type retarder or a liquid crystal coating type retarder and may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may also be a film type polarizer or a liquid crystal coating type polarizer. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a certain array. Each of the retarder and the polarizer may further include a protective film. According to another embodiment, the optical functional layer OFL may include a black matrix and color filters. The color filters may be arranged considering the color of light emitted from each of the pixels of the display device1. Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, each of the color filters may further include, in addition to the pigment or dye, quantum dots. Alternatively, some color filters may not include the pigment or dye and may include scattering particles such as titanium oxide. According to another embodiment, the optical functional layer OFL may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer, which are arranged on different layers from each other. First reflected light and second reflected light, which are respectively reflected from the first reflective layer and the second reflective layer, may destructively interfere with each other. Thus, reflectance of external light may be reduced. The display panel10may include an opening10H. According to an embodiment, the substrate100may include the opening area OA, and each of the display layer DSL, the encapsulation layer ENL, the touch sensor layer TSL, and the optical functional layer OFL may include first to fourth openings (i.e., a first opening, a second opening, a third opening, and a fourth opening) respectively. The opening area OA and the first to fourth openings may overlap each other to form the opening10H of the display panel10. In other words, the opening10H may include the first to fourth openings. According to another embodiment, at least one of the substrate100, the display layer DSL, the encapsulation layer ENL, the touch sensor layer TSL, or the optical functional layer OFL may not include an opening. For example, one or two selected from the substrate100, the display layer DSL, the encapsulation layer ENL, the touch sensor layer TSL, and the optical functional layer OFL may not include an opening. The cover window20may be on the display panel10. The cover window20may protect the display panel10. The cover window20may include at least one of glass, sapphire, or plastic. The cover window20may include, for example, ultra-thin glass (UTG) or colorless polyimide (CPI). The display driver30may be arranged in the fourth non-display area NDA4. The display driver30may receive control signals and power supply voltages and generate and output signals and voltages for driving the display panel10. The display driver30may include an integrated circuit (IC). The display circuit board40may be electrically connected to the display panel10. For example, the display circuit board40may be electrically connected to the fourth non-display area NDA4of the substrate100by an anisotropic conductive film. The display circuit board40may include a flexible printed circuit board (FPCB) that is bendable, or a rigid PCB that is rigid and is thus not easily bent. Alternatively, in some cases, the display circuit board40may include a complex PCB including both the rigid PCB and the FPCB The touch sensor driver50may be on the display circuit board40. The touch sensor driver50may include an IC. The touch sensor driver50may be bonded to the display circuit board40. The touch sensor driver50may be electrically connected to sensor electrodes of the touch sensor layer TSL of the display panel10through the display circuit board40. The component60may overlap the opening area OA. The component60may be located at the opening10H of the display panel10, as indicated by a solid line inFIG.2, or may be under the display panel10, as indicated by a dashed line. The component60may include an electronic element. The component60may include an electronic element using light or sound. For example, the electronic element may include a sensor (e.g., infrared sensor) configured to receive and use light, a camera configured to receive light and capture an image, a sensor configured to output and sense light or sound so as to measure a distance or recognize a fingerprint, a small lamp configured to output light, a speaker configured to output sound, and/or the like. When the component60is an electronic element using light, the component60may use light of various suitable wavelength bands, such as visible light, infrared light, and ultraviolet light. In some embodiments, the opening10H of the display panel10may be understood as a transmission portion through which the light and/or sound output from the component60to the outside or traveling from the outside toward the electronic element may be transmitted. According to another embodiment, when the display device1is used as a smart watch or a dashboard for a vehicle, the component60may be a member including a clock hand or a needle indicating certain information (e.g., vehicle speed, etc.). When the display device1includes a clock hand or a needle indicating certain information (e.g., vehicle speed, etc.), the component60may be exposed to the outside through the cover window20, and the cover window20may include an opening overlapping the opening10H of the display panel10. The component60may include component(s) related to the functions of the display panel10as described above, or may include component(s) such as accessories that increase a sense of beauty (i.e., an aesthetic appeal) of the display panel10. FIG.3is a schematic plan view of a display panel10according to an embodiment, andFIG.4is a schematic equivalent circuit diagram of a pixel P of the display panel10. Referring toFIG.3, the display panel10may include a display area DA, a non-display area NDA, and an opening area OA. In this case, the display area DA, the non-display area NDA, and the opening area OA may be defined in a substrate100of the display panel10. That is, the substrate100may include the display area DA, the non-display area NDA, and the opening area OA. The non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. The display panel10may include a plurality of pixels P arranged in the display area DA. As illustrated inFIG.4, each of the pixels P may include a pixel circuit PC and an organic light-emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. Each of the pixels P may emit red light, green light, blue light, or white light from the organic light-emitting diode OLED. The switching thin-film transistor T2may be connected to a scan line SL and a data line DL and may be configured to transmit, to the driving thin-film transistor T1, a data voltage or a data signal input from the data line DL according to a switching voltage or a switching signal input from the scan line SL. The storage capacitor Cst may be connected to the switching thin-film transistor T2and a driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the switching thin-film transistor T2and a first power supply voltage ELVDD supplied to the driving voltage line PL. The driving thin-film transistor T1may be connected to the driving voltage line PL and the storage capacitor Cst and may be configured to control a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a certain luminance according to the driving current. A second electrode of the organic light-emitting diode OLED may be configured to receive a second power supply voltage ELVSS. AlthoughFIG.4illustrates that the pixel circuit PC includes two thin-film transistors and one storage capacitor, the number of thin-film transistors and the number of storage capacitors may be variously changed in a suitable manner according to the design of the pixel circuit PC. Referring toFIG.3again, the first non-display area NDA1may surround the opening area OA. The first non-display area NDA1is an area in which a display element such as an organic light-emitting diode configured to emit light is not arranged. Signal lines configured to provide signals to the pixels P arranged around the opening area OA may pass through the first non-display area NDA1. The second non-display area NDA2may at least partially surround the display area DA. A scan driver configured to provide scan signals to the pixels P, a data driver configured to provide data signals to the pixels P, main power lines configured to provide a first power supply voltage and/or a second power supply voltage, and/or the like may be arranged in the second non-display area NDA2. The third non-display area NDA3is a bending area, andFIG.3illustrates an unbent (i.e., not bent) shape of the display panel10. The third non-display area NDA3may be connected to the second non-display area NDA2. According to an embodiment, the third non-display area NDA3may be between the second non-display area NDA2and the fourth non-display area NDA4. The fourth non-display area NDA4is a pad area and may be connected to the third non-display area NDA3. The display driver (e.g., see the display driver30of the embodiment shown inFIG.2) and/or the display circuit board (e.g., see the display circuit board40of the embodiment shown inFIG.2) may be arranged in the fourth non-display area NDA4. FIG.5is a schematic plan view of a portion of a display panel according to an embodiment.FIG.5schematically illustrates signal lines arranged in the first non-display area NDA1. Referring toFIG.5, pixels P may be arranged in a display area DA. Each of the pixels P may be connected to a scan line SL and a data line DL. The first non-display area NDA1may be between an opening area OA and the display area DA. The pixels P may be apart from or spaced from each other around the opening area OA. The pixels P may be vertically apart from or vertically spaced from each other around the opening area OA. The pixels P may be horizontally apart from or horizontally spaced from each other around the opening area OA. Signal lines adjacent to the opening area OA from among signal lines configured to supply signals to the pixels P may bypass the opening area OA. Some data lines DL passing through the display area DA may extend in the y direction to provide data signals to the pixels P arranged above and below with the opening area OA therebetween, and may bypass along the edge of the opening area OA in the first non-display area NDA1. Some scan lines SL passing through the display area DA may extend in the x direction to provide scan signals to the pixels P arranged left and right with the opening area OA therebetween, and may bypass along the edge of the opening area OA in the first non-display area NDA1. FIG.6is a plan view of a portion of a display panel according to an embodiment.FIG.6illustrates a transmission hole TAH and a dam portion DP arranged in the first non-display area NDA1. Also,FIG.6illustrates a second electrode213arranged in the first non-display area NDA1and a display area DA. Referring toFIG.6, at least one dam portion DP may be between an opening area OA and the display area DA on a substrate. In this specification, the dam portion DP refers to a configuration protruding with respect to a reference surface. Also, a recess may be defined, and the recess refers to a configuration that is concave with respect to the reference surface. The reference surface may be an upper surface of one of insulating layers on the substrate. The second electrode213and first and second functional layers including an organic material may be removed between the opening area OA and the dam portion DP. Therefore, it is possible to prevent or reduce infiltration of external air such as moisture through the opening area OA. That is, each of the first functional layer, the second functional layer, and the second electrode213may include a transmission hole TAH exposing the opening area OA and a portion of the first non-display area NDA1around the opening area OA. The transmission hole TAH may expose the first non-display area NDA1between the dam portion DP and the opening area OA. For example, the transmission hole TAH may expose a first upper surface ILUS1of a first insulating layer adjacent to the opening area OA. According to an embodiment, the first insulating layer adjacent to the opening area OA may surround or encircle the opening area OA. According to an embodiment, a first recess or a first opening provided in the first insulating layer may be between the transmission hole TAH and the dam portion DP. The transmission hole TAH may be formed by partially removing the first functional layer, the second functional layer, and the second electrode213through a laser lift-off process, and the first recess or the first opening may be introduced so as to form the transmission hole TAH through a laser lift-off process. According to an embodiment, the dam portion DP may have a ring shape that completely surrounds or encircles the opening area OA in the first non-display area NDA1. The diameter of the dam portion DP may be greater than the diameter of the opening area OA. FIGS.7A and7Bare schematic cross-sectional views of the display panel10taken along the line VII-VII′ ofFIG.6, according to an embodiment. Referring toFIGS.7A and7B, the display panel10may include a substrate100, a display layer DSL, and an encapsulation layer ENL. The display layer DSL may include a pixel circuit layer PCL and a display element layer DEL. The pixel circuit layer PCL may include a first insulating layer IL1, a middle insulating layer MIL, a second insulating layer IL2, a first organic insulating layer115, a second organic insulating layer116, a pixel circuit PC, and a data line DL. The display element layer DEL may include an organic light-emitting diode OLED, a pixel defining layer118, a spacer119, and a capping layer215. A substrate100may include a display area DA, a first non-display area NDA1, and an opening area OA. The first non-display area NDA1may be between (e.g., between in the x direction) the display area DA and the opening area OA. The substrate100may include a first base layer100a, a first barrier layer100b, a second base layer100c, and a second barrier layer100d. According to an embodiment, the first base layer100a, the first barrier layer100b, the second base layer100c, and the second barrier layer100dmay be stacked (e.g., sequentially stacked). According to an embodiment, the first base layer100a, the first barrier layer100b, the second base layer100c, and the second barrier layer100dmay be continuously arranged. For example, the first base layer100a, the first barrier layer100b, the second base layer100c, and the second barrier layer100dmay be continuously arranged in a direction from the display area DA to the opening area OA. According to an embodiment, the first base layer100a, the first barrier layer100b, the second base layer100c, and the second barrier layer100dmay extend continuously in the display area DA and the first non-display area NDA1. At least one of the first base layer100aor the second base layer100cmay include a polymer resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. Each of the first barrier layer100band the second barrier layer100dis a barrier layer for preventing or reducing infiltration of an external foreign material. Each of the first barrier layer100band the second barrier layer100dmay be a single layer or multiple layers including an inorganic material such as silicon nitride (SiNx), silicon oxide (SiO2), and/or silicon oxynitride (SiON). The display layer DSL including the pixel circuit layer PCL and the display element layer DEL may be on the substrate100. The first insulating layer IL1of the pixel circuit layer PCL may include a buffer layer111and a gate insulating layer112. The first insulating layer IL1may be arranged in the display area DA and the first non-display area NDA1. The pixel circuit PC may include a thin-film transistor TFT and a storage capacitor Cst. The buffer layer111may be on the substrate100. The buffer layer111may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiO2), and may include a single layer or multiple layers including the above-described inorganic insulating material. The thin-film transistor TFT may include a semiconductor layer Act, and the semiconductor layer Act may be on the buffer layer111. The semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, semiconductor oxide, or an organic semiconductor. The semiconductor layer Act may include a channel region, and a drain region and a source region on or at respective sides of the channel region. A gate electrode GE may overlap (e.g., overlap in the z direction) the channel region. The gate electrode GE may include a low resistance metal material. The gate electrode GE may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may include a single layer or multiple layers including the above-described material. The gate insulating layer112between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The middle insulating layer MIL may be between (e.g., between in the z direction) the first insulating layer IL1and the second insulating layer IL2. According to an embodiment, the middle insulating layer MIL may cover the gate electrode GE. The middle insulating layer MIL may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The second insulating layer IL2may be on the first insulating layer IL1. According to an embodiment, the second insulating layer IL2may be on the middle insulating layer MIL. The second insulating layer IL2may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The second insulating layer IL2may be a single layer or multiple layers including the above-described inorganic insulating material. A conductive pattern CP may be between the first insulating layer IL1and the second insulating layer IL2. According to an embodiment, the conductive pattern CP may be between the middle insulating layer MIL and the second insulating layer IL2. The conductive pattern CP may include a first layer L1and a second layer L2on the first layer L1. According to the present embodiment, the conductive pattern CP includes the first layer L1and the second layer L2so as to form the transmission hole TAH in the first non-display area NDA1through a laser lift-off process. For example, a pattern layer PTL (seeFIG.9A) formed in the first non-display area NDA1concurrently (e.g., simultaneously) with the conductive pattern CP may be removed through a laser lift-off process to form the transmission hole TAH as will be described in more detail below. According to an embodiment, the first layer L1may include titanium (Ti). According to another embodiment, the first layer L1may include amorphous silicon to which a dopant is added. The dopant added to the amorphous silicon (a-Si) may include one selected from boron (B), phosphorus (P), nitrogen (N), nickel (Ni), cobalt (Co), and fluorine (F). The second layer L2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). According to an embodiment, the conductive pattern CP may function as an upper electrode CE2of the storage capacitor Cst. For example, the conductive pattern CP may overlap the gate electrode GE thereunder. In this case, the gate electrode GE and the conductive pattern CP overlapping each other with the middle insulating layer MIL therebetween may form the storage capacitor Cst. That is, the gate electrode GE may function as a lower electrode CE1of the storage capacitor Cst. According to an embodiment, the storage capacitor Cst may overlap (e.g., overlap in the z direction) the thin-film transistor TFT. According to another embodiment, the storage capacitor Cst may not overlap (e.g., not overlap in the z direction) the thin-film transistor TFT. A drain electrode DE and a source electrode SE may be located on the second insulating layer IL2. The drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act through contact holes provided in the gate insulating layer112, the middle insulating layer MIL, and the second insulating layer IL2. Each of the drain electrode DE and the source electrode SE may include a material having good conductivity. Each of the drain electrode DE and the source electrode SE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and/or the like and may include a single layer or multiple layers including the above-described material. According to an embodiment, each of the drain electrode DE and the source electrode SE may have a multiple layer structure of Ti/Al/Ti. The first organic insulating layer115may be arranged to cover the drain electrode DE and the source electrode SE. The first organic insulating layer115may include an organic insulating material such as a general-purpose polymer (polymethylmethacrylate (PMMA), polystyrene (PS), etc.) a polymer derivative having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and any blend thereof. A connection electrode CM may be on the first organic insulating layer115. In this case, the connection electrode CM may be connected to the drain electrode DE or the source electrode SE through a contact hole of the first organic insulating layer115. The connection electrode CM may include a material having good conductivity. The connection electrode CM may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers including the above-described material. According to an embodiment, the connection electrode CM may have a multiple layer structure of Ti/Al/Ti. The second organic insulating layer116may be arranged to cover the connection electrode CM. The second organic insulating layer116may include an organic insulating material such as a general-purpose polymer (polymethylmethacrylate (PMMA), polystyrene (PS), etc.) a polymer derivative having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and any blend thereof. The organic light-emitting diode OLED may be on the second organic insulating layer116. The organic light-emitting diode OLED may emit red light, green light, or blue light, or may emit red light, green light, blue light, or white light. The organic light-emitting diode OLED may include a first electrode211, a middle layer212, and a second electrode213. The first electrode211may be a pixel electrode of the organic light-emitting diode OLED, and the second electrode213may be an opposite electrode of the organic light-emitting diode OLED. The first electrode211may be on the second organic insulating layer116. The first electrode211may be electrically connected to the connection electrode CM through a contact hole of the second organic insulating layer116. The first electrode211may include conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to another embodiment, the first electrode211may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. According to another embodiment, the first electrode211may further include a layer including ITO, IZO, ZnO, or In2O3above and/or below the reflective layer. For example, the first electrode211may have a multiple layer structure of ITO/Ag/ITO. The pixel defining layer118having an opening1180P exposing the central portion of the first electrode211may be on the first electrode211. The pixel defining layer118may include an organic insulating material and/or an inorganic insulating material. The opening1180P of the pixel defining layer118may define an emission area in which light is emitted from the organic light-emitting diode OLED. For example, the width of the opening1180P may correspond to the width of the emission area. The spacer119may be on the pixel defining layer118. The spacer119may include an organic insulating material such as polyimide. Alternatively, the spacer119may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), or may include an organic insulating material and an inorganic insulating material. According to an embodiment, the spacer119may include a material different from that of the pixel defining layer118. Alternatively, according to another embodiment, the spacer119and the pixel defining layer118may include a same material. In this case, the pixel defining layer118and the spacer119may be formed together in a mask process using a halftone mask or the like. According to an embodiment, the pixel defining layer118and the spacer119may be integrally formed (i.e., form a monolithic structure). The middle layer212may be on the pixel defining layer118. The middle layer212may include an emission layer212barranged in the opening1180P of the pixel defining layer118. The emission layer212bmay include a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. The middle layer212may further include at least one of a first functional layer212abetween the first electrode211and the emission layer212bor a second functional layer212cbetween the emission layer212band the second electrodes213. For example, the first functional layer212amay be between the first electrode211and the emission layer212b, and the second functional layer212cmay be omitted between the emission layer212band the second electrode213. As another example, the first functional layer212amay be omitted between the first electrode211and the emission layer212b, and the second functional layer212cmay be between the emission layer212band the second electrode213. As another example, the first functional layer212amay be between the first electrode211and the emission layer212b, and the second functional layer212cmay be between the emission layer212band the second electrode213. Hereinafter, a detailed description will be given focusing on a case in which the first functional layer212aand the second functional layer212care arranged. For example, the first functional layer212amay include a hole transport layer (HTL), or may include an HTL and a hole injection layer (HIL). The second functional layer212cmay include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer212aand/or the second functional layer212cmay be a common layer covering the entire substrate100, as in the second electrode213to be described in more detail below. The second electrode213may include a conductive material having a low work function. For example, the second electrode213may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Alternatively, the second electrode213may further include a layer such as ITO, IZO, ZnO, or In2O3on the (semi)transparent layer including the above-mentioned material. According to an embodiment, the capping layer215may be further on the second electrode213. The capping layer215may include LiF, an inorganic material, and/or an organic material. The first non-display area NDA1may include a first sub-non-display area SNDA1and a second sub-non-display area SNDA2. The first sub-non-display area SNDA1may be farther from the opening area OA than the second sub-non-display area SNDA2. That is, the second sub-non-display area SNDA2may be between the first sub-non-display area SNDA1and the opening area OA. According to an embodiment, the first sub-non-display area SNDA1may be between the second sub-non-display area SNDA2and the display area DA. According to an embodiment, the second organic insulating layer116may cover the side surface of the first organic insulating layer115. According to another embodiment, the second organic insulating layer116may expose the side surface of the first organic insulating layer115. Hereinafter, a detailed description will be given focusing on a case in which the second organic insulating layer116covers the side surface of the first organic insulating layer115, as illustrated inFIGS.7A and7B. According to an embodiment, the pixel defining layer118may cover the side surface of the second organic insulating layer116. According to another embodiment, the pixel defining layer118may expose the side surface of the second organic insulating layer116. Hereinafter, a detailed description will be given focusing on a case in which the pixel defining layer118covers the side surface of the second organic insulating layer116, as illustrated inFIGS.7A and7B. Signal lines, for example, the data lines DL described above with reference toFIG.5, may be on the first sub-non-display area SNDA1. According to an embodiment, the data lines DL may be between the second insulating layer IL2and the first organic insulating layer115and/or between the first organic insulating layer115and the second organic insulating layer116. When the data lines DL are on or at different layers from each other, the width of the first non-display area NDA1may be reduced. AlthoughFIGS.7A and7Billustrate that only the data line DL is arranged in the first sub-non-display area SNDA1, the scan line bypassing the opening area OA, which has been described above with reference toFIG.5, may also be arranged in the first sub-non-display area SNDA1. The dam portion DP may be provided by stacking multiple layers. According to an embodiment, the dam portion DP may protrude from the upper surface of the second insulating layer IL2. According to an embodiment, the dam portion DP may include an organic pattern layer116A, a first upper organic pattern layer118A, and a second upper organic pattern layer119A. The organic pattern layer116A may be separated from or spaced from the first organic insulating layer115and the second organic insulating layer116. According to an embodiment, the organic pattern layer116A and the second organic insulating layer116may include a same material. According to another embodiment, the organic pattern layer116A and the first organic insulating layer115may include a same material. According to another embodiment, the organic pattern layer116A may include a first organic pattern layer and a second organic pattern layer on the first organic pattern layer. In this case, the first organic pattern layer and the first organic insulating layer115may include a same material. The second organic pattern layer and the second organic insulating layer116may include a same material. The first upper organic pattern layer118A may be on the organic pattern layer116A. According to an embodiment, the first upper organic pattern layer118A may be on the upper surface of the organic pattern layer116A. The first upper organic pattern layer118A may be separated from or spaced from the pixel defining layer118. The first upper organic pattern layer118A and the pixel defining layer118may include a same material. The second upper organic pattern layer119A may be on the first upper organic pattern layer118A. The second upper organic pattern layer119A may be separated from or spaced from the spacer119. The second upper organic pattern layer119A and the spacer119may include a same material. The first insulating layer IL1may include a first recess R1or a first opening OP1overlapping the first non-display area NDA1. Referring toFIG.7A, a first opening OP1may penetrate through the upper surface of the first insulating layer IL1and the lower surface of the first insulating layer IL1. According to an embodiment, the first opening OP1may overlap the opening of the buffer layer111and the opening of the gate insulating layer112. Referring toFIG.7B, the first insulating layer IL1may be recessed in a depth or thickness direction to define the first recess R1. According to an embodiment, the first recess R1may be defined by the upper surface of the buffer layer111and the opening of the gate insulating layer112. According to another embodiment, the gate insulating layer112may be recessed in a depth or thickness direction to define the first recess R1. According to another embodiment, the first recess R1may be defined by the recess of the buffer layer111in the depth or thickness direction and the opening of the gate insulating layer112. The first recess R1may be arranged closer to the opening area OA than the dam portion DP. That is, the first recess R1may be between the opening area OA and the dam portion DP. Hereinafter, a detailed description will be given focusing on a case in which the first insulating layer IL1includes the first opening OP1. The first opening OP1may be arranged closer to the opening area OA than the dam portion DP. That is, the first opening OP1may be between the opening area OA and the dam portion DP. According to an embodiment, the first insulating layer IL1may include at least one first opening OP1. For example, the first insulating layer IL1may include one first opening OP1. As another example, the first insulating layer IL1may include a plurality of first openings OP1. The middle insulating layer MIL may include a middle opening MILOP connected to the first recess R1or the first opening OP1. The middle opening MILOP may penetrate through the upper and lower surfaces of the middle insulating layer MIL. The middle opening MILOP may be connected to the first recess R1or the first opening OP1. According to an embodiment, the middle insulating layer MIL may be on the first upper surface ILUS1of the first insulating layer IL1. For example, the first insulating layer IL1(e.g., a portion of the first insulating layer IL1) may be between the first recess R1or the first opening OP1and the opening area OA, and the upper surface of the first insulating layer IL1(e.g., the upper surface of the portion of the first insulating layer IL1) arranged between the first recess R1or the first opening OP1and the opening area OA may be defined or referred to as the first upper surface ILUS1of the first insulating layer IL1. In this case, the middle insulating layer MIL (e.g., a portion of the middle insulating layer MIL) may be on the first upper surface ILUS1of the first insulating layer IL1. The portion of the middle insulating layer MIL may be between the middle opening MILOP and the opening area OA. The second insulating layer IL2may include a second opening OP2. The second opening OP2may penetrate through the upper and lower surfaces of the second insulating layer IL2. The second opening OP2may be connected to the middle opening MILOP. The second opening OP2may expose the first upper surface ILUS1of the first insulating layer IL1. According to an embodiment, the second opening OP2may expose the second upper surface MILUS of the middle insulating layer MIL. The middle insulating layer MIL (e.g., a portion of the middle insulating layer MIL) may be between the middle opening MILOP and the opening area OA, and the upper surface of the middle insulating layer MIL (e.g., the upper surface of the portion of the middle insulating layer MIL) arranged between the middle opening MILOP and the opening area OA may be defined or referred to as the second upper surface MILUS of the middle insulating layer MIL. Alternatively, the upper surface of the middle insulating layer MIL on the first upper surface ILUS1of the first insulating layer IL1may be defined or referred to as the second upper surface MILUS of the middle insulating layer MIL. According to an embodiment, the second insulating layer IL2may include a groove between (e.g., between in the x direction) the organic pattern layer116A and the first organic insulating layer115. The groove may be formed by over-etching the second insulating layer IL2. In other words, the groove may be formed in the second insulating layer IL2. According to some embodiments, the groove may not be provided. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may extend from the display area DA to the first non-display area NDA1. According to an embodiment, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may cover the dam portion DP, and may extend to the first opening OP1or the first recess R1. Therefore, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be within the first opening OP1or the first recess R1, and may overlap the first recess R1or the first opening OP1. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be disconnected from the first non-display area NDA1. According to an embodiment, each of the first functional layer212a, the second functional layers212c, the second electrode213, and the capping layer215may include the transmission hole TAH exposing the first upper surface ILUS1of the first insulating layer IL1. Specifically, at least one of the first functional layer212aor the second functional layer212cmay include a first transmission hole TAH1exposing the first upper surface ILUS1of the first insulating layer IL1. The second electrode213may include a second transmission hole TAH2exposing the first upper surface ILUS1of the first insulating layer IL1. The capping layer215may include a third transmission hole TAH3exposing the first upper surface ILUS1of the first insulating layer IL1. Also, according to an embodiment, each of the first transmission hole TAH1, the second transmission hole TAH2, and the third transmission hole TAH3may expose the second upper surface MILUS of the middle insulating layer MIL. The area of the transmission hole TAH may be greater than the area of the opening area OA. When at least one of the first functional layer212aor the second functional layer212ceach including an organic material is entirely formed in the first non-display area NDA1and extends to the opening area OA, moisture may infiltrate toward the organic light-emitting diode OLED arranged in the display area DA through the first functional layer212aand the second functional layer212cdue to the characteristics of the organic material layer. According to the present embodiment, the first functional layer212aand the second functional layer212cmay be arranged in the first recess R1or the first opening OP1, and the first transmission hole TAH1exposing the first upper surface ILUS1of the first insulating layer IL1may be formed. Therefore, according to the present embodiment, it may be possible to prevent or reduce infiltration of a foreign material or moisture into the organic light-emitting diode OLED by at least one of the first functional layer212aor the second functional layer212c. The encapsulation layer ENL may cover the organic light-emitting diode OLED. The encapsulation layer ENL may be on the second electrode213and/or the capping layer215. According to an embodiment, the encapsulation layer ENL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.FIGS.7A and7Billustrate that the encapsulation layer ENL includes a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330, which are stacked (e.g., sequentially stacked). The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may extend from the display area DA to the first non-display area NDA1. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may be entirely and continuously arranged in the first non-display area NDA1. According to an embodiment, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may extend continuously in the display area DA and in the first non-display area NDA1. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may extend to the dam portion DP and may come in contact with each other on the upper surface of the dam portion DP. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may cover the first recess R1or the first opening OP1, and may extend to the opening area OA. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap the transmission hole TAH. Specifically, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap the first transmission hole TAH1, the second transmission hole TAH2, and the third transmission hole TAH3. In this case, the first inorganic encapsulation layer310may overlap the first recess R1or the first opening OP1, and may come in contact with the second upper surface MILUS of the middle insulating layer MIL adjacent to the opening area OA. According to an embodiment, the first inorganic encapsulation layer310may contact the second inorganic encapsulation layer330and may be between the second inorganic encapsulation layer330and the second upper surface MILUS of the middle insulating layer MIL. Therefore, because the organic material layer is not on the second upper surface MILUS of the middle insulating layer MIL, it is possible to prevent or reduce infiltration of moisture toward the organic light-emitting diode OLED arranged in the display area DA. The organic encapsulation layer320may be formed by applying and curing a monomer. The flow of the monomer may be controlled by the dam portion DP. That is, the end portion of the organic encapsulation layer320may be located at one side of the dam portion DP. FIG.8is a schematic cross-sectional view of the display panel10taken along the line VIII-VIII′ ofFIG.3, according to an embodiment. InFIG.8, the same reference numerals as those inFIG.7Arefer to the same members, and redundant descriptions thereof may not be repeated. Referring toFIG.8, the display panel10may include a substrate100, a first insulating layer IL1, a middle insulating layer MIL, a second insulating layer IL2, a connection line CL, and bending organic layers115B,116B,118B, and119B. The substrate100may include a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. The third non-display area NDA3may be a bending area, and the fourth non-display area NDA4may be a pad area. The third non-display area NDA3may be between the fourth non-display area NDA4and the second non-display area NDA2. The first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may be arranged in the second non-display area NDA2and the fourth non-display area NDA4. Each of the first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may include a bending opening BOP exposing the third non-display area NDA3of the substrate100. That is, a portion of the first insulating layer IL1, a portion of the middle insulating layer MIL, and a portion of the second insulating layer IL2may be respectively separated from or spaced from another portion of the first insulating layer IL1, another portion of the middle insulating layer MIL, and another portion of the second insulating layer IL2based on the third non-display area NDA3. Therefore, the display panel10may be bent while preventing or substantially preventing excessive tensile stress from being applied in the third non-display area NDA3, which is the bending area. The bending opening BOP may be formed by overlapping the opening of the first insulating layer IL1, the opening of the middle insulating layer MIL, and the opening of the second insulating layer IL2, which overlap the third non-display area NDA3. In other words, the bending opening BOP may include the opening of the first insulating layer IL1, the opening of the middle insulating layer MIL, and the opening of the second insulating layer IL2. In this case,FIG.8illustrates that the inner surface of the opening of the first insulating layer IL1, the inner surface of the opening of the middle insulating layer MIL, and the inner surface of the opening of the second insulating layer IL2coincide with each other, but according to an another embodiment, the inner surface of the opening of the first insulating layer IL1, the inner surface of the opening of the middle insulating layer MIL, and the inner surface of the opening of the second insulating layer IL2may not coincide with each other. In this case, the bending opening BOP may have a step. According to an embodiment, the width of the bending opening BOP may be greater than the width of the third non-display area NDA3. In this case, according to an embodiment, the width of the bending opening BOP may be defined as or refer to the shortest distance between facing surfaces of the buffer layer111defining the bending opening BOP. The first bending organic layer115B may be arranged in the bending opening BOP. In this case, the first bending organic layer115B may fill the bending opening BOP. Therefore, the first bending organic layer115B may overlap the bending opening BOP. According to an embodiment, the first bending organic layer115B and the first organic insulating layer (e.g., see the first organic insulating layer115of the embodiment shown inFIG.7A) may include a same material. The connection line CL may overlap the third non-display area NDA3, and the connection line CL may extend from the second non-display area NDA2to the fourth non-display area NDA4. According to an embodiment, the connection line CL may be on the upper surface of the second insulating layer IL2and the upper surface of the first bending organic layer115B. According to an embodiment, the connection line CL and the connection electrode CM ofFIG.7Amay include a same material. The connection line CL may be configured to transmit, to the pixel arranged in the display area, a signal transmitted from the display driver or the display circuit board arranged in the fourth non-display area NDA4, which is the pad area. The second bending organic layer116B, the third bending organic layer118B, and the fourth bending organic layer119B may overlap the third non-display area NDA3, and may be stacked (e.g., sequentially stacked). According to an embodiment, the second bending organic layer116B and the second organic insulating layer (e.g., see the second organic insulating layer116of the embodiment shown inFIG.7A) may include a same material. The third bending organic layer118B and the pixel defining layer (e.g., see the pixel defining layer118of the embodiment shown inFIG.7A) may include a same material. The fourth bending organic layer1196and the spacer (e.g., see the spacer119of the embodiment shown inFIG.7A) may include a same material. When the display panel10is bent, the first bending organic layer1156, the second bending organic layer1166, the third bending organic layer1186, and the fourth bending organic layer1196may prevent or reduce the damage to the connection line CL due to tensile stress. FIGS.9A-9Kare cross-sectional views illustrating a method of manufacturing a display device, according to an embodiment. Referring toFIG.9A, a display substrate DS may be prepared. The display substrate DS may include a substrate100and a first insulating layer IL1. The first insulating layer IL1may be on a display area DA and a first non-display area NDA1. The display substrate DS may include a semiconductor layer Act and a gate electrode GE. The semiconductor layer Act may be between the buffer layer111and the gate insulating layer112. The gate electrode GE may be on the gate insulating layer112. A middle insulating layer MIL may be formed on the first insulating layer IL1. The middle insulating layer MIL may be arranged in the display area DA and the first non-display area NDA1, and may cover the gate electrode GE. A conductive pattern CP may be formed on the first insulating layer IL1. According to an embodiment, after the middle insulating layer MIL is formed, the conductive pattern CP may be formed on the middle insulating layer MIL. The conductive pattern CP may include a first layer L1and a second layer L2on the first layer L1. According to an embodiment, the thickness of the first layer L1may be less than the thickness of the second layer L2. According to an embodiment, the first layer L1may include titanium (Ti). According to another embodiment, the first layer L1may include amorphous silicon to which a dopant is added. The second layer L2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). A pattern layer PTL may be formed on the first non-display area NDA1. According to an embodiment, the pattern layer PTL may be formed on the first insulating layer IL1. According to an embodiment, after the middle insulating layer MIL is formed, the pattern layer PTL may be formed on the middle insulating layer MIL. According to an embodiment, the pattern layer PTL may include a lower pattern layer PTL1and an upper pattern layer PTL2on the lower pattern layer PTL1. According to an embodiment, the thickness of the lower pattern layer PTL1may be less than the thickness of the upper pattern layer PTL2. The lower pattern layer PTL1and the first layer L1of the conductive pattern CP may include a same material. The upper pattern layer PTL2and the second layer L2of the conductive pattern CP may include a same material. The pattern layer PTL may be formed concurrently (e.g., simultaneously) with the conductive pattern CP. Specifically, the conductive layer may be continuously formed on the middle insulating layer MIL and then patterned to form the pattern layer PTL and the conductive pattern CP. Referring toFIG.9B, a second insulating layer IL2may be formed. The second insulating layer IL2may be formed in the display area DA and the first non-display area NDA1. The second insulating layer IL2may be formed on the middle insulating layer MIL. The second insulating layer IL2may cover the conductive pattern CP and the pattern layer PTL. Referring toFIG.9C, the first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may be partially removed. According to an embodiment, the first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may be partially etched. The first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may be partially removed to form a first contact hole CNT1. The first contact hole CNT1may expose a portion of the semiconductor layer Act. A second opening OP2may be formed in the second insulating layer IL2. The second opening OP2may expose the pattern layer PTL. The second opening OP2may expose the upper surface LUS2of the upper pattern layer PTL2. According to an embodiment, the width of the second opening OP2may be greater than the width of the pattern layer PTL. A middle opening MILOP may be formed in the middle insulating layer MIL. The middle opening MILOP may be formed around or adjacent to the pattern layer PTL. According to an embodiment, a plurality of middle openings MILOP may be formed around the pattern layer PTL. The pattern layer PTL may prevent or substantially prevent the middle insulating layer MIL (e.g., the portion of the middle insulating layer MIL) under or covered by the pattern layer PTL from being etched. According to an embodiment, the middle opening MILOP may be formed when the second opening OP2of the second insulating layer IL2is formed. A first recess R1-1may be formed in the first insulating layer IL1. The first recess R1-1may be formed around the pattern layer PTL. According to an embodiment, a plurality of first recesses R1-1may be formed around the middle opening MILOP. The pattern layer PTL may prevent or substantially prevent the first insulating layer IL1under the pattern layer PTL from being etched. The first recess R1-1may be defined by the opening of the gate insulating layer112and the recess of the buffer layer111. The first recess R1-1may be connected to the middle opening MILOP of the middle insulating layer MIL. According to an embodiment, when a plurality of first recesses R1-1and a plurality of middle openings MILOP are provided, the first recesses R1-1may be respectively connected to the middle openings MILOP. According to an embodiment, the first contact hole CNT1exposing the semiconductor layer Act and the second opening OP2exposing the pattern layer PTL may be formed in the same process. Therefore, the pattern layer PTL may be exposed without an additional mask process. Referring toFIG.9D, a source electrode SE, a drain electrode DE, and a data line DL may be formed. The source electrode SE and the drain electrode DE are formed on the middle insulating layer MIL, and may be connected to the semiconductor layer Act through the first contact hole CNT1. In one or more embodiments, the source electrode SE and the drain electrode DE are formed on the second insulating layer IL2, and may be connected to the semiconductor layer Act through the first contact hole CNT1extending through the second insulating layer IL2, the middle insulating layer MIL, and the gate insulating layer112. The data line DL may be formed on the middle insulating layer MIL. For example, the data line DL may be formed on the middle insulating layer MIL with the second insulating layer IL2therebetween. A photoresist layer PRL including a photoresist opening PRLOP may be formed. A photoresist solution may be applied onto the display substrate DS. The photoresist solution may cover the first recess R1-1, the middle opening MILOP, the second opening OP2, the pattern layer PTL, the data line DL, the source electrode SE, the drain electrode DE, and the second insulating layer IL2. The photoresist solution may be formed as a positive type or a negative type. In the case of a positive type photoresist solution, portions of the positive photoresist solution exposed to light may be removed (e.g., etched) in a subsequent develop process. In the case of a negative type photoresist solution, portions of the negative photoresist solution other than the portions of the negative photoresist solution exposed to light may be removed (e.g., etched) in a subsequent develop process. Hereinafter, a detailed description will be given focusing on a case in which the photoresist solution is a positive type. The photoresist solution may be applied by various suitable methods such as spin-coating, slit-coating, spraying, or immersion. The photoresist layer PRL may be exposed. In this case, at least a portion of the photoresist layer PRL may be exposed. For example, when a photo mask is used, a region of the photoresist layer PRL overlapping an opening of the photo mask may be exposed. According to an embodiment, the opening of the photo mask may be arranged to overlap the third non-display area NDA3, and the photoresist layer PRL arranged in the third non-display area NDA3may be exposed. A portion of the photoresist layer PRL may be removed through a develop process. Therefore, a photoresist opening PRLOP overlapping the third non-display area NDA3may be formed. According to an embodiment, the photoresist opening PRLOP may be formed to overlap the third non-display area NDA3, a portion of the second non-display area NDA2, and a portion of the fourth non-display area NDA4. Referring toFIG.9E, the first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2, which overlap the photoresist opening PRLOP, may be etched. Therefore, a bending opening BOP overlapping the third non-display area NDA3may be formed. In this case, because the photoresist layer PRL is arranged in the display area DA and the first non-display area NDA1, it is possible to prevent or substantially prevent the insulating layers under the photoresist layer PRL from being etched. The photoresist layer PRL may be removed or stripped through a develop process. Therefore, the photoresist layer PRL may be removed or stripped from the display substrate DS. Referring toFIG.9F, a first organic insulating layer115may be formed. The first organic insulating layer115may be formed by applying an organic material onto the entire display substrate DS and performing a photocuring process and a patterning process thereon. A connection electrode CM may be formed, and a second organic insulating layer116and an organic pattern layer116A may be formed. The second organic insulating layer116and the organic pattern layer116A may be formed by applying an organic material on the entire display substrate DS and performing a photocuring process and a patterning process thereon. In this case, the second organic insulating layer116and the organic pattern layer116A may include a same material and may be formed at the same time. According to some embodiments, the organic pattern layer116A may be formed concurrently (e.g., simultaneously) when the first organic insulating layer115is formed. A conductive layer211L may be formed on the pattern layer PTL and the display area DA. The conductive layer211L may be formed to cover the upper pattern layer PTL2. The conductive layer211L may include conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to another embodiment, the conductive layer211L may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. According to another embodiment, the conductive layer211L may further include a layer including ITO, IZO, ZnO, or In2O3above and/or below the reflective layer. For example, the conductive layer211L may have a multiple layer structure of ITO/Ag/ITO. Referring toFIG.9G, the conductive layer211L may be patterned to form a first electrode211. Also, according to an embodiment, the upper pattern layer PTL2may be removed. According to an embodiment, after the conductive layer211L is etched, the upper pattern layer PTL2may be etched. Therefore, the conductive layer211L and the upper pattern layer PTL2may be removed to expose the lower pattern layer PTL1. In this case, the upper surface LUS1of the lower pattern layer PTL1may be exposed to the outside. All the pattern layers PTL may be unsuitable for use as a sacrificial layer for a laser lift-off process. According to the present embodiment, the upper pattern layer PTL2may be removed, and only the lower pattern layer PTL1is left to optimize the laser lift-off process. According to an embodiment, when the conductive layer211L and the upper pattern layer PTL2are removed, a first opening OP1may be formed. The first opening OP1may be formed by over-etching the first insulating layer IL1when the conductive layer211L and the upper pattern layer PTL2are removed. According to another embodiment, when the conductive layer211L and the upper pattern layer PTL2are removed, the buffer layer111may be over-etched. In this case, the depth of the first recess may become deeper. According to an embodiment, when the conductive layer211L and the upper pattern layer PTL2are removed, a portion of the second insulating layer IL2may be over-etched. For example, when the conductive layer211L and the upper pattern layer PTL2are removed, the second insulating layer IL2between (e.g., between in the x direction) the organic pattern layer116A and the first organic insulating layer115may be over-etched. In this case, a groove may be formed (e.g., formed in the second insulating layer IL2) between the organic pattern layer116A and the first organic insulating layer115. According to some embodiments, a groove may not be formed (e.g., not be formed in the second insulating layer IL2) between the organic pattern layer116A and the first organic insulating layer115. Referring toFIG.9H, a pixel defining layer118having an opening118OP exposing a central portion of the first electrode211may be formed on the first electrode211, and a spacer119may be formed on the pixel defining layer118. A first upper organic pattern layer118A and a second upper organic pattern layer119A may be formed on the organic pattern layer116A. According to an embodiment, the first upper organic pattern layer118A may be formed concurrently (e.g., simultaneously) with the pixel defining layer118. According to an embodiment, when the first upper organic pattern layer118A and the pixel defining layer118include an organic material, the first upper organic pattern layer118A and the pixel defining layer118may be formed by applying an organic material onto the entire substrate100and performing a photocuring process and a patterning process thereon. In this case, the first upper organic pattern layer118A and the pixel defining layer118may include a same material. According to an embodiment, the second upper organic pattern layer119A may be formed concurrently (e.g., simultaneously) with the spacer119. When the second upper organic pattern layer119A and the spacer119include an organic material, the second upper organic pattern layer119A and the spacer119may be formed by applying an organic material onto the entire substrate100and performing a photocuring process and a patterning process thereon. In this case, the second upper organic pattern layer119A and the spacer119may include a same material. A second electrode213and at least one of a first functional layer212aor a second functional layer212cmay be formed. Specifically, the first functional layer212a, an emission layer212b, the second functional layer212c, the second electrode213, and a capping layer215may be sequentially formed on the entire display substrate DS. The emission layer212bmay overlap the first electrode211. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be stacked (e.g., sequentially stacked) on the lower pattern layer PTL1. The second electrode213and at least one of the first functional layer212aor the second functional layer212con the lower pattern layer PTL1may be removed. According to an embodiment, laser light may be irradiated on the lower pattern layer PTL1. Specifically, the laser light may travel in the thickness direction of the substrate100from the lower surface of the substrate100and may be irradiated on the lower surface of the lower pattern layer PTL1. The laser light may have an infrared wavelength. When the laser light is infrared light, the transmittance of the laser light with respect to the substrate100, the first insulating layer IL1, and the middle insulating layer MIL is about 80% to about 90% or greater, the laser light may efficiently reach the lower pattern layer PTL1. Because the lower pattern layer PTL1includes an opaque metal, the lower pattern layer PTL1may absorb the laser light. According to an embodiment, at least a portion of the lower pattern layer PTL1may be thermally expanded and lifted off from the middle insulating layer MIL. Referring toFIG.9I, when the lower pattern layer PTL1includes titanium (Ti), the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be lifted off together with the lower pattern layer PTL1. Therefore, a first transmission hole TAH1exposing the second upper surface MILUS of the middle insulating layer MIL may be formed in the first functional layer212aand the second functional layer212c. A second transmission hole TAH2exposing the second upper surface MILUS of the middle insulating layer MIL may be formed in the second electrode213. A third transmission hole TAH3exposing the second upper surface MILUS of the middle insulating layer MIL may be formed in the capping layer215. Also, the first transmission hole TAH1, the second transmission hole TAH2, and the third transmission hole TAH3may expose the first upper surface ILUS1of the first insulating layer IL1. The melting point of the material forming the lower pattern layer PTL1may be higher than the melting point of the material forming the second electrode213. As a comparative example, when the lower pattern layer PTL1includes silver (Ag), the lower pattern layer PTL1may be lifted off before the second electrode213on the lower pattern layer PTL1is melted, and silver (Ag) of the second electrode213is bonded thereto. This may act as a foreign material. The foreign material may be arranged around the lower pattern layer PTL1, for example, in the dam portion DP. In this case, the foreign material may damage the encapsulation layer and may form an inflow passage for moisture or the like. Therefore, the organic light-emitting diode OLED may be damaged. According to the present embodiment, the lower pattern layer PTL1may include a material having a melting point higher than that of the second electrode213. The second electrode213may be first melted, and the lower pattern layer PTL1may be lifted off. Therefore, a foreign material such as, for example, silver (Ag) particles may not be generated. Also, according to the present embodiment, because the lower pattern layer PTL1may be formed concurrently (e.g., simultaneously) with the conductive pattern CP, a process time may be shortened, and a mask process may not be added. Referring toFIGS.9J and9K, an encapsulation layer ENL may be formed. The encapsulation layer ENL may include a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may extend from the display area DA to the transmission hole TAH to overlap the transmission hole TAH. Therefore, the first inorganic encapsulation layer310may come in contact with the second upper surface MILUS of the middle insulating layer MIL. The opening area OA may be formed by removing the substrate100and the first insulating layer IL1thereon along a cutting line CUL. According to the present embodiment, because the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215are not exposed to the outside on the opening area OA, it is possible to prevent or reduce infiltration of moisture through at least one of the first functional layer212aor the second functional layer212c. FIG.10is a schematic cross-sectional view of the display panel10taken along the line VII-VII′ ofFIG.6, according to another embodiment. InFIG.10, the same reference numerals as those inFIG.7Arefer to the same members, and redundant descriptions thereof may not be repeated. The display panel10illustrated inFIG.10differs from the embodiment illustrated inFIG.7Ain that the display panel10further includes a lower pattern layer PTL1-1. Referring toFIG.10, the display panel10may include a substrate100, a first insulating layer11_1, a second insulating layer IL2, a conductive pattern CP-1, an organic light-emitting diode OLED as a display element, and a lower pattern layer PTL1-1. The substrate100may include an opening area OA, a display area DA surrounding the opening area OA, and a first non-display area NDA1between the opening area OA and the display area DA. The first insulating layer IL1may include a first recess or a first opening OP1overlapping the first non-display area NDA1and may be on the substrate100. The second insulating layer IL2may include a second opening OP2exposing the first upper surface ILUS1of the first insulating layer IL1between the first recess or the first opening OP1and the opening area OA and may be on the first insulating layer IL1. The conductive pattern CP-1may be between the first insulating layer IL1and the second insulating layer IL2, and may include a first layer L1-1and a second layer L2. The first layer L1-1may include amorphous silicon to which a dopant is added. The dopant added to the amorphous silicon (a-Si) may include one selected from boron (B), phosphorus (P), nitrogen (N), nickel (Ni), cobalt (Co), and fluorine (F). The second layer L2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). The organic light-emitting diode OLED may be arranged to overlap the display area DA on the second insulating layer IL2, and may include a first electrode211, an emission layer212bon the first electrode211, and a second electrode213on the emission layer212b. According to an embodiment, the lower pattern layer PTL1-1may be on the first upper surface ILUS1of the first insulating layer IL1. According to an embodiment, the lower pattern layer PTL1-1may be on the second upper surface MILUS of the middle insulating layer MIL. The lower pattern layer PTL1-1may include amorphous silicon to which a dopant is added. In this case, the lower pattern layer PTL1-1and the first layer L1-1of the conductive pattern CP-1may include a same material. When the display panel10is manufactured, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215, which are formed on the lower pattern layer PTL1-1, may be removed. Specifically, when laser is irradiated on the region in which the lower pattern layer PTL1-1is arranged, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215, which are formed on the lower pattern layer PTL1-1, may be removed. Therefore, the transmission hole TAH exposing the lower pattern layer PTL1-1may be formed, and the first inorganic encapsulation layer310and the lower pattern layer PTL1-1arranged in the transmission hole TAH may come in contact with each other, thereby preventing or reducing infiltration of a foreign material or moisture into the organic light-emitting diode OLED. FIGS.11A and11Bare schematic cross-sectional views illustrating a method of manufacturing a display device, according to another embodiment. InFIGS.11A and11B, the same reference numerals as those inFIGS.9H,9I, and9Jrefer to the same members, and redundant descriptions thereof may not be repeated. Referring toFIG.11A, a display substrate DS including a substrate100including a first non-display area NDA1and a display area DA, and a first insulating layer IL1on the substrate100may be prepared. A conductive pattern CP-1including a first layer L1-1and a second layer L2may be formed. A pattern layer may include a lower pattern layer PTL1-1and an upper pattern layer, and may be formed on the first non-display area NDA1. According to an embodiment, the pattern layer may be formed on a second upper surface MILUS of a middle insulating layer MIL. The lower pattern layer PTL1-1may include amorphous silicon to which a dopant is added. A conductive layer may be formed on the pattern layer and the display area DA, and the conductive layer may be patterned to form a first electrode211. In this case, the upper pattern layer may be removed. At least one of a first functional layer212aor a second functional layer212c, a second electrode213, and a capping layer215may be formed on the lower pattern layer PTL1-1and the first electrode211. At least one of the first functional layer212aor the second functional layer212c, the second electrode213, and the capping layer215, which are on the lower pattern layer PTL1-1, may be removed. Laser light may be irradiated on the lower pattern layer PTL1-1to remove at least one of the first functional layer212aor the second functional layer212c, the second electrode213, and the capping layer215. In this case, the upper surface LUS1-1of the lower pattern layer PTL1-1may be exposed through a transmission hole TAH. That is, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be lifted off from the lower pattern layer PTL1-1. The melting point of the lower pattern layer PTL1-1when the lower pattern layer PTL1-1includes amorphous silicon to which a dopant is added may be higher than the melting point of the lower pattern layer when the lower pattern layer includes titanium (Ti). Therefore, when the lower pattern layer PTL1-1includes amorphous silicon to which a dopant is added, the lower pattern layer PTL1-1may not be lifted off from the middle insulating layer MIL or the first insulating layer IL1. Referring toFIG.11B, an encapsulation layer ENL may be formed. The encapsulation layer ENL may include a first inorganic encapsulation layer310, an organic encapsulation layer320, and a second inorganic encapsulation layer330. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may extend from the display area DA to the transmission hole TAH to overlap the transmission hole TAH. Therefore, the first inorganic encapsulation layer310may come in contact with the upper surface LUS1-1of the lower pattern layer PTL1-1. FIG.12is a schematic cross-sectional view of a display panel according to another embodiment. InFIG.12, the same reference numerals as those inFIG.7Arefer to the same members, and redundant descriptions thereof may not be repeated. Referring toFIG.12, the display panel may include a substrate100, a first insulating layer IL1, a second insulating layer IL2, a conductive pattern, an organic light-emitting diode as a display element, and a middle conductive pattern MCP. The substrate100may include an opening area OA and a first non-display area NDA1. The first insulating layer IL1may include a first recess or a first opening OP1overlapping the first non-display area NDA1and may be on the substrate100. Hereinafter, a detailed description will be given focusing on a case in which the first insulating layer IL1includes the first opening OP1. According to an embodiment, a plurality of first openings OP1may be provided. The first openings OP1may be apart from or spaced from each other in the first non-display area NDA1. The second insulating layer IL2may include a second opening OP2exposing the first upper surface ILUS1of the first insulating layer IL1between the first recess or the first opening OP1and the opening area OA, and may be on the first insulating layer IL1. The middle insulating layer MIL may be between the first insulating layer IL1and the second insulating layer IL2. The middle insulating layer MIL may include a middle opening MILOP connected to the first opening OP1. A plurality of middle openings MILOP may be provided in the first non-display area NDA1. According to an embodiment, the middle openings MILOP may be connected to the first openings OP1, respectively. The middle conductive pattern MCP may be between the first openings OP1. When the first insulating layer IL1includes a plurality of first recesses, the middle conductive pattern MCP may be between the first recesses. The middle conductive pattern MCP and the first layer of the conductive pattern may include a same material. For example, the middle conductive pattern MCP may include titanium (Ti). As another example, the middle conductive pattern MCP may include amorphous silicon to which a dopant is added. The organic light-emitting diode may be on the second insulating layer IL2to overlap the display area, and may include a first electrode211, an emission layer on the first electrode211, and a second electrode213on the emission layer. A capping layer215may be further arranged on the second electrode213. The organic light-emitting diode may further include a first functional layer212abetween the first electrode211and the emission layer and/or a second functional layer212cbetween the emission layer and the second electrode213. According to an embodiment, at least one of the first functional layer212aor the second functional layer212c, the second electrode213, and the capping layer215may extend from the display area to the first non-display area NDA1. At least one of the first functional layer212aor the second functional layer212cmay extend to the first opening OP1, and may be within the first opening OP1. Also, at least one of the first functional layer212aor the second functional layer212cmay cover the middle conductive pattern MCP. At least one of the first functional layer212aor the second functional layer212cmay include a first transmission hole TAH1exposing a first upper surface ILUS1of the first insulating layer IL1and/or a second upper surface MILUS of the middle insulating layer MIL. The second electrode213may include a second transmission hole TAH2exposing the first upper surface ILUS1of the first insulating layer IL1and/or the second upper surface MILUS of the middle insulating layer MIL. The capping layer215may include a third transmission hole TAH3exposing the first upper surface ILUS1of the first insulating layer IL1and/or the second upper surface MILUS of the middle insulating layer MIL. According to an embodiment, the second transmission hole TAH2and the third transmission hole TAH3may expose the middle conductive pattern MCP. The area of the first transmission hole TAH1may be less than the area of the second transmission hole TAH2and/or the area of the third transmission hole TAH3. That is, at least one end portion of the first functional layer212aand the second functional layer212cmay be closer to the opening area OA than the end portions of the second electrode213and the capping layer215. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may cover the first opening OP1, and may extend in a direction from the first non-display area NDA1to the opening area OA. In this case, the first inorganic encapsulation layer310may come in contact with the second upper surface MILUS of the middle insulating layer MIL. In this case, a passage through which a foreign material or moisture infiltrates into the organic light-emitting diode through at least one of the first functional layer212aor the second functional layer212cmay be formed to be long. Therefore, it is possible to prevent or reduce infiltration of a foreign material or moisture into the organic light-emitting diode. FIGS.13A-13Care schematic cross-sectional views illustrating a method of manufacturing a display device, according to another embodiment. InFIGS.13A-13C, the same reference numerals as those inFIG.12refer to the same members, and redundant descriptions thereof may not be repeated. Referring toFIG.13A, a middle conductive pattern MCP overlapping a first non-display area NDA1may be formed on a first insulating layer IL1. The middle conductive pattern MCP may be formed similar to the lower pattern layer PTL1described above with reference toFIGS.9A-9G. For example, a middle conductive pattern MCP may be formed, and an upper conductive pattern may be formed on the middle conductive pattern MCP. A conductive layer may be formed on the upper conductive pattern. When the conductive layer is patterned into a first electrode211, the upper conductive pattern may be removed. According to an embodiment, the middle conductive pattern MCP and the lower pattern layer PTL1may include a same material. Also, the middle conductive pattern MCP and a first layer of the conductive pattern may include a same material. A second electrode213and at least one of a first functional layer212aor a second functional layer212cmay be formed on the middle conductive pattern MCP. According to an embodiment, a capping layer215may be further formed on the second electrode213. At least one of the first functional layer212aor the second functional layer212c, the second electrode213, and the capping layer215may be continuously formed in the first non-display area NDA1. Therefore, at least one of the first functional layer212aor the second functional layer212c, the second electrode213, and the capping layer215may cover the dam portion DP, the first opening OP1, the middle opening MILOP, the second opening OP2, the lower pattern layer PTL1, and the middle conductive pattern MCP. The second electrode213and the capping layer215on the middle conductive pattern MCP may be removed. According to an embodiment, laser light of a first energy density (J/cm2) may be irradiated on the first non-display area NDA1. The laser light of the first energy density may lift off the second electrode213and the capping layer215, but the first functional layer212a, the second functional layer212c, and the middle conductive pattern MCP may not be lifted off. Referring toFIG.13B, a second transmission hole TAH2exposing a portion of the second functional layer212cmay be formed in the second electrode213. A third transmission hole TAH3exposing a portion of the second functional layer212cmay be formed in the capping layer215. Therefore, the upper surface212US of at least one of the first functional layer212aor the second functional layer212con the middle conductive pattern MCP may be exposed. At least one of the first functional layer212aor the second functional layer212con the lower pattern layer PTL1may be removed. According to an embodiment, laser light of a second energy density (J/cm2) may be irradiated on the lower pattern layer PTL1. The second energy density may be greater than the first energy density. Therefore, the laser light of the second energy density may lift off the lower pattern layer PTL1. In this case, the lower pattern layer PTL1and at least one of the first functional layer212aor the second functional layer212con the lower pattern layer PTL1may be lifted off from the middle insulating layer MIL. Referring toFIG.13C, the first transmission hole TAH1exposing the second upper surface MILUS of the middle insulating layer MIL may be formed in the first functional layer212aand the second functional layer212c. According to an embodiment, the area of the second transmission hole TAH2and/or the third transmission hole TAH3may be greater than the area of the first transmission hole TAH1. Therefore, a passage through which a foreign material or moisture infiltrates into the organic light-emitting diode through at least one of the first functional layer212aor the second functional layer212cmay be formed to be long. FIG.14is a schematic cross-sectional view of the display panel10taken along the line VII-VII′ ofFIG.6, according to another embodiment. InFIG.14, the same reference numerals as those inFIG.7Arefer to the same members, and redundant descriptions thereof may not be repeated. The display panel10illustrated inFIG.14differs from the embodiment illustrated inFIG.7Ain that a conductive pattern CP is between a gate insulating layer112and a middle insulating layer MIL. Referring toFIG.14, the display panel10may include a substrate100, a first insulating layer IL1, a second insulating layer IL2, a conductive pattern CP, and an organic light-emitting diode OLED as a display element. The substrate100may include an opening area OA, a display area DA surrounding the opening area OA, and a first non-display area NDA1between the opening area OA and the display area DA. The first insulating layer IL1may include a first recess or a first opening OP1overlapping the first non-display area NDA1and may be on the substrate100. The second insulating layer IL2may include a second opening OP2exposing the first upper surface ILUS1of the first insulating layer IL1between the first recess or the first opening OP1and the opening area OA, and may be on the first insulating layer IL1. The middle insulating layer MIL may be between the first insulating layer IL1and the second insulating layer IL2. The middle insulating layer MIL may include a middle opening MILOP connected to the first recess or the first opening OP1. The middle opening MILOP may penetrate through the upper and lower surfaces of the middle insulating layer MIL. According to an embodiment, the middle opening MILOP may expose the first upper surface ILUS1of the first insulating layer IL1. That is, the middle insulating layer MIL may not be on the first upper surface ILUS1of the first insulating layer IL1. The conductive pattern CP may be between the gate insulating layer112and the middle insulating layer MIL, and may include a first layer L1and a second layer L2. According to an embodiment, the first layer L1may include titanium (Ti). According to another embodiment, the first layer L1may include amorphous silicon to which a dopant is added. The dopant added to the amorphous silicon (a-Si) may include one selected from boron (B), phosphorus (P), nitrogen (N), nickel (Ni), cobalt (Co), and fluorine (F). The conductive pattern CP may function as a lower electrode CE1of a storage capacitor Cst. For example, the conductive pattern CP may overlap an upper electrode CE2of the storage capacitor Cst thereon. According to an embodiment, the conductive pattern CP may function as a gate electrode GE. Therefore, the conductive pattern CP may overlap a semiconductor layer Act thereunder. The upper electrode CE2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may include a single layer or multiple layers including the above-described material. The organic light-emitting diode OLED may be arranged to overlap the display area DA on the second insulating layer IL2, and may include a first electrode211, an emission layer212bon the first electrode211, and a second electrode213on the emission layer212b. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be disconnected from the first non-display area NDA1. According to an embodiment, each of the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may include the transmission hole TAH exposing the first upper surface ILUS1of the first insulating layer IL1. An encapsulation layer ENL may cover the organic light-emitting diode OLED. A first inorganic encapsulation layer310and a second inorganic encapsulation layer330may extend from the display area DA to the first non-display area NDA1. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap the transmission hole TAH. Specifically, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap a first transmission hole TAH1, a second transmission hole TAH2, and a third transmission hole TAH3. In this case, the first inorganic encapsulation layer310may overlap the first recess or the first opening OP1, and may come in contact with the first upper surface ILUS1of the first insulating layer IL1adjacent to the opening area OA. According to an embodiment, the first inorganic encapsulation layer310may contact the second inorganic encapsulation layer330and may be between the second inorganic encapsulation layer330and the first upper surface ILUS1of the first insulating layer IL1. Therefore, because an organic material layer is not on the first upper surface ILUS1of the first insulating layer IL1, it is possible to prevent or reduce infiltration of moisture toward the organic light-emitting diode OLED arranged in the display area DA. FIGS.15A-15Care schematic cross-sectional views illustrating a method of manufacturing a display device, according to another embodiment. InFIGS.15A-15C, the same reference numerals as those inFIG.14refer to the same members, and redundant descriptions thereof may not be repeated. The embodiments illustrated inFIGS.15A-15Cdiffer from the embodiments illustrated inFIGS.9A-9Kin that a middle insulating layer MIL is formed after a conductive pattern CP and a pattern layer PTL are formed. Referring toFIG.15A, a display substrate DS may be prepared. The display substrate DS may include a substrate100and a first insulating layer IL1. The first insulating layer IL1may be on a display area DA and a first non-display area NDA1. A conductive pattern CP may be formed on the first insulating layer IL1. The conductive pattern CP may include a first layer L1and a second layer L2on the first layer L1. According to an embodiment, the conductive pattern CP may function as a gate electrode GE. In this case, the conductive pattern CP may overlap a semiconductor layer Act. A pattern layer PTL may be formed on the first non-display area NDA1. According to an embodiment, the pattern layer PTL may be formed on the first insulating layer IL1. The pattern layer PTL may include a lower pattern layer PTL1and an upper pattern layer PTL2on the lower pattern layer PTL1. The pattern layer PTL may be formed concurrently (e.g., simultaneously) with the conductive pattern CP. Referring toFIG.15B, a middle insulating layer MIL may be formed on the first insulating layer IL1. The middle insulating layer MIL may cover the pattern layer PTL and the conductive pattern CP. Therefore, the conductive pattern CP and the pattern layer PTL may be between the first insulating layer IL1and the middle insulating layer MIL. An upper electrode CE2of a storage capacitor Cst may be formed, and a second insulating layer IL2may be formed. Referring toFIG.15C, the first insulating layer IL1(e.g., the gate insulating layer112of the first insulating layer IL1), the middle insulating layer MIL, and the second insulating layer IL2may be partially removed. According to an embodiment, the first insulating layer IL1(e.g., the gate insulating layer112of the first insulating layer IL1), the middle insulating layer MIL, and the second insulating layer IL2may be partially etched. A second opening OP2may be formed in the second insulating layer IL2. The second opening OP2may expose the pattern layer PTL. The second opening OP2may expose an upper surface LUS2of the upper pattern layer PTL2. According to an embodiment, the width of the second opening OP2may be greater than the width of the pattern layer PTL. For example, the width of the second opening OP2in the x direction may be greater than the width of the pattern layer PTL in the x direction as shown inFIG.15C. A middle opening MILOP may be formed in the middle insulating layer MIL. The middle opening MILOP may be connected to the second opening OP2. Also, the middle opening MILOP may expose the pattern layer PTL. That is, the middle opening MILOP may expose the upper surface LUS2of the upper pattern layer PTL2. According to an embodiment, the width of the middle opening MILOP may be greater than the width of the pattern layer PTL. For example, the width of the middle opening MILOP in the x direction may be greater than the width of the pattern layer PTL in the x direction as shown inFIG.15C. FIG.16is a schematic cross-sectional view of the display panel10taken along the line VII-VII′ ofFIG.6, according to another embodiment. InFIG.16, the same reference numerals as those inFIG.7Arefer to the same members, and redundant descriptions thereof may not be repeated. Referring toFIG.16, the display panel10may include a substrate100, a first insulating layer11_1, a second insulating layer IL2, and an organic light-emitting diode OLED as a display element. The substrate100may include an opening area OA, a display area DA surrounding the opening area OA, and a first non-display area NDA1between the opening area OA and the display area DA. An upper electrode CE2may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may include a single layer or multiple layers including the above-described material. The second insulating layer IL2may include a recess R, which is concave in the depth or thickness direction (e.g., the direction opposite to the z direction) of the second insulating layer IL2, on a second sub-non-display area SNDA2. The recess R may be defined by a bottom surface, a first sidewall RW1, and a second sidewall RW2, which are connected to each other. According to an embodiment, the bottom surface, the first sidewall RW1, and the second sidewall RW2of the recess R may be portions of the second insulating layer IL2. The bottom surface of the recess R may be a surface arranged below the upper surface (e.g., uppermost surface) of the second insulating layer IL2. The first sidewall RW1and the second sidewall RW2may connect the upper surface of the second insulating layer IL2and the bottom surface (e.g., the bottom surface of the recess R or the surface arranged below the upper surface of the second insulating layer IL2). The first sidewall RW1and the second sidewall RW2may be surfaces of the second insulating layer IL2facing each other (e.g., facing each other in the x direction). The first sidewall RW1may be closer to the display area DA than the second sidewall RW2. According to an embodiment, the recess R may be between the first organic insulating layer115and the opening area OA. According to an embodiment, the first sidewall RW1of the recess R may meet a side surface115AS of the first organic insulating layer115. For example, the first sidewall RW1of the recess R and the side surface115AS of the first organic insulating layer115may be continuously arranged. According to an embodiment, the first sidewall RW1of the recess R and the side surface115AS of the first organic insulating layer115may intersect with each other, or may be on the same plane. According to an embodiment, the first sidewall RW1of the recess R and the side surface115AS of the first organic insulating layer115may be aligned. According to an embodiment, the second insulating layer IL2may include at least one recess R. For example, the second insulating layer IL2may include one recess R. As another example, the second insulating layer IL2may include a plurality of recesses R. A dam portion DP may be within the recess R. The dam portion DP may be on the bottom surface of the recess R, and the dam portion DP may include an organic pattern layer116A. A sidewall116AW (e.g., a portion of the sidewall116AW) of the organic pattern layer116A may face the second sidewall RW2of the recess R. According to an embodiment, the second sidewall RW2of the recess R, at least a portion of the bottom surface of the recess R, and the sidewall116AW of the organic pattern layer116A may define a concave portion CVP. The concave portion CVP may be defined between (e.g., between in the x direction) the opening area OA and the dam portion DP. A first functional layer212a, a second functional layer212c, a second electrode213, and a capping layer215may extend from the display area DA to the first non-display area NDA1. According to an embodiment, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may cover the dam portion DP, and may extend to the concave portion CVP. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be disconnected from the second sidewall RW2of the recess R. According to an embodiment, each of the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may include a transmission hole TAH exposing a second upper surface ILUS2of the second insulating layer IL2. The second upper surface ILUS2of the second insulating layer IL2may be the upper surface of the second insulating layer IL2between the opening area OA and the concave portion CVP. At least one of the first functional layer212aor the second functional layer212cmay include a first transmission hole TAH1exposing the second upper surface ILUS2of the second insulating layer IL2. The second electrode213may include a second transmission hole TAH2exposing the second upper surface ILUS2of the second insulating layer IL2. The capping layer215may include a third transmission hole TAH3exposing the second upper surface ILUS2of the second insulating layer IL2. The area of the transmission hole TAH may be greater than the area of the opening area OA. The end of the transmission hole TAH may be arranged at the end of the concave portion CVP at which the dam portion DP is not arranged. According to an embodiment, by forming the first transmission hole TAH1based on the concave portion CVP, it may be possible to prevent or reduce infiltration of a foreign material or moisture into the organic light-emitting diode OLED by at least one of the first functional layer212aor the second functional layer212c. An encapsulation layer ENL may cover the organic light-emitting diode OLED. A first inorganic encapsulation layer310and a second inorganic encapsulation layer330may extend from the display area DA to the first non-display area NDA1. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap the transmission hole TAH. Specifically, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may overlap the first transmission hole TAH1, the second transmission hole TAH2, and the third transmission hole TAH3. In this case, the first inorganic encapsulation layer310may overlap the concave portion CVP, and may come in contact with the second upper surface ILUS2of the second insulating layer IL2adjacent to the opening area OA. According to an embodiment, the first inorganic encapsulation layer310may contact the second inorganic encapsulation layer330and may be between the second inorganic encapsulation layer330and the second upper surface ILUS2of the second insulating layer IL2. Therefore, because an organic material layer is not on the second upper surface ILUS2of the second insulating layer IL2, it is possible to prevent or reduce infiltration of moisture toward the organic light-emitting diode OLED arranged in the display area DA. FIGS.17A-17Eare schematic cross-sectional views illustrating a method of manufacturing a display device, according to another embodiment. The embodiments illustrated inFIGS.17A-17Cdiffer from the embodiments illustrated inFIGS.9A-9Kin that a pattern layer and a connection electrode are formed in the same process. Referring toFIG.17A, a display substrate DS may be prepared. The display substrate DS may include a substrate100, a first insulating layer IL1, a middle insulating layer MIL, a second insulating layer IL2, a pixel circuit PC, a portion of a data line DL, and a first organic insulating layer115. According to an embodiment, the first insulating layer IL1, the middle insulating layer MIL, and the second insulating layer IL2may be continuously arranged in a display area DA and a first non-display area NDA1. A connection conductive layer CML may be formed on the display substrate DS. The connection conductive layer CML may be continuously formed in the first non-display area NDA1and the display area DA. The connection conductive layer CML may be connected to a drain electrode DE or a source electrode SE through a contact hole provided in the first organic insulating layer115. Referring toFIG.17B, the connection conductive layer CML is patterned to form the connection electrode CM and other portions of the data line DL, and the pattern layer PTL-1. In this case, the pattern layer PTL-1and the connection electrode CM may be formed concurrently (e.g., simultaneously) and may include a same material. The pattern layer PTL-1may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and/or the like, and may be formed as a single layer or multiple layers including the above-described material. According to an embodiment, the pattern layer PTL-1may have a multiple layer structure of Ti/Al/Ti. When the pattern layer PTL-1and the connection electrode CM are formed, the second insulating layer IL2is over-etched to form a recess R. The recess R may be formed to be concave in the depth or thickness direction of the second insulating layer IL2. The recess R may be formed between the pattern layer PTL-1and the first organic insulating layer115. The recess R may be defined by a bottom surface, a first sidewall RW1, and a second sidewall RW2. The first sidewall RW1of the recess R may meet a side surface115AS of the first organic insulating layer115. According to an embodiment, the first sidewall RW1of the recess R and the side surface115AS of the first organic insulating layer115may be aligned. The second sidewall RW2of the recess R may meet the sidewall of the pattern layer PTL-1. The recess R may be configured to facilitate disconnection of an organic material layer to be described in more detail below. Referring toFIG.17C, an organic pattern layer116A and a second organic insulating layer116may be formed. The organic pattern layer116A may be formed within the recess R. The organic pattern layer116A and the second organic insulating layer116may be formed by applying an organic material onto the entire resulting structure and performing a photocuring process and a patterning process thereon. The second sidewall RW2of the recess R, at least a portion of the bottom surface of the recess R, and the sidewall116AW of the organic pattern layer116A may define a concave portion CVP. The sidewall116AW of the organic pattern layer116A may face the second sidewall RW2of the recess R. The concave portion CVP may be defined between the pattern layer PTL-1and the organic pattern layer116A. The concave portion CVP may be configured to facilitate disconnection of an organic material layer to be described in more detail below. A first electrode211may be formed on the second organic insulating layer116. The first electrode211may be formed by forming a conductive layer on an entire display substrate DS and patterning the conductive layer. Referring toFIG.17D, a pixel defining layer118including an opening1180P exposing the central portion of the first electrode211may be formed on the first electrode211, and a spacer119may be formed on the pixel defining layer118. A first upper organic pattern layer118A and a second upper organic pattern layer119A may be formed on the organic pattern layer116A. According to an embodiment, the first upper organic pattern layer118A may be formed concurrently (e.g., simultaneously) with the pixel defining layer118. According to an embodiment, the second upper organic pattern layer119A may be formed concurrently (e.g., simultaneously) with the spacer119. A second electrode213and at least one of a first functional layer212aor a second functional layer212cmay be formed. Specifically, the first functional layer212a, an emission layer212b, the second functional layer212c, the second electrode213, and a capping layer215may be sequentially formed on the entire substrate100. The emission layer212bmay overlap the first electrode211. The first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be stacked (e.g., sequentially stacked) on the pattern layer PTL-1. The second electrode213and at least one of the first functional layer212aor the second functional layer212con the pattern layer PTL-1may be removed. According to an embodiment, laser light may be irradiated on the pattern layer PTL-1. Specifically, laser light may be irradiated on the pattern layer PTL-1from below the substrate100. Because the pattern layer PTL-1includes an opaque metal, the pattern layer PTL-1may absorb the laser light. According to an embodiment, at least a portion of the pattern layer PTL-1may be thermally expanded and lifted off from the second insulating layer IL2. Referring toFIG.17E, the first functional layer212a, the second functional layer212c, the second electrode213, and the capping layer215may be lifted off together with the pattern layer PTL-1. Therefore, a first transmission hole TAH1exposing the second upper surface ILUS2of the second insulating layer IL2may be formed in the first functional layer212aand the second functional layer212c. A second transmission hole TAH2exposing the second upper surface ILUS2of the second insulating layer IL2may be formed in the second electrode213. A third transmission hole TAH3exposing the second upper surface ILUS2of the second insulating layer IL2may be formed in the capping layer215. As described above, according to embodiments, because the organic material layer around the opening may be removed by the laser lift-off process, it is possible to prevent or substantially prevent the display elements from being damaged by a foreign material or external moisture. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, and equivalents thereof. | 120,877 |
11943970 | DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the attached drawings. Note, the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but limitation is not made an invention that requires all such features, and multiple such features may be combined as appropriate. Furthermore, in the attached drawings, the same reference numerals are given to the same or similar configurations, and redundant description thereof is omitted. The structure of a light emitting device according to the first embodiment of the present invention will be described with reference toFIGS.1to5.FIG.1is a view showing an example of the arrangement of a light emitting device101according to this embodiment.FIG.2is a circuit diagram showing an example of the arrangement of one pixel102of the light emitting device101shown inFIG.1.FIG.3is a circuit diagram showing the connection relationship between two adjacent pixels102. In this specification, a case will be described in which a driving transistor202is connected to the anode of a light emitting element201and all transistors arranged in the pixel102are p-type transistors. However, the arrangement of the light emitting device101is not limited to this. The polarity of the light emitting element201and the conductivity types of the transistors arranged in the pixel102may all be reversed. Alternatively, for example, the driving transistor202may be a p-type transistor and the remaining transistors may be n-type transistors. Supplied potentials and connection are changed appropriately in accordance with the polarity and conductive types so that the light emitting element201emits light in a predetermined light amount. Therefore, for example, the “drain region” and “source region” of each transistor may be reversed. As shown inFIG.1, an organic EL light emitting device as an example of the light emitting device101includes a pixel array portion103and a driving unit arranged in the periphery of the pixel array portion103. In the pixel array portion103, the plurality of pixels102are arranged on a substrate in an array in an X direction and a Y direction intersecting the X direction, as shown inFIG.1. As shown inFIG.1, the X and Y directions may be orthogonal to each other. As shown inFIG.2, each pixel102includes the light emitting element201. The light emitting element201includes an organic layer with a light emitting layer between the anode and the cathode. The organic layer may appropriately include one or more of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer in addition to the light emitting layer. The driving unit is a circuit for driving each pixel102. For example, the driving unit includes a vertical scanning circuit104and a signal output circuit105. In the pixel array portion103, a scanning line106is arranged for each pixel row in a row direction (the Y direction inFIG.1). In the pixel array portion103, a signal line107is arranged for each pixel column in a column direction (the X direction inFIG.1). Each scanning line106is connected to the output terminal of a corresponding row of the vertical scanning circuit104. Each signal line107is connected to the output terminal of a corresponding column of the signal output circuit105. The vertical scanning circuit104supplies a write control signal to the scanning line106at the time of writing a video signal in each pixel102of the pixel array portion103. The signal output circuit105outputs a luminance signal with a voltage corresponding to luminance information. As shown inFIG.2, each pixel102includes the light emitting element201, the driving transistor202, and a write transistor203. More specifically, one (a drain region in the arrangement shown inFIG.2) of the two main terminals of the driving transistor202is connected to the anode of the two electrodes of the light emitting element201. The other (a source region in the arrangement shown inFIG.2) of the two main terminals of the driving transistor202is connected to a power supply potential Vdd. The cathode of the two electrodes of the light emitting element201is connected to a power supply potential Vss. The power supply potential Vss may be, for example, a ground potential. The main terminal of the transistor indicates a diffusion region functioning as the source or drain region of the transistor. The control terminal of the transistor indicates the gate electrode of the transistor. One (a drain region in the arrangement shown inFIG.2) of the two main terminals of the write transistor203is connected to the control terminal (gate electrode) of the driving transistor202. The other (a source region in the arrangement shown inFIG.2) of the two main terminals of the write transistor203is connected to the signal line107. The gate electrode of the write transistor203is connected to the scanning line106. The total number of transistors, the total number of capacitive elements (to be described later), and a combination of the conductivity types of the transistors are merely examples, and the present invention is not limited to this arrangement. In the following description, when a transistor is connected between elements A and B, one of the main terminals of the transistor is connected to element A and the other of the main terminals of the transistor is connected to element B. That is, when a transistor is connected between elements A and B, a case in which the control terminal of the transistor is connected to element A, one of the main terminals is not connected to element A, and the other of the main terminals is not connected to element B is excluded. The driving transistor202supplies a current from the power supply potential Vdd to the light emitting element201, thereby causing the light emitting element201to emit light. More specifically, the driving transistor202supplies a current corresponding to the signal voltage of the signal line107to the light emitting element201. This current-drives the light emitting element201to emit light. The write transistor203is rendered conductive in response to a write control signal applied to the gate electrode of the write transistor203from the vertical scanning circuit104via the scanning line106. Thus, the write transistor203writes, in the pixel102, the signal voltage of a video signal corresponding to luminance information supplied from the signal output circuit105via the signal line107. The written signal voltage is applied to the gate electrode of the driving transistor202. An organic EL (Organic Electroluminescent) element can be used as the light emitting element201. When the light emitting element201emits light, the amount of a current flowing through the driving transistor202changes in accordance with the signal voltage applied to the gate electrode of the driving transistor202from the signal line107via the write transistor203. This charges the capacitance between the anode and the cathode of the light emitting element201to a predetermined potential, and a current corresponding to the potential difference flows. Thus, the light emitting element201emits light with predetermined luminance. Next, the two adjacent pixels102will be described with reference toFIG.3. As shown inFIG.3, the plurality of pixels102arranged in the pixel array portion103include pixels102aand102badjacent to each other in the X direction. When indicating a specific one of the pixels102, a suffix such as “a” or “b” is appended to a reference numeral like “pixel102“a””. When any pixel is possible without specifying it, “pixel102” is simply used. The same applies to the remaining components. The pixel102aincludes a light emitting element201a, a driving transistor202a, and a write transistor203a. The pixel102bincludes a light emitting element201b, a driving transistor202b, and a write transistor203b. The source region of the write transistor203aof the pixel102aand the source region of the write transistor203bof the pixel102bare connected via the signal line107. In this way, the two pixels102aand102bin which the source regions of the write transistors203are connected to each other form one pixel group301. FIG.4shows an example of the arrangement of the transistors of the circuit shown inFIG.3.FIG.4shows four pixel groups301each formed by the pixels102aand102b. In each pixel group301, the write transistor203aof the pixel102aand the write transistor203bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102b. The write transistor203aincludes a p-type diffusion region401, a gate electrode402a, and a p-type diffusion region403a. The write transistor203bincludes the p-type diffusion region401, a gate electrode402b, and a p-type diffusion region403b. As shown inFIG.4, the write transistors203aand203bshare the diffusion region401connected to the signal line107. In other words, the source region of the write transistor203aof the pixel102aand the source region of the write transistor203bof the pixel102bshare one diffusion region401. This makes it possible to miniaturize the pixels102(pixel groups301), as compared with a case in which a diffusion region forming the source region of the write transistor203aand a diffusion region forming the source region of the write transistor203bare separately arranged in the X direction. The driving transistor202aof the pixel102aincludes a p-type diffusion region404a, a gate electrode405a, and a p-type diffusion region406a. The diffusion region404ais connected to the power supply potential Vdd to function as the source region of the driving transistor202a. The diffusion region406ais connected to the anode of the light emitting element201ato function as the drain region of the driving transistor202a. The driving transistor202bof the pixel102bincludes a p-type diffusion region404b, a gate electrode405b, and a p-type diffusion region406b. The diffusion region404bis connected to the power supply potential Vdd to function as the source region of the driving transistor202b. The diffusion region406bis connected to the anode of the light emitting element201bto function as the drain region of the driving transistor202b. As described above, the source region (diffusion region404a), the gate electrode405a, and the drain region (diffusion region406a) of the driving transistor202aof the pixel102aand the source region (diffusion region404b), the gate electrode405b, and the drain region (diffusion region406b) of the driving transistor202bof the pixel102bare sequentially arranged in the positive X direction. That is, a direction in which a current flows from the power supply potential Vdd to the power supply potential Vss through the driving transistor202and the light emitting element201is the same between the pixels102aand102b. The positive direction corresponds to a direction indicated by an arrow as the X direction inFIG.4. Although the source region, gate electrode, and drain region of each of the driving transistors202aand202bof the pixels102aand102bare sequentially arranged in the positive X direction inFIG.4, the present invention is not limited to this. For example, the source region, gate electrode, and drain region of each of the driving transistors202aand202bmay be arranged in the negative X direction. As miniaturization of the pixel102(pixel group301) advances, the positional relationship between the diffusion region and the gate electrode may deviate from design due to alignment accuracy of a mask pattern at the time of forming the pixel. If the positional relationship between the diffusion region and the gate electrode deviates, the electrical characteristic of the formed transistor may change from a design value. In addition, as transistor miniaturizing advances, the influence when the positional relationship between the diffusion region and the gate electrode deviates may become conspicuous. The positional relationship between the diffusion region and the gate electrode may deviate in the same direction among transistors formed with the same exposure. At this time, consider a case in which currents flow in the opposite directions in the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102b. In this case, since the positional relationship between the diffusion region and the gate electrode deviates in the same direction, if a current larger than a design value flows through the driving transistor202a, a current flowing through the driving transistor202bmay become smaller than a design value. Therefore, a luminance unevenness may occur between the pixels102aand102b, thereby degrading the display image quality. On the other hand, in this embodiment, the directions of currents for causing the light emitting elements201to emit light, which flow through the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102b, are the same. Therefore, if a current larger than the design value flows through the driving transistor202a, a current larger than the design value also flows through the driving transistor202b. Thus, in the light emitting device101according to this embodiment, a difference in electrical characteristic of the driving transistor202between the pixels102can be reduced, thereby suppressing degradation in display image quality. For example, in all the pixels102arranged in the pixel array portion103of the light emitting device101, the source regions, gate electrodes, and drain regions of the driving transistors202may be arranged in the same direction. FIG.5is a sectional view of the pixel group301shown inFIG.4, which is taken along a line Y1-Y1′. The light emitting element201includes an electrode501(to also be referred to as a lower electrode hereinafter), an organic layer502including a light emitting layer, and an electrode503(to also be referred to as an upper electrode hereinafter). The electrode501is arranged for each light emitting element201. As shown inFIG.5, an electrode501ais arranged in the light emitting element201a, and an electrode501bis arranged in the light emitting element201b. The organic layer502and the electrode503can be shared by the plurality of light emitting elements201. For example, the light emitting element201of all the pixels102arranged in the pixel array portion103may share the organic layer502and the electrode503. As shown inFIG.5, a bank portion504may be arranged in an end portion of the electrode501. The bank portion504can be arranged to surround the outer circumference of the electrode501. The bank portion504can reduce leakage of a current flowing between the electrode501aand the electrode503into the adjacent pixel102. The electrode501and the diffusion region406functioning as the source region of the driving transistor202are connected via a via505and a wiring layer506. Each transistor described above is formed on a substrate510. The substrate510can be a semiconductor substrate of, for example, p-type doped silicon. An n-type well layer507is arranged on a p-type semiconductor layer509of the substrate510, and the diffusion regions401,403,404, and406are formed in the well layer507. The well layer507is connected to the power supply potential Vdd. Each transistor is separated by an insulator isolation portion508. The insulator isolation portion508electrically isolates each transistor by an appropriate method such as STI (Shallow Trench Isolation), LOCOS (Local Oxidation Of Silicon), or n-type diffusion region isolation. FIG.5shows only one wiring layer506between the diffusion regions401,403,404, and406and the layer in which the electrodes501are arranged. The present invention, however, is not limited to this, and a plurality of wiring layers may be arranged. In this case, the diffusion regions401,403,404, and406may be respectively connected to wiring patterns arranged in different wiring layers or wiring patterns arranged in the same wiring layer. The structure of a light emitting device according to the second embodiment of the present invention will be described with reference toFIGS.6to13. In this embodiment, as compared with the above-described first embodiment, a light emission control transistor is connected between a power supply potential Vdd and a driving transistor202. Components different from the above-described first embodiment will mainly be described below. FIG.6is a view showing an example of the arrangement of a light emitting device101according to this embodiment. As shown inFIG.6, in a pixel array portion103, a scanning line601is arranged for each pixel row in the Y direction in addition to the above-described first embodiment. Each scanning line601is connected to the output terminal of a corresponding row of a vertical scanning circuit104, and supplies a light emission control signal to each pixel102. FIG.7is a circuit diagram showing an example of the arrangement of one pixel102of the light emitting device101shown inFIG.6. As shown inFIG.7, a light emission control transistor701is connected between the power supply potential Vdd and the driving transistor202in addition to the above-described first embodiment. One (a drain region in the arrangement shown inFIG.7) of the two main terminals of the light emission control transistor701is connected to one (a source region in the arrangement shown inFIG.7) of the two main terminals of the driving transistor202. The other (a source region in the arrangement shown inFIG.7) of the two main terminals of the light emission control transistor701is connected to the power supply potential Vdd. The control terminal (gate electrode) of the light emission control transistor701is connected to the scanning line601. Furthermore, a capacitive element702is connected between the gate electrode and the source electrode of the driving transistor202, and a capacitive element703is connected between the power supply potential Vdd and the source electrode of the driving transistor202. The light emission control transistor701is rendered conductive in response to the light emission control signal applied from the vertical scanning circuit104to the gate electrode via the scanning line601, thereby allowing a current to be supplied from the power supply potential Vdd to the driving transistor202. This allows the driving transistor202to drive a light emitting element201. That is, by controlling the conductive state of the current path, the light emission control transistor701functions as a switch element that controls light emission or non-light emission of the light emitting element201. As described above, a switching operation of the light emission control transistor701can provide a period (non-emission period) during which the light emitting element201is in a non-emission state, and control the ratio between the non-emission period and an emission period during which the light-emitting element201emits light (so-called duty control). This duty control can reduce afterimage blurring accompanying light emission from the light emitting element201of each pixel102over a period of one frame, and further improve the image quality of a moving image in particular. FIG.8is a circuit diagram showing the connection relationship between two adjacent pixels102. As shown inFIG.8, the plurality of pixels102arranged in the pixel array portion103include pixels102aand102badjacent to each other in the X direction. Similar to the above-described first embodiment, the source region of a write transistor203aof the pixel102aand the source region of a write transistor203bof the pixel102bare connected via the signal line107to form one pixel group801. The pixel102aincludes a light emission control transistor701a, a capacitive element702a, and a capacitive element703a, in addition to the pixel102aaccording to the first embodiment. The pixel102bincludes a light emission control transistor701b, a capacitive element702b, and a capacitive element703b, in addition to the pixel102baccording to the first embodiment. FIG.9shows an example of the arrangement of the transistors of the circuit shown inFIG.8.FIG.9shows four pixel groups801each formed by the pixels102aand102b. In each pixel group801, the write transistor203aof the pixel102aand the write transistor203bof the pixel102bare arranged between a driving transistor202aof the pixel102aand a driving transistor202bof the pixel102b. In addition, the light emission control transistor701aof the pixel102ais arranged between the driving transistor202aand the write transistor203aof the pixel102ain the X direction. The light emission control transistor701bof the pixel102bis arranged on the side, opposite to the pixel102a, of the driving transistor202bof the pixel102bin the X direction. As shown inFIG.9, the light emission control transistor701aincludes a p-type diffusion region901a, a gate electrode902a, and a p-type diffusion region404a. The diffusion region901ais connected to the power supply potential Vdd to function as the source region of the light emission control transistor701a. The drain region of the light emission control transistor701aand the source region of the driving transistor202ashare one diffusion region404a. This can miniaturize the pixel102(pixel group801), as compared with a case in which the diffusion region forming the drain region of the light emission control transistor701aand the diffusion region forming the source region of the driving transistor202aare separately arranged in the X direction. Similarly, the light emission control transistor701bincludes a p-type diffusion region901b, a gate electrode902b, and a p-type diffusion region404b. The diffusion region901bis connected to the power supply potential Vdd to function as the source region of the light emission control transistor701b. The drain region of the light emission control transistor701band the source region of the driving transistor202bshare one diffusion region404b. In this embodiment as well, the source region (diffusion region404a), a gate electrode405a, and the drain region (diffusion region406a) of the driving transistor202aof the pixel102aand the source region (diffusion region404b), a gate electrode405b, and the drain region (diffusion region406b) of the driving transistor202bof the pixel102bare sequentially arranged in the positive X direction. Thus, similar to the above-described first embodiment, in the light emitting device101, a difference in electrical characteristic of the driving transistor202between the pixels102can be reduced, thereby suppressing degradation in display image quality. Furthermore, in this embodiment, the source region (diffusion region901a), the gate electrode902a, the drain region (diffusion region404a) of the light emission control transistor701aof the pixel102aand the source region (diffusion region901b), the gate electrode902b, and the drain region (diffusion region404b) of the light emission control transistor701bof the pixel102bare sequentially arranged in the positive X direction. Thus, in the light emitting device101, a difference in electrical characteristic of the light emission control transistor701between the pixels102can be reduced, thereby suppressing degradation in display image quality. As shown inFIG.9, in the pixel102, the arrangement order of the source region, gate electrode, and drain region of the driving transistor202in the positive X direction may be the same as that of the source region, gate electrode, and drain region of the light emission control transistor701. For example, with respect to each of the light emission control transistors701aand701b, the source region, gate electrode, and drain region may be arranged in this order in the negative X direction. In this embodiment, the light emission control transistor701aof the pixel102aand the light emission control transistor701bof the pixel102bare arranged so that currents flow in the same direction. However, the present invention is not limited to this, and currents need not flow in the same direction. For example, the light emission control transistor701aarranged in the pixel102aand the light emission control transistor701barranged in the pixel102bmay be designed so that currents flow in the opposite directions. This is implemented when the driving transistor202causes a current to flow in response to a luminance signal with a voltage corresponding to luminance information while the light emission control transistor701controls light emission or non-light emission of the light emitting element201. Thus, the control accuracy of the light emission control transistor701may be lower than that of the driving transistor202. Therefore, in accordance with the arrangement of the pixels102and the pixel groups801, the flow direction of a current in each light emission control transistor701may be decided appropriately. Next, a wiring pattern903for connecting the gate electrode405of the driving transistor202and the diffusion region403forming the drain region of the write transistor will be described. In the above-described first embodiment, as shown inFIG.4, the distance between the gate electrode405of the driving transistor202and the diffusion region403forming the drain region of the write transistor is almost the same. Therefore, the length of the wiring pattern903is almost the same between the pixels102aand102b, and the parasitic capacitance of the wiring pattern903is almost the same between the pixels102aand102b. On the other hand, in the arrangement shown inFIG.9, the distance between the gate electrode405of the driving transistor202and the diffusion region403forming the drain region of the write transistor is different between the pixels102aand102b. A wiring pattern indicates a conductor wiring for electrically connecting two or more target objects. A wiring of the same shape need not always be used repeatedly. A wiring pattern903ais a wiring pattern for connecting the gate electrode405aof the driving transistor202aand the diffusion region403aforming the drain region of the write transistor203a. A wiring pattern903bis a wiring pattern for connecting the gate electrode405bof the driving transistor202band the diffusion region403bforming the drain region of the write transistor203b. A length904ais a length between the gate electrode405aof the driving transistor202aand the contact portion of the diffusion region403aforming the drain region of the write transistor203a. Similarly, a length904bis a length between the gate electrode405bof the driving transistor202band the contact portion of the diffusion region403bforming the drain region of the write transistor203b. A length905ais the length of a portion where the wiring pattern903aoverlaps the gate electrode405aof the driving transistor202a. Similarly, a length905bis the length of a portion where the wiring pattern903boverlaps the gate electrode405bof the driving transistor202b. In the arrangement shown inFIG.9, the length904aof the pixel102ais longer than the length904bof the pixel102b. To the contrary, the length905aof the pixel102ais shorter than the length905bof the pixel102b. This can increase the parasitic capacitance of the wiring pattern903bto be almost equal to the parasitic capacitance of the wiring pattern903a. As a result, the gate-source capacitance of the driving transistor202afor holding a voltage corresponding to luminance information is almost equal to that of the driving transistor202b, thereby reducing the difference in electrical characteristic between the pixels102aand102b. This can reduce a luminance unevenness between the pixels102aand102b, thereby suppressing degradation in display image quality. In the arrangement shown inFIG.9, the length904ais longer than the length904b, and thus the length905ais shorter than the length905b. However, if the length904ais shorter than the length904b, the length905ais made longer than the length905b. As shown inFIG.9, the wiring pattern903is arranged in the X direction on the gate electrode405. However, the wiring pattern903may be arranged to bend from the X direction to the Y direction. Furthermore, as shown inFIG.9, the wiring pattern903bmay extend from the gate electrode405bon the side opposite to the pixel102a. FIG.10is a sectional view of the pixel group801shown inFIG.9, which is taken along a line Y2-Y2′. As shown inFIG.10, an electrode501and a diffusion region406forming the source region of the driving transistor202are connected via a via505and wiring layers506,1001, and1002. The capacitive element702has a structure that includes an insulating layer between an electrode1003arranged in the wiring layer1001and an electrode1004. The capacitive element703has a structure that includes an insulating film between an electrode1005arranged in the wiring layer1002and an electrode1006. However, the arrangement of the pixel group801is not limited to this. For example, a wiring layer may be arranged in addition to the wiring layers506,1001, and1002, a wiring layer including the electrode1004, and a wiring layer including the electrode1006. The arrangements of the capacitive elements702and703are not limited to them, and an electrode may be formed in another wiring layer. FIG.11shows a modification of the wiring pattern903shown inFIG.9. As described above, the length904aof the pixel102ais longer than the length904bof the pixel102b. To the contrary, in the arrangement shown inFIG.11, an area in the pixel102awhere the wiring pattern903aoverlaps the gate electrode405aof the driving transistor202ais smaller than an area in the pixel102bwhere the wiring pattern903boverlaps the gate electrode405bof the driving transistor202b. To implement this, the width of a portion, extending in the X direction, of the wiring pattern903aof the pixel102amay be smaller than the width of a portion, extending in the X direction, of the wiring pattern903bof the pixel102b. This can increase the parasitic capacitance of the wiring pattern903bto be almost equal to the parasitic capacitance of the wiring pattern903a. As a result, the gate-source capacitance of the driving transistor202afor holding a voltage corresponding to luminance information is almost equal to that of the driving transistor202b, thereby reducing the difference in electrical characteristic between the pixels102aand102b. Thus, in the arrangement shown inFIG.11as well, it is possible to reduce a luminance unevenness between the pixels102aand102b, thereby suppressing degradation in display image quality. In the arrangement shown inFIG.11, since the length904ais longer than the length904b, an area where the wiring pattern903aand the gate electrode405aoverlap each other is smaller than an area where the wiring pattern903band the gate electrode405boverlap each other. On the other hand, if the length904ais shorter than the length904b, the area where the wiring pattern903aand the gate electrode405aoverlap each other is made larger than the area where the wiring pattern903band the gate electrode405boverlap each other. In this case, the width of a portion, extending in the X direction, of the wiring pattern903a of the pixel102amay be larger than that of a portion, extending in the X direction, of the wiring pattern903bof the pixel102b. FIG.12shows another modification of the wiring pattern903shown inFIG.9or11. The portion, extending in the X direction, of the wiring pattern903aof the pixel102aincludes a portion1202aof a length1201aarranged on the side of the pixel102bwith respect to a portion extending in the Y direction. Similarly, the portion, extending in the X direction, of the wiring pattern903bof the pixel102bincludes a portion1202bof a length1201barranged on the side of the pixel102awith respect to a portion extending in the Y direction. As described above, the length904aof the pixel102ais longer than the length904bof the pixel102b. To the contrary, in the arrangement shown inFIG.12, the length1201aof the portion1202ais shorter than the length1201bof the portion1202b. This can increase the parasitic capacitance of the wiring pattern903bto be almost equal to the parasitic capacitance of the wiring pattern903a. As a result, the gate-source capacitance of the driving transistor202afor holding a voltage corresponding to luminance information is almost equal to that of the driving transistor202b, thereby reducing the difference in electrical characteristic between the pixels102aand102b. Thus, in the arrangement shown inFIG.12as well, it is possible to reduce a luminance unevenness between the pixels102aand102b, thereby suppressing degradation in display image quality. In the arrangement shown inFIG.12, since the length904ais longer than the length904b, the length1201ais shorter than the length1201b. However, if the length904ais shorter than the length904b, the length1201ais made longer than the length1201b. As shown inFIG.12, the portion1202of the wiring pattern903extends in the X direction. The present invention, however, is not limited to this. The portion1202of the wiring pattern903may be arranged to bend from the X direction to the Y direction, or a portion extending in the Y direction of the wiring pattern903shown inFIG.12may be extended to one or both sides in the Y direction, and may be adjusted in length. For example, the portion extending in the Y direction of the wiring pattern903may protrude rightward inFIG.12from the portion extending in the X direction. FIG.13shows a modification of the arrangement of the transistors shown inFIG.9. In each pixel group801, the write transistor203aof the pixel102aand the write transistor203bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102b. Furthermore, the light emission control transistor701aof the pixel102aand the light emission control transistor701bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102bin the X direction. The source region of the light emission control transistor701aof the pixel102aand the source region of the light emission control transistor701bof the pixel102bshare one diffusion region1301. The write transistors203aand203bof the pixels102aand102band the light emission control transistors701aand701bof the pixels102aand102bare arranged side by side in the Y direction. The write transistors203aand203bof the pixels102aand102band the light emission control transistors701aand701bof the pixels102aand102bmay be reversed, as compared with the arrangement shown inFIG.13. As shown inFIG.13, the light emission control transistor701aincludes the p-type diffusion region1301, a gate electrode902a, and a p-type diffusion region1302a. Similarly, the light emission control transistor701bincludes the p-type diffusion region1301, a gate electrode902b, and a p-type diffusion region1302b. As shown inFIG.13, the source region of the light emission control transistor701aand the source region of the light emission control transistor701bshare one diffusion region1301connected to the power supply potential Vdd. This can miniaturize the pixels102(pixel groups801), as compared with a case in which the diffusion region forming the source region of the light emission control transistor701aand the diffusion region forming the source region of the light emission control transistor701bare separately arranged in the X direction. The structure of a light emitting device according to the third embodiment of the present invention will be described with reference toFIGS.14to22. In this embodiment, as compared with the above-described first and second embodiments, a reset transistor is connected between the anode of a light emitting element201and a power supply potential Vss. Components different from the above-described first and second embodiments will mainly be described below. FIG.14is a view showing an example of the arrangement of a light emitting device101according to this embodiment. As shown inFIG.14, in a pixel array portion103, a scanning line1401is arranged for each pixel row in the Y direction in addition to the above-described first and second embodiments. Each scanning line1401is connected to the output terminal of a corresponding row of a vertical scanning circuit104, and supplies a reset signal to each pixel102. FIG.15is a circuit diagram showing an example of the arrangement of one pixel102of the light emitting device101shown inFIG.14. As shown inFIG.15, a reset transistor1501is connected between the anode of the light emitting element201(the drain of a driving transistor202) and the power supply potential Vss, in addition to the above-described first and second embodiments. One (a source region in the arrangement shown inFIG.15) of the two main terminals of the reset transistor1501is connected to the anode of the light emitting element201and one (a drain region in the arrangement shown inFIG.15) of the main terminals of the driving transistor202. The other (a drain region in the arrangement shown inFIG.15) of the two main terminals of the reset transistor1501is connected to the power supply potential Vss. The control terminal (gate electrode) of the reset transistor1501is connected to the scanning line1401. When the reset transistor1501is rendered conductive during a non-light emission period, the anode of the light emitting element201is connected to the power supply potential Vss to short-circuit the two terminals of the light emitting element201. This can reset the light emitting element201(sets the light emitting element201in a non-light emission state) (reset operation). By providing the reset transistor1501in the pixel102, the light emitting element201is caused to surely perform black display during the non-light emission period, thereby implementing the light emitting device101with a high contrast ratio.FIGS.14and15show the arrangement in which a light emission control transistor701is arranged. The present invention, however, is not limited to this. For example, the light emission control transistor701need not be arranged. FIG.16is a circuit diagram showing the connection relationship between two adjacent pixels102. As shown inFIG.16, the plurality of pixels102arranged in the pixel array portion103include pixels102aand102badjacent to each other in the X direction. Similar to the above-described first and second embodiments, the source region of a write transistor203aof the pixel102aand the source region of a write transistor203bof the pixel102bare connected via a signal line107to form one pixel group1601. The pixel102aincludes a reset transistor1501a, in addition to the pixel102aaccording to the first or second embodiment. The pixel102bincludes a reset transistor1501b, in addition to the pixel102baccording to the first or second embodiment. FIG.17shows an example of the arrangement of the transistors of the circuit shown inFIG.16.FIG.17shows four pixel groups1601each formed by the pixels102aand102b. In each pixel group1601, a write transistor203aof the pixel102aand a write transistor203bof the pixel102bare arranged between a driving transistor202aof the pixel102aand a driving transistor202bof the pixel102b. In addition, a light emission control transistor701aof the pixel102aand the reset transistor1501bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102bin the X direction. The reset transistor1501aof the pixel102ais arranged on the side, opposite to the pixel102b, of the driving transistor202aof the pixel102a. The light emission control transistor701bof the pixel102bis arranged on the side, opposite to the pixel102a, of the driving transistor202bof the pixel102b. In the arrangement shown inFIG.17, the write transistors203aand203bof the pixels102aand102band the light emission control transistor701aof the pixel102aand the reset transistor1501bof the pixel102bare arranged side by side in the Y direction. The write transistors203aand203bof the pixels102aand102band the light emission control transistor701aof the pixel102aand the reset transistor1501bof the pixel102bmay be reversed, as compared with the arrangement shown inFIG.17. As shown inFIG.17, the reset transistor1501aincludes a p-type diffusion region406a, a gate electrode1701a, and a p-type diffusion region1702a. The diffusion region1702ais connected to the power supply potential Vss to function as the drain region of the reset transistor1501a. The source region of the reset transistor1501aand the drain region of the driving transistor202ashare one diffusion region406a. This can miniaturize the pixels102(pixel groups1601), as compared with a case in which the diffusion region forming the source region of the reset transistor1501aand the diffusion region forming the drain region of the driving transistor202aare separately arranged in the X direction. Similarly, the reset transistor1501bincludes a p-type diffusion region406b, a gate electrode1701b, and a p-type diffusion region1702b. The diffusion region1702bis connected to the power supply potential Vss to function as the drain region of the reset transistor1501b. The source region of the reset transistor1501band the drain region of the driving transistor202bshare one diffusion region406b. In this embodiment as well, the source region (diffusion region404a), a gate electrode405a, and the drain region (diffusion region406a) of the driving transistor202aof the pixel102aand the source region (diffusion region404b), a gate electrode405b, and the drain region (diffusion region406b) of the driving transistor202bof the pixel102bare sequentially arranged in the positive X direction. Thus, similar to the above-described first and second embodiments, in the light emitting device101, a difference in electrical characteristic of the driving transistor202between the pixels102can be reduced, thereby suppressing degradation in display image quality. Furthermore, in this embodiment, the source region (diffusion region406a), the gate electrode1701a, and the drain region (diffusion region1702a) of the reset transistor1501aarranged in the pixel102aand the source region (diffusion region406b), the gate electrode1701b, and the drain region (diffusion region1702b) of the reset transistor1501barranged in the pixel102bare sequentially arranged in the positive X direction. Thus, in the light emitting device101, a difference in electrical characteristic of the reset transistor1501between the pixels102can be reduced, thereby suppressing degradation in display image quality. As shown inFIG.17, in the pixel102, the arrangement order of the source region, gate electrode, and drain region of the driving transistor202in the positive X direction may be the same as that of the source region, gate electrode, and drain region of the reset transistor1501. For example, with respect to each of the reset transistors1501aand1501b, the source region, gate electrode, and drain region may be arranged in this order in the negative X direction. In this embodiment, the reset transistor1501aof the pixel102aand the reset transistor1501bof the pixel102bare arranged so that currents flow in the same direction. However, the present invention is not limited to this, and currents need not flow in the same direction. For example, the reset transistor1501aarranged in the pixel102aand the reset transistor1501barranged in the pixel102bmay be designed so that currents flow in the opposite directions. This is implemented when the driving transistor202causes a current to flow in response to a luminance signal with a voltage corresponding to luminance information while the reset transistor1501resets the light emitting element201. Thus, the control accuracy of the reset transistor1501may be lower than that of the driving transistor202. Therefore, in accordance with the arrangement of the pixels102and the pixel groups1601, the flow direction of a current in each reset transistor1501may be decided appropriately. In this embodiment as well, if the distance between the gate electrode405of the driving transistor202and a diffusion region403forming the drain region of the write transistor is different between the pixels102aand102b, the shape of a wiring pattern903may be different between the pixels102aand102b, similar to the above-described second embodiment. In the arrangement shown inFIG.17, a length1703ais a length between the gate electrode405aof the driving transistor202aand the contact portion of a diffusion region403aforming the drain region of the write transistor203ain the pixel102a. Similarly, a length1703bis a length between the gate electrode405bof the driving transistor202band the contact portion of a diffusion region403bforming the drain region of the write transistor203bin the pixel102b. A length1704ais the length of a portion where the wiring pattern903aoverlaps the gate electrode405aof the driving transistor202a. Similarly, a length1704bis the length of a portion where the wiring pattern903boverlaps the gate electrode405bof the driving transistor202b. In the arrangement shown inFIG.17, the length1703aof the pixel102ais shorter than the length1703bof the pixel102b. To the contrary, the length1704aof the pixel102ais longer than the length1704bof the pixel102b. This can increase the parasitic capacitance of the wiring pattern903ato be almost equal to the parasitic capacitance of the wiring pattern903b. As a result, the gate-source capacitance of the driving transistor202afor holding a voltage corresponding to luminance information is almost equal to that of the driving transistor202b, thereby reducing the difference in electrical characteristic between the pixels102aand102b. Thus, in this embodiment as well, it is possible to reduce a luminance unevenness between the pixels102aand102b, thereby suppressing degradation in display image quality. In the arrangement shown inFIG.17, the length1703ais shorter than the length1703b, and thus the length1704ais shorter than the length1704b. However, if the length1703ais longer than the length1703b, the length1704ais made shorter than the length1704b. As shown inFIG.17, the wiring pattern903is arranged in the X direction on the gate electrode405. However, the wiring pattern903may be arranged to bend from the X direction to the Y direction. Furthermore, as shown inFIG.17, a wiring pattern903amay extend from the gate electrode405aon the side opposite to the pixel102b. In addition, the positions of the write transistors203aand203bare adjusted so that the distance between the gate electrode405of the driving transistor202and the diffusion region403forming the drain region of the write transistor becomes the same between the pixels102aand102b. In this case, the wiring pattern903aand a wiring pattern903bmay have equal lengths and areas. For example, the wiring patterns903aand903bmay have line-symmetric shapes with respect to a line, in the Y direction, which passes through the center of the diffusion region401in the X direction. FIG.18shows a modification of the wiring pattern903shown inFIG.17. Similar to the above-described arrangement shown inFIG.11, the parasitic capacitance of the wiring pattern903may be adjusted by the area where the wiring pattern903overlaps the gate electrode405of the driving transistor202. In the arrangement shown inFIG.18, the length1703ais shorter than the length1703b, and thus the area where the wiring pattern903aand the gate electrode405aoverlap each other is larger than the area where the wiring pattern903band the gate electrode405boverlap each other. This can increase the parasitic capacitance of the wiring pattern903ato be almost equal to the parasitic capacitance of the wiring pattern903b. At this time, as shown inFIG.18, the parasitic capacitance of the wiring pattern903may be adjusted by differentiating the width of a portion, extending in the X direction, of the wiring pattern903between the pixels102aand102b. FIG.19shows another modification of the wiring pattern903shown inFIG.17or18. A length1901aindicates the length of a portion1902aarranged on the side of the pixel102bwith respect to a portion extending in the Y direction of a portion, extending in the X direction, of the wiring pattern903a. Similarly, a length1901bindicates the length of a portion1902barranged on the side of the pixel102awith respect to a portion extending in the Y direction of a portion, extending in the X direction, of the wiring pattern903b. At this time, similar to the above-described arrangement shown inFIG.12, the parasitic capacitance of the wiring pattern903may be adjusted by adjusting the lengths1901aand1901b. In the arrangement shown inFIG.19, the length1703ais shorter than the length1703b, and thus the length1901ais longer than the length1901b. This can increase the parasitic capacitance of the wiring pattern903ato be almost equal to the parasitic capacitance of the wiring pattern903b. FIG.20shows a modification of the arrangement of the transistors shown inFIG.17. In each pixel group1601, the write transistor203aof the pixel102aand the write transistor203bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102b. Furthermore, the reset transistor1501aof the pixel102aand the reset transistor1501bof the pixel102bare arranged between the driving transistor202aof the pixel102aand the driving transistor202bof the pixel102bin the X direction. The light emission control transistor701aof the pixel102ais arranged between the driving transistor202aof the pixel102aand the write transistor203aof the pixel102a. The light emission control transistor701bof the pixel102bis arranged on the side, opposite to the pixel102a, of the driving transistor202bof the pixel102b. The drain region of the reset transistor1501aof the pixel102aand the drain region of the reset transistor arranged in the pixel102bshare one diffusion region2001connected to the power supply potential Vss. This can miniaturize the pixels102(pixel groups1601), as compared with a case in which the diffusion region forming the drain region of the reset transistor1501aand the diffusion region forming the drain region of the reset transistor1501bare separately arranged in the X direction. The write transistors203aand203bof the pixels102aand102band the reset transistors1501aand1501bof the pixels102aand102bare arranged side by side in the Y direction. The write transistors203aand203bof the pixels102aand102band the reset transistors1501aand1501bof the pixels102aand102bmay be reversed, as compared with the arrangement shown inFIG.20. FIG.21is a circuit diagram showing the connection relationship among four adjacent pixels102. The plurality of pixels102further include a pixel102carranged adjacent to the pixel102ain the Y direction and a pixel102darranged adjacent to the pixel102cin the X direction and adjacent to the pixel102bin the Y direction. Similar to each of the above-described embodiments, the source region of the write transistor203aof the pixel102aand the source region of the write transistor203bof the pixel102bare connected via a signal line107ab. The source region of a write transistor203cof the pixel102cand the source region of a write transistor203dof the pixel102dare connected via a signal line107cd. Furthermore, in the pixels102aand102cadjacent to each other in the Y direction, the drain region of the reset transistor1501aof the pixel102aand the drain region of a reset transistor1501cof the pixel102care connected to the same node connected to the power supply potential Vss. Similarly, in the pixels102band102dadjacent to each other in the Y direction, the drain region of the reset transistor1501bof the pixel102band the drain region of a reset transistor1501dof the pixel102dare connected to the same node connected to the power supply potential Vss. The pixels102a,102b,102c, and102dform a pixel group2101. FIG.22shows an example of the arrangement of the transistors of the circuit shown inFIG.21. As shown inFIG.22, the reset transistor1501aof the pixel102aincludes a p-type diffusion region2201, a gate electrode2202a, and the p-type diffusion region1702a. The reset transistor1501bof the pixel102bincludes the diffusion region2201, a gate electrode2202b, and the p-type diffusion region1702b. The reset transistor1501cof the pixel102cincludes the diffusion region2201, a gate electrode2202c, and a p-type diffusion region1702c. The reset transistor1501dof the pixel102dincludes the diffusion region2201, a gate electrode2202d, and a type diffusion region1702d. That is, the drain regions of the reset transistors1501a,1501b,1501c, and1501dof the pixels102a,102b,102c, and102dshare one diffusion region2201. This can miniaturize the pixels102(pixel groups2101). The light emitting element201will now be described. The light emitting element201is provided by forming an anode, an organic compound layer, and a cathode on a substrate. A protection layer, a color filter, or the like may be provided on the cathode. If a color filter is provided, a planarizing layer may be provided between the protection layer and the color filter. The planarizing layer can be made of acrylic resin or the like. In each of the above-described embodiments, a semiconductor substrate of silicon or the like is used as a substrate. However, the present invention is not limited to this, and quartz, glass, a silicon wafer, a resin, a metal, or the like may be used as a substrate. As in each of the above-described embodiments, a switching element such as a transistor and a wiring may be provided on the substrate, and an insulating layer may be provided thereon. The insulating layer may be made of any material as long as a contact hole for ensuring conductivity between the anode of the light emitting element201and the transistor formed on the substrate can be formed and insulation from the unconnected wiring pattern can be ensured. For example, a resin such as polyimide, silicon oxide, silicon nitride, or the like can be used. A pair of electrodes (the above-described electrodes501and503) can be used as electrodes. The pair of electrodes may be an anode and a cathode. When an electric field is applied in the direction in which the light emitting element201emits light, the electrode having a high potential is the anode, and the other is the cathode. It can also be said that the electrode that supplies holes to the light emitting layer of the light emitting element201is the anode and the electrode that supplies electrons is the cathode. As the constituent material of the anode, a material having a large work function can be used. For example, a metal such as gold, platinum, silver, copper, nickel, palladium, cobalt, selenium, vanadium, or tungsten, a mixture containing some of them, an alloy obtained by combining some of them, or a metal oxide such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), or zinc indium oxide can be used as the anode. Furthermore, a conductive polymer such as polyaniline, polypyrrole, or polythiophene can also be used as the anode. One of these electrode materials may be used singly, or two or more of them may be used in combination. The anode may be formed by a single layer or a plurality of layers. When the anode is used as a reflective electrode, for example, chromium, aluminum, silver, titanium, tungsten, molybdenum, an alloy thereof, a stacked layer thereof, or the like can be used. When the anode is used as a transparent electrode, an oxide transparent conductive layer made of indium tin oxide (ITO), indium zinc oxide, or the like can be used, but the present invention is not limited thereto. A photolithography technique can be used to form the electrode. On the other hand, as the constituent material of the cathode, a material having a small work function can be used. Examples of the material include an alkali metal such as lithium, an alkaline earth metal such as calcium, a metal such as aluminum, titanium, manganese, silver, lead, or chromium, and a mixture containing some of them. Alternatively, an alloy obtained by combining these metals can also be used. For example, a magnesium-silver alloy, an aluminum-lithium alloy, an aluminum-magnesium alloy, a silver-copper alloy, a zinc-silver alloy, or the like can be used as the cathode. A metal oxide such as indium tin oxide (ITO) can also be used. One of these electrode materials may be used singly, or two or more of them may be used in combination. The cathode may have a single-layer structure or a multilayer structure. For the cathode, silver may be used, or a silver alloy may be used to suppress aggregation of silver. The ratio of the alloy is not limited as long as aggregation of silver can be suppressed. For example, the ratio between silver and a material other than silver may be 1:1. The cathode may be a top emission element using an oxide conductive layer made of ITO or the like, or may be a bottom emission element using a reflective electrode made of aluminum (Al) or the like, and is not particularly limited. The method of forming the cathode is not particularly limited, but if direct current sputtering or alternating current sputtering is used, the good film coverage is provided and the resistance is easily lowered. A protection layer may be provided on the cathode. For example, by adhering glass provided with a moisture absorbing agent on the cathode, permeation of water or the like into the light emitting layer such as an organic EL layer can be suppressed and occurrence of display defects can be suppressed. Furthermore, as another embodiment, a passivation film made of silicon nitride or the like may be provided on the cathode to suppress permeation of water or the like into the light emitting layer. For example, after forming the cathode and transferring it to another chamber without breaking the vacuum, a silicon nitride film having a thickness of 2 μm may be formed by a chemical vapor deposition method (CVD method), thereby obtaining the protection layer. The protection layer may be provided using an atomic deposition method (ALD method) after forming a film using the CVD method. A color filter may be provided on the protection layer. For example, a color filter considering the size of the light emitting element201may be provided on another substrate, and the substrate with the color filter provided thereon may be bonded to the substrate with the light emitting element201provided thereon. Alternatively, a color filter may be patterned on the above-described protection layer using a photolithography technique. The color filter may be formed from a polymeric material. A planarizing layer may be provided between the color filter and the protection layer. The planarizing layer may be formed from an organic compound, and may be made of a low-molecular material or a polymeric material. For example, the planarizing layer can be formed from a polymeric organic compound. The planarizing layers may be provided above and below the color filter, and the same or different materials may be used for them. More specifically, examples of the material include polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin. A counter substrate may be provided on the planarizing layer. The counter substrate is called a counter substrate because it is provided at a position corresponding to the above-described substrate. The constituent material of the counter substrate may be the same as that of the above-described substrate. The organic layer502(hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, and the like) forming the light emitting element201according to an embodiment of the present invention is formed by the method to be described below. The organic layer502can be formed by a dry process using a vacuum deposition method, an ionization deposition method, a sputtering method, a plasma method, or the like. Instead of the dry process, a wet process that forms a layer by dissolving a solute in an appropriate solvent and using a well-known coating method (for example, a spin coating method, a dipping method, a casting method, an LB method, an inkjet method, or the like) can be used. Here, when the organic layer502is formed by a vacuum deposition method, a solution coating method, or the like, crystallization or the like hardly occurs and excellent temporal stability is obtained. Furthermore, when the organic layer502is formed using a coating method, it is possible to form the film in combination with a suitable binder resin. Examples of the binder resin include polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin. However, the binder resin is not limited to them. One of these binder resins may be used singly as a homopolymer or a copolymer, or two or more of them may be used in combination. Furthermore, additives such as a well-known plasticizer, antioxidant, and an ultraviolet absorber may also be used as needed. Next, a light emitting device according to this embodiment will be described with reference to the accompanying drawings.FIG.23is a schematic sectional view showing an example, different from those shown inFIGS.5and10described above, of the light emitting device including a light emitting element as an example of the above-described light emitting element201and a TFT element connected to the light emitting element. The TFT element is an example of an active element. A light emitting device2310shown inFIG.23is provided with a substrate2311of glass, silicon, or the like and an insulating layer2312thereon. An active element such as a TFT2318is arranged on the insulating layer2312, and a gate electrode2313, a gate insulating film2314, and a semiconductor layer2315of the TFT2318are arranged. The TFT2318shown inFIG.23is an example of the above-described driving transistor202. The TFT2318further includes the semiconductor layer2315, a drain electrode2316, and a source electrode2317. An insulating film2319is provided on the TFT2318. The source electrode2317and an anode2321forming the light emitting element are connected via a contact hole2320formed in the insulating film2319. Note that a method of electrically connecting the electrodes (anode and cathode) included in the light emitting element and the electrodes (source electrode and drain electrode) included in the TFT is not limited to the that shown inFIG.23. That is, one of the anode and cathode and one of the source electrode and drain electrode of the TFT2318are electrically connected. The TFT indicates a thin-film transistor. In the light emitting device2310shown inFIG.23, an organic layer2322is illustrated as one layer. However, the organic layer2322may include a plurality of layers. Protection layers2324and2325are provided on a cathode2323to suppress the degradation of the light emitting element. A transistor is used as a switching element in the light emitting device2310shown inFIG.23but may be used as another switching element. The transistor used in the light emitting device2310shown inFIG.23is not limited to a transistor using a single-crystal silicon wafer, and may be a thin-film transistor including an active layer on an insulating surface of a substrate. Examples of the active layer include single-crystal silicon, amorphous silicon, non-single-crystal silicon such as microcrystalline silicon, and a non-single-crystal oxide semiconductor such as indium zinc oxide and indium gallium zinc oxide. Note that the thin-film transistor is also called a TFT element. The transistor included in the light emitting device2310shown inFIG.23may be formed in a substrate such as an Si substrate. Here, being formed in a substrate means that a transistor is formed by processing the substrate itself such as an Si substrate. In other words, including a transistor in a substrate can be regarded as integrally forming the substrate and the transistor. The light emission luminance of the light emitting element according to this embodiment is controlled by the TFT which is an example of a switching element, and the light emitting elements are provided in a plurality of planes to display an image with the light emission luminances of the respective elements. Note that the switching element according to this embodiment is not limited to the TFT, and may be a transistor formed from low-temperature polysilicon or an active matrix driver formed on the substrate such as an Si substrate. The term “on the substrate” may mean “in the substrate”. Whether to provide a transistor in the substrate or use a TFT is selected based on the size of the display unit. For example, if the size is about 0.5 inch, the organic light emitting element may be provided on the Si substrate. Application examples in which the light emitting device101of each of the above-described embodiments is applied to a display device, a photoelectric conversion device, an electronic device, an illumination device, and a mobile device will be explained below with reference toFIGS.24to29. In addition, the light emitting device101is applicable to the exposure light source of an electrophotographic image forming device, the backlight of a liquid crystal display device, a light emitting device including a color filter in a white light source, and the like. The display device may be an image information processing device that includes an image input unit for inputting image information from an area CCD, a linear CCD, a memory card, or the like, and an information processing unit for processing the input information, and displays the input image on a display unit. In addition, a display unit included in a camera or an inkjet printer may have a touch panel function. The driving type of the touch panel function may be an infrared type, a capacitance type, a resistive film type, or an electromagnetic induction type, and is not particularly limited. The display device may be used for the display unit of a multifunction printer. FIG.24is a schematic view showing an example of the display device using the light emitting device101according to this embodiment. A display device2400can include a touch panel2403, a display panel2405, a frame2406, a circuit board2407, and a battery2408between an upper cover2401and a lower cover2409. Flexible printed circuits (FPCs)2402and2404are respectively connected to the touch panel2403and the display panel2405. Active elements such as transistors are arranged on the circuit board2407. The battery2408is unnecessary if the display device2400is not a portable device. Even when the display device2400is a portable device, the battery2408need not be provided in this position. The above-described light emitting device101in which the light emitting layer of the organic layer502contains an organic light emitting material such as an organic EL is applicable to the display panel2405. The light emitting device101that functions as the display panel2405operates by being connected to the active elements such as transistors arranged on the circuit board2407. The display device2400shown inFIG.24may also be used as a display unit of a photoelectric conversion device (imaging device) including an optical unit having a plurality of lenses, and an imaging element for receiving light having passed through the optical unit and photoelectrically converting the light into an electrical signal. The photoelectric conversion device can have a display unit for displaying information acquired by the imaging element. In addition, the display unit can be either a display unit exposed outside the photoelectric conversion device, or a display unit arranged in the finder. The photoelectric conversion device may also be a digital camera or a digital video camera. FIG.25is a schematic view showing an example of the photoelectric conversion device using the light emitting device101according to this embodiment. A photoelectric conversion device2500can include a viewfinder2501, a rear display2502, an operation unit2503, and a housing2504. The photoelectric conversion device2500can also be referred to as an imaging device. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to the viewfinder2501as a display unit. In this case, the light emitting device101can display not only an image to be captured but also environment information, imaging instructions, and the like. Examples of the environment information are the intensity and direction of external light, the moving velocity of an object, and the possibility that an object is covered with an obstacle. The timing suitable for imaging is often a very short time, so the information is preferably displayed as soon as possible. Accordingly, the above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material can be used as the viewfinder2501. This is so because the organic light emitting material has a high response speed. For the light emitting device101using the organic light emitting material, a display speed is obtained. The light emitting device101is more suitable for these devices than a liquid crystal display device. The photoelectric conversion device2500includes an optical unit (not shown). This optical unit has a plurality of lenses, and forms an image of light having passed through the optical unit on a photoelectric conversion element (not shown) that is accommodated in the housing2504and receives the light. The focal points of the plurality of lenses can be adjusted by adjusting the relative positions. This operation can also automatically be performed. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material may be applied to the display unit of the electronic device. At this time, the light emitting device101can have both a display function and an operation function. Examples of the portable terminal are a portable phone such as a smartphone, a tablet, and a head mounted display. FIG.26is a schematic view showing an example of the electronic device using the light emitting device101according to this embodiment. An electronic device2600includes a display unit2601, an operation unit2602, and a housing2603. The housing2603can accommodate a circuit, a printed board having this circuit, a battery, and a communication unit. The operation unit2602can be either a button or a touch-panel-type reaction unit. The operation unit2602can also be a biometric authentication unit that performs unlocking or the like by authenticating the fingerprint. A portable device including a communication unit can also be regarded as a communication device. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to the display unit2601. FIGS.27A and27Bare schematic views showing examples of the display device using the light emitting device101according to this embodiment.FIG.27Ashows a display device such as a television monitor or a PC monitor. A display device2700includes a frame2701and a display unit2702. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to the display unit2702. The display device2700may also include a base2703that supports the frame2701and the display unit2702. The base2703is not limited to the form shown inFIG.27A. For example, the lower side of the frame2701may also function as the base2703. In addition, the frame2701and the display unit2702can be bent. The radius of curvature in this case can be 5,000 (inclusive) to 6,000 (inclusive) mm. FIG.27Bis a schematic view showing another example of the display device using the light emitting device101according to this embodiment. A display device2710shown inFIG.27Bcan be folded, that is, the display device2710is a so-called foldable display device. The display device2710includes a first display unit2711, a second display unit2712, a housing2713, and a bending point2714. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to each of the first display unit2711and the second display unit2712. The first display unit2711and the second display unit2712can also be one seamless display device. The first display unit2711and the second display unit2712can be divided by the bending point. The first display unit2711and the second display unit2712can display different images, and can also display one image together. FIG.28is a schematic view showing an example of the illumination device using the light emitting device101according to this embodiment. An illumination device2800can include a housing2801, a light source2802, a circuit board2803, an optical film2804, and a light-diffusing unit2805. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to the light source2802. The optical film2804can be a filter that improves the color rendering of the light source. When performing lighting-up or the like, the light-diffusing unit2805can throw the light of the light source over a broad range by effectively diffusing the light. The illumination device2800can also include a cover on the outermost portion, as needed. The illumination device2800can include both the optical film2804and the light-diffusing unit2805, and can also include only one of them. The illumination device2800is a device for illuminating the room or the like. The illumination device2800can emit white light, natural white light, or light of any color from blue to red. The illumination device2800can also include a light control circuit for controlling these light components. The illumination device2800can also include a power supply circuit to be connected to the light emitting device101that functions as the light source2802. This power supply circuit can be a circuit for converting an AC voltage into a DC voltage. “White” has a color temperature of 4,200 K, and “natural white” has a color temperature of 5,000 K. The illumination device2800may also have a color filter. In addition, the illumination device2800can have a heat radiation unit. The heat radiation unit radiates the internal heat of the device to the outside of the device, and examples are a metal having a high specific heat and liquid silicon. FIG.29is a schematic view of an automobile including a taillight as an example of a vehicle lighting appliance using the light emitting device101according to this embodiment. An automobile2900has a taillight2901, and the taillight2901may be turned on when performing a braking operation or the like. The light emitting device101according to this embodiment may be used as a headlight serving as a vehicle lighting appliance. The automobile is an example of a mobile device, and the mobile device may be a ship, a drone, an airplane, a railway vehicle, or the like. The mobile device can include a main body and a lighting appliance installed in the main body. The lighting appliance may also be a device that sends a notification of the current position of the main body. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material is applicable to the taillight2901. The taillight2901can have a protection member for protecting the light emitting device101that functions as the taillight2901. The material of the protection member is not limited as long as the material is a transparent material with a strength that is high to some extent, and can be polycarbonate. The protection member can also be formed by mixing a furandicarboxylic acid derivative or an acrylonitrile derivative in polycarbonate. The automobile2900can include a body2903, and a window2902attached to the body2903. This window can be a window for checking the front and back of the automobile, and can also be a transparent display. The above-described light emitting device101in which the light emitting layer of the organic layer502contains the organic light emitting material can be used as this transparent display. In this case, the constituent materials such as the electrodes of the light emitting device101are formed by transparent members. Some embodiments of the present invention can provide a technique advantageous in miniaturizing pixels and suppressing degradation in image quality in a light emitting device. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. This application claims the benefit of Japanese Patent Application No. 2019-188006, filed Oct. 11, 2019 which is hereby incorporated by reference herein in its entirety. | 77,667 |
11943971 | DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in various aspects without departing from the spirit thereof and is not imitatively interpreted to the description contents of the embodiments illustrated below. In order to further clarify the description, in some cases, the drawings may schematically illustrate width, thickness, shape, and the like of each component as compared with actual appearance, but these are merely examples, and thus, the present invention is not imitatively interpreted. In the present specification and each figure, elements having the same functions as those described with respect to the above-mentioned figure may be denoted by the same reference numerals, and duplicate description thereof may be omitted. In the detailed description of the present invention, when defining the relative position between a certain component and another component, “above” and “below” include, unless otherwise specified, not only a case where another component is located directly above or directly below a certain component but also a case where another component is further interposed. The embodiment described below is an organic EL display device. The organic EL display device is an active matrix type display device and is implemented on a television set, a personal computer (PC), a mobile terminal, a mobile phone, or the like. In an image display region of the display device, a plurality of pixels constituting an image are two-dimensionally arranged. In the following description, an xyz coordinate system, which is a three-dimensional Cartesian coordinate system, is used, and an x-axis and a y-axis are set to correspond to the two-dimensional Cartesian coordinate system corresponding to the image. For example, the x-axis is set to a horizontal direction of the image, and the y-axis is set to a vertical method of the image. The z-axis is set to a thickness direction of an array substrate described later. In the following embodiment, a display device capable of displaying a color image in which a plurality of types of pixels (sub-pixels) having different emission colors are arranged in the image display region will be described. For example, the emission colors are assumed to be three colors of RGB. It is noted that, although a pixel in a color image corresponds to a set of sub-pixel groups configured with a plurality of types of sub-pixels in a display device, in the display device, the sub-pixel is a configurational unit, and an OLED or a pixel circuit is formed for each sub-pixel. Therefore, in the following description, sub-pixels are basically treated as pixels. First Embodiment FIG.1is a schematic view illustrating a schematic configuration of an organic EL display device2according to an embodiment. The organic EL display device2includes a pixel array unit4which is a display unit for displaying an image and a drive unit which drives the pixel array unit. In the organic EL display device2, a stacked structure of a thin film transistor (TFT) and an OLED and the like are formed on a base material made of a glass substrate or a flexible resin film. An OLED6and a pixel circuit8are disposed corresponding to the pixels in a matrix shape in the pixel array unit4. The pixel circuit8is configured with a plurality of TFTs, capacitors, and the like. It is noted that the pixel circuit8inFIG.1illustrates a simplified configuration including TFTs10and12and a capacitor14. On the other hand, the drive unit includes a scan line drive circuit20, a video line drive circuit22, a drive power supply circuit24, a reference power supply circuit26and a control device28and functions such as driving the pixel circuit8and controlling light emission of the OLED6. The scan line drive circuit20is connected to scan signal lines30provided for each horizontal alignment (pixel row) of the pixels. The scan line drive circuit20sequentially selects the scan signal lines30according to a timing signal input from the control device28and applies a voltage for turning on the switching TFT10to the selected scan signal lines30. The video line drive circuit22is connected to video signal lines32provided for each vertical alignment (pixel column) of the pixels. The video line drive circuit22is input with a video signal from the control device28, and a voltage according to the video signal of the selected pixel row is output to each video signal line32according to the selection of the scan signal lines30by the scan line drive circuit20. The voltage is written to the capacitor14through the switching TFT10in the selected pixel row. The drive TFT12supplies a current to the OLED6corresponding to the written voltage, so that the OLED6of the pixel corresponding to the selected scan signal line30emits light. The drive power supply circuit24is connected to the drive power supply lines34provided for each pixel column and supplies a current to the OLED6through the drive power supply line34and through the drive TFT12of the selected pixel row. The reference power supply circuit26applies a constant electric potential ϕREFto a common electrode (not illustrated) constituting the cathode electrode of the OLED6. In the embodiment, a lower electrode of the OLED6is a pixel electrode formed for each pixel, and an upper electrode of the OLED6is a common electrode that is commonly disposed to cover the plurality of pixel electrodes. The lower electrode is connected to the drive TFT12. On the other hand, the upper electrode is configured with an electrode common to the OLEDs6of the entire pixels. In the embodiment, the lower electrode is a positive electrode (anode) of the OLED6, and the upper electrode is a negative electrode (cathode). FIG.2is a schematic plan view of a display panel40of the organic EL display device2. The display panel40has a rectangular shape and has, for example, a structure in which an array substrate41and a counter substrate are bonded together with a filling material interposed therebetween. The array substrate41includes a display region42, a frame region44, and a connection terminal region46. The pixel array unit4illustrated inFIG.1is provided in the display region42, and as described above, the OLED6, the pixel circuit8, and the like are formed in the pixel array unit4. On the other hand, a polarizing plate or a touch panel can be provided on the counter substrate. The frame region44is the outer edge region of the display region42, the inner boundary coincides with the outline of the display region42, the outer boundary is a rectangle, three sides overlap the sides of the display panel40, and the remaining one side is a boundary with the connection terminal region46. However, since the end of the display region42is defined as the end of the light emitting region of the OLED6belonging to the outermost pixels, in some cases, the pixel circuit8is provided to straddle the boundary between the display region42and the frame region44. The connection terminal region46is provided adjacent to the frame region44. The connection terminal region46is a rectangle which has three sides overlapping the sides of the display panel40and the remaining one side being a boundary with the frame region44. Wirings for inputting/outputting an electric signal necessary for the operation of the pixel array unit4formed in the display region42are drawn out from the display region42and the frame region44to the connection terminal region46. That is, a group of wirings drawn out from the display region42and the frame region44are disposed in the connection terminal region46. A connection terminal for connecting the group of wiring to an external circuit is disposed in the connection terminal region46. A plurality of connection terminals are arranged, and one of the connection terminals is connected to one of the group of wirings drawn out from the display region42and the frame region44. For example, an FPC48is connected to the connection terminal, and the FPC48is connected to the control device28or other circuits20,22,24,26, and the like, or an IC50is mounted on the FPC48. The display panel40of the embodiment displays a color image, and the pixels in the color image are configured with, for example, pixels (sub-pixels) that emit light corresponding to any one of the three colors of RGB. In the embodiment, an example in which R pixels52r, G pixels52g, and B pixels52bare formed in a stripe arrangement in the display region will be described. In such arrangement, pixels of the same type (color) are aligned in the y direction of the image, and RGB is periodically aligned in the x direction. It is noted that, inFIG.2, each of the R pixel52r, the G pixel52g, and the B pixel52bschematically illustrates an effective light emitting region, which structurally corresponds to the pixel aperture60, and a region between the above-mentioned regions corresponds to a bank84described later. FIG.3is a schematic vertical cross-sectional view of the array substrate41, and a cross section IIIa is a cross section in the display region42at a position taken along the line IIIa-IIIa illustrated inFIG.2. A cross section IIIb is a cross section taken along the line IIIb-IIIb illustrated inFIG.2and is a cross section of the connection terminal region46and the frame region44adjacent thereto. The substrate70is made of a flexible film of polyimide, polyethylene terephthalate, or the like. The substrate70may also be made of other resin or glass. An undercoat layer71that serves as a barrier against impurities contained in the substrate70is formed on the surface of the substrate70. The undercoat layer71is made of a silicon oxide film, a silicon nitride film, or the like, and may have a stacked structure thereof. A semiconductor layer72is stacked on the undercoat layer71, and by the semiconductor layer72, a channel region, a source region, and a drain region of a TFT73of a pixel circuit or the like are formed. After the formation of the semiconductor layer72, a gate insulating film75is made of silicon oxide or the like, and a metal film stacked on the gate insulating film75is patterned to form a TFT gate electrode76or the like. An inorganic film77as an interlayer insulating film is stacked to cover the gate electrode76and the like. A metal film is formed on the inorganic film77, and the source/drain (S/D) electrodes78sand78dof the TFT are formed by using the metal film. The S/D electrodes78sand78dare electrically connected to the semiconductor layer72of the TFT through contact holes penetrating the gate insulating film75and the inorganic film77. Herein, the region of the semiconductor layer72which includes the connection portion with the S/D electrode78sand is injected with impurities that provide conductivity is used as the source region, and the region which includes the connection portion with the S/D electrode78dand is injected with impurities that provide conductivity is used as the drain region. The metal film is a conductive film stacked between the OLED and the substrate70, and a lower layer wiring located below the OLED can be formed by using the metal film. In particular, by the lower layer wiring, a wiring79of the connection terminal region46and a connection terminal79pthereof are formed. A flattening film80made of an organic material is stacked to cover the inorganic film77. Polyimide, acrylic resin, or the like is used for the flattening film80. The flattening film80flattens the surface on which the OLED is formed. On the other hand, in order to prevent water from infiltrating into the OLED from the flattening film80or the like, an inorganic film81is formed on the flattening film80. The inorganic film81is made of a material that is moisture-proof and has insulation. For example, the inorganic film81is formed by using a silicon nitride film or a stacked film of a silicon nitride film and a silicon oxide film. A pixel electrode82of the OLED is disposed on the surface of the inorganic film81. The pixel electrode82is electrically connected to the S/D electrode78sof the TFT73corresponding to the drive TFT12ofFIG.1through the contact hole penetrating the inorganic film81and the flattening film80. It is noted that the pixel electrode82may have a structure including a reflective film that reflects the light emitted from the OLED to the display surface side. For example, the pixel electrode82can be formed to have a stacked structure of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) and a reflective material such as silver (Ag). It is noted that storage capacitance illustrated as the capacitor14inFIG.1is formed by the source region of the S/D electrode78sand the semiconductor layer72connected to the pixel electrode82and a metal layer76clocated therebetween and connected to the gate electrode76. The conductive film83can be disposed under the pixel electrode82with the inorganic film81interposed therebetween, and by allowing the conductive film83to be grounded, for example, a retention capacitance can be formed between the conductive film83and the pixel electrode82. The retention capacitance stabilizes the voltage written in the storage capacitance and contributes to the stable operation of the organic light emitting diode. The bank84made of an insulating material is formed on the surface of the inorganic film81on which the pixel electrode82is formed. The bank84is formed along the periphery of the pixel, covers the end of the pixel electrode82, and has an opening at a position of a light emitting surface of the OLED. The upper surface of the pixel electrode82is exposed at the bottom of the opening, and the organic material layer85, which is an organic layer including a light emitting layer, is stacked on the surface thereof. The bank84is made of polyimide, acrylic resin, or the like. The upper electrode86of the OLED is formed on the organic material layer85. As described above, the upper electrode86can be a common electrode over the entire pixels of the display region. It is noted that the upper electrode86is made of a material that transmits light emitted from the organic material layer85. Specifically, the upper electrode86is a thin film made of metal having a low work function and being translucent so that electrons can be efficiently injected into the organic material layer85. The upper electrode86is formed with a film thickness that allows light to pass through the upper electrode, for example, by using an MgAg alloy. By the way, the upper electrode86is electrically connected to the wiring79through the contact hole87provided in the frame region44illustrated in the cross section IIIb. A sealing film that seals the upper surface of the OLED and prevents deterioration of the OLED due to moisture is formed in the display region42in which the OLED configured with the pixel electrode82, the organic material layer85, and the upper electrode86is formed. In the embodiment, the sealing film is a multilayer film configured with two inorganic films88and89and an organic film90. The inorganic films88and89are formed, for example, with a silicon nitride film, and the organic film90is formed with acrylic resin or the like. The inorganic film88is stacked on the surface of the upper electrode86in the display region42, the organic film90is interposed between the inorganic film88and the inorganic film89in the display region42, and the inorganic films88and89have contact regions to be in direct contact with each other and overlap each other in the frame region44. Herein, an inorganic film bonding portion91in which the inorganic films88and89and the inorganic film81are bonded is provided to the frame region44. By providing the inorganic film bonding portion91, it is possible to prevent the infiltration of water from the side into the region interposed between the inorganic films88and89and the inorganic film81, so that the prevention of deterioration of the OLED is established. The inorganic film bonding portions91are basically provided in a row around the display region42, so that the infiltration of water can be prevented more effectively. FIG.4is a schematic plan view of a portion of the display region42of the array substrate41and illustrates a state after the formation of the bank84and before the formation of the organic material layer85.FIG.5is a schematic vertical cross-sectional view of a portion of the array substrate41in the state, a cross section Va is a cross section taken along the line Va-Va illustrated inFIG.4, and a cross section Vb is a cross section taken along the line Vb-Vb illustrated inFIG.4. In the plan view ofFIG.4, the formation region of the bank84and the plurality of pixel apertures60in the display region42are illustrated, and similarly toFIG.2, the plurality of pixel apertures60correspond to the R pixels52r, the G pixel52g, and the B pixel52bwhich are formed in stripe arrangement. Convex portions100are formed on the surface of the bank84. In the embodiment, the convex portions100include two types of convex portions100aand100bhaving different heights. Specifically, the first convex portion100ais higher than the second convex portion100b. That is, if the z-axis is defined in a direction in which the z-coordinate increases according to the height, the z-coordinate of the apex of the first convex portion100ais larger than the z-coordinate of the apex of the second convex portion100b. The first convex portion100ais basically disposed in the vicinity of a specific type of the pixel aperture60among RGB pixels. For example, the first convex portion100ais provided adjacent to each B pixel52b. On the other hand, in the embodiment, the second convex portion100bis disposed adjacent to each R pixel52rand each G pixel52g. Herein, in the stripe arrangement, the pixel apertures60can have an elongated shape in the y direction, and the spacing in the x direction can be formed smaller than the spacing in the y direction. That is, since the bank84between the pixels adjacent in the y direction has a width being larger than that between the pixels adjacent in the x direction, it is easy to dispose the convex portion100. Therefore, in the embodiment, the convex portion100is disposed on the bank84between the pixel rows. That is, the convex portion100ais provided adjacent to the B pixel52bin the y direction, and the convex portion100bis provided adjacent to each of the R pixel52rand the G pixel52gin the y direction. The positions of the cross sections Va and Vb inFIG.5are the same in the x direction and different in the y direction. It is noted thatFIG.5is provided to explain the shape and arrangement of the convex portions100, and most of the structures illustrated inFIG.3are not illustrated. For example, the layer101forming the array substrate41has a stacked structure including the layers from the undercoat layer71to the inorganic film81ofFIG.3. The convex portions100aand the convex portions100bare aligned in the x direction on a common straight line, and the convex portions100aand100badjacent to the respective BGB pixels appear at the x coordinates corresponding to the pixel apertures60in the cross section Vb. By the way, the height of the upper end of the bank84in the cross section Va corresponds to the height of the lower end of the convex portion100in the cross section Vb. In the embodiment, the convex portion100is made of a material common to that of the bank84, but the convex portion100may be made of a material different from that of the bank84. That is, when the bank84is made of polyimide or acrylic resin as described above, the convex portion100may be made of the same material, and for example, the convex portion100may be made of another organic material such as epoxy or an inorganic material such as silicon nitride. In the examples ofFIGS.4and5, the convex portion100has a shape with trapezoidal vertical cross section and a circular planar shape, but other shapes may be used. FIG.6is a schematic plan view after the formation of the organic material layer85in a portion of the display region42of the array substrate41corresponding toFIG.4. By the manufacturing method described later, an organic material layer85bis formed in the pixel electrode82exposed on the bottom surface of the pixel aperture60of the B pixel52band a rectangular region including surroundings thereof, and organic material layers85rand85gare formed in the pixel electrode82exposed on the bottom surface of the pixel aperture60and each of the R pixel52rand the G pixel52gand a rectangular region including surroundings thereof. Herein, the first convex portion100ais covered by the organic material layer85bof the adjacent B pixel52b, but the second convex portion100bis not covered by the organic material layer85of any pixel. In other words, the organic material layer85bof the B pixel52bamong the RGB pixels is provided to cover only the first convex portion100aamong the convex portions100aand100b, and the organic material layers85rand85gof the R pixel52rand the G pixel52gare provided not to cover any one of the first convex portion100aand the second convex portion100b. Next, an embodiment relating to the method for manufacturing the display device of the present invention will be described. The manufacturing method of the embodiment is basically different from the manufacturing method in the related art in the viewpoints that manufacturing method of the embodiment has a process of forming the above-mentioned convex portion100and a method of forming the organic material layer85is different. Among the viewpoints, the feature of the manufacturing method according to the present invention is mainly related to the viewpoint of the formation of the organic material layer85, particularly the viewpoint that the organic material layer85is formed by using the convex portion100, and thus, hereinafter, the viewpoint will be described with reference toFIGS.7to12. The convex portion100can be formed by a well-known process which is the same as or similar to forming the pixel aperture60in the bank84, and specifically, the convex portion100can be formed by etching a film such as resin stacked on the surface of the array substrate41by using photolithography technology. The three types of organic material layers85r,85g, and85bcorresponding to the three emission colors are formed by the separate coating method. Specifically, a vapor deposition mask having openings corresponding to the respective film formation positions is prepared for each of the three types of organic material layers, and the organic material layers85r,85g, and85bare sequentially vapor-deposited on the surface of the array substrate41by using the vapor deposition mask. In the embodiment, the organic material layer85bis first formed in the B pixel52badjacent to the first convex portion100a, and after that, the organic material layers85gand85rare sequentially formed in the G pixel52gand the R pixel52r. FIGS.7and8are diagrams illustrating the process of forming the organic material layer85b,FIGS.9and10are diagrams illustrating the process of forming the organic material layer85g, andFIGS.11and12are diagrams illustrating the process of forming the organic material layer85r.FIGS.7,9, and11are schematic plan views of the vapor deposition masks for B, G, and R, respectively, and are illustrated in association with the array substrate41illustrated inFIG.4. As illustrated inFIG.7, by disposing a vapor deposition mask105bfor B on the array substrate41on which the bank84and the convex portion100illustrated inFIGS.4and5are formed and performing the vapor deposition process, the organic material layer85bis formed.FIG.8is a schematic vertical sectional view of the array substrate41and the vapor deposition mask105bin a state where the organic material layer85bis vapor-deposited and is illustrated in association with the sectional view ofFIG.5. That is, a cross section VIIIa is a vertical cross section at a position taken along the line Va-Va illustrated inFIG.4, and a cross section VIIIb is a vertical cross section at a position taken along the line Vb-Vb illustrated inFIG.4. An opening110bof the vapor deposition mask105bfor B is formed in a shape and size including the pixel aperture60of only the B pixels52bamong the RGB pixels on the array substrate41and also including the first convex portion100aadjacent to the B pixels52b. Therefore, when the vapor deposition mask105bis disposed on the array substrate41, as illustrated in the cross section VIIIb ofFIG.8, the first convex portion100ais not in contact with the vapor deposition mask105band the upper end of the second convex portion100bis lower than the first convex portion100a, which is in contact with the back surface of the vapor deposition mask105bto support the vapor deposition mask105b. That is, the first convex portion100adoes not function as a spacer that defines the height of the vapor deposition mask105bon the array substrate41, and the second convex portion100blower than the first convex portion100afunctions as the spacer. When the vapor deposition is performed by using the vapor deposition mask105b, as illustrated in the cross section VIIIa ofFIG.8andFIG.6, the organic material layer85bis stacked on the pixel aperture60of the B pixel52b, and as illustrated in the cross section VIIIb ofFIG.8andFIG.6, the first convex portion100ais also covered. Next, as illustrated inFIG.9, a vapor deposition mask105gfor G is disposed on the array substrate41on which the organic material layer85bis formed, and the vapor deposition process is performed to form the organic material layer85g.FIG.10is a schematic vertical sectional view of the array substrate41and the vapor deposition mask105gin a state where the organic material layer85gis vapor-deposited, and is illustrated in association with the sectional view ofFIG.5. That is, a cross section Xa is a vertical cross section at a position taken along the line Va-Va illustrated inFIG.4, and a cross section Xb is a vertical cross section at a position taken along the line Vb-Vb illustrated inFIG.4. An opening110gof the vapor deposition mask105gfor G is formed in a shape and size including the pixel aperture60of only the G pixels52gamong the RGB pixels on the array substrate41while not including any of the convex portions100. Therefore, when the vapor deposition mask105gis disposed on the array substrate41, as illustrated in the cross section Xb ofFIG.10, the upper end of the first convex portion100ahigher than the second convex portion100bis in contact with the back surface of the vapor deposition mask105gto support the vapor deposition mask105g. That is, the first convex portion100afunctions as a spacer that defines the height of the vapor deposition mask105gon the array substrate41. When vapor deposition is performed by using the vapor deposition mask105g, the organic material layer85gis stacked on the pixel aperture60of the G pixel52gas illustrated in the cross section Xa ofFIG.10andFIG.6. On the other hand, the organic material layer85gdoes not cover any one of the first convex portion100aand the second convex portion100bas illustrated in the cross section Xb ofFIG.10andFIG.6. As illustrated inFIG.11, by disposing a vapor deposition mask105rfor R on the array substrate41on which the organic material layers85band85gare formed and by performing the vapor deposition process, the organic material layer85ris formed.FIG.12is a schematic vertical sectional view of the array substrate41and the vapor deposition mask105rin a state where the organic material layer85ris vapor-deposited, and is illustrated in association with the sectional view ofFIG.5. That is, a cross section XIIa is a vertical cross section at a position taken along the line Va-Va illustrated inFIG.4, and a cross section XIIb is a vertical cross section at a position taken along the line Vb-Vb illustrated inFIG.4. An opening110rof the vapor deposition mask105rfor R is formed in a shape and size including the pixel aperture60of only the R pixel52ramong the RGB pixels on the array substrate41while not including any of the convex portions100similarly to the vapor deposition mask105gfor G. Therefore, when the vapor deposition mask105ris disposed on the array substrate41, as illustrated in the cross section XIIb ofFIG.12, the first convex portion100afunctions as a spacer that defines the height of the vapor deposition mask105ron the array substrate41. When vapor deposition is performed by using the vapor deposition mask105r, the organic material layer85ris stacked on the pixel aperture60of the R pixel52ras illustrated in the cross section XIIa ofFIG.12andFIG.6, while any one of the first convex portion100aand the second convex portion100bis not covered as illustrated in the cross section XIIb ofFIG.12andFIG.6. When the plurality of types of organic material layers85are separately coated by a plurality of vapor deposition processes, as described above, the vapor deposition mask105used in the first vapor deposition process has an opening110into which the first convex portion100aenters, and thus, the second convex portion100bserves as a spacer for the vapor deposition mask105. Accordingly, as compared with the case where the first convex portion100aserves as a spacer, the distance between the array substrate41and the vapor deposition mask105can be reduced, and thus, the vapor deposition can be performed with high positional accuracy. On the other hand, the first convex portion100adoes not enter into the opening110of the vapor deposition mask105used in the second and subsequent vapor deposition processes, and the first convex portion100aserves as a spacer for the vapor deposition mask105. Accordingly, the distance between the array substrate41and the vapor deposition mask105can be increased by the first vapor deposition process, and thus, the foreign matter adhering to the vapor deposition mask105does not destroy the organic material layer already vapor-deposited on the array substrate41, so that it is possible to establish reducing the possibility of occurrence of display defects. It is noted that, in a case where the first convex portion100ais used as a spacer, as compared with the case where the second convex portion100bis used as a spacer, according to the increase in the distance between the vapor deposition mask105and the array substrate41, a wraparound of a vapor deposition material to the region shielded by the vapor deposition mask105can also be increased. Therefore, considering the influence of the wraparound, the opening110of the vapor deposition mask105used in the second and subsequent vapor deposition processes may be formed to be small in advance. Second Embodiment In the first embodiment, the example in which the R pixel52r, the G pixel52g, and the B pixel52bare formed in a stripe arrangement in the display region has been described. However, the present invention can also be applied to a display device having a pixel arrangement other than the stripe arrangement. As a second embodiment, an organic EL display device2having an arrangement of RGB pixels different from that of the first embodiment will be described. Herein, the basic difference between the second embodiment and the first embodiment is the arrangement of RGB pixels, and other configurations, for example, many contents described inFIGS.1to3can be basically common, so that the description thereof will be omitted herein. FIG.13is a schematic plan view of a portion of the display region42of the array substrate41of the organic EL display device2according to the second embodiment and illustrates a state after the formation of the organic material layer85. The plan view ofFIG.13illustrates the positions of the formation region of the bank84, the pixel apertures60and the organic material layers85r,85g, and85bof the respective R pixels52r, the G pixels52g, and the B pixels52b, the first convex portion100aand the second convex portion100bin the display region42. In one pixel configured with three sub-pixels that are the R pixel52r, the G pixel52g, and the B pixel52b, the R pixel52rand the G pixel52gare aligned in the y direction, and the B pixel52bis disposed adjacent to the x direction thereof. In such pixel configuration, as illustrated inFIG.13, for example, columns in which the R pixels52rand the G pixels52gare alternately aligned and columns in which only the B pixels52bare aligned are alternately disposed in the row direction in the display region42. Similarly to the first embodiment, in the embodiment, the first convex portion100ais provided adjacent to each B pixel52b, and the second convex portion100bis provided adjacent to each R pixel52rand each G pixel52g. Then, similarly to the first embodiment, the organic material layer85bof the B pixel52bis provided to cover only the first convex portion100aamong the two types of convex portions100, and the organic material layers85rand85gof the R pixel52rand the G pixel52g, respectively, are provided not to cover any one of the two types of convex portions100aand100b. FIGS.14,15, and16are schematic plan views of the vapor deposition masks for B, R, and G, respectively, and are illustrated in association with the array substrate41illustrated inFIG.13. Similarly to the vapor deposition mask105bof the first embodiment, an opening110bof a vapor deposition mask115bfor B is formed on the array substrate41in a shape and size including the pixel aperture60of the B pixel52band also including the first convex portion100awhich is adjacent to the B pixel52b. Similarly to the vapor deposition masks105rand105bof the first embodiment, the openings110rand110gof the vapor deposition masks105rand105gfor R and G are formed in a shape and size including the pixel apertures60of the R pixel52rand the G pixel52g, respectively, but not including any one of the convex portions100. By using the vapor deposition masks115, the organic material layer85of each pixel is formed by a manufacturing method basically the same as that of the first embodiment. That is, the organic material layer85bof the B pixel52bis formed by supporting the vapor deposition mask115bon the array substrate41by using the second convex portion100bas a spacer, and the organic material layers85rand85bof the R pixel52rand the B pixel52bare formed by supporting vapor deposition masks115rand115bon the array substrate41by using the first convex portion100aas a spacer. Therefore, also in the organic EL display device2according to the second embodiment, similarly to the first embodiment, by forming the OLED by the separate coating method, it is possible to improve the vapor deposition position accuracy and reduce the possibility of occurrence of display defects. Modified Example (1) With respect to the vapor deposition of the organic material layer85, the pixel which uses the lower convex portion among the two types of convex portions100as a spacer for the vapor deposition mask, and vapor deposition process is firstly performed on is referred to as the preceding vapor deposition pixel, and among the plurality of types of pixels, after the preceding vapor deposition pixel, the pixel which the vapor deposition process is performed on by using the higher convex portion among the two types of convex portions100as a spacer is referred to as a subsequent vapor deposition pixel. In the above-described embodiment, the B pixel is set as a preceding vapor deposition pixel, and the G pixel and the R pixel are set as subsequent vapor deposition pixels. However, which one of the plurality of types of pixels is used as the preceding vapor deposition pixel can be basically arbitrarily determined, and from the viewpoint of the present invention, the order of vapor deposition between the subsequent vapor deposition pixels can also be basically arbitrarily determined. (2) As already described, when the higher convex portion among the two types of convex portions100is used as the spacer of the vapor deposition mask, according to the increase in the distance between the vapor deposition mask and the array substrate, the wraparound of the vapor deposition material on the shield region of the vapor deposition mask is increased, and thus, the vapor deposition position accuracy can be lower than that of the case where the low convex portion100is used as a spacer. As one of the countermeasures, it has already been described that the opening of the vapor deposition mask in which the high convex portion100serves as a spacer is formed to be small. Herein, the pixel apertures of the plurality of types of sub-pixels having different emission colors can be set to different sizes depending on the emission efficiency and the visual sensitivity characteristics of the light emitting layer of each color. When an aperture size of the vapor deposition mask is the same, pixels having small pixel apertures are less susceptible to misalignment of the vapor deposition region than pixels having large pixel apertures. Therefore, among a plurality of types of pixels, the pixel having a large pixel aperture may be used as a preceding vapor deposition pixel, and the pixel having a small pixel aperture may be used as a subsequent vapor deposition pixel. By doing so, it is possible to ensure the vapor deposition position accuracy even when it is difficult to further miniaturize the opening of the vapor deposition mask due to the progress and the like of reduction of the pixel aperture. FIG.17illustrates an example thereof. Specifically,FIG.17is a schematic plan view of a portion of the display region42of the array substrate41of the organic EL display device2having a stripe arrangement similarly to the first embodiment and illustrates a state after the formation of the organic material layer85. In a layout of the pixels ofFIG.17, the pixel aperture60of the R pixel52rand the G pixel52gis smaller than that of the B pixel52b. Corresponding to the difference in the size of the pixel aperture, the first convex portion100ais disposed in the vicinity of the B pixel52b, the B pixel52bis used as the preceding vapor deposition pixel, and the R pixel52rand the G pixel52gare used as the subsequent vapor deposition pixels. (3) The first convex portion100adoes not need to be disposed adjacent to each of the preceding vapor deposition pixels and can be disposed at a density that preferably supports the vapor deposition mask of the subsequent vapor deposition pixels. Specifically, the convex portions100acan be thinned out at a density in which bending of the vapor deposition mask of the subsequent vapor deposition pixels does not occur between the convex portions100aserving as the spacer or the influence of the bending on the vapor deposition position accuracy can be ignored. From the same viewpoint, the second convex portion100bcan also be thinned out. For example, in the above-described embodiment, the arrangement density of the convex portions100bis basically twice that of the convex portions100a, but when the strength of the vapor deposition mask is the same for the R pixel, the G pixel, and the B pixel, it is possible to allow the density of the convex portions100bto be basically the same as that of the convex portion100a. (4) The bank84may be configured as a substitute for the second convex portion100b.FIG.18is a schematic vertical cross-sectional view of a portion of the array substrate41having the configuration and is a cross-sectional view taken along the line Vb-Vb illustrated inFIG.4. That is, in the present configuration, the cross section taken along the line Va-Va illustrated inFIG.4is the same as the cross section Va inFIG.5, but the cross section taken along the line Vb-Vb becomes the cross section inFIG.18instead of the cross section Vb inFIG.5. In the present configuration, the second convex portion100billustrated in the cross section Vb or the like ofFIG.5is not formed on the bank84, and the bank84itself functions as the second convex portion100b. That is, when the organic material layer85bof the B pixel52bis vapor-deposited, the upper surface of the bank84supports the vapor deposition mask105band functions as a spacer that holds the vapor deposition mask105babove the pixel electrode exposed on the bottom surface of the pixel aperture60. On the other hand, when the organic material layers85gand85rof the G pixel52gand the R pixel52rare vapor-deposited, the first convex portion100asupports the vapor deposition masks105gand105r. FIG.19is a schematic partial plan view of the array substrate41ofFIG.18after the formation of the organic material layer85. The array substrate41ofFIG.19is different from that ofFIG.6in that the second convex portion100bis not provided, but the array substrate41ofFIG.19is basically the same as that ofFIG.6in other viewpoint. In particular, similarly toFIG.6, the first convex portion100ais covered with the organic material layer85b. (5) In the above-described embodiment, the first convex portion100ais disposed adjacent to the B pixel52bused as the preceding vapor deposition pixel. As a result, the opening of the vapor deposition mask of the preceding vapor deposition pixel can be formed as one hole in which the portion provided corresponding to the pixel aperture and the portion into which the first convex portion100aenters can be integrated, and thus, the formation of the opening of the vapor deposition mask is facilitated. On the other hand, the opening on the pixel aperture and the opening into which the first convex portion100aenters may be formed separately from each other in the vapor deposition mask of the preceding vapor deposition pixel. The present invention is not limited to the above-described embodiments and modified examples, and various modifications are possible. For example, the configurations described in the embodiments can be replaced with substantially the same configurations, configurations that exhibit the same functions and effects, or configurations that can achieve the same object. | 42,132 |
11943972 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Technical solutions in embodiments of the present disclosure will be clearly and completely described below in conjunction with drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure. Please refer toFIG.1, which is a cross-sectional view of a first structure of a display panel provided in the present disclosure. A display panel10is provided in the present disclosure. The display panel10comprises a flexible substrate100, an array layer200, a pixel definition layer300, an insulating layer400, a light-emitting layer500, an additional layer600, and a first inorganic layer700. Please refer toFIG.2, which is a structural cross-sectional view of the flexible substrate and the array layer of the display panel provided in the present disclosure. The array layer200is disposed on the flexible substrate100. The array layer200comprises a transistor210. The transistor comprises an active layer211, a gate insulating layer212, a gate layer213, an interlayer dielectric layer214, a source215, and a drain216. The active layer211is disposed on the flexible substrate100. The active layer211comprises a P-type doped portion2111, a semiconductor portion2112, and an N-type doped portion2113. The P-type doped portion2111and the N-type doped portion2113are located on opposite sides of the semiconductor portion2112. Material of the active layer211comprises indium gallium zinc oxide, indium zinc tin oxide, gallium zinc oxide, zinc oxynitride, and indium gallium zinc titanium oxide. The gate insulating layer212is disposed on the active layer211. Material of the gate insulating layer212comprises SiOx and SiNx. The gate layer213is disposed on the gate insulating layer212. Material of the gate layer213comprises one or a combination of Mo, Al, Cu, and Ti. The interlayer dielectric layer214covers the active layer211, the gate insulting layer212, and the gate layer213. The interlayer dielectric layer214has a third through hole2141and a fourth through hole2142. The third through hole2141penetrates the interlayer dielectric layer214to expose one side of the active layer211. The fourth through hole2142penetrates the interlayer dielectric layer214to expose the other side of the active layer211. Material of the interlayer dielectric layer214comprises SiOx and SiNx. The source215is filled in the third through hole2141and on the interlayer dielectric layer214to electrically connect to the active layer211. The drain216is filled in the fourth through hole2142and on the interlayer dielectric layer214to electrically connect to the active layer211. Material of the source215and the drain216comprises one or a combination of Mo, Al, Cu, and Ti. The pixel definition layer300is disposed on the array layer200. Material of the pixel definition layer300comprises acrylic-based materials or epoxy-based materials. The insulating layer400is disposed on the pixel definition layer300. Material of the insulating layer400comprises SiOx and SiNx. The insulating layer400comprises a plurality of first through holes410and a plurality of second through holes420. The first through holes410and the second through holes420are alternately arranged. The first through holes410and the second through holes420penetrate the insulating layer400and the pixel definition layer300to expose the array layer200. Top diameters R1of the second through holes420are less than bottom diameters R2. The light-emitting layer500is disposed in the first through holes410. The light-emitting layer500comprises one of a red light-emitting layer510, a green light-emitting layer520, or a blue light-emitting layer530. The additional layer600is disposed on the pixel definition layer300, in the second through holes420, and on the insulting layer400and the light-emitting layer500. The additional layer600comprises an electron transport layer, an electron injection layer, and a cathode layer. The additional layer600comprises a plurality of additional portions610. The plurality of additional portions610are divided into first parts611and second parts612. The first parts611and the second parts612are not connected. The first parts611are disposed on the pixel definition layer300and the light-emitting layer500. The second parts612are disposed in the second through holes420. A distance L from one end of each of the second parts612to an opposite end of each of the second parts612is less than the bottom diameter R2of the second through hole420. The first inorganic layer700is disposed on the array layer200and the additional layer600. Material of the first inorganic layer700comprises one or a combination of SiOx, Al2O3, and SiNx. In another embodiment, the display panel10further comprises an organic layer800. The organic layer800is disposed on the first inorganic layer700. Material of the organic layer800comprises acrylic-based materials or epoxy-based materials. In another embodiment, the display panel10further comprises a second inorganic layer900. The second inorganic layer900is disposed on the organic layer800. Material of the second inorganic layer comprises one or a combination of SiOx, Al2O3, and SiNx. In the present disclosure, the second through holes are set such that the top diameters R1are less than the bottom diameters R2, and the distance L from one end of each of the second parts in the second through hole to an opposite end of the second part is less than the bottom diameter R2of the second through hole, so that the second parts do not completely fill the second through holes and expose part of the array layer. In addition, the first inorganic layer is disposed on the array layer and the additional layer, and the second parts in the second through holes are covered by the first inorganic layer and the array layer, adhesion between the array layer and the first inorganic layer is very strong since the two are formed of inorganic materials, and thus peeling of film layers are reduced during bending of the display panel, thereby improving the service life of the display panel. FIG.3is a cross-sectional view of a second structure of the display panel provided in the present disclosure. Ends of the first parts611and ends of the adjacent first parts611are partially suspended. Please refer toFIG.4andFIG.5,FIG.4is a flowchart of a method of manufacturing a display panel provided in the present disclosure.FIG.5is a flow cross-sectional view of the method of manufacturing the display panel provided in the present disclosure. The present disclosure further provides the method of manufacturing the display panel, which comprises following steps: 21, a flexible substrate100is provided. 22, an array layer200, a pixel definition layer300, and an insulating layer400are sequentially formed on the flexible substrate100. Material of the pixel definition layer300comprises acrylic-based materials or epoxy-based materials. Material of the insulating layer400comprises SiOx and SiNx. 23, the pixel definition layer300and the insulating layer400are etched to form a plurality of first through holes410and a plurality of second through holes420, and each of the first through holes410and each of the second through holes420penetrate the pixel definition layer300and the insulating layer400to expose the array layer200. Specifically, the pixel definition layer300and the insulating layer400are exposed to light and first pre-made holes411and second pre-made holes421are formed by etching. Then, the pixel definition layer300is etched. The first pre-made holes411form the first through holes410. The second pre-made holes421form the second through holes420. The first through holes410and the second through holes420are alternately arranged. Top diameters R1of the second through holes420are less than bottom diameters R2. 24, a light-emitting layer500is formed in the first through holes410. Specifically, a light-emitting material is evaporated in the first through holes410to form the light-emitting layer500. The light-emitting layer500comprises one of a red light-emitting layer510, a green light-emitting layer520, or a blue light-emitting layer530. 25, an additional layer material is evaporated on the pixel definition layer300, in the second through holes420, and on the insulating layer400and the light-emitting layer500by an evaporation method to form an additional layer600. A plurality of additional portions610are divided into first parts611and second parts612, the first parts611and the second parts612are not connected. The first parts611are disposed on the pixel definition layer300and the light-emitting layer500, and the second parts612are disposed in the second through holes420. Specifically, the additional layer600comprises an electron transport layer, an electron injection layer, and a cathode layer. A distance L from one end of each of the second parts612to an opposite end of the second part612is less than the bottom diameter R2of the second through hole420. 26, a first inorganic layer700covers the array layer200, the second through holes420, and the additional layer600. Specifically, a first inorganic layer material is disposed on the array layer200, in the second through holes420, and on the additional layer600to form the first inorganic layer700. Material of the first inorganic layer700comprises one or a combination of SiOx, Al2O3, and SiNx. After the step of forming the first inorganic layer700on the array layer200, in the second through holes420, and on the additional layer600, the method further comprises disposing an organic layer material on the first inorganic layer700to form an organic layer800. Material of the organic layer800comprises acrylic-based materials or epoxy-based materials. After the step of forming the organic layer800on the first inorganic layer700, the method further comprises disposing a second inorganic layer material on the organic layer800to form a second inorganic layer900. Material of the second inorganic layer comprises one or a combination of SiOx, Al2O3, and SiNx. The present disclosure provides a display panel and a manufacturing method thereof. In the display panel, the second through holes are set such that the top diameters R1are less than the bottom diameters R2, and the distance L from one end of each of the second parts in the second through hole to an opposite end of the second part is less than the bottom diameter R2of the second through hole, so that the second parts do not completely fill the second through holes and expose part of the array layer. In addition, the first inorganic layer is disposed on the array layer and the additional layer, and the second parts in the second through holes are covered by the first inorganic layer and the array layer. The adhesion between the array layer and the first inorganic layer is very strong since the two are formed of inorganic materials, and thus peeling of film layers are reduced during bending of the display panel, thereby improving the service life of the display panel. The above are only examples of the present disclosure and do not limit the scope of the present disclosure. Any equivalent structure or equivalent process transformation made using the description and drawings of the present disclosure, or directly or indirectly applied to other related technical fields, are included in the scope of patent protection of the present disclosure. | 11,699 |
11943973 | DETAILED DESCRIPTION In order to make the above purposes, features and advantages of the present disclosure more apparent and understandable, the present disclosure will be described in further detail below with reference to the drawings and the particular embodiments. Apparently, the described embodiments are merely certain embodiments of the present disclosure, rather than all of the embodiments. All of the other embodiments that a person skilled in the art obtains on the basis of the embodiments of the present disclosure without paying creative work fall within the protection scope of the present disclosure. Some embodiments of the disclosure provide a display panel. Referring toFIGS.1and2, the display panel may comprise a plurality of first-color subpixels11, and each first-color subpixel11comprises a base21, the base21comprising a first driving electrode10and a second driving electrode12; a flat layer22disposed on the side, near the first driving electrode and the second driving electrode, of the base21; a patterned passivation layer24and at least one first electrode23disposed on the side, away from the base21, of the flat layer22, the first electrode23being connected with the first driving electrode through via holes penetrating the flat layer22; and at least one second electrode25disposed on the side, away from the base21, of the passivation layer24, the second electrode25being connected with the second driving electrode through via holes penetrating the passivation layer24and the flat layer22. The first-color subpixel11may be a red R/green G/blue B subpixel. The first electrode23and the second electrode25may be an anode or a cathode. The base21may comprise a substrate and the first driving electrode and the second driving electrode which are disposed on one side of the substrate, and the flat layer22is disposed on the side, close to the first driving electrode and the second driving electrode, of the base21. The first driving electrode and the second driving electrode may be an active driving electrode, such as a source or drain of a thin film transistor, and can also be a passive driving electrode. Any driving electrode which can drive the first electrode23and the second electrode25separately is within the protection scope of this embodiment. The first electrode23is located on the side, away from the base21, of the flat layer22, and is connected with the first driving electrode through the via holes formed in the flat layer22. The passivation layer24covers the exposed areas of the first electrode23and the flat layer22, and allows a surface of the first electrode23to be exposed at a corresponding position of the first electrode23. The second electrode25is disposed on the side, away from the base21, of the passivation layer24, and is connected with the second driving electrode through the via holes formed in the flat layer22and the passivation layer24. Referring toFIG.1, the first electrodes23and the second electrodes25may be arranged in an array in the first-color subpixels11. Referring toFIG.2, the first electrodes23and the second electrodes25are stacked on different layers of the display panel. The first electrode23and the second electrode25divide the first-color subpixel11into a plurality of secondary pixels, such as the secondary pixels corresponding to the first electrode23and the secondary pixels corresponding to the second electrode25. Since the first electrode23and the second electrode25are insulated from each other and connected with different driving electrodes, the display of each secondary pixel can be independently controlled. In the process of 3D display, by means of the grating type glasses-free 3D technology or cylindrical lens 3D display technology, light emitted by some secondary pixels can be controlled to enter the left eye and light emitted by some other secondary pixels enters the right eye; for example, light emitted by the secondary pixels corresponding to the first electrode23enters the left eye and light emitted by the secondary pixels corresponding to the second electrode25enters the right eye, so as to realize high-resolution 3D glasses-free display and overcome the defects of existing 3D display products such as low PPI, insufficient information and small 3D viewing angle. According to the display panel provided in this embodiment, the first-color subpixel (R/GB subpixel) is finely patterned into the plurality of secondary pixels, such as the secondary pixels corresponding to the first electrode23and the secondary pixels corresponding to the second electrode25, and the electrodes of each secondary pixel are insulated from each other and connected with different driving electrodes respectively, so that the display of each secondary pixel can be driven independently. The display panel provided by the disclosure can realize high-resolution and high-definition glasses-free 3D display by using the grating type glasses-free 3D technology or cylindrical lens 3D display technology, can display more information and has a larger 3D viewing angle. To further enhance the 3D glasses-free display effect, when there are multiple first electrodes23and/or second electrodes25, the front projections of the first electrodes23on the base21and the front projections of the second electrodes25on the base21can be alternately arranged, as shown inFIG.1. Further, the number of the first electrodes23and the number of the second electrodes25can be set to be the same, so that the numbers of rows and columns of the secondary pixels included in the first-color subpixel11are both even, and it can be ensured that the number of the secondary pixels whose light enters the left eye is the same as that of the secondary pixels whose light enters the right eye. For example, the first-color subpixel11can be divided into 4*4 secondary pixels (the number of the first electrodes23and the number of the second electrodes25are both 8), 4*6 secondary pixels (the number of the first electrodes23and the number of the second electrodes25are both 12), or 6*6 secondary pixels (the number of the first electrodes23and the number of the second electrodes25are both 18). In practical application, the arrangement of the first electrodes23and the second electrodes25can be designed according to actual conditions, and is not limited to the above array arrangement. The inventor found that when the front projections, on the base21, of a first electrode23and a second electrode25which are adjacent to each other are separated as shown inFIG.1, the moire pattern tends to occur due to a gap between the electrodes, as shown inFIG.3. In order to avoid the moire pattern, the gap between the electrodes needs to be reduced. In one implementation mode, the front projection of the first electrode23on the base21is adjacent to or partially overlaps with the front projection of the adjacent second electrode25on the base21, that is, the front projections, on the base21, of the first electrode23and the second electrode25which are adjacent to each other adjoin each other or partially overlap. It should be noted that the expression “the front projection of the first electrode on the base is adjacent to the front projection of the adjacent second electrode on the base” herein means that the front projection of the first electrode on the substrate and the front projection of the adjacent second electrode on the base have only one coincident line, for example, the front projection of the first electrode on the base is close to a first side of the front projection of the second electrode, the front projection of the second electrode on the base has a second side close to the front projection of the first electrode, and the first side and the second side coincide with each other. Meanwhile, in order to avoid coupling capacitance or display crosstalk at the overlapping part of the first electrode23and the second electrode25, when the front projection of the first electrode23on the base21partially overlaps with the front projection of the second electrode25on the base21, the overlapping width may be less than or equal to 2 μm. In this implementation mode, although the front projections of the adjacent first electrode23and second electrode25on the base21are close to or overlap with each other, short circuiting between the first electrode23and the second electrode25can be avoided due to the passivation layer24arranged therebetween. The thickness of the passivation layer24may be greater than or equal to 50 nm and less than or equal to 250 nm, and the material of the passivation layer may be, for example, insulating materials such as SiNx and SiOx. The material of the first electrode23and the second electrode25may be ITO/Ag/ITO, ITO/Mo/ITO, ITO/Al/ITO, ITO/ALNb/ITO, Mo/Al/Mo, Mo/Ag/Mo, Mo/AlNd/Mo, etc. The thickness of ITO on both sides can be 8 nm, the thickness of an intermediate metal layer (such as Ag or AlNd) can be 100 nm, and the specific thickness can be set according to the actual situation. In the implementation process, the inventor found that the etching rate of ITO is different from that of the intermediate metal layer, and ITO, near the passivation layer24, of the second electrode25tends to overlap with the first electrode23to cause short circuiting. Therefore, in order to avoid short circuiting, the second electrode25may comprise a metal layer arranged on the side, away from the base21, of the passivation layer24, and ITO covering the side, away from the base21, of the metal layer, and the metal layer may be made of at least one of Ag, AlNd and Al. Experiments show that the second electrode25is not provided with ITO in contact with the passivation layer24, which can effectively avoid the short circuiting problem. In an implementation mode, as shown inFIGS.7A and7B, the base21comprises a substrate and a first thin film transistor and a second thin film transistor which are disposed on the side, near the flat layer22, of the substrate, the first driving electrode is a source or drain (SD1) of the first thin film transistor, and the second driving electrode is a source or drain (SD2) of the second thin film transistor. In the implementation mode, the first driving electrode and the second driving electrode are active driving electrodes. For example, in the embodiment shown inFIGS.7A and7B, the base21comprises a substrate (shown as Glass inFIG.7A), a buffer layer (shown as Buffer inFIG.7A) disposed on the substrate, and a plurality of thin film transistors disposed on the side, away from the substrate, of the buffer layer. The display panel comprises a flat layer (shown as PLN inFIG.7A) disposed on the side, away from the substrate, of the thin film transistors, a first electrode23(shown as AND1inFIG.7A) disposed on the side, away from the substrate, of the flat layer, a passivation layer (shown as PVX2inFIG.7A) disposed on the side, away from the substrate, of the first electrode23, and a second electrode25(shown as AND2inFIG.7A) disposed on the side, away from the substrate, of the passivation layer. The thin film transistor comprises an active layer, a gate insulating layer (shown as GI1inFIG.7A), a gate (shown as GATE inFIG.7A), and a source and a drain (shown as SD1and SD2inFIG.7A). The display panel also comprises a pixel defining layer (shown as PLN inFIG.7A). The pixel defining layer defines a plurality of openings in which electrodes such as the first electrode23and the second electrode25are located. The display panel may also comprise a luminescent layer and a cathode (shown as Cathode inFIG.7A). The luminescent layer may comprise a hole injection layer (shown as HIL inFIG.7A), a hole transporting layer (shown as HTL inFIG.7A), a luminescent material layer (shown as EML inFIG.7A), an electron transporting layer (shown as ETL inFIG.7A), and the like. The display panel may further comprise a packaging layer (shown as TFE inFIG.7A) for packaging the display panel. In one implementation mode, the shapes of the front projections of the first electrode23and the second electrode25on the base21are at least one of quadrangle, pentagon, hexagon and octagon. With reference toFIG.4, a planar structural diagram of a double-layer electrode structure is shown. Through the double-layer electrode structural design (the first electrode23is anode1and the second electrode25is anode2), electrode spacing can be reduced. For example, the front projections of adjacent electrodes on the base21are set to adjoin each other or partially overlap, thereby increasing the luminous area of the secondary pixels, prolonging the life of EL devices indirectly and avoiding the generation of the moire pattern. Since the electrode inFIG.4is hexagonal, there is still a dark area (as shown by “non-luminous hole” inFIG.4) after the double-layer electrodes are spliced. Further, the front projections of the first electrode23and the second electrode25on the base21may be rectangular. FIG.5Ashows a cross-sectional view of a four-layer electrode structure, andFIG.5BandFIG.6show a planar structural diagram of a four-layer electrode structure respectively. A passivation layer is arranged between every two adjacent layers of electrodes (anode1and anode2, anode2and anode3, and anode3and anode4). Since the electrodes are rectangular, by reducing electrode spacing, for example, setting the front projections of adjacent anodes on the base21to adjoin each other or partially overlap, the seamless design of the secondary pixels can be realized, and continuous light emission between the secondary pixels in the sub-pixels can be realized. Referring toFIGS.5A,5B and6, the base may further comprise a third driving electrode13and a fourth driving electrode14. The subpixel may further comprise a first passivation layer28disposed on the side, away from the base, of the second electrode25, at least one third electrode26disposed on the side, away from the base, of the first passivation layer28, a second passivation layer29disposed on the side, away from the base, of the third electrode26, and at least one fourth electrode27disposed on the side, away from the base, of the second passivation layer29. The third electrode26is connected with the third driving electrode13through via holes penetrating the first passivation layer, the passivation layer and the flat layer. The fourth electrode27is connected with the fourth driving electrode14through via holes penetrating the second passivation layer, the first passivation layer, the passivation layer and the flat layer. As shown inFIGS.5B and6, the front projections of the at least one first electrode23, the at least one second electrode25, the at least one third electrode26and the at least one fourth electrode27on the base are distributed in an array along a first direction and a second direction (for example, the horizontal direction and the vertical direction shown inFIGS.5B and6), and the first direction and the second direction intersect. The front projections of the at least one first electrode23, the at least one second electrode25, the at least one third electrode26and the at least one fourth electrode27on the base are alternately arranged in the first direction. The combination of the front projections of the at least one first electrode23, the at least one second electrode25, the at least one third electrode26and the at least one fourth electrode27on the base is a continuously extending pattern. It should be noted that the “continuously extending pattern” here means that the pattern is complete with no gap or blank. By stacking the first electrode23and the second electrode25, the gap between the electrode layers of the secondary pixels can be reduced, the luminous area of the secondary pixels in the subpixels can be increased, and the serious moire effect caused by the large space between the electrodes can be avoided. When the first electrode23and the second electrode25are rectangular, continuous light emission in the subpixels can be realized. In an implementation mode, each first-color subpixel may further comprise a luminescent layer, a cathode and a packaging layer disposed on the side, away from the base21, of the first electrode23and the second electrode25. In order to avoid display crosstalk, the luminescent layer is discontinuous at the junction of the first electrode23and the second electrode25, and the first electrode23and the second electrode25are anodes. The cathode is continuous at the junction of the first electrode23and the second electrode25. In the implementation mode, the display panel is an OLED display panel, which may be of a top emission structure or a bottom emission structure. When the OLED display panel is of a top emission structure, the first electrode23and the second electrode25(anode) can be reused as reflective layers, and can be made of ITO/Ag/ITO, ITO/Mo/ITO, Mo/AL/Mo, Mo/ALNb/Mo, ITO/AL/ITO, Mo/Ag/ITO, etc. The anodes in the R/G/B subpixels are patterned in the top-emitting OLED display panel, and the corresponding secondary pixels are driven independently by a plurality of anodes (the first electrode23and the second electrode25), so that the number of the secondary pixels in the subpixel is maximized, for example, 4×4 secondary pixel division can be realized on the basis of retina resolution (326 PPI), thereby improving the 3D display resolution and image quality of the OLED. By making the front projections of adjacent anodes on the base21adjoin each other or partially overlap, the luminous area of the secondary pixels is increased, the service life of EL devices is prolonged indirectly, and the generation of the moire pattern is avoided. In actual application, the base21may also comprise a GOA (gate driver on array), an EOA (EM GOA), a driving circuit, a compensation circuit and other structures disposed on the substrate. According to the technical solution disclosed by the disclosure, the subpixel electrodes are finely patterned again, and the structural design of the laminated electrodes (the first electrode23and the second electrode25) can further increase the luminous area of the secondary pixels corresponding to the first electrode23and the second electrode25, reduce the proportion of non-luminous areas of the subpixels, reduce the gap between the secondary pixel electrodes, enable the secondary pixels to emit light continuously, and minimize the influence of the moire pattern, thus solving the problems of low visual resolution and discontinuous view of the glasses-free 3D technology at present, and making the 3D view larger and more life-like. Other embodiments of the disclosure also provide a displaying device, which comprises the display panel according to any of the embodiments. It should be noted that the displaying device in this embodiment can be any product or component with a 2D or 3D display function, such as display panel, electronic paper, mobile phone, tablet computer, TV set, notebook computer, digital photo frame and navigator. For products with the 3D display function, the glasses-free 3D technology can be divided into the grating type glasses-free 3D technology and the cylindrical lens 3D display technology according to different display principles. The displaying device based on the grating type glasses-free 3D technology has attracted the attention of the display industry because of its simple manufacturing process, low-level crosstalk and low production cost. This displaying device uses a parallax barrier similar to the grating effect between a backlight module and a display panel to generate alternately bright and dark stripes, the light of each bright stripe passes through the display panel to form a view into the left eye of the viewer and a view into the right eye of the viewer, and because each bright stripe emits light from two angles to form the left view and the right view which are two images with parallax, the viewer can see a 3D image without wearing 3D glasses after the left view and the right view with parallax are superimposed and regenerated in the viewer's brain. Other embodiments of the disclosure also provide a preparation method of a display panel, wherein the display panel comprises a plurality of first-color subpixels. Referring toFIG.8, a preparation method of each first-color subpixel may comprise: Step801, providing a base, wherein the base comprises a first driving electrode and a second driving electrode. The base may comprise a substrate and the first driving electrode and the second driving electrode formed on one side of the substrate. Step802, forming a flat layer on the side, near the first driving electrode and the second driving electrode, of the base. Step803, forming at least one first electrode on the side, away from the base, of the flat layer, wherein the first electrode is connected with the first driving electrode through via holes penetrating the flat layer. Specifically, a patterning process can be adopted to form the first electrode on the flat layer. For example, a first electrode material layer is sputtered on the flat layer, and then patterned by a series of processes such as exposure and development to obtain one or more first electrodes. Step804, sequentially forming a passivation layer and at least one second electrode on the side, away from the base, of the flat layer, wherein the second electrode is connected with the second driving electrode through via holes penetrating the passivation layer and the flat layer. The via holes formed in the passivation layer and the flat layer for connecting the second electrode with the second driving electrode can be formed twice. For example, the via holes in the flat layer can be formed before preparing the passivation layer, and the via holes penetrating the passivation layer and the flat layer can be formed after the passivation layer is prepared. The via holes penetrating the passivation layer and the flat layer can also be formed at one time after the passivation layer is prepared. The preparation method provided in the embodiment can be used to prepare the display panel described in any of the above embodiments. In an implementation mode, referring toFIG.9, Step804may specifically comprise: Step901, forming passivation material layers on the side, away from the base, of the flat layer and the side, away from the base, of the first electrode. Step902, forming at least one second electrode on the side, away from the base, of the passivation material layer by a patterning process, wherein the front projection of the second electrode on the base is adjacent to or partially overlaps with the front projection of the adjacent first electrode on the base. Step903, removing the passivation material layer on the side, away from the base, of the first electrode through dry etching by a self-alignment process to obtain the passivation layer. A first electrode layer Anode1and s second electrode layer Anode2are formed by the patterning process, and a PVX passivation layer is added therein. After the second electrode layer is formed, the PVX on the Anode1is removed through dry etching by means of the self-alignment process of the second electrode layer Anode2, so that the first electrode layer is exposed, which minimizes the gap between the laminated electrodes due to the limitation of the Photo OL level and achieves seamless splicing of the two layers of secondary pixel electrodes. Referring toFIG.11, a schematic diagram of each process stage of a preparation method of a display panel is shown. It should be noted that, considering factors such as actual process errors, in order to make the gap between the prepared first electrode layer and the second electrode layer zero, an overlap between the first electrode layer and the second electrode layer can be set at the design stage, for example, the overlap is greater than 0.8 μm. In specific implementation, referring toFIG.10, the preparation method provided in the embodiment may further comprise: Step1001, forming a luminescent layer on the side, away from the base, of the first electrode and the second electrode, wherein the luminescent layer is discontinuous at the junction of the first electrode and the second electrode. Step1002, forming a cathode on the side, away from the base, of the luminescent layer in a covering mode, wherein the first electrode and the second electrode are anodes. The cathode is continuous at the junction of the first electrode and the second electrode. The embodiments provide a preparation method of a display panel, a display panel and a displaying device. The first-color subpixel (R/G/B subpixel) is patterned again into the plurality of secondary pixels, such as the secondary pixels corresponding to the first electrode and the secondary pixels corresponding to the second electrode, and the electrodes of each secondary pixel are connected with different driving electrodes respectively, so that the display of each secondary pixel can be driven independently. The display panel provided by the disclosure can realize high-resolution and high-definition glasses-free 3D display by using the grating type glasses-free 3D technology or cylindrical lens 3D display technology. Further, through the seamless splicing of the adjacent first electrode and second electrode, the secondary pixels in the sub-pixels can emit light continuously, and the generation of the moire pattern is avoided. All the embodiments in this specification are described in a progressive way, and each embodiment focuses on the differences from other embodiments. The same and similar parts among the embodiments are referable to one another. Finally, it should be noted that relational terms such as first and second are only used herein to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Further, the terms “comprise”, “include” or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, commodity or device. Without further restrictions, the elements defined by the sentence “comprise one . . . ” do not exclude the existence of other identical elements in the process, method, commodity or device comprising the elements. The preparation method of the display panel, the display panel, and the displaying device provided by the disclosure are described in detail above. Specific examples are applied herein to illustrate the principle and implementation of the disclosure. The above embodiments are only used to help understand the method of the disclosure and its core ideas. For those of ordinary skill in the art, according to the idea of this disclosure, there will be some changes in the specific implementation and application scope. To sum up, the contents of this specification should not be understood as a limitation of this disclosure. The description provided herein describes many concrete details. However, it can be understood that the embodiments of the present disclosure may be implemented without those concrete details. In some of the embodiments, well-known processes, structures and techniques are not described in detail, so as not to affect the understanding of the description. Finally, it should be noted that the above embodiments are merely intended to explain the technical solutions of the present disclosure, and not to limit them. Although the present disclosure is explained in detail by referring to the above embodiments, a person skilled in the art should understand that he can still modify the technical solutions set forth by the above embodiments, or make equivalent substitutions to part of the technical features of them. However, those modifications or substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present disclosure. | 28,223 |
11943974 | DETAILED DESCRIPTION Reference will now be made in more detail to aspects of some example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, in the present specification, “at least one of A and B” indicates only A, only B, both A and B, or variations thereof. It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto. When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. In the present specification, “A and/or B” means A or B, or A and B. It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component and/or may be “indirectly connected” to other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component and/or may be “indirectly electrically connected” to other layer, region, or component with other layer, region, or component interposed therebetween. FIG.1is a perspective view of a display device1according to some example embodiments. Referring toFIG.1, the display device1includes a first area OA and a display area DA, which is a second area at least partially surrounding the first area OA. The display device1may provide an image (e.g., a set or predetermined image) by using light emitted from a plurality of pixels arranged (e.g., located or placed) in the display area DA. The first area OA may be entirely surrounded by the display area DA. The first area OA may be an area in which a component described below with reference toFIG.2is arranged or located. A middle area MA as a third area may be arranged (e.g., located) between the first area OA and the display area DA, which is the second area. The display area DA may be surrounded by a peripheral area PA, which is a fourth area. According to some example embodiments the middle area MA and the peripheral area PA may be a non-display area in which pixels are not placed. The middle area MA may be entirely surrounded by the display area DA, and the display area DA may be entirely surrounded by the peripheral area PA. Hereinafter, though an organic light-emitting display device is described as an example of the display device1according to some example embodiments, the display device is not limited thereto. According to some example embodiments, the display device1may be a display device such as an inorganic light-emitting display and a quantum dot light-emitting display. Though it is shown inFIG.1that one first area OA is provided and has a circular shape, the embodiments are not limited thereto. The number of first areas OA may be two or more. Each first area OA may have various shapes such as a circular shape, an elliptical shape, a polygonal shape, a star shape, and a diamond shape. FIGS.2and3are cross-sectional views of the display device1according to some example embodiments, respectively, taken along the line II-II′ ofFIG.1. Referring toFIG.2, the display device1may include a display panel10, an input sensing layer40, and an optical functional layer50placed on the display panel10. The display panel10, the input sensing layer40, and the optical functional layer50may be covered by a window60. The display device1may be various kinds of electronic apparatuses such as mobile phones, notebook computers, and smartwatches. The display panel10may display an image. The display panel10includes pixels located in the display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may be an organic light-emitting diode or a quantum dot organic light-emitting diode. The input sensing layer40obtains coordinate information corresponding to an external input, for example, a touch event. The input sensing layer40may include a sensing electrode (or a touch electrode) and trace lines, the trace lines being connected to the sensing electrode. The input sensing layer40may be on the display panel10. The input sensing layer40may sense an external input by using a mutual cap method and/or a self cap method. In some embodiments, the input sensing layer40may be directly on the display panel10, or separately formed and then coupled to the display panel10by using an adhesive layer such as an optically clear adhesive. For example, the input sensing layer40may be successively formed after a process of forming the display panel10. In this case, the input sensing layer40may be a portion of the display panel10and an adhesive layer may not be placed between the input sensing layer40and the display panel10. Though it is shown inFIG.2that the input sensing layer40is located between the display panel10and the optical functional layer50, the input sensing layer40may be on the optical functional layer50in some other embodiments. The optical functional layer50may include a reflection prevention layer. The reflection prevention layer may reduce reflectivity of the light (e.g., external light) incident towards/on the display panel10from the outside through the window60. The reflection prevention layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystals placed in a set or predetermined arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves, or a protective film may be defined as a base layer of the reflection prevention layer. In some other embodiments, the reflection prevention layer may include a black matrix and color filters. The color filters may be placed by taking into account colors of light emitted respectively from the pixels of the display panel10. In some other embodiments, the reflection prevention layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer respectively placed on different layers. First-reflected light and second-reflected light respectively reflected by the first reflection layer and the second reflection layer may create destructive-interference and thus the reflectivity of external light may be reduced. The optical functional layer50may also include a lens layer. The lens layer may improve emission efficiency of the light emitted from the display panel10or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape and/or include a plurality of layers having different refractive indexes. The optical functional layer50may include both the reflection prevention layer and the lens layer, or one of these layers. In an embodiment, the optical functional layer50may be successively formed after a process of forming the display panel10and/or the input sensing layer40. In this case, an adhesive layer may not be placed between the optical functional layer50and the display panel10and/or the input sensing layer40. The display panel10, the input sensing layer40, and/or the optical functional layer50each may include an opening. With regard to this, it is shown inFIG.2that the display panel10, the input sensing layer40, and the optical functional layer50respectively include a first opening10H, a second opening40H, and a third opening50H, the first opening, the second opening40H, and the third opening50H overlapping one another. The first opening10H, the second opening40H, and the third opening50H may correspond to the first area OA. In some other embodiments, at least one of the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening. For example, one or two of the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening. Alternatively, as shown inFIG.3, the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening. As described above, the first area OA may be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which a component20is located, the component20may add various functions to the display device1. As shown inFIG.2, the component20may be located inside the first to third openings10H,40H, and50H. Alternatively, as shown inFIG.3, the component20may be located below the display panel10. The component20may include an electronic element. For example, the component20may include an electronic element that uses light or sound. For example, an electronic element may be a sensor such as an infrared sensor that emits and/or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance or recognize a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. An electronic element that uses light may use light in various wavelength bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first area OA may be a transmission area through which light and/or sound, which are output from the component20to the outside or propagate toward the electronic element from the outside, may pass. In the case where the display device1is used as a smartwatch or as an instrument panel for an automobile, the component20may be a member such as clock hands or a needle indicating set or predetermined information (e.g., the velocity of a vehicle, etc.). In the case where the display device1includes clock hands or an instrument panel for an automobile, the component20may pass through the window60and may be exposed to the outside. In such a case, the window60may include an opening corresponding to the first area OA. The component20may include an element(s) related to a function of the display panel10as described above, or may include an element such as an accessory that increases the aesthetic sense of the display panel10. Though not shown inFIGS.2and3, a layer including an optically clear adhesive may be located between the window60and the optical functional layer50. FIGS.4A-4Dare cross-sectional views of a display panel according to an embodiment. Referring toFIG.4A, the display panel10includes a display layer200located on a substrate100. The substrate100may include a glass material or a polymer resin. The substrate100may include a multi-layer. For example, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104as shown in an enlarged view ofFIG.4A. The first base layer101and the second base layer103each may include a polymer resin. For example, the first base layer101and the second base layer103may include a polymer resin including polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose tri acetate (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent. The first barrier layer102and the second barrier layer104are barrier layers reducing or preventing the penetration of external foreign substances and may include a single layer or a multi-layer including an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiOx). The display layer200may include a plurality of pixels. The display layer200may include a display element layer200A and a pixel circuit layer200B, the display element layer200A including a display element for each pixel, and the pixel circuit layer200B including a pixel circuit and insulating layers for each pixel. The display element layer200A may include a pixel electrode, an opposite electrode, and a stacked structure therebetween. Each display element may be an organic light-emitting diode OLED. Each pixel circuit (e.g.,200B) may include a thin film transistor and a storage capacitor. Display elements of the display layer200may be covered by an encapsulation member such as a thin-film encapsulation layer300. The thin-film encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the case where the display panel10includes the substrate100and the thin-film encapsulation layer300, the substrate100including a polymer resin, and the thin-film encapsulation layer300including an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display panel10may be improved. The display panel10may include the first opening10H passing through the display panel10. The first opening10H may be located in the first area OA. In this case, the first area OA may be an opening area. It is shown inFIG.4Athat the substrate100and the thin-film encapsulation layer300respectively include through holes100H and300H each corresponding to the first opening10H of the display panel10. The display layer200may include a through hole200H corresponding to the first area OA. In some other embodiments, as shown inFIG.4B, the substrate100may not include a through hole corresponding to the first area OA. The display layer200may include the through hole200H corresponding to the first area OA. The thin-film encapsulation layer300may not include a through hole corresponding to the first area OA. In some other embodiments, as shown inFIG.4C, the display layer200may not include the through hole200H corresponding to the first area OA. Though it is shown inFIGS.4A-4Cthat the display element layer200A is not located in the first area OA, the embodiments are not limited thereto. In some other embodiments, as shown inFIG.4D, an auxiliary display element layer200C may be located in the first area OA. The auxiliary display element layer200C may include a display element that has a structure that is different from that of the display element of the display element layer200A and/or operates in a way that is different from that of the display element of the display element layer200A. In an embodiment, each pixel of the display element layer200A may include an active-type organic light-emitting diode, and the auxiliary display element layer200C may include pixels each including a passive-type organic light-emitting diode. In the case where the auxiliary display element layer200C includes a passive-type organic light-emitting diode as a display element, there is no element constituting a pixel circuit below the passive-type organic light-emitting diode. For example, a portion of the pixel circuit layer200B under the auxiliary display element layer200C does not include a transistor and a storage capacitor. In some other embodiments, though the auxiliary display element layer200C may include the same type of display element (e.g., an active-type organic light-emitting diode) as that of the display element layer200A, a structure of a pixel circuit therebelow may be different. For example, a pixel circuit (e.g., a pixel circuit including a light-blocking layer between a substrate and a transistor) below the auxiliary display element layer200C may have a structure different from that of a pixel circuit below the display element layer200A. Alternatively, display elements of the auxiliary display element layer200C may operate according to a control signal different from a control signal of the display elements of the display element layer200A. A component (e.g., an infrared sensor) that does not require a relatively high transmittance may be located in the first area OA in which the auxiliary display element layer200C is located. In this case, the first area OA may be a component area and an auxiliary display area. FIG.5is a plan view of a display panel10according to an embodiment, andFIG.6is an equivalent circuit representation of one of the pixels in a display panel according to an embodiment. Referring toFIG.5, the display panel10may include the first area OA, the display area DA, which is the second area, the middle area MA, which is the third area, and the peripheral area PA, which is the fourth area.FIG.5illustrates the substrate100of the display panel10. For example, the substrate100may include the first area OA, the display area DA, the middle area MA, and the peripheral area PA. The display panel10includes a plurality of pixels P placed in the display area DA. As shown inFIG.6, each pixel P may include a pixel circuit PC and an organic light-emitting diode OLED as a display element, the display element being connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, blue, or white light from an organic light-emitting diode OLED. The second thin film transistor T2may include a switching thin film transistor, may be connected to a scan line SL and a data line DL, and may transfer a data voltage input to the data line DL to the first thin film transistor T1based on a switching voltage input to the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2and a driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transferred from the second thin film transistor T2and a first power voltage ELVDD supplied through the driving voltage line PL. The first thin film transistor T1is a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage value (or charge) stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a set or predetermined brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS. Though it is shown inFIG.6that the pixel circuit PC includes two thin film transistors and one storage capacitor, the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously modified depending on a design of the pixel circuit PC. For example, the pixel circuit PC may further include four or more thin film transistors in addition to the two thin film transistors. Referring toFIG.5again, the middle area MA may surround the first area OA in a plan view. The middle area MA is an area in which a display element such as an organic light-emitting diode that emits light is not placed. Signal lines may pass across the middle area MA, the signal lines providing a signal to the pixels P located around the first area OA. A scan driver1100, a data driver1200, and a main power line (not shown) may be placed in the peripheral area PA, the scan driver1100providing a scan signal to each pixel P, the data driver1200providing a data signal to each pixel P, and the main power line providing a first power voltage and a second power voltage. Although it is shown inFIG.5that the data driver1200is adjacent to one side of the substrate100, the data driver1200may be located on a flexible printed circuit board (FPCB) electrically connected to a pad located on one side of the display panel10in some other embodiments. FIG.7is a plan view of a portion of a display panel according to an embodiment, andFIG.8is a cross-sectional view of an organic light-emitting diode of one of the pixels in a display panel according to an embodiment. For convenience of description, inFIG.8, a thin-film encapsulation layer, which is an encapsulation member, is omitted. Referring toFIG.7, pixels P are placed around the first area OA in the display area DA. The first area OA may be defined between (e.g., among) the pixels P. For example, pixels P may be vertically placed around the first area OA in a plan view, and pixels P may be horizontally placed around the first area OA in a plan view. As shown inFIG.8, each pixel P may include an organic light-emitting diode OLED. The organic light-emitting diode OLED may include a pixel electrode221, an opposite electrode223, and an intermediate layer222, the opposite electrode223facing the pixel electrode221, and the intermediate layer222being between the pixel electrode221and the opposite electrode223. The pixel electrode221is located on a planarization layer PNL. The pixel electrode221may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some other embodiments, the pixel electrode221may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In some other embodiments, the pixel electrode221may further include a layer including ITO, IZO, ZnO, or In2O3over/under the reflective layer. A pixel-defining layer PDL may be on the pixel electrode221. The pixel-defining layer PDL may include an opening that may expose a top surface of the pixel electrode221and cover edges of the pixel electrode221. The pixel-defining layer PDL may include an organic insulating material. Alternatively, the pixel-defining layer PDL may include an organic insulating material and an inorganic insulating material. The intermediate layer222includes an emission layer222b. The intermediate layer222may include a first functional layer222aunder the emission layer222band/or a second functional layer222con the emission layer222b. The emission layer222bmay include a polymer or low molecular weight organic material that emits light of a set or predetermined color. The first functional layer222amay include a single layer or a multi-layer. For example, in the case where the first functional layer222aincludes a polymer material, the first functional layer222amay be a hole transport layer (HTL), which has a single-layered structure. The first functional layer222amay include poly-(3, 4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer222aincludes a low molecular weight material, the first functional layer222amay include a hole injection layer (HIL) and a hole transport layer (HTL). In some embodiments, the second functional layer222cmay be optional. For example, in the case where the first functional layer222aand the emission layer222binclude a polymer material the second functional layer222cmay be formed. The second functional layer222cmay include a single layer or a multi-layer. The second functional layer222cmay include an electron transport layer (ETL) and/or an electron injection layer (EIL). The emission layer222bof the intermediate layer222may be placed for each pixel. For example, the emission layer222bmay be patterned to correspond to the pixel electrode221. Unlike the emission layer222b, each of the first functional layer222aand/or the second functional layer222cof the intermediate layer222may be formed as one body so as to correspond to a plurality of pixels An opposite electrode223may include a conductive material having a low work function. For example, the opposite electrode223may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the opposite electrode223may further include a layer including ITO, IZO, ZnO, or In2O3on the (semi) transparent layer including the above material. The opposite electrode223may be located in not only the display area DA but also the middle area MA. The first functional layer222a, the second functional layer222c, and the opposite electrode223may be formed by thermal deposition. A capping layer230may be located on the opposite electrode223. For example, the capping layer230may include LiF and be formed by thermal deposition. In an embodiment, the capping layer230may be omitted. A layer(s) including an organic material among layers provided to the display panel may provide a path through which moisture may propagate. The first functional layer222aand/or the second functional layer222cincluded in the stacked structure of the organic light-emitting diode OLED include an organic material and thus may provide a path through which moisture may propagate. However, because the first functional layer222aand/or the second functional layer222care disconnected or separated by grooves G (as shown inFIG.7) provided in the middle area MA, the above-described moisture transmission issue and damage to the organic light-emitting diode OLED may be prevented or reduced. As shown inFIG.7, one or more grooves G may be located in the middle area MA. As shown inFIG.7, in a plan view, grooves G may have a ring shape surrounding the first area OA and be apart from each other. A groove G may be located in a multi-layer including a plurality of layers, and the groove G that is concave in a depth direction of the multi-layer may have an undercut structure. The multi-layer and a structure of the groove G are described below with reference toFIGS.9A-9F. FIGS.9A-9Fare the cross-sectional views of one of the grooves in a display panel according to an embodiment. For convenience of description,FIGS.9A-9Fomit a thin-film encapsulation layer, which is an encapsulation member. Referring toFIGS.9A-9F, a multi-layer ML includes an upper layer UL, a lower layer LL. The lower layer LL and/or the upper layer UL including a plurality of sub-layers. Referring toFIGS.9A and9B, the multi-layer ML includes the lower layer LL and the upper layer UL. The lower layer LL may include a first sub-lower layer LL1and a second sub-lower layer LL2under the first sub-lower layer LL1. The upper layer UL may include a single layer. The lower layer LL and the upper layer UL may include different materials. For example, the first sub-lower layer LL1and the second sub-lower layer LL2may include an organic material, for example, an organic insulating material. The upper layer UL may include an inorganic material. The organic insulating material of the lower layer LL may include an organic insulating material including a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof. The inorganic material of the upper layer UL may include a material different from an organic material containing carbon element, the material including a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and/or AZO. Alternatively, the inorganic material of the upper layer UL may include a metal such as Mo, Al, Cu, and/or Ti. Alternatively, the inorganic material of the upper layer UL may include an insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride. The groove G may be located in a depth direction of the multi-layer ML. The groove G may include a top-hole UL-h passing through the upper layer UL, and a bottom-hole or a bottom-recess located in the lower layer LL. In an embodiment, as shown inFIG.9A, the groove G may include a top-hole UL-h of the upper layer UL, a first bottom-hole LL1-hof the first sub-lower layer LL1, and a second recess LL2-rof the second sub-lower layer LL2. Alternatively, as shown inFIG.9B, the groove G may include a top-hole UL-h of the upper layer UL, a first bottom-hole LL1-hof the first sub-lower layer LL1, and a second bottom-hole LL2-hof the second sub-lower layer LL2. A depth d of the groove G may be less than a thickness t of the lower layer LL, and a bottom surface of the groove G may be located between a top surface and a bottom surface of the second sub-lower layer LL2(seeFIG.9A). Alternatively, a depth d of the groove G may be equal to the thickness t of the lower layer LL, and the bottom surface of the groove G may be located on the same surface as a bottom surface of the second sub-lower layer LL2(seeFIG.9B). The groove G may have an undercut structure. Referring toFIGS.9A and9B, a first width W1of the top-hole UL-h may be less than a width of the lower layer LL, for example, a second width W2of the first bottom-hole LL1-hof the first sub-lower layer LL1. Ends of the upper layer UL that protrude toward the groove G, for example, a center of the groove G may constitute a pair of tips PT. A protruding length dl of each tip PT may be less than a depth d of the groove G. The protruding length dl of the tip PT may be less than 2 μm. For example, the protruding length dl of the tip PT may be about 1 μm to about 1.5 μm. The depth d of the groove G may be 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more. An organic material layer(s) included in the stacked structure of the organic light-emitting diode OLED (seeFIG.8) described with reference toFIGS.7and8may be disconnected or separated by the groove G. For example, as shown inFIGS.9A and9B, the first functional layer222aand the second functional layer222cmay be disconnected or separated around the groove G. Likewise, the opposite electrode223and the capping layer230may be disconnected or separated around the groove G. Though it is shown inFIGS.9A,9BandFIGS.9C-19discussed below that the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230are disconnected or separated around the groove G, the embodiments are not limited thereto. As described above, the second functional layer222cand/or the capping layer230may be omitted. In this case, there is no second functional layer222cand/or capping layer230around the groove G. As described with reference toFIGS.9A and9B, the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may be disconnected or separated by the groove G, and the multi-layer ML in which the groove G is located may have not only the structure shown inFIGS.9A and9Bbut also various structures described below with reference toFIGS.9C-9F. Referring toFIG.9C, the groove G is located in the multi-layer ML. A lower layer LL′ of the multi-layer ML may include a first sub-lower layer LL1, a second sub-lower layer LL2under the first sub-lower layer LL1, and a third sub-lower layer LL3under the second sub-lower layer LL2. Two or three of the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3may include different materials. For example, the first sub-lower layer LL1may include an organic insulating material, and the second sub-lower layer LL2and the third sub-lower layer LL3may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. Though it is shown inFIG.9Cthat the lower layer LL′ includes two inorganic insulating material layers, for example, the second sub-lower layer LL2and the third sub-lower layer LL3, the embodiments are not limited thereto. In some other embodiments, the lower layer LL′ includes the first sub-lower layer LL1and one or three or more sub-layer(s) placed under the first sub-lower layer LL1and including an inorganic insulating material. As described with reference toFIG.9A, the upper layer UL may include a single layer or a multi-layer and includes an inorganic material. The upper layer UL may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Alternatively, the upper layer UL may include a conductive oxide such as IZO or may include a metal such as Mo, Ti, and Cu. The groove G may have an undercut shape. A protruding length dl of a pair of tips PT that protrude toward a center of the groove G, a depth d of the groove G, and a characteristic in which the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230are disconnected around the groove G are the same as those described with reference toFIGS.9A and9B. Though it is shown inFIG.9Cthat a bottom surface of the groove G is located between a top surface and a bottom surface of the third sub-lower layer LL3, the bottom surface of the groove G may be located on the same surface as the bottom surface of the third sub-lower layer LL3in some other embodiments. Referring toFIG.9D, the groove G is located in the multi-layer ML, and as described with reference toFIG.9C, the lower layer LL′ of the multi-layer ML may include the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3. In some other embodiments, the lower layer LL′ ofFIG.9Dmay have the structure of the lower layer LL described with reference toFIGS.9A and9B. A upper layer UL′ of the multi-layer ML may include a first sub-upper layer UL1and a second sub-upper layer UL2on the first sub-upper layer UL1. The upper layer UL may include an inorganic material, and the first sub-upper layer UL1and the second sub-upper layer UL2may have different materials. For example, the first sub-upper layer UL1may include a conductive oxide such as IZO or may include a metal such as Al, Mo, and Ti. The second sub-upper layer UL2may include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. A lateral surface UL1-S of the first sub-upper layer UL1that faces the groove G may be covered by the second sub-upper layer UL2. The lateral surface UL1-S of the first sub-upper layer UL1may be alongside a lateral surface UL2-S of the second sub-upper layer UL2. In an embodiment, in the case where the first sub-upper layer UL1includes three layers of titanium, aluminum, and titanium, aluminum is damaged more than titanium during a process of manufacturing the display panel and thus unevenness may be formed in the lateral surface UL1-S of the first sub-upper layer UL1. In contrast, according to an embodiment, because the lateral surface UL1-S of the first sub-upper layer UL1is covered by the second sub-upper layer UL2, the lateral surface UL1-S of the first sub-upper layer UL1may be saved or prevented from being damaged. The first sub-upper layer UL1and the second sub-upper layer UL2may extend further to the center of the groove G than a lateral surface of the lower layer LL, thereby defining a pair of tips PT. A protruding length dl of each tip PT and the depth d of the groove G are the same as those described above. Though it is shown inFIG.9Dthat the bottom surface of the groove G is between a top surface and a bottom surface of the third sub-lower layer LL3, the embodiments are not limited thereto. In some other embodiments, similar to that described with reference toFIG.9B, the bottom surface of the groove G may be located on the same surface as the bottom surface of the third sub-lower layer LL3. Referring toFIG.9E, the upper layer UL′ of the multi-layer ML is the same as that described with reference toFIG.9Dand the multi-layer ML ofFIG.9Eis different from the multi-layer ML ofFIG.9Din that a lower layer LL″ is a single layer. The lower layer LL″ may include an organic insulating material. A depth d of the groove G may be equal to or less than a thickness of the lower layer LL″. Though it is shown inFIG.9Ethat the bottom surface of the groove G is between a top surface and a bottom surface of the lower layer LL″, the bottom surface of the groove G may be located on the same surface as the bottom surface of the lower layer LL″ in some other embodiments. Referring toFIG.9F, the lower layer LL of the multi-layer ML may include the first sub-lower layer LL1and the second sub-lower layer LL2as shown above inFIGS.9A and9B. In some other embodiments, the lower layer LL may include the bottom layers LL′ and LL″ as described with reference toFIGS.9C-9E. A upper layer UL″ of the multi-layer ML may include a plurality of layers. For example, the upper layer UL″ may include a first sub-upper layer UL1, a second sub-upper layer UL2on the first sub-upper layer UL1, and a third sub-upper layer UL3on the second sub-upper layer UL2. Two or more of the first sub-upper layer UL1, the second sub-upper layer UL2, and the third sub-upper layer UL3may include different materials. For example, the first sub-upper layer UL1and the third sub-upper layer UL3may include a conductive oxide such as IZO or a metal, and the second sub-upper layer UL2may include an insulating material such as silicon nitride. Alternatively, the first sub-upper layer UL1and the third sub-upper layer UL3may include an insulating material such as silicon nitride, and the second sub-upper layer UL2may include a conductive oxide such as IZO or a metal. Though it is shown inFIG.9Fthat the upper layer UL″ includes three sub-layers, the embodiments are not limited thereto. The upper layer UL″ may include two sub-layers including the first sub-upper layer UL1and the second sub-upper layer UL2. Alternatively, the upper layer UL″ may include four or more sub-layers. The first sub-upper layer UL1, the second sub-upper layer UL2, and the third sub-upper layer UL3extend further toward the center of the groove G than a lateral side of the lower layer LL, thereby defining a pair of tips PT. A protruding length dl of each tip PT and the depth d of the groove G are the same as those described above. Though it is shown inFIG.9Fthat the bottom surface of the groove G is between a top surface and a bottom surface of the second sub-lower layer LL2, the embodiments are not limited thereto. In some other embodiments, as described with reference toFIG.9B, the bottom surface of the groove G may be located on the same surface as the bottom surface of the second sub-lower layer LL2. FIG.10is a plan view of a portion of a display panel according to an embodiment. Referring toFIG.10, the middle area MA is between the first area OA and the display area DA, and a plurality of grooves G are located in the middle area MA. ThoughFIG.10shows three grooves G, the number of grooves G may be four or more. Lines may bypass around an edge of the first area OA in the middle area MA. Signal lines connected to pixels P apart from each other around the first area OA may extend along the edge of the first area OA in the middle area MA. In a plan view ofFIG.10, at least one data line DL passing across the display area DA may extend in a y-direction so as to provide a data signal to pixels P vertically placed around the first area OA and extend along the edge of the first area OA in the middle area MA. Similarly, at least one of scan lines SL passing across the display area DA may extend in an x-direction so as to provide a scan signal to pixels P horizontally placed around the first area OA and extend along the edge of the first area OA in the middle area MA. A bypass portion (or a circuitous portion) SL-D of the scan line SL may be located on the same layer on which an extension portion SL-L crossing (e.g., intersecting) the display area DA is placed and may be formed as one body. A bypass portion DL-D1of at least one (referred to as a first data line DL1, hereinafter) of data lines DL may be located on a layer different from a layer on which an extension portion DL-L1crossing the display area DA is located, and the bypass portion DL-D1of the data line DL may be connected to the extension portion DL-L1through a contact hole CNT. A bypass portion DL-D2of at least one (referred to as a second data line DL2, hereinafter) of the data lines DL may be located on the same layer on which an extension portion DL-L2is located and may be formed as one body. FIG.11is a cross-sectional view of a display panel according to an embodiment,FIGS.12A-12Care cross-sectional views of a process of manufacturing a display panel according to some example embodiments and show a middle area, andFIG.13is a cross-sectional view of one of the groove areas.FIG.11may correspond to a cross-section taken along the line X-X′ ofFIG.10. Referring toFIG.11, the middle area MA is between the first area OA and the display area DA, and a pixel circuit PC and an organic light-emitting diode OLED that correspond to each pixel P (seeFIG.10) are located in the display area DA. First, referring to the display area DA ofFIG.11, the substrate100may include a glass material or a polymer resin. In an embodiment, as shown in an enlarged view ofFIG.4A, the substrate100may include a plurality of sub-layers. A buffer layer201may be on the substrate100. The buffer layer201may reduce or prevent impurities from penetrating into a semiconductor layer Act of a thin film transistor TFT. The buffer layer201may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride and may also include a single layer or a multi-layer including the above mentioned inorganic insulating materials. A pixel circuit PC may be on the buffer layer201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include the semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. A data line DL of the pixel circuit PC may be electrically connected to a switching thin film transistor (not shown) included in the pixel circuit PC. Though the present embodiment shows a top gate-type thin film transistor TFT in which a gate electrode GE is placed over a semiconductor layer Act with a gate insulating layer203therebetween, the thin film transistor TFT may be a bottom gate-type thin film transistor TFT in an embodiment. The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. The gate insulating layer203between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer203may include a single layer or a multi-layer including the above materials. The source electrode SE and the drain electrode DE may be located on the same layer on which the data line DL is placed, and may include the same material as that of the data line DL. The source electrode SE, the drain electrode DE, and the data line DL may include a material having a relatively high (e.g., an excellent) conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. In an embodiment, the source electrode SE, the drain electrode DE, and the data line DL may each include a multi-layer of Ti/Al/Ti. The storage capacitor Cst may include a bottom electrode CE1and a top electrode CE2, the bottom electrode CE1overlapping the top electrode CE2with a first interlayer insulating layer205therebetween. The storage capacitor Cst may overlap the thin film transistor TFT. With regard to this, it is shown inFIG.11that the gate electrode GE of the thin film transistor TFT serves as the bottom electrode CE1of the storage capacitor Cst. In some other embodiments, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer207. The top electrode CE2of the storage capacitor Cst may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. The first interlayer insulating layer205and the second interlayer insulating layer207may include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first interlayer insulating layer205and the second interlayer insulating layer207may include a single layer or a multi-layer including the above materials. The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by a first organic insulating layer209. The first organic insulating layer209may include an approximately flat top surface. The pixel circuit PC may be electrically connected to the pixel electrode221. For example, as shown inFIG.11, a contact metal layer CM may be placed between the thin film transistor TFT and the pixel electrode221. The contact metal layer CM may be connected to the thin film transistor TFT through a contact hole in the first organic insulating layer209, and the pixel electrode221may be connected to the contact metal layer CM through a contact hole in a second organic insulating layer211on the contact metal layer CM. The contact metal layer CM may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. In an embodiment, the contact metal layer CM may include three layers of Ti/Al/Ti. The first organic insulating layer209and the second organic insulating layer211may include an organic insulating material including a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof. In an embodiment, the first organic insulating layer209and the second organic insulating layer211may include polyimide. The pixel electrode221may be located on the second organic insulating layer211. The second organic insulating layer211may be the planarization layer described above with reference toFIG.8. Edges of the pixel electrode221may be covered by a pixel-defining layer215. The pixel-defining layer215may include an opening that overlaps a central portion of the pixel electrode221. A spacer217may be located on the pixel-defining layer215. The spacer217may include a material different from that of the pixel-defining layer215or may include the same material as that of the pixel-defining layer215. In an embodiment, the pixel-defining layer215and the spacer217may include the same material and may be concurrently formed during a mask process that uses a halftone mask. In an embodiment, the pixel-defining layer215and the spacer217may include polyimide. The intermediate layer222includes the emission layer222b. The intermediate layer222may include the first functional layer222aand/or the second functional layer222c, the first functional layer222abeing under the emission layer222b, and the second functional layer222cbeing on the emission layer222b. The emission layer222bmay include a polymer or low molecular weight organic material that emits light having a set or predetermined color. The opposite electrode223may be located on the intermediate layer222, and the capping layer230may be located on the opposite electrode223. The capping layer230may be omitted. Materials, structures, and characteristics of the pixel electrode221, the intermediate layer222, and the opposite electrode223are the same as those described with reference toFIG.8. The organic light-emitting diode OLED is covered by the thin-film encapsulation layer300. The thin-film encapsulation layer300may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. It is shown inFIG.11that the thin-film encapsulation layer300includes a first and a second inorganic encapsulation layers310and330, and an organic encapsulation layer320therebetween. In some other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking sequence may be modified. The first and second inorganic encapsulation layers310and330may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon nitride, silicon oxide, and silicon oxynitride. The first and second inorganic encapsulation layers310and330may include a single layer or a multi-layer including the above materials. The organic encapsulation layer320may include a polymer-based material. The polymer-based material may include an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene. In an embodiment, the organic encapsulation layer320may include acrylate. A thickness of the first inorganic encapsulation layer310may be different from a thickness of the second inorganic encapsulation layer330. The thickness of the first inorganic encapsulation layer310may be greater than the thickness of the second inorganic encapsulation layer330. Alternatively, the thickness of the second inorganic encapsulation layer330may be greater than the thickness of the first inorganic encapsulation layer310, or the thickness of the first inorganic encapsulation layer310may be the same as the thickness of the second inorganic encapsulation layer330. Referring to the middle area MA ofFIG.11, the middle area MA may include a first sub-middle area SMA1and a second sub-middle area SMA2, the first sub-middle area SMA1being relatively distant from the first area OA, and the second sub-middle area SMA2being relatively close to the first area OA. Lines, for example, signal lines may be located in the first sub-middle area SMA1. The bypass portions DL-D1and DL-D2of the first and second data lines DL1and DL2described above with reference toFIG.10may be located in the first sub-middle area SMA1ofFIG.11. The first sub-middle area SMA1may be a line area and a bypass area in which the data lines DL bypass. The data lines DL located in the middle area MA described with reference toFIG.10may include the first data lines DL1and the second data lines DL2that are alternately placed on and under the first organic insulating layer209with the first organic insulating layer209therebetween. With regard to this, it is shown inFIG.11that the bypass portion DL-D1of the first data line DL1and the bypass portion DL-D2of the second data line DL2neighbor each other and are respectively placed on and under the first organic insulating layer209. In this case, a gap (or a pitch A d) between the first data line DL1and the second data line DL2that neighbor each other, for example, between the bypass portion DL-D1of the first data line DL1and the bypass portion DL-D2of the second data line DL2, may be reduced. Grooves G are located in the second sub-middle area SMA2. The grooves G are located in the multi-layer ML. In an embodiment, as shown inFIGS.11and12A, the multi-layer ML may include the first organic insulating layer209, the second organic insulating layer211, and an inorganic layer213. The first organic insulating layer209and the second organic insulating layer211may respectively correspond to the first sub-bottom layer and the second sub-bottom layer of the multi-layer ML described with reference toFIGS.9A and9B, and the inorganic layer213may correspond to the top layer. The inorganic layer213may include a material different from that of the pixel electrode221. The inorganic layer213may include a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and/or AZO, may include a metal such as Mo, Cu, and/or Ti, or may include an insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride. Referring toFIG.12A, the groove G may include a hole213hof the inorganic layer213, a hole211hof the second organic insulating layer211, and a recess209rof the first organic insulating layer209. In this case, a bottom surface of the groove G may be located between a top surface and a bottom surface of the first organic insulating layer209. In some other embodiments, the first organic insulating layer209may include a hole passing through the first organic insulating layer209instead of the recess209r. In this case, the bottom surface of the groove G may be placed on the same surface as the bottom surface of the first organic insulating layer209or a top surface of the second interlayer insulating layer207. The inorganic layer213may include a pair of tips PT extending toward the groove G. A protruding length dl of the tip PT may be less than about 2 μm as described above. A depth d of the groove G may be 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more. A partition wall PW may be located in the middle area MA. The partition wall PW may be located between grooves G that neighbor each other. The partition wall PW may be formed while a portion211P of a layer constituting the second organic insulating layer211, a portion215P of a layer constituting the pixel-defining layer215, and a portion217P of a layer constituting the spacer217are sequentially stacked (e.g., arranged). A height from a top surface of the substrate100to a top surface of the partition wall PW may be less than a height from the top surface of the substrate100to a top surface of the spacer217. The intermediate layer MA may include an inorganic contact region ICR. The inorganic contact region ICR may be located between the grooves G that neighbor each other. The inorganic contact region ICR is a region in which layers including an inorganic material directly contact each other. It is shown inFIG.11that the inorganic layer213directly contacts the second interlayer insulating layer207. The inorganic layer213may contact the second interlayer insulating layer207through openings209OP and211OP respectively located in the first organic insulating layer209and the second organic insulating layer211. A first groove G1, a second groove G2, and a third groove G3are formed before a process of forming the intermediate layer222is performed. The first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may be disconnected or separated by the grooves G as described above with reference toFIGS.11and12A-12B. Referring toFIG.12C, the first inorganic encapsulation layer310, the organic encapsulation layer320, and the second inorganic encapsulation layer330may be sequentially formed. The first inorganic encapsulation layer310may be formed by chemical vapor deposition, etc. Unlike the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230, the first inorganic encapsulation layer310has a relatively large (e.g., excellent) step coverage. Therefore, as shown inFIGS.11,12C, and13, the first inorganic encapsulation layer310may continuously cover an inner surface of the first groove G1. For example, the first inorganic encapsulation layer310may continuously extend so as to cover a top surface, a lateral surface, and a bottom surface of the inorganic layer213, a lateral surface of the second organic insulating layer211, and a lateral surface of the first organic insulating layer209. As shown inFIG.13, a first thickness t1of a first portion of the first inorganic encapsulation layer310on a top surface of the inorganic layer213may be greater than a second thickness t2of a second portion of the first inorganic encapsulation layer310under a bottom surface of the inorganic layer213. Also, the first thickness t1may be greater than a third thickness t3of a third portion of the first inorganic encapsulation layer310on a lateral surface of the second organic insulating layer211. The first inorganic encapsulation layer310may include a single layer or a plurality of sub-layers. For example, the first inorganic encapsulation layer310may include two layers of silicon oxynitride that have different membranous materials. In such a case, the capping layer230may be omitted. Alternatively, the first inorganic encapsulation layer310may include silicon oxynitride and silicon oxide, silicon oxynitride and silicon nitride, or silicon nitride and silicon oxide. As shown inFIGS.11and12C, the organic encapsulation layer320may cover a portion of the display area DA and the middle area MA. An end of the organic encapsulation layer320that neighbors the first area OA may be adjacent to one lateral surface of the partition wall PW. The second inorganic encapsulation layer330is located on the organic encapsulation layer320and may directly contact the first inorganic encapsulation layer310in the middle area MA. For example, the first inorganic encapsulation layer310may directly contact the second inorganic encapsulation layer330in an area between the first area OA and the partition wall PW. Similar to the first inorganic encapsulation layer310, the second inorganic encapsulation layer330may have relatively large (e.g., excellent) step coverage. Therefore, the second inorganic encapsulation layer330may continuously cover an inner lateral surface of the grooves G located between the first area OA and the partition wall PW. Similar to the first inorganic encapsulation layer310described inFIG.13, a thickness of a fourth portion of the second inorganic encapsulation layer330on a top surface of the inorganic layer213may be greater than a thickness of a fifth portion of the second inorganic encapsulation layer330under a bottom surface of the inorganic layer213. A structure shown inFIG.11may be a structure surrounding the first area OA in a plan view. For example, as shown inFIG.10, the grooves G ofFIG.11may have a ring shape surrounding the first area OA in a view in a direction perpendicular to the top surface of the substrate100. Similarly, the partition wall PW may have a ring shape surrounding the first area OA in a view in a direction perpendicular to the top surface of the substrate100. FIG.14is a cross-sectional view of a display panel according to an embodiment, taken along the line X-X′ ofFIG.10. A display panel10-2ofFIG.14may have a structure similar to that of the display panel10-1described with reference toFIG.11, etc. A difference is mainly described below. Referring toFIG.14, a multi-layer ML of the display panel10-2may include the first organic insulating layer209, the second organic insulating layer211, and an inorganic layer213′. The inorganic layer213′ may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. The first organic insulating layer209and the second organic insulating layer211may respectively correspond to the first sub-bottom layer and the second sub-bottom layer of the multi-layer ML described with reference toFIGS.9A and9B, and the inorganic layer213′ may correspond to the top layer. The inorganic layer213′ is located in the display area DA and may be formed during the same process as a process of forming a passivation layer212including an inorganic insulating material. The inorganic layer213′ includes a pair of tips PT extending toward the groove G, and a protruding length of the tip PT and structural characteristics of the groove G such as a depth of the groove G are the same as those described above. The middle area MA may include a plurality of inorganic contact regions ICR. With regard to this,FIG.14shows an inorganic contact region ICR that neighbors the partition wall PW, and an inorganic contact region ICR between grooves G that neighbor each other. The plurality of inorganic contact regions ICR described with reference toFIG.14are applicable to the embodiments described with reference toFIG.11, embodiments described with reference toFIGS.15-19, and embodiments derived therefrom. Though it is shown inFIG.14that the passivation layer212located in the display area DA is located on the second organic insulating layer211, the passivation layer212may be located under the second organic insulating layer211in some other embodiments. FIG.15is a cross-sectional view of the first area OA and the middle area MA in a display panel10-3according to an embodiment, taken along the line X-X′ ofFIG.10. The display panel10-3shown inFIG.15includes a plurality of grooves G located in the middle area MA, and a first groove G1among the plurality of grooves G that neighbors the display area DA may be located over signal lines. With regard to this, it is shown inFIG.15that the first groove G1overlaps the bypass portions DL-D1and DL-D2of the data lines extending along the edge of the first area OA. The grooves G located between the first area OA and the first groove G1may be defined in a multi-layer different from that of the first groove G1. The grooves G except for the first groove G1may be in a multi-layer (referred to as a first multi-layer ML1, hereinafter) including the first organic insulating layer209, the second organic insulating layer211, and the inorganic layer213. A specific structure thereof is the same as that described with reference toFIGS.11-13. The first groove G1may be in a multi-layer (referred to as a second multi-layer ML2, hereinafter) including the second organic insulating layer211, the pixel-defining layer215, and an inorganic layer216. The second organic insulating layer211and the pixel-defining layer215may correspond to the bottom layer described with reference toFIGS.9A and9B, and the inorganic layer216may correspond to the top layer. The pixel-defining layer215may include an organic insulating material, and the inorganic layer216may include a conductive oxide such as IZO, or include an inorganic insulating material such as silicon nitride. Alternatively, the inorganic layer216may include a metal such as Mo and Ti. The inorganic layer216of the second multi-layer ML2may include a material that is the same as or different from a material of the inorganic layer213of the first multi-layer ML1. The first groove G1may include a hole216hof the inorganic layer216, a hole215hof the pixel-defining layer215, and a recess211rof the second organic insulating layer211. The inorganic layer216may include a pair of tips PT extending toward a center of the first groove G1. A protruding length of the tip PT and the depth of the first groove G1are the same as those described with reference toFIG.9A. FIG.16is a cross-sectional view of the first area OA and the middle area MA in a display panel10-4according to an embodiment, taken along the line X-X′ ofFIG.10. Because the display panel10-4ofFIG.16is different from the display panel10-3shown inFIG.15in the structure of the first groove G1, a difference is mainly described. The first groove G1is located in a second multi-layer ML2′, and a top layer of the second multi-layer ML2′ may include a plurality of inorganic layers. With regard to this, it is shown inFIG.16that the second multi-layer ML2′ includes the second organic insulating layer211, the pixel-defining layer215, a first inorganic layer216a, and a second inorganic layer216b. As described with reference toFIG.9F, the second organic insulating layer211and the pixel-defining layer215may correspond to the bottom layer, and the first inorganic layer216aand the second inorganic layer216bmay correspond to the top layer. Though it is shown inFIG.16that the top layer includes two layers including the first inorganic layer216aand the second inorganic layer216b, the top layer may include three or more inorganic layers as described with reference toFIG.9F. The first groove G1may include a hole216bhof the second inorganic layer216b, a hole216ahof the first inorganic layer216a, the hole215hof the pixel-defining layer215, and the recess211rof the second organic insulating layer211. As described with reference toFIG.15, the first groove G1may overlap the bypass portions DL-D1and DL-D2of the first and second data lines. The first inorganic layer216amay include a material different from that of the second inorganic layer216b. For example, the first inorganic layer216amay include a conductive oxide such as IZO, and the second inorganic layer216bmay include an insulating material such as silicon nitride. The first inorganic layer216aand the second inorganic layer216bmay include tips PT protruding toward a center of the first groove G1, and conditions for a protruding length of the tip PT and the depth of the first groove G1are the same as those described above. Thought it is shown inFIG.16that the inorganic layer213, which is a top layer of the first multi-layer ML1, includes a single layer, the inorganic layer213may include two or more layers in some other embodiments. A top layer of the second multi-layer ML2′ and a top layer of the first multi-layer ML1may have different stacked structures or include different materials. In an embodiment, the top layer of the second multi-layer ML2′ may include two sub-layers including the first inorganic layer216aand the second inorganic layer216b, but the inorganic layer213, which is the top layer of the first multi-layer ML1, may include one or three or more sub-layers. The above-described characteristics described with reference toFIGS.15and16, for example, a characteristic in which the first groove G1that neighbors the display area DA is located on a layer different from a layer on which other grooves G are placed, a characteristic in which the first groove G1overlaps wirings, and a structure of the second multi-layers ML2and ML2′ are applicable to the embodiments described with reference toFIGS.8-14, embodiments described below with referenced toFIGS.17-19, and embodiments derived therefrom. FIG.17is a cross-sectional view of a display panel10-5according to an embodiment.FIG.17may correspond to a cross-section taken along the line X-X′ ofFIG.10. Referring toFIG.17, the display panel10-5includes the grooves G in the multi-layer ML. The multi-layer ML may include the first organic insulating layer209, the second interlayer insulating layer207, the first interlayer insulating layer205, and the inorganic layer210. The first organic insulating layer209, the second interlayer insulating layer207, and the first interlayer insulating layer205may respectively correspond to the first sub-bottom layer, the second sub-bottom layer, and the second sub-bottom layer of the multi-layer described with reference toFIG.9C, and the inorganic layer210may correspond to the top layer. The inorganic layer210may include a material different from those of the data line DL and the contact metal layer CM, the contact metal layer CM connecting the thin film transistor TFT to the pixel electrode221. The inorganic layer210may include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. Alternatively, the inorganic layer210may include a conductive oxide such as IZO. Alternatively, the inorganic layer210may include a metal such as Mo and Ti. The inorganic layer210may include a pair of tips PT extending toward a center of the groove G, and characteristics for a protruding length of the tip PT and the depth of the groove G are the same as those described above. Though it is shown inFIG.17that the bottom layer of the multi-layer ML include three sub-layers, the embodiments are not limited thereto. In some other embodiments, the bottom layer of the multi-layer ML may include two sub-layers including the first organic insulating layer209and the second interlayer insulating layer207. Alternatively, the bottom layer of the multi-layer ML may further include the gate insulating layer203in addition to the sub-layers ofFIG.17. The partition wall PW located in the middle area MA may be formed while a portion209P of a layer including the first organic insulating layer209, a portion215P of a layer including the pixel-defining layer215, and a portion217P of a layer including the spacer217are sequentially stacked. The structure of the partition wall PW shown inFIG.17is applicable to the embodiments described with reference toFIGS.11-16, embodiments described below with reference toFIG.19, and/or embodiments derived therefrom. FIG.18is a cross-sectional view of a display panel10-6according to an embodiment.FIG.18may correspond to a cross-section taken along the line X-X′ ofFIG.10. Because the display panel10-6ofFIG.18is different from the display panel10-5shown inFIG.17in the structure of the top layer of the multi-layer ML, a difference is mainly described below. Referring toFIG.18, the multi-layer ML may include the first organic insulating layer209, the second interlayer insulating layer207, the first interlayer insulating layer205, the first inorganic layer210a, and the second inorganic layer210b. The first organic insulating layer209, the second interlayer insulating layer207, and the first interlayer insulating layer205may respectively correspond to the first sub-bottom layer, the second sub-bottom layer, and the second sub-bottom layer. The first inorganic layer210aand the second inorganic layer210bmay respectively correspond to the first sub-top layer and the second sub-top layer. Though it is shown inFIG.18that the bottom layer of the multi-layer ML includes three sub-layers, the bottom layer may include a single layer as described with reference toFIG.9Ein some other embodiments. In this case, the bottom layer of the multi-layer ML may include the first organic insulating layer209, which is a bottom layer, the first inorganic layer210a, and the second inorganic layer210b, which are top layers. The first inorganic layer210amay include the same material as that of the contact metal layer CM. For example, the first inorganic layer210amay have a structure of Ti/Al/Ti that are sequentially stacked. The second inorganic layer210bmay include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. A lateral surface of the first inorganic layer210afacing a center of the groove G may be covered by the second inorganic layer210b. The first inorganic layer210a, which has a three-layered structure of Ti/Al/Ti, may be formed during the same mask process as a process of forming the contact metal layer CM. The second inorganic layer210bmay prevent or reduce damage to the first inorganic layer210a. For example, in the case where the first inorganic layer210aincludes a multi-layer including aluminum, which may be damaged during a process, and titanium, which may not be damaged during a process, a lateral surface of the first inorganic layer210amay be made not to include unevenness by reducing or preventing damage to aluminum. The top layer including the first inorganic layer210aand the second inorganic layer210bmay include a pair of tips PT. Characteristics for a protruding length of the tip PT and the depth of the groove G are the same as those described above. Though it is shown inFIG.18that the bottom layer of the multi-layer ML includes three sub-layers, the embodiments are not limited thereto. In some other embodiments, the bottom layer of the multi-layer ML may include two sub-layers including the first organic insulating layer209and the second interlayer insulating layer207. Alternatively, the bottom layer of the multi-layer ML may further include the gate insulating layer203in addition to the sub-layers ofFIG.18. FIG.19is a cross-sectional view of a display panel10-7according to an embodiment, andFIG.20is a cross-sectional view of a display panel10-8according to an embodiment.FIGS.19and20may correspond to cross-sections taken along the line X-X′ ofFIG.10. The display panel10-7ofFIG.19and the display panel10-8ofFIG.20may include a planarization organic material layer420located on the thin-film encapsulation layer300in the middle area MA. In an embodiment, a structure of the display panel10-7ranging from the substrate100to the thin-film encapsulation layer300is the same as that described above with reference toFIG.11. In some other embodiments, as shown inFIG.20, the display panel10-8may include a plurality of partition walls PW and PW in the middle area MA. A groove may not be located between the plurality of partition walls PW and PW. Alternatively, a groove may be located between the plurality of partition walls PW and MN. The plurality of partition walls PW and MAP may control a flow of a material constituting the organic encapsulation layer320during a process of forming the organic encapsulation layer320and/or control a height of the organic encapsulation layer320. With regard to this, though it is shown inFIG.20that a portion of the organic encapsulation layer320is between the partition walls PW and MAP that neighbor each other, an end of the organic encapsulation layer320may be located on one side of the partition wall PW that neighbors the display area DA depending on a flow control condition in some other embodiments. As shown inFIGS.19and20, the planarization organic material layer420may be located in the middle area MA. The planarization organic material layer420may be located in only the intermediated area MA, for example, between the first area OA and the display area DA. The planarization organic material layer420may include an organic insulating layer. The planarization organic material layer420may include a polymer-based material. For example, the planarization organic material layer420may include a silicon-based resin, an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene. In an embodiment, the planarization organic material layer420may include a material different from that of the organic encapsulation layer320. The planarization organic material layer420may cover at least one groove G located in the middle area MA. The planarization organic material layer420may increase flatness of the display panel10-7around the first area OA by covering a region of the middle area MA that is not covered by the organic encapsulation layer320. Therefore, separation or falling apart of the input sensing layer40(seeFIG.2or3) and/or the optical functional layer50(seeFIG.2or3) on the display panel10-7may be reduced or prevented. A portion of the planarization organic material layer420may overlap the organic encapsulation layer320. One edge of the planarization organic material layer420, for example, a first edge420ethat neighbors the display area DA may be located on the second inorganic encapsulation layer330. The planarization organic material layer420may be located in the middle area MA during an exposure and developing process. In the case where external foreign substances, for example, moisture progresses in a lateral direction (or a direction parallel to the top surface of the substrate100, an x-direction) of the display panel10-7during some processes (e.g., a washing process) among processes of forming the planarization organic material layer420, an organic light-emitting diode OLED in the display area DA may be damaged. However, because insulating layers, for example, a first insulating layer410and a second insulating layer430are respectively arranged or placed under and on the planarization organic material layer420, the issue related to moisture penetration and/or floating of a layer located around the planarization organic material layer420may be reduced or prevented during and after a process of forming the planarization organic material layer420. The first insulating layer410and the second insulating layer430may respectively directly contact a bottom surface and a top surface of the planarization organic material layer420. The first insulating layer410and the second insulating layer430may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer410and the second insulating layer430each may include a single layer or a multi-layer including the above materials. The planarization organic material layer420may form a step difference with a layer(s) thereunder. A portion of the planarization organic material layer420that includes the first edge420emay form a step difference with a top surface of the first insulating layer410. To reduce or prevent an issue that the planarization organic material layer420is separated or floated from a layer thereunder due to the above-described step difference during and/or after a process of manufacturing the display panel10-7, a cover layer440may be located on the first edge420e. The cover layer440may include a metal. The first insulating layer410, the second insulating layer430, and a third insulating layer450described below each extend to not only the intermediate layer MA but also the display area DA. In contrast, the cover layer440may cover the first edge420eof the planarization organic material layer420with a set or predetermined width. The cover layer440on the planarization organic material layer420may extend toward the display area DA beyond the first edge420e, but does not extend toward the display area DA. The third insulating layer450may be located on the cover layer440. The third insulating layer450may include an organic insulating material. For example, an organic insulating material of the third insulating layer450may include a photoresist (e.g., a negative or positive photoresist) or a polymer-based organic material, and may extend toward the display area DA so as to cover the display area DA. The structure shown inFIGS.19and20is equally applicable to the embodiments described with reference toFIGS.13-18and embodiments derived therefrom. Though it is shown that each of the display panels described with reference toFIGS.11-20includes the first opening10H corresponding to the first area OA, and the substrate100also includes a through hole corresponding to the first area OA, the embodiments are not limited thereto. In some other embodiments, as described with reference toFIG.4B, the display panel may not include a hole passing through the substrate100. The display panel according to embodiments may reduce or prevent external impurities such as moisture around the first area from damaging display elements. It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section, without departing from the scope of the present disclosure. Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure”. Also, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present. Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of features. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, and their equivalents. | 85,173 |
11943975 | DETAILED DESCRIPTION Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numbers refer to like elements throughout. The present disclosure, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present disclosure may not be described. Further, when a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof may not be repeated. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity. In other words, because sizes and thicknesses of components in the drawings may be arbitrarily illustrated for convenience of explanation, the example embodiments of the present disclosure are not limited thereto. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Similarly, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component and/or may be “indirectly electrically connected” to other layer, region, or component with one or more intervening layers, regions, or components interposed therebetween. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including,” “has,” “have,” and “having,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression “at least one of a, b, or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Also, the term “exemplary” is intended to refer to an example or illustration. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. FIG.1is a perspective view of a display apparatus1according to an embodiment. Referring toFIG.1, the display apparatus1includes a display area DA and a non-display area NDA. Light may be emitted from the display area DA, and light may not be emitted from the non-display area NDA. The non-display area NDA may be adjacent to (e.g., may neighbor) the display area DA. The display apparatus1displays an image by using light emitted from a plurality of pixels arranged at (e.g., in or on) the display area DA. The display apparatus1includes an opening area OA that is at least partially surrounded (e.g., around a periphery thereof) by the display area DA. In an embodiment, as shown inFIG.1, the opening area OA may be entirely surrounded (e.g., around a periphery thereof) by the display area DA. The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may surround (e.g., around a periphery of) the opening area OA, and the second non-display area NDA2 may surround (e.g., around a periphery of) the display area DA. In an embodiment, the first non-display area NDA1 may entirely surround (e.g., around a periphery of) the opening area OA, the display area DA may entirely surround (e.g., around a periphery of) the first non-display area NDA1, and the second non-display area NDA2 may entirely surround (e.g., around a periphery of) the display area DA. In an embodiment, the display apparatus1may be an organic light-emitting display apparatus but the present disclosure is not limited thereto. For example, in other embodiments, the display apparatus1may include (or may be) various suitable display apparatuses, for example, such as an inorganic light-emitting display apparatus or quantum-dot light-emitting display apparatus. FIG.2is a cross-sectional view of the display apparatus1according to an embodiment taken along the line II-II′ ofFIG.1. Referring toFIG.2, the display apparatus1may include a display panel10, an input sensing member (e.g., an input sensing layer)20, and an optical functional member (e.g., an optical functional layer)30on the display panel10. A window40may cover the display panel10, the input sensing member20, and the optical functional member30. The display apparatus1may include (or may be included in) various suitable electronic apparatuses, for example, such as mobile phones, notebook computers, smartwatches, and/or the like. The display panel10displays an image. The display panel10includes pixels arranged at (e.g., in or on) the display area DA. Each of the pixels may include a display element, and a pixel circuit connected to the display element. The display element may include an organic light-emitting diode, an inorganic light-emitting diode, or a quantum-dot light-emitting diode. The input sensing member20obtains coordinate information corresponding to an external input, for example, such as a touch event. The input sensing member20may include a sensing electrode (or a touch electrode), and trace lines connected to the sensing electrode. The input sensing member20may be arranged on the display panel10. The input sensing member20may be directly formed on the display panel10, or may be separately formed and then connected to the display panel10through an adhesive layer, for example, such as an optical clear adhesive (OCA). For example, the input sensing member20may be successively formed after a process of forming the display panel10. In this case, the adhesive layer may not be arranged between the input sensing member20and the display panel10. Though it is shown inFIG.2that the input sensing member20is arranged between the display panel10and the optical functional member30, the input sensing member20may be arranged on the optical sensing member30in another embodiment. The optical functional member30may include a reflection prevention layer. The reflection prevention layer may reduce the reflectivity of light (e.g., of external light) incident toward the display panel10from the outside through the window40. The reflection prevention layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a half-wave (λ/2) retarder and/or a quarter-wave (λ/4) retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystals arranged in a suitable (e.g., a predetermined) arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves, or the protective film of the retarder and the polarizer may be defined as a base layer of the reflection prevention layer. In another embodiment, the reflection prevention layer may include a black matrix and color filters. The color filters may be arranged by taking into account colors of light emitted respectively from the pixels of the display panel10. In another embodiment, the reflection prevention layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer respectively arranged on different layers. First-reflected light and second-reflected light respectively reflected by the first reflection layer and the second reflection layer may create a destructive interference, and thus, the reflectivity of the external light may be reduced. The optical functional member30may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel10, and/or may reduce color deviation. The lens layer may include a layer having a concave or convex lens shape and/or may include a plurality of layers having different refractive indexes from each other. The optical functional member30may include both the reflection prevention layer and the lens layer, or may include one of these layers. The display panel10, the input sensing member20, and the optical functional member30may each include an opening. For example, as shown inFIG.2, the display panel10, the input sensing member20, and the optical functional member30may include first to third openings10H,20H, and30H, respectively, and the first to third openings10H,20H, and30H may overlap with one another. The first to third openings10H,20H, and30H are arranged to correspond to the opening area OA. In another embodiment, at least one of the display panel10, the input sensing member20, and the optical functional member30may not include an opening. For example, one or two from among the display panel10, the input sensing member20, and the optical functional member30may not include an opening. A component50may correspond to the opening area OA. As shown by a solid line inFIG.2, the component50may be arranged inside the first to third openings10H,20H, and30H, or as shown by a dashed line inFIG.2, the component50may be arranged below the display panel10. The component50may include an electronic element. For example, the component50may include an electronic element that uses light or sound. For example, the electronic element may include a sensor such as an infrared sensor that emits and/or receives light, a camera that receives light to capture an image, a sensor that outputs and senses light or sound to measure a distance or to recognize a fingerprint, a small lamp that outputs light, and/or a speaker that outputs sound. In the case of an electronic element that uses light, the electronic element may use light in various wavelength bands, for example, such as visible light, an infrared ray, and/or an ultraviolet ray. In an embodiment, the opening area OA may be understood as a transmission area through which light and/or sound output from the component50to the outside and/or progressing toward the electronic element from the outside may pass. In another embodiment, in the case where the display apparatus1is used as a smartwatch or an instrument panel for an automobile, the component50may be a member, for example, such as clock hands or a needle indicating desired information (e.g., predetermined information, for example, such as the velocity of a vehicle, and/or the like). In the case where the display apparatus1includes clock hands or an instrument panel for an automobile, the component50may pass through the window40and may be exposed to the outside, for example, such that the window40may include an opening corresponding to the opening area OA. As described above, the component50may include one or more elements related to various functions of the display panel10, or an element such as an accessory that increases the aesthetic sense of the display panel10. FIG.3is a plan view of the display panel10according to an embodiment, andFIG.4is an equivalent circuit diagram of a pixel of the display panel10. Referring toFIG.3, the display panel10includes the display area DA, the first non-display area NDA1, and the second non-display area NDA2.FIG.3may be understood as showing a substrate100of the display panel10. For example, it may be understood that the substrate100includes the opening area OA, the display area DA, the first non-display area NDA1, and the second non-display area NDA2. The display panel10includes a plurality of pixels P arranged at (e.g., in or on) the display area DA. As shown inFIG.4, each pixel P includes a pixel circuit PC, and an organic light-emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit light having, for example, red, green, blue, or white light from the organic light-emitting diode OLED. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transfers a data voltage to the driving thin film transistor T1 in response to a switching voltage input through the scan line SL. The data voltage may be input through the data line DL. The storage capacitor Cst is connected to the switching thin film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to a difference between a voltage transferred from the switching thin film transistor T2 and a first power voltage ELVDD supplied to the driving voltage line PL. The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a desired brightness (e.g., a certain brightness) according to the driving current. An opposite electrode (e.g. a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS. AlthoughFIG.4shows an example where the pixel circuit PC includes two thin film transistors and one storage capacitor, the present disclosure is not limited thereto. For example, the number of thin film transistors and the number of storage capacitors may be variously modified depending on a structure or a design of the pixel circuit PC. Referring again toFIG.3, the first non-display area NDA1 may surround (e.g., around a periphery of) the opening area OA. The first non-display area NDA1 includes a region in which a display element such as an organic light-emitting diode that emits light is not arranged. Signal lines may pass across the first non-display area NDA1, or a recess and a dam described in more detail below may be arranged at (e.g., in or on) the first non-display area NDA1. The signal lines may provide a signal to the pixels P arranged around (e.g., surrounding, adjacent to, or near) the opening area OA. A scan driver1100, a data driver1200, a main power line, and/or the like may be arranged at (e.g., in or on) the second non-display area NDA2. The scan driver1100may provide a scan signal to each pixel P, the data driver1200may provide a data signal to each pixel P, and the main power line may provide the first and second power voltages ELVDD and ELVSS. AlthoughFIG.4shows that the data driver1200is arranged to be adjacent to one lateral side of the substrate100, the present disclosure is not limited thereto, and the data driver1200may be arranged on a flexible printed circuit board (FPCB) electrically connected to a pad arranged on one side of the display panel10in another embodiment. FIG.5is a plan view of a portion of the display panel10according to an embodiment, and shows signal lines arranged at (e.g., in or on) the first non-display area NDA1. Referring toFIG.5, pixels P are arranged at (e.g., in or on) the display area DA around (e.g., surrounding, adjacent to, or near) the opening area OA, and the first non-display area NDA1 may be arranged between the opening area OA and the display area DA. The pixels P may be spaced apart from one another with the opening area OA therebetween. The pixels P may be vertically (e.g., in a y-direction) spaced apart from one another with the opening area OA therebetween, and/or may be horizontally (e.g., in an x-direction) spaced apart from one another with the opening area OA therebetween. From among the signal lines configured to supply a signal to the pixels P, the signal lines adjacent to (e.g., neighboring or surrounding a periphery of) the opening area OA may detour (e.g., may extend around a periphery of) the opening area OA. Some of the data lines DL passing across the display area DA may extend in a y-direction to provide a data signal to the pixels P that are vertically arranged with the opening area OA therebetween, and may detour along the edge of (e.g., may extend partially around a periphery of) the opening area OA at (e.g., in or on) the first non-display area NDA1. Some of the scan lines SL passing across the display area DA may extend in an x-direction to provide a scan signal to the pixels P that are horizontally arranged with the opening area OA therebetween, and may detour along the edge of (e.g., may extend partially around a periphery of) the opening area OA at (e.g., in or on) the first non-display area NDA1. FIG.6is a plan view of a portion of the display panel10according to an embodiment, and shows a recess R and a dam DAM arranged at (e.g., in or on) the first non-display area NDA1. In addition,FIG.6shows an opposite electrode223arranged at (e.g., in or on) the first non-display area NDA1. At least one dam DAM may be arranged between the opening area OA and the display area DA. The recess R may be arranged between the dam DAM and the opening area OA. In some embodiments, the dam DAM may be provided in a plurality, and in this case, the recess R may be arranged on one side of a dam DAM that is adjacent to (e.g., closest to) the opening area OA from among the plurality of dams DAM. As used in the present specification, the dam DAM denotes an element protruding with respect to a reference surface, and the recess R denotes an element recessed with respect to the reference surface. For example, the reference surface may include a top surface of one of insulating layers arranged on the substrate100. In other words, the dam DAM may include an element protruding from the top surface of a first insulating layer, and the recess R may include an element recessed in a depth direction of the first insulating layer. Because a region between the recess R and the opening area OA is a region from which first and second functional layers222aand222c(e.g., seeFIG.7A) and the opposite electrode223are removed, the penetration of moisture, external air, and/or the like through the opening area OA may be prevented or substantially prevented. In other words, the first and second functional layers222aand222cand the opposite electrode223may each include a transmission hole TAH exposing the opening area OA and a portion of the first non-display area NDA1 around (e.g., surrounding around a periphery of) the opening area OA. For example, the transmission hole TAH may expose the portion of the first non-display area NDA1 between the recess R and the opening area OA. A boundary or a lateral wall of the transmission hole TAH may be designed to meet an inner lateral wall of the recess R. As described in more detail below, the recess R may include an element configured to efficiently remove the first and second functional layers222aand222cand the opposite electrode223(e.g., seeFIG.7A) by using a laser lift process. The dam DAM and the recess R may each have a ring shape entirely surrounding (e.g., around a periphery of) the opening area OA at (e.g., in or on) the first non-display area NDA1. A diameter of each of the dam DAM and the recess R may be greater than a diameter of the opening area OA. In a plan view, the dam DAM and the recess R each surrounding (e.g., around a periphery of) the opening area OA may be adjacent to (e.g., may neighbor) each other. FIG.7Ais a cross-sectional view of a pixel of the display panel10according to an embodiment taken along the line VII-VII′ ofFIG.6. Referring toFIG.7A, a pixel circuit PC and an organic light-emitting diode OLED may be arranged at (e.g., in or on) the display area DA. The organic light-emitting diode OLED may be electrically connected to the pixel circuit PC. A thin film transistor TFT and a storage capacitor Cst may each be located over the substrate100, and may be electrically connected to a pixel electrode221. The pixel circuit PC may be arranged over the substrate100. The organic light-emitting diode OLED may be arranged on the pixel circuit PC. The substrate100may include a polymer resin or glass. In an embodiment, the substrate100may include a polymer resin, for example, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose tri-acetate, and/or cellulose acetate propionate, and may be flexible. The substrate100may include glass having SiO2as a main component, or may include a resin, for example, such as a reinforced plastic, and may be rigid. A buffer layer201may be formed on the substrate100. The buffer layer201may prevent or substantially prevent impurities from penetrating into a first semiconductor layer Act of a first thin film transistor TFT. The buffer layer201may include an inorganic material, for example, such as oxide or nitride, an organic material, or an organic/inorganic composite material, and may have a single-layer structure or a multi-layered structure including an inorganic material and an organic material. In some embodiments, a barrier layer may be further included between the substrate100and the buffer layer201. In this case, the barrier layer may block or substantially block the penetration of external air. In an embodiment, the buffer layer201may include silicon oxide (SiO2) or silicon nitride (SiNx). The pixel circuit PC may be arranged on the buffer layer201. The pixel circuit PC includes the first thin film transistor TFT and the storage capacitor Cst. The first thin film transistor TFT may include the first semiconductor layer Act, a first gate electrode GE, a first source electrode SE, and a first drain electrode DE. The first thin film transistor TFT shown inFIG.7Amay correspond to the driving thin film transistor described with reference toFIG.4. Although the present embodiment shows a top-gate type thin film transistor in which the first gate electrode GE is arranged over the first semiconductor layer Act with a first gate insulating layer203therebetween, in another embodiment, the first thin film transistor TFT may include a bottom-gate type thin film transistor. The first semiconductor layer Act may include polycrystalline silicon (poly-Si). However, the present disclosure is not limited thereto, and the first semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The first gate electrode GE may include a low-resistance metal material. The first gate electrode GE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. The first gate insulating layer203between the first semiconductor layer Act and the first gate electrode GE may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The first gate insulating layer203may include a single layer structure or a multi-layered structure including one or more of the above materials. The first source electrode SE and the first drain electrode DE may include a material having a suitable conductivity (e.g., an excellent conductivity). The first source electrode SE and the first drain electrode DE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. In an embodiment, the first source electrode SE and the first drain electrode DE may include a multi-layered structure of Ti/Al/Ti. The storage capacitor Cst includes a bottom electrode CE1 and a top electrode CE2 overlapping with each other with a second gate insulating layer205therebetween. The storage capacitor Cst may overlap with the thin film transistor TFT. For example, as shown inFIG.7A, the first gate electrode GE of the first thin film transistor TFT may serve as the bottom electrode CE1 of the storage capacitor Cst. However, the present disclosure is not limited thereto, and in another embodiment, the storage capacitor Cst may not overlap with the first thin film transistor TFT. The top electrode CE2 of the storage capacitor Cst may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. In an embodiment, the top electrode CE2 may include a first layer and a second layer arranged on the first layer, the first layer including titanium (Ti), and the second layer including molybdenum (Mo). As described in more detail below, because the first layer of the top electrode CE2 may be concurrently (e.g., simultaneously) formed with a sacrificial layer described in more detail below, and may include the same material as that of the sacrificial layer, an additional process of separately forming the sacrificial layer may be reduced. In another embodiment, the bottom electrode CE1 may include a first layer and a second layer arranged on the first layer, the first layer including titanium (Ti), and the second layer including molybdenum (Mo). Because the first layer of the bottom electrode CE1 may be concurrently (e.g., simultaneously) formed with a sacrificial layer described in more detail below, and may include the same material as that of the sacrificial layer, an additional process of separately forming the sacrificial layer may be reduced. The second gate insulating layer205may serve as a dielectric of the storage capacitor Cst. The second gate insulating layer205may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate insulating layer205may include a single layer structure or a multi-layered structure including one or more of the above materials. The storage capacitor Cst may be covered by an interlayer insulating layer207. The interlayer insulating layer207may include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The interlayer insulating layer207may include a single layer structure or a multi-layered structure including one or more of the above materials. The pixel circuit PC including the first thin film transistor TFT and the storage capacitor Cst may be covered by a planarization layer209. The planarization layer209may include a flat or substantially flat (e.g., an approximately flat) top surface. The planarization layer209may include an organic insulating material including, for example, a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof. In an embodiment, the planarization layer209may include polyimide. In another embodiment, the planarization layer209may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material. The pixel electrode221may be arranged on the planarization layer209. The pixel electrode221may include a conductive oxide, for example, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode221may include a reflective layer including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), or a compound thereof. In another embodiment, the pixel electrode221may further include a layer including, for example, ITO, IZO, ZnO, or In2O3on/under the reflective layer. In this case, for example, the pixel electrode221may have a stacked structure of ITO/Ag/ITO. A pixel-defining layer211may be arranged on the pixel electrode221. The pixel-defining layer211may include an opening exposing a top surface of the pixel electrode221, and may cover edges (e.g., opposite edges) of the pixel electrode221. Therefore, the pixel-defining layer211may define an emission area of a pixel. The pixel-defining layer211may include an organic insulating material. For example, the pixel-defining layer211may be formed through a spin coating process, and/or the like by using an organic insulating material, for example, such as polyimide, polyamide, an acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and/or a phenolic resin. An intermediate layer222may include an emission layer222b. The intermediate layer222may include the first functional layer222aand/or the second functional layer222c, the first functional layer222abeing under the emission layer222b, and the second functional layer222cbeing on the emission layer222b. The emission layer222bmay include a polymer organic material or a low molecular weight organic material for emitting light having a desired color (e.g., a certain color). The first functional layer222amay include a single layer structure or a multi-layered structure. For example, in the case where the first functional layer222aincludes a polymer material, the first functional layer222amay include a hole transport layer (HTL), which has a single-layered structure, and may include poly(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer222aincludes a low molecular weight material, the first functional layer222amay include a hole injection layer (HIL) and an HTL. The second functional layer222cmay be omitted. For example, in the case where the first functional layer222aand the emission layer222binclude a polymer material, the second functional layer222cmay be formed. The second functional layer222cmay include a single layer structure or a multi-layered structure. The second functional layer222cmay include an electron transport layer (ETL) and/or an electron injection layer (EIL). The emission layer222bof the intermediate layer222may be arranged for each pixel at (e.g., in or on) the display area DA. The emission layer222bmay contact a top surface of the pixel electrode221exposed through the opening of the pixel-defining layer211. The first and second functional layers222aand222cof the intermediate layer222may be formed not only at (e.g., in or on) the display area DA ofFIG.7A, but may also be formed at (e.g., in or on) the first non-display area NDA1. The opposite electrode223may include a conductive material having a low work function. For example, the opposite electrode223may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In another embodiment, the opposite electrode223may further include a layer on the (semi) transparent layer, the layer including, for example, ITO, IZO, ZnO, or In2O3. The opposite electrode223may be formed not only at (e.g., in or on) the display area DA, but may also be formed at (e.g., in or on) the first non-display area NDA1. The intermediate layer222and the opposite electrode223may be formed, for example, by thermal deposition. A spacer213may be formed on the pixel-defining layer211. The spacer213may include an organic insulating material, for example, such as polyimide. The spacer213may include a material different from that of the pixel-defining layer211. In another embodiment, the spacer213may include the same material as that of the pixel-defining layer211. In this case, the pixel-defining layer211and the spacer213may be concurrently (e.g., simultaneously) formed during a mask process that uses a half-tone mask. In an embodiment, the pixel-defining layer211and the spacer213may include polyimide. A capping layer230may be arranged on the opposite electrode223. The capping layer230may be a layer configured to protect the opposite electrode223, and may include lithium fluoride (LiF), an inorganic material, and/or an organic material. However, the present disclosure is not limited thereto, and in another embodiment, the capping layer230may be omitted. FIG.7Bis a cross-sectional view of a pixel of the display panel10according to an embodiment taken along the line VII-VII′ ofFIG.6. InFIG.7B, because the same reference numerals are used to denote the same or substantially the same elements as those ofFIG.7A, redundant descriptions thereof may not be repeated. Referring toFIG.7B, the pixel circuit PC and the organic light-emitting diode OLED may be arranged at (e.g., in or on) the display area DA. The organic light-emitting diode OLED may be electrically connected to the pixel circuit PC. The embodiment ofFIG.7Bis different from the embodiment ofFIG.7Ain that the pixel circuit PC includes a thin film transistor including an oxide semiconductor, and a thin film transistor including polycrystalline silicon. Referring toFIG.7B, the pixel circuit PC of the display panel10may include the first thin film transistor TFT including a semiconductor layer Act including polycrystalline silicon, and a second thin film transistor TFTo including a semiconductor layer Act′ including an oxide semiconductor. The first thin film transistor TFT includes the first semiconductor layer Act, a first gate electrode GE, a first source electrode SE, and a first drain electrode DE. The first thin film transistor TFT is the same or substantially the same as the first thin film transistor TFT described with reference toFIG.7A, and the first semiconductor layer Act of the first thin film transistor TFT may include polycrystalline silicon. The present embodiment includes a first interlayer insulating layer207a, a second interlayer insulating layer207b, a first planarization layer209a, and a second planarization layer209b. In addition, the substrate100may have a multi-layered structure. The substrate100may include a first base layer101, a first inorganic barrier layer102, a second base layer103, and a second inorganic barrier layer104that are sequentially stacked on one another. The first base layer101and the second base layer103may each include a polymer resin. The first inorganic barrier layer102and the second inorganic barrier layer104may include various suitable barrier layers configured to prevent or substantially prevent the penetration of impurities from the outside, may include an inorganic material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), and/or silicon oxynitride (SiOxNy), and may have a single-layer structure or a multi-layered structure. The second thin film transistor TFTo may include the second semiconductor layer Act′, a second gate electrode GE′, a second source electrode SE′, and a second drain electrode DE′. The second thin film transistor TFTo may further include a bottom gate electrode GE″. The second semiconductor layer Act′ may be arranged on the first interlayer insulating layer207a. In other words, the second semiconductor layer Act′ may be arranged at (e.g., in or on) a different layer from that of the first semiconductor layer Act. The second semiconductor layer Act′ may include a channel region, a source region, and a drain region. The source region and the drain region may be respectively arranged on two opposite sides of the channel region. In an embodiment, the second semiconductor layer Act′ may include an oxide semiconductor. For example, the second semiconductor layer Act′ may include a Zn-oxide-based material such as Zn-oxide, In—Zn oxide, and/or Ga—In—Zn oxide. As another example, the second semiconductor layer Act′ may include In—Ga—Zn—O (IGZO), In—Sn—Zn—O (ITZO), or In—Ga—Sn—Zn—O (IGTZO) semiconductor containing metal, for example, such as indium (In), gallium (Ga), and/or stannum (Sn) in ZnO. The source region and the drain region of the second semiconductor layer Act′ may be formed by adjusting a carrier concentration of an oxide semiconductor, and making the source region and the drain region conductive. For example, the source region and the drain region of the second semiconductor layer Act′ may be formed by increasing a carrier concentration through plasma treatment that uses a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof performed on the oxide semiconductor. The second gate electrode GE′ may overlap with the channel region of the second semiconductor layer Act′. A third gate insulating layer206may be arranged between the second semiconductor layer Act′ and the second gate electrode GE′. In other words, the second gate electrode GE′ may be insulated from the second semiconductor layer Act′ by the third gate insulating layer206. AlthoughFIG.7Bshows that the third gate insulating layer206is provided over an entire top surface of the substrate100, the present disclosure is not limited thereto, and the third gate insulating layer206may be patterned along the shape of the second gate electrode GE′. The second gate electrode GE′ may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. In the present embodiment, the second gate electrode GE′ may include a first layer GE1′ and a second layer GE2′. The first layer GE1′ may include titanium (Ti), and the second layer GE2′ may include molybdenum (Mo). In this case, the thickness (e.g., in a direction perpendicular to or substantially perpendicular to a top surface of the substrate100) of the first layer GE1′ may be less than the thickness of the second layer GE2′. In an embodiment, the thickness of the first layer GE1′ may be about 70 Å to about 300 Å. As described in more detail below, because the first layer GE1′ may be concurrently (e.g., simultaneously) formed with a sacrificial layer described in more detail below by using the same material as that of the sacrificial layer, an additional process of separately forming the sacrificial layer may be reduced. The third gate insulating layer206may include an inorganic material including, for example, oxide or nitride. For example, the third gate insulating layer206may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second gate electrode GE′ may be arranged on the third gate insulating layer206, may include at least one of molybdenum (Mo), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure. The bottom gate electrode GE″ may be arranged below the second semiconductor layer Act′ to overlap with a channel region of the second semiconductor layer Act′. The bottom gate electrode GE″ may be arranged at (e.g., in or on) the same layer as that of the top electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer207amay be arranged between the bottom gate electrode GE″ and the second semiconductor layer Act′. The second interlayer insulating layer207bmay cover the second gate electrode GE′ of the second thin film transistor TFTo, and may be arranged over the top surface of the substrate100. The second source electrode SE′, and the second drain electrode DE′ may be arranged on the second interlayer insulating layer207b. The first interlayer insulating layer207aand the second interlayer insulating layer207bmay include an inorganic material including, for example, oxide or nitride. For example, the first interlayer insulating layer207aand the second interlayer insulating layer207bmay include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The second source electrode SE′ and the second drain electrode DE′ may respectively contact the source region and the drain region of the second semiconductor layer Act′ through contact holes passing through the second interlayer insulating layer207b. The second source electrode SE′ and the second drain electrode DE′ may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. Because a thin film transistor including a semiconductor layer including polycrystalline silicon has a high reliability, the thin film transistor may be employed as the driving thin film transistor to implement a high-quality display panel. Because an oxide semiconductor has a high carrier mobility and a low leakage current, a voltage drop may not be large even when a driving time is long. In other words, because a color change of an image according to a voltage drop may not be large even during low-frequency driving, a display panel may be driven at low frequencies. Because an oxide semiconductor may have a low leakage current as described above, a leakage current may be prevented or substantially prevented, and accordingly, power consumption may be reduced by employing an oxide semiconductor as at least one of the other thin film transistors in addition to the driving thin film transistor. The first planarization layer209aand the second planarization layer209bmay be provided on the second interlayer insulating layer207b. Therefore, because conductive patterns such as wirings may be formed between the first planarization layer209aand the second planarization layer209b, high integration may be provided. The first planarization layer209amay be arranged to cover the pixel circuit PC. The second planarization layer209bmay be arranged on the first planarization layer209a, and may have a flat or a substantially flat top surface such that the pixel electrode221may be formed to be flat or substantially flat. The first planarization layer209aand the second planarization layer209bmay include an organic material or an inorganic material, and may have a single-layer structure or a multi-layered structure. The first planarization layer209aand the second planarization layer209bmay include, for example, a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. The first planarization layer209aand the second planarization layer209bmay include an inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). While the first planarization layer209aand the second planarization layer209bare formed, in order to provide a flat or a substantially flat top surface, chemical mechanical polishing may be performed on a top surface thereof after the first planarization layer209aand the second planarization layer209bare formed. The organic light-emitting diode OLED may be arranged on the second planarization layer209b. The pixel electrode221of the organic light-emitting diode OLED may be connected to the pixel circuit PC through a connection metal CM arranged on the first planarization layer209a. The connection metal CM may be arranged between the first planarization layer209aand the second planarization layer209b. The connection metal CM may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may include a single layer structure or a multi-layered structure including one or more of the above materials. For example, in some embodiments, the connection metal CM may have a multi-layered structure of Ti/Al/Ti. FIG.8is a cross-sectional view of the display panel10according to an embodiment, andFIG.9is an enlarged cross-sectional view of a region of the display panel10at (e.g., in or on) which a recess is arranged.FIG.8may correspond to a cross-section of the display panel10taken along line the IX-IX′ ofFIG.6, andFIG.9is an enlarged cross-sectional view of the region X ofFIG.8. Referring toFIG.8, the display panel10includes the opening area OA, the display area DA, and the first non-display area NDA1 therebetween. The display panel10may include the first opening10H corresponding to the opening area OA. As shown inFIG.8, in some embodiments, the display panel10may employ (e.g., may include) the pixel circuit PC shown inFIG.7B. WhileFIG.8shows an embodiment of the display panel10employing (e.g., including) the pixel circuit PC shown inFIG.7Bfor convenience of illustration and related description thereof, the present disclosure is not limited thereto. Referring to the display area DA ofFIG.8, the first thin film transistor TFT, the second thin film transistor TFTo, and the storage capacitor Cst may be arranged at (e.g., in or on) the display area DA. The insulating layers201to209bmay be arranged between the semiconductor layers and the electrodes of the first thin film transistor TFT and the second thin film transistor TFTo, and between the electrodes of the storage capacitor Cst. The pixel electrode221, the intermediate layer222, the opposite electrode223, and the capping layer230may be arranged at (e.g., in or on) the display area DA, and the pixel electrode221may be electrically connected to the pixel circuit PC. The above elements are the same or substantially the same as those described with reference toFIG.7B, and thus, redundant descriptions thereof may not be repeated. The display element including the pixel electrode221, the intermediate layer222, and the opposite electrode223may be covered by a thin-film encapsulation layer300. The thin-film encapsulation layer300may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, as shown inFIG.8, in some embodiments, the thin-film encapsulation layer300may include first and second inorganic encapsulation layers310and330, and an organic encapsulation layer320between the first and second inorganic encapsulation layers310and330. However, the present disclosure is not limited thereto, and in another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking sequence (e.g., a stacking order) may be variously modified as needed or desired. The first and second inorganic encapsulation layers310and330may include at least one inorganic insulating material, for example, such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and be formed by chemical vapor deposition (CVD), and/or the like. The organic encapsulation layer320may include, for example, a polymer-based material. The polymer-based material may include, for example, a silicon-based resin, an acryl-based resin, an epoxy-based resin, polyimide, and/or polyethylene. Referring to the first non-display area NDA1 ofFIG.8, the first non-display area NDA1 may include a first sub-non-display area SNDA1 and a second sub-non-display area SNDA2. The first sub-non-display area SNDA1 may be relatively close to (e.g., may be adjacent to) the display area DA, and the second sub-non-display area SNDA2 may be relatively close to (e.g., may be adjacent to) the opening area OA or the first opening10H. For example, the first sub-non-display area SNDA1 may be between the second sub-non-display area SNDA2 and the display area DA, and the second sub-non-display area SNDA2 may be between the first sub-non-display area SNDA1 and the opening area OA or the first opening10H. The first sub-non-display area SNDA1 may include a region across which the data lines DL described with reference toFIG.5pass (e.g., extend across). The data lines DL shown inFIG.8may correspond to data lines detouring (e.g., extending around a periphery of) the opening area OA. The first sub-non-display area SNDA1 may include a wiring region or a detouring region across which the data lines DL pass. In some embodiments, the data lines DL may be alternately arranged with the insulating layer therebetween as shown inFIG.8. In another embodiment, the data lines DL may be arranged at (e.g., in or on) the same insulating layer as each other. In the case where the data lines DL adjacent to (e.g., neighboring) each other are vertically arranged with an insulating layer therebetween, an interval (e.g., a pitch) between the data lines adjacent to (e.g., neighboring) each other may be reduced, and the width of the first non-display area NDA1 may be reduced. AlthoughFIG.8shows that the data lines DL are arranged at (e.g., in or on) the first sub-non-display area SNDA1, the scan lines detouring (e.g., extending around a periphery of) the opening area OA described with reference toFIG.5may be also arranged at (e.g., in or on) the first sub-non-display area SNDA1. The second sub-non-display area SNDA2 may be a region in which the organic material between the substrate100and the thin-film encapsulation layer300is removed, and may include a region at (e.g., in or on) which the recess R and the dam DAM are arranged. The recess R is concave with respect to a reference surface, and the dam DAM protrudes from the reference surface. In an embodiment, as shown inFIG.8, the recess R and the dam DAM may be provided with respect to the top surface of the third gate insulating layer206serving as the reference surface. Referring to the second sub-non-display area SNDA2 ofFIG.8andFIG.9, the recess R may be concave with respect to a top surface206S of the third gate insulating layer206, and the dam DAM may protrude from the top surface206S of the third gate insulating layer206. The recess R may be formed by removing a portion of the third gate insulating layer206. AlthoughFIGS.8and9show that the recess R is not formed in the first interlayer insulating layer207a, the present disclosure is not limited thereto. For example, in another embodiment, the recess R may be formed by removing a portion of the third gate insulating layer206and a portion of the first interlayer insulating layer207a. The dam DAM may include a plurality of layers that are stacked on one another. For example, the dam DAM may include a first layer251, a second layer253, and a third layer255that are stacked on one another. The first layer251may be arranged at (e.g., in or on) the same layer as that of the second interlayer insulating layer207b, and may include the same material as that of the second interlayer insulating layer207b. The second layer253may be arranged on the first layer251, may be arranged at (e.g., in or on) the same layer as that of the first planarization layer209a, and may include the same material as that of the first planarization layer209a. The third layer255may be arranged on the second layer253, may be arranged at (e.g., in or on) the same layer as that of the second planarization layer209b, and may include the same material as that of the second planarization layer209b. The dam DAM may include an element configured to control the flow of the organic encapsulation layer320while the organic encapsulation layer320of the thin-film encapsulation layer300is formed. The dam DAM and the recess R may be successively arranged. For example, one lateral wall DAMsw of a bottom end of the dam DAM may constitute one surface in cooperation with one lateral wall Rsw of the recess R. In other words, the one lateral wall DAMsw of the bottom end of the dam DAM may meet (e.g., may contact or may extend from) the one lateral wall Rsw of the recess R. The first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may each extend from the display area DA to be arranged on the top surface of the dam DAM and the recess R. The first functional layer222aand the second functional layer222cmay be referred to as a sub-layer222′. The sub-layer222′, the opposite electrode223, and the capping layer230may not be provided on the other side of the recess R at (e.g., in or on) which the dam DAM is not arranged. The sub-layer222′, the opposite electrode223, and the capping layer230may include a transmission hole TAH exposing the opening area OA and a portion of the first non-display area NDA1. The area of the transmission hole TAH may be greater than the area of the opening area OA. The end of the transmission area TAH may correspond to (e.g., may be provided at) the end of the recess R on which the dam DAM is not arranged. When a lateral wall from among the lateral walls Rsw of the recess R that is closer to the display area DA is a first lateral wall, the first lateral wall may meet the lateral wall DAMsw of the dam, and when a lateral wall from among the lateral walls Rsw of the recess R that is closer to the opening area OA is a second lateral wall, the end of the transmission hole TAH may be arranged on (e.g., may be defined by) the second lateral wall. In the case where the first and second functional layers222aand222ceach including an organic material are entirely formed on the first non-display area NDA1 to extend to the opening area OA, moisture may penetrate toward the organic light-emitting diode at (e.g., in or on) the display area DA through the first and second functional layers222aand222cdue to characteristics of the organic material. Therefore, the present embodiment prevents or substantially prevents moisture from penetrating into the display area DA by forming the transmission hole TAH in the first and second functional layers222aand222cincluding the organic material based on the recess R. As shown inFIG.8, the first inorganic encapsulation layer310may entirely cover the display area DA and the first non-display area NDA1. In the first non-display area NDA1, the first inorganic encapsulation layer310may entirely and continuously cover the dam DAM and the inside of the recess R. A stack of the first and second functional layers222aand222c, the opposite electrode223, and the capping layer230may be arranged on the bottom surface of the recess R, and the first inorganic encapsulation layer310may cover the stack. The organic encapsulation layer320may be formed by coating a monomer, and then hardening the monomer. The flow of the monomer may be controlled by the dam DAM. For example, as shown inFIGS.8and9, the end of the organic encapsulation layer320may be arranged on one side of the dam DAM. Similar to the first inorganic encapsulation layer310, the second inorganic encapsulation layer330may entirely and continuously cover the inner surface of the recess R. A portion of the second inorganic encapsulation layer330may directly contact the first inorganic encapsulation layer310at (e.g., in or on) the second sub-non-display area SNDA2. The second inorganic encapsulation layer330may directly contact the first inorganic encapsulation layer310inside the recess R. Further, the first and second inorganic encapsulation layers310and330may contact each other on the top surface of the dam DAM. The first inorganic encapsulation layer310may directly contact the third gate insulating layer206, which is an inorganic insulating layer thereunder, at (e.g., in or on) the second sub-non-display area SNDA2 between the recess R and the opening area OA. In other words, in the present embodiment, because an organic material layer is not arranged at (e.g., in or on) a region between the recess R and the opening area OA, penetration of moisture toward the organic light-emitting diode at (e.g., in or on) the display area DA may be prevented or substantially prevented. FIGS.10A to10Hare cross-sectional views sequentially showing a method of manufacturing the display panel10, according to an embodiment. Referring toFIG.10A, the pixel circuit PC is formed at (e.g., in or on) the display area DA, and a metal layer ML is formed at (e.g., in or on) the first non-display area NDA1. In an embodiment, the pixel circuit PC may include the first thin film transistor TFT and the second thin film transistor TFTo, the first thin film transistor TFT including polycrystalline silicon, and the second thin film transistor TFTo including an oxide semiconductor. The metal layer ML may be concurrently (e.g., simultaneously) formed while the elements of the pixel circuit PC are formed. For example, the metal layer ML may include the same material as that of the second gate electrode GE′, and be concurrently (e.g., simultaneously) formed with the second gate electrode GE′. The metal layer ML may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). In the present embodiment, the metal layer ML may include a sacrificial layer ML1 and a top layer ML2 that are stacked on one another, such that the top layer ML2 is on the sacrificial layer ML1. In this case, the sacrificial layer ML1 may include titanium (Ti), and the top layer ML2 may include molybdenum (Mo). In addition, the thickness of the sacrificial layer ML1 may be about 70 Å to about 300 Å, which may be suitable for a laser lift-off process. Referring toFIG.10B, a first opening207opmay be formed by etching the second interlayer insulating layer207b, which is an insulating layer covering the metal layer ML, to expose the metal layer ML. In this case, the first layer251of the dam DAM may be formed, and the recess R may be formed around (e.g., adjacent to ends of) the metal layer ML. The recess R may be formed by over-etching the first opening207opwhen etching the first opening207op. In other words, the recess R may be formed when a portion of the third gate insulating layer206is removed, the third gate insulating layer206being an insulating layer under the second interlayer insulating layer207b. The recess R may include an element configured to facilitate disconnection of an organic material described in more detail below. Because the first layer251of the dam DAM and the recess R may be concurrently (e.g., simultaneously) formed, one lateral wall of the dam DAM and the inner wall of the recess R may constitute one surface. Referring toFIG.10C, the second layer253of the dam DAM may be formed while the first planarization layer209ais formed, and the third layer255of the dam DAM may be formed while the second planarization layer209bis formed. The first planarization layer209aand the second layer253of the dam DAM may be concurrently (e.g., simultaneously) formed by coating an organic material on an entire surface of the substrate100, and light-hardening and patterning the organic material. Similarly, the second planarization layer209band the third layer255of the dam DAM may be concurrently (e.g., simultaneously) formed by coating an organic material on an entire surface of the substrate100, and light-hardening and patterning the organic material. Referring toFIG.10D, the sacrificial layer ML1 is exposed by removing the top layer ML2 of the metal layer ML. To reduce a mask process, the metal layer ML may be concurrently (e.g., simultaneously) formed with the second gate electrode GE′ of the second thin film transistor TFTo. It may be desirable that the second gate electrode GE′ has a sufficient thickness range to lower a resistance value thereof. In this case, the metal layer ML having the same or substantially the same thickness as that of the second gate electrode GE′ may be inappropriate to be used as a sacrificial layer for a laser lift-off process. Therefore, the laser lift-off process may be improved (e.g., may be optimized) by removing the top layer ML2 of the metal layer ML, and leaving only the sacrificial layer ML1 of the metal layer ML. In this case, a process of removing the top layer ML2 may be performed during the same process as a process of forming the pixel electrode221. In other words, when forming an electrode layer that constitutes the pixel electrode221on the entire surface of the substrate100and then patterning the electrode layer to form the pixel electrode221, the top layer ML2 may be concurrently (e.g., simultaneously) etched. Referring toFIG.10E, the intermediate layer222, the opposite electrode223, and the capping layer230are sequentially formed over the entire surface of the substrate100. The emission layer222b(e.g., seeFIG.7B) of the intermediate layer222may be formed to correspond to the pixel electrode221. The first functional layer222aand the second functional layer222cof the intermediate layer222, the opposite electrode223, and the capping layer230may be sequentially stacked on the sacrificial layer ML1. Laser light LASER may be irradiated from the bottom surface of the substrate100toward the sacrificial layer ML1. In other words, the laser light LASER may progress from the bottom surface of the substrate100in a thickness direction of the substrate100, and may be irradiated to the bottom surface of the sacrificial layer ML1. In an embodiment, the laser light LASER may have an infrared wavelength. In the case where the laser light LASER includes an infrared ray, because a transmittance of the substrate100and the insulating layers201to206may be 80% to 90% or more, the laser light LASER may efficiently reach the sacrificial layer ML1. Because the sacrificial layer ML1 includes an opaque metal, the sacrificial layer ML1 may absorb the laser light LASER. Therefore, thermal expansion of the sacrificial layer ML1 may occur, and the sacrificial layer ML1 to which the laser light LASER is irradiated may be lift-off from the insulating layers201to206. As a portion of the sacrificial layer ML1 is lift-off, the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230arranged on the sacrificial layer ML1 that is lift-off may be removed together. Therefore, as shown inFIG.10F, the transmission hole TAH may be formed, such that the transmission hole TAH includes openings of the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230. Because the recess R is formed around (e.g., adjacent to) the sacrificial layer ML1, disconnection of the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may occur (e.g., may easily occur) due to a step difference between the recess R and the sacrificial layer ML1. A melting point of a material of the sacrificial layer ML1 may be higher than a melting point of a material of the opposite electrode223. For example, in an embodiment, the sacrificial layer ML1 may include titanium (Ti), and the opposite electrode223may include silver (Ag). In the case where the sacrificial layer ML1 includes silver (Ag), which may be the same material as that of the opposite electrode223, the sacrificial layer ML1 may be lift-off before the opposite electrode223on the sacrificial layer ML1 is melted, and thus, may combine with Ag of the opposite electrode223to act as foreign substances. In the present embodiment, because the sacrificial layer ML1 includes a material having a higher melting point than that of the opposite electrode223, the opposite electrode223may be melted first, and then the sacrificial layer ML1 may be lift-off, and thus, foreign substances such as Ag particles may not occur or may be reduced. However, the present disclosure is not limited thereto, and in some embodiments, it may be desired that the sacrificial layer ML1 includes the same material as that of the pixel electrode221, for example, to simplify a process, and in this case, the sacrificial layer ML1 may include the same material as that of the pixel electrode221. However, because the above described issue may occur in the case where the pixel electrode221includes Ag, the sacrificial layer ML1 according to the present embodiment may include the same material as that of the gate electrode (e.g., the second gate electrode GE′) of the thin film transistor (e.g., the second thin film transistor TFTo) to prevent or substantially prevent the above described issue from occurring. Referring toFIG.10G, the thin-film encapsulation layer300may be formed. The first inorganic encapsulation layer310and the second inorganic encapsulation layer330may be formed on the entire surface of the substrate100. The organic encapsulation layer320may be arranged to be outside the dam DAM. The first inorganic encapsulation layer310may directly contact the third gate insulating layer206inside the transmission hole TAH, the third gate insulating layer206being an inorganic insulating layer. The second inorganic encapsulation layer330may directly contact the first inorganic encapsulation layer310inside the transmission hole TAH. Referring toFIG.10H, the first opening10H may be formed by removing (e.g., portions of) the substrate100and the insulating layers above the substrate100along a cutting line CL. In the present embodiment, because the first functional layer222a, the second functional layer222c, and the capping layer230may each include an organic material and are not exposed through the lateral wall of the first opening10H, the penetration of moisture through the first opening10H may be prevented or substantially prevented. In the display panel according to one or more example embodiments, the organic material layers around (e.g., surrounding) the opening may be removed by a laser lift process, and damage to the display elements by foreign substances, for example, such as external moisture may be prevented or substantially prevented. However, aspects and features of the present disclosure are not limited thereto. Although some example embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in the example embodiments without departing from the spirit and scope of the present disclosure. It will be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless otherwise described. Thus, as would be apparent to one of ordinary skill in the art, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed herein, and that various modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims, and their equivalents. | 72,340 |
11943976 | DETAILED DESCRIPTION OF THE EMBODIMENTS The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the disclosure and like reference numerals refer to like elements throughout the specification. When a layer, film, region, substrate, or area, is referred to as being “on” another layer, film, region, substrate, or area, it may be directly on the other film, region, substrate, or area, or intervening films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly on” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, is referred to as being “below” another layer, film, region, substrate, or area, it may be directly below the other layer, film, region, substrate, or area, or intervening layers, films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly below” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity. The spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations. Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to another element, or “electrically connected” to another element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “comprising,” “includes” and/or “including” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof. In the drawings, sizes and thicknesses of elements may be enlarged for better understanding, clarity, and ease of description thereof. However, the disclosure is not limited to the illustrated sizes and thicknesses. In the drawings, the thicknesses of layers, films, panels, regions, and other elements, may be exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas may be exaggerated. Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross-section taken by vertically cutting an object portion is viewed from the side. Additionally, the terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The terms “face” and “facing” mean that a first element may directly or indirectly oppose a second element. In a case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other. When an element is described as ‘not overlapping’ or ‘to not overlap’ another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. In the specification and the claims, the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the disclosure. Similarly, the second element could also be termed the first element. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments pertain. In addition, it will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments will hereinafter be described with reference to the accompanying drawings. FIG.1is a plan view of a display device according to an embodiment. Referring toFIG.1, examples of a display device1may include many varieties or types of electronic devices that may provide a display screen or screens. For example, the display device1may be a television (TV), a notebook computer, a monitor, a billboard, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watchphone, a mobile communication terminal, an electronic notepad, an electronic book reader, a portable multimedia player (PMP), a navigation device, a gaming console, a digital camera, an Internet-of-Things (IoT) device, or the like within the spirit and the scope of the disclosure. The display device1is illustrated as being a TV, but the disclosure is not limited thereto. The display device1may have a high or ultra-high definition of 4K, 8K, or the like within the spirit and the scope of the disclosure. The display device1may be classified according to how it displays an image or images. For example, the display device1may be classified as an organic light-emitting diode (OLED) display device, an inorganic electroluminescent (EL) display device, a quantum-dot light-emitting diode (QED) display device, a micro-light-emitting diode (micro-LED) display device, a plasma display panel (PDP) display device, a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, or an electrophoretic display (EPD) device. The display device1will hereinafter be described as being, for example, an OLED display device, but the disclosure is not limited thereto. For example, the display device1may also be applicable to various other display devices than an OLED display device without departing from the spirit and scope of the disclosure. The display device1may have a substantially rectangular shape in a plan view. In a case where the display device1is a TV, the display device1may be arranged so that its long sides may be aligned in a horizontal direction, but the disclosure is not limited thereto. Alternatively, the display device1may be arranged so that its long sides may be aligned in a vertical direction. Alternatively, the display device1may be rotatably installed so that its long sides may be aligned variably either in the horizontal direction or in the vertical direction. The display device1may include a display area DPA and a non-display area NDA. The display area DPA may be an active region in which an image or images may be displayed. The display area DPA, like the display device1, may have a substantially rectangular shape in a plan view. The display area DPA may include pixels PX. The pixels PX may be arranged in row and column directions. The pixels PX may have a substantially rectangular or square shape in a plan view, but the disclosure is not limited thereto. Alternatively, the pixels PX may have a substantially rhombus shape in a plan view so that the sides of each of the pixels PX may be inclined with respect to the sides of the display device1. The pixels PX may include multiple groups of pixels PX that may display different colors. For example, the pixels PX may include first, second, and third color pixels, which may be red, green, and blue pixels, respectively, but the disclosure is not limited thereto. The pixels PX may be alternately arranged in a stripe or PenTile arrangement. The non-display area NDA may be located or disposed on the periphery of the display area DPA. The non-display area NDA may surround the entire display area DPA or part of the display area DPA. The display area DPA may have a substantially rectangular shape, and the non-display area NDA may be located or disposed adjacent to all four sides of the display area DPA. The non-display area NDA may form the bezel of the display device1, for example. Driving circuits or driving elements for driving the display area DPA may be located or disposed in the non-display area NDA. For example, in first and second non-display areas NDA1, NDA2adjacent to first and second long sides (e.g., the lower and upper sides), respectively, of the display device1, a pad area may be provided on a display substrate of the display device1, and external devices EXD may be mounted on pad electrodes of the pad area. Examples of the external devices EXD may include a connecting film, a printed circuit board (PCB), a driving integrated chip (DIC), a connector, a wire connecting film, and the like. For example, in a third non-display area NDA3adjacent to a first short side (e.g., the left side) of the display device1, a scan driver SDR may be formed directly on the display substrate of the display device1. FIG.2is a schematic cross-sectional view of the display device ofFIG.1. FIG.2illustrates a top emission-type display device which emits light L in a direction away from a first substrate1010where emission layers EML may be formed (i.e., in a direction toward a second substrate21), but the disclosure is not limited thereto. Referring toFIG.2, the display device1may include the emission layers EML, an encapsulation film ENC which may cover the emission layers EML, and a color control structure (WCL, TPL, and CFL) which may be located or disposed on the encapsulation film ENC. The display device1may include a first display substrate10and a second display substrate20which may be opposite to the first display substrate10. The emission layers EML, the encapsulation film ENC, and the color control structure (WCL, TPL, and CFL) may be included in, for example, one of the first and second display substrates10and20. For example, the first display substrate10may include the first substrate1010, the emission layers EML which may be located or disposed on a first surface of the first substrate1010, and the encapsulation film ENC which may be located or disposed on the emission layers EML. For example, the second display substrate20may include the second substrate21and the color control structure (WCL, TPL, and CFL) which may be located or disposed on a first surface of the second substrate21that may face the first substrate1010. The color control structure (WCL, TPL, and CFL) may include color filter layers CFL and wavelength conversion layers WCL. The color control structure (WCL, TPL, and CFL) may include a light-transmitting layer TPL which may be located or disposed in some pixels to be on a level with the wavelength conversion layers WCL. A filler layer30may be located or disposed between the encapsulation film ENC and the color control structure (WCL, TPL, and CFL). The filler layer30may bond the first and second display substrates10and20while filling the space between the first and second display substrates10and20. The first substrate1010of the first display substrate10may be an insulating substrate. The first substrate1010may include a transparent material. For example, the first substrate1010may include a transparent insulating material such as glass, quartz, or the like. The first substrate1010may be a rigid substrate, but the disclosure is not limited thereto. Alternatively, the first substrate1010may include a plastic material such as polyimide and may have flexibility, in which case, the first substrate1010may be bendable, foldable, or rollable, or generally flexible. Pixel electrodes PXE may be located or disposed on the first surface of the first substrate1010. The pixel electrodes PXE may be located or disposed in the respective pixels PX. The pixel electrodes PXE may be separated between adjacent pixels PX. The circuit layer CCL, which may drive the pixels PX, may be located or disposed on the first substrate1010. The circuit layer CCL may be located or disposed between the first substrate1010and the pixel electrodes PXE. The circuit layer CCL will be described later in detail. The pixel electrodes PXE may be the first electrodes of light-emitting elements, e.g., anode electrodes. The pixel electrodes PXE may have a stack of a layer of a high-work function material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) and a layer of a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. The high-work function material layer may be located or disposed on the reflective material layer to be closer than the reflective material layer to the emission layers EML. The pixel electrodes PXE may have a multilayer structure of ITO/Mg, ITO/MgF, ITO/Ag, or ITO/Ag/ITO, but the disclosure is not limited thereto. A pixel-defining film PDL may be located or disposed on the first surface of the first substrate1010along the boundaries between the pixels PX. The pixel-defining film PDL may be located or disposed on the pixel electrodes PXE and may include openings which may expose the pixel electrodes PXE. Due to the pixel-defining film PDL and the openings of the pixel-defining film PDL, emission areas EMA and non-emission areas NEM may be defined. The pixel-defining film PDL may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). The pixel-defining film PDL may include an inorganic material. The emission layers EML may be located or disposed on the pixel electrodes PXE exposed by the pixel-defining film PDL. In a case where the display device1is an OLED display device, the emission layers EML may include an organic layer including an organic material. The organic layer may include an organic light-emitting layer and may include a hole injection/transport layer and/or an electron injection/transport layer as auxiliary layers for assisting the emission of light within the spirit and the scope of the disclosure. In a case where the display device1is an LED display device, the emission layers EML may include an inorganic material such as an inorganic semiconductor. In an embodiment, each of the emission layers EML may have a tandem structure in which organic light-emitting layers may be stacked in a thickness direction with charge generating layers located or disposed therebetween. The organic light-emitting layers may emit light of the same wavelength or may emit light of different wavelengths. At least some of the layers of each of the emission layers EML may be separated between adjacent pixels PX. The emission layers EML may all emit light of the same color in all the pixels PX. For example, the emission layers EML may emit blue light or ultraviolet (UV) light, and the wavelength conversion layers WCL of the color control structure (WCL, TPL, and CFL) may control the pixels PX to display different colors. Alternatively, the wavelength of light emitted by each of the emission layers EML may differ from one pixel PX to another pixel PX. For example, the emission layers EML may emit light of a first color in a first color pixel, light of a second color in a second color pixel, and light of a third color in a third color pixel. A common electrode CME may be located or disposed on the emission layers EML. The common electrode CME may be in contact not only with the emission layers EML, but also with the top surface of the pixel-defining film PDL. The common electrode CME may be electrically connected throughout the pixels PX. The common electrode CME may be located or disposed on the entire surface of the first substrate1010regardless of the distinction between the pixels PX. The common electrode CME may be the second electrode of each of the light-emitting elements, e.g., a cathode electrode. The common electrode CME may include a layer of a low-work function material such as Li, Ca, LiF/Ca, LiF/Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., the mixture of Ag and Mg). The common electrode CME may include a transparent metal oxide layer which may be located or disposed on the low-work function material layer. The pixel electrodes PXE, the emission layers EML, and the common electrode CME may form the light-emitting elements (e.g., OLEDs). Light may be emitted upwardly from the emission layers EML through the common electrode CME. The encapsulation film ENC may be located or disposed on the common electrode CME. The encapsulation film ENC may include at least one encapsulation layer. For example, the encapsulation layer may include a first inorganic film ENC1, an organic film ENC2, and a second inorganic film ENC3. The first and second inorganic films ENC1and ENC3may include silicon nitride, silicon oxide, or silicon oxynitride. The organic film ENC2may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or BCB. The second display substrate20may be located or disposed on the encapsulation film ENC to face the encapsulation film ENC. The second substrate21of the second display substrate20may include a transparent material. The second substrate21may include a transparent insulating material such as glass or quartz. The second substrate21may be a rigid structure, but the disclosure is not limited thereto. Alternatively, the second substrate21may include a plastic material such as polyimide and may have flexibility, in which case, the first substrate1010may be bendable, foldable, or rollable, or generally flexible. The second substrate21may be the same as the first substrate1010or may differ from the first substrate1010in material, thickness, and transmissivity thereof. For example, the second substrate21may have a higher transmissivity than the first substrate1010and may be thicker or thinner than the first substrate1010. A light-blocking member BM may be located or disposed on the first surface of the second substrate21along the boundaries between the pixels PX. The light-blocking member BM may overlap the pixel-defining film PDL and may be located or disposed in the non-emission areas NEM. The light-blocking member BM may include openings which may expose portions of the first surface of the second substrate21that overlap the emission areas EMA. The light-blocking member BM may be formed in a lattice shape in a plan view. The light-blocking member BM may include an organic material. The light-blocking member BM may absorb external light and may thus reduce color distortions that may be caused by the reflection of external light. The light-blocking member BM may prevent light emitted from the emission layers EML from infiltrating into adjacent pixels PX. The light-blocking member BM may absorb all visible wavelengths. The light-blocking member BM may include a light-absorbing material. For example, the light-blocking member BM may be formed of a material that may be used as a black matrix. The color filter layers CFL may be located or disposed on the first surface of the second substrate21where the light-blocking member BM is disposed. The color filter layers CFL may be located or disposed on portions of the first surface of the second substrate21that may be exposed by the openings of the light-blocking member BM. The color filter layers CFL may be located or disposed on the light-blocking member BM. The color filter layers CFL may include a first color filter layer CFL1which may be located or disposed in a first color pixel, a second color filter layer CFL2which may be located or disposed in a second color pixel, and the third color filter layer CFL3which may be located or disposed in a third color pixel. Each of the first, second, and third color filter layers CFL1, CFL2, and CFL3may include a colorant such as a pigment or dye that may absorb all wavelengths except for a particular wavelength. The first, second, and third color filter layers CFL1, CFL2, and CFL3may be red, green, and blue color filter layers, respectively, but the disclosure is not limited thereto. Adjacent color filter layers CFL are illustrated as being spaced apart from one another over the light-blocking member BM, but may partially overlap one another over the light-blocking member BM. A first capping layer22may be located or disposed on the color filter layers CFL. The first capping layer22may prevent impurities such as moisture or air from penetrating and contaminating the color filter layers CFL. The first capping layer22may prevent the diffusion of the colorants of the color filter layers CFL. The first capping layer22may be in direct contact with first surfaces (i.e., the bottom surfaces) of the color filter layers CFL. The first capping layer22may be formed of an inorganic material. For example, the first capping layer22may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, or silicon oxynitride. A barrier wall PTL may be located or disposed on the first capping layer22. The barrier wall PTL may be located or disposed in the non-emission areas NEM. The barrier wall PTL may be located or disposed to overlap the light-blocking member BM. The barrier wall PTL may include openings which may expose the color filter layers CFL. The barrier wall PTL may include a photosensitive organic material, but the disclosure is not limited thereto. The barrier wall PTL may include a light-shielding material. The wavelength conversion layers WCL and/or the light-transmitting layer TPL may be located or disposed in spaces exposed by the openings of the barrier wall PTL. The wavelength conversion layers WCL and the light-transmitting layer TPL may be formed by inkjet printing using the barrier walls PTL as banks, but the disclosure is not limited thereto. In a case where the emission layers EML emit light of the third color, the wavelength conversion layers WCL may include first and second wavelength conversion patterns WCL1and WCL2which may be located or disposed in the first and second color pixels, respectively. The light-transmitting layer TPL may be located or disposed in the third color pixel. The first wavelength conversion pattern WCL1may include a first base resin BRS1and a first wavelength conversion material WCP1which may be located or disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2may include a second base resin BRS2and a second wavelength conversion material WCP2which may be located or disposed in the second base resin BRS2. The light-transmitting layer TPL may include a third base resin BRS3and a scatterer SCP which may be located or disposed in the third base resin BRS3. The first, second, and third base resins BRS1, BRS2, and BRS3may include a light-transmitting organic material. For example, the first, second, and third base resins BRS1, BRS2, and BRS3may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first, second, and third base resins BRS1, BRS2, and BRS3may be formed of the same or similar material, but the disclosure is not limited thereto. The scatterer SCP may be particles of a metal oxide or particles of an organic material. Here, the metal oxide may be titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and the organic material may be an acrylic resin or a urethane resin. The first wavelength conversion material WCP1may convert the third color into the first color, and the second wavelength conversion material WCP2may convert the third color into the second color. The first and second wavelength conversion materials WCP1and WCP2may be quantum dots, quantum rods, or phosphors. The quantum dots may include a group IV nanocrystal material, a group II-VI compound nanocrystal material, a group III-V compound nanocrystal material, a group IV-VI nanocrystal material, or a combination thereof. Each of the first and second wavelength conversion patterns WCL1and WCL2may include a scatterer SCP which may improve the wavelength conversion efficiency of the first and second wavelength conversion patterns WCL1and WCL2. The light-transmitting layer TPL, which may be located or disposed in the third color pixel, transmits therethrough light of the third color incident thereupon from the emission layers EML while maintaining the wavelength of the incident light. The scatterer SCP of the light-transmitting layer TPL may control the path of light emitted through the light-transmitting layer TPL. The light-transmitting layer TPL may not include a wavelength conversion material. A second capping layer23may be located or disposed on the wavelength conversion layers WCL and the light-transmitting layer TPL. The second capping layer23may be formed of an inorganic material. The second capping layer23may include one selected from among the aforementioned materials for forming the first capping layer22. The second capping layer23may be formed of the same or similar material as the first capping layer22, but the disclosure is not limited thereto. The filler layer30may be located or disposed between the first and second display substrates10and20. The filler layer30may fill the space between the first and second display substrates10and20and may bond the first and second display substrates10and20. The filler layer30may be located or disposed between the encapsulation film ENC of the first display substrate1010and the second capping layer23of the second display substrate20. The filler layer30may be formed of a Si-based organic material or an epoxy-based organic material, but the disclosure is not limited thereto. The circuit layer CCL of the display device1will hereinafter be described. FIG.3is a layout view of the circuit layer of the first display substrate of the display device ofFIG.1. Referring toFIG.3, wires may be located or disposed on the first substrate1010of the first display substrate10. The wires may include scan lines SCL, sensing signal lines SSL, data lines DTL, reference voltage lines RVL, a first power supply line ELVDL, and a second power supply line ELVSL. The scan lines SCL and the sensing signal lines SSL may extend in a first direction DR1. The scan lines SCL and the sensing signal lines SSL may be electrically connected to the scan driver SDR. The scan driver SDR may include driving circuitry which consists of the circuit layer CCL. The scan driver SDR may be located or disposed in the third non-display area of the first substrate1010, but the disclosure is not limited thereto. Alternatively, the scan driver SDR may be located or disposed in the fourth non-display area NDA4, which may be on a second short side (e.g., the right side) of the display device1, or in both the third NDA3and fourth NDA4non-display areas. The scan driver SDR may be electrically connected to a signal connecting wire CWL, and at least a first end of the signal connecting wire CWL may form a pad WPD_CW in the first non-display area NDA1and/or in the second non-display area NDA2and may thus be electrically connected to the external devices EXD ofFIG.1. The data lines DTL and the reference voltage lines RVL may extend in a second direction DR2which may intersect the first direction DR1. The first and second power supply lines ELVDL and ELVSL may include portions extending in the second direction DR2. The first and second power supply lines ELVDL and ELVSL may include portions extending in the first direction DR1. The first and second power supply lines ELVDL and ELVSL may have a mesh structure, but the disclosure is not limited thereto. Wire pads WPD may be located or disposed at least first ends of the data lines DTL, the reference voltage lines RVL, and the first and second power supply lines ELVDL and ELVSL. The wire pads WPD may be located or disposed in the non-emission areas NDA. Wire pads WPD_DT (hereinafter, the data pads WPD_DT) of the data lines DTL may be located or disposed in the first non-display area NDA1, and wire pads WPD_RV (hereinafter, the reference voltage pads WPD_RV) of the reference voltage lines RVL, a wire pad WPD_ELVD (hereinafter, the first power supply pad WPD_ELVD) of the first power supply line ELVDL, and a wire pad WPD_ELVS (hereinafter, the second power supply pad WPD_ELVS) of the second power supply line ELVSL) may be located or disposed in the second non-display area NDA2. Alternatively, the data pads WPD_DT, the reference voltage pads WPD_RV, the first power supply pad WPD_ELVD, and the second power supply pad WPD_ELVS may all be located or disposed in the same area, e.g., in the first non-display area NDA1. The external devices EXD ofFIG.1may be mounted on the wire pads WPD. The external devices EXD may be mounted on the wire pads WPD via anisotropic conductive films or via ultrasonic bonding, but the disclosure is not limited thereto. The pixels PX on the first substrate1010may include pixel driving circuits. The aforementioned wires may pass through or around the pixels PX to apply driving signals to the pixel driving circuits. Each of the pixel driving circuits may include one or more transistors and one or more capacitors. The numbers of transistors and capacitors provided in each of the pixel driving circuits may vary. The pixel driving circuits will hereinafter be described as having a “3T1C” structure consisting of three transistors and one capacitor, but the disclosure is not limited thereto. For example, various other structures such as a “2T1C” structure, a “7T1C” structure, or a “6T1C” structure may also be applicable to the pixels PX. FIG.4is an equivalent circuit diagram of a pixel of the display device ofFIG.1. Referring toFIG.4, a pixel PX of the display device1may include a light-emitting element EMD, three transistors (DTR, STR1, and STR2), and a storage capacitor CST. The light-emitting element EMD may emit light in accordance with a current supplied thereto via a driving transistor DTR. The light-emitting element EMD may be implemented as an OLED, a micro-LED, or a nano-LED, but the disclosure is not limited thereto. The first electrode (i.e., the anode electrode) of the light-emitting element EMD may be electrically connected to the source electrode of the driving transistor DTR, and the second electrode (i.e., the cathode electrode) of the light-emitting element EMD may be electrically connected to a second power supply line ELVSL to which a low-potential voltage, i.e., a second power supply voltage, may be supplied. The second power supply voltage may be lower than a high-potential voltage applied to the first power supply line ELVDL, i.e., a first power supply voltage. The driving transistor DTR may control a current that may flow from the first power supply line ELVDL to the light-emitting element EMD, in accordance with the difference in voltage between the gate and source electrodes of the driving transistor DTR. The gate electrode of the driving transistor DTR may be electrically connected to the second source/drain electrode of a first switching transistor STR1, the source electrode of the driving transistor DTR may be electrically connected to the first electrode of the light-emitting element EMD, and the drain electrode of the driving transistor DTR may be electrically connected to the first power supply line ELVDL to which the first power supply voltage may be applied. The first switching transistor STR1may be turned on by a scan signal from a scan line SCL to connect a data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first switching transistor STR1may be electrically connected to the scan line SCL, the first source/drain electrode of the first switching transistor STR1may be electrically connected to the data line DTL, and the second source/drain electrode of the first switching transistor STR1may be electrically connected to the gate electrode of the driving transistor DTR. A second switching transistor STR2may be turned on by a sensing signal from a sensing signal line SSL to connect a reference voltage line RVL to the source electrode of the driving transistor DTR. The gate electrode of the second switching transistor STR2may be electrically connected to the sensing signal line SSL, the first source/drain electrode of the second switching transistor STR2may be electrically connected to the reference voltage line RVL, and the second source/drain electrode of the second switching transistor STR2may be electrically connected to the source electrode of the driving transistor DTR. The first source/drain electrodes of the first and second switching transistors STR1and STR2may be source electrodes, and the second source/drain electrodes of the first and second switching transistors STR1and STR2may be drain electrodes. However, the disclosure is not limited to this. Alternatively, the first source/drain electrodes of the first and second switching transistors STR1and STR2may be drain electrodes, and the second source/drain electrodes of the first and second switching transistors STR1and STR2may be source electrodes. The storage capacitor CST may be formed between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST may store the differential voltage between the gate and source voltages of the driving transistor DTR. The driving transistor DTR and the first and second switching transistors STR1and STR2may be formed as thin-film transistors (TFTs).FIG.3illustrates that the driving transistor DTR and the first and second switching transistors STR1and STR2may be N-type metal oxide semiconductor field effect transistors (MOSFETs), but the disclosure is not limited thereto. Alternatively, the driving transistor DTR and the first and second switching transistors STR1and STR2may be formed as P-type MOSFETs. As an example, at least one of the driving transistor DTR and the first and second switching transistors STR1and STR2may be formed as an N-type MOSFET, and the other transistors may be formed as P-type MOSFETs. FIG.5is a layout view of a pixel of the display device ofFIG.1.FIG.6is a cutout layout view illustrating a part Q ofFIG.5.FIG.7illustrates schematic cross-sectional views taken along lines I-I′, II-II′, and ofFIG.5. FIG.7illustrates schematic cross-sectional views, taken along lines I-I′ and II-II′ ofFIG.5, of part of the display area DPA and a schematic cross-sectional view, taken along line III-III′ ofFIG.5, of part of the non-display area NDA. For example,FIG.7illustrates the display area DPA, as an example, a driving transistor region DTR where a driving transistor DTR may be disposed, a first switching transistor region STR1where a first switching transistor STR1may be disposed, and a capacitor region CPR where a storage capacitor CST may be disposed, and also illustrates the non-display area NDA, for example, a pad area PDA. For convenience,FIG.7mainly illustrates the circuit layer CCL of the first display substrate10that ranges from the first substrate1010to the pixel-defining film PDL. Multiple layers located or disposed in one pixel PX of the display device1will hereinafter be described with reference toFIGS.5through7. Referring toFIGS.5and7, a pixel PX may include transistors (DTR, STR1, and STR2) and a storage capacitor CST. Each of the transistors (DTR, STR1, and STR2) may include conductive layers that may form electrodes, semiconductor patterns that may form a channel, and an insulating layer. The storage capacitor CST may include an insulating layer that may be located or disposed between the conductive layers that form the electrodes. For example, the storage capacitor CST may include a capacitor lower electrode, a capacitor upper electrode and an insulating layer located or disposed between the capacitor lower electrode and the capacitor upper electrode. The aforementioned conductive materials or layers, the semiconductor patterns, and the insulating layers may be located or disposed on the first substrate1010. The circuit layer CCL of the display device1may include a semiconductor layer1200, conductive layers, and insulating layers. The conductive layers may include a first conductive layer1100, a second conductive layer1300, and a pixel electrode PXE. The insulating layers may include an interlayer insulating film1610, a gate insulating film1620, a passivation layer1630, and a planarization film1650. The first conductive layer1110, the interlayer insulating film1610, semiconductor patterns1200, the gate insulating film1620, the second conductive layer1300, the passivation layer1630, and the planarization film1650may be sequentially located or disposed on the first substrate1010. The first conductive layer1100the interlayer insulating film1610, semiconductor patterns1200, the gate insulating film1620, the second conductive layer1300, the passivation layer1630, and the planarization film1650may be formed as single-layer films or as multilayer films each including multiple films. There may be additionally provided layers located or disposed between first conductive layer1110, the interlayer insulating film1610, semiconductor patterns1200, the gate insulating film1620, the second conductive layer1300, the passivation layer1630, and the planarization film1650. The first conductive layer1100may be located or disposed on the first substrate1010. In the display area DPA, the first conductive layer1100may include a first power supply wire1110, which may correspond to the first power supply line ELVDL ofFIG.3, a capacitor lower electrode1121, a capacitor lower electrode first extension1123, a capacitor lower electrode second extension1125, a data signal line1130, which may correspond to the data line DTL ofFIG.3, a second power supply wire1140, which may correspond to the second power supply line ELVSL ofFIG.3, and a reference voltage connecting electrode1150. In the non-display area NDA, the first conductive layer1100may include a data pad1160. The first conductive layer1100may include other lines, wires, and electrodes within the spirit and scope of the disclosure and is not limited to the above description or that which is illustrated in the drawings. The first power supply wire1110may be located or disposed at the center of the pixel PX in a plan view. The first power supply wire1110may extend in the second direction DR2. The first power supply line1110may extend from the pixel PX to neighboring pixels PX in the second direction DR2. The first power supply wire1110may pass through the driving transistor region DTR. The first power supply wire1110may be located or disposed to pass through at least part of the driving transistor region DTR and may overlap, in a thickness direction, with at least part of the first conductive region of a first semiconductor pattern1210and with at least part of a driving transistor first electrode1371. In a plan view, the data signal line1130may be located or disposed on the right side of the first power supply wire1110to be apart from the first power supply line1110. In a plan view, the data signal line1130may be located or disposed on the right side of the pixel PX to extend in the second direction DR2. The data signal line1130may extend from the pixel PX to the neighboring pixels PX in the second direction DR2. The data signal line1130may pass through the first switching transistor region STR1. The data signal line1130may be located or disposed to pass at least part of the first switching transistor region STR1and may overlap, in the thickness direction, at least part of the first conductive region of a second semiconductor pattern1220and at least part of a first switching transistor first electrode1377. In a plan view, the second power supply wire1140may be located or disposed on the left side of the first power supply wire1110to be apart from the first power supply wire1110. In a plan view, the second power supply wire1140may be located or disposed on the left side of the pixel PX to extend in the second direction DR2. The second power supply wire1140may extend from the pixel PX to the neighboring pixels PX in the second direction DR2. The second power supply wire1140may include a wide part1141and a narrow part1142. The width, in the first direction DR1, of the wide part1141may be greater than the width, in the first direction DR1, of the narrow part1142. The second power supply wire1140may generally consist of the wide part1141, but may include the narrow part1142in an area that may overlap the second conductive layer1300in the thickness direction. Since the second power supply wire1140consists of the narrow part1142in the area that may overlap the second conductive layer1300in the thickness direction, the interference or the resistance between the first and second conductive layers1100and1300may be reduced. The capacitor lower electrode1121may extend across the center of the pixel PX and may be located or disposed between the first power supply wire1110and the data signal line1130in a plan view. For example, the capacitor lower electrode1121may be located or disposed on the right side of the first power supply wire1110and on the left side of the data signal line1130to be apart from the first power supply wire1110and the data signal line1130. For example, the capacitor lower electrode1121may protrude from the upper left side of a rectangular shape in an upward direction (or in the second direction DR2) and may also protrude from the lower left side of the rectangular shape in a downward direction (or in the opposite direction of the second direction DR2), but the disclosure is not limited thereto. The capacitor lower electrode1121may be located or disposed in the capacitor region CPR or the entire capacitor region CPR. The capacitor lower electrode1121may be located or disposed in the entire capacitor region CPR and may extend to the outside of the capacitor region CPR over the first substrate1010. Part of the capacitor lower electrode1121on the outside of the capacitor region CPR may be electrically connected to the pixel electrode PXE through a contact hole CNT3. The capacitor lower electrode first extension1123may be located or disposed to protrude from the upper right side of the capacitor lower electrode1121in the upward direction (or in the second direction DR2). The capacitor lower electrode first extension1123may be located or disposed between the data signal line1130and part of the capacitor lower electrode1121that protrudes from the upper left side of the capacitor lower electrode1121and may thus be spaced apart from the capacitor lower electrode1121and the data signal line1130. The capacitor lower electrode first extension1123may have a substantially rectangular shape that may extend longer in the second direction DR2than in the first direction DR1, but the disclosure is not limited thereto. The capacitor lower electrode first extension1123may be located or disposed to pass through at least part of the first switching transistor region STR1and may overlap, in the thickness direction, at least part of the first switching transistor second electrode1333and with at least part of the second conductive region of the second semiconductor pattern1220. The capacitor lower electrode second extension1125may be located or disposed to protrude from the lower left side of the capacitor lower electrode1121in the downward direction (or in the opposite direction of the second direction DR2). The capacitor lower electrode second extension1125may be located or disposed between the first power supply wire1110and the data signal line1130to be apart from the first power supply wire1110and the data signal line1130. The capacitor lower electrode second extension1125may have a substantially rectangular shape that may extend longer in the second direction DR2than in the first direction DR1, but the disclosure is not limited thereto. The capacitor lower electrode second extension1125may be located or disposed to pass through at least part of the driving transistor region DTR and may overlap, in the thickness direction, at least part of the second conductive region of the first semiconductor pattern1210and with a driving transistor second electrode1373. The capacitor lower electrode1121, the capacitor lower electrode first extension1123, and the capacitor lower electrode second extension1125may be integrally formed as a single first conductive pattern. The reference voltage connecting electrode1150may be located or disposed in the gaps between the capacitor lower electrode second extension1125, the data signal line1130, and the capacitor lower electrode1121. For example, in a plan view, the reference voltage connecting electrode1150may be located or disposed on the right side of the capacitor lower electrode second extension1125, on the left side of the data signal line1130, and on the lower side of the capacitor lower electrode1121. The reference voltage connecting electrode1150may be spaced apart from the capacitor lower electrode second extension1125, the data signal line1130, and the capacitor lower electrode1121. For example, the reference voltage connecting electrode1150may have a substantially rectangular shape that may extend longer in the second direction DR2than in the first direction DR1. In this case, the reference voltage connecting electrode1150may extend beyond the capacitor lower electrode second extension1125in the opposite direction of the second direction DR2so that the lower short side of the reference voltage connecting electrode1150may be located or disposed below the lower short side of the capacitor lower electrode second extension1125. The data pad1160may be located or disposed in the pad area PDA of the non-display area NDA. The data pad1160may have a substantially square shape that may extend by the same length in both the first and second directions DR1and DR2. Since the data signal line1130may extend in the second direction DR2to the pad area PDA of the non-display area NDA, the data pad1160may be provided at the end of the data signal line1130. The first conductive layer1100may include at least one metal selected from among Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer1100may be a single- or multi-layer film. The interlayer insulating film1610may be located or disposed on the first conductive layer1100. The interlayer insulating film1610may be located or disposed, in the display area DPA and the non-display area NDA, on the first conductive layer1100and on parts of the first substrate1010exposed by the first conductive layer1100. The interlayer insulating film1610may include contact holes CNT2which may expose parts of the first conductive layer1100. The top surface of the first conductive layer1100may be in contact with at least part of the second conductive layer1300through the contact holes CNT2and with the pixel electrode PXE through the contact hole CNT3. The interlayer insulating film1610may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide or an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or BCB. For example, the interlayer insulating film1610may include SiON. The interlayer insulating film1610may be a single-layer film or a multilayer film including a stack of different materials. The semiconductor layer1200may be located or disposed on the interlayer insulating film1610. The semiconductor layer1200may include the first and second semiconductor patterns1210and1220. The first semiconductor pattern1210may correspond to the active layers of the driving transistor DTR and a second switching transistor STR2, and the second semiconductor pattern1220may correspond to the active layer of the first switching transistor STR1. The semiconductor layer1200may include an oxide semiconductor. The oxide semiconductor may include a binary compound (ABx), a ternary compound (ABxCy), or a quaternary compound (ABxCyDz) containing, for example, indium (In), zinc (Zn), gallium (Ga), tin (Sn), Ti (titanium), Al (aluminum), hafnium (Hf), zirconium (Zr), or Mg (magnesium). For example, the semiconductor layer1200may include indium tin zinc oxide (IGZO). The first and second semiconductor patterns1210and1220may have a predetermined shape in a plan view. For example, each of the first and second semiconductor patterns1210and1220may generally extend in the first direction DR1, and both end parts of each of the first and second semiconductor patterns1210and1220may be expanded in the second direction DR2to be wider than the rest of the corresponding semiconductor pattern. The first semiconductor pattern1210may include an extension that may extend in the first direction DR1and pairs of expanded parts that may extend in the second direction DR2from both sides of the extension by the same or similar distance. Referring toFIG.6, for example, the first semiconductor pattern1210may include an extension1210X which may extend in the first direction DR1, a first conductive region1210a, which may be located or disposed on a first side of the extension and includes expanded parts1210Y that may extend in the second direction DR2, a third conductive region1210cwhich may be located or disposed on a second side of the extension that may be opposite to the first side of the extension and includes expanded parts that extend in the second direction DR2, and a second conductive region1210bwhich may be located or disposed between the first and second sides of the extension and includes expanded parts that extend in the second direction DR2. For example, the first and second sides of the extension may be the left and right sides, respectively, of the extension, but the disclosure is not limited thereto. In a plan view, the first semiconductor pattern1210may be located or disposed on the lower side of the capacitor lower electrode1121, which may be located or disposed at the center of the pixel PX. The first conductive region1210aof the first semiconductor pattern1210may be located or disposed on the first power supply wire1110in the second direction DR2to overlap the first power supply wire1110in the thickness direction, the second conductive region1210bof the first semiconductor pattern1210may be located or disposed on the capacitor lower electrode second extension1125in the second direction DR2to overlap the capacitor lower electrode second extension1125in the thickness direction, and the third conductive region1210cof the first semiconductor pattern1210may be located or disposed on the reference voltage connecting electrode1150in the second direction DR2to overlap the reference voltage connecting electrode1150. The first and second conductive regions1210aand1210bof the first semiconductor pattern1210and part of the extension of the first semiconductor pattern1210that may connect the first and second conductive regions1210aand1210bmay correspond to the active layer of the driving transistor DTR. The first conductive region1210amay correspond to the first source/drain region of the driving transistor DTR, and the part of the extension of the first semiconductor pattern1210that may connect the first and second conductive regions1210aand1210bmay be the channel region of the driving transistor DTR. The second and third conductive regions1210band1210cof the first semiconductor pattern1210and part of the extension of the first semiconductor pattern1210that may connect the second and third conductive regions1210band1210cmay correspond to the active layer of the second switching transistor STR2. The third conductive region1210cmay be the first source/drain region of the second switching transistor STR2, and the part of the extension of the first semiconductor pattern1210that may connect the second and third conductive regions1210band1210cmay be the channel region of the second switching transistor STR2. The second conductive region1210bof the first semiconductor pattern1210may be the second source/drain region of the driving transistor DTR and the second source/drain region of the second switching transistor STR2. In a plan view, the second semiconductor pattern1220may be located or disposed on the upper side of the center of the pixel PX. In a plan view, the second semiconductor pattern1220may include an extension which may extend in the first direction DR1, a second conductive region which may be located or disposed on a first side of the extension and may extend in the second direction DR2, and a first conductive region which may be located or disposed on a second side of the extension and extends in the second direction DR2. For example, the first and second sides of the extension of the second semiconductor pattern1220may be the left and right sides, respectively, of the extension of the second semiconductor pattern1220, but the disclosure is not limited thereto. The second conductive region of the second semiconductor pattern1220may be located or disposed on the capacitor lower electrode first extension1123to overlap the capacitor lower electrode first extension1123, and the first conductive region of the second semiconductor pattern1220may be located or disposed on the data signal line1130in the second direction DR2to overlap the data signal line1130. The first and second conductive regions of the second semiconductor pattern1220and the extension of the second semiconductor pattern1220that may connect the first and second conductive regions of the second semiconductor pattern1220may correspond to the active layer of the first switching transistor STR1. The second conductive region of the second semiconductor pattern1220may be the second source/drain region of the first switching transistor STR1, the first conductive region of the second semiconductor pattern1220may be the first source/drain region of the first switching transistor STR1, and the extension of the second semiconductor pattern1220may be the channel region of the first switching transistor STR1. The gate insulating film1620may be located or disposed on the semiconductor layer1200. The gate insulating film1620may be located or disposed in the display area DPA and the non-display area NDA. In the gate insulating film1620, contact holes CNT1which may expose parts of the semiconductor layer1200and contact holes CNT2which may expose parts of the first conductive layer1100may be formed to penetrate the gate insulating film1620. The gate insulating film1620may include a silicon compound, a metal oxide, or the like, within the spirit and the scope of the disclosure. For example, the gate insulating film1620may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, and these materials may be used alone or in combination. The gate insulating film1620may be a single-layer film or a multilayer film having a stack of different materials. The gate insulating film1620may be formed similar to the second conductive layer1300. Thus, the sides of the gate insulating film1620may be generally aligned with the sides of the second conductive layer1300, which may be located or disposed on the gate insulating film1620, but the disclosure is not limited thereto. The gate insulating film1620may be located or disposed to be patterned on parts of the semiconductor layer1200and on parts of the interlayer insulating film1610, but the disclosure is not limited thereto. Alternatively, the gate insulating film1620may include contact holes (CNT1and CNT2) and may be located or disposed on the semiconductor layer1200and on parts of the interlayer insulating film1610that may be exposed by the semiconductor layer1200. The second conductive layer1300may be located or disposed on the gate insulating film1620. In the display area DPA, the second conductive layer1300may include a second power supply auxiliary wire1310, a scan signal line1320, which may correspond to the scan line SCL ofFIG.3, a first switching transistor gate electrode1325, a capacitor upper electrode1331, a first switching transistor second electrode1333, a driving transistor gate electrode1335, a sensing signal line1340, which may correspond to the sensing signal line SSL ofFIG.4, a first power supply auxiliary wire1350, a reference voltage wire1360, which may correspond to the reference voltage line RVL ofFIG.4, a driving transistor first electrode1371, a transistor shared electrode1373, a second switching transistor first electrode1375. In the non-display area NDA, the second conductive layer1300may include a pad electrode1380. The second conductive layer1300may include other lines, wires, and electrodes within the spirit and scope of the disclosure and is not limited to the above description or that which is illustrated in the drawings. The second conductive layer1300may be formed of a low-resistance material. The second conductive layer1300may include a material such as Cu, Ti, Mo, Al, or Ag, but the disclosure is not limited thereto. The first conductive layer1100may be a single- or multi-layer film. For example, the second conductive layer1300may be a double-layer film of Ti/Cu, and the second conductive layer1300may have a stack of Ti/Cu. In a plan view, the second power supply auxiliary wire1310may be located or disposed on the upper side of the pixel PX. The second power supply auxiliary wire1310may extend in the first direction DR1. The second power supply auxiliary wire1310may extend from the pixel PX to neighboring pixels PX in the first direction DR1. The second power supply auxiliary wire1310may be located or disposed to intersect the narrow part1142of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, which may be located or disposed below the second power supply auxiliary wire1310. Accordingly, in a plan view, the second power supply auxiliary wire1310may overlap parts of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, on the upper side of the pixel PX. A contact hole CNT27may be formed at the intersection between the second power supply auxiliary wire1310and the second power supply wire1140. The second power supply auxiliary wire1310may be electrically connected to the second power supply wire1140through the contact hole CNT27. Although not illustrated inFIG.7, the second power supply auxiliary wire1310may be in contact with part of the top surface of the second power supply wire1140through the contact hole CNT27. Since the second power supply auxiliary wire1310may be electrically connected to the second power supply wire1140, a second power supply voltage may be evenly delivered to multiple pixels PX without being affected by any voltage drop. In a plan view, the scan signal line1320may be located or disposed on the lower side of the second power supply auxiliary wire1310to be apart from the second power supply auxiliary wire1310. The scan signal line1320may extend in the first direction DR1. The scan signal line1320may extend from the pixel PX to the neighboring pixels PX in the first direction DR1. The scan signal line1320may be located or disposed to intersect the narrow part1142of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, which may be located or disposed below the second conductive layer1300. Accordingly, in a plan view, the scan signal line1320may overlap parts of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, on the upper side of the pixel PX. The first switching transistor gate electrode1325may branch off from the scan signal line1320and may extend in the downward direction (i.e., in the opposite direction of the second direction DR2). At least part of the first switching transistor gate electrode1325may be located or disposed to overlap the extension of the second semiconductor pattern1220that may connect, in the first direction DR1, the first and second conductive regions of the second semiconductor pattern1220. The channel region of the first switching transistor STR1may be an area of the second semiconductor pattern1220where the first switching transistor gate electrode1325and the second semiconductor pattern1220may overlap. The capacitor upper electrode1331may be located or disposed on the capacitor lower electrode1121to overlap at least part of the capacitor lower electrode1121. The shape of the capacitor upper electrode1331may be substantially similar to the shape of the capacitor lower electrode1121. The capacitor upper electrode1331may be formed to have a smaller area than the capacitor lower electrode1121and thus to expose an upper left part of the capacitor lower electrode1121. The capacitor upper electrode1331may be located or disposed to overlap the capacitor lower electrode1121with the interlayer insulating film1610and the gate insulating layer1620interposed therebetween and thus to form the storage capacitor CST. The interlayer insulating film1610and the gate insulating layer1620, which may be interposed between the capacitor lower electrode1121and the capacitor upper electrode1331, may serve as the dielectrics of the storage capacitor CST. The first switching transistor second electrode1333may be formed to protrude from the upper right side of the capacitor upper electrode1331. The first switching transistor second electrode1333may branch off from the capacitor upper electrode1331in the second direction DR2and may be located or disposed to overlap the second conductive region of the second semiconductor pattern1220. The first switching transistor second electrode1333may be electrically connected to the second conductive region of the second semiconductor pattern1220through a contact hole CNT15. The first switching transistor second electrode1333may be the second source/drain electrode of the first switching transistor STR1. The driving transistor gate electrode1335may be formed to protrude from the lower left side of the capacitor upper electrode1331. The driving transistor gate electrode1335may branch off from the capacitor upper electrode1331in the opposite direction of the second direction DR2and may be located or disposed to overlap the part of the extension of the first semiconductor pattern1210that may connect the first and second conductive regions1210aand1210bof the first semiconductor pattern1210. An area of the first semiconductor pattern1220where the driving transistor gate electrode1335and the first semiconductor pattern1210may overlap may be the channel region of the driving transistor DTR. The driving transistor gate electrode1335may be the gate electrode of the driving transistor DTR. The capacitor upper electrode1331, the first switching transistor second electrode1333, and the driving transistor gate electrode1335may be integrally formed as a single second conductive pattern. In a plan view, the sensing signal line1340may be located or disposed on the lower side of the first semiconductor pattern1210to be apart from the first semiconductor pattern1210. The sensing signal line1340may extend in the first direction DR1. The sensing signal line1340may extend from the pixel PX to the neighboring pixels PX in the first direction DR1. The sensing signal line1340may be located or disposed to intersect the narrow part1142of the second power supply wire1140, the first power supply wire1110, the data signal line1130, and the reference voltage connecting electrode1150, which may be located or disposed below the sensing signal line1340. Accordingly, in a plan view, the sensing signal line1340may overlap parts of the second power supply wire1140, the first power supply wire1110, the data signal line1130, and the reference voltage connecting electrode1150, on the lower side of the pixel PX. The second switching transistor gate electrode1345may branch off from the sensing signal line1340and may extend in the upward direction (i.e., in the second direction DR2). At least part of the second switching transistor gate electrode1345may be located or disposed to overlap the extension of the first semiconductor pattern1210that may connect, in the first direction DR1, the second and third conductive regions1210band1210cof the first semiconductor pattern1210. The channel region of the second switching transistor STR2may be an area of the first semiconductor pattern1210where the second switching transistor gate electrode1345and the first semiconductor pattern1210may overlap. The second switching transistor gate electrode1345may be the gate electrode of the second switching transistor STR2. In a plan view, the first power supply auxiliary wire1350may be located or disposed on the lower side of the sensing signal line1340to be apart from the sensing signal line1340. In a plan view, the first power supply auxiliary wire1350may be located or disposed on the lower side of the pixel PX. The first power supply auxiliary wire1350may extend in the first direction DR1. The first power supply auxiliary wire1350may extend from the pixel PX to the neighboring pixels PX in the first direction DR1. The first power supply auxiliary wire1350may be located or disposed to intersect the narrow part1142of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, which may be located or disposed below the first power supply auxiliary wire1350. The first power supply auxiliary wire1350may overlap parts of the second power supply wire1140, the first power supply wire1110, and the data signal line1130, on the lower side of the pixel PX in a plan view. A contact hole CNT26may be formed at the intersection between the first power supply auxiliary wire1350and the first power supply wire1110. The first power supply auxiliary wire1350may be electrically connected to the first power supply wire1110through the contact hole CNT26. Although not illustrated inFIG.7, the first power supply auxiliary wire1350may be in contact with part of the top surface of the first power supply wire1110through the contact hole CNT26. Since the first power supply auxiliary wire1350may be electrically connected to the first power supply wire1110, a first power supply voltage may be evenly delivered to multiple pixels PX without being affected by any voltage drop. The reference voltage wire1360may be located or disposed between the sensing signal line1340and the first power supply auxiliary wire1350. The reference voltage wire1360may be formed to be apart from the sensing signal line1340and the first power supply auxiliary wire1350and to extend in the first direction DR1. The reference voltage wire1360may be located or disposed to overlap the reference voltage connecting electrode1150and the data signal line1130. One end of the reference voltage wire1360is illustrated as extending to a neighboring pixel PX to the left of the pixel PX, but the disclosure is not limited thereto. A contact hole CNT25may be formed in the overlapping area of the reference voltage wire1360and the reference voltage connecting electrode1150. The reference voltage wire1360may be electrically connected to the reference voltage connecting electrode1150through the contact hole CNT25. Although not illustrated inFIG.7, the reference voltage wire1360may be in contact with part of the top surface of the reference voltage connecting electrode1150through the contact hole CNT25. The reference voltage wire1360may transmit a reference voltage to the second switching transistor first electrode1375through the contact hole CNT25, the reference voltage connecting electrode1150, and a contact hole CNT14. The driving transistor first electrode1371may be located or disposed above the first conductive region1210aof the first semiconductor pattern1210to overlap the first conductive region1210aof the first semiconductor pattern1210and the first power supply wire1110. The driving transistor first electrode1371may extend in the second direction DR2, and the length, in the first direction DR1, of the driving transistor first electrode1371may be smaller than the length, in the second direction DR2, of the driving transistor first electrode1371. The driving transistor first electrode1371may extend upwardly from the overlapping area with the first conductive region1210aof the first semiconductor pattern1210and may thus overlap part of the first power supply wire1110that does not overlap the first conductive region1210aof the first semiconductor pattern1210. In the overlapping area with the part of the first power supply wire1110that may not overlap the first conductive region1210aof the first semiconductor pattern1210, the driving transistor first electrode1371may be in contact with, and electrically connected to the first power supply wire1110through a contact hole CNT21that may penetrate the interlayer insulating film1610and the gate insulating film1620to expose part of the first power supply wire1110. In a plan view, the contact hole CNT21may be located or disposed on the upper side of the driving transistor first electrode1371, but the disclosure is not limited thereto. The driving transistor first electrode1371may also be in contact with, and electrically connected, to the first conductive region1210aof the first semiconductor pattern1210through a contact hole CNT11that may penetrate the gate insulating film1620to expose the first conductive region1210aof the first semiconductor pattern1210. The contact hole CNT11may be located or disposed on the lower side of the contact hole CNT21in a plan view, but the disclosure is not limited thereto. The driving transistor first electrode1371, which may be located or disposed above the first conductive region1210aof the first semiconductor pattern1210, may be provided in the first source/drain region of the driving transistor DTR and may be the first source/drain electrode of the driving transistor DTR. For example, the first source/drain electrode of the driving transistor DTR may be the drain electrode of the driving transistor DTR. The transistor shared electrode1373may be located or disposed above the second conductive region1210bof the first semiconductor pattern1210to overlap the second conductive region1210bof the first semiconductor pattern1210and the capacitor lower electrode second extension1125. The transistor shared electrode1373may extend in the second direction DR2, and the length, in the first direction DR1, of the transistor shared electrode1373may be smaller than the length, in the second direction DR2, of the transistor shared electrode1373. The transistor shared electrode1373may extend upwardly from the overlapping area with the second conductive region1210bof the first semiconductor pattern1210and may thus overlap part of the capacitor lower electrode second extension1125that may not overlap the second conductive region1210bof the first semiconductor pattern1210. In the overlapping area with the part of the capacitor lower electrode second extension1125that does not overlap the second conductive region1210bof the first semiconductor pattern1210, the transistor shared electrode1373may be in contact with, and electrically connected to the capacitor lower electrode second extension1125through a contact hole CNT22that may penetrate the interlayer insulating film1610and the gate insulating film1620to expose part of the capacitor lower electrode second extension1125. In a plan view, the contact hole CNT22may be located or disposed on the upper side of the transistor shared electrode1373, but the disclosure is not limited thereto. The transistor shared electrode1373may also be in contact with, and electrically connected, to the second conductive region1210bof the first semiconductor pattern1210through a contact hole CNT12that may penetrate the gate insulating film1620to expose the second conductive region1210bof the first semiconductor pattern1210. The contact hole CNT12may be located or disposed on the lower side of the contact hole CNT22in a plan view, but the disclosure is not limited thereto. The transistor shared electrode1373, which may be located or disposed above the second conductive region1210bof the first semiconductor pattern1210, may be provided in the overlapping area of the driving transistor region DRT and the second switching transistor region STR2. The transistor shared electrode1373may be located or disposed in the second source/drain region of the driving transistor DTR and may be the second source/drain electrode of the driving transistor DTR. For example, the transistor shared electrode1373may be located or disposed in the second source/drain region of the second switching transistor STR2and may be the second electrode of the second switching transistor STR2. For example, the second source/drain electrode of the driving transistor DTR may be the source electrode of the driving transistor DTR, and the second electrode of the second switching transistor STR2may be the second source/drain electrode of the second switching transistor STR2. The second switching transistor first electrode1375may be located or disposed on the third conductive region1210cof the first semiconductor pattern1210to overlap the third conductive region1210cof the first semiconductor pattern1210and the reference voltage connecting electrode1150. The second switching transistor first electrode1375may extend in the second direction DR2, and the length, in the first direction DR1, of the second switching transistor first electrode1375may be smaller than the length, in the second direction DR2, of the second switching transistor first electrode1375. The second switching transistor first electrode1375may extend downwardly from the overlapping area with the third conductive region1210cof the first semiconductor pattern1210and may thus overlap part of the reference voltage connecting electrode1150that may not overlap the third conductive region1210cof the first semiconductor pattern1210. In the overlapping area with the part of the reference voltage connecting electrode1150that may not overlap the third conductive region1210cof the first semiconductor pattern1210, the second switching transistor first electrode1375may be in contact with, and electrically connected to the reference voltage connecting electrode1150through a contact hole CNT23that may penetrate the interlayer insulating film1610and the gate insulating film1620to expose part of the reference voltage connecting electrode1150. The contact hole CNT23may be located or disposed on the lower side of the second switching transistor first electrode1375in a plan view, but the disclosure is not limited thereto. The second switching transistor first electrode1375may also be in contact with, and electrically connected, to the third conductive region1210cof the first semiconductor pattern1210through a contact hole CNT14that may penetrate the gate insulating film1620to expose the third conductive region1210cof the first semiconductor pattern1210. In a plan view, the contact hole CNT14may be located or disposed on the upper side of the contact hole CNT23, but the disclosure is not limited thereto. The second switching transistor first electrode1375, which may be located or disposed above the third conductive region1210cof the first semiconductor pattern1210, may be provided in the first source/drain region of the second switching transistor STR2and may be the first electrode of the second switching transistor STR2. The first electrode of the second switching transistor STR2may be the first source/drain electrode of the second switching transistor STR2. The first switching transistor first electrode1377may be located or disposed on the first conductive region of the second semiconductor pattern1220to overlap the second semiconductor pattern1220and the data signal line1130. The first switching transistor first electrode1377may extend in the second direction DR2, and the length, in the first direction DR1, of the first switching transistor first electrode1377may be smaller than the length, in the second direction DR2, of the first switching transistor first electrode1377. The first switching transistor first electrode1377may extend downwardly from the overlapping area with the first conductive region of the second semiconductor pattern1220and may thus overlap part of the data signal line1130that may not overlap the first conductive region of the second semiconductor pattern1220. In the overlapping area with the part of data signal line1130that may not overlap the first conductive region of the second semiconductor pattern1220, the first switching transistor first electrode1377may be in contact with, and electrically connected to the data signal line1130through a contact hole CNT24that may penetrate the interlayer insulating film1610and the gate insulating film1620to expose part of the data signal line1130. The contact hole CNT24may be located or disposed on the lower side of the first switching transistor first electrode1377in a plan view, but the disclosure is not limited thereto. The first switching transistor first electrode1377may also be in contact with, and electrically connected, to the first conductive region of the second semiconductor pattern1220through a contact hole CNT16that may penetrate the gate insulating film1620to expose the first conductive region of the second semiconductor pattern1220. In a plan view, the contact hole CNT16may be located or disposed on the upper side of the contact hole CNT24, but the disclosure is not limited thereto. The first switching transistor first electrode1377, which may be located or disposed above the first conductive region of the second semiconductor pattern1220, may be provided in the first source/drain region of the first switching transistor STR1and may be the first electrode of the first switching transistor STR1. The first electrode of the first switching transistor STR1may be the first source/drain electrode of the first switching transistor STR1. The pad electrode1380may be located or disposed on the data pad1160. The pad electrode1380may be in contact with the top surface of the data pad1160through a contact hole CNT28. The pad electrode1380may be electrically connected to the data pad1160through the contact hole CNT28. The pad electrode1380may be used as the contact electrode of a wire pad WPD in the pad area PDA. The passivation layer1630may be located or disposed on the second conductive layer1300. The passivation layer1630may cover and protect the second conductive layer1300. The passivation layer1630may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zirconium oxide. The passivation layer1630may be formed in the display area DPA and may not be formed in at least part of the non-display area NDA. The passivation layer1630may not be formed at least on the pad electrode1380, which may be located or disposed in the pad area PDA, and may not overlap the pad electrode1380. The via layer1650may be located or disposed on the passivation layer1630. The via layer1650may cover a side of the passivation layer1630adjacent to the pad area PDA. In the pad area PDA, the via layer1650may be located or disposed directly on the passivation layer1630. The via layer1650may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or BCB. The via layer1650may include a photosensitive material, but the disclosure is not limited thereto. For example, the via layer1650may include polyimide. The via layer1650may have different heights in different regions. For example, the via layer1650may have a stepped structure, shape, or height having different heights in different regions. The via layer1650may include a first region which has a first height and a second region which has a second height that may be smaller than the first height. The height of the via layer1650may be measured from a reference surface such as the first surface of the first substrate1010. The via layer1650may be generally flat in each of the first and second regions, regardless of the shape or the presence of patterns therebelow. The via layer1650may have a stepped structure at the boundary between the first and second regions. The first region of the via layer1650may be located or disposed in the display area DPA, and the second region of the via layer1650may be located or disposed in the pad area PDA of the non-display area NDA. At least part of the first region of the via layer1650may overlap the pixel electrode PXE, and another part of the first region of the via layer1650may be located or disposed in the non-emission areas NEM of the display area DPA and may not overlap the pixel electrode PXE. Since the via layer1650may have a small height in the second region thereof, for example, in the pad area PDA, an external device may be properly mounted on the pad electrode1380. The via layer1650may form a pad opening, which may expose the pad electrode1380in the pad area PDA, together with the passivation layer1630. Parts of the via layer1650that may form the sidewalls of the pad opening may be located or disposed to overlap the pad electrode1380. The pixel electrode PXE may be located or disposed on the via layer1650. The material of the pixel electrode PXE is as already described above with reference toFIG.2. For example, the pixel electrode PXE may include a triple-layer film of ITO/Ag/ITO. The pixel electrode PXE may be located or disposed in the display area DPA, but not in the non-display area NDA. The pixel electrode PXE may overlap the display area DPA, for example, the regions where the transistors (DTR, STR1, and STR2) may be located or disposed and the capacitor region CPR, but the disclosure is not limited thereto. The pixel electrode PXE may be in contact with, and electrically connected to the capacitor lower electrode1121of the first conductive layer1100through the contact hole CNT3, which may penetrate the via layer1650, the passivation layer1630, and the interlayer insulating film1610. The pixel-defining film PDL may be located or disposed on the pixel electrode PXE. The material of the pixel-defining film PDL is as already described above with reference toFIG.2. For example, the pixel-defining film PDL may include polyimide. The pixel-defining film PDL may be located or disposed in the display area DPA, but not in the non-display area NDA. The pixel-defining film PDL may be located or disposed to overlap the edges of the pixel electrode PXE. The pixel-defining film PDL may be located or disposed on parts of the via layer1650where the pixel electrode PXE may not be formed. A method of manufacturing the display device1will hereinafter be described. FIGS.8through14are schematic cross-sectional views illustrating a method of manufacturing the display device ofFIG.7. Referring toFIG.8, the first conductive layer1100may be formed on the first substrate1010. The first conductive layer1100, which may be patterned, may be formed by a mask process. For example, the first power supply wire1110, the capacitor lower electrode1121, the capacitor lower electrode second extension1125, the data signal line1130, and a pad light-shielding layer1160may be formed by the same mask process. For example, a material layer for forming the first conductive layer1100may be deposited on the entire surface of the first substrate1010. Thereafter, a photoresist pattern may be formed by applying a photoresist layer on the material layer for forming the first conductive layer1100and subjecting the photoresist layer to exposure and development, and the material layer for forming the first conductive layer1100may be etched using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern may be removed by a strip or ashing process. Since the first power supply wire1110, the capacitor lower electrode1121, the capacitor lower electrode second extension1125, the data signal line1130, and the data pad1160of the lower conductive layer1100may be patterned and formed at the same time, the number of masks may be maintained, and as a result, process economics may be guaranteed. Manufacturing costs may thus be reduced, and manufacturing efficiency may thus be improved. Thereafter, referring toFIG.9, the interlayer insulating film1610may be formed on the entire surface of the first substrate1010with the first conductive layer1100formed thereon. Thereafter, the semiconductor layer1200may be formed on the interlayer insulating film1610. The semiconductor layer1200may be formed by a mask process. For example, the first and second semiconductor patterns1210and1220may be formed, as illustrated inFIG.9, by depositing an oxide semiconductor on the entire surface of the interlayer insulating film1610and patterning the oxide semiconductor via photolithography. Thereafter, referring toFIG.10, the gate insulating film1620may be deposited on the interlayer insulating film1610with the semiconductor layer1200formed thereon, and contact holes may be formed. The contact holes may include contact holes (CNT21, CNT22, CNT24, and CNT28), which may be patterned to expose parts of the first conductive layer1100, and contact holes (CNT11, CNT12, CNT15, and CNT16), which may be patterned to expose parts of the semiconductor layer1200. The contact holes may be formed by the same mask process. For example, a material layer for forming the gate insulating film1620may be deposited on the interlayer insulating film1610with the semiconductor layer1200formed thereon. Thereafter, a photoresist pattern (or contact hole patterns), which may expose the first conductive layer1100and parts of the semiconductor layer1200, may be formed on the material layer for forming the gate insulating film1620, and the contact holes (CNT21, CNT22, CNT24, and CNT28), which may expose the first conductive layer1100, and the contact holes (CNT11, CNT12, CNT15, and CNT16), which may expose parts of the semiconductor layer1200, may be formed using the photoresist pattern as an etching mask. The contact holes (CNT21, CNT22, CNT24, and CNT28), which may expose the first conductive layer1100, and the contact holes (CNT11, CNT12, CNT15, and CNT16), which may expose parts of the semiconductor layer1200, may be sequentially formed using different masks. In this case, damage to the surface of the semiconductor1200may be suppressed because the semiconductor layer1200may not be exposed to an etchant when the interlayer insulating film1610is being etched to form the contact holes (CNT21, CNT22, CNT24, and CNT28), which expose the first conductive layer1100. However, due to the addition of a mask process, the economic efficiency of the manufacture of the display device1may decrease. Thereafter, referring toFIG.11, the second conductive layer1300, which may be patterned, may be formed on the gate insulating film1620. The second conductive layer1300may be formed by a mask process. For example, a material layer for forming the second conductive layer1300may be deposited on the entire surface of the gate insulating film1620. The material layer for forming the second conductive layer1300may be deposited even on the inside of each of the contact holes (CNT11, CNT12, CNT15CNT16, CNT21, CNT22, CNT24, and CNT28) to be electrically connected to the first conductive layer1100and the semiconductor layer1200. Thereafter, a photoresist pattern may be formed by applying a photoresist layer on the material layer for forming the second conductive layer1300and subjecting the photoresist layer to exposure and development, and the material layer for forming the second conductive layer1300may be etched using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern may be removed by a strip or ashing process, thereby forming the driving transistor first electrode1371, the transistor shared electrode1373, the driving transistor gate electrode1335, the capacitor upper electrode1331, the first switching transistor first electrode1377, the first switching transistor second electrode1333, the first switching transistor gate electrode1325, and the pad electrode1380, as illustrated inFIG.11. Thereafter, referring toFIG.12, the passivation layer1630may be formed on the entire surface of the interlayer insulating film1610with the second conductive layer1300formed thereon, in the entire display area DPA except for the pad area PDA. Thereafter, the via layer1650may be deposited on the passivation layer1630and the pad electrode1380. Thereafter, the contact hole CNT3, which may expose part of the capacitor lower electrode1121, and a first opening OP1, which may expose part of the pad electrode1380in the pad area PDA, may be formed, thereby patterning the via layer1650. For example, the via layer1650may include an organic material containing a photosensitive material. In this example, the via layer1650may be formed and patterned by applying an organic material layer for forming the via layer1650and subjecting the material layer for forming the via layer1650to exposure and development. Accordingly, the via layer1650, the contact hole CNT3, and the first opening OP1may be formed by the same mask process. Thereafter, referring toFIG.13, the pixel electrode PXE, which may be patterned is formed on the via layer1650. The pixel electrode PXE may be formed by a mask process. For example, a material layer for forming the pixel electrode PXE may be deposited on the entire surface of the via layer1650in the display area PDA. The material layer for forming the pixel electrode PXE may be deposited even on the inside of the contact hole CNT3to be electrically connected to the capacitor lower electrode1121. Thereafter, a photoresist pattern having a shape in which to form the pixel electrode PXE may be formed by applying a photoresist layer on the material layer for forming the pixel electrode PXE and subjecting the photoresist layer to exposure and development. Thereafter, the material layer for forming the pixel electrode PXE may be etched using the photoresist pattern as an etching mask. The material layer for forming the pixel electrode PXE may be etched by, for example, wet etching, but the disclosure is not limited thereto. During etching, the pixel electrode PXE may be covered and protected by the photoresist pattern, but parts of the via layer1650not covered by the photoresist pattern may be exposed and may thus be partially etched. As a result, the height of the parts of the via layer1650not covered by the photoresist pattern may be reduced. Accordingly, the via layer1650may have a stepped structure having different heights in different regions. Thereafter, the photoresist pattern may be removed by an ashing or strip process, but the disclosure is not limited thereto. Thereafter, referring toFIG.14, the pixel-defining film PDL, which may be patterned, may be formed on the via layer1650with the pixel electrode PXE formed thereon. For example, the pixel-defining film PDL may be formed of an organic material containing a photosensitive material. In this example, the pixel-defining film PDL may be formed by applying an organic material layer for forming the pixel-defining film PDL and subjecting the organic material layer to exposure and development. The pixel-defining film PDL may be formed along the boundaries of the pixel PX and may partially overlap the pixel electrode PXE. The pixel-defining film PDL may fill parts of the via layer1650that may have a relatively small height and may thus compensate for height differences in the via layer1650. As described above, since the first conductive layer1100may be located or disposed below the semiconductor layer1200, an additional mask process for forming a light-shielding layer below the channel region of the semiconductor layer1200may not be needed. For example, the first source/drain electrode, the second source/drain electrode, and the gate electrode of each of the transistors (DTR, STR1, and STR2) may be formed by a single mask process using the material layer for forming the second conductive layer1300. Similarly, since the contact hole CNT3, which may penetrate the via layer1650, the passivation layer1630, and the interlayer insulating film1610, may be formed using the same mask as that used to form the via layer1650, an additional mask may not be needed. Display devices according to other embodiments will hereinafter be described, focusing mainly on the differences with the display device1. FIG.15is a schematic cross-sectional view of a pixel of a display device according to an embodiment.FIG.15illustrates an example in which a pixel electrode PXE may be electrically connected to a transistor shared electrode1373. Referring toFIG.15, a contact hole CNT3_1, which may penetrate a via layer1650, may be located or disposed in a driving transistor region DTR. The contact hole CNT3_1may be located or disposed to overlap the transistor shared electrode1373, which may form the second source/drain electrode of a driving transistor DTR. The contact hole CNT3_1may penetrate a passivation layer1630and a via layer1650, which may be located or disposed on the transistor shared electrode1373, to expose at least part of the transistor shared electrode1373. The pixel electrode PXE may be deposited even on the inside of the contact hole CNT3_1to be in contact with the top surface of the transistor shared electrode1373. Accordingly, the pixel electrode PXE and the second source/drain electrode of the driving transistor DTR may be electrically connected. In a mask process that may form the contact hole CNT3_1, the contact hole CNT3_1and a first opening OP1may be formed in the display area DPA and the non-display area NDA, respectively, using the same mask as that used to form the via layer1650. In this case, in the embodiment ofFIG.7, the pad electrode1380, which may be located or disposed in the non-display area NDA, may be exposed to an etchant while the interlayer insulating film1610may be etched to form the contact hole CNT3. In an embodiment ofFIG.15, since an interlayer insulating film1610may not need to be etched to form the contact hole CNT3_1, damage to the surface of a pad electrode1380in the non-display area NDA may be suppressed. FIG.16is a schematic cross-sectional view of a pixel of a display device according to an embodiment.FIGS.17and18are schematic cross-sectional views illustrating a method of manufacturing the display device ofFIG.16. The embodiment ofFIG.16may differ from the embodiment ofFIG.7in that a conductive capping layer CAP may be located or disposed on a second conductive layer1300. Referring toFIG.16, the conductive capping layer CAP may be located or disposed on the second conductive layer1300. For example, the conductive capping layer CAP may be located or disposed on a driving transistor first electrode1371, a driving transistor gate electrode1375, a transistor shared electrode1373, a capacitor upper electrode1331, a first switching transistor first electrode1377, a first switching transistor gate electrode1325, a first switching transistor second electrode1333, and a pad electrode1380. The conductive capping layer CAP may cover and protect the second conductive layer1300from above the second conductive layer1300. The conductive capping layer CAP may protect the second conductive layer1300from layers located or disposed on the second conductive layer1300or from etchants or other chemicals used in the manufacture of the display device ofFIG.16. The conductive capping layer CAP may be in direct contact with the second conductive layer1300. The conductive capping layer CAP, which may be located or disposed on the pad electrode1380in a pad area PDA, may be integrally formed with the pad electrode1380and may thus serve as the contact electrode of a wire pad WPD of a data signal line. Thus, the conductive capping layer CAP may be formed of a material suitable for use as the contact electrode of the wire pad WPD. The conductive capping layer CAP may include ZIO, IZO, or ITO. For example, the conductive capping layer CAP may include a ZIO film, an IZO film, or an ITO film or may be formed as a multilayer film of Ti/Mo/ITO. In an embodiment ofFIG.16, the second conductive layer1300may be a double-layer film of Ti/Cu, and the conductive capping layer CAP, which may be located or disposed on the second conductive layer1300, may be an ITO film. The second conductive layer1300and the conductive capping layer CAP may be patterned by a single mask process. For example, the sides of the second conductive layer1300and the sides of the conductive capping layer CAP may be aligned. The conductive capping layer CAP, which may be located or disposed on the second conductive layer1300, may not protrude beyond the second conductive layer1300. No insulating layer may be interposed between the second conductive layer1300and the conductive capping layer CAP. Since the conductive capping layer CAP may be provided on the second conductive layer1300, the second conductive layer1300may be prevented from being corroded in subsequent processes. Accordingly, the reliability of the wire pad WPD may be improved. FIG.17is a schematic cross-sectional view illustrating the formation of a pixel electrode PXE as performed in the method of manufacturing the display device ofFIG.16. The embodiment ofFIG.17may differ from the embodiment ofFIG.14in that an opening OP1_17, which may be located or disposed in the pad area PDA, covers the pad electrode1380, and that the conductive capping layer CAP may be located or disposed on the pad electrode1380. Referring toFIG.17, during the formation of a via layer1650, which may be patterned, on a passivation layer1630, a contact hole CNT3, which may be located or disposed in a display area DPA and exposes a capacitor lower electrode1121, may be formed to penetrate the via layer1650, the passivation layer1630, and an interlayer insulating film1610. The opening OP1_17of the via layer1650, which may be located or disposed in a non-display area NDA or the pad area PDA, may be formed to cover the conductive capping layer CAP, which may be located or disposed on the pad electrode1380. The via layer1650, which may have different heights in different regions, may be formed using a halftone mask or a slit mask, but the disclosure is not limited thereto. A material layer for forming the pixel electrode PXE may be deposited on the entire surface of the via layer1650and may be etched using a photoresist pattern PR as an etching mask. At this stage, the pad electrode1380in the pad area PDA and the conductive capping layer CAP, which may be located or disposed on the pad electrode1380, may be covered and protected by the via layer1650where the thickness of the via layer1650has been reduced. Thus, the pad electrode1380and the conductive capping layer CAP may be prevented from being damaged by being placed in contact with an etchant used to form the pixel electrode PXE. Thereafter, referring toFIG.18, etching may be performed with the photoresist pattern PR remaining on the pixel electrode PXE, thereby removing the via layer1650from above the conductive capping layer CAP in the pad area PDA to expose the conductive capping layer CAP on the pad electrode1380. As a result, a pad opening which exposes the conductive capping layer CAP in the pad area PDA may be formed. Parts of the via layer1650that may form the pad opening may at least partially overlap the top surface of the conductive capping layer CAP. For example, the width of the pad opening may be smaller than the width of part of the conductive capping layer CAP located or disposed on the pad electrode1380. In an embodiment ofFIG.16, the conductive capping layer CAP, which may be formed together with the pad electrode1380by a single mask process, may be used as the contact electrode of a wire pad WPD. Accordingly, since an additional mask process for forming the contact electrode of the wire pad WPD may not be needed, process efficiency may be improved. Meanwhile, during etching, the pixel electrode PXE may be covered and protected by the photoresist pattern, but the via layer1650, which may not be covered by the photoresist pattern PR, may be exposed and may be partially etched. As a result, the height (or thickness) of parts of the via layer1650that may not be covered by the photoresist pattern PR may be reduced, and thus, the via layer1650may have a stepped structure having different heights in different regions. FIG.19is a layout view of a pixel of a display device according to an embodiment.FIG.20is a cutout layout view illustrating a case where a defect may have occurred in a transistor in a part A ofFIG.19.FIG.21is a cutout layout view illustrating a repair operation that may be performed when there may exist a defect in the transistor in the part A ofFIG.19. The embodiment ofFIG.19may differ from the embodiment ofFIG.5in that in a plan view, semiconductor patterns having the same shape as first and second semiconductor patterns1210and1220that may form the active layers of transistors (DTR, STR1, and STR2) of a display device1may be provided on the upper side and/or the lower side of the first and second semiconductor patterns1210and1220. Referring toFIG.19, in a plan view, a first redundancy semiconductor pattern1210R may be located or disposed on the upper side of the first semiconductor pattern1210to be apart from the first semiconductor pattern1210. The shape of the first redundancy semiconductor pattern1210R may be substantially the same as the shape of the first semiconductor pattern1210. The first redundancy semiconductor pattern1210R may include the same or similar material as the first semiconductor pattern1210. For example, the first redundancy semiconductor pattern1210R may be substantially the same as the first semiconductor pattern1210in terms of shape, material, and stage of manufacture. The arrangement of the first redundancy semiconductor pattern1210R relative to first and second conductive layers1100and1300may be the same as the arrangement of the first semiconductor pattern1210relative to the first and second conductive layers1100and1300. Thus, first, second, and third conductive regions of the first redundancy semiconductor pattern1210R may be located or disposed to overlap a first power supply wire1110, a capacitor lower electrode second extension1125, and a reference voltage connecting electrode1150of the first conductive layer1100. The first, second, and third conductive regions of the first redundancy semiconductor pattern1210R may be located or disposed to overlap a driving transistor first electrode1371, a transistor shared electrode1373, and a second switching transistor first electrode1375of the second conductive layer1300, and an extension of the first redundancy semiconductor pattern1210R may be located or disposed to overlap a second switching transistor gate electrode1345and a driving transistor gate electrode1335of the second conductive layer1300. In an embodiment ofFIG.19, the driving transistor first electrode1371, the transistor shared electrode1373, the driving transistor gate electrode1335, the second switching transistor gate electrode1345, and the second switching transistor first electrode1375of the second conductive layer1300extend in a second direction DR2to overlap the first redundancy semiconductor pattern1210R and the first semiconductor pattern1210. A gate insulating layer1620may be interposed between the first redundancy semiconductor pattern1210R and the second conductive layer1300. No contact holes may be formed in the gate insulating layer1620, which may be interposed between the first redundancy semiconductor pattern1210R and the second conductive layer1300. Thus, in a schematic cross-sectional view, the first redundancy semiconductor pattern1210R and the second conductive layer1300may be electrically insulated from each other. Similarly, in a plan view, a second redundancy semiconductor pattern1220R may be located or disposed on the lower side of the second semiconductor pattern1220to be apart from the second semiconductor pattern1220. The shape of the second redundancy semiconductor pattern1220R may be substantially the same as the shape of the second semiconductor pattern1220. Also, the second redundancy semiconductor pattern1220R may include the same or similar material as the second semiconductor pattern1220. For example, the second redundancy semiconductor pattern1220R may be substantially the same as the second semiconductor pattern1220in terms of shape, material, and stage of manufacture. The arrangement of the second redundancy semiconductor pattern1220R relative to the first and second conductive layers1100and1300may be the same as the arrangement of the second semiconductor pattern1220relative to the first and second conductive layers1100and1300. Thus, first and second conductive regions of the second redundancy semiconductor pattern1220R may be located or disposed to overlap a capacitor lower electrode second extension1123and a data signal line1130of the first conductive layer1100. The first and second conductive regions and an extension of the second redundancy semiconductor pattern1220R may be located or disposed to overlap a first switching transistor second electrode1333, a first switching transistor gate electrode1325, and a first switching transistor first electrode1377of the second conductive layer1300. In an embodiment ofFIG.19, the first switching transistor second electrode1333, the first switching transistor gate electrode1325, and the first switching transistor first electrode1377of the second conductive layer1300may extend in the second direction DR2to overlap the second redundancy semiconductor pattern1220R and the second semiconductor pattern1220. The gate insulating layer1620may also be interposed between the second redundancy semiconductor pattern1220R and the second conductive layer1300. No contact holes may be formed in the gate insulating layer1620, which may be interposed between the first redundancy semiconductor pattern1220R and the second conductive layer1300. Thus, in a schematic cross-sectional view, the second redundancy semiconductor pattern1220R and the second conductive layer1300may be electrically insulated from each other. If defects occur during the manufacture of the display device1, the first and second redundancy semiconductor patterns1210R and1220R may replace the first and second semiconductor patterns1210and1220and may be used as the active layers of the transistors of the display device1. For example, if a foreign material IP remains on the channel region of the semiconductor layer1200or in the gate electrode of a transistor during the manufacture of the display device1, a defect may occur due to the foreign material IP. Examples of the foreign material IP include an insulating material. In a case where a defect occurs in a transistor, the first source/drain electrode and/or the second source/drain electrode of the transistor may be cut off so that no signals may be applied to the transistor. Referring toFIG.20, if the foreign material IP remains on the extension of the second semiconductor pattern1220or on the first switching transistor gate electrode1325, a defect may occur in a first switching transistor STR1due to the foreign material IP. In this case, a cutting region CP on the first switching transistor second electrode1333, which may be in contact with, and electrically connected to, the second source/drain region of the second semiconductor pattern1220, may be cut, thereby repairing the defect. The cutting region CP may be a region on the first switching transistor second electrode1333that may not overlap the second semiconductor pattern1220and the second redundancy semiconductor pattern1220R. For example, the cutting region CP may correspond to a region on the first switching transistor second electrode1333where the second semiconductor pattern1220and the second redundancy semiconductor pattern1220R may be spaced apart from each other. The cutting region CP may be cut by a laser, by way of example. Referring toFIG.21, the first switching transistor second electrode1333, which may be located or disposed on the second semiconductor pattern1220where a defect may have occurred, may be cut, by a laser, into a first switching transistor defective second electrode1333a_1and a first switching transistor second electrode1333_1, which may be apart from each other. Thereafter, since the gate insulating layer1620may be interposed between the second redundancy semiconductor pattern1220R and the first switching transistor second electrode1333_1, contact holes (CNT15R and CNT16R) may be formed using a laser so that the second redundancy semiconductor pattern1220R, the first switching transistor second electrode1333_1, and the first switching transistor first electrode1337may be electrically connected. In this case, the second redundancy semiconductor pattern1220R may be a new active layer of the first switching transistor STR1. The first switching transistor second electrode1333may be cut by a laser, but the disclosure is not limited thereto. Alternatively, if the first switching transistor STR1is defective, signals may be transmitted to the first switching transistor first electrode1377. In this case, part of the first switching transistor first electrode1377between a contact hole CNT24, which may electrically connect the data signal line1130and the first switching transistor first electrode1377and the data signal line1130, and contact holes CNT16, which may be located or disposed at the right end of the second semiconductor pattern1220, may be cut. As a result, no data signals may be applied to the first switching transistor first electrode1377, which may be located or disposed at the right end of the second semiconductor pattern1220. FIG.22is a cutout layout view of a first switching transistor region of a pixel of a display device according to an embodiment. The embodiment ofFIG.22may differ from the embodiment ofFIG.5in that a first switching transistor gate electrode1325, which may branch off from a scan signal line1320and extend in a second direction DR2, may not be provided. Referring toFIG.22, a second semiconductor pattern1220_22, which may be located or disposed in a first switching transistor region STR1_22, may generally extend in the second direction DR2, and both end parts of the second semiconductor pattern1220_22may be expanded in a first direction DR1to be wider than the rest of the second semiconductor pattern1220_22. For example, the second semiconductor pattern1220_22may include a first conductive region which may be located or disposed on a first side of or a part of the second semiconductor pattern1220_22, a second conductive region which may be located or disposed on a second side of the second semiconductor pattern1220_22that may be opposite to the first side of or a part of the second semiconductor pattern1220_22, and an extension which may connect the first and second conductive regions. For example, the first and second sides of the second semiconductor pattern1220_22may be the upper and lower sides, respectively, of the second semiconductor pattern1220_22. Accordingly, the first conductive region of the second semiconductor pattern1220_22may be located or disposed on the upper side of the extension of the second semiconductor pattern1220_22, and the second conductive region of the second semiconductor pattern1220_22may be located or disposed on the lower side of the extension of the second semiconductor pattern1220_22. The extension of the second semiconductor pattern1220_22and the scan signal line1320may be located or disposed to overlap each other. Part of the extension of the second semiconductor pattern1220_22that may overlap the scan signal line1320may be the channel region of a first switching transistor STR1, and part of the scan signal line1320that may overlap the extension of the second semiconductor pattern1220_22may be the gate electrode of the first switching transistor STR1. For example, the scan signal line1320may include the gate electrode of the first switching transistor STR1. The first conductive region of the second semiconductor pattern1220_22may be the first source/drain region of the first switching transistor STR1, and the second conductive region of the second semiconductor pattern1220_22may be the second source/drain region of the first switching transistor STR1. The first conductive region of the second semiconductor pattern1220_22may not overlap a data signal line1130. The first conductive region of the second semiconductor pattern1220_22and the data signal line1130may be electrically connected via a first switching transistor first electrode1377_22and contact holes (CNT16and CNT24).FIG.22illustrates the second semiconductor pattern1220_22, but the description of the second semiconductor pattern1220_22may be directly applicable to a first semiconductor pattern (not illustrated). In a case where a defect occurs in each of transistors (DTR, STR1, and STR2) of a pixel PX, the first source/drain electrode and/or the first source/drain electrode of each of the transistors (DTR, STR1, and STR2) may be cut by a laser. In this case, a cutting space may be needed for cutting the first source/drain electrode and/or the first source/drain electrode of each of the transistors (DTR, STR1, and STR2). The width of the cutting space may preferably be in a range of about 6 μm to about 8 μm to properly cut the first source/drain electrode and/or the first source/drain electrode of each of the transistors (DTR, STR1, and STR2). In an embodiment ofFIG.22, the extension of the second semiconductor pattern1220_22may be arranged substantially in parallel to the second direction DR2so that the first conductive region of the second semiconductor pattern1220_22may be spaced apart from the data line1130. Accordingly, a sufficient cutting space may be secured. For example, since a semiconductor layer1200may be formed to be substantially perpendicular to multiple lines located or disposed in the first conductive layer1100, a sufficient cutting space may be secured for cutting wires in the second conductive layer1300that may be connected to the first source/drain electrode and/or the first source/drain electrode of each of the transistors (DTR, STR1, and STR2), in case a defect occurs. FIG.23is a layout view of a pixel of a display device according to an embodiment.FIG.24is a schematic cross-sectional view taken along line XXIV-XXIV′ ofFIG.23. The embodiment ofFIGS.23and24may differ from the embodiment ofFIG.22in that the first source/drain electrodes and/or the second source/drain electrodes of transistors (DTR, STR1, and STR2) may be formed of a different conductive layer from the gate electrodes of the transistors (DTR, STR1, and STR2). In the embodiment ofFIG.23, similar to the embodiment ofFIG.22, extensions of a semiconductor layer1200may be arranged substantially in parallel to a first conductive layer1100to be substantially perpendicular to a scan signal line1320and a sensing signal line1340of a second conductive layer1300. The embodiment ofFIG.23will hereinafter be described, focusing mainly on the differences with the embodiment ofFIG.22. Referring toFIGS.23and24, a gate insulating layer1620may be located or disposed on the entire surface of a first interlayer insulating film1610. Gate electrodes may be located or disposed on the gate insulating layer1620to overlap the extensions of the semiconductor pattern layer1200. A second interlayer insulating film1630may be located or disposed on the gate insulating layer1620. A third conductive layer1400may be located or disposed on the second interlayer insulating film1630. The third conductive layer1400may be in contact with first source/drain regions and/or second source/drain regions of the semiconductor layer1200via contact holes or with part of the first conductive layer1100. Accordingly, the third conductive layer1400may be electrically connected to the semiconductor layer1200via contact holes which may penetrate the first interlayer insulating film1610, the gate insulating layer1620, and the second interlayer insulating film1630to expose the first conductive layer1100and via contact holes which may penetrate the gate insulating layer1620and the second interlayer insulating film1630to expose the first source/drain regions and/or the second source/drain regions of the semiconductor layer1200. For example, referring toFIG.24, a driving transistor first electrode1410and a driving transistor second electrode1420in a driving transistor region DTR may be located or disposed on a driving transistor gate electrode1393. The driving transistor first electrode1410may be electrically connected to a second semiconductor pattern1220_23via a contact hole CNT1_23which may penetrate the second interlayer insulating film1630and the gate insulating film1620, and the driving transistor first electrode1410may be electrically connected to a first power supply wire1110via a contact hole CNT2_23which may penetrate the second interlayer insulating film1630, the gate insulating film1620, and the first interlayer insulating film1610. Accordingly, the driving transistor first electrode1410and the driving transistor gate electrode1393may be formed by separate mask processes. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the embodiments without substantially departing from the principles and spirit and scope of the disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation. | 122,226 |
11943977 | DESCRIPTION OF EMBODIMENTS Hereinafter, “the same layer” means that the layer is formed in the same process (film formation process), “a lower layer” means that the layer is formed in an earlier process than the process in which the layer to compare is formed, and “an upper layer” means that the layer is formed in a later process than the process in which the layer to compare is formed. FIG.1is a flowchart illustrating an example of a method of manufacturing a display device.FIG.2is a cross-sectional view illustrating a configuration example of a display portion of the display device. In a case where a flexible display device is manufactured, as illustrated inFIG.1andFIG.2, first, a resin layer12is formed on a transparent support substrate (a mother glass, for example) (step S1). Next, a barrier layer3is formed (step S2). Next, a TFT layer4is formed (step S3). Next, a top-emitting type light-emitting element layer5is formed (step S4). Next, a sealing layer6is formed (step S5). Next, an upper face film is bonded to the sealing layer6(step S6). Next, the support substrate is peeled from the resin layer12due to irradiation with a laser light or the like (step S7). Next, a lower face film10is bonded to the lower face of the resin layer12(step S8). Next, the layered body including the lower face film10, the resin layer12, the barrier layer3, the TFT layer4, the light-emitting element layer5, and the sealing layer6is divided to obtain a plurality of individual pieces (step S9). Next, a function film39is bonded on the obtained individual pieces (step S10). Next, an electronic circuit board (for example, an IC chip or an FPC) is mounted on a portion (terminal portion) of the display region located further outward (a non-display region or a frame) than a portion where a plurality of subpixels are formed (step S11). Note that steps S1to S11are executed by a display device manufacturing apparatus (including a film formation apparatus that executes the process from step S1to S5). Examples of the material of the resin layer12include a polyimide and the like. The barrier layer3is a layer that inhibits foreign matter such as water and oxygen from entering the TFT layer4and the light-emitting element layer5, and can be constituted by a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or by a layered film of these, formed by chemical vapor deposition (CVD), for example. The TFT layer4includes a semiconductor film15, an inorganic insulating film16(a gate insulating film) as an upper layer overlying the semiconductor film15, a first metal layer as an upper layer overlying the inorganic insulating film16, an inorganic insulating film18as an upper layer overlying the first metal layer, a second metal layer as an upper layer overlying the inorganic insulating film18, an inorganic insulating film20as an upper layer overlying the second metal layer, a third metal layer as an upper layer overlying the inorganic insulating film20, and a flattening film21as an upper layer overlying the third metal layer. The first metal layer includes a gate electrode GE, a scanning control line G, and a light emission control line EM. The second metal layer includes a capacitance electrode CE and an initialization power source line Pi. The third metal layer includes a data signal line DL and a high voltage power source line Ph. The semiconductor film15is constituted of, for example, a low-temperature polysilicon (LTPS) or an oxide semiconductor (for example, an In—Ga—Zn—O based semiconductor), and a transistor (TFT) is configured to include the semiconductor film15and the gate electrode GE.FIG.2illustrates the transistor that has a top gate structure, but the transistor may have a bottom gate structure. The gate electrode GE, the scanning control line G, the capacitance electrode CE, and the data signal line DL are each composed of a single layer film or a layered film of a metal including at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper, for example. Each of the inorganic insulating films16,18, and20can be formed of, for example, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, or a layered film of these, formed by using a CVD method. The flattening film21can be formed of, for example, a coatable organic material such as polyimide or acrylic. The light-emitting element layer5includes an anode22in an upper layer overlying the flattening film21, an edge cover23having insulating properties and covering an edge of the anode22, an electroluminescent (EL) layer24in an upper layer overlying the edge cover23, and a cathode25in an upper layer overlying the EL layer24. The edge cover23is formed by applying an organic material such as a polyimide or an acrylic and then patterning the organic material by photolithography, for example. On a subpixel-by-subpixel basis, a light-emitting element ES (for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED)) including the island-shaped anode22, the EL layer24, and the cathode25is formed in the light-emitting element layer5. The control circuit of the light-emitting element ES is formed in the TFT layer4, and each subpixel is formed of the light-emitting element and a control circuit thereof (referred to as a subpixel circuit). For example, the EL layers24are formed by layering a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in this order, from the lower layer side. The light-emitting layer is formed into an island shape at an opening of the edge cover23(on a subpixel-by-subpixel basis) by vapor deposition or an ink-jet method. Other layers are formed in an island shape or a solid-like shape (common layer). A configuration is also possible in which one or more layers out of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer are not formed. When the light-emitting layer of the OLED is formed by vapor deposition, a fine metal mask (FMM) is used. The FMM is a sheet with a large number of openings (for example, made of Invar material), and an island-shaped light-emitting layer (corresponding to one subpixel) is formed of an organic material passing through one of the openings. With the light-emitting layer of the QLED, for example, an island-shaped light-emitting layer (corresponding to one subpixel) can be formed by ink-jet coating a solvent having quantum dots diffused therein. The anode (anode electrode)22is formed by a layering of indium tin oxide (ITO) and silver (Ag) or an alloy containing Ag, for example, and has light reflectivity. The cathodes (cathode electrode)25can be constituted by a transparent conductive material such as a MgAg alloy (extremely thin film), ITO, or indium zinc oxide (IZO). In a case where the light-emitting element ES is an OLED, positive holes and electrons recombine inside the light-emitting layer in response to a drive current between the anode22and the cathode25, and light is emitted when the excitons generated in this manner transition to a ground state. Because the cathode25is transparent and the anode22has light reflectivity, the light emitted from the EL layer24travels upward and becomes top-emitting. In a case where the light-emitting element ES is a QLED, positive holes and electrons recombine inside the light-emitting layer in response to a drive current between the anode22and the cathode25, and light (fluorescence) is emitted when the excitons generated in this manner transition from the conduction band of the quantum dot to the valence band. A light-emitting element (such as an inorganic light emitting diode) other than an OLED or QLED may be formed in the light-emitting element layer5. The sealing layer6is transparent, and includes an inorganic sealing film26for covering the cathode25, an organic buffer film27formed as an upper layer overlying the inorganic sealing film26, and an inorganic sealing film28formed as an upper layer overlying the organic buffer film27. The sealing layer6covering the light-emitting element layer5inhibits foreign matter such as water and oxygen from penetrating the light-emitting element layer5. Each of the inorganic sealing film26and the inorganic sealing film28is an inorganic insulating film and can be formed of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a layered film of these, formed by CVD. The organic buffer film27is a transparent organic film having a flattening effect and can be formed of a coatable organic material such as an acrylic. The organic buffer film27can be formed, for example, by ink-jet application, and a bank for stopping droplets may be provided in the non-display region. The lower face film10is, for example, a PET film bonded in a lower face of the resin layer12after the support substrate is peeled, to realize a display device having excellent flexibility. The function film39has at least one of an optical compensation function, a touch sensor function, and a protection function, for example. The flexible display device has been described above, but when a non-flexible display device is to be manufactured, ordinarily, the formation of a resin layer, the replacement of the base material, etc. are not required. For example, when the non-flexible display device is to be manufactured, the process of layering including steps S2to S5are performed on a glass substrate, after which the process proceeds to step S9. FIRST EMBODIMENT The display device2of a first embodiment will be described with reference toFIG.3.FIG.3is a plan view illustrating the display device2of the first embodiment. The display device2includes a display region DA and a frame region (non-display region) NA surrounding the display region DA. As illustrated inFIG.3, in the display device2, a notch portion NZ is formed in the display region DA. The display region DA includes a first notch display portion SA1located on one side (right side inFIG.3) of the notch portion NZ and a second notch display portion SA2located on the other side (left side inFIG.3) of the notch portion NZ. A plurality of subpixels are provided in each of the notch display portions SA1and SA2. As illustrated inFIG.4, the subpixel SP is formed by a light-emitting element ES (for example, an OLED) and a subpixel circuit thereof (formed in the TFT layer4inFIG.2). The display region DA includes a plurality of data signal lines DL (m lines, where m is an integer of one or greater), a plurality of control lines, and a plurality of subpixel circuits. The control lines include a plurality of scanning control lines G (n lines, where n is an integer of one or greater) and a plurality of light emission control lines EM (n lines, where n is an integer of one or greater). n×m subpixel circuits are provided in a matrix shape so that the subpixel circuits correspond to respective intersections of the data signal lines DL and the scanning control lines G. The plurality of control lines intersect the plurality of data signal lines DL. The plurality of light emission control lines EM intersect the plurality of data signal lines DL. The subpixel SP is connected to, for example, a data signal line DL(m), a scanning control line G(n), a light emission control line EM(n), a high voltage power source line Ph(n), and an initialization power source line Pi(n). Note that one electrode of a capacitance Cp is connected to the high voltage power source line Ph(n), and the other electrode is connected to a gate terminal of a drive transistor Ta and the initialization power source line Pi(n) via an initialization transistor Tf. The drive transistor Ta includes a gate terminal connected to the scanning control line G(n), a source terminal connected to the data signal line DL(m) via a write transistor Tb, and a drain terminal connected to the anode22of the light-emitting element ES via a light emission control transistor Td. The drain terminal of the drive transistor Ta is also connected to a control terminal of the drive transistor Ta via a threshold control transistor Te. The source terminal of the drive transistor Ta is also connected to the high voltage power source line Ph(n) via a power supply transistor Tc. The cathode25of the light-emitting element ES is a common electrode formed in common with a plurality of the light-emitting elements ES, and is connected to a low power supply voltage ELVSS. The data signal line DL(m) is connected to the source driver SDR(m) (drive circuit), the scanning control line G(n) is connected to the gate drivers GD1(n) and GD2(n) (drive circuits), the scanning control line G(n−1) is connected to the gate drivers GD1(n−1) and GD2(n−1) (drive circuits), and the light emission control line EM(n) is connected to the emission drivers ED1(n) and ED2(n) (drive circuits). The gate drivers GD1(n) and GD2(n), the gate drivers GD1(n−1) and GD2(n−1), and the emission drivers ED1(n) and ED2(n) are formed monolithically in the TFT layer4included in the frame region (non-display region) NA. The gate drivers GD1(n) and GD2(n) are disposed to face each other across the display region DA. The control line may be driven on one side or driven on both sides. However, at least the control lines (in the Example, the light emission control lines EM) that are each divided at the first notch display portion SA1or the second notch display portion SA2in the notch portion are driven on one side. In the following, examples in which the lead wiring lines of adjacent scanning control lines G overlap each other via the inorganic insulating film in the frame region on the periphery of the notch portion will be described. The display device2is provided with scanning control lines G1to G5and G(n) extending in the x direction and data signal lines DL extending in the y direction. The scanning control lines G1, G2, G5, and G6are the light emission control lines G that pass through the first notch display portion SA1, sandwich the light emission control line EM therebetween, and are adjacent to each other. The scanning control lines G3and G4are the light emission control lines G that pass through the second notch display portion SA2, sandwich the light emission control line EM therebetween, and are adjacent to each other. Note that the control lines being adjacent to each other (for example, the first control line and the second control line are adjacent to each other) means that the light emission control lines G being the same type of control lines are adjacent to each other, and that the light emission control lines EM being the same type of control lines are adjacent to each other. The scanning control lines G pass through a main display portion MP on the inner side (lower side inFIG.3) of the notch portion NZ. As illustrated inFIG.5, a first lead wiring line W1electrically connected to the first scanning control line G1and a second lead wiring line W2electrically connected to the second scanning control line G2are provided on a periphery WR of the notch portion NZ (the frame region on the periphery of the notch portion NZ). Hereinafter, the first scanning control line G1, the second scanning control line G2, the first lead wiring line W1, and the second lead wiring line W2may be respectively abbreviated as a scanning control line G1, a scanning control line G2, a lead wiring line W1, and a lead wiring line W2. Note that inFIG.5, the third lead wiring line W3and the fourth lead wiring line W4respectively correspond to the lead wiring line W1and the lead wiring line W2. Each of the lead wiring lines W1and W2extends from the display region DA toward the notch portion NZ. The extending direction of the lead wiring line W1and the extending direction of the lead wiring line W2are the same. In the display region DA, the scanning control line G1and the scanning control line G2are formed of a first metal layer so as to be adjacent to each other. On the periphery WR of the notch portion NZ (the frame region on the periphery of the notch portion NZ), the lead wiring line W1is formed of the first metal layer, and the lead wiring line W2is formed of a second metal layer that is a layer different from the first metal layer. The lead wiring lines W1and W2have a shape that bypasses the notch portion NZ to avoid the notch portion NZ, and the camera lenses, sensors, and the like can be arranged to overlap the notch portion NZ. As illustrated inFIG.5, the lead wiring line W1and the scanning control line G1are electrically connected via two contact holes and a relay electrode E1. The lead wiring line W2and the scanning control line G2are electrically connected via two contact holes and a relay electrode E2. The lead wiring line W1and the scanning control line G3are electrically connected via two contact holes and a relay electrode E3. The lead wiring line W2and the scanning control line G4are electrically connected via two contact holes and a relay electrode E4. The relay electrodes E1to E4are formed in the third metal layer (source layer) inFIG.2. The lead wiring line W1includes bypass portions W1x, W1y, and W1zlocated on the periphery WR of the notch portion NZ, the bypass portion W1xextends in the x direction, and the bypass portions W1yand W1zextend in the y direction (a direction orthogonal to the x direction). The lead wiring line W2includes bypass portions W2x, W2y, and W2zlocated on the periphery WR of the notch portion NZ, the bypass portion W2xextends in the x direction, and the bypass portions W2yand W2zextend in the y direction. In Exemplary Embodiment 1, as illustrated inFIG.5, the bypass portion W1xand the bypass portion W2xthat extend in the x direction overlap each other via the inorganic insulating film18in a plan view. The bypass portion W1yand the bypass portion W2ythat extend in the y direction overlap each other via the inorganic insulating film18. The bypass portion W1zand the bypass portion W2zthat extend in the y direction overlap each other via the inorganic insulating film18. Note that “overlap” refers to overlap in a plan view. For example, as illustrated inFIG.7, either one lead wiring line of the lead wiring line W1and the lead wiring line W2has a first region A and a second region B described below. The first region A is a region that overlaps to straddle only an end portion of the lead wiring line on the side opposite to the display region in a direction orthogonal to the extending direction. In other words, inFIG.7, the first region A is a region where the lead wiring line W11overlaps on the upper side of the lead wiring line W12and does not overlap on the lower side in the direction orthogonal to the extending direction of the lead wiring line. The second region B is a region that overlaps to straddle only an end portion of the lead wiring line on the side opposite to the display region in a direction orthogonal to the extending direction. In other words, inFIG.7, the second region B is a region where the lead wiring line W11overlaps on the lower side of the lead wiring line W12and does not overlap on the upper side in the direction orthogonal to the extending direction of the lead wiring line. By bending at least one of the lead wiring line W1and the lead wiring line W2, the lead wiring line W1and the lead wiring line W2can overlap each other. In a case where the lead wiring line W1and the lead wiring line W2overlap each other, both may be straight lines, or one of them may be a straight line and the other may be bent diagonally. By providing the first region A and the second region B, the capacitance of the wiring lines can be increased and the amount of load can be increased. By including the first region A and the second region B, when the finish of each wiring line is misaligned from a predetermined position such as misalignment in the vertical direction, a portion misaligned in a direction in which the capacitance of the wiring line increases and a portion misaligned in a direction in which the capacitance of the wiring line decreases are generated. As a result, the misalignment of the wiring line is offset, and thus, the effect of misalignment is reduced. Thus, luminance variation generated by a difference in the bus line loads of the main display portion and the notch display portion can be suppressed. On the other hand, as illustrated inFIG.6, in a case where the amount of overlap is uniform, in other words, in a case where the first region A and the second region B are not provided, there is a large effect due to generation of wiring line misalignment, and the luminance variation is generated by the difference in the bus line loads of the main display portion and the notch display portion. As illustrated inFIG.7, in the lead wiring line having the first region A and the second region B, the sum of the lengths of the first regions A in the extending direction and the sum of the lengths of the second regions B in the extending direction are preferably the same. For example, when the lead wiring line W2is misaligned in a downward direction, the capacitance of the wiring lines in the first region A is reduced. On the other hand, the capacitance of the wiring lines in the second region B is increased, so that the effect of the misalignment of the lead wiring line W2is offset. As a result, luminance variation can be suppressed. InFIG.7, the first region A and the second region B are aligned in the order of the first region A, the second region B, and the first region A in the extending direction of the lead wiring lines, but may be aligned in the order of the second region B, the first region A, and the second region B in the extending direction of the lead wiring line. InFIG.7, both ends of the overlap region are first regions A in the extending direction of the lead wiring line, but both ends of the overlap region may be second regions B. As illustrated inFIG.7, by configuring the disposition of the first region A and the second region B to be left-right symmetrical, the coupling to the relay electrodes and the signal lines is also designed to be left-right symmetrical, making the design easy. A third region C that overlaps at an upper portion and also overlaps at a lower portion in a direction orthogonal to the extending direction of the lead wiring line may be included between the first region A and the second region B. The lead wiring line W1and the lead wiring line W2may be the same in width or different in width, but are preferably the same in width as illustrated inFIG.7. The materials of the lead wiring line W1and the lead wiring line W2may be the same or different from each other, but are preferably the same. Examples of the material of the lead wiring lines include GE, M3, and the like. InFIG.7, the bending points (intersection points) of the lead wiring lines W1and W2are two, but the number of bending points may be selected as appropriate. In the present specification, each bending point indicates the boundary between the first region A and the second region B. From the perspective of ease of design and ease of wiring operation, both ends of the overlap region are preferably the same region. Thus, the number of bending points is preferably an even number. The bending points may be disposed in a zig-zag shape as the entire lead wiring line. MODIFICATION EXAMPLE 1 As illustrated inFIG.8, the overlap shape of the first lead wiring line and the second lead wiring line of the display device differs from the overlap shape illustrated inFIG.7, in that the lead wiring line W32overlaps the lead wiring line W21that overlaps to straddle only an end portion of the lead wiring line W32on the side opposite to the display region and the lead wiring line W31that straddles only an end portion of the lead wiring line W32on the side closer to the display region. In other words, in a case where the lead wiring line having the first region A and the second region B is the lead wiring line W32, the lead wiring line W21that overlaps to straddle only the end portion on the side opposite to the display region and the lead wiring line W31that straddles only the end portion on the side closer to the display region may be adjacent to each other. The lead wiring line W31may overlap the lead wiring line W22that overlaps to straddle only an end portion of the lead wiring line W31on the side opposite to the display region and the lead wiring line W32that straddles only an end portion on the side closer to the display region. In other words, in a case where the lead wiring line having the first region A and the second region B is the lead wiring line W31, the lead wiring line W22that overlaps to straddle only the end portion on the side opposite to the display region and the lead wiring line W32that straddles only the end portion on the side closer to the display region may be adjacent to each other. MODIFICATION EXAMPLE 2 As a modification example of the display device of the first embodiment illustrated inFIG.7, the display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, the frame region adjacent to a bottom face of the notch portion sandwiched by the first notch display portion and the second notch display portion includes a plurality of first lead wiring lines and second lead wiring lines that overlap each other, and a sum of overlap areas of a first region A and a second region B of a first lead wiring line and a second lead wiring line that are closest to the main display portion and overlap each other may be adjusted, so that the luminance unevenness is not visible at the boundary between the notch display portion and the main display portion. In other words, luminance variation can be suppressed by controlling the amount of load in at and near the boundary between the main display portion and the notch display portion. SECOND EMBODIMENT Next, a display device of a second embodiment of the disclosure will be described with reference toFIG.9andFIG.10. Note that in the following description of each of the embodiments, the contents described above will not be described and will be described mainly about the differences. FIG.9andFIG.10are views illustrating overlap shapes of the first lead wiring lines and the second lead wiring lines in the display device of the second embodiment of the disclosure. The display device of the second embodiment differs from the display device illustrated inFIG.7in the overlap shapes of the first lead wiring lines and the second lead wiring lines in the following points. As illustrated in (a) ofFIG.9, a first lead wiring line on the side closer to the display region out of the first lead wiring lines is referred to as a lower first lead wiring line W21. A first lead wiring line on the side opposite to the display region and adjacent to the lower first lead wiring line W21is referred to as an upper first lead wiring line W11. A second lead wiring line that overlaps the lower first lead wiring line is referred to as a lower second lead wiring line W22. A second lead wiring line on the side opposite to the display region and adjacent to the lower second lead wiring line W22is referred to as an upper second lead wiring line W12. In this case, a second region B of the upper first lead wiring line W11and the upper second lead wiring line W12and a second region B of the lower first lead wiring line W21and the lower second lead wiring line W22have different lengths. This configuration is effective when, for example, a wiring line pitch is narrow and securing a space between the wiring lines is desired. As illustrated inFIG.9andFIG.10, a first region A of the upper first lead wiring line W11and the upper second lead wiring line W12and a first region A of the lower first lead wiring line W21and the lower second lead wiring line W22may also have different lengths. This configuration is effective when, for example, a wiring line pitch is narrow and securing a space between the wiring lines is desired. As described above, when the length of the first region A or the second region B is different, the amount of overlap is different. As illustrated inFIG.9, the amount of overlap of the first region A of the upper first lead wiring line W11and the upper second lead wiring line W12is smaller than the amount of overlap of the first region A of the lower first lead wiring line W21and the lower second lead wiring line W22. On the other hand, the amount of overlap of the second region B is large. According to this configuration, the impact can be minimized when the misalignment of the wiring lines is generated. The region where the second region B of the upper first lead wiring line W11and the upper second lead wiring line W12and the second region B of the lower first lead wiring line W21and the lower second lead wiring line W22have different lengths may be only the frame region of the notch portion adjacent to the main display portion. According to this configuration, the length of the lead wiring line is longer than the length in the frame region of the first notch display portion or the second notch display portion, and the degree of freedom of the design increases. The region where the first region A of the upper first lead wiring line W11and the upper second lead wiring line W12and the first region A of the lower first lead wiring line W21and the lower second lead wiring line W22have different lengths may also be only the frame region of the notch portion adjacent to the main display portion. The frame region of the notch portion adjacent to the main display portion may include the upper first lead wiring line W11, the upper second lead wiring line W12, the lower first lead wiring line W21, and the lower second lead wiring line W22. In a first lead wiring line closest to the display region out of the first lead wiring lines, the first region A and the second region B of a second lead wiring line with which the first lead wiring line overlaps preferably have the same length. According to this configuration, luminance variation between the main display portion and the notch display portion can be suppressed. The length of the first region A and/or the second region B may be longer or shorter from the main display portion toward the notch display portion. THIRD EMBODIMENT Next, a display device of a third embodiment of the disclosure will be described with reference toFIG.11. Note that in the following description of each of the embodiments, the contents described above will not be described and will be described mainly about the differences. FIG.11is a view illustrating an overlap shape of a first lead wiring line and a second lead wiring line in the display device of the third embodiment of the disclosure. The display device of the third embodiment differs from the display device illustrated inFIG.7in the overlap shape of the first lead wiring line and the second lead wiring line with respect to the following points. The display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, and the frame region of a notch portion adjacent to the main display portion includes a plurality of first lead wiring lines and second lead wiring lines that overlap each other. The first lead wiring line on the side closer to the display region out of the above-described plurality of first lead wiring lines is referred to as a lower first lead wiring line W21. A first lead wiring line on the side opposite to the display region and adjacent to the above described lower first lead wiring line W21is referred to as an upper first lead wiring line W11. A second lead wiring line that overlaps the above described lower first lead wiring line W21is referred to as a lower second lead wiring line W22. A second lead wiring line on the side opposite to the display region and adjacent to the above described lower second lead wiring line W22is referred to as an upper second lead wiring line W12. In this case, the second region B of the upper first lead wiring line W11that overlaps the upper second lead wiring line W12and the second region B of the lower first lead wiring line W21that overlaps the lower second lead wiring line W22have different overlap widths in a direction orthogonal to the extending direction of the lead wiring lines in a plan view. As illustrated inFIG.11, the amount of overlap of the upper first lead wiring line W11and the upper second lead wiring line W12on the side closer to the notch display portion having fewer subpixels, is configured to be greater than the amount of overlap of the lower first lead wiring line W21and the lower second lead wiring line W22on the side closer to the display region. By increasing the amount of overlap of at least one of the horizontal direction and the vertical direction, the capacitance can be increased. According to this configuration, a difference in the amount of loads generated between the notch display portion having a small number of subpixels and the display region having a large number of subpixels can be reduced, and luminance variation can be suppressed. The width or area where the upper first lead wiring line W11overlaps the upper second lead wiring line W12in the second region B may be smaller than the width or area where the lower first lead wiring line W21overlaps the lower second lead wiring line W22in the second region B. A width of at least one of the first region A and the second region B in a direction orthogonal to the extending direction of the lead wiring line may be determined according to the number of subpixels electrically connected to the lead wiring lines. As the number of the subpixels to be connected increases, the overlap width may be reduced. MODIFICATION EXAMPLE 1 As a modification example of the display device of the third embodiment illustrated inFIG.11, a display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, in a frame region of the notch portion adjacent to the first notch display portion, either one lead wiring line of the first lead wiring line and the second lead wiring line may have only the first region A, and in the frame region of the notch portion adjacent to the second notch display portion, either one lead wiring line of the first lead wiring line and the second lead wiring line may have only the first region A. According to the above described configuration, the overlap area can be maintained not only when the wiring line is misaligned in the vertical direction, but also when the wiring line is misaligned in the horizontal direction. In the examples described above, the examples in which the lead wiring lines of adjacent light emission control lines G overlap each other via the inorganic insulating film in the frame region on the periphery of the notch portion have been described. Alternatively, the lead wiring lines of adjacent light emission control lines EM may overlap each other via the inorganic insulating film in the frame region on the periphery of the notch portion. In this case, the control lines that are each divided at the first notch display portion SA1or the second notch display portion SA2in the notch portion are the light emission control lines G and are driven on one side. Supplement A display device according to a first aspect of the disclosure includes: a display region formed with a notch portion; and a frame region surrounding the display region, wherein the display region includes a plurality of data signal lines, a plurality of control lines including a plurality of scanning control lines intersecting the plurality of data signal lines and a plurality of light emission control lines intersecting the plurality of data signal lines, and a plurality of subpixel circuits corresponding to respective intersection points of the plurality of data signal lines and the plurality of scanning control lines, a frame region on a periphery of the notch portion out of the frame region includes a first lead wiring line electrically connected to a first control line and extending from the display region toward the notch portion, the first control line being one of the plurality of control lines, and a second lead wiring line electrically connected to a second control line and extending from the display region toward the notch portion, the second control line being adjacent to the first control line, in the display region, the first control line and the second control line are formed of a first metal layer, in the frame region on the periphery of the notch portion, the first lead wiring line is formed of the first metal layer, and the second lead wiring line is formed of a second metal layer, the second metal layer being a different layer from the first metal layer, in a plan view, an extending direction of the first lead wiring line and an extending direction of the second lead wiring line are same, the first lead wiring line and the second lead wiring line overlap each other via an inorganic insulating film, and either one lead wiring line of the first lead wiring line and the second lead wiring line includes a first region overlapping to straddle only an end portion of another lead wiring line of the first lead wiring line and the second lead wiring line on a side opposite to the display region in a direction orthogonal to the extending direction of the other lead wiring line and a second region overlapping to straddle only an end portion of the other lead wiring line on a side closer to the display region in the direction orthogonal to the extending direction the other lead wiring line. In a display device according to a second aspect of the disclosure, the first control line and the second control line are the plurality of scanning control lines. In a display device according to a third aspect of the disclosure, the first control line and the second control line are the plurality of light emission control lines. In a display device according to a fourth aspect of the disclosure, the first lead wiring line and the second lead wiring line are same in width. In a display device according to a fifth aspect of the disclosure, the either one lead wiring line of the first lead wiring line and the second lead wiring line is the first lead wiring line, and a second lead wiring line overlapped with the first lead wiring line straddling only the end portion on the side opposite to the display region and a second lead wiring line overlapped with the first lead wiring line straddling only the end portion on the side closer to the display region are adjacent to each other. In a display device according to a sixth aspect of the disclosure, the either one lead wiring line of the first lead wiring line and the second lead wiring line is the second lead wiring line, and a first lead wiring line overlapped with the second lead wiring line straddling only the end portion on the side opposite to the display region and a first lead wiring line overlapped with the second lead wiring line straddling only the end portion on the side closer to the display region are adjacent to each other. In a display device according to a seventh aspect of the disclosure, in the either one lead wiring line of the first lead wiring line and the second lead wiring line, a sum of a length of the first region in the extending direction and a sum of a length of the second region in the extending direction are same. In a display device according to an eighth aspect of the disclosure, the first region and the second region are arranged in an order of the first region, the second region, and the first region, or in an order of the second region, the first region, and the second region, in the extending direction of the lead wiring line. In a display device according to a ninth aspect of the disclosure, both ends of an overlap region are both the first region or both the second region in the extending direction of at least one of the lead wiring lines. A display device according to a tenth aspect of the disclosure includes a third region between the first region and the second region, the third region involves overlapping at an upper portion of the lead wiring line and overlapping at a lower portion of the lead wiring line in a direction orthogonal to the extending direction. In a display device according to an eleventh aspect of the disclosure, out of the first lead wiring line, a first lead wiring line on the side closer to the display region is configured to be a lower first lead wiring line, and a first lead wiring line adjacent to the lower first lead wiring line and on the side opposite to the display region is configured to be an upper first lead wiring line, a second lead wiring line overlapping the lower first lead wiring line is configured to be a lower second lead wiring line, a second lead wiring line adjacent to the lower second lead wiring line and on the side opposite to the display region is configured to be an upper second lead wiring line, and a second region of the upper first lead wiring line and the upper second lead wiring line and a second region of the lower first lead wiring line and the lower second lead wiring line are different in length from each other. In a display device according to a twelfth aspect of the disclosure, out of the first lead wiring line, a first lead wiring line on the side closer to the display region is configured to be a lower first lead wiring line, and a first lead wiring line adjacent to the lower first lead wiring line and on the side opposite to the display region is configured to be an upper first lead wiring line, a second lead wiring line overlapping the lower first lead wiring line is configured to be a lower second lead wiring line, a second lead wiring line adjacent to the lower second lead wiring line and on the side opposite to the display region is configured to be an upper second lead wiring line, and a first region of the upper first lead wiring line and the upper second lead wiring line and a first region of the lower first lead wiring line and the lower second lead wiring line are different in length from each other. A display device according to a thirteenth aspect of the disclosure, the display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, and a frame region of the notch portion adjacent to the main display portion includes the lower first lead wiring line, the upper first lead wiring line, the lower second lead wiring line, and the upper second lead wiring line. In a display device according to a fourteenth aspect of the disclosure, in a first lead wiring line closest to the display region out of the first lead wiring line, the first region and the second region of the second lead wiring line overlapped with the first lead wiring line are same in length. In a display device according to a fifteenth aspect of the disclosure, a length of the second region of the second lead wiring line increases or decreases from the display region toward the notch portion. In a display device according to a sixteenth aspect of the disclosure, a length of the first region of the second lead wiring line increases or decreases from the display region toward the notch portion. In a display device according to a seventeenth aspect of the disclosure, the display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, a frame region of a notch portion adjacent to the main display portion includes a plurality of first lead wiring lines and a plurality of second lead wiring lines overlapping each other, out of the plurality of first lead wiring lines, a first lead wiring line on the side closer to the display region is configured to be a lower first lead wiring line, and a first lead wiring line adjacent to the lower first lead wiring line and on the side opposite to the display region is configured to be an upper first lead wiring line, a second lead wiring line overlapping the lower first lead wiring line is configured to be a lower second lead wiring line, a second lead wiring line adjacent to the lower second lead wiring line and on the side opposite to the display region is configured to be an upper second lead wiring line, and in a plan view, a second region of the upper first lead wiring line overlapping the upper second lead wiring line and a second region of the lower first lead wiring line overlapping the lower second lead wiring line are different in overlap width from each other in a direction orthogonal to the extending direction of the lead wiring lines. In a display device according to an eighteenth aspect of the disclosure, a width where the upper first lead wiring line overlaps the upper second lead wiring line in the second region is smaller than a width where the lower first lead wiring line overlaps the lower second lead wiring line in the second region. In a display device according to a nineteenth aspect of the disclosure, an area where the upper first lead wiring line overlaps the upper second lead wiring line in the second region is smaller than an area where the lower first lead wiring line overlaps the lower second lead wiring line in the second region. In a display device according to a twentieth aspect of the disclosure, a width of at least one of the first region and the second region in the direction orthogonal to the extending direction of the lead wiring lines is determined according to the number of subpixels electrically connected to the lead wiring lines. In a display device according to a twenty-first aspect of the disclosure, as the number of the subpixels to be connected increases, the overlap width decreases. In a display device according to a twenty-second aspect of the disclosure, the display region includes a main display portion, a first notch display portion, and a second notch display portion, the first notch display portion and the second notch display portion sandwiching the notch portion, in a frame region of the notch portion adjacent to the first notch display portion, either one lead wiring line of the first lead wiring line and the second lead wiring line includes only the first region, and in a frame region of the notch portion adjacent to the second notch display portion, either one lead wiring line of the first lead wiring line and the second lead wiring line includes only the first region. Note that the display device related to the disclosure may be provided with a display panel having flexibility and a bendable display element. The above-mentioned display element includes a display element having luminance or a transmittance controlled by current and a display element having luminance or a transmittance controlled by voltage. For example, the display device according to the disclosure may include an Organic Light Emitting Diode (OLED) as a current-controlled display element. In this case, the display device according to the present embodiment may be an Electro Luminescent (EL) display. Alternatively, the display device according to the disclosure may include an inorganic light emitting diode as a current-controlled display element. In this case, the display device according to the present embodiment may be a Quantum dot Light Emitting Diode (QLED) display provided with an EL display QLED such as an inorganic EL display. Examples of a voltage-controlled display element include a liquid crystal display element and the like. Additional Items The disclosure is not limited to each of the embodiments described above, and various modifications may be made within the scope of the claims. Embodiments obtained by appropriately combining technical approaches disclosed in each of the different embodiments also fall within the technical scope of the disclosure. Furthermore, novel technical features can be formed by combining the technical approaches disclosed in the embodiments. | 48,758 |
11943978 | DESCRIPTION OF EMBODIMENTS The following will describe embodiments of the disclosure in detail with reference to drawings. The disclosure is by no means limited to these embodiments. First Embodiment FIGS.1to13illuminate a first embodiment of a display device in accordance with the disclosure. The current and subsequent embodiments will discuss OLED display devices including OLEDs as an example of the display device that includes light-emitting elements.FIG.1is a schematic plan view of a structure of an OLED display device50ain accordance with the present embodiment.FIG.2is a plan view of a display area D of the OLED display device50a.FIG.3is a cross-sectional view of the display area D of the OLED display device50a.FIG.4is an equivalent circuit diagram of one of pixel circuits29in the OLED display device50a.FIG.5is a cross-sectional view of an organic light-emitting layer23in the OLED display device50a.FIG.6is an enlarged plan view of a first terminal portion Ta of a frame area F of the OLED display device50a.FIG.7is an enlarged plan view of a second terminal portion Tb in a flexible printed board40of the OLED display device50a.FIG.8is a schematic enlarged view of region A shown inFIG.1, depicting the first terminal portion Ta and the second terminal portion Tb in the OLED display device50a.FIG.9is a schematic cross-sectional view, taken along line IX-IX inFIG.8, of the first terminal portion Ta and the second terminal portion Tb in the OLED display device50a.FIG.10is an enlarged plan view, equivalent toFIG.7, of the second terminal portion Tb of the flexible printed board40in a first variation example of the OLED display device50a.FIGS.11,12, and13are diagrams of ranges of the angle of inclination θ of second power supply openings Vah and Vai with respect to first power supply openings Sah and Sai in the OLED display device50a. The OLED display device50a, as shown inFIG.1, has, for example, the rectangular display area D for displaying images and the frame-shaped frame area F around the display area D. The present embodiment will discuss the rectangular display area D as an example. The “rectangular” display area D in the current context however may be “quasi-rectangular” and have, for example, an arched side(s), a round corner(s), and/or a notched side(s). In the display area D is there provided a matrix of subpixels as shown inFIG.2. Also in the display area D, for example, a subpixel including a red-light-emitting region Lr for a display in red, a subpixel including a green-light-emitting region Lg for a display in green, and a subpixel including a blue-light-emitting region Lb for a display in blue are provided adjacent to each other as shown inFIG.2. Each pixel P in the display area D is formed by, for example, three adjacent subpixels including the red-light-emitting region Lr, the green-light-emitting region Lg, and the blue-light-emitting region Lb. Referring toFIG.1, the frame area F includes the first terminal portion Ta on the right side thereof. The first terminal portion Ta extends in direction Y is the top-bottom direction inFIG.1. Still referring toFIG.1, the frame area F further includes a bending portion B extending parallel to direction Y between the display area D and the first terminal portion Ta. The bending portion B can be bent by 180° along direction Y which is the top-bottom direction inFIG.1(to form a “U” shape). The flexible printed board40, which will be described later, is attached to the first terminal portion Ta as shown inFIG.1. The second terminal portion Tb, which will be described later, is provided on one of the sides of the flexible printed board40so as to extend in direction Y. In the OLED display device50a, besides direction Y, direction X is defined that is both perpendicular to direction Y and parallel to the surface of a resin substrate layer10as shown inFIG.1. The resin substrate layer10will be described later. The OLED display device50aincludes, as shown inFIG.3, the resin substrate layer10, a TFT layer20, OLEDs25, and a sealing layer30. The resin substrate layer10serves as a substrate. The TFT layer20resides on the resin substrate layer10and includes a plurality of TFTs (thin film transistors). The OLEDs25resides on the TFT layer20as light-emitting elements forming the display area D. The sealing layer30covers the OLEDs25. The resin substrate layer10is made of, for example, a polyimide resin. The substrate may be, for example, a glass substrate. The TFT layer20includes: a base coat film11on the resin substrate layer10; a first TFT9a, a second TFT9b, and a capacitor9cas the pixel circuit29(seeFIG.4) in each subpixel on the base coat film11; and a TFT planarization film19on the first TFTs9a, the second TFTs9b, and the capacitors9c, as shown inFIG.3. The pixel circuits29, each associated with a different subpixel, are arranged in a matrix in the TFT layer20. The TFT layer20includes a plurality of gate lines14extending parallel to each other in the left-right direction inFIGS.2and4, as shown inFIGS.2and4. The TFT layer20further includes a plurality of source lines18fextending parallel to each other in the top-bottom direction inFIGS.2and4, as shown inFIGS.2and4. The TFT layer20further includes a plurality of power supply lines18gextending parallel to each other in the top-bottom direction inFIGS.2and4, as shown inFIGS.2and4. Each power supply line18gis provided adjacent to an associated one of the source lines18fas shown inFIG.2. The base coat film11includes either a single inorganic insulation film of, for example, silicon nitride, silicon oxide, or silicon oxynitride or a stack of any of these inorganic insulation films. Each first TFT9ais electrically connected to an associated one of the gate lines14and an associated one of the source lines18fin each subpixel as shown inFIG.4. The first TFT9aincludes a semiconductor layer12a, a gate insulation film13, a gate electrode14a, a first interlayer insulation film15, a second interlayer insulation film17, a source electrode18a, and a drain electrode18ball on the base coat film11in this order as shown inFIG.3. The semiconductor layer12ais, for example, a polysilicon film provided in an insular manner on the base coat film11as shown inFIG.3and includes channel regions, source regions, and drain regions. The gate insulation film13is provided so as to cover the semiconductor layer12aas shown inFIG.3. The gate electrode14ais provided on the gate insulation film13so as to overlap the channel region in the semiconductor layer12aas shown inFIG.3. The first interlayer insulation film15and the second interlayer insulation film17are provided in this order so as to cover the gate electrode14aas shown inFIG.3. The source electrode18aand the drain electrode18bare provided on the second interlayer insulation film17so as to be separated from each other as shown inFIG.3. The source electrode18aand the drain electrode18bare electrically connected respectively to a source region and a drain region in the semiconductor layer12avia contact holes formed through the stack of the gate insulation film13, the first interlayer insulation film15, and the second interlayer insulation film17, as shown inFIG.3. The gate insulation film13, the first interlayer insulation film15, and the second interlayer insulation film17each include either a single inorganic insulation film of, for example, silicon nitride, silicon oxide, or silicon oxynitride or a stack of any of these inorganic insulation films. Each second TFT9bis electrically connected to an associated one of the first TFTs9aand an associated one of the power supply lines18gin each subpixel as shown inFIG.4. The second TFT9bincludes a semiconductor layer12b, the gate insulation film13, a gate electrode14b, the first interlayer insulation film15, the second interlayer insulation film17, a source electrode18c, and a drain electrode18dall on the base coat film11in this order as shown inFIG.3. The semiconductor layer12bis, for example, a polysilicon film provided in an insular manner on the base coat film11as shown inFIG.3and includes channel regions, source regions, and drain regions. The gate insulation film13is provided so as to cover the semiconductor layer12bas shown inFIG.3. The gate electrode14bis provided on the gate insulation film13so as to overlap the channel region in the semiconductor layer12bas shown inFIG.3. The first interlayer insulation film15and the second interlayer insulation film17are provided in this order so as to cover the gate electrode14bas shown inFIG.3. The source electrode18cand the drain electrode18dare provided on the second interlayer insulation film17so as to be separated from each other as shown inFIG.3. The source electrode18cand the drain electrode18dare electrically connected respectively to a source region and a drain region in the semiconductor layer12bvia contact holes formed through the stack of the gate insulation film13, the first interlayer insulation film15, and the second interlayer insulation film17, as shown inFIG.3. The first TFTs9aand the second TFTs9bare top-gate TFTs as an example in the present embodiment, but may alternatively be bottom-gate TFTs. Each capacitor9cis electrically connected to an associated one of the first TFTs9aand an associated one of the power supply lines18gin each subpixel as shown inFIG.4. The capacitor9cincludes: a lower conductive layer14cmade of the same material and in the same layer as the gate electrodes14aand14b; the first interlayer insulation film15provided so as to cover the lower conductive layer14c; and an upper conductive layer16provided on the first interlayer insulation film15so as to overlap the lower conductive layer14c, as shown inFIG.3. The upper conductive layer16is electrically connected to the power supply line18gvia a contact hole formed through the second interlayer insulation film17, as shown inFIG.3. The planarization film19is made of, for example, an organic resin material such as a polyimide resin. The OLEDs25include a plurality of first electrodes21, an edge cover22, the organic light-emitting layers (functional layers)23, and a plurality of second electrodes24all on the planarization film19in this order as shown inFIG.3. The first electrodes21are associated with the respective subpixels and arranged in a matrix on the planarization film19as shown inFIG.3. Each first electrode21is electrically connected to the drain electrode18dof the second TFT9bvia a contact hole formed through the planarization film19as shown inFIG.3. The first electrode21has a function of injecting holes to the organic light-emitting layer23. The first electrode21is preferably formed of a material that has a large work function in order to improve the efficiency of hole injection to the organic light-emitting layer23. The first electrode21is made of, for example, a metal material such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), or tin (Sn). The first electrode21may alternatively be made of, for example, an alloy such as astatine-astatine oxide (At—AtO2). As another alternative, the first electrode21may be made of, for example, an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxides (ITO), or indium zinc oxide (IZO). As a further alternative, the first electrode21may be a stack of layers of any of these materials. Examples of compound materials that have a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO). The edge cover22is arranged to form a lattice covering the peripheries of the first electrodes21as shown inFIG.3. The edge cover22may be made of, for example, a positive photosensitive resin such as polyimide resin, acrylic resin, polysiloxane resin, or novolac resin. Parts of the surface of the edge cover22protrude upwards inFIG.3as shown inFIG.3, to provide insular pixel photo spacers. The organic light-emitting layers23, one for each subpixel, are arranged in a matrix on the first electrodes21as shown inFIG.3. Each organic light-emitting layer23includes a hole injection layer1, a hole transport layer2, a light-emitting layer3, an electron transport layer4, and an electron injection layer5all on the first electrode21in this order as shown inFIG.5. The hole injection layer1, alternatively referred to as the anode buffer layer, has a function of bringing the energy levels of the first electrode21and the organic light-emitting layer23closer to each other to improve the efficiency of hole injection from the first electrode21to the organic light-emitting layer23. The hole injection layer1is made of, for example, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyaryl alkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styryl anthracene derivative, a fluorenone derivative, a hydrazone derivative, or a stilbene derivative. The hole transport layer2has a function of improving the efficiency of hole transport from the first electrode21to the organic light-emitting layer23. The hole transport layer2is made of, for example, a porphyrin derivative, an aromatic tertiary amine compound, a styryl amine derivative, polyvinyl carbazole, poly-p-phenylene vinylene, polysilane, a triazole derivative, ab oxadiazole derivative, an imidazole derivative, a polyaryl alkane derivative, a pyrazoline derivative, a pyrazolone derivative, a phenylenediamine derivative, an aryl amine derivative, an amine-substituted chalcone derivative, an oxazole derivative, a styryl anthracene derivative, a fluorenone derivative, a hydrazone derivative, a stilbene derivative, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, or zinc selenide. The light-emitting layer3is injected with holes and electrons from the first electrode21and the second electrode24respectively when the light-emitting layer3is under voltage applied by the first electrode21and the second electrode24. These injected holes and electrons recombine in the light-emitting layer3. The light-emitting layer3is made of a material that has a high light-emission efficiency. The light-emitting layer3is made of, for example, a metal oxinoid compound [8-hydroxy quinoline metal complex], a naphthalene derivative, an anthracene derivative, a diphenyl ethylene derivative, a vinyl acetone derivative, a triphenyl amine derivative, a butadiene derivative, a coumarin derivative, a benzoxazole derivative, an oxadiazole derivative, an oxazole derivative, a benzimidazole derivative, a thiadiazole derivative, a benzthiazole derivative, a styryl derivative, a styryl amine derivative, a bis(styryl)benzene derivative, a tris(styryl)benzene derivative, a perylene derivative, a perynone derivative, an amino pyrene derivative, a pyridine derivative, a rhodamine derivative, an acridine derivative, phenoxazone, a quinacridone derivative, rubrene, poly-p-phenylene vinylene, or polysilane. The electron transport layer4has a function of efficiently transporting electrons to the light-emitting layer3. The electron transport layer4is made of, for example, an organic compound such as an oxadiazole derivative, a triazole derivative, a benzoquinone derivative, a naphthoquinone derivative, an anthraquinone derivative, a tetracyanoanthraquinodimethane derivative, a diphenoquinone derivative, a fluorenone derivative, a silole derivative, or a metal oxinoid compound. The electron injection layer5has a function of bringing the energy levels of the second electrode24and the organic light-emitting layer23closer to each other to improve the efficiency of electron injection from the second electrode24to the organic light-emitting layer23. This function can lower the drive voltage of the OLED25. The electron injection layer5, alternatively referred to as the cathode buffer layer, is made of, for example, an inorganic alkali compound such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), or barium fluoride (BaF2); aluminum oxide (Al2O3); or strontium oxide (SrO). The second electrode24is provided so as to cover the organic light-emitting layer23and the edge cover22as shown inFIG.3. The second electrode24has a function of injecting electrons to the organic light-emitting layer23. The second electrode24is more preferably made of a material that has a small work function in order to improve the efficiency of electron injection to the organic light-emitting layer23. The second electrode24is made of, for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), or lithium fluoride (LiF). The second electrode24may alternatively be made of, for example, a magnesium-copper (Mg—Cu) alloy, a magnesium-silver (Mg—Ag) alloy, a sodium-potassium (Na—K) alloy, an astatine-astatine oxide (At—AtO2), a lithium-aluminum (Li—Al) alloy, a lithium-calcium-aluminum (Li—Ca—Al) alloy; or a lithium fluoride-calcium-aluminum (LiF—Ca—Al) alloy. As another alternative, the second electrode24may be made of, for example, an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). As a further alternative, the second electrode24may be a stack of layers of any of these materials. Examples of materials that have a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium-copper (Mg—Cu), magnesium-silver (Mg—Ag), sodium-potassium (Na—K), lithium-aluminum (Li—Al), lithium-calcium-aluminum (Li—Ca—Al), and lithium fluoride-calcium-aluminum (LiF—Ca—Al). The sealing layer30includes: a first inorganic insulation film26provided so as to cover the second electrodes24; an organic film27on the first inorganic insulation film26; and a second inorganic insulation film28provided so as to cover the organic film27, as shown inFIG.3. The sealing layer30has a function of protecting the organic light-emitting layer23from, for example, water and oxygen. The first inorganic insulation film26and the second inorganic insulation film28are made of, for example, an inorganic material such as silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiNxwhere x is a positive number) (e.g., trisilicon tetranitride (Si3N4), or silicon carbide nitride (SiCN). The organic film27is made of, for example, an organic material such as an acrylic resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin. The OLED display device50aincludes a plurality of first signal terminal electrodes31fand a plurality of first power supply terminal electrodes31hand31ialong the direction in which the first terminal portion Ta extends (direction Y) in the first terminal portion Ta, as shown inFIGS.6,8, and9. Each pixel circuit29(seeFIG.4) is fed with a data signal through an associated one of the first signal terminal electrodes31fand with a power supply voltage through an associated one of the first power supply terminal electrodes31hand an associated one of the first power supply terminal electrodes31i. As shown inFIGS.6,8, and9, the first signal terminal electrodes31freside in a middle portion C of the first terminal portion Ta in terms of direction Y. Meanwhile, the first power supply terminal electrodes31hand31ireside in end portions Eh and Ei of the first terminal portion Ta in terms of direction Y. In other words, the first signal terminal electrodes31fare flanked by the first power supply terminal electrodes31hand31i. Still referring toFIGS.6,8, and9, the first power supply terminal electrodes31hreside in the end portions Eh which are closer to the far ends of the first terminal portion Ta (closer to the exterior) in terms of direction Y than are the end portions Ei in terms of direction Y where the first power supply terminal electrodes31ireside. The first signal terminal electrodes31fand the first power supply terminal electrodes31hand31iare provided to extend parallel to each other in direction X as shown inFIGS.6and8. In other words, the first power supply terminal electrodes31hand the first power supply terminal electrodes31iare provided parallel to each other in direction X. The first signal terminal electrodes31fare electrically connected to the source lines18fthat have a line width equal to Ha (seeFIG.8). The first signal terminal electrodes31fprovide a plurality of routing lines (180electrically connected to the source lines18fon the display area D side. The routing lines (180are continuous all the way to the first signal terminal electrode31f. The routing lines may have a diode built around transistors interposed between a terminal and the line (near a terminal) to remove noise on input signals and are still considered as “continuous” for the purpose of this specification and consistent with the object of the disclosure. The first power supply terminal electrodes31hare electrically connected to low-voltage power supply main lines18hthat are fed with a low-voltage power supply (ELVSS). The main lines18hhave a line width equal to Hb (>Ha, seeFIG.8). The first power supply terminal electrodes31hare also electrically connected to the second electrodes24via the low-voltage power supply main lines18h. The low-voltage power supply main lines18hare routed in the frame area F, substantially like a letter “C” skirting around the display area D in a plan view as shown inFIG.1. The low-voltage power supply main lines18hare continuous all the way to the first power supply terminal electrodes31h. The first power supply terminal electrodes31hand the low-voltage power supply main lines18hare made of the same material and in the same layer as the source lines18f. The first power supply terminal electrodes31iare electrically connected to high-voltage power supply main lines18ithat are led with a high-voltage power supply (ELVDD). The main lines18ihave a line width equal to Hb (seeFIG.8). The first power supply terminal electrodes31iare also electrically connected to the power supply lines18gand the first electrodes21via the high-voltage power supply main lines18i. The high-voltage power supply main lines18iare routed in the frame area F, substantially like a letter “C” skirting around the display area D in a plan view as shown inFIG.1. The high-voltage power supply main lines18ireside internal to the low-voltage power supply main lines18h. The high-voltage power supply main lines18iare continuous all the way to the first power supply terminal electrodes31i. The first power supply terminal electrodes31iand the high-voltage power supply main lines18iare made of the same material and in the same layer as the source lines18f. The power supply lines18gare pulled out to the first terminal portion Ta to provide a plurality of routing lines (18g) electrically connected to the power supply lines18gon the display area D side. The routing lines (18g) are continuous all the way to the first power supply terminal electrodes31i. The first power supply terminal electrodes31hbranch off the low-voltage power supply main lines18hin the first terminal portion Ta as shown inFIGS.6and8(five and three first power supply terminal electrodes31hbranch off a low-voltage power supply main line18hinFIGS.6and8respectively). In other words, the branching, first power supply terminal electrodes31hhave a line width equal to Ha (seeFIG.8). The first power supply terminal electrodes31ibranch off the high-voltage power supply main lines18iin the first terminal portion Ta as shown inFIGS.6and8(five and three first power supply terminal electrodes31ibranch off a high-voltage power supply main line18iinFIGS.6and8respectively). In other words, the branching, first power supply terminal electrodes31ihave a line width equal to Ha (seeFIG.8). The branching, first power supply terminal electrodes31hand31ihave a pitch equal to He (seeFIG.8), and the first signal terminal electrodes31fhave a pitch equal to Hd (seeFIG.8). He is equal to Hd. The OLED display device50aincludes a planarization film32in the first terminal portion Ta so as to cover the first signal terminal electrodes31fand the first power supply terminal electrodes31hand31ias shown inFIGS.6,8, and9. The planarization film32has: a plurality of first signal openings Saf where the first signal terminal electrodes31fare at least partially exposed; and the plurality of first power supply openings Sah and Sai where the branching, first power supply terminal electrodes31hand31iare at least partially exposed. The planarization film32is made of the same material and in the same layer as the planarization film19for the TFTs. The first signal opening Saf is formed in a rectangular shape in a plan view along the periphery of the first signal terminal electrode31fas shown inFIGS.6and8. Meanwhile, the first power supply opening Sah is formed in a rectangular shape in a plan view along the periphery of the brandling, first power supply terminal electrode31h. The first power supply opening Sai is formed in a rectangular shape in a plan view along the periphery of the branching, first power supply terminal electrode31i. The planar shapes of the openings Saf, Sah, and Sai are not necessarily rectangular as shown in the figures and may be, for example, octagonal or otherwise polygonal, trapezoidal, or elliptical. As described here, in the OLED display device50a, as shown inFIGS.6,8, and9, there is provided a first signal terminal35fin a location where the first signal terminal electrode31fis exposed in the first signal opening Saf. There is provided a first power supply terminal35hin a location where the branching, first power supply terminal electrode31his exposed in the first power supply opening Sah. There is provided a first power supply terminal35iin a location where the branching, first power supply terminal electrode31iis exposed in the first power supply opening Sai. The OLED display device50afurther includes a first dummy terminal33between the first signal terminal electrode31fand the adjacent, first power supply terminal electrode31ias shown inFIG.6. The first dummy terminal33is provided parallel to the direction in which the first signal terminal electrode31fand the first power supply terminal electrode31iextend (direction X) as shown inFIG.6. The first dummy terminal33is not electrically connected to the first signal terminal electrode31fand the first power supply terminal electrode31i. This lack of electrical connection prevents short-circuiting between the first signal terminal electrode31fand the first power supply terminal electrode31i. The first dummy terminal33is separated from the adjacent, first signal terminal electrode31fby a pitch P1f and from the adjacent, first power supply terminal electrode31iby a pitch P1i that is equal to the pitch P1f, as shown inFIG.6. The first dummy terminal33is made of the same material and in the same layer as the first signal terminal electrode31fand the first power supply terminal electrodes31hand31i. The OLED display device50afurther includes a second dummy terminal34between the first power supply terminal electrode31hand the adjacent, first power supply terminal electrode31ias shown inFIG.6. The second dummy terminal34is provided parallel to the direction in which the first power supply terminal electrode31hand the first power supply terminal electrode31iextend (direction X) as shown inFIG.6. The second dummy terminal34is not electrically connected to the first power supply terminal electrode31hand the first power supply terminal electrode31i. This lack of electrical connection prevents short-circuiting between the first power supply terminal electrode31hand the first power supply terminal electrode31i. The second dummy terminal34is separated from the adjacent, first power supply terminal electrode31hby a pitch P2h and from the adjacent, first power supply terminal electrode31iby a pitch P2i that is equal to the pitch P2h, as shown inFIG.6. The second dummy terminal34is made of the same material and in the same layer as the first signal terminal electrode31fand the first power supply terminal electrodes31hand31i. The OLED display device50amay include, at both ends (outside) of the first power supply terminal electrode31hin terms of direction Y, a dummy terminal that is not electrically connected to the first power supply terminal electrode31h. In the OLED display device50a, the flexible printed board40is attached to the first terminal portion Ta by pressure bonding through a conductive paste60as shown inFIGS.1,8, and9. The conductive paste60is, for example, an anisotropic conductive film (ACF).FIGS.8and9show no dummy terminals33and34and no dummy terminals43and44which will be described later.FIG.8indicates the first terminal portion Ta of the frame area F with a dotted line and the second terminal portion Tb of the flexible printed board40with a solid line. Referring toFIGS.1,8, and9, in the flexible printed board40, the second terminal portion Tb resides facing the first terminal portion Ta at the pressure-bonded end of the first terminal portion Ta and extends in the top-bottom direction in the figure (direction Y). The second terminal portion Tb includes a plurality of second signal terminal electrodes41f, a plurality of second power supply terminal electrodes41h, and a plurality of second power supply terminal electrodes41iall extending in the direction in which the second terminal portion Tb extends (direction Y), as shown inFIGS.7to9. The second signal terminal electrode41fand the second power supply terminal electrodes41hand41iare made of the same material as the source line18f. More specifically, as shown inFIGS.7to9, each second signal terminal electrode41fis positioned to match, and electrically connected to, an associated one of the first signal terminal electrodes31fthrough the conductive paste60. Each second power supply terminal electrode41his positioned to match, and electrically connected to, an associated one of the branching, first power supply terminal electrodes31hthrough the conductive paste60. Each second power supply terminal electrode41iis positioned to match, and electrically connected to, an associated one of the branching, first power supply terminal electrodes31ithrough the conductive paste60. More specifically, as shown inFIGS.7to9, the second signal terminal electrode41fresides in the middle portion C in terms of direction Y. In contrast, the second power supply terminal electrodes41hand41ireside in the end portions Eh and Ei in terms of direction Y. The second power supply terminal electrode41hresides in the end portions Eh which are closer to the far ends (closer to the exterior) in terms of direction than are the end portions Ei in terms of direction Y Where the second power supply terminal electrodes41ireside, as shown inFIGS.7to9. The OLED display device50afurther includes an insulation film42in the second terminal portion Tb so as to cover the second signal terminal electrodes41fand the second power supply terminal electrodes41hand41ias shown inFIGS.7to9. The insulation film42has: a plurality of second signal openings Vaf where the second signal terminal electrodes41fare at least partially exposed; the plurality of second power supply openings Vah where the second power supply terminal electrodes41hare at least partially exposed; and the plurality of second power supply openings Vai where the second power supply terminal electrodes41iare at least partially exposed. The insulation film42includes either a single inorganic insulation film of, for example, silicon nitride, silicon oxide, or silicon oxynitride or a stack of any of these inorganic insulation films. The second signal opening Vaf is formed along the periphery of the second signal terminal electrode41f. The second power supply opening Vah is formed along the periphery of the second power supply terminal electrode41h. The second power supply opening Vai is formed along the periphery of the second power supply terminal electrode41i. As described here, in the OLED display device50a, there is provided a second signal terminal45fin a location where the second signal terminal electrode41fis exposed in the second signal opening Vaf. There is provided a second power supply terminal45hin a location where the second power supply terminal electrode41his exposed in the second power supply opening Vah. There is provided a second power supply terminal45iin a location where the second power supply terminal electrode41iis exposed in the second power supply opening Vai. The second signal opening Vaf has the same length as the first signal opening Saf in the longer-side direction (direction X) thereof as shown inFIG.8. The third dummy terminals43and the fourth dummy terminals44in the OLED display device50aare provided in those locations in the second terminal portion Tb which correspond to those of the first dummy terminals33and the second dummy terminals34and with the same pitches as the first dummy terminals33and the second dummy terminals34as shown inFIG.7. The third dummy terminal43is not electrically connected to the second signal terminal electrode41fand the second power supply terminal electrode41i. The fourth dummy terminal44is not electrically connected to the second power supply terminal electrode41hand the second power supply terminal electrode41i. The second power supply terminal electrode41hmay include, at both ends (outside) thereof in terms of direction Y, a dummy terminal that is not electrically connected to the second power supply terminal electrode41h. In the OLED display device50a, as shown inFIGS.8and9, the first signal terminal electrode31fat least partially overlaps at least a part of the second signal terminal electrode41fin a plan view. The first power supply terminal electrode31hat least partially overlaps at least a part of the second power supply terminal electrode41hin a plan view. The first power supply terminal electrode31iat least partially overlaps at least a part of the second power supply terminal electrode41iin a plan view. More specifically, as shown inFIGS.8and9, the portion where the first signal terminal electrode31fis exposed in the first signal opening Saf (i.e., the first signal terminal35f) overlaps the portion where the second signal terminal electrode41fis exposed in the second signal opening Vaf (i.e., the second signal terminal45f) in a plan view. The portion where the first power supply terminal electrode31his exposed in the first power supply opening Sah (i.e., the first power supply terminal35h) overlaps the portion where the second power supply terminal electrode41his exposed in the second power supply opening Vah (i.e., the second power supply terminal45h) in a plan view. The portion where the first power supply terminal electrode31iis exposed in the first power supply opening Sai (i.e., the first power supply terminal35i) overlaps the portion where the second power supply terminal electrode41iis exposed in the second power supply opening Vai (i.e., the second power supply terminal45i) in a plan view. The first signal opening Saf, the first power supply openings Sah and Sai, the second signal opening Vaf, and the second power supply openings Vah and Vai are filled with the conductive paste60as shown inFIG.9. In other words, as shown inFIG.9, the first signal terminal35f, the first power supply terminals35hand35i, the second signal terminal45f, and the second power supply terminals45hand45ihave the surfaces thereof covered by the conductive paste60. This particular structure holds the first signal terminal35fand the second signal terminal45fin contact with each other and electrically connects the first signal terminal35fand the second signal terminal45fto each other through the conductive paste60. The structure also holds the first power supply terminal35hand the second power supply terminal45hin contact with each other and electrically connects the first power supply terminal35hand the second power supply terminal45hthrough the conductive paste60. The structure also holds the first power supply terminal35iand the second power supply terminal45iin contact with each other and electrically connects the first power supply terminal35iand the second power supply terminal45ithrough the conductive paste60. In the OLED display device50a, as shown inFIGS.7and8, the second power supply terminal electrode41his inclined from the direction in which the branching, first power supply terminal electrode31hextends (direction X). The second power supply terminal electrode41iis inclined from the direction in which the branching, first power supply terminal electrode31iextends (direction X). In contrast, the first signal terminal electrode31fand the second signal terminal electrode41fare parallel to each other as shown inFIGS.6and8. In other words, the second signal terminal electrode41fis parallel to the direction in which the first signal terminal electrode31fextends (direction X). More specifically, referring toFIG.7, a pair of second power supply terminal electrodes41his inclined in different directions from direction X in the respective end portions Eh of the second terminal portion Tb in terms of direction Y. A pair of second power supply terminal electrodes41iis inclined in different directions from direction X in the respective end portions Ei of the second terminal portion Tb in terms of direction Y. Still referring toFIG.7, a pair of second power supply terminal electrodes41hand41iis symmetric in the left-right direction with respect to the middle portion C of the second terminal portion Tb (more specifically, in direction X in which the second signal terminal electrode41fextends in the middle portion C of the second terminal portion Tb, in other words, with respect to the second signal terminal electrode41f). In other words, as shown inFIGS.7and8, the second power supply opening Vah (second power supply terminal45h) where the second power supply terminal electrode41his exposed resides along the periphery of the second power supply terminal electrode41hand is shaped like a parallelogram in a plan view. The second power supply opening Vai (second power supply terminal45i) where the second power supply terminal electrode41iis exposed resides along the periphery of the second power supply terminal electrode41iand is shaped like a parallelogram in a plan view. Meanwhile, the second signal opening Vaf (second signal terminal45f) resides along the periphery of the second signal terminal electrode41fand is shaped like a rectangle in a plan view as shown inFIGS.7and8. In this particular structure, the pressure bonding area does not change much between the first power supply terminal35hand the second power supply terminal45hand also between the first power supply terminal35iand the second power supply terminal45ieven when precision varies in direction Y (direction perpendicular to the direction in which the second power supply terminals45hand45iextend) in connecting the flexible printed board40to the first terminal portion Ta by pressure bonding. The structure therefore reduces differences in pressure bonding area in the OLED display device50awithout having to provide, for example, a guide member to prevent displacements that may occur under pressurization. Hence, a simple structure is capable of connecting the first power supply terminals35hand the second power supply terminals45hwith high precision and of connecting the first power supply terminals35iand the second power supply terminals45iwith high precision. The language, “connecting power supply terminal electrodes with each other with high precision,” for the purpose of this specification indicates that the power supply terminal electrodes are connected to each other with possibly minimum (small) differences in pressure bonding area between the power supply terminal electrodes caused by pressure bonding discrepancy. The range of the angle of inclination θ of the second power supply openings Vah and Vai (second power supply terminals45hand45i) with respect to direction Y is calculated from, for example, Eqs. 1 to 3 below. Referring toFIG.11, letting Ws represent the width (length in direction Y) of the first power supply openings Sah and Sai (first power supply terminals35hand35i), H represent the length thereof in direction X, P represent the pitch thereof, and Wv represent the width of the second power supply openings Vah and Vai, and assuming that the length and pitch of the second power supply openings Vah and Vai are equal to length H and pitch P of the first power supply openings Sah and Sai, the range of the angle of inclination θ may be determined, for example, so as to satisfy Eq. 1 below. [Math 1] π/2>θ>tan−1(M/(1−K)) Eq. 1 where K=Ws/P(0<K<1), and M=H/P(M>0). To increase the pressure bonding area between the first power supply terminals35hand35iand the second power supply terminals45hand45i, it is increasingly preferable if the angle of inclination θ is closer to π/2 so long as Eq. 1 is satisfied. Meanwhile, referring toFIG.12, when width Ws of the first power supply openings Sah and Sai is increased to increase the pressure bonding area between the first power supply terminals35hand35iand the second power supply terminals45hand45i, the range of the angle of inclination θ may be determined, for example, so as to satisfy Eq. 2 below. [Math 2] π/2>θ>tan−1(M) Eq. 2 where M is defined as described above. Referring toFIG.13, when length H1 of the first power supply openings Sah and Sai in direction X lies within length H2 of the second power supply openings Vah and Vai in direction X in a plan view (the first power supply openings Sah and Sal and the second power supply openings Vah and Vai have the same width W and pitch P), the range of the angle of inclination θ may be determined, for example, so as to satisfy Eq. 3 below. [Math 3] π/2>θ>tan−1((H1−dx)/(2(P−Ws)−dy)) Eq. 3 where dx=(H1−H2)/2, and dy=H2/(2·tan θ). The OLED display device50adescribed above is arranged, in each subpixel, to turn on the first TFT9aby inputting a gate signal to the first TFT9avia the gate line14and to apply a data signal to the gate electrode14band the capacitor9cof the second TFT9bvia the source line18f, to specify the magnitude of the current from the power supply line18gon the basis of the gate voltage of the second TFT9b, so that the specified current is fed to the organic light-emitting layer23, thereby causing the tight-emitting layer3in the organic light-emitting layer23to emit light to produce an image display. In the OLED display device50a, the gate voltage of the second TFT9bis retained by the capacitor9cwhen the first TFT9ais turned off. The light-emitting layer3therefore continuously emits light until another gate signal is inputted in the next frame. Next will be described a method of manufacturing the OLED display device50ain accordance with the present embodiment. The method of manufacturing the OLED display device50ain accordance with the present embodiment includes a TFT layer forming step, an OLED forming step, a sealing layer forming step, a first terminal portion forming step, a second terminal portion forming step, and a flexible printed board attaching step. TFT Layer Forming Step The TFT layer20is formed, for example, by forming the base coat film11, the first TFTs9a, the second TFTs9b, the capacitors9c, and the planarization film19on the surface of the resin substrate layer10on a glass substrate by a well-known method. OLED Forming Step The first electrodes21, the edge cover22, the organic light-emitting layer23(the hole injection layer1, the hole transport layer2, the light-emitting layer3, the electron transport layer4, and the electron injection layer5), and the second electrodes24are formed by a well-known method on the planarization film19in the TFT layer20formed in the TFT layer forming step, to form the OLEDs25. Sealing Layer Forming Step First, an inorganic insulation film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate now carrying the OLEDs25formed thereon in the OLED forming step, to form the first inorganic insulation film26. Subsequently, a film of an organic resin material such as an acrylic resin is formed, for example, by inkjet technology, on the surface of the substrate now carrying the first inorganic insulation film26formed thereon, to form the organic film27. Furthermore, an inorganic insulation film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, on the substrate now carrying the organic film27formed thereon, to form the second inorganic insulation film28, which provides the sealing layer30. Finally, after a protection sheet (not shown) is attached to the surface of the substrate now carrying the sealing layer30formed thereon, a laser beam is projected onto the glass substrate on the resin substrate layer10to detach the glass substrate from the bottom face of the resin substrate layer10. A protection sheet (not shown) is then attached to the bottom face of the resin substrate layer10from which the glass substrate has been detached. First Terminal Portion Forming Step For instance, the first signal terminal electrodes31fand the first power supply terminal electrodes31hand31iare formed in the prescribed planar shape on the second interlayer insulation film17in an end region of the frame area F by a well-known method. Subsequently, the planarization film32is formed and patterned on the first signal terminal electrodes31fand the first power supply terminal electrodes31hand31iso as to form the first signal openings Saf and the first power supply openings Sah and Sai, which provides the first terminal portion Ta. The first signal terminal electrodes31fand the first power supply terminal electrodes31hand31imay be formed together with, for example, the source lines18fand the power supply lines18gat the same time as, for example, the source electrodes18aand the drain electrodes18bin the first TFTs9aare formed in the TFT layer forming step. Second Terminal Portion Forming Step For instance, the second signal terminal electrodes41fand the second power supply terminal electrodes41hand41iare formed in the prescribed planar shape on the flexible printed board40by a well-known method. Subsequently, the insulation film42is formed and patterned on the second signal terminal electrodes41fand the second power supply terminal electrodes41hand41iso as to form the second signal openings Vaf and the second power supply openings Vah and Vai, which provides the second terminal portion Tb. Flexible Printed Board Attaching Step For instance, the conductive paste60is injected to the first terminal portion Ta formed in the first terminal portion forming step, so as to cover the first signal openings Saf and the first power supply openings Sah and Sai. The second terminal portion Tb of the flexible printed board40is attached to the first terminal portion Ta through the conductive paste60in such a manner that the first signal openings Saf covered by the conductive paste60can overlap the second signal openings Vaf in the second terminal portion Tb formed in the second terminal portion forming step. The OLED display device50ain accordance with the present embodiment can be manufactured through these steps. In the OLED display device50a, the second power supply terminal electrodes41hand41iare inclined from the first power supply terminal electrodes31hand31i(direction X). Alternatively, the first power supply terminal electrodes31hand31imay be inclined from the direction in which the second power supply terminal electrodes41hand41iextend. In the OLED display device50a, a pair of second power supply terminal electrodes41hand41i(second power supply openings Vah and Vai) is inclined in different directions from direction X in the respective end portions Eh and Ei of the second terminal portion Tb in terms of direction Y and are symmetric in the left-right direction with respect to the middle portion C of the second terminal portion Tb (in direction X). Alternatively, a pair of second power supply terminal electrodes41hand41imay be inclined in the same direction from direction X and asymmetric in the left-right direction with respect to the middle portion C as shown inFIG.10. In the OLED display device50a, one of the branching, first power supply terminal electrodes31hmay overlap two or more of the second power supply terminal electrodes41hin a plan view, and one of the branching, first power supply terminal electrodes31imay overlap two or more of the second power supply terminal electrodes41iin a plan view. In the OLED display device50a, as shown inFIG.12, one of the second power supply terminal electrodes41hmay overlap two or more of the branching, first power supply terminal electrodes31hin a plan view, and one of the second power supply terminal electrodes41imay overlap two or more of the branching, first power supply terminal electrodes31iin a plan view. The OLED display device50ain accordance with the present embodiment can achieve the following advantages as described above. (1) The second power supply terminal electrodes41hin the second terminal portion Tb of the flexible printed board40are inclined from the direction in which the first power supply terminal electrodes31hextend in the first terminal portion Ta (direction X), and the second power supply terminal electrodes41iare inclined from the direction in which the first power supply terminal electrodes31iextend (direction X). This particular structure reduces differences in pressure bonding area between the first power supply terminal electrodes31h(first power supply terminals35h) and the second power supply terminal electrodes41h(second power supply terminals45h) caused by pressure bonding discrepancy and also reduces differences in pressure bonding area between the first power supply terminal electrodes31i(first power supply terminals35i) and the second power supply terminal electrodes41i(second power supply terminals45i) caused by pressure bonding discrepancy, without having to provide, for example, a guide member. Hence, a simple structure is capable of connecting the first power supply terminal electrodes31hand the second power supply terminal electrodes41hwith high precision and of connecting the first power supply terminal electrodes31iand the second power supply terminal electrodes41iwith high precision. That can in turn restrain display quality deterioration. (2) When a plurality of flexible printed boards40is connected to the first terminal portion Ta by pressure bonding, the power supply terminal electrodes can be connected to each other with high precision because differences in pressure bonding area are reduced that are caused by pressure bonding discrepancy between the power supply terminal electrodes on the FPCs and the first power supply terminal electrodes31hand31iin the first terminal portion Ta. That can in turn restrain display quality deterioration. (3) The first power supply terminal electrodes31hbranch off the low-voltage power supply main lines18h, and the first power supply terminal electrodes31ibranch off the high-voltage power supply main lines18i. This particular structure enables the detection of spaces between the branching, first power supply terminal electrodes31hand31i(more specifically, the first power supply openings Salt and Sai in which the branching, first power supply terminal electrodes31hand31iare exposed (first power supply terminals35hand35i)), which facilitates alignment in mounting the flexible printed board40. Second Embodiment A description is given next of a second embodiment of the disclosure.FIG.14is an enlarged plan view, equivalent toFIG.6, of a first terminal portion Ta of a frame area F of an OLED display device50bin accordance with the present embodiment.FIG.15is an enlarged plan view, equivalent toFIG.7, of a second terminal portion Tb of a flexible printed board40in the OLED display device50b.FIG.16is a schematic enlarged view, equivalent toFIG.8, of region A shown inFIG.1, depicting the first terminal portion Ta and the second terminal portion Tb in the OLED display device50b.FIG.17is a schematic cross-sectional view, taken along line XVII-XVII inFIG.16and being equivalent toFIG.9, of the first terminal portion Ta and the second terminal portion Tb in the OLED display device50b. The OLED display device50bdiffers from the first embodiment described above in the first terminal portion Ta and the second terminal portion Tb, but otherwise has the same overall configuration including, for example, the display area D and the frame area F as the first embodiment. The description of the present embodiment will focus on these differences. Members of the present embodiment that are similar to members of the first embodiment are indicated by the same reference numerals and description thereof may be omitted. As shown inFIG.14, the OLED display device50bis characterized in that there is provided a single, first power supply terminal electrode31hfor each low-voltage power supply main line18hwithout subdividing the first power supply terminal electrode31hin a plan view and also that there is provided a single, first power supply terminal electrode31ifor each high-voltage power supply main line18iwithout subdividing the first power supply terminal electrode31iin a plan view. In other words, the first power supply terminal electrodes31hand31ido not branch off the main lines18h,18i. More specifically, the first power supply terminal electrodes31hand31ihave the same line width Hb as the low-voltage power supply main lines18hand the high-voltage power supply main lines18i(seeFIG.16). Meanwhile, the second power supply terminal electrodes41hand41ihave a line width equal to Ha (seeFIG.16). The line width Hb of the first power supply terminal electrodes31hand31iis hence larger than the line width Ha of the second power supply terminal electrodes41hand41iin the OLED display device50a.FIGS.16and17show no dummy terminals33,34,43, and44.FIG.16indicates the first terminal portion Ta of the frame area F with a dotted line and the second terminal portion Tb of the flexible printed board40with a solid line. In the OLED display device50b, as shown inFIGS.14,16, and17, the first power supply terminal electrodes31hand31iare inclined from the direction in which the second power supply terminal electrodes41hand41iextend (direction X). There are provided first power supply openings Sbh and Sbi (first power supply terminals35hand35i) along the periphery of the first power supply terminal electrodes31hand31i. The first power supply terminal electrodes31hand31iare inclined in different directions from direction X in the respective end portions Eh and Ei of the first terminal portion Ta in terms of direction Y and are symmetric in the left-right direction with respect to the middle portion C of the first terminal portion Ta (in direction X), as shown inFIG.14. More specifically, the first power supply openings Sbh and Sbi (first power supply terminals35hand35i) where the first power supply terminal electrodes31hand31iare exposed are inclined from direction X. In other words, the first power supply openings Sbh and Sbi (first power supply terminals35hand35i) are shaped like a parallelogram in a plan view without being subdivided. Meanwhile, the second power supply terminal electrodes41hand41iare provided parallel to direction X as shown inFIGS.15to17. There is provided a plurality of second power supply openings Vbh and Vbi (second power supply terminals45hand45i) along the periphery of the second power supply terminal electrodes41hand41i. The plurality of second power supply openings Vbh and Vbi is provided and shaped like a rectangle in a plan view. The OLED display device50bcan be manufactured by the method of manufacturing the OLED display device50ain accordance with the first embodiment described above, with changes to the shapes into which the first power supply terminal electrodes31hand31i, the second power supply terminal electrodes41hand41i, the planarization film32, and the insulation film42are patterned. In the OLED display device50b, the first power supply terminal electrodes31hand31iare provided without being subdivided in a plan view and inclined from direction X. Alternatively, the second power supply terminal electrodes41hand41imay be provided without being subdivided in a plan view and inclined from the direction in which the first power supply terminal electrodes31hand31iextend. In the OLED display device50b, the first power supply terminal electrodes31hand31iare inclined in different directions from direction X in the respective end portions Eh and Ei of the first terminal portion Ta in terms of direction Y and are symmetric in the left-right direction with respect to the middle portion C of the first terminal portion Ta (in direction X). Alternatively, the first power supply terminal electrodes31hand31imay be inclined in the same direction from direction X and asymmetric in the left-right direction with respect to the middle portion C. The OLED display device50bdescribed here can achieve the following advantages in addition to the advantages described earlier in items (1) and (2). (4) The first power supply terminal electrodes31hand31i(first power supply terminals35hand35i) are shaped like a parallelogram in a plan view without being subdivided so that the first power supply terminal electrodes31hand31ican be wider than the second power supply terminal electrodes41hand41i(second power supply terminals45hand45i). This particular structure further reduces differences in pressure bonding area between the first power supply terminals35hand35iand the second power supply terminals45hand45icaused by pressure bonding discrepancy. Hence, a simple structure is capable of connecting the first power supply terminal electrodes31hand31iand the second power supply terminal electrodes41hand41iwith higher precision. That can in turn restrain display quality deterioration. Third Embodiment A description is given next of a third embodiment of the disclosure.FIG.18is an enlarged plan view, equivalent toFIG.6, of a first terminal portion Ta of a frame area F of an OLED display device50cin accordance with the present embodiment. The OLED display device50cdiffers from the second embodiment described above in the first terminal portion Ta, but otherwise has the same overall configuration including, for example, the display area D and the frame area F as the second embodiment. The description of the present embodiment will focus on these differences. Members of the present embodiment that are similar to members of the second embodiment are indicated by the same reference numerals and description thereof may be omitted. As shown inFIG.18, the OLED display device50cis characterized in that there is provided a plurality of first power supply openings Sch (first power supply terminals35h) (live first power supply openings Sch inFIG.18) for a plurality of second power supply terminal electrodes41h, each first power supply opening Sch being shaped like a parallelogram in a plan view, and also that there is provided a plurality of first power supply openings Sci (first power supply terminals35i) (five first power supply openings Sci inFIG.18) for a plurality of second power supply terminal electrodes41i, each first power supply opening Sci being shaped like a parallelogram in a plan view. In other words, similarly to the second embodiment above, the first power supply terminal electrodes31hand31iare wider than the second power supply terminal electrodes41hand41i. However, the plurality of first power supply openings Sch is provided with the same width as the second power supply opening Vbh, and the plurality of first power supply openings Sci is provided with the same width as the second power supply opening Vbi. The OLED display device50ccan be manufactured by the method of manufacturing the OLED display device50ain accordance with the first embodiment described above, with changes to the shapes into which the first power supply terminal electrodes31hand31i, the second power supply terminal electrodes41hand41i, the planarization film32, and the insulation film42are patterned. In the OLED display device50c, the plurality of first power supply openings Sch and Sci where the first power supply terminal electrodes31hand31i, which are not subdivided in a plan view, are exposed is provided for the plurality of second power supply terminal electrodes41hand41i. Alternatively, the second power supply terminal electrodes41hand41imay be provided without being subdivided in a plan view, so that there can be provided a plurality of second power supply openings for the plurality of first power supply terminal electrodes31hand31i, the second power supply terminal electrodes41hand41ibeing exposed in the second power supply openings. The OLED display device50cdescribed here can achieve the following advantages in addition to the advantages described earlier in items (1) and (2). (5) The plurality of first power supply openings Sch and Sci (first power supply terminals35hand35i) is provided for the plurality of second power supply terminal electrodes41hand41i. This particular structure enables the detection of spaces between the first power supply openings Sch and Sci, which facilitates alignment in mounting the flexible printed board40. Other Embodiments The embodiments have so far discussed examples where the first signal openings and the second signal openings have the same length in the longer-side direction. Alternatively, the first signal openings and the second signal openings may have different lengths. More specifically, the second signal openings may have a shorter length in the longer-side direction than do the first signal openings in the longer-side direction. The embodiments have so far discussed examples where the organic light-emitting layer has a five-layer structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Alternatively, the organic light-emitting layer may have, for example, a three-layer structure including a hole injection and transport layer, a light-emitting layer, and an electron transport and injection layer. The embodiments have so far discussed examples where the OLED display device includes the first electrodes serving as anodes and the second electrodes serving as cathodes. The disclosure is also applicable to OLED display devices in which the layer structure of the organic light-emitting layer is reversed so that the first electrodes serve as cathodes and the second electrodes serve as anodes. The embodiments have so far discussed exemplary OLED display devices where the TFT electrode connected to the first electrode serves as a drain electrode. The disclosure is also applicable to OLED display devices where the TFT electrode connected to the first electrode serves as a source electrode. The embodiments have so far discussed the OLED display device as an exemplary display device. The disclosure is also applicable to any display device including a plurality of current-driven light-emitting elements, for example, applicable to display devices including QLEDs (quantum-dot light-emitting diodes) which are light-emitting elements including a quantum dot layer. INDUSTRIAL APPLICABILITY As described above, the disclosure is useful in flexible display devices. | 64,112 |
11943979 | DETAILED DESCRIPTION In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure. Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprises,” “comprising,” “includes,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or mechanical connection, but may include an electrical connection, directly or indirectly. “On,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly. Static electricity builds up inside an array substrate, which can easily damage an internal structure of the array substrate; and it is even worse for a high-resolution display device. For example, an electrostatic protection line is provided between the array structures in two adjacent lines of an array substrate motherboard, and then bonding electrodes in bonding regions of respective array structures are extended to the electrostatic protection line, so that static electricity inside the array structures can flow to the electrostatic protection line through the bonding electrodes. Such a structure can alleviate the phenomenon of static electricity accumulation at an end portion of the bonding electrode to a certain extent. However, after the array substrate motherboard is cut into several array substrate, the electrostatic protection line is also cut off and the bonding electrode on a single array substrate extends to an edge of a bonding region, that is, an edge of the single array substrate, in this case, static electricity from the bonding electrode is prone to enter the single array substrate at the edge of the array substrate during a subsequent production and operation process, so as to aggravate damage to the internal structure of the array substrate caused by the static electricity. An embodiment of the present disclosure provides an array substrate motherboard. As illustrated inFIG.1andFIG.2, the array substrate motherboard comprises an array structure101; the array structure101includes a display region aa and a bonding region bb, the bonding region bb is located outside the display region aa. The bonding region bb is provided with a bonding electrode1, and the bonding electrode1is spaced apart from an outer edge of the bonding region bb. The bonding region bb is further provided with an electrostatic barrier line2, and the electrostatic barrier line2has one end electrically connected with the bonding electrode1, and the other end extending to the outer edge of the bonding region bb, that is, extending to an edge of the array structure101, and resistivity of the electrostatic barrier line2is larger than resistivity of the bonding electrode1. For example, the array substrate motherboard comprises a plurality of array structures. For example, after the array substrate motherboard is cut, a plurality of array substrates are obtained, and the plurality of array substrates respectively correspond to the above-described plurality of array structures101, that is, one array structure101forms one array substrate. For example, in a direction parallel to the array substrate motherboard, the bonding electrode1is spaced apart from the outer edge of the bonding region bb. For example, the bonding region bb has an outer edge and an inner edge, and the inner edge of the bonding region bb is located between the display region aa and the outer edge of the bonding region bb. Therefore, the outer edge of the bonding region bb is an edge of the bonding region bb that is close to the edge of the array structure. For example, the outer edge of the bonding region bb is flush with the edge of the array structure. As compared with the structure that the bonding electrode is directly extended to the outer edge of the bonding region, in the embodiment of the present disclosure, it is the electrostatic barrier line2that extends to the outer edge of the bonding region bb, and the resistivity of the electrostatic barrier line2is larger than that of the bonding electrode1. After the array substrate motherboard is cut into a plurality of array substrates, the electrostatic barrier line2blocks external static electricity, so as to prevent the static electricity from entering the inside of the array substrate from the edge of the array substrate, which reduces an amount of static electricity inside the array substrate, and facilitates alleviating damage to the internal structure of the array substrate caused by the static electricity. In addition, in the structure that the bonding electrode is directly extended to the outer edge of the bonding region, when static electricity is generated inside the array structure, the static electricity is easier to accumulate at an end portion of a line or an element, for example, accumulate at an end portion of the bonding electrode. According to the embodiment of the present disclosure, the electrostatic barrier line2extends to the outer edge of the bonding region bb, such that the electrostatic barrier line2can disperse the static electricity generated inside the array structure101, to effectively prevent the static electricity from accumulating at the end portion of the bonding electrode1, which thus can reduce a risk of damage to the internal structure of the array substrate101caused by the static electricity. For example, as a possible design, referring toFIG.1, a plurality of bonding electrodes1are provided in a bonding region bb of each array structure101, and accordingly, a plurality of electrostatic barrier lines2are provided. The plurality of bonding electrodes1are electrically connected with the plurality of electrostatic barrier lines2in a one-to-one manner, that is, each of the bonding electrodes1is protected by an electrostatic barrier line2. In this way, the electrostatic barrier line2can more completely prevents external static electricity from entering the array structure101, and simultaneously disperse static electricity on each bonding electrode1. Further, as illustrated inFIG.1andFIG.2, the array substrate motherboard further comprises an electrostatic protection line3, the electrostatic protection line3is provided between the plurality of array structures101, in this case, the electrostatic barrier line2is electrically connected with the electrostatic protection line3, so that the static electricity generated inside the array structure101can be further dispersed into the electrostatic protection line3. For example, the electrostatic protection line3is set to be spaced apart from each array structure101in the direction parallel to the array substrate motherboard, so that the array structure101is not damaged during a subsequent process of cutting off the electrostatic protection line3. For example, as illustrated inFIG.1, the plurality of array structures101on the array substrate motherboard are arranged in at least two lines (the “line” described herein may be a row, or may be a column). For example, a line direction of each line of array substrate is parallel to a length direction of the electrostatic protection line3. For example, an electrostatic protection line3is provided corresponding to two lines of the array structures101, and bonding regions bb of the array structures101in two lines of array structures101corresponding to the electrostatic protection line3are opposite to each other (that is, the bonding regions bb of the array structures101in each line of array structure101are arranged at a side close to the electrostatic protection line3). For example, the electrostatic protection line3is provided between the two lines of the corresponding array structures101and electrically connected with electrostatic barrier lines2of each array structure in the corresponding two lines of array structures101. With such a design, electrostatic barrier lines2of respective array structures101are electrically connected with a same electrostatic protection line3, so that electrostatic barrier lines2of respective array structures101can implement mutual charge circulation through a same electrostatic protection line3, which facilitates dispersion of static electricity more. For example, as illustrated inFIG.2, an electrostatic protection line3is provided corresponding to one line of array structures101; a bonding region bb of each array structure in the one line of array structures101is provided at a side close to the electrostatic protection line3; and the electrostatic protection line3is electrically connected with electrostatic barrier lines2of each array substrate in the corresponding one line of array structures101. For example, as illustrated inFIG.8andFIG.9, electrostatic barrier lines2of one array structure101on the array substrate motherboard are configured to be electrically connected with electrostatic barrier lines2of another array structure101, so that charge circulation is implemented between different array structures101through the electrostatic barrier lines2, which facilitates dispersion of static electricity. In this case, the electrostatic protection line3may not be provided. Further, for example, a plurality of electrostatic barrier lines2of one array structure101on the array substrate motherboard are configured to be electrically connected with a plurality of electrostatic barrier lines2of another array structure101in a one-to-one manner. For example, with reference toFIG.9again, the plurality of array structures101are arranged in at least two lines and include a first line of array structures (e.g., an upper line of array structures as illustrated in the diagram) and a second line of array structures (e.g., a lower line of array structures as illustrated in the diagram) adjacent to each other. A bonding region bb of each array structure in the first line of array structures is provided at a side close to the second line of array structures, and a bonding region bb of each array structure in the second line of array structures is provided at a side close to the first line of array structures. Bonding regions bb of the first line of array structures are electrically connected with bonding regions bb of the second line of array structures in a one-to-one manner through same electrostatic barrier lines2. In this way, charge circulation can be implemented between the first line of array structures and the second line of array structures through the electrostatic barrier lines2, which facilitates dispersion of static electricity. As illustrated inFIG.3, the array substrate motherboard comprises: a base substrate100, a buffer layer7, an active layer9, a gate insulating layer6, a gate metal layer, an interlayer insulating layer8and a source/drain metal layer. The gate metal layer comprises a gate electrode10, and the source/drain metal layer comprises a source electrode11and a drain electrode12. The gate electrode10is located on a side of the active layer9that faces away from the base substrate100, and such a structure is referred to as a “top gate” structure. It should be noted that, in the embodiment of the present disclosure, it is described with the “top gate” structure as an example, but this does not constitute a limitation to the technical solution provided by the present disclosure. In other embodiment of the present disclosure, an array substrate motherboard may also have a “bottom gate” structure or other structure. In the “bottom gate” structure, a gate electrode10is located on a side of an active layer9that is close to a base substrate100. For example, the source electrode11, the drain electrode12, the active layer9and the gate electrode10together constitute a thin film transistor, and the thin film transistor may be located in the display region aa, as illustrated inFIG.3. For example, as illustrated inFIG.3,FIG.4,FIG.5,FIG.6aandFIG.6b, the electrostatic barrier line2may be provided in a same layer as the active layer9, to facilitate simplification of process steps, and the electrostatic barrier line2and the active layer9may be made of a same material, that is, a semiconductor material, so that the resistivity of the electrostatic barrier line2is larger than the resistivity of the bonding electrode1made of a metal material. Exemplarily, the above-described electrostatic barrier line2may be made of doped polysilicon. For example, the above-described electrostatic barrier line2may be made of doped low-temperature polysilicon. For example, in the embodiment of the present disclosure, that an A component is provided in a same layer as a B component refers to that: in a direction perpendicular to the base substrate, there is no other layer or structure between the A component and the B component. For example, in the embodiment of the present disclosure, that the A component and the B component are provided in a same layer and made of a same material refers to that: the A component and the B component are simultaneously formed by performing a same patterning process on a same thin film, so that in the direction perpendicular to the base substrate, there is no other layer or structure between the A component and the B component, and the A component and the B component are made of a material exactly the same. For example, as illustrated inFIG.3andFIG.4, the bonding electrode1and the electrostatic protection line3may both be provided in the gate metal layer; the bonding electrode1may be electrically connected with the electrostatic barrier line2through a first via hole4provided in the gate insulating layer6, and the electrostatic barrier line2may be electrically connected with the electrostatic protection line3through a second via hole5provided in the gate insulating layer6. For example, as illustrated inFIG.3andFIG.5, the bonding electrode1and the electrostatic protection line3may both be provided in the source/drain metal layer; the first via hole4and the second via hole5are provided in the gate insulating layer6and the interlayer insulating layer8; the bonding electrode1may be electrically connected with the electrostatic barrier line2through the first via hole4; and the electrostatic protection line3may be electrically connected with the electrostatic barrier line2through the second via hole5. For example, as illustrated inFIG.3andFIG.6a, the bonding electrode1may be provided in the source/drain metal layer, the electrostatic protection line3may be provided in the gate metal layer; the second via hole5is provided in the gate insulating layer6, the first via hole4is provided in the gate insulating layer6and the interlayer insulating layer8; the bonding electrode1is electrically connected with the electrostatic barrier line2through the first via hole4, and the electrostatic protection line3is electrically connected with the electrostatic barrier line2through the second via hole5. For example, as illustrated inFIG.3andFIG.6b, the bonding electrode1may be provided in the gate metal layer, the electrostatic protection line3may be provided in the source/drain metal layer; the first via hole4is provided in the gate insulating layer6, the second via hole5is provided in the gate insulating layer6and the interlayer insulating layer8; the bonding electrode1is electrically connected with the electrostatic barrier line2through the first via hole4, and the electrostatic protection line3is electrically connected with the electrostatic barrier line2through the second via hole5. The above-described arrangements of the bonding electrode1, the electrostatic barrier line2and the electrostatic protection line3are compatible with a preparation process of a specific structure in the array substrate motherboard, thus it is not necessary to additionally increase processes for preparing the bonding electrode1, the electrostatic barrier line2and the electrostatic protection line3, which simplifies the process steps. For example, the electrostatic barrier line2may be a fold line, a curved line or a straight line, alternatively, the electrostatic barrier line2may be a combination of at least two of a fold line, a curved line and a straight line. Exemplarily, as illustrated inFIG.7andFIG.8, the electrostatic barrier line2is a fold line, so that a resistance value of the electrostatic barrier line2is increased by extending a length of the electrostatic barrier line2, which, thus, can further alleviate damage to the internal structure of the array substrate101caused by static electricity. In addition, it should be noted that, the array substrate motherboard according to the embodiment of the present disclosure is applicable to an organic light emitting diode (OLED) display device, accordingly, as illustrated inFIG.3, the array substrate motherboard further comprises: a passivation layer13, an anode16, a pixel defining layer15, an organic light-emitting layer17and a cathode18. The anode16is connected to the drain electrode12through a via hole provided in the passivation layer13. In another embodiment of the present disclosure, there is provided a fabrication method of an array substrate motherboard, as illustrated inFIG.10toFIG.14b. For example, the array substrate motherboard comprises a plurality of array structures101, each array structure101comprises a display region aa and a bonding region bb; the bonding region bb is provided with a bonding electrode1, and the bonding electrode1is spaced apart from an outer edge of the bonding region bb. The fabrication method comprises: fabricating an electrostatic barrier line2in the bonding region bb, herein, the electrostatic barrier line2has one end electrically connected with the bonding electrode1, and the other end extending to the outer edge of the bonding region bb, and resistivity of the electrostatic barrier line2is larger than resistivity of the bonding electrode1. The electrostatic barrier line2can block external static electricity, and disperse static electricity on the bonding electrode1to a certain extent, which, thus, can alleviate damage to the internal structure of the array substrate101caused by the static electricity and alleviate damage to an internal structure of an array substrate caused by the static electricity while the array substrate is obtained by cutting the array substrate motherboard. For example, the fabrication method of the array substrate motherboard may comprise steps of: Step S1: as illustrated inFIG.10, forming a semiconductor thin film14on a base substrate100. For example, in the case that the semiconductor thin film14is made of polysilicon, the above-described step S1may be, for example, a process of: depositing an amorphous silicon thin film on the base substrate100; and irradiating the amorphous silicon thin film with laser, to crystallize the amorphous silicon thin film, and obtain the semiconductor thin film14made of polysilicon. For example, before the above-described step S1, the method may further comprise: forming a buffer layer7on the base substrate100, such that impurities in the base substrate100are prevented from diffusing and entering the semiconductor thin film14by the buffer layer7. Step S2: as illustrated inFIG.11aandFIG.11b, patterning the above-described semiconductor thin film14, to form an active layer9and the electrostatic barrier line2. Step S3: performing ion implantation on a source region and a drain region of the active layer9as well as the electrostatic barrier line2, to improve electrical conductivity of the source region and the drain region of the active layer9as well as the electrostatic barrier line2. For example, the source region and the drain region of the active layer9as well as the electrostatic barrier line2become electrically conductive by ion implantation. In the above-described step S3, ion implantation may be performed in one of two modes below: Mode One: as illustrated inFIG.12aandFIG.12b, forming a gate insulating layer6on a side of the active layer9facing away from the base substrate100and the electrostatic barrier line2that faces away from the base substrate100; forming a gate metal layer on a side of the gate insulating layer6that faces away from the base substrate100; patterning the above-described gate metal layer to form a gate electrode10; performing ion implantation on the source region and the drain region of the active layer9by using the gate electrode10as a mask, in which process, the electrostatic barrier line2is simultaneously ion-implanted, because no gate electrode10is disposed above the electrostatic barrier line2. As illustrated inFIG.13aandFIG.13b, after ion implantation, the electrically conductive source region and drain region of the active layer9as well as the electrically conductive electrostatic barrier line2are obtained. In the above-described Mode One, ion implantation is performed directly by using the gate electrode10as a mask, so that a step of additionally preparing a mask for ion implantation may be omitted, which saves a photoetching process, and achieves an effect of simplifying the process steps. In addition, in the step of patterning the gate metal layer, an electrostatic protection line may be further formed; the electrostatic protection line is provided between the plurality of array structures101; and the electrostatic barrier line2is electrically connected with the electrostatic protection line, so that a dispersion effect on static electricity is enhanced by the electrostatic protection line without additional process steps. It should be noted that, the above-described Mode One is applicable to preparation of the array substrate motherboard of the “top gate” structure. Mode Two: forming a photoresist layer on the side of the active layer9and the electrostatic barrier line2that faces away from the base substrate100; patterning the photoresist layer, reserving the photoresist in a region between the source region and the drain region of the active layer9, and making the source region and the drain region of the active layer9as well as the electrostatic barrier line2no longer covered by the photoresist so as to be exposed; performing ion implantation on the source region and the drain region of the active layer9as well as the electrostatic barrier line2by using a patterned photoresist layer as a mask, so that the source region and the drain region of the active layer9as well as the electrostatic barrier line2have electrical conductivity. It should be noted that, the above-described Mode Two in which ion implantation is performed by directly forming the photoresist layer is applicable to preparation of the array substrate motherboard of the “bottom gate” structure, the “top gate” structure, or any other structure. For example, the fabrication method may further comprise a step of preparing a source/drain metal layer. The bonding electrode and the electrostatic protection line may be formed in a same process step as the source/drain metal layer according to actual design requirements. Exemplarily, as illustrated inFIG.14aandFIG.14b, the fabrication method may further comprise: forming an interlayer insulating layer8on a side of the gate electrode10that faces away from the base substrate100; forming the source/drain metal layer on a side of the interlayer insulating layer8that faces away from the base substrate100; and patterning the source/drain metal layer to form a source electrode11, a drain electrode12and the bonding electrode1. The source electrode11is electrically connected with the source region of the active layer9through a via hole; the drain electrode12is electrically connected with the drain region of the active layer9through a via hole; and the bonding electrode1is electrically connected with a corresponding electrostatic barrier line2through a first via hole4. Moreover, an electrostatic protection line is further formed, for example, in the above-described process of patterning the source/drain metal layer. The electrostatic protection line is electrically connected with the electrostatic barrier line2through a second via hole. It should be noted that, in the embodiment of the present disclosure,FIG.11a,FIG.12a,FIG.13aandFIG.14aare cross-section structural views of the display region aa of the above-described array structure101, andFIG.11b,FIG.12b,FIG.13bandFIG.14bare cross-section structural views of the bonding region bb of the above-described array structure101. With reference toFIG.15, another embodiment of the present disclosure provides an array substrate, the array substrate comprises a display region aa and a bonding region bb, herein, the bonding region bb is provided with a bonding electrode1, the bonding electrode1is spaced apart from an outer edge of the bonding region bb, the bonding region bb is further provided with an electrostatic barrier line2, the electrostatic barrier line2has one end electrically connected with the bonding electrode1, and the other end extending to the outer edge of the bonding region bb, and resistivity of the electrostatic barrier line2is larger than resistivity of the bonding electrode1. Due to a blocking effect of the electrostatic barrier line2on external static electricity and a dispersion effect of the electrostatic barrier line2on internal static electricity, the problem of damage to the array substrate caused by the static electricity is solved. For example, in a direction parallel to the array substrate, the bonding electrode1is spaced apart from the outer edge of the bonding region bb. For example, the bonding region bb has the outer edge and an inner edge, and the inner edge of the bonding region bb is located between the display region aa and the outer edge of the bonding region bb. Therefore, the outer edge of the bonding region bb is an edge of the bonding region bb that is close to the edge of the array substrate. For example, the outer edge of the bonding region bb is flush with the edge of the array substrate. For example, there are a plurality of bonding electrodes1and a plurality of electrostatic barrier lines2, and the plurality of bonding electrodes1are electrically connected with the plurality of electrostatic barrier lines2in a one-to-one manner. For example, as illustrated inFIG.3, the above-described array substrate may comprise: a base substrate100, a buffer layer7, an active layer9, a gate insulating layer6, a gate metal layer, an interlayer insulating layer8and a source/drain metal layer; the gate metal layer comprising a gate electrode10, and the source/drain metal layer comprising a source electrode11and a drain electrode12. As illustrated inFIG.3,FIG.4,FIG.5andFIG.6, the electrostatic barrier line2may be provided in a same layer as the active layer9, to facilitate simplification of process steps, and the electrostatic barrier line2and the active layer9are made of a same material, that is, a semiconductor material, so that the resistivity of the electrostatic barrier line2is larger than the resistivity of the bonding electrode1made of a metal material. Exemplarily, the above-described electrostatic barrier line2may be made of doped polysilicon. Exemplarily, the above-described electrostatic barrier line2may be made of doped low-temperature polysilicon. In the structure illustrated inFIG.3, the gate electrode10is located on a side of the active layer9that faces away from the base substrate100, and such a structure is referred to as a “top gate” structure. Based on the structure and as illustrated inFIG.4, the bonding electrode1may be provided in the gate metal layer, the first via hole4is provided in the gate insulating layer6, and the bonding electrode1is electrically connected with the electrostatic barrier line2through the first via hole4. For example, with reference toFIG.5, the bonding electrode1may be provided in the source/drain metal layer, the first via hole4is provided in the gate insulating layer6and the interlayer insulating layer8, and the bonding electrode1is electrically connected with the electrostatic barrier line2through the first via hole4. It should be noted that, a position of the bonding electrode1and a connection structure between the bonding electrode1and the electrostatic barrier line2are introduced above merely with a case where the array structure101has the “top gate” structure as an example; with respect to the array structure101having a “bottom gate” structure, the bonding electrode1may also be provided in the gate metal layer or the source/drain metal layer, and no details will be repeated here. For example, the electrostatic barrier line2may be a fold line, a curved line and a straight line, alternatively, it may be a combination of at least two of a fold line, a curved line and a straight line. Exemplarily, as illustrated inFIG.7andFIG.8, the electrostatic barrier line2is a fold line, so that a resistance value of the electrostatic barrier line2is increased by extending a length of the electrostatic barrier line2, which, thus, may further alleviate damage to the internal structure of the array substrate caused by static electricity. It should be noted that, the array substrate provided by the embodiment of the present disclosure is obtained by cutting the array substrate motherboard along a cutting line. Exemplarily, with reference toFIG.1, after the array substrate motherboard is cut along a cutting line19, a plurality of array substrates as illustrated inFIG.15can be obtained. For example, after the cutting, the electrostatic protection line3on the array substrate motherboard is cut off, so the electrostatic protection line3is not present on the array substrate obtained. In still another embodiment of the present disclosure, there is further provided a display device, the display device comprising the display panel provided by the embodiment of the present disclosure. As described above, the display panel comprises the array substrate provided by the embodiment of the present disclosure, so the display device that comprises the display panel also has same advantageous effects as the array substrate described above. In still another embodiment of the present disclosure, there is further provided a display device, the display device comprising the array substrate provided by the embodiment of the present disclosure. As described above, the display device comprises the array substrate provided by the embodiment of the present disclosure, so the display device also has same advantageous effects as the array substrate described above. The display device according to the embodiment of the present disclosure may be a display panel, a mobile phone, a tablet personal computer, a television, a monitor, a laptop, a digital photo frame, a navigator, and any other product or component having a display function. For specific details of the fabrication method of the array substrate, the fabrication method of the array substrate motherboard as described above may be referred to, and no details will be repeated here. For example, after fabrication of the array substrate motherboard is completed, the array substrate according to the embodiment of the present disclosure may be obtained by just cutting the array substrate motherboard. For example, one array structure of the array substrate motherboard is used to form one array substrate. What is described above is related to the illustrative embodiments of the disclosure only and not limitative to the scope of the disclosure; the scopes of the disclosure are defined by the accompanying claims. | 32,670 |
11943980 | DETAILED DESCRIPTION The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. As used herein, a reference number may indicate a singular element or a plurality of the element. For example, a reference number labeling a singular form of an element within the drawing figures may be used to reference a plurality of the singular element within the text of specification It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can, therefore, encompass both an orientation of above and below. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims. Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. FIGS.1and2are plan views illustrating embodiments of a display device10.FIGS.3and4are cross-sectional views illustrating the display device10ofFIG.1.FIG.5is a cross-sectional view taken along line I-I′ ofFIG.1. In an embodiment, for example,FIG.4may illustrate a bent configuration of the display device10ofFIG.3. Referring toFIGS.1to5, a display device10may include a display panel100, a circuit board200, a driving circuit chip300, and a lower film. The display panel100may generate or display images. The display panel100may include a plurality of pixels for generating the image. Light emitted from each of the pixels may be combined to generate or display images. The display panel100may provide the generated image toward an upper surface of the display device10(e.g., a display surface). In an embodiment, the display panel100may include (or, may have) a first area1A, a second area2A, and a bending area BA. In an embodiment, for example, the second area2A may be spaced apart from the first area1A in a first direction DR1. The pixels may be disposed in the first area1A, and a pad part may be disposed in the second area2A. In an embodiment, for example, the first area1A may be referred to as a display area, and the second area2A may be referred to as a pad area. The first area1A, the bending area BA and the second area2A may be in order along the first direction DR1. The bending area BA may be positioned between the first area1A and the second area2A. The bending area BA may be bendable to be bent along a bending axis extending in a second direction DR2crossing the first direction DR1. In an embodiment, for example, the second direction DR2may be perpendicular to the first direction DR1. In an embodiment, as illustrated inFIG.1, the first area1A, the bending area BA, and the second area2A may have substantially the same width in the second direction DR2. That is, the display panel100may have an overall rectangular shape in a plan view. The display device10(or the display panel100) which is flat or unbent, may be disposed in a plane defined by the first direction DR1and the second direction DR2which cross each other. Various components or layers of the display device10may have a first area1A, a second area2A, and a bending area BA corresponding to those described above. In an embodiment, as illustrated inFIG.2, each of a width of the bending area BA and a width of the second area2A in the second direction DR2may be less than a width of the first area1A in the second direction DR2. In an embodiment, for example, a width of the display panel100may be narrowed in a portion of the first area1A adjacent to the bending area BA (e.g., a portion which is closest to the bending area BA). In an embodiment, for example, the width of the bending area BA in the second direction DR2may be substantially the same as the width of the second area2A in the second direction DR2. In an embodiment, the display panel100may include a substrate110, a transistor TR, a light emitting element150, an encapsulation layer160, a first pad part170, and a second pad part180. The transistor TR and the light emitting element150may be disposed in the first area1A, on the substrate110. The first pad part170and the second pad part180may be disposed in the second area2A, on the substrate110. The substrate110may be a flexible and insulating substrate. In an embodiment, for example, the substrate110may include (or, may be) a transparent resin substrate. In an embodiment, for example, the substrate110may include a polyimide substrate. In this case, the substrate110may have a multi-layered structure in which one or more polyimide layer and one or more barrier layer are alternately stacked. An active layer120may be disposed on the substrate110. The active layer120may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. In an embodiment, for example, the oxide semiconductor may include at least one oxide of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include an amorphous silicon, a polycrystalline silicon, or the like, but embodiments are not limited thereto. The active layer120may include a source area, a drain area, and a channel area which is positioned between the source area and the drain area. In an embodiment, a buffer layer (not shown) may be disposed between the substrate110and the active layer120. The buffer layer may prevent or reduce instances of impurities diffusing into the active layer120from the substrate110. The buffer layer may include an inorganic insulating material such as a silicon compound, a metal oxide, or the like. Examples of the inorganic insulating material may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), or the like, but embodiments are not limited thereto. These can be used alone or in a combination thereof. The buffer layer may have a single-layered structure or a multi-layered structure including a plurality of insulating layers. A first insulating layer111may be disposed on the active layer120. The first insulating layer111may cover the active layer120on the substrate110. The first insulating layer111may include an inorganic insulating material. A gate electrode130may be disposed on the first insulating layer111. The gate electrode130may overlap (or correspond to) the channel area of the active layer120. The gate electrode130may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. Examples of the conductive material may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), or the like, but embodiments are not limited thereto. These can be used alone or in a combination thereof. The gate electrode130may have a single-layered structure or a multi-layered structure including a plurality of conductive layers. A second insulating layer112may be disposed on the gate electrode130. The second insulating layer112may cover the gate electrode130on the first insulating layer111. The second insulating layer112may include an inorganic insulating material. A source electrode141and a drain electrode142may be disposed on the second insulating layer112. The source electrode141and the drain electrode142may be connected to the source area and the drain area of the active layer120, respectively. Each of the source electrode141and the drain electrode142may include a conductive material. In an embodiment, for example, each of the source electrode141and the drain electrode142may have a multi-layered structure of Ti/Al/Ti. The active layer120, the gate electrode130, the source electrode141, and the drain electrode142may together form the transistor TR. A third insulating layer113may be disposed on the source electrode141and the drain electrode142. The third insulating layer113may include an organic insulating material. Examples of the organic insulating material may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, an epoxy-based resin, or the like, but embodiments are not limited thereto. These can be used alone or in a combination thereof. In an embodiment, the third insulating layer113may have a multi-layered structure including at least one organic insulating layer and at least one inorganic insulating layer. A pixel electrode151may be disposed on the third insulating layer113. The pixel electrode151may include a conductive material. The pixel electrode151may be connected to the drain electrode142through a contact hole formed (or defined) in the third insulating layer113. Accordingly, the pixel electrode151may be electrically connected to the transistor TR. A fourth insulating layer114may be disposed on the pixel electrode151. The fourth insulating layer114may cover a peripheral portion of the pixel electrode151, and may define a pixel opening exposing a central portion of the pixel electrode151. The fourth insulating layer114may include an organic insulating material. An emission layer152may be disposed on the pixel electrode151. The emission layer152may be disposed in the pixel opening of the fourth insulating layer114. In some embodiments, the emission layer152may include at least one of an organic light emitting material or quantum dot. In an embodiment, the organic light emitting material may include a low molecular organic compound or a high molecular organic compound. Examples of the low molecular organic compound may include copper phthalocyanine, N,N′-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, or the like. Examples of the high molecular organic compound may include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, or the like. These can be used alone or in a combination thereof. In an embodiment, the quantum dot may include a core including a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, and/or a Group IV compound. In an embodiment, the quantum dot may have a core-shell structure including the core and a shell surrounding the core. The shell may serve as a protection layer for preventing the core from being chemically denatured to maintain semiconductor characteristics, and may serve as a charging layer for imparting electrophoretic characteristics to the quantum dot. A counter electrode153may be disposed on the emission layer152. The counter electrode153may also be disposed on the fourth insulating layer114. The counter electrode153may include a conductive material. The pixel electrode151, the emission layer152, and the counter electrode153may together form the light emitting element150. An encapsulation layer160may be disposed on the counter electrode153. The encapsulation layer160may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer160may include a first inorganic encapsulation layer161disposed on the counter electrode153, an organic encapsulation layer162disposed on the first inorganic encapsulation layer161, and a second inorganic encapsulation layer163disposed on the organic encapsulation layer162. In an embodiment, a first end portion of the circuit board200may be connected to an end portion (e.g., an end portion in the first direction DR1or distal end) of the display panel100. In an embodiment, for example, the circuit board200may be attached to the display panel100by a first conductive film410, and may be electrically connected to the first pad part170of the display panel100by the first conductive film410. This will be described later in detail. The circuit board200may be a flexible printed circuit board (FPCB). A printed circuit board (PCB) (not illustrated) may be attached on a second end portion of the circuit board200which is opposite to the first end portion. In an embodiment, the driving circuit chip300may be disposed in the second area2A, on the display panel100, to be spaced apart from the circuit board200. In an embodiment, for example, the driving circuit chip300may be disposed in the second area2A, on the display panel100, to be spaced apart from the circuit board200in a direction opposite to the first direction DR1. That is, the driving circuit chip300may be directly mounted on the display panel100in a chip on plastic (COP) method. In an embodiment, for example, the driving circuit chip300may be attached on the display panel100by a second conductive film420, and may be electrically connected to the second pad part180of the display panel100by the second conductive film420. This will be described later in detail. In an embodiment, the driving circuit chip300may be mounted on the circuit board200connected to the display panel100, in a chip on film (COF) method. The circuit board200, the driving circuit chip300, and the PCB may provide a driving signal to the display panel100. The driving signal may include various signals (e.g., electrical signals) for driving the display panel100such as driving voltage, a gate signal, a data signal, or the like. The lower film may be disposed under the display panel100(e.g., the substrate110) to protect the display panel100from external impact. The lower film may be attached to a lower surface of the display panel100(e.g., the substrate110) by an adhesive layer. The lower film may be attached to the display panel100at a lower surface of the substrate110, without being limited thereto. In an embodiment, the lower film may include a first lower film610and a second lower film620that are spaced apart from each other (e.g., disconnected from each other at the bending area BA). The first lower film610may be attached to the lower surface of the display panel100to correspond to the first area1A. The second lower film620may be attached to the lower surface of the display panel100to correspond to the second area2A. That is, the second lower film620may be spaced apart from the first lower film610in the first direction DR1with the bending area BA interposed therebetween. The first lower film610and the second lower film620may include a substantially same material. In an embodiment, for example, each of the first lower film610and the second lower film620may include a polymer material. Examples of the polymer material may include polyethylene terephthalate (PET), polyethylene naphthalene (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), polycarbonate oxide (PCO), modified polyphenylene oxide (MPPO), or the like, but embodiments are not limited thereto. These can be used alone or in a combination thereof. The first lower film610may be attached to the lower surface of the display panel100by a first adhesive layer510, and the second lower film620may be attached to the lower surface of the display panel100by a second adhesive layer520. That is, the first adhesive layer510may be disposed between the display panel100and the first lower film610, and may correspond to the first area1A. The second adhesive layer520may be disposed between the display panel100and the second lower film620, and may correspond to the second area2A. The second adhesive layer520may be spaced apart from the first adhesive layer510(e.g., disconnected from the first adhesive layer510) in the first direction DR1with the bending area BA interposed therebetween. The first adhesive layer510and the second adhesive layer520may include a substantially same material. In an embodiment, for example, each of the first adhesive layer510and the second adhesive layer520may include (or, may be) a pressure sensitive adhesive (PSA), an optical clear adhesive (OCA), an optical clear resin (OCR), or the like. In an embodiment, the first adhesive layer510may have a first thickness T1, and the second adhesive layer520may have a second thickness T2which is less than the first thickness T1. In an embodiment, for example, the first thickness T1may mean an average thickness of the first adhesive layer510, and the second thickness T2may mean an average thickness of the second adhesive layer520. In an embodiment, the second adhesive layer520may have a substantially uniform thickness. The second lower film620may include (or, may have) a first side surface620aadjacent to (or closest to) the first lower film610and a second side surface620bwhich is opposite to the first side surface620a. The second adhesive layer520may include (or, may have) a first side surface520aadjacent to or closest to the first adhesive layer510and a second side surface520bwhich is opposite to the first side surface520a. In an embodiment, as illustrated inFIG.3, the first side surface520aof the second adhesive layer520may protrude from the first side surface620aof the second lower film620in the direction opposite to the first direction DR1(e.g., toward the first adhesive layer510), to dispose the first side surface520aof the second adhesive520spaced apart from the first side surface620aof the second lower film620. The second adhesive layer520may protrude further from the first side surface620aof the second lower film620, to define a protruded portion or protrusion of the second adhesive layer520. The first side surface520aof the second adhesive layer520may be curved. In contrast, the second side surface520bof the second adhesive layer520may be aligned with (or coplanar with) the second side surface620bof the second lower film620. The second side surface520bof the second adhesive layer520may be flat. In an embodiment, the second side surface520bof the second adhesive layer520may protrude from the second side surface620bof the second lower film620in the first direction DR1. The second side surface520bof the second adhesive layer520may be curved. FIG.6is an enlarged cross-sectional view of area ‘A’ ofFIG.3.FIG.7is a cross-sectional view taken along line ofFIG.1. Referring toFIGS.1,3,6, and7, in an embodiment, the first pad part170disposed in the second area2A on the substrate110may include a first pad electrode172provided in plural including a plurality of first pad electrodes172arranged in the second direction DR2. In an embodiment, for example, each of the first pad electrodes172may be disposed in a same layer as the source electrode141and the drain electrode142. As used herein, elements which are in a same layer as each other may be respective patterns of a same material layer on the substrate110, without being limited thereto. In an embodiment, for example, each of the first pad electrodes172may have a multi-layered structure of Ti/Al/Ti. The circuit board200may include a first base substrate210and a lead part220. The lead part220may include a lead terminal222provided in plural including a plurality of lead terminals222arranged in the second direction DR2. The circuit board200may be attached to the display panel100such that the lead part220overlaps the first pad part170. The first conductive film410may be disposed between the display panel100and the circuit board200. The first conductive film410may include a film layer412and a plurality of conductive balls414. In an embodiment, for example, the first conductive film410may be an anisotropic conductive film (ACF). The first pad part170of the display panel100and the lead part220of the circuit board200may be electrically connected to each other by the first conductive film410. In an embodiment, for example, the first pad electrodes172may be electrically connected to the corresponding ones of the lead terminals222by the conductive balls414, respectively. In an embodiment, the second adhesive layer520may have a substantially uniform thickness. In an embodiment, for example, as illustrated inFIG.7, a thickness T2aof a first portion of the second adhesive layer520overlapping each of the first pad electrodes172may be substantially the same as a thickness T2bof a second portion of the second adhesive layer520overlapping a first opening OP1between two adjacent first pad electrodes172. FIG.8is an enlarged cross-sectional view of area ‘B’ ofFIG.3.FIG.9is a cross-sectional view taken along line ofFIG.1. Referring toFIGS.1,3,8, and9, in an embodiment, the second pad part180disposed in the second area2A, on the substrate110, may include a second pad electrode182provided in plural including a plurality of second pad electrodes182arranged in the second direction DR2. The second pad part180may be spaced apart from the first pad part170in the direction opposite to the first direction DR1. In an embodiment, for example, each of the second pad electrodes182may be disposed in a same layer as the source electrode141and the drain electrode142. In an embodiment, for example, each of the second pad electrodes182may have a multi-layered structure of Ti/Al/Ti. The driving circuit chip300may include a second base substrate310and a bump part320. The bump part320may include a bump electrode322provided in plural including a plurality of bump electrodes322arranged in the second direction DR2. The driving circuit chip300may be attached to the display panel100such that the bump part320overlaps the second pad part180. The second conductive film420may be disposed between the display panel100and the driving circuit chip300. The second conductive film420may include a film layer422and a plurality of conductive balls424. In an embedment, for example, the second conductive film420may have substantially the same configuration as the first conductive film410. The second pad part180and the bump part320may be electrically connected to each other by the second conductive film420. In an embodiment, for example, the second pad electrodes182may be electrically connected to the corresponding ones of the bump electrodes322by the conductive balls424, respectively. In an embodiment, the second adhesive layer520may have a substantially uniform thickness. In an embodiment, for example, as illustrated inFIG.9, a thickness T2cof a third portion of the second adhesive layer520overlapping each of the second pad electrodes182may be substantially the same as a thickness T2dof a fourth portion of the second adhesive layer520overlapping a second opening OP2between two adjacent second pad electrodes182. In an embodiment, for example, the thickness T2aof the first portion of the second adhesive layer520, the thickness T2bof the second portion of the second adhesive layer520, the thickness T2cof the third portion of the second adhesive layer520, and the thickness T2dof the fourth portion of the second adhesive layer520may be substantially the same. Accordingly, a connection failure between the first pad part170and the lead part220due to a massing of the conductive balls414or a connection failure between the second pad part180and the bump part320due to a massing of the conductive balls424may be prevented or reduced. Accordingly, a reliability of the display device10may be improved. FIGS.10to15are cross-sectional views illustrating an embodiment of a method of manufacturing (or providing) the display device10ofFIG.1. Referring toFIG.10, a display module20including the display panel100, the first adhesive layer510, the second adhesive layer520, the first lower film610, and the second lower film620may be prepared. In an embodiment, for example, the display module20may be a semi-finished product of the display device10. The display panel100, the first adhesive layer510, the second adhesive layer520, the first lower film610, and the second lower film620may be the same as or similar to those described with reference toFIGS.1to9, therefore, repeated descriptions will be omitted or simplified. In an embodiment, the display module20may further include a third lower film630and a third adhesive layer530. The third lower film630may be commonly attached to a lower surface of the first lower film610and a lower surface of the second lower film620by the third adhesive layer530to correspond to an entirety of the first area1A, the second area2A, and the bending area BA. The third lower film630may protect the display panel100from an external impact during a process of manufacturing or providing the display device10, or may maintain a shape of the display module20. As will be described later, the third lower film630and the third adhesive layer530may be separated from the first lower film610and the second lower film620before the display panel100is bent. That is, the third lower film630and the third adhesive layer530are removably attached to the first lower film610and the second lower film620. The first adhesive layer510and the second adhesive layer520may include a substantially same material. The first adhesive layer510may have a first thickness T1. The second adhesive layer520may have a thickness T2′ (e.g., preliminary thickness) that is substantially the same as the first thickness T1. Referring toFIGS.10and11, the second area2A of the display module20may be pre-pressed using a pressing device810. The pre-pressing step (e.g., a first pressing step) may be a pressing step for pre-deforming the second adhesive layer520(e.g., deform the second adhesive layer520) before a main-pressing step (e.g., second and third pressing steps) for electrically connecting the circuit board200and the driving circuit chip300to the display panel100(inFIG.13). As described above with reference toFIGS.6to9, the first pad part170and the lead part220may be electrically connected to each other by the first conductive film410, and the second pad part180and the bump part320may be electrically connected to each other by the second conductive film420. In an embodiment, for example, the first pad electrodes172may be electrically connected to the corresponding ones of the lead terminals222by the conductive balls414, respectively. The second pad electrodes182may be electrically connected to the corresponding ones of the bump electrodes322by the conductive balls424, respectively. In this case, when each of the first pad electrodes172and each of the second pad electrodes182have a multi-layered structure of Ti/Al/Ti, a portion of the upper Ti layer may be easily oxidized to form an insulating oxide layer (TiO). Therefore, in the main-pressing step, the circuit board200and the driving circuit chip300may be respectively main-pressed with a predetermined pressure (hereinafter, referred to as a first pressure) required for the conductive balls414and424to break the insulating oxide layer and connect with the conductive Ti layer, so that the first pad part170and the lead part220may be electrically connected and the second pad part180and the bump part320may be electrically connected. In addition, when the film layers412and422include a thermo-curable resin, in the main-pressing step, the circuit board200and the driving circuit chip300may be respectively main-pressed while heating the second area2A of the display module20to a predetermined temperature (hereinafter, referred to as a first temperature) required to cure the film layers412and422. When the main-pressing step is performed without the pre-pressing step, the second adhesive layer520under the circuit board200may be deformed. In an embodiment, for example, the second adhesive layer520may be deformed such that the thickness T2aof the first portion of the second adhesive layer520overlapping each of the first pad electrodes172is less than the thickness T2′ which is before deformation, and the thickness T2bof the second portion of the second adhesive layer520overlapping the first opening OP1between two adjacent first pad electrodes172is greater than the thickness T2′ which is before deformation. In addition, the second adhesive layer520may be deformed such that the thickness T2cof the third portion of the second adhesive layer520overlapping each of the second pad electrodes182is less than the thickness T2′ which is before deformation, and the thickness T2dof the fourth portion of the second adhesive layer520overlapping a second opening OP2between two adjacent second pad electrodes182is greater than the thickness T2′ which is before deformation. Accordingly, the connection failure between the first pad part170and the lead part220due to the massing of the conductive balls414or the connection failure between the second pad part180and the bump part320due to the massing of the conductive balls424may occur. However, as illustrated inFIGS.10and11, embodiments of the method of manufacturing (or providing) the display device10may include the pre-pressing step (FIG.10) performed before the main-pressing step. By the pre-pressing step, the second adhesive layer520may be pre-deformed to have the second thickness T2(e.g., reduced thickness) that is less than the thickness T2′ which is before deformation. That is, the second adhesive layer520which is pre-deformed to have the second thickness T2may provide a pre-pressed display module including a pre-pressed adhesive layer. The method may include providing first pressing of the second adhesive layer520which has the preliminary thickness to form a pre-pressed display module including the first pad part170. In an embodiment, in the pre-pressing step, the second area2A of the display module20may be pressed with a second pressure equal to or greater than the first pressure (e.g., the pressure applied in the main-pressing step). In addition, in the pre-pressing step, the second area2A of the display module20may be pressed while heating the second area2A of the display module20to a second temperature equal to or greater than the first temperature (e.g., the temperature of the heat applied in the main-pressing step). Accordingly, deformation of the second adhesive layer520which is pre-deformed to have the second thickness T2by the pre-pressing step (e.g., pre-deformed adhesive layer) may be minimal even when the first pressure and heat having the first temperature are applied in the main-pressing step performed after the pre-pressing step. In an embodiment, in the pre-pressing step, the second area2A of the display module20may be pressed as a whole, that is, across an entire planar area of the second area2A (e.g., planar area defined along the first direction DR1and the second direction DR2). After the pre-pressing step, the second adhesive layer520may have a substantially uniform thickness. In an embodiment, in the pre-pressing step, only portions of the second area2A of the display module20respectively overlapping the first pad part170and the second pad part180among areas of the second area2A of the display module20may be selectively pressed. That is, the pre-pressing step may be selectively performed on a planar area to which pressure and heat are applied in the main-pressing step performed later. In an embodiment, the pre-pressing step (e.g., first pressing) may be selectively performed at areas corresponding to the first pad part170and the second pad part180among areas of the second area2A of the display module20. As being selectively pressed, the first pressing may include pressing only a portion of the second adhesive layer520which corresponds to the first pad part170of the display panel100. In an embodiment, as illustrated inFIG.11, a portion of the second adhesive layer520may protrude outwardly from the second lower film620by the pre-pressing step. That is, the second adhesive layer520may include a protrusion protruding outwardly from the second lower film620. In an embodiment, for example, the protrusion may surround the second lower film620in a plan view. In an embodiment, for example, the first side surface520aof the second adhesive layer520may protrude from the first side surface620aof the second lower film620in the direction opposite to the first direction DR1. The first side surface520aof the second adhesive layer520may be curved. In addition, the second side surface520bof the second adhesive layer520may protrude from the second side surface620bof the second lower film620in the first direction DR1. The second side surface520bof the second adhesive layer520may be curved. Referring toFIG.12, in an embodiment, at least a portion of the protrusion of the second adhesive layer520may be removed (e.g., may be cut). In an embodiment, for example, a portion of the protrusion that does not overlap the display panel100in a plan view (e.g., a portion protruding from the second lower film620in the first direction DR1, the second direction DR2, or a direction opposite to the second direction DR2) may be removed. Accordingly, the second side surface520bof the second adhesive layer520may be aligned with the second side surface620bof the second lower film620. The second side surface520bof the second adhesive layer520may each be flat so as to be coplanar with each other. A portion of the protrusion that overlaps the display panel100in a plan view (e.g., a portion protruding from the second lower film620in the direction opposite to the first direction DR1) may not be removed. Accordingly, the first side surface520aof the second adhesive layer520may remain protruded from the first side surface620aof the second lower film620in the direction opposite to the first direction DR1. The first side surface520aof the second adhesive layer520may be curved. When the main-pressing step is performed without the pre-pressing step, as the second adhesive layer520is deformed after the main-pressing step, a portion of the second adhesive layer520may protrude outwardly from the second lower film620. In this case, it may be difficult to remove the protrusion of the second adhesive layer520due to the circuit board200attached on the display panel100. However, one or more embodiment of the method of manufacturing or providing the display device10may include the pre-pressing step performed before the main-pressing step. Accordingly, as the second adhesive layer520is pre-deformed after the pre-pressing step (e.g., before the circuit board200is attached on the display panel100), a portion of the second adhesive layer520may protrude outwardly from the second lower film620and be exposed to outside the display module20. Accordingly, the protrusion of the second adhesive layer520may be easily removed. Accordingly, a defect of the display device10due to the protrusion may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. Referring toFIG.13, the circuit board200and the driving circuit chip300may be attached to the second area2A of the display module20. The first conductive film410and the second conductive film420may be attached on the second area2A of the display module20. Subsequently, the driving circuit chip300may be placed on the second conductive film420such that the bump part320overlaps the second pad part180, and the circuit board200may be placed on the first conductive film410such that the lead part220overlaps the first pad part170. In an embodiment, the driving circuit chip300may be placed on the second conductive film420such that the bump part320overlaps the second pad part180in consideration of an elongation of the display panel100by the pre-pressing step. That is, the driving circuit chip300may be placed on the second conductive film420such that the bump part320overlaps the second pad part180of the display panel100which is unbent or flat. In addition, the circuit board200may be placed on the first conductive film410such that the lead part220overlaps the first pad part170in consideration of the elongation of the display panel100by the pre-pressing step. That is, the display panel100is bendable, the pre-pressed display module further includes the display panel100which is unbent, and the providing of the circuit board200includes disposing the lead part220facing the first pad part170of the display panel100which is unbent. As such, each of the driving circuit chip300and the circuit board200may be attached on the display panel100to be more precisely aligned. Accordingly, a connection failure between the first pad part170and the lead part220due to misalignment between the first pad part170and the lead part220or a connection failure between the second pad part180and the bump part320due to misalignment between the second pad part180and the bump part320may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. In the main-pressing step, the driving circuit chip300and the circuit board200may be respectively main-pressed with the first pressure using pressing devices820and830. In an embodiment, when the film layers412and422include a thermo-curable resin, in the main-pressing step, the circuit board200and the driving circuit chip300may be respectively main-pressed while heating the second area2A of the display module20to the first temperature. With respect to the pressing devices820and830, for example, the method may include providing second pressing of the second adhesive layer520to electrically connect the first pad part170of the display panel100to the lead part220of the circuit board200by the first conductive film410and providing third pressing of the second adhesive layer520to electrically connect the second pad part180of the display panel100to the bump part320of the driving circuit chip300by the second conductive film420. The first pressure may be equal to or less than the second pressure, and the first temperature may be equal to or less than the second temperature. That is, the second pressing may include pressing the second adhesive layer520together with heating the pad area of the display module20to a first temperature, and the first pressing may include pressing the second adhesive layer520together with heating the pad area of the display module20to a second temperature equal to or greater than the first temperature. Accordingly, the second adhesive layer520pre-deformed to have the second thickness T2by the pre-pressing step may be hardly deformed even when the first pressure and heat having the first temperature are applied in the main-pressing step performed after the pre-pressing step. That is, the second pressing of the second adhesive layer520maintains the second adhesive layer520having the second thickness T2and the third pressing of the second adhesive layer520maintains the second adhesive layer520having the second thickness T2. Accordingly, after the main-pressing step, the second adhesive layer520may have a substantially uniform thickness. Accordingly, the connection failure between the first pad part170and the lead part220due to the massing of the conductive balls414or the connection failure between the second pad part180and the bump part320due to the massing of the conductive balls424may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. In an embodiment, the circuit board200may be attached on the display panel100after the driving circuit chip300is attached. That is, the driving circuit chip300may be placed on the second conductive film420, and the driving circuit chip300may be main-pressed with the first pressure using the pressing device820to electrically connecting the second pad part180and the bump part320. Subsequently, the circuit board200may be placed on the first conductive film410, and the circuit board200may be main-pressed with the first pressure using the pressing device830to electrically connecting the first pad part170and the lead part220. In an embodiment, the circuit board200may be substantially simultaneously (or concurrently) attached on the display panel100with the driving circuit chip300. Referring toFIGS.14and15, the third lower film630and the third adhesive layer530may be separated from the first lower film610and the second lower film620to define the display module20having the circuit board200and the driving circuit chip300attached to the display panel100at the distal end thereof. The display device10(and the display panel100) may be bendable at the bending area BA. The display panel100may be bent at the bending area BA. The bending area BA of the display panel100may be bent along the bending axis extending in the second direction DR2. In embodiments, the method of manufacturing or providing the display device10may include the pre-pressing step performed before the main-pressing step. In the pre-pressing step, the second pressure equal to or greater than the first pressure applied to the display module20in the main-pressing step and the heat having the second temperature equal to or greater than the first temperature applied to the display module20in the main-pressing step may be applied to the display module20. Accordingly, the second adhesive layer520pre-deformed to have the second thickness T2by the pre-pressing step may be hardly deformed even when the first pressure and heat having the first temperature are applied in the main-pressing step performed after the pre-pressing step. Accordingly, after the main-pressing step, the second adhesive layer520may have a substantially uniform thickness. Accordingly, the connection failure between the first pad part170and the lead part220due to the massing of the conductive balls414or the connection failure between the second pad part180and the bump part320due to the massing of the conductive balls424may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. In embodiments, as the second adhesive layer520is pre-deformed after the pre-pressing step (e.g., before the circuit board200is attached to the display panel100), a portion of the second adhesive layer520may protrude outwardly from the second lower film620. Accordingly, the protrusion of the second adhesive layer520may be easily removed since the circuit board200is not attached to the display panel100. Accordingly, the defect of the display device10due to the protrusion may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. In embodiments, the driving circuit chip300may be placed on the second conductive film420such that the bump part320overlaps the second pad part180in consideration of the elongation of the display panel100by the pre-pressing step. In addition, the circuit board200may be placed on the first conductive film410such that the lead part220overlaps the first pad part170in consideration of the elongation of the display panel100by the pre-pressing step. That is, each of the driving circuit chip300and the circuit board200may be attached on the display panel100to be more precisely aligned. Accordingly, a connection failure between the first pad part170and the lead part220due to misalignment between the first pad part170and the lead part220or a connection failure between the second pad part180and the bump part320due to misalignment between the second pad part180and the bump part320may be prevented or reduced. Accordingly, the reliability of the display device10may be improved. FIG.16is a block diagram illustrating an embodiment of an electronic device900.FIG.17is a diagram illustrating an example in which the electronic device900ofFIG.16is implemented as a television.FIG.18is a diagram illustrating an example in which the electronic device900ofFIG.16is implemented as a smart phone. Referring toFIGS.16to18, in an embodiment, an electronic device900may include a processor910, a memory device920, a storage device930, an input/output (“I/O”) device940, a power supply950, and a display device960. Here, the display device960may correspond to one or more embodiment of the display device10described with reference toFIGS.1to9. The electronic device900may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (“USB”) device, or the like. In an embodiment, as illustrated inFIG.17, the electronic device900may be implemented as a television. In an embodiment, as illustrated inFIG.18, the electronic device900may be implemented as a smart phone. However, embodiments are not limited thereto, and the electronic device900may be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet personal computer (“PC”), a car navigation system, a computer monitor, a laptop, a head disposed (e.g., mounted) display (“HMD”), or the like. The processor910may perform various computing functions. In an embodiment, the processor910may be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), or the like. The processor910may be coupled to other components via an address bus, a control bus, a data bus, or the like. In an embodiment, the processor910may be coupled to an extended bus such as a peripheral component interconnection (“PCI”) bus. The memory device920may store data for operations of the electronic device900. In an embodiment, the memory device920may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistance random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, or the like, and/or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, or the like. In an embodiment, the storage device930may include a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, or the like. In an embodiment, the I/O device940may include an input device such as a keyboard, a keypad, a mouse device, a touchpad, a touch-screen, or the like, and an output device such as a printer, a speaker, or the like. The power supply950may provide power for operations of the electronic device900. The display device960may be coupled to other components via the buses or other communication links. In an embodiment, the display device960may be included in the I/O device940. Although embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the invention are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art. | 52,381 |
11943981 | DETAILED DESCRIPTION OF EMBODIMENTS In order to make objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of embodiments of the present disclosure are clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part rather than all of embodiments of the present disclosure. Based on embodiments of the present disclosure, all additional embodiments obtained by those ordinary skilled in the art without carrying out inventive effort fall within the scope of protection of the present disclosure. It should be noted that, in the drawings, for clarity and/or description purposes, sizes and relative sizes of elements may be enlarged. Accordingly, the size and relative size of each element need not to be limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar components. When an element is described as being “on”, “connected to” or “coupled to” another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or an intermediate element may be provided. However, when an element is described as being “directly on”, “directly connected to” or “directly coupled to” another element, no intermediate element is provided. Other terms and/or expressions configured to describe the relationship between elements, such as “between” and “directly between”, “adjacent” and “directly adjacent”, “on” and “directly on”, and so on, should be interpreted in a similar manner. In addition, the term “connection” may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. In addition, X-axis, Y-axis and Z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader meaning. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the objective of the present disclosure, “at least one of X, Y and Z” and “at least one selected from a group consisting of X, Y and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the listed related items. It should be noted that although the terms “first”, “second”, and so on may be used herein to describe various components, members, elements, regions, layers and/or parts, these components, members, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are configured to distinguish one component, member, element, region, layer and/or part from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer and/or a first part discussed below may be referred to as a second component, a second member, a second element, a second region, a second layer and/or a second part without departing from teachings of the present disclosure. For ease of description, spatial relationship terms, such as “upper”, “lower”, “left”, “right”, etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that the spatial relationship terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, an element or feature described as “below” or “under” another element or feature will be oriented “above” or “on” the other element or feature. In the present disclosure, the terms “substantially”, “about”, “approximately” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to explain an inherent deviation of a measured or calculated value that will be recognized by those ordinary skilled in the art. Taking into account process fluctuations, measurement problems, and errors related to measurements of specific quantities (that is, limitations of a measurement system), the terms “substantially”, “about” or “approximately” used in the present disclosure includes the stated value and means that the specific value determined by those ordinary skilled in the art is within an acceptable range of deviation. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. It should be noted that the expression of “same layer” herein refers to a layer structure formed by first using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer by using a patterning process. Depending on the specific patterns, the patterning process may include multiple exposure, development or etching processes, and the specific pattern in the layer structure formed may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or parts located in the “same layer” are made of the same material and formed by the same patterning process. Generally, a plurality of elements, components, structures and/or parts located in the “same layer” have substantially the same thickness. Embodiments of the present disclosure provide at least a display substrate and a display apparatus. The display substrate includes: a base substrate, including a display area and a bezel area located on at least one side of the display area; a plurality of pixel units located in the display area, where the plurality of pixel units are arranged in an array along a row direction and a column direction on the base substrate, and each pixel unit includes a plurality of sub-pixels; a plurality of scanning signal lines disposed on the base substrate, where the plurality of scanning signal lines are configured to provide a scanning signal to a plurality of rows of sub-pixels, respectively; a gate driver circuit disposed on the base substrate and located in the bezel area, where the gate driver circuit is configured to output a scanning signal; a plurality of load compensation units disposed on the base substrate and located in the bezel area, where the plurality of load compensation units are located between the gate driver circuit and the plurality of pixel units; and a plurality of scanning signal lead wires disposed on the base substrate and located in the bezel area, the plurality of scanning signal lead wires are configured to transmit the scanning signal output by the gate driver circuit respectively to the plurality of scanning signal lines, where at least one of the scanning signal lead wires crosses at least one of the load compensation units in the row direction. In the display substrate and the display apparatus provided by embodiments of the present disclosure, the scanning signal lead wire(s) for supplying the scanning signal(s) are disposed above the load compensation unit(s), so as to form an overlap between the scanning signal lead wires and the load compensation units, so that the scanning signal lead wires may be compensated, thereby improving the stability of the scanning signal. FIG.1shows a schematic top view of a display apparatus according to some exemplary embodiments of the present disclosure.FIG.2shows a schematic top view of a display apparatus according to some exemplary embodiments of the present disclosure, where a pixel unit and a load compensation unit of a display substrate are schematically shown. Referring toFIG.1andFIG.2in combination, a display apparatus1000may include a display substrate. The display substrate may include a base substrate100, and the base substrate100may include a display area AA and a bezel area NA which is located on at least one side of the display area. It should be noted that, in the embodiment shown inFIG.1, the bezel area NA surrounds the display area AA, but embodiments of the present disclosure are not limited to this. In other embodiments, the bezel area NA may be located on at least one side of the display area AA without surrounding the display area AA. The display substrate may include a plurality of pixel units P located in the display area AA. It should be noted that a pixel unit P is a smallest unit for displaying an image. For example, the pixel unit P may include a light emitting device that emits white light and/or color light. A plurality of pixel units P may be arranged in the form of a matrix whose rows extends in a first direction (e.g., the row direction) and columns extends in a second direction (e.g., the column direction). However, the embodiments of the present disclosure do not specifically limit an arrangement form of the pixel units P, and the pixel units P may be arranged in various forms. For example, the pixel units P may be arranged such that a direction inclined with respect to the first direction X and the first direction Y is the column direction, and a direction crossing the column direction is the row direction. A pixel unit P may include a plurality of sub-pixels. For example, a pixel unit P may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit P may include four sub-pixels, namely, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For example, the first sub-pixel SP1may be a red sub-pixel, the second sub-pixel SP2may be a green sub-pixel, the third sub-pixel SP3may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel. Each sub-pixel may include a light emitting element, and a pixel driver circuit for driving the light emitting element. For example, the first sub-pixel SP1may include a first light emitting element, and a first pixel driver circuit for driving the first light emitting element, and the first light emitting element may emit red light; the second sub-pixel SP2may include a second light emitting element, and a second pixel driver circuit for driving the second light emitting element, and the second light emitting element may emit green light; and the third sub-pixel SP3may include a third light emitting element, and a third pixel driver circuit for driving the third light emitting element, and the third light emitting element may emit blue light. For example, in an OLED display panel, a light emitting element of a sub-pixel may include an anode electrode, a light emitting material layer, and a cathode electrode which are arranged in a stack. Therefore, a light emitting region of the sub-pixel may be a region corresponding to a part of the light emitting material layer sandwiched between the anode electrode and the cathode electrode. Referring toFIG.1, the display substrate may include a load compensation unit1, a test circuit200, a gate driver circuit300, a multiplexer400and other components, which are all located in the peripheral region NA. The display area AA may include a first boundary AA1, a second boundary AA2, a third boundary AA3, and a fourth boundary AA4(e.g., an upper boundary, a lower boundary, a left boundary, and a right boundary) connected in sequence. In some embodiments of the present disclosure, an orthographic projection of the display area AA on the base substrate100may have a shape of a rounded rectangle. For convenience of description, four rounded corners of the rounded rectangle may be respectively referred to as a first rounded corner portion101, a second rounded corner portion102, a third rounded corner portion103, and a fourth rounded corner portion104. For example, the first rounded corner portion101may be located at an upper left corner inFIG.1, the second rounded corner portion102may be located at an upper right corner inFIG.1, the third rounded corner portion103may be located at a lower left corner inFIG.1, and the fourth rounded corner portion104may be located at a lower right corner inFIG.1. The test circuit200may be located on a side in the peripheral region NA adjacent to the first boundary AA1, and the test circuit200is arranged facing the first boundary AA1, the first rounded corner portion101, and the second rounded corner portion102. For example, the test circuit200may include a plurality of test pins (which will be described below) that may be configured to provide a test signal. For example, the test signal may include a data signal used for the plurality of pixel units P in the display area AA. The multiplexer400may be located on a side in the peripheral region NA adjacent to the second boundary AA2, and the multiplexer400is arranged facing the second boundary AA2, the third rounded corner portion103and the fourth rounded corner portion104. For example, the multiplexer400may perform time-division multiplex on signal lines in a wiring region. As shown inFIG.1, the display substrate includes an integrated circuit IC disposed in the peripheral region NA, and a wiring region500located between the integrated circuit IC and the multiplexer400. Various signals output by the integrated circuit IC may be transmitted to the multiplexer400through the signal lines in the wiring region500. Under the control of a signal control terminal of the multiplexer400, the various signals are output to the respective pixel units P in the display area AA. By providing the multiplexer400, the number of signal lines disposed in the wiring region may be reduced, so that a pressure on wiring in the wiring region may be reduced. The gate driver circuit300may be located on a side in the peripheral region NA adjacent to the third boundary AA3and on a side in the peripheral region NA adjacent to the fourth boundary AA4. It should be noted that althoughFIG.1shows that the driver circuit is located on left and right sides of the display area AA, the embodiments of the present disclosure are not limited thereto, and the driver circuit may be located at any suitable position in the peripheral region NA. For example, the gate driver circuit300may adopt a GOA (Gate Driver on Array) technology. In the GOA technology, a gate driver circuit instead of an external driving chip is directly disposed on an array substrate. Each GOA unit serves as a stage of shift register, and each stage of shift register is connected to a gate line. Various stages of shift registers sequentially output turn-on voltages in turn, so that a progressive scanning on pixels may be achieved. In some embodiments, each stage of shift register may also be connected to a plurality of gate lines. This may adapt to a development trend of high resolution and narrow bezel of the display substrate. The display substrate may include a plurality of load compensation units1. As shown inFIG.1andFIG.2, some of the plurality of load compensation units1are located adjacent to the first rounded corner portion101in the peripheral region NA, and some others of the plurality of load compensation units1are located adjacent to the second rounded corner portion102in the peripheral region NA. The plurality of load compensation units1are all located between the test circuit200and the display area AA. FIG.3shows a partial enlarged view of part I inFIG.2. Referring toFIG.2andFIG.3in combination, a plurality of sub-pixels are arranged in an array on the base substrate100, that is, a plurality of rows of sub-pixels and a plurality of columns of sub-pixels are formed on the base substrate100. For the plurality of columns of sub-pixels, since the display area AA has a rounded rectangular shape, the number of sub-pixels included in each of the columns of sub-pixels may be inconsistent. Referring toFIG.2, the rounded rectangle has a center105. A first straight line L1extends in the column direction Y and passes through the center105. A second straight line L2extends in the column direction Y and passes through a rounded corner of the rounded rectangle, for example, through the first rounded corner portion101. In a region where the first straight line L1is located, a column of sub-pixels include N sub-pixels. In a region where the second straight line L2is located, a column of sub-pixels include M sub-pixels. Due to a presence of the rounded corner, M is less than N. Referring toFIG.2in combination, as the second straight line L2gradually approaches the third boundary AA3, M may gradually decrease. In the embodiments of the present disclosure, for convenience of description, a column of sub-pixels in the region where the first straight line L1is located is referred to as a reference pixel column, and a column of sub-pixels corresponding to each rounded corner is referred to as an edge pixel column. The display substrate further includes a plurality of data signal lines disposed on the base substrate100, and the plurality of data signal lines are configured to provide a data signal to a plurality of columns of sub-pixels, respectively. Since the number of sub-pixels in an edge pixel column is less than the number of sub-pixels in the reference pixel column, a load on a data signal line for supplying a data signal to the edge pixel column is inconsistent with a load on a data signal line for supplying a data signal to the reference pixel column. Therefore, it is necessary to perform a load compensation on the edge pixel column, so as to make the loads on the respective data signal lines consistent, thereby avoiding a display difference and ensuring a display quality. For example, the less the sub-pixels in an edge pixel column, the less a load on a data signal line for supplying a data signal to the edge pixel column, and the greater the load is required to be compensated. Therefore, optionally, in the display substrate provided by the embodiments of the present disclosure, the more the sub-pixels connected to a data signal line corresponding to a load compensation unit, the less a load value required to be compensated by the load compensation unit. The data signal lines corresponding to different numbers of sub-pixels are compensated by the load compensation units with different compensation load values, so as to uniform the loads on different data signal lines, which may avoid the display difference and ensure the display quality. For example, the reference pixel column includes N sub-pixels, and the edge pixel column includes M sub-pixels. When compensating a load on a data signal line, a value of the load required to be compensated may be determined according to a difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column. FIG.4shows a partial enlarged view of part II inFIG.3. Referring toFIG.1toFIG.4in combination, the plurality of load compensation units1are arranged along an outline of the rounded corner of the rounded rectangle. Referring toFIG.3andFIG.4, the plurality of load compensation units1are in a one-to-one correspondence with the plurality of columns of pixel units P. A pixel unit P may include a plurality of sub-pixels, for example, three sub-pixels (e.g., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3). A load compensation unit1may include a plurality of compensation capacitors, for example, three compensation capacitors. The plurality of compensation capacitors may include a first compensation capacitor11, a second compensation capacitor12, and a third compensation capacitor13. In a group of a load compensation unit1and a column of pixel units P corresponding to the load compensation unit1, the first compensation capacitor11may be configured to compensate a column of first sub-pixels SP1, the second compensation capacitor12may be configured to compensate a column of second sub-pixels SP2, and the third compensation capacitor13may be configured to compensate a column of third sub-pixels SP3. In an embodiment of the present disclosure, each sub-pixel may include a light emitting element, and a pixel driver circuit for driving the light emitting element. InFIG.4, a rectangular region surrounded by a dot-dash line represents a region of each sub-pixel. A 7T1C pixel driver circuit is illustrated below by way of example in describing a structure of a pixel driver circuit of each sub-pixel located in the display area AA in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driver circuit. In a case of no conflict, other known pixel driver circuit structures may be applied to the embodiments of the present disclosure. FIG.5shows an equivalent circuit diagram of a pixel driver circuit of a display substrate according to some exemplary embodiments of the present disclosure.FIG.6shows a top view of an exemplary implementation of a sub-pixel in a display area of a display substrate according to some exemplary embodiments of the present disclosure.FIG.7toFIG.10show top views of some film layers of an exemplary implementation of the sub-pixel inFIG.6. For example, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer are schematically shown inFIG.7toFIG.10, respectively. Referring toFIG.5toFIG.10in combination, the pixel driver circuit may include a plurality of thin film transistors and a storage capacitor Cst. The pixel driver circuit is configured to drive an organic light-emitting diode (OLED). The plurality of thin film transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor may include a gate electrode, a source electrode, and a drain electrode. The display substrate may further include a plurality of signal lines. For example, the plurality of signal lines may include: a scanning signal line61for transmitting a scanning signal Sn, a reset signal line62for transmitting a reset control signal RESET (namely a scanning signal for a previous row), a light emission control line63for transmitting a light emission control signal En, a data signal line64for transmitting a data signal Dm, a driving voltage line65for transmitting a driving voltage VDD, an initialization voltage line66for transmitting an initialization voltage Vint, and a power line67for transmitting a VSS voltage. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may be formed along an active layer (namely the semiconductor layer) as shown inFIG.7. The active layer may have a curved or bent shape, and may include a first active layer20acorresponding to the first transistor T1, a second active layer20bcorresponding to the second transistor T2, a third active layer20ccorresponding to the third transistor T3, a fourth active layer20dcorresponding to the fourth transistor T4, a fifth active layer20ecorresponding to the fifth transistor T5, a sixth active layer20fcorresponding to the sixth transistor T6, and a seventh active layer20gcorresponding to the seventh transistor T7. The active layer may include, for example, polysilicon, and may include, for example, a channel region, a source region, and a drain region. The channel region may be non-doped or have a doping type different from those of the source region and the drain region, and therefore possess a semiconductor property. The source region and the drain region are respectively located on both sides of the channel region, and are doped with impurities, and therefore conductive. The impurities may vary depending on whether the TFT is an N-type transistor or a P-type transistor. The first transistor T1may include the first active layer20aand a first gate electrode G1. The first active layer20amay include a first channel region201a, a first source region203a, and a first drain region205a. The first transistor T1has the gate electrode G1electrically connected to the reset signal line62, a source electrode S1electrically connected to the initialization voltage line66, and a drain electrode D1electrically connected to a terminal Cst1of the storage capacitor Cst, a drain electrode D2of the second transistor T2, and a gate electrode G3of the third transistor T3. As shown inFIG.4, the drain electrode D1of the first transistor T1, the terminal Cst1of the storage capacitor Cst, the drain electrode D2of the second transistor T2, and the gate electrode G3of the third transistor T3are connected at a node N1. The first transistor T1may be turned on in response to the reset control signal RESET transmitted through the reset signal line62, so as to transmit the initialization voltage Vint to the gate electrode G1of the third transistor T3, so that an initialization operation is performed to initialize a voltage of the gate electrode G3of the third transistor T3. That is, the first transistor T1is also referred to as an initialization transistor. The second transistor T2includes the second active layer20band a second gate electrode G2. The second active layer20bmay include a second channel region201b, a second source region203b, and a second drain region205b. The second transistor T2has the gate electrode G2electrically connected to the scanning signal line61, a source electrode S2electrically connected to a node N3, and the drain electrode D2electrically connected to the node N1. The second transistor T2is turned on in response to the scanning signal Sn transmitted through the scanning signal line61, so as to electrically connect the gate electrode G3and the drain electrode D3of the third transistor T3, realizing a diode connection of the third transistor T3. The third transistor T3includes the third active layer20cand a third gate electrode G3. The third active layer20cincludes a third source region203c, a third drain region205c, and a third channel region201cconnecting the third source region203cand the third drain region205c. The third source region203cand the third drain region205cextend in two opposite directions with respect to the third channel region201c. The third source region203cof the third transistor T3is connected to a fourth drain region205dand a fifth drain region205e. The third drain region205cis connected to the second source region203band a sixth source region203f. The gate electrode G3of the third transistor T3is electrically connected to the node N1through via holes VAH1and VAH2, and a first connection line68. The third transistor T3has the gate electrode G3electrically connected to the node N1, a source electrode S3electrically connected to a node N2, and a drain electrode D3electrically connected to the node N3. The third transistor T3may receive the data signal Dm in response to a switching operation of the fourth transistor T4, so as to supply a driving current Id to the OLED. That is, the third transistor T3is also referred to as a driving transistor. The fourth transistor T4includes the fourth active layer20dand a fourth gate electrode G4. The fourth active layer20dmay include a fourth channel region201d, a fourth source region203d, and a fourth drain region205d. The fourth transistor T4is used as a switching device for selecting a target light emitting sub-pixel. The fourth gate electrode G4is connected to the scanning signal line61, the fourth source region203dis connected to the data signal line64through a via hole VAH4, and the fourth drain region205dis connected to the first transistor T1and the fifth transistor T5, that is, the fourth drain region205dis electrically connected to the node N2. The fourth transistor T4is turned on in response to the scanning signal Sn transmitted through the scanning signal line61, so that a switching operation is performed to transmit the data signal Dm to the source electrode S3of the third transistor T3. The fifth transistor T5includes the fifth active layer20eand a fifth gate electrode G5. The fifth active layer20emay include a fifth channel region201e, a fifth source region203e, and a fifth drain region205e. The fifth source region203emay be connected to the driving voltage line65through a via hole VAH6. The fifth transistor T5has the gate electrode G5electrically connected to the light emission control line63, a source electrode S5electrically connected to the driving voltage line65, and a drain electrode D5electrically connected to the node N2. The sixth transistor T6includes the sixth active layer20fand a sixth gate electrode G6. The sixth active layer20fmay include a sixth channel region201f, a sixth source region203f, and a sixth drain region205f. The sixth drain region205fmay be connected to the anode electrode of the OLED through a via hole VAH7. The sixth transistor T6has the gate electrode G6electrically connected to the light emission control line63, a source electrode S6electrically connected to the node N3, and a drain electrode D6electrically connected to a node N4, that is, the drain electrode D6is electrically connected to the anode electrode of the OLED. The fifth transistor T5and the sixth transistor T6may be turned on concurrently (for example, simultaneously) in response to the light emission control signal En transmitted through the light emission control line63, so as to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED. The seventh transistor T7includes the seventh active layer20gand a seventh gate electrode G7. The seventh active layer20gmay include a seventh source region203g, a seventh drain region205g, and a seventh channel region201g. The seventh drain region205gis connected to the first source region203aof the first transistor T1. The seventh drain region205gmay be electrically connected to the initialization voltage line66through a via hole VAH8, a second connection line69, and a via hole VAH5. The seventh transistor T7has the gate electrode G7electrically connected to the reset signal line62, a source electrode S7electrically connected to the node N4, and a drain electrode D7electrically connected to the initialization voltage line66. The storage capacitor Cst has the terminal (hereinafter referred to as a first capacitor electrode) Cst1electrically connected to the node N1, and another terminal (hereinafter referred to as a second capacitor electrode) Cst2electrically connected to the driving voltage line65. The OLED has the anode electrode electrically connected to the node N4, and a cathode electrode electrically connected to the power line67to receive a common voltage VSS. Accordingly, the OLED may receive the driving current Id from the third transistor T3to emit light, so as to display an image. It should be noted that inFIG.4, the thin film transistors T1, T2, T3, T4, T5, T6, and T7are p-channel field effect transistors. However, embodiments of the present disclosure are not limited thereto. At least some of the thin film transistors T1, T2, T3, T4, T5, T6and T7may be n-channel field effect transistors. In operation, in an initialization phase, the reset control signal RESET at a low level is supplied through the reset signal line62. Subsequently, the first transistor T1may be turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line66is transmitted to the gate electrode G1of the third transistor T3through the first transistor T1. Then, the third transistor T3is initialized due to the initialization voltage Vint. In a data programming phase, the scanning signal Sn at a low level is supplied through the scanning signal line61. Subsequently, the fourth transistor T4and the second transistor T2may be turned on based on the low level of the scanning signal Sn. Then, the third transistor T3is placed in a diode-connection state by the turned-on second transistor T2and is biased in a forward direction. Subsequently, a compensation voltage (Dm+Vth) (for example, Vth is of a negative value) obtained by subtracting a threshold voltage Vth of the third transistor T3from the data signal Dm supplied through the data signal line64is applied to the gate electrode G3of the third transistor T3. Next, the driving voltage VDD and the compensation voltage (Dm+Vth) are applied to both terminals of the storage capacitor Cst, so that electric charges corresponding to a voltage difference between the corresponding terminals are stored into the storage capacitor Cst. In a light emission phase, the light emission control signal En from the light emission control line63changes from being at a high level to being at a low level. Subsequently, in the light emission phase, the fifth transistor T5and the sixth transistor T6may be turned on in response to the low level of the light emission control signal En. Next, a driving current is generated based on a difference between the voltage of the gate electrode G3of the third transistor T3and the driving voltage VDD. The driving current Id corresponding to a difference between the driving current and a bypass current is supplied to the OLED through the sixth transistor T6. In the light emission phase, based on a current-voltage relationship of the third transistor T3, a gate-source voltage of the third transistor T3is maintained at ((Dm+Vth)−VDD) due to the presence of the storage capacitor Cst. The driving current Id is proportional to (Dm−VDD)2. Therefore, the driving current Id may not be affected by a variation in the threshold voltage Vth of the third transistor T3. FIG.11shows a schematic diagram of a sectional structure of the display substrate taken along line AA′ inFIG.6, according to some exemplary embodiments of the present disclosure. Referring toFIG.6toFIG.11in combination, the display substrate may include the base substrate100and a plurality of film layers disposed on the base substrate100. In some embodiments, the plurality of film layers include at least a semiconductor layer20, a first conductive layer21, a second conductive layer22, and a third conductive layer23, which are sequentially disposed in a direction away from the base substrate100. The plurality of film layers may further include at least a plurality of insulation film layers, which may include, for example, a first gate insulation layer24, a second gate insulation layer25, and an interlayer insulation layer26. The first gate insulation layer24may be disposed between the semiconductor layer20and the first conductive layer21, the second gate insulation layer25may be disposed between the first conductive layer21and the second conductive layer22, and the interlayer insulation layer26may be disposed between the second conductive layer22and the third conductive layer23. For example, the semiconductor layer20may be formed of a semiconductor material such as low-temperature polysilicon, and may have a film layer thickness in a range of 400 angstroms to 800 angstroms, such as 500 angstroms. The first conductive layer21and the second conductive layer22may be formed of a conductive material that forms the gate electrode of the thin film transistor. For example, the conductive material may be Mo. The first conductive layer21and the second conductive layer22may have a film layer thickness in a range of 2000 angstroms to 4000 angstroms, such as 3000 angstroms. The third conductive layer23may be formed of a conductive material that forms the source electrode and the drain electrode of the thin film transistor. For example, the conductive material may include Ti, Al, etc. The third conductive layer23may have a stacked structure formed of Ti/Al/Ti, and have a film layer thickness in a range of 6000 angstroms to 9000 angstroms. For example, in the case that the third conductive layer23has the stacked structure formed of Ti/Al/Ti, the respective layers of the stacked structure formed of Ti/Al/Ti may have a thickness of about 500 angstroms, a thickness of about 6000 angstroms, and a thickness of about 500 angstroms, respectively. For example, the first gate insulation layer24and the second gate insulation layer25may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and each of the first gate insulation layer24and the second gate insulation layer25may have a thickness of about 1000 angstroms to 2000 angstroms. For example, the interlayer insulation layer26may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and may have a thickness of about 3000 angstroms to 6000 angstroms. The display substrate includes the scanning signal line61, the reset signal line62, the light emission control line63, and the initialization voltage line66that are arranged in the row direction to respectively apply the scanning signal Sn, the reset control signal RESET, the light emission control signal En, and the initialization voltage Vint to sub-pixels11,12, and13. The display substrate may further include the data signal line64and the driving voltage line65that cross the scanning signal line61, the reset signal line62, the light emission control line63, and the initialization voltage line66to respectively apply the data signal Dm and the driving voltage VDD to a sub-pixel10. As shown inFIG.8, the scanning signal line61, the reset signal line62, and the light emission control line63are all located in the first conductive layer21. The gate electrodes G1to G7of the respective transistors are also located in the first conductive layer21. For example, parts of the reset signal line62overlapping with the semiconductor layer20respectively form the gate electrode G1of the first transistor T1and the gate electrode G7of the seventh transistor T7, parts of the scanning signal line61overlapping with the semiconductor layer20respectively form the gate electrode G2of the second transistor T2and the gate electrode G4of the fourth transistor T4, and parts of the light emission control line63overlapping with the semiconductor layer20respectively form the gate electrode G6of the sixth transistor T6and the gate electrode G5of the fifth transistor T5. Continuing to refer toFIG.8, the display substrate may further include a plurality of first gate structures CG1. The plurality of first gate structures CG1are also located in the first conductive layer21. A part of the first gate structure CG1that overlaps with the semiconductor layer20forms the third gate electrode G3of the third transistor T3. The first gate structure CG1further forms a terminal of the storage capacitor Cst, for example, the first capacitor electrode Cst1. That is, the third transistor T3and the storage capacitor Cst share the first gate structure CG1simultaneously as the gate electrode of the third transistor T3and an electrode of the storage capacitor Cst. As shown inFIG.9, the initialization voltage line66is located in the second conductive layer22. The display substrate may further include a plurality of second gate structures CG2. The plurality of second gate structures CG2are also located in the second conductive layer22. The second gate structure CG2forms another terminal of the storage capacitor Cst, for example, the second capacitor electrode Cst2. That is, the first gate structure CG1and the second gate structure CG2are arranged facing each other, where orthographic projections of the two on the base substrate100at least partially overlap with each other, and the second gate insulation layer25is disposed between the two. For example, the first gate structure CG1may be electrically connected to the node N1through the via holes VAH1and VAH2, and the first connection line68, and the second gate structure CG2may be electrically connected to the driving voltage line65through a via hole VAH9. That is, the first gate structure CG1and the second gate structure CG2are connected to different voltage signals. In this way, the overlapping parts of the first gate structure CG1and the second gate structure CG2may form the storage capacitor Cst. As shown inFIG.10, the data signal line64and the driving voltage line65are located in the third conductive layer23. In addition, the first connection line68and the second connection line69are also located in the third conductive layer23. FIG.12toFIG.14respectively show schematic diagrams of the respective layers inFIG.4, whereFIG.12schematically shows a partial top view of the first conductive layer,FIG.13schematically shows a partial top view of the second conductive layer, andFIG.14schematically shows a partial top view of the third conductive layer. It should be noted that in order to clearly show the structure of the embodiments of the present disclosure, a plane structure of the respective sub-pixels in the display area AA is omitted inFIG.12toFIG.14. For details of the plane structure of the respective sub-pixels, reference may be made to the above description forFIG.5toFIG.10. Referring toFIG.4andFIG.12toFIG.14in combination, each compensation capacitor may include a first compensation capacitor electrode110and a second compensation capacitor electrode120. The first compensation capacitor electrode110is located in the first conductive layer21, and the second compensation capacitor electrode120is located in the second conductive layer22. The first compensation capacitor electrode110and the second compensation capacitor electrode120are arranged facing each other, orthographic projections of the two on the base substrate at least partially overlap with each other, and the second gate insulation layer25is disposed between the two. For example, the first compensation capacitor electrode110may be electrically connected to the data signal, and the second compensation capacitor electrode120may be electrically connected to the driving voltage, that is, the two are connected to different voltage signals. In this way, the overlapping parts of the first compensation capacitor electrode110and the second compensation capacitor electrode120may form the compensation capacitor. In some exemplary embodiments of the present disclosure, within a load compensation unit, first compensation capacitor electrodes110of a plurality of compensation capacitors are spaced apart from each other, that is, there is a gap provided between any two adjacent first compensation capacitor electrodes110. For example, in the illustrated embodiment, the load compensation unit1may include three compensation capacitors, namely, the first compensation capacitor11, the second compensation capacitor12, and the third compensation capacitor13. A first compensation capacitor electrode110of the first compensation capacitor11, a first compensation capacitor electrode110of the second compensation capacitor12, and a first compensation capacitor electrode110of the third compensation capacitor13are spaced apart from each other. That is, there is a first gap14provided between the first compensation capacitor electrode110of the first compensation capacitor11and the first compensation capacitor electrode110of the second compensation capacitor12, and there is a second gap15provided between the first compensation capacitor electrode110of the second compensation capacitor12and the first compensation capacitor electrode110of the third compensation capacitor13. For example, in the illustrated embodiment, each of the first compensation capacitor electrodes110may extend in the column direction Y, the plurality of first compensation capacitor electrodes110within the load compensation unit1may be arranged at intervals in the row direction X, and each of the first gap14and the second gap15extends in the column direction Y. In some exemplary embodiments of the present disclosure, within one load compensation unit, second compensation capacitor electrodes120of a plurality of compensation capacitors are connected to each other. In other words, the plurality of second compensation capacitor electrodes120of the load compensation unit are formed as a continuously extending integral structure. For example, in the load compensation unit1, orthographic projections of the first compensation capacitor electrodes110of the plurality of compensation capacitors on the base substrate100falls within an orthographic projection of the plurality of second compensation capacitor electrodes120that are connected to each other on the base substrate100. This is beneficial to an increase of an area of an overlapping region between the first compensation capacitor electrodes and the second compensation capacitor electrodes, which may help increase capacitance values of the compensation capacitors. It should be noted that, in an embodiment of the present disclosure, second compensation capacitor electrodes120of a plurality of adjacent load compensation units may be connected to each other. In other words, the plurality of second compensation capacitor electrodes120of the plurality of load compensation units may be formed as a continuously extending integral structure. Referring toFIG.12, the first compensation capacitor electrode110may include a first electrode body111, a first electrode connection portion112, and a second electrode connection portion113. An orthographic projection of the first electrode body111on the base substrate is substantially rectangular. The first electrode connection portion112is connected to an end of the first electrode body111proximate to the display area AA, and the second electrode connection portion113is connected to an end of the first electrode body111away from the display area AA. Referring toFIG.13, the second compensation capacitor electrode120may include a second electrode body121, a third electrode connection portion122, and a fourth electrode connection portion123. An orthographic projection of the second electrode body121on the base substrate is substantially rectangular. The third electrode connection portion122is connected to an end of the second electrode body121proximate to the display area AA, and the fourth electrode connection portion123is connected to an end of the second electrode body121away from the display area AA. Referring toFIG.4, the display substrate further includes a plurality of first via holes VH1, for example, at least two first via holes VH1. The plurality of first via holes VH1expose a part of the first electrode connection portion112. A data signal line64is electrically connected to a first compensation capacitor electrode110through the plurality of first via holes VH1. As shown inFIG.4, the plurality of first via holes VH1are arranged at intervals in the row direction X. That is, the plurality of first via holes VH1that are connected to the same data signal line64are arranged in the row direction X. This is conducive to a full use of a space to arrange a connection structure between the compensation capacitor and the data signal line. The display substrate further includes a plurality of second via holes VH2, for example, at least two second via holes VH2. The plurality of second via holes VH2expose a part of the third electrode connection portion122. A driving voltage line65is electrically connected to a second compensation capacitor electrode120through the plurality of second via holes VH2. The plurality of second via holes VH2are arranged at intervals in the column direction Y. That is, the plurality of second via holes VH2that are connected to the same driving voltage line65are arranged in the column direction Y. This is conducive to a full use of a space to arrange a connection structure between the compensation capacitor and the driving voltage line. With reference toFIG.1andFIG.4in combination, the test circuit200may include a plurality of test pins201, which may be configured to provide a test signal. For example, the test signal may include a data signal used for the plurality of pixel units P in the display area AA. The display substrate may further include a plurality of third via holes VH3, for example, at least two third via holes VH3. The plurality of third via holes VH3expose a part of the second electrode connection portion113. A test pin201is electrically connected to a first compensation capacitor electrode110through the plurality of third via holes VH3. The plurality of third via holes VH3are arranged at intervals in the column direction Y. That is, the plurality of third via holes VH3that are connected to the same test pin201are arranged in the column direction Y. In other words, the first compensation capacitor electrode110has an end electrically connected to the test pin201of the test circuit200, and another end electrically connected to the data signal line64. In this way, the compensation capacitor is electrically connected to the data signal line64, so as to compensate a load on a data signal line64corresponding to a column of sub-pixels. The display substrate further includes a plurality of fourth via holes VH4, for example, at least two fourth via holes VH4. The plurality of fourth via holes VH4expose a part of the fourth electrode connection portion123. The display substrate may further include a driving voltage lead wire650for providing the driving voltage VDD. The driving voltage lead wire650is electrically connected to a second compensation capacitor electrode120through the plurality of fourth via holes VH4. The plurality of fourth via holes VH4are arranged at intervals in the column direction Y. In other words, the second compensation capacitor electrode120has an end electrically connected to the driving voltage lead wire650, and another end electrically connected to the driving voltage line65. The display substrate may further include a plurality of scanning signal lead wires610disposed on the base substrate100and located in the bezel area NA. The plurality of scanning signal lead wires610are configured to transmit the scanning signal output by the gate driver circuit300to the plurality of scanning signal lines61and the plurality of reset signal lines62. For example, the plurality of scanning signal lead wires610may be located in the third conductive layer23. Referring toFIG.3andFIG.4, at least one of the plurality of scanning signal lead wires610crosses at least one load compensation unit1in the row direction X. For each row of sub-pixels, a scanning signal line61and a reset signal line62extending in the row direction X respectively provide a scanning signal and a reset signal to respective sub-pixels in the row. Correspondingly, the scanning signal lead wire610has an end electrically connected to the gate driver circuit300, and another end respectively electrically connected to the scanning signal line61and the reset signal line62through a signal transfer structure. As such, the scanning signal output by the gate driver circuit300are transmitted to the plurality of scanning signal lines61and the plurality of reset signal lines62. At the first rounded corner portion101and the second rounded corner portion102, since the load compensation units1are disposed between the gate driver circuit300and the respective rows of sub-pixels, a plurality of scanning signal lead wires610at the first rounded corner portion101and the second rounded corner portion102cross at least one load compensation unit1in the row direction X. For example, the scanning signal lead wire610may cross one load compensation unit1in the row direction X. Optionally, the scanning signal lead wire610may cross two adjacent load compensation units1in the row direction X. For example, an orthographic projection of at least one of the plurality of scanning signal lead wires610on the base substrate100at least partially overlaps with both orthographic projections of first compensation capacitor electrodes110of a plurality of compensation capacitors of the at least one load compensation unit1on the base substrate100and orthographic projections of second compensation capacitor electrodes120of a plurality of compensation capacitors of the at least one load compensation unit1on the base substrate100. In an embodiment of the present disclosure, a scanning signal lead wire for supplying the scanning signal is disposed above a load compensation unit to form an overlap between the scanning signal lead wire and the load compensation unit, so that the scanning signal lead wire may be compensated, and the stability of the scanning signal may be improved. FIG.15shows a schematic diagram of a sectional structure of a display substrate taken along line BB′ inFIG.4, according to some exemplary embodiments of the present disclosure. Referring toFIG.4andFIG.15in combination, in the load compensation unit1, the first compensation capacitor electrodes110of the plurality of compensation capacitors are arranged at intervals in the row direction X, so as to form a gap, such as the first gap14and the second gap15described above, between the plurality of first compensation capacitor electrodes110. At least one of the plurality of scanning signal lead wires610includes a first portion611. An orthographic projection of the first portion611on the base substrate100partially overlaps with an orthographic projection of the gap on the base substrate100. For example, the first portion611of the scanning signal lead wire610extends in a direction which is inclined with respect to each of the row direction X and the column direction Y. For example, at least one of the plurality of scanning signal lead wires610includes a first portion611and a second portion612. An orthographic projection of the first portion611on the base substrate100partially overlaps with an orthographic projection of the first gap14on the base substrate100, and an orthographic projection of the second portion612on the base substrate100partially overlaps with an orthographic projection of the second gap15on the base substrate100. For example, at least one of the first portion611and the second portion612of the scanning signal lead wire610extends in a direction inclined with respect to each of the row direction X and the column direction Y. Optionally, both of the first portion611and the second portion612of the scanning signal lead wire610extend in the direction inclined with respect to each of the row direction X and the column direction Y. Optionally, one of the first portion611and the second portion612of the scanning signal lead wire610extends in the direction inclined with respect to each of the row direction X and the column direction Y, and the other one of the first portion611and the second portion612extends in the row direction X. Continuing to refer toFIG.4, the display substrate may further include a plurality of initialization voltage lead wires660disposed on the base substrate100and located in the bezel area NA. The plurality of initialization voltage lead wires660are configured to transmit the initialization voltage signal to the initialization voltage lines66. For example, the plurality of initialization voltage lead wires660may be located in the third conductive layer23. Referring toFIG.3andFIG.4, at least one of the plurality of initialization voltage lead wires660crosses at least one load compensation unit1in the row direction X. For example, at the first rounded corner portion101and the second rounded corner portion102, a plurality of initialization voltage lead wires660at the first rounded corner portion101and the second rounded corner portion102cross at least one load compensation unit1in the row direction X. For example, the initialization voltage lead wire660may cross one load compensation unit1in the row direction X. Optionally, the initialization voltage lead wire660may cross two adjacent load compensation units1in the row direction X. For example, an orthographic projection of at least one of the plurality of initialization voltage lead wires660on the base substrate100at least partially overlaps with orthographic projections of first compensation capacitor electrodes110of a plurality of compensation capacitors of at least one load compensation unit1on the base substrate100and orthographic projections of second compensation capacitor electrodes120of the plurality of compensation capacitors of the at least one load compensation unit1on the base substrate100. In an embodiment of the present disclosure, an initialization voltage lead wire for supplying the initialization voltage signal is disposed above a load compensation unit to form an overlap between the initialization voltage lead wire and the load compensation unit, so that the initialization voltage lead wire may be compensated, and the stability of the initialization voltage signal may be improved. At least one of the plurality of initialization voltage lead wires660includes a first portion661. An orthographic projection of the first portion661on the base substrate100partially overlaps with the orthographic projection of the gap on the base substrate100. For example, the first portion661of the initialization voltage lead wire660extends in a direction inclined with respect to each of the row direction X and the column direction Y. For example, at least one of the plurality of initialization voltage lead wires660includes a first portion661and a second portion662. The orthographic projection of the first portion661on the base substrate100partially overlaps with the orthographic projection of the first gap14on the base substrate100, and an orthographic projection of the second portion662on the base substrate100partially overlaps with the orthographic projection of the second gap15on the base substrate100. For example, at least one of the first portion661and the second portion662of the initialization voltage lead wire660extends in the direction inclined with respect to each of the row direction X and the column direction Y. Optionally, both of the first portion661and the second portion662of the initialization voltage lead wire660extend in the direction inclined with respect to each of the row direction X and the column direction Y. Optionally, one of the first portion661and the second portion662of the initialization voltage lead wire660extends in the direction inclined with respect to each of the row direction X and the column direction Y, and the other one of the first portion661and the second portion662extends in the row direction X. Continuing to refer toFIG.3,FIG.4, andFIG.12toFIG.14, the orthographic projection of the first compensation capacitor electrode110on the base substrate100has a first size in the column direction Y. The first size of the orthographic projection of the first compensation capacitor electrode110on the base substrate100in the column direction Y may be represented by a size of an orthographic projection of the first electrode body111on the base substrate100in the column direction Y, namely H1inFIG.3. For example, a load compensation unit1and another adjacent load compensation unit1may partially overlap with each other in the column direction Y, and a size of the overlapping parts of the two adjacent load compensation units in the column direction Y may be less than or equal to half of the first size H1. For example, the size of the overlapping portion of the two adjacent load compensation units in the column direction Y may be less than or equal to half of the first size H1. For example, a load compensation unit1and another adjacent load compensation unit1may not overlap with each other in the column direction Y. That is, the load compensation unit1and the other load compensation unit1adjacent to the load compensation unit1may be spaced apart in the column direction Y. In the embodiments of the present disclosure, as described above, the reference pixel column includes N sub-pixels, and the edge pixel column includes M sub-pixels. When compensating the load on the data signal line, a value of the load required to be compensated may be determined according to a difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column. For the display substrate having the rounded rectangular shape as shown inFIG.1, since the difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column is small, the capacitance value of the compensation capacitor may be set small. In other words, an area of the overlap between a first compensation capacitor electrode110and a second compensation capacitor electrode120in each load compensation unit1is proportional to the number of missing pixel units of a column of pixel units corresponding to the load compensation unit1(i.e., (N−M)). In some exemplary embodiments, a capacitance value of each compensation capacitor may be less than a capacitance threshold. For example, the capacitance threshold may be about 5 fF. Since the capacitance value of the compensation capacitor is small, a mutual influence between adjacent compensation capacitors is also small. Accordingly, a gap between adjacent compensation capacitors may be set small. For example, in an embodiment of the present disclosure, each of a size of the first gap14in the row direction X and a size of the second gap15in the row direction X may be in a range from 1 microns to 6 microns. In addition, in an embodiment of the present disclosure, since the mutual influence between the adjacent compensation capacitors is small, the first gap14and the second gap15may not be provided with, for example, a partition member which is located in the semiconductor layer20and configured to isolate the adjacent compensation capacitors. That is, each of the orthographic projection of the first gap14on the base substrate100and the orthographic projection of the second gap15on the base substrate100does not overlap with an orthographic projection of the semiconductor layer20on the base substrate100. Through the above configurations, an area occupied by the load compensation unit may be reduced, which is conducive to a narrow bezel. At least some embodiments of the present disclosure further provide a display panel including the display substrate as described above. For example, the display panel may be an OLED display panel. Referring toFIG.1, at least some embodiments of the present disclosure further provide a display apparatus, which may include the display substrate as described above. The display apparatus includes the display area AA and the bezel area NA, and the bezel area NA has a small width, so that a display apparatus with a narrow bezel may be achieved. The display apparatus may include any apparatus or product with a display function. For example, the display apparatus may be a smart phone, a mobile phone, an e-book reader, a personal computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical apparatus, a camera, a wearable device (such as a head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smart watch), a television, etc. It should be understood that the display apparatus according to the embodiments of the present disclosure has all the features and advantages of the display substrate described above. Details may be referred to the above description and will not be repeated here. Although some embodiments of a general technical concept of the present disclosure have been illustrated and described, it should be understood by those ordinary skilled in the art that these embodiments may be changed without departing from the principle and spirit of the general technical concept of the present disclosure. The scope of the present disclosure is defined by the claims and their equivalents. | 64,086 |
11943982 | DETAILED DESCRIPTION Hereinafter, display devices and methods of manufacturing display devices in embodiments will be explained in detail with reference to the accompanying drawings. It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. In an embodiment, when the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below. “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In an embodiment, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims. Hereinafter, a display device in an embodiment will be described with reference toFIGS.1to5. FIG.1is a plan view illustrating an embodiment of a display device. Referring toFIG.1, a display device100may include a display area DA and a non-display area NDA. Pixels for emitting light may be disposed in the display area DA. The non-display area NDA may surround at least a portion of the display area DA. In an embodiment, the non-display area NDA may entirely surround the display area DA. Drivers providing control signals to the pixels and pads providing signals to the pixels and connected to an integrated circuit, a printed circuit board, etc., may be disposed in the non-display area NDA. In an embodiment, the display device100may divided into a first area1A, a second area2A, and a bendable area BA. The second area2A may be spaced apart from the first area1A. The bendable area BA may be disposed between the first area1A and the second area2A. The bendable area BA may be bent. In an embodiment, the bendable area BA may be bent such that the first area1A and the second area2A face each other. In an embodiment, the display area DA may be disposed inside the first area1A, and the non-display area NDA may include a portion of the first area1A other than the display area DA, the second area2A, and the bendable area BA. In an embodiment, the drivers may be disposed in the portion of the first area1A other than the display area DA, the pads may be disposed in the second area2A, and wirings connecting the pixels and the pads may be disposed in the bendable area BA, for example. FIG.2is a cross-sectional view illustrating an embodiment of the display device100taken along line I-I′ and line II-IF inFIG.1. Referring toFIG.2, the display device100may include a base substrate110, a buffer layer120, an active layer130, a first gate insulation layer140, a first gate line150, a second gate insulation layer160, a second gate line170, an inter-insulation layer180, a stress relaxation layer190, a conductive line200, a planarization layer210, a first electrode220, a pixel defining layer230, an emission layer240, and a second electrode250. In an embodiment, the base substrate110may be a flexible substrate. In an embodiment, the base substrate110may include an organic material. In such an embodiment, the display device100may be a flexible display device, for example. In an embodiment, the base substrate110may include a first organic layer111, a first barrier layer112, a second organic layer113, and a second barrier layer114. The first barrier layer112may be disposed on the first organic layer111. The second organic layer113may be disposed on the first barrier layer112. The second barrier layer114may be disposed on the second organic layer113. Each of the first organic layer111and the second organic layer113may include an organic material such as a photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, or the like. In an embodiment, the polyimide resin may be a random copolymer or a block copolymer, for example. Each of the first barrier layer112and the second barrier layer114may include an inorganic material such as a silicon compound, a metal oxide, or the like. In an embodiment, each of the first barrier layer112and the second barrier layer114may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride. (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or the like, for example. Since the base substrate110includes the first organic layer111and the second organic layer113, the base substrate110may have a flexible characteristic. Further, the first barrier layer112and the second barrier layer114may block moisture penetrating through the first organic layer111and the second organic layer113. The buffer layer120may be disposed on the base substrate110. The buffer layer120may planarize over the base substrate110, and may block impurities from flowing into the active layer130from the base substrate110in a process of heat-treating the active layer130. The buffer layer120may include a plurality of layers. In an embodiment, the buffer layer120may include a first buffer layer121and a second buffer layer122. The second buffer layer122may be disposed on the first buffer layer121. In an embodiment, the first buffer layer121may include silicon oxide (SiOx). In an embodiment, the second buffer layer122may include silicon nitride (SiNx). The active layer130may be disposed on the buffer layer120in the display area DA. In an embodiment, the active layer130may include polycrystalline silicon. However, the invention is not limited thereto, and in another embodiment, the active layer130may include amorphous silicon, an oxide semiconductor, or the like. The active layer130may include a source region, a drain region, and a channel region. The drain region may be spaced apart from the source region. The channel region may be disposed between the source region and the drain region. Impurities may be doped into the source region and the drain region. The first gate insulation layer140may be disposed on the active layer130. The first gate insulation layer140may cover the active layer130, and may be disposed on the buffer layer120. The first gate insulation layer140may include an inorganic material such as a silicon compound, a metal oxide, or the like. In an embodiment, the first gate insulation layer140may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride. (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or the like, for example. The first gate line150may be disposed on the first gate insulation layer140in the display area DA. A portion of the first gate line150may overlap the channel region of the active layer130. In an embodiment, the first gate line150may transmit a scan signal. The active layer130and the first gate line150may form at least one thin film transistor (“TFT”). In an embodiment, the first gate line150may include molybdenum (Mo). In an embodiment, when the first gate line150includes aluminum (Al), a void defect may occur in the first gate line150due to a high temperature process performed during the manufacturing process of the display device100. In an embodiment, when the first gate line150is provided as a multilayer including a layer including aluminum (Al) and a capping layer including titanium (Ti) or titanium nitride (TiN), the first gate line150may block dispersion of hydrogen, and thus, hydrogen inflow into the active layer130or hydrogen outflow from the active layer130may decrease. In this case, a driving range of the TFT may decrease, and an instantaneous afterimage of the display device100may increase. The second gate insulation layer160may be disposed on the first gate line150. The second gate insulation layer160may cover the first gate line150, and may be disposed on the first gate insulation layer140. The second gate insulation layer160may include an inorganic material such as a silicon compound, a metal oxide, or the like. In an embodiment, the second gate insulation layer160may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or the like, for example. The second gate line170may be disposed on the second gate insulation layer160in the display area DA. Although it is not illustrated inFIG.2, a portion of the second gate line170may overlap the channel region of the active layer130. The active layer130and the second gate line170may form at least one TFT. Further, the first gate line150and the second gate line170may form at least one capacitor. In an embodiment, the second gate line170may include aluminum (Al) or aluminum alloy. In an embodiment, when the second gate line170includes molybdenum (Mo), a stress applied to the second gate line170may increase due to external impact, and accordingly, a crack defect may occur in the second gate line170. FIG.3is a cross-sectional view illustrating an embodiment of the second gate line170inFIG.2. Referring toFIG.3, in an embodiment, the second gate line170may include a first layer171and a second layer172disposed on the first layer171. In such an embodiment, the second gate line170may have a multilayer structure including two conductive layers. In an embodiment, the first layer171may include aluminum (Al) or aluminum alloy. In an embodiment, the second layer172may include titanium (Ti) or titanium nitride (TiN). In an embodiment, a thickness of the second layer172may be less than a thickness of the first layer171. In an embodiment, the thickness of the first layer171may be about 1500 angstroms (Å) to about 3000 Å, and the thickness of the second layer172may be about 300 Å, for example. In such an embodiment, the first layer171may serve as a main conductive layer of the second gate line170, and the second layer172may serve as a capping layer for protecting the first layer171. FIG.4is a cross-sectional view illustrating another embodiment of the second gate line170inFIG.2. Referring toFIG.4, in an embodiment, the second gate line170may include a first layer171, a second layer172disposed on the first layer171, and a third layer173disposed on the second layer172. In such an embodiment, the second gate line170may have a multilayer structure including three conductive layers. In an embodiment, the first layer171may include aluminum (Al) or aluminum alloy. In an embodiment, the second layer172may include titanium (Ti) or titanium nitride (TiN). The third layer173may include titanium (Ti) or titanium nitride (TiN). In an embodiment, the second layer172may include one of titanium (Ti) and titanium nitride (TiN), and the third layer173may include another one of titanium (Ti) and titanium nitride (TiN). In an embodiment, the third layer173may include titanium nitride (TiN) when the second layer172includes titanium (Ti), and the third layer173may include titanium (Ti) when the second layer172includes titanium nitride (TiN), for example. In an embodiment, a thickness of the second layer172and a thickness of the third layer173may be less than a thickness of the first layer171in a thickness direction (e.g., vertical direction inFIG.4). In such an embodiment, the first layer171may serve as a main conductive layer of the second gate line170, and each of the second layer172and the third layer173may serve as a capping layer for protecting the first layer171. Referring toFIG.2again, the insulation interlayer180may be disposed on the second gate line170. The insulation interlayer180may cover the second gate line170, and may be disposed on the second gate insulation layer160. The insulation interlayer180may include an inorganic material such as a silicon compound, a metal oxide, or the like. In an embodiment, the insulation interlayer180may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), or the like, for example. An active contact hole ACH may be defined in the insulation interlayer180, the second gate insulation layer160, and the first gate insulation layer140. The active contact hole ACH may pass through the insulation interlayer180, the second gate insulation layer160, and the first gate insulation layer140, and may expose the active layer130. In an embodiment, the active contact hole ACH may expose the source region or the drain region of the active layer130, for example. A first gate contact hole GCH1may be defined in the insulation interlayer180and the second gate insulation layer160. The first gate contact hole GCH1may pass through the insulation interlayer180and the second gate insulation layer160, and may expose the first gate line150. A second gate contact hole GCH2may be defined in the insulation interlayer180. The second gate contact hole GCH2may pass through the insulation interlayer180, and may expose the second gate line170. A first opening OP1may be defined in the insulation interlayer180, the second gate insulation layer160, the first gate insulation layer140, and a first portion of the buffer layer120. The first opening OP1may overlap the bendable area BA. In an embodiment, the active contact hole ACH, the first gate contact hole GCH1, and the first opening OP1may be substantially simultaneously defined. The formation of the active contact hole ACH, the first gate contact hole GCH1, and the first opening OP1will be described with reference toFIGS.9to15below. In an embodiment, the first portion of the buffer layer120may be the second buffer layer122. In other words, the first opening OP1may be defined in the insulation interlayer180, the second gate insulation layer160, the first gate insulation layer140, and the second buffer layer122. A second opening OP2may be defined in a second portion of the buffer layer120and a portion of the base substrate110. The second opening OP2may overlap the bendable area BA. The second portion of the buffer layer120may be a portion of the buffer layer120other than the first portion of the buffer layer120. In an embodiment, the second gate contact hole GCH2and the second opening OP2may be substantially simultaneously defined. The formation of the second gate contact hole GCH2and the second opening OP2will be described with reference toFIGS.9to15below. In an embodiment, the second portion of the buffer layer120may be the first buffer layer121, and the portion of the base substrate110may be the second barrier layer114. In other words, the second opening OP2may be defined in the first buffer layer121and the second barrier layer114. In an embodiment, a width of the first opening OP1may be greater than a width of the second opening OP2in a direction parallel to main plane extension direction (e.g., horizontal direction inFIG.2). In such an embodiment, a lateral part of the second portion of the buffer layer120and the portion of the base substrate110exposed by the second opening OP2may protrude from a lateral part of the insulation interlayer180, the second gate insulation layer160, the first gate insulation layer140, and the first portion of the buffer layer120. In an embodiment, a lateral part of the first buffer layer121may protrude from a lateral part of the second buffer layer122, for example. Further, the first opening OP1may expose an upper surface of the second portion of the buffer layer120. In an embodiment, the first opening OP1may expose an upper surface of the first buffer layer121, for example. The stress relaxation layer190may be disposed on the insulation interlayer180in the bendable area BA. The stress relaxation layer190may fill the first opening OP1and the second opening OP2. The stress relaxation layer190may include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, or the like. When a layered-structure is bent, a stress neutral plane may exist within the layered-structure. When the stress relaxation layer190does not exist, excessive tensile stress or the like may be applied to lines in the bendable area BA when the display device100is bent, because the positions of the lines may not correspond to the stress neutral plane. However, by disposing the stress relaxation layer190in the bendable area BA and adjusting the thickness and modulus of the stress relaxation layer190, the position of the stress neutral plane in the layered-structure included in the display device100may be adjusted. Accordingly, the stress-neutral plane may be positioned in the vicinity of the lines due to the stress relaxation layer190, thereby minimizing tensile stress applied to the lines. The conductive line200may be disposed on the insulation interlayer180in the display area DA. In an embodiment, the conductive line200may include at least one of aluminum (Al) and titanium (Ti). In an embodiment, the conductive line200may have a multilayer structure including a titanium (Ti) layer, an aluminum (Al) layer, and a titanium (Ti) layer that are sequentially stacked. In such an embodiment, the aluminum (Al) layer may serve as a main conductive layer of the conductive line200, and each of the titanium (Ti) layers may serve as a capping layer for protecting the aluminum (Al) layer. The conductive line200may include a first conductive line201, a second conductive line202, and a third conductive line203. The first conductive line201may be connected to the active layer130through the active contact hole ACH. In an embodiment, the first conductive line201may transmit a data voltage. The second conductive line202may be connected to the first gate line150through the first gate contact hole GCH1. The third conductive line203may be connected to the second gate line170through the second gate contact hole GCH2. In an embodiment, the third conductive line203may transmit a first power voltage. In an embodiment, the third conductive line203may directly contact the second gate line170through the second gate contact hole GCH2. In such an embodiment, corrosions of aluminum (Al) or titanium (Ti) may not exist on the second gate line170exposed by the second gate contact hole GCH2, and accordingly, the third conductive line203may directly contact the second gate line170. The planarization layer210may be disposed on the stress relaxation layer190and the conductive line200. The planarization layer210may cover the stress relaxation layer190and the conductive line200, and may be disposed on the insulation interlayer180. The planarization layer210may include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, or the like. The first electrode220may be disposed on the planarization layer210in the display area DA. The first electrode220may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in any combinations thereof. In an embodiment, the first electrode220may include silver (Ag), indium tin oxide (“ITO”), or the like, for example. The pixel defining layer230may be disposed on the first electrode220in the display area DA. The pixel defining layer230may partially cover the first electrode220, and may be disposed on the planarization layer210. In an embodiment, an opening exposing a central portion of the first electrode220may be defined in the pixel defining layer230, and the pixel defining layer230may cover a peripheral portion of the first electrode220. The pixel defining layer230may include an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, or the like. The emission layer240may be disposed on the first electrode220in the opening of the pixel defining layer230. The emission layer240may include at least one of an organic light emitting material and a quantum dot. In an embodiment, the organic light emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. In an embodiment, the low molecular weight organic compound may include copper phthalocyanine, N,N′-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, or the like, and the high molecular organic compound may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, or the like, for example. In an embodiment, the quantum dot may include a core including a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core, and as a charging layer for imparting electrophoretic properties to the quantum dot. The second electrode250may be disposed on the pixel defining layer230and the emission layer240. The second electrode250may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in any combinations thereof. In an embodiment, the second electrode250may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), or the like, for example. A second power voltage may be applied to the second electrode250. In an embodiment, the second power voltage may be lower than the first power voltage. The first electrode220, the emission layer240, and the second electrode250may form a light emitting element EL. FIG.5is a cross-sectional view illustrating another embodiment of the display device100taken along line I-I′ and line II-IF inFIG.1. Another embodiment of the display device described with reference toFIG.5may be substantially the same as or similar to the embodiment of the display device described with reference toFIG.2except for the thickness of the second gate line. Accordingly, descriptions on repeated elements will be omitted. Referring toFIG.5, in an embodiment, a thickness Th2of the second gate line170′ may be less than a thickness Th1of the first gate line150. In an embodiment, the thickness Th1of the first gate line150may be about 2500 Å, and the thickness Th2of the second gate line170′ may be about 700 Å to about 800 Å, for example. In an embodiment, an electrical resistance of the second gate line170′ may be substantially equal to an electrical resistance of the first gate line150. A resistivity of aluminum (Al) included in the second gate line170′ is less than a resistivity of molybdenum (Mo) included in the first gate line150, however, the thickness of the second gate line170′ may be less than the thickness of the first gate line150, so that the electrical resistance of the second gate line170′ may be substantially equal to the electrical resistance of the first gate line150. Hereinafter, a display device in an embodiment will be described with reference toFIGS.6to8. Descriptions on elements of the display device101described with reference toFIGS.6to8, which are substantially the same as or similar to those of the display device100described with reference toFIGS.1to5, will not be repeated. FIG.6is a plan view illustrating an embodiment of a display device. Referring toFIG.6, a pad portion PP and a wiring portion WP may be disposed in the non-display area NDA. The pads for providing signals to the pixels that are disposed in the display area DA may be disposed in the pad portion PP, and the lines for connecting the pixels and the pads may be disposed in the wiring portion WP. The lines may transmit the signals from the pads to the pixels. The signals may include the data voltage, the first power voltage, the second power voltage, and various control signals. FIG.7is a cross-sectional view illustrating an embodiment of the display device101taken along line and line IV-IV′ inFIG.6. Referring toFIG.7, the display device101may include a base substrate110, a buffer layer120, an active layer130, a first gate insulation layer140, a first gate line150, a first signal line155, a second gate insulation layer160, a second gate line170, a second signal line175, an inter-insulation layer180, a conductive line200, a third signal line205, a planarization layer210, a first electrode220, a pixel defining layer230, an emission layer240, and a second electrode250. The display device101described with reference toFIG.7may be substantially the same as or similar to the display device100described with reference toFIG.2except for the omission of the first opening OP1, the second opening OP2and the stress relaxation layer190, the addition of the first signal line155, the second signal line175and the third signal line205, and elements of the base substrate110. Accordingly, descriptions on repeated elements will be omitted. In an embodiment, the base substrate110may be a rigid substrate. In an embodiment, the base substrate110may include glass, quartz, metal, or the like. In such an embodiment, the display device101may be a rigid display device, for example. The first signal line155may be disposed in the same layer as the first gate line150in the non-display area NDA, and may include the same material as that of the first gate line150. In other words, the first signal line155may be disposed between the first gate insulation layer140and the second gate insulation layer160, and may include molybdenum (Mo). In an embodiment, a conductive layer including molybdenum (Mo) may be disposed on the first gate insulation layer140, and the conductive layer may be patterned to substantially simultaneously form the first gate line150and the first signal line155, for example. In an embodiment, the first signal line155may transmit a signal applied to at least one of the first gate line150, the second gate line170, and the conductive line200. In an embodiment, the first signal line155may transmit at least one of the data voltage, the first power voltage, the second power voltage, and the control signals, for example. The second signal line175may be disposed in the same layer as the second gate line170in the non-display area NDA, and may include the same material as that of the second gate line170. In other words, the second signal line175may be disposed between the second gate insulation layer160and the insulation interlayer180, and may include aluminum (Al) or an aluminum alloy. In an embodiment, a conductive layer including aluminum (Al) or an aluminum alloy may be disposed on the second gate insulation layer160, and the conductive layer may be patterned to substantially simultaneously form the second gate line170and the second signal line175, for example. In an embodiment, a width155W of the first signal line155may be greater than a width175W of the second signal line175. In an embodiment, the width155W of the first signal line155may be about 5.0 micrometers (μm), and the width175W of the second signal line175may be about 2.2 μm, for example. A resistivity of molybdenum (Mo) included in the first signal line155is greater than a resistivity of aluminum (Al) included in the second signal line175, however, the width155W of the first signal line155may be greater than the width175W of the second signal line175, so that the signal transmitted by the first signal line155may not be delayed. The third signal line205may be disposed in the same layer as the conductive line200in the non-display area NDA, and may include the same material as that of the conductive line200. In other words, the third signal line205may be disposed between the insulation interlayer180and the planarization layer210, and may include aluminum (Al) and titanium (Ti). In an embodiment, a conductive layer including aluminum (Al) and titanium (Ti) may be disposed on the insulation interlayer180, and the conductive layer may be patterned to substantially simultaneously form the conductive line200and the third signal line205, for example. FIG.8is a cross-sectional view illustrating another embodiment of the display device101taken along line and line IV-IV′ inFIG.6. Another embodiment of the display device described with reference toFIG.8may be substantially the same as or similar to the embodiment of the display device described with reference toFIG.7except for the width of the first signal line. Accordingly, descriptions on repeated elements will be omitted. Referring toFIG.8, in an embodiment, a width155W′ of the first signal line155′ may be substantially equal to a width175W of the second signal line175. In an embodiment, each of the width155W′ of the first signal line155′ and the width175W of the second signal line175may be about 2.2 μm, for example. In an embodiment, the third signal line205may transmit a signal applied to at least one of the first gate line150, the second gate line170, and the conductive line200. In an embodiment, the third signal line205may transmit at least one of the data voltage, the first power voltage, the second power voltage, and the control signals, for example. Hereinafter, a method of manufacturing a display device in an embodiment will be described with reference toFIGS.9to15. FIGS.9,10,11,12,13,14, and15are cross-sectional views illustrating an embodiment of a method of manufacturing a display device. In an embodiment,FIGS.9to15may illustrate a method of manufacturing the display device100described with reference toFIGS.1to5. Referring toFIG.9, the buffer layer120, the active layer130, the first gate insulation layer140, the first gate line150, the second gate insulation layer160, the second gate line170, and the insulation interlayer180may be sequentially disposed on the base substrate110. First, the buffer layer120may be disposed on the base substrate110. In an embodiment, the base substrate110may include the first organic layer111, the first barrier layer112disposed on the first organic layer111, the second organic layer113disposed on the first barrier layer112, and the second barrier layer114disposed on the second organic layer113. In an embodiment, the buffer layer120may include the first buffer layer121and the second buffer layer122disposed on the first buffer layer121. Then, the active layer130may be disposed on the buffer layer120, and the first gate insulation layer140may be disposed on the active layer130. The active layer130may be disposed in the display area DA. Then, the first gate line150may be disposed on the first gate insulation layer140, the second gate insulation layer160may be disposed on the first gate line150, and the second gate line170may be disposed on the second gate insulation layer160. The first gate line150and the second gate line170may be disposed in the display area DA. In an embodiment, the first gate line150may include molybdenum (Mo), and the second gate line170may include aluminum (Al) or an aluminum alloy. Then, the insulation interlayer180may be disposed on the second gate line170. Referring toFIG.10, the active contact hole ACH exposing the active layer130may be defined in the insulation interlayer180, the second gate insulation layer160, and the first gate insulation layer140, the first gate contact hole GCH1exposing the first gate line150may be defined in the insulation interlayer180and the second gate insulation layer160, and the first opening OP1overlapping the bendable area BA may be defined in the insulation interlayer180, the second gate insulation layer160, the first gate insulation layer140, and a first portion of the buffer layer120. The active contact hole ACH, the first gate contact hole GCH1, and the first opening OP1may be substantially simultaneously defined. In an embodiment, the first portion of the buffer layer120may be the second buffer layer122. In other words, the first opening OP1may be defined in the insulation interlayer180, the second gate insulation layer160, the first gate insulation layer140, and the second buffer layer122. Referring toFIG.11, after substantially simultaneously defining the active contact hole ACH, the first gate contact hole GCH1, and the first opening OP1, the active layer130may be heat-treated. When the active layer130is heat-treated, electrical characteristics of at least one TFT provided by the active layer130and the first gate line150and electrical characteristics of at least one TFT provided by the active layer130and the second gate line170may be improved. In an embodiment, when the TFTs include a driving TFT and a switching TFT, by the heat-treatment of the active layer130, a driving range of the driving TFT may be widened, and a deviation of a threshold voltage of the switching TFT may decrease. An oxide layer OXL may be disposed on the active layer130in the process of heat-treating the active layer130. In an embodiment, in the process of heat-treating the active layer130, oxygen ions may react with an upper surface of the active layer130exposed by the active contact hole ACH to form the oxide layer OXL, for example. Referring toFIG.12, the oxide layer OXL disposed on the active layer130by the heat-treatment may be removed. In an embodiment, the oxide layer OXL may be removed with a buffered oxide etchant (“BOE”) or hydrogen fluoride (“HF”). Referring toFIG.13, the second gate contact hole GCH2exposing the second gate line170may be defined in the insulation interlayer180, and the second opening OP2overlapping the bendable area BA may be defined in a second portion of the buffer layer120and a portion of the base substrate110. The second gate contact hole GCH2and the second opening OP2may be substantially simultaneously defined. In an embodiment, the second portion of the buffer layer120may be the first buffer layer121, and the portion of the base substrate110may be the second barrier layer114. In other words, the second opening OP2may be defined in the first buffer layer121and the second barrier layer114. In the prior art, after substantially simultaneously defining the active contact hole ACH, the first gate contact hole GCH1, the second gate contact hole GCH2, and the first opening OP1, the oxide layer OXL disposed in the active contact hole ACH may be removed with BOE or HF. In the prior art, the second gate line170exposed by the second gate contact hole GCH2may be damaged by BOE or HF. In the embodiments of the invention, after removing the oxide layer OXL disposed in the active contact hole ACH with BOE or HF, the second gate contact hole GCH2may be defined, so that the second gate line170exposed by the second gate contact hole GCH2may not be damaged by BOE or HF. Further, since the second gate contact hole GCH2is substantially simultaneously defined with the second opening OP2, an additional process for defining the second opening OP2may not be desired. Referring toFIG.14, the stress relaxation layer190may be disposed on the insulation interlayer180in the bendable area BA. The stress relaxation layer190may fill the first opening OP1and the second opening OP2. Referring toFIG.15, the conductive line200may be disposed on the insulation interlayer180in the display area DA. The conductive line200may be connected to the active layer130through the active contact hole ACH, may be connected to the first gate line150through the first gate contact hole GCH1, and may directly contact the second gate line170through the second gate contact hole GCH2. FIG.16is a cross-sectional view illustrating an embodiment of a display device. The display device102described with reference toFIG.16may be substantially the same as or similar to the display device100described with reference toFIGS.2to4except for the addition of an encapsulation layer260, a color conversion member300, and a filling layer400. Accordingly, descriptions on repeated elements will be omitted. Referring toFIG.16, the display device102may further include an encapsulation layer260, a color conversion member300, and a filling layer400. The encapsulation layer260may be disposed on the second electrode250. The encapsulation layer260may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer260may have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are sequentially stacked. The color conversion member300may be disposed on the encapsulation layer260. The color conversion member300may receive light from the light emitting element EL, and may convert a color of the light or transmit the light. In an embodiment, the color conversion member300may receive blue light from the light emitting element EL, and may convert the blue light into red light or green light, or transmit the blue light. The color conversion member300may include a substrate310, a color filter320, a partition wall330, an optical filter340, and a planarization layer350. The substrate310may be a transparent insulation substrate. In an embodiment, the substrate310may include glass, plastic, quartz, or the like, for example. The color filter320may be disposed under the substrate310. The color filter320may selectively transmit light of a predetermined wavelength band. The color filter320may be provided as an organic material pattern including a dye or pigment. The optical filter340may be disposed under the color filter320. The optical filter340may be provided with an inkjet manner in a space defined by the partition wall330. The optical filter340may convert a color of light incident on the optical filter340or transmit the light. In an embodiment, the optical filter340may convert blue light incident on the optical filter340into red light or green light or transmit the blue light. The partition wall330may be disposed under the color filter320, and may surround the optical filter340. The partition wall330may overlap the pixel defining layer230. The partition wall330may have a reverse-tapered cross-sectional shape in which a width of the partition wall330decreases as distancing from the substrate310. The planarization layer350may be disposed under the partition wall330and the optical filter340. In an embodiment, the planarization layer350may include an inorganic insulation material such as silicon nitride and/or silicon oxide. In another embodiment, the planarization layer350may include an organic insulation material such as polyimide resin, acrylic resin, or the like. The filling layer400may be disposed between the encapsulation layer260and the color conversion member300. The filling layer400may include a photocurable epoxy-based material, an acrylate-based material, or the like. The color conversion member300may be provided separately from the encapsulation layer260on the base substrate110, and then may be combined to the encapsulation layer260with the filling layer400interposed therebetween. FIG.17is a cross-sectional view illustrating an embodiment of a display device. Descriptions on elements of the display device103described with reference toFIG.17, which are substantially the same as or similar to those of the display device102described with reference toFIG.16, will not be repeated. Referring toFIG.17, the display device103may include a color conversion member301. The color conversion member301may include a color filter320, a partition wall330, an optical filter340, and a cover layer360. The optical filter340may be disposed on the encapsulation layer260. The partition wall330may be disposed on the encapsulation layer260, and may surround the optical filter340. The partition wall330may have a forward-tapered cross-sectional shape in which a width of the partition wall330decreases as distancing from the encapsulation layer260. The color filter320may be disposed on the partition wall330and the optical filter340. The cover layer360may be disposed on the color filter320. The cover layer360may protect the color filter320, the partition wall330, and the optical filter340. The cover layer360may include a high-hardness polymer material such as siloxane or the like. The color conversion member301may be disposed on the encapsulation layer260. Specifically, the partition wall330, the optical filter340, the color filter320, and the cover layer360may be sequentially disposed on the encapsulation layer260. The display device in the embodiments may be applied to a display device included in a computer, a notebook, a mobile phone, a smartphone, a smart pad, a portable media player (“PMP”), a personal digital assistance (“PDA”), an MP3 player, or the like. Although the display devices and the methods of manufacturing the display devices in the embodiments have been described with reference to the drawings, the illustrated embodiments are examples, and may be modified and changed by a person having ordinary knowledge in the relevant technical field without departing from the technical spirit of the invention. | 45,607 |
11943983 | DETAILED DESCRIPTION In order to further illustrate a display substrate, a method for manufacturing the same and a display device provided by the embodiments of the present disclosure, a detailed description will be given below with reference to the accompanying drawings. The structure of the AMOLED display panel includes a substrate, a plurality of sub-pixel driving circuits arranged on the substrate, and a plurality of light emitting elements arranged on a side of the sub-pixel driving circuit away from the substrate. The sub-pixel driving circuits have a one-to-one correspondence with the plurality of light emitting elements, and the sub-pixel driving circuit is used to drive a corresponding light emitting element to emit light, so as to realize the display function of the display panel. In the related art, the sub-pixel driving circuit generally includes a plurality of thin film transistors, as shown inFIG.1a. When the sub-pixel driving circuit includes 7 thin film transistors Q1to Q7, the specific layout of the 7 thin film transistors is shown inFIG.1a. With this layout, the sub-pixel driving circuit includes an active layer as shown inFIG.1b, a first metal layer as shown inFIG.1c, and a second metal layer as shown in FIG.1d, and a third metal layer as shown inFIG.1e. The active layer includes an active pattern used to form a channel region of each thin film transistor (the part within the dashed box inFIG.1b), and a doped active pattern electrically connected to the active pattern, the doped active pattern has conductive properties (the part outside the dashed box inFIG.1b); the first metal layer includes a gate electrode of each thin film transistor, a scan signal line GATE electrically connected to the gate electrode, an electrode plate CE1of a storage capacitor in the sub-pixel driving circuit, a reset signal line RST, and a light emitting control signal line EM. The second metal layer includes an initialization signal line VINT, another electrode plate CE2of the storage capacitor in the sub-pixel driving circuit. The third metal layer includes a data line DATA, a power signal line VDD, and some conductive connection portions (marked as341to343). As shown inFIG.1, in the layout of the sub-pixel driving circuit, in order to realize the electrical connection between the functional patterns arranged in different layers, some via holes (marked as381to388) can also be set. When the sub-pixel driving circuit in the related art implements high-frequency driving, since the data writing time of each row of pixels controlled by the pixel driving circuit is short, it is easy to cause the problem of insufficient data writing time for each row of pixels. Referring toFIGS.2to4, the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arranged on the substrate in an array, the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels arranged in sequence along a second direction, and a plurality of columns of sub-pixels arranged in sequence along a first direction, each sub-pixel includes: a light emitting element, an initialization signal line pattern94, a reset signal line pattern95, a gate line pattern92, and a light emitting control signal line pattern93. The plurality of sub-pixels include a first sub-pixel and a second sub-pixel alternately arranged along the second direction, the first sub-pixel includes a first data line pattern981, the second sub-pixel includes a second data line pattern982, and at least part of the first data line981and at least part of the second data line pattern982extend along the second direction, and the first data line pattern981is located at a first side of a same column of first sub-pixels extending along the second direction, the second data line pattern982is located at a second side of a same column of second sub-pixels extending along the second direction, and the first side and the second side are opposite to each other along the first direction, the first direction intersects the second direction. Exemplarily, the first side is the right side inFIG.4, and the second side is the left side inFIG.4. The first sub-pixel and the second sub-pixel both include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor (that is, a third transistor T3) and a data writing transistor (that is, a fourth transistor T4). In the first sub-pixel, a first electrode of the data writing transistor is electrically connected to the first data line pattern981, and a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor. In the second sub-pixel, the first electrode of the data writing transistor is electrically connected to the second data line pattern982, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor. According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the present disclosure, among the same column of sub-pixels extending along the second direction, a first electrode of a data writing transistor included in one of two adjacent sub-pixels is electrically connected to the first data line pattern981, and a first electrode of a data writing transistor included in the other sub-pixel of the two adjacent sub-pixels is electrically connected to the second data line pattern982. In the display substrate provided by the present disclosure, by arranging data writing transistors of adjacent sub-pixels in the same column of sub-pixels to be connected to different data line patterns, data signals are applied to adjacent sub-pixels in the same column of sub-pixels by different data line patterns, so as to ensure that each sub-pixel has enough data signal writing time, thereby solving the problem of insufficient data signal writing time for each row of sub-pixels when the high frequency display mode is adopted in the display substrate. However, in the above-mentioned display substrate, since the power signal line patterns included in each sub-pixel in each row of sub-pixels are independent of each other, the display uniformity of the display substrate is poor, which is not conducive to improving the display image quality of the display substrate. Referring toFIGS.5,12,13c, and13d, an embodiment of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels including: a first sub-pixel M1and a second sub-pixel M2arranged along a second direction. The first sub-pixel M1includes a first data line pattern981, and the second sub-pixel M2includes a second data line pattern982. The first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel; at least part of the first data line pattern981and at least part of the second data line pattern982both extend along the second direction, and the first data line pattern981is located on a first side of the same column of the first sub-pixels extending along the second direction, the second data line pattern982is located on a second side of the same column of second sub-pixels extending along the second direction, the first side and the second side are opposite to each other along the first direction, intersects to each other. As shown inFIGS.5,8,10,12, and19, the first sub-pixel M1and the second sub-pixel M2both include: a power signal line pattern91, at least part of the power signal line pattern91extends along the second direction; a power compensation pattern97, at least part of the power compensation pattern97extends along the first direction, and the power signal line pattern and the power compensation pattern are both located on a side of the first data line pattern and the second data line pattern close to the substrate, the power compensation pattern97is electrically connected to the power signal line pattern91and the power signal line pattern91in adjacent sub-pixels along the first direction. Specifically, the display substrate includes a plurality of sub-pixels arranged on a substrate in an array, and the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels include a plurality of the sub-pixels sequentially arranged along the first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels include a plurality of sub-pixels sequentially arranged along a second direction. Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction. At least part of the first data line pattern981and at least part of the second data line pattern982extend along the second direction. The first data line patterns981included in the first sub-pixels M1in the same column of sub-pixels are electrically connected in sequence to form an integral structure. The second data line patterns982included in the second sub-pixels M2in the same column of sub-pixels are electrically connected in sequence to form an integral structure. Exemplarily, as shown inFIG.15, the first data line pattern981is a data line portion between a data writing position of a current first sub-pixel M1(for example, the position where a data line protrusion9802is located) and a data writing position of an adjacent first sub-pixel M1in the next row along the second direction. Exemplarily, in the same column of sub-pixels, the first sub-pixel M1and the second sub-pixel M2are alternately arranged. Exemplarily, in the same column of sub-pixels, the first sub-pixel M1is an odd-numbered sub-pixel, and the odd-numbered sub-pixel receives the first data signal provided by the first data line pattern981included therein, and the second sub-pixel. The pixel M2is an even-numbered sub-pixel, and the even-numbered sub-pixel receives the second data signal provided by the second data line pattern982included therein. Exemplarily, the first side is the right side inFIG.5, and the second side is the left side inFIG.5. In the same column of sub-pixels, the first data line pattern981is located at the first side of the same column of sub-pixels, and the second data line pattern982is located at the second side of the same column of sub-pixels. Each of the first sub-pixel M1and the second sub-pixel M2includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and a plurality of thin film transistors. As shown inFIG.2andFIG.5, exemplarily, the sub-pixel driving circuit includes 7T1C, that is, seven transistors and one storage capacitor. The sub-pixel driving circuit is used to generate a driving signal for driving the light emitting element to emit light. Exemplarily, the sub-pixel driving circuit includes a driving transistor and a data writing transistor. In the first sub-pixel M1, a first electrode of the data writing transistor is electrically connected to the first data line pattern981. In the second sub-pixel M2, a first electrode of the data writing transistor is electrically connected to the second data line pattern982. In each sub-pixel, a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the data writing transistor can transmit the data signal received by the first electrode thereof to the first electrode of the driving transistor. In the same column of sub-pixels, the data line patterns electrically connected to the first electrodes of the data writing transistors in adjacent sub-pixels are different. In more detail, in the same column of sub-pixels, the first electrode of the data writing transistor included in one of the adjacent sub-pixels is electrically connected to the first data line pattern981, and the first electrode of the data writing transistor included in the other of the adjacent sub-pixels is electrically connected to the second data line pattern982. Each sub-pixel includes a light emitting element on a side of the sub-pixel driving circuit away from the substrate. The light emitting element includes an anode pattern, a light emitting function layer, and a cathode that are sequentially stacked in a direction away from the substrate. The anode pattern is electrically connected to the sub-pixel driving circuit in the sub-pixel to which the anode pattern belongs, and receives the driving signal provided by the sub-pixel driving circuit. The light emitting functional layer includes an organic light emitting material layer. In addition, the light emitting functional layer may also include: an electron transporting layer (ETL), an electron injection layer (EIL), and an hole transporting layer (HTL) and a hole injection layer (HIL) that are common layers of the entire structure. The cathode is electrically connected to a negative power signal line in the display substrate, and receives a negative power signal provided by the negative power signal line. The light emitting function layer emits light under the cooperation of the anode pattern and the cathode to realize the display function of the display substrate. Each sub-pixel includes the power signal line pattern91, and at least part of the power signal line pattern91extends along the second direction. In the same column of sub-pixels, the power signal line patterns91included in the sub-pixels are electrically connected in sequence to form an integral structure. The sub-pixel also includes a power compensation pattern97. The power signal line pattern91and the power compensation pattern97are both located on a side of the first data line pattern981and the second data line pattern982close to the substrate. For example, the side of the first data line pattern981and the second data line pattern982close to the substrate are provided with an interlayer insulating layer ILD, the power compensation pattern97and the power signal line pattern91both are located on a surface of the interlayer insulating layer ILD away from the substrate. This arrangement allows the power signal line pattern91and the power compensation pattern97to be arranged on the same layer. When the power signal line pattern91and the power compensation pattern97are made of the same material, the power source signal line pattern91and the power compensation pattern97are formed in the same patterning process, which simplifies the manufacturing process of the display substrate and saves the manufacturing cost. It should be noted that the power signal line pattern91and the power compensation pattern97may form the first source-drain metal layer in the display substrate. Of course, the first source-drain metal layer may also include other structures. As shown inFIG.5, the power compensation pattern97is electrically connected to the power signal line pattern91in the sub-pixel to which the power compensation pattern97belongs, and a power signal line pattern91′ in an adjacent sub-pixel along the first direction. Exemplarily, the power compensation pattern97and the two power signal line patterns91electrically connected to the power compensation pattern97form an integral structure. It is worth noting that the integrated structure includes: the power compensation pattern97and the power signal line pattern91that are formed at the same time and in contact to each other through a single patterning process. According to the specific structure of the above display substrate, in the display substrate provided by the embodiments of the present disclosure, different data line patterns provide data signals to adjacent sub-pixels in the same column, thereby ensuring that each sub-pixel has enough data signal writing time, so as to solve the problem of insufficient data signal writing time for each row of sub-pixels when the display substrate is in high-frequency display. In the display substrate provided by the embodiment of the present disclosure, the power compensation pattern97is electrically connected to the power signal line pattern91in the sub-pixel to which the power compensation pattern97belongs, and the power signal line patterns91′ in an adjacent sub-pixel in the same row along the first direction, so that the power signal line patterns91included in the sub-pixels in the same row are electrically connected together, the overall resistance of the power signal line patterns91is reduced, it is beneficial to improve the display uniformity of the display substrate. At the same time, by arranging the power signal line patterns91in the sub-pixels in the same column to be electrically connected in sequence, all the power signal line patterns91included in the display substrate are formed into a mesh structure, thereby further improving the display uniformity of the display substrate. In the display substrate provided by the embodiment of the present disclosure, the power compensation pattern97and the power signal line pattern91are both located on the surface of the interlayer insulating layer ILD of the display substrate away from the substrate, and the power signal line pattern91and the power compensation pattern97are formed as the first source-drain metal layer in the display substrate, so that the power signal line pattern91and the power compensation pattern97can be formed in the same patterning process. Therefore, the manufacturing process of the display substrate is simplified, and the manufacturing cost is saved. Moreover, since the power compensation pattern97and the power signal line pattern91are made of the same source-drain metal material, the resistance of the power compensation pattern97and the power signal line pattern91are both smaller, the display uniformity of the display substrate is improved. In the display substrate provided by the embodiment of the present disclosure, all the power signal line patterns91are jointly formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line pattern, and the power signal is provided to the source electrode of the driving transistor in the sub-pixel driving circuit, and the light-emitting current generated by the sub-pixel driving circuit is Ioled=k[(Vgs−Vth)]2, Vgs=Vg−Vs, Vg is a gate voltage of the driving transistor, and Vs is a source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor. Therefore, the power signal is Vs it will affect the value of the light-emitting current Ioled. Therefore, the above setting method improves the stability of the power signal line layer and the stability of the light-emitting current Ioled at the same time, and the occurrence of dynamic crosstalk is effectively avoided. As shown inFIG.5,FIG.8,FIG.10,FIG.12, andFIG.19, in some embodiments, the plurality of sub-pixels further include: a third sub-pixel M3and a fourth sub-pixel M4arranged along the second direction, the third sub-pixel M3and the first sub-pixel M1are located in the same row along the first direction, the fourth sub-pixel M4and the second sub-pixel M2are located in the same row. The third sub-pixel M3includes a third data line pattern983, the fourth sub-pixel M4includes a fourth data line pattern984, at least part of the third data line pattern983and at least part of the fourth data line pattern984extends along the second direction, the third data line pattern983is located on a second side of the same row of third sub-pixels extending along the second direction, and the fourth data line pattern984is located on a first side of the same column of fourth sub-pixels extending along the second direction. The third sub-pixel M3and the fourth sub-pixel M4both include: the power signal line pattern and the power compensation pattern. The power compensation pattern included in the third sub-pixel M3is electrically connected to the power signal line pattern included in the third sub-pixel M3and the power signal line pattern in an adjacent first sub-pixel M1in the first direction. The power compensation pattern included in the fourth sub-pixel M4is electrically connected to the power signal line pattern included in the fourth sub-pixel M4and the power signal line pattern in an adjacent second sub-pixel M2in the first direction. Specifically, at least part of the third data line pattern983and at least part of the fourth data line pattern984both extend along the second direction. The third data line patterns983included in third sub-pixel M3in the same column of sub-pixels are electrically connected in sequence to form an integrated structure. The fourth data line patterns984included in fourth sub-pixel M4in the same column of sub-pixels are electrically connected in sequence to form an integral structure. The third data line pattern is configured to provide a third data signal to the third sub-pixel, and the fourth data line pattern is configured to provide a fourth data signal to the fourth sub-pixel. Exemplarily, along the first direction, the third sub-pixel M3and the first sub-pixel M1are located in the same row, and the fourth sub-pixel M4and the second sub-pixel M2are located in the same row. Exemplarily, in the same column of sub-pixels, the third sub-pixel M3and the fourth sub-pixel M4are alternately arranged. Similarly, the third sub-pixel M3and the fourth sub-pixel M4also include a sub-pixel driving circuit. In the third sub-pixel M3, a first electrode of a data writing transistor is electrically connected to the third data line patterns983. In the fourth sub-pixel M4, the first electrode of the data writing transistor is electrically connected to the fourth data line pattern984. In each sub-pixel, the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the data writing transistor can transmit a data signal received by the first electrode thereof to the first electrode of the driving transistor. Exemplarily, the first side is set as the right side inFIG.5, and the second side is set as the left side inFIG.5. The third data line pattern983is located on the second side of the third sub-pixels in the same row extending along the second direction, and the fourth data line pattern984is located on the first side of the fourth sub-pixels in the same column extending along the second direction. Exemplarily, among the sub-pixels located in the same row along the first direction, the first data line pattern981and the third data line pattern983are both located between the first sub-pixel M1to which the first data line pattern981belongs and the third sub-pixel M3to which the third data line pattern983belongs. Among the sub-pixels located in the same row along the first direction, the second data line pattern982and the fourth data line pattern984are both located between the second sub-pixel M2to which the second data line pattern982belongs and the fourth sub-pixel M4to which the fourth data line pattern984belongs. The third sub-pixel M3and the fourth sub-pixel M4both include: the power signal line pattern and the power compensation pattern, and the structure of the power signal line pattern is similar to a structure of a power signal line pattern in the first sub-pixel M1and the second sub-pixel M2, and the structure of the power compensation pattern is the same as a structure of a power compensation pattern in the first sub-pixel M1and the second sub-pixel M2. It is worth noting that the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4include sub-pixel driving circuits that have the same structure, and the difference among the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4lies in the arrangement of data lines and the structure of the light-emitting elements. It should be noted that, as shown inFIG.12, the plurality of sub-pixels further include: a fifth sub-pixel M5, a sixth sub-pixel M6, a seventh sub-pixel M7, and an eighth sub-pixel M8. The fifth sub-pixel M5and the sixth sub-pixels M6are alternately arranged along the second direction, the seventh sub-pixels M7and the eighth sub-pixels M8are alternately arranged along the second direction; the first sub-pixel M1, the third sub-pixel M3, the fifth sub-pixel M5, and the seventh sub-pixel M7are located in the same row along the first direction; the second sub-pixel M2, the fourth sub-pixel M4, the sixth sub-pixel M6, and the eighth sub-pixel M8are located in the same row along the first direction. As shown inFIG.12, the eight sub-pixels from the first sub-pixel M1to the eighth sub-pixel M8form a repeating unit, and the display substrate includes a plurality of the repeating units. As shown inFIGS.5and8, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include: a reset signal line pattern95, a gate line pattern92and a light emitting control signal line pattern93arranged along the second direction; at least part of the reset signal line pattern95extends along the first direction, and at least part of the gate line pattern92extends along the first direction, at least part of the light emitting control signal line pattern93extends along the first direction. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern97on the substrate is located between the orthographic projection of the gate line pattern92on the substrate and the orthographic projection of the light emitting control signal line pattern93on the substrate. Specifically, the sub-pixel further includes: a reset signal line pattern95, a gate line pattern92, and a light-emission control signal line pattern93sequentially arranged along the second direction. The reset signal line is used to transmit a reset signal, and the gate line pattern92is used to transmit a scan signal. The light emitting control signal line pattern93is used to transmit a light emitting control signal. At least part of the reset signal line pattern95extends along the first direction, and the reset signal line patterns95included in the same row of sub-pixels along the first direction are electrically connected in sequence to form an integral structure. At least part of the gate line pattern92extends along the first direction, and the gate line patterns92included in the same row of sub-pixels along the first direction are electrically connected in sequence to form an integral structure. At least part of the light emitting control signal line pattern93extends along a first direction, and the light emitting control signal line patterns93included in the same row of sub-pixels along the first direction are electrically connected in sequence to form an integral structure. The specific layout positions of the power compensation pattern97are various, for example, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern97on the substrate does not overlap the orthographic projection of the reset signal line pattern95on the substrate, and the orthographic projection of the power compensation pattern97on the substrate does not overlap the orthographic projection of the gate line pattern92on the substrate, the orthographic projection of the power compensation pattern97on the substrate does not overlap the orthographic projection of the light emitting control signal line pattern93on the substrate. Exemplarily, the orthographic projection of the power compensation pattern97on the substrate is arranged between the orthographic projection of the gate line pattern92on the substrate and the orthographic projection of the light emitting control signal line pattern93on the substrate. Exemplarily, along the second direction, the minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the gate line pattern92on the substrate is greater than the minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the light emitting control signal line pattern93on the substrate. The power compensation pattern97is laid out in the above method, so that the power compensation pattern97has a relatively long distance to the reset signal line pattern95, the gate line pattern92, and the light emitting control signal line pattern93, thereby avoiding the increase of the loads of the reset signal line pattern95, the gate line pattern92and the light emitting control signal line pattern93. In some embodiments, the minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the gate line pattern92on the substrate is greater than a threshold; the minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the light emitting control signal line pattern93on the substrate is greater than the threshold. Exemplarily, the threshold is 5 μm. The minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the gate line pattern92on the substrate is greater than 5 μm; the minimum distance between the orthographic projection of the power compensation pattern97on the substrate and the orthographic projection of the light emitting control signal line pattern93on the substrate is greater than 5 μm. In the above arrangement, the power compensation pattern97has a long distance to the reset signal line pattern95, the gate line pattern92and the light emitting control signal line pattern93, thereby avoiding the increase of the loads of the reset signal line pattern95, the gate line pattern92, and the light emitting control signal line pattern93. As shown inFIGS.5,8,10,12, and19, in some embodiments, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the power signal line pattern91in each sub-pixel includes: a power main body (including a first portion911and a second portion912) and a power protruding portion913that are electrically connected. A first end of the power compensation pattern97is electrically connected to the power protruding portion913; a second end of the power compensation pattern97is electrically connected to the power main body in an adjacent sub-pixel along the first direction (the power main body of the power signal line pattern91′ inFIG.8). Exemplarily, at least part of the power protruding portion913extends along the second direction, and the second end of the power compensation pattern97is electrically connected to the middle portion of the power protruding portion913. The above arrangement method can shorten the length of the power compensation pattern97, thereby effectively reducing the layout difficulty of the power compensation pattern97. As shown inFIGS.5,8,10,12, and19, in some embodiments, at least part of the power protruding portion913extends along the second direction, and there is a gap50between the power protruding portion913and the power main body. In more detail, the power protruding portion913includes a third portion9130, a fourth portion9131, and a fifth portion9132. The third portion9130is electrically connected to the power compensation pattern97, and the third portion9130extends along the second direction; the fourth portion9131is electrically connected to one end of the third portion9130and the power main body; the fifth portion9132is respectively electrically connected to the other end of the third portion9130and the power main body; a gap50is formed between the third portion9130and the power main body. Specifically, the specific structure of the power protruding portion913is various. For example, the power protruding portion913includes the third portion9130, the fourth portion9131, and the fifth portion9132in an integral structure. As described above, the fourth portion9131is electrically connected to one end of the third portion9130and the power main body; the fifth portion9132is electrically connected to the other end of the third part9130and the power main body respectively, thereby ensuring the connection performance between the power protruding portion913and the power main body, and more effectively improving the display uniformity of the display substrate. In addition, the display substrate may also include a fingerprint identification module. Exemplarily, the fingerprint identification module is located on a side of the substrate away from the sub-pixel driving circuit. Exemplarily, the orthographic projection of the fingerprint identification area of the fingerprint identification module on the substrate overlaps the orthographic projection of the gap50on the substrate. During fingerprint identification, the finger touches the side of the light emitting element away from the substrate, and the light reflected by the finger can be received by the fingerprint identification module through the gap50to realize the fingerprint identification function. The gap50is set between the third portion9130and the power main body, thereby improving the light transmittance of the display substrate. Therefore, when the optical fingerprint identification technology is applied to the display substrate provided in the above embodiment, it can provide good conditions for the sensor to collect light signals, thereby effectively improving the speed and accuracy of fingerprint identification. In addition, in the display substrate provided by the above embodiment, the gap50is only formed on the power signal line pattern91, and the width of the metal trace line other than the power signal line pattern91is not reduced, and the size of the light emitting element is not reduced, and the size of the transistor or the capacitor is not reduced. Therefore, the display substrate provided by the above embodiment improves the resolution while not negatively affecting the performance of the display substrate. As shown inFIGS.5and9, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include: a storage capacitor Cst and a driving transistor. In each sub-pixel, the first electrode plate Cst1of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor, and the second electrode plate Cst2of the storage capacitor Cst is electrically connected to the power protruding portion913. Exemplarily, the orthographic projection of the second electrode plate Cst2of the storage capacitor Cst on the substrate overlaps the orthographic projection of the power protruding portion913on the substrate, and the second electrode plate Cst2of the storage capacitor Cst is electrically connected to the power protruding portion at the overlapping position. Exemplarily, the third portion9130includes a first sub-portion9130aand a second sub-portion9130b, the first sub-portion9130ais close to the fourth portion9131, and the second sub-portion9130bis close to the fifth portion. On a plane parallel to the substrate and in a direction perpendicular to the second direction, the width L1of the first sub-portion9130ais greater than the width L2of the second sub-portion9130b. The orthographic projection of the second electrode plate Cst2of the storage capacitor Cst on the substrate overlaps the orthographic projection of the first sub-portion9130aon the substrate, and the second electrode plate Cst2of the storage capacitor Cst is electrically connected to the first sub-portion9130athrough a via hole provided at the overlapping position. In the above arrangement, an overlapping area with a large area is formed between the second electrode plate Cst2of the storage capacitor Cst and the first sub-portion9130a, which is more conducive to reduce the layout difficulty of the via hole. It should be noted that the reference number40inFIG.13arepresents the substrate and some film layers (such as a buffer layer, an isolation layer, etc.) provided on the substrate. As shown inFIGS.5and9, in some embodiments, in a direction perpendicular to the first direction, the first end D of the power compensation pattern97has a first width, and along the direction close to the power signal line pattern in the sub-pixel to which the first sub-pattern belongs (that is, the direction pointed by the dotted line with an arrow inFIG.9), the first width gradually increases. In the above setting method, the connection between the power compensation pattern97and the power signal line pattern91has a better performance, a right-angle structure is avoided to be formed at the connection position between the power compensation pattern97and the power signal line pattern91, which leads to the risk of static electricity. As shown inFIGS.5,8,10, and12, in some embodiments, in the first sub-pixel M1, the orthographic projection of the power protruding portion913on the substrate overlaps the orthographic projection of the first data line pattern981on the substrate, and the orthographic projection of the power main body (including the first portion911and the second portion912) on the substrate at least partially overlaps the orthographic projections of an adjacent data line pattern along the first direction (the third data line pattern983inFIG.12) on the substrate. Specifically, in the display substrate, each sub-pixel includes the power signal line pattern91, and at least part of the power signal line pattern91extends along the second direction. In the same column of sub-pixels, the power signal line patterns91included in respective sub-pixels are electrically connected in sequence to form an integral structure. The specific structure of the power signal line pattern91is various. For example, the power signal line pattern91includes a first portion911and a second portion912that are electrically connected, the first portion911and the second portion912are alternately arranged. Exemplarily, the second portion912protrudes from the first portion911along the first direction. Exemplarily, in the first sub-pixel M1, the orthographic projection of the first portion911on the substrate overlaps an orthographic projection of a data line main body9801of an adjacent third data line pattern983along the first direction are on the substrate, and the orthographic projection of the second portion912on the substrate does not overlap the orthographic projection of the data line main portion9801of the third data line pattern983on the substrate. Exemplarily, at least part of the first portion911extends along the second direction, and at least part of the second portion912extends along the second direction, in a direction perpendicular to the second direction, a width of the first portion911is equal to a width of the second portion912, or the width of the first portion911is greater than the width of the second portion912, or the width of the first portion911is smaller than the width of the second portion912. In the display substrate provided by the foregoing embodiment, an overlapping area between the orthographic projection of the first data line pattern981on the substrate and the orthographic projection of a functional pattern with a fixed potential on the substrate is close to an overlapping area between the orthographic projection of a data line pattern adjacent to the first data line pattern981in the first direction on the substrate and the orthographic projection of the functional pattern with the fixed potential on the substrate. Therefore, the load difference between the first data line pattern981and an adjacent data line pattern along the first direction is effectively reduced. It should be noted that the functional pattern with the fixed unit includes: a power signal line pattern91, an initialization signal line pattern94, and a conductive function pattern electrically connected to the power signal line pattern91or the initialization signal line pattern94(E.g., the second conductive connection portion962) and so on. As shown inFIG.12, in some embodiments, in the second sub-pixel M2, the orthographic projection of the power protruding portion913on the substrate does not overlap the orthographic projection of the second data line pattern982on the substrate. Exemplarily, in the second sub-pixel M2, the orthographic projection of the power protruding portion913on the substrate overlaps the orthographic projection of an adjacent first data line981in the second direction on the substrate. As shown inFIG.12, in some embodiments, in the third sub-pixel M3, the orthographic projection of the power protruding portion913on the substrate does not overlap the orthographic projection of the third data line pattern983on the substrate. Exemplarily, in the third sub-pixel M3, the orthographic projection of the power protruding portion913on the substrate overlaps the orthographic projection of an adjacent fourth data line984in the second direction on the substrate. As shown inFIG.12, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the power protruding portion913on the substrate overlaps the orthographic projection of the fourth data line pattern984on the substrate, the orthographic projection of the power main body on the substrate overlaps the orthographic projection of the adjacent data line pattern along the first direction on the substrate. Exemplarily, in the fourth sub-pixel M4, the power main body includes a first portion911and a second portion912, and the orthographic projection of the first portion911on the substrate overlaps the orthographic projection of the data line main body9801of the adjacent sixth data line pattern986along the first direction on the substrate, and the orthographic projection of the second portion912on the substrate does not overlap the orthographic projection of the data line main body9801of the sixth data line pattern986on the substrate. In the display substrate provided by the above-mentioned embodiment, an overlapping area between the orthographic projection of the fourth data line pattern984on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is close to an overlapping area between the orthographic projection of the sixth data line pattern986on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby effectively reducing the load difference between the fourth data line pattern984and the sixth data line pattern986. It is worth noting thatFIG.12also shows that the fifth sub-pixel M5further includes a fifth data line pattern985, the seventh sub-pixel M7further includes a seventh data line pattern987, and the eighth sub-pixel further includes an eighth data line pattern988. In the display substrate provided by the foregoing embodiment, an overlapping area between the orthographic projection of the fourth data line pattern984on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is close to an overlapping area between the orthographic projection of a data line pattern adjacent to the fourth data line pattern984in the first direction on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate. Therefore, the load difference between the fourth data line pattern984and the adjacent data line pattern along the first direction is effectively reduced. As shown inFIGS.10and11, in some embodiments, the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984each includes a data line main body9801and a data line protruding portion9802, the data line main body9801extends along the second direction, and the data line protruding portion9802protrudes from the data line main body along the first direction9801. The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include a first conductive connection portion961and a data writing transistor. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the data line protruding portion9802is electrically connected to the first electrode of the data writing transistor through the first conductive connection portion961. Exemplarily, at least part of the first conductive connection portion961extends along the second direction. The orthographic projection of the first end of the first conductive connection portion961on the substrate and the orthographic projection of the data line protruding portion9802on the substrate have a first overlapping area, and the first end of the first conductive connection portion961is electrically connected to the data line protruding portion9802through a via hole provided in the first overlapping area. The orthographic projection of the second end of the first conductive connection portion961on the substrate and the orthographic projection of the first electrode of the data writing transistor on the substrate have a second overlapping area. The second end of the first conductive connection portion961is electrically connected to the first electrode of the data writing transistor through a via hole provided in the second overlapping area, and the first electrode of the data writing transistor receives a data signal provided by the corresponding data line pattern through the first conductive connection portion961. Exemplarily, the orthographic projection of the second portion912of the power signal line pattern91on the substrate and the first overlapping area are arranged along the first direction. Along the first direction, the distance between the first conductive connection portion961and the power signal line pattern91is relatively long, and the orthographic projection of the second portion912of the power signal line pattern91on the substrate and the first overlapping area are arranged along the first direction, so that the second portion912has sufficient layout space, thereby reducing layout difficulty of the display substrate while ensuring the second portion912has a larger area. As shown inFIGS.5,10, and12, in some embodiments, the first sub-pixel M1and the second sub-pixel M2each include: an initialization signal line pattern94, a second transistor T2, and a second conductive connection portion962. At least part of the initialization signal line pattern94extends along the second direction, and the initialization signal line pattern94is used to transmit an initialization signal. The first electrode of the second transistor T2is electrically connected to the initialization signal line pattern94through the second conductive connection portion962, and the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. In the first sub-pixel M1, the orthographic projection of the second conductive connection portion962on the substrate overlaps the orthographic projection of the first data line pattern981on the substrate. In the second sub-pixel M2, the orthographic projection of the second conductive connection portion962on the substrate does not overlap the orthographic projection of the second data line pattern982on the substrate. As shown inFIG.12, in some embodiments, the third sub-pixel M3and the fourth sub-pixel M4each include: an initialization signal line pattern94, a second transistor T2, and a second conductive connection portion962. At least part of the initialization signal line pattern94extends along the second direction, and the initialization signal line pattern94is used to transmit an initialization signal. The first electrode of the second transistor T2is electrically connected to the initialization signal line pattern94through the second conductive connection portion962, and the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. In the third sub-pixel M3, the orthographic projection of the second conductive connection portion962on the substrate does not overlap the orthographic projection of the third data line pattern983on the substrate. In the fourth sub-pixel M4, the orthographic projection of the second conductive connection portion962on the substrate overlaps the orthographic projection of the fourth data line pattern984on the substrate. Specifically, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include the initialization signal line pattern94, the second transistor T2and the second conductive connection portion962. Exemplarily, the orthographic projection of the first electrode of the second transistor T2on the substrate overlaps the orthographic projection of the first end of the second conductive connection portion962on the substrate, and the first electrode of the second transistor T2and the first end of the second conductive connection portion962are electrically connected through a via hole located at the overlapping position. The orthographic projection of the second end of the second conductive connection portion962on the substrate overlaps the orthographic projection of the initialization signal line pattern94on the substrate. The second end of the second conductive connection portion962and the initialization signal line pattern94are electrically connected through a via hole located at the overlapping position. The second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. During the reset period, the second transistor T2can transmit the received initialization signal to the gate electrode of the driving transistor, so as to reset the gate electrode of the driving transistor. Since the second conductive connection portion962is electrically connected to the initialization signal line pattern94, the initialization signal line pattern94has a stable potential. In the first sub-pixel M1, the orthographic projection of the second conductive connection portion962on the substrate overlaps the orthographic projection of the first data line pattern981on the substrate; so that the overlapping area between the orthographic projection of the first data line pattern981on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is closer to the overlapping area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby further reducing the load difference between the first data line pattern981and the third data line pattern. As described above, in the fourth sub-pixel M4, the orthographic projection of the second conductive connection portion962on the substrate overlaps the orthographic projection of the fourth data line pattern984on the substrate, so that the overlapping area between the orthographic projection of the second data line pattern982on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is closer to the overlapping area between the orthographic projection of the fourth data line pattern984on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby further reducing the load difference between the second data line pattern982and the fourth data line pattern984. In some embodiments, the overlapping area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the first portion911on the substrate has a first area. The overlapping area between the orthographic projection of the first data line pattern981on the substrate and the orthographic projection of the power protruding portion913on the substrate has a second area. The overlapping area between the orthographic projection of the first data line pattern981on the substrate and the orthographic projection of the second conductive connection portion962on substrate have a third area. The sum of the second area and the third area is approximately the same as the first area. The sum of the second area and the third area is set to be approximately the same as the first area, so that the load of the first data line pattern981is substantially the same as the load of the third data line pattern and the display uniformity of the display substrate is improved. In some embodiments, the overlapping area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the first portion911on the substrate has a first area. The overlapping area between the orthographic projection of the fourth data line pattern984on the substrate and the orthographic projection of the power protruding portion913on the substrate has a second area. The overlapping area between the orthographic projection of the fourth data line pattern984on the substrate and the orthographic projection of the second conductive connection portion962on the substrate have a third area. The sum of the second area and the third area is approximately the same as the first area. The sum of the second area and the third area is set to be approximately the same as the first area, so that the load of the second data line pattern982is substantially the same as the load of the fourth data line pattern984, the display uniformity of the display substrate is improved. As shown inFIGS.5,8,9,12, and19, in some embodiments, the power protruding portion913includes a third portion9130, a fourth portion9131, and a fifth portion9132; the third portion9130extends along the second direction. In the first sub-pixel M1, the orthographic projection of the third portion9130on the substrate overlaps the orthographic projection of the first data line pattern981on the substrate. In the fourth sub-pixel M4, the orthographic projection of the third portion9130on the substrate overlaps the orthographic projection of the fourth data line pattern984on the substrate. In the first sub-pixel M1, by setting the length of the third portion9130along the second direction, the overlapping area between the first data line pattern981and the third portion9130can be controlled, thereby adjusting the load of the first data line pattern981. In the third sub-pixel M3, by setting the length of the third portion9130along the second direction, the overlapping area between the fourth data line pattern984and the third portion9130can be controlled, thereby adjusting the load of the fourth data line pattern984. As shown inFIGS.5,12and13a, in some embodiments, the display substrate further includes an interlayer insulating layer ILD and a first planarization layer PLN1that are sequentially stacked in a direction away from the substrate. The first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984are all located on the surface of the first planarization layer PLN1away from the substrate. The power signal line pattern91and the power compensation pattern97are both located on the surface of the interlayer insulating layer ILD away from the substrate. Specifically, the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984are all located on the surface of the first planarization layer PLN1away from the substrate, so that the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984are all arranged in the same layer. When the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984are made of the same material, the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984are formed in the same patterning process, thereby simplifying the production process of the display substrate and saving production cost. It should be noted that the first data line pattern981, the second data line pattern982, the third data line pattern983, and the fourth data line pattern984may form the second source-drain metal layer in the display substrate. It is worth noting that the second source-drain metal layer may also include other structures. As shown inFIGS.12,13a, and15, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include a sixth transistor T6, and a third conductive connection portion963, a fourth conductive connection portion964, and a light emitting element that are sequentially stacked in a direction away from the substrate. The light emitting element includes an anode pattern (the first anode pattern71shown inFIG.13a). In each sub-pixel, the first electrode of the sixth transistor T6is connected to the second electrode of the driving transistor (that is, the third transistor); the second electrode of the sixth transistor T6is electrically connected to the anode pattern through the third conductive connection portion963and the fourth conductive connection portion964. Exemplarily, in each sub-pixel, the gate electrode of the sixth transistor T6is electrically connected to the light emitting control signal line pattern93, and the first electrode of the sixth transistor T6is electrically connected to the second electrode of the driving transistor. The orthographic projection of the second electrode of the sixth transistor T6on the substrate and the orthographic projection of the third conductive connection portion963on the substrate have a third overlapping area, and the second electrode of the sixth transistor T6is electrically connected to the third conductive connection portion963through the first via hole61provided in the third overlapping area; the orthographic projection of the third conductive connection portion963on the substrate and the orthographic projection of the fourth conductive connecting portion964on the substrate has a fourth overlapping area, and the third conductive connecting portion963is electrically connected to the fourth conductive connecting portion964through the second via hole62in the fourth overlapping area. The orthographic projection of the fourth conductive connecting portion964on the substrate and the orthographic projection of the anode pattern (such as: the first anode pattern71, the second anode pattern72, and the third anode pattern73) on the substrate has a fifth overlapping area, and the fourth conductive connection portion964is electrically connected to the anode pattern through a third via hole63provided in the fifth overlapping area. During the light emitting period, the sixth transistor T6transmits the driving signal outputted by the second electrode of the driving transistor to the anode of the light emitting element through the third conductive connection portion963and the fourth conductive connection portion964in sequence. In the display substrate provided by the above-mentioned embodiment, the second electrode of the sixth transistor T6is electrically connected to the anode pattern through the third conductive connection portion963and the fourth conductive connection portion964in sequence, which ensures the electrical connection performance between the second electrode of the sixth transistor T6and the anode pattern. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the fifth sub-pixel M5, the fourth conductive connection portion964includes a solid portion9641and a hollow portion9642. The orthographic projection of the solid portion9641on the substrate and the orthographic projection of the hollow portion9642on the substrate both at least partially overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the fifth data line pattern985on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the adjacent seventh data line pattern987in the first direction on the substrate. Specifically, in the fifth sub-pixel M5, the light emitting element includes a fifth light emitting element, and the fifth light emitting element includes a fifth anode pattern75and a fifth light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the fifth light emitting element includes a blue light emitting element. Exemplarily, in the fifth sub-pixel M5, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connecting portion963on the substrate have the fourth overlapping area. The orthographic projection of the solid portion9641on the substrate and the orthographic projection of the fifth anode pattern75on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the first side portion of the fifth anode pattern75on the substrate overlaps the orthographic projection of the fifth data line pattern985in the sub-pixel to which the fifth anode pattern75belongs on the substrate, overlaps the orthographic projection the seventh data line pattern987adjacent to the fifth data line pattern985along the first direction on the substrate; the orthographic projection of the second side portion of the fifth anode pattern75overlaps the orthographic projection of the hollow portion9642on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction. Exemplarily, the hollow portion9642is formed in a mouth shape, and the orthographic projection of the second side portion of the fifth anode pattern75on the substrate overlaps each of the orthographic projections of two sides of the hollow portion9642opposite to each other along the first direction on the substrate. Exemplarily, the orthographic projection of the second side portion of the fifth anode pattern75on the substrate overlaps each of the orthographic projections of the two sides of the hollow portion9642opposite to each other along the second direction on the substrate. Exemplarily, there is a first distance L3between the two sides of the hollow portion9642opposite to each other along the first direction, and in two adjacent sub-pixels along the first direction, there is a second distance L4between the seventh data line pattern987and the fifth data line pattern985that are adjacent to each other along the first direction, and the first distance L3is equal to the second distance L4. In the above arrangement, the fourth conductive connecting portion964is able to compensate for the step difference between the fifth data line pattern985and the seventh data line pattern987under the fifth anode pattern75, so that the fifth anode pattern75can be formed on a relatively flat surface, the fifth anode pattern75has a higher flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the first sub-pixel M1, the fourth conductive connecting portion964includes a solid portion; the orthographic projection of the solid portion on the substrate at least partially overlaps the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate does not overlap the orthographic projection of the first data line pattern981on the substrate. Specifically, the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the second data line pattern982on the substrate. Exemplarily, in the first sub-pixel M1, the light emitting element includes a first light emitting element, and the first light emitting element includes a first anode pattern71, a first light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the first light emitting element includes a red light emitting element. Exemplarily, in the first sub-pixel M1, the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion on the substrate and the orthographic projection of the first anode pattern71on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the first anode pattern71on the substrate does not overlap the orthographic projection of the first data line pattern981on the substrate. The orthographic projection of the first anode pattern71on the substrate does not overlap the orthographic projection of the adjacent third data line pattern983along the first direction on the substrate, and the orthographic projection of the first anode pattern71on the substrate at least partially overlaps the orthographic projection of the adjacent second data line pattern982in the second direction on the substrate. Exemplarily, the orthographic projection of the first side portion of the first anode pattern71on the substrate overlaps the orthographic projection of the adjacent second data line pattern982in the second direction on the substrate. The orthographic projection of the second side portion of the first anode pattern71on the substrate overlaps the orthographic projection of the eighth data line pattern988adjacent to the second data line pattern982in the first direction on the substrate; the first side portion and the second side portion are oppositely arranged along the first direction. In the above arrangement, the second data line pattern982and the eighth data line pattern988are able to compensate for the step difference generated by the second data line pattern982and the eighth data line pattern984under the first anode pattern71, so that the first anode pattern71can be formed on a relatively flat surface, the first anode pattern71has a relatively high flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in part of the second sub-pixel M2, the fourth conductive connection portion964includes a solid portion and a hollow portion. The orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate each at least partially overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the second data line pattern982on the substrate. Specifically, in the second sub-pixel M2, the light emitting element includes a second light emitting element, and the second light emitting element includes a second anode pattern72and a second light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the second light emitting element includes a blue light emitting element. Exemplarily, in the second sub-pixel M2, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connecting portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the second anode pattern72on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the second side portion of the second anode pattern72on the substrate at least partially overlaps the orthographic projection of the second data line pattern982in the sub-pixels to which the second anode pattern72belongs on the substrate. The orthographic projection of the second side portion of the second anode pattern72on the substrate overlaps the orthographic projection of the solid portion on the substrate, and the orthographic projection of the hollow portion on the substrate. The orthographic projection of the first side portion of the second anode pattern72on the substrate overlaps the orthographic projection of the adjacent first data line pattern981in the second direction on the substrate, and the orthographic projection of the third data line pattern983adjacent to the first data line pattern981along the second direction on the substrate. The first side portion and the second side portion are arranged opposite to each other along the first direction. Exemplarily, the hollow portion9642is formed in a mouth shape, and the orthographic projection of the second side portion of the second anode pattern72on the substrate overlaps each of the orthographic projections of two sides of the hollow portion9642opposite to each other along the first direction. Exemplarily, the orthographic projection of the second side portion of the second anode pattern72on the substrate overlaps each of the orthographic projections of the two sides of the hollow portion9642opposite to each other along the second direction. In the above arrangement, the fourth conductive connecting portion964and the second data line pattern982are able to compensate for the step difference generated by the first data line pattern981, and an extension portion of the third data line pattern983under the second anode pattern72, so that the second anode pattern72may be formed on a relatively flat surface, the second anode pattern72has a higher flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the sixth sub-pixel M6, the fourth conductive connection portion964includes a solid portion. The orthographic projection of the solid portion on the substrate at least partially overlaps the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the sixth data line pattern986on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the adjacent fourth data line patterns984in the first direction on the substrate. Specifically, in the sixth sub-pixel M6, the light emitting element includes a sixth light emitting element, and the sixth light emitting element includes a sixth anode pattern76and a sixth light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the sixth light emitting element includes a red light emitting element. Exemplarily, in the sixth sub-pixel M6, the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion on the substrate and the orthographic projection of the sixth anode pattern76on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the first side portion of the sixth anode pattern76on the substrate at least partially overlaps the orthographic projection of the sixth data line pattern986on the substrate, and the orthographic projection of the second side portion of the sixth anode pattern76on the substrate at least partially overlaps the orthographic projection of the adjacent fourth data line pattern984in the first direction on the substrate. The first side portion and the second side portion are arranged opposite to each other along the first direction. In the above arrangement, the sixth data line pattern986and the fourth data line pattern984are able to compensate for the step difference generated under the sixth anode pattern76, so that the sixth anode pattern76can be formed on a flat surface, the sixth anode pattern76has a relatively high flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in part of the third sub-pixel M3, the fourth conductive connection portion964includes a solid portion9641and a hollow portion9642; the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the hollow portion9642on the substrate each at least partially overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the third data line pattern983on the substrate. Specifically, in the third sub-pixel M3, the light emitting element includes a third light emitting element, and the third light emitting element includes a third anode pattern73and a third light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the third light emitting element includes a green light emitting element. Exemplarily, in part of the third sub-pixels M3, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connecting portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third anode pattern73on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the second side portion of the third anode pattern73on the substrate at least partially overlaps the orthographic projection of the third data line pattern983in the sub-pixel to which the third anode pattern73belongs on the substrate, the orthographic projection of the second side portion of the third anode pattern73on the substrate at least partially overlaps the orthographic projection of the adjacent first data line981in the first direction on the substrate; the orthographic projection of the first side portion of the third anode pattern73on the substrate overlaps each of the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate; the first side portion and the second side portion are oppositely arranged along the first direction. Exemplarily, the hollow portion9642is formed in a mouth shape, and the orthographic projection of the first side portion of the third anode pattern73on the substrate overlaps each of the orthographic projections of two sides of the hollow portion9642opposite to each other along the first direction on the substrate. In the above arrangement, the fourth conductive connecting portion964is able to compensate for the step difference between the first data line pattern981and the third data line pattern983under the third anode pattern73, so that the third anode pattern73can be formed on a relatively flat surface, so that the fifth anode pattern75has a higher flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the seventh sub-pixel M7, the fourth conductive connection portion includes a solid portion and a hollow portion. The orthographic projection of the solid portion on the substrate at least partially overlaps the orthographic projection of the anode pattern on the substrate, and the orthographic projection of the hollow portion on the substrate does not overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the seventh data line pattern987on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the adjacent fifth data line patterns985in the first direction on the substrate. Specifically, in the seventh sub-pixel M7, the light emitting element includes a seventh light emitting element, and the seventh light emitting element includes a seventh anode pattern77and a seventh light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the seventh light emitting element includes a green light emitting element. Exemplarily, in the seventh sub-pixel M7, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connection portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the seventh anode pattern77on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the second side portion of the seventh anode pattern77on the substrate least partially overlaps the orthographic projection of the seventh data line pattern987in the sub-pixels to which the seventh anode pattern77belongs on the substrate, the orthographic projection of the second side portion of the seventh anode pattern77on the substrate at least partially overlaps the orthographic projection of the adjacent fifth data line pattern985in the first direction on the substrate; the orthographic projection of the first side portion of the seventh anode pattern77on the substrate overlaps the orthographic projection of the solid portion on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction. In the above arrangement, the fourth conductive connection portion964is able to compensate for the step difference generated by the seventh data line pattern987and the fifth data line pattern985under the seventh anode pattern77, so that the seventh anode pattern77can be formed on a relatively flat surface, so that the seventh anode pattern77has a relatively high flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the eighth sub-pixel M8, the fourth conductive connection portion964includes a solid portion9641and a hollow portion9642. The orthographic projection of the solid portion9641on the substrate and the orthographic projection of the hollow portion9642on the substrate each at least partially overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate does not overlap the orthographic projection of the eighth data line pattern988on the substrate, and does not overlap the orthographic projection of the adjacent sixth data line pattern986in the first direction on the substrate. Specifically, in the eighth sub-pixel M8, the light emitting element includes an eighth light emitting element, and the eighth light emitting element includes an eighth anode pattern78and an eighth light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the eighth light emitting element includes a green light emitting element. Exemplarily, in part of the eighth sub-pixels M8, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connecting portion963on the substrate have the fourth overlapping area; the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the eighth anode pattern78on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the second side portion of the eighth anode pattern78on the substrate at least partially overlaps the orthographic projection of the adjacent seventh data line pattern987in the second direction on the substrate. The orthographic projection of the second side portion of the eighth anode pattern78on the substrate, at least partially overlaps the orthographic projection of the fifth data line pattern985adjacent to the seventh data line pattern987in the first direction on the substrate; the orthographic projection of the first side portion of the eighth anode pattern78on the substrate overlaps the orthographic projection of the solid portion on the substrate, and also overlaps the orthographic projection of the hollow portion on the substrate; the first side portion and the second side portion are oppositely arranged along the first direction. In the above arrangement, the fourth conductive connection portion964is able to compensate for the step difference between the seventh data line pattern987and the fifth data line pattern985under the eighth anode pattern78, so that the eighth anode pattern78can be formed on a relatively flat surface, so that the eighth anode pattern78has a higher flatness, which effectively reduces the color shift caused by the display substrate during display. As shown inFIGS.11,12,13a,14and15, in some embodiments, in the fourth sub-pixel M4, the fourth conductive connection portion964includes a solid portion9641and a hollow portion9642. The orthographic projection of the solid portion9641on the substrate at least partially overlaps the orthographic projection of the anode pattern on the substrate, and the orthographic projection of the hollow portion9642on the substrate does not overlap the orthographic projection of the anode pattern on the substrate. The orthographic projection of the anode pattern on the substrate does not overlap the orthographic projection of the fourth data line pattern984on the substrate, and the orthographic projection of the anode pattern on the substrate does not overlap the orthographic projection of the adjacent second data line patterns982in the first direction on the substrate. Specifically, in the fourth sub-pixel M4, the light emitting element includes a fourth light emitting element, and the fourth light emitting element includes a fourth anode pattern74and a fourth light emitting functional layer and cathode that are sequentially stacked in a direction away from the substrate. Exemplarily, the fourth light emitting element includes a green light emitting element. Exemplarily, in the fourth sub-pixel M4, the orthographic projection of the solid portion9641on the substrate and the orthographic projection of the third conductive connection portion963on the substrate have the fourth overlapping area. The orthographic projection of the solid portion9641on the substrate and the orthographic projection of the fourth anode pattern74on the substrate have the fifth overlapping area. Exemplarily, the orthographic projection of the second side portion of the fourth anode pattern74on the substrate at least partially overlaps the orthographic projection of the adjacent third data line pattern983in the second direction on the substrate. The orthographic projection of the second side portion of the fourth anode pattern74on the substrate at least partially overlaps the orthographic projection of the first data line pattern981adjacent to the third data line pattern983in the first direction on the substrate; the orthographic projection of the first side portion of the fourth anode pattern74on the substrate overlaps the orthographic projection of the solid portion on the substrate, and does not overlap the orthographic projection of the hollow portion on the substrate; the first side portion and the second side portion are arranged opposite to each other along the first direction. In the above arrangement, the fourth conductive connection portion964is able to compensate for the step difference between the first data line pattern981and the third data line pattern983under the fourth anode pattern74, so that the fourth anode pattern74can be formed on a relatively flat surface, the fourth anode pattern74has a higher flatness, which effectively reduces the color shift caused by the display substrate during display. It is worth noting thatFIG.16is a schematic diagram of the layout of the active layer inFIG.12;FIG.17is a schematic diagram of the layout of the first gate metal layer inFIG.12;FIG.18is a schematic diagram of the layout of the second gate metal layer inFIG.12. The active layer, the first gate metal layer, the second gate metal layer, and the first source-drain metal layer are sequentially stacked in a direction away from the substrate. As shown inFIGS.5,7and18, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include: an anode pattern, an initialization signal line pattern94, a shielding pattern80, a driving transistor, a second transistor T2and a seventh transistor T7. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the first electrode of the second transistor T2is electrically connected to the initialization signal line pattern94, and the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. The first electrode of the seventh transistor T7is electrically connected to the initialization signal line pattern94′ in an adjacent next sub-pixel in the second direction, and the second electrode of the seventh transistor T7is electrically connected to the anode pattern in the sub-pixel to which the seventh transistor T7belongs. The shielding pattern80is electrically connected to the power signal line pattern91, and the orthographic projection of the shielding pattern80on the substrate at least partially overlaps the orthographic projection of the first electrode of the second transistor T2on the substrate. Specifically, each of the sub-pixels further includes: an anode pattern, an initialization signal line pattern94, a shielding pattern80, a driving transistor, a second transistor T2, and a seventh transistor T7. The gate electrode of the second transistor T2is electrically connected to the reset signal line pattern95, the first electrode of the second transistor T2is electrically connected to the initialization signal line pattern94, the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. The second transistor T2is used to reset the gate electrode of the driving transistor. The gate electrode of the seventh transistor T7is electrically connected to the reset signal line pattern95′ included in the next sub-pixel adjacent to the sub-pixel to which the seventh transistor T7belongs along the second direction. The first electrode of the seventh transistor T7is electrically connected to the initialization signal line pattern94′ in an adjacent next sub-pixel in the second direction, the second electrode of the seventh transistor T7is electrically connected to the anode pattern in the sub-pixel, and the seventh transistor T7is used to reset the anode pattern. Each of the sub-pixels also includes a shielding pattern80, and the orthographic projection of the shielding pattern80on the substrate overlaps the orthographic projection of the power signal line pattern91on the substrate, and the shielding pattern80is electrically connected to the power signal line pattern91through the via hole provided at the overlapping position. Exemplarily, the orthographic projection of the shielding pattern80on the substrate overlaps the orthographic projection of the second portion912of the power signal line pattern91on the substrate, and the shielding pattern80is electrically connected to the second portion912of the power signal line pattern91through the via hole provided at the overlapping position. The shielding pattern80is electrically connected to the power signal line pattern91, so that the shielding pattern80have a stable potential, which not only helps the sub-pixel driving circuit to be in a stable working state, but also better guarantees the shielding effect of the shielding pattern80. By setting the orthographic projection of the shielding pattern80on the substrate to overlap the orthographic projection of the first electrode of the second transistor T2on the substrate, and/or, the orthographic projection of the shielding pattern80on the substrate to overlap the orthographic projection of the first electrode of the seventh transistor T7in an adjacent sub-pixel in the second direction on the substrate, so that the shielding pattern80shields the influence of the data signal change on the first electrode of the second transistor T2and/or the first electrode of the seventh transistor T7, thereby avoiding the influence on the initialization signal transmitted on the initialization signal line pattern94. As shown inFIGS.5,7and18, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include: a first conductive connection portion and a fifth conductive connection portion965. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor through the fifth conductive connection portion965. The first conductive connection portion961is electrically connected to the first electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor. The orthographic projection of the shielding pattern80on the substrate at least partially overlaps the orthographic projection of the first conductive connection portion961on the substrate. Specifically, in each sub-pixel, at least part of the fifth conductive connection portion965extends along the second direction. The orthographic projection of one end of the fifth conductive connection portion965on the substrate and the orthographic projection of the second electrode of the second transistor T2on the substrate have a sixth overlapping area, and one end of the fifth conductive connection portion965is electrically connected to the second electrode of the second transistor T2through a via hole provided in the sixth overlapping area, and the orthographic projection of the other end of the fifth conductive connection portion965on the substrate overlaps the orthographic projection of the gate electrode of the driving transistor on the substrate, and the other end of the fifth conductive connection portion965is electrically connected to the gate electrode of the driving transistor through a via hole provided at the overlapping position. Each of the sub-pixels further includes a first conductive connection portion961. For example, at least part of the first conductive connection portion961extends along the second direction. The orthographic projection of the first end of the first conductive connecting portion961on the substrate and the orthographic projection of the corresponding data line protruding portion9802on the substrate have a first overlapping area, and the first end of the first conductive connecting portion961is electrically connected to the data line protruding portion9802through the via hole provided in the first overlapping area. The orthographic projection of the second end of the first conductive connection portion961on the substrate and the orthographic projection of the first electrode of the data writing transistor on the substrate have a second overlapping area. The second end of the first conductive connection portion961is electrically connected to the first electrode of the data writing transistor through the via hole provided in the second overlapping area, and the first electrode of the data writing transistor receives the data signal provided by the corresponding data line pattern through the first conductive connection portion961. Exemplarily, the shielding pattern80includes a first shielding portion801and a second shielding portion802that are electrically connected to each other, and the orthographic projection of the first shielding portion801on the substrate overlaps the orthographic projection of the power signal line pattern91on the substrate, and the first shielding portion801is directly electrically connected to the power signal line pattern91through a via hole provided at the overlapping position. Exemplarily, the first shielding portion801and the second shielding portion802are formed as an integral structure. Exemplarily, the first shielding portion801has a square structure extending along the first direction, and the orthographic projection of the first shielding portion801on the substrate overlaps the orthographic projection of the first electrode of the second transistor T2on the substrate, and/or, the orthographic projection of the first shielding portion801on the substrate overlaps the orthographic projection of the first electrode of the seventh transistor T7in the adjacent sub-pixel along the second direction on the substrate. Exemplarily, the orthographic projection of the first shielding portion801on the substrate does not overlap the orthographic projection of the reset signal line pattern95on the substrate. Exemplarily, the orthographic projection of the first shielding portion801in the shielding pattern80on the substrate at least partially overlaps the orthographic projection of the first conductive connecting portion961on the substrate. As shown inFIG.5, in some embodiments, the orthographic projection of at least part of the shielding pattern80on the substrate is located between the orthographic projection of the first conductive connection portion961on the substrate and the orthographic projection of the fifth conductive connection portion965on the substrate. Exemplarily, as shown inFIG.13b, the orthographic projection of the second shielding portion802in the shielding pattern80on the substrate is located between the second overlapping area and the sixth overlapping area. Exemplarily, the second shielding portion802is a square structure extending along the second direction. The above arrangement enables the second shielding portion802to better shield the influence of the data signal change on the second electrode of the second transistor T2, thereby avoiding the influence of the data signal change on the gate signal of the driving transistor. Since the gate signal of the driving transistor directly affects the brightness of the sub-pixel, the above arrangement makes the gate potential of the driving transistor more stable, so that a better display effect can be obtained when the display substrate is used for display. As shown inFIGS.5,7and18, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include a first transistor T1. In each sub-pixel, the first electrode of the first transistor T1is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor T1is electrically connected to the gate electrode of the driving transistor. The active pattern of the first transistor T1includes two semiconductor portions arranged at intervals, and a first conductor portion respectively connected to the two semiconductor portions. The orthographic projection of the shielding pattern80on the substrate also at least partially overlaps the orthographic projection of the first conductor portion on the substrate. Specifically, each of the sub-pixels further includes a first transistor T1, the gate electrode of the first transistor T1is electrically connected to the gate line pattern92, and the first electrode of the first transistor T1is connected to the second electrode of the driving transistor. The second electrode of the first transistor T1is electrically connected to the gate electrode of the driving transistor. The first transistor T1is formed in a double-gate structure, and the active pattern of the first transistor T1includes two semiconductor portions arranged at intervals, and a first conductor portion respectively connected to the two semiconductor portions. The orthographic projection of the gate electrode of the first transistor T1on the substrate covers the orthographic projection of the two semiconductor portions on the substrate, and the orthographic projection of the gate electrode of the first transistor T1on the substrate does not overlap the orthographic projection of the first conductor portion on the substrate. Exemplarily, the shielding pattern80further includes a third shielding portion803electrically connected to the first shielding portion801, and at least part of the third shielding portion803is a square structure extending along the second direction. Exemplarily, the first shielding portion801and the third shielding portion803are formed as an integral structure. Exemplarily, the shielding pattern80further includes a third shielding portion803electrically connected to the first shielding portion801, and the orthographic projection of the third shielding portion803on the substrate overlaps the orthographic projection of the first conductor portion on the substrate. The orthographic projection of the third shielding portion803on the substrate overlaps the orthographic projection of the first conductor portion on the substrate. This arrangement allows the third shielding pattern80to shield the first conductor portion, avoids the influence of the data signal change on the first transistor T1, and avoids the influence of the data signal change on the gate electrode of the driving transistor. In some embodiments, in a direction perpendicular to the substrate, the shielding pattern80is located between the first electrode of the second transistor T2and the first conductive connection portion961. Exemplarily, the display substrate further includes a second gate insulating layer located between the first electrode of the second transistor T2and the first conductive connection portion961. In each sub-pixel, the initialization signal line pattern94and the shielding pattern80are both located on a surface of the second gate insulating layer away from the substrate. The initialization signal line pattern94and the shielding pattern80are both located on the surface of the second gate insulating layer away from the substrate, so that the initialization signal line pattern94and the shielding pattern80are arranged on the same layer. When the initialization signal line pattern94and the shielding pattern80are made of the same material, the initialization signal line pattern94and the shielding pattern80can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate, and saving the manufacturing cost. As shown inFIGS.2,5, and12, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4all include: a light emitting element, an initialization signal line pattern94, a reset signal line pattern95, a gate line pattern92, and a light emitting control signal line pattern93. At least part of the initialization signal line pattern94, at least part of the reset signal line pattern95, at least part of the gate line pattern92and at least part of the light emitting control signal line pattern93extend along the first direction. The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4further include: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. In each sub-pixel, the gate electrode of the driving transistor is electrically connected to the second electrode of the first transistor T1, the first electrode of the driving transistor is electrically connected to the second electrode of the fifth transistor T5, the second electrode of the driving transistor is electrically connected to the first electrode of the first transistor T1. The gate electrode of the first transistor T1is electrically connected to the gate line pattern92. The gate electrode of the second transistor T2is electrically connected to the reset signal line pattern95, the first electrode of the second transistor T2is electrically connected to the initialization signal line pattern94, and the second electrode of the second transistor T2is electrically connected to the gate electrode of the driving transistor. The gate electrode of the data writing transistor is electrically connected to the gate line pattern92, the first electrode of the data writing transistor is electrically connected to the data line pattern included in the sub-pixel, and the first electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor. The gate electrode of the fifth transistor T5is electrically connected to the light emitting control signal line pattern93, and the first electrode of the fifth transistor T5is electrically connected to the power signal line pattern91. The gate electrode of the sixth transistor T6is electrically connected to the light emitting control signal line pattern93, the first electrode of the sixth transistor T6is electrically connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6is electrically connected to the light emitting element. The gate electrode of the seventh transistor T7is electrically connected to the reset signal line pattern95in an adjacent next sub-pixel along the second direction, and the first electrode of the seventh transistor T7is connected to the initialization signal line pattern94in the next adjacent sub-pixel along the second direction, and the second electrode of the seventh transistor T7is electrically connected to the light emitting element. The first electrode plate of the storage capacitor is multiplexed as the gate electrode of the driving transistor, and the second electrode plate of the storage capacitor is electrically connected to the power signal line pattern91. Exemplarily, each sub-pixel in the display substrate includes a sub-pixel driving circuit, and each sub-pixel driving circuit includes: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, a first conductive connection portion961, a second conductive connection portion962, a third conductive connection portion963, a fourth conductive connection portion964and a fifth conductive connection portion965and so on. Specifically, the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels sequentially arranged along the second direction, and a plurality of columns of sub-pixels sequentially arranged along the first direction. The initialization signal line patterns94included in the same row of sub-pixels include are electrically connected in sequence to form an integral structure; the gate line patterns92included in the same row of sub-pixels are electrically connected in sequence to form an integral structure; the light emitting control signal line patterns93included in the same row of sub-pixels are electrically connected in sequence to form an integral structure; the reset signal line patterns95included in the same row of sub-pixels are electrically connected in sequence to form an integral structure; the first data line patterns981included in the same column of sub-pixels are electrically connected in sequence to form an integral structure; the second data line patterns982included in the same column of sub-pixels are electrically connected in sequence to form an integral structure; the power signal line patterns91included in the same column of sub-pixels are electrically connected in sequence to form an integral structure. As shown inFIG.2, taking a sub-pixel driving circuit as an example, the sub-pixel driving circuit includes seven thin film transistors and one capacitor. Each transistor included in the sub-pixel driving circuit is a P-type transistor, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode. The first transistor T1has a double-gate structure, the gate electrode201gof the first transistor T1is electrically connected to the gate line pattern92, and the source electrode S1of the first transistor T1is electrically connected to the drain electrode D3of the third transistor T3(that is, the driving transistor), the drain electrode D1of the first transistor T1is electrically connected to the gate electrode203gof the third transistor T3. The second transistor T2has a double-gate structure. The gate electrode202gof the second transistor T2is electrically connected to the reset signal line pattern95, and the source electrode S2of the second transistor T2is electrically connected to the initialization signal line pattern94. The drain electrode D2of T2is electrically connected to the gate electrode203gof the third transistor T3. The gate electrode204gof the fourth transistor T4(that is, the data writing transistor) is electrically connected to the gate line pattern92, and the source electrode S4of the fourth transistor T4is electrically connected to data line pattern in a sub-pixel to which the fourth transistor T4belongs, the drain electrode D4of the fourth transistor T4is electrically connected to the source electrode S3of the third transistor T3. The gate electrode205gof the fifth transistor T5is electrically connected to the light emitting control signal line pattern93, the source electrode S5of the fifth transistor T5is electrically connected to the power signal line pattern91, and the drain electrode D5of the fifth transistor T5is electrically connected to the source electrode S3of the third transistor T3. The gate electrode206gof the sixth transistor T6is electrically connected to the light emitting control signal line pattern93, the source electrode S6of the sixth transistor T6is electrically connected to the drain electrode D3of the third transistor T3, and the drain electrode D6of the sixth transistor T6is electrically connected to the anode of the light emitting element EL. The gate electrode207gof the seventh transistor T7is electrically connected to the reset signal line pattern95′ in an adjacent next sub-pixel in the second direction, and the drain electrode D7of the seventh transistor T7is electrically connected to the anode of the corresponding light emitting element EL. The source electrode S7of the seventh transistor T7is electrically connected to the initialization signal line pattern94′ in an adjacent next sub-pixel in the second direction. The first electrode plate Cst1of the storage capacitor Cst is multiplexed as the gate electrode203gof the third transistor T3, and the second electrode plate Cst2of the storage capacitor Cst is electrically connected to the power signal line pattern91. As shown inFIG.3, when the sub-pixel driving circuit of the above structure is in operation, each work cycle includes a reset period P1, a writing compensation period P2, and a light emitting period P3. InFIG.3, E1represents the light emitting control signal transmitted on the light emitting control signal line pattern93in the current sub-pixel, R1represents a reset signal transmitted on the reset signal line pattern95in the current sub-pixel, and D1represents the data signal transmitted on the data line pattern in the current sub-pixel, G1represents a gate scan signal transmitted on the gate line pattern92in the current sub-pixel, and R1′ represents the reset signal transmitted on the reset signal line pattern95′ in a next sub-pixel adjacent to the current sub-pixel in the second direction. In the first reset period P1, the reset signal inputted by the reset signal line pattern95is at a valid level, the second transistor T2is turned on, and the initialization signal transmitted by the initialization signal line pattern94is inputted to the gate electrode203gof the third transistor T3, so that the gate-source voltage Vgs kept at the third transistor T3in the previous frame is changed to zero, so as to reset the gate electrode203gof the third transistor T3. In the writing compensation period P2, the reset signal inputted from the reset signal line pattern95is at an invalid level, the second transistor T2is turned off, and the gate scan signal inputted from the gate line pattern92is at a valid level, the first transistor T1and the fourth transistor T4are controlled to be turned on, a data signal is written by a corresponding data line pattern, and transmitted to the source electrode S3of the third transistor T3through the fourth transistor T4, and at the same time, the first transistor T1and the fourth transistor T4are turned on, the third transistor T3is formed into a diode structure. Therefore, the first transistor T1, the third transistor T3, and the fourth transistor T4work together to realize the threshold voltage compensation of the third transistor T3. When the compensation time is long enough, the potential of the gate electrode203gof the third transistor T3is controlled to finally reach Vdata+Vth, where Vdata represents a voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3. In the writing compensation period P2, the reset signal inputted from the reset signal line pattern95′ is at a valid level, the seventh transistor T7is controlled to be turned on, and the initialization signal transmitted by the initialization signal line pattern94′ is inputted to the anode of the light emitting element EL, so as to control the light emitting element EL to not emit light. In the light emitting period P3, the light emitting control signal written by the light emitting control signal line pattern93is at a valid level, and the fifth transistor T5and the sixth transistor T6are controlled to be turned on, so that the power signal transmitted by the power signal line pattern91is inputted to the source electrode S3of the transistor T3, and the gate electrode203gof the third transistor T3is kept at Vdata+Vth, so that the third transistor T3is turned on. The corresponding gate-source voltage of the third transistor T3is Vdata+Vth-VDD, and VDD is the voltage value corresponding to the power signal, the drain current generated based on the gate-source voltage flows to the anode of the corresponding light emitting element EL, so as to drive the corresponding light emitting element EL to emit light. As shown inFIGS.6-8andFIGS.10-13a, when the above sub-pixels are made, the layout of each layer corresponding to the sub-pixels is as follows. The active film layer, the first gate insulating layer GI1, the first gate metal layer, the second gate insulating layer GI2, the second gate metal layer, the interlayer insulating layer ILD, a first source-drain metal layer, a first planarization layer PLN1, a second source-drain metal layer, a second planarization layer PLN2and an anode layer are sequentially stacked in a direction away from the substrate. As shown inFIG.6, the active film layer is used to form the channel region (the portion covered by the gate electrode of each transistor) of each transistor in the sub-pixel driving circuit, the source electrode (such as S1-S7) and the drain electrode (such as D1-D7). Due to the doping effect, the conductivity of the active film corresponding to the source electrode and drain electrode will be better than that of the active film corresponding to the channel region; the active film can be amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source electrode and drain electrode may be doped with n-type impurities or p-type impurities. As shown inFIG.6, the first gate metal layer is used to form the gate electrodes of the transistors in the sub-pixel driving circuit (for example,201g-207g), and the gate line pattern92, the light emitting control signal line pattern93, and the reset signal line pattern95and other structures included in the sub-pixel, the gate electrode203gof the third transistor T3in each sub-pixel driving circuit is multiplexed as the first electrode plate Cst1of the second storage capacitor Cst in the sub-pixel driving circuit. As shown inFIG.7, the second gate metal layer is used to form the second electrode plate Cst2of the second storage capacitor Cst, the initialization signal line pattern94included in the sub-pixel, and the shielding pattern80. As shown inFIG.8, the first source-drain metal layer is used to form the power signal line pattern91, the power compensation pattern and some conductive connection portions included in the sub-pixel. As shown inFIG.11, the second source-drain metal layer is used to form the first data line pattern981, the second data line pattern982and some conductive connection portions included in the sub-pixel. In addition, as shown inFIG.5, in the display substrate provided by the present disclosure, in the second direction, the gate electrode204gof the fourth transistor T4, the gate electrode201gof the first transistor T1, and the gate electrode202gof the second transistor T2are all located at the first side of the gate electrode of the driving transistor (that is, the gate electrode203gof the third transistor T3). The gate electrode of the seventh transistor T7, the gate electrode206gof the sixth transistor T6, and the gate electrode of the fifth transistor T5are all located at the second side of the gate electrode of the driving transistor. Exemplarily, the first side and the second side of the gate electrode of the driving transistor are two sides opposite to each other along the second direction. Further, the first side of the gate opposite of the driving transistor may be the upper side of the gate opposite of the driving transistor. On the other hand, the second side of the gate opposite of the driving transistor may be the lower side of the gate opposite of the driving transistor. For example, a side of the display substrate for bonding the ICs is the lower side of the display substrate, and the lower side of the gate electrode of the driving transistor is a side of the gate electrode of the driving transistor closer to the ICs. The upper side is an opposite side of the lower side, for example, the side of the gate electrode of the driving transistor farther away from the ICs. In the first direction, the gate electrode204gof the fourth transistor T4and the gate electrode205gof the fifth transistor T5are both located at a third side of the gate electrode of the driving transistor. The gate electrode201gof the first transistor T1and the gate electrode206gof the sixth transistor T6are both located at a fourth side of the gate electrode of the driving transistor. Exemplarily, the third side and the fourth side of the gate electrode of the driving transistor are opposite sides along the first direction; further, the third side of the gate electrode of the driving transistor may be the right side of the gate electrode of the driving transistor, the fourth side of the gate electrode of the driving transistor may be the left side of the gate electrode of the driving transistor. For the left and right sides, for example, in the same sub-pixel, the second data line pattern982is located at the right side of the gate electrode of the driving transistor, and the first data line pattern981is located at the left side of the gate electrode of the driving transistor. The embodiments of the present disclosure also provide a display device, including the display substrate. In the display substrate provided by the above embodiment, it is realized that in the same column of sub-pixels, different data line patterns provide data signals to adjacent sub-pixels, which ensures that each sub-pixel has sufficient data signal writing time, thereby solving the problem that the data signal writing time of each row of sub-pixels is insufficient when the display substrate is in high-frequency display. In the display substrate provided in the above embodiment, the power compensation pattern97is electrically connected to the power signal line pattern91in the sub-pixel to which the power compensation pattern97belongs, and the power signal line pattern91′ in a sub-pixel adjacent to the sub-pixel in the same row along the first direction; so that the power signal line patterns91included in the same row of sub-pixels are electrically connected together, the overall resistance of the power signal line patterns91is reduced, which is more beneficial to improve the display uniformity of the display substrate. At the same time, the power signal line patterns91in the same column of sub-pixels are arranged to be electrically connected in sequence, all the power signal line patterns91included in the display substrate are formed into a mesh structure, thereby further improving the display uniformity of the display substrate. In the display substrate provided by the above embodiment, the power compensation pattern97and the power signal line pattern91are both located on the surface of the interlayer insulating layer ILD of the display substrate away from the substrate, and the power signal line pattern91and the power compensation pattern97are formed as the first source-drain metal layer in the display substrate, so that the power signal line pattern91and the power compensation pattern97can be formed in the same patterning process, thereby simplifying the production process of the display substrate, and saving the production cost. Moreover, since the power compensation pattern97and the power signal line pattern91are made of the same source-drain metal material, the resistance of the power compensation pattern97and the power signal line pattern91are both smaller, which is facilitated to improve the display uniformity of the display substrate. In the display substrate provided by the above embodiment, all the power signal line patterns91are jointly formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line pattern, and the power signal is provided to the source electrode of the driving transistor in the sub-pixel driving circuit, and the light-emitting current generated by the sub-pixel driving circuit is Ioled=k[(Vgs−Vth)]2, Vgs=Vg−Vs, Vg is the gate voltage of the driving transistor, and Vs is the source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor. Therefore, the power signal is Vs, which will affect the value of the light-emitting current Ioled. Therefore, the above setting method improves the stability of the power signal line layer and ensures the stability of the light-emitting current Ioled, and effectively avoids the occurrence of the dynamic crosstalk phenomenon. Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has all the effects of the above-mentioned display substrate, which will not be repeated here. It should be noted that the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and so on. The embodiment of the present disclosure also provides a method for manufacturing a display substrate, including: forming a plurality of sub-pixels arranged in an array on a substrate, the plurality of sub-pixels includes a first sub-pixel M1and a second sub-pixel M2alternately arranged along a second direction. The first sub-pixel M1includes a first data line pattern981, and the second sub-pixel M2includes a second data line pattern982. The first data line pattern981is configured to provide a first data signal to the first sub-pixel M1, and the second data line pattern982is configured to provide a second data signal to the second sub-pixel M2; at least part of the first data line pattern981and at least part of the second data line pattern982extend along the second direction, and the first data line pattern981is located on a first side of a same column of the first sub-pixels extending along the second direction. The second data line pattern982is located on a second side of a same column of the second sub-pixels extending along the second direction, and the first side and the second side are opposite to each other along the first direction, the first direction intersects the second direction. As shown inFIGS.5,8,10,12, and19, the first sub-pixel M1and the second sub-pixel M2both include: a power signal line pattern91, at least part of the power signal line pattern91extends along the second direction; and a power compensation pattern97, at least part of the power compensation pattern97extends along the first direction, the power signal line pattern91and the power compensation pattern97are both located on a side of the first data line pattern981and the second data line pattern982close to the substrate; the power compensation pattern97is electrically connected to the power signal line pattern91and the power signal line pattern91in an adjacent sub-pixel along the first direction. In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, in the same column of sub-pixels, different data line patterns provides data signals to adjacent sub-pixels, which ensures that each sub-pixel has enough data signal writing, solves the problem of insufficient data signal writing time for each row of sub-pixels when the display substrate is in high-frequency display. In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, the power compensation pattern97is electrically connected to the power signal line pattern91in the sub-pixel to which the power compensation pattern97belongs, and the power signal line patterns91′ in an adjacent sub-pixel in the same row along the first direction, so that the power signal line patterns91included in the sub-pixels in the same row are electrically connected together, the overall resistance of the power signal line patterns91is reduced, it is beneficial to improve the display uniformity of the display substrate. At the same time, by arranging the power signal line patterns91in the sub-pixels in the same column to be electrically connected in sequence, all the power signal line patterns91included in the display substrate are formed into a mesh structure, thereby further improving the display uniformity of the display substrate. In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, the power compensation pattern97and the power signal line pattern91are both located on the surface of the interlayer insulating layer ILD of the display substrate away from the substrate, and the power signal line pattern91and the power compensation pattern97are formed as the first source-drain metal layer in the display substrate, so that the power signal line pattern91and the power compensation pattern97can be formed in the same patterning process. Therefore, the manufacturing process of the display substrate is simplified, and the manufacturing cost is saved. Moreover, since the power compensation pattern97and the power signal line pattern91are made of the same source-drain metal material, the resistance of the power compensation pattern97and the power signal line pattern91are both smaller, the display uniformity of the display substrate is improved. In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, all the power signal line patterns91are jointly formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line pattern, and the power signal is provided to the source electrode of the driving transistor in the sub-pixel driving circuit, and the light-emitting current generated by the sub-pixel driving circuit is Ioled=k[(Vgs−Vth)]2, Vgs=Vg−Vs, Vg is a gate voltage of the driving transistor, and Vs is a source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor. Therefore, the power signal is Vs it will affect the value of the light-emitting current Ioled. Therefore, the above setting method improves the stability of the power signal line layer and the stability of the light-emitting current Ioled at the same time, and the occurrence of dynamic crosstalk is effectively avoided. It should be further appreciated that, the above embodiments have been described in a progressive manner, and the same or similar contents in the embodiments have not been repeated, i.e., each embodiment has merely focused on the difference from the others. Especially, the product embodiments are substantially similar to the method embodiments, and thus have been described in a simple manner. Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as “include” or “including” intends to indicate that an element or object before the word contains an element or object or equivalents thereof listed after the word, without excluding any other element or object. Such words as “connect/connected to” or “couple/coupled to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too. It should be appreciated that, in the case that such an element as layer, film, region or substrate is arranged “on” or “under” another element, it may be directly arranged “on” or “under” the other element, or an intermediate element may be arranged therebetween. In the above description, the features, structures, materials or characteristics may be combined in any embodiment or embodiments in an appropriate manner. The above embodiments are for illustrative purposes only, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure. | 128,372 |
11943984 | DETAILED DESCRIPTION OF EMBODIMENTS In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure. The affirmatively described embodiments constitute only a subset of the embodiments contemplated in view of the present disclosure, and not all of such embodiments. Based on the described embodiments of the present disclosure, further embodiments obtained by those skilled in the art without creative work are within the protection scope of the present disclosure. It should be noted that, in the drawings, for clarity and/or description purposes, a size and relative size of an element may be enlarged, the size and relative size of each element need not be limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar components. When an element is described as being “on”, “connected to” or “coupled to” another element, the element may be directly on the another element, directly connected to the another element or directly coupled to the another element, or an intermediate element may be present. However, when an element is described as being “directly on”, “directly connected to” or “directly coupled to” another element, there are no intermediate element. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, “between” and “directly between”, “adjacent” and “directly adjacent”, “on” and “directly on” etc. In addition, the term “connect” may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. In addition, X axis, Y axis, and Z axis are not limited to the three axes of the Cartesian coordinate system, which may be interpreted in broader meaning. For example, the X axis, the Y axis, and the Z axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from a group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As shown in the present disclosure, the term “and/or” includes any and all combinations of one or more of the related items. It should be noted that although the terms “first”, “second”, etc. may be used to describe various components, members, elements, regions, layers and/or portions, these components, components, elements, regions, layers and/or portions should not be limited by these terms. Actually, the terms are used to distinguish one component, member, element, region, layer, and/or portion from another one. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion described below may be referred to as a second component, a second member, a second element, a second region, a second layer and/or a second portion, which does not depart from the teachings of this disclosure. For the convenience of description, the spatial relationship terms, for example, “upper”, “lower”, “left”, “right”, etc. may be used to describe the relationship between one element or feature and another element or feature as shown in figures. It should be understood that, in addition to an orientation described in figures, the spatial relationship terms include other different orientations of a device in operation. For example, if the device in figures is turned upside down, elements described as “below” or “lower” other elements or features will be oriented “on” or “upper” other elements or features. In the present disclosure, the terms “substantially”, “approximately”, “circa”, “about” and other similar terms are used as approximate terms rather than as terms of degree, and these terms explain a inherent deviation of a measured value or a calculated value recognized by those skilled in the art. Taking into factors such as process fluctuations, measurement problems, and errors related to the measurement of specific quantities (i.e. the limitations of the measurement system), the “substantially” or “approximately” includes a stated value and means that a specific value determined by those skilled in the art is within an acceptable deviation range. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. It should be noted that, in the present disclosure, the expression “same layer” refers to a film layer formed by the same film forming process, wherein the film layer is used to form a specific pattern, and then the same mask is used to pattern the film layer and form a layer structure through one patterning process. Depending on the specific pattern, the one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, a plurality of elements, components, structures and/or portions located in the “same layer” are made of the same material and formed by the same patterning process. Generally, the plurality of elements, components, structures and/or portions located in the “same layer” have approximately the same thickness. Those skilled in the art should understand that, in the present disclosure, unless otherwise specified, the expression “height” or “thickness” refers to a size along a surface of each film layer arranged perpendicular to a display substrate, that is, the size in a light-emission direction of the display substrate, or the size in a normal direction of the display device. The embodiments of the present disclosure relate to at least one display substrate, the display substrate includes a display area and a non-display area, wherein the display substrate includes: a base substrate; a plurality of sub-pixels, wherein the plurality of sub-pixels are arranged on the base substrate in an array in a row direction and a column direction, the plurality of sub-pixels is located in the display area, each sub-pixel includes a light-emission device, and the light-emission device includes a first electrode; a plurality of signal lines on the base substrate, wherein the plurality of signal lines include at least a first signal line and a second signal line, the first signal line is configured to transmit a voltage signal, and the second signal line is configured to transmit a scan signal; a signal line lead on the base substrate, wherein the signal line lead is located in the non-display area; and a signal line transfer structure on the base substrate, wherein the signal line transfer structure is configured to connect the signal line lead and the second signal line, wherein the signal line transfer structure and the first signal line are located in the same layer, and the signal line transfer structure is spaced apart from the first signal line; and wherein an orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the first signal line on the base substrate, and the orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the signal line transfer structure on the base substrate. In this way, the plainness of the first electrode may be improved, a tilt of the first electrode may be avoided, and a color shift phenomenon of the display substrate may be improved. FIG.1is a partial plan view of an organic light-emission diode (hereinafter referred to as OLED) display substrate in the related art, andFIG.2is a cross-sectional view taken along line AA′ inFIG.1. It should be noted that in order to clearly illustrate the relative positional relationship among a signal line, a planarization layer and an anode, some other film layer structures included in the OLED display substrate are omitted inFIGS.1and2. Referring toFIGS.1and2, the OLED display substrate may include a base substrate02and a plurality of sub-pixels arranged on the base substrate02, for example, SP1, SP2, and SP3shown inFIG.1. For example, SP1, SP2, and SP3inFIG.1may represent an area for display in each sub-pixel. For example, a portion corresponding to an opening of a pixel defining layer. It should be understood that the OLED display substrate may further include: an OLED light-emission device01and a pixel driving circuit electrically connected to the OLED light-emission device01. The pixel driving circuit may be electrically connected to a driving IC located outside the OLED display substrate through a signal line03. The OLED display substrate may include a planarization layer04for covering the pixel driving circuit and the signal line03. The OLED light-emission device01may include an anode011, an organic light-emission layer012, and a cathode013that are stacked onto each other. The pixel driving circuit may include a plurality of thin film transistors. For example, the signal line03may be located in the same layer as both a source electrode and a drain electrode of a thin film transistor, and may be formed of the same material as the source electrode and the drain electrode. As shown inFIG.1andFIG.2, in a direction perpendicular to the base substrate02, at least a portion031of the signal line03is located below the anode011. The signal line03has a certain thickness that is usually large, for example, usually above 3000 angstroms, and the thickness of the planarization layer04covering the signal line03and the thickness of the anode011are not enough to compensate for a height difference caused by the signal line03, thus the planarization layer04fail to completely planarize the signal line03. As a result, at a position corresponding to the portion031of the signal line03, the planarization layer04may be convex, so that the anode011formed on the planarization layer04is not sufficiently planar, for example, it may “slope”. FIG.3is a schematic view schematically illustrating the plainness of anodes in different sub-pixels of the display substrate in the related art. It should be noted that in order to clearly show unevenness of the anode,FIG.3exaggerates a degree of slope. It should be understood thatFIG.3is not drawn according to actual scale. Referring toFIG.3, anodes of three sub-pixels are schematically illustrated. For the convenience of description, the anodes of the three sub-pixels are referred to as013A,013B, and013C, respectively. The anode013A is located on the leftmost side, under the influence of a signal line03below the anode013A, a right side of the anode013A is higher than a left side of the anode013A, so the anode013A is tilted toward upper-right side as shown inFIG.3. The anode013B is located on the middle, under the influence of the signal line03below the anode013B, a left side of the anode013B is higher than a right side of the anode013B, so the anode013B is tilted toward upper-left side as shown inFIG.3. The anode013C is located on the rightmost side, there is no signal line03below the anode013C, so the anode013C does not tilt. Since the anodes of sub-pixels of different colors tilt in different directions and degrees, intensities of light emitted from the three sub-pixels toward left and right sides do not match with each other. In this case, when an image displayed on display substrate is observed at a large viewing angle, color shift may occur. For example, the displayed image may turn red when it is observed from one side, and the displayed image may turn green when it is observed from the other side. FIG.4is a schematic plan view of a display substrate according to some embodiments of the present disclosure. For example, the display substrate may be an array substrate for an OLED display panel. Referring toFIG.4, the display substrate may include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA may include multiple boundaries, such as AAS1, AAS2, AAS3, and AAS4as shown inFIG.4. The display substrate may further include a driving circuit located in the non-display area NA. For example, the driving circuit may be located in at least one side of the display area AA. In the embodiment shown inFIG.4, the driving circuits are respectively located in left and right sides of the display area AA. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) viewed by human eyes during display. The driving circuits are configured to drive pixels in the display substrate for display. For example, the driving circuits may include a gate driving circuit and a data driving circuit. The data driving circuit is configured to sequentially latch input data according to a clock signal, then convert the latched data into an analog signal, and input the analog signal to respective data lines of the display substrate. The gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage and outputs the on/off voltage to respective gate lines of the display substrate. It should be noted that althoughFIG.4illustrates that the driving circuit is located in the left and right sides of the display area AA, but the embodiment of the present disclosure is not limited to this, and the driving circuit may be located at any suitable position in the non-display area NA. For example, the driving circuit may adopt GOA technology, that is, Gate Driver on Array. In GOA technology, the gate driving circuit is directly arranged on the array substrate to replace an external driving chip. Each GOA unit acts as a stage of a shift register, and each stage of the shift register is connected to one gate line. The turn-on voltage is output in turn through each stage of the shift register to scan the pixels one-row by one-row. In some embodiments, each stage of the shift register may also be connected to multiple gate lines, thereby adapting to a development trend of high resolution and narrow frame of the display substrate. Referring toFIG.4, a left GOA circuit DA1, a plurality of pixels Pin the display area AA, and a right GOA circuit DA2are provided on the display substrate. The left GOA circuit DA1and the right GOA circuit DA2are respectively electrically connected to a display IC through signal lines, and the supply of the GOA signal is controlled by the display IC. The display IC is, for example, arranged on the lower side of the display substrate (in the direction observed by human eyes). The left GOA circuit DA1and the right GOA circuit DA2are also electrically connected to the pixels through signal lines (for example, gate lines GL) to supply a driving signal to the pixels. FIG.5is a partial enlarged view of the display substrate according to some embodiments of the present disclosure at part I inFIG.4, andFIG.6is a cross-section of the display substrate according to some embodiments of the present disclosure taken along line BB′ inFIG.5. It should be noted that in order to clearly illustrate the relative positional relationship between a signal line, a planarization layer and an anode, some other film layer structures included in the display substrate are omitted inFIGS.5and6. It should also be noted thatFIG.5exemplarily illustrates that a shape of an orthographic projection of a sub-pixel on a base substrate is a rounded rectangle, but the embodiments of the present disclosure are not limited to this, for example, the shape of the orthographic projection of the sub-pixel on the base substrate may be rectangular, hexagonal, pentagonal, square, circular and other shapes. Moreover, the arrangement of three sub-pixels in one pixel unit is not limited to the form shown inFIG.5. Referring toFIGS.4,5and6in combination, the display substrate may include a base substrate1, and a plurality of pixel units P arranged on the base substrate1and located in the display area AA. Each pixel unit P may include a plurality of sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For ease of understanding, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3may be described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, but the embodiments of the present disclosure are not limited thereto. The plurality of sub-pixels are arranged on the base substrate1in an array in a row direction X and in a column direction Y. It should be noted that although in the illustrated embodiments, the row direction X and the column direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited to this. It should be understood that each sub-pixel includes a pixel driving circuit and a light-emission device. For example, the light-emission device may be an OLED light-emission device, including an anode, an organic light-emission layer, and a cathode that are stacked onto each other. The pixel driving circuit may include a plurality of thin film transistors. Referring toFIGS.5and6in combination, the display substrate may include a first signal line31on the base substrate1, a planarization layer4disposed on the base substrate1and covering the first signal line31, and an anode5on a side of the planarization layer4away from the base substrate1. The first signal line31is configured to supply signals required by sub-pixels located in the display area AA. Hereinafter, the signal line will be described in detail. Referring toFIG.5, the display substrate may further include a dummy pixel column and a signal line transfer structure7, wherein the signal line transfer structure7is arranged between the dummy pixel column and the GOA circuit. The dummy pixel column includes a plurality of dummy sub-pixels. The dummy pixel column is located at an edge position of the display area AA close to the GOA circuit. The plurality of dummy sub-pixels are arranged in a column direction Y. It should be noted that the signal line transfer structure will be described in detail below in conjunction with the drawings. As shown inFIG.5, an orthographic projection of the anode5on the base substrate1at least partially overlaps with an orthographic projection of the first signal line31on the base substrate1, for example, the orthographic projection of the anode5on the base substrate1covers at least a part of the orthographic projection of the first signal line31on the base substrate1. For one column of sub-pixels closest to the GOA circuit, for example, the leftmost column of sub-pixels inFIG.5, an orthographic projection of the anode5of each sub-pixel on the base substrate1at least partially overlaps with an orthographic projection of a dummy sub-pixel on the base substrate. Specifically, the dummy sub-pixel includes a cushion structure6. The cushion structure6may be located in the same layer as the first signal line31, that is, the cushion structure6and the first signal line31may be made of the same material and formed by the same patterning process. For example, the cushion structure6and the first signal line31may be located in the same layer as the source/drain electrodes of the thin film transistor. In this way, a thickness of the cushion structure6is approximately equal to a thickness of the first signal line31. For the leftmost column of sub-pixels inFIG.5, the orthographic projection of the anode5of each sub-pixel on the base substrate1at least partially overlaps with an orthographic projection of the cushion structure6of the dummy sub-pixel on the base substrate1. Herein, for the convenience of description, a sub-pixel located at the edge of the display area close to the non-display area may be called an edge sub-pixel. For example, the leftmost column of sub-pixels inFIG.5includes a plurality of edge sub-pixels. In some embodiments, a boundary between the display area and the non-display area may be determined according to the column of sub-pixels for display when the display substrate emits light. For example, a left boundary between the display area and the non-display area may be located on the left side of the leftmost column of edge sub-pixels close to the non-display area, and the leftmost column of edge sub-pixels close to the non-display area may be located in the display area. For example, the plurality of sub-pixels include at least one array of edge sub-pixels located at an edge position of the display area close to the non-display area. For example, the at least one array of edge sub-pixels may include one column of edge sub-pixels, and/or may include one row of edge sub-pixels. And for example, the at least one array of edge sub-pixels may include two columns of edge sub-pixels on opposite sides, and/or two rows of edge sub-pixels on opposite sides. For example, in some embodiments, the display area may be approximately rectangular. In this case, the at least one array of edge sub-pixels may include two columns of sub-pixels, wherein the two columns of sub-pixels are located in two opposite sides of the rectangle and close to the non-display area. With reference toFIGS.4and5in combination, the at least one array of edge sub-pixels may include some edge sub-pixels disposed close to the boundaries AAS1and AAS3, or in other words, the at least one array of edge sub-pixels is located on a side where the GOA circuit is located. In the examples ofFIGS.4and5, the GOA circuits are located on the left and right sides. Accordingly, the at least one array of edge sub-pixels includes edge sub-pixels located at the left and right edges of the display area AA, that is, the at least one array of edge sub-pixels may include the leftmost column of sub-pixels and the rightmost column of sub-pixels. That is, the first signal line31is provided below one side of the anode5of each edge sub-pixel, the cushion structure6is provided below the other side of the anode5of each edge sub-pixel, and the thickness of the first signal line31is equal to the thickness of cushion structure6. In this way, the plainness of the anode5may be improved, and the slope of the anode5may be avoided, so that a color shift phenomenon of the display substrate may be improved. The inventor discovered that since the signal lines are relatively concentrated at the edge of the display area, the tilt phenomenon of anodes of sub-pixels located at the edge of the display area is more obvious. In the embodiments of the present disclosure, the anodes of the sub-pixels located at the edge of the display area is padded by the structure in the dummy sub-pixels located at the edge of the display area, so that the anode tilt phenomenon at the edge may be improved, and the color shift phenomenon of the display substrate may be improved effectively. Hereinafter, a signal line transfer structure included in a display substrate according to some embodiments of the present disclosure will be described in detail with reference to the drawings. FIG.7A,FIG.8AandFIG.9Aare respectively schematic views of a signal line transfer structure of the display substrate according to some embodiments of the present disclosure. Referring toFIG.7A,FIG.8AandFIG.9A, the display substrate may include: a second signal line32at least in the display area AA, a signal line lead8in the non-display area NA, and a signal line transfer structure7at least in the non-display area NA. One end of the second signal line32(for example, an end away from the signal line lead) is connected to a pixel driving circuit of a sub-pixel. One end of the signal line lead8(for example, an end away from the second signal line32) is connected to a GOA circuit. One end of the signal line transfer structure7is connected to the other end of the second signal line32, and the other end of the signal line transfer structure7is connected to the other end of the signal line lead8. In the embodiments of the present disclosure, the second signal line32and the signal line lead8are two independent portions, wherein the two independent portions means that the second signal line32and the signal line lead8are spaced apart from each other, that is, orthographic projections of the second signal line32and the signal line lead8on the base substrate1are not in contact with each other. In this way, even if a large amount of static charge is accumulated on the signal line lead8in the non-display area NA, the second signal line32and the signal line lead8are two independent portions in the embodiments of the present disclosure, before the signal line32and the signal line lead8are connected by the signal line transfer structure7, a large amount of static charge accumulated on the signal line lead8in the non-display area NA may not be transferred to the second signal line32in the display area AA, thereby reducing the probability of damage to electronic devices in the display area AA that are electrically connected to the second signal line32(for example, transistors T2and T3in a pixel driving circuit mentioned hereinafter) due to electrostatic impact, thus the product yield may be improved. In some exemplary embodiments, at least one of the second signal line32and the signal line lead8is located in a different layer from the signal line transfer structure7. For example, the second signal line32and the signal line lead8may be located in the same layer, that is, the second signal line32and the signal line lead8are made of the same material and formed by one patterning process. Optionally, the second signal line32and the signal line lead8may be located in different layers, that is, the second signal line32and the signal line lead8need to be formed by two patterning processes, which are not limited in the embodiment of the present disclosure. The setting method may be selected according to the type of the display substrate and the type of the signal line, as long as the signal line transfer structure7, the second signal line32and the signal line lead8are not located in the same layer and are not directly connected, that is, the signal line transfer structure7, the second signal line32, and the signal line lead8are arranged in at least two layers. FIG.7Bis a cross-sectional view taken along line CC′ inFIG.7A. Referring toFIGS.7A and7Bin combination, the second signal line32and the signal line lead8are located in the same layer, and they are located in a different layer from the signal line transfer structure7. An insulating layer101is provided between the layer where the second signal line32and the signal line lead8are located and the layer where the signal line transfer structure7is located. A first via hole V1and a second via hole V2are formed in the insulating layer101. For example, the second signal line32and the signal line lead8may be located in the same layer as source/drain electrodes of a thin film transistor, that is, the second signal line32and the signal line lead8may be made of material forming the source/drain electrodes. The signal line transfer structure7may be located in a side of the layer where the second signal line32and the signal line lead8are located away from the base substrate1. The signal line transfer structure7may also be made of, for example, material forming the source/drain electrodes. Of course, the embodiments of the present disclosure are not limited to this, and the second signal line32, the signal line lead8and the signal line transfer structure7may also be made of other conductive materials. The insulating layer101may be made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The insulating layer101may have a single film layer structure or a stacked structure composed of a plurality of film layers. The first via hole V1passes through the insulating layer101to expose a part of the second signal line32. The second via hole V2passes through the insulating layer101to expose a par of the signal line lead8. A part of the signal line transfer structure7is formed in the first via hole V1to form a first conductive plug71, and the signal line transfer structure7is in contact with the second signal line32through the first conductive plug71. Another part of the signal line transfer structure7is formed in the second via hole V2to form a second conductive plug72, and the signal line transfer structure7is in contact with the signal line lead8through the second conductive plug72. FIG.8Bis a cross-sectional view taken along line CC′ inFIG.8A. Referring toFIGS.8A and8Bin combination, the second signal line32and the signal line lead8are located in different layers, and the signal line transfer structure7and the signal line lead8may be located in the same layer. One end of the signal line transfer structure7is directly connected to the signal line lead8. Optionally, the signal line transfer structure7and the signal line lead8may be continuously extended, that is, the signal line transfer structure7and the signal line lead8are formed in an integral structure. An insulating layer101is provided between the second signal line32and the layer where the signal line transfer structure7and the signal line lead8are located. A first via hole V1is provided in the insulating layer101. The first via hole V1passes through the insulating layer101to expose a part of the second signal line32. A part of the signal line transfer structure7is formed in the first via hole V1to form a first conductive plug71, and the signal line transfer structure7is in contact with the second signal line32through the first conductive plug71. FIG.9Bis a cross-sectional view taken along line CC′ inFIG.9A. Referring toFIGS.9A and9Bin combination, the second signal line32and the signal line lead8are located in different layers, and the signal line transfer structure7and the second signal line32may be located in the same layer. One end of the signal line transfer structure7is directly connected to the second signal line32. Optionally, the signal line transfer structure7and the second signal line32may extend continuously, that is, the signal line transfer structure7and the second signal line32are formed in an integral structure. An insulating layer101is provided between the signal line lead8and the layer where the signal line transfer structure7and the second signal line32are located. A second via hole V2is provided in the insulating layer101. The second via hole V2passes through the insulating layer101to expose a part of the signal line lead8. A part of the signal line transfer structure7is formed in the second via hole V2to form a second conductive plug72, and the signal line transfer structure7is in contact with the signal line lead8through the second conductive plug72. FIG.10is a partial enlarged view of the display substrate according to some embodiments of the present disclosure at part I inFIG.4, andFIG.11is a cross-section of the display substrate according to some embodiments of the present disclosure taken along line DD′ inFIG.10. It should be noted that, in order to clearly illustrate the relative positional relationship between a signal line, a planarization layer and an anode, some other film layer structures included in the display substrate are omitted inFIGS.10and11. In the following, the differences between the embodiments and the above-mentioned embodiments with reference toFIG.4andFIG.5will be mainly described. For similarities between the embodiments, which may be refer the above description and will not be repeated here. Referring toFIGS.4,10, and11, in some embodiments of the present disclosure, the dummy pixel column is omitted. In other words, there is no dummy pixel column between the pixel unit P located in the display area AA and the GOA circuit. In this way, the width of the non-display area NA may be further reduced, thereby realizing a display panel and a display device with a narrow frame. Referring toFIGS.10and11in combination, the display substrate may include the first signal line31on the base substrate1, the planarization layer4on the base substrate1and covering the first signal line31, and the anode5on a side of the planarization layer4away from the base substrate1. The display substrate may further include the signal line transfer structure7at a position of the display area AA close to the edge of the GOA circuit. As shown inFIG.10, the plurality of signal line transfer structures7may be arranged in the column direction Y. As shown inFIG.10, the edge sub-pixels include at least one column of edge sub-pixels, and the at least one column of edge sub-pixels are arranged in a direction that is substantially the same as an extending direction of the first signal line31, and the plurality of signal line transfer structures7are arranged in the direction that is substantially the same as the extending direction of the first signal line31. As shown inFIG.10, an orthographic projection of the anode5on the base substrate1at least partially overlaps with an orthographic projection of the first signal line31on the base substrate1, for example, the orthographic projection of the anode5on the base substrate1covers the orthographic projection of the first signal line31on the base substrate1. For one column of sub-pixels closest to the GOA circuit, for example, the leftmost column of sub-pixels inFIG.10, that is, for a plurality of edge sub-pixels, orthographic projections of the anodes5of the edge sub-pixels on the base substrate1at least partially overlap with orthographic projections of respective signal line transfer structures7on the base substrate1. It should be noted that, for other sub-pixels except the plurality of edge sub-pixels, for example, a plurality of sub-pixels located inside the display area, the plurality of sub-pixels are all located between two adjacent first signal lines31. That is, an orthographic projection of a side of the anode5of one sub-pixel on the base substrate1at least partially overlaps with an orthographic projection of one first signal line31on the base substrate1, an orthographic projection of an opposite side of the anode5of the sub-pixel on the base substrate1at least partially overlaps with an orthographic projection of another adjacent first signal line31on the base substrate1. For example, the at least one array of edge sub-pixels may include a plurality of red sub-pixels and a plurality of blue sub-pixels alternately arranged in the column direction. An orthographic projection of the anode5of each green sub-pixel on the base substrate1does not overlap with an orthographic projection of the signal line transfer structure7on the base substrate1. For example, as described above, the orthographic projection of the anode5of each green sub-pixel on the base substrate1may at least partially overlaps with the orthographic projection of each of two adjacent first signal lines31on the base substrate1. Specifically, referring toFIG.11, the first signal line31is provided below one side of the anode5of each edge sub-pixel, and the signal line transfer structure7is provided below the other side of the anode5of each edge sub-pixel. More specifically, the anode5of each edge sub-pixel includes a first edge portion51close to the non-display area NA and a second edge portion52away from the non-display area NA (the first edge portion51and the second edge portion52will be described in detail below). An orthographic projection of the first edge portion51on the base substrate1at least partially overlaps with the orthographic projection of the signal line transfer structure7on the base substrate1, and an orthographic projection of the second edge portion52on the base substrate1at least partially overlaps with the orthographic projection of the first signal line31on the base substrate1. For example, the first signal line31and the signal line transfer structure7are located in the same layer, and the first signal line31and the signal line transfer structure7may be located in the same layer as source/drain electrodes of a thin film transistor, that is, the first signal line31and the signal line transfer structure7may be made of materials forming the source/drain electrodes and formed by the same patterning process. In this way, the thickness of the first signal line31may be equal to the thickness of the signal line transfer structure7, that is, the thickness of the signal line transfer structure7in the direction perpendicular to the base substrate1is equal to the thickness of the first signal line31in the direction perpendicular to the base substrate1. With continued reference toFIG.11, the planarization layer4includes a first surface portion41and a second surface portion42. An orthographic projection of the first surface portion41on the base substrate1at least partially overlaps with the orthographic projection of the signal line transfer structure7on the base substrate1, and an orthographic projection of the second surface portion42on the base substrate1at least partially overlaps with the orthographic projection of the first signal line31on the base substrate1. A distance between the first surface portion41and the base substrate1in the direction perpendicular to the base substrate1is approximately equal to a distance between the second surface portion42and the base substrate1in the direction perpendicular to the base substrate1, or the ratio of the distances is approximately 0.8 to 1.2. It should be noted that, inFIG.11, the relative positional relationship of the signal line transfer structure, the signal line, the planarization layer, and the anode is schematically illustrated. Limited by the actual processing technology, the first surface portion41and the second surface portion42of the planarization layer4may have a height error. In such a case, the distance between the first surface portion41and the base substrate1in the direction perpendicular to the base substrate1may be understood as the maximum distance between the first surface portion41and the base substrate1in the direction perpendicular to the base substrate1, and the distance between the second surface portion42and the base substrate1in the direction perpendicular to the base substrate1may be understood as the maximum distance between the second surface portion42and the base substrate1in the direction perpendicular to the base substrate1; or, the distance between the first surface portion41and the base substrate1in the direction perpendicular to the base substrate1may be understood as an average distance between the first surface portion41and the base substrate1in the direction perpendicular to the base substrate1, and the distance between the second surface portion42and the base substrate1in the direction perpendicular to the base substrate1may be understood as an average distance between the second surface portion42and the base substrate1in the direction perpendicular to the base substrate1. In this way, the plainness of the anode5may be improved, so that a distance between the first edge portion51of the anode5and the base substrate1in the direction perpendicular to the base substrate1is substantially equal to a distance between the second edge portion52and the base substrate1in the direction perpendicular to the base substrate1. Therefore, the anode5may not tilt, so that color shift of the display substrate may be improved. Based on the above description, the distance between the first edge51of the anode5and the base substrate1in the direction perpendicular to the base substrate1may be understood as the maximum distance between the first edge51of the anode5and the base substrate1in the direction perpendicular to the base substrate1, and the distance between the second edge portion52and the base substrate1in the direction perpendicular to the base substrate1may be understood as the maximum distance between the second edge portion52and the base substrate1in the direction perpendicular to the base substrate1. Alternatively, the distance between the first edge51of the anode5and the base substrate1in the direction perpendicular to the base substrate1may be understood as an average distance between the first edge51of the anode5and the base substrate1in the direction perpendicular to the base substrate1, and the distance between the second edge portion52and the base substrate1in the direction perpendicular to the base substrate1may be understood as an average distance between the second edge portion52and the base substrate1in the direction perpendicular to the base substrate1. In addition, in the embodiments of the present disclosure, the signal line transfer structure is used to cushion the anode, and the dummy pixel column is omitted. While improving the plainness of anode, the width of the non-display area may be reduced, which is beneficial to realize a display device with a narrow frame. Hereinafter, by taking 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit will be described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit, and other known pixel driving circuit structures may be applied to the embodiments of the present disclosure under the condition of no conflict. FIG.12is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some embodiments of the present disclosure. As shown inFIG.12, the pixel driving circuit may include a plurality of signal lines61,62,63,64,65,66and67, a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The pixel driving circuit is configured to drive an organic light-emission diode (i.e., OLED). The plurality of thin film transistors include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, a first light-emission control thin film transistor T5, a second light-emission control thin film transistor T6, and a bypass thin film transistor T7. The plurality of signal lines include: a scan signal lines61for transmitting scan signals Sn, a reset control signal line62for transmitting reset control signal Sn−1 to the initialization thin film transistor T4, a light-emission control line63for transmitting light-emission control signal En to the first light-emission control thin film transistor T5and the second light-emission control thin film transistor T6, a data line64for transmitting data signals Dm, a driving voltage line65for transmitting driving voltage ELVDD, an initializing voltage line66for transmitting initialization voltage Vint for initializing the driving thin film transistor T1, and a power supply line67for transmitting ELVSS voltage. A gate electrode G1of the driving thin film transistor T1is electrically connected to an end Cst1(hereinafter referred to as a first capacitor electrode) of the storage capacitor Cst, a source electrode S1of the driving thin film transistor T1is electrically connected to the driving voltage line65through the first light-emission control thin film transistor T5, and a drain electrode D1of the driving thin film transistor T1is electrically connected to an anode of the OLED through the second light-emission control thin film transistor T6. The driving thin film transistor T1receives a data signal Dm according to a switching operation of the switching thin film transistor T2, so as to supply a driving current Id to the OLED. A gate electrode G2of the switching thin film transistor T2is electrically connected to the scan signal line61, a source electrode S2of the switching thin film transistor T2is electrically connected to the data line64. A drain electrode D2of the switching thin film transistor T2is electrically connected to the driving voltage line65through the first light-emission control thin film transistor T5and is also electrically connected to the source electrode S1of the driving thin film transistor T1. The switching thin film transistor T2is turned on according to the scan signal Sn transmitted through the scan signal line61, then performs a switching operation to transmit the data signal Dm transmitted to the data line64to the source electrode S1of the driving thin film transistor T1. A gate electrode G3of the compensation thin film transistor T3is electrically connected to the scan signal line61, a source electrode S3of the compensation thin film transistor T3is electrically connected to the anode of the OLED via the second light-emission control thin film transistor T6and is electrically connected to the drain electrode D1of the driving thin film transistor T1. A drain electrode D3of the compensation thin film transistor T3is electrically connected to one end Cst1(i.e., the first capacitor electrode) of the storage capacitor Cst, a drain electrode D4of the initialization thin film transistor T4, and the gate electrode G1of the driving thin film transistor T1. The compensation thin film transistor T3is turned on according to the scan signal Sn transmitted through the scan signal line61, so that the gate electrode G1of the driving thin film transistor T1is connected to the drain electrode D1of the driving thin film transistor T1, thereby performing diode connection for the driving thin film transistor T1. A gate electrode G4of the initialization thin film transistor T4is electrically connected to the reset control signal line62, and a source electrode S4of the initialization thin film transistor T4is electrically connected to the initializing voltage line66. In addition, the drain electrode D4of the initializing thin film transistor T4is electrically connected to one end Cst1of the storage capacitor Cst, the drain electrode D3of the compensation thin film transistor T3, and the gate electrode G1of the driving thin film transistor T1. The initialization thin film transistor T4is turned on according to the reset control signal Sn−1 transmitted through the reset control signal line62, thereby, an initialization operation is performed to initialize a voltage of the gate electrode G1of the driving thin film transistor T1. A gate electrode G5of the first light-emission control thin film transistor T5is electrically connected to the light-emission control line63, and a source electrode S5of the first light-emission control thin film transistor T5is electrically connected to the driving voltage line65. A drain electrode D5of the first light-emission control thin film transistor T5is electrically connected to the source electrode S1of the driving thin film transistor T1and is electrically connected to the drain electrode D2of the switching thin film transistor T2. A gate electrode G6of the second light-emission control thin film transistor T6is electrically connected to the light-emission control line63, a source electrode S6of the second light-emission control thin film transistor T6is electrically connected to the drain electrode D1of the driving thin film transistor T1and is electrically connected to the source electrode S3of the compensation thin film transistor T3. A drain electrode D6of the second light-emission control thin film transistor T6is electrically connected to the anode of the OLED. The first light-emission control thin film transistor T5and the second light-emission control thin film transistor T6are turned on simultaneously according to the light-emission control signal En transmitted through the light-emission control line63, to transmit the driving voltage ELVDD to the OLED, thereby allowing the driving current Id to flow into the OLED. The bypass thin film transistor T7includes a gate electrode G7, a source electrode S7and a drain electrode D7. The gate electrode G7is connected to the reset control signal line62, the source electrode S7is connected to the drain electrode D6of the second light-emission control thin film transistor T6and the anode electrode of the OLED, and the drain electrode D7is connected to the initializing voltage line66. The bypass thin film transistor T7transmits the reset control signal Sn−1 from the reset control signal line62to the gate electrode G7. The other end Cst2(hereinafter referred to as a second capacitance electrode) of the storage capacitor Cst is electrically connected to the driving voltage line65, and a cathode of the OLED is electrically connected to the power supply line67to receive a common voltage ELVSS. Accordingly, the OLED receives the driving current Id from the driving thin film transistor T1to emit light, thereby displaying an image. It should be noted that, inFIG.12, the thin film transistors T1, T2, T3, T4, T5, T6, and T7each have a single gate structure, but the embodiments of the present disclosure are not limited thereto, at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7may have a dual gate structure. InFIG.12, the thin film transistor T1, T2, T3, T4, T5, T6, and T7each are p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7may be n-channel field effect transistors. In operation, during initialization phase, the reset control signal Sn−1 with a low level is supplied through the reset control signal line62. Next, the initialization thin film transistor T4is turned on based on the low level of the reset control signal Sn−1, and the initialization voltage Vint from the initializing voltage line66is transmitted to the gate electrode G1of the driving thin film transistor T1through the initialization thin film transistor T4. Therefore, the driving thin film transistor T1is initialized due to the initialization voltage Vint. During data programming phase, the scan signal Sn with a low level is supplied through the scan signal line61. Next, the switching thin film transistor T2and the compensation thin film transistor T3are turned on based on the low level of the scan signal Sn. Therefore, the driving thin film transistor T1is placed in a diode connection state due to the turned-on compensation thin film transistor T3, and the driving thin film transistor T1is biased in a forward direction. Next, a compensation voltage Dm+Vth (for example, Vth is a negative value) is obtained by subtracting a threshold voltage Vth of the driving thin film transistor T1from the data signal Dm supplied via the data line64, and the compensation voltage Dm+Vth is applied to the gate electrode G1of the driving thin film transistor T1. Next, the driving voltage ELVDD and the compensation voltage Dm+Vth are applied to two ends of the storage capacitor Cst, so that the electric charge corresponding to a voltage difference between the two ends is stored in the storage capacitor Cst. During the light-emission phase, the light-emission control signal En from the light-emission control line63changes from a high level to a low level. Next, during the light emission phase, the first light-emission control thin film transistor T5and the second light-emission control thin film transistor T6are turned on based on a low level of the light-emission control signal En. Next, a driving current is generated based on a difference between the voltage of the gate electrode G1of the driving thin film transistor T1and the driving voltage ELVDD. The driving current Id corresponding to a difference between the driving current and the bypass current is supplied to the OLED through the second light-emission control thin film transistor T6. During the light-emission phase, based on the current-voltage relationship of the driving thin film transistor T1, a gate-source voltage of the driving thin film transistor T1is maintained at (Dm+Vth)-ELVDD due to the storage capacitor Cst. The driving current Id is proportional to (Dm-ELVDD)2. Therefore, the driving current Id may not be affected by a variation of the threshold voltage Vth of the driving thin film transistor T1. FIG.13is a plan view illustrating an exemplary embodiment of sub-pixels in a display area AA of a display substrate according to some embodiments of the present disclosure.FIGS.14to17are plan views illustrating some film layers of an exemplary embodiment of the sub-pixels inFIG.13. For example,FIGS.14to17schematically illustrate a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer, respectively. With reference toFIGS.12to17, sub-pixels include a scan signal lines61arranged in a row direction to apply a scan signal Sn to the sub-pixels, a reset control signal line62arranged in a row direction to apply a reset control signal Sn−1 to the sub-pixels, an light-emission control line63arranged in a row direction to apply a light-emission control signal En to the sub-pixels, and an initializing voltage line66arranged in a row direction to apply an initialization voltage Vint to the sub-pixels. The sub-pixels may include a data line64and a driving voltage line65that cross a scan signal line61, a reset control signal line62, a light-emission control line63, and an initializing voltage line66to respectively apply a data signal Dm and a driving voltage ELVDD to the sub-pixels. The sub-pixels may include: a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, a first light-emission control thin film transistor T5, a second light-emission control thin film transistor T6, a bypass thin film transistor T7, a storage capacitor Cst and an organic light-emission diode OLED. The driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the initializing thin film transistor T4, the first light-emission control thin film transistor T5, the second light-emitting control thin film transistor T6, and the bypass thin film transistor T7may be formed along an active layer as shown inFIG.10. The active layer may have a curved or bent shape, and the active layer may include a driving active layer20acorresponding to the driving thin film transistor T1, a switching active layer20bcorresponding to the switching thin film transistor T2, a compensation active layer20ccorresponding to the compensation thin film transistor T3, an initialization active layer20dcorresponding to the initialization thin film transistor T4, an operation control active layer20ecorresponding to the first light-emission control thin film transistor T5, a light-emission control active layer20fcorresponding to the second light-emission control thin film transistor T6and a bypass active layer20gcorresponding to the bypass thin film transistor T7. The active layer may include, for example, a polysilicon. For example, the active layer may include a channel region, a source region, and a drain region. The channel region may not be doped, or the doping type of the channel region is different from the doping types of the source region and the drain region, and therefore the channel region has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region, and the source region and the drain region are doped with impurities, and therefore the source region and the drain region have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor. The driving thin film transistor T1includes a driving active layer20aand a driving gate electrode G1. The driving active layer20aincludes a driving source region203a, a driving drain region205a, a driving channel region201aconnecting the driving source region203aand the driving drain region205a. The driving source region203aand the driving drain region205aextend in two opposite directions with respect to the driving channel region201a. The driving source region203aof the driving thin film transistor T1is connected to a switch drain region205band an operation control drain region205e. The driving drain region205ais connected to a compensation source region203cand a light-emission control source region203f. The driving gate electrode G1of the driving thin film transistor T1is connected to a compensation gate electrode G3of the compensation thin film transistor T3through via holes VAH1and VAH2and the first connection line68. The switching thin film transistor T2includes a switching active layer20band a switching gate electrode G2. The switch active layer20bincludes a switch channel region201b, a switch source region203b, and a switch drain region205b. The switching thin film transistor T2is used as a switching device for selecting a target sub-pixel to emit light. The switch gate electrode G2is connected to the scan signal line61, the switch source region203bis connected to the data line64through a via hole VAH4, and the switch drain region205bis connected to the driving thin film transistor T1and the first light-emission control thin film transistor T5. The compensation thin film transistor T3includes a compensation active layer20cand a compensation gate electrode G3. The compensation active layer20cincludes a compensation channel region201c, a compensation source region203c, and a compensation drain region205c. The initialization thin film transistor T4includes an initialization active layer20dand an initialization gate electrode G4. The initialization active layer20dincludes an initialization channel region201d, an initialization source region203d, and an initialization drain region205d. The initialization source region203dis connected to the initializing voltage line66through a via hole VAH5. The first light-emission control thin film transistor T5includes an operation control active layer20eand an operation control gate electrode G5. The operation control active layer20eincludes an operation control channel region201e, an operation control source region203e, and an operation control drain region205e. The operation control source region203emay be connected to the driving voltage line65through a via hole VAH6. The second light-emission control thin film transistor T6includes a light-emission control active layer20fand a light-emission control gate electrode G6, and the light-emission control active layer20fincludes a light-emission control channel region201f, a light-emission control source region203f, and a light-emission control drain region205fThe light-emission control drain region205fmay be connected to the anode of the OLED through a via hole VAH7. The bypass thin film transistor T7includes a bypass active layer20gand a bypass gate electrode G7. The bypass active layer20gincludes a bypass source region203g, a bypass drain region205g, and a bypass channel region201g. The bypass drain region205gis connected to the initialization source region203dof the initialization thin film transistor T4. The bypass drain region205gmay be connected to the initializing voltage line66through the via VAH8and the second connection line69. As shown inFIGS.12to17, some signal lines are schematically shown, for example, the scan signal lines61arranged in the row direction to apply the scan signal Sn to sub-pixels, the reset control signal line62arranged in the row direction to apply the reset control signal Sn−1 to sub-pixels, the light-emission control line63arranged in the row direction to apply the light-emission control signal En to sub-pixels, and the initializing voltage line66arranged in the row direction to apply the initialization voltage Vint to sub-pixels, the data line64and the driving voltage line65that cross the scan signal line61, the reset control signal line62, the light-emission control line63and the initializing voltage line66to respectively apply the data signal Dm and the driving voltage ELVDD to sub-pixels. In the embodiments of the present disclosure, the GOA circuit may include a first scan driving circuit, for example, the first scan driving circuit may be an EM GOA circuit for transmitting a light-emission control signal En. As shown inFIG.18, it schematically illustrates a circuit diagram of a first scan driving circuit according to some embodiments of the present disclosure. The first scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB, and a signal output line E0. The first scan driving circuit further includes a plurality of shift register units. As shown inFIG.18, at least one of the plurality of shift register units may include a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor M10, an output reset transistor M9, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. A gate electrode MG10of the output transistor M10is coupled to a first plate C2aof the output capacitor C2, a first electrode MS10of the output transistor M10is coupled to the second voltage signal line VGL, and a second electrode MD10of the output transistor M10is coupled to the signal output line E0. A gate electrode MG9of the output reset transistor M9is coupled to the first plate C3aof the output reset capacitor C3, a first electrode MS9of the output reset transistor M9is coupled to a second plate C3bof the output reset capacitor C3, and a second electrode MD9of the output reset transistor M9is coupled to the signal output line E0. The second plate C3bof the output reset capacitor C3is coupled to the first voltage signal line VGH, and the second plate C2bof the output capacitor C2is coupled to the second clock signal line CB. A first electrode MS1of the first transistor M1is coupled to the second clock signal line CB, a second electrode MD1of the first transistor M1and a first electrode MS2of the second transistor M2are respectively coupled to a second plate C1bof the first capacitor C1, a gate electrode MG1of the first transistor M1is coupled to a first plate C1aof the first capacitor C1. A gate electrode MG2of the second transistor M2and a gate electrode MG7of the seventh transistor M7are respectively coupled to the first clock signal line CB, a second electrode MD2of the second transistor M2is coupled to a second electrode MD3of the third transistor M3, and a first electrode MS2of the second transistor M2is coupled to a second plate C1bof the first capacitor. A gate electrode MG3of the third transistor M3is coupled to a gate electrode MG10of the output transistor M10, and a first electrode MS3of the third transistor M3is coupled to the first voltage signal line VGH. A gate electrode MG4of the fourth transistor M4and a gate electrode MG5of the fifth transistor M5are both coupled to the first clock signal line CK, a first electrode MS4of the fourth transistor M4and the first electrode MS10of the output transistor M10are both coupled to the second voltage signal line VGL, and a second electrode MD4of the fourth transistor M4is coupled to a second electrode MD6of the sixth transistor M6. The gate electrode MG5of the fifth transistor M5is coupled to the first clock signal line CK, a second electrode MD5of the fifth transistor M5is coupled to a gate electrode MG6of the sixth transistor M6, and a first electrode MS5of the fifth transistor M5is coupled to an input signal terminal E1. A first electrode MS1of the sixth transistor M6and the gate electrode MG4of the fourth transistor M4are both coupled to the first clock signal line CK, the second electrode MD6of the sixth transistor M6is coupled to the second electrode MD4of the fourth transistor M4, and the gate electrode MG6of the sixth transistor M6is coupled to a second electrode MD1of the fifth transistor. The gate electrode MG7of the seventh transistor M7and the second plate C2bof the output capacitor C2are both coupled to the second clock signal line CB, a first electrode MS7of the seventh transistor M7is coupled to a second electrode MD8of the eighth transistor M8, and a second electrode MD7of the seventh transistor M7is coupled to the gate electrode MG6of the sixth transistor M6. A gate electrode MG8of the eighth transistor M8is coupled to the gate electrode MG1of the first transistor M1, and a first electrode MS8of the eighth transistor M8is coupled to the first voltage signal line VGH. In the embodiments of the shift register unit shown inFIG.18, all transistors are p-type transistors, but the embodiments of the present disclosure are not limited thereto. In the embodiments of the present disclosure, a first electrode of a transistor may be a source electrode while a second electrode of a transistor may be a drain electrode; or, a first electrode of a transistor may be a drain electrode while a second electrode of a transistor may be a source electrode. InFIG.18, a node labeled N1is a first node, a node labeled N2is a second node, a node labeled N3is a third node, and a node labeled N4is a fourth node. In the embodiments shown inFIG.18, the first voltage signal line VGH may provide a high voltage VGH, and the second voltage signal line VGL may provide a low voltage VGL, but the embodiments are not limited to this. FIG.19is a sequence diagram of the scan driving circuit shown inFIG.18. With reference toFIG.18andFIG.19, an operation process of the shift register unit shown inFIG.18is exemplified. In first time period P1, E1provides high level, CK provides low level, CB provides high level, the M5and the M4are turned on, a potential of the N1is high level, the M6is turned off, a potential of the N2is low level, so the M7, the M3and the M10are turned off, the M8and the M1are turned on; at this time, a potential of the N3is high level and the CB provides high level, so the M2is turned off; since a voltage across capacitor does not change suddenly, a potential of the N4is maintained at high level of previous frame, the M9is turned off, and a potential of the light-emission control signal output by the E0is maintained at low level of previous frame. In second time period P2, the E1and the CK provide high level, the CB provides low level, the M5, the M6and the M4are turned off, the potential of the N1remains high level, the potential of the N2remains low level, the M7, the M8and the M1are turned on, the potential of the N3changes from high level to low level, the M2is turned on, the potential of the N4is low level, the M9is turned on, and the E0outputs high level; the M3and the M10are turned off. In third time period P3, the E1and the CB provide high level, the CK provides low level, the M5and the M4are turned on, the potential of the N1is high, the potential of the N2is low, and the M6and the M7are turned off, the M8and the M1are turned on, the potential of the N3changes from the low level of the previous period to the high level, the M2is turned off, the potential of the N4remains low level, the M9is turned on, and the E0outputs high level; the M3and the M10are turned off. In fourth time period P4, the E1and the CB provide low level, the CK provides high level, the M5and the M4are turned off, the potential of the N1is high level, the M6is turned off, the potential of the N2is maintained at low level; the M7, the M8and the M1are turned on, a voltage of the N3changes to low level, the M2is turned on, the potential of the N4is low level, the M9is turned on, the E0outputs high level; the M3and the M10are turned off. In fifth time period P5, the E1and the CK provide low level, the CB provides high level, the M5, the M6, and the M4are turned on, the potentials of the N1and the N2are both low level, the M7is turned off, the M7and the M1are turned on, the voltage of the N3becomes high level, the M2is turned off, the M3is turned on, a voltage of the N4becomes high level, the M9is turned off, the M10is turned on, and the E0outputs a low level. In sixth time period P6, the E1and the CB signals are at low level, the CK is at high level, the M1and the M3are turned off, the N1remains at low level, the M2is turned on, a voltage of the N2is at high level, and the M4and the M5are turned on, the M6is turned off, the N3is high level, the M7and M8are turned on, the N4is high level, the M9is turned off, the M10is turned on, and the E0outputs low level. In seventh time period P7, the E1and the CK provide low level, the CB provides high level, the M5, the M6and the M4are turned on, the potential of the N1and the N2are low level, the M7is turned off, the M8and the M1are turned on, the potential of the N3is high level, the M2is turned off, the M3is turned on, the potential of the N4is high level, the M9is turned off, the M10is turned on, and the E0outputs low level. In eighth time period P8, the E1and the CB provide low level, the CK provides high level, the M5and the M4are turned off, the potential of the N1is maintained at low level, the M6is turned on, the potential of the N2is high level, and the M7is turned on, the M8and the M1are turned off, the potential of the N3is high level, the M2and the M3are turned on, the voltage of the N4is high level, the M9is turned off, the M10is turned on, and the E0outputs low level. After the sixth time period P6, the M3is continuously turned on, the M9is continuously turned off, the M5periodically charges the C2, the potential of the N1remains low level, the M10is continuously turned on, and the E0outputs low level until the next frame E1receives input signal. In exemplary embodiments of the present disclosure, the GOA circuit may include a second scan driving circuit, for example, the second scan driving circuit may be a GATE GOA circuit for transmitting a scan signal Sn and/or a reset control signal Sn−1. For example, the GATE GOA circuit may correspond to pixel rows one to one, that is, one GATE GOA circuit corresponds to one row of pixels, in this case, a signal output by one GATE GOA circuit may be used as a scan signal of one row of pixels corresponding to the row of GATE GOA circuit, and also used as a reset control signal of next row of pixels. In other words, a scan signal of a row of pixels comes from a signal output by the GATE GOA circuit corresponding to the row of pixels, and a reset control signal of the row of pixels comes from a signal output from the GATE GOA circuit corresponding to previous row of pixels. It should be noted that, for EM GOA circuit, there may be two rows or four rows driving method, that is, an output signal of one EM GOA circuit may be used to drive two or four rows of pixels. As shown inFIG.20, a circuit diagram of a second scan driving circuit according to some embodiments of the present disclosure is schematically illustrated. The second scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a third clock signal line GCK, a fourth clock signal line GCB, and a signal output line GO. The second scan driving circuit further includes a plurality of shift register units. As shown inFIG.20, at least one of the plurality of shift register units may include a first capacitor C1, a second capacitor C2, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistors Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and a eighth transistor Q8. A gate electrode QG1of the first transistor Q1is coupled to the clock signal line GCK, a first electrode QS1is coupled to an input signal terminal GI, and a second electrode QD1is coupled to a gate electrode QG2of the second transistor Q2. A first electrode QS2of the second transistor Q2is coupled to the clock signal line GCK, and a second electrode QD2is coupled to a sixth node N6. A gate electrode QG3of the third transistor Q3is coupled to the clock signal terminal GCK, a first electrode QS3is coupled to the voltage signal line VGL, and a second electrode QD3is coupled to the sixth node N6. A gate electrode QG4of the fourth transistor Q4is coupled to the sixth node N6, a first electrode QS4is coupled to the voltage signal line VGH, and a second electrode QD4is coupled to the signal output line GO. A gate electrode QG5of the fifth transistor Q5is coupled to an eighth node N8, a first electrode QS5is coupled to the clock signal terminal QCB, and a second electrode QD5is coupled to the signal output line GO. A gate electrode QG6of the sixth transistor Q6is coupled to the sixth node N6, a first electrode QS6is coupled to the voltage signal line VGH, and a second electrode QD6is coupled to a seventh node N7. A gate electrode QG7of the seventh transistor Q7is coupled to the clock signal terminal GCB, a first electrode QS7is coupled to the seventh node N7, and a second electrode QD7is coupled to a fifth node N5. A gate electrode QG8of the eighth transistor Q8is coupled to the voltage signal line VGL, a first electrode QS8is coupled to the fifth node N5, and a second electrode QD8is coupled to the eighth node N8. One end of the first capacitor C1is coupled to the eighth node N8, and the other end of the first capacitor C1is coupled to the second electrode QD5of the fifth transistor Q5. One end of the second capacitor C2is coupled to the sixth node N6, and the other end of the second capacitor C2is coupled to the first electrode QS4of the fourth transistor Q4. With reference to the sequence diagrams ofFIG.20andFIG.21, an operation process of the shift register unit shown inFIG.20is exemplified. In time period t1, the second scan driving circuit receives a low potential pulse GSTV output by previous stage, a alternating signal GCK is at low level, at this time, the transistors Q1, Q2, Q3, Q4, Q5, Q6, and Q8are turned on, and the signal output line GO outputs high level. In time period t2, potentials of GCK and GCB are reversed, and only the transistors Q2, Q5and Q7are turned on, at this time, a low-level signal GCB is output to the signal output line GO through the transistor Q5, the transistor Q4is turned off, so the voltage signal VGH may not be output and the signal output line GO outputs low level. In time period t3, GCK becomes low level, GCB becomes high level, and the signal output line GO outputs high level. That is, only in the time period t2, the signal output line GO outputs the low level. FIG.22is an enlarged view of a signal line transfer structure of a display substrate according to some embodiments of the present disclosure. Referring toFIGS.13,15,20and22, the signal line transfer structure7is configured to transfer the signal output line GO of the second scan driving circuit to the scan signal line61and the reset control signal line62, that is, the signal line transfer structure7is configured to transfer gate scan signal and reset control signal. FIG.24is a timing diagram of light-emission control signals, scan signals, and reset control signals for driving multiple adjacent rows of pixels of a display substrate according to some embodiments of the present disclosure. As mentioned above, an output signal of one EM GOA circuit may be used to drive two or four rows of pixels. Then, a light-emission control signal En shown inFIG.24may be used to drive adjacent rows of pixels (such as two or four rows), for example, the light-emission control signal En may be used as light-emission control signals for pixel driving circuits of pixels in nthrow and (n+1)throw, or the light-emission control signal En may be used as the light-emission control signals for the pixel driving circuits of the pixels in nthrow, (n+1)throw, (n+2)throw, and (n+3)throw. A scan signal for a certain row of pixels comes from signal output by the GATE GOA circuit corresponding to the row of pixels, and a reset control signal for the row of pixels comes from signal output by the GATE GOA circuit corresponding to previous row of pixels. Then, the signal Sn−1 shown inFIG.24may be used as scan signal for the pixel driving circuits of pixels in (n−1)throw, and the signal Sn−1 may be used as reset control signal for the pixel driving circuits of pixels in nthrow. The signal Sn shown inFIG.24may be used as scan signal for the pixel driving circuits of pixels in nthrow, and the signal Sn may be used as reset control signal for the pixel driving circuits of pixels in (n+1)throw. The scan signal Sn+1 shown inFIG.24may be used as scan signal for the pixel driving circuits of pixels in (n+1)throw, and the signal Sn+1 may be used as reset control signal for the pixel driving circuits of pixels in (n+2)throw. With reference toFIG.22, the signal line transfer structure7is used for transferring the signal output line GO of the second scan driving circuit (i.e., the GATE GOA circuit) to the scan signal line61and the reset control signal line62. The signal output by the signal output line GO may be the Sn signal as shown inFIG.24, so that the Sn signal transmitted by the scan signal line61may be used as the scan signal for the pixel driving circuits of the pixels in the nthrow, and the Sn signal transmitted by the reset control signal line62may be used as the reset control signal for the pixel driving circuits of the pixels in the (n+1)throw. FIG.23is a plan view of a display substrate according to some embodiments of the present disclosure, in which some film layer structures such as a signal line transfer structure and an anode layer are shown.FIG.25is a schematic cross-sectional view of the display panel according to some embodiments of the present disclosure taken along line HH′ inFIG.23.FIG.27is a schematic cross-sectional view of the display panel according to some embodiments of the present disclosure taken along line II′ inFIG.23.FIG.28is a schematic cross-sectional view of the display panel according to some embodiments of the present disclosure taken along line JJ′ inFIG.23. With reference toFIGS.12,13to17,FIG.23,FIG.25,FIG.27, andFIG.28, the insulating layer may include at least some insulating layers selected from a gate insulating layer30, a first interlayer insulating layer40, a second interlayer insulating layer45and a first planarization layer50. With reference toFIGS.23and25, the display substrate may include: an active layer20(a layer where a light-emission control source region203fand a light-emission control drain region205finFIG.25are located) on the base substrate1, a gate insulating layer30on a side of the active layer20away from the base substrate1, a gate electrode G6on a side of the gate insulating layer30away from the base substrate1, a first interlayer insulating layer40on a side of the gate electrode G6away from the base substrate1, an initializing voltage line66on a side of the first interlayer insulating layer40away from the base substrate1, a second interlayer insulating layer45on a side of the initializing voltage line66away from the base substrate1, a drain electrode D6on a side of the second interlayer insulating layer45away from the base substrate1, a first planarization layer50covering the drain electrode D6, and an anode5on a side of the first planarization layer50away from the base substrate1. The drain electrode D6may be connected to the light-emission control drain region205fthrough a via hole VAH7, and the anode5may be connected to the drain electrode D6through a via hole VAH9. Referring toFIGS.15and16, the display substrate may further include a first capacitor electrode Cst1and a second capacitor electrode Cst2. Referring toFIG.13in combination, the first capacitor electrode Cst1and the second capacitor electrode Cst2are opposed to each other and may be spaced apart from each other by the first interlayer insulating layer40to form a storage capacitor Cst. In the illustrated examples, conductive elements such as the first capacitor electrode Cst1and the gate electrode G6may be located in the same layer, for example, the conductive elements are formed by the same patterning process. For the convenience of description, the layer where the first capacitor electrode Cst1and the gate G6are located may be referred to as a first conductive layer. Conductive elements such as the second capacitor electrode Cst2and the initializing voltage line66may be located in the same layer, for example, the conductive elements are formed by the same patterning process. For the convenience of description, the layer where the second capacitor electrode Cst2and the initializing voltage line66are located may be referred to as a second conductive layer. The layer where the drain electrode D6is located may be referred to as a third conductive layer. For example, conductive elements such as the driving voltage line65and/or the data line64may be located in the third conductive layer. It should be understood that conductive elements of the first scan driving circuit, the second scan driving circuit, and various signal lines may be arranged in the first conductive layer, the second conductive layer, and the third conductive layer, respectively. Optionally, a buffer layer11may be provided between the semiconductor layer20and the base substrate1. Specifically, referring toFIG.27, the scan signal line61and the reset control signal line62may be located in the first conductive layer, that is, located in the layer where gate electrodes of the thin film transistors are located. Referring toFIG.28, the signal output line GO of the second scan driving circuit may be located in the second conductive layer. Referring toFIGS.27and28, the signal line transfer structure7may be located in the third conductive layer. InFIG.22, the initializing voltage signal line660is also schematically shown, and the initializing voltage signal line660may be located in the third conductive layer. For example, the initializing voltage signal line660may cross the signal output line GO of the second scan driving circuit, that is, a projection of the initializing voltage signal line660on the base substrate may partially overlaps a projection of the the signal output line GO on the base substrate. For example, the signal output line GO is located in a peripheral area and on first side of a display area in a row direction, and the signal output line GO extends toward the display area. The initializing voltage signal line660is located in the peripheral area and on the first side of the display area in the row direction, and the initializing voltage signal line660extends along an outline direction of a boundary of the display area on the first side. For example, the signal output line GO crosses the initializing voltage signal line660, and extends into the display area or extends to a position that is closer to the display area than the initializing voltage signal line660. The signal output line GO is electrically connected to the signal line transfer structure7. Exemplarily, two via holes VH3are shown inFIG.22, the signal output line GO of the second scan driving circuit may be electrically connected to the signal line transfer structure7through two via holes VH3. Specifically, referring toFIG.27, the signal output line GO is located in the second conductive layer, the signal line transfer structure7is located in the third conductive layer, and the signal output line GO and the signal line transfer structure7in different layers are electrically connected to each other through two via holes VH3. In this way, an electrical connection between the signal output line GO and the signal line transfer structure7in different layers is realized. Exemplarily, two via holes VH3may be arranged in a direction parallel to an extending direction of the initializing voltage signal line660, that is, in the up-down direction (column direction) inFIG.22. It should be understood that the number of the via holes VH3is not limited to two, and more via holes VH3may also be provided. By providing a plurality of via holes VH3, a contact area between the signal output line GO and the signal line transfer structure7may be increased, thereby realizing a good electrical connection between the signal output line GO and the signal line transfer structure7. Further, referring toFIGS.23and27, a first end of the signal line transfer structure7is electrically connected to the scan signal line61through two via holes VH1. In this way, an electrical connection between the signal line transfer structure7and the scan signal line61located in different layers is realized. Exemplarily, two via holes VH1may be arranged in a direction perpendicular to the extending direction of the initializing voltage signal line660, that is, in the left-right direction inFIG.22. It should be understood that the number of via holes VH1is not limited to two, and more via holes VH1may also be provided. By providing a plurality of via holes VH1, a contact area between the signal line transfer structure7and the scan signal line61may be increased, thereby realizing a good electrical connection between the signal line transfer structure7and the scan signal line61. Further, referring toFIGS.23and27, a first end of the same signal line transfer structure7connected to one GOA unit is electrically connected to the scan signal line61through the two via holes VH1, and a second end thereof is electrically connected to the reset control signal line62through two via holes VH2. In this way, a electrical connection between the signal line transfer structure7and the reset control signal line62located in different layers is realized. Exemplarily, two via holes VH1may be arranged in a direction perpendicular to the extending direction of the initializing voltage signal line660, and two via holes VH2may be arranged in the direction perpendicular to the extending direction of the initializing voltage signal line660, that is, in the left-right direction (row direction) inFIG.22. It should be understood that the number of via holes VH2is not limited to two, and more via holes VH2may also be provided. By providing a plurality of via holes VH2, a contact area between the signal line transfer structure7and the reset control signal line62may be increased, thereby realizing a good electrical connection between the signal line transfer structure7and the reset control signal line62. As shown inFIG.22, the first end and the second end of the signal line transfer structure7are respectively located on opposite sides, or in other words, are respectively located on two sides of the signal output line GO (for example, two sides in the column direction). Through the signal line transfer structure7, an electrical connection between the signal output line GO and the scan signal line61located in different layers as well as an electrical connection between the signal output line GO and the reset control signal line62located in different layers may be realized. Thus, the gate scan signal and the reset control signal generated by the second scan driving circuit are transmitted to the pixel driving circuit. A signal output line GO may include three sections, which are respectively marked as a first sub-section of signal output line G01, a second sub-section of signal output line G02, and a third sub-section of signal output line G03, for convenience of description. An orthographic projection of the first sub-section of signal output line GO1on the base substrate at least partially overlaps with an orthographic projection of the signal line transfer structure7on the base substrate, so as to implement via-hole connection. The second sub-section of signal output line GO2crosses the initializing voltage signal line660, that is, an orthographic projection of the second sub-section of signal output line GO2on the base substrate at least partially overlaps with an orthographic projection of the initializing voltage signal line660on the base substrate. For example, an extending direction of the second sub-section of signal output line GO2is substantially perpendicular to an extending direction of the initializing voltage signal line660. For example, an orthographic projection of the second sub-section of signal output line GO2on the base substrate partially overlaps with an orthographic projection of the initializing voltage signal line660on the base substrate, and an area of the overlapped portion is obtained by multiplying a line width of the second sub-section of signal output line GO2by a line width of the initializing voltage signal line660. Referring toFIG.23in combination, an orthographic projection of the third sub-section of signal output line GO3on the base substrate at least partially overlaps with an orthographic projection of the second electrode QD5of the fifth transistor Q5of the second scan driving circuit on the base substrate. In a direction parallel to the extending direction of the initializing voltage signal line660(for example, the column direction), a size of the first sub-section of signal output line GO1is smaller than a size of the third sub-section of signal output line G03, a size of the second sub-section of signal output line GO2is smaller than a size of each of the first sub-section of signal output line GO1and the third sub-section of signal output line G03. Continue to refer toFIG.22, the second capacitor electrode Cst2may include a second capacitor electrode body portion Cs21and a second capacitor electrode connecting portion Cs22for connecting the second capacitor electrode body portion Cs21. That is, the second capacitor electrode connecting portion Cs22is provided between every two adjacent second capacitor electrode body portions Cs21. In a direction perpendicular to the extending direction of the initializing voltage signal line660, the second sub-section of signal output line GO2and the second capacitor electrode connecting portion Cs22are substantially aligned with each other. For example, a projection of the second sub-section of signal output line GO2in the direction perpendicular to the extending direction of the initializing voltage signal line660at least partially overlaps with a projection of the second capacitor electrode connecting portion Cs22in the direction perpendicular to the extending direction of the initializing voltage signal line660. Referring toFIG.23, an anode5of an edge sub-pixel is schematically illustrated. The anode5includes a body portion53and a connecting portion54, the body portion53covers an opening of the sub-pixel, and the connecting portion54covers a via hole VAH9for connecting the anode5to other conductive portions (for example, drain electrode D6). For example, an orthographic projection of the body portion53on the base substrate may have a regular shape, such as rounded rectangle described inFIG.23. The body portion53may have a center, for example, the center may be an intersection of two diagonal lines of the rounded rectangle. As described above, the anode5includes a first edge portion51and a second edge portion52, the first edge portion51and the second edge portion52do not overlap with the center of the body portion53. Specifically, the first edge portion51and the second edge portion52are respectively located on both sides of the center of the body portion53in a row direction, and both the first edge portion51and the second edge portion52are spaced apart from the center of the body portion53in the row direction. For example, a size of each of the first edge portion51and the second edge portion52in the row direction may be 1/10 to ⅕ of a size of the body portion53in the row direction. An orthographic projection of the anode5of the edge sub-pixel on the base substrate1at least partially overlaps with an orthographic projection of the signal line transfer structure7on the base substrate1, wherein the signal line transfer structure7is connected to a pixel driving circuit (for example, a scan signal line or a reset control signal line) of a pixel where the anode5of the edge sub-pixel is located. The signal line transfer structure7is located below the first edge portion51of the anode5, and the driving voltage line65and the data line64are provided below the second edge portion52of the anode5. In other words, an orthographic projection of the first edge portion51on the base substrate1at least partially overlaps with an orthographic projection of the signal line transfer structure7on the base substrate1, and an orthographic projection of the driving voltage line65and/or the data line64on the base substrate1at least partially overlaps with an orthographic projection of the second edge portion52on the base substrate1. For the anode5of the same one edge sub-pixel, a first portion of the anode5and a second portion of the anode5are located on two sides with regard to a center line of the anode of the edge sub-pixel, for example, on two opposite edges on left and right sides (row direction), wherein an orthographic projection of the first portion of the anode5on the base substrate1overlaps with an orthographic projection of the signal line transfer structure7that is connected to a pixel driving circuit (for example, a scan signal line or a reset control signal line) of a pixel where the anode5is located on the base substrate1, and an orthographic projection of the second portion of the anode5on the base substrate1overlaps with an orthographic projection of the driving voltage line65and/or the data line64on the base substrate1. As shown inFIG.23, an orthographic projection of the signal line transfer structure7overlapping with the edge sub-pixel on the base substrate1passes through the orthographic projection of the anode5of the edge sub-pixel on the base substrate1. It should be noted that the expression “pass through” herein means that at least a part of two ends of the signal line transfer structure7in the column direction does not overlap with the anode5, or in other words, a line in the column direction on the signal line transfer structure7passes through the anode5. Referring toFIGS.23and25in combination, the display substrate further includes a pixel defining layer56located on a side of the anode5away from the base substrate1. The pixel defining layer56includes an opening50, and the anode5is at least partially exposed by the opening50. As shown inFIG.23, a size of the signal line transfer structure7extending in the column direction is larger than a size of the opening50of the pixel defining layer56extending in the column direction. A size of the pixel driving circuit corresponding to the sub-pixel in the column direction is marked as a, and a size of the signal line transfer structure7in the column direction is between ⅓a and a, or the size of the signal line transfer structure7in the column direction is between ½a and a, or the size of the signal line transfer structure7in the column direction is between ½a and ¾a. It should be noted that the expression “the size of the pixel driving circuit in the column direction” herein may be understood as follows: a distance in the column direction between two signal lines that transmit the same signal, with a startpoint on one signal line that extends in the row direction and drives sub-pixels in previous row and an endpoint on another signal line that drives sub-pixels in current row and transmits the same signal as the one signal line. For example, “the size of the pixel driving circuit in the column direction” may be the distance in the column direction between a reset control signal line for sub-pixels in previous row and a reset control signal line for sub-pixels in current row. As shown inFIG.23, the size of the signal line transfer structure7in the column direction is larger than a spacing in the column direction between the scan signal line61and the light-emission control line63in the pixel driving circuit connected to the signal line transfer structure7. As shown inFIG.23, in a direction perpendicular to the driving voltage line65and the data line64(for example, the row direction), the signal line transfer structure7is located on a side that is closer to the non-display area than the driving voltage line65and the data line64. In the embodiments of the present disclosure, the data line64, the driving voltage line65and the signal line transfer structure7are located in the same layer as the source/drain electrodes of the thin film transistor, that is, the data line64, the driving voltage line65and the signal line transfer structure7may be composed of materials constituting the source/drain electrodes and formed by the same patterning process. In this way, thicknesses of the data line64, the driving voltage line65and the signal line transfer structure7are approximately equal to one another, that is, a thickness of the signal line transfer structure7in a direction perpendicular to the base substrate1is approximately equal to a thickness of each of the data line64and the driving voltage line65in a direction perpendicular to the base substrate1. For example, the expression “approximately equal to” may mean a range from 0.8 to 1.2, that is, a ratio of “the thickness of the signal line transfer structure7in the direction perpendicular to the base substrate1” to “thickness of each of the data line64and the driving voltage line65in the direction perpendicular to the base substrate1” may be in the range of 0.8 to 1.2. Specifically, the signal line transfer structure7includes a widened portion73. As shown inFIG.23, orthographic projections of a plurality of via holes VH1and a plurality of via holes VH3on the base substrate all fall within an orthographic projection of the widened portion73on the base substrate. An orthographic projection of the first edge portion51on the base substrate1at least partially overlaps with the orthographic projection of the widened portion73on the base substrate1. In this way, the widened portion73may be used to cushion the anode and improve the plainness of the anode. It should be noted that in the embodiments shown inFIG.23, the plurality of via holes VH1are arranged in left-right direction, and the plurality of via holes VH3are arranged in up-down direction. In this way, sizes of the widened portion73in both the left-right direction and the up-down direction are widened, which is beneficial to cushion the anode5and implement the reliability of via hole connection. Continuing to refer toFIG.23, the initializing voltage signal line660may be electrically connected to the initializing voltage line66through a via hole VH4to transmit the initializing voltage Vint to the pixel driving circuit. For example, the initializing voltage signal line660may be located in the third conductive layer, and the initializing voltage line66may be located in the second conductive layer. For example, the number of via holes VH4may be two, and the two via holes VH4may be arranged in a direction parallel to the extending direction of the initializing voltage signal line660, that is, the two via holes is in up-down direction inFIG.23(for example, the column direction). It should be understood that the number of via holes VH4is not limited to two, and more via holes VH4may also be provided. Referring toFIGS.23and28in combination, the second electrode QD5of the fifth transistor Q5of the second scan driving circuit may be electrically connected to the signal output line GO through via hole VH5. For example, the number of via holes VH5may be three, and the three via holes VH5may be arranged in a direction parallel to the extending direction of the initializing voltage signal line660, that is, the three via holes VH5arranged in up-down direction inFIG.23. It should be understood that the number of via holes VH5is not limited to three, and more via holes VH5may also be provided. The display substrate may further include a second initializing voltage signal line661. In this case, the initializing voltage signal line660may be referred to as a first initializing voltage signal line660. The second initializing voltage signal line661may be located in the same layer as the anode5. Specifically, referring toFIGS.23and28in combination, a groove662is provided in the first planarization layer50, and the groove662exposes an upper surface of the first initializing voltage signal line660. A part of the second initializing voltage signal line661above the first initializing voltage signal line660is located in the groove662, so that the first initializing voltage signal line660and the second initializing voltage signal line661may be connected. In this way, the second initializing voltage signal line661may be connected in parallel with the first initializing voltage signal line660to reduce the resistance on the lines transmitting the initializing voltage. For example, widths of the first initializing voltage signal line660and the second initializing voltage signal line661may be approximately equal to each other. A width of the groove662may be smaller than the width of the first initializing voltage signal line660or the width of the second initializing voltage signal line661. The width may refer to a size in a direction perpendicular to the extending direction of the first initializing voltage signal line660(i.e., the row direction). Exemplarily, the width of the first initializing voltage signal line660and the width of the second initializing voltage signal line661may be in the range of 15 to 35 microns, and the width of the groove662may be in the range of 13 to 30 microns. Optionally,FIG.26is a schematic cross-sectional view of the display panel according to other embodiments of the present disclosure taken along line HH′ inFIG.23, In these embodiments, the display substrate may further include a fourth conductive layer located between the third conductive layer and the layer where the anode5is located. For example, the display substrate may further include a connecting conductive portion70provided on a side of the first planarization layer50away from the base substrate1. The connecting conductive portion70is located in the fourth conductive layer. The connecting conductive portion70is electrically connected to the drain electrode D6through a via hole VAH10, and the anode5is electrically connected to the connecting conductive portion70through a via hole VAH11. That is, the anode5and the drain electrode D6are electrically connected through the connecting conductive portion70. In the case where the fourth conductive layer is provided, some of the signal lines may be arranged in the fourth conductive layer according to wiring needs, or a data line connected in parallel with the data line64for transmitting the data signal Dm and/or the driving voltage line65for transmitting the driving voltage ELVDD may be arranged in the fourth conductive layer, so that the resistance on the lines that transmit data signal and/or driving voltage may be reduced. Optionally, inFIG.26, the via hole VAH11may also be located on left side of the via hole VAH10, for example, the via hole VAH11is between the via hole VAH10and the via hole VAH7, that is, an orthographic projection of the via hole VAH11on the base substrate1may be located between an orthographic projection of the via hole VAH10on the base substrate1and an orthographic projection of the via hole VAH7on the base substrate1. Optionally, in the embodiments shown inFIGS.25,27, and28, the first planarization layer50is shown in the form of one film layer, but the embodiments of the present disclosure are not limited thereto. In optional embodiments, the first planarization layer50may include at least two film layers. For example, two insulating layers may be provided between the third conductive layer and the layer where the anode5is located. The two insulating layers may include a passivation layer composed of an inorganic material and a planarization layer composed of an organic material. Optionally, continuing to refer toFIG.26, the display substrate may further include a second planarization layer55disposed on a side of the connecting conductive portion70away from the base substrate1. The anode5of OLED is arranged on a side of the second planarization layer55away from the base substrate1. It should be understood that the OLED may also include an organic light-emission layer and a cathode disposed on a side of the anode5away from the base substrate1. For example, the first conductive layer and the second conductive layer may be conductive layers made of gate electrode material, such as Mo. For example, the third conductive layer and the fourth conductive layer may be conductive layers composed of source/drain electrode materials, such as Ti/Al/Ti. For example, the gate electrode material may include metal materials, such as Mo, Al, Cu and other metals as well as alloys thereof. The source/drain electrodes materials may include metal materials, such as Mo, Al, Cu and other metals as well as alloys thereof. The semiconductor material constituting the active layer may include, for example, amorphous silicon, polysilicon, oxide semiconductor, etc, and the oxide semiconductor material may include, for example, IGZO (Indium Gallium Zinc Oxide), ZnO (Zinc Oxide), etc. Referring toFIG.23, for convenience of description, the layer where the anode5is located is referred to as a fifth conductive layer. The orthographic projection of the third sub-section of signal output line GO3on the base substrate does not overlap with the orthographic projection of the fifth conductive layer on the base substrate, so as to avoid interference of an electrical signal transmitted on the fifth conductive layer on an output signal of the signal output line GO. For example, the third sub-section of signal output line GO3is located in the peripheral area, neither the second initializing voltage signal line661nor the anode5located in the fifth conductive layer overlap with the third sub-section of signal output line G03. Referring back toFIG.11in combination, optionally, the first signal line31and the signal line transfer structure7may be located in the fourth conductive layer, that is, the first signal line31and the signal line transfer structure7may be located in the same layer as the connecting conductive portion70. In this case, the first signal line31and the signal line transfer structure7may also be composed of the source/drain electrode materials and formed by the same patterning process. Optionally, the first signal line31and the signal line transfer structure7may be located in the first conductive layer, that is, the first signal line31and the signal line transfer structure7may be located in the same layer as the gate electrode G6. In this case, the first signal line31and the signal line transfer structure7may be composed of the gate electrode material and formed by the same patterning process. Optionally, the first signal line31and the signal line transfer structure7may be located in the second conductive layer, that is, the first signal line31and the signal line transfer structure7may be located in the same layer as the first capacitor electrode Cst1. In this case, the first signal line31and the signal line transfer structure7may also be made of the gate electrode material and formed by the same patterning process. In this way, in the embodiments of the present disclosure, the first signal line31and the signal line transfer structure7are formed of the same material and through the same patterning process, so the first signal line31and the signal line transfer structure7have the same thickness. Referring toFIG.11, the first signal line31and the signal line transfer structure7having the same thickness are respectively located below the anode5, so that it is beneficial to improving the plainness of the anode5and avoiding the slope of the anode5, thereby improving the color shift of the display substrate. It should be noted that the planarization layer4in the embodiments may include the first planarization layer50and the second planarization layer55as shown inFIG.26. However, the embodiments of the present disclosure are not limited to this, and the planarization layer4may also have a structure of a single film layer. It should also be noted that, as described above with respect toFIG.4, a left GOA circuit DA1and a right GOA circuit DA2are provided on the display substrate according to some embodiments. Correspondingly, the at least one array of edge sub-pixels may include a column of edge sub-pixels located on the left side of the display area and a column of edge sub-pixels located on the right side of the display area. A plurality of the signal line transfer structures7are provided between the GOA circuit DA1on the left side and a column of edge sub-pixels on the left side of the display area, and orthographic projections of first electrodes of a column of edge sub-pixels on the left side of the display area on the base substrate at least partially overlap with orthographic projections of the signal line transfer structures7on the base substrate, respectively. Similarly, a plurality of the signal line transfer structures7are also provided between the right GOA circuit DA2and a column of edge sub-pixels located on the right side of the display area, and orthographic projections of first electrodes of a column of edge sub-pixels located on the right side of the display area on the base substrate at least partially overlap with orthographic projections of the signal line transfer structures7on the base substrate, respectively. In the above-mentioned embodiments, the signal line transfer structures7are arranged at edge positions on the left and right sides of the display area AA to cushion the anodes5. However, the embodiments of the present disclosure are not limited to this. The signal line transfer structures7may also be arranged at other positions, for example, at edge positions of upper and lower sides of the display area AA, or at edge positions of corners of the display area AA. Some embodiments of the present disclosure further provide a display panel including the display substrate as described above. For example, the display panel may be an OLED display panel. Referring toFIG.29, some embodiments of the present disclosure also provide a display device. The display device may include the display substrate as described above. The display device includes a display area AA and a non-display area NA, and the non-display area NA has a relatively small width, thereby realizing a display device with a narrow frame. The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), digital audio players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), televisions, etc. It should be understood that the display device according to the embodiments of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description, which will not be repeated here. Although some embodiments of the general technical concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made to these embodiments without departing from the principle and spirit of the general technical concept. The scope of the present disclosure shall be defined by the claims and their equivalents. | 112,050 |
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